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drm/i915: Use GPLL ref clock to calculate GPU freqs on VLV/CHV
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "intel_dsi.h"
40 #include "i915_trace.h"
41 #include <drm/drm_atomic.h>
42 #include <drm/drm_atomic_helper.h>
43 #include <drm/drm_dp_helper.h>
44 #include <drm/drm_crtc_helper.h>
45 #include <drm/drm_plane_helper.h>
46 #include <drm/drm_rect.h>
47 #include <linux/dma_remapping.h>
48 #include <linux/reservation.h>
49 #include <linux/dma-buf.h>
50
51 /* Primary plane formats for gen <= 3 */
52 static const uint32_t i8xx_primary_formats[] = {
53 DRM_FORMAT_C8,
54 DRM_FORMAT_RGB565,
55 DRM_FORMAT_XRGB1555,
56 DRM_FORMAT_XRGB8888,
57 };
58
59 /* Primary plane formats for gen >= 4 */
60 static const uint32_t i965_primary_formats[] = {
61 DRM_FORMAT_C8,
62 DRM_FORMAT_RGB565,
63 DRM_FORMAT_XRGB8888,
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_XBGR2101010,
67 };
68
69 static const uint32_t skl_primary_formats[] = {
70 DRM_FORMAT_C8,
71 DRM_FORMAT_RGB565,
72 DRM_FORMAT_XRGB8888,
73 DRM_FORMAT_XBGR8888,
74 DRM_FORMAT_ARGB8888,
75 DRM_FORMAT_ABGR8888,
76 DRM_FORMAT_XRGB2101010,
77 DRM_FORMAT_XBGR2101010,
78 DRM_FORMAT_YUYV,
79 DRM_FORMAT_YVYU,
80 DRM_FORMAT_UYVY,
81 DRM_FORMAT_VYUY,
82 };
83
84 /* Cursor formats */
85 static const uint32_t intel_cursor_formats[] = {
86 DRM_FORMAT_ARGB8888,
87 };
88
89 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
90 struct intel_crtc_state *pipe_config);
91 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
92 struct intel_crtc_state *pipe_config);
93
94 static int intel_framebuffer_init(struct drm_device *dev,
95 struct intel_framebuffer *ifb,
96 struct drm_mode_fb_cmd2 *mode_cmd,
97 struct drm_i915_gem_object *obj);
98 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
99 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
100 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc);
101 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
102 struct intel_link_m_n *m_n,
103 struct intel_link_m_n *m2_n2);
104 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
105 static void haswell_set_pipeconf(struct drm_crtc *crtc);
106 static void haswell_set_pipemisc(struct drm_crtc *crtc);
107 static void vlv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void chv_prepare_pll(struct intel_crtc *crtc,
110 const struct intel_crtc_state *pipe_config);
111 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
112 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
113 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
114 struct intel_crtc_state *crtc_state);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary_noatomic(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg, int ref_freq)
152 {
153 u32 val;
154 int divider;
155
156 mutex_lock(&dev_priv->sb_lock);
157 val = vlv_cck_read(dev_priv, reg);
158 mutex_unlock(&dev_priv->sb_lock);
159
160 divider = val & CCK_FREQUENCY_VALUES;
161
162 WARN((val & CCK_FREQUENCY_STATUS) !=
163 (divider << CCK_FREQUENCY_STATUS_SHIFT),
164 "%s change in progress\n", name);
165
166 return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
167 }
168
169 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
170 const char *name, u32 reg)
171 {
172 if (dev_priv->hpll_freq == 0)
173 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
174
175 return vlv_get_cck_clock(dev_priv, name, reg,
176 dev_priv->hpll_freq);
177 }
178
179 static int
180 intel_pch_rawclk(struct drm_i915_private *dev_priv)
181 {
182 return (I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
183 }
184
185 static int
186 intel_vlv_hrawclk(struct drm_i915_private *dev_priv)
187 {
188 return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
189 CCK_DISPLAY_REF_CLOCK_CONTROL);
190 }
191
192 static int
193 intel_g4x_hrawclk(struct drm_i915_private *dev_priv)
194 {
195 uint32_t clkcfg;
196
197 /* hrawclock is 1/4 the FSB frequency */
198 clkcfg = I915_READ(CLKCFG);
199 switch (clkcfg & CLKCFG_FSB_MASK) {
200 case CLKCFG_FSB_400:
201 return 100000;
202 case CLKCFG_FSB_533:
203 return 133333;
204 case CLKCFG_FSB_667:
205 return 166667;
206 case CLKCFG_FSB_800:
207 return 200000;
208 case CLKCFG_FSB_1067:
209 return 266667;
210 case CLKCFG_FSB_1333:
211 return 333333;
212 /* these two are just a guess; one of them might be right */
213 case CLKCFG_FSB_1600:
214 case CLKCFG_FSB_1600_ALT:
215 return 400000;
216 default:
217 return 133333;
218 }
219 }
220
221 static void intel_update_rawclk(struct drm_i915_private *dev_priv)
222 {
223 if (HAS_PCH_SPLIT(dev_priv))
224 dev_priv->rawclk_freq = intel_pch_rawclk(dev_priv);
225 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
226 dev_priv->rawclk_freq = intel_vlv_hrawclk(dev_priv);
227 else if (IS_G4X(dev_priv) || IS_PINEVIEW(dev_priv))
228 dev_priv->rawclk_freq = intel_g4x_hrawclk(dev_priv);
229 else
230 return; /* no rawclk on other platforms, or no need to know it */
231
232 DRM_DEBUG_DRIVER("rawclk rate: %d kHz\n", dev_priv->rawclk_freq);
233 }
234
235 static void intel_update_czclk(struct drm_i915_private *dev_priv)
236 {
237 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
238 return;
239
240 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
241 CCK_CZ_CLOCK_CONTROL);
242
243 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
244 }
245
246 static inline u32 /* units of 100MHz */
247 intel_fdi_link_freq(struct drm_i915_private *dev_priv,
248 const struct intel_crtc_state *pipe_config)
249 {
250 if (HAS_DDI(dev_priv))
251 return pipe_config->port_clock; /* SPLL */
252 else if (IS_GEN5(dev_priv))
253 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000;
254 else
255 return 270000;
256 }
257
258 static const intel_limit_t intel_limits_i8xx_dac = {
259 .dot = { .min = 25000, .max = 350000 },
260 .vco = { .min = 908000, .max = 1512000 },
261 .n = { .min = 2, .max = 16 },
262 .m = { .min = 96, .max = 140 },
263 .m1 = { .min = 18, .max = 26 },
264 .m2 = { .min = 6, .max = 16 },
265 .p = { .min = 4, .max = 128 },
266 .p1 = { .min = 2, .max = 33 },
267 .p2 = { .dot_limit = 165000,
268 .p2_slow = 4, .p2_fast = 2 },
269 };
270
271 static const intel_limit_t intel_limits_i8xx_dvo = {
272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 908000, .max = 1512000 },
274 .n = { .min = 2, .max = 16 },
275 .m = { .min = 96, .max = 140 },
276 .m1 = { .min = 18, .max = 26 },
277 .m2 = { .min = 6, .max = 16 },
278 .p = { .min = 4, .max = 128 },
279 .p1 = { .min = 2, .max = 33 },
280 .p2 = { .dot_limit = 165000,
281 .p2_slow = 4, .p2_fast = 4 },
282 };
283
284 static const intel_limit_t intel_limits_i8xx_lvds = {
285 .dot = { .min = 25000, .max = 350000 },
286 .vco = { .min = 908000, .max = 1512000 },
287 .n = { .min = 2, .max = 16 },
288 .m = { .min = 96, .max = 140 },
289 .m1 = { .min = 18, .max = 26 },
290 .m2 = { .min = 6, .max = 16 },
291 .p = { .min = 4, .max = 128 },
292 .p1 = { .min = 1, .max = 6 },
293 .p2 = { .dot_limit = 165000,
294 .p2_slow = 14, .p2_fast = 7 },
295 };
296
297 static const intel_limit_t intel_limits_i9xx_sdvo = {
298 .dot = { .min = 20000, .max = 400000 },
299 .vco = { .min = 1400000, .max = 2800000 },
300 .n = { .min = 1, .max = 6 },
301 .m = { .min = 70, .max = 120 },
302 .m1 = { .min = 8, .max = 18 },
303 .m2 = { .min = 3, .max = 7 },
304 .p = { .min = 5, .max = 80 },
305 .p1 = { .min = 1, .max = 8 },
306 .p2 = { .dot_limit = 200000,
307 .p2_slow = 10, .p2_fast = 5 },
308 };
309
310 static const intel_limit_t intel_limits_i9xx_lvds = {
311 .dot = { .min = 20000, .max = 400000 },
312 .vco = { .min = 1400000, .max = 2800000 },
313 .n = { .min = 1, .max = 6 },
314 .m = { .min = 70, .max = 120 },
315 .m1 = { .min = 8, .max = 18 },
316 .m2 = { .min = 3, .max = 7 },
317 .p = { .min = 7, .max = 98 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 112000,
320 .p2_slow = 14, .p2_fast = 7 },
321 };
322
323
324 static const intel_limit_t intel_limits_g4x_sdvo = {
325 .dot = { .min = 25000, .max = 270000 },
326 .vco = { .min = 1750000, .max = 3500000},
327 .n = { .min = 1, .max = 4 },
328 .m = { .min = 104, .max = 138 },
329 .m1 = { .min = 17, .max = 23 },
330 .m2 = { .min = 5, .max = 11 },
331 .p = { .min = 10, .max = 30 },
332 .p1 = { .min = 1, .max = 3},
333 .p2 = { .dot_limit = 270000,
334 .p2_slow = 10,
335 .p2_fast = 10
336 },
337 };
338
339 static const intel_limit_t intel_limits_g4x_hdmi = {
340 .dot = { .min = 22000, .max = 400000 },
341 .vco = { .min = 1750000, .max = 3500000},
342 .n = { .min = 1, .max = 4 },
343 .m = { .min = 104, .max = 138 },
344 .m1 = { .min = 16, .max = 23 },
345 .m2 = { .min = 5, .max = 11 },
346 .p = { .min = 5, .max = 80 },
347 .p1 = { .min = 1, .max = 8},
348 .p2 = { .dot_limit = 165000,
349 .p2_slow = 10, .p2_fast = 5 },
350 };
351
352 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
353 .dot = { .min = 20000, .max = 115000 },
354 .vco = { .min = 1750000, .max = 3500000 },
355 .n = { .min = 1, .max = 3 },
356 .m = { .min = 104, .max = 138 },
357 .m1 = { .min = 17, .max = 23 },
358 .m2 = { .min = 5, .max = 11 },
359 .p = { .min = 28, .max = 112 },
360 .p1 = { .min = 2, .max = 8 },
361 .p2 = { .dot_limit = 0,
362 .p2_slow = 14, .p2_fast = 14
363 },
364 };
365
366 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
367 .dot = { .min = 80000, .max = 224000 },
368 .vco = { .min = 1750000, .max = 3500000 },
369 .n = { .min = 1, .max = 3 },
370 .m = { .min = 104, .max = 138 },
371 .m1 = { .min = 17, .max = 23 },
372 .m2 = { .min = 5, .max = 11 },
373 .p = { .min = 14, .max = 42 },
374 .p1 = { .min = 2, .max = 6 },
375 .p2 = { .dot_limit = 0,
376 .p2_slow = 7, .p2_fast = 7
377 },
378 };
379
380 static const intel_limit_t intel_limits_pineview_sdvo = {
381 .dot = { .min = 20000, .max = 400000},
382 .vco = { .min = 1700000, .max = 3500000 },
383 /* Pineview's Ncounter is a ring counter */
384 .n = { .min = 3, .max = 6 },
385 .m = { .min = 2, .max = 256 },
386 /* Pineview only has one combined m divider, which we treat as m2. */
387 .m1 = { .min = 0, .max = 0 },
388 .m2 = { .min = 0, .max = 254 },
389 .p = { .min = 5, .max = 80 },
390 .p1 = { .min = 1, .max = 8 },
391 .p2 = { .dot_limit = 200000,
392 .p2_slow = 10, .p2_fast = 5 },
393 };
394
395 static const intel_limit_t intel_limits_pineview_lvds = {
396 .dot = { .min = 20000, .max = 400000 },
397 .vco = { .min = 1700000, .max = 3500000 },
398 .n = { .min = 3, .max = 6 },
399 .m = { .min = 2, .max = 256 },
400 .m1 = { .min = 0, .max = 0 },
401 .m2 = { .min = 0, .max = 254 },
402 .p = { .min = 7, .max = 112 },
403 .p1 = { .min = 1, .max = 8 },
404 .p2 = { .dot_limit = 112000,
405 .p2_slow = 14, .p2_fast = 14 },
406 };
407
408 /* Ironlake / Sandybridge
409 *
410 * We calculate clock using (register_value + 2) for N/M1/M2, so here
411 * the range value for them is (actual_value - 2).
412 */
413 static const intel_limit_t intel_limits_ironlake_dac = {
414 .dot = { .min = 25000, .max = 350000 },
415 .vco = { .min = 1760000, .max = 3510000 },
416 .n = { .min = 1, .max = 5 },
417 .m = { .min = 79, .max = 127 },
418 .m1 = { .min = 12, .max = 22 },
419 .m2 = { .min = 5, .max = 9 },
420 .p = { .min = 5, .max = 80 },
421 .p1 = { .min = 1, .max = 8 },
422 .p2 = { .dot_limit = 225000,
423 .p2_slow = 10, .p2_fast = 5 },
424 };
425
426 static const intel_limit_t intel_limits_ironlake_single_lvds = {
427 .dot = { .min = 25000, .max = 350000 },
428 .vco = { .min = 1760000, .max = 3510000 },
429 .n = { .min = 1, .max = 3 },
430 .m = { .min = 79, .max = 118 },
431 .m1 = { .min = 12, .max = 22 },
432 .m2 = { .min = 5, .max = 9 },
433 .p = { .min = 28, .max = 112 },
434 .p1 = { .min = 2, .max = 8 },
435 .p2 = { .dot_limit = 225000,
436 .p2_slow = 14, .p2_fast = 14 },
437 };
438
439 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
440 .dot = { .min = 25000, .max = 350000 },
441 .vco = { .min = 1760000, .max = 3510000 },
442 .n = { .min = 1, .max = 3 },
443 .m = { .min = 79, .max = 127 },
444 .m1 = { .min = 12, .max = 22 },
445 .m2 = { .min = 5, .max = 9 },
446 .p = { .min = 14, .max = 56 },
447 .p1 = { .min = 2, .max = 8 },
448 .p2 = { .dot_limit = 225000,
449 .p2_slow = 7, .p2_fast = 7 },
450 };
451
452 /* LVDS 100mhz refclk limits. */
453 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
454 .dot = { .min = 25000, .max = 350000 },
455 .vco = { .min = 1760000, .max = 3510000 },
456 .n = { .min = 1, .max = 2 },
457 .m = { .min = 79, .max = 126 },
458 .m1 = { .min = 12, .max = 22 },
459 .m2 = { .min = 5, .max = 9 },
460 .p = { .min = 28, .max = 112 },
461 .p1 = { .min = 2, .max = 8 },
462 .p2 = { .dot_limit = 225000,
463 .p2_slow = 14, .p2_fast = 14 },
464 };
465
466 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
467 .dot = { .min = 25000, .max = 350000 },
468 .vco = { .min = 1760000, .max = 3510000 },
469 .n = { .min = 1, .max = 3 },
470 .m = { .min = 79, .max = 126 },
471 .m1 = { .min = 12, .max = 22 },
472 .m2 = { .min = 5, .max = 9 },
473 .p = { .min = 14, .max = 42 },
474 .p1 = { .min = 2, .max = 6 },
475 .p2 = { .dot_limit = 225000,
476 .p2_slow = 7, .p2_fast = 7 },
477 };
478
479 static const intel_limit_t intel_limits_vlv = {
480 /*
481 * These are the data rate limits (measured in fast clocks)
482 * since those are the strictest limits we have. The fast
483 * clock and actual rate limits are more relaxed, so checking
484 * them would make no difference.
485 */
486 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
487 .vco = { .min = 4000000, .max = 6000000 },
488 .n = { .min = 1, .max = 7 },
489 .m1 = { .min = 2, .max = 3 },
490 .m2 = { .min = 11, .max = 156 },
491 .p1 = { .min = 2, .max = 3 },
492 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
493 };
494
495 static const intel_limit_t intel_limits_chv = {
496 /*
497 * These are the data rate limits (measured in fast clocks)
498 * since those are the strictest limits we have. The fast
499 * clock and actual rate limits are more relaxed, so checking
500 * them would make no difference.
501 */
502 .dot = { .min = 25000 * 5, .max = 540000 * 5},
503 .vco = { .min = 4800000, .max = 6480000 },
504 .n = { .min = 1, .max = 1 },
505 .m1 = { .min = 2, .max = 2 },
506 .m2 = { .min = 24 << 22, .max = 175 << 22 },
507 .p1 = { .min = 2, .max = 4 },
508 .p2 = { .p2_slow = 1, .p2_fast = 14 },
509 };
510
511 static const intel_limit_t intel_limits_bxt = {
512 /* FIXME: find real dot limits */
513 .dot = { .min = 0, .max = INT_MAX },
514 .vco = { .min = 4800000, .max = 6700000 },
515 .n = { .min = 1, .max = 1 },
516 .m1 = { .min = 2, .max = 2 },
517 /* FIXME: find real m2 limits */
518 .m2 = { .min = 2 << 22, .max = 255 << 22 },
519 .p1 = { .min = 2, .max = 4 },
520 .p2 = { .p2_slow = 1, .p2_fast = 20 },
521 };
522
523 static bool
524 needs_modeset(struct drm_crtc_state *state)
525 {
526 return drm_atomic_crtc_needs_modeset(state);
527 }
528
529 /**
530 * Returns whether any output on the specified pipe is of the specified type
531 */
532 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
533 {
534 struct drm_device *dev = crtc->base.dev;
535 struct intel_encoder *encoder;
536
537 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
538 if (encoder->type == type)
539 return true;
540
541 return false;
542 }
543
544 /**
545 * Returns whether any output on the specified pipe will have the specified
546 * type after a staged modeset is complete, i.e., the same as
547 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
548 * encoder->crtc.
549 */
550 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
551 int type)
552 {
553 struct drm_atomic_state *state = crtc_state->base.state;
554 struct drm_connector *connector;
555 struct drm_connector_state *connector_state;
556 struct intel_encoder *encoder;
557 int i, num_connectors = 0;
558
559 for_each_connector_in_state(state, connector, connector_state, i) {
560 if (connector_state->crtc != crtc_state->base.crtc)
561 continue;
562
563 num_connectors++;
564
565 encoder = to_intel_encoder(connector_state->best_encoder);
566 if (encoder->type == type)
567 return true;
568 }
569
570 WARN_ON(num_connectors == 0);
571
572 return false;
573 }
574
575 /*
576 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
577 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
578 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
579 * The helpers' return value is the rate of the clock that is fed to the
580 * display engine's pipe which can be the above fast dot clock rate or a
581 * divided-down version of it.
582 */
583 /* m1 is reserved as 0 in Pineview, n is a ring counter */
584 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
585 {
586 clock->m = clock->m2 + 2;
587 clock->p = clock->p1 * clock->p2;
588 if (WARN_ON(clock->n == 0 || clock->p == 0))
589 return 0;
590 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
591 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
592
593 return clock->dot;
594 }
595
596 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
597 {
598 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
599 }
600
601 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
602 {
603 clock->m = i9xx_dpll_compute_m(clock);
604 clock->p = clock->p1 * clock->p2;
605 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
606 return 0;
607 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
608 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
609
610 return clock->dot;
611 }
612
613 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
614 {
615 clock->m = clock->m1 * clock->m2;
616 clock->p = clock->p1 * clock->p2;
617 if (WARN_ON(clock->n == 0 || clock->p == 0))
618 return 0;
619 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
620 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
621
622 return clock->dot / 5;
623 }
624
625 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
626 {
627 clock->m = clock->m1 * clock->m2;
628 clock->p = clock->p1 * clock->p2;
629 if (WARN_ON(clock->n == 0 || clock->p == 0))
630 return 0;
631 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
632 clock->n << 22);
633 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
634
635 return clock->dot / 5;
636 }
637
638 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
639 /**
640 * Returns whether the given set of divisors are valid for a given refclk with
641 * the given connectors.
642 */
643
644 static bool intel_PLL_is_valid(struct drm_device *dev,
645 const intel_limit_t *limit,
646 const intel_clock_t *clock)
647 {
648 if (clock->n < limit->n.min || limit->n.max < clock->n)
649 INTELPllInvalid("n out of range\n");
650 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
651 INTELPllInvalid("p1 out of range\n");
652 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
653 INTELPllInvalid("m2 out of range\n");
654 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
655 INTELPllInvalid("m1 out of range\n");
656
657 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
658 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
659 if (clock->m1 <= clock->m2)
660 INTELPllInvalid("m1 <= m2\n");
661
662 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
663 if (clock->p < limit->p.min || limit->p.max < clock->p)
664 INTELPllInvalid("p out of range\n");
665 if (clock->m < limit->m.min || limit->m.max < clock->m)
666 INTELPllInvalid("m out of range\n");
667 }
668
669 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
670 INTELPllInvalid("vco out of range\n");
671 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
672 * connector, etc., rather than just a single range.
673 */
674 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
675 INTELPllInvalid("dot out of range\n");
676
677 return true;
678 }
679
680 static int
681 i9xx_select_p2_div(const intel_limit_t *limit,
682 const struct intel_crtc_state *crtc_state,
683 int target)
684 {
685 struct drm_device *dev = crtc_state->base.crtc->dev;
686
687 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
688 /*
689 * For LVDS just rely on its current settings for dual-channel.
690 * We haven't figured out how to reliably set up different
691 * single/dual channel state, if we even can.
692 */
693 if (intel_is_dual_link_lvds(dev))
694 return limit->p2.p2_fast;
695 else
696 return limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 return limit->p2.p2_slow;
700 else
701 return limit->p2.p2_fast;
702 }
703 }
704
705 /*
706 * Returns a set of divisors for the desired target clock with the given
707 * refclk, or FALSE. The returned values represent the clock equation:
708 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
709 *
710 * Target and reference clocks are specified in kHz.
711 *
712 * If match_clock is provided, then best_clock P divider must match the P
713 * divider from @match_clock used for LVDS downclocking.
714 */
715 static bool
716 i9xx_find_best_dpll(const intel_limit_t *limit,
717 struct intel_crtc_state *crtc_state,
718 int target, int refclk, intel_clock_t *match_clock,
719 intel_clock_t *best_clock)
720 {
721 struct drm_device *dev = crtc_state->base.crtc->dev;
722 intel_clock_t clock;
723 int err = target;
724
725 memset(best_clock, 0, sizeof(*best_clock));
726
727 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
728
729 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
730 clock.m1++) {
731 for (clock.m2 = limit->m2.min;
732 clock.m2 <= limit->m2.max; clock.m2++) {
733 if (clock.m2 >= clock.m1)
734 break;
735 for (clock.n = limit->n.min;
736 clock.n <= limit->n.max; clock.n++) {
737 for (clock.p1 = limit->p1.min;
738 clock.p1 <= limit->p1.max; clock.p1++) {
739 int this_err;
740
741 i9xx_calc_dpll_params(refclk, &clock);
742 if (!intel_PLL_is_valid(dev, limit,
743 &clock))
744 continue;
745 if (match_clock &&
746 clock.p != match_clock->p)
747 continue;
748
749 this_err = abs(clock.dot - target);
750 if (this_err < err) {
751 *best_clock = clock;
752 err = this_err;
753 }
754 }
755 }
756 }
757 }
758
759 return (err != target);
760 }
761
762 /*
763 * Returns a set of divisors for the desired target clock with the given
764 * refclk, or FALSE. The returned values represent the clock equation:
765 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
766 *
767 * Target and reference clocks are specified in kHz.
768 *
769 * If match_clock is provided, then best_clock P divider must match the P
770 * divider from @match_clock used for LVDS downclocking.
771 */
772 static bool
773 pnv_find_best_dpll(const intel_limit_t *limit,
774 struct intel_crtc_state *crtc_state,
775 int target, int refclk, intel_clock_t *match_clock,
776 intel_clock_t *best_clock)
777 {
778 struct drm_device *dev = crtc_state->base.crtc->dev;
779 intel_clock_t clock;
780 int err = target;
781
782 memset(best_clock, 0, sizeof(*best_clock));
783
784 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
785
786 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
787 clock.m1++) {
788 for (clock.m2 = limit->m2.min;
789 clock.m2 <= limit->m2.max; clock.m2++) {
790 for (clock.n = limit->n.min;
791 clock.n <= limit->n.max; clock.n++) {
792 for (clock.p1 = limit->p1.min;
793 clock.p1 <= limit->p1.max; clock.p1++) {
794 int this_err;
795
796 pnv_calc_dpll_params(refclk, &clock);
797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
799 continue;
800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
803
804 this_err = abs(clock.dot - target);
805 if (this_err < err) {
806 *best_clock = clock;
807 err = this_err;
808 }
809 }
810 }
811 }
812 }
813
814 return (err != target);
815 }
816
817 /*
818 * Returns a set of divisors for the desired target clock with the given
819 * refclk, or FALSE. The returned values represent the clock equation:
820 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
821 *
822 * Target and reference clocks are specified in kHz.
823 *
824 * If match_clock is provided, then best_clock P divider must match the P
825 * divider from @match_clock used for LVDS downclocking.
826 */
827 static bool
828 g4x_find_best_dpll(const intel_limit_t *limit,
829 struct intel_crtc_state *crtc_state,
830 int target, int refclk, intel_clock_t *match_clock,
831 intel_clock_t *best_clock)
832 {
833 struct drm_device *dev = crtc_state->base.crtc->dev;
834 intel_clock_t clock;
835 int max_n;
836 bool found = false;
837 /* approximately equals target * 0.00585 */
838 int err_most = (target >> 8) + (target >> 9);
839
840 memset(best_clock, 0, sizeof(*best_clock));
841
842 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
843
844 max_n = limit->n.max;
845 /* based on hardware requirement, prefer smaller n to precision */
846 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
847 /* based on hardware requirement, prefere larger m1,m2 */
848 for (clock.m1 = limit->m1.max;
849 clock.m1 >= limit->m1.min; clock.m1--) {
850 for (clock.m2 = limit->m2.max;
851 clock.m2 >= limit->m2.min; clock.m2--) {
852 for (clock.p1 = limit->p1.max;
853 clock.p1 >= limit->p1.min; clock.p1--) {
854 int this_err;
855
856 i9xx_calc_dpll_params(refclk, &clock);
857 if (!intel_PLL_is_valid(dev, limit,
858 &clock))
859 continue;
860
861 this_err = abs(clock.dot - target);
862 if (this_err < err_most) {
863 *best_clock = clock;
864 err_most = this_err;
865 max_n = clock.n;
866 found = true;
867 }
868 }
869 }
870 }
871 }
872 return found;
873 }
874
875 /*
876 * Check if the calculated PLL configuration is more optimal compared to the
877 * best configuration and error found so far. Return the calculated error.
878 */
879 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
880 const intel_clock_t *calculated_clock,
881 const intel_clock_t *best_clock,
882 unsigned int best_error_ppm,
883 unsigned int *error_ppm)
884 {
885 /*
886 * For CHV ignore the error and consider only the P value.
887 * Prefer a bigger P value based on HW requirements.
888 */
889 if (IS_CHERRYVIEW(dev)) {
890 *error_ppm = 0;
891
892 return calculated_clock->p > best_clock->p;
893 }
894
895 if (WARN_ON_ONCE(!target_freq))
896 return false;
897
898 *error_ppm = div_u64(1000000ULL *
899 abs(target_freq - calculated_clock->dot),
900 target_freq);
901 /*
902 * Prefer a better P value over a better (smaller) error if the error
903 * is small. Ensure this preference for future configurations too by
904 * setting the error to 0.
905 */
906 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
907 *error_ppm = 0;
908
909 return true;
910 }
911
912 return *error_ppm + 10 < best_error_ppm;
913 }
914
915 /*
916 * Returns a set of divisors for the desired target clock with the given
917 * refclk, or FALSE. The returned values represent the clock equation:
918 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
919 */
920 static bool
921 vlv_find_best_dpll(const intel_limit_t *limit,
922 struct intel_crtc_state *crtc_state,
923 int target, int refclk, intel_clock_t *match_clock,
924 intel_clock_t *best_clock)
925 {
926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
927 struct drm_device *dev = crtc->base.dev;
928 intel_clock_t clock;
929 unsigned int bestppm = 1000000;
930 /* min update 19.2 MHz */
931 int max_n = min(limit->n.max, refclk / 19200);
932 bool found = false;
933
934 target *= 5; /* fast clock */
935
936 memset(best_clock, 0, sizeof(*best_clock));
937
938 /* based on hardware requirement, prefer smaller n to precision */
939 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
940 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
941 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
942 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
943 clock.p = clock.p1 * clock.p2;
944 /* based on hardware requirement, prefer bigger m1,m2 values */
945 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
946 unsigned int ppm;
947
948 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
949 refclk * clock.m1);
950
951 vlv_calc_dpll_params(refclk, &clock);
952
953 if (!intel_PLL_is_valid(dev, limit,
954 &clock))
955 continue;
956
957 if (!vlv_PLL_is_optimal(dev, target,
958 &clock,
959 best_clock,
960 bestppm, &ppm))
961 continue;
962
963 *best_clock = clock;
964 bestppm = ppm;
965 found = true;
966 }
967 }
968 }
969 }
970
971 return found;
972 }
973
974 /*
975 * Returns a set of divisors for the desired target clock with the given
976 * refclk, or FALSE. The returned values represent the clock equation:
977 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
978 */
979 static bool
980 chv_find_best_dpll(const intel_limit_t *limit,
981 struct intel_crtc_state *crtc_state,
982 int target, int refclk, intel_clock_t *match_clock,
983 intel_clock_t *best_clock)
984 {
985 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
986 struct drm_device *dev = crtc->base.dev;
987 unsigned int best_error_ppm;
988 intel_clock_t clock;
989 uint64_t m2;
990 int found = false;
991
992 memset(best_clock, 0, sizeof(*best_clock));
993 best_error_ppm = 1000000;
994
995 /*
996 * Based on hardware doc, the n always set to 1, and m1 always
997 * set to 2. If requires to support 200Mhz refclk, we need to
998 * revisit this because n may not 1 anymore.
999 */
1000 clock.n = 1, clock.m1 = 2;
1001 target *= 5; /* fast clock */
1002
1003 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1004 for (clock.p2 = limit->p2.p2_fast;
1005 clock.p2 >= limit->p2.p2_slow;
1006 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1007 unsigned int error_ppm;
1008
1009 clock.p = clock.p1 * clock.p2;
1010
1011 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1012 clock.n) << 22, refclk * clock.m1);
1013
1014 if (m2 > INT_MAX/clock.m1)
1015 continue;
1016
1017 clock.m2 = m2;
1018
1019 chv_calc_dpll_params(refclk, &clock);
1020
1021 if (!intel_PLL_is_valid(dev, limit, &clock))
1022 continue;
1023
1024 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1025 best_error_ppm, &error_ppm))
1026 continue;
1027
1028 *best_clock = clock;
1029 best_error_ppm = error_ppm;
1030 found = true;
1031 }
1032 }
1033
1034 return found;
1035 }
1036
1037 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1038 intel_clock_t *best_clock)
1039 {
1040 int refclk = 100000;
1041 const intel_limit_t *limit = &intel_limits_bxt;
1042
1043 return chv_find_best_dpll(limit, crtc_state,
1044 target_clock, refclk, NULL, best_clock);
1045 }
1046
1047 bool intel_crtc_active(struct drm_crtc *crtc)
1048 {
1049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1050
1051 /* Be paranoid as we can arrive here with only partial
1052 * state retrieved from the hardware during setup.
1053 *
1054 * We can ditch the adjusted_mode.crtc_clock check as soon
1055 * as Haswell has gained clock readout/fastboot support.
1056 *
1057 * We can ditch the crtc->primary->fb check as soon as we can
1058 * properly reconstruct framebuffers.
1059 *
1060 * FIXME: The intel_crtc->active here should be switched to
1061 * crtc->state->active once we have proper CRTC states wired up
1062 * for atomic.
1063 */
1064 return intel_crtc->active && crtc->primary->state->fb &&
1065 intel_crtc->config->base.adjusted_mode.crtc_clock;
1066 }
1067
1068 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1069 enum pipe pipe)
1070 {
1071 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1073
1074 return intel_crtc->config->cpu_transcoder;
1075 }
1076
1077 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1078 {
1079 struct drm_i915_private *dev_priv = dev->dev_private;
1080 i915_reg_t reg = PIPEDSL(pipe);
1081 u32 line1, line2;
1082 u32 line_mask;
1083
1084 if (IS_GEN2(dev))
1085 line_mask = DSL_LINEMASK_GEN2;
1086 else
1087 line_mask = DSL_LINEMASK_GEN3;
1088
1089 line1 = I915_READ(reg) & line_mask;
1090 msleep(5);
1091 line2 = I915_READ(reg) & line_mask;
1092
1093 return line1 == line2;
1094 }
1095
1096 /*
1097 * intel_wait_for_pipe_off - wait for pipe to turn off
1098 * @crtc: crtc whose pipe to wait for
1099 *
1100 * After disabling a pipe, we can't wait for vblank in the usual way,
1101 * spinning on the vblank interrupt status bit, since we won't actually
1102 * see an interrupt when the pipe is disabled.
1103 *
1104 * On Gen4 and above:
1105 * wait for the pipe register state bit to turn off
1106 *
1107 * Otherwise:
1108 * wait for the display line value to settle (it usually
1109 * ends up stopping at the start of the next frame).
1110 *
1111 */
1112 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1113 {
1114 struct drm_device *dev = crtc->base.dev;
1115 struct drm_i915_private *dev_priv = dev->dev_private;
1116 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1117 enum pipe pipe = crtc->pipe;
1118
1119 if (INTEL_INFO(dev)->gen >= 4) {
1120 i915_reg_t reg = PIPECONF(cpu_transcoder);
1121
1122 /* Wait for the Pipe State to go off */
1123 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1124 100))
1125 WARN(1, "pipe_off wait timed out\n");
1126 } else {
1127 /* Wait for the display line to settle */
1128 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1129 WARN(1, "pipe_off wait timed out\n");
1130 }
1131 }
1132
1133 /* Only for pre-ILK configs */
1134 void assert_pll(struct drm_i915_private *dev_priv,
1135 enum pipe pipe, bool state)
1136 {
1137 u32 val;
1138 bool cur_state;
1139
1140 val = I915_READ(DPLL(pipe));
1141 cur_state = !!(val & DPLL_VCO_ENABLE);
1142 I915_STATE_WARN(cur_state != state,
1143 "PLL state assertion failure (expected %s, current %s)\n",
1144 onoff(state), onoff(cur_state));
1145 }
1146
1147 /* XXX: the dsi pll is shared between MIPI DSI ports */
1148 void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1149 {
1150 u32 val;
1151 bool cur_state;
1152
1153 mutex_lock(&dev_priv->sb_lock);
1154 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1155 mutex_unlock(&dev_priv->sb_lock);
1156
1157 cur_state = val & DSI_PLL_VCO_EN;
1158 I915_STATE_WARN(cur_state != state,
1159 "DSI PLL state assertion failure (expected %s, current %s)\n",
1160 onoff(state), onoff(cur_state));
1161 }
1162
1163 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1164 enum pipe pipe, bool state)
1165 {
1166 bool cur_state;
1167 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1168 pipe);
1169
1170 if (HAS_DDI(dev_priv->dev)) {
1171 /* DDI does not have a specific FDI_TX register */
1172 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1173 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1174 } else {
1175 u32 val = I915_READ(FDI_TX_CTL(pipe));
1176 cur_state = !!(val & FDI_TX_ENABLE);
1177 }
1178 I915_STATE_WARN(cur_state != state,
1179 "FDI TX state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1181 }
1182 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1183 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1184
1185 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 u32 val;
1189 bool cur_state;
1190
1191 val = I915_READ(FDI_RX_CTL(pipe));
1192 cur_state = !!(val & FDI_RX_ENABLE);
1193 I915_STATE_WARN(cur_state != state,
1194 "FDI RX state assertion failure (expected %s, current %s)\n",
1195 onoff(state), onoff(cur_state));
1196 }
1197 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1198 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1199
1200 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1201 enum pipe pipe)
1202 {
1203 u32 val;
1204
1205 /* ILK FDI PLL is always enabled */
1206 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1207 return;
1208
1209 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1210 if (HAS_DDI(dev_priv->dev))
1211 return;
1212
1213 val = I915_READ(FDI_TX_CTL(pipe));
1214 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1215 }
1216
1217 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 u32 val;
1221 bool cur_state;
1222
1223 val = I915_READ(FDI_RX_CTL(pipe));
1224 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1225 I915_STATE_WARN(cur_state != state,
1226 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1227 onoff(state), onoff(cur_state));
1228 }
1229
1230 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 struct drm_device *dev = dev_priv->dev;
1234 i915_reg_t pp_reg;
1235 u32 val;
1236 enum pipe panel_pipe = PIPE_A;
1237 bool locked = true;
1238
1239 if (WARN_ON(HAS_DDI(dev)))
1240 return;
1241
1242 if (HAS_PCH_SPLIT(dev)) {
1243 u32 port_sel;
1244
1245 pp_reg = PCH_PP_CONTROL;
1246 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1247
1248 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1249 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1250 panel_pipe = PIPE_B;
1251 /* XXX: else fix for eDP */
1252 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1253 /* presumably write lock depends on pipe, not port select */
1254 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1255 panel_pipe = pipe;
1256 } else {
1257 pp_reg = PP_CONTROL;
1258 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1259 panel_pipe = PIPE_B;
1260 }
1261
1262 val = I915_READ(pp_reg);
1263 if (!(val & PANEL_POWER_ON) ||
1264 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1265 locked = false;
1266
1267 I915_STATE_WARN(panel_pipe == pipe && locked,
1268 "panel assertion failure, pipe %c regs locked\n",
1269 pipe_name(pipe));
1270 }
1271
1272 static void assert_cursor(struct drm_i915_private *dev_priv,
1273 enum pipe pipe, bool state)
1274 {
1275 struct drm_device *dev = dev_priv->dev;
1276 bool cur_state;
1277
1278 if (IS_845G(dev) || IS_I865G(dev))
1279 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1280 else
1281 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1282
1283 I915_STATE_WARN(cur_state != state,
1284 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1285 pipe_name(pipe), onoff(state), onoff(cur_state));
1286 }
1287 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1288 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1289
1290 void assert_pipe(struct drm_i915_private *dev_priv,
1291 enum pipe pipe, bool state)
1292 {
1293 bool cur_state;
1294 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1295 pipe);
1296 enum intel_display_power_domain power_domain;
1297
1298 /* if we need the pipe quirk it must be always on */
1299 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1300 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1301 state = true;
1302
1303 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
1304 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
1305 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1306 cur_state = !!(val & PIPECONF_ENABLE);
1307
1308 intel_display_power_put(dev_priv, power_domain);
1309 } else {
1310 cur_state = false;
1311 }
1312
1313 I915_STATE_WARN(cur_state != state,
1314 "pipe %c assertion failure (expected %s, current %s)\n",
1315 pipe_name(pipe), onoff(state), onoff(cur_state));
1316 }
1317
1318 static void assert_plane(struct drm_i915_private *dev_priv,
1319 enum plane plane, bool state)
1320 {
1321 u32 val;
1322 bool cur_state;
1323
1324 val = I915_READ(DSPCNTR(plane));
1325 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1326 I915_STATE_WARN(cur_state != state,
1327 "plane %c assertion failure (expected %s, current %s)\n",
1328 plane_name(plane), onoff(state), onoff(cur_state));
1329 }
1330
1331 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1332 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1333
1334 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1335 enum pipe pipe)
1336 {
1337 struct drm_device *dev = dev_priv->dev;
1338 int i;
1339
1340 /* Primary planes are fixed to pipes on gen4+ */
1341 if (INTEL_INFO(dev)->gen >= 4) {
1342 u32 val = I915_READ(DSPCNTR(pipe));
1343 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1344 "plane %c assertion failure, should be disabled but not\n",
1345 plane_name(pipe));
1346 return;
1347 }
1348
1349 /* Need to check both planes against the pipe */
1350 for_each_pipe(dev_priv, i) {
1351 u32 val = I915_READ(DSPCNTR(i));
1352 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1353 DISPPLANE_SEL_PIPE_SHIFT;
1354 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1355 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(i), pipe_name(pipe));
1357 }
1358 }
1359
1360 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1361 enum pipe pipe)
1362 {
1363 struct drm_device *dev = dev_priv->dev;
1364 int sprite;
1365
1366 if (INTEL_INFO(dev)->gen >= 9) {
1367 for_each_sprite(dev_priv, pipe, sprite) {
1368 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1369 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1370 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1371 sprite, pipe_name(pipe));
1372 }
1373 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1374 for_each_sprite(dev_priv, pipe, sprite) {
1375 u32 val = I915_READ(SPCNTR(pipe, sprite));
1376 I915_STATE_WARN(val & SP_ENABLE,
1377 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1378 sprite_name(pipe, sprite), pipe_name(pipe));
1379 }
1380 } else if (INTEL_INFO(dev)->gen >= 7) {
1381 u32 val = I915_READ(SPRCTL(pipe));
1382 I915_STATE_WARN(val & SPRITE_ENABLE,
1383 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1384 plane_name(pipe), pipe_name(pipe));
1385 } else if (INTEL_INFO(dev)->gen >= 5) {
1386 u32 val = I915_READ(DVSCNTR(pipe));
1387 I915_STATE_WARN(val & DVS_ENABLE,
1388 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(pipe), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_vblank_disabled(struct drm_crtc *crtc)
1394 {
1395 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1396 drm_crtc_vblank_put(crtc);
1397 }
1398
1399 void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe)
1401 {
1402 u32 val;
1403 bool enabled;
1404
1405 val = I915_READ(PCH_TRANSCONF(pipe));
1406 enabled = !!(val & TRANS_ENABLE);
1407 I915_STATE_WARN(enabled,
1408 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1409 pipe_name(pipe));
1410 }
1411
1412 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1413 enum pipe pipe, u32 port_sel, u32 val)
1414 {
1415 if ((val & DP_PORT_EN) == 0)
1416 return false;
1417
1418 if (HAS_PCH_CPT(dev_priv->dev)) {
1419 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1420 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1421 return false;
1422 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1423 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1424 return false;
1425 } else {
1426 if ((val & DP_PIPE_MASK) != (pipe << 30))
1427 return false;
1428 }
1429 return true;
1430 }
1431
1432 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1433 enum pipe pipe, u32 val)
1434 {
1435 if ((val & SDVO_ENABLE) == 0)
1436 return false;
1437
1438 if (HAS_PCH_CPT(dev_priv->dev)) {
1439 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1440 return false;
1441 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1442 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1443 return false;
1444 } else {
1445 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1446 return false;
1447 }
1448 return true;
1449 }
1450
1451 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe, u32 val)
1453 {
1454 if ((val & LVDS_PORT_EN) == 0)
1455 return false;
1456
1457 if (HAS_PCH_CPT(dev_priv->dev)) {
1458 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459 return false;
1460 } else {
1461 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1462 return false;
1463 }
1464 return true;
1465 }
1466
1467 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe, u32 val)
1469 {
1470 if ((val & ADPA_DAC_ENABLE) == 0)
1471 return false;
1472 if (HAS_PCH_CPT(dev_priv->dev)) {
1473 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1474 return false;
1475 } else {
1476 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1477 return false;
1478 }
1479 return true;
1480 }
1481
1482 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1483 enum pipe pipe, i915_reg_t reg,
1484 u32 port_sel)
1485 {
1486 u32 val = I915_READ(reg);
1487 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1488 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1489 i915_mmio_reg_offset(reg), pipe_name(pipe));
1490
1491 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1492 && (val & DP_PIPEB_SELECT),
1493 "IBX PCH dp port still using transcoder B\n");
1494 }
1495
1496 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, i915_reg_t reg)
1498 {
1499 u32 val = I915_READ(reg);
1500 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1501 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1502 i915_mmio_reg_offset(reg), pipe_name(pipe));
1503
1504 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1505 && (val & SDVO_PIPE_B_SELECT),
1506 "IBX PCH hdmi port still using transcoder B\n");
1507 }
1508
1509 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1510 enum pipe pipe)
1511 {
1512 u32 val;
1513
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1516 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1517
1518 val = I915_READ(PCH_ADPA);
1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
1521 pipe_name(pipe));
1522
1523 val = I915_READ(PCH_LVDS);
1524 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1525 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1526 pipe_name(pipe));
1527
1528 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1531 }
1532
1533 static void vlv_enable_pll(struct intel_crtc *crtc,
1534 const struct intel_crtc_state *pipe_config)
1535 {
1536 struct drm_device *dev = crtc->base.dev;
1537 struct drm_i915_private *dev_priv = dev->dev_private;
1538 enum pipe pipe = crtc->pipe;
1539 i915_reg_t reg = DPLL(pipe);
1540 u32 dpll = pipe_config->dpll_hw_state.dpll;
1541
1542 assert_pipe_disabled(dev_priv, pipe);
1543
1544 /* PLL is protected by panel, make sure we can write it */
1545 assert_panel_unlocked(dev_priv, pipe);
1546
1547 I915_WRITE(reg, dpll);
1548 POSTING_READ(reg);
1549 udelay(150);
1550
1551 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552 DRM_ERROR("DPLL %d failed to lock\n", pipe);
1553
1554 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1555 POSTING_READ(DPLL_MD(pipe));
1556 }
1557
1558 static void chv_enable_pll(struct intel_crtc *crtc,
1559 const struct intel_crtc_state *pipe_config)
1560 {
1561 struct drm_device *dev = crtc->base.dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 enum pipe pipe = crtc->pipe;
1564 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1565 u32 tmp;
1566
1567 assert_pipe_disabled(dev_priv, pipe);
1568
1569 /* PLL is protected by panel, make sure we can write it */
1570 assert_panel_unlocked(dev_priv, pipe);
1571
1572 mutex_lock(&dev_priv->sb_lock);
1573
1574 /* Enable back the 10bit clock to display controller */
1575 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1576 tmp |= DPIO_DCLKP_EN;
1577 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1578
1579 mutex_unlock(&dev_priv->sb_lock);
1580
1581 /*
1582 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1583 */
1584 udelay(1);
1585
1586 /* Enable PLL */
1587 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1588
1589 /* Check PLL is locked */
1590 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1591 DRM_ERROR("PLL %d failed to lock\n", pipe);
1592
1593 if (pipe != PIPE_A) {
1594 /*
1595 * WaPixelRepeatModeFixForC0:chv
1596 *
1597 * DPLLCMD is AWOL. Use chicken bits to propagate
1598 * the value from DPLLBMD to either pipe B or C.
1599 */
1600 I915_WRITE(CBR4_VLV, pipe == PIPE_B ? CBR_DPLLBMD_PIPE_B : CBR_DPLLBMD_PIPE_C);
1601 I915_WRITE(DPLL_MD(PIPE_B), pipe_config->dpll_hw_state.dpll_md);
1602 I915_WRITE(CBR4_VLV, 0);
1603 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md;
1604
1605 /*
1606 * DPLLB VGA mode also seems to cause problems.
1607 * We should always have it disabled.
1608 */
1609 WARN_ON((I915_READ(DPLL(PIPE_B)) & DPLL_VGA_MODE_DIS) == 0);
1610 } else {
1611 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1612 POSTING_READ(DPLL_MD(pipe));
1613 }
1614 }
1615
1616 static int intel_num_dvo_pipes(struct drm_device *dev)
1617 {
1618 struct intel_crtc *crtc;
1619 int count = 0;
1620
1621 for_each_intel_crtc(dev, crtc)
1622 count += crtc->base.state->active &&
1623 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1624
1625 return count;
1626 }
1627
1628 static void i9xx_enable_pll(struct intel_crtc *crtc)
1629 {
1630 struct drm_device *dev = crtc->base.dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 i915_reg_t reg = DPLL(crtc->pipe);
1633 u32 dpll = crtc->config->dpll_hw_state.dpll;
1634
1635 assert_pipe_disabled(dev_priv, crtc->pipe);
1636
1637 /* PLL is protected by panel, make sure we can write it */
1638 if (IS_MOBILE(dev) && !IS_I830(dev))
1639 assert_panel_unlocked(dev_priv, crtc->pipe);
1640
1641 /* Enable DVO 2x clock on both PLLs if necessary */
1642 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1643 /*
1644 * It appears to be important that we don't enable this
1645 * for the current pipe before otherwise configuring the
1646 * PLL. No idea how this should be handled if multiple
1647 * DVO outputs are enabled simultaneosly.
1648 */
1649 dpll |= DPLL_DVO_2X_MODE;
1650 I915_WRITE(DPLL(!crtc->pipe),
1651 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1652 }
1653
1654 /*
1655 * Apparently we need to have VGA mode enabled prior to changing
1656 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1657 * dividers, even though the register value does change.
1658 */
1659 I915_WRITE(reg, 0);
1660
1661 I915_WRITE(reg, dpll);
1662
1663 /* Wait for the clocks to stabilize. */
1664 POSTING_READ(reg);
1665 udelay(150);
1666
1667 if (INTEL_INFO(dev)->gen >= 4) {
1668 I915_WRITE(DPLL_MD(crtc->pipe),
1669 crtc->config->dpll_hw_state.dpll_md);
1670 } else {
1671 /* The pixel multiplier can only be updated once the
1672 * DPLL is enabled and the clocks are stable.
1673 *
1674 * So write it again.
1675 */
1676 I915_WRITE(reg, dpll);
1677 }
1678
1679 /* We do this three times for luck */
1680 I915_WRITE(reg, dpll);
1681 POSTING_READ(reg);
1682 udelay(150); /* wait for warmup */
1683 I915_WRITE(reg, dpll);
1684 POSTING_READ(reg);
1685 udelay(150); /* wait for warmup */
1686 I915_WRITE(reg, dpll);
1687 POSTING_READ(reg);
1688 udelay(150); /* wait for warmup */
1689 }
1690
1691 /**
1692 * i9xx_disable_pll - disable a PLL
1693 * @dev_priv: i915 private structure
1694 * @pipe: pipe PLL to disable
1695 *
1696 * Disable the PLL for @pipe, making sure the pipe is off first.
1697 *
1698 * Note! This is for pre-ILK only.
1699 */
1700 static void i9xx_disable_pll(struct intel_crtc *crtc)
1701 {
1702 struct drm_device *dev = crtc->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 enum pipe pipe = crtc->pipe;
1705
1706 /* Disable DVO 2x clock on both PLLs if necessary */
1707 if (IS_I830(dev) &&
1708 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1709 !intel_num_dvo_pipes(dev)) {
1710 I915_WRITE(DPLL(PIPE_B),
1711 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1712 I915_WRITE(DPLL(PIPE_A),
1713 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1714 }
1715
1716 /* Don't disable pipe or pipe PLLs if needed */
1717 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1718 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1719 return;
1720
1721 /* Make sure the pipe isn't still relying on us */
1722 assert_pipe_disabled(dev_priv, pipe);
1723
1724 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1725 POSTING_READ(DPLL(pipe));
1726 }
1727
1728 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1729 {
1730 u32 val;
1731
1732 /* Make sure the pipe isn't still relying on us */
1733 assert_pipe_disabled(dev_priv, pipe);
1734
1735 val = DPLL_INTEGRATED_REF_CLK_VLV |
1736 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1737 if (pipe != PIPE_A)
1738 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1739
1740 I915_WRITE(DPLL(pipe), val);
1741 POSTING_READ(DPLL(pipe));
1742 }
1743
1744 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1745 {
1746 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1747 u32 val;
1748
1749 /* Make sure the pipe isn't still relying on us */
1750 assert_pipe_disabled(dev_priv, pipe);
1751
1752 val = DPLL_SSC_REF_CLK_CHV |
1753 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1754 if (pipe != PIPE_A)
1755 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1756
1757 I915_WRITE(DPLL(pipe), val);
1758 POSTING_READ(DPLL(pipe));
1759
1760 mutex_lock(&dev_priv->sb_lock);
1761
1762 /* Disable 10bit clock to display controller */
1763 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1764 val &= ~DPIO_DCLKP_EN;
1765 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1766
1767 mutex_unlock(&dev_priv->sb_lock);
1768 }
1769
1770 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1771 struct intel_digital_port *dport,
1772 unsigned int expected_mask)
1773 {
1774 u32 port_mask;
1775 i915_reg_t dpll_reg;
1776
1777 switch (dport->port) {
1778 case PORT_B:
1779 port_mask = DPLL_PORTB_READY_MASK;
1780 dpll_reg = DPLL(0);
1781 break;
1782 case PORT_C:
1783 port_mask = DPLL_PORTC_READY_MASK;
1784 dpll_reg = DPLL(0);
1785 expected_mask <<= 4;
1786 break;
1787 case PORT_D:
1788 port_mask = DPLL_PORTD_READY_MASK;
1789 dpll_reg = DPIO_PHY_STATUS;
1790 break;
1791 default:
1792 BUG();
1793 }
1794
1795 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1796 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1797 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1798 }
1799
1800 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1801 enum pipe pipe)
1802 {
1803 struct drm_device *dev = dev_priv->dev;
1804 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1806 i915_reg_t reg;
1807 uint32_t val, pipeconf_val;
1808
1809 /* Make sure PCH DPLL is enabled */
1810 assert_shared_dpll_enabled(dev_priv, intel_crtc->config->shared_dpll);
1811
1812 /* FDI must be feeding us bits for PCH ports */
1813 assert_fdi_tx_enabled(dev_priv, pipe);
1814 assert_fdi_rx_enabled(dev_priv, pipe);
1815
1816 if (HAS_PCH_CPT(dev)) {
1817 /* Workaround: Set the timing override bit before enabling the
1818 * pch transcoder. */
1819 reg = TRANS_CHICKEN2(pipe);
1820 val = I915_READ(reg);
1821 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1822 I915_WRITE(reg, val);
1823 }
1824
1825 reg = PCH_TRANSCONF(pipe);
1826 val = I915_READ(reg);
1827 pipeconf_val = I915_READ(PIPECONF(pipe));
1828
1829 if (HAS_PCH_IBX(dev_priv->dev)) {
1830 /*
1831 * Make the BPC in transcoder be consistent with
1832 * that in pipeconf reg. For HDMI we must use 8bpc
1833 * here for both 8bpc and 12bpc.
1834 */
1835 val &= ~PIPECONF_BPC_MASK;
1836 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1837 val |= PIPECONF_8BPC;
1838 else
1839 val |= pipeconf_val & PIPECONF_BPC_MASK;
1840 }
1841
1842 val &= ~TRANS_INTERLACE_MASK;
1843 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1844 if (HAS_PCH_IBX(dev_priv->dev) &&
1845 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1846 val |= TRANS_LEGACY_INTERLACED_ILK;
1847 else
1848 val |= TRANS_INTERLACED;
1849 else
1850 val |= TRANS_PROGRESSIVE;
1851
1852 I915_WRITE(reg, val | TRANS_ENABLE);
1853 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1854 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1855 }
1856
1857 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1858 enum transcoder cpu_transcoder)
1859 {
1860 u32 val, pipeconf_val;
1861
1862 /* FDI must be feeding us bits for PCH ports */
1863 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1864 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1865
1866 /* Workaround: set timing override bit. */
1867 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1868 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1869 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1870
1871 val = TRANS_ENABLE;
1872 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1873
1874 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1875 PIPECONF_INTERLACED_ILK)
1876 val |= TRANS_INTERLACED;
1877 else
1878 val |= TRANS_PROGRESSIVE;
1879
1880 I915_WRITE(LPT_TRANSCONF, val);
1881 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1882 DRM_ERROR("Failed to enable PCH transcoder\n");
1883 }
1884
1885 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887 {
1888 struct drm_device *dev = dev_priv->dev;
1889 i915_reg_t reg;
1890 uint32_t val;
1891
1892 /* FDI relies on the transcoder */
1893 assert_fdi_tx_disabled(dev_priv, pipe);
1894 assert_fdi_rx_disabled(dev_priv, pipe);
1895
1896 /* Ports must be off as well */
1897 assert_pch_ports_disabled(dev_priv, pipe);
1898
1899 reg = PCH_TRANSCONF(pipe);
1900 val = I915_READ(reg);
1901 val &= ~TRANS_ENABLE;
1902 I915_WRITE(reg, val);
1903 /* wait for PCH transcoder off, transcoder state */
1904 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1905 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1906
1907 if (HAS_PCH_CPT(dev)) {
1908 /* Workaround: Clear the timing override chicken bit again. */
1909 reg = TRANS_CHICKEN2(pipe);
1910 val = I915_READ(reg);
1911 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1912 I915_WRITE(reg, val);
1913 }
1914 }
1915
1916 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1917 {
1918 u32 val;
1919
1920 val = I915_READ(LPT_TRANSCONF);
1921 val &= ~TRANS_ENABLE;
1922 I915_WRITE(LPT_TRANSCONF, val);
1923 /* wait for PCH transcoder off, transcoder state */
1924 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1925 DRM_ERROR("Failed to disable PCH transcoder\n");
1926
1927 /* Workaround: clear timing override bit. */
1928 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
1929 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1930 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
1931 }
1932
1933 /**
1934 * intel_enable_pipe - enable a pipe, asserting requirements
1935 * @crtc: crtc responsible for the pipe
1936 *
1937 * Enable @crtc's pipe, making sure that various hardware specific requirements
1938 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1939 */
1940 static void intel_enable_pipe(struct intel_crtc *crtc)
1941 {
1942 struct drm_device *dev = crtc->base.dev;
1943 struct drm_i915_private *dev_priv = dev->dev_private;
1944 enum pipe pipe = crtc->pipe;
1945 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1946 enum pipe pch_transcoder;
1947 i915_reg_t reg;
1948 u32 val;
1949
1950 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
1951
1952 assert_planes_disabled(dev_priv, pipe);
1953 assert_cursor_disabled(dev_priv, pipe);
1954 assert_sprites_disabled(dev_priv, pipe);
1955
1956 if (HAS_PCH_LPT(dev_priv->dev))
1957 pch_transcoder = TRANSCODER_A;
1958 else
1959 pch_transcoder = pipe;
1960
1961 /*
1962 * A pipe without a PLL won't actually be able to drive bits from
1963 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1964 * need the check.
1965 */
1966 if (HAS_GMCH_DISPLAY(dev_priv->dev))
1967 if (crtc->config->has_dsi_encoder)
1968 assert_dsi_pll_enabled(dev_priv);
1969 else
1970 assert_pll_enabled(dev_priv, pipe);
1971 else {
1972 if (crtc->config->has_pch_encoder) {
1973 /* if driving the PCH, we need FDI enabled */
1974 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1975 assert_fdi_tx_pll_enabled(dev_priv,
1976 (enum pipe) cpu_transcoder);
1977 }
1978 /* FIXME: assert CPU port conditions for SNB+ */
1979 }
1980
1981 reg = PIPECONF(cpu_transcoder);
1982 val = I915_READ(reg);
1983 if (val & PIPECONF_ENABLE) {
1984 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1985 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
1986 return;
1987 }
1988
1989 I915_WRITE(reg, val | PIPECONF_ENABLE);
1990 POSTING_READ(reg);
1991
1992 /*
1993 * Until the pipe starts DSL will read as 0, which would cause
1994 * an apparent vblank timestamp jump, which messes up also the
1995 * frame count when it's derived from the timestamps. So let's
1996 * wait for the pipe to start properly before we call
1997 * drm_crtc_vblank_on()
1998 */
1999 if (dev->max_vblank_count == 0 &&
2000 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2001 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2002 }
2003
2004 /**
2005 * intel_disable_pipe - disable a pipe, asserting requirements
2006 * @crtc: crtc whose pipes is to be disabled
2007 *
2008 * Disable the pipe of @crtc, making sure that various hardware
2009 * specific requirements are met, if applicable, e.g. plane
2010 * disabled, panel fitter off, etc.
2011 *
2012 * Will wait until the pipe has shut down before returning.
2013 */
2014 static void intel_disable_pipe(struct intel_crtc *crtc)
2015 {
2016 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2017 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2018 enum pipe pipe = crtc->pipe;
2019 i915_reg_t reg;
2020 u32 val;
2021
2022 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2023
2024 /*
2025 * Make sure planes won't keep trying to pump pixels to us,
2026 * or we might hang the display.
2027 */
2028 assert_planes_disabled(dev_priv, pipe);
2029 assert_cursor_disabled(dev_priv, pipe);
2030 assert_sprites_disabled(dev_priv, pipe);
2031
2032 reg = PIPECONF(cpu_transcoder);
2033 val = I915_READ(reg);
2034 if ((val & PIPECONF_ENABLE) == 0)
2035 return;
2036
2037 /*
2038 * Double wide has implications for planes
2039 * so best keep it disabled when not needed.
2040 */
2041 if (crtc->config->double_wide)
2042 val &= ~PIPECONF_DOUBLE_WIDE;
2043
2044 /* Don't disable pipe or pipe PLLs if needed */
2045 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2046 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2047 val &= ~PIPECONF_ENABLE;
2048
2049 I915_WRITE(reg, val);
2050 if ((val & PIPECONF_ENABLE) == 0)
2051 intel_wait_for_pipe_off(crtc);
2052 }
2053
2054 static bool need_vtd_wa(struct drm_device *dev)
2055 {
2056 #ifdef CONFIG_INTEL_IOMMU
2057 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2058 return true;
2059 #endif
2060 return false;
2061 }
2062
2063 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2064 {
2065 return IS_GEN2(dev_priv) ? 2048 : 4096;
2066 }
2067
2068 static unsigned int intel_tile_width_bytes(const struct drm_i915_private *dev_priv,
2069 uint64_t fb_modifier, unsigned int cpp)
2070 {
2071 switch (fb_modifier) {
2072 case DRM_FORMAT_MOD_NONE:
2073 return cpp;
2074 case I915_FORMAT_MOD_X_TILED:
2075 if (IS_GEN2(dev_priv))
2076 return 128;
2077 else
2078 return 512;
2079 case I915_FORMAT_MOD_Y_TILED:
2080 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2081 return 128;
2082 else
2083 return 512;
2084 case I915_FORMAT_MOD_Yf_TILED:
2085 switch (cpp) {
2086 case 1:
2087 return 64;
2088 case 2:
2089 case 4:
2090 return 128;
2091 case 8:
2092 case 16:
2093 return 256;
2094 default:
2095 MISSING_CASE(cpp);
2096 return cpp;
2097 }
2098 break;
2099 default:
2100 MISSING_CASE(fb_modifier);
2101 return cpp;
2102 }
2103 }
2104
2105 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2106 uint64_t fb_modifier, unsigned int cpp)
2107 {
2108 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2109 return 1;
2110 else
2111 return intel_tile_size(dev_priv) /
2112 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2113 }
2114
2115 /* Return the tile dimensions in pixel units */
2116 static void intel_tile_dims(const struct drm_i915_private *dev_priv,
2117 unsigned int *tile_width,
2118 unsigned int *tile_height,
2119 uint64_t fb_modifier,
2120 unsigned int cpp)
2121 {
2122 unsigned int tile_width_bytes =
2123 intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2124
2125 *tile_width = tile_width_bytes / cpp;
2126 *tile_height = intel_tile_size(dev_priv) / tile_width_bytes;
2127 }
2128
2129 unsigned int
2130 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2131 uint32_t pixel_format, uint64_t fb_modifier)
2132 {
2133 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2134 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2135
2136 return ALIGN(height, tile_height);
2137 }
2138
2139 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
2140 {
2141 unsigned int size = 0;
2142 int i;
2143
2144 for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
2145 size += rot_info->plane[i].width * rot_info->plane[i].height;
2146
2147 return size;
2148 }
2149
2150 static void
2151 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
2152 const struct drm_framebuffer *fb,
2153 unsigned int rotation)
2154 {
2155 if (intel_rotation_90_or_270(rotation)) {
2156 *view = i915_ggtt_view_rotated;
2157 view->params.rotated = to_intel_framebuffer(fb)->rot_info;
2158 } else {
2159 *view = i915_ggtt_view_normal;
2160 }
2161 }
2162
2163 static void
2164 intel_fill_fb_info(struct drm_i915_private *dev_priv,
2165 struct drm_framebuffer *fb)
2166 {
2167 struct intel_rotation_info *info = &to_intel_framebuffer(fb)->rot_info;
2168 unsigned int tile_size, tile_width, tile_height, cpp;
2169
2170 tile_size = intel_tile_size(dev_priv);
2171
2172 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2173 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2174 fb->modifier[0], cpp);
2175
2176 info->plane[0].width = DIV_ROUND_UP(fb->pitches[0], tile_width * cpp);
2177 info->plane[0].height = DIV_ROUND_UP(fb->height, tile_height);
2178
2179 if (info->pixel_format == DRM_FORMAT_NV12) {
2180 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2181 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2182 fb->modifier[1], cpp);
2183
2184 info->uv_offset = fb->offsets[1];
2185 info->plane[1].width = DIV_ROUND_UP(fb->pitches[1], tile_width * cpp);
2186 info->plane[1].height = DIV_ROUND_UP(fb->height / 2, tile_height);
2187 }
2188 }
2189
2190 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2191 {
2192 if (INTEL_INFO(dev_priv)->gen >= 9)
2193 return 256 * 1024;
2194 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2195 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2196 return 128 * 1024;
2197 else if (INTEL_INFO(dev_priv)->gen >= 4)
2198 return 4 * 1024;
2199 else
2200 return 0;
2201 }
2202
2203 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2204 uint64_t fb_modifier)
2205 {
2206 switch (fb_modifier) {
2207 case DRM_FORMAT_MOD_NONE:
2208 return intel_linear_alignment(dev_priv);
2209 case I915_FORMAT_MOD_X_TILED:
2210 if (INTEL_INFO(dev_priv)->gen >= 9)
2211 return 256 * 1024;
2212 return 0;
2213 case I915_FORMAT_MOD_Y_TILED:
2214 case I915_FORMAT_MOD_Yf_TILED:
2215 return 1 * 1024 * 1024;
2216 default:
2217 MISSING_CASE(fb_modifier);
2218 return 0;
2219 }
2220 }
2221
2222 int
2223 intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
2224 unsigned int rotation)
2225 {
2226 struct drm_device *dev = fb->dev;
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2229 struct i915_ggtt_view view;
2230 u32 alignment;
2231 int ret;
2232
2233 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2234
2235 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2236
2237 intel_fill_fb_ggtt_view(&view, fb, rotation);
2238
2239 /* Note that the w/a also requires 64 PTE of padding following the
2240 * bo. We currently fill all unused PTE with the shadow page and so
2241 * we should always have valid PTE following the scanout preventing
2242 * the VT-d warning.
2243 */
2244 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2245 alignment = 256 * 1024;
2246
2247 /*
2248 * Global gtt pte registers are special registers which actually forward
2249 * writes to a chunk of system memory. Which means that there is no risk
2250 * that the register values disappear as soon as we call
2251 * intel_runtime_pm_put(), so it is correct to wrap only the
2252 * pin/unpin/fence and not more.
2253 */
2254 intel_runtime_pm_get(dev_priv);
2255
2256 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2257 &view);
2258 if (ret)
2259 goto err_pm;
2260
2261 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2262 * fence, whereas 965+ only requires a fence if using
2263 * framebuffer compression. For simplicity, we always install
2264 * a fence as the cost is not that onerous.
2265 */
2266 if (view.type == I915_GGTT_VIEW_NORMAL) {
2267 ret = i915_gem_object_get_fence(obj);
2268 if (ret == -EDEADLK) {
2269 /*
2270 * -EDEADLK means there are no free fences
2271 * no pending flips.
2272 *
2273 * This is propagated to atomic, but it uses
2274 * -EDEADLK to force a locking recovery, so
2275 * change the returned error to -EBUSY.
2276 */
2277 ret = -EBUSY;
2278 goto err_unpin;
2279 } else if (ret)
2280 goto err_unpin;
2281
2282 i915_gem_object_pin_fence(obj);
2283 }
2284
2285 intel_runtime_pm_put(dev_priv);
2286 return 0;
2287
2288 err_unpin:
2289 i915_gem_object_unpin_from_display_plane(obj, &view);
2290 err_pm:
2291 intel_runtime_pm_put(dev_priv);
2292 return ret;
2293 }
2294
2295 static void intel_unpin_fb_obj(struct drm_framebuffer *fb, unsigned int rotation)
2296 {
2297 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2298 struct i915_ggtt_view view;
2299
2300 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2301
2302 intel_fill_fb_ggtt_view(&view, fb, rotation);
2303
2304 if (view.type == I915_GGTT_VIEW_NORMAL)
2305 i915_gem_object_unpin_fence(obj);
2306
2307 i915_gem_object_unpin_from_display_plane(obj, &view);
2308 }
2309
2310 /*
2311 * Adjust the tile offset by moving the difference into
2312 * the x/y offsets.
2313 *
2314 * Input tile dimensions and pitch must already be
2315 * rotated to match x and y, and in pixel units.
2316 */
2317 static u32 intel_adjust_tile_offset(int *x, int *y,
2318 unsigned int tile_width,
2319 unsigned int tile_height,
2320 unsigned int tile_size,
2321 unsigned int pitch_tiles,
2322 u32 old_offset,
2323 u32 new_offset)
2324 {
2325 unsigned int tiles;
2326
2327 WARN_ON(old_offset & (tile_size - 1));
2328 WARN_ON(new_offset & (tile_size - 1));
2329 WARN_ON(new_offset > old_offset);
2330
2331 tiles = (old_offset - new_offset) / tile_size;
2332
2333 *y += tiles / pitch_tiles * tile_height;
2334 *x += tiles % pitch_tiles * tile_width;
2335
2336 return new_offset;
2337 }
2338
2339 /*
2340 * Computes the linear offset to the base tile and adjusts
2341 * x, y. bytes per pixel is assumed to be a power-of-two.
2342 *
2343 * In the 90/270 rotated case, x and y are assumed
2344 * to be already rotated to match the rotated GTT view, and
2345 * pitch is the tile_height aligned framebuffer height.
2346 */
2347 u32 intel_compute_tile_offset(int *x, int *y,
2348 const struct drm_framebuffer *fb, int plane,
2349 unsigned int pitch,
2350 unsigned int rotation)
2351 {
2352 const struct drm_i915_private *dev_priv = to_i915(fb->dev);
2353 uint64_t fb_modifier = fb->modifier[plane];
2354 unsigned int cpp = drm_format_plane_cpp(fb->pixel_format, plane);
2355 u32 offset, offset_aligned, alignment;
2356
2357 alignment = intel_surf_alignment(dev_priv, fb_modifier);
2358 if (alignment)
2359 alignment--;
2360
2361 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2362 unsigned int tile_size, tile_width, tile_height;
2363 unsigned int tile_rows, tiles, pitch_tiles;
2364
2365 tile_size = intel_tile_size(dev_priv);
2366 intel_tile_dims(dev_priv, &tile_width, &tile_height,
2367 fb_modifier, cpp);
2368
2369 if (intel_rotation_90_or_270(rotation)) {
2370 pitch_tiles = pitch / tile_height;
2371 swap(tile_width, tile_height);
2372 } else {
2373 pitch_tiles = pitch / (tile_width * cpp);
2374 }
2375
2376 tile_rows = *y / tile_height;
2377 *y %= tile_height;
2378
2379 tiles = *x / tile_width;
2380 *x %= tile_width;
2381
2382 offset = (tile_rows * pitch_tiles + tiles) * tile_size;
2383 offset_aligned = offset & ~alignment;
2384
2385 intel_adjust_tile_offset(x, y, tile_width, tile_height,
2386 tile_size, pitch_tiles,
2387 offset, offset_aligned);
2388 } else {
2389 offset = *y * pitch + *x * cpp;
2390 offset_aligned = offset & ~alignment;
2391
2392 *y = (offset & alignment) / pitch;
2393 *x = ((offset & alignment) - *y * pitch) / cpp;
2394 }
2395
2396 return offset_aligned;
2397 }
2398
2399 static int i9xx_format_to_fourcc(int format)
2400 {
2401 switch (format) {
2402 case DISPPLANE_8BPP:
2403 return DRM_FORMAT_C8;
2404 case DISPPLANE_BGRX555:
2405 return DRM_FORMAT_XRGB1555;
2406 case DISPPLANE_BGRX565:
2407 return DRM_FORMAT_RGB565;
2408 default:
2409 case DISPPLANE_BGRX888:
2410 return DRM_FORMAT_XRGB8888;
2411 case DISPPLANE_RGBX888:
2412 return DRM_FORMAT_XBGR8888;
2413 case DISPPLANE_BGRX101010:
2414 return DRM_FORMAT_XRGB2101010;
2415 case DISPPLANE_RGBX101010:
2416 return DRM_FORMAT_XBGR2101010;
2417 }
2418 }
2419
2420 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2421 {
2422 switch (format) {
2423 case PLANE_CTL_FORMAT_RGB_565:
2424 return DRM_FORMAT_RGB565;
2425 default:
2426 case PLANE_CTL_FORMAT_XRGB_8888:
2427 if (rgb_order) {
2428 if (alpha)
2429 return DRM_FORMAT_ABGR8888;
2430 else
2431 return DRM_FORMAT_XBGR8888;
2432 } else {
2433 if (alpha)
2434 return DRM_FORMAT_ARGB8888;
2435 else
2436 return DRM_FORMAT_XRGB8888;
2437 }
2438 case PLANE_CTL_FORMAT_XRGB_2101010:
2439 if (rgb_order)
2440 return DRM_FORMAT_XBGR2101010;
2441 else
2442 return DRM_FORMAT_XRGB2101010;
2443 }
2444 }
2445
2446 static bool
2447 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2448 struct intel_initial_plane_config *plane_config)
2449 {
2450 struct drm_device *dev = crtc->base.dev;
2451 struct drm_i915_private *dev_priv = to_i915(dev);
2452 struct i915_ggtt *ggtt = &dev_priv->ggtt;
2453 struct drm_i915_gem_object *obj = NULL;
2454 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2455 struct drm_framebuffer *fb = &plane_config->fb->base;
2456 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2457 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2458 PAGE_SIZE);
2459
2460 size_aligned -= base_aligned;
2461
2462 if (plane_config->size == 0)
2463 return false;
2464
2465 /* If the FB is too big, just don't use it since fbdev is not very
2466 * important and we should probably use that space with FBC or other
2467 * features. */
2468 if (size_aligned * 2 > ggtt->stolen_usable_size)
2469 return false;
2470
2471 mutex_lock(&dev->struct_mutex);
2472
2473 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2474 base_aligned,
2475 base_aligned,
2476 size_aligned);
2477 if (!obj) {
2478 mutex_unlock(&dev->struct_mutex);
2479 return false;
2480 }
2481
2482 obj->tiling_mode = plane_config->tiling;
2483 if (obj->tiling_mode == I915_TILING_X)
2484 obj->stride = fb->pitches[0];
2485
2486 mode_cmd.pixel_format = fb->pixel_format;
2487 mode_cmd.width = fb->width;
2488 mode_cmd.height = fb->height;
2489 mode_cmd.pitches[0] = fb->pitches[0];
2490 mode_cmd.modifier[0] = fb->modifier[0];
2491 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2492
2493 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2494 &mode_cmd, obj)) {
2495 DRM_DEBUG_KMS("intel fb init failed\n");
2496 goto out_unref_obj;
2497 }
2498
2499 mutex_unlock(&dev->struct_mutex);
2500
2501 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2502 return true;
2503
2504 out_unref_obj:
2505 drm_gem_object_unreference(&obj->base);
2506 mutex_unlock(&dev->struct_mutex);
2507 return false;
2508 }
2509
2510 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2511 static void
2512 update_state_fb(struct drm_plane *plane)
2513 {
2514 if (plane->fb == plane->state->fb)
2515 return;
2516
2517 if (plane->state->fb)
2518 drm_framebuffer_unreference(plane->state->fb);
2519 plane->state->fb = plane->fb;
2520 if (plane->state->fb)
2521 drm_framebuffer_reference(plane->state->fb);
2522 }
2523
2524 static void
2525 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2526 struct intel_initial_plane_config *plane_config)
2527 {
2528 struct drm_device *dev = intel_crtc->base.dev;
2529 struct drm_i915_private *dev_priv = dev->dev_private;
2530 struct drm_crtc *c;
2531 struct intel_crtc *i;
2532 struct drm_i915_gem_object *obj;
2533 struct drm_plane *primary = intel_crtc->base.primary;
2534 struct drm_plane_state *plane_state = primary->state;
2535 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2536 struct intel_plane *intel_plane = to_intel_plane(primary);
2537 struct intel_plane_state *intel_state =
2538 to_intel_plane_state(plane_state);
2539 struct drm_framebuffer *fb;
2540
2541 if (!plane_config->fb)
2542 return;
2543
2544 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2545 fb = &plane_config->fb->base;
2546 goto valid_fb;
2547 }
2548
2549 kfree(plane_config->fb);
2550
2551 /*
2552 * Failed to alloc the obj, check to see if we should share
2553 * an fb with another CRTC instead
2554 */
2555 for_each_crtc(dev, c) {
2556 i = to_intel_crtc(c);
2557
2558 if (c == &intel_crtc->base)
2559 continue;
2560
2561 if (!i->active)
2562 continue;
2563
2564 fb = c->primary->fb;
2565 if (!fb)
2566 continue;
2567
2568 obj = intel_fb_obj(fb);
2569 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2570 drm_framebuffer_reference(fb);
2571 goto valid_fb;
2572 }
2573 }
2574
2575 /*
2576 * We've failed to reconstruct the BIOS FB. Current display state
2577 * indicates that the primary plane is visible, but has a NULL FB,
2578 * which will lead to problems later if we don't fix it up. The
2579 * simplest solution is to just disable the primary plane now and
2580 * pretend the BIOS never had it enabled.
2581 */
2582 to_intel_plane_state(plane_state)->visible = false;
2583 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2584 intel_pre_disable_primary_noatomic(&intel_crtc->base);
2585 intel_plane->disable_plane(primary, &intel_crtc->base);
2586
2587 return;
2588
2589 valid_fb:
2590 plane_state->src_x = 0;
2591 plane_state->src_y = 0;
2592 plane_state->src_w = fb->width << 16;
2593 plane_state->src_h = fb->height << 16;
2594
2595 plane_state->crtc_x = 0;
2596 plane_state->crtc_y = 0;
2597 plane_state->crtc_w = fb->width;
2598 plane_state->crtc_h = fb->height;
2599
2600 intel_state->src.x1 = plane_state->src_x;
2601 intel_state->src.y1 = plane_state->src_y;
2602 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2603 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2604 intel_state->dst.x1 = plane_state->crtc_x;
2605 intel_state->dst.y1 = plane_state->crtc_y;
2606 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2607 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2608
2609 obj = intel_fb_obj(fb);
2610 if (obj->tiling_mode != I915_TILING_NONE)
2611 dev_priv->preserve_bios_swizzle = true;
2612
2613 drm_framebuffer_reference(fb);
2614 primary->fb = primary->state->fb = fb;
2615 primary->crtc = primary->state->crtc = &intel_crtc->base;
2616 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2617 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2618 }
2619
2620 static void i9xx_update_primary_plane(struct drm_plane *primary,
2621 const struct intel_crtc_state *crtc_state,
2622 const struct intel_plane_state *plane_state)
2623 {
2624 struct drm_device *dev = primary->dev;
2625 struct drm_i915_private *dev_priv = dev->dev_private;
2626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2627 struct drm_framebuffer *fb = plane_state->base.fb;
2628 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2629 int plane = intel_crtc->plane;
2630 u32 linear_offset;
2631 u32 dspcntr;
2632 i915_reg_t reg = DSPCNTR(plane);
2633 unsigned int rotation = plane_state->base.rotation;
2634 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2635 int x = plane_state->src.x1 >> 16;
2636 int y = plane_state->src.y1 >> 16;
2637
2638 dspcntr = DISPPLANE_GAMMA_ENABLE;
2639
2640 dspcntr |= DISPLAY_PLANE_ENABLE;
2641
2642 if (INTEL_INFO(dev)->gen < 4) {
2643 if (intel_crtc->pipe == PIPE_B)
2644 dspcntr |= DISPPLANE_SEL_PIPE_B;
2645
2646 /* pipesrc and dspsize control the size that is scaled from,
2647 * which should always be the user's requested size.
2648 */
2649 I915_WRITE(DSPSIZE(plane),
2650 ((crtc_state->pipe_src_h - 1) << 16) |
2651 (crtc_state->pipe_src_w - 1));
2652 I915_WRITE(DSPPOS(plane), 0);
2653 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2654 I915_WRITE(PRIMSIZE(plane),
2655 ((crtc_state->pipe_src_h - 1) << 16) |
2656 (crtc_state->pipe_src_w - 1));
2657 I915_WRITE(PRIMPOS(plane), 0);
2658 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2659 }
2660
2661 switch (fb->pixel_format) {
2662 case DRM_FORMAT_C8:
2663 dspcntr |= DISPPLANE_8BPP;
2664 break;
2665 case DRM_FORMAT_XRGB1555:
2666 dspcntr |= DISPPLANE_BGRX555;
2667 break;
2668 case DRM_FORMAT_RGB565:
2669 dspcntr |= DISPPLANE_BGRX565;
2670 break;
2671 case DRM_FORMAT_XRGB8888:
2672 dspcntr |= DISPPLANE_BGRX888;
2673 break;
2674 case DRM_FORMAT_XBGR8888:
2675 dspcntr |= DISPPLANE_RGBX888;
2676 break;
2677 case DRM_FORMAT_XRGB2101010:
2678 dspcntr |= DISPPLANE_BGRX101010;
2679 break;
2680 case DRM_FORMAT_XBGR2101010:
2681 dspcntr |= DISPPLANE_RGBX101010;
2682 break;
2683 default:
2684 BUG();
2685 }
2686
2687 if (INTEL_INFO(dev)->gen >= 4 &&
2688 obj->tiling_mode != I915_TILING_NONE)
2689 dspcntr |= DISPPLANE_TILED;
2690
2691 if (IS_G4X(dev))
2692 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2693
2694 linear_offset = y * fb->pitches[0] + x * cpp;
2695
2696 if (INTEL_INFO(dev)->gen >= 4) {
2697 intel_crtc->dspaddr_offset =
2698 intel_compute_tile_offset(&x, &y, fb, 0,
2699 fb->pitches[0], rotation);
2700 linear_offset -= intel_crtc->dspaddr_offset;
2701 } else {
2702 intel_crtc->dspaddr_offset = linear_offset;
2703 }
2704
2705 if (rotation == BIT(DRM_ROTATE_180)) {
2706 dspcntr |= DISPPLANE_ROTATE_180;
2707
2708 x += (crtc_state->pipe_src_w - 1);
2709 y += (crtc_state->pipe_src_h - 1);
2710
2711 /* Finding the last pixel of the last line of the display
2712 data and adding to linear_offset*/
2713 linear_offset +=
2714 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2715 (crtc_state->pipe_src_w - 1) * cpp;
2716 }
2717
2718 intel_crtc->adjusted_x = x;
2719 intel_crtc->adjusted_y = y;
2720
2721 I915_WRITE(reg, dspcntr);
2722
2723 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2724 if (INTEL_INFO(dev)->gen >= 4) {
2725 I915_WRITE(DSPSURF(plane),
2726 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2727 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2728 I915_WRITE(DSPLINOFF(plane), linear_offset);
2729 } else
2730 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2731 POSTING_READ(reg);
2732 }
2733
2734 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2735 struct drm_crtc *crtc)
2736 {
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int plane = intel_crtc->plane;
2741
2742 I915_WRITE(DSPCNTR(plane), 0);
2743 if (INTEL_INFO(dev_priv)->gen >= 4)
2744 I915_WRITE(DSPSURF(plane), 0);
2745 else
2746 I915_WRITE(DSPADDR(plane), 0);
2747 POSTING_READ(DSPCNTR(plane));
2748 }
2749
2750 static void ironlake_update_primary_plane(struct drm_plane *primary,
2751 const struct intel_crtc_state *crtc_state,
2752 const struct intel_plane_state *plane_state)
2753 {
2754 struct drm_device *dev = primary->dev;
2755 struct drm_i915_private *dev_priv = dev->dev_private;
2756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2757 struct drm_framebuffer *fb = plane_state->base.fb;
2758 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2759 int plane = intel_crtc->plane;
2760 u32 linear_offset;
2761 u32 dspcntr;
2762 i915_reg_t reg = DSPCNTR(plane);
2763 unsigned int rotation = plane_state->base.rotation;
2764 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2765 int x = plane_state->src.x1 >> 16;
2766 int y = plane_state->src.y1 >> 16;
2767
2768 dspcntr = DISPPLANE_GAMMA_ENABLE;
2769 dspcntr |= DISPLAY_PLANE_ENABLE;
2770
2771 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2772 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2773
2774 switch (fb->pixel_format) {
2775 case DRM_FORMAT_C8:
2776 dspcntr |= DISPPLANE_8BPP;
2777 break;
2778 case DRM_FORMAT_RGB565:
2779 dspcntr |= DISPPLANE_BGRX565;
2780 break;
2781 case DRM_FORMAT_XRGB8888:
2782 dspcntr |= DISPPLANE_BGRX888;
2783 break;
2784 case DRM_FORMAT_XBGR8888:
2785 dspcntr |= DISPPLANE_RGBX888;
2786 break;
2787 case DRM_FORMAT_XRGB2101010:
2788 dspcntr |= DISPPLANE_BGRX101010;
2789 break;
2790 case DRM_FORMAT_XBGR2101010:
2791 dspcntr |= DISPPLANE_RGBX101010;
2792 break;
2793 default:
2794 BUG();
2795 }
2796
2797 if (obj->tiling_mode != I915_TILING_NONE)
2798 dspcntr |= DISPPLANE_TILED;
2799
2800 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2801 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2802
2803 linear_offset = y * fb->pitches[0] + x * cpp;
2804 intel_crtc->dspaddr_offset =
2805 intel_compute_tile_offset(&x, &y, fb, 0,
2806 fb->pitches[0], rotation);
2807 linear_offset -= intel_crtc->dspaddr_offset;
2808 if (rotation == BIT(DRM_ROTATE_180)) {
2809 dspcntr |= DISPPLANE_ROTATE_180;
2810
2811 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2812 x += (crtc_state->pipe_src_w - 1);
2813 y += (crtc_state->pipe_src_h - 1);
2814
2815 /* Finding the last pixel of the last line of the display
2816 data and adding to linear_offset*/
2817 linear_offset +=
2818 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2819 (crtc_state->pipe_src_w - 1) * cpp;
2820 }
2821 }
2822
2823 intel_crtc->adjusted_x = x;
2824 intel_crtc->adjusted_y = y;
2825
2826 I915_WRITE(reg, dspcntr);
2827
2828 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2829 I915_WRITE(DSPSURF(plane),
2830 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2831 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2832 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2833 } else {
2834 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2835 I915_WRITE(DSPLINOFF(plane), linear_offset);
2836 }
2837 POSTING_READ(reg);
2838 }
2839
2840 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2841 uint64_t fb_modifier, uint32_t pixel_format)
2842 {
2843 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2844 return 64;
2845 } else {
2846 int cpp = drm_format_plane_cpp(pixel_format, 0);
2847
2848 return intel_tile_width_bytes(dev_priv, fb_modifier, cpp);
2849 }
2850 }
2851
2852 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2853 struct drm_i915_gem_object *obj,
2854 unsigned int plane)
2855 {
2856 struct i915_ggtt_view view;
2857 struct i915_vma *vma;
2858 u64 offset;
2859
2860 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2861 intel_plane->base.state->rotation);
2862
2863 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2864 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2865 view.type))
2866 return -1;
2867
2868 offset = vma->node.start;
2869
2870 if (plane == 1) {
2871 offset += vma->ggtt_view.params.rotated.uv_start_page *
2872 PAGE_SIZE;
2873 }
2874
2875 WARN_ON(upper_32_bits(offset));
2876
2877 return lower_32_bits(offset);
2878 }
2879
2880 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2881 {
2882 struct drm_device *dev = intel_crtc->base.dev;
2883 struct drm_i915_private *dev_priv = dev->dev_private;
2884
2885 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2886 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2887 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2888 }
2889
2890 /*
2891 * This function detaches (aka. unbinds) unused scalers in hardware
2892 */
2893 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2894 {
2895 struct intel_crtc_scaler_state *scaler_state;
2896 int i;
2897
2898 scaler_state = &intel_crtc->config->scaler_state;
2899
2900 /* loop through and disable scalers that aren't in use */
2901 for (i = 0; i < intel_crtc->num_scalers; i++) {
2902 if (!scaler_state->scalers[i].in_use)
2903 skl_detach_scaler(intel_crtc, i);
2904 }
2905 }
2906
2907 u32 skl_plane_ctl_format(uint32_t pixel_format)
2908 {
2909 switch (pixel_format) {
2910 case DRM_FORMAT_C8:
2911 return PLANE_CTL_FORMAT_INDEXED;
2912 case DRM_FORMAT_RGB565:
2913 return PLANE_CTL_FORMAT_RGB_565;
2914 case DRM_FORMAT_XBGR8888:
2915 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2916 case DRM_FORMAT_XRGB8888:
2917 return PLANE_CTL_FORMAT_XRGB_8888;
2918 /*
2919 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2920 * to be already pre-multiplied. We need to add a knob (or a different
2921 * DRM_FORMAT) for user-space to configure that.
2922 */
2923 case DRM_FORMAT_ABGR8888:
2924 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2925 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2926 case DRM_FORMAT_ARGB8888:
2927 return PLANE_CTL_FORMAT_XRGB_8888 |
2928 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2929 case DRM_FORMAT_XRGB2101010:
2930 return PLANE_CTL_FORMAT_XRGB_2101010;
2931 case DRM_FORMAT_XBGR2101010:
2932 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2933 case DRM_FORMAT_YUYV:
2934 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2935 case DRM_FORMAT_YVYU:
2936 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2937 case DRM_FORMAT_UYVY:
2938 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2939 case DRM_FORMAT_VYUY:
2940 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2941 default:
2942 MISSING_CASE(pixel_format);
2943 }
2944
2945 return 0;
2946 }
2947
2948 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2949 {
2950 switch (fb_modifier) {
2951 case DRM_FORMAT_MOD_NONE:
2952 break;
2953 case I915_FORMAT_MOD_X_TILED:
2954 return PLANE_CTL_TILED_X;
2955 case I915_FORMAT_MOD_Y_TILED:
2956 return PLANE_CTL_TILED_Y;
2957 case I915_FORMAT_MOD_Yf_TILED:
2958 return PLANE_CTL_TILED_YF;
2959 default:
2960 MISSING_CASE(fb_modifier);
2961 }
2962
2963 return 0;
2964 }
2965
2966 u32 skl_plane_ctl_rotation(unsigned int rotation)
2967 {
2968 switch (rotation) {
2969 case BIT(DRM_ROTATE_0):
2970 break;
2971 /*
2972 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
2973 * while i915 HW rotation is clockwise, thats why this swapping.
2974 */
2975 case BIT(DRM_ROTATE_90):
2976 return PLANE_CTL_ROTATE_270;
2977 case BIT(DRM_ROTATE_180):
2978 return PLANE_CTL_ROTATE_180;
2979 case BIT(DRM_ROTATE_270):
2980 return PLANE_CTL_ROTATE_90;
2981 default:
2982 MISSING_CASE(rotation);
2983 }
2984
2985 return 0;
2986 }
2987
2988 static void skylake_update_primary_plane(struct drm_plane *plane,
2989 const struct intel_crtc_state *crtc_state,
2990 const struct intel_plane_state *plane_state)
2991 {
2992 struct drm_device *dev = plane->dev;
2993 struct drm_i915_private *dev_priv = dev->dev_private;
2994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2995 struct drm_framebuffer *fb = plane_state->base.fb;
2996 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2997 int pipe = intel_crtc->pipe;
2998 u32 plane_ctl, stride_div, stride;
2999 u32 tile_height, plane_offset, plane_size;
3000 unsigned int rotation = plane_state->base.rotation;
3001 int x_offset, y_offset;
3002 u32 surf_addr;
3003 int scaler_id = plane_state->scaler_id;
3004 int src_x = plane_state->src.x1 >> 16;
3005 int src_y = plane_state->src.y1 >> 16;
3006 int src_w = drm_rect_width(&plane_state->src) >> 16;
3007 int src_h = drm_rect_height(&plane_state->src) >> 16;
3008 int dst_x = plane_state->dst.x1;
3009 int dst_y = plane_state->dst.y1;
3010 int dst_w = drm_rect_width(&plane_state->dst);
3011 int dst_h = drm_rect_height(&plane_state->dst);
3012
3013 plane_ctl = PLANE_CTL_ENABLE |
3014 PLANE_CTL_PIPE_GAMMA_ENABLE |
3015 PLANE_CTL_PIPE_CSC_ENABLE;
3016
3017 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3018 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3019 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3020 plane_ctl |= skl_plane_ctl_rotation(rotation);
3021
3022 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3023 fb->pixel_format);
3024 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3025
3026 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3027
3028 if (intel_rotation_90_or_270(rotation)) {
3029 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3030
3031 /* stride = Surface height in tiles */
3032 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3033 stride = DIV_ROUND_UP(fb->height, tile_height);
3034 x_offset = stride * tile_height - src_y - src_h;
3035 y_offset = src_x;
3036 plane_size = (src_w - 1) << 16 | (src_h - 1);
3037 } else {
3038 stride = fb->pitches[0] / stride_div;
3039 x_offset = src_x;
3040 y_offset = src_y;
3041 plane_size = (src_h - 1) << 16 | (src_w - 1);
3042 }
3043 plane_offset = y_offset << 16 | x_offset;
3044
3045 intel_crtc->adjusted_x = x_offset;
3046 intel_crtc->adjusted_y = y_offset;
3047
3048 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3049 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3050 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3051 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3052
3053 if (scaler_id >= 0) {
3054 uint32_t ps_ctrl = 0;
3055
3056 WARN_ON(!dst_w || !dst_h);
3057 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3058 crtc_state->scaler_state.scalers[scaler_id].mode;
3059 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3060 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3061 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3062 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3063 I915_WRITE(PLANE_POS(pipe, 0), 0);
3064 } else {
3065 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3066 }
3067
3068 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3069
3070 POSTING_READ(PLANE_SURF(pipe, 0));
3071 }
3072
3073 static void skylake_disable_primary_plane(struct drm_plane *primary,
3074 struct drm_crtc *crtc)
3075 {
3076 struct drm_device *dev = crtc->dev;
3077 struct drm_i915_private *dev_priv = dev->dev_private;
3078 int pipe = to_intel_crtc(crtc)->pipe;
3079
3080 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3081 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3082 POSTING_READ(PLANE_SURF(pipe, 0));
3083 }
3084
3085 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3086 static int
3087 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3088 int x, int y, enum mode_set_atomic state)
3089 {
3090 /* Support for kgdboc is disabled, this needs a major rework. */
3091 DRM_ERROR("legacy panic handler not supported any more.\n");
3092
3093 return -ENODEV;
3094 }
3095
3096 static void intel_complete_page_flips(struct drm_device *dev)
3097 {
3098 struct drm_crtc *crtc;
3099
3100 for_each_crtc(dev, crtc) {
3101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3102 enum plane plane = intel_crtc->plane;
3103
3104 intel_prepare_page_flip(dev, plane);
3105 intel_finish_page_flip_plane(dev, plane);
3106 }
3107 }
3108
3109 static void intel_update_primary_planes(struct drm_device *dev)
3110 {
3111 struct drm_crtc *crtc;
3112
3113 for_each_crtc(dev, crtc) {
3114 struct intel_plane *plane = to_intel_plane(crtc->primary);
3115 struct intel_plane_state *plane_state;
3116
3117 drm_modeset_lock_crtc(crtc, &plane->base);
3118 plane_state = to_intel_plane_state(plane->base.state);
3119
3120 if (plane_state->visible)
3121 plane->update_plane(&plane->base,
3122 to_intel_crtc_state(crtc->state),
3123 plane_state);
3124
3125 drm_modeset_unlock_crtc(crtc);
3126 }
3127 }
3128
3129 void intel_prepare_reset(struct drm_device *dev)
3130 {
3131 /* no reset support for gen2 */
3132 if (IS_GEN2(dev))
3133 return;
3134
3135 /* reset doesn't touch the display */
3136 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3137 return;
3138
3139 drm_modeset_lock_all(dev);
3140 /*
3141 * Disabling the crtcs gracefully seems nicer. Also the
3142 * g33 docs say we should at least disable all the planes.
3143 */
3144 intel_display_suspend(dev);
3145 }
3146
3147 void intel_finish_reset(struct drm_device *dev)
3148 {
3149 struct drm_i915_private *dev_priv = to_i915(dev);
3150
3151 /*
3152 * Flips in the rings will be nuked by the reset,
3153 * so complete all pending flips so that user space
3154 * will get its events and not get stuck.
3155 */
3156 intel_complete_page_flips(dev);
3157
3158 /* no reset support for gen2 */
3159 if (IS_GEN2(dev))
3160 return;
3161
3162 /* reset doesn't touch the display */
3163 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3164 /*
3165 * Flips in the rings have been nuked by the reset,
3166 * so update the base address of all primary
3167 * planes to the the last fb to make sure we're
3168 * showing the correct fb after a reset.
3169 *
3170 * FIXME: Atomic will make this obsolete since we won't schedule
3171 * CS-based flips (which might get lost in gpu resets) any more.
3172 */
3173 intel_update_primary_planes(dev);
3174 return;
3175 }
3176
3177 /*
3178 * The display has been reset as well,
3179 * so need a full re-initialization.
3180 */
3181 intel_runtime_pm_disable_interrupts(dev_priv);
3182 intel_runtime_pm_enable_interrupts(dev_priv);
3183
3184 intel_modeset_init_hw(dev);
3185
3186 spin_lock_irq(&dev_priv->irq_lock);
3187 if (dev_priv->display.hpd_irq_setup)
3188 dev_priv->display.hpd_irq_setup(dev);
3189 spin_unlock_irq(&dev_priv->irq_lock);
3190
3191 intel_display_resume(dev);
3192
3193 intel_hpd_init(dev_priv);
3194
3195 drm_modeset_unlock_all(dev);
3196 }
3197
3198 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3199 {
3200 struct drm_device *dev = crtc->dev;
3201 struct drm_i915_private *dev_priv = dev->dev_private;
3202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3203 bool pending;
3204
3205 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3206 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3207 return false;
3208
3209 spin_lock_irq(&dev->event_lock);
3210 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3211 spin_unlock_irq(&dev->event_lock);
3212
3213 return pending;
3214 }
3215
3216 static void intel_update_pipe_config(struct intel_crtc *crtc,
3217 struct intel_crtc_state *old_crtc_state)
3218 {
3219 struct drm_device *dev = crtc->base.dev;
3220 struct drm_i915_private *dev_priv = dev->dev_private;
3221 struct intel_crtc_state *pipe_config =
3222 to_intel_crtc_state(crtc->base.state);
3223
3224 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3225 crtc->base.mode = crtc->base.state->mode;
3226
3227 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3228 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3229 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3230
3231 /*
3232 * Update pipe size and adjust fitter if needed: the reason for this is
3233 * that in compute_mode_changes we check the native mode (not the pfit
3234 * mode) to see if we can flip rather than do a full mode set. In the
3235 * fastboot case, we'll flip, but if we don't update the pipesrc and
3236 * pfit state, we'll end up with a big fb scanned out into the wrong
3237 * sized surface.
3238 */
3239
3240 I915_WRITE(PIPESRC(crtc->pipe),
3241 ((pipe_config->pipe_src_w - 1) << 16) |
3242 (pipe_config->pipe_src_h - 1));
3243
3244 /* on skylake this is done by detaching scalers */
3245 if (INTEL_INFO(dev)->gen >= 9) {
3246 skl_detach_scalers(crtc);
3247
3248 if (pipe_config->pch_pfit.enabled)
3249 skylake_pfit_enable(crtc);
3250 } else if (HAS_PCH_SPLIT(dev)) {
3251 if (pipe_config->pch_pfit.enabled)
3252 ironlake_pfit_enable(crtc);
3253 else if (old_crtc_state->pch_pfit.enabled)
3254 ironlake_pfit_disable(crtc, true);
3255 }
3256 }
3257
3258 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3259 {
3260 struct drm_device *dev = crtc->dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3263 int pipe = intel_crtc->pipe;
3264 i915_reg_t reg;
3265 u32 temp;
3266
3267 /* enable normal train */
3268 reg = FDI_TX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 if (IS_IVYBRIDGE(dev)) {
3271 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3272 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3273 } else {
3274 temp &= ~FDI_LINK_TRAIN_NONE;
3275 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3276 }
3277 I915_WRITE(reg, temp);
3278
3279 reg = FDI_RX_CTL(pipe);
3280 temp = I915_READ(reg);
3281 if (HAS_PCH_CPT(dev)) {
3282 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3283 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3284 } else {
3285 temp &= ~FDI_LINK_TRAIN_NONE;
3286 temp |= FDI_LINK_TRAIN_NONE;
3287 }
3288 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3289
3290 /* wait one idle pattern time */
3291 POSTING_READ(reg);
3292 udelay(1000);
3293
3294 /* IVB wants error correction enabled */
3295 if (IS_IVYBRIDGE(dev))
3296 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3297 FDI_FE_ERRC_ENABLE);
3298 }
3299
3300 /* The FDI link training functions for ILK/Ibexpeak. */
3301 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3302 {
3303 struct drm_device *dev = crtc->dev;
3304 struct drm_i915_private *dev_priv = dev->dev_private;
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306 int pipe = intel_crtc->pipe;
3307 i915_reg_t reg;
3308 u32 temp, tries;
3309
3310 /* FDI needs bits from pipe first */
3311 assert_pipe_enabled(dev_priv, pipe);
3312
3313 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3314 for train result */
3315 reg = FDI_RX_IMR(pipe);
3316 temp = I915_READ(reg);
3317 temp &= ~FDI_RX_SYMBOL_LOCK;
3318 temp &= ~FDI_RX_BIT_LOCK;
3319 I915_WRITE(reg, temp);
3320 I915_READ(reg);
3321 udelay(150);
3322
3323 /* enable CPU FDI TX and PCH FDI RX */
3324 reg = FDI_TX_CTL(pipe);
3325 temp = I915_READ(reg);
3326 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3327 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3328 temp &= ~FDI_LINK_TRAIN_NONE;
3329 temp |= FDI_LINK_TRAIN_PATTERN_1;
3330 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3331
3332 reg = FDI_RX_CTL(pipe);
3333 temp = I915_READ(reg);
3334 temp &= ~FDI_LINK_TRAIN_NONE;
3335 temp |= FDI_LINK_TRAIN_PATTERN_1;
3336 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3337
3338 POSTING_READ(reg);
3339 udelay(150);
3340
3341 /* Ironlake workaround, enable clock pointer after FDI enable*/
3342 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3343 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3344 FDI_RX_PHASE_SYNC_POINTER_EN);
3345
3346 reg = FDI_RX_IIR(pipe);
3347 for (tries = 0; tries < 5; tries++) {
3348 temp = I915_READ(reg);
3349 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3350
3351 if ((temp & FDI_RX_BIT_LOCK)) {
3352 DRM_DEBUG_KMS("FDI train 1 done.\n");
3353 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3354 break;
3355 }
3356 }
3357 if (tries == 5)
3358 DRM_ERROR("FDI train 1 fail!\n");
3359
3360 /* Train 2 */
3361 reg = FDI_TX_CTL(pipe);
3362 temp = I915_READ(reg);
3363 temp &= ~FDI_LINK_TRAIN_NONE;
3364 temp |= FDI_LINK_TRAIN_PATTERN_2;
3365 I915_WRITE(reg, temp);
3366
3367 reg = FDI_RX_CTL(pipe);
3368 temp = I915_READ(reg);
3369 temp &= ~FDI_LINK_TRAIN_NONE;
3370 temp |= FDI_LINK_TRAIN_PATTERN_2;
3371 I915_WRITE(reg, temp);
3372
3373 POSTING_READ(reg);
3374 udelay(150);
3375
3376 reg = FDI_RX_IIR(pipe);
3377 for (tries = 0; tries < 5; tries++) {
3378 temp = I915_READ(reg);
3379 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3380
3381 if (temp & FDI_RX_SYMBOL_LOCK) {
3382 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3383 DRM_DEBUG_KMS("FDI train 2 done.\n");
3384 break;
3385 }
3386 }
3387 if (tries == 5)
3388 DRM_ERROR("FDI train 2 fail!\n");
3389
3390 DRM_DEBUG_KMS("FDI train done\n");
3391
3392 }
3393
3394 static const int snb_b_fdi_train_param[] = {
3395 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3396 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3397 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3398 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3399 };
3400
3401 /* The FDI link training functions for SNB/Cougarpoint. */
3402 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3403 {
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 int pipe = intel_crtc->pipe;
3408 i915_reg_t reg;
3409 u32 temp, i, retry;
3410
3411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3412 for train result */
3413 reg = FDI_RX_IMR(pipe);
3414 temp = I915_READ(reg);
3415 temp &= ~FDI_RX_SYMBOL_LOCK;
3416 temp &= ~FDI_RX_BIT_LOCK;
3417 I915_WRITE(reg, temp);
3418
3419 POSTING_READ(reg);
3420 udelay(150);
3421
3422 /* enable CPU FDI TX and PCH FDI RX */
3423 reg = FDI_TX_CTL(pipe);
3424 temp = I915_READ(reg);
3425 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3426 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3427 temp &= ~FDI_LINK_TRAIN_NONE;
3428 temp |= FDI_LINK_TRAIN_PATTERN_1;
3429 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3430 /* SNB-B */
3431 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3432 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3433
3434 I915_WRITE(FDI_RX_MISC(pipe),
3435 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3436
3437 reg = FDI_RX_CTL(pipe);
3438 temp = I915_READ(reg);
3439 if (HAS_PCH_CPT(dev)) {
3440 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3441 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3442 } else {
3443 temp &= ~FDI_LINK_TRAIN_NONE;
3444 temp |= FDI_LINK_TRAIN_PATTERN_1;
3445 }
3446 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3447
3448 POSTING_READ(reg);
3449 udelay(150);
3450
3451 for (i = 0; i < 4; i++) {
3452 reg = FDI_TX_CTL(pipe);
3453 temp = I915_READ(reg);
3454 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3455 temp |= snb_b_fdi_train_param[i];
3456 I915_WRITE(reg, temp);
3457
3458 POSTING_READ(reg);
3459 udelay(500);
3460
3461 for (retry = 0; retry < 5; retry++) {
3462 reg = FDI_RX_IIR(pipe);
3463 temp = I915_READ(reg);
3464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465 if (temp & FDI_RX_BIT_LOCK) {
3466 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3467 DRM_DEBUG_KMS("FDI train 1 done.\n");
3468 break;
3469 }
3470 udelay(50);
3471 }
3472 if (retry < 5)
3473 break;
3474 }
3475 if (i == 4)
3476 DRM_ERROR("FDI train 1 fail!\n");
3477
3478 /* Train 2 */
3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
3481 temp &= ~FDI_LINK_TRAIN_NONE;
3482 temp |= FDI_LINK_TRAIN_PATTERN_2;
3483 if (IS_GEN6(dev)) {
3484 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3485 /* SNB-B */
3486 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3487 }
3488 I915_WRITE(reg, temp);
3489
3490 reg = FDI_RX_CTL(pipe);
3491 temp = I915_READ(reg);
3492 if (HAS_PCH_CPT(dev)) {
3493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3494 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3495 } else {
3496 temp &= ~FDI_LINK_TRAIN_NONE;
3497 temp |= FDI_LINK_TRAIN_PATTERN_2;
3498 }
3499 I915_WRITE(reg, temp);
3500
3501 POSTING_READ(reg);
3502 udelay(150);
3503
3504 for (i = 0; i < 4; i++) {
3505 reg = FDI_TX_CTL(pipe);
3506 temp = I915_READ(reg);
3507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3508 temp |= snb_b_fdi_train_param[i];
3509 I915_WRITE(reg, temp);
3510
3511 POSTING_READ(reg);
3512 udelay(500);
3513
3514 for (retry = 0; retry < 5; retry++) {
3515 reg = FDI_RX_IIR(pipe);
3516 temp = I915_READ(reg);
3517 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3518 if (temp & FDI_RX_SYMBOL_LOCK) {
3519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3520 DRM_DEBUG_KMS("FDI train 2 done.\n");
3521 break;
3522 }
3523 udelay(50);
3524 }
3525 if (retry < 5)
3526 break;
3527 }
3528 if (i == 4)
3529 DRM_ERROR("FDI train 2 fail!\n");
3530
3531 DRM_DEBUG_KMS("FDI train done.\n");
3532 }
3533
3534 /* Manual link training for Ivy Bridge A0 parts */
3535 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3536 {
3537 struct drm_device *dev = crtc->dev;
3538 struct drm_i915_private *dev_priv = dev->dev_private;
3539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3540 int pipe = intel_crtc->pipe;
3541 i915_reg_t reg;
3542 u32 temp, i, j;
3543
3544 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3545 for train result */
3546 reg = FDI_RX_IMR(pipe);
3547 temp = I915_READ(reg);
3548 temp &= ~FDI_RX_SYMBOL_LOCK;
3549 temp &= ~FDI_RX_BIT_LOCK;
3550 I915_WRITE(reg, temp);
3551
3552 POSTING_READ(reg);
3553 udelay(150);
3554
3555 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3556 I915_READ(FDI_RX_IIR(pipe)));
3557
3558 /* Try each vswing and preemphasis setting twice before moving on */
3559 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3560 /* disable first in case we need to retry */
3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
3563 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3564 temp &= ~FDI_TX_ENABLE;
3565 I915_WRITE(reg, temp);
3566
3567 reg = FDI_RX_CTL(pipe);
3568 temp = I915_READ(reg);
3569 temp &= ~FDI_LINK_TRAIN_AUTO;
3570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3571 temp &= ~FDI_RX_ENABLE;
3572 I915_WRITE(reg, temp);
3573
3574 /* enable CPU FDI TX and PCH FDI RX */
3575 reg = FDI_TX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3578 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3579 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3580 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3581 temp |= snb_b_fdi_train_param[j/2];
3582 temp |= FDI_COMPOSITE_SYNC;
3583 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3584
3585 I915_WRITE(FDI_RX_MISC(pipe),
3586 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3587
3588 reg = FDI_RX_CTL(pipe);
3589 temp = I915_READ(reg);
3590 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3591 temp |= FDI_COMPOSITE_SYNC;
3592 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3593
3594 POSTING_READ(reg);
3595 udelay(1); /* should be 0.5us */
3596
3597 for (i = 0; i < 4; i++) {
3598 reg = FDI_RX_IIR(pipe);
3599 temp = I915_READ(reg);
3600 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3601
3602 if (temp & FDI_RX_BIT_LOCK ||
3603 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3604 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3605 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3606 i);
3607 break;
3608 }
3609 udelay(1); /* should be 0.5us */
3610 }
3611 if (i == 4) {
3612 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3613 continue;
3614 }
3615
3616 /* Train 2 */
3617 reg = FDI_TX_CTL(pipe);
3618 temp = I915_READ(reg);
3619 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3620 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3621 I915_WRITE(reg, temp);
3622
3623 reg = FDI_RX_CTL(pipe);
3624 temp = I915_READ(reg);
3625 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3626 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3627 I915_WRITE(reg, temp);
3628
3629 POSTING_READ(reg);
3630 udelay(2); /* should be 1.5us */
3631
3632 for (i = 0; i < 4; i++) {
3633 reg = FDI_RX_IIR(pipe);
3634 temp = I915_READ(reg);
3635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3636
3637 if (temp & FDI_RX_SYMBOL_LOCK ||
3638 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3639 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3640 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3641 i);
3642 goto train_done;
3643 }
3644 udelay(2); /* should be 1.5us */
3645 }
3646 if (i == 4)
3647 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3648 }
3649
3650 train_done:
3651 DRM_DEBUG_KMS("FDI train done.\n");
3652 }
3653
3654 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3655 {
3656 struct drm_device *dev = intel_crtc->base.dev;
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 int pipe = intel_crtc->pipe;
3659 i915_reg_t reg;
3660 u32 temp;
3661
3662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3663 reg = FDI_RX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3667 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3668 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3669
3670 POSTING_READ(reg);
3671 udelay(200);
3672
3673 /* Switch from Rawclk to PCDclk */
3674 temp = I915_READ(reg);
3675 I915_WRITE(reg, temp | FDI_PCDCLK);
3676
3677 POSTING_READ(reg);
3678 udelay(200);
3679
3680 /* Enable CPU FDI TX PLL, always on for Ironlake */
3681 reg = FDI_TX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3684 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3685
3686 POSTING_READ(reg);
3687 udelay(100);
3688 }
3689 }
3690
3691 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3692 {
3693 struct drm_device *dev = intel_crtc->base.dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 int pipe = intel_crtc->pipe;
3696 i915_reg_t reg;
3697 u32 temp;
3698
3699 /* Switch from PCDclk to Rawclk */
3700 reg = FDI_RX_CTL(pipe);
3701 temp = I915_READ(reg);
3702 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3703
3704 /* Disable CPU FDI TX PLL */
3705 reg = FDI_TX_CTL(pipe);
3706 temp = I915_READ(reg);
3707 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3708
3709 POSTING_READ(reg);
3710 udelay(100);
3711
3712 reg = FDI_RX_CTL(pipe);
3713 temp = I915_READ(reg);
3714 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3715
3716 /* Wait for the clocks to turn off. */
3717 POSTING_READ(reg);
3718 udelay(100);
3719 }
3720
3721 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3722 {
3723 struct drm_device *dev = crtc->dev;
3724 struct drm_i915_private *dev_priv = dev->dev_private;
3725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3726 int pipe = intel_crtc->pipe;
3727 i915_reg_t reg;
3728 u32 temp;
3729
3730 /* disable CPU FDI tx and PCH FDI rx */
3731 reg = FDI_TX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3734 POSTING_READ(reg);
3735
3736 reg = FDI_RX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 temp &= ~(0x7 << 16);
3739 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3740 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3741
3742 POSTING_READ(reg);
3743 udelay(100);
3744
3745 /* Ironlake workaround, disable clock pointer after downing FDI */
3746 if (HAS_PCH_IBX(dev))
3747 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3748
3749 /* still set train pattern 1 */
3750 reg = FDI_TX_CTL(pipe);
3751 temp = I915_READ(reg);
3752 temp &= ~FDI_LINK_TRAIN_NONE;
3753 temp |= FDI_LINK_TRAIN_PATTERN_1;
3754 I915_WRITE(reg, temp);
3755
3756 reg = FDI_RX_CTL(pipe);
3757 temp = I915_READ(reg);
3758 if (HAS_PCH_CPT(dev)) {
3759 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3760 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3761 } else {
3762 temp &= ~FDI_LINK_TRAIN_NONE;
3763 temp |= FDI_LINK_TRAIN_PATTERN_1;
3764 }
3765 /* BPC in FDI rx is consistent with that in PIPECONF */
3766 temp &= ~(0x07 << 16);
3767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3768 I915_WRITE(reg, temp);
3769
3770 POSTING_READ(reg);
3771 udelay(100);
3772 }
3773
3774 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3775 {
3776 struct intel_crtc *crtc;
3777
3778 /* Note that we don't need to be called with mode_config.lock here
3779 * as our list of CRTC objects is static for the lifetime of the
3780 * device and so cannot disappear as we iterate. Similarly, we can
3781 * happily treat the predicates as racy, atomic checks as userspace
3782 * cannot claim and pin a new fb without at least acquring the
3783 * struct_mutex and so serialising with us.
3784 */
3785 for_each_intel_crtc(dev, crtc) {
3786 if (atomic_read(&crtc->unpin_work_count) == 0)
3787 continue;
3788
3789 if (crtc->unpin_work)
3790 intel_wait_for_vblank(dev, crtc->pipe);
3791
3792 return true;
3793 }
3794
3795 return false;
3796 }
3797
3798 static void page_flip_completed(struct intel_crtc *intel_crtc)
3799 {
3800 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3801 struct intel_unpin_work *work = intel_crtc->unpin_work;
3802
3803 /* ensure that the unpin work is consistent wrt ->pending. */
3804 smp_rmb();
3805 intel_crtc->unpin_work = NULL;
3806
3807 if (work->event)
3808 drm_send_vblank_event(intel_crtc->base.dev,
3809 intel_crtc->pipe,
3810 work->event);
3811
3812 drm_crtc_vblank_put(&intel_crtc->base);
3813
3814 wake_up_all(&dev_priv->pending_flip_queue);
3815 queue_work(dev_priv->wq, &work->work);
3816
3817 trace_i915_flip_complete(intel_crtc->plane,
3818 work->pending_flip_obj);
3819 }
3820
3821 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3822 {
3823 struct drm_device *dev = crtc->dev;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 long ret;
3826
3827 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3828
3829 ret = wait_event_interruptible_timeout(
3830 dev_priv->pending_flip_queue,
3831 !intel_crtc_has_pending_flip(crtc),
3832 60*HZ);
3833
3834 if (ret < 0)
3835 return ret;
3836
3837 if (ret == 0) {
3838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3839
3840 spin_lock_irq(&dev->event_lock);
3841 if (intel_crtc->unpin_work) {
3842 WARN_ONCE(1, "Removing stuck page flip\n");
3843 page_flip_completed(intel_crtc);
3844 }
3845 spin_unlock_irq(&dev->event_lock);
3846 }
3847
3848 return 0;
3849 }
3850
3851 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3852 {
3853 u32 temp;
3854
3855 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3856
3857 mutex_lock(&dev_priv->sb_lock);
3858
3859 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3860 temp |= SBI_SSCCTL_DISABLE;
3861 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3862
3863 mutex_unlock(&dev_priv->sb_lock);
3864 }
3865
3866 /* Program iCLKIP clock to the desired frequency */
3867 static void lpt_program_iclkip(struct drm_crtc *crtc)
3868 {
3869 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3870 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3871 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3872 u32 temp;
3873
3874 lpt_disable_iclkip(dev_priv);
3875
3876 /* The iCLK virtual clock root frequency is in MHz,
3877 * but the adjusted_mode->crtc_clock in in KHz. To get the
3878 * divisors, it is necessary to divide one by another, so we
3879 * convert the virtual clock precision to KHz here for higher
3880 * precision.
3881 */
3882 for (auxdiv = 0; auxdiv < 2; auxdiv++) {
3883 u32 iclk_virtual_root_freq = 172800 * 1000;
3884 u32 iclk_pi_range = 64;
3885 u32 desired_divisor;
3886
3887 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3888 clock << auxdiv);
3889 divsel = (desired_divisor / iclk_pi_range) - 2;
3890 phaseinc = desired_divisor % iclk_pi_range;
3891
3892 /*
3893 * Near 20MHz is a corner case which is
3894 * out of range for the 7-bit divisor
3895 */
3896 if (divsel <= 0x7f)
3897 break;
3898 }
3899
3900 /* This should not happen with any sane values */
3901 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3902 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3903 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3904 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3905
3906 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3907 clock,
3908 auxdiv,
3909 divsel,
3910 phasedir,
3911 phaseinc);
3912
3913 mutex_lock(&dev_priv->sb_lock);
3914
3915 /* Program SSCDIVINTPHASE6 */
3916 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3917 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3918 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3919 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3920 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3921 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3922 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3923 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3924
3925 /* Program SSCAUXDIV */
3926 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3927 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3928 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3929 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3930
3931 /* Enable modulator and associated divider */
3932 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3933 temp &= ~SBI_SSCCTL_DISABLE;
3934 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3935
3936 mutex_unlock(&dev_priv->sb_lock);
3937
3938 /* Wait for initialization time */
3939 udelay(24);
3940
3941 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3942 }
3943
3944 int lpt_get_iclkip(struct drm_i915_private *dev_priv)
3945 {
3946 u32 divsel, phaseinc, auxdiv;
3947 u32 iclk_virtual_root_freq = 172800 * 1000;
3948 u32 iclk_pi_range = 64;
3949 u32 desired_divisor;
3950 u32 temp;
3951
3952 if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0)
3953 return 0;
3954
3955 mutex_lock(&dev_priv->sb_lock);
3956
3957 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3958 if (temp & SBI_SSCCTL_DISABLE) {
3959 mutex_unlock(&dev_priv->sb_lock);
3960 return 0;
3961 }
3962
3963 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3964 divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >>
3965 SBI_SSCDIVINTPHASE_DIVSEL_SHIFT;
3966 phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >>
3967 SBI_SSCDIVINTPHASE_INCVAL_SHIFT;
3968
3969 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3970 auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >>
3971 SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT;
3972
3973 mutex_unlock(&dev_priv->sb_lock);
3974
3975 desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc;
3976
3977 return DIV_ROUND_CLOSEST(iclk_virtual_root_freq,
3978 desired_divisor << auxdiv);
3979 }
3980
3981 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3982 enum pipe pch_transcoder)
3983 {
3984 struct drm_device *dev = crtc->base.dev;
3985 struct drm_i915_private *dev_priv = dev->dev_private;
3986 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3987
3988 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3989 I915_READ(HTOTAL(cpu_transcoder)));
3990 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3991 I915_READ(HBLANK(cpu_transcoder)));
3992 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3993 I915_READ(HSYNC(cpu_transcoder)));
3994
3995 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3996 I915_READ(VTOTAL(cpu_transcoder)));
3997 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3998 I915_READ(VBLANK(cpu_transcoder)));
3999 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4000 I915_READ(VSYNC(cpu_transcoder)));
4001 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4002 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4003 }
4004
4005 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4006 {
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 uint32_t temp;
4009
4010 temp = I915_READ(SOUTH_CHICKEN1);
4011 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4012 return;
4013
4014 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4015 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4016
4017 temp &= ~FDI_BC_BIFURCATION_SELECT;
4018 if (enable)
4019 temp |= FDI_BC_BIFURCATION_SELECT;
4020
4021 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4022 I915_WRITE(SOUTH_CHICKEN1, temp);
4023 POSTING_READ(SOUTH_CHICKEN1);
4024 }
4025
4026 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4027 {
4028 struct drm_device *dev = intel_crtc->base.dev;
4029
4030 switch (intel_crtc->pipe) {
4031 case PIPE_A:
4032 break;
4033 case PIPE_B:
4034 if (intel_crtc->config->fdi_lanes > 2)
4035 cpt_set_fdi_bc_bifurcation(dev, false);
4036 else
4037 cpt_set_fdi_bc_bifurcation(dev, true);
4038
4039 break;
4040 case PIPE_C:
4041 cpt_set_fdi_bc_bifurcation(dev, true);
4042
4043 break;
4044 default:
4045 BUG();
4046 }
4047 }
4048
4049 /* Return which DP Port should be selected for Transcoder DP control */
4050 static enum port
4051 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4052 {
4053 struct drm_device *dev = crtc->dev;
4054 struct intel_encoder *encoder;
4055
4056 for_each_encoder_on_crtc(dev, crtc, encoder) {
4057 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4058 encoder->type == INTEL_OUTPUT_EDP)
4059 return enc_to_dig_port(&encoder->base)->port;
4060 }
4061
4062 return -1;
4063 }
4064
4065 /*
4066 * Enable PCH resources required for PCH ports:
4067 * - PCH PLLs
4068 * - FDI training & RX/TX
4069 * - update transcoder timings
4070 * - DP transcoding bits
4071 * - transcoder
4072 */
4073 static void ironlake_pch_enable(struct drm_crtc *crtc)
4074 {
4075 struct drm_device *dev = crtc->dev;
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4078 int pipe = intel_crtc->pipe;
4079 u32 temp;
4080
4081 assert_pch_transcoder_disabled(dev_priv, pipe);
4082
4083 if (IS_IVYBRIDGE(dev))
4084 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4085
4086 /* Write the TU size bits before fdi link training, so that error
4087 * detection works. */
4088 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4089 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4090
4091 /*
4092 * Sometimes spurious CPU pipe underruns happen during FDI
4093 * training, at least with VGA+HDMI cloning. Suppress them.
4094 */
4095 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4096
4097 /* For PCH output, training FDI link */
4098 dev_priv->display.fdi_link_train(crtc);
4099
4100 /* We need to program the right clock selection before writing the pixel
4101 * mutliplier into the DPLL. */
4102 if (HAS_PCH_CPT(dev)) {
4103 u32 sel;
4104
4105 temp = I915_READ(PCH_DPLL_SEL);
4106 temp |= TRANS_DPLL_ENABLE(pipe);
4107 sel = TRANS_DPLLB_SEL(pipe);
4108 if (intel_crtc->config->shared_dpll ==
4109 intel_get_shared_dpll_by_id(dev_priv, DPLL_ID_PCH_PLL_B))
4110 temp |= sel;
4111 else
4112 temp &= ~sel;
4113 I915_WRITE(PCH_DPLL_SEL, temp);
4114 }
4115
4116 /* XXX: pch pll's can be enabled any time before we enable the PCH
4117 * transcoder, and we actually should do this to not upset any PCH
4118 * transcoder that already use the clock when we share it.
4119 *
4120 * Note that enable_shared_dpll tries to do the right thing, but
4121 * get_shared_dpll unconditionally resets the pll - we need that to have
4122 * the right LVDS enable sequence. */
4123 intel_enable_shared_dpll(intel_crtc);
4124
4125 /* set transcoder timing, panel must allow it */
4126 assert_panel_unlocked(dev_priv, pipe);
4127 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4128
4129 intel_fdi_normal_train(crtc);
4130
4131 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4132
4133 /* For PCH DP, enable TRANS_DP_CTL */
4134 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4135 const struct drm_display_mode *adjusted_mode =
4136 &intel_crtc->config->base.adjusted_mode;
4137 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4138 i915_reg_t reg = TRANS_DP_CTL(pipe);
4139 temp = I915_READ(reg);
4140 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4141 TRANS_DP_SYNC_MASK |
4142 TRANS_DP_BPC_MASK);
4143 temp |= TRANS_DP_OUTPUT_ENABLE;
4144 temp |= bpc << 9; /* same format but at 11:9 */
4145
4146 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4147 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4148 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4149 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4150
4151 switch (intel_trans_dp_port_sel(crtc)) {
4152 case PORT_B:
4153 temp |= TRANS_DP_PORT_SEL_B;
4154 break;
4155 case PORT_C:
4156 temp |= TRANS_DP_PORT_SEL_C;
4157 break;
4158 case PORT_D:
4159 temp |= TRANS_DP_PORT_SEL_D;
4160 break;
4161 default:
4162 BUG();
4163 }
4164
4165 I915_WRITE(reg, temp);
4166 }
4167
4168 ironlake_enable_pch_transcoder(dev_priv, pipe);
4169 }
4170
4171 static void lpt_pch_enable(struct drm_crtc *crtc)
4172 {
4173 struct drm_device *dev = crtc->dev;
4174 struct drm_i915_private *dev_priv = dev->dev_private;
4175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4177
4178 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4179
4180 lpt_program_iclkip(crtc);
4181
4182 /* Set transcoder timing. */
4183 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4184
4185 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4186 }
4187
4188 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4189 {
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 i915_reg_t dslreg = PIPEDSL(pipe);
4192 u32 temp;
4193
4194 temp = I915_READ(dslreg);
4195 udelay(500);
4196 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4197 if (wait_for(I915_READ(dslreg) != temp, 5))
4198 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4199 }
4200 }
4201
4202 static int
4203 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4204 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4205 int src_w, int src_h, int dst_w, int dst_h)
4206 {
4207 struct intel_crtc_scaler_state *scaler_state =
4208 &crtc_state->scaler_state;
4209 struct intel_crtc *intel_crtc =
4210 to_intel_crtc(crtc_state->base.crtc);
4211 int need_scaling;
4212
4213 need_scaling = intel_rotation_90_or_270(rotation) ?
4214 (src_h != dst_w || src_w != dst_h):
4215 (src_w != dst_w || src_h != dst_h);
4216
4217 /*
4218 * if plane is being disabled or scaler is no more required or force detach
4219 * - free scaler binded to this plane/crtc
4220 * - in order to do this, update crtc->scaler_usage
4221 *
4222 * Here scaler state in crtc_state is set free so that
4223 * scaler can be assigned to other user. Actual register
4224 * update to free the scaler is done in plane/panel-fit programming.
4225 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4226 */
4227 if (force_detach || !need_scaling) {
4228 if (*scaler_id >= 0) {
4229 scaler_state->scaler_users &= ~(1 << scaler_user);
4230 scaler_state->scalers[*scaler_id].in_use = 0;
4231
4232 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4233 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4234 intel_crtc->pipe, scaler_user, *scaler_id,
4235 scaler_state->scaler_users);
4236 *scaler_id = -1;
4237 }
4238 return 0;
4239 }
4240
4241 /* range checks */
4242 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4243 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4244
4245 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4246 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4247 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4248 "size is out of scaler range\n",
4249 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4250 return -EINVAL;
4251 }
4252
4253 /* mark this plane as a scaler user in crtc_state */
4254 scaler_state->scaler_users |= (1 << scaler_user);
4255 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4256 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4257 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4258 scaler_state->scaler_users);
4259
4260 return 0;
4261 }
4262
4263 /**
4264 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4265 *
4266 * @state: crtc's scaler state
4267 *
4268 * Return
4269 * 0 - scaler_usage updated successfully
4270 * error - requested scaling cannot be supported or other error condition
4271 */
4272 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4273 {
4274 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4275 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4276
4277 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4278 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4279
4280 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4281 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4282 state->pipe_src_w, state->pipe_src_h,
4283 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4284 }
4285
4286 /**
4287 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4288 *
4289 * @state: crtc's scaler state
4290 * @plane_state: atomic plane state to update
4291 *
4292 * Return
4293 * 0 - scaler_usage updated successfully
4294 * error - requested scaling cannot be supported or other error condition
4295 */
4296 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4297 struct intel_plane_state *plane_state)
4298 {
4299
4300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4301 struct intel_plane *intel_plane =
4302 to_intel_plane(plane_state->base.plane);
4303 struct drm_framebuffer *fb = plane_state->base.fb;
4304 int ret;
4305
4306 bool force_detach = !fb || !plane_state->visible;
4307
4308 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4309 intel_plane->base.base.id, intel_crtc->pipe,
4310 drm_plane_index(&intel_plane->base));
4311
4312 ret = skl_update_scaler(crtc_state, force_detach,
4313 drm_plane_index(&intel_plane->base),
4314 &plane_state->scaler_id,
4315 plane_state->base.rotation,
4316 drm_rect_width(&plane_state->src) >> 16,
4317 drm_rect_height(&plane_state->src) >> 16,
4318 drm_rect_width(&plane_state->dst),
4319 drm_rect_height(&plane_state->dst));
4320
4321 if (ret || plane_state->scaler_id < 0)
4322 return ret;
4323
4324 /* check colorkey */
4325 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4326 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4327 intel_plane->base.base.id);
4328 return -EINVAL;
4329 }
4330
4331 /* Check src format */
4332 switch (fb->pixel_format) {
4333 case DRM_FORMAT_RGB565:
4334 case DRM_FORMAT_XBGR8888:
4335 case DRM_FORMAT_XRGB8888:
4336 case DRM_FORMAT_ABGR8888:
4337 case DRM_FORMAT_ARGB8888:
4338 case DRM_FORMAT_XRGB2101010:
4339 case DRM_FORMAT_XBGR2101010:
4340 case DRM_FORMAT_YUYV:
4341 case DRM_FORMAT_YVYU:
4342 case DRM_FORMAT_UYVY:
4343 case DRM_FORMAT_VYUY:
4344 break;
4345 default:
4346 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4347 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4348 return -EINVAL;
4349 }
4350
4351 return 0;
4352 }
4353
4354 static void skylake_scaler_disable(struct intel_crtc *crtc)
4355 {
4356 int i;
4357
4358 for (i = 0; i < crtc->num_scalers; i++)
4359 skl_detach_scaler(crtc, i);
4360 }
4361
4362 static void skylake_pfit_enable(struct intel_crtc *crtc)
4363 {
4364 struct drm_device *dev = crtc->base.dev;
4365 struct drm_i915_private *dev_priv = dev->dev_private;
4366 int pipe = crtc->pipe;
4367 struct intel_crtc_scaler_state *scaler_state =
4368 &crtc->config->scaler_state;
4369
4370 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4371
4372 if (crtc->config->pch_pfit.enabled) {
4373 int id;
4374
4375 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4376 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4377 return;
4378 }
4379
4380 id = scaler_state->scaler_id;
4381 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4382 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4383 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4384 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4385
4386 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4387 }
4388 }
4389
4390 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4391 {
4392 struct drm_device *dev = crtc->base.dev;
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394 int pipe = crtc->pipe;
4395
4396 if (crtc->config->pch_pfit.enabled) {
4397 /* Force use of hard-coded filter coefficients
4398 * as some pre-programmed values are broken,
4399 * e.g. x201.
4400 */
4401 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4402 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4403 PF_PIPE_SEL_IVB(pipe));
4404 else
4405 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4406 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4407 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4408 }
4409 }
4410
4411 void hsw_enable_ips(struct intel_crtc *crtc)
4412 {
4413 struct drm_device *dev = crtc->base.dev;
4414 struct drm_i915_private *dev_priv = dev->dev_private;
4415
4416 if (!crtc->config->ips_enabled)
4417 return;
4418
4419 /*
4420 * We can only enable IPS after we enable a plane and wait for a vblank
4421 * This function is called from post_plane_update, which is run after
4422 * a vblank wait.
4423 */
4424
4425 assert_plane_enabled(dev_priv, crtc->plane);
4426 if (IS_BROADWELL(dev)) {
4427 mutex_lock(&dev_priv->rps.hw_lock);
4428 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4429 mutex_unlock(&dev_priv->rps.hw_lock);
4430 /* Quoting Art Runyan: "its not safe to expect any particular
4431 * value in IPS_CTL bit 31 after enabling IPS through the
4432 * mailbox." Moreover, the mailbox may return a bogus state,
4433 * so we need to just enable it and continue on.
4434 */
4435 } else {
4436 I915_WRITE(IPS_CTL, IPS_ENABLE);
4437 /* The bit only becomes 1 in the next vblank, so this wait here
4438 * is essentially intel_wait_for_vblank. If we don't have this
4439 * and don't wait for vblanks until the end of crtc_enable, then
4440 * the HW state readout code will complain that the expected
4441 * IPS_CTL value is not the one we read. */
4442 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4443 DRM_ERROR("Timed out waiting for IPS enable\n");
4444 }
4445 }
4446
4447 void hsw_disable_ips(struct intel_crtc *crtc)
4448 {
4449 struct drm_device *dev = crtc->base.dev;
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451
4452 if (!crtc->config->ips_enabled)
4453 return;
4454
4455 assert_plane_enabled(dev_priv, crtc->plane);
4456 if (IS_BROADWELL(dev)) {
4457 mutex_lock(&dev_priv->rps.hw_lock);
4458 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4459 mutex_unlock(&dev_priv->rps.hw_lock);
4460 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4461 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4462 DRM_ERROR("Timed out waiting for IPS disable\n");
4463 } else {
4464 I915_WRITE(IPS_CTL, 0);
4465 POSTING_READ(IPS_CTL);
4466 }
4467
4468 /* We need to wait for a vblank before we can disable the plane. */
4469 intel_wait_for_vblank(dev, crtc->pipe);
4470 }
4471
4472 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4473 {
4474 if (intel_crtc->overlay) {
4475 struct drm_device *dev = intel_crtc->base.dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477
4478 mutex_lock(&dev->struct_mutex);
4479 dev_priv->mm.interruptible = false;
4480 (void) intel_overlay_switch_off(intel_crtc->overlay);
4481 dev_priv->mm.interruptible = true;
4482 mutex_unlock(&dev->struct_mutex);
4483 }
4484
4485 /* Let userspace switch the overlay on again. In most cases userspace
4486 * has to recompute where to put it anyway.
4487 */
4488 }
4489
4490 /**
4491 * intel_post_enable_primary - Perform operations after enabling primary plane
4492 * @crtc: the CRTC whose primary plane was just enabled
4493 *
4494 * Performs potentially sleeping operations that must be done after the primary
4495 * plane is enabled, such as updating FBC and IPS. Note that this may be
4496 * called due to an explicit primary plane update, or due to an implicit
4497 * re-enable that is caused when a sprite plane is updated to no longer
4498 * completely hide the primary plane.
4499 */
4500 static void
4501 intel_post_enable_primary(struct drm_crtc *crtc)
4502 {
4503 struct drm_device *dev = crtc->dev;
4504 struct drm_i915_private *dev_priv = dev->dev_private;
4505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4506 int pipe = intel_crtc->pipe;
4507
4508 /*
4509 * FIXME IPS should be fine as long as one plane is
4510 * enabled, but in practice it seems to have problems
4511 * when going from primary only to sprite only and vice
4512 * versa.
4513 */
4514 hsw_enable_ips(intel_crtc);
4515
4516 /*
4517 * Gen2 reports pipe underruns whenever all planes are disabled.
4518 * So don't enable underrun reporting before at least some planes
4519 * are enabled.
4520 * FIXME: Need to fix the logic to work when we turn off all planes
4521 * but leave the pipe running.
4522 */
4523 if (IS_GEN2(dev))
4524 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4525
4526 /* Underruns don't always raise interrupts, so check manually. */
4527 intel_check_cpu_fifo_underruns(dev_priv);
4528 intel_check_pch_fifo_underruns(dev_priv);
4529 }
4530
4531 /* FIXME move all this to pre_plane_update() with proper state tracking */
4532 static void
4533 intel_pre_disable_primary(struct drm_crtc *crtc)
4534 {
4535 struct drm_device *dev = crtc->dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538 int pipe = intel_crtc->pipe;
4539
4540 /*
4541 * Gen2 reports pipe underruns whenever all planes are disabled.
4542 * So diasble underrun reporting before all the planes get disabled.
4543 * FIXME: Need to fix the logic to work when we turn off all planes
4544 * but leave the pipe running.
4545 */
4546 if (IS_GEN2(dev))
4547 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4548
4549 /*
4550 * FIXME IPS should be fine as long as one plane is
4551 * enabled, but in practice it seems to have problems
4552 * when going from primary only to sprite only and vice
4553 * versa.
4554 */
4555 hsw_disable_ips(intel_crtc);
4556 }
4557
4558 /* FIXME get rid of this and use pre_plane_update */
4559 static void
4560 intel_pre_disable_primary_noatomic(struct drm_crtc *crtc)
4561 {
4562 struct drm_device *dev = crtc->dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565 int pipe = intel_crtc->pipe;
4566
4567 intel_pre_disable_primary(crtc);
4568
4569 /*
4570 * Vblank time updates from the shadow to live plane control register
4571 * are blocked if the memory self-refresh mode is active at that
4572 * moment. So to make sure the plane gets truly disabled, disable
4573 * first the self-refresh mode. The self-refresh enable bit in turn
4574 * will be checked/applied by the HW only at the next frame start
4575 * event which is after the vblank start event, so we need to have a
4576 * wait-for-vblank between disabling the plane and the pipe.
4577 */
4578 if (HAS_GMCH_DISPLAY(dev)) {
4579 intel_set_memory_cxsr(dev_priv, false);
4580 dev_priv->wm.vlv.cxsr = false;
4581 intel_wait_for_vblank(dev, pipe);
4582 }
4583 }
4584
4585 static void intel_post_plane_update(struct intel_crtc_state *old_crtc_state)
4586 {
4587 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4588 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4589 struct intel_crtc_state *pipe_config =
4590 to_intel_crtc_state(crtc->base.state);
4591 struct drm_device *dev = crtc->base.dev;
4592 struct drm_plane *primary = crtc->base.primary;
4593 struct drm_plane_state *old_pri_state =
4594 drm_atomic_get_existing_plane_state(old_state, primary);
4595
4596 intel_frontbuffer_flip(dev, pipe_config->fb_bits);
4597
4598 crtc->wm.cxsr_allowed = true;
4599
4600 if (pipe_config->update_wm_post && pipe_config->base.active)
4601 intel_update_watermarks(&crtc->base);
4602
4603 if (old_pri_state) {
4604 struct intel_plane_state *primary_state =
4605 to_intel_plane_state(primary->state);
4606 struct intel_plane_state *old_primary_state =
4607 to_intel_plane_state(old_pri_state);
4608
4609 intel_fbc_post_update(crtc);
4610
4611 if (primary_state->visible &&
4612 (needs_modeset(&pipe_config->base) ||
4613 !old_primary_state->visible))
4614 intel_post_enable_primary(&crtc->base);
4615 }
4616 }
4617
4618 static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state)
4619 {
4620 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
4621 struct drm_device *dev = crtc->base.dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 struct intel_crtc_state *pipe_config =
4624 to_intel_crtc_state(crtc->base.state);
4625 struct drm_atomic_state *old_state = old_crtc_state->base.state;
4626 struct drm_plane *primary = crtc->base.primary;
4627 struct drm_plane_state *old_pri_state =
4628 drm_atomic_get_existing_plane_state(old_state, primary);
4629 bool modeset = needs_modeset(&pipe_config->base);
4630
4631 if (old_pri_state) {
4632 struct intel_plane_state *primary_state =
4633 to_intel_plane_state(primary->state);
4634 struct intel_plane_state *old_primary_state =
4635 to_intel_plane_state(old_pri_state);
4636
4637 intel_fbc_pre_update(crtc);
4638
4639 if (old_primary_state->visible &&
4640 (modeset || !primary_state->visible))
4641 intel_pre_disable_primary(&crtc->base);
4642 }
4643
4644 if (pipe_config->disable_cxsr) {
4645 crtc->wm.cxsr_allowed = false;
4646
4647 /*
4648 * Vblank time updates from the shadow to live plane control register
4649 * are blocked if the memory self-refresh mode is active at that
4650 * moment. So to make sure the plane gets truly disabled, disable
4651 * first the self-refresh mode. The self-refresh enable bit in turn
4652 * will be checked/applied by the HW only at the next frame start
4653 * event which is after the vblank start event, so we need to have a
4654 * wait-for-vblank between disabling the plane and the pipe.
4655 */
4656 if (old_crtc_state->base.active) {
4657 intel_set_memory_cxsr(dev_priv, false);
4658 dev_priv->wm.vlv.cxsr = false;
4659 intel_wait_for_vblank(dev, crtc->pipe);
4660 }
4661 }
4662
4663 /*
4664 * IVB workaround: must disable low power watermarks for at least
4665 * one frame before enabling scaling. LP watermarks can be re-enabled
4666 * when scaling is disabled.
4667 *
4668 * WaCxSRDisabledForSpriteScaling:ivb
4669 */
4670 if (pipe_config->disable_lp_wm) {
4671 ilk_disable_lp_wm(dev);
4672 intel_wait_for_vblank(dev, crtc->pipe);
4673 }
4674
4675 /*
4676 * If we're doing a modeset, we're done. No need to do any pre-vblank
4677 * watermark programming here.
4678 */
4679 if (needs_modeset(&pipe_config->base))
4680 return;
4681
4682 /*
4683 * For platforms that support atomic watermarks, program the
4684 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4685 * will be the intermediate values that are safe for both pre- and
4686 * post- vblank; when vblank happens, the 'active' values will be set
4687 * to the final 'target' values and we'll do this again to get the
4688 * optimal watermarks. For gen9+ platforms, the values we program here
4689 * will be the final target values which will get automatically latched
4690 * at vblank time; no further programming will be necessary.
4691 *
4692 * If a platform hasn't been transitioned to atomic watermarks yet,
4693 * we'll continue to update watermarks the old way, if flags tell
4694 * us to.
4695 */
4696 if (dev_priv->display.initial_watermarks != NULL)
4697 dev_priv->display.initial_watermarks(pipe_config);
4698 else if (pipe_config->update_wm_pre)
4699 intel_update_watermarks(&crtc->base);
4700 }
4701
4702 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4703 {
4704 struct drm_device *dev = crtc->dev;
4705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4706 struct drm_plane *p;
4707 int pipe = intel_crtc->pipe;
4708
4709 intel_crtc_dpms_overlay_disable(intel_crtc);
4710
4711 drm_for_each_plane_mask(p, dev, plane_mask)
4712 to_intel_plane(p)->disable_plane(p, crtc);
4713
4714 /*
4715 * FIXME: Once we grow proper nuclear flip support out of this we need
4716 * to compute the mask of flip planes precisely. For the time being
4717 * consider this a flip to a NULL plane.
4718 */
4719 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4720 }
4721
4722 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4723 {
4724 struct drm_device *dev = crtc->dev;
4725 struct drm_i915_private *dev_priv = dev->dev_private;
4726 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4727 struct intel_encoder *encoder;
4728 int pipe = intel_crtc->pipe;
4729 struct intel_crtc_state *pipe_config =
4730 to_intel_crtc_state(crtc->state);
4731
4732 if (WARN_ON(intel_crtc->active))
4733 return;
4734
4735 if (intel_crtc->config->has_pch_encoder)
4736 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4737
4738 if (intel_crtc->config->has_pch_encoder)
4739 intel_prepare_shared_dpll(intel_crtc);
4740
4741 if (intel_crtc->config->has_dp_encoder)
4742 intel_dp_set_m_n(intel_crtc, M1_N1);
4743
4744 intel_set_pipe_timings(intel_crtc);
4745 intel_set_pipe_src_size(intel_crtc);
4746
4747 if (intel_crtc->config->has_pch_encoder) {
4748 intel_cpu_transcoder_set_m_n(intel_crtc,
4749 &intel_crtc->config->fdi_m_n, NULL);
4750 }
4751
4752 ironlake_set_pipeconf(crtc);
4753
4754 intel_crtc->active = true;
4755
4756 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4757
4758 for_each_encoder_on_crtc(dev, crtc, encoder)
4759 if (encoder->pre_enable)
4760 encoder->pre_enable(encoder);
4761
4762 if (intel_crtc->config->has_pch_encoder) {
4763 /* Note: FDI PLL enabling _must_ be done before we enable the
4764 * cpu pipes, hence this is separate from all the other fdi/pch
4765 * enabling. */
4766 ironlake_fdi_pll_enable(intel_crtc);
4767 } else {
4768 assert_fdi_tx_disabled(dev_priv, pipe);
4769 assert_fdi_rx_disabled(dev_priv, pipe);
4770 }
4771
4772 ironlake_pfit_enable(intel_crtc);
4773
4774 /*
4775 * On ILK+ LUT must be loaded before the pipe is running but with
4776 * clocks enabled
4777 */
4778 intel_color_load_luts(&pipe_config->base);
4779
4780 if (dev_priv->display.initial_watermarks != NULL)
4781 dev_priv->display.initial_watermarks(intel_crtc->config);
4782 intel_enable_pipe(intel_crtc);
4783
4784 if (intel_crtc->config->has_pch_encoder)
4785 ironlake_pch_enable(crtc);
4786
4787 assert_vblank_disabled(crtc);
4788 drm_crtc_vblank_on(crtc);
4789
4790 for_each_encoder_on_crtc(dev, crtc, encoder)
4791 encoder->enable(encoder);
4792
4793 if (HAS_PCH_CPT(dev))
4794 cpt_verify_modeset(dev, intel_crtc->pipe);
4795
4796 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4797 if (intel_crtc->config->has_pch_encoder)
4798 intel_wait_for_vblank(dev, pipe);
4799 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4800 }
4801
4802 /* IPS only exists on ULT machines and is tied to pipe A. */
4803 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4804 {
4805 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4806 }
4807
4808 static void haswell_crtc_enable(struct drm_crtc *crtc)
4809 {
4810 struct drm_device *dev = crtc->dev;
4811 struct drm_i915_private *dev_priv = dev->dev_private;
4812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4813 struct intel_encoder *encoder;
4814 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4815 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4816 struct intel_crtc_state *pipe_config =
4817 to_intel_crtc_state(crtc->state);
4818
4819 if (WARN_ON(intel_crtc->active))
4820 return;
4821
4822 if (intel_crtc->config->has_pch_encoder)
4823 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4824 false);
4825
4826 if (intel_crtc->config->shared_dpll)
4827 intel_enable_shared_dpll(intel_crtc);
4828
4829 if (intel_crtc->config->has_dp_encoder)
4830 intel_dp_set_m_n(intel_crtc, M1_N1);
4831
4832 if (!intel_crtc->config->has_dsi_encoder)
4833 intel_set_pipe_timings(intel_crtc);
4834
4835 intel_set_pipe_src_size(intel_crtc);
4836
4837 if (cpu_transcoder != TRANSCODER_EDP &&
4838 !transcoder_is_dsi(cpu_transcoder)) {
4839 I915_WRITE(PIPE_MULT(cpu_transcoder),
4840 intel_crtc->config->pixel_multiplier - 1);
4841 }
4842
4843 if (intel_crtc->config->has_pch_encoder) {
4844 intel_cpu_transcoder_set_m_n(intel_crtc,
4845 &intel_crtc->config->fdi_m_n, NULL);
4846 }
4847
4848 if (!intel_crtc->config->has_dsi_encoder)
4849 haswell_set_pipeconf(crtc);
4850
4851 haswell_set_pipemisc(crtc);
4852
4853 intel_color_set_csc(&pipe_config->base);
4854
4855 intel_crtc->active = true;
4856
4857 if (intel_crtc->config->has_pch_encoder)
4858 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4859 else
4860 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4861
4862 for_each_encoder_on_crtc(dev, crtc, encoder) {
4863 if (encoder->pre_enable)
4864 encoder->pre_enable(encoder);
4865 }
4866
4867 if (intel_crtc->config->has_pch_encoder)
4868 dev_priv->display.fdi_link_train(crtc);
4869
4870 if (!intel_crtc->config->has_dsi_encoder)
4871 intel_ddi_enable_pipe_clock(intel_crtc);
4872
4873 if (INTEL_INFO(dev)->gen >= 9)
4874 skylake_pfit_enable(intel_crtc);
4875 else
4876 ironlake_pfit_enable(intel_crtc);
4877
4878 /*
4879 * On ILK+ LUT must be loaded before the pipe is running but with
4880 * clocks enabled
4881 */
4882 intel_color_load_luts(&pipe_config->base);
4883
4884 intel_ddi_set_pipe_settings(crtc);
4885 if (!intel_crtc->config->has_dsi_encoder)
4886 intel_ddi_enable_transcoder_func(crtc);
4887
4888 if (dev_priv->display.initial_watermarks != NULL)
4889 dev_priv->display.initial_watermarks(pipe_config);
4890 else
4891 intel_update_watermarks(crtc);
4892
4893 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
4894 if (!intel_crtc->config->has_dsi_encoder)
4895 intel_enable_pipe(intel_crtc);
4896
4897 if (intel_crtc->config->has_pch_encoder)
4898 lpt_pch_enable(crtc);
4899
4900 if (intel_crtc->config->dp_encoder_is_mst)
4901 intel_ddi_set_vc_payload_alloc(crtc, true);
4902
4903 assert_vblank_disabled(crtc);
4904 drm_crtc_vblank_on(crtc);
4905
4906 for_each_encoder_on_crtc(dev, crtc, encoder) {
4907 encoder->enable(encoder);
4908 intel_opregion_notify_encoder(encoder, true);
4909 }
4910
4911 if (intel_crtc->config->has_pch_encoder) {
4912 intel_wait_for_vblank(dev, pipe);
4913 intel_wait_for_vblank(dev, pipe);
4914 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4915 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4916 true);
4917 }
4918
4919 /* If we change the relative order between pipe/planes enabling, we need
4920 * to change the workaround. */
4921 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4922 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4923 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4924 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4925 }
4926 }
4927
4928 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
4929 {
4930 struct drm_device *dev = crtc->base.dev;
4931 struct drm_i915_private *dev_priv = dev->dev_private;
4932 int pipe = crtc->pipe;
4933
4934 /* To avoid upsetting the power well on haswell only disable the pfit if
4935 * it's in use. The hw state code will make sure we get this right. */
4936 if (force || crtc->config->pch_pfit.enabled) {
4937 I915_WRITE(PF_CTL(pipe), 0);
4938 I915_WRITE(PF_WIN_POS(pipe), 0);
4939 I915_WRITE(PF_WIN_SZ(pipe), 0);
4940 }
4941 }
4942
4943 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4944 {
4945 struct drm_device *dev = crtc->dev;
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4948 struct intel_encoder *encoder;
4949 int pipe = intel_crtc->pipe;
4950
4951 if (intel_crtc->config->has_pch_encoder)
4952 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4953
4954 for_each_encoder_on_crtc(dev, crtc, encoder)
4955 encoder->disable(encoder);
4956
4957 drm_crtc_vblank_off(crtc);
4958 assert_vblank_disabled(crtc);
4959
4960 /*
4961 * Sometimes spurious CPU pipe underruns happen when the
4962 * pipe is already disabled, but FDI RX/TX is still enabled.
4963 * Happens at least with VGA+HDMI cloning. Suppress them.
4964 */
4965 if (intel_crtc->config->has_pch_encoder)
4966 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4967
4968 intel_disable_pipe(intel_crtc);
4969
4970 ironlake_pfit_disable(intel_crtc, false);
4971
4972 if (intel_crtc->config->has_pch_encoder) {
4973 ironlake_fdi_disable(crtc);
4974 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4975 }
4976
4977 for_each_encoder_on_crtc(dev, crtc, encoder)
4978 if (encoder->post_disable)
4979 encoder->post_disable(encoder);
4980
4981 if (intel_crtc->config->has_pch_encoder) {
4982 ironlake_disable_pch_transcoder(dev_priv, pipe);
4983
4984 if (HAS_PCH_CPT(dev)) {
4985 i915_reg_t reg;
4986 u32 temp;
4987
4988 /* disable TRANS_DP_CTL */
4989 reg = TRANS_DP_CTL(pipe);
4990 temp = I915_READ(reg);
4991 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4992 TRANS_DP_PORT_SEL_MASK);
4993 temp |= TRANS_DP_PORT_SEL_NONE;
4994 I915_WRITE(reg, temp);
4995
4996 /* disable DPLL_SEL */
4997 temp = I915_READ(PCH_DPLL_SEL);
4998 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4999 I915_WRITE(PCH_DPLL_SEL, temp);
5000 }
5001
5002 ironlake_fdi_pll_disable(intel_crtc);
5003 }
5004
5005 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5006 }
5007
5008 static void haswell_crtc_disable(struct drm_crtc *crtc)
5009 {
5010 struct drm_device *dev = crtc->dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5013 struct intel_encoder *encoder;
5014 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5015
5016 if (intel_crtc->config->has_pch_encoder)
5017 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5018 false);
5019
5020 for_each_encoder_on_crtc(dev, crtc, encoder) {
5021 intel_opregion_notify_encoder(encoder, false);
5022 encoder->disable(encoder);
5023 }
5024
5025 drm_crtc_vblank_off(crtc);
5026 assert_vblank_disabled(crtc);
5027
5028 /* XXX: Do the pipe assertions at the right place for BXT DSI. */
5029 if (!intel_crtc->config->has_dsi_encoder)
5030 intel_disable_pipe(intel_crtc);
5031
5032 if (intel_crtc->config->dp_encoder_is_mst)
5033 intel_ddi_set_vc_payload_alloc(crtc, false);
5034
5035 if (!intel_crtc->config->has_dsi_encoder)
5036 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5037
5038 if (INTEL_INFO(dev)->gen >= 9)
5039 skylake_scaler_disable(intel_crtc);
5040 else
5041 ironlake_pfit_disable(intel_crtc, false);
5042
5043 if (!intel_crtc->config->has_dsi_encoder)
5044 intel_ddi_disable_pipe_clock(intel_crtc);
5045
5046 for_each_encoder_on_crtc(dev, crtc, encoder)
5047 if (encoder->post_disable)
5048 encoder->post_disable(encoder);
5049
5050 if (intel_crtc->config->has_pch_encoder) {
5051 lpt_disable_pch_transcoder(dev_priv);
5052 lpt_disable_iclkip(dev_priv);
5053 intel_ddi_fdi_disable(crtc);
5054
5055 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5056 true);
5057 }
5058 }
5059
5060 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5061 {
5062 struct drm_device *dev = crtc->base.dev;
5063 struct drm_i915_private *dev_priv = dev->dev_private;
5064 struct intel_crtc_state *pipe_config = crtc->config;
5065
5066 if (!pipe_config->gmch_pfit.control)
5067 return;
5068
5069 /*
5070 * The panel fitter should only be adjusted whilst the pipe is disabled,
5071 * according to register description and PRM.
5072 */
5073 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5074 assert_pipe_disabled(dev_priv, crtc->pipe);
5075
5076 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5077 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5078
5079 /* Border color in case we don't scale up to the full screen. Black by
5080 * default, change to something else for debugging. */
5081 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5082 }
5083
5084 static enum intel_display_power_domain port_to_power_domain(enum port port)
5085 {
5086 switch (port) {
5087 case PORT_A:
5088 return POWER_DOMAIN_PORT_DDI_A_LANES;
5089 case PORT_B:
5090 return POWER_DOMAIN_PORT_DDI_B_LANES;
5091 case PORT_C:
5092 return POWER_DOMAIN_PORT_DDI_C_LANES;
5093 case PORT_D:
5094 return POWER_DOMAIN_PORT_DDI_D_LANES;
5095 case PORT_E:
5096 return POWER_DOMAIN_PORT_DDI_E_LANES;
5097 default:
5098 MISSING_CASE(port);
5099 return POWER_DOMAIN_PORT_OTHER;
5100 }
5101 }
5102
5103 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5104 {
5105 switch (port) {
5106 case PORT_A:
5107 return POWER_DOMAIN_AUX_A;
5108 case PORT_B:
5109 return POWER_DOMAIN_AUX_B;
5110 case PORT_C:
5111 return POWER_DOMAIN_AUX_C;
5112 case PORT_D:
5113 return POWER_DOMAIN_AUX_D;
5114 case PORT_E:
5115 /* FIXME: Check VBT for actual wiring of PORT E */
5116 return POWER_DOMAIN_AUX_D;
5117 default:
5118 MISSING_CASE(port);
5119 return POWER_DOMAIN_AUX_A;
5120 }
5121 }
5122
5123 enum intel_display_power_domain
5124 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5125 {
5126 struct drm_device *dev = intel_encoder->base.dev;
5127 struct intel_digital_port *intel_dig_port;
5128
5129 switch (intel_encoder->type) {
5130 case INTEL_OUTPUT_UNKNOWN:
5131 /* Only DDI platforms should ever use this output type */
5132 WARN_ON_ONCE(!HAS_DDI(dev));
5133 case INTEL_OUTPUT_DISPLAYPORT:
5134 case INTEL_OUTPUT_HDMI:
5135 case INTEL_OUTPUT_EDP:
5136 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5137 return port_to_power_domain(intel_dig_port->port);
5138 case INTEL_OUTPUT_DP_MST:
5139 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5140 return port_to_power_domain(intel_dig_port->port);
5141 case INTEL_OUTPUT_ANALOG:
5142 return POWER_DOMAIN_PORT_CRT;
5143 case INTEL_OUTPUT_DSI:
5144 return POWER_DOMAIN_PORT_DSI;
5145 default:
5146 return POWER_DOMAIN_PORT_OTHER;
5147 }
5148 }
5149
5150 enum intel_display_power_domain
5151 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5152 {
5153 struct drm_device *dev = intel_encoder->base.dev;
5154 struct intel_digital_port *intel_dig_port;
5155
5156 switch (intel_encoder->type) {
5157 case INTEL_OUTPUT_UNKNOWN:
5158 case INTEL_OUTPUT_HDMI:
5159 /*
5160 * Only DDI platforms should ever use these output types.
5161 * We can get here after the HDMI detect code has already set
5162 * the type of the shared encoder. Since we can't be sure
5163 * what's the status of the given connectors, play safe and
5164 * run the DP detection too.
5165 */
5166 WARN_ON_ONCE(!HAS_DDI(dev));
5167 case INTEL_OUTPUT_DISPLAYPORT:
5168 case INTEL_OUTPUT_EDP:
5169 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5170 return port_to_aux_power_domain(intel_dig_port->port);
5171 case INTEL_OUTPUT_DP_MST:
5172 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5173 return port_to_aux_power_domain(intel_dig_port->port);
5174 default:
5175 MISSING_CASE(intel_encoder->type);
5176 return POWER_DOMAIN_AUX_A;
5177 }
5178 }
5179
5180 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc,
5181 struct intel_crtc_state *crtc_state)
5182 {
5183 struct drm_device *dev = crtc->dev;
5184 struct drm_encoder *encoder;
5185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5186 enum pipe pipe = intel_crtc->pipe;
5187 unsigned long mask;
5188 enum transcoder transcoder = crtc_state->cpu_transcoder;
5189
5190 if (!crtc_state->base.active)
5191 return 0;
5192
5193 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5194 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5195 if (crtc_state->pch_pfit.enabled ||
5196 crtc_state->pch_pfit.force_thru)
5197 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5198
5199 drm_for_each_encoder_mask(encoder, dev, crtc_state->base.encoder_mask) {
5200 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5201
5202 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5203 }
5204
5205 if (crtc_state->shared_dpll)
5206 mask |= BIT(POWER_DOMAIN_PLLS);
5207
5208 return mask;
5209 }
5210
5211 static unsigned long
5212 modeset_get_crtc_power_domains(struct drm_crtc *crtc,
5213 struct intel_crtc_state *crtc_state)
5214 {
5215 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5217 enum intel_display_power_domain domain;
5218 unsigned long domains, new_domains, old_domains;
5219
5220 old_domains = intel_crtc->enabled_power_domains;
5221 intel_crtc->enabled_power_domains = new_domains =
5222 get_crtc_power_domains(crtc, crtc_state);
5223
5224 domains = new_domains & ~old_domains;
5225
5226 for_each_power_domain(domain, domains)
5227 intel_display_power_get(dev_priv, domain);
5228
5229 return old_domains & ~new_domains;
5230 }
5231
5232 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5233 unsigned long domains)
5234 {
5235 enum intel_display_power_domain domain;
5236
5237 for_each_power_domain(domain, domains)
5238 intel_display_power_put(dev_priv, domain);
5239 }
5240
5241 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5242 {
5243 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5244
5245 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5246 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5247 return max_cdclk_freq;
5248 else if (IS_CHERRYVIEW(dev_priv))
5249 return max_cdclk_freq*95/100;
5250 else if (INTEL_INFO(dev_priv)->gen < 4)
5251 return 2*max_cdclk_freq*90/100;
5252 else
5253 return max_cdclk_freq*90/100;
5254 }
5255
5256 static void intel_update_max_cdclk(struct drm_device *dev)
5257 {
5258 struct drm_i915_private *dev_priv = dev->dev_private;
5259
5260 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5261 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5262
5263 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5264 dev_priv->max_cdclk_freq = 675000;
5265 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5266 dev_priv->max_cdclk_freq = 540000;
5267 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5268 dev_priv->max_cdclk_freq = 450000;
5269 else
5270 dev_priv->max_cdclk_freq = 337500;
5271 } else if (IS_BROADWELL(dev)) {
5272 /*
5273 * FIXME with extra cooling we can allow
5274 * 540 MHz for ULX and 675 Mhz for ULT.
5275 * How can we know if extra cooling is
5276 * available? PCI ID, VTB, something else?
5277 */
5278 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5279 dev_priv->max_cdclk_freq = 450000;
5280 else if (IS_BDW_ULX(dev))
5281 dev_priv->max_cdclk_freq = 450000;
5282 else if (IS_BDW_ULT(dev))
5283 dev_priv->max_cdclk_freq = 540000;
5284 else
5285 dev_priv->max_cdclk_freq = 675000;
5286 } else if (IS_CHERRYVIEW(dev)) {
5287 dev_priv->max_cdclk_freq = 320000;
5288 } else if (IS_VALLEYVIEW(dev)) {
5289 dev_priv->max_cdclk_freq = 400000;
5290 } else {
5291 /* otherwise assume cdclk is fixed */
5292 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5293 }
5294
5295 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5296
5297 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5298 dev_priv->max_cdclk_freq);
5299
5300 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5301 dev_priv->max_dotclk_freq);
5302 }
5303
5304 static void intel_update_cdclk(struct drm_device *dev)
5305 {
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307
5308 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5309 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5310 dev_priv->cdclk_freq);
5311
5312 /*
5313 * Program the gmbus_freq based on the cdclk frequency.
5314 * BSpec erroneously claims we should aim for 4MHz, but
5315 * in fact 1MHz is the correct frequency.
5316 */
5317 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5318 /*
5319 * Program the gmbus_freq based on the cdclk frequency.
5320 * BSpec erroneously claims we should aim for 4MHz, but
5321 * in fact 1MHz is the correct frequency.
5322 */
5323 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5324 }
5325
5326 if (dev_priv->max_cdclk_freq == 0)
5327 intel_update_max_cdclk(dev);
5328 }
5329
5330 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5331 {
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 uint32_t divider;
5334 uint32_t ratio;
5335 uint32_t current_freq;
5336 int ret;
5337
5338 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5339 switch (frequency) {
5340 case 144000:
5341 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5342 ratio = BXT_DE_PLL_RATIO(60);
5343 break;
5344 case 288000:
5345 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5346 ratio = BXT_DE_PLL_RATIO(60);
5347 break;
5348 case 384000:
5349 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5350 ratio = BXT_DE_PLL_RATIO(60);
5351 break;
5352 case 576000:
5353 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5354 ratio = BXT_DE_PLL_RATIO(60);
5355 break;
5356 case 624000:
5357 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5358 ratio = BXT_DE_PLL_RATIO(65);
5359 break;
5360 case 19200:
5361 /*
5362 * Bypass frequency with DE PLL disabled. Init ratio, divider
5363 * to suppress GCC warning.
5364 */
5365 ratio = 0;
5366 divider = 0;
5367 break;
5368 default:
5369 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5370
5371 return;
5372 }
5373
5374 mutex_lock(&dev_priv->rps.hw_lock);
5375 /* Inform power controller of upcoming frequency change */
5376 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5377 0x80000000);
5378 mutex_unlock(&dev_priv->rps.hw_lock);
5379
5380 if (ret) {
5381 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5382 ret, frequency);
5383 return;
5384 }
5385
5386 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5387 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5388 current_freq = current_freq * 500 + 1000;
5389
5390 /*
5391 * DE PLL has to be disabled when
5392 * - setting to 19.2MHz (bypass, PLL isn't used)
5393 * - before setting to 624MHz (PLL needs toggling)
5394 * - before setting to any frequency from 624MHz (PLL needs toggling)
5395 */
5396 if (frequency == 19200 || frequency == 624000 ||
5397 current_freq == 624000) {
5398 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5399 /* Timeout 200us */
5400 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5401 1))
5402 DRM_ERROR("timout waiting for DE PLL unlock\n");
5403 }
5404
5405 if (frequency != 19200) {
5406 uint32_t val;
5407
5408 val = I915_READ(BXT_DE_PLL_CTL);
5409 val &= ~BXT_DE_PLL_RATIO_MASK;
5410 val |= ratio;
5411 I915_WRITE(BXT_DE_PLL_CTL, val);
5412
5413 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5414 /* Timeout 200us */
5415 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5416 DRM_ERROR("timeout waiting for DE PLL lock\n");
5417
5418 val = I915_READ(CDCLK_CTL);
5419 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5420 val |= divider;
5421 /*
5422 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5423 * enable otherwise.
5424 */
5425 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5426 if (frequency >= 500000)
5427 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5428
5429 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5430 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5431 val |= (frequency - 1000) / 500;
5432 I915_WRITE(CDCLK_CTL, val);
5433 }
5434
5435 mutex_lock(&dev_priv->rps.hw_lock);
5436 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5437 DIV_ROUND_UP(frequency, 25000));
5438 mutex_unlock(&dev_priv->rps.hw_lock);
5439
5440 if (ret) {
5441 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5442 ret, frequency);
5443 return;
5444 }
5445
5446 intel_update_cdclk(dev);
5447 }
5448
5449 void broxton_init_cdclk(struct drm_device *dev)
5450 {
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 uint32_t val;
5453
5454 /*
5455 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5456 * or else the reset will hang because there is no PCH to respond.
5457 * Move the handshake programming to initialization sequence.
5458 * Previously was left up to BIOS.
5459 */
5460 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5461 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5462 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5463
5464 /* Enable PG1 for cdclk */
5465 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5466
5467 /* check if cd clock is enabled */
5468 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5469 DRM_DEBUG_KMS("Display already initialized\n");
5470 return;
5471 }
5472
5473 /*
5474 * FIXME:
5475 * - The initial CDCLK needs to be read from VBT.
5476 * Need to make this change after VBT has changes for BXT.
5477 * - check if setting the max (or any) cdclk freq is really necessary
5478 * here, it belongs to modeset time
5479 */
5480 broxton_set_cdclk(dev, 624000);
5481
5482 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5483 POSTING_READ(DBUF_CTL);
5484
5485 udelay(10);
5486
5487 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5488 DRM_ERROR("DBuf power enable timeout!\n");
5489 }
5490
5491 void broxton_uninit_cdclk(struct drm_device *dev)
5492 {
5493 struct drm_i915_private *dev_priv = dev->dev_private;
5494
5495 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5496 POSTING_READ(DBUF_CTL);
5497
5498 udelay(10);
5499
5500 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5501 DRM_ERROR("DBuf power disable timeout!\n");
5502
5503 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5504 broxton_set_cdclk(dev, 19200);
5505
5506 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5507 }
5508
5509 static const struct skl_cdclk_entry {
5510 unsigned int freq;
5511 unsigned int vco;
5512 } skl_cdclk_frequencies[] = {
5513 { .freq = 308570, .vco = 8640 },
5514 { .freq = 337500, .vco = 8100 },
5515 { .freq = 432000, .vco = 8640 },
5516 { .freq = 450000, .vco = 8100 },
5517 { .freq = 540000, .vco = 8100 },
5518 { .freq = 617140, .vco = 8640 },
5519 { .freq = 675000, .vco = 8100 },
5520 };
5521
5522 static unsigned int skl_cdclk_decimal(unsigned int freq)
5523 {
5524 return (freq - 1000) / 500;
5525 }
5526
5527 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5528 {
5529 unsigned int i;
5530
5531 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5532 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5533
5534 if (e->freq == freq)
5535 return e->vco;
5536 }
5537
5538 return 8100;
5539 }
5540
5541 static void
5542 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5543 {
5544 unsigned int min_freq;
5545 u32 val;
5546
5547 /* select the minimum CDCLK before enabling DPLL 0 */
5548 val = I915_READ(CDCLK_CTL);
5549 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5550 val |= CDCLK_FREQ_337_308;
5551
5552 if (required_vco == 8640)
5553 min_freq = 308570;
5554 else
5555 min_freq = 337500;
5556
5557 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5558
5559 I915_WRITE(CDCLK_CTL, val);
5560 POSTING_READ(CDCLK_CTL);
5561
5562 /*
5563 * We always enable DPLL0 with the lowest link rate possible, but still
5564 * taking into account the VCO required to operate the eDP panel at the
5565 * desired frequency. The usual DP link rates operate with a VCO of
5566 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5567 * The modeset code is responsible for the selection of the exact link
5568 * rate later on, with the constraint of choosing a frequency that
5569 * works with required_vco.
5570 */
5571 val = I915_READ(DPLL_CTRL1);
5572
5573 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5574 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5575 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5576 if (required_vco == 8640)
5577 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5578 SKL_DPLL0);
5579 else
5580 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5581 SKL_DPLL0);
5582
5583 I915_WRITE(DPLL_CTRL1, val);
5584 POSTING_READ(DPLL_CTRL1);
5585
5586 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5587
5588 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5589 DRM_ERROR("DPLL0 not locked\n");
5590 }
5591
5592 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5593 {
5594 int ret;
5595 u32 val;
5596
5597 /* inform PCU we want to change CDCLK */
5598 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5599 mutex_lock(&dev_priv->rps.hw_lock);
5600 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5601 mutex_unlock(&dev_priv->rps.hw_lock);
5602
5603 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5604 }
5605
5606 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5607 {
5608 unsigned int i;
5609
5610 for (i = 0; i < 15; i++) {
5611 if (skl_cdclk_pcu_ready(dev_priv))
5612 return true;
5613 udelay(10);
5614 }
5615
5616 return false;
5617 }
5618
5619 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5620 {
5621 struct drm_device *dev = dev_priv->dev;
5622 u32 freq_select, pcu_ack;
5623
5624 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5625
5626 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5627 DRM_ERROR("failed to inform PCU about cdclk change\n");
5628 return;
5629 }
5630
5631 /* set CDCLK_CTL */
5632 switch(freq) {
5633 case 450000:
5634 case 432000:
5635 freq_select = CDCLK_FREQ_450_432;
5636 pcu_ack = 1;
5637 break;
5638 case 540000:
5639 freq_select = CDCLK_FREQ_540;
5640 pcu_ack = 2;
5641 break;
5642 case 308570:
5643 case 337500:
5644 default:
5645 freq_select = CDCLK_FREQ_337_308;
5646 pcu_ack = 0;
5647 break;
5648 case 617140:
5649 case 675000:
5650 freq_select = CDCLK_FREQ_675_617;
5651 pcu_ack = 3;
5652 break;
5653 }
5654
5655 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5656 POSTING_READ(CDCLK_CTL);
5657
5658 /* inform PCU of the change */
5659 mutex_lock(&dev_priv->rps.hw_lock);
5660 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5661 mutex_unlock(&dev_priv->rps.hw_lock);
5662
5663 intel_update_cdclk(dev);
5664 }
5665
5666 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5667 {
5668 /* disable DBUF power */
5669 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5670 POSTING_READ(DBUF_CTL);
5671
5672 udelay(10);
5673
5674 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5675 DRM_ERROR("DBuf power disable timeout\n");
5676
5677 /* disable DPLL0 */
5678 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5679 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5680 DRM_ERROR("Couldn't disable DPLL0\n");
5681 }
5682
5683 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5684 {
5685 unsigned int required_vco;
5686
5687 /* DPLL0 not enabled (happens on early BIOS versions) */
5688 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5689 /* enable DPLL0 */
5690 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5691 skl_dpll0_enable(dev_priv, required_vco);
5692 }
5693
5694 /* set CDCLK to the frequency the BIOS chose */
5695 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5696
5697 /* enable DBUF power */
5698 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5699 POSTING_READ(DBUF_CTL);
5700
5701 udelay(10);
5702
5703 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5704 DRM_ERROR("DBuf power enable timeout\n");
5705 }
5706
5707 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5708 {
5709 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5710 uint32_t cdctl = I915_READ(CDCLK_CTL);
5711 int freq = dev_priv->skl_boot_cdclk;
5712
5713 /*
5714 * check if the pre-os intialized the display
5715 * There is SWF18 scratchpad register defined which is set by the
5716 * pre-os which can be used by the OS drivers to check the status
5717 */
5718 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5719 goto sanitize;
5720
5721 /* Is PLL enabled and locked ? */
5722 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5723 goto sanitize;
5724
5725 /* DPLL okay; verify the cdclock
5726 *
5727 * Noticed in some instances that the freq selection is correct but
5728 * decimal part is programmed wrong from BIOS where pre-os does not
5729 * enable display. Verify the same as well.
5730 */
5731 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5732 /* All well; nothing to sanitize */
5733 return false;
5734 sanitize:
5735 /*
5736 * As of now initialize with max cdclk till
5737 * we get dynamic cdclk support
5738 * */
5739 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5740 skl_init_cdclk(dev_priv);
5741
5742 /* we did have to sanitize */
5743 return true;
5744 }
5745
5746 /* Adjust CDclk dividers to allow high res or save power if possible */
5747 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5748 {
5749 struct drm_i915_private *dev_priv = dev->dev_private;
5750 u32 val, cmd;
5751
5752 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5753 != dev_priv->cdclk_freq);
5754
5755 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5756 cmd = 2;
5757 else if (cdclk == 266667)
5758 cmd = 1;
5759 else
5760 cmd = 0;
5761
5762 mutex_lock(&dev_priv->rps.hw_lock);
5763 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5764 val &= ~DSPFREQGUAR_MASK;
5765 val |= (cmd << DSPFREQGUAR_SHIFT);
5766 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5767 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5768 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5769 50)) {
5770 DRM_ERROR("timed out waiting for CDclk change\n");
5771 }
5772 mutex_unlock(&dev_priv->rps.hw_lock);
5773
5774 mutex_lock(&dev_priv->sb_lock);
5775
5776 if (cdclk == 400000) {
5777 u32 divider;
5778
5779 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5780
5781 /* adjust cdclk divider */
5782 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5783 val &= ~CCK_FREQUENCY_VALUES;
5784 val |= divider;
5785 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5786
5787 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5788 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5789 50))
5790 DRM_ERROR("timed out waiting for CDclk change\n");
5791 }
5792
5793 /* adjust self-refresh exit latency value */
5794 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5795 val &= ~0x7f;
5796
5797 /*
5798 * For high bandwidth configs, we set a higher latency in the bunit
5799 * so that the core display fetch happens in time to avoid underruns.
5800 */
5801 if (cdclk == 400000)
5802 val |= 4500 / 250; /* 4.5 usec */
5803 else
5804 val |= 3000 / 250; /* 3.0 usec */
5805 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5806
5807 mutex_unlock(&dev_priv->sb_lock);
5808
5809 intel_update_cdclk(dev);
5810 }
5811
5812 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5813 {
5814 struct drm_i915_private *dev_priv = dev->dev_private;
5815 u32 val, cmd;
5816
5817 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5818 != dev_priv->cdclk_freq);
5819
5820 switch (cdclk) {
5821 case 333333:
5822 case 320000:
5823 case 266667:
5824 case 200000:
5825 break;
5826 default:
5827 MISSING_CASE(cdclk);
5828 return;
5829 }
5830
5831 /*
5832 * Specs are full of misinformation, but testing on actual
5833 * hardware has shown that we just need to write the desired
5834 * CCK divider into the Punit register.
5835 */
5836 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5837
5838 mutex_lock(&dev_priv->rps.hw_lock);
5839 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5840 val &= ~DSPFREQGUAR_MASK_CHV;
5841 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5842 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5843 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5844 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5845 50)) {
5846 DRM_ERROR("timed out waiting for CDclk change\n");
5847 }
5848 mutex_unlock(&dev_priv->rps.hw_lock);
5849
5850 intel_update_cdclk(dev);
5851 }
5852
5853 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5854 int max_pixclk)
5855 {
5856 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5857 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5858
5859 /*
5860 * Really only a few cases to deal with, as only 4 CDclks are supported:
5861 * 200MHz
5862 * 267MHz
5863 * 320/333MHz (depends on HPLL freq)
5864 * 400MHz (VLV only)
5865 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5866 * of the lower bin and adjust if needed.
5867 *
5868 * We seem to get an unstable or solid color picture at 200MHz.
5869 * Not sure what's wrong. For now use 200MHz only when all pipes
5870 * are off.
5871 */
5872 if (!IS_CHERRYVIEW(dev_priv) &&
5873 max_pixclk > freq_320*limit/100)
5874 return 400000;
5875 else if (max_pixclk > 266667*limit/100)
5876 return freq_320;
5877 else if (max_pixclk > 0)
5878 return 266667;
5879 else
5880 return 200000;
5881 }
5882
5883 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5884 int max_pixclk)
5885 {
5886 /*
5887 * FIXME:
5888 * - remove the guardband, it's not needed on BXT
5889 * - set 19.2MHz bypass frequency if there are no active pipes
5890 */
5891 if (max_pixclk > 576000*9/10)
5892 return 624000;
5893 else if (max_pixclk > 384000*9/10)
5894 return 576000;
5895 else if (max_pixclk > 288000*9/10)
5896 return 384000;
5897 else if (max_pixclk > 144000*9/10)
5898 return 288000;
5899 else
5900 return 144000;
5901 }
5902
5903 /* Compute the max pixel clock for new configuration. */
5904 static int intel_mode_max_pixclk(struct drm_device *dev,
5905 struct drm_atomic_state *state)
5906 {
5907 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5908 struct drm_i915_private *dev_priv = dev->dev_private;
5909 struct drm_crtc *crtc;
5910 struct drm_crtc_state *crtc_state;
5911 unsigned max_pixclk = 0, i;
5912 enum pipe pipe;
5913
5914 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
5915 sizeof(intel_state->min_pixclk));
5916
5917 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5918 int pixclk = 0;
5919
5920 if (crtc_state->enable)
5921 pixclk = crtc_state->adjusted_mode.crtc_clock;
5922
5923 intel_state->min_pixclk[i] = pixclk;
5924 }
5925
5926 for_each_pipe(dev_priv, pipe)
5927 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
5928
5929 return max_pixclk;
5930 }
5931
5932 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
5933 {
5934 struct drm_device *dev = state->dev;
5935 struct drm_i915_private *dev_priv = dev->dev_private;
5936 int max_pixclk = intel_mode_max_pixclk(dev, state);
5937 struct intel_atomic_state *intel_state =
5938 to_intel_atomic_state(state);
5939
5940 if (max_pixclk < 0)
5941 return max_pixclk;
5942
5943 intel_state->cdclk = intel_state->dev_cdclk =
5944 valleyview_calc_cdclk(dev_priv, max_pixclk);
5945
5946 if (!intel_state->active_crtcs)
5947 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
5948
5949 return 0;
5950 }
5951
5952 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5953 {
5954 struct drm_device *dev = state->dev;
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 int max_pixclk = intel_mode_max_pixclk(dev, state);
5957 struct intel_atomic_state *intel_state =
5958 to_intel_atomic_state(state);
5959
5960 if (max_pixclk < 0)
5961 return max_pixclk;
5962
5963 intel_state->cdclk = intel_state->dev_cdclk =
5964 broxton_calc_cdclk(dev_priv, max_pixclk);
5965
5966 if (!intel_state->active_crtcs)
5967 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
5968
5969 return 0;
5970 }
5971
5972 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5973 {
5974 unsigned int credits, default_credits;
5975
5976 if (IS_CHERRYVIEW(dev_priv))
5977 default_credits = PFI_CREDIT(12);
5978 else
5979 default_credits = PFI_CREDIT(8);
5980
5981 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
5982 /* CHV suggested value is 31 or 63 */
5983 if (IS_CHERRYVIEW(dev_priv))
5984 credits = PFI_CREDIT_63;
5985 else
5986 credits = PFI_CREDIT(15);
5987 } else {
5988 credits = default_credits;
5989 }
5990
5991 /*
5992 * WA - write default credits before re-programming
5993 * FIXME: should we also set the resend bit here?
5994 */
5995 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5996 default_credits);
5997
5998 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5999 credits | PFI_CREDIT_RESEND);
6000
6001 /*
6002 * FIXME is this guaranteed to clear
6003 * immediately or should we poll for it?
6004 */
6005 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6006 }
6007
6008 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6009 {
6010 struct drm_device *dev = old_state->dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 struct intel_atomic_state *old_intel_state =
6013 to_intel_atomic_state(old_state);
6014 unsigned req_cdclk = old_intel_state->dev_cdclk;
6015
6016 /*
6017 * FIXME: We can end up here with all power domains off, yet
6018 * with a CDCLK frequency other than the minimum. To account
6019 * for this take the PIPE-A power domain, which covers the HW
6020 * blocks needed for the following programming. This can be
6021 * removed once it's guaranteed that we get here either with
6022 * the minimum CDCLK set, or the required power domains
6023 * enabled.
6024 */
6025 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6026
6027 if (IS_CHERRYVIEW(dev))
6028 cherryview_set_cdclk(dev, req_cdclk);
6029 else
6030 valleyview_set_cdclk(dev, req_cdclk);
6031
6032 vlv_program_pfi_credits(dev_priv);
6033
6034 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6035 }
6036
6037 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6038 {
6039 struct drm_device *dev = crtc->dev;
6040 struct drm_i915_private *dev_priv = to_i915(dev);
6041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6042 struct intel_encoder *encoder;
6043 struct intel_crtc_state *pipe_config =
6044 to_intel_crtc_state(crtc->state);
6045 int pipe = intel_crtc->pipe;
6046
6047 if (WARN_ON(intel_crtc->active))
6048 return;
6049
6050 if (intel_crtc->config->has_dp_encoder)
6051 intel_dp_set_m_n(intel_crtc, M1_N1);
6052
6053 intel_set_pipe_timings(intel_crtc);
6054 intel_set_pipe_src_size(intel_crtc);
6055
6056 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058
6059 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6060 I915_WRITE(CHV_CANVAS(pipe), 0);
6061 }
6062
6063 i9xx_set_pipeconf(intel_crtc);
6064
6065 intel_crtc->active = true;
6066
6067 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6068
6069 for_each_encoder_on_crtc(dev, crtc, encoder)
6070 if (encoder->pre_pll_enable)
6071 encoder->pre_pll_enable(encoder);
6072
6073 if (!intel_crtc->config->has_dsi_encoder) {
6074 if (IS_CHERRYVIEW(dev)) {
6075 chv_prepare_pll(intel_crtc, intel_crtc->config);
6076 chv_enable_pll(intel_crtc, intel_crtc->config);
6077 } else {
6078 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6079 vlv_enable_pll(intel_crtc, intel_crtc->config);
6080 }
6081 }
6082
6083 for_each_encoder_on_crtc(dev, crtc, encoder)
6084 if (encoder->pre_enable)
6085 encoder->pre_enable(encoder);
6086
6087 i9xx_pfit_enable(intel_crtc);
6088
6089 intel_color_load_luts(&pipe_config->base);
6090
6091 intel_update_watermarks(crtc);
6092 intel_enable_pipe(intel_crtc);
6093
6094 assert_vblank_disabled(crtc);
6095 drm_crtc_vblank_on(crtc);
6096
6097 for_each_encoder_on_crtc(dev, crtc, encoder)
6098 encoder->enable(encoder);
6099 }
6100
6101 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6102 {
6103 struct drm_device *dev = crtc->base.dev;
6104 struct drm_i915_private *dev_priv = dev->dev_private;
6105
6106 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6107 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6108 }
6109
6110 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6111 {
6112 struct drm_device *dev = crtc->dev;
6113 struct drm_i915_private *dev_priv = to_i915(dev);
6114 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6115 struct intel_encoder *encoder;
6116 struct intel_crtc_state *pipe_config =
6117 to_intel_crtc_state(crtc->state);
6118 int pipe = intel_crtc->pipe;
6119
6120 if (WARN_ON(intel_crtc->active))
6121 return;
6122
6123 i9xx_set_pll_dividers(intel_crtc);
6124
6125 if (intel_crtc->config->has_dp_encoder)
6126 intel_dp_set_m_n(intel_crtc, M1_N1);
6127
6128 intel_set_pipe_timings(intel_crtc);
6129 intel_set_pipe_src_size(intel_crtc);
6130
6131 i9xx_set_pipeconf(intel_crtc);
6132
6133 intel_crtc->active = true;
6134
6135 if (!IS_GEN2(dev))
6136 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6137
6138 for_each_encoder_on_crtc(dev, crtc, encoder)
6139 if (encoder->pre_enable)
6140 encoder->pre_enable(encoder);
6141
6142 i9xx_enable_pll(intel_crtc);
6143
6144 i9xx_pfit_enable(intel_crtc);
6145
6146 intel_color_load_luts(&pipe_config->base);
6147
6148 intel_update_watermarks(crtc);
6149 intel_enable_pipe(intel_crtc);
6150
6151 assert_vblank_disabled(crtc);
6152 drm_crtc_vblank_on(crtc);
6153
6154 for_each_encoder_on_crtc(dev, crtc, encoder)
6155 encoder->enable(encoder);
6156 }
6157
6158 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6159 {
6160 struct drm_device *dev = crtc->base.dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162
6163 if (!crtc->config->gmch_pfit.control)
6164 return;
6165
6166 assert_pipe_disabled(dev_priv, crtc->pipe);
6167
6168 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6169 I915_READ(PFIT_CONTROL));
6170 I915_WRITE(PFIT_CONTROL, 0);
6171 }
6172
6173 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6174 {
6175 struct drm_device *dev = crtc->dev;
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6178 struct intel_encoder *encoder;
6179 int pipe = intel_crtc->pipe;
6180
6181 /*
6182 * On gen2 planes are double buffered but the pipe isn't, so we must
6183 * wait for planes to fully turn off before disabling the pipe.
6184 */
6185 if (IS_GEN2(dev))
6186 intel_wait_for_vblank(dev, pipe);
6187
6188 for_each_encoder_on_crtc(dev, crtc, encoder)
6189 encoder->disable(encoder);
6190
6191 drm_crtc_vblank_off(crtc);
6192 assert_vblank_disabled(crtc);
6193
6194 intel_disable_pipe(intel_crtc);
6195
6196 i9xx_pfit_disable(intel_crtc);
6197
6198 for_each_encoder_on_crtc(dev, crtc, encoder)
6199 if (encoder->post_disable)
6200 encoder->post_disable(encoder);
6201
6202 if (!intel_crtc->config->has_dsi_encoder) {
6203 if (IS_CHERRYVIEW(dev))
6204 chv_disable_pll(dev_priv, pipe);
6205 else if (IS_VALLEYVIEW(dev))
6206 vlv_disable_pll(dev_priv, pipe);
6207 else
6208 i9xx_disable_pll(intel_crtc);
6209 }
6210
6211 for_each_encoder_on_crtc(dev, crtc, encoder)
6212 if (encoder->post_pll_disable)
6213 encoder->post_pll_disable(encoder);
6214
6215 if (!IS_GEN2(dev))
6216 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6217 }
6218
6219 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6220 {
6221 struct intel_encoder *encoder;
6222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6223 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6224 enum intel_display_power_domain domain;
6225 unsigned long domains;
6226
6227 if (!intel_crtc->active)
6228 return;
6229
6230 if (to_intel_plane_state(crtc->primary->state)->visible) {
6231 WARN_ON(intel_crtc->unpin_work);
6232
6233 intel_pre_disable_primary_noatomic(crtc);
6234
6235 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6236 to_intel_plane_state(crtc->primary->state)->visible = false;
6237 }
6238
6239 dev_priv->display.crtc_disable(crtc);
6240
6241 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was enabled, now disabled\n",
6242 crtc->base.id);
6243
6244 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->state, NULL) < 0);
6245 crtc->state->active = false;
6246 intel_crtc->active = false;
6247 crtc->enabled = false;
6248 crtc->state->connector_mask = 0;
6249 crtc->state->encoder_mask = 0;
6250
6251 for_each_encoder_on_crtc(crtc->dev, crtc, encoder)
6252 encoder->base.crtc = NULL;
6253
6254 intel_fbc_disable(intel_crtc);
6255 intel_update_watermarks(crtc);
6256 intel_disable_shared_dpll(intel_crtc);
6257
6258 domains = intel_crtc->enabled_power_domains;
6259 for_each_power_domain(domain, domains)
6260 intel_display_power_put(dev_priv, domain);
6261 intel_crtc->enabled_power_domains = 0;
6262
6263 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6264 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6265 }
6266
6267 /*
6268 * turn all crtc's off, but do not adjust state
6269 * This has to be paired with a call to intel_modeset_setup_hw_state.
6270 */
6271 int intel_display_suspend(struct drm_device *dev)
6272 {
6273 struct drm_i915_private *dev_priv = to_i915(dev);
6274 struct drm_atomic_state *state;
6275 int ret;
6276
6277 state = drm_atomic_helper_suspend(dev);
6278 ret = PTR_ERR_OR_ZERO(state);
6279 if (ret)
6280 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6281 else
6282 dev_priv->modeset_restore_state = state;
6283 return ret;
6284 }
6285
6286 void intel_encoder_destroy(struct drm_encoder *encoder)
6287 {
6288 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6289
6290 drm_encoder_cleanup(encoder);
6291 kfree(intel_encoder);
6292 }
6293
6294 /* Cross check the actual hw state with our own modeset state tracking (and it's
6295 * internal consistency). */
6296 static void intel_connector_check_state(struct intel_connector *connector)
6297 {
6298 struct drm_crtc *crtc = connector->base.state->crtc;
6299
6300 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6301 connector->base.base.id,
6302 connector->base.name);
6303
6304 if (connector->get_hw_state(connector)) {
6305 struct intel_encoder *encoder = connector->encoder;
6306 struct drm_connector_state *conn_state = connector->base.state;
6307
6308 I915_STATE_WARN(!crtc,
6309 "connector enabled without attached crtc\n");
6310
6311 if (!crtc)
6312 return;
6313
6314 I915_STATE_WARN(!crtc->state->active,
6315 "connector is active, but attached crtc isn't\n");
6316
6317 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6318 return;
6319
6320 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6321 "atomic encoder doesn't match attached encoder\n");
6322
6323 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6324 "attached encoder crtc differs from connector crtc\n");
6325 } else {
6326 I915_STATE_WARN(crtc && crtc->state->active,
6327 "attached crtc is active, but connector isn't\n");
6328 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6329 "best encoder set without crtc!\n");
6330 }
6331 }
6332
6333 int intel_connector_init(struct intel_connector *connector)
6334 {
6335 drm_atomic_helper_connector_reset(&connector->base);
6336
6337 if (!connector->base.state)
6338 return -ENOMEM;
6339
6340 return 0;
6341 }
6342
6343 struct intel_connector *intel_connector_alloc(void)
6344 {
6345 struct intel_connector *connector;
6346
6347 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6348 if (!connector)
6349 return NULL;
6350
6351 if (intel_connector_init(connector) < 0) {
6352 kfree(connector);
6353 return NULL;
6354 }
6355
6356 return connector;
6357 }
6358
6359 /* Simple connector->get_hw_state implementation for encoders that support only
6360 * one connector and no cloning and hence the encoder state determines the state
6361 * of the connector. */
6362 bool intel_connector_get_hw_state(struct intel_connector *connector)
6363 {
6364 enum pipe pipe = 0;
6365 struct intel_encoder *encoder = connector->encoder;
6366
6367 return encoder->get_hw_state(encoder, &pipe);
6368 }
6369
6370 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6371 {
6372 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6373 return crtc_state->fdi_lanes;
6374
6375 return 0;
6376 }
6377
6378 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6379 struct intel_crtc_state *pipe_config)
6380 {
6381 struct drm_atomic_state *state = pipe_config->base.state;
6382 struct intel_crtc *other_crtc;
6383 struct intel_crtc_state *other_crtc_state;
6384
6385 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6386 pipe_name(pipe), pipe_config->fdi_lanes);
6387 if (pipe_config->fdi_lanes > 4) {
6388 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6389 pipe_name(pipe), pipe_config->fdi_lanes);
6390 return -EINVAL;
6391 }
6392
6393 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6394 if (pipe_config->fdi_lanes > 2) {
6395 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6396 pipe_config->fdi_lanes);
6397 return -EINVAL;
6398 } else {
6399 return 0;
6400 }
6401 }
6402
6403 if (INTEL_INFO(dev)->num_pipes == 2)
6404 return 0;
6405
6406 /* Ivybridge 3 pipe is really complicated */
6407 switch (pipe) {
6408 case PIPE_A:
6409 return 0;
6410 case PIPE_B:
6411 if (pipe_config->fdi_lanes <= 2)
6412 return 0;
6413
6414 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6415 other_crtc_state =
6416 intel_atomic_get_crtc_state(state, other_crtc);
6417 if (IS_ERR(other_crtc_state))
6418 return PTR_ERR(other_crtc_state);
6419
6420 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6421 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6422 pipe_name(pipe), pipe_config->fdi_lanes);
6423 return -EINVAL;
6424 }
6425 return 0;
6426 case PIPE_C:
6427 if (pipe_config->fdi_lanes > 2) {
6428 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6429 pipe_name(pipe), pipe_config->fdi_lanes);
6430 return -EINVAL;
6431 }
6432
6433 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6434 other_crtc_state =
6435 intel_atomic_get_crtc_state(state, other_crtc);
6436 if (IS_ERR(other_crtc_state))
6437 return PTR_ERR(other_crtc_state);
6438
6439 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6440 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6441 return -EINVAL;
6442 }
6443 return 0;
6444 default:
6445 BUG();
6446 }
6447 }
6448
6449 #define RETRY 1
6450 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6451 struct intel_crtc_state *pipe_config)
6452 {
6453 struct drm_device *dev = intel_crtc->base.dev;
6454 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6455 int lane, link_bw, fdi_dotclock, ret;
6456 bool needs_recompute = false;
6457
6458 retry:
6459 /* FDI is a binary signal running at ~2.7GHz, encoding
6460 * each output octet as 10 bits. The actual frequency
6461 * is stored as a divider into a 100MHz clock, and the
6462 * mode pixel clock is stored in units of 1KHz.
6463 * Hence the bw of each lane in terms of the mode signal
6464 * is:
6465 */
6466 link_bw = intel_fdi_link_freq(to_i915(dev), pipe_config);
6467
6468 fdi_dotclock = adjusted_mode->crtc_clock;
6469
6470 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6471 pipe_config->pipe_bpp);
6472
6473 pipe_config->fdi_lanes = lane;
6474
6475 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6476 link_bw, &pipe_config->fdi_m_n);
6477
6478 ret = ironlake_check_fdi_lanes(dev, intel_crtc->pipe, pipe_config);
6479 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6480 pipe_config->pipe_bpp -= 2*3;
6481 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6482 pipe_config->pipe_bpp);
6483 needs_recompute = true;
6484 pipe_config->bw_constrained = true;
6485
6486 goto retry;
6487 }
6488
6489 if (needs_recompute)
6490 return RETRY;
6491
6492 return ret;
6493 }
6494
6495 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6496 struct intel_crtc_state *pipe_config)
6497 {
6498 if (pipe_config->pipe_bpp > 24)
6499 return false;
6500
6501 /* HSW can handle pixel rate up to cdclk? */
6502 if (IS_HASWELL(dev_priv->dev))
6503 return true;
6504
6505 /*
6506 * We compare against max which means we must take
6507 * the increased cdclk requirement into account when
6508 * calculating the new cdclk.
6509 *
6510 * Should measure whether using a lower cdclk w/o IPS
6511 */
6512 return ilk_pipe_pixel_rate(pipe_config) <=
6513 dev_priv->max_cdclk_freq * 95 / 100;
6514 }
6515
6516 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6517 struct intel_crtc_state *pipe_config)
6518 {
6519 struct drm_device *dev = crtc->base.dev;
6520 struct drm_i915_private *dev_priv = dev->dev_private;
6521
6522 pipe_config->ips_enabled = i915.enable_ips &&
6523 hsw_crtc_supports_ips(crtc) &&
6524 pipe_config_supports_ips(dev_priv, pipe_config);
6525 }
6526
6527 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6528 {
6529 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6530
6531 /* GDG double wide on either pipe, otherwise pipe A only */
6532 return INTEL_INFO(dev_priv)->gen < 4 &&
6533 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6534 }
6535
6536 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6537 struct intel_crtc_state *pipe_config)
6538 {
6539 struct drm_device *dev = crtc->base.dev;
6540 struct drm_i915_private *dev_priv = dev->dev_private;
6541 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6542
6543 /* FIXME should check pixel clock limits on all platforms */
6544 if (INTEL_INFO(dev)->gen < 4) {
6545 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6546
6547 /*
6548 * Enable double wide mode when the dot clock
6549 * is > 90% of the (display) core speed.
6550 */
6551 if (intel_crtc_supports_double_wide(crtc) &&
6552 adjusted_mode->crtc_clock > clock_limit) {
6553 clock_limit *= 2;
6554 pipe_config->double_wide = true;
6555 }
6556
6557 if (adjusted_mode->crtc_clock > clock_limit) {
6558 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6559 adjusted_mode->crtc_clock, clock_limit,
6560 yesno(pipe_config->double_wide));
6561 return -EINVAL;
6562 }
6563 }
6564
6565 /*
6566 * Pipe horizontal size must be even in:
6567 * - DVO ganged mode
6568 * - LVDS dual channel mode
6569 * - Double wide pipe
6570 */
6571 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6572 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6573 pipe_config->pipe_src_w &= ~1;
6574
6575 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6576 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6577 */
6578 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6579 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6580 return -EINVAL;
6581
6582 if (HAS_IPS(dev))
6583 hsw_compute_ips_config(crtc, pipe_config);
6584
6585 if (pipe_config->has_pch_encoder)
6586 return ironlake_fdi_compute_config(crtc, pipe_config);
6587
6588 return 0;
6589 }
6590
6591 static int skylake_get_display_clock_speed(struct drm_device *dev)
6592 {
6593 struct drm_i915_private *dev_priv = to_i915(dev);
6594 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6595 uint32_t cdctl = I915_READ(CDCLK_CTL);
6596 uint32_t linkrate;
6597
6598 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6599 return 24000; /* 24MHz is the cd freq with NSSC ref */
6600
6601 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6602 return 540000;
6603
6604 linkrate = (I915_READ(DPLL_CTRL1) &
6605 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6606
6607 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6608 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6609 /* vco 8640 */
6610 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6611 case CDCLK_FREQ_450_432:
6612 return 432000;
6613 case CDCLK_FREQ_337_308:
6614 return 308570;
6615 case CDCLK_FREQ_675_617:
6616 return 617140;
6617 default:
6618 WARN(1, "Unknown cd freq selection\n");
6619 }
6620 } else {
6621 /* vco 8100 */
6622 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6623 case CDCLK_FREQ_450_432:
6624 return 450000;
6625 case CDCLK_FREQ_337_308:
6626 return 337500;
6627 case CDCLK_FREQ_675_617:
6628 return 675000;
6629 default:
6630 WARN(1, "Unknown cd freq selection\n");
6631 }
6632 }
6633
6634 /* error case, do as if DPLL0 isn't enabled */
6635 return 24000;
6636 }
6637
6638 static int broxton_get_display_clock_speed(struct drm_device *dev)
6639 {
6640 struct drm_i915_private *dev_priv = to_i915(dev);
6641 uint32_t cdctl = I915_READ(CDCLK_CTL);
6642 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6643 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6644 int cdclk;
6645
6646 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6647 return 19200;
6648
6649 cdclk = 19200 * pll_ratio / 2;
6650
6651 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6652 case BXT_CDCLK_CD2X_DIV_SEL_1:
6653 return cdclk; /* 576MHz or 624MHz */
6654 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6655 return cdclk * 2 / 3; /* 384MHz */
6656 case BXT_CDCLK_CD2X_DIV_SEL_2:
6657 return cdclk / 2; /* 288MHz */
6658 case BXT_CDCLK_CD2X_DIV_SEL_4:
6659 return cdclk / 4; /* 144MHz */
6660 }
6661
6662 /* error case, do as if DE PLL isn't enabled */
6663 return 19200;
6664 }
6665
6666 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6667 {
6668 struct drm_i915_private *dev_priv = dev->dev_private;
6669 uint32_t lcpll = I915_READ(LCPLL_CTL);
6670 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6671
6672 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6673 return 800000;
6674 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6675 return 450000;
6676 else if (freq == LCPLL_CLK_FREQ_450)
6677 return 450000;
6678 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6679 return 540000;
6680 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6681 return 337500;
6682 else
6683 return 675000;
6684 }
6685
6686 static int haswell_get_display_clock_speed(struct drm_device *dev)
6687 {
6688 struct drm_i915_private *dev_priv = dev->dev_private;
6689 uint32_t lcpll = I915_READ(LCPLL_CTL);
6690 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6691
6692 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6693 return 800000;
6694 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6695 return 450000;
6696 else if (freq == LCPLL_CLK_FREQ_450)
6697 return 450000;
6698 else if (IS_HSW_ULT(dev))
6699 return 337500;
6700 else
6701 return 540000;
6702 }
6703
6704 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6705 {
6706 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6707 CCK_DISPLAY_CLOCK_CONTROL);
6708 }
6709
6710 static int ilk_get_display_clock_speed(struct drm_device *dev)
6711 {
6712 return 450000;
6713 }
6714
6715 static int i945_get_display_clock_speed(struct drm_device *dev)
6716 {
6717 return 400000;
6718 }
6719
6720 static int i915_get_display_clock_speed(struct drm_device *dev)
6721 {
6722 return 333333;
6723 }
6724
6725 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6726 {
6727 return 200000;
6728 }
6729
6730 static int pnv_get_display_clock_speed(struct drm_device *dev)
6731 {
6732 u16 gcfgc = 0;
6733
6734 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6735
6736 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6737 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6738 return 266667;
6739 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6740 return 333333;
6741 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6742 return 444444;
6743 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6744 return 200000;
6745 default:
6746 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6747 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6748 return 133333;
6749 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6750 return 166667;
6751 }
6752 }
6753
6754 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6755 {
6756 u16 gcfgc = 0;
6757
6758 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6759
6760 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6761 return 133333;
6762 else {
6763 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6764 case GC_DISPLAY_CLOCK_333_MHZ:
6765 return 333333;
6766 default:
6767 case GC_DISPLAY_CLOCK_190_200_MHZ:
6768 return 190000;
6769 }
6770 }
6771 }
6772
6773 static int i865_get_display_clock_speed(struct drm_device *dev)
6774 {
6775 return 266667;
6776 }
6777
6778 static int i85x_get_display_clock_speed(struct drm_device *dev)
6779 {
6780 u16 hpllcc = 0;
6781
6782 /*
6783 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6784 * encoding is different :(
6785 * FIXME is this the right way to detect 852GM/852GMV?
6786 */
6787 if (dev->pdev->revision == 0x1)
6788 return 133333;
6789
6790 pci_bus_read_config_word(dev->pdev->bus,
6791 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6792
6793 /* Assume that the hardware is in the high speed state. This
6794 * should be the default.
6795 */
6796 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6797 case GC_CLOCK_133_200:
6798 case GC_CLOCK_133_200_2:
6799 case GC_CLOCK_100_200:
6800 return 200000;
6801 case GC_CLOCK_166_250:
6802 return 250000;
6803 case GC_CLOCK_100_133:
6804 return 133333;
6805 case GC_CLOCK_133_266:
6806 case GC_CLOCK_133_266_2:
6807 case GC_CLOCK_166_266:
6808 return 266667;
6809 }
6810
6811 /* Shouldn't happen */
6812 return 0;
6813 }
6814
6815 static int i830_get_display_clock_speed(struct drm_device *dev)
6816 {
6817 return 133333;
6818 }
6819
6820 static unsigned int intel_hpll_vco(struct drm_device *dev)
6821 {
6822 struct drm_i915_private *dev_priv = dev->dev_private;
6823 static const unsigned int blb_vco[8] = {
6824 [0] = 3200000,
6825 [1] = 4000000,
6826 [2] = 5333333,
6827 [3] = 4800000,
6828 [4] = 6400000,
6829 };
6830 static const unsigned int pnv_vco[8] = {
6831 [0] = 3200000,
6832 [1] = 4000000,
6833 [2] = 5333333,
6834 [3] = 4800000,
6835 [4] = 2666667,
6836 };
6837 static const unsigned int cl_vco[8] = {
6838 [0] = 3200000,
6839 [1] = 4000000,
6840 [2] = 5333333,
6841 [3] = 6400000,
6842 [4] = 3333333,
6843 [5] = 3566667,
6844 [6] = 4266667,
6845 };
6846 static const unsigned int elk_vco[8] = {
6847 [0] = 3200000,
6848 [1] = 4000000,
6849 [2] = 5333333,
6850 [3] = 4800000,
6851 };
6852 static const unsigned int ctg_vco[8] = {
6853 [0] = 3200000,
6854 [1] = 4000000,
6855 [2] = 5333333,
6856 [3] = 6400000,
6857 [4] = 2666667,
6858 [5] = 4266667,
6859 };
6860 const unsigned int *vco_table;
6861 unsigned int vco;
6862 uint8_t tmp = 0;
6863
6864 /* FIXME other chipsets? */
6865 if (IS_GM45(dev))
6866 vco_table = ctg_vco;
6867 else if (IS_G4X(dev))
6868 vco_table = elk_vco;
6869 else if (IS_CRESTLINE(dev))
6870 vco_table = cl_vco;
6871 else if (IS_PINEVIEW(dev))
6872 vco_table = pnv_vco;
6873 else if (IS_G33(dev))
6874 vco_table = blb_vco;
6875 else
6876 return 0;
6877
6878 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6879
6880 vco = vco_table[tmp & 0x7];
6881 if (vco == 0)
6882 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6883 else
6884 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6885
6886 return vco;
6887 }
6888
6889 static int gm45_get_display_clock_speed(struct drm_device *dev)
6890 {
6891 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6892 uint16_t tmp = 0;
6893
6894 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6895
6896 cdclk_sel = (tmp >> 12) & 0x1;
6897
6898 switch (vco) {
6899 case 2666667:
6900 case 4000000:
6901 case 5333333:
6902 return cdclk_sel ? 333333 : 222222;
6903 case 3200000:
6904 return cdclk_sel ? 320000 : 228571;
6905 default:
6906 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6907 return 222222;
6908 }
6909 }
6910
6911 static int i965gm_get_display_clock_speed(struct drm_device *dev)
6912 {
6913 static const uint8_t div_3200[] = { 16, 10, 8 };
6914 static const uint8_t div_4000[] = { 20, 12, 10 };
6915 static const uint8_t div_5333[] = { 24, 16, 14 };
6916 const uint8_t *div_table;
6917 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6918 uint16_t tmp = 0;
6919
6920 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6921
6922 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6923
6924 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6925 goto fail;
6926
6927 switch (vco) {
6928 case 3200000:
6929 div_table = div_3200;
6930 break;
6931 case 4000000:
6932 div_table = div_4000;
6933 break;
6934 case 5333333:
6935 div_table = div_5333;
6936 break;
6937 default:
6938 goto fail;
6939 }
6940
6941 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6942
6943 fail:
6944 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6945 return 200000;
6946 }
6947
6948 static int g33_get_display_clock_speed(struct drm_device *dev)
6949 {
6950 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6951 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6952 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6953 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6954 const uint8_t *div_table;
6955 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6956 uint16_t tmp = 0;
6957
6958 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6959
6960 cdclk_sel = (tmp >> 4) & 0x7;
6961
6962 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6963 goto fail;
6964
6965 switch (vco) {
6966 case 3200000:
6967 div_table = div_3200;
6968 break;
6969 case 4000000:
6970 div_table = div_4000;
6971 break;
6972 case 4800000:
6973 div_table = div_4800;
6974 break;
6975 case 5333333:
6976 div_table = div_5333;
6977 break;
6978 default:
6979 goto fail;
6980 }
6981
6982 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6983
6984 fail:
6985 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
6986 return 190476;
6987 }
6988
6989 static void
6990 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6991 {
6992 while (*num > DATA_LINK_M_N_MASK ||
6993 *den > DATA_LINK_M_N_MASK) {
6994 *num >>= 1;
6995 *den >>= 1;
6996 }
6997 }
6998
6999 static void compute_m_n(unsigned int m, unsigned int n,
7000 uint32_t *ret_m, uint32_t *ret_n)
7001 {
7002 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7003 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7004 intel_reduce_m_n_ratio(ret_m, ret_n);
7005 }
7006
7007 void
7008 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7009 int pixel_clock, int link_clock,
7010 struct intel_link_m_n *m_n)
7011 {
7012 m_n->tu = 64;
7013
7014 compute_m_n(bits_per_pixel * pixel_clock,
7015 link_clock * nlanes * 8,
7016 &m_n->gmch_m, &m_n->gmch_n);
7017
7018 compute_m_n(pixel_clock, link_clock,
7019 &m_n->link_m, &m_n->link_n);
7020 }
7021
7022 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7023 {
7024 if (i915.panel_use_ssc >= 0)
7025 return i915.panel_use_ssc != 0;
7026 return dev_priv->vbt.lvds_use_ssc
7027 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7028 }
7029
7030 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7031 {
7032 return (1 << dpll->n) << 16 | dpll->m2;
7033 }
7034
7035 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7036 {
7037 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7038 }
7039
7040 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7041 struct intel_crtc_state *crtc_state,
7042 intel_clock_t *reduced_clock)
7043 {
7044 struct drm_device *dev = crtc->base.dev;
7045 u32 fp, fp2 = 0;
7046
7047 if (IS_PINEVIEW(dev)) {
7048 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7049 if (reduced_clock)
7050 fp2 = pnv_dpll_compute_fp(reduced_clock);
7051 } else {
7052 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7053 if (reduced_clock)
7054 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7055 }
7056
7057 crtc_state->dpll_hw_state.fp0 = fp;
7058
7059 crtc->lowfreq_avail = false;
7060 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7061 reduced_clock) {
7062 crtc_state->dpll_hw_state.fp1 = fp2;
7063 crtc->lowfreq_avail = true;
7064 } else {
7065 crtc_state->dpll_hw_state.fp1 = fp;
7066 }
7067 }
7068
7069 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7070 pipe)
7071 {
7072 u32 reg_val;
7073
7074 /*
7075 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7076 * and set it to a reasonable value instead.
7077 */
7078 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7079 reg_val &= 0xffffff00;
7080 reg_val |= 0x00000030;
7081 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7082
7083 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7084 reg_val &= 0x8cffffff;
7085 reg_val = 0x8c000000;
7086 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7087
7088 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7089 reg_val &= 0xffffff00;
7090 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7091
7092 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7093 reg_val &= 0x00ffffff;
7094 reg_val |= 0xb0000000;
7095 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7096 }
7097
7098 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7099 struct intel_link_m_n *m_n)
7100 {
7101 struct drm_device *dev = crtc->base.dev;
7102 struct drm_i915_private *dev_priv = dev->dev_private;
7103 int pipe = crtc->pipe;
7104
7105 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7106 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7107 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7108 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7109 }
7110
7111 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7112 struct intel_link_m_n *m_n,
7113 struct intel_link_m_n *m2_n2)
7114 {
7115 struct drm_device *dev = crtc->base.dev;
7116 struct drm_i915_private *dev_priv = dev->dev_private;
7117 int pipe = crtc->pipe;
7118 enum transcoder transcoder = crtc->config->cpu_transcoder;
7119
7120 if (INTEL_INFO(dev)->gen >= 5) {
7121 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7122 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7123 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7124 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7125 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7126 * for gen < 8) and if DRRS is supported (to make sure the
7127 * registers are not unnecessarily accessed).
7128 */
7129 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7130 crtc->config->has_drrs) {
7131 I915_WRITE(PIPE_DATA_M2(transcoder),
7132 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7133 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7134 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7135 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7136 }
7137 } else {
7138 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7139 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7140 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7141 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7142 }
7143 }
7144
7145 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7146 {
7147 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7148
7149 if (m_n == M1_N1) {
7150 dp_m_n = &crtc->config->dp_m_n;
7151 dp_m2_n2 = &crtc->config->dp_m2_n2;
7152 } else if (m_n == M2_N2) {
7153
7154 /*
7155 * M2_N2 registers are not supported. Hence m2_n2 divider value
7156 * needs to be programmed into M1_N1.
7157 */
7158 dp_m_n = &crtc->config->dp_m2_n2;
7159 } else {
7160 DRM_ERROR("Unsupported divider value\n");
7161 return;
7162 }
7163
7164 if (crtc->config->has_pch_encoder)
7165 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7166 else
7167 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7168 }
7169
7170 static void vlv_compute_dpll(struct intel_crtc *crtc,
7171 struct intel_crtc_state *pipe_config)
7172 {
7173 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV |
7174 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7175 DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV;
7176 if (crtc->pipe != PIPE_A)
7177 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7178
7179 pipe_config->dpll_hw_state.dpll_md =
7180 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7181 }
7182
7183 static void chv_compute_dpll(struct intel_crtc *crtc,
7184 struct intel_crtc_state *pipe_config)
7185 {
7186 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7187 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7188 DPLL_VCO_ENABLE;
7189 if (crtc->pipe != PIPE_A)
7190 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7191
7192 pipe_config->dpll_hw_state.dpll_md =
7193 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7194 }
7195
7196 static void vlv_prepare_pll(struct intel_crtc *crtc,
7197 const struct intel_crtc_state *pipe_config)
7198 {
7199 struct drm_device *dev = crtc->base.dev;
7200 struct drm_i915_private *dev_priv = dev->dev_private;
7201 int pipe = crtc->pipe;
7202 u32 mdiv;
7203 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7204 u32 coreclk, reg_val;
7205
7206 mutex_lock(&dev_priv->sb_lock);
7207
7208 bestn = pipe_config->dpll.n;
7209 bestm1 = pipe_config->dpll.m1;
7210 bestm2 = pipe_config->dpll.m2;
7211 bestp1 = pipe_config->dpll.p1;
7212 bestp2 = pipe_config->dpll.p2;
7213
7214 /* See eDP HDMI DPIO driver vbios notes doc */
7215
7216 /* PLL B needs special handling */
7217 if (pipe == PIPE_B)
7218 vlv_pllb_recal_opamp(dev_priv, pipe);
7219
7220 /* Set up Tx target for periodic Rcomp update */
7221 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7222
7223 /* Disable target IRef on PLL */
7224 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7225 reg_val &= 0x00ffffff;
7226 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7227
7228 /* Disable fast lock */
7229 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7230
7231 /* Set idtafcrecal before PLL is enabled */
7232 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7233 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7234 mdiv |= ((bestn << DPIO_N_SHIFT));
7235 mdiv |= (1 << DPIO_K_SHIFT);
7236
7237 /*
7238 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7239 * but we don't support that).
7240 * Note: don't use the DAC post divider as it seems unstable.
7241 */
7242 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7243 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7244
7245 mdiv |= DPIO_ENABLE_CALIBRATION;
7246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7247
7248 /* Set HBR and RBR LPF coefficients */
7249 if (pipe_config->port_clock == 162000 ||
7250 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7251 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7252 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7253 0x009f0003);
7254 else
7255 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7256 0x00d0000f);
7257
7258 if (pipe_config->has_dp_encoder) {
7259 /* Use SSC source */
7260 if (pipe == PIPE_A)
7261 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7262 0x0df40000);
7263 else
7264 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7265 0x0df70000);
7266 } else { /* HDMI or VGA */
7267 /* Use bend source */
7268 if (pipe == PIPE_A)
7269 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7270 0x0df70000);
7271 else
7272 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7273 0x0df40000);
7274 }
7275
7276 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7277 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7278 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7279 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7280 coreclk |= 0x01000000;
7281 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7282
7283 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7284 mutex_unlock(&dev_priv->sb_lock);
7285 }
7286
7287 static void chv_prepare_pll(struct intel_crtc *crtc,
7288 const struct intel_crtc_state *pipe_config)
7289 {
7290 struct drm_device *dev = crtc->base.dev;
7291 struct drm_i915_private *dev_priv = dev->dev_private;
7292 int pipe = crtc->pipe;
7293 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7294 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7295 u32 loopfilter, tribuf_calcntr;
7296 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7297 u32 dpio_val;
7298 int vco;
7299
7300 bestn = pipe_config->dpll.n;
7301 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7302 bestm1 = pipe_config->dpll.m1;
7303 bestm2 = pipe_config->dpll.m2 >> 22;
7304 bestp1 = pipe_config->dpll.p1;
7305 bestp2 = pipe_config->dpll.p2;
7306 vco = pipe_config->dpll.vco;
7307 dpio_val = 0;
7308 loopfilter = 0;
7309
7310 /*
7311 * Enable Refclk and SSC
7312 */
7313 I915_WRITE(dpll_reg,
7314 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7315
7316 mutex_lock(&dev_priv->sb_lock);
7317
7318 /* p1 and p2 divider */
7319 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7320 5 << DPIO_CHV_S1_DIV_SHIFT |
7321 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7322 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7323 1 << DPIO_CHV_K_DIV_SHIFT);
7324
7325 /* Feedback post-divider - m2 */
7326 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7327
7328 /* Feedback refclk divider - n and m1 */
7329 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7330 DPIO_CHV_M1_DIV_BY_2 |
7331 1 << DPIO_CHV_N_DIV_SHIFT);
7332
7333 /* M2 fraction division */
7334 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7335
7336 /* M2 fraction division enable */
7337 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7338 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7339 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7340 if (bestm2_frac)
7341 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7342 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7343
7344 /* Program digital lock detect threshold */
7345 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7346 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7347 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7348 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7349 if (!bestm2_frac)
7350 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7351 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7352
7353 /* Loop filter */
7354 if (vco == 5400000) {
7355 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7356 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7357 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7358 tribuf_calcntr = 0x9;
7359 } else if (vco <= 6200000) {
7360 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7361 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7362 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7363 tribuf_calcntr = 0x9;
7364 } else if (vco <= 6480000) {
7365 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7366 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7367 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7368 tribuf_calcntr = 0x8;
7369 } else {
7370 /* Not supported. Apply the same limits as in the max case */
7371 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7372 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7373 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7374 tribuf_calcntr = 0;
7375 }
7376 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7377
7378 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7379 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7380 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7381 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7382
7383 /* AFC Recal */
7384 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7385 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7386 DPIO_AFC_RECAL);
7387
7388 mutex_unlock(&dev_priv->sb_lock);
7389 }
7390
7391 /**
7392 * vlv_force_pll_on - forcibly enable just the PLL
7393 * @dev_priv: i915 private structure
7394 * @pipe: pipe PLL to enable
7395 * @dpll: PLL configuration
7396 *
7397 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7398 * in cases where we need the PLL enabled even when @pipe is not going to
7399 * be enabled.
7400 */
7401 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7402 const struct dpll *dpll)
7403 {
7404 struct intel_crtc *crtc =
7405 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7406 struct intel_crtc_state *pipe_config;
7407
7408 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7409 if (!pipe_config)
7410 return -ENOMEM;
7411
7412 pipe_config->base.crtc = &crtc->base;
7413 pipe_config->pixel_multiplier = 1;
7414 pipe_config->dpll = *dpll;
7415
7416 if (IS_CHERRYVIEW(dev)) {
7417 chv_compute_dpll(crtc, pipe_config);
7418 chv_prepare_pll(crtc, pipe_config);
7419 chv_enable_pll(crtc, pipe_config);
7420 } else {
7421 vlv_compute_dpll(crtc, pipe_config);
7422 vlv_prepare_pll(crtc, pipe_config);
7423 vlv_enable_pll(crtc, pipe_config);
7424 }
7425
7426 kfree(pipe_config);
7427
7428 return 0;
7429 }
7430
7431 /**
7432 * vlv_force_pll_off - forcibly disable just the PLL
7433 * @dev_priv: i915 private structure
7434 * @pipe: pipe PLL to disable
7435 *
7436 * Disable the PLL for @pipe. To be used in cases where we need
7437 * the PLL enabled even when @pipe is not going to be enabled.
7438 */
7439 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7440 {
7441 if (IS_CHERRYVIEW(dev))
7442 chv_disable_pll(to_i915(dev), pipe);
7443 else
7444 vlv_disable_pll(to_i915(dev), pipe);
7445 }
7446
7447 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7448 struct intel_crtc_state *crtc_state,
7449 intel_clock_t *reduced_clock)
7450 {
7451 struct drm_device *dev = crtc->base.dev;
7452 struct drm_i915_private *dev_priv = dev->dev_private;
7453 u32 dpll;
7454 bool is_sdvo;
7455 struct dpll *clock = &crtc_state->dpll;
7456
7457 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7458
7459 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7460 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7461
7462 dpll = DPLL_VGA_MODE_DIS;
7463
7464 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7465 dpll |= DPLLB_MODE_LVDS;
7466 else
7467 dpll |= DPLLB_MODE_DAC_SERIAL;
7468
7469 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7470 dpll |= (crtc_state->pixel_multiplier - 1)
7471 << SDVO_MULTIPLIER_SHIFT_HIRES;
7472 }
7473
7474 if (is_sdvo)
7475 dpll |= DPLL_SDVO_HIGH_SPEED;
7476
7477 if (crtc_state->has_dp_encoder)
7478 dpll |= DPLL_SDVO_HIGH_SPEED;
7479
7480 /* compute bitmask from p1 value */
7481 if (IS_PINEVIEW(dev))
7482 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7483 else {
7484 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7485 if (IS_G4X(dev) && reduced_clock)
7486 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7487 }
7488 switch (clock->p2) {
7489 case 5:
7490 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7491 break;
7492 case 7:
7493 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7494 break;
7495 case 10:
7496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7497 break;
7498 case 14:
7499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7500 break;
7501 }
7502 if (INTEL_INFO(dev)->gen >= 4)
7503 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7504
7505 if (crtc_state->sdvo_tv_clock)
7506 dpll |= PLL_REF_INPUT_TVCLKINBC;
7507 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7508 intel_panel_use_ssc(dev_priv))
7509 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7510 else
7511 dpll |= PLL_REF_INPUT_DREFCLK;
7512
7513 dpll |= DPLL_VCO_ENABLE;
7514 crtc_state->dpll_hw_state.dpll = dpll;
7515
7516 if (INTEL_INFO(dev)->gen >= 4) {
7517 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7518 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7519 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7520 }
7521 }
7522
7523 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7524 struct intel_crtc_state *crtc_state,
7525 intel_clock_t *reduced_clock)
7526 {
7527 struct drm_device *dev = crtc->base.dev;
7528 struct drm_i915_private *dev_priv = dev->dev_private;
7529 u32 dpll;
7530 struct dpll *clock = &crtc_state->dpll;
7531
7532 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7533
7534 dpll = DPLL_VGA_MODE_DIS;
7535
7536 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7537 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7538 } else {
7539 if (clock->p1 == 2)
7540 dpll |= PLL_P1_DIVIDE_BY_TWO;
7541 else
7542 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7543 if (clock->p2 == 4)
7544 dpll |= PLL_P2_DIVIDE_BY_4;
7545 }
7546
7547 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7548 dpll |= DPLL_DVO_2X_MODE;
7549
7550 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7551 intel_panel_use_ssc(dev_priv))
7552 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7553 else
7554 dpll |= PLL_REF_INPUT_DREFCLK;
7555
7556 dpll |= DPLL_VCO_ENABLE;
7557 crtc_state->dpll_hw_state.dpll = dpll;
7558 }
7559
7560 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7561 {
7562 struct drm_device *dev = intel_crtc->base.dev;
7563 struct drm_i915_private *dev_priv = dev->dev_private;
7564 enum pipe pipe = intel_crtc->pipe;
7565 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7566 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7567 uint32_t crtc_vtotal, crtc_vblank_end;
7568 int vsyncshift = 0;
7569
7570 /* We need to be careful not to changed the adjusted mode, for otherwise
7571 * the hw state checker will get angry at the mismatch. */
7572 crtc_vtotal = adjusted_mode->crtc_vtotal;
7573 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7574
7575 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7576 /* the chip adds 2 halflines automatically */
7577 crtc_vtotal -= 1;
7578 crtc_vblank_end -= 1;
7579
7580 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7581 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7582 else
7583 vsyncshift = adjusted_mode->crtc_hsync_start -
7584 adjusted_mode->crtc_htotal / 2;
7585 if (vsyncshift < 0)
7586 vsyncshift += adjusted_mode->crtc_htotal;
7587 }
7588
7589 if (INTEL_INFO(dev)->gen > 3)
7590 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7591
7592 I915_WRITE(HTOTAL(cpu_transcoder),
7593 (adjusted_mode->crtc_hdisplay - 1) |
7594 ((adjusted_mode->crtc_htotal - 1) << 16));
7595 I915_WRITE(HBLANK(cpu_transcoder),
7596 (adjusted_mode->crtc_hblank_start - 1) |
7597 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7598 I915_WRITE(HSYNC(cpu_transcoder),
7599 (adjusted_mode->crtc_hsync_start - 1) |
7600 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7601
7602 I915_WRITE(VTOTAL(cpu_transcoder),
7603 (adjusted_mode->crtc_vdisplay - 1) |
7604 ((crtc_vtotal - 1) << 16));
7605 I915_WRITE(VBLANK(cpu_transcoder),
7606 (adjusted_mode->crtc_vblank_start - 1) |
7607 ((crtc_vblank_end - 1) << 16));
7608 I915_WRITE(VSYNC(cpu_transcoder),
7609 (adjusted_mode->crtc_vsync_start - 1) |
7610 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7611
7612 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7613 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7614 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7615 * bits. */
7616 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7617 (pipe == PIPE_B || pipe == PIPE_C))
7618 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7619
7620 }
7621
7622 static void intel_set_pipe_src_size(struct intel_crtc *intel_crtc)
7623 {
7624 struct drm_device *dev = intel_crtc->base.dev;
7625 struct drm_i915_private *dev_priv = dev->dev_private;
7626 enum pipe pipe = intel_crtc->pipe;
7627
7628 /* pipesrc controls the size that is scaled from, which should
7629 * always be the user's requested size.
7630 */
7631 I915_WRITE(PIPESRC(pipe),
7632 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7633 (intel_crtc->config->pipe_src_h - 1));
7634 }
7635
7636 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7637 struct intel_crtc_state *pipe_config)
7638 {
7639 struct drm_device *dev = crtc->base.dev;
7640 struct drm_i915_private *dev_priv = dev->dev_private;
7641 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7642 uint32_t tmp;
7643
7644 tmp = I915_READ(HTOTAL(cpu_transcoder));
7645 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7646 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7647 tmp = I915_READ(HBLANK(cpu_transcoder));
7648 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7649 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7650 tmp = I915_READ(HSYNC(cpu_transcoder));
7651 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7652 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7653
7654 tmp = I915_READ(VTOTAL(cpu_transcoder));
7655 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7656 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7657 tmp = I915_READ(VBLANK(cpu_transcoder));
7658 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7659 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7660 tmp = I915_READ(VSYNC(cpu_transcoder));
7661 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7662 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7663
7664 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7665 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7666 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7667 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7668 }
7669 }
7670
7671 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
7672 struct intel_crtc_state *pipe_config)
7673 {
7674 struct drm_device *dev = crtc->base.dev;
7675 struct drm_i915_private *dev_priv = dev->dev_private;
7676 u32 tmp;
7677
7678 tmp = I915_READ(PIPESRC(crtc->pipe));
7679 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7680 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7681
7682 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7683 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7684 }
7685
7686 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7687 struct intel_crtc_state *pipe_config)
7688 {
7689 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7690 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7691 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7692 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7693
7694 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7695 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7696 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7697 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7698
7699 mode->flags = pipe_config->base.adjusted_mode.flags;
7700 mode->type = DRM_MODE_TYPE_DRIVER;
7701
7702 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7703 mode->flags |= pipe_config->base.adjusted_mode.flags;
7704
7705 mode->hsync = drm_mode_hsync(mode);
7706 mode->vrefresh = drm_mode_vrefresh(mode);
7707 drm_mode_set_name(mode);
7708 }
7709
7710 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7711 {
7712 struct drm_device *dev = intel_crtc->base.dev;
7713 struct drm_i915_private *dev_priv = dev->dev_private;
7714 uint32_t pipeconf;
7715
7716 pipeconf = 0;
7717
7718 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7719 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7720 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7721
7722 if (intel_crtc->config->double_wide)
7723 pipeconf |= PIPECONF_DOUBLE_WIDE;
7724
7725 /* only g4x and later have fancy bpc/dither controls */
7726 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7727 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7728 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7729 pipeconf |= PIPECONF_DITHER_EN |
7730 PIPECONF_DITHER_TYPE_SP;
7731
7732 switch (intel_crtc->config->pipe_bpp) {
7733 case 18:
7734 pipeconf |= PIPECONF_6BPC;
7735 break;
7736 case 24:
7737 pipeconf |= PIPECONF_8BPC;
7738 break;
7739 case 30:
7740 pipeconf |= PIPECONF_10BPC;
7741 break;
7742 default:
7743 /* Case prevented by intel_choose_pipe_bpp_dither. */
7744 BUG();
7745 }
7746 }
7747
7748 if (HAS_PIPE_CXSR(dev)) {
7749 if (intel_crtc->lowfreq_avail) {
7750 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7751 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7752 } else {
7753 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7754 }
7755 }
7756
7757 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7758 if (INTEL_INFO(dev)->gen < 4 ||
7759 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7760 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7761 else
7762 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7763 } else
7764 pipeconf |= PIPECONF_PROGRESSIVE;
7765
7766 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7767 intel_crtc->config->limited_color_range)
7768 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7769
7770 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7771 POSTING_READ(PIPECONF(intel_crtc->pipe));
7772 }
7773
7774 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc,
7775 struct intel_crtc_state *crtc_state)
7776 {
7777 struct drm_device *dev = crtc->base.dev;
7778 struct drm_i915_private *dev_priv = dev->dev_private;
7779 const intel_limit_t *limit;
7780 int refclk = 48000;
7781
7782 memset(&crtc_state->dpll_hw_state, 0,
7783 sizeof(crtc_state->dpll_hw_state));
7784
7785 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7786 if (intel_panel_use_ssc(dev_priv)) {
7787 refclk = dev_priv->vbt.lvds_ssc_freq;
7788 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7789 }
7790
7791 limit = &intel_limits_i8xx_lvds;
7792 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO)) {
7793 limit = &intel_limits_i8xx_dvo;
7794 } else {
7795 limit = &intel_limits_i8xx_dac;
7796 }
7797
7798 if (!crtc_state->clock_set &&
7799 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7800 refclk, NULL, &crtc_state->dpll)) {
7801 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7802 return -EINVAL;
7803 }
7804
7805 i8xx_compute_dpll(crtc, crtc_state, NULL);
7806
7807 return 0;
7808 }
7809
7810 static int g4x_crtc_compute_clock(struct intel_crtc *crtc,
7811 struct intel_crtc_state *crtc_state)
7812 {
7813 struct drm_device *dev = crtc->base.dev;
7814 struct drm_i915_private *dev_priv = dev->dev_private;
7815 const intel_limit_t *limit;
7816 int refclk = 96000;
7817
7818 memset(&crtc_state->dpll_hw_state, 0,
7819 sizeof(crtc_state->dpll_hw_state));
7820
7821 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7822 if (intel_panel_use_ssc(dev_priv)) {
7823 refclk = dev_priv->vbt.lvds_ssc_freq;
7824 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7825 }
7826
7827 if (intel_is_dual_link_lvds(dev))
7828 limit = &intel_limits_g4x_dual_channel_lvds;
7829 else
7830 limit = &intel_limits_g4x_single_channel_lvds;
7831 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
7832 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
7833 limit = &intel_limits_g4x_hdmi;
7834 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
7835 limit = &intel_limits_g4x_sdvo;
7836 } else {
7837 /* The option is for other outputs */
7838 limit = &intel_limits_i9xx_sdvo;
7839 }
7840
7841 if (!crtc_state->clock_set &&
7842 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7843 refclk, NULL, &crtc_state->dpll)) {
7844 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7845 return -EINVAL;
7846 }
7847
7848 i9xx_compute_dpll(crtc, crtc_state, NULL);
7849
7850 return 0;
7851 }
7852
7853 static int pnv_crtc_compute_clock(struct intel_crtc *crtc,
7854 struct intel_crtc_state *crtc_state)
7855 {
7856 struct drm_device *dev = crtc->base.dev;
7857 struct drm_i915_private *dev_priv = dev->dev_private;
7858 const intel_limit_t *limit;
7859 int refclk = 96000;
7860
7861 memset(&crtc_state->dpll_hw_state, 0,
7862 sizeof(crtc_state->dpll_hw_state));
7863
7864 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7865 if (intel_panel_use_ssc(dev_priv)) {
7866 refclk = dev_priv->vbt.lvds_ssc_freq;
7867 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7868 }
7869
7870 limit = &intel_limits_pineview_lvds;
7871 } else {
7872 limit = &intel_limits_pineview_sdvo;
7873 }
7874
7875 if (!crtc_state->clock_set &&
7876 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7877 refclk, NULL, &crtc_state->dpll)) {
7878 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7879 return -EINVAL;
7880 }
7881
7882 i9xx_compute_dpll(crtc, crtc_state, NULL);
7883
7884 return 0;
7885 }
7886
7887 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7888 struct intel_crtc_state *crtc_state)
7889 {
7890 struct drm_device *dev = crtc->base.dev;
7891 struct drm_i915_private *dev_priv = dev->dev_private;
7892 const intel_limit_t *limit;
7893 int refclk = 96000;
7894
7895 memset(&crtc_state->dpll_hw_state, 0,
7896 sizeof(crtc_state->dpll_hw_state));
7897
7898 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7899 if (intel_panel_use_ssc(dev_priv)) {
7900 refclk = dev_priv->vbt.lvds_ssc_freq;
7901 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7902 }
7903
7904 limit = &intel_limits_i9xx_lvds;
7905 } else {
7906 limit = &intel_limits_i9xx_sdvo;
7907 }
7908
7909 if (!crtc_state->clock_set &&
7910 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7911 refclk, NULL, &crtc_state->dpll)) {
7912 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7913 return -EINVAL;
7914 }
7915
7916 i9xx_compute_dpll(crtc, crtc_state, NULL);
7917
7918 return 0;
7919 }
7920
7921 static int chv_crtc_compute_clock(struct intel_crtc *crtc,
7922 struct intel_crtc_state *crtc_state)
7923 {
7924 int refclk = 100000;
7925 const intel_limit_t *limit = &intel_limits_chv;
7926
7927 memset(&crtc_state->dpll_hw_state, 0,
7928 sizeof(crtc_state->dpll_hw_state));
7929
7930 if (crtc_state->has_dsi_encoder)
7931 return 0;
7932
7933 if (!crtc_state->clock_set &&
7934 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7935 refclk, NULL, &crtc_state->dpll)) {
7936 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7937 return -EINVAL;
7938 }
7939
7940 chv_compute_dpll(crtc, crtc_state);
7941
7942 return 0;
7943 }
7944
7945 static int vlv_crtc_compute_clock(struct intel_crtc *crtc,
7946 struct intel_crtc_state *crtc_state)
7947 {
7948 int refclk = 100000;
7949 const intel_limit_t *limit = &intel_limits_vlv;
7950
7951 memset(&crtc_state->dpll_hw_state, 0,
7952 sizeof(crtc_state->dpll_hw_state));
7953
7954 if (crtc_state->has_dsi_encoder)
7955 return 0;
7956
7957 if (!crtc_state->clock_set &&
7958 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
7959 refclk, NULL, &crtc_state->dpll)) {
7960 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7961 return -EINVAL;
7962 }
7963
7964 vlv_compute_dpll(crtc, crtc_state);
7965
7966 return 0;
7967 }
7968
7969 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7970 struct intel_crtc_state *pipe_config)
7971 {
7972 struct drm_device *dev = crtc->base.dev;
7973 struct drm_i915_private *dev_priv = dev->dev_private;
7974 uint32_t tmp;
7975
7976 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7977 return;
7978
7979 tmp = I915_READ(PFIT_CONTROL);
7980 if (!(tmp & PFIT_ENABLE))
7981 return;
7982
7983 /* Check whether the pfit is attached to our pipe. */
7984 if (INTEL_INFO(dev)->gen < 4) {
7985 if (crtc->pipe != PIPE_B)
7986 return;
7987 } else {
7988 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7989 return;
7990 }
7991
7992 pipe_config->gmch_pfit.control = tmp;
7993 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7994 if (INTEL_INFO(dev)->gen < 5)
7995 pipe_config->gmch_pfit.lvds_border_bits =
7996 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7997 }
7998
7999 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8000 struct intel_crtc_state *pipe_config)
8001 {
8002 struct drm_device *dev = crtc->base.dev;
8003 struct drm_i915_private *dev_priv = dev->dev_private;
8004 int pipe = pipe_config->cpu_transcoder;
8005 intel_clock_t clock;
8006 u32 mdiv;
8007 int refclk = 100000;
8008
8009 /* In case of MIPI DPLL will not even be used */
8010 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8011 return;
8012
8013 mutex_lock(&dev_priv->sb_lock);
8014 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8015 mutex_unlock(&dev_priv->sb_lock);
8016
8017 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8018 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8019 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8020 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8021 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8022
8023 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8024 }
8025
8026 static void
8027 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8028 struct intel_initial_plane_config *plane_config)
8029 {
8030 struct drm_device *dev = crtc->base.dev;
8031 struct drm_i915_private *dev_priv = dev->dev_private;
8032 u32 val, base, offset;
8033 int pipe = crtc->pipe, plane = crtc->plane;
8034 int fourcc, pixel_format;
8035 unsigned int aligned_height;
8036 struct drm_framebuffer *fb;
8037 struct intel_framebuffer *intel_fb;
8038
8039 val = I915_READ(DSPCNTR(plane));
8040 if (!(val & DISPLAY_PLANE_ENABLE))
8041 return;
8042
8043 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8044 if (!intel_fb) {
8045 DRM_DEBUG_KMS("failed to alloc fb\n");
8046 return;
8047 }
8048
8049 fb = &intel_fb->base;
8050
8051 if (INTEL_INFO(dev)->gen >= 4) {
8052 if (val & DISPPLANE_TILED) {
8053 plane_config->tiling = I915_TILING_X;
8054 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8055 }
8056 }
8057
8058 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8059 fourcc = i9xx_format_to_fourcc(pixel_format);
8060 fb->pixel_format = fourcc;
8061 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8062
8063 if (INTEL_INFO(dev)->gen >= 4) {
8064 if (plane_config->tiling)
8065 offset = I915_READ(DSPTILEOFF(plane));
8066 else
8067 offset = I915_READ(DSPLINOFF(plane));
8068 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8069 } else {
8070 base = I915_READ(DSPADDR(plane));
8071 }
8072 plane_config->base = base;
8073
8074 val = I915_READ(PIPESRC(pipe));
8075 fb->width = ((val >> 16) & 0xfff) + 1;
8076 fb->height = ((val >> 0) & 0xfff) + 1;
8077
8078 val = I915_READ(DSPSTRIDE(pipe));
8079 fb->pitches[0] = val & 0xffffffc0;
8080
8081 aligned_height = intel_fb_align_height(dev, fb->height,
8082 fb->pixel_format,
8083 fb->modifier[0]);
8084
8085 plane_config->size = fb->pitches[0] * aligned_height;
8086
8087 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8088 pipe_name(pipe), plane, fb->width, fb->height,
8089 fb->bits_per_pixel, base, fb->pitches[0],
8090 plane_config->size);
8091
8092 plane_config->fb = intel_fb;
8093 }
8094
8095 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8096 struct intel_crtc_state *pipe_config)
8097 {
8098 struct drm_device *dev = crtc->base.dev;
8099 struct drm_i915_private *dev_priv = dev->dev_private;
8100 int pipe = pipe_config->cpu_transcoder;
8101 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8102 intel_clock_t clock;
8103 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8104 int refclk = 100000;
8105
8106 mutex_lock(&dev_priv->sb_lock);
8107 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8108 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8109 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8110 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8111 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8112 mutex_unlock(&dev_priv->sb_lock);
8113
8114 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8115 clock.m2 = (pll_dw0 & 0xff) << 22;
8116 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8117 clock.m2 |= pll_dw2 & 0x3fffff;
8118 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8119 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8120 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8121
8122 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8123 }
8124
8125 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8126 struct intel_crtc_state *pipe_config)
8127 {
8128 struct drm_device *dev = crtc->base.dev;
8129 struct drm_i915_private *dev_priv = dev->dev_private;
8130 enum intel_display_power_domain power_domain;
8131 uint32_t tmp;
8132 bool ret;
8133
8134 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
8135 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
8136 return false;
8137
8138 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8139 pipe_config->shared_dpll = NULL;
8140
8141 ret = false;
8142
8143 tmp = I915_READ(PIPECONF(crtc->pipe));
8144 if (!(tmp & PIPECONF_ENABLE))
8145 goto out;
8146
8147 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8148 switch (tmp & PIPECONF_BPC_MASK) {
8149 case PIPECONF_6BPC:
8150 pipe_config->pipe_bpp = 18;
8151 break;
8152 case PIPECONF_8BPC:
8153 pipe_config->pipe_bpp = 24;
8154 break;
8155 case PIPECONF_10BPC:
8156 pipe_config->pipe_bpp = 30;
8157 break;
8158 default:
8159 break;
8160 }
8161 }
8162
8163 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8164 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8165 pipe_config->limited_color_range = true;
8166
8167 if (INTEL_INFO(dev)->gen < 4)
8168 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8169
8170 intel_get_pipe_timings(crtc, pipe_config);
8171 intel_get_pipe_src_size(crtc, pipe_config);
8172
8173 i9xx_get_pfit_config(crtc, pipe_config);
8174
8175 if (INTEL_INFO(dev)->gen >= 4) {
8176 /* No way to read it out on pipes B and C */
8177 if (IS_CHERRYVIEW(dev) && crtc->pipe != PIPE_A)
8178 tmp = dev_priv->chv_dpll_md[crtc->pipe];
8179 else
8180 tmp = I915_READ(DPLL_MD(crtc->pipe));
8181 pipe_config->pixel_multiplier =
8182 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8183 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8184 pipe_config->dpll_hw_state.dpll_md = tmp;
8185 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8186 tmp = I915_READ(DPLL(crtc->pipe));
8187 pipe_config->pixel_multiplier =
8188 ((tmp & SDVO_MULTIPLIER_MASK)
8189 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8190 } else {
8191 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8192 * port and will be fixed up in the encoder->get_config
8193 * function. */
8194 pipe_config->pixel_multiplier = 1;
8195 }
8196 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8197 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8198 /*
8199 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8200 * on 830. Filter it out here so that we don't
8201 * report errors due to that.
8202 */
8203 if (IS_I830(dev))
8204 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8205
8206 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8207 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8208 } else {
8209 /* Mask out read-only status bits. */
8210 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8211 DPLL_PORTC_READY_MASK |
8212 DPLL_PORTB_READY_MASK);
8213 }
8214
8215 if (IS_CHERRYVIEW(dev))
8216 chv_crtc_clock_get(crtc, pipe_config);
8217 else if (IS_VALLEYVIEW(dev))
8218 vlv_crtc_clock_get(crtc, pipe_config);
8219 else
8220 i9xx_crtc_clock_get(crtc, pipe_config);
8221
8222 /*
8223 * Normally the dotclock is filled in by the encoder .get_config()
8224 * but in case the pipe is enabled w/o any ports we need a sane
8225 * default.
8226 */
8227 pipe_config->base.adjusted_mode.crtc_clock =
8228 pipe_config->port_clock / pipe_config->pixel_multiplier;
8229
8230 ret = true;
8231
8232 out:
8233 intel_display_power_put(dev_priv, power_domain);
8234
8235 return ret;
8236 }
8237
8238 static void ironlake_init_pch_refclk(struct drm_device *dev)
8239 {
8240 struct drm_i915_private *dev_priv = dev->dev_private;
8241 struct intel_encoder *encoder;
8242 u32 val, final;
8243 bool has_lvds = false;
8244 bool has_cpu_edp = false;
8245 bool has_panel = false;
8246 bool has_ck505 = false;
8247 bool can_ssc = false;
8248
8249 /* We need to take the global config into account */
8250 for_each_intel_encoder(dev, encoder) {
8251 switch (encoder->type) {
8252 case INTEL_OUTPUT_LVDS:
8253 has_panel = true;
8254 has_lvds = true;
8255 break;
8256 case INTEL_OUTPUT_EDP:
8257 has_panel = true;
8258 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8259 has_cpu_edp = true;
8260 break;
8261 default:
8262 break;
8263 }
8264 }
8265
8266 if (HAS_PCH_IBX(dev)) {
8267 has_ck505 = dev_priv->vbt.display_clock_mode;
8268 can_ssc = has_ck505;
8269 } else {
8270 has_ck505 = false;
8271 can_ssc = true;
8272 }
8273
8274 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8275 has_panel, has_lvds, has_ck505);
8276
8277 /* Ironlake: try to setup display ref clock before DPLL
8278 * enabling. This is only under driver's control after
8279 * PCH B stepping, previous chipset stepping should be
8280 * ignoring this setting.
8281 */
8282 val = I915_READ(PCH_DREF_CONTROL);
8283
8284 /* As we must carefully and slowly disable/enable each source in turn,
8285 * compute the final state we want first and check if we need to
8286 * make any changes at all.
8287 */
8288 final = val;
8289 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8290 if (has_ck505)
8291 final |= DREF_NONSPREAD_CK505_ENABLE;
8292 else
8293 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8294
8295 final &= ~DREF_SSC_SOURCE_MASK;
8296 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8297 final &= ~DREF_SSC1_ENABLE;
8298
8299 if (has_panel) {
8300 final |= DREF_SSC_SOURCE_ENABLE;
8301
8302 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8303 final |= DREF_SSC1_ENABLE;
8304
8305 if (has_cpu_edp) {
8306 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8307 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8308 else
8309 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8310 } else
8311 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8312 } else {
8313 final |= DREF_SSC_SOURCE_DISABLE;
8314 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8315 }
8316
8317 if (final == val)
8318 return;
8319
8320 /* Always enable nonspread source */
8321 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8322
8323 if (has_ck505)
8324 val |= DREF_NONSPREAD_CK505_ENABLE;
8325 else
8326 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8327
8328 if (has_panel) {
8329 val &= ~DREF_SSC_SOURCE_MASK;
8330 val |= DREF_SSC_SOURCE_ENABLE;
8331
8332 /* SSC must be turned on before enabling the CPU output */
8333 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8334 DRM_DEBUG_KMS("Using SSC on panel\n");
8335 val |= DREF_SSC1_ENABLE;
8336 } else
8337 val &= ~DREF_SSC1_ENABLE;
8338
8339 /* Get SSC going before enabling the outputs */
8340 I915_WRITE(PCH_DREF_CONTROL, val);
8341 POSTING_READ(PCH_DREF_CONTROL);
8342 udelay(200);
8343
8344 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8345
8346 /* Enable CPU source on CPU attached eDP */
8347 if (has_cpu_edp) {
8348 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8349 DRM_DEBUG_KMS("Using SSC on eDP\n");
8350 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8351 } else
8352 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8353 } else
8354 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8355
8356 I915_WRITE(PCH_DREF_CONTROL, val);
8357 POSTING_READ(PCH_DREF_CONTROL);
8358 udelay(200);
8359 } else {
8360 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8361
8362 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8363
8364 /* Turn off CPU output */
8365 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8366
8367 I915_WRITE(PCH_DREF_CONTROL, val);
8368 POSTING_READ(PCH_DREF_CONTROL);
8369 udelay(200);
8370
8371 /* Turn off the SSC source */
8372 val &= ~DREF_SSC_SOURCE_MASK;
8373 val |= DREF_SSC_SOURCE_DISABLE;
8374
8375 /* Turn off SSC1 */
8376 val &= ~DREF_SSC1_ENABLE;
8377
8378 I915_WRITE(PCH_DREF_CONTROL, val);
8379 POSTING_READ(PCH_DREF_CONTROL);
8380 udelay(200);
8381 }
8382
8383 BUG_ON(val != final);
8384 }
8385
8386 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8387 {
8388 uint32_t tmp;
8389
8390 tmp = I915_READ(SOUTH_CHICKEN2);
8391 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8392 I915_WRITE(SOUTH_CHICKEN2, tmp);
8393
8394 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8395 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8396 DRM_ERROR("FDI mPHY reset assert timeout\n");
8397
8398 tmp = I915_READ(SOUTH_CHICKEN2);
8399 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8400 I915_WRITE(SOUTH_CHICKEN2, tmp);
8401
8402 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8403 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8404 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8405 }
8406
8407 /* WaMPhyProgramming:hsw */
8408 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8409 {
8410 uint32_t tmp;
8411
8412 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8413 tmp &= ~(0xFF << 24);
8414 tmp |= (0x12 << 24);
8415 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8416
8417 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8418 tmp |= (1 << 11);
8419 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8420
8421 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8422 tmp |= (1 << 11);
8423 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8424
8425 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8426 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8427 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8428
8429 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8430 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8431 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8432
8433 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8434 tmp &= ~(7 << 13);
8435 tmp |= (5 << 13);
8436 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8437
8438 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8439 tmp &= ~(7 << 13);
8440 tmp |= (5 << 13);
8441 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8442
8443 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8444 tmp &= ~0xFF;
8445 tmp |= 0x1C;
8446 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8447
8448 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8449 tmp &= ~0xFF;
8450 tmp |= 0x1C;
8451 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8452
8453 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8454 tmp &= ~(0xFF << 16);
8455 tmp |= (0x1C << 16);
8456 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8457
8458 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8459 tmp &= ~(0xFF << 16);
8460 tmp |= (0x1C << 16);
8461 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8462
8463 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8464 tmp |= (1 << 27);
8465 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8466
8467 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8468 tmp |= (1 << 27);
8469 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8470
8471 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8472 tmp &= ~(0xF << 28);
8473 tmp |= (4 << 28);
8474 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8475
8476 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8477 tmp &= ~(0xF << 28);
8478 tmp |= (4 << 28);
8479 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8480 }
8481
8482 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8483 * Programming" based on the parameters passed:
8484 * - Sequence to enable CLKOUT_DP
8485 * - Sequence to enable CLKOUT_DP without spread
8486 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8487 */
8488 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8489 bool with_fdi)
8490 {
8491 struct drm_i915_private *dev_priv = dev->dev_private;
8492 uint32_t reg, tmp;
8493
8494 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8495 with_spread = true;
8496 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8497 with_fdi = false;
8498
8499 mutex_lock(&dev_priv->sb_lock);
8500
8501 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8502 tmp &= ~SBI_SSCCTL_DISABLE;
8503 tmp |= SBI_SSCCTL_PATHALT;
8504 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8505
8506 udelay(24);
8507
8508 if (with_spread) {
8509 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8510 tmp &= ~SBI_SSCCTL_PATHALT;
8511 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8512
8513 if (with_fdi) {
8514 lpt_reset_fdi_mphy(dev_priv);
8515 lpt_program_fdi_mphy(dev_priv);
8516 }
8517 }
8518
8519 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8520 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8521 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8522 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8523
8524 mutex_unlock(&dev_priv->sb_lock);
8525 }
8526
8527 /* Sequence to disable CLKOUT_DP */
8528 static void lpt_disable_clkout_dp(struct drm_device *dev)
8529 {
8530 struct drm_i915_private *dev_priv = dev->dev_private;
8531 uint32_t reg, tmp;
8532
8533 mutex_lock(&dev_priv->sb_lock);
8534
8535 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8536 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8537 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8538 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8539
8540 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8541 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8542 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8543 tmp |= SBI_SSCCTL_PATHALT;
8544 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8545 udelay(32);
8546 }
8547 tmp |= SBI_SSCCTL_DISABLE;
8548 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8549 }
8550
8551 mutex_unlock(&dev_priv->sb_lock);
8552 }
8553
8554 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8555
8556 static const uint16_t sscdivintphase[] = {
8557 [BEND_IDX( 50)] = 0x3B23,
8558 [BEND_IDX( 45)] = 0x3B23,
8559 [BEND_IDX( 40)] = 0x3C23,
8560 [BEND_IDX( 35)] = 0x3C23,
8561 [BEND_IDX( 30)] = 0x3D23,
8562 [BEND_IDX( 25)] = 0x3D23,
8563 [BEND_IDX( 20)] = 0x3E23,
8564 [BEND_IDX( 15)] = 0x3E23,
8565 [BEND_IDX( 10)] = 0x3F23,
8566 [BEND_IDX( 5)] = 0x3F23,
8567 [BEND_IDX( 0)] = 0x0025,
8568 [BEND_IDX( -5)] = 0x0025,
8569 [BEND_IDX(-10)] = 0x0125,
8570 [BEND_IDX(-15)] = 0x0125,
8571 [BEND_IDX(-20)] = 0x0225,
8572 [BEND_IDX(-25)] = 0x0225,
8573 [BEND_IDX(-30)] = 0x0325,
8574 [BEND_IDX(-35)] = 0x0325,
8575 [BEND_IDX(-40)] = 0x0425,
8576 [BEND_IDX(-45)] = 0x0425,
8577 [BEND_IDX(-50)] = 0x0525,
8578 };
8579
8580 /*
8581 * Bend CLKOUT_DP
8582 * steps -50 to 50 inclusive, in steps of 5
8583 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8584 * change in clock period = -(steps / 10) * 5.787 ps
8585 */
8586 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8587 {
8588 uint32_t tmp;
8589 int idx = BEND_IDX(steps);
8590
8591 if (WARN_ON(steps % 5 != 0))
8592 return;
8593
8594 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8595 return;
8596
8597 mutex_lock(&dev_priv->sb_lock);
8598
8599 if (steps % 10 != 0)
8600 tmp = 0xAAAAAAAB;
8601 else
8602 tmp = 0x00000000;
8603 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8604
8605 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8606 tmp &= 0xffff0000;
8607 tmp |= sscdivintphase[idx];
8608 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8609
8610 mutex_unlock(&dev_priv->sb_lock);
8611 }
8612
8613 #undef BEND_IDX
8614
8615 static void lpt_init_pch_refclk(struct drm_device *dev)
8616 {
8617 struct intel_encoder *encoder;
8618 bool has_vga = false;
8619
8620 for_each_intel_encoder(dev, encoder) {
8621 switch (encoder->type) {
8622 case INTEL_OUTPUT_ANALOG:
8623 has_vga = true;
8624 break;
8625 default:
8626 break;
8627 }
8628 }
8629
8630 if (has_vga) {
8631 lpt_bend_clkout_dp(to_i915(dev), 0);
8632 lpt_enable_clkout_dp(dev, true, true);
8633 } else {
8634 lpt_disable_clkout_dp(dev);
8635 }
8636 }
8637
8638 /*
8639 * Initialize reference clocks when the driver loads
8640 */
8641 void intel_init_pch_refclk(struct drm_device *dev)
8642 {
8643 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8644 ironlake_init_pch_refclk(dev);
8645 else if (HAS_PCH_LPT(dev))
8646 lpt_init_pch_refclk(dev);
8647 }
8648
8649 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8650 {
8651 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8653 int pipe = intel_crtc->pipe;
8654 uint32_t val;
8655
8656 val = 0;
8657
8658 switch (intel_crtc->config->pipe_bpp) {
8659 case 18:
8660 val |= PIPECONF_6BPC;
8661 break;
8662 case 24:
8663 val |= PIPECONF_8BPC;
8664 break;
8665 case 30:
8666 val |= PIPECONF_10BPC;
8667 break;
8668 case 36:
8669 val |= PIPECONF_12BPC;
8670 break;
8671 default:
8672 /* Case prevented by intel_choose_pipe_bpp_dither. */
8673 BUG();
8674 }
8675
8676 if (intel_crtc->config->dither)
8677 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8678
8679 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8680 val |= PIPECONF_INTERLACED_ILK;
8681 else
8682 val |= PIPECONF_PROGRESSIVE;
8683
8684 if (intel_crtc->config->limited_color_range)
8685 val |= PIPECONF_COLOR_RANGE_SELECT;
8686
8687 I915_WRITE(PIPECONF(pipe), val);
8688 POSTING_READ(PIPECONF(pipe));
8689 }
8690
8691 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8692 {
8693 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8695 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8696 u32 val = 0;
8697
8698 if (IS_HASWELL(dev_priv) && intel_crtc->config->dither)
8699 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8700
8701 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8702 val |= PIPECONF_INTERLACED_ILK;
8703 else
8704 val |= PIPECONF_PROGRESSIVE;
8705
8706 I915_WRITE(PIPECONF(cpu_transcoder), val);
8707 POSTING_READ(PIPECONF(cpu_transcoder));
8708 }
8709
8710 static void haswell_set_pipemisc(struct drm_crtc *crtc)
8711 {
8712 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8714
8715 if (IS_BROADWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 9) {
8716 u32 val = 0;
8717
8718 switch (intel_crtc->config->pipe_bpp) {
8719 case 18:
8720 val |= PIPEMISC_DITHER_6_BPC;
8721 break;
8722 case 24:
8723 val |= PIPEMISC_DITHER_8_BPC;
8724 break;
8725 case 30:
8726 val |= PIPEMISC_DITHER_10_BPC;
8727 break;
8728 case 36:
8729 val |= PIPEMISC_DITHER_12_BPC;
8730 break;
8731 default:
8732 /* Case prevented by pipe_config_set_bpp. */
8733 BUG();
8734 }
8735
8736 if (intel_crtc->config->dither)
8737 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8738
8739 I915_WRITE(PIPEMISC(intel_crtc->pipe), val);
8740 }
8741 }
8742
8743 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8744 {
8745 /*
8746 * Account for spread spectrum to avoid
8747 * oversubscribing the link. Max center spread
8748 * is 2.5%; use 5% for safety's sake.
8749 */
8750 u32 bps = target_clock * bpp * 21 / 20;
8751 return DIV_ROUND_UP(bps, link_bw * 8);
8752 }
8753
8754 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8755 {
8756 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8757 }
8758
8759 static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8760 struct intel_crtc_state *crtc_state,
8761 intel_clock_t *reduced_clock)
8762 {
8763 struct drm_crtc *crtc = &intel_crtc->base;
8764 struct drm_device *dev = crtc->dev;
8765 struct drm_i915_private *dev_priv = dev->dev_private;
8766 struct drm_atomic_state *state = crtc_state->base.state;
8767 struct drm_connector *connector;
8768 struct drm_connector_state *connector_state;
8769 struct intel_encoder *encoder;
8770 u32 dpll, fp, fp2;
8771 int factor, i;
8772 bool is_lvds = false, is_sdvo = false;
8773
8774 for_each_connector_in_state(state, connector, connector_state, i) {
8775 if (connector_state->crtc != crtc_state->base.crtc)
8776 continue;
8777
8778 encoder = to_intel_encoder(connector_state->best_encoder);
8779
8780 switch (encoder->type) {
8781 case INTEL_OUTPUT_LVDS:
8782 is_lvds = true;
8783 break;
8784 case INTEL_OUTPUT_SDVO:
8785 case INTEL_OUTPUT_HDMI:
8786 is_sdvo = true;
8787 break;
8788 default:
8789 break;
8790 }
8791 }
8792
8793 /* Enable autotuning of the PLL clock (if permissible) */
8794 factor = 21;
8795 if (is_lvds) {
8796 if ((intel_panel_use_ssc(dev_priv) &&
8797 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8798 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8799 factor = 25;
8800 } else if (crtc_state->sdvo_tv_clock)
8801 factor = 20;
8802
8803 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8804
8805 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8806 fp |= FP_CB_TUNE;
8807
8808 if (reduced_clock) {
8809 fp2 = i9xx_dpll_compute_fp(reduced_clock);
8810
8811 if (reduced_clock->m < factor * reduced_clock->n)
8812 fp2 |= FP_CB_TUNE;
8813 } else {
8814 fp2 = fp;
8815 }
8816
8817 dpll = 0;
8818
8819 if (is_lvds)
8820 dpll |= DPLLB_MODE_LVDS;
8821 else
8822 dpll |= DPLLB_MODE_DAC_SERIAL;
8823
8824 dpll |= (crtc_state->pixel_multiplier - 1)
8825 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8826
8827 if (is_sdvo)
8828 dpll |= DPLL_SDVO_HIGH_SPEED;
8829 if (crtc_state->has_dp_encoder)
8830 dpll |= DPLL_SDVO_HIGH_SPEED;
8831
8832 /* compute bitmask from p1 value */
8833 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8834 /* also FPA1 */
8835 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8836
8837 switch (crtc_state->dpll.p2) {
8838 case 5:
8839 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8840 break;
8841 case 7:
8842 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8843 break;
8844 case 10:
8845 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8846 break;
8847 case 14:
8848 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8849 break;
8850 }
8851
8852 if (is_lvds && intel_panel_use_ssc(dev_priv))
8853 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8854 else
8855 dpll |= PLL_REF_INPUT_DREFCLK;
8856
8857 dpll |= DPLL_VCO_ENABLE;
8858
8859 crtc_state->dpll_hw_state.dpll = dpll;
8860 crtc_state->dpll_hw_state.fp0 = fp;
8861 crtc_state->dpll_hw_state.fp1 = fp2;
8862 }
8863
8864 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8865 struct intel_crtc_state *crtc_state)
8866 {
8867 struct drm_device *dev = crtc->base.dev;
8868 struct drm_i915_private *dev_priv = dev->dev_private;
8869 intel_clock_t reduced_clock;
8870 bool has_reduced_clock = false;
8871 struct intel_shared_dpll *pll;
8872 const intel_limit_t *limit;
8873 int refclk = 120000;
8874
8875 memset(&crtc_state->dpll_hw_state, 0,
8876 sizeof(crtc_state->dpll_hw_state));
8877
8878 crtc->lowfreq_avail = false;
8879
8880 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8881 if (!crtc_state->has_pch_encoder)
8882 return 0;
8883
8884 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
8885 if (intel_panel_use_ssc(dev_priv)) {
8886 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8887 dev_priv->vbt.lvds_ssc_freq);
8888 refclk = dev_priv->vbt.lvds_ssc_freq;
8889 }
8890
8891 if (intel_is_dual_link_lvds(dev)) {
8892 if (refclk == 100000)
8893 limit = &intel_limits_ironlake_dual_lvds_100m;
8894 else
8895 limit = &intel_limits_ironlake_dual_lvds;
8896 } else {
8897 if (refclk == 100000)
8898 limit = &intel_limits_ironlake_single_lvds_100m;
8899 else
8900 limit = &intel_limits_ironlake_single_lvds;
8901 }
8902 } else {
8903 limit = &intel_limits_ironlake_dac;
8904 }
8905
8906 if (!crtc_state->clock_set &&
8907 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
8908 refclk, NULL, &crtc_state->dpll)) {
8909 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8910 return -EINVAL;
8911 }
8912
8913 ironlake_compute_dpll(crtc, crtc_state,
8914 has_reduced_clock ? &reduced_clock : NULL);
8915
8916 pll = intel_get_shared_dpll(crtc, crtc_state, NULL);
8917 if (pll == NULL) {
8918 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8919 pipe_name(crtc->pipe));
8920 return -EINVAL;
8921 }
8922
8923 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
8924 has_reduced_clock)
8925 crtc->lowfreq_avail = true;
8926
8927 return 0;
8928 }
8929
8930 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8931 struct intel_link_m_n *m_n)
8932 {
8933 struct drm_device *dev = crtc->base.dev;
8934 struct drm_i915_private *dev_priv = dev->dev_private;
8935 enum pipe pipe = crtc->pipe;
8936
8937 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8938 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8939 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8940 & ~TU_SIZE_MASK;
8941 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8942 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8943 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8944 }
8945
8946 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8947 enum transcoder transcoder,
8948 struct intel_link_m_n *m_n,
8949 struct intel_link_m_n *m2_n2)
8950 {
8951 struct drm_device *dev = crtc->base.dev;
8952 struct drm_i915_private *dev_priv = dev->dev_private;
8953 enum pipe pipe = crtc->pipe;
8954
8955 if (INTEL_INFO(dev)->gen >= 5) {
8956 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8957 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8958 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8959 & ~TU_SIZE_MASK;
8960 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8961 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8962 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8963 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8964 * gen < 8) and if DRRS is supported (to make sure the
8965 * registers are not unnecessarily read).
8966 */
8967 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8968 crtc->config->has_drrs) {
8969 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8970 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8971 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8972 & ~TU_SIZE_MASK;
8973 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8974 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8975 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8976 }
8977 } else {
8978 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8979 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8980 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8981 & ~TU_SIZE_MASK;
8982 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8983 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8984 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8985 }
8986 }
8987
8988 void intel_dp_get_m_n(struct intel_crtc *crtc,
8989 struct intel_crtc_state *pipe_config)
8990 {
8991 if (pipe_config->has_pch_encoder)
8992 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8993 else
8994 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8995 &pipe_config->dp_m_n,
8996 &pipe_config->dp_m2_n2);
8997 }
8998
8999 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9000 struct intel_crtc_state *pipe_config)
9001 {
9002 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9003 &pipe_config->fdi_m_n, NULL);
9004 }
9005
9006 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9007 struct intel_crtc_state *pipe_config)
9008 {
9009 struct drm_device *dev = crtc->base.dev;
9010 struct drm_i915_private *dev_priv = dev->dev_private;
9011 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9012 uint32_t ps_ctrl = 0;
9013 int id = -1;
9014 int i;
9015
9016 /* find scaler attached to this pipe */
9017 for (i = 0; i < crtc->num_scalers; i++) {
9018 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9019 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9020 id = i;
9021 pipe_config->pch_pfit.enabled = true;
9022 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9023 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9024 break;
9025 }
9026 }
9027
9028 scaler_state->scaler_id = id;
9029 if (id >= 0) {
9030 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9031 } else {
9032 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9033 }
9034 }
9035
9036 static void
9037 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9038 struct intel_initial_plane_config *plane_config)
9039 {
9040 struct drm_device *dev = crtc->base.dev;
9041 struct drm_i915_private *dev_priv = dev->dev_private;
9042 u32 val, base, offset, stride_mult, tiling;
9043 int pipe = crtc->pipe;
9044 int fourcc, pixel_format;
9045 unsigned int aligned_height;
9046 struct drm_framebuffer *fb;
9047 struct intel_framebuffer *intel_fb;
9048
9049 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9050 if (!intel_fb) {
9051 DRM_DEBUG_KMS("failed to alloc fb\n");
9052 return;
9053 }
9054
9055 fb = &intel_fb->base;
9056
9057 val = I915_READ(PLANE_CTL(pipe, 0));
9058 if (!(val & PLANE_CTL_ENABLE))
9059 goto error;
9060
9061 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9062 fourcc = skl_format_to_fourcc(pixel_format,
9063 val & PLANE_CTL_ORDER_RGBX,
9064 val & PLANE_CTL_ALPHA_MASK);
9065 fb->pixel_format = fourcc;
9066 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9067
9068 tiling = val & PLANE_CTL_TILED_MASK;
9069 switch (tiling) {
9070 case PLANE_CTL_TILED_LINEAR:
9071 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9072 break;
9073 case PLANE_CTL_TILED_X:
9074 plane_config->tiling = I915_TILING_X;
9075 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9076 break;
9077 case PLANE_CTL_TILED_Y:
9078 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9079 break;
9080 case PLANE_CTL_TILED_YF:
9081 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9082 break;
9083 default:
9084 MISSING_CASE(tiling);
9085 goto error;
9086 }
9087
9088 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9089 plane_config->base = base;
9090
9091 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9092
9093 val = I915_READ(PLANE_SIZE(pipe, 0));
9094 fb->height = ((val >> 16) & 0xfff) + 1;
9095 fb->width = ((val >> 0) & 0x1fff) + 1;
9096
9097 val = I915_READ(PLANE_STRIDE(pipe, 0));
9098 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9099 fb->pixel_format);
9100 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9101
9102 aligned_height = intel_fb_align_height(dev, fb->height,
9103 fb->pixel_format,
9104 fb->modifier[0]);
9105
9106 plane_config->size = fb->pitches[0] * aligned_height;
9107
9108 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9109 pipe_name(pipe), fb->width, fb->height,
9110 fb->bits_per_pixel, base, fb->pitches[0],
9111 plane_config->size);
9112
9113 plane_config->fb = intel_fb;
9114 return;
9115
9116 error:
9117 kfree(fb);
9118 }
9119
9120 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9121 struct intel_crtc_state *pipe_config)
9122 {
9123 struct drm_device *dev = crtc->base.dev;
9124 struct drm_i915_private *dev_priv = dev->dev_private;
9125 uint32_t tmp;
9126
9127 tmp = I915_READ(PF_CTL(crtc->pipe));
9128
9129 if (tmp & PF_ENABLE) {
9130 pipe_config->pch_pfit.enabled = true;
9131 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9132 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9133
9134 /* We currently do not free assignements of panel fitters on
9135 * ivb/hsw (since we don't use the higher upscaling modes which
9136 * differentiates them) so just WARN about this case for now. */
9137 if (IS_GEN7(dev)) {
9138 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9139 PF_PIPE_SEL_IVB(crtc->pipe));
9140 }
9141 }
9142 }
9143
9144 static void
9145 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9146 struct intel_initial_plane_config *plane_config)
9147 {
9148 struct drm_device *dev = crtc->base.dev;
9149 struct drm_i915_private *dev_priv = dev->dev_private;
9150 u32 val, base, offset;
9151 int pipe = crtc->pipe;
9152 int fourcc, pixel_format;
9153 unsigned int aligned_height;
9154 struct drm_framebuffer *fb;
9155 struct intel_framebuffer *intel_fb;
9156
9157 val = I915_READ(DSPCNTR(pipe));
9158 if (!(val & DISPLAY_PLANE_ENABLE))
9159 return;
9160
9161 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9162 if (!intel_fb) {
9163 DRM_DEBUG_KMS("failed to alloc fb\n");
9164 return;
9165 }
9166
9167 fb = &intel_fb->base;
9168
9169 if (INTEL_INFO(dev)->gen >= 4) {
9170 if (val & DISPPLANE_TILED) {
9171 plane_config->tiling = I915_TILING_X;
9172 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9173 }
9174 }
9175
9176 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9177 fourcc = i9xx_format_to_fourcc(pixel_format);
9178 fb->pixel_format = fourcc;
9179 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9180
9181 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9182 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9183 offset = I915_READ(DSPOFFSET(pipe));
9184 } else {
9185 if (plane_config->tiling)
9186 offset = I915_READ(DSPTILEOFF(pipe));
9187 else
9188 offset = I915_READ(DSPLINOFF(pipe));
9189 }
9190 plane_config->base = base;
9191
9192 val = I915_READ(PIPESRC(pipe));
9193 fb->width = ((val >> 16) & 0xfff) + 1;
9194 fb->height = ((val >> 0) & 0xfff) + 1;
9195
9196 val = I915_READ(DSPSTRIDE(pipe));
9197 fb->pitches[0] = val & 0xffffffc0;
9198
9199 aligned_height = intel_fb_align_height(dev, fb->height,
9200 fb->pixel_format,
9201 fb->modifier[0]);
9202
9203 plane_config->size = fb->pitches[0] * aligned_height;
9204
9205 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9206 pipe_name(pipe), fb->width, fb->height,
9207 fb->bits_per_pixel, base, fb->pitches[0],
9208 plane_config->size);
9209
9210 plane_config->fb = intel_fb;
9211 }
9212
9213 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9214 struct intel_crtc_state *pipe_config)
9215 {
9216 struct drm_device *dev = crtc->base.dev;
9217 struct drm_i915_private *dev_priv = dev->dev_private;
9218 enum intel_display_power_domain power_domain;
9219 uint32_t tmp;
9220 bool ret;
9221
9222 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9223 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9224 return false;
9225
9226 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9227 pipe_config->shared_dpll = NULL;
9228
9229 ret = false;
9230 tmp = I915_READ(PIPECONF(crtc->pipe));
9231 if (!(tmp & PIPECONF_ENABLE))
9232 goto out;
9233
9234 switch (tmp & PIPECONF_BPC_MASK) {
9235 case PIPECONF_6BPC:
9236 pipe_config->pipe_bpp = 18;
9237 break;
9238 case PIPECONF_8BPC:
9239 pipe_config->pipe_bpp = 24;
9240 break;
9241 case PIPECONF_10BPC:
9242 pipe_config->pipe_bpp = 30;
9243 break;
9244 case PIPECONF_12BPC:
9245 pipe_config->pipe_bpp = 36;
9246 break;
9247 default:
9248 break;
9249 }
9250
9251 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9252 pipe_config->limited_color_range = true;
9253
9254 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9255 struct intel_shared_dpll *pll;
9256 enum intel_dpll_id pll_id;
9257
9258 pipe_config->has_pch_encoder = true;
9259
9260 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9261 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9262 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9263
9264 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9265
9266 if (HAS_PCH_IBX(dev_priv->dev)) {
9267 pll_id = (enum intel_dpll_id) crtc->pipe;
9268 } else {
9269 tmp = I915_READ(PCH_DPLL_SEL);
9270 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9271 pll_id = DPLL_ID_PCH_PLL_B;
9272 else
9273 pll_id= DPLL_ID_PCH_PLL_A;
9274 }
9275
9276 pipe_config->shared_dpll =
9277 intel_get_shared_dpll_by_id(dev_priv, pll_id);
9278 pll = pipe_config->shared_dpll;
9279
9280 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9281 &pipe_config->dpll_hw_state));
9282
9283 tmp = pipe_config->dpll_hw_state.dpll;
9284 pipe_config->pixel_multiplier =
9285 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9286 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9287
9288 ironlake_pch_clock_get(crtc, pipe_config);
9289 } else {
9290 pipe_config->pixel_multiplier = 1;
9291 }
9292
9293 intel_get_pipe_timings(crtc, pipe_config);
9294 intel_get_pipe_src_size(crtc, pipe_config);
9295
9296 ironlake_get_pfit_config(crtc, pipe_config);
9297
9298 ret = true;
9299
9300 out:
9301 intel_display_power_put(dev_priv, power_domain);
9302
9303 return ret;
9304 }
9305
9306 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9307 {
9308 struct drm_device *dev = dev_priv->dev;
9309 struct intel_crtc *crtc;
9310
9311 for_each_intel_crtc(dev, crtc)
9312 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9313 pipe_name(crtc->pipe));
9314
9315 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9316 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9317 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9318 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9319 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9320 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9321 "CPU PWM1 enabled\n");
9322 if (IS_HASWELL(dev))
9323 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9324 "CPU PWM2 enabled\n");
9325 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9326 "PCH PWM1 enabled\n");
9327 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9328 "Utility pin enabled\n");
9329 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9330
9331 /*
9332 * In theory we can still leave IRQs enabled, as long as only the HPD
9333 * interrupts remain enabled. We used to check for that, but since it's
9334 * gen-specific and since we only disable LCPLL after we fully disable
9335 * the interrupts, the check below should be enough.
9336 */
9337 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9338 }
9339
9340 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9341 {
9342 struct drm_device *dev = dev_priv->dev;
9343
9344 if (IS_HASWELL(dev))
9345 return I915_READ(D_COMP_HSW);
9346 else
9347 return I915_READ(D_COMP_BDW);
9348 }
9349
9350 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9351 {
9352 struct drm_device *dev = dev_priv->dev;
9353
9354 if (IS_HASWELL(dev)) {
9355 mutex_lock(&dev_priv->rps.hw_lock);
9356 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9357 val))
9358 DRM_ERROR("Failed to write to D_COMP\n");
9359 mutex_unlock(&dev_priv->rps.hw_lock);
9360 } else {
9361 I915_WRITE(D_COMP_BDW, val);
9362 POSTING_READ(D_COMP_BDW);
9363 }
9364 }
9365
9366 /*
9367 * This function implements pieces of two sequences from BSpec:
9368 * - Sequence for display software to disable LCPLL
9369 * - Sequence for display software to allow package C8+
9370 * The steps implemented here are just the steps that actually touch the LCPLL
9371 * register. Callers should take care of disabling all the display engine
9372 * functions, doing the mode unset, fixing interrupts, etc.
9373 */
9374 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9375 bool switch_to_fclk, bool allow_power_down)
9376 {
9377 uint32_t val;
9378
9379 assert_can_disable_lcpll(dev_priv);
9380
9381 val = I915_READ(LCPLL_CTL);
9382
9383 if (switch_to_fclk) {
9384 val |= LCPLL_CD_SOURCE_FCLK;
9385 I915_WRITE(LCPLL_CTL, val);
9386
9387 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9388 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9389 DRM_ERROR("Switching to FCLK failed\n");
9390
9391 val = I915_READ(LCPLL_CTL);
9392 }
9393
9394 val |= LCPLL_PLL_DISABLE;
9395 I915_WRITE(LCPLL_CTL, val);
9396 POSTING_READ(LCPLL_CTL);
9397
9398 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9399 DRM_ERROR("LCPLL still locked\n");
9400
9401 val = hsw_read_dcomp(dev_priv);
9402 val |= D_COMP_COMP_DISABLE;
9403 hsw_write_dcomp(dev_priv, val);
9404 ndelay(100);
9405
9406 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9407 1))
9408 DRM_ERROR("D_COMP RCOMP still in progress\n");
9409
9410 if (allow_power_down) {
9411 val = I915_READ(LCPLL_CTL);
9412 val |= LCPLL_POWER_DOWN_ALLOW;
9413 I915_WRITE(LCPLL_CTL, val);
9414 POSTING_READ(LCPLL_CTL);
9415 }
9416 }
9417
9418 /*
9419 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9420 * source.
9421 */
9422 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9423 {
9424 uint32_t val;
9425
9426 val = I915_READ(LCPLL_CTL);
9427
9428 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9429 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9430 return;
9431
9432 /*
9433 * Make sure we're not on PC8 state before disabling PC8, otherwise
9434 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9435 */
9436 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9437
9438 if (val & LCPLL_POWER_DOWN_ALLOW) {
9439 val &= ~LCPLL_POWER_DOWN_ALLOW;
9440 I915_WRITE(LCPLL_CTL, val);
9441 POSTING_READ(LCPLL_CTL);
9442 }
9443
9444 val = hsw_read_dcomp(dev_priv);
9445 val |= D_COMP_COMP_FORCE;
9446 val &= ~D_COMP_COMP_DISABLE;
9447 hsw_write_dcomp(dev_priv, val);
9448
9449 val = I915_READ(LCPLL_CTL);
9450 val &= ~LCPLL_PLL_DISABLE;
9451 I915_WRITE(LCPLL_CTL, val);
9452
9453 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9454 DRM_ERROR("LCPLL not locked yet\n");
9455
9456 if (val & LCPLL_CD_SOURCE_FCLK) {
9457 val = I915_READ(LCPLL_CTL);
9458 val &= ~LCPLL_CD_SOURCE_FCLK;
9459 I915_WRITE(LCPLL_CTL, val);
9460
9461 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9462 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9463 DRM_ERROR("Switching back to LCPLL failed\n");
9464 }
9465
9466 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9467 intel_update_cdclk(dev_priv->dev);
9468 }
9469
9470 /*
9471 * Package states C8 and deeper are really deep PC states that can only be
9472 * reached when all the devices on the system allow it, so even if the graphics
9473 * device allows PC8+, it doesn't mean the system will actually get to these
9474 * states. Our driver only allows PC8+ when going into runtime PM.
9475 *
9476 * The requirements for PC8+ are that all the outputs are disabled, the power
9477 * well is disabled and most interrupts are disabled, and these are also
9478 * requirements for runtime PM. When these conditions are met, we manually do
9479 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9480 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9481 * hang the machine.
9482 *
9483 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9484 * the state of some registers, so when we come back from PC8+ we need to
9485 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9486 * need to take care of the registers kept by RC6. Notice that this happens even
9487 * if we don't put the device in PCI D3 state (which is what currently happens
9488 * because of the runtime PM support).
9489 *
9490 * For more, read "Display Sequences for Package C8" on the hardware
9491 * documentation.
9492 */
9493 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9494 {
9495 struct drm_device *dev = dev_priv->dev;
9496 uint32_t val;
9497
9498 DRM_DEBUG_KMS("Enabling package C8+\n");
9499
9500 if (HAS_PCH_LPT_LP(dev)) {
9501 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9502 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9503 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9504 }
9505
9506 lpt_disable_clkout_dp(dev);
9507 hsw_disable_lcpll(dev_priv, true, true);
9508 }
9509
9510 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9511 {
9512 struct drm_device *dev = dev_priv->dev;
9513 uint32_t val;
9514
9515 DRM_DEBUG_KMS("Disabling package C8+\n");
9516
9517 hsw_restore_lcpll(dev_priv);
9518 lpt_init_pch_refclk(dev);
9519
9520 if (HAS_PCH_LPT_LP(dev)) {
9521 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9522 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9523 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9524 }
9525 }
9526
9527 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9528 {
9529 struct drm_device *dev = old_state->dev;
9530 struct intel_atomic_state *old_intel_state =
9531 to_intel_atomic_state(old_state);
9532 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9533
9534 broxton_set_cdclk(dev, req_cdclk);
9535 }
9536
9537 /* compute the max rate for new configuration */
9538 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9539 {
9540 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9541 struct drm_i915_private *dev_priv = state->dev->dev_private;
9542 struct drm_crtc *crtc;
9543 struct drm_crtc_state *cstate;
9544 struct intel_crtc_state *crtc_state;
9545 unsigned max_pixel_rate = 0, i;
9546 enum pipe pipe;
9547
9548 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9549 sizeof(intel_state->min_pixclk));
9550
9551 for_each_crtc_in_state(state, crtc, cstate, i) {
9552 int pixel_rate;
9553
9554 crtc_state = to_intel_crtc_state(cstate);
9555 if (!crtc_state->base.enable) {
9556 intel_state->min_pixclk[i] = 0;
9557 continue;
9558 }
9559
9560 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9561
9562 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9563 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9564 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9565
9566 intel_state->min_pixclk[i] = pixel_rate;
9567 }
9568
9569 for_each_pipe(dev_priv, pipe)
9570 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9571
9572 return max_pixel_rate;
9573 }
9574
9575 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9576 {
9577 struct drm_i915_private *dev_priv = dev->dev_private;
9578 uint32_t val, data;
9579 int ret;
9580
9581 if (WARN((I915_READ(LCPLL_CTL) &
9582 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9583 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9584 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9585 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9586 "trying to change cdclk frequency with cdclk not enabled\n"))
9587 return;
9588
9589 mutex_lock(&dev_priv->rps.hw_lock);
9590 ret = sandybridge_pcode_write(dev_priv,
9591 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9592 mutex_unlock(&dev_priv->rps.hw_lock);
9593 if (ret) {
9594 DRM_ERROR("failed to inform pcode about cdclk change\n");
9595 return;
9596 }
9597
9598 val = I915_READ(LCPLL_CTL);
9599 val |= LCPLL_CD_SOURCE_FCLK;
9600 I915_WRITE(LCPLL_CTL, val);
9601
9602 if (wait_for_us(I915_READ(LCPLL_CTL) &
9603 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9604 DRM_ERROR("Switching to FCLK failed\n");
9605
9606 val = I915_READ(LCPLL_CTL);
9607 val &= ~LCPLL_CLK_FREQ_MASK;
9608
9609 switch (cdclk) {
9610 case 450000:
9611 val |= LCPLL_CLK_FREQ_450;
9612 data = 0;
9613 break;
9614 case 540000:
9615 val |= LCPLL_CLK_FREQ_54O_BDW;
9616 data = 1;
9617 break;
9618 case 337500:
9619 val |= LCPLL_CLK_FREQ_337_5_BDW;
9620 data = 2;
9621 break;
9622 case 675000:
9623 val |= LCPLL_CLK_FREQ_675_BDW;
9624 data = 3;
9625 break;
9626 default:
9627 WARN(1, "invalid cdclk frequency\n");
9628 return;
9629 }
9630
9631 I915_WRITE(LCPLL_CTL, val);
9632
9633 val = I915_READ(LCPLL_CTL);
9634 val &= ~LCPLL_CD_SOURCE_FCLK;
9635 I915_WRITE(LCPLL_CTL, val);
9636
9637 if (wait_for_us((I915_READ(LCPLL_CTL) &
9638 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9639 DRM_ERROR("Switching back to LCPLL failed\n");
9640
9641 mutex_lock(&dev_priv->rps.hw_lock);
9642 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9643 mutex_unlock(&dev_priv->rps.hw_lock);
9644
9645 intel_update_cdclk(dev);
9646
9647 WARN(cdclk != dev_priv->cdclk_freq,
9648 "cdclk requested %d kHz but got %d kHz\n",
9649 cdclk, dev_priv->cdclk_freq);
9650 }
9651
9652 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9653 {
9654 struct drm_i915_private *dev_priv = to_i915(state->dev);
9655 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9656 int max_pixclk = ilk_max_pixel_rate(state);
9657 int cdclk;
9658
9659 /*
9660 * FIXME should also account for plane ratio
9661 * once 64bpp pixel formats are supported.
9662 */
9663 if (max_pixclk > 540000)
9664 cdclk = 675000;
9665 else if (max_pixclk > 450000)
9666 cdclk = 540000;
9667 else if (max_pixclk > 337500)
9668 cdclk = 450000;
9669 else
9670 cdclk = 337500;
9671
9672 if (cdclk > dev_priv->max_cdclk_freq) {
9673 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9674 cdclk, dev_priv->max_cdclk_freq);
9675 return -EINVAL;
9676 }
9677
9678 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9679 if (!intel_state->active_crtcs)
9680 intel_state->dev_cdclk = 337500;
9681
9682 return 0;
9683 }
9684
9685 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9686 {
9687 struct drm_device *dev = old_state->dev;
9688 struct intel_atomic_state *old_intel_state =
9689 to_intel_atomic_state(old_state);
9690 unsigned req_cdclk = old_intel_state->dev_cdclk;
9691
9692 broadwell_set_cdclk(dev, req_cdclk);
9693 }
9694
9695 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9696 struct intel_crtc_state *crtc_state)
9697 {
9698 struct intel_encoder *intel_encoder =
9699 intel_ddi_get_crtc_new_encoder(crtc_state);
9700
9701 if (intel_encoder->type != INTEL_OUTPUT_DSI) {
9702 if (!intel_ddi_pll_select(crtc, crtc_state))
9703 return -EINVAL;
9704 }
9705
9706 crtc->lowfreq_avail = false;
9707
9708 return 0;
9709 }
9710
9711 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9712 enum port port,
9713 struct intel_crtc_state *pipe_config)
9714 {
9715 enum intel_dpll_id id;
9716
9717 switch (port) {
9718 case PORT_A:
9719 pipe_config->ddi_pll_sel = SKL_DPLL0;
9720 id = DPLL_ID_SKL_DPLL0;
9721 break;
9722 case PORT_B:
9723 pipe_config->ddi_pll_sel = SKL_DPLL1;
9724 id = DPLL_ID_SKL_DPLL1;
9725 break;
9726 case PORT_C:
9727 pipe_config->ddi_pll_sel = SKL_DPLL2;
9728 id = DPLL_ID_SKL_DPLL2;
9729 break;
9730 default:
9731 DRM_ERROR("Incorrect port type\n");
9732 return;
9733 }
9734
9735 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9736 }
9737
9738 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9739 enum port port,
9740 struct intel_crtc_state *pipe_config)
9741 {
9742 enum intel_dpll_id id;
9743 u32 temp;
9744
9745 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9746 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9747
9748 switch (pipe_config->ddi_pll_sel) {
9749 case SKL_DPLL0:
9750 id = DPLL_ID_SKL_DPLL0;
9751 break;
9752 case SKL_DPLL1:
9753 id = DPLL_ID_SKL_DPLL1;
9754 break;
9755 case SKL_DPLL2:
9756 id = DPLL_ID_SKL_DPLL2;
9757 break;
9758 case SKL_DPLL3:
9759 id = DPLL_ID_SKL_DPLL3;
9760 break;
9761 default:
9762 MISSING_CASE(pipe_config->ddi_pll_sel);
9763 return;
9764 }
9765
9766 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9767 }
9768
9769 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9770 enum port port,
9771 struct intel_crtc_state *pipe_config)
9772 {
9773 enum intel_dpll_id id;
9774
9775 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9776
9777 switch (pipe_config->ddi_pll_sel) {
9778 case PORT_CLK_SEL_WRPLL1:
9779 id = DPLL_ID_WRPLL1;
9780 break;
9781 case PORT_CLK_SEL_WRPLL2:
9782 id = DPLL_ID_WRPLL2;
9783 break;
9784 case PORT_CLK_SEL_SPLL:
9785 id = DPLL_ID_SPLL;
9786 break;
9787 case PORT_CLK_SEL_LCPLL_810:
9788 id = DPLL_ID_LCPLL_810;
9789 break;
9790 case PORT_CLK_SEL_LCPLL_1350:
9791 id = DPLL_ID_LCPLL_1350;
9792 break;
9793 case PORT_CLK_SEL_LCPLL_2700:
9794 id = DPLL_ID_LCPLL_2700;
9795 break;
9796 default:
9797 MISSING_CASE(pipe_config->ddi_pll_sel);
9798 /* fall through */
9799 case PORT_CLK_SEL_NONE:
9800 return;
9801 }
9802
9803 pipe_config->shared_dpll = intel_get_shared_dpll_by_id(dev_priv, id);
9804 }
9805
9806 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
9807 struct intel_crtc_state *pipe_config,
9808 unsigned long *power_domain_mask)
9809 {
9810 struct drm_device *dev = crtc->base.dev;
9811 struct drm_i915_private *dev_priv = dev->dev_private;
9812 enum intel_display_power_domain power_domain;
9813 u32 tmp;
9814
9815 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9816
9817 /*
9818 * XXX: Do intel_display_power_get_if_enabled before reading this (for
9819 * consistency and less surprising code; it's in always on power).
9820 */
9821 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9822 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9823 enum pipe trans_edp_pipe;
9824 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9825 default:
9826 WARN(1, "unknown pipe linked to edp transcoder\n");
9827 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9828 case TRANS_DDI_EDP_INPUT_A_ON:
9829 trans_edp_pipe = PIPE_A;
9830 break;
9831 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9832 trans_edp_pipe = PIPE_B;
9833 break;
9834 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9835 trans_edp_pipe = PIPE_C;
9836 break;
9837 }
9838
9839 if (trans_edp_pipe == crtc->pipe)
9840 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9841 }
9842
9843 power_domain = POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder);
9844 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9845 return false;
9846 *power_domain_mask |= BIT(power_domain);
9847
9848 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9849
9850 return tmp & PIPECONF_ENABLE;
9851 }
9852
9853 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
9854 struct intel_crtc_state *pipe_config,
9855 unsigned long *power_domain_mask)
9856 {
9857 struct drm_device *dev = crtc->base.dev;
9858 struct drm_i915_private *dev_priv = dev->dev_private;
9859 enum intel_display_power_domain power_domain;
9860 enum port port;
9861 enum transcoder cpu_transcoder;
9862 u32 tmp;
9863
9864 pipe_config->has_dsi_encoder = false;
9865
9866 for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
9867 if (port == PORT_A)
9868 cpu_transcoder = TRANSCODER_DSI_A;
9869 else
9870 cpu_transcoder = TRANSCODER_DSI_C;
9871
9872 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
9873 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9874 continue;
9875 *power_domain_mask |= BIT(power_domain);
9876
9877 /*
9878 * The PLL needs to be enabled with a valid divider
9879 * configuration, otherwise accessing DSI registers will hang
9880 * the machine. See BSpec North Display Engine
9881 * registers/MIPI[BXT]. We can break out here early, since we
9882 * need the same DSI PLL to be enabled for both DSI ports.
9883 */
9884 if (!intel_dsi_pll_is_enabled(dev_priv))
9885 break;
9886
9887 /* XXX: this works for video mode only */
9888 tmp = I915_READ(BXT_MIPI_PORT_CTRL(port));
9889 if (!(tmp & DPI_ENABLE))
9890 continue;
9891
9892 tmp = I915_READ(MIPI_CTRL(port));
9893 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
9894 continue;
9895
9896 pipe_config->cpu_transcoder = cpu_transcoder;
9897 pipe_config->has_dsi_encoder = true;
9898 break;
9899 }
9900
9901 return pipe_config->has_dsi_encoder;
9902 }
9903
9904 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9905 struct intel_crtc_state *pipe_config)
9906 {
9907 struct drm_device *dev = crtc->base.dev;
9908 struct drm_i915_private *dev_priv = dev->dev_private;
9909 struct intel_shared_dpll *pll;
9910 enum port port;
9911 uint32_t tmp;
9912
9913 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9914
9915 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9916
9917 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9918 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9919 else if (IS_BROXTON(dev))
9920 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9921 else
9922 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9923
9924 pll = pipe_config->shared_dpll;
9925 if (pll) {
9926 WARN_ON(!pll->funcs.get_hw_state(dev_priv, pll,
9927 &pipe_config->dpll_hw_state));
9928 }
9929
9930 /*
9931 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9932 * DDI E. So just check whether this pipe is wired to DDI E and whether
9933 * the PCH transcoder is on.
9934 */
9935 if (INTEL_INFO(dev)->gen < 9 &&
9936 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9937 pipe_config->has_pch_encoder = true;
9938
9939 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9940 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9941 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9942
9943 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9944 }
9945 }
9946
9947 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9948 struct intel_crtc_state *pipe_config)
9949 {
9950 struct drm_device *dev = crtc->base.dev;
9951 struct drm_i915_private *dev_priv = dev->dev_private;
9952 enum intel_display_power_domain power_domain;
9953 unsigned long power_domain_mask;
9954 bool active;
9955
9956 power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
9957 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
9958 return false;
9959 power_domain_mask = BIT(power_domain);
9960
9961 pipe_config->shared_dpll = NULL;
9962
9963 active = hsw_get_transcoder_state(crtc, pipe_config, &power_domain_mask);
9964
9965 if (IS_BROXTON(dev_priv)) {
9966 bxt_get_dsi_transcoder_state(crtc, pipe_config,
9967 &power_domain_mask);
9968 WARN_ON(active && pipe_config->has_dsi_encoder);
9969 if (pipe_config->has_dsi_encoder)
9970 active = true;
9971 }
9972
9973 if (!active)
9974 goto out;
9975
9976 if (!pipe_config->has_dsi_encoder) {
9977 haswell_get_ddi_port_state(crtc, pipe_config);
9978 intel_get_pipe_timings(crtc, pipe_config);
9979 }
9980
9981 intel_get_pipe_src_size(crtc, pipe_config);
9982
9983 pipe_config->gamma_mode =
9984 I915_READ(GAMMA_MODE(crtc->pipe)) & GAMMA_MODE_MODE_MASK;
9985
9986 if (INTEL_INFO(dev)->gen >= 9) {
9987 skl_init_scalers(dev, crtc, pipe_config);
9988 }
9989
9990 if (INTEL_INFO(dev)->gen >= 9) {
9991 pipe_config->scaler_state.scaler_id = -1;
9992 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9993 }
9994
9995 power_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9996 if (intel_display_power_get_if_enabled(dev_priv, power_domain)) {
9997 power_domain_mask |= BIT(power_domain);
9998 if (INTEL_INFO(dev)->gen >= 9)
9999 skylake_get_pfit_config(crtc, pipe_config);
10000 else
10001 ironlake_get_pfit_config(crtc, pipe_config);
10002 }
10003
10004 if (IS_HASWELL(dev))
10005 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10006 (I915_READ(IPS_CTL) & IPS_ENABLE);
10007
10008 if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
10009 !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
10010 pipe_config->pixel_multiplier =
10011 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10012 } else {
10013 pipe_config->pixel_multiplier = 1;
10014 }
10015
10016 out:
10017 for_each_power_domain(power_domain, power_domain_mask)
10018 intel_display_power_put(dev_priv, power_domain);
10019
10020 return active;
10021 }
10022
10023 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10024 const struct intel_plane_state *plane_state)
10025 {
10026 struct drm_device *dev = crtc->dev;
10027 struct drm_i915_private *dev_priv = dev->dev_private;
10028 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10029 uint32_t cntl = 0, size = 0;
10030
10031 if (plane_state && plane_state->visible) {
10032 unsigned int width = plane_state->base.crtc_w;
10033 unsigned int height = plane_state->base.crtc_h;
10034 unsigned int stride = roundup_pow_of_two(width) * 4;
10035
10036 switch (stride) {
10037 default:
10038 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10039 width, stride);
10040 stride = 256;
10041 /* fallthrough */
10042 case 256:
10043 case 512:
10044 case 1024:
10045 case 2048:
10046 break;
10047 }
10048
10049 cntl |= CURSOR_ENABLE |
10050 CURSOR_GAMMA_ENABLE |
10051 CURSOR_FORMAT_ARGB |
10052 CURSOR_STRIDE(stride);
10053
10054 size = (height << 12) | width;
10055 }
10056
10057 if (intel_crtc->cursor_cntl != 0 &&
10058 (intel_crtc->cursor_base != base ||
10059 intel_crtc->cursor_size != size ||
10060 intel_crtc->cursor_cntl != cntl)) {
10061 /* On these chipsets we can only modify the base/size/stride
10062 * whilst the cursor is disabled.
10063 */
10064 I915_WRITE(CURCNTR(PIPE_A), 0);
10065 POSTING_READ(CURCNTR(PIPE_A));
10066 intel_crtc->cursor_cntl = 0;
10067 }
10068
10069 if (intel_crtc->cursor_base != base) {
10070 I915_WRITE(CURBASE(PIPE_A), base);
10071 intel_crtc->cursor_base = base;
10072 }
10073
10074 if (intel_crtc->cursor_size != size) {
10075 I915_WRITE(CURSIZE, size);
10076 intel_crtc->cursor_size = size;
10077 }
10078
10079 if (intel_crtc->cursor_cntl != cntl) {
10080 I915_WRITE(CURCNTR(PIPE_A), cntl);
10081 POSTING_READ(CURCNTR(PIPE_A));
10082 intel_crtc->cursor_cntl = cntl;
10083 }
10084 }
10085
10086 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10087 const struct intel_plane_state *plane_state)
10088 {
10089 struct drm_device *dev = crtc->dev;
10090 struct drm_i915_private *dev_priv = dev->dev_private;
10091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10092 int pipe = intel_crtc->pipe;
10093 uint32_t cntl = 0;
10094
10095 if (plane_state && plane_state->visible) {
10096 cntl = MCURSOR_GAMMA_ENABLE;
10097 switch (plane_state->base.crtc_w) {
10098 case 64:
10099 cntl |= CURSOR_MODE_64_ARGB_AX;
10100 break;
10101 case 128:
10102 cntl |= CURSOR_MODE_128_ARGB_AX;
10103 break;
10104 case 256:
10105 cntl |= CURSOR_MODE_256_ARGB_AX;
10106 break;
10107 default:
10108 MISSING_CASE(plane_state->base.crtc_w);
10109 return;
10110 }
10111 cntl |= pipe << 28; /* Connect to correct pipe */
10112
10113 if (HAS_DDI(dev))
10114 cntl |= CURSOR_PIPE_CSC_ENABLE;
10115
10116 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10117 cntl |= CURSOR_ROTATE_180;
10118 }
10119
10120 if (intel_crtc->cursor_cntl != cntl) {
10121 I915_WRITE(CURCNTR(pipe), cntl);
10122 POSTING_READ(CURCNTR(pipe));
10123 intel_crtc->cursor_cntl = cntl;
10124 }
10125
10126 /* and commit changes on next vblank */
10127 I915_WRITE(CURBASE(pipe), base);
10128 POSTING_READ(CURBASE(pipe));
10129
10130 intel_crtc->cursor_base = base;
10131 }
10132
10133 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10134 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10135 const struct intel_plane_state *plane_state)
10136 {
10137 struct drm_device *dev = crtc->dev;
10138 struct drm_i915_private *dev_priv = dev->dev_private;
10139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10140 int pipe = intel_crtc->pipe;
10141 u32 base = intel_crtc->cursor_addr;
10142 u32 pos = 0;
10143
10144 if (plane_state) {
10145 int x = plane_state->base.crtc_x;
10146 int y = plane_state->base.crtc_y;
10147
10148 if (x < 0) {
10149 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10150 x = -x;
10151 }
10152 pos |= x << CURSOR_X_SHIFT;
10153
10154 if (y < 0) {
10155 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10156 y = -y;
10157 }
10158 pos |= y << CURSOR_Y_SHIFT;
10159
10160 /* ILK+ do this automagically */
10161 if (HAS_GMCH_DISPLAY(dev) &&
10162 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10163 base += (plane_state->base.crtc_h *
10164 plane_state->base.crtc_w - 1) * 4;
10165 }
10166 }
10167
10168 I915_WRITE(CURPOS(pipe), pos);
10169
10170 if (IS_845G(dev) || IS_I865G(dev))
10171 i845_update_cursor(crtc, base, plane_state);
10172 else
10173 i9xx_update_cursor(crtc, base, plane_state);
10174 }
10175
10176 static bool cursor_size_ok(struct drm_device *dev,
10177 uint32_t width, uint32_t height)
10178 {
10179 if (width == 0 || height == 0)
10180 return false;
10181
10182 /*
10183 * 845g/865g are special in that they are only limited by
10184 * the width of their cursors, the height is arbitrary up to
10185 * the precision of the register. Everything else requires
10186 * square cursors, limited to a few power-of-two sizes.
10187 */
10188 if (IS_845G(dev) || IS_I865G(dev)) {
10189 if ((width & 63) != 0)
10190 return false;
10191
10192 if (width > (IS_845G(dev) ? 64 : 512))
10193 return false;
10194
10195 if (height > 1023)
10196 return false;
10197 } else {
10198 switch (width | height) {
10199 case 256:
10200 case 128:
10201 if (IS_GEN2(dev))
10202 return false;
10203 case 64:
10204 break;
10205 default:
10206 return false;
10207 }
10208 }
10209
10210 return true;
10211 }
10212
10213 /* VESA 640x480x72Hz mode to set on the pipe */
10214 static struct drm_display_mode load_detect_mode = {
10215 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10216 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10217 };
10218
10219 struct drm_framebuffer *
10220 __intel_framebuffer_create(struct drm_device *dev,
10221 struct drm_mode_fb_cmd2 *mode_cmd,
10222 struct drm_i915_gem_object *obj)
10223 {
10224 struct intel_framebuffer *intel_fb;
10225 int ret;
10226
10227 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10228 if (!intel_fb)
10229 return ERR_PTR(-ENOMEM);
10230
10231 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10232 if (ret)
10233 goto err;
10234
10235 return &intel_fb->base;
10236
10237 err:
10238 kfree(intel_fb);
10239 return ERR_PTR(ret);
10240 }
10241
10242 static struct drm_framebuffer *
10243 intel_framebuffer_create(struct drm_device *dev,
10244 struct drm_mode_fb_cmd2 *mode_cmd,
10245 struct drm_i915_gem_object *obj)
10246 {
10247 struct drm_framebuffer *fb;
10248 int ret;
10249
10250 ret = i915_mutex_lock_interruptible(dev);
10251 if (ret)
10252 return ERR_PTR(ret);
10253 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10254 mutex_unlock(&dev->struct_mutex);
10255
10256 return fb;
10257 }
10258
10259 static u32
10260 intel_framebuffer_pitch_for_width(int width, int bpp)
10261 {
10262 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10263 return ALIGN(pitch, 64);
10264 }
10265
10266 static u32
10267 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10268 {
10269 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10270 return PAGE_ALIGN(pitch * mode->vdisplay);
10271 }
10272
10273 static struct drm_framebuffer *
10274 intel_framebuffer_create_for_mode(struct drm_device *dev,
10275 struct drm_display_mode *mode,
10276 int depth, int bpp)
10277 {
10278 struct drm_framebuffer *fb;
10279 struct drm_i915_gem_object *obj;
10280 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10281
10282 obj = i915_gem_alloc_object(dev,
10283 intel_framebuffer_size_for_mode(mode, bpp));
10284 if (obj == NULL)
10285 return ERR_PTR(-ENOMEM);
10286
10287 mode_cmd.width = mode->hdisplay;
10288 mode_cmd.height = mode->vdisplay;
10289 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10290 bpp);
10291 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10292
10293 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10294 if (IS_ERR(fb))
10295 drm_gem_object_unreference_unlocked(&obj->base);
10296
10297 return fb;
10298 }
10299
10300 static struct drm_framebuffer *
10301 mode_fits_in_fbdev(struct drm_device *dev,
10302 struct drm_display_mode *mode)
10303 {
10304 #ifdef CONFIG_DRM_FBDEV_EMULATION
10305 struct drm_i915_private *dev_priv = dev->dev_private;
10306 struct drm_i915_gem_object *obj;
10307 struct drm_framebuffer *fb;
10308
10309 if (!dev_priv->fbdev)
10310 return NULL;
10311
10312 if (!dev_priv->fbdev->fb)
10313 return NULL;
10314
10315 obj = dev_priv->fbdev->fb->obj;
10316 BUG_ON(!obj);
10317
10318 fb = &dev_priv->fbdev->fb->base;
10319 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10320 fb->bits_per_pixel))
10321 return NULL;
10322
10323 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10324 return NULL;
10325
10326 drm_framebuffer_reference(fb);
10327 return fb;
10328 #else
10329 return NULL;
10330 #endif
10331 }
10332
10333 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10334 struct drm_crtc *crtc,
10335 struct drm_display_mode *mode,
10336 struct drm_framebuffer *fb,
10337 int x, int y)
10338 {
10339 struct drm_plane_state *plane_state;
10340 int hdisplay, vdisplay;
10341 int ret;
10342
10343 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10344 if (IS_ERR(plane_state))
10345 return PTR_ERR(plane_state);
10346
10347 if (mode)
10348 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10349 else
10350 hdisplay = vdisplay = 0;
10351
10352 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10353 if (ret)
10354 return ret;
10355 drm_atomic_set_fb_for_plane(plane_state, fb);
10356 plane_state->crtc_x = 0;
10357 plane_state->crtc_y = 0;
10358 plane_state->crtc_w = hdisplay;
10359 plane_state->crtc_h = vdisplay;
10360 plane_state->src_x = x << 16;
10361 plane_state->src_y = y << 16;
10362 plane_state->src_w = hdisplay << 16;
10363 plane_state->src_h = vdisplay << 16;
10364
10365 return 0;
10366 }
10367
10368 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10369 struct drm_display_mode *mode,
10370 struct intel_load_detect_pipe *old,
10371 struct drm_modeset_acquire_ctx *ctx)
10372 {
10373 struct intel_crtc *intel_crtc;
10374 struct intel_encoder *intel_encoder =
10375 intel_attached_encoder(connector);
10376 struct drm_crtc *possible_crtc;
10377 struct drm_encoder *encoder = &intel_encoder->base;
10378 struct drm_crtc *crtc = NULL;
10379 struct drm_device *dev = encoder->dev;
10380 struct drm_framebuffer *fb;
10381 struct drm_mode_config *config = &dev->mode_config;
10382 struct drm_atomic_state *state = NULL, *restore_state = NULL;
10383 struct drm_connector_state *connector_state;
10384 struct intel_crtc_state *crtc_state;
10385 int ret, i = -1;
10386
10387 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10388 connector->base.id, connector->name,
10389 encoder->base.id, encoder->name);
10390
10391 old->restore_state = NULL;
10392
10393 retry:
10394 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10395 if (ret)
10396 goto fail;
10397
10398 /*
10399 * Algorithm gets a little messy:
10400 *
10401 * - if the connector already has an assigned crtc, use it (but make
10402 * sure it's on first)
10403 *
10404 * - try to find the first unused crtc that can drive this connector,
10405 * and use that if we find one
10406 */
10407
10408 /* See if we already have a CRTC for this connector */
10409 if (connector->state->crtc) {
10410 crtc = connector->state->crtc;
10411
10412 ret = drm_modeset_lock(&crtc->mutex, ctx);
10413 if (ret)
10414 goto fail;
10415
10416 /* Make sure the crtc and connector are running */
10417 goto found;
10418 }
10419
10420 /* Find an unused one (if possible) */
10421 for_each_crtc(dev, possible_crtc) {
10422 i++;
10423 if (!(encoder->possible_crtcs & (1 << i)))
10424 continue;
10425
10426 ret = drm_modeset_lock(&possible_crtc->mutex, ctx);
10427 if (ret)
10428 goto fail;
10429
10430 if (possible_crtc->state->enable) {
10431 drm_modeset_unlock(&possible_crtc->mutex);
10432 continue;
10433 }
10434
10435 crtc = possible_crtc;
10436 break;
10437 }
10438
10439 /*
10440 * If we didn't find an unused CRTC, don't use any.
10441 */
10442 if (!crtc) {
10443 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10444 goto fail;
10445 }
10446
10447 found:
10448 intel_crtc = to_intel_crtc(crtc);
10449
10450 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10451 if (ret)
10452 goto fail;
10453
10454 state = drm_atomic_state_alloc(dev);
10455 restore_state = drm_atomic_state_alloc(dev);
10456 if (!state || !restore_state) {
10457 ret = -ENOMEM;
10458 goto fail;
10459 }
10460
10461 state->acquire_ctx = ctx;
10462 restore_state->acquire_ctx = ctx;
10463
10464 connector_state = drm_atomic_get_connector_state(state, connector);
10465 if (IS_ERR(connector_state)) {
10466 ret = PTR_ERR(connector_state);
10467 goto fail;
10468 }
10469
10470 ret = drm_atomic_set_crtc_for_connector(connector_state, crtc);
10471 if (ret)
10472 goto fail;
10473
10474 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10475 if (IS_ERR(crtc_state)) {
10476 ret = PTR_ERR(crtc_state);
10477 goto fail;
10478 }
10479
10480 crtc_state->base.active = crtc_state->base.enable = true;
10481
10482 if (!mode)
10483 mode = &load_detect_mode;
10484
10485 /* We need a framebuffer large enough to accommodate all accesses
10486 * that the plane may generate whilst we perform load detection.
10487 * We can not rely on the fbcon either being present (we get called
10488 * during its initialisation to detect all boot displays, or it may
10489 * not even exist) or that it is large enough to satisfy the
10490 * requested mode.
10491 */
10492 fb = mode_fits_in_fbdev(dev, mode);
10493 if (fb == NULL) {
10494 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10495 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10496 } else
10497 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10498 if (IS_ERR(fb)) {
10499 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10500 goto fail;
10501 }
10502
10503 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10504 if (ret)
10505 goto fail;
10506
10507 drm_framebuffer_unreference(fb);
10508
10509 ret = drm_atomic_set_mode_for_crtc(&crtc_state->base, mode);
10510 if (ret)
10511 goto fail;
10512
10513 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(restore_state, connector));
10514 if (!ret)
10515 ret = PTR_ERR_OR_ZERO(drm_atomic_get_crtc_state(restore_state, crtc));
10516 if (!ret)
10517 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(restore_state, crtc->primary));
10518 if (ret) {
10519 DRM_DEBUG_KMS("Failed to create a copy of old state to restore: %i\n", ret);
10520 goto fail;
10521 }
10522
10523 ret = drm_atomic_commit(state);
10524 if (ret) {
10525 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10526 goto fail;
10527 }
10528
10529 old->restore_state = restore_state;
10530
10531 /* let the connector get through one full cycle before testing */
10532 intel_wait_for_vblank(dev, intel_crtc->pipe);
10533 return true;
10534
10535 fail:
10536 drm_atomic_state_free(state);
10537 drm_atomic_state_free(restore_state);
10538 restore_state = state = NULL;
10539
10540 if (ret == -EDEADLK) {
10541 drm_modeset_backoff(ctx);
10542 goto retry;
10543 }
10544
10545 return false;
10546 }
10547
10548 void intel_release_load_detect_pipe(struct drm_connector *connector,
10549 struct intel_load_detect_pipe *old,
10550 struct drm_modeset_acquire_ctx *ctx)
10551 {
10552 struct intel_encoder *intel_encoder =
10553 intel_attached_encoder(connector);
10554 struct drm_encoder *encoder = &intel_encoder->base;
10555 struct drm_atomic_state *state = old->restore_state;
10556 int ret;
10557
10558 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10559 connector->base.id, connector->name,
10560 encoder->base.id, encoder->name);
10561
10562 if (!state)
10563 return;
10564
10565 ret = drm_atomic_commit(state);
10566 if (ret) {
10567 DRM_DEBUG_KMS("Couldn't release load detect pipe: %i\n", ret);
10568 drm_atomic_state_free(state);
10569 }
10570 }
10571
10572 static int i9xx_pll_refclk(struct drm_device *dev,
10573 const struct intel_crtc_state *pipe_config)
10574 {
10575 struct drm_i915_private *dev_priv = dev->dev_private;
10576 u32 dpll = pipe_config->dpll_hw_state.dpll;
10577
10578 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10579 return dev_priv->vbt.lvds_ssc_freq;
10580 else if (HAS_PCH_SPLIT(dev))
10581 return 120000;
10582 else if (!IS_GEN2(dev))
10583 return 96000;
10584 else
10585 return 48000;
10586 }
10587
10588 /* Returns the clock of the currently programmed mode of the given pipe. */
10589 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10590 struct intel_crtc_state *pipe_config)
10591 {
10592 struct drm_device *dev = crtc->base.dev;
10593 struct drm_i915_private *dev_priv = dev->dev_private;
10594 int pipe = pipe_config->cpu_transcoder;
10595 u32 dpll = pipe_config->dpll_hw_state.dpll;
10596 u32 fp;
10597 intel_clock_t clock;
10598 int port_clock;
10599 int refclk = i9xx_pll_refclk(dev, pipe_config);
10600
10601 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10602 fp = pipe_config->dpll_hw_state.fp0;
10603 else
10604 fp = pipe_config->dpll_hw_state.fp1;
10605
10606 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10607 if (IS_PINEVIEW(dev)) {
10608 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10609 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10610 } else {
10611 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10612 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10613 }
10614
10615 if (!IS_GEN2(dev)) {
10616 if (IS_PINEVIEW(dev))
10617 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10618 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10619 else
10620 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10621 DPLL_FPA01_P1_POST_DIV_SHIFT);
10622
10623 switch (dpll & DPLL_MODE_MASK) {
10624 case DPLLB_MODE_DAC_SERIAL:
10625 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10626 5 : 10;
10627 break;
10628 case DPLLB_MODE_LVDS:
10629 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10630 7 : 14;
10631 break;
10632 default:
10633 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10634 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10635 return;
10636 }
10637
10638 if (IS_PINEVIEW(dev))
10639 port_clock = pnv_calc_dpll_params(refclk, &clock);
10640 else
10641 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10642 } else {
10643 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10644 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10645
10646 if (is_lvds) {
10647 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10648 DPLL_FPA01_P1_POST_DIV_SHIFT);
10649
10650 if (lvds & LVDS_CLKB_POWER_UP)
10651 clock.p2 = 7;
10652 else
10653 clock.p2 = 14;
10654 } else {
10655 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10656 clock.p1 = 2;
10657 else {
10658 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10659 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10660 }
10661 if (dpll & PLL_P2_DIVIDE_BY_4)
10662 clock.p2 = 4;
10663 else
10664 clock.p2 = 2;
10665 }
10666
10667 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10668 }
10669
10670 /*
10671 * This value includes pixel_multiplier. We will use
10672 * port_clock to compute adjusted_mode.crtc_clock in the
10673 * encoder's get_config() function.
10674 */
10675 pipe_config->port_clock = port_clock;
10676 }
10677
10678 int intel_dotclock_calculate(int link_freq,
10679 const struct intel_link_m_n *m_n)
10680 {
10681 /*
10682 * The calculation for the data clock is:
10683 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10684 * But we want to avoid losing precison if possible, so:
10685 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10686 *
10687 * and the link clock is simpler:
10688 * link_clock = (m * link_clock) / n
10689 */
10690
10691 if (!m_n->link_n)
10692 return 0;
10693
10694 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10695 }
10696
10697 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10698 struct intel_crtc_state *pipe_config)
10699 {
10700 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
10701
10702 /* read out port_clock from the DPLL */
10703 i9xx_crtc_clock_get(crtc, pipe_config);
10704
10705 /*
10706 * In case there is an active pipe without active ports,
10707 * we may need some idea for the dotclock anyway.
10708 * Calculate one based on the FDI configuration.
10709 */
10710 pipe_config->base.adjusted_mode.crtc_clock =
10711 intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
10712 &pipe_config->fdi_m_n);
10713 }
10714
10715 /** Returns the currently programmed mode of the given pipe. */
10716 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10717 struct drm_crtc *crtc)
10718 {
10719 struct drm_i915_private *dev_priv = dev->dev_private;
10720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10721 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10722 struct drm_display_mode *mode;
10723 struct intel_crtc_state *pipe_config;
10724 int htot = I915_READ(HTOTAL(cpu_transcoder));
10725 int hsync = I915_READ(HSYNC(cpu_transcoder));
10726 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10727 int vsync = I915_READ(VSYNC(cpu_transcoder));
10728 enum pipe pipe = intel_crtc->pipe;
10729
10730 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10731 if (!mode)
10732 return NULL;
10733
10734 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10735 if (!pipe_config) {
10736 kfree(mode);
10737 return NULL;
10738 }
10739
10740 /*
10741 * Construct a pipe_config sufficient for getting the clock info
10742 * back out of crtc_clock_get.
10743 *
10744 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10745 * to use a real value here instead.
10746 */
10747 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10748 pipe_config->pixel_multiplier = 1;
10749 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10750 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10751 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10752 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10753
10754 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10755 mode->hdisplay = (htot & 0xffff) + 1;
10756 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10757 mode->hsync_start = (hsync & 0xffff) + 1;
10758 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10759 mode->vdisplay = (vtot & 0xffff) + 1;
10760 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10761 mode->vsync_start = (vsync & 0xffff) + 1;
10762 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10763
10764 drm_mode_set_name(mode);
10765
10766 kfree(pipe_config);
10767
10768 return mode;
10769 }
10770
10771 void intel_mark_busy(struct drm_device *dev)
10772 {
10773 struct drm_i915_private *dev_priv = dev->dev_private;
10774
10775 if (dev_priv->mm.busy)
10776 return;
10777
10778 intel_runtime_pm_get(dev_priv);
10779 i915_update_gfx_val(dev_priv);
10780 if (INTEL_INFO(dev)->gen >= 6)
10781 gen6_rps_busy(dev_priv);
10782 dev_priv->mm.busy = true;
10783 }
10784
10785 void intel_mark_idle(struct drm_device *dev)
10786 {
10787 struct drm_i915_private *dev_priv = dev->dev_private;
10788
10789 if (!dev_priv->mm.busy)
10790 return;
10791
10792 dev_priv->mm.busy = false;
10793
10794 if (INTEL_INFO(dev)->gen >= 6)
10795 gen6_rps_idle(dev->dev_private);
10796
10797 intel_runtime_pm_put(dev_priv);
10798 }
10799
10800 static void intel_crtc_destroy(struct drm_crtc *crtc)
10801 {
10802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10803 struct drm_device *dev = crtc->dev;
10804 struct intel_unpin_work *work;
10805
10806 spin_lock_irq(&dev->event_lock);
10807 work = intel_crtc->unpin_work;
10808 intel_crtc->unpin_work = NULL;
10809 spin_unlock_irq(&dev->event_lock);
10810
10811 if (work) {
10812 cancel_work_sync(&work->work);
10813 kfree(work);
10814 }
10815
10816 drm_crtc_cleanup(crtc);
10817
10818 kfree(intel_crtc);
10819 }
10820
10821 static void intel_unpin_work_fn(struct work_struct *__work)
10822 {
10823 struct intel_unpin_work *work =
10824 container_of(__work, struct intel_unpin_work, work);
10825 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10826 struct drm_device *dev = crtc->base.dev;
10827 struct drm_plane *primary = crtc->base.primary;
10828
10829 mutex_lock(&dev->struct_mutex);
10830 intel_unpin_fb_obj(work->old_fb, primary->state->rotation);
10831 drm_gem_object_unreference(&work->pending_flip_obj->base);
10832
10833 if (work->flip_queued_req)
10834 i915_gem_request_assign(&work->flip_queued_req, NULL);
10835 mutex_unlock(&dev->struct_mutex);
10836
10837 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10838 intel_fbc_post_update(crtc);
10839 drm_framebuffer_unreference(work->old_fb);
10840
10841 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10842 atomic_dec(&crtc->unpin_work_count);
10843
10844 kfree(work);
10845 }
10846
10847 static void do_intel_finish_page_flip(struct drm_device *dev,
10848 struct drm_crtc *crtc)
10849 {
10850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10851 struct intel_unpin_work *work;
10852 unsigned long flags;
10853
10854 /* Ignore early vblank irqs */
10855 if (intel_crtc == NULL)
10856 return;
10857
10858 /*
10859 * This is called both by irq handlers and the reset code (to complete
10860 * lost pageflips) so needs the full irqsave spinlocks.
10861 */
10862 spin_lock_irqsave(&dev->event_lock, flags);
10863 work = intel_crtc->unpin_work;
10864
10865 /* Ensure we don't miss a work->pending update ... */
10866 smp_rmb();
10867
10868 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10869 spin_unlock_irqrestore(&dev->event_lock, flags);
10870 return;
10871 }
10872
10873 page_flip_completed(intel_crtc);
10874
10875 spin_unlock_irqrestore(&dev->event_lock, flags);
10876 }
10877
10878 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10879 {
10880 struct drm_i915_private *dev_priv = dev->dev_private;
10881 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10882
10883 do_intel_finish_page_flip(dev, crtc);
10884 }
10885
10886 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10887 {
10888 struct drm_i915_private *dev_priv = dev->dev_private;
10889 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10890
10891 do_intel_finish_page_flip(dev, crtc);
10892 }
10893
10894 /* Is 'a' after or equal to 'b'? */
10895 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10896 {
10897 return !((a - b) & 0x80000000);
10898 }
10899
10900 static bool page_flip_finished(struct intel_crtc *crtc)
10901 {
10902 struct drm_device *dev = crtc->base.dev;
10903 struct drm_i915_private *dev_priv = dev->dev_private;
10904
10905 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10906 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10907 return true;
10908
10909 /*
10910 * The relevant registers doen't exist on pre-ctg.
10911 * As the flip done interrupt doesn't trigger for mmio
10912 * flips on gmch platforms, a flip count check isn't
10913 * really needed there. But since ctg has the registers,
10914 * include it in the check anyway.
10915 */
10916 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10917 return true;
10918
10919 /*
10920 * BDW signals flip done immediately if the plane
10921 * is disabled, even if the plane enable is already
10922 * armed to occur at the next vblank :(
10923 */
10924
10925 /*
10926 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10927 * used the same base address. In that case the mmio flip might
10928 * have completed, but the CS hasn't even executed the flip yet.
10929 *
10930 * A flip count check isn't enough as the CS might have updated
10931 * the base address just after start of vblank, but before we
10932 * managed to process the interrupt. This means we'd complete the
10933 * CS flip too soon.
10934 *
10935 * Combining both checks should get us a good enough result. It may
10936 * still happen that the CS flip has been executed, but has not
10937 * yet actually completed. But in case the base address is the same
10938 * anyway, we don't really care.
10939 */
10940 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10941 crtc->unpin_work->gtt_offset &&
10942 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10943 crtc->unpin_work->flip_count);
10944 }
10945
10946 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10947 {
10948 struct drm_i915_private *dev_priv = dev->dev_private;
10949 struct intel_crtc *intel_crtc =
10950 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10951 unsigned long flags;
10952
10953
10954 /*
10955 * This is called both by irq handlers and the reset code (to complete
10956 * lost pageflips) so needs the full irqsave spinlocks.
10957 *
10958 * NB: An MMIO update of the plane base pointer will also
10959 * generate a page-flip completion irq, i.e. every modeset
10960 * is also accompanied by a spurious intel_prepare_page_flip().
10961 */
10962 spin_lock_irqsave(&dev->event_lock, flags);
10963 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10964 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10965 spin_unlock_irqrestore(&dev->event_lock, flags);
10966 }
10967
10968 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10969 {
10970 /* Ensure that the work item is consistent when activating it ... */
10971 smp_wmb();
10972 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10973 /* and that it is marked active as soon as the irq could fire. */
10974 smp_wmb();
10975 }
10976
10977 static int intel_gen2_queue_flip(struct drm_device *dev,
10978 struct drm_crtc *crtc,
10979 struct drm_framebuffer *fb,
10980 struct drm_i915_gem_object *obj,
10981 struct drm_i915_gem_request *req,
10982 uint32_t flags)
10983 {
10984 struct intel_engine_cs *engine = req->engine;
10985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10986 u32 flip_mask;
10987 int ret;
10988
10989 ret = intel_ring_begin(req, 6);
10990 if (ret)
10991 return ret;
10992
10993 /* Can't queue multiple flips, so wait for the previous
10994 * one to finish before executing the next.
10995 */
10996 if (intel_crtc->plane)
10997 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10998 else
10999 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11000 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11001 intel_ring_emit(engine, MI_NOOP);
11002 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11003 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11004 intel_ring_emit(engine, fb->pitches[0]);
11005 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11006 intel_ring_emit(engine, 0); /* aux display base address, unused */
11007
11008 intel_mark_page_flip_active(intel_crtc->unpin_work);
11009 return 0;
11010 }
11011
11012 static int intel_gen3_queue_flip(struct drm_device *dev,
11013 struct drm_crtc *crtc,
11014 struct drm_framebuffer *fb,
11015 struct drm_i915_gem_object *obj,
11016 struct drm_i915_gem_request *req,
11017 uint32_t flags)
11018 {
11019 struct intel_engine_cs *engine = req->engine;
11020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11021 u32 flip_mask;
11022 int ret;
11023
11024 ret = intel_ring_begin(req, 6);
11025 if (ret)
11026 return ret;
11027
11028 if (intel_crtc->plane)
11029 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11030 else
11031 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11032 intel_ring_emit(engine, MI_WAIT_FOR_EVENT | flip_mask);
11033 intel_ring_emit(engine, MI_NOOP);
11034 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 |
11035 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11036 intel_ring_emit(engine, fb->pitches[0]);
11037 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11038 intel_ring_emit(engine, MI_NOOP);
11039
11040 intel_mark_page_flip_active(intel_crtc->unpin_work);
11041 return 0;
11042 }
11043
11044 static int intel_gen4_queue_flip(struct drm_device *dev,
11045 struct drm_crtc *crtc,
11046 struct drm_framebuffer *fb,
11047 struct drm_i915_gem_object *obj,
11048 struct drm_i915_gem_request *req,
11049 uint32_t flags)
11050 {
11051 struct intel_engine_cs *engine = req->engine;
11052 struct drm_i915_private *dev_priv = dev->dev_private;
11053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11054 uint32_t pf, pipesrc;
11055 int ret;
11056
11057 ret = intel_ring_begin(req, 4);
11058 if (ret)
11059 return ret;
11060
11061 /* i965+ uses the linear or tiled offsets from the
11062 * Display Registers (which do not change across a page-flip)
11063 * so we need only reprogram the base address.
11064 */
11065 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11066 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11067 intel_ring_emit(engine, fb->pitches[0]);
11068 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset |
11069 obj->tiling_mode);
11070
11071 /* XXX Enabling the panel-fitter across page-flip is so far
11072 * untested on non-native modes, so ignore it for now.
11073 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11074 */
11075 pf = 0;
11076 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11077 intel_ring_emit(engine, pf | pipesrc);
11078
11079 intel_mark_page_flip_active(intel_crtc->unpin_work);
11080 return 0;
11081 }
11082
11083 static int intel_gen6_queue_flip(struct drm_device *dev,
11084 struct drm_crtc *crtc,
11085 struct drm_framebuffer *fb,
11086 struct drm_i915_gem_object *obj,
11087 struct drm_i915_gem_request *req,
11088 uint32_t flags)
11089 {
11090 struct intel_engine_cs *engine = req->engine;
11091 struct drm_i915_private *dev_priv = dev->dev_private;
11092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11093 uint32_t pf, pipesrc;
11094 int ret;
11095
11096 ret = intel_ring_begin(req, 4);
11097 if (ret)
11098 return ret;
11099
11100 intel_ring_emit(engine, MI_DISPLAY_FLIP |
11101 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11102 intel_ring_emit(engine, fb->pitches[0] | obj->tiling_mode);
11103 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11104
11105 /* Contrary to the suggestions in the documentation,
11106 * "Enable Panel Fitter" does not seem to be required when page
11107 * flipping with a non-native mode, and worse causes a normal
11108 * modeset to fail.
11109 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11110 */
11111 pf = 0;
11112 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11113 intel_ring_emit(engine, pf | pipesrc);
11114
11115 intel_mark_page_flip_active(intel_crtc->unpin_work);
11116 return 0;
11117 }
11118
11119 static int intel_gen7_queue_flip(struct drm_device *dev,
11120 struct drm_crtc *crtc,
11121 struct drm_framebuffer *fb,
11122 struct drm_i915_gem_object *obj,
11123 struct drm_i915_gem_request *req,
11124 uint32_t flags)
11125 {
11126 struct intel_engine_cs *engine = req->engine;
11127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11128 uint32_t plane_bit = 0;
11129 int len, ret;
11130
11131 switch (intel_crtc->plane) {
11132 case PLANE_A:
11133 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11134 break;
11135 case PLANE_B:
11136 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11137 break;
11138 case PLANE_C:
11139 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11140 break;
11141 default:
11142 WARN_ONCE(1, "unknown plane in flip command\n");
11143 return -ENODEV;
11144 }
11145
11146 len = 4;
11147 if (engine->id == RCS) {
11148 len += 6;
11149 /*
11150 * On Gen 8, SRM is now taking an extra dword to accommodate
11151 * 48bits addresses, and we need a NOOP for the batch size to
11152 * stay even.
11153 */
11154 if (IS_GEN8(dev))
11155 len += 2;
11156 }
11157
11158 /*
11159 * BSpec MI_DISPLAY_FLIP for IVB:
11160 * "The full packet must be contained within the same cache line."
11161 *
11162 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11163 * cacheline, if we ever start emitting more commands before
11164 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11165 * then do the cacheline alignment, and finally emit the
11166 * MI_DISPLAY_FLIP.
11167 */
11168 ret = intel_ring_cacheline_align(req);
11169 if (ret)
11170 return ret;
11171
11172 ret = intel_ring_begin(req, len);
11173 if (ret)
11174 return ret;
11175
11176 /* Unmask the flip-done completion message. Note that the bspec says that
11177 * we should do this for both the BCS and RCS, and that we must not unmask
11178 * more than one flip event at any time (or ensure that one flip message
11179 * can be sent by waiting for flip-done prior to queueing new flips).
11180 * Experimentation says that BCS works despite DERRMR masking all
11181 * flip-done completion events and that unmasking all planes at once
11182 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11183 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11184 */
11185 if (engine->id == RCS) {
11186 intel_ring_emit(engine, MI_LOAD_REGISTER_IMM(1));
11187 intel_ring_emit_reg(engine, DERRMR);
11188 intel_ring_emit(engine, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11189 DERRMR_PIPEB_PRI_FLIP_DONE |
11190 DERRMR_PIPEC_PRI_FLIP_DONE));
11191 if (IS_GEN8(dev))
11192 intel_ring_emit(engine, MI_STORE_REGISTER_MEM_GEN8 |
11193 MI_SRM_LRM_GLOBAL_GTT);
11194 else
11195 intel_ring_emit(engine, MI_STORE_REGISTER_MEM |
11196 MI_SRM_LRM_GLOBAL_GTT);
11197 intel_ring_emit_reg(engine, DERRMR);
11198 intel_ring_emit(engine, engine->scratch.gtt_offset + 256);
11199 if (IS_GEN8(dev)) {
11200 intel_ring_emit(engine, 0);
11201 intel_ring_emit(engine, MI_NOOP);
11202 }
11203 }
11204
11205 intel_ring_emit(engine, MI_DISPLAY_FLIP_I915 | plane_bit);
11206 intel_ring_emit(engine, (fb->pitches[0] | obj->tiling_mode));
11207 intel_ring_emit(engine, intel_crtc->unpin_work->gtt_offset);
11208 intel_ring_emit(engine, (MI_NOOP));
11209
11210 intel_mark_page_flip_active(intel_crtc->unpin_work);
11211 return 0;
11212 }
11213
11214 static bool use_mmio_flip(struct intel_engine_cs *engine,
11215 struct drm_i915_gem_object *obj)
11216 {
11217 /*
11218 * This is not being used for older platforms, because
11219 * non-availability of flip done interrupt forces us to use
11220 * CS flips. Older platforms derive flip done using some clever
11221 * tricks involving the flip_pending status bits and vblank irqs.
11222 * So using MMIO flips there would disrupt this mechanism.
11223 */
11224
11225 if (engine == NULL)
11226 return true;
11227
11228 if (INTEL_INFO(engine->dev)->gen < 5)
11229 return false;
11230
11231 if (i915.use_mmio_flip < 0)
11232 return false;
11233 else if (i915.use_mmio_flip > 0)
11234 return true;
11235 else if (i915.enable_execlists)
11236 return true;
11237 else if (obj->base.dma_buf &&
11238 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11239 false))
11240 return true;
11241 else
11242 return engine != i915_gem_request_get_engine(obj->last_write_req);
11243 }
11244
11245 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11246 unsigned int rotation,
11247 struct intel_unpin_work *work)
11248 {
11249 struct drm_device *dev = intel_crtc->base.dev;
11250 struct drm_i915_private *dev_priv = dev->dev_private;
11251 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11252 const enum pipe pipe = intel_crtc->pipe;
11253 u32 ctl, stride, tile_height;
11254
11255 ctl = I915_READ(PLANE_CTL(pipe, 0));
11256 ctl &= ~PLANE_CTL_TILED_MASK;
11257 switch (fb->modifier[0]) {
11258 case DRM_FORMAT_MOD_NONE:
11259 break;
11260 case I915_FORMAT_MOD_X_TILED:
11261 ctl |= PLANE_CTL_TILED_X;
11262 break;
11263 case I915_FORMAT_MOD_Y_TILED:
11264 ctl |= PLANE_CTL_TILED_Y;
11265 break;
11266 case I915_FORMAT_MOD_Yf_TILED:
11267 ctl |= PLANE_CTL_TILED_YF;
11268 break;
11269 default:
11270 MISSING_CASE(fb->modifier[0]);
11271 }
11272
11273 /*
11274 * The stride is either expressed as a multiple of 64 bytes chunks for
11275 * linear buffers or in number of tiles for tiled buffers.
11276 */
11277 if (intel_rotation_90_or_270(rotation)) {
11278 /* stride = Surface height in tiles */
11279 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11280 stride = DIV_ROUND_UP(fb->height, tile_height);
11281 } else {
11282 stride = fb->pitches[0] /
11283 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11284 fb->pixel_format);
11285 }
11286
11287 /*
11288 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11289 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11290 */
11291 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11292 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11293
11294 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11295 POSTING_READ(PLANE_SURF(pipe, 0));
11296 }
11297
11298 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11299 struct intel_unpin_work *work)
11300 {
11301 struct drm_device *dev = intel_crtc->base.dev;
11302 struct drm_i915_private *dev_priv = dev->dev_private;
11303 struct intel_framebuffer *intel_fb =
11304 to_intel_framebuffer(intel_crtc->base.primary->fb);
11305 struct drm_i915_gem_object *obj = intel_fb->obj;
11306 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11307 u32 dspcntr;
11308
11309 dspcntr = I915_READ(reg);
11310
11311 if (obj->tiling_mode != I915_TILING_NONE)
11312 dspcntr |= DISPPLANE_TILED;
11313 else
11314 dspcntr &= ~DISPPLANE_TILED;
11315
11316 I915_WRITE(reg, dspcntr);
11317
11318 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11319 POSTING_READ(DSPSURF(intel_crtc->plane));
11320 }
11321
11322 /*
11323 * XXX: This is the temporary way to update the plane registers until we get
11324 * around to using the usual plane update functions for MMIO flips
11325 */
11326 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11327 {
11328 struct intel_crtc *crtc = mmio_flip->crtc;
11329 struct intel_unpin_work *work;
11330
11331 spin_lock_irq(&crtc->base.dev->event_lock);
11332 work = crtc->unpin_work;
11333 spin_unlock_irq(&crtc->base.dev->event_lock);
11334 if (work == NULL)
11335 return;
11336
11337 intel_mark_page_flip_active(work);
11338
11339 intel_pipe_update_start(crtc);
11340
11341 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11342 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11343 else
11344 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11345 ilk_do_mmio_flip(crtc, work);
11346
11347 intel_pipe_update_end(crtc);
11348 }
11349
11350 static void intel_mmio_flip_work_func(struct work_struct *work)
11351 {
11352 struct intel_mmio_flip *mmio_flip =
11353 container_of(work, struct intel_mmio_flip, work);
11354 struct intel_framebuffer *intel_fb =
11355 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11356 struct drm_i915_gem_object *obj = intel_fb->obj;
11357
11358 if (mmio_flip->req) {
11359 WARN_ON(__i915_wait_request(mmio_flip->req,
11360 mmio_flip->crtc->reset_counter,
11361 false, NULL,
11362 &mmio_flip->i915->rps.mmioflips));
11363 i915_gem_request_unreference__unlocked(mmio_flip->req);
11364 }
11365
11366 /* For framebuffer backed by dmabuf, wait for fence */
11367 if (obj->base.dma_buf)
11368 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11369 false, false,
11370 MAX_SCHEDULE_TIMEOUT) < 0);
11371
11372 intel_do_mmio_flip(mmio_flip);
11373 kfree(mmio_flip);
11374 }
11375
11376 static int intel_queue_mmio_flip(struct drm_device *dev,
11377 struct drm_crtc *crtc,
11378 struct drm_i915_gem_object *obj)
11379 {
11380 struct intel_mmio_flip *mmio_flip;
11381
11382 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11383 if (mmio_flip == NULL)
11384 return -ENOMEM;
11385
11386 mmio_flip->i915 = to_i915(dev);
11387 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11388 mmio_flip->crtc = to_intel_crtc(crtc);
11389 mmio_flip->rotation = crtc->primary->state->rotation;
11390
11391 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11392 schedule_work(&mmio_flip->work);
11393
11394 return 0;
11395 }
11396
11397 static int intel_default_queue_flip(struct drm_device *dev,
11398 struct drm_crtc *crtc,
11399 struct drm_framebuffer *fb,
11400 struct drm_i915_gem_object *obj,
11401 struct drm_i915_gem_request *req,
11402 uint32_t flags)
11403 {
11404 return -ENODEV;
11405 }
11406
11407 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11408 struct drm_crtc *crtc)
11409 {
11410 struct drm_i915_private *dev_priv = dev->dev_private;
11411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11412 struct intel_unpin_work *work = intel_crtc->unpin_work;
11413 u32 addr;
11414
11415 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11416 return true;
11417
11418 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11419 return false;
11420
11421 if (!work->enable_stall_check)
11422 return false;
11423
11424 if (work->flip_ready_vblank == 0) {
11425 if (work->flip_queued_req &&
11426 !i915_gem_request_completed(work->flip_queued_req, true))
11427 return false;
11428
11429 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11430 }
11431
11432 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11433 return false;
11434
11435 /* Potential stall - if we see that the flip has happened,
11436 * assume a missed interrupt. */
11437 if (INTEL_INFO(dev)->gen >= 4)
11438 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11439 else
11440 addr = I915_READ(DSPADDR(intel_crtc->plane));
11441
11442 /* There is a potential issue here with a false positive after a flip
11443 * to the same address. We could address this by checking for a
11444 * non-incrementing frame counter.
11445 */
11446 return addr == work->gtt_offset;
11447 }
11448
11449 void intel_check_page_flip(struct drm_device *dev, int pipe)
11450 {
11451 struct drm_i915_private *dev_priv = dev->dev_private;
11452 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11454 struct intel_unpin_work *work;
11455
11456 WARN_ON(!in_interrupt());
11457
11458 if (crtc == NULL)
11459 return;
11460
11461 spin_lock(&dev->event_lock);
11462 work = intel_crtc->unpin_work;
11463 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11464 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11465 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11466 page_flip_completed(intel_crtc);
11467 work = NULL;
11468 }
11469 if (work != NULL &&
11470 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11471 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11472 spin_unlock(&dev->event_lock);
11473 }
11474
11475 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11476 struct drm_framebuffer *fb,
11477 struct drm_pending_vblank_event *event,
11478 uint32_t page_flip_flags)
11479 {
11480 struct drm_device *dev = crtc->dev;
11481 struct drm_i915_private *dev_priv = dev->dev_private;
11482 struct drm_framebuffer *old_fb = crtc->primary->fb;
11483 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11485 struct drm_plane *primary = crtc->primary;
11486 enum pipe pipe = intel_crtc->pipe;
11487 struct intel_unpin_work *work;
11488 struct intel_engine_cs *engine;
11489 bool mmio_flip;
11490 struct drm_i915_gem_request *request = NULL;
11491 int ret;
11492
11493 /*
11494 * drm_mode_page_flip_ioctl() should already catch this, but double
11495 * check to be safe. In the future we may enable pageflipping from
11496 * a disabled primary plane.
11497 */
11498 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11499 return -EBUSY;
11500
11501 /* Can't change pixel format via MI display flips. */
11502 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11503 return -EINVAL;
11504
11505 /*
11506 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11507 * Note that pitch changes could also affect these register.
11508 */
11509 if (INTEL_INFO(dev)->gen > 3 &&
11510 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11511 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11512 return -EINVAL;
11513
11514 if (i915_terminally_wedged(&dev_priv->gpu_error))
11515 goto out_hang;
11516
11517 work = kzalloc(sizeof(*work), GFP_KERNEL);
11518 if (work == NULL)
11519 return -ENOMEM;
11520
11521 work->event = event;
11522 work->crtc = crtc;
11523 work->old_fb = old_fb;
11524 INIT_WORK(&work->work, intel_unpin_work_fn);
11525
11526 ret = drm_crtc_vblank_get(crtc);
11527 if (ret)
11528 goto free_work;
11529
11530 /* We borrow the event spin lock for protecting unpin_work */
11531 spin_lock_irq(&dev->event_lock);
11532 if (intel_crtc->unpin_work) {
11533 /* Before declaring the flip queue wedged, check if
11534 * the hardware completed the operation behind our backs.
11535 */
11536 if (__intel_pageflip_stall_check(dev, crtc)) {
11537 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11538 page_flip_completed(intel_crtc);
11539 } else {
11540 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11541 spin_unlock_irq(&dev->event_lock);
11542
11543 drm_crtc_vblank_put(crtc);
11544 kfree(work);
11545 return -EBUSY;
11546 }
11547 }
11548 intel_crtc->unpin_work = work;
11549 spin_unlock_irq(&dev->event_lock);
11550
11551 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11552 flush_workqueue(dev_priv->wq);
11553
11554 /* Reference the objects for the scheduled work. */
11555 drm_framebuffer_reference(work->old_fb);
11556 drm_gem_object_reference(&obj->base);
11557
11558 crtc->primary->fb = fb;
11559 update_state_fb(crtc->primary);
11560 intel_fbc_pre_update(intel_crtc);
11561
11562 work->pending_flip_obj = obj;
11563
11564 ret = i915_mutex_lock_interruptible(dev);
11565 if (ret)
11566 goto cleanup;
11567
11568 atomic_inc(&intel_crtc->unpin_work_count);
11569 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11570
11571 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11572 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11573
11574 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11575 engine = &dev_priv->engine[BCS];
11576 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11577 /* vlv: DISPLAY_FLIP fails to change tiling */
11578 engine = NULL;
11579 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11580 engine = &dev_priv->engine[BCS];
11581 } else if (INTEL_INFO(dev)->gen >= 7) {
11582 engine = i915_gem_request_get_engine(obj->last_write_req);
11583 if (engine == NULL || engine->id != RCS)
11584 engine = &dev_priv->engine[BCS];
11585 } else {
11586 engine = &dev_priv->engine[RCS];
11587 }
11588
11589 mmio_flip = use_mmio_flip(engine, obj);
11590
11591 /* When using CS flips, we want to emit semaphores between rings.
11592 * However, when using mmio flips we will create a task to do the
11593 * synchronisation, so all we want here is to pin the framebuffer
11594 * into the display plane and skip any waits.
11595 */
11596 if (!mmio_flip) {
11597 ret = i915_gem_object_sync(obj, engine, &request);
11598 if (ret)
11599 goto cleanup_pending;
11600 }
11601
11602 ret = intel_pin_and_fence_fb_obj(fb, primary->state->rotation);
11603 if (ret)
11604 goto cleanup_pending;
11605
11606 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11607 obj, 0);
11608 work->gtt_offset += intel_crtc->dspaddr_offset;
11609
11610 if (mmio_flip) {
11611 ret = intel_queue_mmio_flip(dev, crtc, obj);
11612 if (ret)
11613 goto cleanup_unpin;
11614
11615 i915_gem_request_assign(&work->flip_queued_req,
11616 obj->last_write_req);
11617 } else {
11618 if (!request) {
11619 request = i915_gem_request_alloc(engine, NULL);
11620 if (IS_ERR(request)) {
11621 ret = PTR_ERR(request);
11622 goto cleanup_unpin;
11623 }
11624 }
11625
11626 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11627 page_flip_flags);
11628 if (ret)
11629 goto cleanup_unpin;
11630
11631 i915_gem_request_assign(&work->flip_queued_req, request);
11632 }
11633
11634 if (request)
11635 i915_add_request_no_flush(request);
11636
11637 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11638 work->enable_stall_check = true;
11639
11640 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11641 to_intel_plane(primary)->frontbuffer_bit);
11642 mutex_unlock(&dev->struct_mutex);
11643
11644 intel_frontbuffer_flip_prepare(dev,
11645 to_intel_plane(primary)->frontbuffer_bit);
11646
11647 trace_i915_flip_request(intel_crtc->plane, obj);
11648
11649 return 0;
11650
11651 cleanup_unpin:
11652 intel_unpin_fb_obj(fb, crtc->primary->state->rotation);
11653 cleanup_pending:
11654 if (!IS_ERR_OR_NULL(request))
11655 i915_gem_request_cancel(request);
11656 atomic_dec(&intel_crtc->unpin_work_count);
11657 mutex_unlock(&dev->struct_mutex);
11658 cleanup:
11659 crtc->primary->fb = old_fb;
11660 update_state_fb(crtc->primary);
11661
11662 drm_gem_object_unreference_unlocked(&obj->base);
11663 drm_framebuffer_unreference(work->old_fb);
11664
11665 spin_lock_irq(&dev->event_lock);
11666 intel_crtc->unpin_work = NULL;
11667 spin_unlock_irq(&dev->event_lock);
11668
11669 drm_crtc_vblank_put(crtc);
11670 free_work:
11671 kfree(work);
11672
11673 if (ret == -EIO) {
11674 struct drm_atomic_state *state;
11675 struct drm_plane_state *plane_state;
11676
11677 out_hang:
11678 state = drm_atomic_state_alloc(dev);
11679 if (!state)
11680 return -ENOMEM;
11681 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11682
11683 retry:
11684 plane_state = drm_atomic_get_plane_state(state, primary);
11685 ret = PTR_ERR_OR_ZERO(plane_state);
11686 if (!ret) {
11687 drm_atomic_set_fb_for_plane(plane_state, fb);
11688
11689 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11690 if (!ret)
11691 ret = drm_atomic_commit(state);
11692 }
11693
11694 if (ret == -EDEADLK) {
11695 drm_modeset_backoff(state->acquire_ctx);
11696 drm_atomic_state_clear(state);
11697 goto retry;
11698 }
11699
11700 if (ret)
11701 drm_atomic_state_free(state);
11702
11703 if (ret == 0 && event) {
11704 spin_lock_irq(&dev->event_lock);
11705 drm_send_vblank_event(dev, pipe, event);
11706 spin_unlock_irq(&dev->event_lock);
11707 }
11708 }
11709 return ret;
11710 }
11711
11712
11713 /**
11714 * intel_wm_need_update - Check whether watermarks need updating
11715 * @plane: drm plane
11716 * @state: new plane state
11717 *
11718 * Check current plane state versus the new one to determine whether
11719 * watermarks need to be recalculated.
11720 *
11721 * Returns true or false.
11722 */
11723 static bool intel_wm_need_update(struct drm_plane *plane,
11724 struct drm_plane_state *state)
11725 {
11726 struct intel_plane_state *new = to_intel_plane_state(state);
11727 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11728
11729 /* Update watermarks on tiling or size changes. */
11730 if (new->visible != cur->visible)
11731 return true;
11732
11733 if (!cur->base.fb || !new->base.fb)
11734 return false;
11735
11736 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11737 cur->base.rotation != new->base.rotation ||
11738 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11739 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11740 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11741 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11742 return true;
11743
11744 return false;
11745 }
11746
11747 static bool needs_scaling(struct intel_plane_state *state)
11748 {
11749 int src_w = drm_rect_width(&state->src) >> 16;
11750 int src_h = drm_rect_height(&state->src) >> 16;
11751 int dst_w = drm_rect_width(&state->dst);
11752 int dst_h = drm_rect_height(&state->dst);
11753
11754 return (src_w != dst_w || src_h != dst_h);
11755 }
11756
11757 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11758 struct drm_plane_state *plane_state)
11759 {
11760 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11761 struct drm_crtc *crtc = crtc_state->crtc;
11762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11763 struct drm_plane *plane = plane_state->plane;
11764 struct drm_device *dev = crtc->dev;
11765 struct drm_i915_private *dev_priv = to_i915(dev);
11766 struct intel_plane_state *old_plane_state =
11767 to_intel_plane_state(plane->state);
11768 int idx = intel_crtc->base.base.id, ret;
11769 bool mode_changed = needs_modeset(crtc_state);
11770 bool was_crtc_enabled = crtc->state->active;
11771 bool is_crtc_enabled = crtc_state->active;
11772 bool turn_off, turn_on, visible, was_visible;
11773 struct drm_framebuffer *fb = plane_state->fb;
11774
11775 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11776 plane->type != DRM_PLANE_TYPE_CURSOR) {
11777 ret = skl_update_scaler_plane(
11778 to_intel_crtc_state(crtc_state),
11779 to_intel_plane_state(plane_state));
11780 if (ret)
11781 return ret;
11782 }
11783
11784 was_visible = old_plane_state->visible;
11785 visible = to_intel_plane_state(plane_state)->visible;
11786
11787 if (!was_crtc_enabled && WARN_ON(was_visible))
11788 was_visible = false;
11789
11790 /*
11791 * Visibility is calculated as if the crtc was on, but
11792 * after scaler setup everything depends on it being off
11793 * when the crtc isn't active.
11794 */
11795 if (!is_crtc_enabled)
11796 to_intel_plane_state(plane_state)->visible = visible = false;
11797
11798 if (!was_visible && !visible)
11799 return 0;
11800
11801 if (fb != old_plane_state->base.fb)
11802 pipe_config->fb_changed = true;
11803
11804 turn_off = was_visible && (!visible || mode_changed);
11805 turn_on = visible && (!was_visible || mode_changed);
11806
11807 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11808 plane->base.id, fb ? fb->base.id : -1);
11809
11810 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11811 plane->base.id, was_visible, visible,
11812 turn_off, turn_on, mode_changed);
11813
11814 if (turn_on) {
11815 pipe_config->update_wm_pre = true;
11816
11817 /* must disable cxsr around plane enable/disable */
11818 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11819 pipe_config->disable_cxsr = true;
11820 } else if (turn_off) {
11821 pipe_config->update_wm_post = true;
11822
11823 /* must disable cxsr around plane enable/disable */
11824 if (plane->type != DRM_PLANE_TYPE_CURSOR)
11825 pipe_config->disable_cxsr = true;
11826 } else if (intel_wm_need_update(plane, plane_state)) {
11827 /* FIXME bollocks */
11828 pipe_config->update_wm_pre = true;
11829 pipe_config->update_wm_post = true;
11830 }
11831
11832 /* Pre-gen9 platforms need two-step watermark updates */
11833 if ((pipe_config->update_wm_pre || pipe_config->update_wm_post) &&
11834 INTEL_INFO(dev)->gen < 9 && dev_priv->display.optimize_watermarks)
11835 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11836
11837 if (visible || was_visible)
11838 pipe_config->fb_bits |= to_intel_plane(plane)->frontbuffer_bit;
11839
11840 /*
11841 * WaCxSRDisabledForSpriteScaling:ivb
11842 *
11843 * cstate->update_wm was already set above, so this flag will
11844 * take effect when we commit and program watermarks.
11845 */
11846 if (plane->type == DRM_PLANE_TYPE_OVERLAY && IS_IVYBRIDGE(dev) &&
11847 needs_scaling(to_intel_plane_state(plane_state)) &&
11848 !needs_scaling(old_plane_state))
11849 pipe_config->disable_lp_wm = true;
11850
11851 return 0;
11852 }
11853
11854 static bool encoders_cloneable(const struct intel_encoder *a,
11855 const struct intel_encoder *b)
11856 {
11857 /* masks could be asymmetric, so check both ways */
11858 return a == b || (a->cloneable & (1 << b->type) &&
11859 b->cloneable & (1 << a->type));
11860 }
11861
11862 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11863 struct intel_crtc *crtc,
11864 struct intel_encoder *encoder)
11865 {
11866 struct intel_encoder *source_encoder;
11867 struct drm_connector *connector;
11868 struct drm_connector_state *connector_state;
11869 int i;
11870
11871 for_each_connector_in_state(state, connector, connector_state, i) {
11872 if (connector_state->crtc != &crtc->base)
11873 continue;
11874
11875 source_encoder =
11876 to_intel_encoder(connector_state->best_encoder);
11877 if (!encoders_cloneable(encoder, source_encoder))
11878 return false;
11879 }
11880
11881 return true;
11882 }
11883
11884 static bool check_encoder_cloning(struct drm_atomic_state *state,
11885 struct intel_crtc *crtc)
11886 {
11887 struct intel_encoder *encoder;
11888 struct drm_connector *connector;
11889 struct drm_connector_state *connector_state;
11890 int i;
11891
11892 for_each_connector_in_state(state, connector, connector_state, i) {
11893 if (connector_state->crtc != &crtc->base)
11894 continue;
11895
11896 encoder = to_intel_encoder(connector_state->best_encoder);
11897 if (!check_single_encoder_cloning(state, crtc, encoder))
11898 return false;
11899 }
11900
11901 return true;
11902 }
11903
11904 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11905 struct drm_crtc_state *crtc_state)
11906 {
11907 struct drm_device *dev = crtc->dev;
11908 struct drm_i915_private *dev_priv = dev->dev_private;
11909 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11910 struct intel_crtc_state *pipe_config =
11911 to_intel_crtc_state(crtc_state);
11912 struct drm_atomic_state *state = crtc_state->state;
11913 int ret;
11914 bool mode_changed = needs_modeset(crtc_state);
11915
11916 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11917 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11918 return -EINVAL;
11919 }
11920
11921 if (mode_changed && !crtc_state->active)
11922 pipe_config->update_wm_post = true;
11923
11924 if (mode_changed && crtc_state->enable &&
11925 dev_priv->display.crtc_compute_clock &&
11926 !WARN_ON(pipe_config->shared_dpll)) {
11927 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11928 pipe_config);
11929 if (ret)
11930 return ret;
11931 }
11932
11933 if (crtc_state->color_mgmt_changed) {
11934 ret = intel_color_check(crtc, crtc_state);
11935 if (ret)
11936 return ret;
11937 }
11938
11939 ret = 0;
11940 if (dev_priv->display.compute_pipe_wm) {
11941 ret = dev_priv->display.compute_pipe_wm(pipe_config);
11942 if (ret) {
11943 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
11944 return ret;
11945 }
11946 }
11947
11948 if (dev_priv->display.compute_intermediate_wm &&
11949 !to_intel_atomic_state(state)->skip_intermediate_wm) {
11950 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
11951 return 0;
11952
11953 /*
11954 * Calculate 'intermediate' watermarks that satisfy both the
11955 * old state and the new state. We can program these
11956 * immediately.
11957 */
11958 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
11959 intel_crtc,
11960 pipe_config);
11961 if (ret) {
11962 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
11963 return ret;
11964 }
11965 }
11966
11967 if (INTEL_INFO(dev)->gen >= 9) {
11968 if (mode_changed)
11969 ret = skl_update_scaler_crtc(pipe_config);
11970
11971 if (!ret)
11972 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11973 pipe_config);
11974 }
11975
11976 return ret;
11977 }
11978
11979 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11980 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11981 .atomic_begin = intel_begin_crtc_commit,
11982 .atomic_flush = intel_finish_crtc_commit,
11983 .atomic_check = intel_crtc_atomic_check,
11984 };
11985
11986 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11987 {
11988 struct intel_connector *connector;
11989
11990 for_each_intel_connector(dev, connector) {
11991 if (connector->base.encoder) {
11992 connector->base.state->best_encoder =
11993 connector->base.encoder;
11994 connector->base.state->crtc =
11995 connector->base.encoder->crtc;
11996 } else {
11997 connector->base.state->best_encoder = NULL;
11998 connector->base.state->crtc = NULL;
11999 }
12000 }
12001 }
12002
12003 static void
12004 connected_sink_compute_bpp(struct intel_connector *connector,
12005 struct intel_crtc_state *pipe_config)
12006 {
12007 int bpp = pipe_config->pipe_bpp;
12008
12009 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12010 connector->base.base.id,
12011 connector->base.name);
12012
12013 /* Don't use an invalid EDID bpc value */
12014 if (connector->base.display_info.bpc &&
12015 connector->base.display_info.bpc * 3 < bpp) {
12016 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12017 bpp, connector->base.display_info.bpc*3);
12018 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12019 }
12020
12021 /* Clamp bpp to default limit on screens without EDID 1.4 */
12022 if (connector->base.display_info.bpc == 0) {
12023 int type = connector->base.connector_type;
12024 int clamp_bpp = 24;
12025
12026 /* Fall back to 18 bpp when DP sink capability is unknown. */
12027 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12028 type == DRM_MODE_CONNECTOR_eDP)
12029 clamp_bpp = 18;
12030
12031 if (bpp > clamp_bpp) {
12032 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12033 bpp, clamp_bpp);
12034 pipe_config->pipe_bpp = clamp_bpp;
12035 }
12036 }
12037 }
12038
12039 static int
12040 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12041 struct intel_crtc_state *pipe_config)
12042 {
12043 struct drm_device *dev = crtc->base.dev;
12044 struct drm_atomic_state *state;
12045 struct drm_connector *connector;
12046 struct drm_connector_state *connector_state;
12047 int bpp, i;
12048
12049 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12050 bpp = 10*3;
12051 else if (INTEL_INFO(dev)->gen >= 5)
12052 bpp = 12*3;
12053 else
12054 bpp = 8*3;
12055
12056
12057 pipe_config->pipe_bpp = bpp;
12058
12059 state = pipe_config->base.state;
12060
12061 /* Clamp display bpp to EDID value */
12062 for_each_connector_in_state(state, connector, connector_state, i) {
12063 if (connector_state->crtc != &crtc->base)
12064 continue;
12065
12066 connected_sink_compute_bpp(to_intel_connector(connector),
12067 pipe_config);
12068 }
12069
12070 return bpp;
12071 }
12072
12073 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12074 {
12075 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12076 "type: 0x%x flags: 0x%x\n",
12077 mode->crtc_clock,
12078 mode->crtc_hdisplay, mode->crtc_hsync_start,
12079 mode->crtc_hsync_end, mode->crtc_htotal,
12080 mode->crtc_vdisplay, mode->crtc_vsync_start,
12081 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12082 }
12083
12084 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12085 struct intel_crtc_state *pipe_config,
12086 const char *context)
12087 {
12088 struct drm_device *dev = crtc->base.dev;
12089 struct drm_plane *plane;
12090 struct intel_plane *intel_plane;
12091 struct intel_plane_state *state;
12092 struct drm_framebuffer *fb;
12093
12094 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12095 context, pipe_config, pipe_name(crtc->pipe));
12096
12097 DRM_DEBUG_KMS("cpu_transcoder: %s\n", transcoder_name(pipe_config->cpu_transcoder));
12098 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12099 pipe_config->pipe_bpp, pipe_config->dither);
12100 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12101 pipe_config->has_pch_encoder,
12102 pipe_config->fdi_lanes,
12103 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12104 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12105 pipe_config->fdi_m_n.tu);
12106 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12107 pipe_config->has_dp_encoder,
12108 pipe_config->lane_count,
12109 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12110 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12111 pipe_config->dp_m_n.tu);
12112
12113 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12114 pipe_config->has_dp_encoder,
12115 pipe_config->lane_count,
12116 pipe_config->dp_m2_n2.gmch_m,
12117 pipe_config->dp_m2_n2.gmch_n,
12118 pipe_config->dp_m2_n2.link_m,
12119 pipe_config->dp_m2_n2.link_n,
12120 pipe_config->dp_m2_n2.tu);
12121
12122 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12123 pipe_config->has_audio,
12124 pipe_config->has_infoframe);
12125
12126 DRM_DEBUG_KMS("requested mode:\n");
12127 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12128 DRM_DEBUG_KMS("adjusted mode:\n");
12129 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12130 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12131 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12132 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12133 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12134 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12135 crtc->num_scalers,
12136 pipe_config->scaler_state.scaler_users,
12137 pipe_config->scaler_state.scaler_id);
12138 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12139 pipe_config->gmch_pfit.control,
12140 pipe_config->gmch_pfit.pgm_ratios,
12141 pipe_config->gmch_pfit.lvds_border_bits);
12142 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12143 pipe_config->pch_pfit.pos,
12144 pipe_config->pch_pfit.size,
12145 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12146 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12147 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12148
12149 if (IS_BROXTON(dev)) {
12150 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12151 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12152 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12153 pipe_config->ddi_pll_sel,
12154 pipe_config->dpll_hw_state.ebb0,
12155 pipe_config->dpll_hw_state.ebb4,
12156 pipe_config->dpll_hw_state.pll0,
12157 pipe_config->dpll_hw_state.pll1,
12158 pipe_config->dpll_hw_state.pll2,
12159 pipe_config->dpll_hw_state.pll3,
12160 pipe_config->dpll_hw_state.pll6,
12161 pipe_config->dpll_hw_state.pll8,
12162 pipe_config->dpll_hw_state.pll9,
12163 pipe_config->dpll_hw_state.pll10,
12164 pipe_config->dpll_hw_state.pcsdw12);
12165 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12166 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12167 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12168 pipe_config->ddi_pll_sel,
12169 pipe_config->dpll_hw_state.ctrl1,
12170 pipe_config->dpll_hw_state.cfgcr1,
12171 pipe_config->dpll_hw_state.cfgcr2);
12172 } else if (HAS_DDI(dev)) {
12173 DRM_DEBUG_KMS("ddi_pll_sel: 0x%x; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12174 pipe_config->ddi_pll_sel,
12175 pipe_config->dpll_hw_state.wrpll,
12176 pipe_config->dpll_hw_state.spll);
12177 } else {
12178 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12179 "fp0: 0x%x, fp1: 0x%x\n",
12180 pipe_config->dpll_hw_state.dpll,
12181 pipe_config->dpll_hw_state.dpll_md,
12182 pipe_config->dpll_hw_state.fp0,
12183 pipe_config->dpll_hw_state.fp1);
12184 }
12185
12186 DRM_DEBUG_KMS("planes on this crtc\n");
12187 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12188 intel_plane = to_intel_plane(plane);
12189 if (intel_plane->pipe != crtc->pipe)
12190 continue;
12191
12192 state = to_intel_plane_state(plane->state);
12193 fb = state->base.fb;
12194 if (!fb) {
12195 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12196 "disabled, scaler_id = %d\n",
12197 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12198 plane->base.id, intel_plane->pipe,
12199 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12200 drm_plane_index(plane), state->scaler_id);
12201 continue;
12202 }
12203
12204 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12205 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12206 plane->base.id, intel_plane->pipe,
12207 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12208 drm_plane_index(plane));
12209 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12210 fb->base.id, fb->width, fb->height, fb->pixel_format);
12211 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12212 state->scaler_id,
12213 state->src.x1 >> 16, state->src.y1 >> 16,
12214 drm_rect_width(&state->src) >> 16,
12215 drm_rect_height(&state->src) >> 16,
12216 state->dst.x1, state->dst.y1,
12217 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12218 }
12219 }
12220
12221 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12222 {
12223 struct drm_device *dev = state->dev;
12224 struct drm_connector *connector;
12225 unsigned int used_ports = 0;
12226
12227 /*
12228 * Walk the connector list instead of the encoder
12229 * list to detect the problem on ddi platforms
12230 * where there's just one encoder per digital port.
12231 */
12232 drm_for_each_connector(connector, dev) {
12233 struct drm_connector_state *connector_state;
12234 struct intel_encoder *encoder;
12235
12236 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12237 if (!connector_state)
12238 connector_state = connector->state;
12239
12240 if (!connector_state->best_encoder)
12241 continue;
12242
12243 encoder = to_intel_encoder(connector_state->best_encoder);
12244
12245 WARN_ON(!connector_state->crtc);
12246
12247 switch (encoder->type) {
12248 unsigned int port_mask;
12249 case INTEL_OUTPUT_UNKNOWN:
12250 if (WARN_ON(!HAS_DDI(dev)))
12251 break;
12252 case INTEL_OUTPUT_DISPLAYPORT:
12253 case INTEL_OUTPUT_HDMI:
12254 case INTEL_OUTPUT_EDP:
12255 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12256
12257 /* the same port mustn't appear more than once */
12258 if (used_ports & port_mask)
12259 return false;
12260
12261 used_ports |= port_mask;
12262 default:
12263 break;
12264 }
12265 }
12266
12267 return true;
12268 }
12269
12270 static void
12271 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12272 {
12273 struct drm_crtc_state tmp_state;
12274 struct intel_crtc_scaler_state scaler_state;
12275 struct intel_dpll_hw_state dpll_hw_state;
12276 struct intel_shared_dpll *shared_dpll;
12277 uint32_t ddi_pll_sel;
12278 bool force_thru;
12279
12280 /* FIXME: before the switch to atomic started, a new pipe_config was
12281 * kzalloc'd. Code that depends on any field being zero should be
12282 * fixed, so that the crtc_state can be safely duplicated. For now,
12283 * only fields that are know to not cause problems are preserved. */
12284
12285 tmp_state = crtc_state->base;
12286 scaler_state = crtc_state->scaler_state;
12287 shared_dpll = crtc_state->shared_dpll;
12288 dpll_hw_state = crtc_state->dpll_hw_state;
12289 ddi_pll_sel = crtc_state->ddi_pll_sel;
12290 force_thru = crtc_state->pch_pfit.force_thru;
12291
12292 memset(crtc_state, 0, sizeof *crtc_state);
12293
12294 crtc_state->base = tmp_state;
12295 crtc_state->scaler_state = scaler_state;
12296 crtc_state->shared_dpll = shared_dpll;
12297 crtc_state->dpll_hw_state = dpll_hw_state;
12298 crtc_state->ddi_pll_sel = ddi_pll_sel;
12299 crtc_state->pch_pfit.force_thru = force_thru;
12300 }
12301
12302 static int
12303 intel_modeset_pipe_config(struct drm_crtc *crtc,
12304 struct intel_crtc_state *pipe_config)
12305 {
12306 struct drm_atomic_state *state = pipe_config->base.state;
12307 struct intel_encoder *encoder;
12308 struct drm_connector *connector;
12309 struct drm_connector_state *connector_state;
12310 int base_bpp, ret = -EINVAL;
12311 int i;
12312 bool retry = true;
12313
12314 clear_intel_crtc_state(pipe_config);
12315
12316 pipe_config->cpu_transcoder =
12317 (enum transcoder) to_intel_crtc(crtc)->pipe;
12318
12319 /*
12320 * Sanitize sync polarity flags based on requested ones. If neither
12321 * positive or negative polarity is requested, treat this as meaning
12322 * negative polarity.
12323 */
12324 if (!(pipe_config->base.adjusted_mode.flags &
12325 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12326 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12327
12328 if (!(pipe_config->base.adjusted_mode.flags &
12329 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12330 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12331
12332 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12333 pipe_config);
12334 if (base_bpp < 0)
12335 goto fail;
12336
12337 /*
12338 * Determine the real pipe dimensions. Note that stereo modes can
12339 * increase the actual pipe size due to the frame doubling and
12340 * insertion of additional space for blanks between the frame. This
12341 * is stored in the crtc timings. We use the requested mode to do this
12342 * computation to clearly distinguish it from the adjusted mode, which
12343 * can be changed by the connectors in the below retry loop.
12344 */
12345 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12346 &pipe_config->pipe_src_w,
12347 &pipe_config->pipe_src_h);
12348
12349 encoder_retry:
12350 /* Ensure the port clock defaults are reset when retrying. */
12351 pipe_config->port_clock = 0;
12352 pipe_config->pixel_multiplier = 1;
12353
12354 /* Fill in default crtc timings, allow encoders to overwrite them. */
12355 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12356 CRTC_STEREO_DOUBLE);
12357
12358 /* Pass our mode to the connectors and the CRTC to give them a chance to
12359 * adjust it according to limitations or connector properties, and also
12360 * a chance to reject the mode entirely.
12361 */
12362 for_each_connector_in_state(state, connector, connector_state, i) {
12363 if (connector_state->crtc != crtc)
12364 continue;
12365
12366 encoder = to_intel_encoder(connector_state->best_encoder);
12367
12368 if (!(encoder->compute_config(encoder, pipe_config))) {
12369 DRM_DEBUG_KMS("Encoder config failure\n");
12370 goto fail;
12371 }
12372 }
12373
12374 /* Set default port clock if not overwritten by the encoder. Needs to be
12375 * done afterwards in case the encoder adjusts the mode. */
12376 if (!pipe_config->port_clock)
12377 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12378 * pipe_config->pixel_multiplier;
12379
12380 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12381 if (ret < 0) {
12382 DRM_DEBUG_KMS("CRTC fixup failed\n");
12383 goto fail;
12384 }
12385
12386 if (ret == RETRY) {
12387 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12388 ret = -EINVAL;
12389 goto fail;
12390 }
12391
12392 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12393 retry = false;
12394 goto encoder_retry;
12395 }
12396
12397 /* Dithering seems to not pass-through bits correctly when it should, so
12398 * only enable it on 6bpc panels. */
12399 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12400 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12401 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12402
12403 fail:
12404 return ret;
12405 }
12406
12407 static void
12408 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12409 {
12410 struct drm_crtc *crtc;
12411 struct drm_crtc_state *crtc_state;
12412 int i;
12413
12414 /* Double check state. */
12415 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12416 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12417
12418 /* Update hwmode for vblank functions */
12419 if (crtc->state->active)
12420 crtc->hwmode = crtc->state->adjusted_mode;
12421 else
12422 crtc->hwmode.crtc_clock = 0;
12423
12424 /*
12425 * Update legacy state to satisfy fbc code. This can
12426 * be removed when fbc uses the atomic state.
12427 */
12428 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12429 struct drm_plane_state *plane_state = crtc->primary->state;
12430
12431 crtc->primary->fb = plane_state->fb;
12432 crtc->x = plane_state->src_x >> 16;
12433 crtc->y = plane_state->src_y >> 16;
12434 }
12435 }
12436 }
12437
12438 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12439 {
12440 int diff;
12441
12442 if (clock1 == clock2)
12443 return true;
12444
12445 if (!clock1 || !clock2)
12446 return false;
12447
12448 diff = abs(clock1 - clock2);
12449
12450 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12451 return true;
12452
12453 return false;
12454 }
12455
12456 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12457 list_for_each_entry((intel_crtc), \
12458 &(dev)->mode_config.crtc_list, \
12459 base.head) \
12460 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12461
12462 static bool
12463 intel_compare_m_n(unsigned int m, unsigned int n,
12464 unsigned int m2, unsigned int n2,
12465 bool exact)
12466 {
12467 if (m == m2 && n == n2)
12468 return true;
12469
12470 if (exact || !m || !n || !m2 || !n2)
12471 return false;
12472
12473 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12474
12475 if (n > n2) {
12476 while (n > n2) {
12477 m2 <<= 1;
12478 n2 <<= 1;
12479 }
12480 } else if (n < n2) {
12481 while (n < n2) {
12482 m <<= 1;
12483 n <<= 1;
12484 }
12485 }
12486
12487 if (n != n2)
12488 return false;
12489
12490 return intel_fuzzy_clock_check(m, m2);
12491 }
12492
12493 static bool
12494 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12495 struct intel_link_m_n *m2_n2,
12496 bool adjust)
12497 {
12498 if (m_n->tu == m2_n2->tu &&
12499 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12500 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12501 intel_compare_m_n(m_n->link_m, m_n->link_n,
12502 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12503 if (adjust)
12504 *m2_n2 = *m_n;
12505
12506 return true;
12507 }
12508
12509 return false;
12510 }
12511
12512 static bool
12513 intel_pipe_config_compare(struct drm_device *dev,
12514 struct intel_crtc_state *current_config,
12515 struct intel_crtc_state *pipe_config,
12516 bool adjust)
12517 {
12518 bool ret = true;
12519
12520 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12521 do { \
12522 if (!adjust) \
12523 DRM_ERROR(fmt, ##__VA_ARGS__); \
12524 else \
12525 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12526 } while (0)
12527
12528 #define PIPE_CONF_CHECK_X(name) \
12529 if (current_config->name != pipe_config->name) { \
12530 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12531 "(expected 0x%08x, found 0x%08x)\n", \
12532 current_config->name, \
12533 pipe_config->name); \
12534 ret = false; \
12535 }
12536
12537 #define PIPE_CONF_CHECK_I(name) \
12538 if (current_config->name != pipe_config->name) { \
12539 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12540 "(expected %i, found %i)\n", \
12541 current_config->name, \
12542 pipe_config->name); \
12543 ret = false; \
12544 }
12545
12546 #define PIPE_CONF_CHECK_P(name) \
12547 if (current_config->name != pipe_config->name) { \
12548 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12549 "(expected %p, found %p)\n", \
12550 current_config->name, \
12551 pipe_config->name); \
12552 ret = false; \
12553 }
12554
12555 #define PIPE_CONF_CHECK_M_N(name) \
12556 if (!intel_compare_link_m_n(&current_config->name, \
12557 &pipe_config->name,\
12558 adjust)) { \
12559 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12560 "(expected tu %i gmch %i/%i link %i/%i, " \
12561 "found tu %i, gmch %i/%i link %i/%i)\n", \
12562 current_config->name.tu, \
12563 current_config->name.gmch_m, \
12564 current_config->name.gmch_n, \
12565 current_config->name.link_m, \
12566 current_config->name.link_n, \
12567 pipe_config->name.tu, \
12568 pipe_config->name.gmch_m, \
12569 pipe_config->name.gmch_n, \
12570 pipe_config->name.link_m, \
12571 pipe_config->name.link_n); \
12572 ret = false; \
12573 }
12574
12575 /* This is required for BDW+ where there is only one set of registers for
12576 * switching between high and low RR.
12577 * This macro can be used whenever a comparison has to be made between one
12578 * hw state and multiple sw state variables.
12579 */
12580 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12581 if (!intel_compare_link_m_n(&current_config->name, \
12582 &pipe_config->name, adjust) && \
12583 !intel_compare_link_m_n(&current_config->alt_name, \
12584 &pipe_config->name, adjust)) { \
12585 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12586 "(expected tu %i gmch %i/%i link %i/%i, " \
12587 "or tu %i gmch %i/%i link %i/%i, " \
12588 "found tu %i, gmch %i/%i link %i/%i)\n", \
12589 current_config->name.tu, \
12590 current_config->name.gmch_m, \
12591 current_config->name.gmch_n, \
12592 current_config->name.link_m, \
12593 current_config->name.link_n, \
12594 current_config->alt_name.tu, \
12595 current_config->alt_name.gmch_m, \
12596 current_config->alt_name.gmch_n, \
12597 current_config->alt_name.link_m, \
12598 current_config->alt_name.link_n, \
12599 pipe_config->name.tu, \
12600 pipe_config->name.gmch_m, \
12601 pipe_config->name.gmch_n, \
12602 pipe_config->name.link_m, \
12603 pipe_config->name.link_n); \
12604 ret = false; \
12605 }
12606
12607 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12608 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12609 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12610 "(expected %i, found %i)\n", \
12611 current_config->name & (mask), \
12612 pipe_config->name & (mask)); \
12613 ret = false; \
12614 }
12615
12616 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12617 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12618 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12619 "(expected %i, found %i)\n", \
12620 current_config->name, \
12621 pipe_config->name); \
12622 ret = false; \
12623 }
12624
12625 #define PIPE_CONF_QUIRK(quirk) \
12626 ((current_config->quirks | pipe_config->quirks) & (quirk))
12627
12628 PIPE_CONF_CHECK_I(cpu_transcoder);
12629
12630 PIPE_CONF_CHECK_I(has_pch_encoder);
12631 PIPE_CONF_CHECK_I(fdi_lanes);
12632 PIPE_CONF_CHECK_M_N(fdi_m_n);
12633
12634 PIPE_CONF_CHECK_I(has_dp_encoder);
12635 PIPE_CONF_CHECK_I(lane_count);
12636
12637 if (INTEL_INFO(dev)->gen < 8) {
12638 PIPE_CONF_CHECK_M_N(dp_m_n);
12639
12640 if (current_config->has_drrs)
12641 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12642 } else
12643 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12644
12645 PIPE_CONF_CHECK_I(has_dsi_encoder);
12646
12647 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12648 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12649 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12650 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12651 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12652 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12653
12654 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12655 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12656 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12657 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12658 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12659 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12660
12661 PIPE_CONF_CHECK_I(pixel_multiplier);
12662 PIPE_CONF_CHECK_I(has_hdmi_sink);
12663 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12664 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12665 PIPE_CONF_CHECK_I(limited_color_range);
12666 PIPE_CONF_CHECK_I(has_infoframe);
12667
12668 PIPE_CONF_CHECK_I(has_audio);
12669
12670 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12671 DRM_MODE_FLAG_INTERLACE);
12672
12673 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12674 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12675 DRM_MODE_FLAG_PHSYNC);
12676 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12677 DRM_MODE_FLAG_NHSYNC);
12678 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12679 DRM_MODE_FLAG_PVSYNC);
12680 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12681 DRM_MODE_FLAG_NVSYNC);
12682 }
12683
12684 PIPE_CONF_CHECK_X(gmch_pfit.control);
12685 /* pfit ratios are autocomputed by the hw on gen4+ */
12686 if (INTEL_INFO(dev)->gen < 4)
12687 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12688 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12689
12690 if (!adjust) {
12691 PIPE_CONF_CHECK_I(pipe_src_w);
12692 PIPE_CONF_CHECK_I(pipe_src_h);
12693
12694 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12695 if (current_config->pch_pfit.enabled) {
12696 PIPE_CONF_CHECK_X(pch_pfit.pos);
12697 PIPE_CONF_CHECK_X(pch_pfit.size);
12698 }
12699
12700 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12701 }
12702
12703 /* BDW+ don't expose a synchronous way to read the state */
12704 if (IS_HASWELL(dev))
12705 PIPE_CONF_CHECK_I(ips_enabled);
12706
12707 PIPE_CONF_CHECK_I(double_wide);
12708
12709 PIPE_CONF_CHECK_X(ddi_pll_sel);
12710
12711 PIPE_CONF_CHECK_P(shared_dpll);
12712 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12713 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12714 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12715 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12716 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12717 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12718 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12719 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12720 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12721
12722 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12723 PIPE_CONF_CHECK_I(pipe_bpp);
12724
12725 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12726 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12727
12728 #undef PIPE_CONF_CHECK_X
12729 #undef PIPE_CONF_CHECK_I
12730 #undef PIPE_CONF_CHECK_P
12731 #undef PIPE_CONF_CHECK_FLAGS
12732 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12733 #undef PIPE_CONF_QUIRK
12734 #undef INTEL_ERR_OR_DBG_KMS
12735
12736 return ret;
12737 }
12738
12739 static void intel_pipe_config_sanity_check(struct drm_i915_private *dev_priv,
12740 const struct intel_crtc_state *pipe_config)
12741 {
12742 if (pipe_config->has_pch_encoder) {
12743 int fdi_dotclock = intel_dotclock_calculate(intel_fdi_link_freq(dev_priv, pipe_config),
12744 &pipe_config->fdi_m_n);
12745 int dotclock = pipe_config->base.adjusted_mode.crtc_clock;
12746
12747 /*
12748 * FDI already provided one idea for the dotclock.
12749 * Yell if the encoder disagrees.
12750 */
12751 WARN(!intel_fuzzy_clock_check(fdi_dotclock, dotclock),
12752 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12753 fdi_dotclock, dotclock);
12754 }
12755 }
12756
12757 static void check_wm_state(struct drm_device *dev)
12758 {
12759 struct drm_i915_private *dev_priv = dev->dev_private;
12760 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12761 struct intel_crtc *intel_crtc;
12762 int plane;
12763
12764 if (INTEL_INFO(dev)->gen < 9)
12765 return;
12766
12767 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12768 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12769
12770 for_each_intel_crtc(dev, intel_crtc) {
12771 struct skl_ddb_entry *hw_entry, *sw_entry;
12772 const enum pipe pipe = intel_crtc->pipe;
12773
12774 if (!intel_crtc->active)
12775 continue;
12776
12777 /* planes */
12778 for_each_plane(dev_priv, pipe, plane) {
12779 hw_entry = &hw_ddb.plane[pipe][plane];
12780 sw_entry = &sw_ddb->plane[pipe][plane];
12781
12782 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12783 continue;
12784
12785 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12786 "(expected (%u,%u), found (%u,%u))\n",
12787 pipe_name(pipe), plane + 1,
12788 sw_entry->start, sw_entry->end,
12789 hw_entry->start, hw_entry->end);
12790 }
12791
12792 /* cursor */
12793 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12794 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12795
12796 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12797 continue;
12798
12799 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12800 "(expected (%u,%u), found (%u,%u))\n",
12801 pipe_name(pipe),
12802 sw_entry->start, sw_entry->end,
12803 hw_entry->start, hw_entry->end);
12804 }
12805 }
12806
12807 static void
12808 check_connector_state(struct drm_device *dev,
12809 struct drm_atomic_state *old_state)
12810 {
12811 struct drm_connector_state *old_conn_state;
12812 struct drm_connector *connector;
12813 int i;
12814
12815 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12816 struct drm_encoder *encoder = connector->encoder;
12817 struct drm_connector_state *state = connector->state;
12818
12819 /* This also checks the encoder/connector hw state with the
12820 * ->get_hw_state callbacks. */
12821 intel_connector_check_state(to_intel_connector(connector));
12822
12823 I915_STATE_WARN(state->best_encoder != encoder,
12824 "connector's atomic encoder doesn't match legacy encoder\n");
12825 }
12826 }
12827
12828 static void
12829 check_encoder_state(struct drm_device *dev)
12830 {
12831 struct intel_encoder *encoder;
12832 struct intel_connector *connector;
12833
12834 for_each_intel_encoder(dev, encoder) {
12835 bool enabled = false;
12836 enum pipe pipe;
12837
12838 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12839 encoder->base.base.id,
12840 encoder->base.name);
12841
12842 for_each_intel_connector(dev, connector) {
12843 if (connector->base.state->best_encoder != &encoder->base)
12844 continue;
12845 enabled = true;
12846
12847 I915_STATE_WARN(connector->base.state->crtc !=
12848 encoder->base.crtc,
12849 "connector's crtc doesn't match encoder crtc\n");
12850 }
12851
12852 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12853 "encoder's enabled state mismatch "
12854 "(expected %i, found %i)\n",
12855 !!encoder->base.crtc, enabled);
12856
12857 if (!encoder->base.crtc) {
12858 bool active;
12859
12860 active = encoder->get_hw_state(encoder, &pipe);
12861 I915_STATE_WARN(active,
12862 "encoder detached but still enabled on pipe %c.\n",
12863 pipe_name(pipe));
12864 }
12865 }
12866 }
12867
12868 static void
12869 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12870 {
12871 struct drm_i915_private *dev_priv = dev->dev_private;
12872 struct intel_encoder *encoder;
12873 struct drm_crtc_state *old_crtc_state;
12874 struct drm_crtc *crtc;
12875 int i;
12876
12877 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12879 struct intel_crtc_state *pipe_config, *sw_config;
12880 bool active;
12881
12882 if (!needs_modeset(crtc->state) &&
12883 !to_intel_crtc_state(crtc->state)->update_pipe)
12884 continue;
12885
12886 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12887 pipe_config = to_intel_crtc_state(old_crtc_state);
12888 memset(pipe_config, 0, sizeof(*pipe_config));
12889 pipe_config->base.crtc = crtc;
12890 pipe_config->base.state = old_state;
12891
12892 DRM_DEBUG_KMS("[CRTC:%d]\n",
12893 crtc->base.id);
12894
12895 active = dev_priv->display.get_pipe_config(intel_crtc,
12896 pipe_config);
12897
12898 /* hw state is inconsistent with the pipe quirk */
12899 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12900 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12901 active = crtc->state->active;
12902
12903 I915_STATE_WARN(crtc->state->active != active,
12904 "crtc active state doesn't match with hw state "
12905 "(expected %i, found %i)\n", crtc->state->active, active);
12906
12907 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12908 "transitional active state does not match atomic hw state "
12909 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12910
12911 for_each_encoder_on_crtc(dev, crtc, encoder) {
12912 enum pipe pipe;
12913
12914 active = encoder->get_hw_state(encoder, &pipe);
12915 I915_STATE_WARN(active != crtc->state->active,
12916 "[ENCODER:%i] active %i with crtc active %i\n",
12917 encoder->base.base.id, active, crtc->state->active);
12918
12919 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12920 "Encoder connected to wrong pipe %c\n",
12921 pipe_name(pipe));
12922
12923 if (active)
12924 encoder->get_config(encoder, pipe_config);
12925 }
12926
12927 if (!crtc->state->active)
12928 continue;
12929
12930 intel_pipe_config_sanity_check(dev_priv, pipe_config);
12931
12932 sw_config = to_intel_crtc_state(crtc->state);
12933 if (!intel_pipe_config_compare(dev, sw_config,
12934 pipe_config, false)) {
12935 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12936 intel_dump_pipe_config(intel_crtc, pipe_config,
12937 "[hw state]");
12938 intel_dump_pipe_config(intel_crtc, sw_config,
12939 "[sw state]");
12940 }
12941 }
12942 }
12943
12944 static void
12945 check_shared_dpll_state(struct drm_device *dev)
12946 {
12947 struct drm_i915_private *dev_priv = dev->dev_private;
12948 struct intel_crtc *crtc;
12949 struct intel_dpll_hw_state dpll_hw_state;
12950 int i;
12951
12952 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12953 struct intel_shared_dpll *pll =
12954 intel_get_shared_dpll_by_id(dev_priv, i);
12955 unsigned enabled_crtcs = 0, active_crtcs = 0;
12956 bool active;
12957
12958 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12959
12960 DRM_DEBUG_KMS("%s\n", pll->name);
12961
12962 active = pll->funcs.get_hw_state(dev_priv, pll, &dpll_hw_state);
12963
12964 I915_STATE_WARN(pll->active_mask & ~pll->config.crtc_mask,
12965 "more active pll users than references: %x vs %x\n",
12966 pll->active_mask, pll->config.crtc_mask);
12967
12968 if (!(pll->flags & INTEL_DPLL_ALWAYS_ON)) {
12969 I915_STATE_WARN(!pll->on && pll->active_mask,
12970 "pll in active use but not on in sw tracking\n");
12971 I915_STATE_WARN(pll->on && !pll->active_mask,
12972 "pll is on but not used by any active crtc\n");
12973 I915_STATE_WARN(pll->on != active,
12974 "pll on state mismatch (expected %i, found %i)\n",
12975 pll->on, active);
12976 }
12977
12978 for_each_intel_crtc(dev, crtc) {
12979 if (crtc->base.state->enable && crtc->config->shared_dpll == pll)
12980 enabled_crtcs |= 1 << drm_crtc_index(&crtc->base);
12981 if (crtc->base.state->active && crtc->config->shared_dpll == pll)
12982 active_crtcs |= 1 << drm_crtc_index(&crtc->base);
12983 }
12984
12985 I915_STATE_WARN(pll->active_mask != active_crtcs,
12986 "pll active crtcs mismatch (expected %x, found %x)\n",
12987 pll->active_mask, active_crtcs);
12988 I915_STATE_WARN(pll->config.crtc_mask != enabled_crtcs,
12989 "pll enabled crtcs mismatch (expected %x, found %x)\n",
12990 pll->config.crtc_mask, enabled_crtcs);
12991
12992 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12993 sizeof(dpll_hw_state)),
12994 "pll hw state mismatch\n");
12995 }
12996 }
12997
12998 static void
12999 intel_modeset_check_state(struct drm_device *dev,
13000 struct drm_atomic_state *old_state)
13001 {
13002 check_wm_state(dev);
13003 check_connector_state(dev, old_state);
13004 check_encoder_state(dev);
13005 check_crtc_state(dev, old_state);
13006 check_shared_dpll_state(dev);
13007 }
13008
13009 static void update_scanline_offset(struct intel_crtc *crtc)
13010 {
13011 struct drm_device *dev = crtc->base.dev;
13012
13013 /*
13014 * The scanline counter increments at the leading edge of hsync.
13015 *
13016 * On most platforms it starts counting from vtotal-1 on the
13017 * first active line. That means the scanline counter value is
13018 * always one less than what we would expect. Ie. just after
13019 * start of vblank, which also occurs at start of hsync (on the
13020 * last active line), the scanline counter will read vblank_start-1.
13021 *
13022 * On gen2 the scanline counter starts counting from 1 instead
13023 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13024 * to keep the value positive), instead of adding one.
13025 *
13026 * On HSW+ the behaviour of the scanline counter depends on the output
13027 * type. For DP ports it behaves like most other platforms, but on HDMI
13028 * there's an extra 1 line difference. So we need to add two instead of
13029 * one to the value.
13030 */
13031 if (IS_GEN2(dev)) {
13032 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13033 int vtotal;
13034
13035 vtotal = adjusted_mode->crtc_vtotal;
13036 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13037 vtotal /= 2;
13038
13039 crtc->scanline_offset = vtotal - 1;
13040 } else if (HAS_DDI(dev) &&
13041 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13042 crtc->scanline_offset = 2;
13043 } else
13044 crtc->scanline_offset = 1;
13045 }
13046
13047 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13048 {
13049 struct drm_device *dev = state->dev;
13050 struct drm_i915_private *dev_priv = to_i915(dev);
13051 struct intel_shared_dpll_config *shared_dpll = NULL;
13052 struct drm_crtc *crtc;
13053 struct drm_crtc_state *crtc_state;
13054 int i;
13055
13056 if (!dev_priv->display.crtc_compute_clock)
13057 return;
13058
13059 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13061 struct intel_shared_dpll *old_dpll =
13062 to_intel_crtc_state(crtc->state)->shared_dpll;
13063
13064 if (!needs_modeset(crtc_state))
13065 continue;
13066
13067 to_intel_crtc_state(crtc_state)->shared_dpll = NULL;
13068
13069 if (!old_dpll)
13070 continue;
13071
13072 if (!shared_dpll)
13073 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13074
13075 intel_shared_dpll_config_put(shared_dpll, old_dpll, intel_crtc);
13076 }
13077 }
13078
13079 /*
13080 * This implements the workaround described in the "notes" section of the mode
13081 * set sequence documentation. When going from no pipes or single pipe to
13082 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13083 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13084 */
13085 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13086 {
13087 struct drm_crtc_state *crtc_state;
13088 struct intel_crtc *intel_crtc;
13089 struct drm_crtc *crtc;
13090 struct intel_crtc_state *first_crtc_state = NULL;
13091 struct intel_crtc_state *other_crtc_state = NULL;
13092 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13093 int i;
13094
13095 /* look at all crtc's that are going to be enabled in during modeset */
13096 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13097 intel_crtc = to_intel_crtc(crtc);
13098
13099 if (!crtc_state->active || !needs_modeset(crtc_state))
13100 continue;
13101
13102 if (first_crtc_state) {
13103 other_crtc_state = to_intel_crtc_state(crtc_state);
13104 break;
13105 } else {
13106 first_crtc_state = to_intel_crtc_state(crtc_state);
13107 first_pipe = intel_crtc->pipe;
13108 }
13109 }
13110
13111 /* No workaround needed? */
13112 if (!first_crtc_state)
13113 return 0;
13114
13115 /* w/a possibly needed, check how many crtc's are already enabled. */
13116 for_each_intel_crtc(state->dev, intel_crtc) {
13117 struct intel_crtc_state *pipe_config;
13118
13119 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13120 if (IS_ERR(pipe_config))
13121 return PTR_ERR(pipe_config);
13122
13123 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13124
13125 if (!pipe_config->base.active ||
13126 needs_modeset(&pipe_config->base))
13127 continue;
13128
13129 /* 2 or more enabled crtcs means no need for w/a */
13130 if (enabled_pipe != INVALID_PIPE)
13131 return 0;
13132
13133 enabled_pipe = intel_crtc->pipe;
13134 }
13135
13136 if (enabled_pipe != INVALID_PIPE)
13137 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13138 else if (other_crtc_state)
13139 other_crtc_state->hsw_workaround_pipe = first_pipe;
13140
13141 return 0;
13142 }
13143
13144 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13145 {
13146 struct drm_crtc *crtc;
13147 struct drm_crtc_state *crtc_state;
13148 int ret = 0;
13149
13150 /* add all active pipes to the state */
13151 for_each_crtc(state->dev, crtc) {
13152 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13153 if (IS_ERR(crtc_state))
13154 return PTR_ERR(crtc_state);
13155
13156 if (!crtc_state->active || needs_modeset(crtc_state))
13157 continue;
13158
13159 crtc_state->mode_changed = true;
13160
13161 ret = drm_atomic_add_affected_connectors(state, crtc);
13162 if (ret)
13163 break;
13164
13165 ret = drm_atomic_add_affected_planes(state, crtc);
13166 if (ret)
13167 break;
13168 }
13169
13170 return ret;
13171 }
13172
13173 static int intel_modeset_checks(struct drm_atomic_state *state)
13174 {
13175 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13176 struct drm_i915_private *dev_priv = state->dev->dev_private;
13177 struct drm_crtc *crtc;
13178 struct drm_crtc_state *crtc_state;
13179 int ret = 0, i;
13180
13181 if (!check_digital_port_conflicts(state)) {
13182 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13183 return -EINVAL;
13184 }
13185
13186 intel_state->modeset = true;
13187 intel_state->active_crtcs = dev_priv->active_crtcs;
13188
13189 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13190 if (crtc_state->active)
13191 intel_state->active_crtcs |= 1 << i;
13192 else
13193 intel_state->active_crtcs &= ~(1 << i);
13194 }
13195
13196 /*
13197 * See if the config requires any additional preparation, e.g.
13198 * to adjust global state with pipes off. We need to do this
13199 * here so we can get the modeset_pipe updated config for the new
13200 * mode set on this crtc. For other crtcs we need to use the
13201 * adjusted_mode bits in the crtc directly.
13202 */
13203 if (dev_priv->display.modeset_calc_cdclk) {
13204 ret = dev_priv->display.modeset_calc_cdclk(state);
13205
13206 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13207 ret = intel_modeset_all_pipes(state);
13208
13209 if (ret < 0)
13210 return ret;
13211
13212 DRM_DEBUG_KMS("New cdclk calculated to be atomic %u, actual %u\n",
13213 intel_state->cdclk, intel_state->dev_cdclk);
13214 } else
13215 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13216
13217 intel_modeset_clear_plls(state);
13218
13219 if (IS_HASWELL(dev_priv))
13220 return haswell_mode_set_planes_workaround(state);
13221
13222 return 0;
13223 }
13224
13225 /*
13226 * Handle calculation of various watermark data at the end of the atomic check
13227 * phase. The code here should be run after the per-crtc and per-plane 'check'
13228 * handlers to ensure that all derived state has been updated.
13229 */
13230 static void calc_watermark_data(struct drm_atomic_state *state)
13231 {
13232 struct drm_device *dev = state->dev;
13233 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13234 struct drm_crtc *crtc;
13235 struct drm_crtc_state *cstate;
13236 struct drm_plane *plane;
13237 struct drm_plane_state *pstate;
13238
13239 /*
13240 * Calculate watermark configuration details now that derived
13241 * plane/crtc state is all properly updated.
13242 */
13243 drm_for_each_crtc(crtc, dev) {
13244 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13245 crtc->state;
13246
13247 if (cstate->active)
13248 intel_state->wm_config.num_pipes_active++;
13249 }
13250 drm_for_each_legacy_plane(plane, dev) {
13251 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13252 plane->state;
13253
13254 if (!to_intel_plane_state(pstate)->visible)
13255 continue;
13256
13257 intel_state->wm_config.sprites_enabled = true;
13258 if (pstate->crtc_w != pstate->src_w >> 16 ||
13259 pstate->crtc_h != pstate->src_h >> 16)
13260 intel_state->wm_config.sprites_scaled = true;
13261 }
13262 }
13263
13264 /**
13265 * intel_atomic_check - validate state object
13266 * @dev: drm device
13267 * @state: state to validate
13268 */
13269 static int intel_atomic_check(struct drm_device *dev,
13270 struct drm_atomic_state *state)
13271 {
13272 struct drm_i915_private *dev_priv = to_i915(dev);
13273 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13274 struct drm_crtc *crtc;
13275 struct drm_crtc_state *crtc_state;
13276 int ret, i;
13277 bool any_ms = false;
13278
13279 ret = drm_atomic_helper_check_modeset(dev, state);
13280 if (ret)
13281 return ret;
13282
13283 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13284 struct intel_crtc_state *pipe_config =
13285 to_intel_crtc_state(crtc_state);
13286
13287 /* Catch I915_MODE_FLAG_INHERITED */
13288 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13289 crtc_state->mode_changed = true;
13290
13291 if (!crtc_state->enable) {
13292 if (needs_modeset(crtc_state))
13293 any_ms = true;
13294 continue;
13295 }
13296
13297 if (!needs_modeset(crtc_state))
13298 continue;
13299
13300 /* FIXME: For only active_changed we shouldn't need to do any
13301 * state recomputation at all. */
13302
13303 ret = drm_atomic_add_affected_connectors(state, crtc);
13304 if (ret)
13305 return ret;
13306
13307 ret = intel_modeset_pipe_config(crtc, pipe_config);
13308 if (ret)
13309 return ret;
13310
13311 if (i915.fastboot &&
13312 intel_pipe_config_compare(dev,
13313 to_intel_crtc_state(crtc->state),
13314 pipe_config, true)) {
13315 crtc_state->mode_changed = false;
13316 to_intel_crtc_state(crtc_state)->update_pipe = true;
13317 }
13318
13319 if (needs_modeset(crtc_state)) {
13320 any_ms = true;
13321
13322 ret = drm_atomic_add_affected_planes(state, crtc);
13323 if (ret)
13324 return ret;
13325 }
13326
13327 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13328 needs_modeset(crtc_state) ?
13329 "[modeset]" : "[fastset]");
13330 }
13331
13332 if (any_ms) {
13333 ret = intel_modeset_checks(state);
13334
13335 if (ret)
13336 return ret;
13337 } else
13338 intel_state->cdclk = dev_priv->cdclk_freq;
13339
13340 ret = drm_atomic_helper_check_planes(dev, state);
13341 if (ret)
13342 return ret;
13343
13344 intel_fbc_choose_crtc(dev_priv, state);
13345 calc_watermark_data(state);
13346
13347 return 0;
13348 }
13349
13350 static int intel_atomic_prepare_commit(struct drm_device *dev,
13351 struct drm_atomic_state *state,
13352 bool async)
13353 {
13354 struct drm_i915_private *dev_priv = dev->dev_private;
13355 struct drm_plane_state *plane_state;
13356 struct drm_crtc_state *crtc_state;
13357 struct drm_plane *plane;
13358 struct drm_crtc *crtc;
13359 int i, ret;
13360
13361 if (async) {
13362 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13363 return -EINVAL;
13364 }
13365
13366 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13367 ret = intel_crtc_wait_for_pending_flips(crtc);
13368 if (ret)
13369 return ret;
13370
13371 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13372 flush_workqueue(dev_priv->wq);
13373 }
13374
13375 ret = mutex_lock_interruptible(&dev->struct_mutex);
13376 if (ret)
13377 return ret;
13378
13379 ret = drm_atomic_helper_prepare_planes(dev, state);
13380 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13381 u32 reset_counter;
13382
13383 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13384 mutex_unlock(&dev->struct_mutex);
13385
13386 for_each_plane_in_state(state, plane, plane_state, i) {
13387 struct intel_plane_state *intel_plane_state =
13388 to_intel_plane_state(plane_state);
13389
13390 if (!intel_plane_state->wait_req)
13391 continue;
13392
13393 ret = __i915_wait_request(intel_plane_state->wait_req,
13394 reset_counter, true,
13395 NULL, NULL);
13396
13397 /* Swallow -EIO errors to allow updates during hw lockup. */
13398 if (ret == -EIO)
13399 ret = 0;
13400
13401 if (ret)
13402 break;
13403 }
13404
13405 if (!ret)
13406 return 0;
13407
13408 mutex_lock(&dev->struct_mutex);
13409 drm_atomic_helper_cleanup_planes(dev, state);
13410 }
13411
13412 mutex_unlock(&dev->struct_mutex);
13413 return ret;
13414 }
13415
13416 static void intel_atomic_wait_for_vblanks(struct drm_device *dev,
13417 struct drm_i915_private *dev_priv,
13418 unsigned crtc_mask)
13419 {
13420 unsigned last_vblank_count[I915_MAX_PIPES];
13421 enum pipe pipe;
13422 int ret;
13423
13424 if (!crtc_mask)
13425 return;
13426
13427 for_each_pipe(dev_priv, pipe) {
13428 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13429
13430 if (!((1 << pipe) & crtc_mask))
13431 continue;
13432
13433 ret = drm_crtc_vblank_get(crtc);
13434 if (WARN_ON(ret != 0)) {
13435 crtc_mask &= ~(1 << pipe);
13436 continue;
13437 }
13438
13439 last_vblank_count[pipe] = drm_crtc_vblank_count(crtc);
13440 }
13441
13442 for_each_pipe(dev_priv, pipe) {
13443 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
13444 long lret;
13445
13446 if (!((1 << pipe) & crtc_mask))
13447 continue;
13448
13449 lret = wait_event_timeout(dev->vblank[pipe].queue,
13450 last_vblank_count[pipe] !=
13451 drm_crtc_vblank_count(crtc),
13452 msecs_to_jiffies(50));
13453
13454 WARN_ON(!lret);
13455
13456 drm_crtc_vblank_put(crtc);
13457 }
13458 }
13459
13460 static bool needs_vblank_wait(struct intel_crtc_state *crtc_state)
13461 {
13462 /* fb updated, need to unpin old fb */
13463 if (crtc_state->fb_changed)
13464 return true;
13465
13466 /* wm changes, need vblank before final wm's */
13467 if (crtc_state->update_wm_post)
13468 return true;
13469
13470 /*
13471 * cxsr is re-enabled after vblank.
13472 * This is already handled by crtc_state->update_wm_post,
13473 * but added for clarity.
13474 */
13475 if (crtc_state->disable_cxsr)
13476 return true;
13477
13478 return false;
13479 }
13480
13481 /**
13482 * intel_atomic_commit - commit validated state object
13483 * @dev: DRM device
13484 * @state: the top-level driver state object
13485 * @async: asynchronous commit
13486 *
13487 * This function commits a top-level state object that has been validated
13488 * with drm_atomic_helper_check().
13489 *
13490 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13491 * we can only handle plane-related operations and do not yet support
13492 * asynchronous commit.
13493 *
13494 * RETURNS
13495 * Zero for success or -errno.
13496 */
13497 static int intel_atomic_commit(struct drm_device *dev,
13498 struct drm_atomic_state *state,
13499 bool async)
13500 {
13501 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13502 struct drm_i915_private *dev_priv = dev->dev_private;
13503 struct drm_crtc_state *old_crtc_state;
13504 struct drm_crtc *crtc;
13505 struct intel_crtc_state *intel_cstate;
13506 int ret = 0, i;
13507 bool hw_check = intel_state->modeset;
13508 unsigned long put_domains[I915_MAX_PIPES] = {};
13509 unsigned crtc_vblank_mask = 0;
13510
13511 ret = intel_atomic_prepare_commit(dev, state, async);
13512 if (ret) {
13513 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13514 return ret;
13515 }
13516
13517 drm_atomic_helper_swap_state(dev, state);
13518 dev_priv->wm.config = intel_state->wm_config;
13519 intel_shared_dpll_commit(state);
13520
13521 if (intel_state->modeset) {
13522 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13523 sizeof(intel_state->min_pixclk));
13524 dev_priv->active_crtcs = intel_state->active_crtcs;
13525 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13526
13527 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13528 }
13529
13530 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13531 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13532
13533 if (needs_modeset(crtc->state) ||
13534 to_intel_crtc_state(crtc->state)->update_pipe) {
13535 hw_check = true;
13536
13537 put_domains[to_intel_crtc(crtc)->pipe] =
13538 modeset_get_crtc_power_domains(crtc,
13539 to_intel_crtc_state(crtc->state));
13540 }
13541
13542 if (!needs_modeset(crtc->state))
13543 continue;
13544
13545 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13546
13547 if (old_crtc_state->active) {
13548 intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
13549 dev_priv->display.crtc_disable(crtc);
13550 intel_crtc->active = false;
13551 intel_fbc_disable(intel_crtc);
13552 intel_disable_shared_dpll(intel_crtc);
13553
13554 /*
13555 * Underruns don't always raise
13556 * interrupts, so check manually.
13557 */
13558 intel_check_cpu_fifo_underruns(dev_priv);
13559 intel_check_pch_fifo_underruns(dev_priv);
13560
13561 if (!crtc->state->active)
13562 intel_update_watermarks(crtc);
13563 }
13564 }
13565
13566 /* Only after disabling all output pipelines that will be changed can we
13567 * update the the output configuration. */
13568 intel_modeset_update_crtc_state(state);
13569
13570 if (intel_state->modeset) {
13571 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13572
13573 if (dev_priv->display.modeset_commit_cdclk &&
13574 intel_state->dev_cdclk != dev_priv->cdclk_freq)
13575 dev_priv->display.modeset_commit_cdclk(state);
13576 }
13577
13578 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13579 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13581 bool modeset = needs_modeset(crtc->state);
13582 struct intel_crtc_state *pipe_config =
13583 to_intel_crtc_state(crtc->state);
13584 bool update_pipe = !modeset && pipe_config->update_pipe;
13585
13586 if (modeset && crtc->state->active) {
13587 update_scanline_offset(to_intel_crtc(crtc));
13588 dev_priv->display.crtc_enable(crtc);
13589 }
13590
13591 if (!modeset)
13592 intel_pre_plane_update(to_intel_crtc_state(old_crtc_state));
13593
13594 if (crtc->state->active &&
13595 drm_atomic_get_existing_plane_state(state, crtc->primary))
13596 intel_fbc_enable(intel_crtc);
13597
13598 if (crtc->state->active &&
13599 (crtc->state->planes_changed || update_pipe))
13600 drm_atomic_helper_commit_planes_on_crtc(old_crtc_state);
13601
13602 if (pipe_config->base.active && needs_vblank_wait(pipe_config))
13603 crtc_vblank_mask |= 1 << i;
13604 }
13605
13606 /* FIXME: add subpixel order */
13607
13608 if (!state->legacy_cursor_update)
13609 intel_atomic_wait_for_vblanks(dev, dev_priv, crtc_vblank_mask);
13610
13611 /*
13612 * Now that the vblank has passed, we can go ahead and program the
13613 * optimal watermarks on platforms that need two-step watermark
13614 * programming.
13615 *
13616 * TODO: Move this (and other cleanup) to an async worker eventually.
13617 */
13618 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13619 intel_cstate = to_intel_crtc_state(crtc->state);
13620
13621 if (dev_priv->display.optimize_watermarks)
13622 dev_priv->display.optimize_watermarks(intel_cstate);
13623 }
13624
13625 for_each_crtc_in_state(state, crtc, old_crtc_state, i) {
13626 intel_post_plane_update(to_intel_crtc_state(old_crtc_state));
13627
13628 if (put_domains[i])
13629 modeset_put_power_domains(dev_priv, put_domains[i]);
13630 }
13631
13632 if (intel_state->modeset)
13633 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13634
13635 mutex_lock(&dev->struct_mutex);
13636 drm_atomic_helper_cleanup_planes(dev, state);
13637 mutex_unlock(&dev->struct_mutex);
13638
13639 if (hw_check)
13640 intel_modeset_check_state(dev, state);
13641
13642 drm_atomic_state_free(state);
13643
13644 /* As one of the primary mmio accessors, KMS has a high likelihood
13645 * of triggering bugs in unclaimed access. After we finish
13646 * modesetting, see if an error has been flagged, and if so
13647 * enable debugging for the next modeset - and hope we catch
13648 * the culprit.
13649 *
13650 * XXX note that we assume display power is on at this point.
13651 * This might hold true now but we need to add pm helper to check
13652 * unclaimed only when the hardware is on, as atomic commits
13653 * can happen also when the device is completely off.
13654 */
13655 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13656
13657 return 0;
13658 }
13659
13660 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13661 {
13662 struct drm_device *dev = crtc->dev;
13663 struct drm_atomic_state *state;
13664 struct drm_crtc_state *crtc_state;
13665 int ret;
13666
13667 state = drm_atomic_state_alloc(dev);
13668 if (!state) {
13669 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13670 crtc->base.id);
13671 return;
13672 }
13673
13674 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13675
13676 retry:
13677 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13678 ret = PTR_ERR_OR_ZERO(crtc_state);
13679 if (!ret) {
13680 if (!crtc_state->active)
13681 goto out;
13682
13683 crtc_state->mode_changed = true;
13684 ret = drm_atomic_commit(state);
13685 }
13686
13687 if (ret == -EDEADLK) {
13688 drm_atomic_state_clear(state);
13689 drm_modeset_backoff(state->acquire_ctx);
13690 goto retry;
13691 }
13692
13693 if (ret)
13694 out:
13695 drm_atomic_state_free(state);
13696 }
13697
13698 #undef for_each_intel_crtc_masked
13699
13700 static const struct drm_crtc_funcs intel_crtc_funcs = {
13701 .gamma_set = drm_atomic_helper_legacy_gamma_set,
13702 .set_config = drm_atomic_helper_set_config,
13703 .set_property = drm_atomic_helper_crtc_set_property,
13704 .destroy = intel_crtc_destroy,
13705 .page_flip = intel_crtc_page_flip,
13706 .atomic_duplicate_state = intel_crtc_duplicate_state,
13707 .atomic_destroy_state = intel_crtc_destroy_state,
13708 };
13709
13710 /**
13711 * intel_prepare_plane_fb - Prepare fb for usage on plane
13712 * @plane: drm plane to prepare for
13713 * @fb: framebuffer to prepare for presentation
13714 *
13715 * Prepares a framebuffer for usage on a display plane. Generally this
13716 * involves pinning the underlying object and updating the frontbuffer tracking
13717 * bits. Some older platforms need special physical address handling for
13718 * cursor planes.
13719 *
13720 * Must be called with struct_mutex held.
13721 *
13722 * Returns 0 on success, negative error code on failure.
13723 */
13724 int
13725 intel_prepare_plane_fb(struct drm_plane *plane,
13726 const struct drm_plane_state *new_state)
13727 {
13728 struct drm_device *dev = plane->dev;
13729 struct drm_framebuffer *fb = new_state->fb;
13730 struct intel_plane *intel_plane = to_intel_plane(plane);
13731 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13732 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13733 int ret = 0;
13734
13735 if (!obj && !old_obj)
13736 return 0;
13737
13738 if (old_obj) {
13739 struct drm_crtc_state *crtc_state =
13740 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13741
13742 /* Big Hammer, we also need to ensure that any pending
13743 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13744 * current scanout is retired before unpinning the old
13745 * framebuffer. Note that we rely on userspace rendering
13746 * into the buffer attached to the pipe they are waiting
13747 * on. If not, userspace generates a GPU hang with IPEHR
13748 * point to the MI_WAIT_FOR_EVENT.
13749 *
13750 * This should only fail upon a hung GPU, in which case we
13751 * can safely continue.
13752 */
13753 if (needs_modeset(crtc_state))
13754 ret = i915_gem_object_wait_rendering(old_obj, true);
13755
13756 /* Swallow -EIO errors to allow updates during hw lockup. */
13757 if (ret && ret != -EIO)
13758 return ret;
13759 }
13760
13761 /* For framebuffer backed by dmabuf, wait for fence */
13762 if (obj && obj->base.dma_buf) {
13763 long lret;
13764
13765 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13766 false, true,
13767 MAX_SCHEDULE_TIMEOUT);
13768 if (lret == -ERESTARTSYS)
13769 return lret;
13770
13771 WARN(lret < 0, "waiting returns %li\n", lret);
13772 }
13773
13774 if (!obj) {
13775 ret = 0;
13776 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13777 INTEL_INFO(dev)->cursor_needs_physical) {
13778 int align = IS_I830(dev) ? 16 * 1024 : 256;
13779 ret = i915_gem_object_attach_phys(obj, align);
13780 if (ret)
13781 DRM_DEBUG_KMS("failed to attach phys object\n");
13782 } else {
13783 ret = intel_pin_and_fence_fb_obj(fb, new_state->rotation);
13784 }
13785
13786 if (ret == 0) {
13787 if (obj) {
13788 struct intel_plane_state *plane_state =
13789 to_intel_plane_state(new_state);
13790
13791 i915_gem_request_assign(&plane_state->wait_req,
13792 obj->last_write_req);
13793 }
13794
13795 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13796 }
13797
13798 return ret;
13799 }
13800
13801 /**
13802 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13803 * @plane: drm plane to clean up for
13804 * @fb: old framebuffer that was on plane
13805 *
13806 * Cleans up a framebuffer that has just been removed from a plane.
13807 *
13808 * Must be called with struct_mutex held.
13809 */
13810 void
13811 intel_cleanup_plane_fb(struct drm_plane *plane,
13812 const struct drm_plane_state *old_state)
13813 {
13814 struct drm_device *dev = plane->dev;
13815 struct intel_plane *intel_plane = to_intel_plane(plane);
13816 struct intel_plane_state *old_intel_state;
13817 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13818 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13819
13820 old_intel_state = to_intel_plane_state(old_state);
13821
13822 if (!obj && !old_obj)
13823 return;
13824
13825 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13826 !INTEL_INFO(dev)->cursor_needs_physical))
13827 intel_unpin_fb_obj(old_state->fb, old_state->rotation);
13828
13829 /* prepare_fb aborted? */
13830 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13831 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13832 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13833
13834 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13835 }
13836
13837 int
13838 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13839 {
13840 int max_scale;
13841 struct drm_device *dev;
13842 struct drm_i915_private *dev_priv;
13843 int crtc_clock, cdclk;
13844
13845 if (!intel_crtc || !crtc_state->base.enable)
13846 return DRM_PLANE_HELPER_NO_SCALING;
13847
13848 dev = intel_crtc->base.dev;
13849 dev_priv = dev->dev_private;
13850 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13851 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13852
13853 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13854 return DRM_PLANE_HELPER_NO_SCALING;
13855
13856 /*
13857 * skl max scale is lower of:
13858 * close to 3 but not 3, -1 is for that purpose
13859 * or
13860 * cdclk/crtc_clock
13861 */
13862 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13863
13864 return max_scale;
13865 }
13866
13867 static int
13868 intel_check_primary_plane(struct drm_plane *plane,
13869 struct intel_crtc_state *crtc_state,
13870 struct intel_plane_state *state)
13871 {
13872 struct drm_crtc *crtc = state->base.crtc;
13873 struct drm_framebuffer *fb = state->base.fb;
13874 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13875 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13876 bool can_position = false;
13877
13878 if (INTEL_INFO(plane->dev)->gen >= 9) {
13879 /* use scaler when colorkey is not required */
13880 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13881 min_scale = 1;
13882 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13883 }
13884 can_position = true;
13885 }
13886
13887 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13888 &state->dst, &state->clip,
13889 min_scale, max_scale,
13890 can_position, true,
13891 &state->visible);
13892 }
13893
13894 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13895 struct drm_crtc_state *old_crtc_state)
13896 {
13897 struct drm_device *dev = crtc->dev;
13898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13899 struct intel_crtc_state *old_intel_state =
13900 to_intel_crtc_state(old_crtc_state);
13901 bool modeset = needs_modeset(crtc->state);
13902
13903 /* Perform vblank evasion around commit operation */
13904 intel_pipe_update_start(intel_crtc);
13905
13906 if (modeset)
13907 return;
13908
13909 if (crtc->state->color_mgmt_changed || to_intel_crtc_state(crtc->state)->update_pipe) {
13910 intel_color_set_csc(crtc->state);
13911 intel_color_load_luts(crtc->state);
13912 }
13913
13914 if (to_intel_crtc_state(crtc->state)->update_pipe)
13915 intel_update_pipe_config(intel_crtc, old_intel_state);
13916 else if (INTEL_INFO(dev)->gen >= 9)
13917 skl_detach_scalers(intel_crtc);
13918 }
13919
13920 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13921 struct drm_crtc_state *old_crtc_state)
13922 {
13923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13924
13925 intel_pipe_update_end(intel_crtc);
13926 }
13927
13928 /**
13929 * intel_plane_destroy - destroy a plane
13930 * @plane: plane to destroy
13931 *
13932 * Common destruction function for all types of planes (primary, cursor,
13933 * sprite).
13934 */
13935 void intel_plane_destroy(struct drm_plane *plane)
13936 {
13937 struct intel_plane *intel_plane = to_intel_plane(plane);
13938 drm_plane_cleanup(plane);
13939 kfree(intel_plane);
13940 }
13941
13942 const struct drm_plane_funcs intel_plane_funcs = {
13943 .update_plane = drm_atomic_helper_update_plane,
13944 .disable_plane = drm_atomic_helper_disable_plane,
13945 .destroy = intel_plane_destroy,
13946 .set_property = drm_atomic_helper_plane_set_property,
13947 .atomic_get_property = intel_plane_atomic_get_property,
13948 .atomic_set_property = intel_plane_atomic_set_property,
13949 .atomic_duplicate_state = intel_plane_duplicate_state,
13950 .atomic_destroy_state = intel_plane_destroy_state,
13951
13952 };
13953
13954 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13955 int pipe)
13956 {
13957 struct intel_plane *primary = NULL;
13958 struct intel_plane_state *state = NULL;
13959 const uint32_t *intel_primary_formats;
13960 unsigned int num_formats;
13961 int ret;
13962
13963 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13964 if (!primary)
13965 goto fail;
13966
13967 state = intel_create_plane_state(&primary->base);
13968 if (!state)
13969 goto fail;
13970 primary->base.state = &state->base;
13971
13972 primary->can_scale = false;
13973 primary->max_downscale = 1;
13974 if (INTEL_INFO(dev)->gen >= 9) {
13975 primary->can_scale = true;
13976 state->scaler_id = -1;
13977 }
13978 primary->pipe = pipe;
13979 primary->plane = pipe;
13980 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13981 primary->check_plane = intel_check_primary_plane;
13982 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13983 primary->plane = !pipe;
13984
13985 if (INTEL_INFO(dev)->gen >= 9) {
13986 intel_primary_formats = skl_primary_formats;
13987 num_formats = ARRAY_SIZE(skl_primary_formats);
13988
13989 primary->update_plane = skylake_update_primary_plane;
13990 primary->disable_plane = skylake_disable_primary_plane;
13991 } else if (HAS_PCH_SPLIT(dev)) {
13992 intel_primary_formats = i965_primary_formats;
13993 num_formats = ARRAY_SIZE(i965_primary_formats);
13994
13995 primary->update_plane = ironlake_update_primary_plane;
13996 primary->disable_plane = i9xx_disable_primary_plane;
13997 } else if (INTEL_INFO(dev)->gen >= 4) {
13998 intel_primary_formats = i965_primary_formats;
13999 num_formats = ARRAY_SIZE(i965_primary_formats);
14000
14001 primary->update_plane = i9xx_update_primary_plane;
14002 primary->disable_plane = i9xx_disable_primary_plane;
14003 } else {
14004 intel_primary_formats = i8xx_primary_formats;
14005 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14006
14007 primary->update_plane = i9xx_update_primary_plane;
14008 primary->disable_plane = i9xx_disable_primary_plane;
14009 }
14010
14011 ret = drm_universal_plane_init(dev, &primary->base, 0,
14012 &intel_plane_funcs,
14013 intel_primary_formats, num_formats,
14014 DRM_PLANE_TYPE_PRIMARY, NULL);
14015 if (ret)
14016 goto fail;
14017
14018 if (INTEL_INFO(dev)->gen >= 4)
14019 intel_create_rotation_property(dev, primary);
14020
14021 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14022
14023 return &primary->base;
14024
14025 fail:
14026 kfree(state);
14027 kfree(primary);
14028
14029 return NULL;
14030 }
14031
14032 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14033 {
14034 if (!dev->mode_config.rotation_property) {
14035 unsigned long flags = BIT(DRM_ROTATE_0) |
14036 BIT(DRM_ROTATE_180);
14037
14038 if (INTEL_INFO(dev)->gen >= 9)
14039 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14040
14041 dev->mode_config.rotation_property =
14042 drm_mode_create_rotation_property(dev, flags);
14043 }
14044 if (dev->mode_config.rotation_property)
14045 drm_object_attach_property(&plane->base.base,
14046 dev->mode_config.rotation_property,
14047 plane->base.state->rotation);
14048 }
14049
14050 static int
14051 intel_check_cursor_plane(struct drm_plane *plane,
14052 struct intel_crtc_state *crtc_state,
14053 struct intel_plane_state *state)
14054 {
14055 struct drm_crtc *crtc = crtc_state->base.crtc;
14056 struct drm_framebuffer *fb = state->base.fb;
14057 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14058 enum pipe pipe = to_intel_plane(plane)->pipe;
14059 unsigned stride;
14060 int ret;
14061
14062 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14063 &state->dst, &state->clip,
14064 DRM_PLANE_HELPER_NO_SCALING,
14065 DRM_PLANE_HELPER_NO_SCALING,
14066 true, true, &state->visible);
14067 if (ret)
14068 return ret;
14069
14070 /* if we want to turn off the cursor ignore width and height */
14071 if (!obj)
14072 return 0;
14073
14074 /* Check for which cursor types we support */
14075 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14076 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14077 state->base.crtc_w, state->base.crtc_h);
14078 return -EINVAL;
14079 }
14080
14081 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14082 if (obj->base.size < stride * state->base.crtc_h) {
14083 DRM_DEBUG_KMS("buffer is too small\n");
14084 return -ENOMEM;
14085 }
14086
14087 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14088 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14089 return -EINVAL;
14090 }
14091
14092 /*
14093 * There's something wrong with the cursor on CHV pipe C.
14094 * If it straddles the left edge of the screen then
14095 * moving it away from the edge or disabling it often
14096 * results in a pipe underrun, and often that can lead to
14097 * dead pipe (constant underrun reported, and it scans
14098 * out just a solid color). To recover from that, the
14099 * display power well must be turned off and on again.
14100 * Refuse the put the cursor into that compromised position.
14101 */
14102 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14103 state->visible && state->base.crtc_x < 0) {
14104 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14105 return -EINVAL;
14106 }
14107
14108 return 0;
14109 }
14110
14111 static void
14112 intel_disable_cursor_plane(struct drm_plane *plane,
14113 struct drm_crtc *crtc)
14114 {
14115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14116
14117 intel_crtc->cursor_addr = 0;
14118 intel_crtc_update_cursor(crtc, NULL);
14119 }
14120
14121 static void
14122 intel_update_cursor_plane(struct drm_plane *plane,
14123 const struct intel_crtc_state *crtc_state,
14124 const struct intel_plane_state *state)
14125 {
14126 struct drm_crtc *crtc = crtc_state->base.crtc;
14127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14128 struct drm_device *dev = plane->dev;
14129 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14130 uint32_t addr;
14131
14132 if (!obj)
14133 addr = 0;
14134 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14135 addr = i915_gem_obj_ggtt_offset(obj);
14136 else
14137 addr = obj->phys_handle->busaddr;
14138
14139 intel_crtc->cursor_addr = addr;
14140 intel_crtc_update_cursor(crtc, state);
14141 }
14142
14143 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14144 int pipe)
14145 {
14146 struct intel_plane *cursor = NULL;
14147 struct intel_plane_state *state = NULL;
14148 int ret;
14149
14150 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14151 if (!cursor)
14152 goto fail;
14153
14154 state = intel_create_plane_state(&cursor->base);
14155 if (!state)
14156 goto fail;
14157 cursor->base.state = &state->base;
14158
14159 cursor->can_scale = false;
14160 cursor->max_downscale = 1;
14161 cursor->pipe = pipe;
14162 cursor->plane = pipe;
14163 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14164 cursor->check_plane = intel_check_cursor_plane;
14165 cursor->update_plane = intel_update_cursor_plane;
14166 cursor->disable_plane = intel_disable_cursor_plane;
14167
14168 ret = drm_universal_plane_init(dev, &cursor->base, 0,
14169 &intel_plane_funcs,
14170 intel_cursor_formats,
14171 ARRAY_SIZE(intel_cursor_formats),
14172 DRM_PLANE_TYPE_CURSOR, NULL);
14173 if (ret)
14174 goto fail;
14175
14176 if (INTEL_INFO(dev)->gen >= 4) {
14177 if (!dev->mode_config.rotation_property)
14178 dev->mode_config.rotation_property =
14179 drm_mode_create_rotation_property(dev,
14180 BIT(DRM_ROTATE_0) |
14181 BIT(DRM_ROTATE_180));
14182 if (dev->mode_config.rotation_property)
14183 drm_object_attach_property(&cursor->base.base,
14184 dev->mode_config.rotation_property,
14185 state->base.rotation);
14186 }
14187
14188 if (INTEL_INFO(dev)->gen >=9)
14189 state->scaler_id = -1;
14190
14191 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14192
14193 return &cursor->base;
14194
14195 fail:
14196 kfree(state);
14197 kfree(cursor);
14198
14199 return NULL;
14200 }
14201
14202 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14203 struct intel_crtc_state *crtc_state)
14204 {
14205 int i;
14206 struct intel_scaler *intel_scaler;
14207 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14208
14209 for (i = 0; i < intel_crtc->num_scalers; i++) {
14210 intel_scaler = &scaler_state->scalers[i];
14211 intel_scaler->in_use = 0;
14212 intel_scaler->mode = PS_SCALER_MODE_DYN;
14213 }
14214
14215 scaler_state->scaler_id = -1;
14216 }
14217
14218 static void intel_crtc_init(struct drm_device *dev, int pipe)
14219 {
14220 struct drm_i915_private *dev_priv = dev->dev_private;
14221 struct intel_crtc *intel_crtc;
14222 struct intel_crtc_state *crtc_state = NULL;
14223 struct drm_plane *primary = NULL;
14224 struct drm_plane *cursor = NULL;
14225 int ret;
14226
14227 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14228 if (intel_crtc == NULL)
14229 return;
14230
14231 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14232 if (!crtc_state)
14233 goto fail;
14234 intel_crtc->config = crtc_state;
14235 intel_crtc->base.state = &crtc_state->base;
14236 crtc_state->base.crtc = &intel_crtc->base;
14237
14238 /* initialize shared scalers */
14239 if (INTEL_INFO(dev)->gen >= 9) {
14240 if (pipe == PIPE_C)
14241 intel_crtc->num_scalers = 1;
14242 else
14243 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14244
14245 skl_init_scalers(dev, intel_crtc, crtc_state);
14246 }
14247
14248 primary = intel_primary_plane_create(dev, pipe);
14249 if (!primary)
14250 goto fail;
14251
14252 cursor = intel_cursor_plane_create(dev, pipe);
14253 if (!cursor)
14254 goto fail;
14255
14256 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14257 cursor, &intel_crtc_funcs, NULL);
14258 if (ret)
14259 goto fail;
14260
14261 /*
14262 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14263 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14264 */
14265 intel_crtc->pipe = pipe;
14266 intel_crtc->plane = pipe;
14267 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14268 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14269 intel_crtc->plane = !pipe;
14270 }
14271
14272 intel_crtc->cursor_base = ~0;
14273 intel_crtc->cursor_cntl = ~0;
14274 intel_crtc->cursor_size = ~0;
14275
14276 intel_crtc->wm.cxsr_allowed = true;
14277
14278 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14279 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14280 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14281 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14282
14283 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14284
14285 intel_color_init(&intel_crtc->base);
14286
14287 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14288 return;
14289
14290 fail:
14291 if (primary)
14292 drm_plane_cleanup(primary);
14293 if (cursor)
14294 drm_plane_cleanup(cursor);
14295 kfree(crtc_state);
14296 kfree(intel_crtc);
14297 }
14298
14299 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14300 {
14301 struct drm_encoder *encoder = connector->base.encoder;
14302 struct drm_device *dev = connector->base.dev;
14303
14304 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14305
14306 if (!encoder || WARN_ON(!encoder->crtc))
14307 return INVALID_PIPE;
14308
14309 return to_intel_crtc(encoder->crtc)->pipe;
14310 }
14311
14312 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14313 struct drm_file *file)
14314 {
14315 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14316 struct drm_crtc *drmmode_crtc;
14317 struct intel_crtc *crtc;
14318
14319 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14320
14321 if (!drmmode_crtc) {
14322 DRM_ERROR("no such CRTC id\n");
14323 return -ENOENT;
14324 }
14325
14326 crtc = to_intel_crtc(drmmode_crtc);
14327 pipe_from_crtc_id->pipe = crtc->pipe;
14328
14329 return 0;
14330 }
14331
14332 static int intel_encoder_clones(struct intel_encoder *encoder)
14333 {
14334 struct drm_device *dev = encoder->base.dev;
14335 struct intel_encoder *source_encoder;
14336 int index_mask = 0;
14337 int entry = 0;
14338
14339 for_each_intel_encoder(dev, source_encoder) {
14340 if (encoders_cloneable(encoder, source_encoder))
14341 index_mask |= (1 << entry);
14342
14343 entry++;
14344 }
14345
14346 return index_mask;
14347 }
14348
14349 static bool has_edp_a(struct drm_device *dev)
14350 {
14351 struct drm_i915_private *dev_priv = dev->dev_private;
14352
14353 if (!IS_MOBILE(dev))
14354 return false;
14355
14356 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14357 return false;
14358
14359 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14360 return false;
14361
14362 return true;
14363 }
14364
14365 static bool intel_crt_present(struct drm_device *dev)
14366 {
14367 struct drm_i915_private *dev_priv = dev->dev_private;
14368
14369 if (INTEL_INFO(dev)->gen >= 9)
14370 return false;
14371
14372 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14373 return false;
14374
14375 if (IS_CHERRYVIEW(dev))
14376 return false;
14377
14378 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14379 return false;
14380
14381 /* DDI E can't be used if DDI A requires 4 lanes */
14382 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14383 return false;
14384
14385 if (!dev_priv->vbt.int_crt_support)
14386 return false;
14387
14388 return true;
14389 }
14390
14391 static void intel_setup_outputs(struct drm_device *dev)
14392 {
14393 struct drm_i915_private *dev_priv = dev->dev_private;
14394 struct intel_encoder *encoder;
14395 bool dpd_is_edp = false;
14396
14397 intel_lvds_init(dev);
14398
14399 if (intel_crt_present(dev))
14400 intel_crt_init(dev);
14401
14402 if (IS_BROXTON(dev)) {
14403 /*
14404 * FIXME: Broxton doesn't support port detection via the
14405 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14406 * detect the ports.
14407 */
14408 intel_ddi_init(dev, PORT_A);
14409 intel_ddi_init(dev, PORT_B);
14410 intel_ddi_init(dev, PORT_C);
14411
14412 intel_dsi_init(dev);
14413 } else if (HAS_DDI(dev)) {
14414 int found;
14415
14416 /*
14417 * Haswell uses DDI functions to detect digital outputs.
14418 * On SKL pre-D0 the strap isn't connected, so we assume
14419 * it's there.
14420 */
14421 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14422 /* WaIgnoreDDIAStrap: skl */
14423 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14424 intel_ddi_init(dev, PORT_A);
14425
14426 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14427 * register */
14428 found = I915_READ(SFUSE_STRAP);
14429
14430 if (found & SFUSE_STRAP_DDIB_DETECTED)
14431 intel_ddi_init(dev, PORT_B);
14432 if (found & SFUSE_STRAP_DDIC_DETECTED)
14433 intel_ddi_init(dev, PORT_C);
14434 if (found & SFUSE_STRAP_DDID_DETECTED)
14435 intel_ddi_init(dev, PORT_D);
14436 /*
14437 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14438 */
14439 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14440 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14441 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14442 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14443 intel_ddi_init(dev, PORT_E);
14444
14445 } else if (HAS_PCH_SPLIT(dev)) {
14446 int found;
14447 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14448
14449 if (has_edp_a(dev))
14450 intel_dp_init(dev, DP_A, PORT_A);
14451
14452 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14453 /* PCH SDVOB multiplex with HDMIB */
14454 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14455 if (!found)
14456 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14457 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14458 intel_dp_init(dev, PCH_DP_B, PORT_B);
14459 }
14460
14461 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14462 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14463
14464 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14465 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14466
14467 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14468 intel_dp_init(dev, PCH_DP_C, PORT_C);
14469
14470 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14471 intel_dp_init(dev, PCH_DP_D, PORT_D);
14472 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14473 /*
14474 * The DP_DETECTED bit is the latched state of the DDC
14475 * SDA pin at boot. However since eDP doesn't require DDC
14476 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14477 * eDP ports may have been muxed to an alternate function.
14478 * Thus we can't rely on the DP_DETECTED bit alone to detect
14479 * eDP ports. Consult the VBT as well as DP_DETECTED to
14480 * detect eDP ports.
14481 */
14482 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14483 !intel_dp_is_edp(dev, PORT_B))
14484 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14485 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14486 intel_dp_is_edp(dev, PORT_B))
14487 intel_dp_init(dev, VLV_DP_B, PORT_B);
14488
14489 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14490 !intel_dp_is_edp(dev, PORT_C))
14491 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14492 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14493 intel_dp_is_edp(dev, PORT_C))
14494 intel_dp_init(dev, VLV_DP_C, PORT_C);
14495
14496 if (IS_CHERRYVIEW(dev)) {
14497 /* eDP not supported on port D, so don't check VBT */
14498 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14499 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14500 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14501 intel_dp_init(dev, CHV_DP_D, PORT_D);
14502 }
14503
14504 intel_dsi_init(dev);
14505 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14506 bool found = false;
14507
14508 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14509 DRM_DEBUG_KMS("probing SDVOB\n");
14510 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14511 if (!found && IS_G4X(dev)) {
14512 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14513 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14514 }
14515
14516 if (!found && IS_G4X(dev))
14517 intel_dp_init(dev, DP_B, PORT_B);
14518 }
14519
14520 /* Before G4X SDVOC doesn't have its own detect register */
14521
14522 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14523 DRM_DEBUG_KMS("probing SDVOC\n");
14524 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14525 }
14526
14527 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14528
14529 if (IS_G4X(dev)) {
14530 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14531 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14532 }
14533 if (IS_G4X(dev))
14534 intel_dp_init(dev, DP_C, PORT_C);
14535 }
14536
14537 if (IS_G4X(dev) &&
14538 (I915_READ(DP_D) & DP_DETECTED))
14539 intel_dp_init(dev, DP_D, PORT_D);
14540 } else if (IS_GEN2(dev))
14541 intel_dvo_init(dev);
14542
14543 if (SUPPORTS_TV(dev))
14544 intel_tv_init(dev);
14545
14546 intel_psr_init(dev);
14547
14548 for_each_intel_encoder(dev, encoder) {
14549 encoder->base.possible_crtcs = encoder->crtc_mask;
14550 encoder->base.possible_clones =
14551 intel_encoder_clones(encoder);
14552 }
14553
14554 intel_init_pch_refclk(dev);
14555
14556 drm_helper_move_panel_connectors_to_head(dev);
14557 }
14558
14559 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14560 {
14561 struct drm_device *dev = fb->dev;
14562 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14563
14564 drm_framebuffer_cleanup(fb);
14565 mutex_lock(&dev->struct_mutex);
14566 WARN_ON(!intel_fb->obj->framebuffer_references--);
14567 drm_gem_object_unreference(&intel_fb->obj->base);
14568 mutex_unlock(&dev->struct_mutex);
14569 kfree(intel_fb);
14570 }
14571
14572 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14573 struct drm_file *file,
14574 unsigned int *handle)
14575 {
14576 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14577 struct drm_i915_gem_object *obj = intel_fb->obj;
14578
14579 if (obj->userptr.mm) {
14580 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14581 return -EINVAL;
14582 }
14583
14584 return drm_gem_handle_create(file, &obj->base, handle);
14585 }
14586
14587 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14588 struct drm_file *file,
14589 unsigned flags, unsigned color,
14590 struct drm_clip_rect *clips,
14591 unsigned num_clips)
14592 {
14593 struct drm_device *dev = fb->dev;
14594 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14595 struct drm_i915_gem_object *obj = intel_fb->obj;
14596
14597 mutex_lock(&dev->struct_mutex);
14598 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14599 mutex_unlock(&dev->struct_mutex);
14600
14601 return 0;
14602 }
14603
14604 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14605 .destroy = intel_user_framebuffer_destroy,
14606 .create_handle = intel_user_framebuffer_create_handle,
14607 .dirty = intel_user_framebuffer_dirty,
14608 };
14609
14610 static
14611 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14612 uint32_t pixel_format)
14613 {
14614 u32 gen = INTEL_INFO(dev)->gen;
14615
14616 if (gen >= 9) {
14617 int cpp = drm_format_plane_cpp(pixel_format, 0);
14618
14619 /* "The stride in bytes must not exceed the of the size of 8K
14620 * pixels and 32K bytes."
14621 */
14622 return min(8192 * cpp, 32768);
14623 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14624 return 32*1024;
14625 } else if (gen >= 4) {
14626 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14627 return 16*1024;
14628 else
14629 return 32*1024;
14630 } else if (gen >= 3) {
14631 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14632 return 8*1024;
14633 else
14634 return 16*1024;
14635 } else {
14636 /* XXX DSPC is limited to 4k tiled */
14637 return 8*1024;
14638 }
14639 }
14640
14641 static int intel_framebuffer_init(struct drm_device *dev,
14642 struct intel_framebuffer *intel_fb,
14643 struct drm_mode_fb_cmd2 *mode_cmd,
14644 struct drm_i915_gem_object *obj)
14645 {
14646 struct drm_i915_private *dev_priv = to_i915(dev);
14647 unsigned int aligned_height;
14648 int ret;
14649 u32 pitch_limit, stride_alignment;
14650
14651 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14652
14653 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14654 /* Enforce that fb modifier and tiling mode match, but only for
14655 * X-tiled. This is needed for FBC. */
14656 if (!!(obj->tiling_mode == I915_TILING_X) !=
14657 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14658 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14659 return -EINVAL;
14660 }
14661 } else {
14662 if (obj->tiling_mode == I915_TILING_X)
14663 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14664 else if (obj->tiling_mode == I915_TILING_Y) {
14665 DRM_DEBUG("No Y tiling for legacy addfb\n");
14666 return -EINVAL;
14667 }
14668 }
14669
14670 /* Passed in modifier sanity checking. */
14671 switch (mode_cmd->modifier[0]) {
14672 case I915_FORMAT_MOD_Y_TILED:
14673 case I915_FORMAT_MOD_Yf_TILED:
14674 if (INTEL_INFO(dev)->gen < 9) {
14675 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14676 mode_cmd->modifier[0]);
14677 return -EINVAL;
14678 }
14679 case DRM_FORMAT_MOD_NONE:
14680 case I915_FORMAT_MOD_X_TILED:
14681 break;
14682 default:
14683 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14684 mode_cmd->modifier[0]);
14685 return -EINVAL;
14686 }
14687
14688 stride_alignment = intel_fb_stride_alignment(dev_priv,
14689 mode_cmd->modifier[0],
14690 mode_cmd->pixel_format);
14691 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14692 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14693 mode_cmd->pitches[0], stride_alignment);
14694 return -EINVAL;
14695 }
14696
14697 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14698 mode_cmd->pixel_format);
14699 if (mode_cmd->pitches[0] > pitch_limit) {
14700 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14701 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14702 "tiled" : "linear",
14703 mode_cmd->pitches[0], pitch_limit);
14704 return -EINVAL;
14705 }
14706
14707 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14708 mode_cmd->pitches[0] != obj->stride) {
14709 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14710 mode_cmd->pitches[0], obj->stride);
14711 return -EINVAL;
14712 }
14713
14714 /* Reject formats not supported by any plane early. */
14715 switch (mode_cmd->pixel_format) {
14716 case DRM_FORMAT_C8:
14717 case DRM_FORMAT_RGB565:
14718 case DRM_FORMAT_XRGB8888:
14719 case DRM_FORMAT_ARGB8888:
14720 break;
14721 case DRM_FORMAT_XRGB1555:
14722 if (INTEL_INFO(dev)->gen > 3) {
14723 DRM_DEBUG("unsupported pixel format: %s\n",
14724 drm_get_format_name(mode_cmd->pixel_format));
14725 return -EINVAL;
14726 }
14727 break;
14728 case DRM_FORMAT_ABGR8888:
14729 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14730 INTEL_INFO(dev)->gen < 9) {
14731 DRM_DEBUG("unsupported pixel format: %s\n",
14732 drm_get_format_name(mode_cmd->pixel_format));
14733 return -EINVAL;
14734 }
14735 break;
14736 case DRM_FORMAT_XBGR8888:
14737 case DRM_FORMAT_XRGB2101010:
14738 case DRM_FORMAT_XBGR2101010:
14739 if (INTEL_INFO(dev)->gen < 4) {
14740 DRM_DEBUG("unsupported pixel format: %s\n",
14741 drm_get_format_name(mode_cmd->pixel_format));
14742 return -EINVAL;
14743 }
14744 break;
14745 case DRM_FORMAT_ABGR2101010:
14746 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14747 DRM_DEBUG("unsupported pixel format: %s\n",
14748 drm_get_format_name(mode_cmd->pixel_format));
14749 return -EINVAL;
14750 }
14751 break;
14752 case DRM_FORMAT_YUYV:
14753 case DRM_FORMAT_UYVY:
14754 case DRM_FORMAT_YVYU:
14755 case DRM_FORMAT_VYUY:
14756 if (INTEL_INFO(dev)->gen < 5) {
14757 DRM_DEBUG("unsupported pixel format: %s\n",
14758 drm_get_format_name(mode_cmd->pixel_format));
14759 return -EINVAL;
14760 }
14761 break;
14762 default:
14763 DRM_DEBUG("unsupported pixel format: %s\n",
14764 drm_get_format_name(mode_cmd->pixel_format));
14765 return -EINVAL;
14766 }
14767
14768 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14769 if (mode_cmd->offsets[0] != 0)
14770 return -EINVAL;
14771
14772 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14773 mode_cmd->pixel_format,
14774 mode_cmd->modifier[0]);
14775 /* FIXME drm helper for size checks (especially planar formats)? */
14776 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14777 return -EINVAL;
14778
14779 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14780 intel_fb->obj = obj;
14781
14782 intel_fill_fb_info(dev_priv, &intel_fb->base);
14783
14784 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14785 if (ret) {
14786 DRM_ERROR("framebuffer init failed %d\n", ret);
14787 return ret;
14788 }
14789
14790 intel_fb->obj->framebuffer_references++;
14791
14792 return 0;
14793 }
14794
14795 static struct drm_framebuffer *
14796 intel_user_framebuffer_create(struct drm_device *dev,
14797 struct drm_file *filp,
14798 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14799 {
14800 struct drm_framebuffer *fb;
14801 struct drm_i915_gem_object *obj;
14802 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14803
14804 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14805 mode_cmd.handles[0]));
14806 if (&obj->base == NULL)
14807 return ERR_PTR(-ENOENT);
14808
14809 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14810 if (IS_ERR(fb))
14811 drm_gem_object_unreference_unlocked(&obj->base);
14812
14813 return fb;
14814 }
14815
14816 #ifndef CONFIG_DRM_FBDEV_EMULATION
14817 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14818 {
14819 }
14820 #endif
14821
14822 static const struct drm_mode_config_funcs intel_mode_funcs = {
14823 .fb_create = intel_user_framebuffer_create,
14824 .output_poll_changed = intel_fbdev_output_poll_changed,
14825 .atomic_check = intel_atomic_check,
14826 .atomic_commit = intel_atomic_commit,
14827 .atomic_state_alloc = intel_atomic_state_alloc,
14828 .atomic_state_clear = intel_atomic_state_clear,
14829 };
14830
14831 /**
14832 * intel_init_display_hooks - initialize the display modesetting hooks
14833 * @dev_priv: device private
14834 */
14835 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
14836 {
14837 if (INTEL_INFO(dev_priv)->gen >= 9) {
14838 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14839 dev_priv->display.get_initial_plane_config =
14840 skylake_get_initial_plane_config;
14841 dev_priv->display.crtc_compute_clock =
14842 haswell_crtc_compute_clock;
14843 dev_priv->display.crtc_enable = haswell_crtc_enable;
14844 dev_priv->display.crtc_disable = haswell_crtc_disable;
14845 } else if (HAS_DDI(dev_priv)) {
14846 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14847 dev_priv->display.get_initial_plane_config =
14848 ironlake_get_initial_plane_config;
14849 dev_priv->display.crtc_compute_clock =
14850 haswell_crtc_compute_clock;
14851 dev_priv->display.crtc_enable = haswell_crtc_enable;
14852 dev_priv->display.crtc_disable = haswell_crtc_disable;
14853 } else if (HAS_PCH_SPLIT(dev_priv)) {
14854 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14855 dev_priv->display.get_initial_plane_config =
14856 ironlake_get_initial_plane_config;
14857 dev_priv->display.crtc_compute_clock =
14858 ironlake_crtc_compute_clock;
14859 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14860 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14861 } else if (IS_CHERRYVIEW(dev_priv)) {
14862 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14863 dev_priv->display.get_initial_plane_config =
14864 i9xx_get_initial_plane_config;
14865 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock;
14866 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14867 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14868 } else if (IS_VALLEYVIEW(dev_priv)) {
14869 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14870 dev_priv->display.get_initial_plane_config =
14871 i9xx_get_initial_plane_config;
14872 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock;
14873 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14874 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14875 } else if (IS_G4X(dev_priv)) {
14876 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14877 dev_priv->display.get_initial_plane_config =
14878 i9xx_get_initial_plane_config;
14879 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock;
14880 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14881 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14882 } else if (IS_PINEVIEW(dev_priv)) {
14883 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14884 dev_priv->display.get_initial_plane_config =
14885 i9xx_get_initial_plane_config;
14886 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock;
14887 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14888 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14889 } else if (!IS_GEN2(dev_priv)) {
14890 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14891 dev_priv->display.get_initial_plane_config =
14892 i9xx_get_initial_plane_config;
14893 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14894 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14895 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14896 } else {
14897 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14898 dev_priv->display.get_initial_plane_config =
14899 i9xx_get_initial_plane_config;
14900 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock;
14901 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14902 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14903 }
14904
14905 /* Returns the core display clock speed */
14906 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
14907 dev_priv->display.get_display_clock_speed =
14908 skylake_get_display_clock_speed;
14909 else if (IS_BROXTON(dev_priv))
14910 dev_priv->display.get_display_clock_speed =
14911 broxton_get_display_clock_speed;
14912 else if (IS_BROADWELL(dev_priv))
14913 dev_priv->display.get_display_clock_speed =
14914 broadwell_get_display_clock_speed;
14915 else if (IS_HASWELL(dev_priv))
14916 dev_priv->display.get_display_clock_speed =
14917 haswell_get_display_clock_speed;
14918 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
14919 dev_priv->display.get_display_clock_speed =
14920 valleyview_get_display_clock_speed;
14921 else if (IS_GEN5(dev_priv))
14922 dev_priv->display.get_display_clock_speed =
14923 ilk_get_display_clock_speed;
14924 else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
14925 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
14926 dev_priv->display.get_display_clock_speed =
14927 i945_get_display_clock_speed;
14928 else if (IS_GM45(dev_priv))
14929 dev_priv->display.get_display_clock_speed =
14930 gm45_get_display_clock_speed;
14931 else if (IS_CRESTLINE(dev_priv))
14932 dev_priv->display.get_display_clock_speed =
14933 i965gm_get_display_clock_speed;
14934 else if (IS_PINEVIEW(dev_priv))
14935 dev_priv->display.get_display_clock_speed =
14936 pnv_get_display_clock_speed;
14937 else if (IS_G33(dev_priv) || IS_G4X(dev_priv))
14938 dev_priv->display.get_display_clock_speed =
14939 g33_get_display_clock_speed;
14940 else if (IS_I915G(dev_priv))
14941 dev_priv->display.get_display_clock_speed =
14942 i915_get_display_clock_speed;
14943 else if (IS_I945GM(dev_priv) || IS_845G(dev_priv))
14944 dev_priv->display.get_display_clock_speed =
14945 i9xx_misc_get_display_clock_speed;
14946 else if (IS_I915GM(dev_priv))
14947 dev_priv->display.get_display_clock_speed =
14948 i915gm_get_display_clock_speed;
14949 else if (IS_I865G(dev_priv))
14950 dev_priv->display.get_display_clock_speed =
14951 i865_get_display_clock_speed;
14952 else if (IS_I85X(dev_priv))
14953 dev_priv->display.get_display_clock_speed =
14954 i85x_get_display_clock_speed;
14955 else { /* 830 */
14956 WARN(!IS_I830(dev_priv), "Unknown platform. Assuming 133 MHz CDCLK\n");
14957 dev_priv->display.get_display_clock_speed =
14958 i830_get_display_clock_speed;
14959 }
14960
14961 if (IS_GEN5(dev_priv)) {
14962 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14963 } else if (IS_GEN6(dev_priv)) {
14964 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14965 } else if (IS_IVYBRIDGE(dev_priv)) {
14966 /* FIXME: detect B0+ stepping and use auto training */
14967 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14968 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
14969 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14970 if (IS_BROADWELL(dev_priv)) {
14971 dev_priv->display.modeset_commit_cdclk =
14972 broadwell_modeset_commit_cdclk;
14973 dev_priv->display.modeset_calc_cdclk =
14974 broadwell_modeset_calc_cdclk;
14975 }
14976 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
14977 dev_priv->display.modeset_commit_cdclk =
14978 valleyview_modeset_commit_cdclk;
14979 dev_priv->display.modeset_calc_cdclk =
14980 valleyview_modeset_calc_cdclk;
14981 } else if (IS_BROXTON(dev_priv)) {
14982 dev_priv->display.modeset_commit_cdclk =
14983 broxton_modeset_commit_cdclk;
14984 dev_priv->display.modeset_calc_cdclk =
14985 broxton_modeset_calc_cdclk;
14986 }
14987
14988 switch (INTEL_INFO(dev_priv)->gen) {
14989 case 2:
14990 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14991 break;
14992
14993 case 3:
14994 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14995 break;
14996
14997 case 4:
14998 case 5:
14999 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15000 break;
15001
15002 case 6:
15003 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15004 break;
15005 case 7:
15006 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15007 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15008 break;
15009 case 9:
15010 /* Drop through - unsupported since execlist only. */
15011 default:
15012 /* Default just returns -ENODEV to indicate unsupported */
15013 dev_priv->display.queue_flip = intel_default_queue_flip;
15014 }
15015 }
15016
15017 /*
15018 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15019 * resume, or other times. This quirk makes sure that's the case for
15020 * affected systems.
15021 */
15022 static void quirk_pipea_force(struct drm_device *dev)
15023 {
15024 struct drm_i915_private *dev_priv = dev->dev_private;
15025
15026 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15027 DRM_INFO("applying pipe a force quirk\n");
15028 }
15029
15030 static void quirk_pipeb_force(struct drm_device *dev)
15031 {
15032 struct drm_i915_private *dev_priv = dev->dev_private;
15033
15034 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15035 DRM_INFO("applying pipe b force quirk\n");
15036 }
15037
15038 /*
15039 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15040 */
15041 static void quirk_ssc_force_disable(struct drm_device *dev)
15042 {
15043 struct drm_i915_private *dev_priv = dev->dev_private;
15044 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15045 DRM_INFO("applying lvds SSC disable quirk\n");
15046 }
15047
15048 /*
15049 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15050 * brightness value
15051 */
15052 static void quirk_invert_brightness(struct drm_device *dev)
15053 {
15054 struct drm_i915_private *dev_priv = dev->dev_private;
15055 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15056 DRM_INFO("applying inverted panel brightness quirk\n");
15057 }
15058
15059 /* Some VBT's incorrectly indicate no backlight is present */
15060 static void quirk_backlight_present(struct drm_device *dev)
15061 {
15062 struct drm_i915_private *dev_priv = dev->dev_private;
15063 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15064 DRM_INFO("applying backlight present quirk\n");
15065 }
15066
15067 struct intel_quirk {
15068 int device;
15069 int subsystem_vendor;
15070 int subsystem_device;
15071 void (*hook)(struct drm_device *dev);
15072 };
15073
15074 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15075 struct intel_dmi_quirk {
15076 void (*hook)(struct drm_device *dev);
15077 const struct dmi_system_id (*dmi_id_list)[];
15078 };
15079
15080 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15081 {
15082 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15083 return 1;
15084 }
15085
15086 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15087 {
15088 .dmi_id_list = &(const struct dmi_system_id[]) {
15089 {
15090 .callback = intel_dmi_reverse_brightness,
15091 .ident = "NCR Corporation",
15092 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15093 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15094 },
15095 },
15096 { } /* terminating entry */
15097 },
15098 .hook = quirk_invert_brightness,
15099 },
15100 };
15101
15102 static struct intel_quirk intel_quirks[] = {
15103 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15104 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15105
15106 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15107 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15108
15109 /* 830 needs to leave pipe A & dpll A up */
15110 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15111
15112 /* 830 needs to leave pipe B & dpll B up */
15113 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15114
15115 /* Lenovo U160 cannot use SSC on LVDS */
15116 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15117
15118 /* Sony Vaio Y cannot use SSC on LVDS */
15119 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15120
15121 /* Acer Aspire 5734Z must invert backlight brightness */
15122 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15123
15124 /* Acer/eMachines G725 */
15125 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15126
15127 /* Acer/eMachines e725 */
15128 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15129
15130 /* Acer/Packard Bell NCL20 */
15131 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15132
15133 /* Acer Aspire 4736Z */
15134 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15135
15136 /* Acer Aspire 5336 */
15137 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15138
15139 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15140 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15141
15142 /* Acer C720 Chromebook (Core i3 4005U) */
15143 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15144
15145 /* Apple Macbook 2,1 (Core 2 T7400) */
15146 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15147
15148 /* Apple Macbook 4,1 */
15149 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15150
15151 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15152 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15153
15154 /* HP Chromebook 14 (Celeron 2955U) */
15155 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15156
15157 /* Dell Chromebook 11 */
15158 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15159
15160 /* Dell Chromebook 11 (2015 version) */
15161 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15162 };
15163
15164 static void intel_init_quirks(struct drm_device *dev)
15165 {
15166 struct pci_dev *d = dev->pdev;
15167 int i;
15168
15169 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15170 struct intel_quirk *q = &intel_quirks[i];
15171
15172 if (d->device == q->device &&
15173 (d->subsystem_vendor == q->subsystem_vendor ||
15174 q->subsystem_vendor == PCI_ANY_ID) &&
15175 (d->subsystem_device == q->subsystem_device ||
15176 q->subsystem_device == PCI_ANY_ID))
15177 q->hook(dev);
15178 }
15179 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15180 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15181 intel_dmi_quirks[i].hook(dev);
15182 }
15183 }
15184
15185 /* Disable the VGA plane that we never use */
15186 static void i915_disable_vga(struct drm_device *dev)
15187 {
15188 struct drm_i915_private *dev_priv = dev->dev_private;
15189 u8 sr1;
15190 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15191
15192 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15193 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15194 outb(SR01, VGA_SR_INDEX);
15195 sr1 = inb(VGA_SR_DATA);
15196 outb(sr1 | 1<<5, VGA_SR_DATA);
15197 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15198 udelay(300);
15199
15200 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15201 POSTING_READ(vga_reg);
15202 }
15203
15204 void intel_modeset_init_hw(struct drm_device *dev)
15205 {
15206 struct drm_i915_private *dev_priv = dev->dev_private;
15207
15208 intel_update_cdclk(dev);
15209
15210 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15211
15212 intel_init_clock_gating(dev);
15213 intel_enable_gt_powersave(dev);
15214 }
15215
15216 /*
15217 * Calculate what we think the watermarks should be for the state we've read
15218 * out of the hardware and then immediately program those watermarks so that
15219 * we ensure the hardware settings match our internal state.
15220 *
15221 * We can calculate what we think WM's should be by creating a duplicate of the
15222 * current state (which was constructed during hardware readout) and running it
15223 * through the atomic check code to calculate new watermark values in the
15224 * state object.
15225 */
15226 static void sanitize_watermarks(struct drm_device *dev)
15227 {
15228 struct drm_i915_private *dev_priv = to_i915(dev);
15229 struct drm_atomic_state *state;
15230 struct drm_crtc *crtc;
15231 struct drm_crtc_state *cstate;
15232 struct drm_modeset_acquire_ctx ctx;
15233 int ret;
15234 int i;
15235
15236 /* Only supported on platforms that use atomic watermark design */
15237 if (!dev_priv->display.optimize_watermarks)
15238 return;
15239
15240 /*
15241 * We need to hold connection_mutex before calling duplicate_state so
15242 * that the connector loop is protected.
15243 */
15244 drm_modeset_acquire_init(&ctx, 0);
15245 retry:
15246 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15247 if (ret == -EDEADLK) {
15248 drm_modeset_backoff(&ctx);
15249 goto retry;
15250 } else if (WARN_ON(ret)) {
15251 goto fail;
15252 }
15253
15254 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15255 if (WARN_ON(IS_ERR(state)))
15256 goto fail;
15257
15258 /*
15259 * Hardware readout is the only time we don't want to calculate
15260 * intermediate watermarks (since we don't trust the current
15261 * watermarks).
15262 */
15263 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15264
15265 ret = intel_atomic_check(dev, state);
15266 if (ret) {
15267 /*
15268 * If we fail here, it means that the hardware appears to be
15269 * programmed in a way that shouldn't be possible, given our
15270 * understanding of watermark requirements. This might mean a
15271 * mistake in the hardware readout code or a mistake in the
15272 * watermark calculations for a given platform. Raise a WARN
15273 * so that this is noticeable.
15274 *
15275 * If this actually happens, we'll have to just leave the
15276 * BIOS-programmed watermarks untouched and hope for the best.
15277 */
15278 WARN(true, "Could not determine valid watermarks for inherited state\n");
15279 goto fail;
15280 }
15281
15282 /* Write calculated watermark values back */
15283 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15284 for_each_crtc_in_state(state, crtc, cstate, i) {
15285 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15286
15287 cs->wm.need_postvbl_update = true;
15288 dev_priv->display.optimize_watermarks(cs);
15289 }
15290
15291 drm_atomic_state_free(state);
15292 fail:
15293 drm_modeset_drop_locks(&ctx);
15294 drm_modeset_acquire_fini(&ctx);
15295 }
15296
15297 void intel_modeset_init(struct drm_device *dev)
15298 {
15299 struct drm_i915_private *dev_priv = to_i915(dev);
15300 struct i915_ggtt *ggtt = &dev_priv->ggtt;
15301 int sprite, ret;
15302 enum pipe pipe;
15303 struct intel_crtc *crtc;
15304
15305 drm_mode_config_init(dev);
15306
15307 dev->mode_config.min_width = 0;
15308 dev->mode_config.min_height = 0;
15309
15310 dev->mode_config.preferred_depth = 24;
15311 dev->mode_config.prefer_shadow = 1;
15312
15313 dev->mode_config.allow_fb_modifiers = true;
15314
15315 dev->mode_config.funcs = &intel_mode_funcs;
15316
15317 intel_init_quirks(dev);
15318
15319 intel_init_pm(dev);
15320
15321 if (INTEL_INFO(dev)->num_pipes == 0)
15322 return;
15323
15324 /*
15325 * There may be no VBT; and if the BIOS enabled SSC we can
15326 * just keep using it to avoid unnecessary flicker. Whereas if the
15327 * BIOS isn't using it, don't assume it will work even if the VBT
15328 * indicates as much.
15329 */
15330 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15331 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15332 DREF_SSC1_ENABLE);
15333
15334 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15335 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15336 bios_lvds_use_ssc ? "en" : "dis",
15337 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15338 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15339 }
15340 }
15341
15342 if (IS_GEN2(dev)) {
15343 dev->mode_config.max_width = 2048;
15344 dev->mode_config.max_height = 2048;
15345 } else if (IS_GEN3(dev)) {
15346 dev->mode_config.max_width = 4096;
15347 dev->mode_config.max_height = 4096;
15348 } else {
15349 dev->mode_config.max_width = 8192;
15350 dev->mode_config.max_height = 8192;
15351 }
15352
15353 if (IS_845G(dev) || IS_I865G(dev)) {
15354 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15355 dev->mode_config.cursor_height = 1023;
15356 } else if (IS_GEN2(dev)) {
15357 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15358 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15359 } else {
15360 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15361 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15362 }
15363
15364 dev->mode_config.fb_base = ggtt->mappable_base;
15365
15366 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15367 INTEL_INFO(dev)->num_pipes,
15368 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15369
15370 for_each_pipe(dev_priv, pipe) {
15371 intel_crtc_init(dev, pipe);
15372 for_each_sprite(dev_priv, pipe, sprite) {
15373 ret = intel_plane_init(dev, pipe, sprite);
15374 if (ret)
15375 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15376 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15377 }
15378 }
15379
15380 intel_update_czclk(dev_priv);
15381 intel_update_rawclk(dev_priv);
15382 intel_update_cdclk(dev);
15383
15384 intel_shared_dpll_init(dev);
15385
15386 /* Just disable it once at startup */
15387 i915_disable_vga(dev);
15388 intel_setup_outputs(dev);
15389
15390 drm_modeset_lock_all(dev);
15391 intel_modeset_setup_hw_state(dev);
15392 drm_modeset_unlock_all(dev);
15393
15394 for_each_intel_crtc(dev, crtc) {
15395 struct intel_initial_plane_config plane_config = {};
15396
15397 if (!crtc->active)
15398 continue;
15399
15400 /*
15401 * Note that reserving the BIOS fb up front prevents us
15402 * from stuffing other stolen allocations like the ring
15403 * on top. This prevents some ugliness at boot time, and
15404 * can even allow for smooth boot transitions if the BIOS
15405 * fb is large enough for the active pipe configuration.
15406 */
15407 dev_priv->display.get_initial_plane_config(crtc,
15408 &plane_config);
15409
15410 /*
15411 * If the fb is shared between multiple heads, we'll
15412 * just get the first one.
15413 */
15414 intel_find_initial_plane_obj(crtc, &plane_config);
15415 }
15416
15417 /*
15418 * Make sure hardware watermarks really match the state we read out.
15419 * Note that we need to do this after reconstructing the BIOS fb's
15420 * since the watermark calculation done here will use pstate->fb.
15421 */
15422 sanitize_watermarks(dev);
15423 }
15424
15425 static void intel_enable_pipe_a(struct drm_device *dev)
15426 {
15427 struct intel_connector *connector;
15428 struct drm_connector *crt = NULL;
15429 struct intel_load_detect_pipe load_detect_temp;
15430 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15431
15432 /* We can't just switch on the pipe A, we need to set things up with a
15433 * proper mode and output configuration. As a gross hack, enable pipe A
15434 * by enabling the load detect pipe once. */
15435 for_each_intel_connector(dev, connector) {
15436 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15437 crt = &connector->base;
15438 break;
15439 }
15440 }
15441
15442 if (!crt)
15443 return;
15444
15445 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15446 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15447 }
15448
15449 static bool
15450 intel_check_plane_mapping(struct intel_crtc *crtc)
15451 {
15452 struct drm_device *dev = crtc->base.dev;
15453 struct drm_i915_private *dev_priv = dev->dev_private;
15454 u32 val;
15455
15456 if (INTEL_INFO(dev)->num_pipes == 1)
15457 return true;
15458
15459 val = I915_READ(DSPCNTR(!crtc->plane));
15460
15461 if ((val & DISPLAY_PLANE_ENABLE) &&
15462 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15463 return false;
15464
15465 return true;
15466 }
15467
15468 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15469 {
15470 struct drm_device *dev = crtc->base.dev;
15471 struct intel_encoder *encoder;
15472
15473 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15474 return true;
15475
15476 return false;
15477 }
15478
15479 static bool intel_encoder_has_connectors(struct intel_encoder *encoder)
15480 {
15481 struct drm_device *dev = encoder->base.dev;
15482 struct intel_connector *connector;
15483
15484 for_each_connector_on_encoder(dev, &encoder->base, connector)
15485 return true;
15486
15487 return false;
15488 }
15489
15490 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15491 {
15492 struct drm_device *dev = crtc->base.dev;
15493 struct drm_i915_private *dev_priv = dev->dev_private;
15494 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
15495
15496 /* Clear any frame start delays used for debugging left by the BIOS */
15497 if (!transcoder_is_dsi(cpu_transcoder)) {
15498 i915_reg_t reg = PIPECONF(cpu_transcoder);
15499
15500 I915_WRITE(reg,
15501 I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15502 }
15503
15504 /* restore vblank interrupts to correct state */
15505 drm_crtc_vblank_reset(&crtc->base);
15506 if (crtc->active) {
15507 struct intel_plane *plane;
15508
15509 drm_crtc_vblank_on(&crtc->base);
15510
15511 /* Disable everything but the primary plane */
15512 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15513 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15514 continue;
15515
15516 plane->disable_plane(&plane->base, &crtc->base);
15517 }
15518 }
15519
15520 /* We need to sanitize the plane -> pipe mapping first because this will
15521 * disable the crtc (and hence change the state) if it is wrong. Note
15522 * that gen4+ has a fixed plane -> pipe mapping. */
15523 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15524 bool plane;
15525
15526 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15527 crtc->base.base.id);
15528
15529 /* Pipe has the wrong plane attached and the plane is active.
15530 * Temporarily change the plane mapping and disable everything
15531 * ... */
15532 plane = crtc->plane;
15533 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15534 crtc->plane = !plane;
15535 intel_crtc_disable_noatomic(&crtc->base);
15536 crtc->plane = plane;
15537 }
15538
15539 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15540 crtc->pipe == PIPE_A && !crtc->active) {
15541 /* BIOS forgot to enable pipe A, this mostly happens after
15542 * resume. Force-enable the pipe to fix this, the update_dpms
15543 * call below we restore the pipe to the right state, but leave
15544 * the required bits on. */
15545 intel_enable_pipe_a(dev);
15546 }
15547
15548 /* Adjust the state of the output pipe according to whether we
15549 * have active connectors/encoders. */
15550 if (crtc->active && !intel_crtc_has_encoders(crtc))
15551 intel_crtc_disable_noatomic(&crtc->base);
15552
15553 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15554 /*
15555 * We start out with underrun reporting disabled to avoid races.
15556 * For correct bookkeeping mark this on active crtcs.
15557 *
15558 * Also on gmch platforms we dont have any hardware bits to
15559 * disable the underrun reporting. Which means we need to start
15560 * out with underrun reporting disabled also on inactive pipes,
15561 * since otherwise we'll complain about the garbage we read when
15562 * e.g. coming up after runtime pm.
15563 *
15564 * No protection against concurrent access is required - at
15565 * worst a fifo underrun happens which also sets this to false.
15566 */
15567 crtc->cpu_fifo_underrun_disabled = true;
15568 crtc->pch_fifo_underrun_disabled = true;
15569 }
15570 }
15571
15572 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15573 {
15574 struct intel_connector *connector;
15575 struct drm_device *dev = encoder->base.dev;
15576
15577 /* We need to check both for a crtc link (meaning that the
15578 * encoder is active and trying to read from a pipe) and the
15579 * pipe itself being active. */
15580 bool has_active_crtc = encoder->base.crtc &&
15581 to_intel_crtc(encoder->base.crtc)->active;
15582
15583 if (intel_encoder_has_connectors(encoder) && !has_active_crtc) {
15584 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15585 encoder->base.base.id,
15586 encoder->base.name);
15587
15588 /* Connector is active, but has no active pipe. This is
15589 * fallout from our resume register restoring. Disable
15590 * the encoder manually again. */
15591 if (encoder->base.crtc) {
15592 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15593 encoder->base.base.id,
15594 encoder->base.name);
15595 encoder->disable(encoder);
15596 if (encoder->post_disable)
15597 encoder->post_disable(encoder);
15598 }
15599 encoder->base.crtc = NULL;
15600
15601 /* Inconsistent output/port/pipe state happens presumably due to
15602 * a bug in one of the get_hw_state functions. Or someplace else
15603 * in our code, like the register restore mess on resume. Clamp
15604 * things to off as a safer default. */
15605 for_each_intel_connector(dev, connector) {
15606 if (connector->encoder != encoder)
15607 continue;
15608 connector->base.dpms = DRM_MODE_DPMS_OFF;
15609 connector->base.encoder = NULL;
15610 }
15611 }
15612 /* Enabled encoders without active connectors will be fixed in
15613 * the crtc fixup. */
15614 }
15615
15616 void i915_redisable_vga_power_on(struct drm_device *dev)
15617 {
15618 struct drm_i915_private *dev_priv = dev->dev_private;
15619 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15620
15621 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15622 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15623 i915_disable_vga(dev);
15624 }
15625 }
15626
15627 void i915_redisable_vga(struct drm_device *dev)
15628 {
15629 struct drm_i915_private *dev_priv = dev->dev_private;
15630
15631 /* This function can be called both from intel_modeset_setup_hw_state or
15632 * at a very early point in our resume sequence, where the power well
15633 * structures are not yet restored. Since this function is at a very
15634 * paranoid "someone might have enabled VGA while we were not looking"
15635 * level, just check if the power well is enabled instead of trying to
15636 * follow the "don't touch the power well if we don't need it" policy
15637 * the rest of the driver uses. */
15638 if (!intel_display_power_get_if_enabled(dev_priv, POWER_DOMAIN_VGA))
15639 return;
15640
15641 i915_redisable_vga_power_on(dev);
15642
15643 intel_display_power_put(dev_priv, POWER_DOMAIN_VGA);
15644 }
15645
15646 static bool primary_get_hw_state(struct intel_plane *plane)
15647 {
15648 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15649
15650 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15651 }
15652
15653 /* FIXME read out full plane state for all planes */
15654 static void readout_plane_state(struct intel_crtc *crtc)
15655 {
15656 struct drm_plane *primary = crtc->base.primary;
15657 struct intel_plane_state *plane_state =
15658 to_intel_plane_state(primary->state);
15659
15660 plane_state->visible = crtc->active &&
15661 primary_get_hw_state(to_intel_plane(primary));
15662
15663 if (plane_state->visible)
15664 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15665 }
15666
15667 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15668 {
15669 struct drm_i915_private *dev_priv = dev->dev_private;
15670 enum pipe pipe;
15671 struct intel_crtc *crtc;
15672 struct intel_encoder *encoder;
15673 struct intel_connector *connector;
15674 int i;
15675
15676 dev_priv->active_crtcs = 0;
15677
15678 for_each_intel_crtc(dev, crtc) {
15679 struct intel_crtc_state *crtc_state = crtc->config;
15680 int pixclk = 0;
15681
15682 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15683 memset(crtc_state, 0, sizeof(*crtc_state));
15684 crtc_state->base.crtc = &crtc->base;
15685
15686 crtc_state->base.active = crtc_state->base.enable =
15687 dev_priv->display.get_pipe_config(crtc, crtc_state);
15688
15689 crtc->base.enabled = crtc_state->base.enable;
15690 crtc->active = crtc_state->base.active;
15691
15692 if (crtc_state->base.active) {
15693 dev_priv->active_crtcs |= 1 << crtc->pipe;
15694
15695 if (IS_BROADWELL(dev_priv)) {
15696 pixclk = ilk_pipe_pixel_rate(crtc_state);
15697
15698 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15699 if (crtc_state->ips_enabled)
15700 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15701 } else if (IS_VALLEYVIEW(dev_priv) ||
15702 IS_CHERRYVIEW(dev_priv) ||
15703 IS_BROXTON(dev_priv))
15704 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15705 else
15706 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15707 }
15708
15709 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15710
15711 readout_plane_state(crtc);
15712
15713 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15714 crtc->base.base.id,
15715 crtc->active ? "enabled" : "disabled");
15716 }
15717
15718 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15719 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15720
15721 pll->on = pll->funcs.get_hw_state(dev_priv, pll,
15722 &pll->config.hw_state);
15723 pll->config.crtc_mask = 0;
15724 for_each_intel_crtc(dev, crtc) {
15725 if (crtc->active && crtc->config->shared_dpll == pll)
15726 pll->config.crtc_mask |= 1 << crtc->pipe;
15727 }
15728 pll->active_mask = pll->config.crtc_mask;
15729
15730 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15731 pll->name, pll->config.crtc_mask, pll->on);
15732 }
15733
15734 for_each_intel_encoder(dev, encoder) {
15735 pipe = 0;
15736
15737 if (encoder->get_hw_state(encoder, &pipe)) {
15738 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15739 encoder->base.crtc = &crtc->base;
15740 encoder->get_config(encoder, crtc->config);
15741 } else {
15742 encoder->base.crtc = NULL;
15743 }
15744
15745 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15746 encoder->base.base.id,
15747 encoder->base.name,
15748 encoder->base.crtc ? "enabled" : "disabled",
15749 pipe_name(pipe));
15750 }
15751
15752 for_each_intel_connector(dev, connector) {
15753 if (connector->get_hw_state(connector)) {
15754 connector->base.dpms = DRM_MODE_DPMS_ON;
15755
15756 encoder = connector->encoder;
15757 connector->base.encoder = &encoder->base;
15758
15759 if (encoder->base.crtc &&
15760 encoder->base.crtc->state->active) {
15761 /*
15762 * This has to be done during hardware readout
15763 * because anything calling .crtc_disable may
15764 * rely on the connector_mask being accurate.
15765 */
15766 encoder->base.crtc->state->connector_mask |=
15767 1 << drm_connector_index(&connector->base);
15768 encoder->base.crtc->state->encoder_mask |=
15769 1 << drm_encoder_index(&encoder->base);
15770 }
15771
15772 } else {
15773 connector->base.dpms = DRM_MODE_DPMS_OFF;
15774 connector->base.encoder = NULL;
15775 }
15776 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15777 connector->base.base.id,
15778 connector->base.name,
15779 connector->base.encoder ? "enabled" : "disabled");
15780 }
15781
15782 for_each_intel_crtc(dev, crtc) {
15783 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15784
15785 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15786 if (crtc->base.state->active) {
15787 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15788 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15789 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15790
15791 /*
15792 * The initial mode needs to be set in order to keep
15793 * the atomic core happy. It wants a valid mode if the
15794 * crtc's enabled, so we do the above call.
15795 *
15796 * At this point some state updated by the connectors
15797 * in their ->detect() callback has not run yet, so
15798 * no recalculation can be done yet.
15799 *
15800 * Even if we could do a recalculation and modeset
15801 * right now it would cause a double modeset if
15802 * fbdev or userspace chooses a different initial mode.
15803 *
15804 * If that happens, someone indicated they wanted a
15805 * mode change, which means it's safe to do a full
15806 * recalculation.
15807 */
15808 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15809
15810 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15811 update_scanline_offset(crtc);
15812 }
15813
15814 intel_pipe_config_sanity_check(dev_priv, crtc->config);
15815 }
15816 }
15817
15818 /* Scan out the current hw modeset state,
15819 * and sanitizes it to the current state
15820 */
15821 static void
15822 intel_modeset_setup_hw_state(struct drm_device *dev)
15823 {
15824 struct drm_i915_private *dev_priv = dev->dev_private;
15825 enum pipe pipe;
15826 struct intel_crtc *crtc;
15827 struct intel_encoder *encoder;
15828 int i;
15829
15830 intel_modeset_readout_hw_state(dev);
15831
15832 /* HW state is read out, now we need to sanitize this mess. */
15833 for_each_intel_encoder(dev, encoder) {
15834 intel_sanitize_encoder(encoder);
15835 }
15836
15837 for_each_pipe(dev_priv, pipe) {
15838 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15839 intel_sanitize_crtc(crtc);
15840 intel_dump_pipe_config(crtc, crtc->config,
15841 "[setup_hw_state]");
15842 }
15843
15844 intel_modeset_update_connector_atomic_state(dev);
15845
15846 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15847 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15848
15849 if (!pll->on || pll->active_mask)
15850 continue;
15851
15852 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15853
15854 pll->funcs.disable(dev_priv, pll);
15855 pll->on = false;
15856 }
15857
15858 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15859 vlv_wm_get_hw_state(dev);
15860 else if (IS_GEN9(dev))
15861 skl_wm_get_hw_state(dev);
15862 else if (HAS_PCH_SPLIT(dev))
15863 ilk_wm_get_hw_state(dev);
15864
15865 for_each_intel_crtc(dev, crtc) {
15866 unsigned long put_domains;
15867
15868 put_domains = modeset_get_crtc_power_domains(&crtc->base, crtc->config);
15869 if (WARN_ON(put_domains))
15870 modeset_put_power_domains(dev_priv, put_domains);
15871 }
15872 intel_display_set_init_power(dev_priv, false);
15873
15874 intel_fbc_init_pipe_state(dev_priv);
15875 }
15876
15877 void intel_display_resume(struct drm_device *dev)
15878 {
15879 struct drm_i915_private *dev_priv = to_i915(dev);
15880 struct drm_atomic_state *state = dev_priv->modeset_restore_state;
15881 struct drm_modeset_acquire_ctx ctx;
15882 int ret;
15883 bool setup = false;
15884
15885 dev_priv->modeset_restore_state = NULL;
15886
15887 /*
15888 * This is a cludge because with real atomic modeset mode_config.mutex
15889 * won't be taken. Unfortunately some probed state like
15890 * audio_codec_enable is still protected by mode_config.mutex, so lock
15891 * it here for now.
15892 */
15893 mutex_lock(&dev->mode_config.mutex);
15894 drm_modeset_acquire_init(&ctx, 0);
15895
15896 retry:
15897 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15898
15899 if (ret == 0 && !setup) {
15900 setup = true;
15901
15902 intel_modeset_setup_hw_state(dev);
15903 i915_redisable_vga(dev);
15904 }
15905
15906 if (ret == 0 && state) {
15907 struct drm_crtc_state *crtc_state;
15908 struct drm_crtc *crtc;
15909 int i;
15910
15911 state->acquire_ctx = &ctx;
15912
15913 for_each_crtc_in_state(state, crtc, crtc_state, i) {
15914 /*
15915 * Force recalculation even if we restore
15916 * current state. With fast modeset this may not result
15917 * in a modeset when the state is compatible.
15918 */
15919 crtc_state->mode_changed = true;
15920 }
15921
15922 ret = drm_atomic_commit(state);
15923 }
15924
15925 if (ret == -EDEADLK) {
15926 drm_modeset_backoff(&ctx);
15927 goto retry;
15928 }
15929
15930 drm_modeset_drop_locks(&ctx);
15931 drm_modeset_acquire_fini(&ctx);
15932 mutex_unlock(&dev->mode_config.mutex);
15933
15934 if (ret) {
15935 DRM_ERROR("Restoring old state failed with %i\n", ret);
15936 drm_atomic_state_free(state);
15937 }
15938 }
15939
15940 void intel_modeset_gem_init(struct drm_device *dev)
15941 {
15942 struct drm_crtc *c;
15943 struct drm_i915_gem_object *obj;
15944 int ret;
15945
15946 intel_init_gt_powersave(dev);
15947
15948 intel_modeset_init_hw(dev);
15949
15950 intel_setup_overlay(dev);
15951
15952 /*
15953 * Make sure any fbs we allocated at startup are properly
15954 * pinned & fenced. When we do the allocation it's too early
15955 * for this.
15956 */
15957 for_each_crtc(dev, c) {
15958 obj = intel_fb_obj(c->primary->fb);
15959 if (obj == NULL)
15960 continue;
15961
15962 mutex_lock(&dev->struct_mutex);
15963 ret = intel_pin_and_fence_fb_obj(c->primary->fb,
15964 c->primary->state->rotation);
15965 mutex_unlock(&dev->struct_mutex);
15966 if (ret) {
15967 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15968 to_intel_crtc(c)->pipe);
15969 drm_framebuffer_unreference(c->primary->fb);
15970 c->primary->fb = NULL;
15971 c->primary->crtc = c->primary->state->crtc = NULL;
15972 update_state_fb(c->primary);
15973 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15974 }
15975 }
15976
15977 intel_backlight_register(dev);
15978 }
15979
15980 void intel_connector_unregister(struct intel_connector *intel_connector)
15981 {
15982 struct drm_connector *connector = &intel_connector->base;
15983
15984 intel_panel_destroy_backlight(connector);
15985 drm_connector_unregister(connector);
15986 }
15987
15988 void intel_modeset_cleanup(struct drm_device *dev)
15989 {
15990 struct drm_i915_private *dev_priv = dev->dev_private;
15991 struct intel_connector *connector;
15992
15993 intel_disable_gt_powersave(dev);
15994
15995 intel_backlight_unregister(dev);
15996
15997 /*
15998 * Interrupts and polling as the first thing to avoid creating havoc.
15999 * Too much stuff here (turning of connectors, ...) would
16000 * experience fancy races otherwise.
16001 */
16002 intel_irq_uninstall(dev_priv);
16003
16004 /*
16005 * Due to the hpd irq storm handling the hotplug work can re-arm the
16006 * poll handlers. Hence disable polling after hpd handling is shut down.
16007 */
16008 drm_kms_helper_poll_fini(dev);
16009
16010 intel_unregister_dsm_handler();
16011
16012 intel_fbc_global_disable(dev_priv);
16013
16014 /* flush any delayed tasks or pending work */
16015 flush_scheduled_work();
16016
16017 /* destroy the backlight and sysfs files before encoders/connectors */
16018 for_each_intel_connector(dev, connector)
16019 connector->unregister(connector);
16020
16021 drm_mode_config_cleanup(dev);
16022
16023 intel_cleanup_overlay(dev);
16024
16025 intel_cleanup_gt_powersave(dev);
16026
16027 intel_teardown_gmbus(dev);
16028 }
16029
16030 /*
16031 * Return which encoder is currently attached for connector.
16032 */
16033 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16034 {
16035 return &intel_attached_encoder(connector)->base;
16036 }
16037
16038 void intel_connector_attach_encoder(struct intel_connector *connector,
16039 struct intel_encoder *encoder)
16040 {
16041 connector->encoder = encoder;
16042 drm_mode_connector_attach_encoder(&connector->base,
16043 &encoder->base);
16044 }
16045
16046 /*
16047 * set vga decode state - true == enable VGA decode
16048 */
16049 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16050 {
16051 struct drm_i915_private *dev_priv = dev->dev_private;
16052 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16053 u16 gmch_ctrl;
16054
16055 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16056 DRM_ERROR("failed to read control word\n");
16057 return -EIO;
16058 }
16059
16060 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16061 return 0;
16062
16063 if (state)
16064 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16065 else
16066 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16067
16068 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16069 DRM_ERROR("failed to write control word\n");
16070 return -EIO;
16071 }
16072
16073 return 0;
16074 }
16075
16076 struct intel_display_error_state {
16077
16078 u32 power_well_driver;
16079
16080 int num_transcoders;
16081
16082 struct intel_cursor_error_state {
16083 u32 control;
16084 u32 position;
16085 u32 base;
16086 u32 size;
16087 } cursor[I915_MAX_PIPES];
16088
16089 struct intel_pipe_error_state {
16090 bool power_domain_on;
16091 u32 source;
16092 u32 stat;
16093 } pipe[I915_MAX_PIPES];
16094
16095 struct intel_plane_error_state {
16096 u32 control;
16097 u32 stride;
16098 u32 size;
16099 u32 pos;
16100 u32 addr;
16101 u32 surface;
16102 u32 tile_offset;
16103 } plane[I915_MAX_PIPES];
16104
16105 struct intel_transcoder_error_state {
16106 bool power_domain_on;
16107 enum transcoder cpu_transcoder;
16108
16109 u32 conf;
16110
16111 u32 htotal;
16112 u32 hblank;
16113 u32 hsync;
16114 u32 vtotal;
16115 u32 vblank;
16116 u32 vsync;
16117 } transcoder[4];
16118 };
16119
16120 struct intel_display_error_state *
16121 intel_display_capture_error_state(struct drm_device *dev)
16122 {
16123 struct drm_i915_private *dev_priv = dev->dev_private;
16124 struct intel_display_error_state *error;
16125 int transcoders[] = {
16126 TRANSCODER_A,
16127 TRANSCODER_B,
16128 TRANSCODER_C,
16129 TRANSCODER_EDP,
16130 };
16131 int i;
16132
16133 if (INTEL_INFO(dev)->num_pipes == 0)
16134 return NULL;
16135
16136 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16137 if (error == NULL)
16138 return NULL;
16139
16140 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16141 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16142
16143 for_each_pipe(dev_priv, i) {
16144 error->pipe[i].power_domain_on =
16145 __intel_display_power_is_enabled(dev_priv,
16146 POWER_DOMAIN_PIPE(i));
16147 if (!error->pipe[i].power_domain_on)
16148 continue;
16149
16150 error->cursor[i].control = I915_READ(CURCNTR(i));
16151 error->cursor[i].position = I915_READ(CURPOS(i));
16152 error->cursor[i].base = I915_READ(CURBASE(i));
16153
16154 error->plane[i].control = I915_READ(DSPCNTR(i));
16155 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16156 if (INTEL_INFO(dev)->gen <= 3) {
16157 error->plane[i].size = I915_READ(DSPSIZE(i));
16158 error->plane[i].pos = I915_READ(DSPPOS(i));
16159 }
16160 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16161 error->plane[i].addr = I915_READ(DSPADDR(i));
16162 if (INTEL_INFO(dev)->gen >= 4) {
16163 error->plane[i].surface = I915_READ(DSPSURF(i));
16164 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16165 }
16166
16167 error->pipe[i].source = I915_READ(PIPESRC(i));
16168
16169 if (HAS_GMCH_DISPLAY(dev))
16170 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16171 }
16172
16173 /* Note: this does not include DSI transcoders. */
16174 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16175 if (HAS_DDI(dev_priv->dev))
16176 error->num_transcoders++; /* Account for eDP. */
16177
16178 for (i = 0; i < error->num_transcoders; i++) {
16179 enum transcoder cpu_transcoder = transcoders[i];
16180
16181 error->transcoder[i].power_domain_on =
16182 __intel_display_power_is_enabled(dev_priv,
16183 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16184 if (!error->transcoder[i].power_domain_on)
16185 continue;
16186
16187 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16188
16189 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16190 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16191 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16192 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16193 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16194 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16195 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16196 }
16197
16198 return error;
16199 }
16200
16201 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16202
16203 void
16204 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16205 struct drm_device *dev,
16206 struct intel_display_error_state *error)
16207 {
16208 struct drm_i915_private *dev_priv = dev->dev_private;
16209 int i;
16210
16211 if (!error)
16212 return;
16213
16214 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16215 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16216 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16217 error->power_well_driver);
16218 for_each_pipe(dev_priv, i) {
16219 err_printf(m, "Pipe [%d]:\n", i);
16220 err_printf(m, " Power: %s\n",
16221 onoff(error->pipe[i].power_domain_on));
16222 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16223 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16224
16225 err_printf(m, "Plane [%d]:\n", i);
16226 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16227 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16228 if (INTEL_INFO(dev)->gen <= 3) {
16229 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16230 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16231 }
16232 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16233 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16234 if (INTEL_INFO(dev)->gen >= 4) {
16235 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16236 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16237 }
16238
16239 err_printf(m, "Cursor [%d]:\n", i);
16240 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16241 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16242 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16243 }
16244
16245 for (i = 0; i < error->num_transcoders; i++) {
16246 err_printf(m, "CPU transcoder: %s\n",
16247 transcoder_name(error->transcoder[i].cpu_transcoder));
16248 err_printf(m, " Power: %s\n",
16249 onoff(error->transcoder[i].power_domain_on));
16250 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16251 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16252 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16253 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16254 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16255 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16256 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16257 }
16258 }
Linux kernel - Deliverables
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