2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/i2c.h>
28 #include <linux/kernel.h>
30 #include "intel_drv.h"
35 #include "drm_crtc_helper.h"
37 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
39 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
40 static void intel_update_watermarks(struct drm_device
*dev
);
41 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
);
64 #define INTEL_P2_NUM 2
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
69 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
70 int, int, intel_clock_t
*);
71 bool (* find_reduced_pll
)(const intel_limit_t
*, struct drm_crtc
*,
72 int, int, intel_clock_t
*);
75 #define I8XX_DOT_MIN 25000
76 #define I8XX_DOT_MAX 350000
77 #define I8XX_VCO_MIN 930000
78 #define I8XX_VCO_MAX 1400000
82 #define I8XX_M_MAX 140
83 #define I8XX_M1_MIN 18
84 #define I8XX_M1_MAX 26
86 #define I8XX_M2_MAX 16
88 #define I8XX_P_MAX 128
90 #define I8XX_P1_MAX 33
91 #define I8XX_P1_LVDS_MIN 1
92 #define I8XX_P1_LVDS_MAX 6
93 #define I8XX_P2_SLOW 4
94 #define I8XX_P2_FAST 2
95 #define I8XX_P2_LVDS_SLOW 14
96 #define I8XX_P2_LVDS_FAST 7
97 #define I8XX_P2_SLOW_LIMIT 165000
99 #define I9XX_DOT_MIN 20000
100 #define I9XX_DOT_MAX 400000
101 #define I9XX_VCO_MIN 1400000
102 #define I9XX_VCO_MAX 2800000
103 #define IGD_VCO_MIN 1700000
104 #define IGD_VCO_MAX 3500000
107 /* IGD's Ncounter is a ring counter */
110 #define I9XX_M_MIN 70
111 #define I9XX_M_MAX 120
113 #define IGD_M_MAX 256
114 #define I9XX_M1_MIN 10
115 #define I9XX_M1_MAX 22
116 #define I9XX_M2_MIN 5
117 #define I9XX_M2_MAX 9
118 /* IGD M1 is reserved, and must be 0 */
122 #define IGD_M2_MAX 254
123 #define I9XX_P_SDVO_DAC_MIN 5
124 #define I9XX_P_SDVO_DAC_MAX 80
125 #define I9XX_P_LVDS_MIN 7
126 #define I9XX_P_LVDS_MAX 98
127 #define IGD_P_LVDS_MIN 7
128 #define IGD_P_LVDS_MAX 112
129 #define I9XX_P1_MIN 1
130 #define I9XX_P1_MAX 8
131 #define I9XX_P2_SDVO_DAC_SLOW 10
132 #define I9XX_P2_SDVO_DAC_FAST 5
133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
134 #define I9XX_P2_LVDS_SLOW 14
135 #define I9XX_P2_LVDS_FAST 7
136 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
138 /*The parameter is for SDVO on G4x platform*/
139 #define G4X_DOT_SDVO_MIN 25000
140 #define G4X_DOT_SDVO_MAX 270000
141 #define G4X_VCO_MIN 1750000
142 #define G4X_VCO_MAX 3500000
143 #define G4X_N_SDVO_MIN 1
144 #define G4X_N_SDVO_MAX 4
145 #define G4X_M_SDVO_MIN 104
146 #define G4X_M_SDVO_MAX 138
147 #define G4X_M1_SDVO_MIN 17
148 #define G4X_M1_SDVO_MAX 23
149 #define G4X_M2_SDVO_MIN 5
150 #define G4X_M2_SDVO_MAX 11
151 #define G4X_P_SDVO_MIN 10
152 #define G4X_P_SDVO_MAX 30
153 #define G4X_P1_SDVO_MIN 1
154 #define G4X_P1_SDVO_MAX 3
155 #define G4X_P2_SDVO_SLOW 10
156 #define G4X_P2_SDVO_FAST 10
157 #define G4X_P2_SDVO_LIMIT 270000
159 /*The parameter is for HDMI_DAC on G4x platform*/
160 #define G4X_DOT_HDMI_DAC_MIN 22000
161 #define G4X_DOT_HDMI_DAC_MAX 400000
162 #define G4X_N_HDMI_DAC_MIN 1
163 #define G4X_N_HDMI_DAC_MAX 4
164 #define G4X_M_HDMI_DAC_MIN 104
165 #define G4X_M_HDMI_DAC_MAX 138
166 #define G4X_M1_HDMI_DAC_MIN 16
167 #define G4X_M1_HDMI_DAC_MAX 23
168 #define G4X_M2_HDMI_DAC_MIN 5
169 #define G4X_M2_HDMI_DAC_MAX 11
170 #define G4X_P_HDMI_DAC_MIN 5
171 #define G4X_P_HDMI_DAC_MAX 80
172 #define G4X_P1_HDMI_DAC_MIN 1
173 #define G4X_P1_HDMI_DAC_MAX 8
174 #define G4X_P2_HDMI_DAC_SLOW 10
175 #define G4X_P2_HDMI_DAC_FAST 5
176 #define G4X_P2_HDMI_DAC_LIMIT 165000
178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
216 /*The parameter is for DISPLAY PORT on G4x platform*/
217 #define G4X_DOT_DISPLAY_PORT_MIN 161670
218 #define G4X_DOT_DISPLAY_PORT_MAX 227000
219 #define G4X_N_DISPLAY_PORT_MIN 1
220 #define G4X_N_DISPLAY_PORT_MAX 2
221 #define G4X_M_DISPLAY_PORT_MIN 97
222 #define G4X_M_DISPLAY_PORT_MAX 108
223 #define G4X_M1_DISPLAY_PORT_MIN 0x10
224 #define G4X_M1_DISPLAY_PORT_MAX 0x12
225 #define G4X_M2_DISPLAY_PORT_MIN 0x05
226 #define G4X_M2_DISPLAY_PORT_MAX 0x06
227 #define G4X_P_DISPLAY_PORT_MIN 10
228 #define G4X_P_DISPLAY_PORT_MAX 20
229 #define G4X_P1_DISPLAY_PORT_MIN 1
230 #define G4X_P1_DISPLAY_PORT_MAX 2
231 #define G4X_P2_DISPLAY_PORT_SLOW 10
232 #define G4X_P2_DISPLAY_PORT_FAST 10
233 #define G4X_P2_DISPLAY_PORT_LIMIT 0
236 /* as we calculate clock using (register_value + 2) for
237 N/M1/M2, so here the range value for them is (actual_value-2).
239 #define IGDNG_DOT_MIN 25000
240 #define IGDNG_DOT_MAX 350000
241 #define IGDNG_VCO_MIN 1760000
242 #define IGDNG_VCO_MAX 3510000
243 #define IGDNG_N_MIN 1
244 #define IGDNG_N_MAX 5
245 #define IGDNG_M_MIN 79
246 #define IGDNG_M_MAX 118
247 #define IGDNG_M1_MIN 12
248 #define IGDNG_M1_MAX 23
249 #define IGDNG_M2_MIN 5
250 #define IGDNG_M2_MAX 9
251 #define IGDNG_P_SDVO_DAC_MIN 5
252 #define IGDNG_P_SDVO_DAC_MAX 80
253 #define IGDNG_P_LVDS_MIN 28
254 #define IGDNG_P_LVDS_MAX 112
255 #define IGDNG_P1_MIN 1
256 #define IGDNG_P1_MAX 8
257 #define IGDNG_P2_SDVO_DAC_SLOW 10
258 #define IGDNG_P2_SDVO_DAC_FAST 5
259 #define IGDNG_P2_LVDS_SLOW 14 /* single channel */
260 #define IGDNG_P2_LVDS_FAST 7 /* double channel */
261 #define IGDNG_P2_DOT_LIMIT 225000 /* 225Mhz */
264 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
265 int target
, int refclk
, intel_clock_t
*best_clock
);
267 intel_find_best_reduced_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
268 int target
, int refclk
, intel_clock_t
*best_clock
);
270 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
271 int target
, int refclk
, intel_clock_t
*best_clock
);
273 intel_igdng_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
274 int target
, int refclk
, intel_clock_t
*best_clock
);
277 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
278 int target
, int refclk
, intel_clock_t
*best_clock
);
280 intel_find_pll_igdng_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
281 int target
, int refclk
, intel_clock_t
*best_clock
);
283 static const intel_limit_t intel_limits_i8xx_dvo
= {
284 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
285 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
286 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
287 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
288 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
289 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
290 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
291 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
292 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
293 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
294 .find_pll
= intel_find_best_PLL
,
295 .find_reduced_pll
= intel_find_best_reduced_PLL
,
298 static const intel_limit_t intel_limits_i8xx_lvds
= {
299 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
300 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
301 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
302 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
303 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
304 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
305 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
306 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
307 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
308 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
309 .find_pll
= intel_find_best_PLL
,
310 .find_reduced_pll
= intel_find_best_reduced_PLL
,
313 static const intel_limit_t intel_limits_i9xx_sdvo
= {
314 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
315 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
316 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
317 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
318 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
319 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
320 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
321 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
322 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
323 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
324 .find_pll
= intel_find_best_PLL
,
325 .find_reduced_pll
= intel_find_best_reduced_PLL
,
328 static const intel_limit_t intel_limits_i9xx_lvds
= {
329 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
330 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
331 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
332 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
333 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
334 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
335 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
336 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
337 /* The single-channel range is 25-112Mhz, and dual-channel
338 * is 80-224Mhz. Prefer single channel as much as possible.
340 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
341 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
342 .find_pll
= intel_find_best_PLL
,
343 .find_reduced_pll
= intel_find_best_reduced_PLL
,
346 /* below parameter and function is for G4X Chipset Family*/
347 static const intel_limit_t intel_limits_g4x_sdvo
= {
348 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
349 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
350 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
351 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
352 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
353 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
354 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
355 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
356 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
357 .p2_slow
= G4X_P2_SDVO_SLOW
,
358 .p2_fast
= G4X_P2_SDVO_FAST
360 .find_pll
= intel_g4x_find_best_PLL
,
361 .find_reduced_pll
= intel_g4x_find_best_PLL
,
364 static const intel_limit_t intel_limits_g4x_hdmi
= {
365 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
366 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
367 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
368 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
369 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
370 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
371 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
372 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
373 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
374 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
375 .p2_fast
= G4X_P2_HDMI_DAC_FAST
377 .find_pll
= intel_g4x_find_best_PLL
,
378 .find_reduced_pll
= intel_g4x_find_best_PLL
,
381 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
382 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
383 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
384 .vco
= { .min
= G4X_VCO_MIN
,
385 .max
= G4X_VCO_MAX
},
386 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
387 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
388 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
389 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
390 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
391 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
392 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
393 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
394 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
395 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
396 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
397 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
398 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
399 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
400 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
402 .find_pll
= intel_g4x_find_best_PLL
,
403 .find_reduced_pll
= intel_g4x_find_best_PLL
,
406 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
407 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
408 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
409 .vco
= { .min
= G4X_VCO_MIN
,
410 .max
= G4X_VCO_MAX
},
411 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
412 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
413 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
414 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
415 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
416 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
417 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
418 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
419 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
420 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
421 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
422 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
423 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
424 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
425 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
427 .find_pll
= intel_g4x_find_best_PLL
,
428 .find_reduced_pll
= intel_g4x_find_best_PLL
,
431 static const intel_limit_t intel_limits_g4x_display_port
= {
432 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
433 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
434 .vco
= { .min
= G4X_VCO_MIN
,
436 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
437 .max
= G4X_N_DISPLAY_PORT_MAX
},
438 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
439 .max
= G4X_M_DISPLAY_PORT_MAX
},
440 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
441 .max
= G4X_M1_DISPLAY_PORT_MAX
},
442 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
443 .max
= G4X_M2_DISPLAY_PORT_MAX
},
444 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
445 .max
= G4X_P_DISPLAY_PORT_MAX
},
446 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
447 .max
= G4X_P1_DISPLAY_PORT_MAX
},
448 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
449 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
450 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
451 .find_pll
= intel_find_pll_g4x_dp
,
454 static const intel_limit_t intel_limits_igd_sdvo
= {
455 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
456 .vco
= { .min
= IGD_VCO_MIN
, .max
= IGD_VCO_MAX
},
457 .n
= { .min
= IGD_N_MIN
, .max
= IGD_N_MAX
},
458 .m
= { .min
= IGD_M_MIN
, .max
= IGD_M_MAX
},
459 .m1
= { .min
= IGD_M1_MIN
, .max
= IGD_M1_MAX
},
460 .m2
= { .min
= IGD_M2_MIN
, .max
= IGD_M2_MAX
},
461 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
462 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
463 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
464 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
465 .find_pll
= intel_find_best_PLL
,
466 .find_reduced_pll
= intel_find_best_reduced_PLL
,
469 static const intel_limit_t intel_limits_igd_lvds
= {
470 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
471 .vco
= { .min
= IGD_VCO_MIN
, .max
= IGD_VCO_MAX
},
472 .n
= { .min
= IGD_N_MIN
, .max
= IGD_N_MAX
},
473 .m
= { .min
= IGD_M_MIN
, .max
= IGD_M_MAX
},
474 .m1
= { .min
= IGD_M1_MIN
, .max
= IGD_M1_MAX
},
475 .m2
= { .min
= IGD_M2_MIN
, .max
= IGD_M2_MAX
},
476 .p
= { .min
= IGD_P_LVDS_MIN
, .max
= IGD_P_LVDS_MAX
},
477 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
478 /* IGD only supports single-channel mode. */
479 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
480 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
481 .find_pll
= intel_find_best_PLL
,
482 .find_reduced_pll
= intel_find_best_reduced_PLL
,
485 static const intel_limit_t intel_limits_igdng_sdvo
= {
486 .dot
= { .min
= IGDNG_DOT_MIN
, .max
= IGDNG_DOT_MAX
},
487 .vco
= { .min
= IGDNG_VCO_MIN
, .max
= IGDNG_VCO_MAX
},
488 .n
= { .min
= IGDNG_N_MIN
, .max
= IGDNG_N_MAX
},
489 .m
= { .min
= IGDNG_M_MIN
, .max
= IGDNG_M_MAX
},
490 .m1
= { .min
= IGDNG_M1_MIN
, .max
= IGDNG_M1_MAX
},
491 .m2
= { .min
= IGDNG_M2_MIN
, .max
= IGDNG_M2_MAX
},
492 .p
= { .min
= IGDNG_P_SDVO_DAC_MIN
, .max
= IGDNG_P_SDVO_DAC_MAX
},
493 .p1
= { .min
= IGDNG_P1_MIN
, .max
= IGDNG_P1_MAX
},
494 .p2
= { .dot_limit
= IGDNG_P2_DOT_LIMIT
,
495 .p2_slow
= IGDNG_P2_SDVO_DAC_SLOW
,
496 .p2_fast
= IGDNG_P2_SDVO_DAC_FAST
},
497 .find_pll
= intel_igdng_find_best_PLL
,
500 static const intel_limit_t intel_limits_igdng_lvds
= {
501 .dot
= { .min
= IGDNG_DOT_MIN
, .max
= IGDNG_DOT_MAX
},
502 .vco
= { .min
= IGDNG_VCO_MIN
, .max
= IGDNG_VCO_MAX
},
503 .n
= { .min
= IGDNG_N_MIN
, .max
= IGDNG_N_MAX
},
504 .m
= { .min
= IGDNG_M_MIN
, .max
= IGDNG_M_MAX
},
505 .m1
= { .min
= IGDNG_M1_MIN
, .max
= IGDNG_M1_MAX
},
506 .m2
= { .min
= IGDNG_M2_MIN
, .max
= IGDNG_M2_MAX
},
507 .p
= { .min
= IGDNG_P_LVDS_MIN
, .max
= IGDNG_P_LVDS_MAX
},
508 .p1
= { .min
= IGDNG_P1_MIN
, .max
= IGDNG_P1_MAX
},
509 .p2
= { .dot_limit
= IGDNG_P2_DOT_LIMIT
,
510 .p2_slow
= IGDNG_P2_LVDS_SLOW
,
511 .p2_fast
= IGDNG_P2_LVDS_FAST
},
512 .find_pll
= intel_igdng_find_best_PLL
,
515 static const intel_limit_t
*intel_igdng_limit(struct drm_crtc
*crtc
)
517 const intel_limit_t
*limit
;
518 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
519 limit
= &intel_limits_igdng_lvds
;
521 limit
= &intel_limits_igdng_sdvo
;
526 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
528 struct drm_device
*dev
= crtc
->dev
;
529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
530 const intel_limit_t
*limit
;
532 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
533 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
535 /* LVDS with dual channel */
536 limit
= &intel_limits_g4x_dual_channel_lvds
;
538 /* LVDS with dual channel */
539 limit
= &intel_limits_g4x_single_channel_lvds
;
540 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
541 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
542 limit
= &intel_limits_g4x_hdmi
;
543 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
544 limit
= &intel_limits_g4x_sdvo
;
545 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
546 limit
= &intel_limits_g4x_display_port
;
547 } else /* The option is for other outputs */
548 limit
= &intel_limits_i9xx_sdvo
;
553 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
555 struct drm_device
*dev
= crtc
->dev
;
556 const intel_limit_t
*limit
;
559 limit
= intel_igdng_limit(crtc
);
560 else if (IS_G4X(dev
)) {
561 limit
= intel_g4x_limit(crtc
);
562 } else if (IS_I9XX(dev
) && !IS_IGD(dev
)) {
563 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
564 limit
= &intel_limits_i9xx_lvds
;
566 limit
= &intel_limits_i9xx_sdvo
;
567 } else if (IS_IGD(dev
)) {
568 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
569 limit
= &intel_limits_igd_lvds
;
571 limit
= &intel_limits_igd_sdvo
;
573 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
574 limit
= &intel_limits_i8xx_lvds
;
576 limit
= &intel_limits_i8xx_dvo
;
581 /* m1 is reserved as 0 in IGD, n is a ring counter */
582 static void igd_clock(int refclk
, intel_clock_t
*clock
)
584 clock
->m
= clock
->m2
+ 2;
585 clock
->p
= clock
->p1
* clock
->p2
;
586 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
587 clock
->dot
= clock
->vco
/ clock
->p
;
590 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
593 igd_clock(refclk
, clock
);
596 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
597 clock
->p
= clock
->p1
* clock
->p2
;
598 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
599 clock
->dot
= clock
->vco
/ clock
->p
;
603 * Returns whether any output on the specified pipe is of the specified type
605 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
607 struct drm_device
*dev
= crtc
->dev
;
608 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
609 struct drm_connector
*l_entry
;
611 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
612 if (l_entry
->encoder
&&
613 l_entry
->encoder
->crtc
== crtc
) {
614 struct intel_output
*intel_output
= to_intel_output(l_entry
);
615 if (intel_output
->type
== type
)
622 struct drm_connector
*
623 intel_pipe_get_output (struct drm_crtc
*crtc
)
625 struct drm_device
*dev
= crtc
->dev
;
626 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
627 struct drm_connector
*l_entry
, *ret
= NULL
;
629 list_for_each_entry(l_entry
, &mode_config
->connector_list
, head
) {
630 if (l_entry
->encoder
&&
631 l_entry
->encoder
->crtc
== crtc
) {
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
645 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
647 const intel_limit_t
*limit
= intel_limit (crtc
);
648 struct drm_device
*dev
= crtc
->dev
;
650 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
651 INTELPllInvalid ("p1 out of range\n");
652 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
653 INTELPllInvalid ("p out of range\n");
654 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
655 INTELPllInvalid ("m2 out of range\n");
656 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
657 INTELPllInvalid ("m1 out of range\n");
658 if (clock
->m1
<= clock
->m2
&& !IS_IGD(dev
))
659 INTELPllInvalid ("m1 <= m2\n");
660 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
661 INTELPllInvalid ("m out of range\n");
662 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
663 INTELPllInvalid ("n out of range\n");
664 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
665 INTELPllInvalid ("vco out of range\n");
666 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
667 * connector, etc., rather than just a single range.
669 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
670 INTELPllInvalid ("dot out of range\n");
676 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
677 int target
, int refclk
, intel_clock_t
*best_clock
)
680 struct drm_device
*dev
= crtc
->dev
;
681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
685 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
686 (I915_READ(LVDS
)) != 0) {
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
693 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
695 clock
.p2
= limit
->p2
.p2_fast
;
697 clock
.p2
= limit
->p2
.p2_slow
;
699 if (target
< limit
->p2
.dot_limit
)
700 clock
.p2
= limit
->p2
.p2_slow
;
702 clock
.p2
= limit
->p2
.p2_fast
;
705 memset (best_clock
, 0, sizeof (*best_clock
));
707 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
708 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
710 for (clock
.m2
= limit
->m2
.min
;
711 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
712 /* m1 is always 0 in IGD */
713 if (clock
.m2
>= clock
.m1
&& !IS_IGD(dev
))
715 for (clock
.n
= limit
->n
.min
;
716 clock
.n
<= limit
->n
.max
; clock
.n
++) {
719 intel_clock(dev
, refclk
, &clock
);
721 if (!intel_PLL_is_valid(crtc
, &clock
))
724 this_err
= abs(clock
.dot
- target
);
725 if (this_err
< err
) {
734 return (err
!= target
);
739 intel_find_best_reduced_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
740 int target
, int refclk
, intel_clock_t
*best_clock
)
743 struct drm_device
*dev
= crtc
->dev
;
748 memcpy(&clock
, best_clock
, sizeof(intel_clock_t
));
750 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
751 for (clock
.m2
= limit
->m2
.min
; clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
752 /* m1 is always 0 in IGD */
753 if (clock
.m2
>= clock
.m1
&& !IS_IGD(dev
))
755 for (clock
.n
= limit
->n
.min
; clock
.n
<= limit
->n
.max
;
759 intel_clock(dev
, refclk
, &clock
);
761 if (!intel_PLL_is_valid(crtc
, &clock
))
764 this_err
= abs(clock
.dot
- target
);
765 if (this_err
< err
) {
778 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
779 int target
, int refclk
, intel_clock_t
*best_clock
)
781 struct drm_device
*dev
= crtc
->dev
;
782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
786 /* approximately equals target * 0.00488 */
787 int err_most
= (target
>> 8) + (target
>> 10);
790 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
791 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
793 clock
.p2
= limit
->p2
.p2_fast
;
795 clock
.p2
= limit
->p2
.p2_slow
;
797 if (target
< limit
->p2
.dot_limit
)
798 clock
.p2
= limit
->p2
.p2_slow
;
800 clock
.p2
= limit
->p2
.p2_fast
;
803 memset(best_clock
, 0, sizeof(*best_clock
));
804 max_n
= limit
->n
.max
;
805 /* based on hardware requriment prefer smaller n to precision */
806 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
807 /* based on hardware requirment prefere larger m1,m2 */
808 for (clock
.m1
= limit
->m1
.max
;
809 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
810 for (clock
.m2
= limit
->m2
.max
;
811 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
812 for (clock
.p1
= limit
->p1
.max
;
813 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
816 intel_clock(dev
, refclk
, &clock
);
817 if (!intel_PLL_is_valid(crtc
, &clock
))
819 this_err
= abs(clock
.dot
- target
) ;
820 if (this_err
< err_most
) {
834 intel_find_pll_igdng_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
835 int target
, int refclk
, intel_clock_t
*best_clock
)
837 struct drm_device
*dev
= crtc
->dev
;
839 if (target
< 200000) {
852 intel_clock(dev
, refclk
, &clock
);
853 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
858 intel_igdng_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
859 int target
, int refclk
, intel_clock_t
*best_clock
)
861 struct drm_device
*dev
= crtc
->dev
;
862 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
869 /* eDP has only 2 clock choice, no n/m/p setting */
873 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
874 return intel_find_pll_igdng_dp(limit
, crtc
, target
,
877 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
878 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
880 clock
.p2
= limit
->p2
.p2_fast
;
882 clock
.p2
= limit
->p2
.p2_slow
;
884 if (target
< limit
->p2
.dot_limit
)
885 clock
.p2
= limit
->p2
.p2_slow
;
887 clock
.p2
= limit
->p2
.p2_fast
;
890 memset(best_clock
, 0, sizeof(*best_clock
));
891 max_n
= limit
->n
.max
;
892 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
893 /* based on hardware requriment prefer smaller n to precision */
894 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
895 /* based on hardware requirment prefere larger m1,m2 */
896 for (clock
.m1
= limit
->m1
.max
;
897 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
898 for (clock
.m2
= limit
->m2
.max
;
899 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
902 intel_clock(dev
, refclk
, &clock
);
903 if (!intel_PLL_is_valid(crtc
, &clock
))
905 this_err
= abs((10000 - (target
*10000/clock
.dot
)));
906 if (this_err
< err_most
) {
911 /* found on first matching */
922 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
924 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
925 int target
, int refclk
, intel_clock_t
*best_clock
)
928 if (target
< 200000) {
941 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
942 clock
.p
= (clock
.p1
* clock
.p2
);
943 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
944 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
949 intel_wait_for_vblank(struct drm_device
*dev
)
951 /* Wait for 20ms, i.e. one cycle at 50hz. */
956 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
957 struct drm_framebuffer
*old_fb
)
959 struct drm_device
*dev
= crtc
->dev
;
960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
961 struct drm_i915_master_private
*master_priv
;
962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
963 struct intel_framebuffer
*intel_fb
;
964 struct drm_i915_gem_object
*obj_priv
;
965 struct drm_gem_object
*obj
;
966 int pipe
= intel_crtc
->pipe
;
967 unsigned long Start
, Offset
;
968 int dspbase
= (pipe
== 0 ? DSPAADDR
: DSPBADDR
);
969 int dspsurf
= (pipe
== 0 ? DSPASURF
: DSPBSURF
);
970 int dspstride
= (pipe
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
971 int dsptileoff
= (pipe
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
972 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
973 u32 dspcntr
, alignment
;
978 DRM_DEBUG("No FB bound\n");
987 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
991 intel_fb
= to_intel_framebuffer(crtc
->fb
);
993 obj_priv
= obj
->driver_private
;
995 switch (obj_priv
->tiling_mode
) {
996 case I915_TILING_NONE
:
997 alignment
= 64 * 1024;
1000 /* pin() will align the object as required by fence */
1004 /* FIXME: Is this true? */
1005 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1011 mutex_lock(&dev
->struct_mutex
);
1012 ret
= i915_gem_object_pin(obj
, alignment
);
1014 mutex_unlock(&dev
->struct_mutex
);
1018 ret
= i915_gem_object_set_to_gtt_domain(obj
, 1);
1020 i915_gem_object_unpin(obj
);
1021 mutex_unlock(&dev
->struct_mutex
);
1025 /* Pre-i965 needs to install a fence for tiled scan-out */
1026 if (!IS_I965G(dev
) &&
1027 obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1028 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1029 ret
= i915_gem_object_get_fence_reg(obj
);
1031 i915_gem_object_unpin(obj
);
1032 mutex_unlock(&dev
->struct_mutex
);
1037 dspcntr
= I915_READ(dspcntr_reg
);
1038 /* Mask out pixel format bits in case we change it */
1039 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1040 switch (crtc
->fb
->bits_per_pixel
) {
1042 dspcntr
|= DISPPLANE_8BPP
;
1045 if (crtc
->fb
->depth
== 15)
1046 dspcntr
|= DISPPLANE_15_16BPP
;
1048 dspcntr
|= DISPPLANE_16BPP
;
1052 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1055 DRM_ERROR("Unknown color depth\n");
1056 i915_gem_object_unpin(obj
);
1057 mutex_unlock(&dev
->struct_mutex
);
1060 if (IS_I965G(dev
)) {
1061 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1062 dspcntr
|= DISPPLANE_TILED
;
1064 dspcntr
&= ~DISPPLANE_TILED
;
1069 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1071 I915_WRITE(dspcntr_reg
, dspcntr
);
1073 Start
= obj_priv
->gtt_offset
;
1074 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
1076 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
1077 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
1078 if (IS_I965G(dev
)) {
1079 I915_WRITE(dspbase
, Offset
);
1081 I915_WRITE(dspsurf
, Start
);
1083 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1085 I915_WRITE(dspbase
, Start
+ Offset
);
1089 intel_wait_for_vblank(dev
);
1092 intel_fb
= to_intel_framebuffer(old_fb
);
1093 obj_priv
= intel_fb
->obj
->driver_private
;
1094 i915_gem_object_unpin(intel_fb
->obj
);
1096 intel_increase_pllclock(crtc
, true);
1098 mutex_unlock(&dev
->struct_mutex
);
1100 if (!dev
->primary
->master
)
1103 master_priv
= dev
->primary
->master
->driver_priv
;
1104 if (!master_priv
->sarea_priv
)
1108 master_priv
->sarea_priv
->pipeB_x
= x
;
1109 master_priv
->sarea_priv
->pipeB_y
= y
;
1111 master_priv
->sarea_priv
->pipeA_x
= x
;
1112 master_priv
->sarea_priv
->pipeA_y
= y
;
1118 /* Disable the VGA plane that we never use */
1119 static void i915_disable_vga (struct drm_device
*dev
)
1121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1126 vga_reg
= CPU_VGACNTRL
;
1130 if (I915_READ(vga_reg
) & VGA_DISP_DISABLE
)
1133 I915_WRITE8(VGA_SR_INDEX
, 1);
1134 sr1
= I915_READ8(VGA_SR_DATA
);
1135 I915_WRITE8(VGA_SR_DATA
, sr1
| (1 << 5));
1138 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
1141 static void igdng_disable_pll_edp (struct drm_crtc
*crtc
)
1143 struct drm_device
*dev
= crtc
->dev
;
1144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1148 dpa_ctl
= I915_READ(DP_A
);
1149 dpa_ctl
&= ~DP_PLL_ENABLE
;
1150 I915_WRITE(DP_A
, dpa_ctl
);
1153 static void igdng_enable_pll_edp (struct drm_crtc
*crtc
)
1155 struct drm_device
*dev
= crtc
->dev
;
1156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1159 dpa_ctl
= I915_READ(DP_A
);
1160 dpa_ctl
|= DP_PLL_ENABLE
;
1161 I915_WRITE(DP_A
, dpa_ctl
);
1166 static void igdng_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1168 struct drm_device
*dev
= crtc
->dev
;
1169 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1172 DRM_DEBUG("eDP PLL enable for clock %d\n", clock
);
1173 dpa_ctl
= I915_READ(DP_A
);
1174 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1176 if (clock
< 200000) {
1178 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1179 /* workaround for 160Mhz:
1180 1) program 0x4600c bits 15:0 = 0x8124
1181 2) program 0x46010 bit 0 = 1
1182 3) program 0x46034 bit 24 = 1
1183 4) program 0x64000 bit 14 = 1
1185 temp
= I915_READ(0x4600c);
1187 I915_WRITE(0x4600c, temp
| 0x8124);
1189 temp
= I915_READ(0x46010);
1190 I915_WRITE(0x46010, temp
| 1);
1192 temp
= I915_READ(0x46034);
1193 I915_WRITE(0x46034, temp
| (1 << 24));
1195 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1197 I915_WRITE(DP_A
, dpa_ctl
);
1202 static void igdng_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1204 struct drm_device
*dev
= crtc
->dev
;
1205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1207 int pipe
= intel_crtc
->pipe
;
1208 int plane
= intel_crtc
->plane
;
1209 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1210 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1211 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1212 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1213 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1214 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1215 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1216 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1217 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1218 int pf_ctl_reg
= (pipe
== 0) ? PFA_CTL_1
: PFB_CTL_1
;
1219 int pf_win_size
= (pipe
== 0) ? PFA_WIN_SZ
: PFB_WIN_SZ
;
1220 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1221 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1222 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1223 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1224 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1225 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1226 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1227 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1228 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1229 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1230 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1231 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1233 int tries
= 5, j
, n
;
1235 /* XXX: When our outputs are all unaware of DPMS modes other than off
1236 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1239 case DRM_MODE_DPMS_ON
:
1240 case DRM_MODE_DPMS_STANDBY
:
1241 case DRM_MODE_DPMS_SUSPEND
:
1242 DRM_DEBUG("crtc %d dpms on\n", pipe
);
1244 /* enable eDP PLL */
1245 igdng_enable_pll_edp(crtc
);
1247 /* enable PCH DPLL */
1248 temp
= I915_READ(pch_dpll_reg
);
1249 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1250 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1251 I915_READ(pch_dpll_reg
);
1254 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1255 temp
= I915_READ(fdi_rx_reg
);
1256 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
|
1258 FDI_DP_PORT_WIDTH_X4
); /* default 4 lanes */
1259 I915_READ(fdi_rx_reg
);
1262 /* Enable CPU FDI TX PLL, always on for IGDNG */
1263 temp
= I915_READ(fdi_tx_reg
);
1264 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1265 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
1266 I915_READ(fdi_tx_reg
);
1271 /* Enable CPU pipe */
1272 temp
= I915_READ(pipeconf_reg
);
1273 if ((temp
& PIPEACONF_ENABLE
) == 0) {
1274 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1275 I915_READ(pipeconf_reg
);
1279 /* configure and enable CPU plane */
1280 temp
= I915_READ(dspcntr_reg
);
1281 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1282 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1283 /* Flush the plane changes */
1284 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1288 /* enable CPU FDI TX and PCH FDI RX */
1289 temp
= I915_READ(fdi_tx_reg
);
1290 temp
|= FDI_TX_ENABLE
;
1291 temp
|= FDI_DP_PORT_WIDTH_X4
; /* default */
1292 temp
&= ~FDI_LINK_TRAIN_NONE
;
1293 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1294 I915_WRITE(fdi_tx_reg
, temp
);
1295 I915_READ(fdi_tx_reg
);
1297 temp
= I915_READ(fdi_rx_reg
);
1298 temp
&= ~FDI_LINK_TRAIN_NONE
;
1299 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1300 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1301 I915_READ(fdi_rx_reg
);
1306 /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1308 temp
= I915_READ(fdi_rx_imr_reg
);
1309 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1310 temp
&= ~FDI_RX_BIT_LOCK
;
1311 I915_WRITE(fdi_rx_imr_reg
, temp
);
1312 I915_READ(fdi_rx_imr_reg
);
1315 temp
= I915_READ(fdi_rx_iir_reg
);
1316 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp
);
1318 if ((temp
& FDI_RX_BIT_LOCK
) == 0) {
1319 for (j
= 0; j
< tries
; j
++) {
1320 temp
= I915_READ(fdi_rx_iir_reg
);
1321 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp
);
1322 if (temp
& FDI_RX_BIT_LOCK
)
1327 I915_WRITE(fdi_rx_iir_reg
,
1328 temp
| FDI_RX_BIT_LOCK
);
1330 DRM_DEBUG("train 1 fail\n");
1332 I915_WRITE(fdi_rx_iir_reg
,
1333 temp
| FDI_RX_BIT_LOCK
);
1334 DRM_DEBUG("train 1 ok 2!\n");
1336 temp
= I915_READ(fdi_tx_reg
);
1337 temp
&= ~FDI_LINK_TRAIN_NONE
;
1338 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1339 I915_WRITE(fdi_tx_reg
, temp
);
1341 temp
= I915_READ(fdi_rx_reg
);
1342 temp
&= ~FDI_LINK_TRAIN_NONE
;
1343 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1344 I915_WRITE(fdi_rx_reg
, temp
);
1348 temp
= I915_READ(fdi_rx_iir_reg
);
1349 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp
);
1351 if ((temp
& FDI_RX_SYMBOL_LOCK
) == 0) {
1352 for (j
= 0; j
< tries
; j
++) {
1353 temp
= I915_READ(fdi_rx_iir_reg
);
1354 DRM_DEBUG("FDI_RX_IIR 0x%x\n", temp
);
1355 if (temp
& FDI_RX_SYMBOL_LOCK
)
1360 I915_WRITE(fdi_rx_iir_reg
,
1361 temp
| FDI_RX_SYMBOL_LOCK
);
1362 DRM_DEBUG("train 2 ok 1!\n");
1364 DRM_DEBUG("train 2 fail\n");
1366 I915_WRITE(fdi_rx_iir_reg
,
1367 temp
| FDI_RX_SYMBOL_LOCK
);
1368 DRM_DEBUG("train 2 ok 2!\n");
1370 DRM_DEBUG("train done\n");
1372 /* set transcoder timing */
1373 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
1374 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
1375 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
1377 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
1378 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
1379 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
1381 /* enable PCH transcoder */
1382 temp
= I915_READ(transconf_reg
);
1383 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
1384 I915_READ(transconf_reg
);
1386 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0)
1391 temp
= I915_READ(fdi_tx_reg
);
1392 temp
&= ~FDI_LINK_TRAIN_NONE
;
1393 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1394 FDI_TX_ENHANCE_FRAME_ENABLE
);
1395 I915_READ(fdi_tx_reg
);
1397 temp
= I915_READ(fdi_rx_reg
);
1398 temp
&= ~FDI_LINK_TRAIN_NONE
;
1399 I915_WRITE(fdi_rx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
1400 FDI_RX_ENHANCE_FRAME_ENABLE
);
1401 I915_READ(fdi_rx_reg
);
1403 /* wait one idle pattern time */
1408 intel_crtc_load_lut(crtc
);
1411 case DRM_MODE_DPMS_OFF
:
1412 DRM_DEBUG("crtc %d dpms off\n", pipe
);
1414 i915_disable_vga(dev
);
1416 /* Disable display plane */
1417 temp
= I915_READ(dspcntr_reg
);
1418 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1419 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1420 /* Flush the plane changes */
1421 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1422 I915_READ(dspbase_reg
);
1425 /* disable cpu pipe, disable after all planes disabled */
1426 temp
= I915_READ(pipeconf_reg
);
1427 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1428 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1429 I915_READ(pipeconf_reg
);
1431 /* wait for cpu pipe off, pipe state */
1432 while ((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) != 0) {
1438 DRM_DEBUG("pipe %d off delay\n", pipe
);
1443 DRM_DEBUG("crtc %d is disabled\n", pipe
);
1446 igdng_disable_pll_edp(crtc
);
1449 /* disable CPU FDI tx and PCH FDI rx */
1450 temp
= I915_READ(fdi_tx_reg
);
1451 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
1452 I915_READ(fdi_tx_reg
);
1454 temp
= I915_READ(fdi_rx_reg
);
1455 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
1456 I915_READ(fdi_rx_reg
);
1460 /* still set train pattern 1 */
1461 temp
= I915_READ(fdi_tx_reg
);
1462 temp
&= ~FDI_LINK_TRAIN_NONE
;
1463 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1464 I915_WRITE(fdi_tx_reg
, temp
);
1466 temp
= I915_READ(fdi_rx_reg
);
1467 temp
&= ~FDI_LINK_TRAIN_NONE
;
1468 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1469 I915_WRITE(fdi_rx_reg
, temp
);
1473 /* disable PCH transcoder */
1474 temp
= I915_READ(transconf_reg
);
1475 if ((temp
& TRANS_ENABLE
) != 0) {
1476 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
1477 I915_READ(transconf_reg
);
1479 /* wait for PCH transcoder off, transcoder state */
1480 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) != 0) {
1486 DRM_DEBUG("transcoder %d off delay\n", pipe
);
1492 /* disable PCH DPLL */
1493 temp
= I915_READ(pch_dpll_reg
);
1494 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
1495 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
1496 I915_READ(pch_dpll_reg
);
1499 temp
= I915_READ(fdi_rx_reg
);
1500 if ((temp
& FDI_RX_PLL_ENABLE
) != 0) {
1501 temp
&= ~FDI_SEL_PCDCLK
;
1502 temp
&= ~FDI_RX_PLL_ENABLE
;
1503 I915_WRITE(fdi_rx_reg
, temp
);
1504 I915_READ(fdi_rx_reg
);
1507 /* Disable CPU FDI TX PLL */
1508 temp
= I915_READ(fdi_tx_reg
);
1509 if ((temp
& FDI_TX_PLL_ENABLE
) != 0) {
1510 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
1511 I915_READ(fdi_tx_reg
);
1516 temp
= I915_READ(pf_ctl_reg
);
1517 if ((temp
& PF_ENABLE
) != 0) {
1518 I915_WRITE(pf_ctl_reg
, temp
& ~PF_ENABLE
);
1519 I915_READ(pf_ctl_reg
);
1521 I915_WRITE(pf_win_size
, 0);
1523 /* Wait for the clocks to turn off. */
1529 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1531 struct drm_device
*dev
= crtc
->dev
;
1532 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1533 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1534 int pipe
= intel_crtc
->pipe
;
1535 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
1536 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
1537 int dspbase_reg
= (pipe
== 0) ? DSPAADDR
: DSPBADDR
;
1538 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1541 /* XXX: When our outputs are all unaware of DPMS modes other than off
1542 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1545 case DRM_MODE_DPMS_ON
:
1546 case DRM_MODE_DPMS_STANDBY
:
1547 case DRM_MODE_DPMS_SUSPEND
:
1548 /* Enable the DPLL */
1549 temp
= I915_READ(dpll_reg
);
1550 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
1551 I915_WRITE(dpll_reg
, temp
);
1552 I915_READ(dpll_reg
);
1553 /* Wait for the clocks to stabilize. */
1555 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1556 I915_READ(dpll_reg
);
1557 /* Wait for the clocks to stabilize. */
1559 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
1560 I915_READ(dpll_reg
);
1561 /* Wait for the clocks to stabilize. */
1565 /* Enable the pipe */
1566 temp
= I915_READ(pipeconf_reg
);
1567 if ((temp
& PIPEACONF_ENABLE
) == 0)
1568 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
1570 /* Enable the plane */
1571 temp
= I915_READ(dspcntr_reg
);
1572 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
1573 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
1574 /* Flush the plane changes */
1575 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1578 intel_crtc_load_lut(crtc
);
1580 /* Give the overlay scaler a chance to enable if it's on this pipe */
1581 //intel_crtc_dpms_video(crtc, true); TODO
1582 intel_update_watermarks(dev
);
1584 case DRM_MODE_DPMS_OFF
:
1585 intel_update_watermarks(dev
);
1586 /* Give the overlay scaler a chance to disable if it's on this pipe */
1587 //intel_crtc_dpms_video(crtc, FALSE); TODO
1589 /* Disable the VGA plane that we never use */
1590 i915_disable_vga(dev
);
1592 /* Disable display plane */
1593 temp
= I915_READ(dspcntr_reg
);
1594 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
1595 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
1596 /* Flush the plane changes */
1597 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
1598 I915_READ(dspbase_reg
);
1601 if (!IS_I9XX(dev
)) {
1602 /* Wait for vblank for the disable to take effect */
1603 intel_wait_for_vblank(dev
);
1606 /* Next, disable display pipes */
1607 temp
= I915_READ(pipeconf_reg
);
1608 if ((temp
& PIPEACONF_ENABLE
) != 0) {
1609 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
1610 I915_READ(pipeconf_reg
);
1613 /* Wait for vblank for the disable to take effect. */
1614 intel_wait_for_vblank(dev
);
1616 temp
= I915_READ(dpll_reg
);
1617 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
1618 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
1619 I915_READ(dpll_reg
);
1622 /* Wait for the clocks to turn off. */
1629 * Sets the power management mode of the pipe and plane.
1631 * This code should probably grow support for turning the cursor off and back
1632 * on appropriately at the same time as we're turning the pipe off/on.
1634 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1636 struct drm_device
*dev
= crtc
->dev
;
1637 struct drm_i915_master_private
*master_priv
;
1638 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1639 int pipe
= intel_crtc
->pipe
;
1643 igdng_crtc_dpms(crtc
, mode
);
1645 i9xx_crtc_dpms(crtc
, mode
);
1647 intel_crtc
->dpms_mode
= mode
;
1649 if (!dev
->primary
->master
)
1652 master_priv
= dev
->primary
->master
->driver_priv
;
1653 if (!master_priv
->sarea_priv
)
1656 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
1660 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
1661 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
1664 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
1665 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
1668 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
1673 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
1675 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1676 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
1679 static void intel_crtc_commit (struct drm_crtc
*crtc
)
1681 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
1682 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
1685 void intel_encoder_prepare (struct drm_encoder
*encoder
)
1687 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1688 /* lvds has its own version of prepare see intel_lvds_prepare */
1689 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
1692 void intel_encoder_commit (struct drm_encoder
*encoder
)
1694 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
1695 /* lvds has its own version of commit see intel_lvds_commit */
1696 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
1699 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
1700 struct drm_display_mode
*mode
,
1701 struct drm_display_mode
*adjusted_mode
)
1703 struct drm_device
*dev
= crtc
->dev
;
1704 if (IS_IGDNG(dev
)) {
1705 /* FDI link clock is fixed at 2.7G */
1706 if (mode
->clock
* 3 > 27000 * 4)
1707 return MODE_CLOCK_HIGH
;
1713 /** Returns the core display clock speed for i830 - i945 */
1714 static int intel_get_core_clock_speed(struct drm_device
*dev
)
1717 /* Core clock values taken from the published datasheets.
1718 * The 830 may go up to 166 Mhz, which we should check.
1722 else if (IS_I915G(dev
))
1724 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_IGDGM(dev
))
1726 else if (IS_I915GM(dev
)) {
1729 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
1731 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
1734 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
1735 case GC_DISPLAY_CLOCK_333_MHZ
:
1738 case GC_DISPLAY_CLOCK_190_200_MHZ
:
1742 } else if (IS_I865G(dev
))
1744 else if (IS_I855(dev
)) {
1746 /* Assume that the hardware is in the high speed state. This
1747 * should be the default.
1749 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
1750 case GC_CLOCK_133_200
:
1751 case GC_CLOCK_100_200
:
1753 case GC_CLOCK_166_250
:
1755 case GC_CLOCK_100_133
:
1758 } else /* 852, 830 */
1761 return 0; /* Silence gcc warning */
1765 * Return the pipe currently connected to the panel fitter,
1766 * or -1 if the panel fitter is not present or not in use
1768 static int intel_panel_fitter_pipe (struct drm_device
*dev
)
1770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1773 /* i830 doesn't have a panel fitter */
1777 pfit_control
= I915_READ(PFIT_CONTROL
);
1779 /* See if the panel fitter is in use */
1780 if ((pfit_control
& PFIT_ENABLE
) == 0)
1783 /* 965 can place panel fitter on either pipe */
1785 return (pfit_control
>> 29) & 0x3;
1787 /* older chips can only use pipe 1 */
1800 fdi_reduce_ratio(u32
*num
, u32
*den
)
1802 while (*num
> 0xffffff || *den
> 0xffffff) {
1808 #define DATA_N 0x800000
1809 #define LINK_N 0x80000
1812 igdng_compute_m_n(int bytes_per_pixel
, int nlanes
,
1813 int pixel_clock
, int link_clock
,
1814 struct fdi_m_n
*m_n
)
1818 m_n
->tu
= 64; /* default size */
1820 temp
= (u64
) DATA_N
* pixel_clock
;
1821 temp
= div_u64(temp
, link_clock
);
1822 m_n
->gmch_m
= div_u64(temp
* bytes_per_pixel
, nlanes
);
1823 m_n
->gmch_n
= DATA_N
;
1824 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
1826 temp
= (u64
) LINK_N
* pixel_clock
;
1827 m_n
->link_m
= div_u64(temp
, link_clock
);
1828 m_n
->link_n
= LINK_N
;
1829 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
1833 struct intel_watermark_params
{
1834 unsigned long fifo_size
;
1835 unsigned long max_wm
;
1836 unsigned long default_wm
;
1837 unsigned long guard_size
;
1838 unsigned long cacheline_size
;
1841 /* IGD has different values for various configs */
1842 static struct intel_watermark_params igd_display_wm
= {
1849 static struct intel_watermark_params igd_display_hplloff_wm
= {
1856 static struct intel_watermark_params igd_cursor_wm
= {
1860 IGD_CURSOR_GUARD_WM
,
1863 static struct intel_watermark_params igd_cursor_hplloff_wm
= {
1867 IGD_CURSOR_GUARD_WM
,
1870 static struct intel_watermark_params i945_wm_info
= {
1877 static struct intel_watermark_params i915_wm_info
= {
1884 static struct intel_watermark_params i855_wm_info
= {
1891 static struct intel_watermark_params i830_wm_info
= {
1900 * intel_calculate_wm - calculate watermark level
1901 * @clock_in_khz: pixel clock
1902 * @wm: chip FIFO params
1903 * @pixel_size: display pixel size
1904 * @latency_ns: memory latency for the platform
1906 * Calculate the watermark level (the level at which the display plane will
1907 * start fetching from memory again). Each chip has a different display
1908 * FIFO size and allocation, so the caller needs to figure that out and pass
1909 * in the correct intel_watermark_params structure.
1911 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1912 * on the pixel size. When it reaches the watermark level, it'll start
1913 * fetching FIFO line sized based chunks from memory until the FIFO fills
1914 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1915 * will occur, and a display engine hang could result.
1917 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
1918 struct intel_watermark_params
*wm
,
1920 unsigned long latency_ns
)
1922 long entries_required
, wm_size
;
1924 entries_required
= (clock_in_khz
* pixel_size
* latency_ns
) / 1000000;
1925 entries_required
/= wm
->cacheline_size
;
1927 DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required
);
1929 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
1931 DRM_DEBUG("FIFO watermark level: %d\n", wm_size
);
1933 /* Don't promote wm_size to unsigned... */
1934 if (wm_size
> (long)wm
->max_wm
)
1935 wm_size
= wm
->max_wm
;
1937 wm_size
= wm
->default_wm
;
1941 struct cxsr_latency
{
1943 unsigned long fsb_freq
;
1944 unsigned long mem_freq
;
1945 unsigned long display_sr
;
1946 unsigned long display_hpll_disable
;
1947 unsigned long cursor_sr
;
1948 unsigned long cursor_hpll_disable
;
1951 static struct cxsr_latency cxsr_latency_table
[] = {
1952 {1, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
1953 {1, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
1954 {1, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
1956 {1, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
1957 {1, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
1958 {1, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
1960 {1, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
1961 {1, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
1962 {1, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
1964 {0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
1965 {0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
1966 {0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
1968 {0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
1969 {0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
1970 {0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
1972 {0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
1973 {0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
1974 {0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
1977 static struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
, int fsb
,
1981 struct cxsr_latency
*latency
;
1983 if (fsb
== 0 || mem
== 0)
1986 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
1987 latency
= &cxsr_latency_table
[i
];
1988 if (is_desktop
== latency
->is_desktop
&&
1989 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
1992 if (i
>= ARRAY_SIZE(cxsr_latency_table
)) {
1993 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
1999 static void igd_disable_cxsr(struct drm_device
*dev
)
2001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2004 /* deactivate cxsr */
2005 reg
= I915_READ(DSPFW3
);
2006 reg
&= ~(IGD_SELF_REFRESH_EN
);
2007 I915_WRITE(DSPFW3
, reg
);
2008 DRM_INFO("Big FIFO is disabled\n");
2011 static void igd_enable_cxsr(struct drm_device
*dev
, unsigned long clock
,
2014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2017 struct cxsr_latency
*latency
;
2019 latency
= intel_get_cxsr_latency(IS_IGDG(dev
), dev_priv
->fsb_freq
,
2020 dev_priv
->mem_freq
);
2022 DRM_DEBUG("Unknown FSB/MEM found, disable CxSR\n");
2023 igd_disable_cxsr(dev
);
2028 wm
= intel_calculate_wm(clock
, &igd_display_wm
, pixel_size
,
2029 latency
->display_sr
);
2030 reg
= I915_READ(DSPFW1
);
2033 I915_WRITE(DSPFW1
, reg
);
2034 DRM_DEBUG("DSPFW1 register is %x\n", reg
);
2037 wm
= intel_calculate_wm(clock
, &igd_cursor_wm
, pixel_size
,
2038 latency
->cursor_sr
);
2039 reg
= I915_READ(DSPFW3
);
2040 reg
&= ~(0x3f << 24);
2041 reg
|= (wm
& 0x3f) << 24;
2042 I915_WRITE(DSPFW3
, reg
);
2044 /* Display HPLL off SR */
2045 wm
= intel_calculate_wm(clock
, &igd_display_hplloff_wm
,
2046 latency
->display_hpll_disable
, I915_FIFO_LINE_SIZE
);
2047 reg
= I915_READ(DSPFW3
);
2050 I915_WRITE(DSPFW3
, reg
);
2052 /* cursor HPLL off SR */
2053 wm
= intel_calculate_wm(clock
, &igd_cursor_hplloff_wm
, pixel_size
,
2054 latency
->cursor_hpll_disable
);
2055 reg
= I915_READ(DSPFW3
);
2056 reg
&= ~(0x3f << 16);
2057 reg
|= (wm
& 0x3f) << 16;
2058 I915_WRITE(DSPFW3
, reg
);
2059 DRM_DEBUG("DSPFW3 register is %x\n", reg
);
2062 reg
= I915_READ(DSPFW3
);
2063 reg
|= IGD_SELF_REFRESH_EN
;
2064 I915_WRITE(DSPFW3
, reg
);
2066 DRM_INFO("Big FIFO is enabled\n");
2072 * Latency for FIFO fetches is dependent on several factors:
2073 * - memory configuration (speed, channels)
2075 * - current MCH state
2076 * It can be fairly high in some situations, so here we assume a fairly
2077 * pessimal value. It's a tradeoff between extra memory fetches (if we
2078 * set this value too high, the FIFO will fetch frequently to stay full)
2079 * and power consumption (set it too low to save power and we might see
2080 * FIFO underruns and display "flicker").
2082 * A value of 5us seems to be a good balance; safe for very low end
2083 * platforms but not overly aggressive on lower latency configs.
2085 const static int latency_ns
= 5000;
2087 static int intel_get_fifo_size(struct drm_device
*dev
, int plane
)
2089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2090 uint32_t dsparb
= I915_READ(DSPARB
);
2095 size
= dsparb
& 0x7f;
2097 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) -
2099 } else if (IS_I85X(dev
)) {
2101 size
= dsparb
& 0x1ff;
2103 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) -
2105 size
>>= 1; /* Convert to cachelines */
2106 } else if (IS_845G(dev
)) {
2107 size
= dsparb
& 0x7f;
2108 size
>>= 2; /* Convert to cachelines */
2110 size
= dsparb
& 0x7f;
2111 size
>>= 1; /* Convert to cachelines */
2114 DRM_DEBUG("FIFO size - (0x%08x) %s: %d\n", dsparb
, plane
? "B" : "A",
2120 static void g4x_update_wm(struct drm_device
*dev
)
2122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2123 u32 fw_blc_self
= I915_READ(FW_BLC_SELF
);
2126 fw_blc_self
|= FW_BLC_SELF_EN
;
2128 fw_blc_self
&= ~FW_BLC_SELF_EN
;
2129 I915_WRITE(FW_BLC_SELF
, fw_blc_self
);
2132 static void i965_update_wm(struct drm_device
*dev
)
2134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2136 DRM_DEBUG("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR 8\n");
2138 /* 965 has limitations... */
2139 I915_WRITE(DSPFW1
, (8 << 16) | (8 << 8) | (8 << 0));
2140 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
2143 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
2144 int planeb_clock
, int sr_hdisplay
, int pixel_size
)
2146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2149 int total_size
, cacheline_size
, cwm
, srwm
= 1;
2150 int planea_wm
, planeb_wm
;
2151 struct intel_watermark_params planea_params
, planeb_params
;
2152 unsigned long line_time_us
;
2153 int sr_clock
, sr_entries
= 0;
2155 /* Create copies of the base settings for each pipe */
2156 if (IS_I965GM(dev
) || IS_I945GM(dev
))
2157 planea_params
= planeb_params
= i945_wm_info
;
2158 else if (IS_I9XX(dev
))
2159 planea_params
= planeb_params
= i915_wm_info
;
2161 planea_params
= planeb_params
= i855_wm_info
;
2163 /* Grab a couple of global values before we overwrite them */
2164 total_size
= planea_params
.fifo_size
;
2165 cacheline_size
= planea_params
.cacheline_size
;
2167 /* Update per-plane FIFO sizes */
2168 planea_params
.fifo_size
= intel_get_fifo_size(dev
, 0);
2169 planeb_params
.fifo_size
= intel_get_fifo_size(dev
, 1);
2171 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
2172 pixel_size
, latency_ns
);
2173 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
2174 pixel_size
, latency_ns
);
2175 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
2178 * Overlay gets an aggressive default since video jitter is bad.
2182 /* Calc sr entries for one plane configs */
2183 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
2184 (!planea_clock
|| !planeb_clock
)) {
2185 /* self-refresh has much higher latency */
2186 const static int sr_latency_ns
= 6000;
2188 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
2189 line_time_us
= ((sr_hdisplay
* 1000) / sr_clock
);
2191 /* Use ns/us then divide to preserve precision */
2192 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1) *
2193 pixel_size
* sr_hdisplay
) / 1000;
2194 sr_entries
= roundup(sr_entries
/ cacheline_size
, 1);
2195 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
2196 srwm
= total_size
- sr_entries
;
2199 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
| (srwm
& 0x3f));
2202 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2203 planea_wm
, planeb_wm
, cwm
, srwm
);
2205 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
2206 fwater_hi
= (cwm
& 0x1f);
2208 /* Set request length to 8 cachelines per fetch */
2209 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
2210 fwater_hi
= fwater_hi
| (1 << 8);
2212 I915_WRITE(FW_BLC
, fwater_lo
);
2213 I915_WRITE(FW_BLC2
, fwater_hi
);
2216 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
,
2219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2220 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
2223 i830_wm_info
.fifo_size
= intel_get_fifo_size(dev
, 0);
2225 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
2226 pixel_size
, latency_ns
);
2227 fwater_lo
|= (3<<8) | planea_wm
;
2229 DRM_DEBUG("Setting FIFO watermarks - A: %d\n", planea_wm
);
2231 I915_WRITE(FW_BLC
, fwater_lo
);
2235 * intel_update_watermarks - update FIFO watermark values based on current modes
2237 * Calculate watermark values for the various WM regs based on current mode
2238 * and plane configuration.
2240 * There are several cases to deal with here:
2241 * - normal (i.e. non-self-refresh)
2242 * - self-refresh (SR) mode
2243 * - lines are large relative to FIFO size (buffer can hold up to 2)
2244 * - lines are small relative to FIFO size (buffer can hold more than 2
2245 * lines), so need to account for TLB latency
2247 * The normal calculation is:
2248 * watermark = dotclock * bytes per pixel * latency
2249 * where latency is platform & configuration dependent (we assume pessimal
2252 * The SR calculation is:
2253 * watermark = (trunc(latency/line time)+1) * surface width *
2256 * line time = htotal / dotclock
2257 * and latency is assumed to be high, as above.
2259 * The final value programmed to the register should always be rounded up,
2260 * and include an extra 2 entries to account for clock crossings.
2262 * We don't use the sprite, so we can ignore that. And on Crestline we have
2263 * to set the non-SR watermarks to 8.
2265 static void intel_update_watermarks(struct drm_device
*dev
)
2267 struct drm_crtc
*crtc
;
2268 struct intel_crtc
*intel_crtc
;
2269 int sr_hdisplay
= 0;
2270 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
2271 int enabled
= 0, pixel_size
= 0;
2273 /* Get the clock config from both planes */
2274 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2275 intel_crtc
= to_intel_crtc(crtc
);
2276 if (crtc
->enabled
) {
2278 if (intel_crtc
->plane
== 0) {
2279 DRM_DEBUG("plane A (pipe %d) clock: %d\n",
2280 intel_crtc
->pipe
, crtc
->mode
.clock
);
2281 planea_clock
= crtc
->mode
.clock
;
2283 DRM_DEBUG("plane B (pipe %d) clock: %d\n",
2284 intel_crtc
->pipe
, crtc
->mode
.clock
);
2285 planeb_clock
= crtc
->mode
.clock
;
2287 sr_hdisplay
= crtc
->mode
.hdisplay
;
2288 sr_clock
= crtc
->mode
.clock
;
2290 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
2292 pixel_size
= 4; /* by default */
2299 /* Single plane configs can enable self refresh */
2300 if (enabled
== 1 && IS_IGD(dev
))
2301 igd_enable_cxsr(dev
, sr_clock
, pixel_size
);
2302 else if (IS_IGD(dev
))
2303 igd_disable_cxsr(dev
);
2307 else if (IS_I965G(dev
))
2308 i965_update_wm(dev
);
2309 else if (IS_I9XX(dev
) || IS_MOBILE(dev
))
2310 i9xx_update_wm(dev
, planea_clock
, planeb_clock
, sr_hdisplay
,
2313 i830_update_wm(dev
, planea_clock
, pixel_size
);
2316 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
2317 struct drm_display_mode
*mode
,
2318 struct drm_display_mode
*adjusted_mode
,
2320 struct drm_framebuffer
*old_fb
)
2322 struct drm_device
*dev
= crtc
->dev
;
2323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2324 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2325 int pipe
= intel_crtc
->pipe
;
2326 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
2327 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2328 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
2329 int dspcntr_reg
= (pipe
== 0) ? DSPACNTR
: DSPBCNTR
;
2330 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2331 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
2332 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
2333 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
2334 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
2335 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
2336 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
2337 int dspsize_reg
= (pipe
== 0) ? DSPASIZE
: DSPBSIZE
;
2338 int dsppos_reg
= (pipe
== 0) ? DSPAPOS
: DSPBPOS
;
2339 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
2340 int refclk
, num_outputs
= 0;
2341 intel_clock_t clock
, reduced_clock
;
2342 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
2343 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
2344 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
2345 bool is_edp
= false;
2346 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2347 struct drm_connector
*connector
;
2348 const intel_limit_t
*limit
;
2350 struct fdi_m_n m_n
= {0};
2351 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
2352 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
2353 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
2354 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
2355 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
2356 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
2357 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
2358 int lvds_reg
= LVDS
;
2360 int sdvo_pixel_multiply
;
2363 drm_vblank_pre_modeset(dev
, pipe
);
2365 list_for_each_entry(connector
, &mode_config
->connector_list
, head
) {
2366 struct intel_output
*intel_output
= to_intel_output(connector
);
2368 if (!connector
->encoder
|| connector
->encoder
->crtc
!= crtc
)
2371 switch (intel_output
->type
) {
2372 case INTEL_OUTPUT_LVDS
:
2375 case INTEL_OUTPUT_SDVO
:
2376 case INTEL_OUTPUT_HDMI
:
2378 if (intel_output
->needs_tv_clock
)
2381 case INTEL_OUTPUT_DVO
:
2384 case INTEL_OUTPUT_TVOUT
:
2387 case INTEL_OUTPUT_ANALOG
:
2390 case INTEL_OUTPUT_DISPLAYPORT
:
2393 case INTEL_OUTPUT_EDP
:
2401 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2) {
2402 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
2403 DRM_DEBUG("using SSC reference clock of %d MHz\n", refclk
/ 1000);
2404 } else if (IS_I9XX(dev
)) {
2407 refclk
= 120000; /* 120Mhz refclk */
2414 * Returns a set of divisors for the desired target clock with the given
2415 * refclk, or FALSE. The returned values represent the clock equation:
2416 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2418 limit
= intel_limit(crtc
);
2419 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
2421 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2422 drm_vblank_post_modeset(dev
, pipe
);
2426 if (limit
->find_reduced_pll
&& dev_priv
->lvds_downclock_avail
) {
2427 memcpy(&reduced_clock
, &clock
, sizeof(intel_clock_t
));
2428 has_reduced_clock
= limit
->find_reduced_pll(limit
, crtc
,
2429 (adjusted_mode
->clock
*3/4),
2434 /* SDVO TV has fixed PLL values depend on its clock range,
2435 this mirrors vbios setting. */
2436 if (is_sdvo
&& is_tv
) {
2437 if (adjusted_mode
->clock
>= 100000
2438 && adjusted_mode
->clock
< 140500) {
2444 } else if (adjusted_mode
->clock
>= 140500
2445 && adjusted_mode
->clock
<= 200000) {
2455 if (IS_IGDNG(dev
)) {
2457 /* eDP doesn't require FDI link, so just set DP M/N
2458 according to current link config */
2460 struct drm_connector
*edp
;
2461 target_clock
= mode
->clock
;
2462 edp
= intel_pipe_get_output(crtc
);
2463 intel_edp_link_config(to_intel_output(edp
),
2466 /* DP over FDI requires target mode clock
2467 instead of link clock */
2469 target_clock
= mode
->clock
;
2471 target_clock
= adjusted_mode
->clock
;
2475 igdng_compute_m_n(3, lane
, target_clock
,
2480 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
2481 if (has_reduced_clock
)
2482 fp2
= (1 << reduced_clock
.n
) << 16 |
2483 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
2485 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
2486 if (has_reduced_clock
)
2487 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
2492 dpll
= DPLL_VGA_MODE_DIS
;
2496 dpll
|= DPLLB_MODE_LVDS
;
2498 dpll
|= DPLLB_MODE_DAC_SERIAL
;
2500 dpll
|= DPLL_DVO_HIGH_SPEED
;
2501 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
2502 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
2503 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
2504 else if (IS_IGDNG(dev
))
2505 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
2508 dpll
|= DPLL_DVO_HIGH_SPEED
;
2510 /* compute bitmask from p1 value */
2512 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_IGD
;
2514 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
2517 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
2518 if (IS_G4X(dev
) && has_reduced_clock
)
2519 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
2523 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
2526 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
2529 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
2532 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
2535 if (IS_I965G(dev
) && !IS_IGDNG(dev
))
2536 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
2539 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
2542 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
2544 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
2546 dpll
|= PLL_P2_DIVIDE_BY_4
;
2550 if (is_sdvo
&& is_tv
)
2551 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
2553 /* XXX: just matching BIOS for now */
2554 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
2556 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_outputs
< 2)
2557 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
2559 dpll
|= PLL_REF_INPUT_DREFCLK
;
2561 /* setup pipeconf */
2562 pipeconf
= I915_READ(pipeconf_reg
);
2564 /* Set up the display plane register */
2565 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2567 /* IGDNG's plane is forced to pipe, bit 24 is to
2568 enable color space conversion */
2569 if (!IS_IGDNG(dev
)) {
2571 dspcntr
|= DISPPLANE_SEL_PIPE_A
;
2573 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2576 if (pipe
== 0 && !IS_I965G(dev
)) {
2577 /* Enable pixel doubling when the dot clock is > 90% of the (display)
2580 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
2583 if (mode
->clock
> intel_get_core_clock_speed(dev
) * 9 / 10)
2584 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
2586 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
2589 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2590 pipeconf
|= PIPEACONF_ENABLE
;
2591 dpll
|= DPLL_VCO_ENABLE
;
2594 /* Disable the panel fitter if it was on our pipe */
2595 if (!IS_IGDNG(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
2596 I915_WRITE(PFIT_CONTROL
, 0);
2598 DRM_DEBUG("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
2599 drm_mode_debug_printmodeline(mode
);
2601 /* assign to IGDNG registers */
2602 if (IS_IGDNG(dev
)) {
2603 fp_reg
= pch_fp_reg
;
2604 dpll_reg
= pch_dpll_reg
;
2608 igdng_disable_pll_edp(crtc
);
2609 } else if ((dpll
& DPLL_VCO_ENABLE
)) {
2610 I915_WRITE(fp_reg
, fp
);
2611 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
2612 I915_READ(dpll_reg
);
2616 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
2617 * This is an exception to the general rule that mode_set doesn't turn
2624 lvds_reg
= PCH_LVDS
;
2626 lvds
= I915_READ(lvds_reg
);
2627 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
| LVDS_PIPEB_SELECT
;
2628 /* Set the B0-B3 data pairs corresponding to whether we're going to
2629 * set the DPLLs for dual-channel mode or not.
2632 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
2634 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
2636 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
2637 * appropriately here, but we need to look more thoroughly into how
2638 * panels behave in the two modes.
2641 I915_WRITE(lvds_reg
, lvds
);
2642 I915_READ(lvds_reg
);
2645 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
2648 I915_WRITE(fp_reg
, fp
);
2649 I915_WRITE(dpll_reg
, dpll
);
2650 I915_READ(dpll_reg
);
2651 /* Wait for the clocks to stabilize. */
2654 if (IS_I965G(dev
) && !IS_IGDNG(dev
)) {
2656 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
2657 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
2658 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
2660 I915_WRITE(dpll_md_reg
, 0);
2662 /* write it again -- the BIOS does, after all */
2663 I915_WRITE(dpll_reg
, dpll
);
2665 I915_READ(dpll_reg
);
2666 /* Wait for the clocks to stabilize. */
2670 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
2671 I915_WRITE(fp_reg
+ 4, fp2
);
2672 intel_crtc
->lowfreq_avail
= true;
2673 if (HAS_PIPE_CXSR(dev
)) {
2674 DRM_DEBUG("enabling CxSR downclocking\n");
2675 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
2678 I915_WRITE(fp_reg
+ 4, fp
);
2679 intel_crtc
->lowfreq_avail
= false;
2680 if (HAS_PIPE_CXSR(dev
)) {
2681 DRM_DEBUG("disabling CxSR downclocking\n");
2682 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
2686 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
2687 ((adjusted_mode
->crtc_htotal
- 1) << 16));
2688 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
2689 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
2690 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
2691 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
2692 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
2693 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
2694 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
2695 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
2696 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
2697 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
2698 /* pipesrc and dspsize control the size that is scaled from, which should
2699 * always be the user's requested size.
2701 if (!IS_IGDNG(dev
)) {
2702 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
2703 (mode
->hdisplay
- 1));
2704 I915_WRITE(dsppos_reg
, 0);
2706 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
2708 if (IS_IGDNG(dev
)) {
2709 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
2710 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
2711 I915_WRITE(link_m1_reg
, m_n
.link_m
);
2712 I915_WRITE(link_n1_reg
, m_n
.link_n
);
2715 igdng_set_pll_edp(crtc
, adjusted_mode
->clock
);
2717 /* enable FDI RX PLL too */
2718 temp
= I915_READ(fdi_rx_reg
);
2719 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
2724 I915_WRITE(pipeconf_reg
, pipeconf
);
2725 I915_READ(pipeconf_reg
);
2727 intel_wait_for_vblank(dev
);
2729 if (IS_IGDNG(dev
)) {
2730 /* enable address swizzle for tiling buffer */
2731 temp
= I915_READ(DISP_ARB_CTL
);
2732 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
2735 I915_WRITE(dspcntr_reg
, dspcntr
);
2737 /* Flush the plane changes */
2738 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
2740 intel_update_watermarks(dev
);
2742 drm_vblank_post_modeset(dev
, pipe
);
2747 /** Loads the palette/gamma unit for the CRTC with the prepared values */
2748 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
2750 struct drm_device
*dev
= crtc
->dev
;
2751 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2752 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2753 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
2756 /* The clocks have to be on to load the palette. */
2760 /* use legacy palette for IGDNG */
2762 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
2765 for (i
= 0; i
< 256; i
++) {
2766 I915_WRITE(palreg
+ 4 * i
,
2767 (intel_crtc
->lut_r
[i
] << 16) |
2768 (intel_crtc
->lut_g
[i
] << 8) |
2769 intel_crtc
->lut_b
[i
]);
2773 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
2774 struct drm_file
*file_priv
,
2776 uint32_t width
, uint32_t height
)
2778 struct drm_device
*dev
= crtc
->dev
;
2779 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2780 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2781 struct drm_gem_object
*bo
;
2782 struct drm_i915_gem_object
*obj_priv
;
2783 int pipe
= intel_crtc
->pipe
;
2784 uint32_t control
= (pipe
== 0) ? CURACNTR
: CURBCNTR
;
2785 uint32_t base
= (pipe
== 0) ? CURABASE
: CURBBASE
;
2786 uint32_t temp
= I915_READ(control
);
2792 /* if we want to turn off the cursor ignore width and height */
2794 DRM_DEBUG("cursor off\n");
2795 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
2796 temp
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
2797 temp
|= CURSOR_MODE_DISABLE
;
2799 temp
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
2803 mutex_lock(&dev
->struct_mutex
);
2807 /* Currently we only support 64x64 cursors */
2808 if (width
!= 64 || height
!= 64) {
2809 DRM_ERROR("we currently only support 64x64 cursors\n");
2813 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
2817 obj_priv
= bo
->driver_private
;
2819 if (bo
->size
< width
* height
* 4) {
2820 DRM_ERROR("buffer is to small\n");
2825 /* we only need to pin inside GTT if cursor is non-phy */
2826 mutex_lock(&dev
->struct_mutex
);
2827 if (!dev_priv
->cursor_needs_physical
) {
2828 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
2830 DRM_ERROR("failed to pin cursor bo\n");
2833 addr
= obj_priv
->gtt_offset
;
2835 ret
= i915_gem_attach_phys_object(dev
, bo
, (pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
2837 DRM_ERROR("failed to attach phys object\n");
2840 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
2844 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
2846 /* Hooray for CUR*CNTR differences */
2847 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
2848 temp
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
2849 temp
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
2850 temp
|= (pipe
<< 28); /* Connect to correct pipe */
2852 temp
&= ~(CURSOR_FORMAT_MASK
);
2853 temp
|= CURSOR_ENABLE
;
2854 temp
|= CURSOR_FORMAT_ARGB
| CURSOR_GAMMA_ENABLE
;
2858 I915_WRITE(control
, temp
);
2859 I915_WRITE(base
, addr
);
2861 if (intel_crtc
->cursor_bo
) {
2862 if (dev_priv
->cursor_needs_physical
) {
2863 if (intel_crtc
->cursor_bo
!= bo
)
2864 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
2866 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
2867 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
2869 mutex_unlock(&dev
->struct_mutex
);
2871 intel_crtc
->cursor_addr
= addr
;
2872 intel_crtc
->cursor_bo
= bo
;
2876 mutex_lock(&dev
->struct_mutex
);
2878 drm_gem_object_unreference(bo
);
2879 mutex_unlock(&dev
->struct_mutex
);
2883 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
2885 struct drm_device
*dev
= crtc
->dev
;
2886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2887 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2888 struct intel_framebuffer
*intel_fb
;
2889 int pipe
= intel_crtc
->pipe
;
2894 intel_fb
= to_intel_framebuffer(crtc
->fb
);
2895 intel_mark_busy(dev
, intel_fb
->obj
);
2899 temp
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
2903 temp
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
2907 temp
|= x
<< CURSOR_X_SHIFT
;
2908 temp
|= y
<< CURSOR_Y_SHIFT
;
2910 adder
= intel_crtc
->cursor_addr
;
2911 I915_WRITE((pipe
== 0) ? CURAPOS
: CURBPOS
, temp
);
2912 I915_WRITE((pipe
== 0) ? CURABASE
: CURBBASE
, adder
);
2917 /** Sets the color ramps on behalf of RandR */
2918 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
2919 u16 blue
, int regno
)
2921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2923 intel_crtc
->lut_r
[regno
] = red
>> 8;
2924 intel_crtc
->lut_g
[regno
] = green
>> 8;
2925 intel_crtc
->lut_b
[regno
] = blue
>> 8;
2928 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
2929 u16
*blue
, uint32_t size
)
2931 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2937 for (i
= 0; i
< 256; i
++) {
2938 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
2939 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
2940 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
2943 intel_crtc_load_lut(crtc
);
2947 * Get a pipe with a simple mode set on it for doing load-based monitor
2950 * It will be up to the load-detect code to adjust the pipe as appropriate for
2951 * its requirements. The pipe will be connected to no other outputs.
2953 * Currently this code will only succeed if there is a pipe with no outputs
2954 * configured for it. In the future, it could choose to temporarily disable
2955 * some outputs to free up a pipe for its use.
2957 * \return crtc, or NULL if no pipes are available.
2960 /* VESA 640x480x72Hz mode to set on the pipe */
2961 static struct drm_display_mode load_detect_mode
= {
2962 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
2963 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
2966 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_output
*intel_output
,
2967 struct drm_display_mode
*mode
,
2970 struct intel_crtc
*intel_crtc
;
2971 struct drm_crtc
*possible_crtc
;
2972 struct drm_crtc
*supported_crtc
=NULL
;
2973 struct drm_encoder
*encoder
= &intel_output
->enc
;
2974 struct drm_crtc
*crtc
= NULL
;
2975 struct drm_device
*dev
= encoder
->dev
;
2976 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2977 struct drm_crtc_helper_funcs
*crtc_funcs
;
2981 * Algorithm gets a little messy:
2982 * - if the connector already has an assigned crtc, use it (but make
2983 * sure it's on first)
2984 * - try to find the first unused crtc that can drive this connector,
2985 * and use that if we find one
2986 * - if there are no unused crtcs available, try to use the first
2987 * one we found that supports the connector
2990 /* See if we already have a CRTC for this connector */
2991 if (encoder
->crtc
) {
2992 crtc
= encoder
->crtc
;
2993 /* Make sure the crtc and connector are running */
2994 intel_crtc
= to_intel_crtc(crtc
);
2995 *dpms_mode
= intel_crtc
->dpms_mode
;
2996 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
2997 crtc_funcs
= crtc
->helper_private
;
2998 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
2999 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3004 /* Find an unused one (if possible) */
3005 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
3007 if (!(encoder
->possible_crtcs
& (1 << i
)))
3009 if (!possible_crtc
->enabled
) {
3010 crtc
= possible_crtc
;
3013 if (!supported_crtc
)
3014 supported_crtc
= possible_crtc
;
3018 * If we didn't find an unused CRTC, don't use any.
3024 encoder
->crtc
= crtc
;
3025 intel_output
->base
.encoder
= encoder
;
3026 intel_output
->load_detect_temp
= true;
3028 intel_crtc
= to_intel_crtc(crtc
);
3029 *dpms_mode
= intel_crtc
->dpms_mode
;
3031 if (!crtc
->enabled
) {
3033 mode
= &load_detect_mode
;
3034 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
3036 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
3037 crtc_funcs
= crtc
->helper_private
;
3038 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
3041 /* Add this connector to the crtc */
3042 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
3043 encoder_funcs
->commit(encoder
);
3045 /* let the connector get through one full cycle before testing */
3046 intel_wait_for_vblank(dev
);
3051 void intel_release_load_detect_pipe(struct intel_output
*intel_output
, int dpms_mode
)
3053 struct drm_encoder
*encoder
= &intel_output
->enc
;
3054 struct drm_device
*dev
= encoder
->dev
;
3055 struct drm_crtc
*crtc
= encoder
->crtc
;
3056 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3057 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3059 if (intel_output
->load_detect_temp
) {
3060 encoder
->crtc
= NULL
;
3061 intel_output
->base
.encoder
= NULL
;
3062 intel_output
->load_detect_temp
= false;
3063 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
3064 drm_helper_disable_unused_functions(dev
);
3067 /* Switch crtc and output back off if necessary */
3068 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
3069 if (encoder
->crtc
== crtc
)
3070 encoder_funcs
->dpms(encoder
, dpms_mode
);
3071 crtc_funcs
->dpms(crtc
, dpms_mode
);
3075 /* Returns the clock of the currently programmed mode of the given pipe. */
3076 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
3078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3079 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3080 int pipe
= intel_crtc
->pipe
;
3081 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
3083 intel_clock_t clock
;
3085 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
3086 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
3088 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
3090 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
3092 clock
.n
= ffs((fp
& FP_N_IGD_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
3093 clock
.m2
= (fp
& FP_M2_IGD_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
3095 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
3096 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
3101 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_IGD
) >>
3102 DPLL_FPA01_P1_POST_DIV_SHIFT_IGD
);
3104 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
3105 DPLL_FPA01_P1_POST_DIV_SHIFT
);
3107 switch (dpll
& DPLL_MODE_MASK
) {
3108 case DPLLB_MODE_DAC_SERIAL
:
3109 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
3112 case DPLLB_MODE_LVDS
:
3113 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
3117 DRM_DEBUG("Unknown DPLL mode %08x in programmed "
3118 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
3122 /* XXX: Handle the 100Mhz refclk */
3123 intel_clock(dev
, 96000, &clock
);
3125 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
3128 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
3129 DPLL_FPA01_P1_POST_DIV_SHIFT
);
3132 if ((dpll
& PLL_REF_INPUT_MASK
) ==
3133 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
3134 /* XXX: might not be 66MHz */
3135 intel_clock(dev
, 66000, &clock
);
3137 intel_clock(dev
, 48000, &clock
);
3139 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
3142 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
3143 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
3145 if (dpll
& PLL_P2_DIVIDE_BY_4
)
3150 intel_clock(dev
, 48000, &clock
);
3154 /* XXX: It would be nice to validate the clocks, but we can't reuse
3155 * i830PllIsValid() because it relies on the xf86_config connector
3156 * configuration being accurate, which it isn't necessarily.
3162 /** Returns the currently programmed mode of the given pipe. */
3163 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
3164 struct drm_crtc
*crtc
)
3166 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3167 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3168 int pipe
= intel_crtc
->pipe
;
3169 struct drm_display_mode
*mode
;
3170 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
3171 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
3172 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
3173 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
3175 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
3179 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
3180 mode
->hdisplay
= (htot
& 0xffff) + 1;
3181 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
3182 mode
->hsync_start
= (hsync
& 0xffff) + 1;
3183 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
3184 mode
->vdisplay
= (vtot
& 0xffff) + 1;
3185 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
3186 mode
->vsync_start
= (vsync
& 0xffff) + 1;
3187 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
3189 drm_mode_set_name(mode
);
3190 drm_mode_set_crtcinfo(mode
, 0);
3195 #define GPU_IDLE_TIMEOUT 500 /* ms */
3197 /* When this timer fires, we've been idle for awhile */
3198 static void intel_gpu_idle_timer(unsigned long arg
)
3200 struct drm_device
*dev
= (struct drm_device
*)arg
;
3201 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3203 DRM_DEBUG("idle timer fired, downclocking\n");
3205 dev_priv
->busy
= false;
3207 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
3210 void intel_increase_renderclock(struct drm_device
*dev
, bool schedule
)
3212 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3217 if (!dev_priv
->render_reclock_avail
) {
3218 DRM_DEBUG("not reclocking render clock\n");
3222 /* Restore render clock frequency to original value */
3223 if (IS_G4X(dev
) || IS_I9XX(dev
))
3224 pci_write_config_word(dev
->pdev
, GCFGC
, dev_priv
->orig_clock
);
3225 else if (IS_I85X(dev
))
3226 pci_write_config_word(dev
->pdev
, HPLLCC
, dev_priv
->orig_clock
);
3227 DRM_DEBUG("increasing render clock frequency\n");
3229 /* Schedule downclock */
3231 mod_timer(&dev_priv
->idle_timer
, jiffies
+
3232 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
3235 void intel_decrease_renderclock(struct drm_device
*dev
)
3237 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3242 if (!dev_priv
->render_reclock_avail
) {
3243 DRM_DEBUG("not reclocking render clock\n");
3250 /* Adjust render clock... */
3251 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3253 /* Down to minimum... */
3254 gcfgc
&= ~GM45_GC_RENDER_CLOCK_MASK
;
3255 gcfgc
|= GM45_GC_RENDER_CLOCK_266_MHZ
;
3257 pci_write_config_word(dev
->pdev
, GCFGC
, gcfgc
);
3258 } else if (IS_I965G(dev
)) {
3261 /* Adjust render clock... */
3262 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3264 /* Down to minimum... */
3265 gcfgc
&= ~I965_GC_RENDER_CLOCK_MASK
;
3266 gcfgc
|= I965_GC_RENDER_CLOCK_267_MHZ
;
3268 pci_write_config_word(dev
->pdev
, GCFGC
, gcfgc
);
3269 } else if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3272 /* Adjust render clock... */
3273 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3275 /* Down to minimum... */
3276 gcfgc
&= ~I945_GC_RENDER_CLOCK_MASK
;
3277 gcfgc
|= I945_GC_RENDER_CLOCK_166_MHZ
;
3279 pci_write_config_word(dev
->pdev
, GCFGC
, gcfgc
);
3280 } else if (IS_I915G(dev
)) {
3283 /* Adjust render clock... */
3284 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3286 /* Down to minimum... */
3287 gcfgc
&= ~I915_GC_RENDER_CLOCK_MASK
;
3288 gcfgc
|= I915_GC_RENDER_CLOCK_166_MHZ
;
3290 pci_write_config_word(dev
->pdev
, GCFGC
, gcfgc
);
3291 } else if (IS_I85X(dev
)) {
3294 /* Adjust render clock... */
3295 pci_read_config_word(dev
->pdev
, HPLLCC
, &hpllcc
);
3297 /* Up to maximum... */
3298 hpllcc
&= ~GC_CLOCK_CONTROL_MASK
;
3299 hpllcc
|= GC_CLOCK_133_200
;
3301 pci_write_config_word(dev
->pdev
, HPLLCC
, hpllcc
);
3303 DRM_DEBUG("decreasing render clock frequency\n");
3306 /* Note that no increase function is needed for this - increase_renderclock()
3307 * will also rewrite these bits
3309 void intel_decrease_displayclock(struct drm_device
*dev
)
3314 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_I915G(dev
) ||
3318 /* Adjust render clock... */
3319 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3321 /* Down to minimum... */
3325 pci_write_config_word(dev
->pdev
, GCFGC
, gcfgc
);
3329 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3331 static void intel_crtc_idle_timer(unsigned long arg
)
3333 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
3334 struct drm_crtc
*crtc
= &intel_crtc
->base
;
3335 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
3337 DRM_DEBUG("idle timer fired, downclocking\n");
3339 intel_crtc
->busy
= false;
3341 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
3344 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
)
3346 struct drm_device
*dev
= crtc
->dev
;
3347 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3349 int pipe
= intel_crtc
->pipe
;
3350 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3351 int dpll
= I915_READ(dpll_reg
);
3356 if (!dev_priv
->lvds_downclock_avail
)
3359 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
3360 DRM_DEBUG("upclocking LVDS\n");
3362 /* Unlock panel regs */
3363 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
3365 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
3366 I915_WRITE(dpll_reg
, dpll
);
3367 dpll
= I915_READ(dpll_reg
);
3368 intel_wait_for_vblank(dev
);
3369 dpll
= I915_READ(dpll_reg
);
3370 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
3371 DRM_DEBUG("failed to upclock LVDS!\n");
3373 /* ...and lock them again */
3374 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
3377 /* Schedule downclock */
3379 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
3380 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
3383 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
3385 struct drm_device
*dev
= crtc
->dev
;
3386 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3387 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3388 int pipe
= intel_crtc
->pipe
;
3389 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3390 int dpll
= I915_READ(dpll_reg
);
3395 if (!dev_priv
->lvds_downclock_avail
)
3399 * Since this is called by a timer, we should never get here in
3402 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
3403 DRM_DEBUG("downclocking LVDS\n");
3405 /* Unlock panel regs */
3406 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) | (0xabcd << 16));
3408 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
3409 I915_WRITE(dpll_reg
, dpll
);
3410 dpll
= I915_READ(dpll_reg
);
3411 intel_wait_for_vblank(dev
);
3412 dpll
= I915_READ(dpll_reg
);
3413 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
3414 DRM_DEBUG("failed to downclock LVDS!\n");
3416 /* ...and lock them again */
3417 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
3423 * intel_idle_update - adjust clocks for idleness
3424 * @work: work struct
3426 * Either the GPU or display (or both) went idle. Check the busy status
3427 * here and adjust the CRTC and GPU clocks as necessary.
3429 static void intel_idle_update(struct work_struct
*work
)
3431 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
3433 struct drm_device
*dev
= dev_priv
->dev
;
3434 struct drm_crtc
*crtc
;
3435 struct intel_crtc
*intel_crtc
;
3437 if (!i915_powersave
)
3440 mutex_lock(&dev
->struct_mutex
);
3442 /* GPU isn't processing, downclock it. */
3443 if (!dev_priv
->busy
) {
3444 intel_decrease_renderclock(dev
);
3445 intel_decrease_displayclock(dev
);
3448 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3449 /* Skip inactive CRTCs */
3453 intel_crtc
= to_intel_crtc(crtc
);
3454 if (!intel_crtc
->busy
)
3455 intel_decrease_pllclock(crtc
);
3458 mutex_unlock(&dev
->struct_mutex
);
3462 * intel_mark_busy - mark the GPU and possibly the display busy
3464 * @obj: object we're operating on
3466 * Callers can use this function to indicate that the GPU is busy processing
3467 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
3468 * buffer), we'll also mark the display as busy, so we know to increase its
3471 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
3473 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3474 struct drm_crtc
*crtc
= NULL
;
3475 struct intel_framebuffer
*intel_fb
;
3476 struct intel_crtc
*intel_crtc
;
3478 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
3481 dev_priv
->busy
= true;
3482 intel_increase_renderclock(dev
, true);
3484 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3488 intel_crtc
= to_intel_crtc(crtc
);
3489 intel_fb
= to_intel_framebuffer(crtc
->fb
);
3490 if (intel_fb
->obj
== obj
) {
3491 if (!intel_crtc
->busy
) {
3492 /* Non-busy -> busy, upclock */
3493 intel_increase_pllclock(crtc
, true);
3494 intel_crtc
->busy
= true;
3496 /* Busy -> busy, put off timer */
3497 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
3498 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
3504 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
3506 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3508 drm_crtc_cleanup(crtc
);
3512 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
3513 .dpms
= intel_crtc_dpms
,
3514 .mode_fixup
= intel_crtc_mode_fixup
,
3515 .mode_set
= intel_crtc_mode_set
,
3516 .mode_set_base
= intel_pipe_set_base
,
3517 .prepare
= intel_crtc_prepare
,
3518 .commit
= intel_crtc_commit
,
3521 static const struct drm_crtc_funcs intel_crtc_funcs
= {
3522 .cursor_set
= intel_crtc_cursor_set
,
3523 .cursor_move
= intel_crtc_cursor_move
,
3524 .gamma_set
= intel_crtc_gamma_set
,
3525 .set_config
= drm_crtc_helper_set_config
,
3526 .destroy
= intel_crtc_destroy
,
3530 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
3532 struct intel_crtc
*intel_crtc
;
3535 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
3536 if (intel_crtc
== NULL
)
3539 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
3541 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
3542 intel_crtc
->pipe
= pipe
;
3543 intel_crtc
->plane
= pipe
;
3544 for (i
= 0; i
< 256; i
++) {
3545 intel_crtc
->lut_r
[i
] = i
;
3546 intel_crtc
->lut_g
[i
] = i
;
3547 intel_crtc
->lut_b
[i
] = i
;
3550 intel_crtc
->cursor_addr
= 0;
3551 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
3552 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
3554 intel_crtc
->busy
= false;
3556 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
3557 (unsigned long)intel_crtc
);
3560 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
3561 struct drm_file
*file_priv
)
3563 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
3564 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
3565 struct drm_mode_object
*drmmode_obj
;
3566 struct intel_crtc
*crtc
;
3569 DRM_ERROR("called with no initialization\n");
3573 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
3574 DRM_MODE_OBJECT_CRTC
);
3577 DRM_ERROR("no such CRTC id\n");
3581 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
3582 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
3587 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
3589 struct drm_crtc
*crtc
= NULL
;
3591 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3592 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3593 if (intel_crtc
->pipe
== pipe
)
3599 static int intel_connector_clones(struct drm_device
*dev
, int type_mask
)
3602 struct drm_connector
*connector
;
3605 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3606 struct intel_output
*intel_output
= to_intel_output(connector
);
3607 if (type_mask
& intel_output
->clone_mask
)
3608 index_mask
|= (1 << entry
);
3615 static void intel_setup_outputs(struct drm_device
*dev
)
3617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3618 struct drm_connector
*connector
;
3620 intel_crt_init(dev
);
3622 /* Set up integrated LVDS */
3623 if (IS_MOBILE(dev
) && !IS_I830(dev
))
3624 intel_lvds_init(dev
);
3626 if (IS_IGDNG(dev
)) {
3629 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
3630 intel_dp_init(dev
, DP_A
);
3632 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
3634 /* found = intel_sdvo_init(dev, HDMIB); */
3637 intel_hdmi_init(dev
, HDMIB
);
3638 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
3639 intel_dp_init(dev
, PCH_DP_B
);
3642 if (I915_READ(HDMIC
) & PORT_DETECTED
)
3643 intel_hdmi_init(dev
, HDMIC
);
3645 if (I915_READ(HDMID
) & PORT_DETECTED
)
3646 intel_hdmi_init(dev
, HDMID
);
3648 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
3649 intel_dp_init(dev
, PCH_DP_C
);
3651 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
3652 intel_dp_init(dev
, PCH_DP_D
);
3654 } else if (IS_I9XX(dev
)) {
3657 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
3658 found
= intel_sdvo_init(dev
, SDVOB
);
3659 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
))
3660 intel_hdmi_init(dev
, SDVOB
);
3662 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
3663 intel_dp_init(dev
, DP_B
);
3666 /* Before G4X SDVOC doesn't have its own detect register */
3668 if (I915_READ(SDVOB
) & SDVO_DETECTED
)
3669 found
= intel_sdvo_init(dev
, SDVOC
);
3671 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
3673 if (SUPPORTS_INTEGRATED_HDMI(dev
))
3674 intel_hdmi_init(dev
, SDVOC
);
3675 if (SUPPORTS_INTEGRATED_DP(dev
))
3676 intel_dp_init(dev
, DP_C
);
3679 if (SUPPORTS_INTEGRATED_DP(dev
) && (I915_READ(DP_D
) & DP_DETECTED
))
3680 intel_dp_init(dev
, DP_D
);
3682 intel_dvo_init(dev
);
3684 if (IS_I9XX(dev
) && IS_MOBILE(dev
) && !IS_IGDNG(dev
))
3687 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3688 struct intel_output
*intel_output
= to_intel_output(connector
);
3689 struct drm_encoder
*encoder
= &intel_output
->enc
;
3691 encoder
->possible_crtcs
= intel_output
->crtc_mask
;
3692 encoder
->possible_clones
= intel_connector_clones(dev
,
3693 intel_output
->clone_mask
);
3697 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
3699 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
3700 struct drm_device
*dev
= fb
->dev
;
3703 intelfb_remove(dev
, fb
);
3705 drm_framebuffer_cleanup(fb
);
3706 mutex_lock(&dev
->struct_mutex
);
3707 drm_gem_object_unreference(intel_fb
->obj
);
3708 mutex_unlock(&dev
->struct_mutex
);
3713 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
3714 struct drm_file
*file_priv
,
3715 unsigned int *handle
)
3717 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
3718 struct drm_gem_object
*object
= intel_fb
->obj
;
3720 return drm_gem_handle_create(file_priv
, object
, handle
);
3723 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
3724 .destroy
= intel_user_framebuffer_destroy
,
3725 .create_handle
= intel_user_framebuffer_create_handle
,
3728 int intel_framebuffer_create(struct drm_device
*dev
,
3729 struct drm_mode_fb_cmd
*mode_cmd
,
3730 struct drm_framebuffer
**fb
,
3731 struct drm_gem_object
*obj
)
3733 struct intel_framebuffer
*intel_fb
;
3736 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
3740 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
3742 DRM_ERROR("framebuffer init failed %d\n", ret
);
3746 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
3748 intel_fb
->obj
= obj
;
3750 *fb
= &intel_fb
->base
;
3756 static struct drm_framebuffer
*
3757 intel_user_framebuffer_create(struct drm_device
*dev
,
3758 struct drm_file
*filp
,
3759 struct drm_mode_fb_cmd
*mode_cmd
)
3761 struct drm_gem_object
*obj
;
3762 struct drm_framebuffer
*fb
;
3765 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
3769 ret
= intel_framebuffer_create(dev
, mode_cmd
, &fb
, obj
);
3771 mutex_lock(&dev
->struct_mutex
);
3772 drm_gem_object_unreference(obj
);
3773 mutex_unlock(&dev
->struct_mutex
);
3780 static const struct drm_mode_config_funcs intel_mode_funcs
= {
3781 .fb_create
= intel_user_framebuffer_create
,
3782 .fb_changed
= intelfb_probe
,
3785 void intel_init_clock_gating(struct drm_device
*dev
)
3787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3790 * Disable clock gating reported to work incorrectly according to the
3791 * specs, but enable as much else as we can.
3794 uint32_t dspclk_gate
;
3795 I915_WRITE(RENCLK_GATE_D1
, 0);
3796 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
3797 GS_UNIT_CLOCK_GATE_DISABLE
|
3798 CL_UNIT_CLOCK_GATE_DISABLE
);
3799 I915_WRITE(RAMCLK_GATE_D
, 0);
3800 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
3801 OVRUNIT_CLOCK_GATE_DISABLE
|
3802 OVCUNIT_CLOCK_GATE_DISABLE
;
3804 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
3805 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
3806 } else if (IS_I965GM(dev
)) {
3807 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
3808 I915_WRITE(RENCLK_GATE_D2
, 0);
3809 I915_WRITE(DSPCLK_GATE_D
, 0);
3810 I915_WRITE(RAMCLK_GATE_D
, 0);
3811 I915_WRITE16(DEUC
, 0);
3812 } else if (IS_I965G(dev
)) {
3813 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
3814 I965_RCC_CLOCK_GATE_DISABLE
|
3815 I965_RCPB_CLOCK_GATE_DISABLE
|
3816 I965_ISC_CLOCK_GATE_DISABLE
|
3817 I965_FBC_CLOCK_GATE_DISABLE
);
3818 I915_WRITE(RENCLK_GATE_D2
, 0);
3819 } else if (IS_I9XX(dev
)) {
3820 u32 dstate
= I915_READ(D_STATE
);
3822 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
3823 DSTATE_DOT_CLOCK_GATING
;
3824 I915_WRITE(D_STATE
, dstate
);
3825 } else if (IS_I855(dev
) || IS_I865G(dev
)) {
3826 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
3827 } else if (IS_I830(dev
)) {
3828 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
3832 void intel_modeset_init(struct drm_device
*dev
)
3834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3838 drm_mode_config_init(dev
);
3840 dev
->mode_config
.min_width
= 0;
3841 dev
->mode_config
.min_height
= 0;
3843 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
3845 if (IS_I965G(dev
)) {
3846 dev
->mode_config
.max_width
= 8192;
3847 dev
->mode_config
.max_height
= 8192;
3848 } else if (IS_I9XX(dev
)) {
3849 dev
->mode_config
.max_width
= 4096;
3850 dev
->mode_config
.max_height
= 4096;
3852 dev
->mode_config
.max_width
= 2048;
3853 dev
->mode_config
.max_height
= 2048;
3856 /* set memory base */
3858 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
3860 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
3862 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
3866 DRM_DEBUG("%d display pipe%s available.\n",
3867 num_pipe
, num_pipe
> 1 ? "s" : "");
3870 pci_read_config_word(dev
->pdev
, HPLLCC
, &dev_priv
->orig_clock
);
3871 else if (IS_I9XX(dev
) || IS_G4X(dev
))
3872 pci_read_config_word(dev
->pdev
, GCFGC
, &dev_priv
->orig_clock
);
3874 for (i
= 0; i
< num_pipe
; i
++) {
3875 intel_crtc_init(dev
, i
);
3878 intel_setup_outputs(dev
);
3880 intel_init_clock_gating(dev
);
3882 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
3883 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
3884 (unsigned long)dev
);
3887 void intel_modeset_cleanup(struct drm_device
*dev
)
3889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3890 struct drm_crtc
*crtc
;
3891 struct intel_crtc
*intel_crtc
;
3893 mutex_lock(&dev
->struct_mutex
);
3895 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3896 /* Skip inactive CRTCs */
3900 intel_crtc
= to_intel_crtc(crtc
);
3901 intel_increase_pllclock(crtc
, false);
3902 del_timer_sync(&intel_crtc
->idle_timer
);
3905 intel_increase_renderclock(dev
, false);
3906 del_timer_sync(&dev_priv
->idle_timer
);
3908 mutex_unlock(&dev
->struct_mutex
);
3910 drm_mode_config_cleanup(dev
);
3914 /* current intel driver doesn't take advantage of encoders
3915 always give back the encoder for the connector
3917 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
3919 struct intel_output
*intel_output
= to_intel_output(connector
);
3921 return &intel_output
->enc
;