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drm/i915/hdmi: convert to encoder->disable/enable
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include "drmP.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 static bool
84 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
87 static bool
88 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
91
92 static bool
93 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
96 static bool
97 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
100
101 static bool
102 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
106 static inline u32 /* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device *dev)
108 {
109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
114 }
115
116 static const intel_limit_t intel_limits_i8xx_dvo = {
117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
127 .find_pll = intel_find_best_PLL,
128 };
129
130 static const intel_limit_t intel_limits_i8xx_lvds = {
131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
141 .find_pll = intel_find_best_PLL,
142 };
143
144 static const intel_limit_t intel_limits_i9xx_sdvo = {
145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
155 .find_pll = intel_find_best_PLL,
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 .find_pll = intel_find_best_PLL,
170 };
171
172
173 static const intel_limit_t intel_limits_g4x_sdvo = {
174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
185 },
186 .find_pll = intel_g4x_find_best_PLL,
187 };
188
189 static const intel_limit_t intel_limits_g4x_hdmi = {
190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
200 .find_pll = intel_g4x_find_best_PLL,
201 };
202
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
214 },
215 .find_pll = intel_g4x_find_best_PLL,
216 };
217
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
229 },
230 .find_pll = intel_g4x_find_best_PLL,
231 };
232
233 static const intel_limit_t intel_limits_g4x_display_port = {
234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 10, .p2_fast = 10 },
244 .find_pll = intel_find_pll_g4x_dp,
245 };
246
247 static const intel_limit_t intel_limits_pineview_sdvo = {
248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
260 .find_pll = intel_find_best_PLL,
261 };
262
263 static const intel_limit_t intel_limits_pineview_lvds = {
264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
274 .find_pll = intel_find_best_PLL,
275 };
276
277 /* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
282 static const intel_limit_t intel_limits_ironlake_dac = {
283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
293 .find_pll = intel_g4x_find_best_PLL,
294 };
295
296 static const intel_limit_t intel_limits_ironlake_single_lvds = {
297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
307 .find_pll = intel_g4x_find_best_PLL,
308 };
309
310 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
321 .find_pll = intel_g4x_find_best_PLL,
322 };
323
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
336 .find_pll = intel_g4x_find_best_PLL,
337 };
338
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
347 .p1 = { .min = 2, .max = 6 },
348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
350 .find_pll = intel_g4x_find_best_PLL,
351 };
352
353 static const intel_limit_t intel_limits_ironlake_display_port = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
363 .p2_slow = 10, .p2_fast = 10 },
364 .find_pll = intel_find_pll_ironlake_dp,
365 };
366
367 static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379 };
380
381 static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393 };
394
395 static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407 };
408
409 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410 {
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429 out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432 }
433
434 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436 {
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452 out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454 }
455
456 static void vlv_init_dpio(struct drm_device *dev)
457 {
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465 }
466
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468 {
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471 }
472
473 static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483 };
484
485 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487 {
488 unsigned int val;
489
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511 }
512
513 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
515 {
516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
518 const intel_limit_t *limit;
519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
522 /* LVDS dual channel */
523 if (refclk == 100000)
524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
528 if (refclk == 100000)
529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
536 else
537 limit = &intel_limits_ironlake_dac;
538
539 return limit;
540 }
541
542 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543 {
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
549 if (is_dual_link_lvds(dev_priv, LVDS))
550 /* LVDS with dual channel */
551 limit = &intel_limits_g4x_dual_channel_lvds;
552 else
553 /* LVDS with dual channel */
554 limit = &intel_limits_g4x_single_channel_lvds;
555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
557 limit = &intel_limits_g4x_hdmi;
558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
559 limit = &intel_limits_g4x_sdvo;
560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
561 limit = &intel_limits_g4x_display_port;
562 } else /* The option is for other outputs */
563 limit = &intel_limits_i9xx_sdvo;
564
565 return limit;
566 }
567
568 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
569 {
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
573 if (HAS_PCH_SPLIT(dev))
574 limit = intel_ironlake_limit(crtc, refclk);
575 else if (IS_G4X(dev)) {
576 limit = intel_g4x_limit(crtc);
577 } else if (IS_PINEVIEW(dev)) {
578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
579 limit = &intel_limits_pineview_lvds;
580 else
581 limit = &intel_limits_pineview_sdvo;
582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
596 limit = &intel_limits_i8xx_lvds;
597 else
598 limit = &intel_limits_i8xx_dvo;
599 }
600 return limit;
601 }
602
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk, intel_clock_t *clock)
605 {
606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610 }
611
612 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613 {
614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
616 return;
617 }
618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622 }
623
624 /**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
627 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
628 {
629 struct drm_device *dev = crtc->dev;
630 struct intel_encoder *encoder;
631
632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
634 return true;
635
636 return false;
637 }
638
639 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
640 /**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
645 static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
648 {
649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
650 INTELPllInvalid("p1 out of range\n");
651 if (clock->p < limit->p.min || limit->p.max < clock->p)
652 INTELPllInvalid("p out of range\n");
653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
654 INTELPllInvalid("m2 out of range\n");
655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
656 INTELPllInvalid("m1 out of range\n");
657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
658 INTELPllInvalid("m1 <= m2\n");
659 if (clock->m < limit->m.min || limit->m.max < clock->m)
660 INTELPllInvalid("m out of range\n");
661 if (clock->n < limit->n.min || limit->n.max < clock->n)
662 INTELPllInvalid("n out of range\n");
663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
664 INTELPllInvalid("vco out of range\n");
665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
669 INTELPllInvalid("dot out of range\n");
670
671 return true;
672 }
673
674 static bool
675 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678
679 {
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
683 int err = target;
684
685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
686 (I915_READ(LVDS)) != 0) {
687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
693 if (is_dual_link_lvds(dev_priv, LVDS))
694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
704 memset(best_clock, 0, sizeof(*best_clock));
705
706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
717 int this_err;
718
719 intel_clock(dev, refclk, &clock);
720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
722 continue;
723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738 }
739
740 static bool
741 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
744 {
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
755 int lvds_reg;
756
757 if (HAS_PCH_SPLIT(dev))
758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
775 /* based on hardware requirement, prefer smaller n to precision */
776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
777 /* based on hardware requirement, prefere larger m1,m2 */
778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
786 intel_clock(dev, refclk, &clock);
787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
789 continue;
790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
793
794 this_err = abs(clock.dot - target);
795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
805 return found;
806 }
807
808 static bool
809 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815
816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832 }
833
834 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
835 static bool
836 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
860 }
861 static bool
862 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
872 flag = 0;
873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928 }
929
930 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931 {
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939 }
940
941 /**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 int pipestat_reg = PIPESTAT(pipe);
953
954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
979 DRM_DEBUG_KMS("vblank wait timed out\n");
980 }
981
982 /*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
997 *
998 */
999 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1000 {
1001 struct drm_i915_private *dev_priv = dev->dev_private;
1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
1004 int reg = PIPECONF(pipe);
1005
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
1011 u32 last_line, line_mask;
1012 int reg = PIPEDSL(pipe);
1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
1020 /* Wait for the display line to settle */
1021 do {
1022 last_line = I915_READ(reg) & line_mask;
1023 mdelay(5);
1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
1029 }
1030
1031 static const char *state_string(bool enabled)
1032 {
1033 return enabled ? "on" : "off";
1034 }
1035
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039 {
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050 }
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
1054 /* For ILK+ */
1055 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
1059 {
1060 u32 val;
1061 bool cur_state;
1062
1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1070 return;
1071
1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
1095 }
1096 }
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1099
1100 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102 {
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120 }
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126 {
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142 }
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148 {
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163 }
1164
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167 {
1168 int reg;
1169 u32 val;
1170
1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178 }
1179
1180 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182 {
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
1186 bool locked = true;
1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
1206 pipe_name(pipe));
1207 }
1208
1209 void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
1211 {
1212 int reg;
1213 u32 val;
1214 bool cur_state;
1215
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe), state_string(state), state_string(cur_state));
1226 }
1227
1228 static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
1230 {
1231 int reg;
1232 u32 val;
1233 bool cur_state;
1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
1241 }
1242
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
1246 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248 {
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
1260 return;
1261 }
1262
1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
1272 }
1273 }
1274
1275 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276 {
1277 u32 val;
1278 bool enabled;
1279
1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289 }
1290
1291 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293 {
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
1304 }
1305
1306 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
1308 {
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322 }
1323
1324 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326 {
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338 }
1339
1340 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342 {
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354 }
1355
1356 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358 {
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369 }
1370
1371 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1372 enum pipe pipe, int reg, u32 port_sel)
1373 {
1374 u32 val = I915_READ(reg);
1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg, pipe_name(pipe));
1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
1381 }
1382
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385 {
1386 u32 val = I915_READ(reg);
1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg, pipe_name(pipe));
1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
1393 }
1394
1395 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397 {
1398 int reg;
1399 u32 val;
1400
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
1409 pipe_name(pipe));
1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1415 pipe_name(pipe));
1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420 }
1421
1422 /**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1434 */
1435 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461 }
1462
1463 /**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473 {
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489 }
1490
1491 /* SBI access */
1492 static void
1493 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494 {
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518 out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520 }
1521
1522 static u32
1523 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524 {
1525 unsigned long flags;
1526 u32 value = 0;
1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549 out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552 }
1553
1554 /**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
1562 static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
1563 {
1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1565 struct intel_pch_pll *pll;
1566 int reg;
1567 u32 val;
1568
1569 /* PCH PLLs only available on ILK, SNB and IVB */
1570 BUG_ON(dev_priv->info->gen < 5);
1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
1585 if (pll->active++ && pll->on) {
1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
1598
1599 pll->on = true;
1600 }
1601
1602 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1603 {
1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1606 int reg;
1607 u32 val;
1608
1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
1611 if (pll == NULL)
1612 return;
1613
1614 if (WARN_ON(pll->refcount == 0))
1615 return;
1616
1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1620
1621 if (WARN_ON(pll->active == 0)) {
1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
1623 return;
1624 }
1625
1626 if (--pll->active) {
1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
1628 return;
1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1635
1636 reg = pll->pll_reg;
1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
1642
1643 pll->on = false;
1644 }
1645
1646 static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648 {
1649 int reg;
1650 u32 val, pipeconf_val;
1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
1671 pipeconf_val = I915_READ(PIPECONF(pipe));
1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
1679 val |= pipeconf_val & PIPE_BPC_MASK;
1680 }
1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695 }
1696
1697 static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699 {
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1717 }
1718
1719 /**
1720 * intel_enable_pipe - enable a pipe, asserting requirements
1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
1733 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
1735 {
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762 }
1763
1764 /**
1765 * intel_disable_pipe - disable a pipe, asserting requirements
1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778 {
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799 }
1800
1801 /*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
1805 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1806 enum plane plane)
1807 {
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810 }
1811
1812 /**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822 {
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1835 intel_flush_display_plane(dev_priv, plane);
1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837 }
1838
1839 /**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849 {
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861 }
1862
1863 static void disable_pch_dp(struct drm_i915_private *dev_priv,
1864 enum pipe pipe, int reg, u32 port_sel)
1865 {
1866 u32 val = I915_READ(reg);
1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
1869 I915_WRITE(reg, val & ~DP_PORT_EN);
1870 }
1871 }
1872
1873 static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875 {
1876 u32 val = I915_READ(reg);
1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
1880 I915_WRITE(reg, val & ~PORT_ENABLE);
1881 }
1882 }
1883
1884 /* Disable any ports connected to this transcoder */
1885 static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887 {
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914 }
1915
1916 int
1917 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1918 struct drm_i915_gem_object *obj,
1919 struct intel_ring_buffer *pipelined)
1920 {
1921 struct drm_i915_private *dev_priv = dev->dev_private;
1922 u32 alignment;
1923 int ret;
1924
1925 switch (obj->tiling_mode) {
1926 case I915_TILING_NONE:
1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
1929 else if (INTEL_INFO(dev)->gen >= 4)
1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
1946 dev_priv->mm.interruptible = false;
1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1948 if (ret)
1949 goto err_interruptible;
1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
1956 ret = i915_gem_object_get_fence(obj);
1957 if (ret)
1958 goto err_unpin;
1959
1960 i915_gem_object_pin_fence(obj);
1961
1962 dev_priv->mm.interruptible = true;
1963 return 0;
1964
1965 err_unpin:
1966 i915_gem_object_unpin(obj);
1967 err_interruptible:
1968 dev_priv->mm.interruptible = true;
1969 return ret;
1970 }
1971
1972 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973 {
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976 }
1977
1978 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980 static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983 {
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992 }
1993
1994 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
1996 {
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
2001 struct drm_i915_gem_object *obj;
2002 int plane = intel_crtc->plane;
2003 unsigned long linear_offset;
2004 u32 dspcntr;
2005 u32 reg;
2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
2018
2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2039 return -EINVAL;
2040 }
2041 if (INTEL_INFO(dev)->gen >= 4) {
2042 if (obj->tiling_mode != I915_TILING_NONE)
2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
2048 I915_WRITE(reg, dspcntr);
2049
2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2051
2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
2059 intel_crtc->dspaddr_offset = linear_offset;
2060 }
2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2065 if (INTEL_INFO(dev)->gen >= 4) {
2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
2070 } else
2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2072 POSTING_READ(reg);
2073
2074 return 0;
2075 }
2076
2077 static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079 {
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
2086 unsigned long linear_offset;
2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
2093 case 2:
2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
2147
2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
2155 POSTING_READ(reg);
2156
2157 return 0;
2158 }
2159
2160 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2161 static int
2162 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164 {
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
2167
2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
2170 intel_increase_pllclock(crtc);
2171
2172 return dev_priv->display.update_plane(crtc, fb, x, y);
2173 }
2174
2175 static int
2176 intel_finish_fb(struct drm_framebuffer *old_fb)
2177 {
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200 }
2201
2202 static int
2203 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2204 struct drm_framebuffer *old_fb)
2205 {
2206 struct drm_device *dev = crtc->dev;
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2210 int ret;
2211
2212 /* no fb bound */
2213 if (!crtc->fb) {
2214 DRM_ERROR("No FB bound\n");
2215 return 0;
2216 }
2217
2218 if(intel_crtc->plane > dev_priv->num_pipe) {
2219 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2220 intel_crtc->plane,
2221 dev_priv->num_pipe);
2222 return -EINVAL;
2223 }
2224
2225 mutex_lock(&dev->struct_mutex);
2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
2228 NULL);
2229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
2231 DRM_ERROR("pin & fence failed\n");
2232 return ret;
2233 }
2234
2235 if (old_fb)
2236 intel_finish_fb(old_fb);
2237
2238 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
2239 if (ret) {
2240 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
2241 mutex_unlock(&dev->struct_mutex);
2242 DRM_ERROR("failed to update base address\n");
2243 return ret;
2244 }
2245
2246 if (old_fb) {
2247 intel_wait_for_vblank(dev, intel_crtc->pipe);
2248 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2249 }
2250
2251 intel_update_fbc(dev);
2252 mutex_unlock(&dev->struct_mutex);
2253
2254 if (!dev->primary->master)
2255 return 0;
2256
2257 master_priv = dev->primary->master->driver_priv;
2258 if (!master_priv->sarea_priv)
2259 return 0;
2260
2261 if (intel_crtc->pipe) {
2262 master_priv->sarea_priv->pipeB_x = x;
2263 master_priv->sarea_priv->pipeB_y = y;
2264 } else {
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
2267 }
2268
2269 return 0;
2270 }
2271
2272 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2273 {
2274 struct drm_device *dev = crtc->dev;
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276 u32 dpa_ctl;
2277
2278 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2279 dpa_ctl = I915_READ(DP_A);
2280 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2281
2282 if (clock < 200000) {
2283 u32 temp;
2284 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2285 /* workaround for 160Mhz:
2286 1) program 0x4600c bits 15:0 = 0x8124
2287 2) program 0x46010 bit 0 = 1
2288 3) program 0x46034 bit 24 = 1
2289 4) program 0x64000 bit 14 = 1
2290 */
2291 temp = I915_READ(0x4600c);
2292 temp &= 0xffff0000;
2293 I915_WRITE(0x4600c, temp | 0x8124);
2294
2295 temp = I915_READ(0x46010);
2296 I915_WRITE(0x46010, temp | 1);
2297
2298 temp = I915_READ(0x46034);
2299 I915_WRITE(0x46034, temp | (1 << 24));
2300 } else {
2301 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2302 }
2303 I915_WRITE(DP_A, dpa_ctl);
2304
2305 POSTING_READ(DP_A);
2306 udelay(500);
2307 }
2308
2309 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2310 {
2311 struct drm_device *dev = crtc->dev;
2312 struct drm_i915_private *dev_priv = dev->dev_private;
2313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2314 int pipe = intel_crtc->pipe;
2315 u32 reg, temp;
2316
2317 /* enable normal train */
2318 reg = FDI_TX_CTL(pipe);
2319 temp = I915_READ(reg);
2320 if (IS_IVYBRIDGE(dev)) {
2321 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2322 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2323 } else {
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2326 }
2327 I915_WRITE(reg, temp);
2328
2329 reg = FDI_RX_CTL(pipe);
2330 temp = I915_READ(reg);
2331 if (HAS_PCH_CPT(dev)) {
2332 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2333 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2334 } else {
2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_NONE;
2337 }
2338 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2339
2340 /* wait one idle pattern time */
2341 POSTING_READ(reg);
2342 udelay(1000);
2343
2344 /* IVB wants error correction enabled */
2345 if (IS_IVYBRIDGE(dev))
2346 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2347 FDI_FE_ERRC_ENABLE);
2348 }
2349
2350 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2351 {
2352 struct drm_i915_private *dev_priv = dev->dev_private;
2353 u32 flags = I915_READ(SOUTH_CHICKEN1);
2354
2355 flags |= FDI_PHASE_SYNC_OVR(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2357 flags |= FDI_PHASE_SYNC_EN(pipe);
2358 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2359 POSTING_READ(SOUTH_CHICKEN1);
2360 }
2361
2362 /* The FDI link training functions for ILK/Ibexpeak. */
2363 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2364 {
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 int plane = intel_crtc->plane;
2370 u32 reg, temp, tries;
2371
2372 /* FDI needs bits from pipe & plane first */
2373 assert_pipe_enabled(dev_priv, pipe);
2374 assert_plane_enabled(dev_priv, plane);
2375
2376 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2377 for train result */
2378 reg = FDI_RX_IMR(pipe);
2379 temp = I915_READ(reg);
2380 temp &= ~FDI_RX_SYMBOL_LOCK;
2381 temp &= ~FDI_RX_BIT_LOCK;
2382 I915_WRITE(reg, temp);
2383 I915_READ(reg);
2384 udelay(150);
2385
2386 /* enable CPU FDI TX and PCH FDI RX */
2387 reg = FDI_TX_CTL(pipe);
2388 temp = I915_READ(reg);
2389 temp &= ~(7 << 19);
2390 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2391 temp &= ~FDI_LINK_TRAIN_NONE;
2392 temp |= FDI_LINK_TRAIN_PATTERN_1;
2393 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2394
2395 reg = FDI_RX_CTL(pipe);
2396 temp = I915_READ(reg);
2397 temp &= ~FDI_LINK_TRAIN_NONE;
2398 temp |= FDI_LINK_TRAIN_PATTERN_1;
2399 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2400
2401 POSTING_READ(reg);
2402 udelay(150);
2403
2404 /* Ironlake workaround, enable clock pointer after FDI enable*/
2405 if (HAS_PCH_IBX(dev)) {
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2407 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2408 FDI_RX_PHASE_SYNC_POINTER_EN);
2409 }
2410
2411 reg = FDI_RX_IIR(pipe);
2412 for (tries = 0; tries < 5; tries++) {
2413 temp = I915_READ(reg);
2414 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2415
2416 if ((temp & FDI_RX_BIT_LOCK)) {
2417 DRM_DEBUG_KMS("FDI train 1 done.\n");
2418 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2419 break;
2420 }
2421 }
2422 if (tries == 5)
2423 DRM_ERROR("FDI train 1 fail!\n");
2424
2425 /* Train 2 */
2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
2428 temp &= ~FDI_LINK_TRAIN_NONE;
2429 temp |= FDI_LINK_TRAIN_PATTERN_2;
2430 I915_WRITE(reg, temp);
2431
2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
2434 temp &= ~FDI_LINK_TRAIN_NONE;
2435 temp |= FDI_LINK_TRAIN_PATTERN_2;
2436 I915_WRITE(reg, temp);
2437
2438 POSTING_READ(reg);
2439 udelay(150);
2440
2441 reg = FDI_RX_IIR(pipe);
2442 for (tries = 0; tries < 5; tries++) {
2443 temp = I915_READ(reg);
2444 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2445
2446 if (temp & FDI_RX_SYMBOL_LOCK) {
2447 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2448 DRM_DEBUG_KMS("FDI train 2 done.\n");
2449 break;
2450 }
2451 }
2452 if (tries == 5)
2453 DRM_ERROR("FDI train 2 fail!\n");
2454
2455 DRM_DEBUG_KMS("FDI train done\n");
2456
2457 }
2458
2459 static const int snb_b_fdi_train_param[] = {
2460 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2461 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2462 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2463 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2464 };
2465
2466 /* The FDI link training functions for SNB/Cougarpoint. */
2467 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2468 {
2469 struct drm_device *dev = crtc->dev;
2470 struct drm_i915_private *dev_priv = dev->dev_private;
2471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2472 int pipe = intel_crtc->pipe;
2473 u32 reg, temp, i, retry;
2474
2475 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2476 for train result */
2477 reg = FDI_RX_IMR(pipe);
2478 temp = I915_READ(reg);
2479 temp &= ~FDI_RX_SYMBOL_LOCK;
2480 temp &= ~FDI_RX_BIT_LOCK;
2481 I915_WRITE(reg, temp);
2482
2483 POSTING_READ(reg);
2484 udelay(150);
2485
2486 /* enable CPU FDI TX and PCH FDI RX */
2487 reg = FDI_TX_CTL(pipe);
2488 temp = I915_READ(reg);
2489 temp &= ~(7 << 19);
2490 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_1;
2493 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2494 /* SNB-B */
2495 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2496 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2497
2498 reg = FDI_RX_CTL(pipe);
2499 temp = I915_READ(reg);
2500 if (HAS_PCH_CPT(dev)) {
2501 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2502 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2503 } else {
2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_1;
2506 }
2507 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2508
2509 POSTING_READ(reg);
2510 udelay(150);
2511
2512 if (HAS_PCH_CPT(dev))
2513 cpt_phase_pointer_enable(dev, pipe);
2514
2515 for (i = 0; i < 4; i++) {
2516 reg = FDI_TX_CTL(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2519 temp |= snb_b_fdi_train_param[i];
2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
2523 udelay(500);
2524
2525 for (retry = 0; retry < 5; retry++) {
2526 reg = FDI_RX_IIR(pipe);
2527 temp = I915_READ(reg);
2528 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2529 if (temp & FDI_RX_BIT_LOCK) {
2530 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2531 DRM_DEBUG_KMS("FDI train 1 done.\n");
2532 break;
2533 }
2534 udelay(50);
2535 }
2536 if (retry < 5)
2537 break;
2538 }
2539 if (i == 4)
2540 DRM_ERROR("FDI train 1 fail!\n");
2541
2542 /* Train 2 */
2543 reg = FDI_TX_CTL(pipe);
2544 temp = I915_READ(reg);
2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_2;
2547 if (IS_GEN6(dev)) {
2548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2549 /* SNB-B */
2550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2551 }
2552 I915_WRITE(reg, temp);
2553
2554 reg = FDI_RX_CTL(pipe);
2555 temp = I915_READ(reg);
2556 if (HAS_PCH_CPT(dev)) {
2557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2558 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2559 } else {
2560 temp &= ~FDI_LINK_TRAIN_NONE;
2561 temp |= FDI_LINK_TRAIN_PATTERN_2;
2562 }
2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
2566 udelay(150);
2567
2568 for (i = 0; i < 4; i++) {
2569 reg = FDI_TX_CTL(pipe);
2570 temp = I915_READ(reg);
2571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2572 temp |= snb_b_fdi_train_param[i];
2573 I915_WRITE(reg, temp);
2574
2575 POSTING_READ(reg);
2576 udelay(500);
2577
2578 for (retry = 0; retry < 5; retry++) {
2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2585 break;
2586 }
2587 udelay(50);
2588 }
2589 if (retry < 5)
2590 break;
2591 }
2592 if (i == 4)
2593 DRM_ERROR("FDI train 2 fail!\n");
2594
2595 DRM_DEBUG_KMS("FDI train done.\n");
2596 }
2597
2598 /* Manual link training for Ivy Bridge A0 parts */
2599 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2600 {
2601 struct drm_device *dev = crtc->dev;
2602 struct drm_i915_private *dev_priv = dev->dev_private;
2603 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2604 int pipe = intel_crtc->pipe;
2605 u32 reg, temp, i;
2606
2607 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2608 for train result */
2609 reg = FDI_RX_IMR(pipe);
2610 temp = I915_READ(reg);
2611 temp &= ~FDI_RX_SYMBOL_LOCK;
2612 temp &= ~FDI_RX_BIT_LOCK;
2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 /* enable CPU FDI TX and PCH FDI RX */
2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~(7 << 19);
2622 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2623 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2624 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2627 temp |= FDI_COMPOSITE_SYNC;
2628 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2629
2630 reg = FDI_RX_CTL(pipe);
2631 temp = I915_READ(reg);
2632 temp &= ~FDI_LINK_TRAIN_AUTO;
2633 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2634 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2635 temp |= FDI_COMPOSITE_SYNC;
2636 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2637
2638 POSTING_READ(reg);
2639 udelay(150);
2640
2641 if (HAS_PCH_CPT(dev))
2642 cpt_phase_pointer_enable(dev, pipe);
2643
2644 for (i = 0; i < 4; i++) {
2645 reg = FDI_TX_CTL(pipe);
2646 temp = I915_READ(reg);
2647 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2648 temp |= snb_b_fdi_train_param[i];
2649 I915_WRITE(reg, temp);
2650
2651 POSTING_READ(reg);
2652 udelay(500);
2653
2654 reg = FDI_RX_IIR(pipe);
2655 temp = I915_READ(reg);
2656 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2657
2658 if (temp & FDI_RX_BIT_LOCK ||
2659 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2660 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2662 break;
2663 }
2664 }
2665 if (i == 4)
2666 DRM_ERROR("FDI train 1 fail!\n");
2667
2668 /* Train 2 */
2669 reg = FDI_TX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2672 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2673 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 I915_WRITE(reg, temp);
2676
2677 reg = FDI_RX_CTL(pipe);
2678 temp = I915_READ(reg);
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2681 I915_WRITE(reg, temp);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
2686 for (i = 0; i < 4; i++) {
2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_SYMBOL_LOCK) {
2701 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2702 DRM_DEBUG_KMS("FDI train 2 done.\n");
2703 break;
2704 }
2705 }
2706 if (i == 4)
2707 DRM_ERROR("FDI train 2 fail!\n");
2708
2709 DRM_DEBUG_KMS("FDI train done.\n");
2710 }
2711
2712 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2713 {
2714 struct drm_device *dev = intel_crtc->base.dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 int pipe = intel_crtc->pipe;
2717 u32 reg, temp;
2718
2719 /* Write the TU size bits so error detection works */
2720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2722
2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
2727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
2732 udelay(200);
2733
2734 /* Switch from Rawclk to PCDclk */
2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738 POSTING_READ(reg);
2739 udelay(200);
2740
2741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2749
2750 POSTING_READ(reg);
2751 udelay(100);
2752 }
2753 }
2754 }
2755
2756 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2757 {
2758 struct drm_device *dev = intel_crtc->base.dev;
2759 struct drm_i915_private *dev_priv = dev->dev_private;
2760 int pipe = intel_crtc->pipe;
2761 u32 reg, temp;
2762
2763 /* Switch from PCDclk to Rawclk */
2764 reg = FDI_RX_CTL(pipe);
2765 temp = I915_READ(reg);
2766 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2767
2768 /* Disable CPU FDI TX PLL */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2772
2773 POSTING_READ(reg);
2774 udelay(100);
2775
2776 reg = FDI_RX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2779
2780 /* Wait for the clocks to turn off. */
2781 POSTING_READ(reg);
2782 udelay(100);
2783 }
2784
2785 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2786 {
2787 struct drm_i915_private *dev_priv = dev->dev_private;
2788 u32 flags = I915_READ(SOUTH_CHICKEN1);
2789
2790 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2791 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2792 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2793 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2794 POSTING_READ(SOUTH_CHICKEN1);
2795 }
2796 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2797 {
2798 struct drm_device *dev = crtc->dev;
2799 struct drm_i915_private *dev_priv = dev->dev_private;
2800 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2801 int pipe = intel_crtc->pipe;
2802 u32 reg, temp;
2803
2804 /* disable CPU FDI tx and PCH FDI rx */
2805 reg = FDI_TX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2808 POSTING_READ(reg);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~(0x7 << 16);
2813 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2814 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2815
2816 POSTING_READ(reg);
2817 udelay(100);
2818
2819 /* Ironlake workaround, disable clock pointer after downing FDI */
2820 if (HAS_PCH_IBX(dev)) {
2821 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2822 I915_WRITE(FDI_RX_CHICKEN(pipe),
2823 I915_READ(FDI_RX_CHICKEN(pipe) &
2824 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2825 } else if (HAS_PCH_CPT(dev)) {
2826 cpt_phase_pointer_disable(dev, pipe);
2827 }
2828
2829 /* still set train pattern 1 */
2830 reg = FDI_TX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 if (HAS_PCH_CPT(dev)) {
2839 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2840 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2841 } else {
2842 temp &= ~FDI_LINK_TRAIN_NONE;
2843 temp |= FDI_LINK_TRAIN_PATTERN_1;
2844 }
2845 /* BPC in FDI rx is consistent with that in PIPECONF */
2846 temp &= ~(0x07 << 16);
2847 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2848 I915_WRITE(reg, temp);
2849
2850 POSTING_READ(reg);
2851 udelay(100);
2852 }
2853
2854 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2855 {
2856 struct drm_device *dev = crtc->dev;
2857
2858 if (crtc->fb == NULL)
2859 return;
2860
2861 mutex_lock(&dev->struct_mutex);
2862 intel_finish_fb(crtc->fb);
2863 mutex_unlock(&dev->struct_mutex);
2864 }
2865
2866 static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2867 {
2868 struct drm_device *dev = crtc->dev;
2869 struct intel_encoder *intel_encoder;
2870
2871 /*
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2874 */
2875 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2876
2877 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2878 * CPU handles all others */
2879 if (IS_HASWELL(dev)) {
2880 /* It is still unclear how this will work on PPT, so throw up a warning */
2881 WARN_ON(!HAS_PCH_LPT(dev));
2882
2883 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
2884 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2885 return true;
2886 } else {
2887 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2888 intel_encoder->type);
2889 return false;
2890 }
2891 }
2892
2893 switch (intel_encoder->type) {
2894 case INTEL_OUTPUT_EDP:
2895 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2896 return false;
2897 continue;
2898 }
2899 }
2900
2901 return true;
2902 }
2903
2904 /* Program iCLKIP clock to the desired frequency */
2905 static void lpt_program_iclkip(struct drm_crtc *crtc)
2906 {
2907 struct drm_device *dev = crtc->dev;
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2910 u32 temp;
2911
2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2919 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2920 SBI_SSCCTL_DISABLE);
2921
2922 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2923 if (crtc->mode.clock == 20000) {
2924 auxdiv = 1;
2925 divsel = 0x41;
2926 phaseinc = 0x20;
2927 } else {
2928 /* The iCLK virtual clock root frequency is in MHz,
2929 * but the crtc->mode.clock in in KHz. To get the divisors,
2930 * it is necessary to divide one by another, so we
2931 * convert the virtual clock precision to KHz here for higher
2932 * precision.
2933 */
2934 u32 iclk_virtual_root_freq = 172800 * 1000;
2935 u32 iclk_pi_range = 64;
2936 u32 desired_divisor, msb_divisor_value, pi_value;
2937
2938 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2939 msb_divisor_value = desired_divisor / iclk_pi_range;
2940 pi_value = desired_divisor % iclk_pi_range;
2941
2942 auxdiv = 0;
2943 divsel = msb_divisor_value - 2;
2944 phaseinc = pi_value;
2945 }
2946
2947 /* This should not happen with any sane values */
2948 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2949 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2950 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2951 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2952
2953 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2954 crtc->mode.clock,
2955 auxdiv,
2956 divsel,
2957 phasedir,
2958 phaseinc);
2959
2960 /* Program SSCDIVINTPHASE6 */
2961 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2962 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2963 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2964 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2965 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2966 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2967 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2968
2969 intel_sbi_write(dev_priv,
2970 SBI_SSCDIVINTPHASE6,
2971 temp);
2972
2973 /* Program SSCAUXDIV */
2974 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2975 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2976 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2977 intel_sbi_write(dev_priv,
2978 SBI_SSCAUXDIV6,
2979 temp);
2980
2981
2982 /* Enable modulator and associated divider */
2983 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2984 temp &= ~SBI_SSCCTL_DISABLE;
2985 intel_sbi_write(dev_priv,
2986 SBI_SSCCTL6,
2987 temp);
2988
2989 /* Wait for initialization time */
2990 udelay(24);
2991
2992 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2993 }
2994
2995 /*
2996 * Enable PCH resources required for PCH ports:
2997 * - PCH PLLs
2998 * - FDI training & RX/TX
2999 * - update transcoder timings
3000 * - DP transcoding bits
3001 * - transcoder
3002 */
3003 static void ironlake_pch_enable(struct drm_crtc *crtc)
3004 {
3005 struct drm_device *dev = crtc->dev;
3006 struct drm_i915_private *dev_priv = dev->dev_private;
3007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3008 int pipe = intel_crtc->pipe;
3009 u32 reg, temp;
3010
3011 assert_transcoder_disabled(dev_priv, pipe);
3012
3013 /* For PCH output, training FDI link */
3014 dev_priv->display.fdi_link_train(crtc);
3015
3016 intel_enable_pch_pll(intel_crtc);
3017
3018 if (HAS_PCH_LPT(dev)) {
3019 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3020 lpt_program_iclkip(crtc);
3021 } else if (HAS_PCH_CPT(dev)) {
3022 u32 sel;
3023
3024 temp = I915_READ(PCH_DPLL_SEL);
3025 switch (pipe) {
3026 default:
3027 case 0:
3028 temp |= TRANSA_DPLL_ENABLE;
3029 sel = TRANSA_DPLLB_SEL;
3030 break;
3031 case 1:
3032 temp |= TRANSB_DPLL_ENABLE;
3033 sel = TRANSB_DPLLB_SEL;
3034 break;
3035 case 2:
3036 temp |= TRANSC_DPLL_ENABLE;
3037 sel = TRANSC_DPLLB_SEL;
3038 break;
3039 }
3040 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3041 temp |= sel;
3042 else
3043 temp &= ~sel;
3044 I915_WRITE(PCH_DPLL_SEL, temp);
3045 }
3046
3047 /* set transcoder timing, panel must allow it */
3048 assert_panel_unlocked(dev_priv, pipe);
3049 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3050 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3051 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3052
3053 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3054 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3055 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3056 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3057
3058 if (!IS_HASWELL(dev))
3059 intel_fdi_normal_train(crtc);
3060
3061 /* For PCH DP, enable TRANS_DP_CTL */
3062 if (HAS_PCH_CPT(dev) &&
3063 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3064 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3065 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3066 reg = TRANS_DP_CTL(pipe);
3067 temp = I915_READ(reg);
3068 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3069 TRANS_DP_SYNC_MASK |
3070 TRANS_DP_BPC_MASK);
3071 temp |= (TRANS_DP_OUTPUT_ENABLE |
3072 TRANS_DP_ENH_FRAMING);
3073 temp |= bpc << 9; /* same format but at 11:9 */
3074
3075 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3076 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3077 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3078 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3079
3080 switch (intel_trans_dp_port_sel(crtc)) {
3081 case PCH_DP_B:
3082 temp |= TRANS_DP_PORT_SEL_B;
3083 break;
3084 case PCH_DP_C:
3085 temp |= TRANS_DP_PORT_SEL_C;
3086 break;
3087 case PCH_DP_D:
3088 temp |= TRANS_DP_PORT_SEL_D;
3089 break;
3090 default:
3091 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3092 temp |= TRANS_DP_PORT_SEL_B;
3093 break;
3094 }
3095
3096 I915_WRITE(reg, temp);
3097 }
3098
3099 intel_enable_transcoder(dev_priv, pipe);
3100 }
3101
3102 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3103 {
3104 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3105
3106 if (pll == NULL)
3107 return;
3108
3109 if (pll->refcount == 0) {
3110 WARN(1, "bad PCH PLL refcount\n");
3111 return;
3112 }
3113
3114 --pll->refcount;
3115 intel_crtc->pch_pll = NULL;
3116 }
3117
3118 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3119 {
3120 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3121 struct intel_pch_pll *pll;
3122 int i;
3123
3124 pll = intel_crtc->pch_pll;
3125 if (pll) {
3126 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3127 intel_crtc->base.base.id, pll->pll_reg);
3128 goto prepare;
3129 }
3130
3131 if (HAS_PCH_IBX(dev_priv->dev)) {
3132 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3133 i = intel_crtc->pipe;
3134 pll = &dev_priv->pch_plls[i];
3135
3136 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138
3139 goto found;
3140 }
3141
3142 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3143 pll = &dev_priv->pch_plls[i];
3144
3145 /* Only want to check enabled timings first */
3146 if (pll->refcount == 0)
3147 continue;
3148
3149 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3150 fp == I915_READ(pll->fp0_reg)) {
3151 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3152 intel_crtc->base.base.id,
3153 pll->pll_reg, pll->refcount, pll->active);
3154
3155 goto found;
3156 }
3157 }
3158
3159 /* Ok no matching timings, maybe there's a free one? */
3160 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3161 pll = &dev_priv->pch_plls[i];
3162 if (pll->refcount == 0) {
3163 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3164 intel_crtc->base.base.id, pll->pll_reg);
3165 goto found;
3166 }
3167 }
3168
3169 return NULL;
3170
3171 found:
3172 intel_crtc->pch_pll = pll;
3173 pll->refcount++;
3174 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3175 prepare: /* separate function? */
3176 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3177
3178 /* Wait for the clocks to stabilize before rewriting the regs */
3179 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3180 POSTING_READ(pll->pll_reg);
3181 udelay(150);
3182
3183 I915_WRITE(pll->fp0_reg, fp);
3184 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3185 pll->on = false;
3186 return pll;
3187 }
3188
3189 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3190 {
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3193 u32 temp;
3194
3195 temp = I915_READ(dslreg);
3196 udelay(500);
3197 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3198 /* Without this, mode sets may fail silently on FDI */
3199 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3200 udelay(250);
3201 I915_WRITE(tc2reg, 0);
3202 if (wait_for(I915_READ(dslreg) != temp, 5))
3203 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3204 }
3205 }
3206
3207 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3208 {
3209 struct drm_device *dev = crtc->dev;
3210 struct drm_i915_private *dev_priv = dev->dev_private;
3211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3212 struct intel_encoder *encoder;
3213 int pipe = intel_crtc->pipe;
3214 int plane = intel_crtc->plane;
3215 u32 temp;
3216 bool is_pch_port;
3217
3218 /* XXX: For compatability with the crtc helper code, call the encoder's
3219 * enable function unconditionally for now. */
3220 if (intel_crtc->active)
3221 goto encoders;
3222
3223 intel_crtc->active = true;
3224 intel_update_watermarks(dev);
3225
3226 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3227 temp = I915_READ(PCH_LVDS);
3228 if ((temp & LVDS_PORT_EN) == 0)
3229 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3230 }
3231
3232 is_pch_port = intel_crtc_driving_pch(crtc);
3233
3234 if (is_pch_port)
3235 ironlake_fdi_pll_enable(intel_crtc);
3236 else
3237 ironlake_fdi_disable(crtc);
3238
3239 /* Enable panel fitting for LVDS */
3240 if (dev_priv->pch_pf_size &&
3241 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3242 /* Force use of hard-coded filter coefficients
3243 * as some pre-programmed values are broken,
3244 * e.g. x201.
3245 */
3246 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3247 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3248 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3249 }
3250
3251 /*
3252 * On ILK+ LUT must be loaded before the pipe is running but with
3253 * clocks enabled
3254 */
3255 intel_crtc_load_lut(crtc);
3256
3257 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3258 intel_enable_plane(dev_priv, plane, pipe);
3259
3260 if (is_pch_port)
3261 ironlake_pch_enable(crtc);
3262
3263 mutex_lock(&dev->struct_mutex);
3264 intel_update_fbc(dev);
3265 mutex_unlock(&dev->struct_mutex);
3266
3267 intel_crtc_update_cursor(crtc, true);
3268
3269 encoders:
3270 for_each_encoder_on_crtc(dev, crtc, encoder) {
3271 if (encoder->enable)
3272 encoder->enable(encoder);
3273 }
3274 }
3275
3276 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3277 {
3278 struct drm_device *dev = crtc->dev;
3279 struct drm_i915_private *dev_priv = dev->dev_private;
3280 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3281 struct intel_encoder *encoder;
3282 int pipe = intel_crtc->pipe;
3283 int plane = intel_crtc->plane;
3284 u32 reg, temp;
3285
3286 /* XXX: For compatability with the crtc helper code, call the encoder's
3287 * disable function unconditionally for now. */
3288 for_each_encoder_on_crtc(dev, crtc, encoder) {
3289 if (encoder->disable)
3290 encoder->disable(encoder);
3291 }
3292
3293 if (!intel_crtc->active)
3294 return;
3295
3296 intel_crtc_wait_for_pending_flips(crtc);
3297 drm_vblank_off(dev, pipe);
3298 intel_crtc_update_cursor(crtc, false);
3299
3300 intel_disable_plane(dev_priv, plane, pipe);
3301
3302 if (dev_priv->cfb_plane == plane)
3303 intel_disable_fbc(dev);
3304
3305 intel_disable_pipe(dev_priv, pipe);
3306
3307 /* Disable PF */
3308 I915_WRITE(PF_CTL(pipe), 0);
3309 I915_WRITE(PF_WIN_SZ(pipe), 0);
3310
3311 ironlake_fdi_disable(crtc);
3312
3313 /* This is a horrible layering violation; we should be doing this in
3314 * the connector/encoder ->prepare instead, but we don't always have
3315 * enough information there about the config to know whether it will
3316 * actually be necessary or just cause undesired flicker.
3317 */
3318 intel_disable_pch_ports(dev_priv, pipe);
3319
3320 intel_disable_transcoder(dev_priv, pipe);
3321
3322 if (HAS_PCH_CPT(dev)) {
3323 /* disable TRANS_DP_CTL */
3324 reg = TRANS_DP_CTL(pipe);
3325 temp = I915_READ(reg);
3326 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3327 temp |= TRANS_DP_PORT_SEL_NONE;
3328 I915_WRITE(reg, temp);
3329
3330 /* disable DPLL_SEL */
3331 temp = I915_READ(PCH_DPLL_SEL);
3332 switch (pipe) {
3333 case 0:
3334 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3335 break;
3336 case 1:
3337 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3338 break;
3339 case 2:
3340 /* C shares PLL A or B */
3341 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3342 break;
3343 default:
3344 BUG(); /* wtf */
3345 }
3346 I915_WRITE(PCH_DPLL_SEL, temp);
3347 }
3348
3349 /* disable PCH DPLL */
3350 intel_disable_pch_pll(intel_crtc);
3351
3352 ironlake_fdi_pll_disable(intel_crtc);
3353
3354 intel_crtc->active = false;
3355 intel_update_watermarks(dev);
3356
3357 mutex_lock(&dev->struct_mutex);
3358 intel_update_fbc(dev);
3359 mutex_unlock(&dev->struct_mutex);
3360 }
3361
3362 static void ironlake_crtc_off(struct drm_crtc *crtc)
3363 {
3364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3365 intel_put_pch_pll(intel_crtc);
3366 }
3367
3368 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3369 {
3370 if (!enable && intel_crtc->overlay) {
3371 struct drm_device *dev = intel_crtc->base.dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373
3374 mutex_lock(&dev->struct_mutex);
3375 dev_priv->mm.interruptible = false;
3376 (void) intel_overlay_switch_off(intel_crtc->overlay);
3377 dev_priv->mm.interruptible = true;
3378 mutex_unlock(&dev->struct_mutex);
3379 }
3380
3381 /* Let userspace switch the overlay on again. In most cases userspace
3382 * has to recompute where to put it anyway.
3383 */
3384 }
3385
3386 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3387 {
3388 struct drm_device *dev = crtc->dev;
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3391 struct intel_encoder *encoder;
3392 int pipe = intel_crtc->pipe;
3393 int plane = intel_crtc->plane;
3394
3395 /* XXX: For compatability with the crtc helper code, call the encoder's
3396 * enable function unconditionally for now. */
3397 if (intel_crtc->active)
3398 goto encoders;
3399
3400 intel_crtc->active = true;
3401 intel_update_watermarks(dev);
3402
3403 intel_enable_pll(dev_priv, pipe);
3404 intel_enable_pipe(dev_priv, pipe, false);
3405 intel_enable_plane(dev_priv, plane, pipe);
3406
3407 intel_crtc_load_lut(crtc);
3408 intel_update_fbc(dev);
3409
3410 /* Give the overlay scaler a chance to enable if it's on this pipe */
3411 intel_crtc_dpms_overlay(intel_crtc, true);
3412 intel_crtc_update_cursor(crtc, true);
3413
3414 encoders:
3415 for_each_encoder_on_crtc(dev, crtc, encoder) {
3416 if (encoder->enable)
3417 encoder->enable(encoder);
3418 }
3419 }
3420
3421 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3422 {
3423 struct drm_device *dev = crtc->dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3426 struct intel_encoder *encoder;
3427 int pipe = intel_crtc->pipe;
3428 int plane = intel_crtc->plane;
3429
3430 /* XXX: For compatability with the crtc helper code, call the encoder's
3431 * disable function unconditionally for now. */
3432 for_each_encoder_on_crtc(dev, crtc, encoder) {
3433 if (encoder->disable)
3434 encoder->disable(encoder);
3435 }
3436
3437 if (!intel_crtc->active)
3438 return;
3439
3440 /* Give the overlay scaler a chance to disable if it's on this pipe */
3441 intel_crtc_wait_for_pending_flips(crtc);
3442 drm_vblank_off(dev, pipe);
3443 intel_crtc_dpms_overlay(intel_crtc, false);
3444 intel_crtc_update_cursor(crtc, false);
3445
3446 if (dev_priv->cfb_plane == plane)
3447 intel_disable_fbc(dev);
3448
3449 intel_disable_plane(dev_priv, plane, pipe);
3450 intel_disable_pipe(dev_priv, pipe);
3451 intel_disable_pll(dev_priv, pipe);
3452
3453 intel_crtc->active = false;
3454 intel_update_fbc(dev);
3455 intel_update_watermarks(dev);
3456 }
3457
3458 static void i9xx_crtc_off(struct drm_crtc *crtc)
3459 {
3460 }
3461
3462 /**
3463 * Sets the power management mode of the pipe and plane.
3464 */
3465 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3466 {
3467 struct drm_device *dev = crtc->dev;
3468 struct drm_i915_private *dev_priv = dev->dev_private;
3469 struct drm_i915_master_private *master_priv;
3470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3471 int pipe = intel_crtc->pipe;
3472 bool enabled;
3473
3474 if (intel_crtc->dpms_mode == mode)
3475 return;
3476
3477 intel_crtc->dpms_mode = mode;
3478
3479 /* XXX: When our outputs are all unaware of DPMS modes other than off
3480 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3481 */
3482 switch (mode) {
3483 case DRM_MODE_DPMS_ON:
3484 case DRM_MODE_DPMS_STANDBY:
3485 case DRM_MODE_DPMS_SUSPEND:
3486 dev_priv->display.crtc_enable(crtc);
3487 break;
3488
3489 case DRM_MODE_DPMS_OFF:
3490 dev_priv->display.crtc_disable(crtc);
3491 break;
3492 }
3493
3494 if (!dev->primary->master)
3495 return;
3496
3497 master_priv = dev->primary->master->driver_priv;
3498 if (!master_priv->sarea_priv)
3499 return;
3500
3501 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3502
3503 switch (pipe) {
3504 case 0:
3505 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3506 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3507 break;
3508 case 1:
3509 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3510 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3511 break;
3512 default:
3513 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3514 break;
3515 }
3516 }
3517
3518 static void intel_crtc_disable(struct drm_crtc *crtc)
3519 {
3520 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3521 struct drm_device *dev = crtc->dev;
3522 struct drm_i915_private *dev_priv = dev->dev_private;
3523
3524 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3525 dev_priv->display.off(crtc);
3526
3527 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3528 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3529
3530 if (crtc->fb) {
3531 mutex_lock(&dev->struct_mutex);
3532 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3533 mutex_unlock(&dev->struct_mutex);
3534 }
3535 }
3536
3537 void intel_encoder_prepare(struct drm_encoder *encoder)
3538 {
3539 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3540 /* lvds has its own version of prepare see intel_lvds_prepare */
3541 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3542 }
3543
3544 void intel_encoder_commit(struct drm_encoder *encoder)
3545 {
3546 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3547 struct drm_device *dev = encoder->dev;
3548 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
3549
3550 /* lvds has its own version of commit see intel_lvds_commit */
3551 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3552
3553 if (HAS_PCH_CPT(dev))
3554 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3555 }
3556
3557 void intel_encoder_noop(struct drm_encoder *encoder)
3558 {
3559 }
3560
3561 void intel_encoder_disable(struct drm_encoder *encoder)
3562 {
3563 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3564
3565 intel_encoder->disable(intel_encoder);
3566 }
3567
3568 void intel_encoder_destroy(struct drm_encoder *encoder)
3569 {
3570 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3571
3572 drm_encoder_cleanup(encoder);
3573 kfree(intel_encoder);
3574 }
3575
3576 /* Simple dpms helper for encodres with just one connector, no cloning and only
3577 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3578 * state of the entire output pipe. */
3579 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3580 {
3581 if (mode == DRM_MODE_DPMS_ON) {
3582 encoder->connectors_active = true;
3583
3584 intel_crtc_dpms(encoder->base.crtc, DRM_MODE_DPMS_ON);
3585 } else {
3586 encoder->connectors_active = false;
3587
3588 intel_crtc_dpms(encoder->base.crtc, DRM_MODE_DPMS_OFF);
3589 }
3590 }
3591
3592 /* Even simpler default implementation, if there's really no special case to
3593 * consider. */
3594 void intel_connector_dpms(struct drm_connector *connector, int mode)
3595 {
3596 struct intel_encoder *encoder = intel_attached_encoder(connector);
3597
3598 /* All the simple cases only support two dpms states. */
3599 if (mode != DRM_MODE_DPMS_ON)
3600 mode = DRM_MODE_DPMS_OFF;
3601
3602 if (mode == connector->dpms)
3603 return;
3604
3605 connector->dpms = mode;
3606
3607 /* Only need to change hw state when actually enabled */
3608 if (encoder->base.crtc)
3609 intel_encoder_dpms(encoder, mode);
3610 else
3611 encoder->connectors_active = false;
3612 }
3613
3614 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3615 const struct drm_display_mode *mode,
3616 struct drm_display_mode *adjusted_mode)
3617 {
3618 struct drm_device *dev = crtc->dev;
3619
3620 if (HAS_PCH_SPLIT(dev)) {
3621 /* FDI link clock is fixed at 2.7G */
3622 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3623 return false;
3624 }
3625
3626 /* All interlaced capable intel hw wants timings in frames. Note though
3627 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3628 * timings, so we need to be careful not to clobber these.*/
3629 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3630 drm_mode_set_crtcinfo(adjusted_mode, 0);
3631
3632 return true;
3633 }
3634
3635 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3636 {
3637 return 400000; /* FIXME */
3638 }
3639
3640 static int i945_get_display_clock_speed(struct drm_device *dev)
3641 {
3642 return 400000;
3643 }
3644
3645 static int i915_get_display_clock_speed(struct drm_device *dev)
3646 {
3647 return 333000;
3648 }
3649
3650 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3651 {
3652 return 200000;
3653 }
3654
3655 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3656 {
3657 u16 gcfgc = 0;
3658
3659 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3660
3661 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3662 return 133000;
3663 else {
3664 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3665 case GC_DISPLAY_CLOCK_333_MHZ:
3666 return 333000;
3667 default:
3668 case GC_DISPLAY_CLOCK_190_200_MHZ:
3669 return 190000;
3670 }
3671 }
3672 }
3673
3674 static int i865_get_display_clock_speed(struct drm_device *dev)
3675 {
3676 return 266000;
3677 }
3678
3679 static int i855_get_display_clock_speed(struct drm_device *dev)
3680 {
3681 u16 hpllcc = 0;
3682 /* Assume that the hardware is in the high speed state. This
3683 * should be the default.
3684 */
3685 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3686 case GC_CLOCK_133_200:
3687 case GC_CLOCK_100_200:
3688 return 200000;
3689 case GC_CLOCK_166_250:
3690 return 250000;
3691 case GC_CLOCK_100_133:
3692 return 133000;
3693 }
3694
3695 /* Shouldn't happen */
3696 return 0;
3697 }
3698
3699 static int i830_get_display_clock_speed(struct drm_device *dev)
3700 {
3701 return 133000;
3702 }
3703
3704 struct fdi_m_n {
3705 u32 tu;
3706 u32 gmch_m;
3707 u32 gmch_n;
3708 u32 link_m;
3709 u32 link_n;
3710 };
3711
3712 static void
3713 fdi_reduce_ratio(u32 *num, u32 *den)
3714 {
3715 while (*num > 0xffffff || *den > 0xffffff) {
3716 *num >>= 1;
3717 *den >>= 1;
3718 }
3719 }
3720
3721 static void
3722 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3723 int link_clock, struct fdi_m_n *m_n)
3724 {
3725 m_n->tu = 64; /* default size */
3726
3727 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3728 m_n->gmch_m = bits_per_pixel * pixel_clock;
3729 m_n->gmch_n = link_clock * nlanes * 8;
3730 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3731
3732 m_n->link_m = pixel_clock;
3733 m_n->link_n = link_clock;
3734 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3735 }
3736
3737 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3738 {
3739 if (i915_panel_use_ssc >= 0)
3740 return i915_panel_use_ssc != 0;
3741 return dev_priv->lvds_use_ssc
3742 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
3743 }
3744
3745 /**
3746 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3747 * @crtc: CRTC structure
3748 * @mode: requested mode
3749 *
3750 * A pipe may be connected to one or more outputs. Based on the depth of the
3751 * attached framebuffer, choose a good color depth to use on the pipe.
3752 *
3753 * If possible, match the pipe depth to the fb depth. In some cases, this
3754 * isn't ideal, because the connected output supports a lesser or restricted
3755 * set of depths. Resolve that here:
3756 * LVDS typically supports only 6bpc, so clamp down in that case
3757 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3758 * Displays may support a restricted set as well, check EDID and clamp as
3759 * appropriate.
3760 * DP may want to dither down to 6bpc to fit larger modes
3761 *
3762 * RETURNS:
3763 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3764 * true if they don't match).
3765 */
3766 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3767 unsigned int *pipe_bpp,
3768 struct drm_display_mode *mode)
3769 {
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct drm_connector *connector;
3773 struct intel_encoder *intel_encoder;
3774 unsigned int display_bpc = UINT_MAX, bpc;
3775
3776 /* Walk the encoders & connectors on this crtc, get min bpc */
3777 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3778
3779 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3780 unsigned int lvds_bpc;
3781
3782 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3783 LVDS_A3_POWER_UP)
3784 lvds_bpc = 8;
3785 else
3786 lvds_bpc = 6;
3787
3788 if (lvds_bpc < display_bpc) {
3789 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
3790 display_bpc = lvds_bpc;
3791 }
3792 continue;
3793 }
3794
3795 /* Not one of the known troublemakers, check the EDID */
3796 list_for_each_entry(connector, &dev->mode_config.connector_list,
3797 head) {
3798 if (connector->encoder != &intel_encoder->base)
3799 continue;
3800
3801 /* Don't use an invalid EDID bpc value */
3802 if (connector->display_info.bpc &&
3803 connector->display_info.bpc < display_bpc) {
3804 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
3805 display_bpc = connector->display_info.bpc;
3806 }
3807 }
3808
3809 /*
3810 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3811 * through, clamp it down. (Note: >12bpc will be caught below.)
3812 */
3813 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3814 if (display_bpc > 8 && display_bpc < 12) {
3815 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3816 display_bpc = 12;
3817 } else {
3818 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3819 display_bpc = 8;
3820 }
3821 }
3822 }
3823
3824 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3825 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3826 display_bpc = 6;
3827 }
3828
3829 /*
3830 * We could just drive the pipe at the highest bpc all the time and
3831 * enable dithering as needed, but that costs bandwidth. So choose
3832 * the minimum value that expresses the full color range of the fb but
3833 * also stays within the max display bpc discovered above.
3834 */
3835
3836 switch (crtc->fb->depth) {
3837 case 8:
3838 bpc = 8; /* since we go through a colormap */
3839 break;
3840 case 15:
3841 case 16:
3842 bpc = 6; /* min is 18bpp */
3843 break;
3844 case 24:
3845 bpc = 8;
3846 break;
3847 case 30:
3848 bpc = 10;
3849 break;
3850 case 48:
3851 bpc = 12;
3852 break;
3853 default:
3854 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3855 bpc = min((unsigned int)8, display_bpc);
3856 break;
3857 }
3858
3859 display_bpc = min(display_bpc, bpc);
3860
3861 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3862 bpc, display_bpc);
3863
3864 *pipe_bpp = display_bpc * 3;
3865
3866 return display_bpc != bpc;
3867 }
3868
3869 static int vlv_get_refclk(struct drm_crtc *crtc)
3870 {
3871 struct drm_device *dev = crtc->dev;
3872 struct drm_i915_private *dev_priv = dev->dev_private;
3873 int refclk = 27000; /* for DP & HDMI */
3874
3875 return 100000; /* only one validated so far */
3876
3877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3878 refclk = 96000;
3879 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3880 if (intel_panel_use_ssc(dev_priv))
3881 refclk = 100000;
3882 else
3883 refclk = 96000;
3884 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3885 refclk = 100000;
3886 }
3887
3888 return refclk;
3889 }
3890
3891 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3892 {
3893 struct drm_device *dev = crtc->dev;
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895 int refclk;
3896
3897 if (IS_VALLEYVIEW(dev)) {
3898 refclk = vlv_get_refclk(crtc);
3899 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3900 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3901 refclk = dev_priv->lvds_ssc_freq * 1000;
3902 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3903 refclk / 1000);
3904 } else if (!IS_GEN2(dev)) {
3905 refclk = 96000;
3906 } else {
3907 refclk = 48000;
3908 }
3909
3910 return refclk;
3911 }
3912
3913 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3914 intel_clock_t *clock)
3915 {
3916 /* SDVO TV has fixed PLL values depend on its clock range,
3917 this mirrors vbios setting. */
3918 if (adjusted_mode->clock >= 100000
3919 && adjusted_mode->clock < 140500) {
3920 clock->p1 = 2;
3921 clock->p2 = 10;
3922 clock->n = 3;
3923 clock->m1 = 16;
3924 clock->m2 = 8;
3925 } else if (adjusted_mode->clock >= 140500
3926 && adjusted_mode->clock <= 200000) {
3927 clock->p1 = 1;
3928 clock->p2 = 10;
3929 clock->n = 6;
3930 clock->m1 = 12;
3931 clock->m2 = 8;
3932 }
3933 }
3934
3935 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3936 intel_clock_t *clock,
3937 intel_clock_t *reduced_clock)
3938 {
3939 struct drm_device *dev = crtc->dev;
3940 struct drm_i915_private *dev_priv = dev->dev_private;
3941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3942 int pipe = intel_crtc->pipe;
3943 u32 fp, fp2 = 0;
3944
3945 if (IS_PINEVIEW(dev)) {
3946 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3947 if (reduced_clock)
3948 fp2 = (1 << reduced_clock->n) << 16 |
3949 reduced_clock->m1 << 8 | reduced_clock->m2;
3950 } else {
3951 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3952 if (reduced_clock)
3953 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3954 reduced_clock->m2;
3955 }
3956
3957 I915_WRITE(FP0(pipe), fp);
3958
3959 intel_crtc->lowfreq_avail = false;
3960 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3961 reduced_clock && i915_powersave) {
3962 I915_WRITE(FP1(pipe), fp2);
3963 intel_crtc->lowfreq_avail = true;
3964 } else {
3965 I915_WRITE(FP1(pipe), fp);
3966 }
3967 }
3968
3969 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3970 struct drm_display_mode *adjusted_mode)
3971 {
3972 struct drm_device *dev = crtc->dev;
3973 struct drm_i915_private *dev_priv = dev->dev_private;
3974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3975 int pipe = intel_crtc->pipe;
3976 u32 temp;
3977
3978 temp = I915_READ(LVDS);
3979 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3980 if (pipe == 1) {
3981 temp |= LVDS_PIPEB_SELECT;
3982 } else {
3983 temp &= ~LVDS_PIPEB_SELECT;
3984 }
3985 /* set the corresponsding LVDS_BORDER bit */
3986 temp |= dev_priv->lvds_border_bits;
3987 /* Set the B0-B3 data pairs corresponding to whether we're going to
3988 * set the DPLLs for dual-channel mode or not.
3989 */
3990 if (clock->p2 == 7)
3991 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3992 else
3993 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3994
3995 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3996 * appropriately here, but we need to look more thoroughly into how
3997 * panels behave in the two modes.
3998 */
3999 /* set the dithering flag on LVDS as needed */
4000 if (INTEL_INFO(dev)->gen >= 4) {
4001 if (dev_priv->lvds_dither)
4002 temp |= LVDS_ENABLE_DITHER;
4003 else
4004 temp &= ~LVDS_ENABLE_DITHER;
4005 }
4006 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4007 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4008 temp |= LVDS_HSYNC_POLARITY;
4009 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4010 temp |= LVDS_VSYNC_POLARITY;
4011 I915_WRITE(LVDS, temp);
4012 }
4013
4014 static void vlv_update_pll(struct drm_crtc *crtc,
4015 struct drm_display_mode *mode,
4016 struct drm_display_mode *adjusted_mode,
4017 intel_clock_t *clock, intel_clock_t *reduced_clock,
4018 int refclk, int num_connectors)
4019 {
4020 struct drm_device *dev = crtc->dev;
4021 struct drm_i915_private *dev_priv = dev->dev_private;
4022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4023 int pipe = intel_crtc->pipe;
4024 u32 dpll, mdiv, pdiv;
4025 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4026 bool is_hdmi;
4027
4028 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4029
4030 bestn = clock->n;
4031 bestm1 = clock->m1;
4032 bestm2 = clock->m2;
4033 bestp1 = clock->p1;
4034 bestp2 = clock->p2;
4035
4036 /* Enable DPIO clock input */
4037 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4038 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4039 I915_WRITE(DPLL(pipe), dpll);
4040 POSTING_READ(DPLL(pipe));
4041
4042 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4043 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4044 mdiv |= ((bestn << DPIO_N_SHIFT));
4045 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4046 mdiv |= (1 << DPIO_K_SHIFT);
4047 mdiv |= DPIO_ENABLE_CALIBRATION;
4048 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4049
4050 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4051
4052 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4053 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4054 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4055 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4056
4057 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4058
4059 dpll |= DPLL_VCO_ENABLE;
4060 I915_WRITE(DPLL(pipe), dpll);
4061 POSTING_READ(DPLL(pipe));
4062 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4063 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4064
4065 if (is_hdmi) {
4066 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4067
4068 if (temp > 1)
4069 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4070 else
4071 temp = 0;
4072
4073 I915_WRITE(DPLL_MD(pipe), temp);
4074 POSTING_READ(DPLL_MD(pipe));
4075 }
4076
4077 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4078 }
4079
4080 static void i9xx_update_pll(struct drm_crtc *crtc,
4081 struct drm_display_mode *mode,
4082 struct drm_display_mode *adjusted_mode,
4083 intel_clock_t *clock, intel_clock_t *reduced_clock,
4084 int num_connectors)
4085 {
4086 struct drm_device *dev = crtc->dev;
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4089 int pipe = intel_crtc->pipe;
4090 u32 dpll;
4091 bool is_sdvo;
4092
4093 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4094 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4095
4096 dpll = DPLL_VGA_MODE_DIS;
4097
4098 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4099 dpll |= DPLLB_MODE_LVDS;
4100 else
4101 dpll |= DPLLB_MODE_DAC_SERIAL;
4102 if (is_sdvo) {
4103 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4104 if (pixel_multiplier > 1) {
4105 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4106 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4107 }
4108 dpll |= DPLL_DVO_HIGH_SPEED;
4109 }
4110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4111 dpll |= DPLL_DVO_HIGH_SPEED;
4112
4113 /* compute bitmask from p1 value */
4114 if (IS_PINEVIEW(dev))
4115 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4116 else {
4117 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4118 if (IS_G4X(dev) && reduced_clock)
4119 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4120 }
4121 switch (clock->p2) {
4122 case 5:
4123 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4124 break;
4125 case 7:
4126 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4127 break;
4128 case 10:
4129 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4130 break;
4131 case 14:
4132 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4133 break;
4134 }
4135 if (INTEL_INFO(dev)->gen >= 4)
4136 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4137
4138 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4139 dpll |= PLL_REF_INPUT_TVCLKINBC;
4140 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4141 /* XXX: just matching BIOS for now */
4142 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4143 dpll |= 3;
4144 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4145 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4146 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4147 else
4148 dpll |= PLL_REF_INPUT_DREFCLK;
4149
4150 dpll |= DPLL_VCO_ENABLE;
4151 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4152 POSTING_READ(DPLL(pipe));
4153 udelay(150);
4154
4155 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4156 * This is an exception to the general rule that mode_set doesn't turn
4157 * things on.
4158 */
4159 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4160 intel_update_lvds(crtc, clock, adjusted_mode);
4161
4162 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4163 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4164
4165 I915_WRITE(DPLL(pipe), dpll);
4166
4167 /* Wait for the clocks to stabilize. */
4168 POSTING_READ(DPLL(pipe));
4169 udelay(150);
4170
4171 if (INTEL_INFO(dev)->gen >= 4) {
4172 u32 temp = 0;
4173 if (is_sdvo) {
4174 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4175 if (temp > 1)
4176 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4177 else
4178 temp = 0;
4179 }
4180 I915_WRITE(DPLL_MD(pipe), temp);
4181 } else {
4182 /* The pixel multiplier can only be updated once the
4183 * DPLL is enabled and the clocks are stable.
4184 *
4185 * So write it again.
4186 */
4187 I915_WRITE(DPLL(pipe), dpll);
4188 }
4189 }
4190
4191 static void i8xx_update_pll(struct drm_crtc *crtc,
4192 struct drm_display_mode *adjusted_mode,
4193 intel_clock_t *clock,
4194 int num_connectors)
4195 {
4196 struct drm_device *dev = crtc->dev;
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4199 int pipe = intel_crtc->pipe;
4200 u32 dpll;
4201
4202 dpll = DPLL_VGA_MODE_DIS;
4203
4204 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4205 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4206 } else {
4207 if (clock->p1 == 2)
4208 dpll |= PLL_P1_DIVIDE_BY_TWO;
4209 else
4210 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4211 if (clock->p2 == 4)
4212 dpll |= PLL_P2_DIVIDE_BY_4;
4213 }
4214
4215 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4216 /* XXX: just matching BIOS for now */
4217 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4218 dpll |= 3;
4219 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4220 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4221 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4222 else
4223 dpll |= PLL_REF_INPUT_DREFCLK;
4224
4225 dpll |= DPLL_VCO_ENABLE;
4226 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4227 POSTING_READ(DPLL(pipe));
4228 udelay(150);
4229
4230 I915_WRITE(DPLL(pipe), dpll);
4231
4232 /* Wait for the clocks to stabilize. */
4233 POSTING_READ(DPLL(pipe));
4234 udelay(150);
4235
4236 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4237 * This is an exception to the general rule that mode_set doesn't turn
4238 * things on.
4239 */
4240 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4241 intel_update_lvds(crtc, clock, adjusted_mode);
4242
4243 /* The pixel multiplier can only be updated once the
4244 * DPLL is enabled and the clocks are stable.
4245 *
4246 * So write it again.
4247 */
4248 I915_WRITE(DPLL(pipe), dpll);
4249 }
4250
4251 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4252 struct drm_display_mode *mode,
4253 struct drm_display_mode *adjusted_mode,
4254 int x, int y,
4255 struct drm_framebuffer *old_fb)
4256 {
4257 struct drm_device *dev = crtc->dev;
4258 struct drm_i915_private *dev_priv = dev->dev_private;
4259 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4260 int pipe = intel_crtc->pipe;
4261 int plane = intel_crtc->plane;
4262 int refclk, num_connectors = 0;
4263 intel_clock_t clock, reduced_clock;
4264 u32 dspcntr, pipeconf, vsyncshift;
4265 bool ok, has_reduced_clock = false, is_sdvo = false;
4266 bool is_lvds = false, is_tv = false, is_dp = false;
4267 struct intel_encoder *encoder;
4268 const intel_limit_t *limit;
4269 int ret;
4270
4271 for_each_encoder_on_crtc(dev, crtc, encoder) {
4272 switch (encoder->type) {
4273 case INTEL_OUTPUT_LVDS:
4274 is_lvds = true;
4275 break;
4276 case INTEL_OUTPUT_SDVO:
4277 case INTEL_OUTPUT_HDMI:
4278 is_sdvo = true;
4279 if (encoder->needs_tv_clock)
4280 is_tv = true;
4281 break;
4282 case INTEL_OUTPUT_TVOUT:
4283 is_tv = true;
4284 break;
4285 case INTEL_OUTPUT_DISPLAYPORT:
4286 is_dp = true;
4287 break;
4288 }
4289
4290 num_connectors++;
4291 }
4292
4293 refclk = i9xx_get_refclk(crtc, num_connectors);
4294
4295 /*
4296 * Returns a set of divisors for the desired target clock with the given
4297 * refclk, or FALSE. The returned values represent the clock equation:
4298 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4299 */
4300 limit = intel_limit(crtc, refclk);
4301 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4302 &clock);
4303 if (!ok) {
4304 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4305 return -EINVAL;
4306 }
4307
4308 /* Ensure that the cursor is valid for the new mode before changing... */
4309 intel_crtc_update_cursor(crtc, true);
4310
4311 if (is_lvds && dev_priv->lvds_downclock_avail) {
4312 /*
4313 * Ensure we match the reduced clock's P to the target clock.
4314 * If the clocks don't match, we can't switch the display clock
4315 * by using the FP0/FP1. In such case we will disable the LVDS
4316 * downclock feature.
4317 */
4318 has_reduced_clock = limit->find_pll(limit, crtc,
4319 dev_priv->lvds_downclock,
4320 refclk,
4321 &clock,
4322 &reduced_clock);
4323 }
4324
4325 if (is_sdvo && is_tv)
4326 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4327
4328 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4329 &reduced_clock : NULL);
4330
4331 if (IS_GEN2(dev))
4332 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
4333 else if (IS_VALLEYVIEW(dev))
4334 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4335 refclk, num_connectors);
4336 else
4337 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4338 has_reduced_clock ? &reduced_clock : NULL,
4339 num_connectors);
4340
4341 /* setup pipeconf */
4342 pipeconf = I915_READ(PIPECONF(pipe));
4343
4344 /* Set up the display plane register */
4345 dspcntr = DISPPLANE_GAMMA_ENABLE;
4346
4347 if (pipe == 0)
4348 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4349 else
4350 dspcntr |= DISPPLANE_SEL_PIPE_B;
4351
4352 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4353 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4354 * core speed.
4355 *
4356 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4357 * pipe == 0 check?
4358 */
4359 if (mode->clock >
4360 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4361 pipeconf |= PIPECONF_DOUBLE_WIDE;
4362 else
4363 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4364 }
4365
4366 /* default to 8bpc */
4367 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4368 if (is_dp) {
4369 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4370 pipeconf |= PIPECONF_BPP_6 |
4371 PIPECONF_DITHER_EN |
4372 PIPECONF_DITHER_TYPE_SP;
4373 }
4374 }
4375
4376 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4377 drm_mode_debug_printmodeline(mode);
4378
4379 if (HAS_PIPE_CXSR(dev)) {
4380 if (intel_crtc->lowfreq_avail) {
4381 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4382 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4383 } else {
4384 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4385 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4386 }
4387 }
4388
4389 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4390 if (!IS_GEN2(dev) &&
4391 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4392 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4393 /* the chip adds 2 halflines automatically */
4394 adjusted_mode->crtc_vtotal -= 1;
4395 adjusted_mode->crtc_vblank_end -= 1;
4396 vsyncshift = adjusted_mode->crtc_hsync_start
4397 - adjusted_mode->crtc_htotal/2;
4398 } else {
4399 pipeconf |= PIPECONF_PROGRESSIVE;
4400 vsyncshift = 0;
4401 }
4402
4403 if (!IS_GEN3(dev))
4404 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
4405
4406 I915_WRITE(HTOTAL(pipe),
4407 (adjusted_mode->crtc_hdisplay - 1) |
4408 ((adjusted_mode->crtc_htotal - 1) << 16));
4409 I915_WRITE(HBLANK(pipe),
4410 (adjusted_mode->crtc_hblank_start - 1) |
4411 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4412 I915_WRITE(HSYNC(pipe),
4413 (adjusted_mode->crtc_hsync_start - 1) |
4414 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4415
4416 I915_WRITE(VTOTAL(pipe),
4417 (adjusted_mode->crtc_vdisplay - 1) |
4418 ((adjusted_mode->crtc_vtotal - 1) << 16));
4419 I915_WRITE(VBLANK(pipe),
4420 (adjusted_mode->crtc_vblank_start - 1) |
4421 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4422 I915_WRITE(VSYNC(pipe),
4423 (adjusted_mode->crtc_vsync_start - 1) |
4424 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4425
4426 /* pipesrc and dspsize control the size that is scaled from,
4427 * which should always be the user's requested size.
4428 */
4429 I915_WRITE(DSPSIZE(plane),
4430 ((mode->vdisplay - 1) << 16) |
4431 (mode->hdisplay - 1));
4432 I915_WRITE(DSPPOS(plane), 0);
4433 I915_WRITE(PIPESRC(pipe),
4434 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4435
4436 I915_WRITE(PIPECONF(pipe), pipeconf);
4437 POSTING_READ(PIPECONF(pipe));
4438 intel_enable_pipe(dev_priv, pipe, false);
4439
4440 intel_wait_for_vblank(dev, pipe);
4441
4442 I915_WRITE(DSPCNTR(plane), dspcntr);
4443 POSTING_READ(DSPCNTR(plane));
4444
4445 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4446
4447 intel_update_watermarks(dev);
4448
4449 return ret;
4450 }
4451
4452 /*
4453 * Initialize reference clocks when the driver loads
4454 */
4455 void ironlake_init_pch_refclk(struct drm_device *dev)
4456 {
4457 struct drm_i915_private *dev_priv = dev->dev_private;
4458 struct drm_mode_config *mode_config = &dev->mode_config;
4459 struct intel_encoder *encoder;
4460 u32 temp;
4461 bool has_lvds = false;
4462 bool has_cpu_edp = false;
4463 bool has_pch_edp = false;
4464 bool has_panel = false;
4465 bool has_ck505 = false;
4466 bool can_ssc = false;
4467
4468 /* We need to take the global config into account */
4469 list_for_each_entry(encoder, &mode_config->encoder_list,
4470 base.head) {
4471 switch (encoder->type) {
4472 case INTEL_OUTPUT_LVDS:
4473 has_panel = true;
4474 has_lvds = true;
4475 break;
4476 case INTEL_OUTPUT_EDP:
4477 has_panel = true;
4478 if (intel_encoder_is_pch_edp(&encoder->base))
4479 has_pch_edp = true;
4480 else
4481 has_cpu_edp = true;
4482 break;
4483 }
4484 }
4485
4486 if (HAS_PCH_IBX(dev)) {
4487 has_ck505 = dev_priv->display_clock_mode;
4488 can_ssc = has_ck505;
4489 } else {
4490 has_ck505 = false;
4491 can_ssc = true;
4492 }
4493
4494 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4495 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4496 has_ck505);
4497
4498 /* Ironlake: try to setup display ref clock before DPLL
4499 * enabling. This is only under driver's control after
4500 * PCH B stepping, previous chipset stepping should be
4501 * ignoring this setting.
4502 */
4503 temp = I915_READ(PCH_DREF_CONTROL);
4504 /* Always enable nonspread source */
4505 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4506
4507 if (has_ck505)
4508 temp |= DREF_NONSPREAD_CK505_ENABLE;
4509 else
4510 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4511
4512 if (has_panel) {
4513 temp &= ~DREF_SSC_SOURCE_MASK;
4514 temp |= DREF_SSC_SOURCE_ENABLE;
4515
4516 /* SSC must be turned on before enabling the CPU output */
4517 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4518 DRM_DEBUG_KMS("Using SSC on panel\n");
4519 temp |= DREF_SSC1_ENABLE;
4520 } else
4521 temp &= ~DREF_SSC1_ENABLE;
4522
4523 /* Get SSC going before enabling the outputs */
4524 I915_WRITE(PCH_DREF_CONTROL, temp);
4525 POSTING_READ(PCH_DREF_CONTROL);
4526 udelay(200);
4527
4528 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4529
4530 /* Enable CPU source on CPU attached eDP */
4531 if (has_cpu_edp) {
4532 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4533 DRM_DEBUG_KMS("Using SSC on eDP\n");
4534 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4535 }
4536 else
4537 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4538 } else
4539 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4540
4541 I915_WRITE(PCH_DREF_CONTROL, temp);
4542 POSTING_READ(PCH_DREF_CONTROL);
4543 udelay(200);
4544 } else {
4545 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4546
4547 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4548
4549 /* Turn off CPU output */
4550 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4551
4552 I915_WRITE(PCH_DREF_CONTROL, temp);
4553 POSTING_READ(PCH_DREF_CONTROL);
4554 udelay(200);
4555
4556 /* Turn off the SSC source */
4557 temp &= ~DREF_SSC_SOURCE_MASK;
4558 temp |= DREF_SSC_SOURCE_DISABLE;
4559
4560 /* Turn off SSC1 */
4561 temp &= ~ DREF_SSC1_ENABLE;
4562
4563 I915_WRITE(PCH_DREF_CONTROL, temp);
4564 POSTING_READ(PCH_DREF_CONTROL);
4565 udelay(200);
4566 }
4567 }
4568
4569 static int ironlake_get_refclk(struct drm_crtc *crtc)
4570 {
4571 struct drm_device *dev = crtc->dev;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 struct intel_encoder *encoder;
4574 struct intel_encoder *edp_encoder = NULL;
4575 int num_connectors = 0;
4576 bool is_lvds = false;
4577
4578 for_each_encoder_on_crtc(dev, crtc, encoder) {
4579 switch (encoder->type) {
4580 case INTEL_OUTPUT_LVDS:
4581 is_lvds = true;
4582 break;
4583 case INTEL_OUTPUT_EDP:
4584 edp_encoder = encoder;
4585 break;
4586 }
4587 num_connectors++;
4588 }
4589
4590 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4591 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4592 dev_priv->lvds_ssc_freq);
4593 return dev_priv->lvds_ssc_freq * 1000;
4594 }
4595
4596 return 120000;
4597 }
4598
4599 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4600 struct drm_display_mode *mode,
4601 struct drm_display_mode *adjusted_mode,
4602 int x, int y,
4603 struct drm_framebuffer *old_fb)
4604 {
4605 struct drm_device *dev = crtc->dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4608 int pipe = intel_crtc->pipe;
4609 int plane = intel_crtc->plane;
4610 int refclk, num_connectors = 0;
4611 intel_clock_t clock, reduced_clock;
4612 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
4613 bool ok, has_reduced_clock = false, is_sdvo = false;
4614 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
4615 struct intel_encoder *encoder, *edp_encoder = NULL;
4616 const intel_limit_t *limit;
4617 int ret;
4618 struct fdi_m_n m_n = {0};
4619 u32 temp;
4620 int target_clock, pixel_multiplier, lane, link_bw, factor;
4621 unsigned int pipe_bpp;
4622 bool dither;
4623 bool is_cpu_edp = false, is_pch_edp = false;
4624
4625 for_each_encoder_on_crtc(dev, crtc, encoder) {
4626 switch (encoder->type) {
4627 case INTEL_OUTPUT_LVDS:
4628 is_lvds = true;
4629 break;
4630 case INTEL_OUTPUT_SDVO:
4631 case INTEL_OUTPUT_HDMI:
4632 is_sdvo = true;
4633 if (encoder->needs_tv_clock)
4634 is_tv = true;
4635 break;
4636 case INTEL_OUTPUT_TVOUT:
4637 is_tv = true;
4638 break;
4639 case INTEL_OUTPUT_ANALOG:
4640 is_crt = true;
4641 break;
4642 case INTEL_OUTPUT_DISPLAYPORT:
4643 is_dp = true;
4644 break;
4645 case INTEL_OUTPUT_EDP:
4646 is_dp = true;
4647 if (intel_encoder_is_pch_edp(&encoder->base))
4648 is_pch_edp = true;
4649 else
4650 is_cpu_edp = true;
4651 edp_encoder = encoder;
4652 break;
4653 }
4654
4655 num_connectors++;
4656 }
4657
4658 refclk = ironlake_get_refclk(crtc);
4659
4660 /*
4661 * Returns a set of divisors for the desired target clock with the given
4662 * refclk, or FALSE. The returned values represent the clock equation:
4663 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4664 */
4665 limit = intel_limit(crtc, refclk);
4666 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4667 &clock);
4668 if (!ok) {
4669 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4670 return -EINVAL;
4671 }
4672
4673 /* Ensure that the cursor is valid for the new mode before changing... */
4674 intel_crtc_update_cursor(crtc, true);
4675
4676 if (is_lvds && dev_priv->lvds_downclock_avail) {
4677 /*
4678 * Ensure we match the reduced clock's P to the target clock.
4679 * If the clocks don't match, we can't switch the display clock
4680 * by using the FP0/FP1. In such case we will disable the LVDS
4681 * downclock feature.
4682 */
4683 has_reduced_clock = limit->find_pll(limit, crtc,
4684 dev_priv->lvds_downclock,
4685 refclk,
4686 &clock,
4687 &reduced_clock);
4688 }
4689
4690 if (is_sdvo && is_tv)
4691 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4692
4693
4694 /* FDI link */
4695 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4696 lane = 0;
4697 /* CPU eDP doesn't require FDI link, so just set DP M/N
4698 according to current link config */
4699 if (is_cpu_edp) {
4700 intel_edp_link_config(edp_encoder, &lane, &link_bw);
4701 } else {
4702 /* FDI is a binary signal running at ~2.7GHz, encoding
4703 * each output octet as 10 bits. The actual frequency
4704 * is stored as a divider into a 100MHz clock, and the
4705 * mode pixel clock is stored in units of 1KHz.
4706 * Hence the bw of each lane in terms of the mode signal
4707 * is:
4708 */
4709 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4710 }
4711
4712 /* [e]DP over FDI requires target mode clock instead of link clock. */
4713 if (edp_encoder)
4714 target_clock = intel_edp_target_clock(edp_encoder, mode);
4715 else if (is_dp)
4716 target_clock = mode->clock;
4717 else
4718 target_clock = adjusted_mode->clock;
4719
4720 /* determine panel color depth */
4721 temp = I915_READ(PIPECONF(pipe));
4722 temp &= ~PIPE_BPC_MASK;
4723 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
4724 switch (pipe_bpp) {
4725 case 18:
4726 temp |= PIPE_6BPC;
4727 break;
4728 case 24:
4729 temp |= PIPE_8BPC;
4730 break;
4731 case 30:
4732 temp |= PIPE_10BPC;
4733 break;
4734 case 36:
4735 temp |= PIPE_12BPC;
4736 break;
4737 default:
4738 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4739 pipe_bpp);
4740 temp |= PIPE_8BPC;
4741 pipe_bpp = 24;
4742 break;
4743 }
4744
4745 intel_crtc->bpp = pipe_bpp;
4746 I915_WRITE(PIPECONF(pipe), temp);
4747
4748 if (!lane) {
4749 /*
4750 * Account for spread spectrum to avoid
4751 * oversubscribing the link. Max center spread
4752 * is 2.5%; use 5% for safety's sake.
4753 */
4754 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
4755 lane = bps / (link_bw * 8) + 1;
4756 }
4757
4758 intel_crtc->fdi_lanes = lane;
4759
4760 if (pixel_multiplier > 1)
4761 link_bw *= pixel_multiplier;
4762 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4763 &m_n);
4764
4765 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4766 if (has_reduced_clock)
4767 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4768 reduced_clock.m2;
4769
4770 /* Enable autotuning of the PLL clock (if permissible) */
4771 factor = 21;
4772 if (is_lvds) {
4773 if ((intel_panel_use_ssc(dev_priv) &&
4774 dev_priv->lvds_ssc_freq == 100) ||
4775 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4776 factor = 25;
4777 } else if (is_sdvo && is_tv)
4778 factor = 20;
4779
4780 if (clock.m < factor * clock.n)
4781 fp |= FP_CB_TUNE;
4782
4783 dpll = 0;
4784
4785 if (is_lvds)
4786 dpll |= DPLLB_MODE_LVDS;
4787 else
4788 dpll |= DPLLB_MODE_DAC_SERIAL;
4789 if (is_sdvo) {
4790 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4791 if (pixel_multiplier > 1) {
4792 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4793 }
4794 dpll |= DPLL_DVO_HIGH_SPEED;
4795 }
4796 if (is_dp && !is_cpu_edp)
4797 dpll |= DPLL_DVO_HIGH_SPEED;
4798
4799 /* compute bitmask from p1 value */
4800 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4801 /* also FPA1 */
4802 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4803
4804 switch (clock.p2) {
4805 case 5:
4806 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4807 break;
4808 case 7:
4809 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4810 break;
4811 case 10:
4812 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4813 break;
4814 case 14:
4815 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4816 break;
4817 }
4818
4819 if (is_sdvo && is_tv)
4820 dpll |= PLL_REF_INPUT_TVCLKINBC;
4821 else if (is_tv)
4822 /* XXX: just matching BIOS for now */
4823 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4824 dpll |= 3;
4825 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4826 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4827 else
4828 dpll |= PLL_REF_INPUT_DREFCLK;
4829
4830 /* setup pipeconf */
4831 pipeconf = I915_READ(PIPECONF(pipe));
4832
4833 /* Set up the display plane register */
4834 dspcntr = DISPPLANE_GAMMA_ENABLE;
4835
4836 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
4837 drm_mode_debug_printmodeline(mode);
4838
4839 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4840 * pre-Haswell/LPT generation */
4841 if (HAS_PCH_LPT(dev)) {
4842 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4843 pipe);
4844 } else if (!is_cpu_edp) {
4845 struct intel_pch_pll *pll;
4846
4847 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4848 if (pll == NULL) {
4849 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4850 pipe);
4851 return -EINVAL;
4852 }
4853 } else
4854 intel_put_pch_pll(intel_crtc);
4855
4856 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4857 * This is an exception to the general rule that mode_set doesn't turn
4858 * things on.
4859 */
4860 if (is_lvds) {
4861 temp = I915_READ(PCH_LVDS);
4862 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4863 if (HAS_PCH_CPT(dev)) {
4864 temp &= ~PORT_TRANS_SEL_MASK;
4865 temp |= PORT_TRANS_SEL_CPT(pipe);
4866 } else {
4867 if (pipe == 1)
4868 temp |= LVDS_PIPEB_SELECT;
4869 else
4870 temp &= ~LVDS_PIPEB_SELECT;
4871 }
4872
4873 /* set the corresponsding LVDS_BORDER bit */
4874 temp |= dev_priv->lvds_border_bits;
4875 /* Set the B0-B3 data pairs corresponding to whether we're going to
4876 * set the DPLLs for dual-channel mode or not.
4877 */
4878 if (clock.p2 == 7)
4879 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4880 else
4881 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4882
4883 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4884 * appropriately here, but we need to look more thoroughly into how
4885 * panels behave in the two modes.
4886 */
4887 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4888 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4889 temp |= LVDS_HSYNC_POLARITY;
4890 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4891 temp |= LVDS_VSYNC_POLARITY;
4892 I915_WRITE(PCH_LVDS, temp);
4893 }
4894
4895 pipeconf &= ~PIPECONF_DITHER_EN;
4896 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4897 if ((is_lvds && dev_priv->lvds_dither) || dither) {
4898 pipeconf |= PIPECONF_DITHER_EN;
4899 pipeconf |= PIPECONF_DITHER_TYPE_SP;
4900 }
4901 if (is_dp && !is_cpu_edp) {
4902 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4903 } else {
4904 /* For non-DP output, clear any trans DP clock recovery setting.*/
4905 I915_WRITE(TRANSDATA_M1(pipe), 0);
4906 I915_WRITE(TRANSDATA_N1(pipe), 0);
4907 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4908 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
4909 }
4910
4911 if (intel_crtc->pch_pll) {
4912 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4913
4914 /* Wait for the clocks to stabilize. */
4915 POSTING_READ(intel_crtc->pch_pll->pll_reg);
4916 udelay(150);
4917
4918 /* The pixel multiplier can only be updated once the
4919 * DPLL is enabled and the clocks are stable.
4920 *
4921 * So write it again.
4922 */
4923 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
4924 }
4925
4926 intel_crtc->lowfreq_avail = false;
4927 if (intel_crtc->pch_pll) {
4928 if (is_lvds && has_reduced_clock && i915_powersave) {
4929 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4930 intel_crtc->lowfreq_avail = true;
4931 } else {
4932 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
4933 }
4934 }
4935
4936 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4937 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4938 pipeconf |= PIPECONF_INTERLACED_ILK;
4939 /* the chip adds 2 halflines automatically */
4940 adjusted_mode->crtc_vtotal -= 1;
4941 adjusted_mode->crtc_vblank_end -= 1;
4942 I915_WRITE(VSYNCSHIFT(pipe),
4943 adjusted_mode->crtc_hsync_start
4944 - adjusted_mode->crtc_htotal/2);
4945 } else {
4946 pipeconf |= PIPECONF_PROGRESSIVE;
4947 I915_WRITE(VSYNCSHIFT(pipe), 0);
4948 }
4949
4950 I915_WRITE(HTOTAL(pipe),
4951 (adjusted_mode->crtc_hdisplay - 1) |
4952 ((adjusted_mode->crtc_htotal - 1) << 16));
4953 I915_WRITE(HBLANK(pipe),
4954 (adjusted_mode->crtc_hblank_start - 1) |
4955 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4956 I915_WRITE(HSYNC(pipe),
4957 (adjusted_mode->crtc_hsync_start - 1) |
4958 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4959
4960 I915_WRITE(VTOTAL(pipe),
4961 (adjusted_mode->crtc_vdisplay - 1) |
4962 ((adjusted_mode->crtc_vtotal - 1) << 16));
4963 I915_WRITE(VBLANK(pipe),
4964 (adjusted_mode->crtc_vblank_start - 1) |
4965 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4966 I915_WRITE(VSYNC(pipe),
4967 (adjusted_mode->crtc_vsync_start - 1) |
4968 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4969
4970 /* pipesrc controls the size that is scaled from, which should
4971 * always be the user's requested size.
4972 */
4973 I915_WRITE(PIPESRC(pipe),
4974 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4975
4976 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4977 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4978 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4979 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4980
4981 if (is_cpu_edp)
4982 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4983
4984 I915_WRITE(PIPECONF(pipe), pipeconf);
4985 POSTING_READ(PIPECONF(pipe));
4986
4987 intel_wait_for_vblank(dev, pipe);
4988
4989 I915_WRITE(DSPCNTR(plane), dspcntr);
4990 POSTING_READ(DSPCNTR(plane));
4991
4992 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4993
4994 intel_update_watermarks(dev);
4995
4996 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4997
4998 return ret;
4999 }
5000
5001 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5002 struct drm_display_mode *mode,
5003 struct drm_display_mode *adjusted_mode,
5004 int x, int y,
5005 struct drm_framebuffer *old_fb)
5006 {
5007 struct drm_device *dev = crtc->dev;
5008 struct drm_i915_private *dev_priv = dev->dev_private;
5009 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5010 int pipe = intel_crtc->pipe;
5011 int ret;
5012
5013 drm_vblank_pre_modeset(dev, pipe);
5014
5015 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5016 x, y, old_fb);
5017 drm_vblank_post_modeset(dev, pipe);
5018
5019 if (ret)
5020 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5021 else
5022 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5023
5024 return ret;
5025 }
5026
5027 static bool intel_eld_uptodate(struct drm_connector *connector,
5028 int reg_eldv, uint32_t bits_eldv,
5029 int reg_elda, uint32_t bits_elda,
5030 int reg_edid)
5031 {
5032 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5033 uint8_t *eld = connector->eld;
5034 uint32_t i;
5035
5036 i = I915_READ(reg_eldv);
5037 i &= bits_eldv;
5038
5039 if (!eld[0])
5040 return !i;
5041
5042 if (!i)
5043 return false;
5044
5045 i = I915_READ(reg_elda);
5046 i &= ~bits_elda;
5047 I915_WRITE(reg_elda, i);
5048
5049 for (i = 0; i < eld[2]; i++)
5050 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5051 return false;
5052
5053 return true;
5054 }
5055
5056 static void g4x_write_eld(struct drm_connector *connector,
5057 struct drm_crtc *crtc)
5058 {
5059 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5060 uint8_t *eld = connector->eld;
5061 uint32_t eldv;
5062 uint32_t len;
5063 uint32_t i;
5064
5065 i = I915_READ(G4X_AUD_VID_DID);
5066
5067 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5068 eldv = G4X_ELDV_DEVCL_DEVBLC;
5069 else
5070 eldv = G4X_ELDV_DEVCTG;
5071
5072 if (intel_eld_uptodate(connector,
5073 G4X_AUD_CNTL_ST, eldv,
5074 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5075 G4X_HDMIW_HDMIEDID))
5076 return;
5077
5078 i = I915_READ(G4X_AUD_CNTL_ST);
5079 i &= ~(eldv | G4X_ELD_ADDR);
5080 len = (i >> 9) & 0x1f; /* ELD buffer size */
5081 I915_WRITE(G4X_AUD_CNTL_ST, i);
5082
5083 if (!eld[0])
5084 return;
5085
5086 len = min_t(uint8_t, eld[2], len);
5087 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5088 for (i = 0; i < len; i++)
5089 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5090
5091 i = I915_READ(G4X_AUD_CNTL_ST);
5092 i |= eldv;
5093 I915_WRITE(G4X_AUD_CNTL_ST, i);
5094 }
5095
5096 static void haswell_write_eld(struct drm_connector *connector,
5097 struct drm_crtc *crtc)
5098 {
5099 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5100 uint8_t *eld = connector->eld;
5101 struct drm_device *dev = crtc->dev;
5102 uint32_t eldv;
5103 uint32_t i;
5104 int len;
5105 int pipe = to_intel_crtc(crtc)->pipe;
5106 int tmp;
5107
5108 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5109 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5110 int aud_config = HSW_AUD_CFG(pipe);
5111 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5112
5113
5114 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5115
5116 /* Audio output enable */
5117 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5118 tmp = I915_READ(aud_cntrl_st2);
5119 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5120 I915_WRITE(aud_cntrl_st2, tmp);
5121
5122 /* Wait for 1 vertical blank */
5123 intel_wait_for_vblank(dev, pipe);
5124
5125 /* Set ELD valid state */
5126 tmp = I915_READ(aud_cntrl_st2);
5127 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5128 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5129 I915_WRITE(aud_cntrl_st2, tmp);
5130 tmp = I915_READ(aud_cntrl_st2);
5131 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5132
5133 /* Enable HDMI mode */
5134 tmp = I915_READ(aud_config);
5135 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5136 /* clear N_programing_enable and N_value_index */
5137 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5138 I915_WRITE(aud_config, tmp);
5139
5140 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5141
5142 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5143
5144 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5145 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5146 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5147 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5148 } else
5149 I915_WRITE(aud_config, 0);
5150
5151 if (intel_eld_uptodate(connector,
5152 aud_cntrl_st2, eldv,
5153 aud_cntl_st, IBX_ELD_ADDRESS,
5154 hdmiw_hdmiedid))
5155 return;
5156
5157 i = I915_READ(aud_cntrl_st2);
5158 i &= ~eldv;
5159 I915_WRITE(aud_cntrl_st2, i);
5160
5161 if (!eld[0])
5162 return;
5163
5164 i = I915_READ(aud_cntl_st);
5165 i &= ~IBX_ELD_ADDRESS;
5166 I915_WRITE(aud_cntl_st, i);
5167 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5168 DRM_DEBUG_DRIVER("port num:%d\n", i);
5169
5170 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5171 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5172 for (i = 0; i < len; i++)
5173 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5174
5175 i = I915_READ(aud_cntrl_st2);
5176 i |= eldv;
5177 I915_WRITE(aud_cntrl_st2, i);
5178
5179 }
5180
5181 static void ironlake_write_eld(struct drm_connector *connector,
5182 struct drm_crtc *crtc)
5183 {
5184 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5185 uint8_t *eld = connector->eld;
5186 uint32_t eldv;
5187 uint32_t i;
5188 int len;
5189 int hdmiw_hdmiedid;
5190 int aud_config;
5191 int aud_cntl_st;
5192 int aud_cntrl_st2;
5193 int pipe = to_intel_crtc(crtc)->pipe;
5194
5195 if (HAS_PCH_IBX(connector->dev)) {
5196 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5197 aud_config = IBX_AUD_CFG(pipe);
5198 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5199 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5200 } else {
5201 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5202 aud_config = CPT_AUD_CFG(pipe);
5203 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5204 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5205 }
5206
5207 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5208
5209 i = I915_READ(aud_cntl_st);
5210 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5211 if (!i) {
5212 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5213 /* operate blindly on all ports */
5214 eldv = IBX_ELD_VALIDB;
5215 eldv |= IBX_ELD_VALIDB << 4;
5216 eldv |= IBX_ELD_VALIDB << 8;
5217 } else {
5218 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5219 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5220 }
5221
5222 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5223 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5224 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5225 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5226 } else
5227 I915_WRITE(aud_config, 0);
5228
5229 if (intel_eld_uptodate(connector,
5230 aud_cntrl_st2, eldv,
5231 aud_cntl_st, IBX_ELD_ADDRESS,
5232 hdmiw_hdmiedid))
5233 return;
5234
5235 i = I915_READ(aud_cntrl_st2);
5236 i &= ~eldv;
5237 I915_WRITE(aud_cntrl_st2, i);
5238
5239 if (!eld[0])
5240 return;
5241
5242 i = I915_READ(aud_cntl_st);
5243 i &= ~IBX_ELD_ADDRESS;
5244 I915_WRITE(aud_cntl_st, i);
5245
5246 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5247 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5248 for (i = 0; i < len; i++)
5249 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5250
5251 i = I915_READ(aud_cntrl_st2);
5252 i |= eldv;
5253 I915_WRITE(aud_cntrl_st2, i);
5254 }
5255
5256 void intel_write_eld(struct drm_encoder *encoder,
5257 struct drm_display_mode *mode)
5258 {
5259 struct drm_crtc *crtc = encoder->crtc;
5260 struct drm_connector *connector;
5261 struct drm_device *dev = encoder->dev;
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263
5264 connector = drm_select_eld(encoder, mode);
5265 if (!connector)
5266 return;
5267
5268 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5269 connector->base.id,
5270 drm_get_connector_name(connector),
5271 connector->encoder->base.id,
5272 drm_get_encoder_name(connector->encoder));
5273
5274 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5275
5276 if (dev_priv->display.write_eld)
5277 dev_priv->display.write_eld(connector, crtc);
5278 }
5279
5280 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5281 void intel_crtc_load_lut(struct drm_crtc *crtc)
5282 {
5283 struct drm_device *dev = crtc->dev;
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5286 int palreg = PALETTE(intel_crtc->pipe);
5287 int i;
5288
5289 /* The clocks have to be on to load the palette. */
5290 if (!crtc->enabled || !intel_crtc->active)
5291 return;
5292
5293 /* use legacy palette for Ironlake */
5294 if (HAS_PCH_SPLIT(dev))
5295 palreg = LGC_PALETTE(intel_crtc->pipe);
5296
5297 for (i = 0; i < 256; i++) {
5298 I915_WRITE(palreg + 4 * i,
5299 (intel_crtc->lut_r[i] << 16) |
5300 (intel_crtc->lut_g[i] << 8) |
5301 intel_crtc->lut_b[i]);
5302 }
5303 }
5304
5305 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5306 {
5307 struct drm_device *dev = crtc->dev;
5308 struct drm_i915_private *dev_priv = dev->dev_private;
5309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5310 bool visible = base != 0;
5311 u32 cntl;
5312
5313 if (intel_crtc->cursor_visible == visible)
5314 return;
5315
5316 cntl = I915_READ(_CURACNTR);
5317 if (visible) {
5318 /* On these chipsets we can only modify the base whilst
5319 * the cursor is disabled.
5320 */
5321 I915_WRITE(_CURABASE, base);
5322
5323 cntl &= ~(CURSOR_FORMAT_MASK);
5324 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5325 cntl |= CURSOR_ENABLE |
5326 CURSOR_GAMMA_ENABLE |
5327 CURSOR_FORMAT_ARGB;
5328 } else
5329 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
5330 I915_WRITE(_CURACNTR, cntl);
5331
5332 intel_crtc->cursor_visible = visible;
5333 }
5334
5335 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5336 {
5337 struct drm_device *dev = crtc->dev;
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5340 int pipe = intel_crtc->pipe;
5341 bool visible = base != 0;
5342
5343 if (intel_crtc->cursor_visible != visible) {
5344 uint32_t cntl = I915_READ(CURCNTR(pipe));
5345 if (base) {
5346 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5347 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5348 cntl |= pipe << 28; /* Connect to correct pipe */
5349 } else {
5350 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5351 cntl |= CURSOR_MODE_DISABLE;
5352 }
5353 I915_WRITE(CURCNTR(pipe), cntl);
5354
5355 intel_crtc->cursor_visible = visible;
5356 }
5357 /* and commit changes on next vblank */
5358 I915_WRITE(CURBASE(pipe), base);
5359 }
5360
5361 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5362 {
5363 struct drm_device *dev = crtc->dev;
5364 struct drm_i915_private *dev_priv = dev->dev_private;
5365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5366 int pipe = intel_crtc->pipe;
5367 bool visible = base != 0;
5368
5369 if (intel_crtc->cursor_visible != visible) {
5370 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5371 if (base) {
5372 cntl &= ~CURSOR_MODE;
5373 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5374 } else {
5375 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5376 cntl |= CURSOR_MODE_DISABLE;
5377 }
5378 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5379
5380 intel_crtc->cursor_visible = visible;
5381 }
5382 /* and commit changes on next vblank */
5383 I915_WRITE(CURBASE_IVB(pipe), base);
5384 }
5385
5386 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5387 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5388 bool on)
5389 {
5390 struct drm_device *dev = crtc->dev;
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5393 int pipe = intel_crtc->pipe;
5394 int x = intel_crtc->cursor_x;
5395 int y = intel_crtc->cursor_y;
5396 u32 base, pos;
5397 bool visible;
5398
5399 pos = 0;
5400
5401 if (on && crtc->enabled && crtc->fb) {
5402 base = intel_crtc->cursor_addr;
5403 if (x > (int) crtc->fb->width)
5404 base = 0;
5405
5406 if (y > (int) crtc->fb->height)
5407 base = 0;
5408 } else
5409 base = 0;
5410
5411 if (x < 0) {
5412 if (x + intel_crtc->cursor_width < 0)
5413 base = 0;
5414
5415 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5416 x = -x;
5417 }
5418 pos |= x << CURSOR_X_SHIFT;
5419
5420 if (y < 0) {
5421 if (y + intel_crtc->cursor_height < 0)
5422 base = 0;
5423
5424 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5425 y = -y;
5426 }
5427 pos |= y << CURSOR_Y_SHIFT;
5428
5429 visible = base != 0;
5430 if (!visible && !intel_crtc->cursor_visible)
5431 return;
5432
5433 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
5434 I915_WRITE(CURPOS_IVB(pipe), pos);
5435 ivb_update_cursor(crtc, base);
5436 } else {
5437 I915_WRITE(CURPOS(pipe), pos);
5438 if (IS_845G(dev) || IS_I865G(dev))
5439 i845_update_cursor(crtc, base);
5440 else
5441 i9xx_update_cursor(crtc, base);
5442 }
5443 }
5444
5445 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
5446 struct drm_file *file,
5447 uint32_t handle,
5448 uint32_t width, uint32_t height)
5449 {
5450 struct drm_device *dev = crtc->dev;
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5453 struct drm_i915_gem_object *obj;
5454 uint32_t addr;
5455 int ret;
5456
5457 DRM_DEBUG_KMS("\n");
5458
5459 /* if we want to turn off the cursor ignore width and height */
5460 if (!handle) {
5461 DRM_DEBUG_KMS("cursor off\n");
5462 addr = 0;
5463 obj = NULL;
5464 mutex_lock(&dev->struct_mutex);
5465 goto finish;
5466 }
5467
5468 /* Currently we only support 64x64 cursors */
5469 if (width != 64 || height != 64) {
5470 DRM_ERROR("we currently only support 64x64 cursors\n");
5471 return -EINVAL;
5472 }
5473
5474 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
5475 if (&obj->base == NULL)
5476 return -ENOENT;
5477
5478 if (obj->base.size < width * height * 4) {
5479 DRM_ERROR("buffer is to small\n");
5480 ret = -ENOMEM;
5481 goto fail;
5482 }
5483
5484 /* we only need to pin inside GTT if cursor is non-phy */
5485 mutex_lock(&dev->struct_mutex);
5486 if (!dev_priv->info->cursor_needs_physical) {
5487 if (obj->tiling_mode) {
5488 DRM_ERROR("cursor cannot be tiled\n");
5489 ret = -EINVAL;
5490 goto fail_locked;
5491 }
5492
5493 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
5494 if (ret) {
5495 DRM_ERROR("failed to move cursor bo into the GTT\n");
5496 goto fail_locked;
5497 }
5498
5499 ret = i915_gem_object_put_fence(obj);
5500 if (ret) {
5501 DRM_ERROR("failed to release fence for cursor");
5502 goto fail_unpin;
5503 }
5504
5505 addr = obj->gtt_offset;
5506 } else {
5507 int align = IS_I830(dev) ? 16 * 1024 : 256;
5508 ret = i915_gem_attach_phys_object(dev, obj,
5509 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5510 align);
5511 if (ret) {
5512 DRM_ERROR("failed to attach phys object\n");
5513 goto fail_locked;
5514 }
5515 addr = obj->phys_obj->handle->busaddr;
5516 }
5517
5518 if (IS_GEN2(dev))
5519 I915_WRITE(CURSIZE, (height << 12) | width);
5520
5521 finish:
5522 if (intel_crtc->cursor_bo) {
5523 if (dev_priv->info->cursor_needs_physical) {
5524 if (intel_crtc->cursor_bo != obj)
5525 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5526 } else
5527 i915_gem_object_unpin(intel_crtc->cursor_bo);
5528 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
5529 }
5530
5531 mutex_unlock(&dev->struct_mutex);
5532
5533 intel_crtc->cursor_addr = addr;
5534 intel_crtc->cursor_bo = obj;
5535 intel_crtc->cursor_width = width;
5536 intel_crtc->cursor_height = height;
5537
5538 intel_crtc_update_cursor(crtc, true);
5539
5540 return 0;
5541 fail_unpin:
5542 i915_gem_object_unpin(obj);
5543 fail_locked:
5544 mutex_unlock(&dev->struct_mutex);
5545 fail:
5546 drm_gem_object_unreference_unlocked(&obj->base);
5547 return ret;
5548 }
5549
5550 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5551 {
5552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5553
5554 intel_crtc->cursor_x = x;
5555 intel_crtc->cursor_y = y;
5556
5557 intel_crtc_update_cursor(crtc, true);
5558
5559 return 0;
5560 }
5561
5562 /** Sets the color ramps on behalf of RandR */
5563 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5564 u16 blue, int regno)
5565 {
5566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5567
5568 intel_crtc->lut_r[regno] = red >> 8;
5569 intel_crtc->lut_g[regno] = green >> 8;
5570 intel_crtc->lut_b[regno] = blue >> 8;
5571 }
5572
5573 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5574 u16 *blue, int regno)
5575 {
5576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5577
5578 *red = intel_crtc->lut_r[regno] << 8;
5579 *green = intel_crtc->lut_g[regno] << 8;
5580 *blue = intel_crtc->lut_b[regno] << 8;
5581 }
5582
5583 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
5584 u16 *blue, uint32_t start, uint32_t size)
5585 {
5586 int end = (start + size > 256) ? 256 : start + size, i;
5587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5588
5589 for (i = start; i < end; i++) {
5590 intel_crtc->lut_r[i] = red[i] >> 8;
5591 intel_crtc->lut_g[i] = green[i] >> 8;
5592 intel_crtc->lut_b[i] = blue[i] >> 8;
5593 }
5594
5595 intel_crtc_load_lut(crtc);
5596 }
5597
5598 /**
5599 * Get a pipe with a simple mode set on it for doing load-based monitor
5600 * detection.
5601 *
5602 * It will be up to the load-detect code to adjust the pipe as appropriate for
5603 * its requirements. The pipe will be connected to no other encoders.
5604 *
5605 * Currently this code will only succeed if there is a pipe with no encoders
5606 * configured for it. In the future, it could choose to temporarily disable
5607 * some outputs to free up a pipe for its use.
5608 *
5609 * \return crtc, or NULL if no pipes are available.
5610 */
5611
5612 /* VESA 640x480x72Hz mode to set on the pipe */
5613 static struct drm_display_mode load_detect_mode = {
5614 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5615 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5616 };
5617
5618 static struct drm_framebuffer *
5619 intel_framebuffer_create(struct drm_device *dev,
5620 struct drm_mode_fb_cmd2 *mode_cmd,
5621 struct drm_i915_gem_object *obj)
5622 {
5623 struct intel_framebuffer *intel_fb;
5624 int ret;
5625
5626 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5627 if (!intel_fb) {
5628 drm_gem_object_unreference_unlocked(&obj->base);
5629 return ERR_PTR(-ENOMEM);
5630 }
5631
5632 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5633 if (ret) {
5634 drm_gem_object_unreference_unlocked(&obj->base);
5635 kfree(intel_fb);
5636 return ERR_PTR(ret);
5637 }
5638
5639 return &intel_fb->base;
5640 }
5641
5642 static u32
5643 intel_framebuffer_pitch_for_width(int width, int bpp)
5644 {
5645 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5646 return ALIGN(pitch, 64);
5647 }
5648
5649 static u32
5650 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5651 {
5652 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5653 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5654 }
5655
5656 static struct drm_framebuffer *
5657 intel_framebuffer_create_for_mode(struct drm_device *dev,
5658 struct drm_display_mode *mode,
5659 int depth, int bpp)
5660 {
5661 struct drm_i915_gem_object *obj;
5662 struct drm_mode_fb_cmd2 mode_cmd;
5663
5664 obj = i915_gem_alloc_object(dev,
5665 intel_framebuffer_size_for_mode(mode, bpp));
5666 if (obj == NULL)
5667 return ERR_PTR(-ENOMEM);
5668
5669 mode_cmd.width = mode->hdisplay;
5670 mode_cmd.height = mode->vdisplay;
5671 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5672 bpp);
5673 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
5674
5675 return intel_framebuffer_create(dev, &mode_cmd, obj);
5676 }
5677
5678 static struct drm_framebuffer *
5679 mode_fits_in_fbdev(struct drm_device *dev,
5680 struct drm_display_mode *mode)
5681 {
5682 struct drm_i915_private *dev_priv = dev->dev_private;
5683 struct drm_i915_gem_object *obj;
5684 struct drm_framebuffer *fb;
5685
5686 if (dev_priv->fbdev == NULL)
5687 return NULL;
5688
5689 obj = dev_priv->fbdev->ifb.obj;
5690 if (obj == NULL)
5691 return NULL;
5692
5693 fb = &dev_priv->fbdev->ifb.base;
5694 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5695 fb->bits_per_pixel))
5696 return NULL;
5697
5698 if (obj->base.size < mode->vdisplay * fb->pitches[0])
5699 return NULL;
5700
5701 return fb;
5702 }
5703
5704 bool intel_get_load_detect_pipe(struct drm_connector *connector,
5705 struct drm_display_mode *mode,
5706 struct intel_load_detect_pipe *old)
5707 {
5708 struct intel_crtc *intel_crtc;
5709 struct intel_encoder *intel_encoder =
5710 intel_attached_encoder(connector);
5711 struct drm_crtc *possible_crtc;
5712 struct drm_encoder *encoder = &intel_encoder->base;
5713 struct drm_crtc *crtc = NULL;
5714 struct drm_device *dev = encoder->dev;
5715 struct drm_framebuffer *old_fb;
5716 int i = -1;
5717
5718 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5719 connector->base.id, drm_get_connector_name(connector),
5720 encoder->base.id, drm_get_encoder_name(encoder));
5721
5722 /*
5723 * Algorithm gets a little messy:
5724 *
5725 * - if the connector already has an assigned crtc, use it (but make
5726 * sure it's on first)
5727 *
5728 * - try to find the first unused crtc that can drive this connector,
5729 * and use that if we find one
5730 */
5731
5732 /* See if we already have a CRTC for this connector */
5733 if (encoder->crtc) {
5734 crtc = encoder->crtc;
5735
5736 old->dpms_mode = connector->dpms;
5737 old->load_detect_temp = false;
5738
5739 /* Make sure the crtc and connector are running */
5740 if (connector->dpms != DRM_MODE_DPMS_ON)
5741 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
5742
5743 return true;
5744 }
5745
5746 /* Find an unused one (if possible) */
5747 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5748 i++;
5749 if (!(encoder->possible_crtcs & (1 << i)))
5750 continue;
5751 if (!possible_crtc->enabled) {
5752 crtc = possible_crtc;
5753 break;
5754 }
5755 }
5756
5757 /*
5758 * If we didn't find an unused CRTC, don't use any.
5759 */
5760 if (!crtc) {
5761 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5762 return false;
5763 }
5764
5765 encoder->crtc = crtc;
5766 connector->encoder = encoder;
5767
5768 intel_crtc = to_intel_crtc(crtc);
5769 old->dpms_mode = connector->dpms;
5770 old->load_detect_temp = true;
5771 old->release_fb = NULL;
5772
5773 if (!mode)
5774 mode = &load_detect_mode;
5775
5776 old_fb = crtc->fb;
5777
5778 /* We need a framebuffer large enough to accommodate all accesses
5779 * that the plane may generate whilst we perform load detection.
5780 * We can not rely on the fbcon either being present (we get called
5781 * during its initialisation to detect all boot displays, or it may
5782 * not even exist) or that it is large enough to satisfy the
5783 * requested mode.
5784 */
5785 crtc->fb = mode_fits_in_fbdev(dev, mode);
5786 if (crtc->fb == NULL) {
5787 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5788 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5789 old->release_fb = crtc->fb;
5790 } else
5791 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5792 if (IS_ERR(crtc->fb)) {
5793 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5794 goto fail;
5795 }
5796
5797 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
5798 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5799 if (old->release_fb)
5800 old->release_fb->funcs->destroy(old->release_fb);
5801 goto fail;
5802 }
5803
5804 /* let the connector get through one full cycle before testing */
5805 intel_wait_for_vblank(dev, intel_crtc->pipe);
5806
5807 return true;
5808 fail:
5809 connector->encoder = NULL;
5810 encoder->crtc = NULL;
5811 crtc->fb = old_fb;
5812 return false;
5813 }
5814
5815 void intel_release_load_detect_pipe(struct drm_connector *connector,
5816 struct intel_load_detect_pipe *old)
5817 {
5818 struct intel_encoder *intel_encoder =
5819 intel_attached_encoder(connector);
5820 struct drm_encoder *encoder = &intel_encoder->base;
5821 struct drm_device *dev = encoder->dev;
5822
5823 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5824 connector->base.id, drm_get_connector_name(connector),
5825 encoder->base.id, drm_get_encoder_name(encoder));
5826
5827 if (old->load_detect_temp) {
5828 connector->encoder = NULL;
5829 encoder->crtc = NULL;
5830 drm_helper_disable_unused_functions(dev);
5831
5832 if (old->release_fb)
5833 old->release_fb->funcs->destroy(old->release_fb);
5834
5835 return;
5836 }
5837
5838 /* Switch crtc and encoder back off if necessary */
5839 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5840 connector->funcs->dpms(connector, old->dpms_mode);
5841 }
5842
5843 /* Returns the clock of the currently programmed mode of the given pipe. */
5844 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5845 {
5846 struct drm_i915_private *dev_priv = dev->dev_private;
5847 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5848 int pipe = intel_crtc->pipe;
5849 u32 dpll = I915_READ(DPLL(pipe));
5850 u32 fp;
5851 intel_clock_t clock;
5852
5853 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
5854 fp = I915_READ(FP0(pipe));
5855 else
5856 fp = I915_READ(FP1(pipe));
5857
5858 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
5859 if (IS_PINEVIEW(dev)) {
5860 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5861 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
5862 } else {
5863 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5864 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5865 }
5866
5867 if (!IS_GEN2(dev)) {
5868 if (IS_PINEVIEW(dev))
5869 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5870 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
5871 else
5872 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
5873 DPLL_FPA01_P1_POST_DIV_SHIFT);
5874
5875 switch (dpll & DPLL_MODE_MASK) {
5876 case DPLLB_MODE_DAC_SERIAL:
5877 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5878 5 : 10;
5879 break;
5880 case DPLLB_MODE_LVDS:
5881 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5882 7 : 14;
5883 break;
5884 default:
5885 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5886 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5887 return 0;
5888 }
5889
5890 /* XXX: Handle the 100Mhz refclk */
5891 intel_clock(dev, 96000, &clock);
5892 } else {
5893 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5894
5895 if (is_lvds) {
5896 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5897 DPLL_FPA01_P1_POST_DIV_SHIFT);
5898 clock.p2 = 14;
5899
5900 if ((dpll & PLL_REF_INPUT_MASK) ==
5901 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5902 /* XXX: might not be 66MHz */
5903 intel_clock(dev, 66000, &clock);
5904 } else
5905 intel_clock(dev, 48000, &clock);
5906 } else {
5907 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5908 clock.p1 = 2;
5909 else {
5910 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5911 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5912 }
5913 if (dpll & PLL_P2_DIVIDE_BY_4)
5914 clock.p2 = 4;
5915 else
5916 clock.p2 = 2;
5917
5918 intel_clock(dev, 48000, &clock);
5919 }
5920 }
5921
5922 /* XXX: It would be nice to validate the clocks, but we can't reuse
5923 * i830PllIsValid() because it relies on the xf86_config connector
5924 * configuration being accurate, which it isn't necessarily.
5925 */
5926
5927 return clock.dot;
5928 }
5929
5930 /** Returns the currently programmed mode of the given pipe. */
5931 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5932 struct drm_crtc *crtc)
5933 {
5934 struct drm_i915_private *dev_priv = dev->dev_private;
5935 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5936 int pipe = intel_crtc->pipe;
5937 struct drm_display_mode *mode;
5938 int htot = I915_READ(HTOTAL(pipe));
5939 int hsync = I915_READ(HSYNC(pipe));
5940 int vtot = I915_READ(VTOTAL(pipe));
5941 int vsync = I915_READ(VSYNC(pipe));
5942
5943 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5944 if (!mode)
5945 return NULL;
5946
5947 mode->clock = intel_crtc_clock_get(dev, crtc);
5948 mode->hdisplay = (htot & 0xffff) + 1;
5949 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5950 mode->hsync_start = (hsync & 0xffff) + 1;
5951 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5952 mode->vdisplay = (vtot & 0xffff) + 1;
5953 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5954 mode->vsync_start = (vsync & 0xffff) + 1;
5955 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5956
5957 drm_mode_set_name(mode);
5958
5959 return mode;
5960 }
5961
5962 static void intel_increase_pllclock(struct drm_crtc *crtc)
5963 {
5964 struct drm_device *dev = crtc->dev;
5965 drm_i915_private_t *dev_priv = dev->dev_private;
5966 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5967 int pipe = intel_crtc->pipe;
5968 int dpll_reg = DPLL(pipe);
5969 int dpll;
5970
5971 if (HAS_PCH_SPLIT(dev))
5972 return;
5973
5974 if (!dev_priv->lvds_downclock_avail)
5975 return;
5976
5977 dpll = I915_READ(dpll_reg);
5978 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5979 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5980
5981 assert_panel_unlocked(dev_priv, pipe);
5982
5983 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5984 I915_WRITE(dpll_reg, dpll);
5985 intel_wait_for_vblank(dev, pipe);
5986
5987 dpll = I915_READ(dpll_reg);
5988 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5989 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5990 }
5991 }
5992
5993 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5994 {
5995 struct drm_device *dev = crtc->dev;
5996 drm_i915_private_t *dev_priv = dev->dev_private;
5997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5998
5999 if (HAS_PCH_SPLIT(dev))
6000 return;
6001
6002 if (!dev_priv->lvds_downclock_avail)
6003 return;
6004
6005 /*
6006 * Since this is called by a timer, we should never get here in
6007 * the manual case.
6008 */
6009 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6010 int pipe = intel_crtc->pipe;
6011 int dpll_reg = DPLL(pipe);
6012 int dpll;
6013
6014 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6015
6016 assert_panel_unlocked(dev_priv, pipe);
6017
6018 dpll = I915_READ(dpll_reg);
6019 dpll |= DISPLAY_RATE_SELECT_FPA1;
6020 I915_WRITE(dpll_reg, dpll);
6021 intel_wait_for_vblank(dev, pipe);
6022 dpll = I915_READ(dpll_reg);
6023 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6024 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6025 }
6026
6027 }
6028
6029 void intel_mark_busy(struct drm_device *dev)
6030 {
6031 i915_update_gfx_val(dev->dev_private);
6032 }
6033
6034 void intel_mark_idle(struct drm_device *dev)
6035 {
6036 }
6037
6038 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6039 {
6040 struct drm_device *dev = obj->base.dev;
6041 struct drm_crtc *crtc;
6042
6043 if (!i915_powersave)
6044 return;
6045
6046 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6047 if (!crtc->fb)
6048 continue;
6049
6050 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6051 intel_increase_pllclock(crtc);
6052 }
6053 }
6054
6055 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6056 {
6057 struct drm_device *dev = obj->base.dev;
6058 struct drm_crtc *crtc;
6059
6060 if (!i915_powersave)
6061 return;
6062
6063 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6064 if (!crtc->fb)
6065 continue;
6066
6067 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6068 intel_decrease_pllclock(crtc);
6069 }
6070 }
6071
6072 static void intel_crtc_destroy(struct drm_crtc *crtc)
6073 {
6074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6075 struct drm_device *dev = crtc->dev;
6076 struct intel_unpin_work *work;
6077 unsigned long flags;
6078
6079 spin_lock_irqsave(&dev->event_lock, flags);
6080 work = intel_crtc->unpin_work;
6081 intel_crtc->unpin_work = NULL;
6082 spin_unlock_irqrestore(&dev->event_lock, flags);
6083
6084 if (work) {
6085 cancel_work_sync(&work->work);
6086 kfree(work);
6087 }
6088
6089 drm_crtc_cleanup(crtc);
6090
6091 kfree(intel_crtc);
6092 }
6093
6094 static void intel_unpin_work_fn(struct work_struct *__work)
6095 {
6096 struct intel_unpin_work *work =
6097 container_of(__work, struct intel_unpin_work, work);
6098
6099 mutex_lock(&work->dev->struct_mutex);
6100 intel_unpin_fb_obj(work->old_fb_obj);
6101 drm_gem_object_unreference(&work->pending_flip_obj->base);
6102 drm_gem_object_unreference(&work->old_fb_obj->base);
6103
6104 intel_update_fbc(work->dev);
6105 mutex_unlock(&work->dev->struct_mutex);
6106 kfree(work);
6107 }
6108
6109 static void do_intel_finish_page_flip(struct drm_device *dev,
6110 struct drm_crtc *crtc)
6111 {
6112 drm_i915_private_t *dev_priv = dev->dev_private;
6113 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6114 struct intel_unpin_work *work;
6115 struct drm_i915_gem_object *obj;
6116 struct drm_pending_vblank_event *e;
6117 struct timeval tnow, tvbl;
6118 unsigned long flags;
6119
6120 /* Ignore early vblank irqs */
6121 if (intel_crtc == NULL)
6122 return;
6123
6124 do_gettimeofday(&tnow);
6125
6126 spin_lock_irqsave(&dev->event_lock, flags);
6127 work = intel_crtc->unpin_work;
6128 if (work == NULL || !work->pending) {
6129 spin_unlock_irqrestore(&dev->event_lock, flags);
6130 return;
6131 }
6132
6133 intel_crtc->unpin_work = NULL;
6134
6135 if (work->event) {
6136 e = work->event;
6137 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6138
6139 /* Called before vblank count and timestamps have
6140 * been updated for the vblank interval of flip
6141 * completion? Need to increment vblank count and
6142 * add one videorefresh duration to returned timestamp
6143 * to account for this. We assume this happened if we
6144 * get called over 0.9 frame durations after the last
6145 * timestamped vblank.
6146 *
6147 * This calculation can not be used with vrefresh rates
6148 * below 5Hz (10Hz to be on the safe side) without
6149 * promoting to 64 integers.
6150 */
6151 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6152 9 * crtc->framedur_ns) {
6153 e->event.sequence++;
6154 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6155 crtc->framedur_ns);
6156 }
6157
6158 e->event.tv_sec = tvbl.tv_sec;
6159 e->event.tv_usec = tvbl.tv_usec;
6160
6161 list_add_tail(&e->base.link,
6162 &e->base.file_priv->event_list);
6163 wake_up_interruptible(&e->base.file_priv->event_wait);
6164 }
6165
6166 drm_vblank_put(dev, intel_crtc->pipe);
6167
6168 spin_unlock_irqrestore(&dev->event_lock, flags);
6169
6170 obj = work->old_fb_obj;
6171
6172 atomic_clear_mask(1 << intel_crtc->plane,
6173 &obj->pending_flip.counter);
6174 if (atomic_read(&obj->pending_flip) == 0)
6175 wake_up(&dev_priv->pending_flip_queue);
6176
6177 schedule_work(&work->work);
6178
6179 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6180 }
6181
6182 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6183 {
6184 drm_i915_private_t *dev_priv = dev->dev_private;
6185 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6186
6187 do_intel_finish_page_flip(dev, crtc);
6188 }
6189
6190 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6191 {
6192 drm_i915_private_t *dev_priv = dev->dev_private;
6193 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6194
6195 do_intel_finish_page_flip(dev, crtc);
6196 }
6197
6198 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6199 {
6200 drm_i915_private_t *dev_priv = dev->dev_private;
6201 struct intel_crtc *intel_crtc =
6202 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6203 unsigned long flags;
6204
6205 spin_lock_irqsave(&dev->event_lock, flags);
6206 if (intel_crtc->unpin_work) {
6207 if ((++intel_crtc->unpin_work->pending) > 1)
6208 DRM_ERROR("Prepared flip multiple times\n");
6209 } else {
6210 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6211 }
6212 spin_unlock_irqrestore(&dev->event_lock, flags);
6213 }
6214
6215 static int intel_gen2_queue_flip(struct drm_device *dev,
6216 struct drm_crtc *crtc,
6217 struct drm_framebuffer *fb,
6218 struct drm_i915_gem_object *obj)
6219 {
6220 struct drm_i915_private *dev_priv = dev->dev_private;
6221 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6222 u32 flip_mask;
6223 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6224 int ret;
6225
6226 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6227 if (ret)
6228 goto err;
6229
6230 ret = intel_ring_begin(ring, 6);
6231 if (ret)
6232 goto err_unpin;
6233
6234 /* Can't queue multiple flips, so wait for the previous
6235 * one to finish before executing the next.
6236 */
6237 if (intel_crtc->plane)
6238 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6239 else
6240 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6241 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6242 intel_ring_emit(ring, MI_NOOP);
6243 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6244 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6245 intel_ring_emit(ring, fb->pitches[0]);
6246 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6247 intel_ring_emit(ring, 0); /* aux display base address, unused */
6248 intel_ring_advance(ring);
6249 return 0;
6250
6251 err_unpin:
6252 intel_unpin_fb_obj(obj);
6253 err:
6254 return ret;
6255 }
6256
6257 static int intel_gen3_queue_flip(struct drm_device *dev,
6258 struct drm_crtc *crtc,
6259 struct drm_framebuffer *fb,
6260 struct drm_i915_gem_object *obj)
6261 {
6262 struct drm_i915_private *dev_priv = dev->dev_private;
6263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6264 u32 flip_mask;
6265 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6266 int ret;
6267
6268 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6269 if (ret)
6270 goto err;
6271
6272 ret = intel_ring_begin(ring, 6);
6273 if (ret)
6274 goto err_unpin;
6275
6276 if (intel_crtc->plane)
6277 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6278 else
6279 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6280 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6281 intel_ring_emit(ring, MI_NOOP);
6282 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6283 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6284 intel_ring_emit(ring, fb->pitches[0]);
6285 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6286 intel_ring_emit(ring, MI_NOOP);
6287
6288 intel_ring_advance(ring);
6289 return 0;
6290
6291 err_unpin:
6292 intel_unpin_fb_obj(obj);
6293 err:
6294 return ret;
6295 }
6296
6297 static int intel_gen4_queue_flip(struct drm_device *dev,
6298 struct drm_crtc *crtc,
6299 struct drm_framebuffer *fb,
6300 struct drm_i915_gem_object *obj)
6301 {
6302 struct drm_i915_private *dev_priv = dev->dev_private;
6303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6304 uint32_t pf, pipesrc;
6305 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6306 int ret;
6307
6308 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6309 if (ret)
6310 goto err;
6311
6312 ret = intel_ring_begin(ring, 4);
6313 if (ret)
6314 goto err_unpin;
6315
6316 /* i965+ uses the linear or tiled offsets from the
6317 * Display Registers (which do not change across a page-flip)
6318 * so we need only reprogram the base address.
6319 */
6320 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6321 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6322 intel_ring_emit(ring, fb->pitches[0]);
6323 intel_ring_emit(ring,
6324 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6325 obj->tiling_mode);
6326
6327 /* XXX Enabling the panel-fitter across page-flip is so far
6328 * untested on non-native modes, so ignore it for now.
6329 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6330 */
6331 pf = 0;
6332 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6333 intel_ring_emit(ring, pf | pipesrc);
6334 intel_ring_advance(ring);
6335 return 0;
6336
6337 err_unpin:
6338 intel_unpin_fb_obj(obj);
6339 err:
6340 return ret;
6341 }
6342
6343 static int intel_gen6_queue_flip(struct drm_device *dev,
6344 struct drm_crtc *crtc,
6345 struct drm_framebuffer *fb,
6346 struct drm_i915_gem_object *obj)
6347 {
6348 struct drm_i915_private *dev_priv = dev->dev_private;
6349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6350 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6351 uint32_t pf, pipesrc;
6352 int ret;
6353
6354 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6355 if (ret)
6356 goto err;
6357
6358 ret = intel_ring_begin(ring, 4);
6359 if (ret)
6360 goto err_unpin;
6361
6362 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6363 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6364 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
6365 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6366
6367 /* Contrary to the suggestions in the documentation,
6368 * "Enable Panel Fitter" does not seem to be required when page
6369 * flipping with a non-native mode, and worse causes a normal
6370 * modeset to fail.
6371 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6372 */
6373 pf = 0;
6374 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6375 intel_ring_emit(ring, pf | pipesrc);
6376 intel_ring_advance(ring);
6377 return 0;
6378
6379 err_unpin:
6380 intel_unpin_fb_obj(obj);
6381 err:
6382 return ret;
6383 }
6384
6385 /*
6386 * On gen7 we currently use the blit ring because (in early silicon at least)
6387 * the render ring doesn't give us interrpts for page flip completion, which
6388 * means clients will hang after the first flip is queued. Fortunately the
6389 * blit ring generates interrupts properly, so use it instead.
6390 */
6391 static int intel_gen7_queue_flip(struct drm_device *dev,
6392 struct drm_crtc *crtc,
6393 struct drm_framebuffer *fb,
6394 struct drm_i915_gem_object *obj)
6395 {
6396 struct drm_i915_private *dev_priv = dev->dev_private;
6397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
6399 uint32_t plane_bit = 0;
6400 int ret;
6401
6402 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6403 if (ret)
6404 goto err;
6405
6406 switch(intel_crtc->plane) {
6407 case PLANE_A:
6408 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6409 break;
6410 case PLANE_B:
6411 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6412 break;
6413 case PLANE_C:
6414 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6415 break;
6416 default:
6417 WARN_ONCE(1, "unknown plane in flip command\n");
6418 ret = -ENODEV;
6419 goto err_unpin;
6420 }
6421
6422 ret = intel_ring_begin(ring, 4);
6423 if (ret)
6424 goto err_unpin;
6425
6426 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
6427 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
6428 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6429 intel_ring_emit(ring, (MI_NOOP));
6430 intel_ring_advance(ring);
6431 return 0;
6432
6433 err_unpin:
6434 intel_unpin_fb_obj(obj);
6435 err:
6436 return ret;
6437 }
6438
6439 static int intel_default_queue_flip(struct drm_device *dev,
6440 struct drm_crtc *crtc,
6441 struct drm_framebuffer *fb,
6442 struct drm_i915_gem_object *obj)
6443 {
6444 return -ENODEV;
6445 }
6446
6447 static int intel_crtc_page_flip(struct drm_crtc *crtc,
6448 struct drm_framebuffer *fb,
6449 struct drm_pending_vblank_event *event)
6450 {
6451 struct drm_device *dev = crtc->dev;
6452 struct drm_i915_private *dev_priv = dev->dev_private;
6453 struct intel_framebuffer *intel_fb;
6454 struct drm_i915_gem_object *obj;
6455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6456 struct intel_unpin_work *work;
6457 unsigned long flags;
6458 int ret;
6459
6460 /* Can't change pixel format via MI display flips. */
6461 if (fb->pixel_format != crtc->fb->pixel_format)
6462 return -EINVAL;
6463
6464 /*
6465 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6466 * Note that pitch changes could also affect these register.
6467 */
6468 if (INTEL_INFO(dev)->gen > 3 &&
6469 (fb->offsets[0] != crtc->fb->offsets[0] ||
6470 fb->pitches[0] != crtc->fb->pitches[0]))
6471 return -EINVAL;
6472
6473 work = kzalloc(sizeof *work, GFP_KERNEL);
6474 if (work == NULL)
6475 return -ENOMEM;
6476
6477 work->event = event;
6478 work->dev = crtc->dev;
6479 intel_fb = to_intel_framebuffer(crtc->fb);
6480 work->old_fb_obj = intel_fb->obj;
6481 INIT_WORK(&work->work, intel_unpin_work_fn);
6482
6483 ret = drm_vblank_get(dev, intel_crtc->pipe);
6484 if (ret)
6485 goto free_work;
6486
6487 /* We borrow the event spin lock for protecting unpin_work */
6488 spin_lock_irqsave(&dev->event_lock, flags);
6489 if (intel_crtc->unpin_work) {
6490 spin_unlock_irqrestore(&dev->event_lock, flags);
6491 kfree(work);
6492 drm_vblank_put(dev, intel_crtc->pipe);
6493
6494 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6495 return -EBUSY;
6496 }
6497 intel_crtc->unpin_work = work;
6498 spin_unlock_irqrestore(&dev->event_lock, flags);
6499
6500 intel_fb = to_intel_framebuffer(fb);
6501 obj = intel_fb->obj;
6502
6503 ret = i915_mutex_lock_interruptible(dev);
6504 if (ret)
6505 goto cleanup;
6506
6507 /* Reference the objects for the scheduled work. */
6508 drm_gem_object_reference(&work->old_fb_obj->base);
6509 drm_gem_object_reference(&obj->base);
6510
6511 crtc->fb = fb;
6512
6513 work->pending_flip_obj = obj;
6514
6515 work->enable_stall_check = true;
6516
6517 /* Block clients from rendering to the new back buffer until
6518 * the flip occurs and the object is no longer visible.
6519 */
6520 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6521
6522 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6523 if (ret)
6524 goto cleanup_pending;
6525
6526 intel_disable_fbc(dev);
6527 intel_mark_fb_busy(obj);
6528 mutex_unlock(&dev->struct_mutex);
6529
6530 trace_i915_flip_request(intel_crtc->plane, obj);
6531
6532 return 0;
6533
6534 cleanup_pending:
6535 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
6536 drm_gem_object_unreference(&work->old_fb_obj->base);
6537 drm_gem_object_unreference(&obj->base);
6538 mutex_unlock(&dev->struct_mutex);
6539
6540 cleanup:
6541 spin_lock_irqsave(&dev->event_lock, flags);
6542 intel_crtc->unpin_work = NULL;
6543 spin_unlock_irqrestore(&dev->event_lock, flags);
6544
6545 drm_vblank_put(dev, intel_crtc->pipe);
6546 free_work:
6547 kfree(work);
6548
6549 return ret;
6550 }
6551
6552 static void intel_sanitize_modesetting(struct drm_device *dev,
6553 int pipe, int plane)
6554 {
6555 struct drm_i915_private *dev_priv = dev->dev_private;
6556 u32 reg, val;
6557 int i;
6558
6559 /* Clear any frame start delays used for debugging left by the BIOS */
6560 for_each_pipe(i) {
6561 reg = PIPECONF(i);
6562 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6563 }
6564
6565 if (HAS_PCH_SPLIT(dev))
6566 return;
6567
6568 /* Who knows what state these registers were left in by the BIOS or
6569 * grub?
6570 *
6571 * If we leave the registers in a conflicting state (e.g. with the
6572 * display plane reading from the other pipe than the one we intend
6573 * to use) then when we attempt to teardown the active mode, we will
6574 * not disable the pipes and planes in the correct order -- leaving
6575 * a plane reading from a disabled pipe and possibly leading to
6576 * undefined behaviour.
6577 */
6578
6579 reg = DSPCNTR(plane);
6580 val = I915_READ(reg);
6581
6582 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6583 return;
6584 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6585 return;
6586
6587 /* This display plane is active and attached to the other CPU pipe. */
6588 pipe = !pipe;
6589
6590 /* Disable the plane and wait for it to stop reading from the pipe. */
6591 intel_disable_plane(dev_priv, plane, pipe);
6592 intel_disable_pipe(dev_priv, pipe);
6593 }
6594
6595 static void intel_crtc_reset(struct drm_crtc *crtc)
6596 {
6597 struct drm_device *dev = crtc->dev;
6598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6599
6600 /* Reset flags back to the 'unknown' status so that they
6601 * will be correctly set on the initial modeset.
6602 */
6603 intel_crtc->dpms_mode = -1;
6604
6605 /* We need to fix up any BIOS configuration that conflicts with
6606 * our expectations.
6607 */
6608 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6609 }
6610
6611 static struct drm_crtc_helper_funcs intel_helper_funcs = {
6612 .dpms = intel_crtc_dpms,
6613 .mode_fixup = intel_crtc_mode_fixup,
6614 .mode_set = intel_crtc_mode_set,
6615 .mode_set_base = intel_pipe_set_base,
6616 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6617 .load_lut = intel_crtc_load_lut,
6618 .disable = intel_crtc_disable,
6619 };
6620
6621 static const struct drm_crtc_funcs intel_crtc_funcs = {
6622 .reset = intel_crtc_reset,
6623 .cursor_set = intel_crtc_cursor_set,
6624 .cursor_move = intel_crtc_cursor_move,
6625 .gamma_set = intel_crtc_gamma_set,
6626 .set_config = drm_crtc_helper_set_config,
6627 .destroy = intel_crtc_destroy,
6628 .page_flip = intel_crtc_page_flip,
6629 };
6630
6631 static void intel_pch_pll_init(struct drm_device *dev)
6632 {
6633 drm_i915_private_t *dev_priv = dev->dev_private;
6634 int i;
6635
6636 if (dev_priv->num_pch_pll == 0) {
6637 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6638 return;
6639 }
6640
6641 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6642 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6643 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6644 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6645 }
6646 }
6647
6648 static void intel_crtc_init(struct drm_device *dev, int pipe)
6649 {
6650 drm_i915_private_t *dev_priv = dev->dev_private;
6651 struct intel_crtc *intel_crtc;
6652 int i;
6653
6654 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6655 if (intel_crtc == NULL)
6656 return;
6657
6658 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6659
6660 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
6661 for (i = 0; i < 256; i++) {
6662 intel_crtc->lut_r[i] = i;
6663 intel_crtc->lut_g[i] = i;
6664 intel_crtc->lut_b[i] = i;
6665 }
6666
6667 /* Swap pipes & planes for FBC on pre-965 */
6668 intel_crtc->pipe = pipe;
6669 intel_crtc->plane = pipe;
6670 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
6671 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6672 intel_crtc->plane = !pipe;
6673 }
6674
6675 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6676 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6677 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6678 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6679
6680 intel_crtc_reset(&intel_crtc->base);
6681 intel_crtc->active = true; /* force the pipe off on setup_init_config */
6682 intel_crtc->bpp = 24; /* default for pre-Ironlake */
6683
6684 intel_helper_funcs.prepare = dev_priv->display.crtc_disable;
6685 intel_helper_funcs.commit = dev_priv->display.crtc_enable;
6686
6687 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6688 }
6689
6690 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
6691 struct drm_file *file)
6692 {
6693 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
6694 struct drm_mode_object *drmmode_obj;
6695 struct intel_crtc *crtc;
6696
6697 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6698 return -ENODEV;
6699
6700 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6701 DRM_MODE_OBJECT_CRTC);
6702
6703 if (!drmmode_obj) {
6704 DRM_ERROR("no such CRTC id\n");
6705 return -EINVAL;
6706 }
6707
6708 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6709 pipe_from_crtc_id->pipe = crtc->pipe;
6710
6711 return 0;
6712 }
6713
6714 static int intel_encoder_clones(struct intel_encoder *encoder)
6715 {
6716 struct drm_device *dev = encoder->base.dev;
6717 struct intel_encoder *source_encoder;
6718 int index_mask = 0;
6719 int entry = 0;
6720
6721 list_for_each_entry(source_encoder,
6722 &dev->mode_config.encoder_list, base.head) {
6723
6724 if (encoder == source_encoder)
6725 index_mask |= (1 << entry);
6726
6727 /* Intel hw has only one MUX where enocoders could be cloned. */
6728 if (encoder->cloneable && source_encoder->cloneable)
6729 index_mask |= (1 << entry);
6730
6731 entry++;
6732 }
6733
6734 return index_mask;
6735 }
6736
6737 static bool has_edp_a(struct drm_device *dev)
6738 {
6739 struct drm_i915_private *dev_priv = dev->dev_private;
6740
6741 if (!IS_MOBILE(dev))
6742 return false;
6743
6744 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6745 return false;
6746
6747 if (IS_GEN5(dev) &&
6748 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6749 return false;
6750
6751 return true;
6752 }
6753
6754 static void intel_setup_outputs(struct drm_device *dev)
6755 {
6756 struct drm_i915_private *dev_priv = dev->dev_private;
6757 struct intel_encoder *encoder;
6758 bool dpd_is_edp = false;
6759 bool has_lvds;
6760
6761 has_lvds = intel_lvds_init(dev);
6762 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6763 /* disable the panel fitter on everything but LVDS */
6764 I915_WRITE(PFIT_CONTROL, 0);
6765 }
6766
6767 if (HAS_PCH_SPLIT(dev)) {
6768 dpd_is_edp = intel_dpd_is_edp(dev);
6769
6770 if (has_edp_a(dev))
6771 intel_dp_init(dev, DP_A, PORT_A);
6772
6773 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6774 intel_dp_init(dev, PCH_DP_D, PORT_D);
6775 }
6776
6777 intel_crt_init(dev);
6778
6779 if (IS_HASWELL(dev)) {
6780 int found;
6781
6782 /* Haswell uses DDI functions to detect digital outputs */
6783 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6784 /* DDI A only supports eDP */
6785 if (found)
6786 intel_ddi_init(dev, PORT_A);
6787
6788 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6789 * register */
6790 found = I915_READ(SFUSE_STRAP);
6791
6792 if (found & SFUSE_STRAP_DDIB_DETECTED)
6793 intel_ddi_init(dev, PORT_B);
6794 if (found & SFUSE_STRAP_DDIC_DETECTED)
6795 intel_ddi_init(dev, PORT_C);
6796 if (found & SFUSE_STRAP_DDID_DETECTED)
6797 intel_ddi_init(dev, PORT_D);
6798 } else if (HAS_PCH_SPLIT(dev)) {
6799 int found;
6800
6801 if (I915_READ(HDMIB) & PORT_DETECTED) {
6802 /* PCH SDVOB multiplex with HDMIB */
6803 found = intel_sdvo_init(dev, PCH_SDVOB, true);
6804 if (!found)
6805 intel_hdmi_init(dev, HDMIB, PORT_B);
6806 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6807 intel_dp_init(dev, PCH_DP_B, PORT_B);
6808 }
6809
6810 if (I915_READ(HDMIC) & PORT_DETECTED)
6811 intel_hdmi_init(dev, HDMIC, PORT_C);
6812
6813 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
6814 intel_hdmi_init(dev, HDMID, PORT_D);
6815
6816 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6817 intel_dp_init(dev, PCH_DP_C, PORT_C);
6818
6819 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6820 intel_dp_init(dev, PCH_DP_D, PORT_D);
6821 } else if (IS_VALLEYVIEW(dev)) {
6822 int found;
6823
6824 if (I915_READ(SDVOB) & PORT_DETECTED) {
6825 /* SDVOB multiplex with HDMIB */
6826 found = intel_sdvo_init(dev, SDVOB, true);
6827 if (!found)
6828 intel_hdmi_init(dev, SDVOB, PORT_B);
6829 if (!found && (I915_READ(DP_B) & DP_DETECTED))
6830 intel_dp_init(dev, DP_B, PORT_B);
6831 }
6832
6833 if (I915_READ(SDVOC) & PORT_DETECTED)
6834 intel_hdmi_init(dev, SDVOC, PORT_C);
6835
6836 /* Shares lanes with HDMI on SDVOC */
6837 if (I915_READ(DP_C) & DP_DETECTED)
6838 intel_dp_init(dev, DP_C, PORT_C);
6839 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
6840 bool found = false;
6841
6842 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6843 DRM_DEBUG_KMS("probing SDVOB\n");
6844 found = intel_sdvo_init(dev, SDVOB, true);
6845 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6846 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6847 intel_hdmi_init(dev, SDVOB, PORT_B);
6848 }
6849
6850 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6851 DRM_DEBUG_KMS("probing DP_B\n");
6852 intel_dp_init(dev, DP_B, PORT_B);
6853 }
6854 }
6855
6856 /* Before G4X SDVOC doesn't have its own detect register */
6857
6858 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6859 DRM_DEBUG_KMS("probing SDVOC\n");
6860 found = intel_sdvo_init(dev, SDVOC, false);
6861 }
6862
6863 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6864
6865 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6866 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6867 intel_hdmi_init(dev, SDVOC, PORT_C);
6868 }
6869 if (SUPPORTS_INTEGRATED_DP(dev)) {
6870 DRM_DEBUG_KMS("probing DP_C\n");
6871 intel_dp_init(dev, DP_C, PORT_C);
6872 }
6873 }
6874
6875 if (SUPPORTS_INTEGRATED_DP(dev) &&
6876 (I915_READ(DP_D) & DP_DETECTED)) {
6877 DRM_DEBUG_KMS("probing DP_D\n");
6878 intel_dp_init(dev, DP_D, PORT_D);
6879 }
6880 } else if (IS_GEN2(dev))
6881 intel_dvo_init(dev);
6882
6883 if (SUPPORTS_TV(dev))
6884 intel_tv_init(dev);
6885
6886 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6887 encoder->base.possible_crtcs = encoder->crtc_mask;
6888 encoder->base.possible_clones =
6889 intel_encoder_clones(encoder);
6890 }
6891
6892 /* disable all the possible outputs/crtcs before entering KMS mode */
6893 drm_helper_disable_unused_functions(dev);
6894
6895 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6896 ironlake_init_pch_refclk(dev);
6897 }
6898
6899 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6900 {
6901 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6902
6903 drm_framebuffer_cleanup(fb);
6904 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
6905
6906 kfree(intel_fb);
6907 }
6908
6909 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
6910 struct drm_file *file,
6911 unsigned int *handle)
6912 {
6913 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
6914 struct drm_i915_gem_object *obj = intel_fb->obj;
6915
6916 return drm_gem_handle_create(file, &obj->base, handle);
6917 }
6918
6919 static const struct drm_framebuffer_funcs intel_fb_funcs = {
6920 .destroy = intel_user_framebuffer_destroy,
6921 .create_handle = intel_user_framebuffer_create_handle,
6922 };
6923
6924 int intel_framebuffer_init(struct drm_device *dev,
6925 struct intel_framebuffer *intel_fb,
6926 struct drm_mode_fb_cmd2 *mode_cmd,
6927 struct drm_i915_gem_object *obj)
6928 {
6929 int ret;
6930
6931 if (obj->tiling_mode == I915_TILING_Y)
6932 return -EINVAL;
6933
6934 if (mode_cmd->pitches[0] & 63)
6935 return -EINVAL;
6936
6937 switch (mode_cmd->pixel_format) {
6938 case DRM_FORMAT_RGB332:
6939 case DRM_FORMAT_RGB565:
6940 case DRM_FORMAT_XRGB8888:
6941 case DRM_FORMAT_XBGR8888:
6942 case DRM_FORMAT_ARGB8888:
6943 case DRM_FORMAT_XRGB2101010:
6944 case DRM_FORMAT_ARGB2101010:
6945 /* RGB formats are common across chipsets */
6946 break;
6947 case DRM_FORMAT_YUYV:
6948 case DRM_FORMAT_UYVY:
6949 case DRM_FORMAT_YVYU:
6950 case DRM_FORMAT_VYUY:
6951 break;
6952 default:
6953 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6954 mode_cmd->pixel_format);
6955 return -EINVAL;
6956 }
6957
6958 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6959 if (ret) {
6960 DRM_ERROR("framebuffer init failed %d\n", ret);
6961 return ret;
6962 }
6963
6964 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
6965 intel_fb->obj = obj;
6966 return 0;
6967 }
6968
6969 static struct drm_framebuffer *
6970 intel_user_framebuffer_create(struct drm_device *dev,
6971 struct drm_file *filp,
6972 struct drm_mode_fb_cmd2 *mode_cmd)
6973 {
6974 struct drm_i915_gem_object *obj;
6975
6976 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6977 mode_cmd->handles[0]));
6978 if (&obj->base == NULL)
6979 return ERR_PTR(-ENOENT);
6980
6981 return intel_framebuffer_create(dev, mode_cmd, obj);
6982 }
6983
6984 static const struct drm_mode_config_funcs intel_mode_funcs = {
6985 .fb_create = intel_user_framebuffer_create,
6986 .output_poll_changed = intel_fb_output_poll_changed,
6987 };
6988
6989 /* Set up chip specific display functions */
6990 static void intel_init_display(struct drm_device *dev)
6991 {
6992 struct drm_i915_private *dev_priv = dev->dev_private;
6993
6994 /* We always want a DPMS function */
6995 if (HAS_PCH_SPLIT(dev)) {
6996 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
6997 dev_priv->display.crtc_enable = ironlake_crtc_enable;
6998 dev_priv->display.crtc_disable = ironlake_crtc_disable;
6999 dev_priv->display.off = ironlake_crtc_off;
7000 dev_priv->display.update_plane = ironlake_update_plane;
7001 } else {
7002 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
7003 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7004 dev_priv->display.crtc_disable = i9xx_crtc_disable;
7005 dev_priv->display.off = i9xx_crtc_off;
7006 dev_priv->display.update_plane = i9xx_update_plane;
7007 }
7008
7009 /* Returns the core display clock speed */
7010 if (IS_VALLEYVIEW(dev))
7011 dev_priv->display.get_display_clock_speed =
7012 valleyview_get_display_clock_speed;
7013 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
7014 dev_priv->display.get_display_clock_speed =
7015 i945_get_display_clock_speed;
7016 else if (IS_I915G(dev))
7017 dev_priv->display.get_display_clock_speed =
7018 i915_get_display_clock_speed;
7019 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
7020 dev_priv->display.get_display_clock_speed =
7021 i9xx_misc_get_display_clock_speed;
7022 else if (IS_I915GM(dev))
7023 dev_priv->display.get_display_clock_speed =
7024 i915gm_get_display_clock_speed;
7025 else if (IS_I865G(dev))
7026 dev_priv->display.get_display_clock_speed =
7027 i865_get_display_clock_speed;
7028 else if (IS_I85X(dev))
7029 dev_priv->display.get_display_clock_speed =
7030 i855_get_display_clock_speed;
7031 else /* 852, 830 */
7032 dev_priv->display.get_display_clock_speed =
7033 i830_get_display_clock_speed;
7034
7035 if (HAS_PCH_SPLIT(dev)) {
7036 if (IS_GEN5(dev)) {
7037 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
7038 dev_priv->display.write_eld = ironlake_write_eld;
7039 } else if (IS_GEN6(dev)) {
7040 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
7041 dev_priv->display.write_eld = ironlake_write_eld;
7042 } else if (IS_IVYBRIDGE(dev)) {
7043 /* FIXME: detect B0+ stepping and use auto training */
7044 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
7045 dev_priv->display.write_eld = ironlake_write_eld;
7046 } else if (IS_HASWELL(dev)) {
7047 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
7048 dev_priv->display.write_eld = haswell_write_eld;
7049 } else
7050 dev_priv->display.update_wm = NULL;
7051 } else if (IS_G4X(dev)) {
7052 dev_priv->display.write_eld = g4x_write_eld;
7053 }
7054
7055 /* Default just returns -ENODEV to indicate unsupported */
7056 dev_priv->display.queue_flip = intel_default_queue_flip;
7057
7058 switch (INTEL_INFO(dev)->gen) {
7059 case 2:
7060 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7061 break;
7062
7063 case 3:
7064 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7065 break;
7066
7067 case 4:
7068 case 5:
7069 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7070 break;
7071
7072 case 6:
7073 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7074 break;
7075 case 7:
7076 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7077 break;
7078 }
7079 }
7080
7081 /*
7082 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7083 * resume, or other times. This quirk makes sure that's the case for
7084 * affected systems.
7085 */
7086 static void quirk_pipea_force(struct drm_device *dev)
7087 {
7088 struct drm_i915_private *dev_priv = dev->dev_private;
7089
7090 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
7091 DRM_INFO("applying pipe a force quirk\n");
7092 }
7093
7094 /*
7095 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7096 */
7097 static void quirk_ssc_force_disable(struct drm_device *dev)
7098 {
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
7101 DRM_INFO("applying lvds SSC disable quirk\n");
7102 }
7103
7104 /*
7105 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7106 * brightness value
7107 */
7108 static void quirk_invert_brightness(struct drm_device *dev)
7109 {
7110 struct drm_i915_private *dev_priv = dev->dev_private;
7111 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
7112 DRM_INFO("applying inverted panel brightness quirk\n");
7113 }
7114
7115 struct intel_quirk {
7116 int device;
7117 int subsystem_vendor;
7118 int subsystem_device;
7119 void (*hook)(struct drm_device *dev);
7120 };
7121
7122 static struct intel_quirk intel_quirks[] = {
7123 /* HP Mini needs pipe A force quirk (LP: #322104) */
7124 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
7125
7126 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7127 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7128
7129 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7130 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7131
7132 /* 855 & before need to leave pipe A & dpll A up */
7133 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7134 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7135 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7136
7137 /* Lenovo U160 cannot use SSC on LVDS */
7138 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
7139
7140 /* Sony Vaio Y cannot use SSC on LVDS */
7141 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
7142
7143 /* Acer Aspire 5734Z must invert backlight brightness */
7144 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
7145 };
7146
7147 static void intel_init_quirks(struct drm_device *dev)
7148 {
7149 struct pci_dev *d = dev->pdev;
7150 int i;
7151
7152 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7153 struct intel_quirk *q = &intel_quirks[i];
7154
7155 if (d->device == q->device &&
7156 (d->subsystem_vendor == q->subsystem_vendor ||
7157 q->subsystem_vendor == PCI_ANY_ID) &&
7158 (d->subsystem_device == q->subsystem_device ||
7159 q->subsystem_device == PCI_ANY_ID))
7160 q->hook(dev);
7161 }
7162 }
7163
7164 /* Disable the VGA plane that we never use */
7165 static void i915_disable_vga(struct drm_device *dev)
7166 {
7167 struct drm_i915_private *dev_priv = dev->dev_private;
7168 u8 sr1;
7169 u32 vga_reg;
7170
7171 if (HAS_PCH_SPLIT(dev))
7172 vga_reg = CPU_VGACNTRL;
7173 else
7174 vga_reg = VGACNTRL;
7175
7176 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
7177 outb(SR01, VGA_SR_INDEX);
7178 sr1 = inb(VGA_SR_DATA);
7179 outb(sr1 | 1<<5, VGA_SR_DATA);
7180 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7181 udelay(300);
7182
7183 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7184 POSTING_READ(vga_reg);
7185 }
7186
7187 void intel_modeset_init_hw(struct drm_device *dev)
7188 {
7189 /* We attempt to init the necessary power wells early in the initialization
7190 * time, so the subsystems that expect power to be enabled can work.
7191 */
7192 intel_init_power_wells(dev);
7193
7194 intel_prepare_ddi(dev);
7195
7196 intel_init_clock_gating(dev);
7197
7198 mutex_lock(&dev->struct_mutex);
7199 intel_enable_gt_powersave(dev);
7200 mutex_unlock(&dev->struct_mutex);
7201 }
7202
7203 void intel_modeset_init(struct drm_device *dev)
7204 {
7205 struct drm_i915_private *dev_priv = dev->dev_private;
7206 int i, ret;
7207
7208 drm_mode_config_init(dev);
7209
7210 dev->mode_config.min_width = 0;
7211 dev->mode_config.min_height = 0;
7212
7213 dev->mode_config.preferred_depth = 24;
7214 dev->mode_config.prefer_shadow = 1;
7215
7216 dev->mode_config.funcs = &intel_mode_funcs;
7217
7218 intel_init_quirks(dev);
7219
7220 intel_init_pm(dev);
7221
7222 intel_init_display(dev);
7223
7224 if (IS_GEN2(dev)) {
7225 dev->mode_config.max_width = 2048;
7226 dev->mode_config.max_height = 2048;
7227 } else if (IS_GEN3(dev)) {
7228 dev->mode_config.max_width = 4096;
7229 dev->mode_config.max_height = 4096;
7230 } else {
7231 dev->mode_config.max_width = 8192;
7232 dev->mode_config.max_height = 8192;
7233 }
7234 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
7235
7236 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7237 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
7238
7239 for (i = 0; i < dev_priv->num_pipe; i++) {
7240 intel_crtc_init(dev, i);
7241 ret = intel_plane_init(dev, i);
7242 if (ret)
7243 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
7244 }
7245
7246 intel_pch_pll_init(dev);
7247
7248 /* Just disable it once at startup */
7249 i915_disable_vga(dev);
7250 intel_setup_outputs(dev);
7251 }
7252
7253 void intel_modeset_gem_init(struct drm_device *dev)
7254 {
7255 intel_modeset_init_hw(dev);
7256
7257 intel_setup_overlay(dev);
7258 }
7259
7260 void intel_modeset_cleanup(struct drm_device *dev)
7261 {
7262 struct drm_i915_private *dev_priv = dev->dev_private;
7263 struct drm_crtc *crtc;
7264 struct intel_crtc *intel_crtc;
7265
7266 drm_kms_helper_poll_fini(dev);
7267 mutex_lock(&dev->struct_mutex);
7268
7269 intel_unregister_dsm_handler();
7270
7271
7272 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7273 /* Skip inactive CRTCs */
7274 if (!crtc->fb)
7275 continue;
7276
7277 intel_crtc = to_intel_crtc(crtc);
7278 intel_increase_pllclock(crtc);
7279 }
7280
7281 intel_disable_fbc(dev);
7282
7283 intel_disable_gt_powersave(dev);
7284
7285 ironlake_teardown_rc6(dev);
7286
7287 if (IS_VALLEYVIEW(dev))
7288 vlv_init_dpio(dev);
7289
7290 mutex_unlock(&dev->struct_mutex);
7291
7292 /* Disable the irq before mode object teardown, for the irq might
7293 * enqueue unpin/hotplug work. */
7294 drm_irq_uninstall(dev);
7295 cancel_work_sync(&dev_priv->hotplug_work);
7296 cancel_work_sync(&dev_priv->rps.work);
7297
7298 /* flush any delayed tasks or pending work */
7299 flush_scheduled_work();
7300
7301 drm_mode_config_cleanup(dev);
7302 }
7303
7304 /*
7305 * Return which encoder is currently attached for connector.
7306 */
7307 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
7308 {
7309 return &intel_attached_encoder(connector)->base;
7310 }
7311
7312 void intel_connector_attach_encoder(struct intel_connector *connector,
7313 struct intel_encoder *encoder)
7314 {
7315 connector->encoder = encoder;
7316 drm_mode_connector_attach_encoder(&connector->base,
7317 &encoder->base);
7318 }
7319
7320 /*
7321 * set vga decode state - true == enable VGA decode
7322 */
7323 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7324 {
7325 struct drm_i915_private *dev_priv = dev->dev_private;
7326 u16 gmch_ctrl;
7327
7328 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7329 if (state)
7330 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7331 else
7332 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7333 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7334 return 0;
7335 }
7336
7337 #ifdef CONFIG_DEBUG_FS
7338 #include <linux/seq_file.h>
7339
7340 struct intel_display_error_state {
7341 struct intel_cursor_error_state {
7342 u32 control;
7343 u32 position;
7344 u32 base;
7345 u32 size;
7346 } cursor[I915_MAX_PIPES];
7347
7348 struct intel_pipe_error_state {
7349 u32 conf;
7350 u32 source;
7351
7352 u32 htotal;
7353 u32 hblank;
7354 u32 hsync;
7355 u32 vtotal;
7356 u32 vblank;
7357 u32 vsync;
7358 } pipe[I915_MAX_PIPES];
7359
7360 struct intel_plane_error_state {
7361 u32 control;
7362 u32 stride;
7363 u32 size;
7364 u32 pos;
7365 u32 addr;
7366 u32 surface;
7367 u32 tile_offset;
7368 } plane[I915_MAX_PIPES];
7369 };
7370
7371 struct intel_display_error_state *
7372 intel_display_capture_error_state(struct drm_device *dev)
7373 {
7374 drm_i915_private_t *dev_priv = dev->dev_private;
7375 struct intel_display_error_state *error;
7376 int i;
7377
7378 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7379 if (error == NULL)
7380 return NULL;
7381
7382 for_each_pipe(i) {
7383 error->cursor[i].control = I915_READ(CURCNTR(i));
7384 error->cursor[i].position = I915_READ(CURPOS(i));
7385 error->cursor[i].base = I915_READ(CURBASE(i));
7386
7387 error->plane[i].control = I915_READ(DSPCNTR(i));
7388 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7389 error->plane[i].size = I915_READ(DSPSIZE(i));
7390 error->plane[i].pos = I915_READ(DSPPOS(i));
7391 error->plane[i].addr = I915_READ(DSPADDR(i));
7392 if (INTEL_INFO(dev)->gen >= 4) {
7393 error->plane[i].surface = I915_READ(DSPSURF(i));
7394 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7395 }
7396
7397 error->pipe[i].conf = I915_READ(PIPECONF(i));
7398 error->pipe[i].source = I915_READ(PIPESRC(i));
7399 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7400 error->pipe[i].hblank = I915_READ(HBLANK(i));
7401 error->pipe[i].hsync = I915_READ(HSYNC(i));
7402 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7403 error->pipe[i].vblank = I915_READ(VBLANK(i));
7404 error->pipe[i].vsync = I915_READ(VSYNC(i));
7405 }
7406
7407 return error;
7408 }
7409
7410 void
7411 intel_display_print_error_state(struct seq_file *m,
7412 struct drm_device *dev,
7413 struct intel_display_error_state *error)
7414 {
7415 drm_i915_private_t *dev_priv = dev->dev_private;
7416 int i;
7417
7418 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
7419 for_each_pipe(i) {
7420 seq_printf(m, "Pipe [%d]:\n", i);
7421 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7422 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7423 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7424 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7425 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7426 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7427 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7428 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7429
7430 seq_printf(m, "Plane [%d]:\n", i);
7431 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7432 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7433 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7434 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7435 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7436 if (INTEL_INFO(dev)->gen >= 4) {
7437 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7438 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7439 }
7440
7441 seq_printf(m, "Cursor [%d]:\n", i);
7442 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7443 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7444 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7445 }
7446 }
7447 #endif
Linux kernel - Deliverables
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