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[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
49
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
52 DRM_FORMAT_C8,
53 DRM_FORMAT_RGB565,
54 DRM_FORMAT_XRGB1555,
55 DRM_FORMAT_XRGB8888,
56 };
57
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
60 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
66 };
67
68 static const uint32_t skl_primary_formats[] = {
69 DRM_FORMAT_C8,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_XBGR8888,
73 DRM_FORMAT_ARGB8888,
74 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
77 DRM_FORMAT_YUYV,
78 DRM_FORMAT_YVYU,
79 DRM_FORMAT_UYVY,
80 DRM_FORMAT_VYUY,
81 };
82
83 /* Cursor formats */
84 static const uint32_t intel_cursor_formats[] = {
85 DRM_FORMAT_ARGB8888,
86 };
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg)
152 {
153 u32 val;
154 int divider;
155
156 if (dev_priv->hpll_freq == 0)
157 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
170 }
171
172 int
173 intel_pch_rawclk(struct drm_device *dev)
174 {
175 struct drm_i915_private *dev_priv = dev->dev_private;
176
177 WARN_ON(!HAS_PCH_SPLIT(dev));
178
179 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
180 }
181
182 /* hrawclock is 1/4 the FSB frequency */
183 int intel_hrawclk(struct drm_device *dev)
184 {
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 uint32_t clkcfg;
187
188 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
189 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
190 return 200;
191
192 clkcfg = I915_READ(CLKCFG);
193 switch (clkcfg & CLKCFG_FSB_MASK) {
194 case CLKCFG_FSB_400:
195 return 100;
196 case CLKCFG_FSB_533:
197 return 133;
198 case CLKCFG_FSB_667:
199 return 166;
200 case CLKCFG_FSB_800:
201 return 200;
202 case CLKCFG_FSB_1067:
203 return 266;
204 case CLKCFG_FSB_1333:
205 return 333;
206 /* these two are just a guess; one of them might be right */
207 case CLKCFG_FSB_1600:
208 case CLKCFG_FSB_1600_ALT:
209 return 400;
210 default:
211 return 133;
212 }
213 }
214
215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
216 {
217 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
218 return;
219
220 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
221 CCK_CZ_CLOCK_CONTROL);
222
223 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
224 }
225
226 static inline u32 /* units of 100MHz */
227 intel_fdi_link_freq(struct drm_device *dev)
228 {
229 if (IS_GEN5(dev)) {
230 struct drm_i915_private *dev_priv = dev->dev_private;
231 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
232 } else
233 return 27;
234 }
235
236 static const intel_limit_t intel_limits_i8xx_dac = {
237 .dot = { .min = 25000, .max = 350000 },
238 .vco = { .min = 908000, .max = 1512000 },
239 .n = { .min = 2, .max = 16 },
240 .m = { .min = 96, .max = 140 },
241 .m1 = { .min = 18, .max = 26 },
242 .m2 = { .min = 6, .max = 16 },
243 .p = { .min = 4, .max = 128 },
244 .p1 = { .min = 2, .max = 33 },
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 4, .p2_fast = 2 },
247 };
248
249 static const intel_limit_t intel_limits_i8xx_dvo = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 908000, .max = 1512000 },
252 .n = { .min = 2, .max = 16 },
253 .m = { .min = 96, .max = 140 },
254 .m1 = { .min = 18, .max = 26 },
255 .m2 = { .min = 6, .max = 16 },
256 .p = { .min = 4, .max = 128 },
257 .p1 = { .min = 2, .max = 33 },
258 .p2 = { .dot_limit = 165000,
259 .p2_slow = 4, .p2_fast = 4 },
260 };
261
262 static const intel_limit_t intel_limits_i8xx_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 1, .max = 6 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 14, .p2_fast = 7 },
273 };
274
275 static const intel_limit_t intel_limits_i9xx_sdvo = {
276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1400000, .max = 2800000 },
278 .n = { .min = 1, .max = 6 },
279 .m = { .min = 70, .max = 120 },
280 .m1 = { .min = 8, .max = 18 },
281 .m2 = { .min = 3, .max = 7 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 200000,
285 .p2_slow = 10, .p2_fast = 5 },
286 };
287
288 static const intel_limit_t intel_limits_i9xx_lvds = {
289 .dot = { .min = 20000, .max = 400000 },
290 .vco = { .min = 1400000, .max = 2800000 },
291 .n = { .min = 1, .max = 6 },
292 .m = { .min = 70, .max = 120 },
293 .m1 = { .min = 8, .max = 18 },
294 .m2 = { .min = 3, .max = 7 },
295 .p = { .min = 7, .max = 98 },
296 .p1 = { .min = 1, .max = 8 },
297 .p2 = { .dot_limit = 112000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301
302 static const intel_limit_t intel_limits_g4x_sdvo = {
303 .dot = { .min = 25000, .max = 270000 },
304 .vco = { .min = 1750000, .max = 3500000},
305 .n = { .min = 1, .max = 4 },
306 .m = { .min = 104, .max = 138 },
307 .m1 = { .min = 17, .max = 23 },
308 .m2 = { .min = 5, .max = 11 },
309 .p = { .min = 10, .max = 30 },
310 .p1 = { .min = 1, .max = 3},
311 .p2 = { .dot_limit = 270000,
312 .p2_slow = 10,
313 .p2_fast = 10
314 },
315 };
316
317 static const intel_limit_t intel_limits_g4x_hdmi = {
318 .dot = { .min = 22000, .max = 400000 },
319 .vco = { .min = 1750000, .max = 3500000},
320 .n = { .min = 1, .max = 4 },
321 .m = { .min = 104, .max = 138 },
322 .m1 = { .min = 16, .max = 23 },
323 .m2 = { .min = 5, .max = 11 },
324 .p = { .min = 5, .max = 80 },
325 .p1 = { .min = 1, .max = 8},
326 .p2 = { .dot_limit = 165000,
327 .p2_slow = 10, .p2_fast = 5 },
328 };
329
330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
331 .dot = { .min = 20000, .max = 115000 },
332 .vco = { .min = 1750000, .max = 3500000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 104, .max = 138 },
335 .m1 = { .min = 17, .max = 23 },
336 .m2 = { .min = 5, .max = 11 },
337 .p = { .min = 28, .max = 112 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 0,
340 .p2_slow = 14, .p2_fast = 14
341 },
342 };
343
344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
345 .dot = { .min = 80000, .max = 224000 },
346 .vco = { .min = 1750000, .max = 3500000 },
347 .n = { .min = 1, .max = 3 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 17, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 14, .max = 42 },
352 .p1 = { .min = 2, .max = 6 },
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 7, .p2_fast = 7
355 },
356 };
357
358 static const intel_limit_t intel_limits_pineview_sdvo = {
359 .dot = { .min = 20000, .max = 400000},
360 .vco = { .min = 1700000, .max = 3500000 },
361 /* Pineview's Ncounter is a ring counter */
362 .n = { .min = 3, .max = 6 },
363 .m = { .min = 2, .max = 256 },
364 /* Pineview only has one combined m divider, which we treat as m2. */
365 .m1 = { .min = 0, .max = 0 },
366 .m2 = { .min = 0, .max = 254 },
367 .p = { .min = 5, .max = 80 },
368 .p1 = { .min = 1, .max = 8 },
369 .p2 = { .dot_limit = 200000,
370 .p2_slow = 10, .p2_fast = 5 },
371 };
372
373 static const intel_limit_t intel_limits_pineview_lvds = {
374 .dot = { .min = 20000, .max = 400000 },
375 .vco = { .min = 1700000, .max = 3500000 },
376 .n = { .min = 3, .max = 6 },
377 .m = { .min = 2, .max = 256 },
378 .m1 = { .min = 0, .max = 0 },
379 .m2 = { .min = 0, .max = 254 },
380 .p = { .min = 7, .max = 112 },
381 .p1 = { .min = 1, .max = 8 },
382 .p2 = { .dot_limit = 112000,
383 .p2_slow = 14, .p2_fast = 14 },
384 };
385
386 /* Ironlake / Sandybridge
387 *
388 * We calculate clock using (register_value + 2) for N/M1/M2, so here
389 * the range value for them is (actual_value - 2).
390 */
391 static const intel_limit_t intel_limits_ironlake_dac = {
392 .dot = { .min = 25000, .max = 350000 },
393 .vco = { .min = 1760000, .max = 3510000 },
394 .n = { .min = 1, .max = 5 },
395 .m = { .min = 79, .max = 127 },
396 .m1 = { .min = 12, .max = 22 },
397 .m2 = { .min = 5, .max = 9 },
398 .p = { .min = 5, .max = 80 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 225000,
401 .p2_slow = 10, .p2_fast = 5 },
402 };
403
404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
405 .dot = { .min = 25000, .max = 350000 },
406 .vco = { .min = 1760000, .max = 3510000 },
407 .n = { .min = 1, .max = 3 },
408 .m = { .min = 79, .max = 118 },
409 .m1 = { .min = 12, .max = 22 },
410 .m2 = { .min = 5, .max = 9 },
411 .p = { .min = 28, .max = 112 },
412 .p1 = { .min = 2, .max = 8 },
413 .p2 = { .dot_limit = 225000,
414 .p2_slow = 14, .p2_fast = 14 },
415 };
416
417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 3 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 14, .max = 56 },
425 .p1 = { .min = 2, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 7, .p2_fast = 7 },
428 };
429
430 /* LVDS 100mhz refclk limits. */
431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 2 },
435 .m = { .min = 79, .max = 126 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 126 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 42 },
452 .p1 = { .min = 2, .max = 6 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 static const intel_limit_t intel_limits_vlv = {
458 /*
459 * These are the data rate limits (measured in fast clocks)
460 * since those are the strictest limits we have. The fast
461 * clock and actual rate limits are more relaxed, so checking
462 * them would make no difference.
463 */
464 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
465 .vco = { .min = 4000000, .max = 6000000 },
466 .n = { .min = 1, .max = 7 },
467 .m1 = { .min = 2, .max = 3 },
468 .m2 = { .min = 11, .max = 156 },
469 .p1 = { .min = 2, .max = 3 },
470 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
471 };
472
473 static const intel_limit_t intel_limits_chv = {
474 /*
475 * These are the data rate limits (measured in fast clocks)
476 * since those are the strictest limits we have. The fast
477 * clock and actual rate limits are more relaxed, so checking
478 * them would make no difference.
479 */
480 .dot = { .min = 25000 * 5, .max = 540000 * 5},
481 .vco = { .min = 4800000, .max = 6480000 },
482 .n = { .min = 1, .max = 1 },
483 .m1 = { .min = 2, .max = 2 },
484 .m2 = { .min = 24 << 22, .max = 175 << 22 },
485 .p1 = { .min = 2, .max = 4 },
486 .p2 = { .p2_slow = 1, .p2_fast = 14 },
487 };
488
489 static const intel_limit_t intel_limits_bxt = {
490 /* FIXME: find real dot limits */
491 .dot = { .min = 0, .max = INT_MAX },
492 .vco = { .min = 4800000, .max = 6700000 },
493 .n = { .min = 1, .max = 1 },
494 .m1 = { .min = 2, .max = 2 },
495 /* FIXME: find real m2 limits */
496 .m2 = { .min = 2 << 22, .max = 255 << 22 },
497 .p1 = { .min = 2, .max = 4 },
498 .p2 = { .p2_slow = 1, .p2_fast = 20 },
499 };
500
501 static bool
502 needs_modeset(struct drm_crtc_state *state)
503 {
504 return drm_atomic_crtc_needs_modeset(state);
505 }
506
507 /**
508 * Returns whether any output on the specified pipe is of the specified type
509 */
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
511 {
512 struct drm_device *dev = crtc->base.dev;
513 struct intel_encoder *encoder;
514
515 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
516 if (encoder->type == type)
517 return true;
518
519 return false;
520 }
521
522 /**
523 * Returns whether any output on the specified pipe will have the specified
524 * type after a staged modeset is complete, i.e., the same as
525 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
526 * encoder->crtc.
527 */
528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
529 int type)
530 {
531 struct drm_atomic_state *state = crtc_state->base.state;
532 struct drm_connector *connector;
533 struct drm_connector_state *connector_state;
534 struct intel_encoder *encoder;
535 int i, num_connectors = 0;
536
537 for_each_connector_in_state(state, connector, connector_state, i) {
538 if (connector_state->crtc != crtc_state->base.crtc)
539 continue;
540
541 num_connectors++;
542
543 encoder = to_intel_encoder(connector_state->best_encoder);
544 if (encoder->type == type)
545 return true;
546 }
547
548 WARN_ON(num_connectors == 0);
549
550 return false;
551 }
552
553 static const intel_limit_t *
554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
555 {
556 struct drm_device *dev = crtc_state->base.crtc->dev;
557 const intel_limit_t *limit;
558
559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
560 if (intel_is_dual_link_lvds(dev)) {
561 if (refclk == 100000)
562 limit = &intel_limits_ironlake_dual_lvds_100m;
563 else
564 limit = &intel_limits_ironlake_dual_lvds;
565 } else {
566 if (refclk == 100000)
567 limit = &intel_limits_ironlake_single_lvds_100m;
568 else
569 limit = &intel_limits_ironlake_single_lvds;
570 }
571 } else
572 limit = &intel_limits_ironlake_dac;
573
574 return limit;
575 }
576
577 static const intel_limit_t *
578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
579 {
580 struct drm_device *dev = crtc_state->base.crtc->dev;
581 const intel_limit_t *limit;
582
583 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
584 if (intel_is_dual_link_lvds(dev))
585 limit = &intel_limits_g4x_dual_channel_lvds;
586 else
587 limit = &intel_limits_g4x_single_channel_lvds;
588 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
589 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
590 limit = &intel_limits_g4x_hdmi;
591 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
592 limit = &intel_limits_g4x_sdvo;
593 } else /* The option is for other outputs */
594 limit = &intel_limits_i9xx_sdvo;
595
596 return limit;
597 }
598
599 static const intel_limit_t *
600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
601 {
602 struct drm_device *dev = crtc_state->base.crtc->dev;
603 const intel_limit_t *limit;
604
605 if (IS_BROXTON(dev))
606 limit = &intel_limits_bxt;
607 else if (HAS_PCH_SPLIT(dev))
608 limit = intel_ironlake_limit(crtc_state, refclk);
609 else if (IS_G4X(dev)) {
610 limit = intel_g4x_limit(crtc_state);
611 } else if (IS_PINEVIEW(dev)) {
612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
613 limit = &intel_limits_pineview_lvds;
614 else
615 limit = &intel_limits_pineview_sdvo;
616 } else if (IS_CHERRYVIEW(dev)) {
617 limit = &intel_limits_chv;
618 } else if (IS_VALLEYVIEW(dev)) {
619 limit = &intel_limits_vlv;
620 } else if (!IS_GEN2(dev)) {
621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
622 limit = &intel_limits_i9xx_lvds;
623 else
624 limit = &intel_limits_i9xx_sdvo;
625 } else {
626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
627 limit = &intel_limits_i8xx_lvds;
628 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
629 limit = &intel_limits_i8xx_dvo;
630 else
631 limit = &intel_limits_i8xx_dac;
632 }
633 return limit;
634 }
635
636 /*
637 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
638 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
639 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
640 * The helpers' return value is the rate of the clock that is fed to the
641 * display engine's pipe which can be the above fast dot clock rate or a
642 * divided-down version of it.
643 */
644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
646 {
647 clock->m = clock->m2 + 2;
648 clock->p = clock->p1 * clock->p2;
649 if (WARN_ON(clock->n == 0 || clock->p == 0))
650 return 0;
651 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
652 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
653
654 return clock->dot;
655 }
656
657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
658 {
659 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
660 }
661
662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
663 {
664 clock->m = i9xx_dpll_compute_m(clock);
665 clock->p = clock->p1 * clock->p2;
666 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
667 return 0;
668 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
669 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
670
671 return clock->dot;
672 }
673
674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
675 {
676 clock->m = clock->m1 * clock->m2;
677 clock->p = clock->p1 * clock->p2;
678 if (WARN_ON(clock->n == 0 || clock->p == 0))
679 return 0;
680 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
681 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682
683 return clock->dot / 5;
684 }
685
686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
687 {
688 clock->m = clock->m1 * clock->m2;
689 clock->p = clock->p1 * clock->p2;
690 if (WARN_ON(clock->n == 0 || clock->p == 0))
691 return 0;
692 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
693 clock->n << 22);
694 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
695
696 return clock->dot / 5;
697 }
698
699 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
700 /**
701 * Returns whether the given set of divisors are valid for a given refclk with
702 * the given connectors.
703 */
704
705 static bool intel_PLL_is_valid(struct drm_device *dev,
706 const intel_limit_t *limit,
707 const intel_clock_t *clock)
708 {
709 if (clock->n < limit->n.min || limit->n.max < clock->n)
710 INTELPllInvalid("n out of range\n");
711 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
712 INTELPllInvalid("p1 out of range\n");
713 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
714 INTELPllInvalid("m2 out of range\n");
715 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
716 INTELPllInvalid("m1 out of range\n");
717
718 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
719 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
720 if (clock->m1 <= clock->m2)
721 INTELPllInvalid("m1 <= m2\n");
722
723 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
724 if (clock->p < limit->p.min || limit->p.max < clock->p)
725 INTELPllInvalid("p out of range\n");
726 if (clock->m < limit->m.min || limit->m.max < clock->m)
727 INTELPllInvalid("m out of range\n");
728 }
729
730 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
731 INTELPllInvalid("vco out of range\n");
732 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
733 * connector, etc., rather than just a single range.
734 */
735 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
736 INTELPllInvalid("dot out of range\n");
737
738 return true;
739 }
740
741 static int
742 i9xx_select_p2_div(const intel_limit_t *limit,
743 const struct intel_crtc_state *crtc_state,
744 int target)
745 {
746 struct drm_device *dev = crtc_state->base.crtc->dev;
747
748 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
749 /*
750 * For LVDS just rely on its current settings for dual-channel.
751 * We haven't figured out how to reliably set up different
752 * single/dual channel state, if we even can.
753 */
754 if (intel_is_dual_link_lvds(dev))
755 return limit->p2.p2_fast;
756 else
757 return limit->p2.p2_slow;
758 } else {
759 if (target < limit->p2.dot_limit)
760 return limit->p2.p2_slow;
761 else
762 return limit->p2.p2_fast;
763 }
764 }
765
766 static bool
767 i9xx_find_best_dpll(const intel_limit_t *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc_state->base.crtc->dev;
773 intel_clock_t clock;
774 int err = target;
775
776 memset(best_clock, 0, sizeof(*best_clock));
777
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
779
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
781 clock.m1++) {
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 if (clock.m2 >= clock.m1)
785 break;
786 for (clock.n = limit->n.min;
787 clock.n <= limit->n.max; clock.n++) {
788 for (clock.p1 = limit->p1.min;
789 clock.p1 <= limit->p1.max; clock.p1++) {
790 int this_err;
791
792 i9xx_calc_dpll_params(refclk, &clock);
793 if (!intel_PLL_is_valid(dev, limit,
794 &clock))
795 continue;
796 if (match_clock &&
797 clock.p != match_clock->p)
798 continue;
799
800 this_err = abs(clock.dot - target);
801 if (this_err < err) {
802 *best_clock = clock;
803 err = this_err;
804 }
805 }
806 }
807 }
808 }
809
810 return (err != target);
811 }
812
813 static bool
814 pnv_find_best_dpll(const intel_limit_t *limit,
815 struct intel_crtc_state *crtc_state,
816 int target, int refclk, intel_clock_t *match_clock,
817 intel_clock_t *best_clock)
818 {
819 struct drm_device *dev = crtc_state->base.crtc->dev;
820 intel_clock_t clock;
821 int err = target;
822
823 memset(best_clock, 0, sizeof(*best_clock));
824
825 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
826
827 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
828 clock.m1++) {
829 for (clock.m2 = limit->m2.min;
830 clock.m2 <= limit->m2.max; clock.m2++) {
831 for (clock.n = limit->n.min;
832 clock.n <= limit->n.max; clock.n++) {
833 for (clock.p1 = limit->p1.min;
834 clock.p1 <= limit->p1.max; clock.p1++) {
835 int this_err;
836
837 pnv_calc_dpll_params(refclk, &clock);
838 if (!intel_PLL_is_valid(dev, limit,
839 &clock))
840 continue;
841 if (match_clock &&
842 clock.p != match_clock->p)
843 continue;
844
845 this_err = abs(clock.dot - target);
846 if (this_err < err) {
847 *best_clock = clock;
848 err = this_err;
849 }
850 }
851 }
852 }
853 }
854
855 return (err != target);
856 }
857
858 static bool
859 g4x_find_best_dpll(const intel_limit_t *limit,
860 struct intel_crtc_state *crtc_state,
861 int target, int refclk, intel_clock_t *match_clock,
862 intel_clock_t *best_clock)
863 {
864 struct drm_device *dev = crtc_state->base.crtc->dev;
865 intel_clock_t clock;
866 int max_n;
867 bool found = false;
868 /* approximately equals target * 0.00585 */
869 int err_most = (target >> 8) + (target >> 9);
870
871 memset(best_clock, 0, sizeof(*best_clock));
872
873 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
874
875 max_n = limit->n.max;
876 /* based on hardware requirement, prefer smaller n to precision */
877 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
878 /* based on hardware requirement, prefere larger m1,m2 */
879 for (clock.m1 = limit->m1.max;
880 clock.m1 >= limit->m1.min; clock.m1--) {
881 for (clock.m2 = limit->m2.max;
882 clock.m2 >= limit->m2.min; clock.m2--) {
883 for (clock.p1 = limit->p1.max;
884 clock.p1 >= limit->p1.min; clock.p1--) {
885 int this_err;
886
887 i9xx_calc_dpll_params(refclk, &clock);
888 if (!intel_PLL_is_valid(dev, limit,
889 &clock))
890 continue;
891
892 this_err = abs(clock.dot - target);
893 if (this_err < err_most) {
894 *best_clock = clock;
895 err_most = this_err;
896 max_n = clock.n;
897 found = true;
898 }
899 }
900 }
901 }
902 }
903 return found;
904 }
905
906 /*
907 * Check if the calculated PLL configuration is more optimal compared to the
908 * best configuration and error found so far. Return the calculated error.
909 */
910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
911 const intel_clock_t *calculated_clock,
912 const intel_clock_t *best_clock,
913 unsigned int best_error_ppm,
914 unsigned int *error_ppm)
915 {
916 /*
917 * For CHV ignore the error and consider only the P value.
918 * Prefer a bigger P value based on HW requirements.
919 */
920 if (IS_CHERRYVIEW(dev)) {
921 *error_ppm = 0;
922
923 return calculated_clock->p > best_clock->p;
924 }
925
926 if (WARN_ON_ONCE(!target_freq))
927 return false;
928
929 *error_ppm = div_u64(1000000ULL *
930 abs(target_freq - calculated_clock->dot),
931 target_freq);
932 /*
933 * Prefer a better P value over a better (smaller) error if the error
934 * is small. Ensure this preference for future configurations too by
935 * setting the error to 0.
936 */
937 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
938 *error_ppm = 0;
939
940 return true;
941 }
942
943 return *error_ppm + 10 < best_error_ppm;
944 }
945
946 static bool
947 vlv_find_best_dpll(const intel_limit_t *limit,
948 struct intel_crtc_state *crtc_state,
949 int target, int refclk, intel_clock_t *match_clock,
950 intel_clock_t *best_clock)
951 {
952 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
953 struct drm_device *dev = crtc->base.dev;
954 intel_clock_t clock;
955 unsigned int bestppm = 1000000;
956 /* min update 19.2 MHz */
957 int max_n = min(limit->n.max, refclk / 19200);
958 bool found = false;
959
960 target *= 5; /* fast clock */
961
962 memset(best_clock, 0, sizeof(*best_clock));
963
964 /* based on hardware requirement, prefer smaller n to precision */
965 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
966 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
967 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
968 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
969 clock.p = clock.p1 * clock.p2;
970 /* based on hardware requirement, prefer bigger m1,m2 values */
971 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
972 unsigned int ppm;
973
974 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
975 refclk * clock.m1);
976
977 vlv_calc_dpll_params(refclk, &clock);
978
979 if (!intel_PLL_is_valid(dev, limit,
980 &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target,
984 &clock,
985 best_clock,
986 bestppm, &ppm))
987 continue;
988
989 *best_clock = clock;
990 bestppm = ppm;
991 found = true;
992 }
993 }
994 }
995 }
996
997 return found;
998 }
999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002 struct intel_crtc_state *crtc_state,
1003 int target, int refclk, intel_clock_t *match_clock,
1004 intel_clock_t *best_clock)
1005 {
1006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007 struct drm_device *dev = crtc->base.dev;
1008 unsigned int best_error_ppm;
1009 intel_clock_t clock;
1010 uint64_t m2;
1011 int found = false;
1012
1013 memset(best_clock, 0, sizeof(*best_clock));
1014 best_error_ppm = 1000000;
1015
1016 /*
1017 * Based on hardware doc, the n always set to 1, and m1 always
1018 * set to 2. If requires to support 200Mhz refclk, we need to
1019 * revisit this because n may not 1 anymore.
1020 */
1021 clock.n = 1, clock.m1 = 2;
1022 target *= 5; /* fast clock */
1023
1024 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025 for (clock.p2 = limit->p2.p2_fast;
1026 clock.p2 >= limit->p2.p2_slow;
1027 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028 unsigned int error_ppm;
1029
1030 clock.p = clock.p1 * clock.p2;
1031
1032 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033 clock.n) << 22, refclk * clock.m1);
1034
1035 if (m2 > INT_MAX/clock.m1)
1036 continue;
1037
1038 clock.m2 = m2;
1039
1040 chv_calc_dpll_params(refclk, &clock);
1041
1042 if (!intel_PLL_is_valid(dev, limit, &clock))
1043 continue;
1044
1045 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046 best_error_ppm, &error_ppm))
1047 continue;
1048
1049 *best_clock = clock;
1050 best_error_ppm = error_ppm;
1051 found = true;
1052 }
1053 }
1054
1055 return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059 intel_clock_t *best_clock)
1060 {
1061 int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064 target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071 /* Be paranoid as we can arrive here with only partial
1072 * state retrieved from the hardware during setup.
1073 *
1074 * We can ditch the adjusted_mode.crtc_clock check as soon
1075 * as Haswell has gained clock readout/fastboot support.
1076 *
1077 * We can ditch the crtc->primary->fb check as soon as we can
1078 * properly reconstruct framebuffers.
1079 *
1080 * FIXME: The intel_crtc->active here should be switched to
1081 * crtc->state->active once we have proper CRTC states wired up
1082 * for atomic.
1083 */
1084 return intel_crtc->active && crtc->primary->state->fb &&
1085 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089 enum pipe pipe)
1090 {
1091 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094 return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 i915_reg_t reg = PIPEDSL(pipe);
1101 u32 line1, line2;
1102 u32 line_mask;
1103
1104 if (IS_GEN2(dev))
1105 line_mask = DSL_LINEMASK_GEN2;
1106 else
1107 line_mask = DSL_LINEMASK_GEN3;
1108
1109 line1 = I915_READ(reg) & line_mask;
1110 msleep(5);
1111 line2 = I915_READ(reg) & line_mask;
1112
1113 return line1 == line2;
1114 }
1115
1116 /*
1117 * intel_wait_for_pipe_off - wait for pipe to turn off
1118 * @crtc: crtc whose pipe to wait for
1119 *
1120 * After disabling a pipe, we can't wait for vblank in the usual way,
1121 * spinning on the vblank interrupt status bit, since we won't actually
1122 * see an interrupt when the pipe is disabled.
1123 *
1124 * On Gen4 and above:
1125 * wait for the pipe register state bit to turn off
1126 *
1127 * Otherwise:
1128 * wait for the display line value to settle (it usually
1129 * ends up stopping at the start of the next frame).
1130 *
1131 */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134 struct drm_device *dev = crtc->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137 enum pipe pipe = crtc->pipe;
1138
1139 if (INTEL_INFO(dev)->gen >= 4) {
1140 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142 /* Wait for the Pipe State to go off */
1143 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144 100))
1145 WARN(1, "pipe_off wait timed out\n");
1146 } else {
1147 /* Wait for the display line to settle */
1148 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149 WARN(1, "pipe_off wait timed out\n");
1150 }
1151 }
1152
1153 /* Only for pre-ILK configs */
1154 void assert_pll(struct drm_i915_private *dev_priv,
1155 enum pipe pipe, bool state)
1156 {
1157 u32 val;
1158 bool cur_state;
1159
1160 val = I915_READ(DPLL(pipe));
1161 cur_state = !!(val & DPLL_VCO_ENABLE);
1162 I915_STATE_WARN(cur_state != state,
1163 "PLL state assertion failure (expected %s, current %s)\n",
1164 onoff(state), onoff(cur_state));
1165 }
1166
1167 /* XXX: the dsi pll is shared between MIPI DSI ports */
1168 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1169 {
1170 u32 val;
1171 bool cur_state;
1172
1173 mutex_lock(&dev_priv->sb_lock);
1174 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1175 mutex_unlock(&dev_priv->sb_lock);
1176
1177 cur_state = val & DSI_PLL_VCO_EN;
1178 I915_STATE_WARN(cur_state != state,
1179 "DSI PLL state assertion failure (expected %s, current %s)\n",
1180 onoff(state), onoff(cur_state));
1181 }
1182 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1183 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1184
1185 struct intel_shared_dpll *
1186 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1187 {
1188 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1189
1190 if (crtc->config->shared_dpll < 0)
1191 return NULL;
1192
1193 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1194 }
1195
1196 /* For ILK+ */
1197 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1198 struct intel_shared_dpll *pll,
1199 bool state)
1200 {
1201 bool cur_state;
1202 struct intel_dpll_hw_state hw_state;
1203
1204 if (WARN(!pll, "asserting DPLL %s with no DPLL\n", onoff(state)))
1205 return;
1206
1207 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1208 I915_STATE_WARN(cur_state != state,
1209 "%s assertion failure (expected %s, current %s)\n",
1210 pll->name, onoff(state), onoff(cur_state));
1211 }
1212
1213 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215 {
1216 bool cur_state;
1217 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1218 pipe);
1219
1220 if (HAS_DDI(dev_priv->dev)) {
1221 /* DDI does not have a specific FDI_TX register */
1222 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1223 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1224 } else {
1225 u32 val = I915_READ(FDI_TX_CTL(pipe));
1226 cur_state = !!(val & FDI_TX_ENABLE);
1227 }
1228 I915_STATE_WARN(cur_state != state,
1229 "FDI TX state assertion failure (expected %s, current %s)\n",
1230 onoff(state), onoff(cur_state));
1231 }
1232 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1233 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1234
1235 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1236 enum pipe pipe, bool state)
1237 {
1238 u32 val;
1239 bool cur_state;
1240
1241 val = I915_READ(FDI_RX_CTL(pipe));
1242 cur_state = !!(val & FDI_RX_ENABLE);
1243 I915_STATE_WARN(cur_state != state,
1244 "FDI RX state assertion failure (expected %s, current %s)\n",
1245 onoff(state), onoff(cur_state));
1246 }
1247 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1248 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1249
1250 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1251 enum pipe pipe)
1252 {
1253 u32 val;
1254
1255 /* ILK FDI PLL is always enabled */
1256 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1257 return;
1258
1259 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1260 if (HAS_DDI(dev_priv->dev))
1261 return;
1262
1263 val = I915_READ(FDI_TX_CTL(pipe));
1264 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1265 }
1266
1267 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1268 enum pipe pipe, bool state)
1269 {
1270 u32 val;
1271 bool cur_state;
1272
1273 val = I915_READ(FDI_RX_CTL(pipe));
1274 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1275 I915_STATE_WARN(cur_state != state,
1276 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1277 onoff(state), onoff(cur_state));
1278 }
1279
1280 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 struct drm_device *dev = dev_priv->dev;
1284 i915_reg_t pp_reg;
1285 u32 val;
1286 enum pipe panel_pipe = PIPE_A;
1287 bool locked = true;
1288
1289 if (WARN_ON(HAS_DDI(dev)))
1290 return;
1291
1292 if (HAS_PCH_SPLIT(dev)) {
1293 u32 port_sel;
1294
1295 pp_reg = PCH_PP_CONTROL;
1296 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1297
1298 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1299 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1300 panel_pipe = PIPE_B;
1301 /* XXX: else fix for eDP */
1302 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1303 /* presumably write lock depends on pipe, not port select */
1304 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1305 panel_pipe = pipe;
1306 } else {
1307 pp_reg = PP_CONTROL;
1308 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1309 panel_pipe = PIPE_B;
1310 }
1311
1312 val = I915_READ(pp_reg);
1313 if (!(val & PANEL_POWER_ON) ||
1314 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1315 locked = false;
1316
1317 I915_STATE_WARN(panel_pipe == pipe && locked,
1318 "panel assertion failure, pipe %c regs locked\n",
1319 pipe_name(pipe));
1320 }
1321
1322 static void assert_cursor(struct drm_i915_private *dev_priv,
1323 enum pipe pipe, bool state)
1324 {
1325 struct drm_device *dev = dev_priv->dev;
1326 bool cur_state;
1327
1328 if (IS_845G(dev) || IS_I865G(dev))
1329 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1330 else
1331 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1332
1333 I915_STATE_WARN(cur_state != state,
1334 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1335 pipe_name(pipe), onoff(state), onoff(cur_state));
1336 }
1337 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1338 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1339
1340 void assert_pipe(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, bool state)
1342 {
1343 bool cur_state;
1344 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1345 pipe);
1346
1347 /* if we need the pipe quirk it must be always on */
1348 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1349 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1350 state = true;
1351
1352 if (!intel_display_power_is_enabled(dev_priv,
1353 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1354 cur_state = false;
1355 } else {
1356 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1357 cur_state = !!(val & PIPECONF_ENABLE);
1358 }
1359
1360 I915_STATE_WARN(cur_state != state,
1361 "pipe %c assertion failure (expected %s, current %s)\n",
1362 pipe_name(pipe), onoff(state), onoff(cur_state));
1363 }
1364
1365 static void assert_plane(struct drm_i915_private *dev_priv,
1366 enum plane plane, bool state)
1367 {
1368 u32 val;
1369 bool cur_state;
1370
1371 val = I915_READ(DSPCNTR(plane));
1372 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1373 I915_STATE_WARN(cur_state != state,
1374 "plane %c assertion failure (expected %s, current %s)\n",
1375 plane_name(plane), onoff(state), onoff(cur_state));
1376 }
1377
1378 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1379 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1380
1381 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe)
1383 {
1384 struct drm_device *dev = dev_priv->dev;
1385 int i;
1386
1387 /* Primary planes are fixed to pipes on gen4+ */
1388 if (INTEL_INFO(dev)->gen >= 4) {
1389 u32 val = I915_READ(DSPCNTR(pipe));
1390 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1391 "plane %c assertion failure, should be disabled but not\n",
1392 plane_name(pipe));
1393 return;
1394 }
1395
1396 /* Need to check both planes against the pipe */
1397 for_each_pipe(dev_priv, i) {
1398 u32 val = I915_READ(DSPCNTR(i));
1399 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1400 DISPPLANE_SEL_PIPE_SHIFT;
1401 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1402 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1403 plane_name(i), pipe_name(pipe));
1404 }
1405 }
1406
1407 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe)
1409 {
1410 struct drm_device *dev = dev_priv->dev;
1411 int sprite;
1412
1413 if (INTEL_INFO(dev)->gen >= 9) {
1414 for_each_sprite(dev_priv, pipe, sprite) {
1415 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1416 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1417 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1418 sprite, pipe_name(pipe));
1419 }
1420 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1421 for_each_sprite(dev_priv, pipe, sprite) {
1422 u32 val = I915_READ(SPCNTR(pipe, sprite));
1423 I915_STATE_WARN(val & SP_ENABLE,
1424 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1425 sprite_name(pipe, sprite), pipe_name(pipe));
1426 }
1427 } else if (INTEL_INFO(dev)->gen >= 7) {
1428 u32 val = I915_READ(SPRCTL(pipe));
1429 I915_STATE_WARN(val & SPRITE_ENABLE,
1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431 plane_name(pipe), pipe_name(pipe));
1432 } else if (INTEL_INFO(dev)->gen >= 5) {
1433 u32 val = I915_READ(DVSCNTR(pipe));
1434 I915_STATE_WARN(val & DVS_ENABLE,
1435 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1436 plane_name(pipe), pipe_name(pipe));
1437 }
1438 }
1439
1440 static void assert_vblank_disabled(struct drm_crtc *crtc)
1441 {
1442 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1443 drm_crtc_vblank_put(crtc);
1444 }
1445
1446 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1447 {
1448 u32 val;
1449 bool enabled;
1450
1451 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1452
1453 val = I915_READ(PCH_DREF_CONTROL);
1454 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1455 DREF_SUPERSPREAD_SOURCE_MASK));
1456 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1457 }
1458
1459 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1460 enum pipe pipe)
1461 {
1462 u32 val;
1463 bool enabled;
1464
1465 val = I915_READ(PCH_TRANSCONF(pipe));
1466 enabled = !!(val & TRANS_ENABLE);
1467 I915_STATE_WARN(enabled,
1468 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1469 pipe_name(pipe));
1470 }
1471
1472 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1473 enum pipe pipe, u32 port_sel, u32 val)
1474 {
1475 if ((val & DP_PORT_EN) == 0)
1476 return false;
1477
1478 if (HAS_PCH_CPT(dev_priv->dev)) {
1479 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1480 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1481 return false;
1482 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1483 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1484 return false;
1485 } else {
1486 if ((val & DP_PIPE_MASK) != (pipe << 30))
1487 return false;
1488 }
1489 return true;
1490 }
1491
1492 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1493 enum pipe pipe, u32 val)
1494 {
1495 if ((val & SDVO_ENABLE) == 0)
1496 return false;
1497
1498 if (HAS_PCH_CPT(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1500 return false;
1501 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1502 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1503 return false;
1504 } else {
1505 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1506 return false;
1507 }
1508 return true;
1509 }
1510
1511 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1512 enum pipe pipe, u32 val)
1513 {
1514 if ((val & LVDS_PORT_EN) == 0)
1515 return false;
1516
1517 if (HAS_PCH_CPT(dev_priv->dev)) {
1518 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1519 return false;
1520 } else {
1521 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1522 return false;
1523 }
1524 return true;
1525 }
1526
1527 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1528 enum pipe pipe, u32 val)
1529 {
1530 if ((val & ADPA_DAC_ENABLE) == 0)
1531 return false;
1532 if (HAS_PCH_CPT(dev_priv->dev)) {
1533 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1534 return false;
1535 } else {
1536 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1537 return false;
1538 }
1539 return true;
1540 }
1541
1542 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1543 enum pipe pipe, i915_reg_t reg,
1544 u32 port_sel)
1545 {
1546 u32 val = I915_READ(reg);
1547 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1548 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1549 i915_mmio_reg_offset(reg), pipe_name(pipe));
1550
1551 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1552 && (val & DP_PIPEB_SELECT),
1553 "IBX PCH dp port still using transcoder B\n");
1554 }
1555
1556 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1557 enum pipe pipe, i915_reg_t reg)
1558 {
1559 u32 val = I915_READ(reg);
1560 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1561 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1562 i915_mmio_reg_offset(reg), pipe_name(pipe));
1563
1564 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1565 && (val & SDVO_PIPE_B_SELECT),
1566 "IBX PCH hdmi port still using transcoder B\n");
1567 }
1568
1569 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1570 enum pipe pipe)
1571 {
1572 u32 val;
1573
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1575 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1576 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1577
1578 val = I915_READ(PCH_ADPA);
1579 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1580 "PCH VGA enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 val = I915_READ(PCH_LVDS);
1584 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1585 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1586 pipe_name(pipe));
1587
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1591 }
1592
1593 static void vlv_enable_pll(struct intel_crtc *crtc,
1594 const struct intel_crtc_state *pipe_config)
1595 {
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 i915_reg_t reg = DPLL(crtc->pipe);
1599 u32 dpll = pipe_config->dpll_hw_state.dpll;
1600
1601 assert_pipe_disabled(dev_priv, crtc->pipe);
1602
1603 /* PLL is protected by panel, make sure we can write it */
1604 if (IS_MOBILE(dev_priv->dev))
1605 assert_panel_unlocked(dev_priv, crtc->pipe);
1606
1607 I915_WRITE(reg, dpll);
1608 POSTING_READ(reg);
1609 udelay(150);
1610
1611 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1612 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1613
1614 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1615 POSTING_READ(DPLL_MD(crtc->pipe));
1616
1617 /* We do this three times for luck */
1618 I915_WRITE(reg, dpll);
1619 POSTING_READ(reg);
1620 udelay(150); /* wait for warmup */
1621 I915_WRITE(reg, dpll);
1622 POSTING_READ(reg);
1623 udelay(150); /* wait for warmup */
1624 I915_WRITE(reg, dpll);
1625 POSTING_READ(reg);
1626 udelay(150); /* wait for warmup */
1627 }
1628
1629 static void chv_enable_pll(struct intel_crtc *crtc,
1630 const struct intel_crtc_state *pipe_config)
1631 {
1632 struct drm_device *dev = crtc->base.dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int pipe = crtc->pipe;
1635 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1636 u32 tmp;
1637
1638 assert_pipe_disabled(dev_priv, crtc->pipe);
1639
1640 mutex_lock(&dev_priv->sb_lock);
1641
1642 /* Enable back the 10bit clock to display controller */
1643 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1644 tmp |= DPIO_DCLKP_EN;
1645 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1646
1647 mutex_unlock(&dev_priv->sb_lock);
1648
1649 /*
1650 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1651 */
1652 udelay(1);
1653
1654 /* Enable PLL */
1655 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1656
1657 /* Check PLL is locked */
1658 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1659 DRM_ERROR("PLL %d failed to lock\n", pipe);
1660
1661 /* not sure when this should be written */
1662 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1663 POSTING_READ(DPLL_MD(pipe));
1664 }
1665
1666 static int intel_num_dvo_pipes(struct drm_device *dev)
1667 {
1668 struct intel_crtc *crtc;
1669 int count = 0;
1670
1671 for_each_intel_crtc(dev, crtc)
1672 count += crtc->base.state->active &&
1673 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1674
1675 return count;
1676 }
1677
1678 static void i9xx_enable_pll(struct intel_crtc *crtc)
1679 {
1680 struct drm_device *dev = crtc->base.dev;
1681 struct drm_i915_private *dev_priv = dev->dev_private;
1682 i915_reg_t reg = DPLL(crtc->pipe);
1683 u32 dpll = crtc->config->dpll_hw_state.dpll;
1684
1685 assert_pipe_disabled(dev_priv, crtc->pipe);
1686
1687 /* No really, not for ILK+ */
1688 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1689
1690 /* PLL is protected by panel, make sure we can write it */
1691 if (IS_MOBILE(dev) && !IS_I830(dev))
1692 assert_panel_unlocked(dev_priv, crtc->pipe);
1693
1694 /* Enable DVO 2x clock on both PLLs if necessary */
1695 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1696 /*
1697 * It appears to be important that we don't enable this
1698 * for the current pipe before otherwise configuring the
1699 * PLL. No idea how this should be handled if multiple
1700 * DVO outputs are enabled simultaneosly.
1701 */
1702 dpll |= DPLL_DVO_2X_MODE;
1703 I915_WRITE(DPLL(!crtc->pipe),
1704 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1705 }
1706
1707 /*
1708 * Apparently we need to have VGA mode enabled prior to changing
1709 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1710 * dividers, even though the register value does change.
1711 */
1712 I915_WRITE(reg, 0);
1713
1714 I915_WRITE(reg, dpll);
1715
1716 /* Wait for the clocks to stabilize. */
1717 POSTING_READ(reg);
1718 udelay(150);
1719
1720 if (INTEL_INFO(dev)->gen >= 4) {
1721 I915_WRITE(DPLL_MD(crtc->pipe),
1722 crtc->config->dpll_hw_state.dpll_md);
1723 } else {
1724 /* The pixel multiplier can only be updated once the
1725 * DPLL is enabled and the clocks are stable.
1726 *
1727 * So write it again.
1728 */
1729 I915_WRITE(reg, dpll);
1730 }
1731
1732 /* We do this three times for luck */
1733 I915_WRITE(reg, dpll);
1734 POSTING_READ(reg);
1735 udelay(150); /* wait for warmup */
1736 I915_WRITE(reg, dpll);
1737 POSTING_READ(reg);
1738 udelay(150); /* wait for warmup */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 }
1743
1744 /**
1745 * i9xx_disable_pll - disable a PLL
1746 * @dev_priv: i915 private structure
1747 * @pipe: pipe PLL to disable
1748 *
1749 * Disable the PLL for @pipe, making sure the pipe is off first.
1750 *
1751 * Note! This is for pre-ILK only.
1752 */
1753 static void i9xx_disable_pll(struct intel_crtc *crtc)
1754 {
1755 struct drm_device *dev = crtc->base.dev;
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 enum pipe pipe = crtc->pipe;
1758
1759 /* Disable DVO 2x clock on both PLLs if necessary */
1760 if (IS_I830(dev) &&
1761 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1762 !intel_num_dvo_pipes(dev)) {
1763 I915_WRITE(DPLL(PIPE_B),
1764 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1765 I915_WRITE(DPLL(PIPE_A),
1766 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1767 }
1768
1769 /* Don't disable pipe or pipe PLLs if needed */
1770 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1771 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1772 return;
1773
1774 /* Make sure the pipe isn't still relying on us */
1775 assert_pipe_disabled(dev_priv, pipe);
1776
1777 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1778 POSTING_READ(DPLL(pipe));
1779 }
1780
1781 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1782 {
1783 u32 val;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 /*
1789 * Leave integrated clock source and reference clock enabled for pipe B.
1790 * The latter is needed for VGA hotplug / manual detection.
1791 */
1792 val = DPLL_VGA_MODE_DIS;
1793 if (pipe == PIPE_B)
1794 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1795 I915_WRITE(DPLL(pipe), val);
1796 POSTING_READ(DPLL(pipe));
1797
1798 }
1799
1800 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1801 {
1802 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1803 u32 val;
1804
1805 /* Make sure the pipe isn't still relying on us */
1806 assert_pipe_disabled(dev_priv, pipe);
1807
1808 /* Set PLL en = 0 */
1809 val = DPLL_SSC_REF_CLK_CHV |
1810 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1811 if (pipe != PIPE_A)
1812 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1813 I915_WRITE(DPLL(pipe), val);
1814 POSTING_READ(DPLL(pipe));
1815
1816 mutex_lock(&dev_priv->sb_lock);
1817
1818 /* Disable 10bit clock to display controller */
1819 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1820 val &= ~DPIO_DCLKP_EN;
1821 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1822
1823 mutex_unlock(&dev_priv->sb_lock);
1824 }
1825
1826 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1827 struct intel_digital_port *dport,
1828 unsigned int expected_mask)
1829 {
1830 u32 port_mask;
1831 i915_reg_t dpll_reg;
1832
1833 switch (dport->port) {
1834 case PORT_B:
1835 port_mask = DPLL_PORTB_READY_MASK;
1836 dpll_reg = DPLL(0);
1837 break;
1838 case PORT_C:
1839 port_mask = DPLL_PORTC_READY_MASK;
1840 dpll_reg = DPLL(0);
1841 expected_mask <<= 4;
1842 break;
1843 case PORT_D:
1844 port_mask = DPLL_PORTD_READY_MASK;
1845 dpll_reg = DPIO_PHY_STATUS;
1846 break;
1847 default:
1848 BUG();
1849 }
1850
1851 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1852 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1853 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1854 }
1855
1856 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1857 {
1858 struct drm_device *dev = crtc->base.dev;
1859 struct drm_i915_private *dev_priv = dev->dev_private;
1860 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1861
1862 if (WARN_ON(pll == NULL))
1863 return;
1864
1865 WARN_ON(!pll->config.crtc_mask);
1866 if (pll->active == 0) {
1867 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1868 WARN_ON(pll->on);
1869 assert_shared_dpll_disabled(dev_priv, pll);
1870
1871 pll->mode_set(dev_priv, pll);
1872 }
1873 }
1874
1875 /**
1876 * intel_enable_shared_dpll - enable PCH PLL
1877 * @dev_priv: i915 private structure
1878 * @pipe: pipe PLL to enable
1879 *
1880 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1881 * drives the transcoder clock.
1882 */
1883 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1884 {
1885 struct drm_device *dev = crtc->base.dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1888
1889 if (WARN_ON(pll == NULL))
1890 return;
1891
1892 if (WARN_ON(pll->config.crtc_mask == 0))
1893 return;
1894
1895 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1896 pll->name, pll->active, pll->on,
1897 crtc->base.base.id);
1898
1899 if (pll->active++) {
1900 WARN_ON(!pll->on);
1901 assert_shared_dpll_enabled(dev_priv, pll);
1902 return;
1903 }
1904 WARN_ON(pll->on);
1905
1906 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1907
1908 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1909 pll->enable(dev_priv, pll);
1910 pll->on = true;
1911 }
1912
1913 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1914 {
1915 struct drm_device *dev = crtc->base.dev;
1916 struct drm_i915_private *dev_priv = dev->dev_private;
1917 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1918
1919 /* PCH only available on ILK+ */
1920 if (INTEL_INFO(dev)->gen < 5)
1921 return;
1922
1923 if (pll == NULL)
1924 return;
1925
1926 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1927 return;
1928
1929 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1930 pll->name, pll->active, pll->on,
1931 crtc->base.base.id);
1932
1933 if (WARN_ON(pll->active == 0)) {
1934 assert_shared_dpll_disabled(dev_priv, pll);
1935 return;
1936 }
1937
1938 assert_shared_dpll_enabled(dev_priv, pll);
1939 WARN_ON(!pll->on);
1940 if (--pll->active)
1941 return;
1942
1943 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1944 pll->disable(dev_priv, pll);
1945 pll->on = false;
1946
1947 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1948 }
1949
1950 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1951 enum pipe pipe)
1952 {
1953 struct drm_device *dev = dev_priv->dev;
1954 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1956 i915_reg_t reg;
1957 uint32_t val, pipeconf_val;
1958
1959 /* PCH only available on ILK+ */
1960 BUG_ON(!HAS_PCH_SPLIT(dev));
1961
1962 /* Make sure PCH DPLL is enabled */
1963 assert_shared_dpll_enabled(dev_priv,
1964 intel_crtc_to_shared_dpll(intel_crtc));
1965
1966 /* FDI must be feeding us bits for PCH ports */
1967 assert_fdi_tx_enabled(dev_priv, pipe);
1968 assert_fdi_rx_enabled(dev_priv, pipe);
1969
1970 if (HAS_PCH_CPT(dev)) {
1971 /* Workaround: Set the timing override bit before enabling the
1972 * pch transcoder. */
1973 reg = TRANS_CHICKEN2(pipe);
1974 val = I915_READ(reg);
1975 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1976 I915_WRITE(reg, val);
1977 }
1978
1979 reg = PCH_TRANSCONF(pipe);
1980 val = I915_READ(reg);
1981 pipeconf_val = I915_READ(PIPECONF(pipe));
1982
1983 if (HAS_PCH_IBX(dev_priv->dev)) {
1984 /*
1985 * Make the BPC in transcoder be consistent with
1986 * that in pipeconf reg. For HDMI we must use 8bpc
1987 * here for both 8bpc and 12bpc.
1988 */
1989 val &= ~PIPECONF_BPC_MASK;
1990 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1991 val |= PIPECONF_8BPC;
1992 else
1993 val |= pipeconf_val & PIPECONF_BPC_MASK;
1994 }
1995
1996 val &= ~TRANS_INTERLACE_MASK;
1997 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1998 if (HAS_PCH_IBX(dev_priv->dev) &&
1999 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2000 val |= TRANS_LEGACY_INTERLACED_ILK;
2001 else
2002 val |= TRANS_INTERLACED;
2003 else
2004 val |= TRANS_PROGRESSIVE;
2005
2006 I915_WRITE(reg, val | TRANS_ENABLE);
2007 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2008 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2009 }
2010
2011 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2012 enum transcoder cpu_transcoder)
2013 {
2014 u32 val, pipeconf_val;
2015
2016 /* PCH only available on ILK+ */
2017 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2018
2019 /* FDI must be feeding us bits for PCH ports */
2020 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2021 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2022
2023 /* Workaround: set timing override bit. */
2024 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2025 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2026 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2027
2028 val = TRANS_ENABLE;
2029 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2030
2031 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2032 PIPECONF_INTERLACED_ILK)
2033 val |= TRANS_INTERLACED;
2034 else
2035 val |= TRANS_PROGRESSIVE;
2036
2037 I915_WRITE(LPT_TRANSCONF, val);
2038 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2039 DRM_ERROR("Failed to enable PCH transcoder\n");
2040 }
2041
2042 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2043 enum pipe pipe)
2044 {
2045 struct drm_device *dev = dev_priv->dev;
2046 i915_reg_t reg;
2047 uint32_t val;
2048
2049 /* FDI relies on the transcoder */
2050 assert_fdi_tx_disabled(dev_priv, pipe);
2051 assert_fdi_rx_disabled(dev_priv, pipe);
2052
2053 /* Ports must be off as well */
2054 assert_pch_ports_disabled(dev_priv, pipe);
2055
2056 reg = PCH_TRANSCONF(pipe);
2057 val = I915_READ(reg);
2058 val &= ~TRANS_ENABLE;
2059 I915_WRITE(reg, val);
2060 /* wait for PCH transcoder off, transcoder state */
2061 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2062 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2063
2064 if (HAS_PCH_CPT(dev)) {
2065 /* Workaround: Clear the timing override chicken bit again. */
2066 reg = TRANS_CHICKEN2(pipe);
2067 val = I915_READ(reg);
2068 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2069 I915_WRITE(reg, val);
2070 }
2071 }
2072
2073 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2074 {
2075 u32 val;
2076
2077 val = I915_READ(LPT_TRANSCONF);
2078 val &= ~TRANS_ENABLE;
2079 I915_WRITE(LPT_TRANSCONF, val);
2080 /* wait for PCH transcoder off, transcoder state */
2081 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2082 DRM_ERROR("Failed to disable PCH transcoder\n");
2083
2084 /* Workaround: clear timing override bit. */
2085 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2086 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2087 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2088 }
2089
2090 /**
2091 * intel_enable_pipe - enable a pipe, asserting requirements
2092 * @crtc: crtc responsible for the pipe
2093 *
2094 * Enable @crtc's pipe, making sure that various hardware specific requirements
2095 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2096 */
2097 static void intel_enable_pipe(struct intel_crtc *crtc)
2098 {
2099 struct drm_device *dev = crtc->base.dev;
2100 struct drm_i915_private *dev_priv = dev->dev_private;
2101 enum pipe pipe = crtc->pipe;
2102 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2103 enum pipe pch_transcoder;
2104 i915_reg_t reg;
2105 u32 val;
2106
2107 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2108
2109 assert_planes_disabled(dev_priv, pipe);
2110 assert_cursor_disabled(dev_priv, pipe);
2111 assert_sprites_disabled(dev_priv, pipe);
2112
2113 if (HAS_PCH_LPT(dev_priv->dev))
2114 pch_transcoder = TRANSCODER_A;
2115 else
2116 pch_transcoder = pipe;
2117
2118 /*
2119 * A pipe without a PLL won't actually be able to drive bits from
2120 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2121 * need the check.
2122 */
2123 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2124 if (crtc->config->has_dsi_encoder)
2125 assert_dsi_pll_enabled(dev_priv);
2126 else
2127 assert_pll_enabled(dev_priv, pipe);
2128 else {
2129 if (crtc->config->has_pch_encoder) {
2130 /* if driving the PCH, we need FDI enabled */
2131 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2132 assert_fdi_tx_pll_enabled(dev_priv,
2133 (enum pipe) cpu_transcoder);
2134 }
2135 /* FIXME: assert CPU port conditions for SNB+ */
2136 }
2137
2138 reg = PIPECONF(cpu_transcoder);
2139 val = I915_READ(reg);
2140 if (val & PIPECONF_ENABLE) {
2141 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2142 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2143 return;
2144 }
2145
2146 I915_WRITE(reg, val | PIPECONF_ENABLE);
2147 POSTING_READ(reg);
2148
2149 /*
2150 * Until the pipe starts DSL will read as 0, which would cause
2151 * an apparent vblank timestamp jump, which messes up also the
2152 * frame count when it's derived from the timestamps. So let's
2153 * wait for the pipe to start properly before we call
2154 * drm_crtc_vblank_on()
2155 */
2156 if (dev->max_vblank_count == 0 &&
2157 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2158 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2159 }
2160
2161 /**
2162 * intel_disable_pipe - disable a pipe, asserting requirements
2163 * @crtc: crtc whose pipes is to be disabled
2164 *
2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175 enum pipe pipe = crtc->pipe;
2176 i915_reg_t reg;
2177 u32 val;
2178
2179 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2180
2181 /*
2182 * Make sure planes won't keep trying to pump pixels to us,
2183 * or we might hang the display.
2184 */
2185 assert_planes_disabled(dev_priv, pipe);
2186 assert_cursor_disabled(dev_priv, pipe);
2187 assert_sprites_disabled(dev_priv, pipe);
2188
2189 reg = PIPECONF(cpu_transcoder);
2190 val = I915_READ(reg);
2191 if ((val & PIPECONF_ENABLE) == 0)
2192 return;
2193
2194 /*
2195 * Double wide has implications for planes
2196 * so best keep it disabled when not needed.
2197 */
2198 if (crtc->config->double_wide)
2199 val &= ~PIPECONF_DOUBLE_WIDE;
2200
2201 /* Don't disable pipe or pipe PLLs if needed */
2202 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2203 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2204 val &= ~PIPECONF_ENABLE;
2205
2206 I915_WRITE(reg, val);
2207 if ((val & PIPECONF_ENABLE) == 0)
2208 intel_wait_for_pipe_off(crtc);
2209 }
2210
2211 static bool need_vtd_wa(struct drm_device *dev)
2212 {
2213 #ifdef CONFIG_INTEL_IOMMU
2214 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2215 return true;
2216 #endif
2217 return false;
2218 }
2219
2220 static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
2221 {
2222 return IS_GEN2(dev_priv) ? 2048 : 4096;
2223 }
2224
2225 static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
2226 uint64_t fb_modifier, unsigned int cpp)
2227 {
2228 switch (fb_modifier) {
2229 case DRM_FORMAT_MOD_NONE:
2230 return cpp;
2231 case I915_FORMAT_MOD_X_TILED:
2232 if (IS_GEN2(dev_priv))
2233 return 128;
2234 else
2235 return 512;
2236 case I915_FORMAT_MOD_Y_TILED:
2237 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2238 return 128;
2239 else
2240 return 512;
2241 case I915_FORMAT_MOD_Yf_TILED:
2242 switch (cpp) {
2243 case 1:
2244 return 64;
2245 case 2:
2246 case 4:
2247 return 128;
2248 case 8:
2249 case 16:
2250 return 256;
2251 default:
2252 MISSING_CASE(cpp);
2253 return cpp;
2254 }
2255 break;
2256 default:
2257 MISSING_CASE(fb_modifier);
2258 return cpp;
2259 }
2260 }
2261
2262 unsigned int intel_tile_height(const struct drm_i915_private *dev_priv,
2263 uint64_t fb_modifier, unsigned int cpp)
2264 {
2265 if (fb_modifier == DRM_FORMAT_MOD_NONE)
2266 return 1;
2267 else
2268 return intel_tile_size(dev_priv) /
2269 intel_tile_width(dev_priv, fb_modifier, cpp);
2270 }
2271
2272 unsigned int
2273 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2274 uint32_t pixel_format, uint64_t fb_modifier)
2275 {
2276 unsigned int cpp = drm_format_plane_cpp(pixel_format, 0);
2277 unsigned int tile_height = intel_tile_height(to_i915(dev), fb_modifier, cpp);
2278
2279 return ALIGN(height, tile_height);
2280 }
2281
2282 static void
2283 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2284 const struct drm_plane_state *plane_state)
2285 {
2286 struct drm_i915_private *dev_priv = to_i915(fb->dev);
2287 struct intel_rotation_info *info = &view->params.rotated;
2288 unsigned int tile_size, tile_width, tile_height, cpp;
2289
2290 *view = i915_ggtt_view_normal;
2291
2292 if (!plane_state)
2293 return;
2294
2295 if (!intel_rotation_90_or_270(plane_state->rotation))
2296 return;
2297
2298 *view = i915_ggtt_view_rotated;
2299
2300 info->height = fb->height;
2301 info->pixel_format = fb->pixel_format;
2302 info->pitch = fb->pitches[0];
2303 info->uv_offset = fb->offsets[1];
2304 info->fb_modifier = fb->modifier[0];
2305
2306 tile_size = intel_tile_size(dev_priv);
2307
2308 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2309 tile_width = intel_tile_width(dev_priv, fb->modifier[0], cpp);
2310 tile_height = tile_size / tile_width;
2311
2312 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_width);
2313 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2314 info->size = info->width_pages * info->height_pages * tile_size;
2315
2316 if (info->pixel_format == DRM_FORMAT_NV12) {
2317 cpp = drm_format_plane_cpp(fb->pixel_format, 1);
2318 tile_width = intel_tile_width(dev_priv, fb->modifier[1], cpp);
2319 tile_height = tile_size / tile_width;
2320
2321 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[1], tile_width);
2322 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2, tile_height);
2323 info->size_uv = info->width_pages_uv * info->height_pages_uv * tile_size;
2324 }
2325 }
2326
2327 static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_priv)
2328 {
2329 if (INTEL_INFO(dev_priv)->gen >= 9)
2330 return 256 * 1024;
2331 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2332 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2333 return 128 * 1024;
2334 else if (INTEL_INFO(dev_priv)->gen >= 4)
2335 return 4 * 1024;
2336 else
2337 return 0;
2338 }
2339
2340 static unsigned int intel_surf_alignment(const struct drm_i915_private *dev_priv,
2341 uint64_t fb_modifier)
2342 {
2343 switch (fb_modifier) {
2344 case DRM_FORMAT_MOD_NONE:
2345 return intel_linear_alignment(dev_priv);
2346 case I915_FORMAT_MOD_X_TILED:
2347 if (INTEL_INFO(dev_priv)->gen >= 9)
2348 return 256 * 1024;
2349 return 0;
2350 case I915_FORMAT_MOD_Y_TILED:
2351 case I915_FORMAT_MOD_Yf_TILED:
2352 return 1 * 1024 * 1024;
2353 default:
2354 MISSING_CASE(fb_modifier);
2355 return 0;
2356 }
2357 }
2358
2359 int
2360 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2361 struct drm_framebuffer *fb,
2362 const struct drm_plane_state *plane_state)
2363 {
2364 struct drm_device *dev = fb->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2367 struct i915_ggtt_view view;
2368 u32 alignment;
2369 int ret;
2370
2371 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2372
2373 alignment = intel_surf_alignment(dev_priv, fb->modifier[0]);
2374
2375 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2376
2377 /* Note that the w/a also requires 64 PTE of padding following the
2378 * bo. We currently fill all unused PTE with the shadow page and so
2379 * we should always have valid PTE following the scanout preventing
2380 * the VT-d warning.
2381 */
2382 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2383 alignment = 256 * 1024;
2384
2385 /*
2386 * Global gtt pte registers are special registers which actually forward
2387 * writes to a chunk of system memory. Which means that there is no risk
2388 * that the register values disappear as soon as we call
2389 * intel_runtime_pm_put(), so it is correct to wrap only the
2390 * pin/unpin/fence and not more.
2391 */
2392 intel_runtime_pm_get(dev_priv);
2393
2394 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2395 &view);
2396 if (ret)
2397 goto err_pm;
2398
2399 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2400 * fence, whereas 965+ only requires a fence if using
2401 * framebuffer compression. For simplicity, we always install
2402 * a fence as the cost is not that onerous.
2403 */
2404 if (view.type == I915_GGTT_VIEW_NORMAL) {
2405 ret = i915_gem_object_get_fence(obj);
2406 if (ret == -EDEADLK) {
2407 /*
2408 * -EDEADLK means there are no free fences
2409 * no pending flips.
2410 *
2411 * This is propagated to atomic, but it uses
2412 * -EDEADLK to force a locking recovery, so
2413 * change the returned error to -EBUSY.
2414 */
2415 ret = -EBUSY;
2416 goto err_unpin;
2417 } else if (ret)
2418 goto err_unpin;
2419
2420 i915_gem_object_pin_fence(obj);
2421 }
2422
2423 intel_runtime_pm_put(dev_priv);
2424 return 0;
2425
2426 err_unpin:
2427 i915_gem_object_unpin_from_display_plane(obj, &view);
2428 err_pm:
2429 intel_runtime_pm_put(dev_priv);
2430 return ret;
2431 }
2432
2433 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
2435 {
2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2437 struct i915_ggtt_view view;
2438
2439 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2440
2441 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2442
2443 if (view.type == I915_GGTT_VIEW_NORMAL)
2444 i915_gem_object_unpin_fence(obj);
2445
2446 i915_gem_object_unpin_from_display_plane(obj, &view);
2447 }
2448
2449 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
2451 u32 intel_compute_tile_offset(struct drm_i915_private *dev_priv,
2452 int *x, int *y,
2453 uint64_t fb_modifier,
2454 unsigned int cpp,
2455 unsigned int pitch)
2456 {
2457 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2458 unsigned int tile_size, tile_width, tile_height;
2459 unsigned int tile_rows, tiles;
2460
2461 tile_size = intel_tile_size(dev_priv);
2462 tile_width = intel_tile_width(dev_priv, fb_modifier, cpp);
2463 tile_height = tile_size / tile_width;
2464
2465 tile_rows = *y / tile_height;
2466 *y %= tile_height;
2467
2468 tiles = *x / (tile_width/cpp);
2469 *x %= tile_width/cpp;
2470
2471 return tile_rows * pitch * tile_height + tiles * tile_size;
2472 } else {
2473 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2474 unsigned int offset;
2475
2476 offset = *y * pitch + *x * cpp;
2477 *y = (offset & alignment) / pitch;
2478 *x = ((offset & alignment) - *y * pitch) / cpp;
2479 return offset & ~alignment;
2480 }
2481 }
2482
2483 static int i9xx_format_to_fourcc(int format)
2484 {
2485 switch (format) {
2486 case DISPPLANE_8BPP:
2487 return DRM_FORMAT_C8;
2488 case DISPPLANE_BGRX555:
2489 return DRM_FORMAT_XRGB1555;
2490 case DISPPLANE_BGRX565:
2491 return DRM_FORMAT_RGB565;
2492 default:
2493 case DISPPLANE_BGRX888:
2494 return DRM_FORMAT_XRGB8888;
2495 case DISPPLANE_RGBX888:
2496 return DRM_FORMAT_XBGR8888;
2497 case DISPPLANE_BGRX101010:
2498 return DRM_FORMAT_XRGB2101010;
2499 case DISPPLANE_RGBX101010:
2500 return DRM_FORMAT_XBGR2101010;
2501 }
2502 }
2503
2504 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2505 {
2506 switch (format) {
2507 case PLANE_CTL_FORMAT_RGB_565:
2508 return DRM_FORMAT_RGB565;
2509 default:
2510 case PLANE_CTL_FORMAT_XRGB_8888:
2511 if (rgb_order) {
2512 if (alpha)
2513 return DRM_FORMAT_ABGR8888;
2514 else
2515 return DRM_FORMAT_XBGR8888;
2516 } else {
2517 if (alpha)
2518 return DRM_FORMAT_ARGB8888;
2519 else
2520 return DRM_FORMAT_XRGB8888;
2521 }
2522 case PLANE_CTL_FORMAT_XRGB_2101010:
2523 if (rgb_order)
2524 return DRM_FORMAT_XBGR2101010;
2525 else
2526 return DRM_FORMAT_XRGB2101010;
2527 }
2528 }
2529
2530 static bool
2531 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2532 struct intel_initial_plane_config *plane_config)
2533 {
2534 struct drm_device *dev = crtc->base.dev;
2535 struct drm_i915_private *dev_priv = to_i915(dev);
2536 struct drm_i915_gem_object *obj = NULL;
2537 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2538 struct drm_framebuffer *fb = &plane_config->fb->base;
2539 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2540 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2541 PAGE_SIZE);
2542
2543 size_aligned -= base_aligned;
2544
2545 if (plane_config->size == 0)
2546 return false;
2547
2548 /* If the FB is too big, just don't use it since fbdev is not very
2549 * important and we should probably use that space with FBC or other
2550 * features. */
2551 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2552 return false;
2553
2554 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2555 base_aligned,
2556 base_aligned,
2557 size_aligned);
2558 if (!obj)
2559 return false;
2560
2561 obj->tiling_mode = plane_config->tiling;
2562 if (obj->tiling_mode == I915_TILING_X)
2563 obj->stride = fb->pitches[0];
2564
2565 mode_cmd.pixel_format = fb->pixel_format;
2566 mode_cmd.width = fb->width;
2567 mode_cmd.height = fb->height;
2568 mode_cmd.pitches[0] = fb->pitches[0];
2569 mode_cmd.modifier[0] = fb->modifier[0];
2570 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2571
2572 mutex_lock(&dev->struct_mutex);
2573 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2574 &mode_cmd, obj)) {
2575 DRM_DEBUG_KMS("intel fb init failed\n");
2576 goto out_unref_obj;
2577 }
2578 mutex_unlock(&dev->struct_mutex);
2579
2580 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2581 return true;
2582
2583 out_unref_obj:
2584 drm_gem_object_unreference(&obj->base);
2585 mutex_unlock(&dev->struct_mutex);
2586 return false;
2587 }
2588
2589 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2590 static void
2591 update_state_fb(struct drm_plane *plane)
2592 {
2593 if (plane->fb == plane->state->fb)
2594 return;
2595
2596 if (plane->state->fb)
2597 drm_framebuffer_unreference(plane->state->fb);
2598 plane->state->fb = plane->fb;
2599 if (plane->state->fb)
2600 drm_framebuffer_reference(plane->state->fb);
2601 }
2602
2603 static void
2604 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2605 struct intel_initial_plane_config *plane_config)
2606 {
2607 struct drm_device *dev = intel_crtc->base.dev;
2608 struct drm_i915_private *dev_priv = dev->dev_private;
2609 struct drm_crtc *c;
2610 struct intel_crtc *i;
2611 struct drm_i915_gem_object *obj;
2612 struct drm_plane *primary = intel_crtc->base.primary;
2613 struct drm_plane_state *plane_state = primary->state;
2614 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2615 struct intel_plane *intel_plane = to_intel_plane(primary);
2616 struct intel_plane_state *intel_state =
2617 to_intel_plane_state(plane_state);
2618 struct drm_framebuffer *fb;
2619
2620 if (!plane_config->fb)
2621 return;
2622
2623 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2624 fb = &plane_config->fb->base;
2625 goto valid_fb;
2626 }
2627
2628 kfree(plane_config->fb);
2629
2630 /*
2631 * Failed to alloc the obj, check to see if we should share
2632 * an fb with another CRTC instead
2633 */
2634 for_each_crtc(dev, c) {
2635 i = to_intel_crtc(c);
2636
2637 if (c == &intel_crtc->base)
2638 continue;
2639
2640 if (!i->active)
2641 continue;
2642
2643 fb = c->primary->fb;
2644 if (!fb)
2645 continue;
2646
2647 obj = intel_fb_obj(fb);
2648 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2649 drm_framebuffer_reference(fb);
2650 goto valid_fb;
2651 }
2652 }
2653
2654 /*
2655 * We've failed to reconstruct the BIOS FB. Current display state
2656 * indicates that the primary plane is visible, but has a NULL FB,
2657 * which will lead to problems later if we don't fix it up. The
2658 * simplest solution is to just disable the primary plane now and
2659 * pretend the BIOS never had it enabled.
2660 */
2661 to_intel_plane_state(plane_state)->visible = false;
2662 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2663 intel_pre_disable_primary(&intel_crtc->base);
2664 intel_plane->disable_plane(primary, &intel_crtc->base);
2665
2666 return;
2667
2668 valid_fb:
2669 plane_state->src_x = 0;
2670 plane_state->src_y = 0;
2671 plane_state->src_w = fb->width << 16;
2672 plane_state->src_h = fb->height << 16;
2673
2674 plane_state->crtc_x = 0;
2675 plane_state->crtc_y = 0;
2676 plane_state->crtc_w = fb->width;
2677 plane_state->crtc_h = fb->height;
2678
2679 intel_state->src.x1 = plane_state->src_x;
2680 intel_state->src.y1 = plane_state->src_y;
2681 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2682 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2683 intel_state->dst.x1 = plane_state->crtc_x;
2684 intel_state->dst.y1 = plane_state->crtc_y;
2685 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2686 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2687
2688 obj = intel_fb_obj(fb);
2689 if (obj->tiling_mode != I915_TILING_NONE)
2690 dev_priv->preserve_bios_swizzle = true;
2691
2692 drm_framebuffer_reference(fb);
2693 primary->fb = primary->state->fb = fb;
2694 primary->crtc = primary->state->crtc = &intel_crtc->base;
2695 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2696 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2697 }
2698
2699 static void i9xx_update_primary_plane(struct drm_plane *primary,
2700 const struct intel_crtc_state *crtc_state,
2701 const struct intel_plane_state *plane_state)
2702 {
2703 struct drm_device *dev = primary->dev;
2704 struct drm_i915_private *dev_priv = dev->dev_private;
2705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2706 struct drm_framebuffer *fb = plane_state->base.fb;
2707 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2708 int plane = intel_crtc->plane;
2709 u32 linear_offset;
2710 u32 dspcntr;
2711 i915_reg_t reg = DSPCNTR(plane);
2712 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2713 int x = plane_state->src.x1 >> 16;
2714 int y = plane_state->src.y1 >> 16;
2715
2716 dspcntr = DISPPLANE_GAMMA_ENABLE;
2717
2718 dspcntr |= DISPLAY_PLANE_ENABLE;
2719
2720 if (INTEL_INFO(dev)->gen < 4) {
2721 if (intel_crtc->pipe == PIPE_B)
2722 dspcntr |= DISPPLANE_SEL_PIPE_B;
2723
2724 /* pipesrc and dspsize control the size that is scaled from,
2725 * which should always be the user's requested size.
2726 */
2727 I915_WRITE(DSPSIZE(plane),
2728 ((crtc_state->pipe_src_h - 1) << 16) |
2729 (crtc_state->pipe_src_w - 1));
2730 I915_WRITE(DSPPOS(plane), 0);
2731 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2732 I915_WRITE(PRIMSIZE(plane),
2733 ((crtc_state->pipe_src_h - 1) << 16) |
2734 (crtc_state->pipe_src_w - 1));
2735 I915_WRITE(PRIMPOS(plane), 0);
2736 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2737 }
2738
2739 switch (fb->pixel_format) {
2740 case DRM_FORMAT_C8:
2741 dspcntr |= DISPPLANE_8BPP;
2742 break;
2743 case DRM_FORMAT_XRGB1555:
2744 dspcntr |= DISPPLANE_BGRX555;
2745 break;
2746 case DRM_FORMAT_RGB565:
2747 dspcntr |= DISPPLANE_BGRX565;
2748 break;
2749 case DRM_FORMAT_XRGB8888:
2750 dspcntr |= DISPPLANE_BGRX888;
2751 break;
2752 case DRM_FORMAT_XBGR8888:
2753 dspcntr |= DISPPLANE_RGBX888;
2754 break;
2755 case DRM_FORMAT_XRGB2101010:
2756 dspcntr |= DISPPLANE_BGRX101010;
2757 break;
2758 case DRM_FORMAT_XBGR2101010:
2759 dspcntr |= DISPPLANE_RGBX101010;
2760 break;
2761 default:
2762 BUG();
2763 }
2764
2765 if (INTEL_INFO(dev)->gen >= 4 &&
2766 obj->tiling_mode != I915_TILING_NONE)
2767 dspcntr |= DISPPLANE_TILED;
2768
2769 if (IS_G4X(dev))
2770 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2771
2772 linear_offset = y * fb->pitches[0] + x * cpp;
2773
2774 if (INTEL_INFO(dev)->gen >= 4) {
2775 intel_crtc->dspaddr_offset =
2776 intel_compute_tile_offset(dev_priv, &x, &y,
2777 fb->modifier[0], cpp,
2778 fb->pitches[0]);
2779 linear_offset -= intel_crtc->dspaddr_offset;
2780 } else {
2781 intel_crtc->dspaddr_offset = linear_offset;
2782 }
2783
2784 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2785 dspcntr |= DISPPLANE_ROTATE_180;
2786
2787 x += (crtc_state->pipe_src_w - 1);
2788 y += (crtc_state->pipe_src_h - 1);
2789
2790 /* Finding the last pixel of the last line of the display
2791 data and adding to linear_offset*/
2792 linear_offset +=
2793 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2794 (crtc_state->pipe_src_w - 1) * cpp;
2795 }
2796
2797 intel_crtc->adjusted_x = x;
2798 intel_crtc->adjusted_y = y;
2799
2800 I915_WRITE(reg, dspcntr);
2801
2802 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2803 if (INTEL_INFO(dev)->gen >= 4) {
2804 I915_WRITE(DSPSURF(plane),
2805 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2806 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2807 I915_WRITE(DSPLINOFF(plane), linear_offset);
2808 } else
2809 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2810 POSTING_READ(reg);
2811 }
2812
2813 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2814 struct drm_crtc *crtc)
2815 {
2816 struct drm_device *dev = crtc->dev;
2817 struct drm_i915_private *dev_priv = dev->dev_private;
2818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2819 int plane = intel_crtc->plane;
2820
2821 I915_WRITE(DSPCNTR(plane), 0);
2822 if (INTEL_INFO(dev_priv)->gen >= 4)
2823 I915_WRITE(DSPSURF(plane), 0);
2824 else
2825 I915_WRITE(DSPADDR(plane), 0);
2826 POSTING_READ(DSPCNTR(plane));
2827 }
2828
2829 static void ironlake_update_primary_plane(struct drm_plane *primary,
2830 const struct intel_crtc_state *crtc_state,
2831 const struct intel_plane_state *plane_state)
2832 {
2833 struct drm_device *dev = primary->dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2836 struct drm_framebuffer *fb = plane_state->base.fb;
2837 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2838 int plane = intel_crtc->plane;
2839 u32 linear_offset;
2840 u32 dspcntr;
2841 i915_reg_t reg = DSPCNTR(plane);
2842 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
2843 int x = plane_state->src.x1 >> 16;
2844 int y = plane_state->src.y1 >> 16;
2845
2846 dspcntr = DISPPLANE_GAMMA_ENABLE;
2847 dspcntr |= DISPLAY_PLANE_ENABLE;
2848
2849 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2850 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2851
2852 switch (fb->pixel_format) {
2853 case DRM_FORMAT_C8:
2854 dspcntr |= DISPPLANE_8BPP;
2855 break;
2856 case DRM_FORMAT_RGB565:
2857 dspcntr |= DISPPLANE_BGRX565;
2858 break;
2859 case DRM_FORMAT_XRGB8888:
2860 dspcntr |= DISPPLANE_BGRX888;
2861 break;
2862 case DRM_FORMAT_XBGR8888:
2863 dspcntr |= DISPPLANE_RGBX888;
2864 break;
2865 case DRM_FORMAT_XRGB2101010:
2866 dspcntr |= DISPPLANE_BGRX101010;
2867 break;
2868 case DRM_FORMAT_XBGR2101010:
2869 dspcntr |= DISPPLANE_RGBX101010;
2870 break;
2871 default:
2872 BUG();
2873 }
2874
2875 if (obj->tiling_mode != I915_TILING_NONE)
2876 dspcntr |= DISPPLANE_TILED;
2877
2878 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2879 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2880
2881 linear_offset = y * fb->pitches[0] + x * cpp;
2882 intel_crtc->dspaddr_offset =
2883 intel_compute_tile_offset(dev_priv, &x, &y,
2884 fb->modifier[0], cpp,
2885 fb->pitches[0]);
2886 linear_offset -= intel_crtc->dspaddr_offset;
2887 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2888 dspcntr |= DISPPLANE_ROTATE_180;
2889
2890 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2891 x += (crtc_state->pipe_src_w - 1);
2892 y += (crtc_state->pipe_src_h - 1);
2893
2894 /* Finding the last pixel of the last line of the display
2895 data and adding to linear_offset*/
2896 linear_offset +=
2897 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2898 (crtc_state->pipe_src_w - 1) * cpp;
2899 }
2900 }
2901
2902 intel_crtc->adjusted_x = x;
2903 intel_crtc->adjusted_y = y;
2904
2905 I915_WRITE(reg, dspcntr);
2906
2907 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2908 I915_WRITE(DSPSURF(plane),
2909 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2910 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2911 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2912 } else {
2913 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2914 I915_WRITE(DSPLINOFF(plane), linear_offset);
2915 }
2916 POSTING_READ(reg);
2917 }
2918
2919 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2920 uint64_t fb_modifier, uint32_t pixel_format)
2921 {
2922 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2923 return 64;
2924 } else {
2925 int cpp = drm_format_plane_cpp(pixel_format, 0);
2926
2927 return intel_tile_width(dev_priv, fb_modifier, cpp);
2928 }
2929 }
2930
2931 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2932 struct drm_i915_gem_object *obj,
2933 unsigned int plane)
2934 {
2935 struct i915_ggtt_view view;
2936 struct i915_vma *vma;
2937 u64 offset;
2938
2939 intel_fill_fb_ggtt_view(&view, intel_plane->base.state->fb,
2940 intel_plane->base.state);
2941
2942 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2943 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2944 view.type))
2945 return -1;
2946
2947 offset = vma->node.start;
2948
2949 if (plane == 1) {
2950 offset += vma->ggtt_view.params.rotated.uv_start_page *
2951 PAGE_SIZE;
2952 }
2953
2954 WARN_ON(upper_32_bits(offset));
2955
2956 return lower_32_bits(offset);
2957 }
2958
2959 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2960 {
2961 struct drm_device *dev = intel_crtc->base.dev;
2962 struct drm_i915_private *dev_priv = dev->dev_private;
2963
2964 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2965 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2966 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2967 }
2968
2969 /*
2970 * This function detaches (aka. unbinds) unused scalers in hardware
2971 */
2972 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2973 {
2974 struct intel_crtc_scaler_state *scaler_state;
2975 int i;
2976
2977 scaler_state = &intel_crtc->config->scaler_state;
2978
2979 /* loop through and disable scalers that aren't in use */
2980 for (i = 0; i < intel_crtc->num_scalers; i++) {
2981 if (!scaler_state->scalers[i].in_use)
2982 skl_detach_scaler(intel_crtc, i);
2983 }
2984 }
2985
2986 u32 skl_plane_ctl_format(uint32_t pixel_format)
2987 {
2988 switch (pixel_format) {
2989 case DRM_FORMAT_C8:
2990 return PLANE_CTL_FORMAT_INDEXED;
2991 case DRM_FORMAT_RGB565:
2992 return PLANE_CTL_FORMAT_RGB_565;
2993 case DRM_FORMAT_XBGR8888:
2994 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2995 case DRM_FORMAT_XRGB8888:
2996 return PLANE_CTL_FORMAT_XRGB_8888;
2997 /*
2998 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2999 * to be already pre-multiplied. We need to add a knob (or a different
3000 * DRM_FORMAT) for user-space to configure that.
3001 */
3002 case DRM_FORMAT_ABGR8888:
3003 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3004 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3005 case DRM_FORMAT_ARGB8888:
3006 return PLANE_CTL_FORMAT_XRGB_8888 |
3007 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3008 case DRM_FORMAT_XRGB2101010:
3009 return PLANE_CTL_FORMAT_XRGB_2101010;
3010 case DRM_FORMAT_XBGR2101010:
3011 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3012 case DRM_FORMAT_YUYV:
3013 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3014 case DRM_FORMAT_YVYU:
3015 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3016 case DRM_FORMAT_UYVY:
3017 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3018 case DRM_FORMAT_VYUY:
3019 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3020 default:
3021 MISSING_CASE(pixel_format);
3022 }
3023
3024 return 0;
3025 }
3026
3027 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3028 {
3029 switch (fb_modifier) {
3030 case DRM_FORMAT_MOD_NONE:
3031 break;
3032 case I915_FORMAT_MOD_X_TILED:
3033 return PLANE_CTL_TILED_X;
3034 case I915_FORMAT_MOD_Y_TILED:
3035 return PLANE_CTL_TILED_Y;
3036 case I915_FORMAT_MOD_Yf_TILED:
3037 return PLANE_CTL_TILED_YF;
3038 default:
3039 MISSING_CASE(fb_modifier);
3040 }
3041
3042 return 0;
3043 }
3044
3045 u32 skl_plane_ctl_rotation(unsigned int rotation)
3046 {
3047 switch (rotation) {
3048 case BIT(DRM_ROTATE_0):
3049 break;
3050 /*
3051 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3052 * while i915 HW rotation is clockwise, thats why this swapping.
3053 */
3054 case BIT(DRM_ROTATE_90):
3055 return PLANE_CTL_ROTATE_270;
3056 case BIT(DRM_ROTATE_180):
3057 return PLANE_CTL_ROTATE_180;
3058 case BIT(DRM_ROTATE_270):
3059 return PLANE_CTL_ROTATE_90;
3060 default:
3061 MISSING_CASE(rotation);
3062 }
3063
3064 return 0;
3065 }
3066
3067 static void skylake_update_primary_plane(struct drm_plane *plane,
3068 const struct intel_crtc_state *crtc_state,
3069 const struct intel_plane_state *plane_state)
3070 {
3071 struct drm_device *dev = plane->dev;
3072 struct drm_i915_private *dev_priv = dev->dev_private;
3073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3074 struct drm_framebuffer *fb = plane_state->base.fb;
3075 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3076 int pipe = intel_crtc->pipe;
3077 u32 plane_ctl, stride_div, stride;
3078 u32 tile_height, plane_offset, plane_size;
3079 unsigned int rotation = plane_state->base.rotation;
3080 int x_offset, y_offset;
3081 u32 surf_addr;
3082 int scaler_id = plane_state->scaler_id;
3083 int src_x = plane_state->src.x1 >> 16;
3084 int src_y = plane_state->src.y1 >> 16;
3085 int src_w = drm_rect_width(&plane_state->src) >> 16;
3086 int src_h = drm_rect_height(&plane_state->src) >> 16;
3087 int dst_x = plane_state->dst.x1;
3088 int dst_y = plane_state->dst.y1;
3089 int dst_w = drm_rect_width(&plane_state->dst);
3090 int dst_h = drm_rect_height(&plane_state->dst);
3091
3092 plane_ctl = PLANE_CTL_ENABLE |
3093 PLANE_CTL_PIPE_GAMMA_ENABLE |
3094 PLANE_CTL_PIPE_CSC_ENABLE;
3095
3096 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3097 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3098 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3099 plane_ctl |= skl_plane_ctl_rotation(rotation);
3100
3101 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3102 fb->pixel_format);
3103 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3104
3105 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3106
3107 if (intel_rotation_90_or_270(rotation)) {
3108 int cpp = drm_format_plane_cpp(fb->pixel_format, 0);
3109
3110 /* stride = Surface height in tiles */
3111 tile_height = intel_tile_height(dev_priv, fb->modifier[0], cpp);
3112 stride = DIV_ROUND_UP(fb->height, tile_height);
3113 x_offset = stride * tile_height - src_y - src_h;
3114 y_offset = src_x;
3115 plane_size = (src_w - 1) << 16 | (src_h - 1);
3116 } else {
3117 stride = fb->pitches[0] / stride_div;
3118 x_offset = src_x;
3119 y_offset = src_y;
3120 plane_size = (src_h - 1) << 16 | (src_w - 1);
3121 }
3122 plane_offset = y_offset << 16 | x_offset;
3123
3124 intel_crtc->adjusted_x = x_offset;
3125 intel_crtc->adjusted_y = y_offset;
3126
3127 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3128 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3129 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3130 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3131
3132 if (scaler_id >= 0) {
3133 uint32_t ps_ctrl = 0;
3134
3135 WARN_ON(!dst_w || !dst_h);
3136 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3137 crtc_state->scaler_state.scalers[scaler_id].mode;
3138 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3139 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3140 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3141 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3142 I915_WRITE(PLANE_POS(pipe, 0), 0);
3143 } else {
3144 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3145 }
3146
3147 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3148
3149 POSTING_READ(PLANE_SURF(pipe, 0));
3150 }
3151
3152 static void skylake_disable_primary_plane(struct drm_plane *primary,
3153 struct drm_crtc *crtc)
3154 {
3155 struct drm_device *dev = crtc->dev;
3156 struct drm_i915_private *dev_priv = dev->dev_private;
3157 int pipe = to_intel_crtc(crtc)->pipe;
3158
3159 if (dev_priv->fbc.deactivate)
3160 dev_priv->fbc.deactivate(dev_priv);
3161
3162 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3163 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3164 POSTING_READ(PLANE_SURF(pipe, 0));
3165 }
3166
3167 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3168 static int
3169 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3170 int x, int y, enum mode_set_atomic state)
3171 {
3172 /* Support for kgdboc is disabled, this needs a major rework. */
3173 DRM_ERROR("legacy panic handler not supported any more.\n");
3174
3175 return -ENODEV;
3176 }
3177
3178 static void intel_complete_page_flips(struct drm_device *dev)
3179 {
3180 struct drm_crtc *crtc;
3181
3182 for_each_crtc(dev, crtc) {
3183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3184 enum plane plane = intel_crtc->plane;
3185
3186 intel_prepare_page_flip(dev, plane);
3187 intel_finish_page_flip_plane(dev, plane);
3188 }
3189 }
3190
3191 static void intel_update_primary_planes(struct drm_device *dev)
3192 {
3193 struct drm_crtc *crtc;
3194
3195 for_each_crtc(dev, crtc) {
3196 struct intel_plane *plane = to_intel_plane(crtc->primary);
3197 struct intel_plane_state *plane_state;
3198
3199 drm_modeset_lock_crtc(crtc, &plane->base);
3200 plane_state = to_intel_plane_state(plane->base.state);
3201
3202 if (plane_state->visible)
3203 plane->update_plane(&plane->base,
3204 to_intel_crtc_state(crtc->state),
3205 plane_state);
3206
3207 drm_modeset_unlock_crtc(crtc);
3208 }
3209 }
3210
3211 void intel_prepare_reset(struct drm_device *dev)
3212 {
3213 /* no reset support for gen2 */
3214 if (IS_GEN2(dev))
3215 return;
3216
3217 /* reset doesn't touch the display */
3218 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3219 return;
3220
3221 drm_modeset_lock_all(dev);
3222 /*
3223 * Disabling the crtcs gracefully seems nicer. Also the
3224 * g33 docs say we should at least disable all the planes.
3225 */
3226 intel_display_suspend(dev);
3227 }
3228
3229 void intel_finish_reset(struct drm_device *dev)
3230 {
3231 struct drm_i915_private *dev_priv = to_i915(dev);
3232
3233 /*
3234 * Flips in the rings will be nuked by the reset,
3235 * so complete all pending flips so that user space
3236 * will get its events and not get stuck.
3237 */
3238 intel_complete_page_flips(dev);
3239
3240 /* no reset support for gen2 */
3241 if (IS_GEN2(dev))
3242 return;
3243
3244 /* reset doesn't touch the display */
3245 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3246 /*
3247 * Flips in the rings have been nuked by the reset,
3248 * so update the base address of all primary
3249 * planes to the the last fb to make sure we're
3250 * showing the correct fb after a reset.
3251 *
3252 * FIXME: Atomic will make this obsolete since we won't schedule
3253 * CS-based flips (which might get lost in gpu resets) any more.
3254 */
3255 intel_update_primary_planes(dev);
3256 return;
3257 }
3258
3259 /*
3260 * The display has been reset as well,
3261 * so need a full re-initialization.
3262 */
3263 intel_runtime_pm_disable_interrupts(dev_priv);
3264 intel_runtime_pm_enable_interrupts(dev_priv);
3265
3266 intel_modeset_init_hw(dev);
3267
3268 spin_lock_irq(&dev_priv->irq_lock);
3269 if (dev_priv->display.hpd_irq_setup)
3270 dev_priv->display.hpd_irq_setup(dev);
3271 spin_unlock_irq(&dev_priv->irq_lock);
3272
3273 intel_display_resume(dev);
3274
3275 intel_hpd_init(dev_priv);
3276
3277 drm_modeset_unlock_all(dev);
3278 }
3279
3280 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3281 {
3282 struct drm_device *dev = crtc->dev;
3283 struct drm_i915_private *dev_priv = dev->dev_private;
3284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3285 bool pending;
3286
3287 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3288 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3289 return false;
3290
3291 spin_lock_irq(&dev->event_lock);
3292 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3293 spin_unlock_irq(&dev->event_lock);
3294
3295 return pending;
3296 }
3297
3298 static void intel_update_pipe_config(struct intel_crtc *crtc,
3299 struct intel_crtc_state *old_crtc_state)
3300 {
3301 struct drm_device *dev = crtc->base.dev;
3302 struct drm_i915_private *dev_priv = dev->dev_private;
3303 struct intel_crtc_state *pipe_config =
3304 to_intel_crtc_state(crtc->base.state);
3305
3306 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3307 crtc->base.mode = crtc->base.state->mode;
3308
3309 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3310 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3311 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3312
3313 if (HAS_DDI(dev))
3314 intel_set_pipe_csc(&crtc->base);
3315
3316 /*
3317 * Update pipe size and adjust fitter if needed: the reason for this is
3318 * that in compute_mode_changes we check the native mode (not the pfit
3319 * mode) to see if we can flip rather than do a full mode set. In the
3320 * fastboot case, we'll flip, but if we don't update the pipesrc and
3321 * pfit state, we'll end up with a big fb scanned out into the wrong
3322 * sized surface.
3323 */
3324
3325 I915_WRITE(PIPESRC(crtc->pipe),
3326 ((pipe_config->pipe_src_w - 1) << 16) |
3327 (pipe_config->pipe_src_h - 1));
3328
3329 /* on skylake this is done by detaching scalers */
3330 if (INTEL_INFO(dev)->gen >= 9) {
3331 skl_detach_scalers(crtc);
3332
3333 if (pipe_config->pch_pfit.enabled)
3334 skylake_pfit_enable(crtc);
3335 } else if (HAS_PCH_SPLIT(dev)) {
3336 if (pipe_config->pch_pfit.enabled)
3337 ironlake_pfit_enable(crtc);
3338 else if (old_crtc_state->pch_pfit.enabled)
3339 ironlake_pfit_disable(crtc, true);
3340 }
3341 }
3342
3343 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3344 {
3345 struct drm_device *dev = crtc->dev;
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3348 int pipe = intel_crtc->pipe;
3349 i915_reg_t reg;
3350 u32 temp;
3351
3352 /* enable normal train */
3353 reg = FDI_TX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 if (IS_IVYBRIDGE(dev)) {
3356 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3357 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3358 } else {
3359 temp &= ~FDI_LINK_TRAIN_NONE;
3360 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3361 }
3362 I915_WRITE(reg, temp);
3363
3364 reg = FDI_RX_CTL(pipe);
3365 temp = I915_READ(reg);
3366 if (HAS_PCH_CPT(dev)) {
3367 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3368 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3369 } else {
3370 temp &= ~FDI_LINK_TRAIN_NONE;
3371 temp |= FDI_LINK_TRAIN_NONE;
3372 }
3373 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3374
3375 /* wait one idle pattern time */
3376 POSTING_READ(reg);
3377 udelay(1000);
3378
3379 /* IVB wants error correction enabled */
3380 if (IS_IVYBRIDGE(dev))
3381 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3382 FDI_FE_ERRC_ENABLE);
3383 }
3384
3385 /* The FDI link training functions for ILK/Ibexpeak. */
3386 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3387 {
3388 struct drm_device *dev = crtc->dev;
3389 struct drm_i915_private *dev_priv = dev->dev_private;
3390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3391 int pipe = intel_crtc->pipe;
3392 i915_reg_t reg;
3393 u32 temp, tries;
3394
3395 /* FDI needs bits from pipe first */
3396 assert_pipe_enabled(dev_priv, pipe);
3397
3398 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3399 for train result */
3400 reg = FDI_RX_IMR(pipe);
3401 temp = I915_READ(reg);
3402 temp &= ~FDI_RX_SYMBOL_LOCK;
3403 temp &= ~FDI_RX_BIT_LOCK;
3404 I915_WRITE(reg, temp);
3405 I915_READ(reg);
3406 udelay(150);
3407
3408 /* enable CPU FDI TX and PCH FDI RX */
3409 reg = FDI_TX_CTL(pipe);
3410 temp = I915_READ(reg);
3411 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3412 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3413 temp &= ~FDI_LINK_TRAIN_NONE;
3414 temp |= FDI_LINK_TRAIN_PATTERN_1;
3415 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3416
3417 reg = FDI_RX_CTL(pipe);
3418 temp = I915_READ(reg);
3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_1;
3421 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3422
3423 POSTING_READ(reg);
3424 udelay(150);
3425
3426 /* Ironlake workaround, enable clock pointer after FDI enable*/
3427 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3428 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3429 FDI_RX_PHASE_SYNC_POINTER_EN);
3430
3431 reg = FDI_RX_IIR(pipe);
3432 for (tries = 0; tries < 5; tries++) {
3433 temp = I915_READ(reg);
3434 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3435
3436 if ((temp & FDI_RX_BIT_LOCK)) {
3437 DRM_DEBUG_KMS("FDI train 1 done.\n");
3438 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3439 break;
3440 }
3441 }
3442 if (tries == 5)
3443 DRM_ERROR("FDI train 1 fail!\n");
3444
3445 /* Train 2 */
3446 reg = FDI_TX_CTL(pipe);
3447 temp = I915_READ(reg);
3448 temp &= ~FDI_LINK_TRAIN_NONE;
3449 temp |= FDI_LINK_TRAIN_PATTERN_2;
3450 I915_WRITE(reg, temp);
3451
3452 reg = FDI_RX_CTL(pipe);
3453 temp = I915_READ(reg);
3454 temp &= ~FDI_LINK_TRAIN_NONE;
3455 temp |= FDI_LINK_TRAIN_PATTERN_2;
3456 I915_WRITE(reg, temp);
3457
3458 POSTING_READ(reg);
3459 udelay(150);
3460
3461 reg = FDI_RX_IIR(pipe);
3462 for (tries = 0; tries < 5; tries++) {
3463 temp = I915_READ(reg);
3464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465
3466 if (temp & FDI_RX_SYMBOL_LOCK) {
3467 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3468 DRM_DEBUG_KMS("FDI train 2 done.\n");
3469 break;
3470 }
3471 }
3472 if (tries == 5)
3473 DRM_ERROR("FDI train 2 fail!\n");
3474
3475 DRM_DEBUG_KMS("FDI train done\n");
3476
3477 }
3478
3479 static const int snb_b_fdi_train_param[] = {
3480 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3481 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3482 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3483 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3484 };
3485
3486 /* The FDI link training functions for SNB/Cougarpoint. */
3487 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3488 {
3489 struct drm_device *dev = crtc->dev;
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3492 int pipe = intel_crtc->pipe;
3493 i915_reg_t reg;
3494 u32 temp, i, retry;
3495
3496 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3497 for train result */
3498 reg = FDI_RX_IMR(pipe);
3499 temp = I915_READ(reg);
3500 temp &= ~FDI_RX_SYMBOL_LOCK;
3501 temp &= ~FDI_RX_BIT_LOCK;
3502 I915_WRITE(reg, temp);
3503
3504 POSTING_READ(reg);
3505 udelay(150);
3506
3507 /* enable CPU FDI TX and PCH FDI RX */
3508 reg = FDI_TX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3511 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3512 temp &= ~FDI_LINK_TRAIN_NONE;
3513 temp |= FDI_LINK_TRAIN_PATTERN_1;
3514 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3515 /* SNB-B */
3516 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3517 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3518
3519 I915_WRITE(FDI_RX_MISC(pipe),
3520 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3521
3522 reg = FDI_RX_CTL(pipe);
3523 temp = I915_READ(reg);
3524 if (HAS_PCH_CPT(dev)) {
3525 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3526 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3527 } else {
3528 temp &= ~FDI_LINK_TRAIN_NONE;
3529 temp |= FDI_LINK_TRAIN_PATTERN_1;
3530 }
3531 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3532
3533 POSTING_READ(reg);
3534 udelay(150);
3535
3536 for (i = 0; i < 4; i++) {
3537 reg = FDI_TX_CTL(pipe);
3538 temp = I915_READ(reg);
3539 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3540 temp |= snb_b_fdi_train_param[i];
3541 I915_WRITE(reg, temp);
3542
3543 POSTING_READ(reg);
3544 udelay(500);
3545
3546 for (retry = 0; retry < 5; retry++) {
3547 reg = FDI_RX_IIR(pipe);
3548 temp = I915_READ(reg);
3549 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3550 if (temp & FDI_RX_BIT_LOCK) {
3551 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552 DRM_DEBUG_KMS("FDI train 1 done.\n");
3553 break;
3554 }
3555 udelay(50);
3556 }
3557 if (retry < 5)
3558 break;
3559 }
3560 if (i == 4)
3561 DRM_ERROR("FDI train 1 fail!\n");
3562
3563 /* Train 2 */
3564 reg = FDI_TX_CTL(pipe);
3565 temp = I915_READ(reg);
3566 temp &= ~FDI_LINK_TRAIN_NONE;
3567 temp |= FDI_LINK_TRAIN_PATTERN_2;
3568 if (IS_GEN6(dev)) {
3569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3570 /* SNB-B */
3571 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3572 }
3573 I915_WRITE(reg, temp);
3574
3575 reg = FDI_RX_CTL(pipe);
3576 temp = I915_READ(reg);
3577 if (HAS_PCH_CPT(dev)) {
3578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3579 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3580 } else {
3581 temp &= ~FDI_LINK_TRAIN_NONE;
3582 temp |= FDI_LINK_TRAIN_PATTERN_2;
3583 }
3584 I915_WRITE(reg, temp);
3585
3586 POSTING_READ(reg);
3587 udelay(150);
3588
3589 for (i = 0; i < 4; i++) {
3590 reg = FDI_TX_CTL(pipe);
3591 temp = I915_READ(reg);
3592 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3593 temp |= snb_b_fdi_train_param[i];
3594 I915_WRITE(reg, temp);
3595
3596 POSTING_READ(reg);
3597 udelay(500);
3598
3599 for (retry = 0; retry < 5; retry++) {
3600 reg = FDI_RX_IIR(pipe);
3601 temp = I915_READ(reg);
3602 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3603 if (temp & FDI_RX_SYMBOL_LOCK) {
3604 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3605 DRM_DEBUG_KMS("FDI train 2 done.\n");
3606 break;
3607 }
3608 udelay(50);
3609 }
3610 if (retry < 5)
3611 break;
3612 }
3613 if (i == 4)
3614 DRM_ERROR("FDI train 2 fail!\n");
3615
3616 DRM_DEBUG_KMS("FDI train done.\n");
3617 }
3618
3619 /* Manual link training for Ivy Bridge A0 parts */
3620 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3621 {
3622 struct drm_device *dev = crtc->dev;
3623 struct drm_i915_private *dev_priv = dev->dev_private;
3624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3625 int pipe = intel_crtc->pipe;
3626 i915_reg_t reg;
3627 u32 temp, i, j;
3628
3629 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3630 for train result */
3631 reg = FDI_RX_IMR(pipe);
3632 temp = I915_READ(reg);
3633 temp &= ~FDI_RX_SYMBOL_LOCK;
3634 temp &= ~FDI_RX_BIT_LOCK;
3635 I915_WRITE(reg, temp);
3636
3637 POSTING_READ(reg);
3638 udelay(150);
3639
3640 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3641 I915_READ(FDI_RX_IIR(pipe)));
3642
3643 /* Try each vswing and preemphasis setting twice before moving on */
3644 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3645 /* disable first in case we need to retry */
3646 reg = FDI_TX_CTL(pipe);
3647 temp = I915_READ(reg);
3648 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3649 temp &= ~FDI_TX_ENABLE;
3650 I915_WRITE(reg, temp);
3651
3652 reg = FDI_RX_CTL(pipe);
3653 temp = I915_READ(reg);
3654 temp &= ~FDI_LINK_TRAIN_AUTO;
3655 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3656 temp &= ~FDI_RX_ENABLE;
3657 I915_WRITE(reg, temp);
3658
3659 /* enable CPU FDI TX and PCH FDI RX */
3660 reg = FDI_TX_CTL(pipe);
3661 temp = I915_READ(reg);
3662 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3663 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3664 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3665 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3666 temp |= snb_b_fdi_train_param[j/2];
3667 temp |= FDI_COMPOSITE_SYNC;
3668 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3669
3670 I915_WRITE(FDI_RX_MISC(pipe),
3671 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3672
3673 reg = FDI_RX_CTL(pipe);
3674 temp = I915_READ(reg);
3675 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3676 temp |= FDI_COMPOSITE_SYNC;
3677 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3678
3679 POSTING_READ(reg);
3680 udelay(1); /* should be 0.5us */
3681
3682 for (i = 0; i < 4; i++) {
3683 reg = FDI_RX_IIR(pipe);
3684 temp = I915_READ(reg);
3685 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3686
3687 if (temp & FDI_RX_BIT_LOCK ||
3688 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3689 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3690 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3691 i);
3692 break;
3693 }
3694 udelay(1); /* should be 0.5us */
3695 }
3696 if (i == 4) {
3697 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3698 continue;
3699 }
3700
3701 /* Train 2 */
3702 reg = FDI_TX_CTL(pipe);
3703 temp = I915_READ(reg);
3704 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3705 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3706 I915_WRITE(reg, temp);
3707
3708 reg = FDI_RX_CTL(pipe);
3709 temp = I915_READ(reg);
3710 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3711 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3712 I915_WRITE(reg, temp);
3713
3714 POSTING_READ(reg);
3715 udelay(2); /* should be 1.5us */
3716
3717 for (i = 0; i < 4; i++) {
3718 reg = FDI_RX_IIR(pipe);
3719 temp = I915_READ(reg);
3720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3721
3722 if (temp & FDI_RX_SYMBOL_LOCK ||
3723 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3724 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3725 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3726 i);
3727 goto train_done;
3728 }
3729 udelay(2); /* should be 1.5us */
3730 }
3731 if (i == 4)
3732 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3733 }
3734
3735 train_done:
3736 DRM_DEBUG_KMS("FDI train done.\n");
3737 }
3738
3739 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3740 {
3741 struct drm_device *dev = intel_crtc->base.dev;
3742 struct drm_i915_private *dev_priv = dev->dev_private;
3743 int pipe = intel_crtc->pipe;
3744 i915_reg_t reg;
3745 u32 temp;
3746
3747 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3748 reg = FDI_RX_CTL(pipe);
3749 temp = I915_READ(reg);
3750 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3751 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3752 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3753 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3754
3755 POSTING_READ(reg);
3756 udelay(200);
3757
3758 /* Switch from Rawclk to PCDclk */
3759 temp = I915_READ(reg);
3760 I915_WRITE(reg, temp | FDI_PCDCLK);
3761
3762 POSTING_READ(reg);
3763 udelay(200);
3764
3765 /* Enable CPU FDI TX PLL, always on for Ironlake */
3766 reg = FDI_TX_CTL(pipe);
3767 temp = I915_READ(reg);
3768 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3769 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3770
3771 POSTING_READ(reg);
3772 udelay(100);
3773 }
3774 }
3775
3776 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3777 {
3778 struct drm_device *dev = intel_crtc->base.dev;
3779 struct drm_i915_private *dev_priv = dev->dev_private;
3780 int pipe = intel_crtc->pipe;
3781 i915_reg_t reg;
3782 u32 temp;
3783
3784 /* Switch from PCDclk to Rawclk */
3785 reg = FDI_RX_CTL(pipe);
3786 temp = I915_READ(reg);
3787 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3788
3789 /* Disable CPU FDI TX PLL */
3790 reg = FDI_TX_CTL(pipe);
3791 temp = I915_READ(reg);
3792 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3793
3794 POSTING_READ(reg);
3795 udelay(100);
3796
3797 reg = FDI_RX_CTL(pipe);
3798 temp = I915_READ(reg);
3799 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3800
3801 /* Wait for the clocks to turn off. */
3802 POSTING_READ(reg);
3803 udelay(100);
3804 }
3805
3806 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3807 {
3808 struct drm_device *dev = crtc->dev;
3809 struct drm_i915_private *dev_priv = dev->dev_private;
3810 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3811 int pipe = intel_crtc->pipe;
3812 i915_reg_t reg;
3813 u32 temp;
3814
3815 /* disable CPU FDI tx and PCH FDI rx */
3816 reg = FDI_TX_CTL(pipe);
3817 temp = I915_READ(reg);
3818 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3819 POSTING_READ(reg);
3820
3821 reg = FDI_RX_CTL(pipe);
3822 temp = I915_READ(reg);
3823 temp &= ~(0x7 << 16);
3824 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3825 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3826
3827 POSTING_READ(reg);
3828 udelay(100);
3829
3830 /* Ironlake workaround, disable clock pointer after downing FDI */
3831 if (HAS_PCH_IBX(dev))
3832 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3833
3834 /* still set train pattern 1 */
3835 reg = FDI_TX_CTL(pipe);
3836 temp = I915_READ(reg);
3837 temp &= ~FDI_LINK_TRAIN_NONE;
3838 temp |= FDI_LINK_TRAIN_PATTERN_1;
3839 I915_WRITE(reg, temp);
3840
3841 reg = FDI_RX_CTL(pipe);
3842 temp = I915_READ(reg);
3843 if (HAS_PCH_CPT(dev)) {
3844 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3845 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3846 } else {
3847 temp &= ~FDI_LINK_TRAIN_NONE;
3848 temp |= FDI_LINK_TRAIN_PATTERN_1;
3849 }
3850 /* BPC in FDI rx is consistent with that in PIPECONF */
3851 temp &= ~(0x07 << 16);
3852 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3853 I915_WRITE(reg, temp);
3854
3855 POSTING_READ(reg);
3856 udelay(100);
3857 }
3858
3859 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3860 {
3861 struct intel_crtc *crtc;
3862
3863 /* Note that we don't need to be called with mode_config.lock here
3864 * as our list of CRTC objects is static for the lifetime of the
3865 * device and so cannot disappear as we iterate. Similarly, we can
3866 * happily treat the predicates as racy, atomic checks as userspace
3867 * cannot claim and pin a new fb without at least acquring the
3868 * struct_mutex and so serialising with us.
3869 */
3870 for_each_intel_crtc(dev, crtc) {
3871 if (atomic_read(&crtc->unpin_work_count) == 0)
3872 continue;
3873
3874 if (crtc->unpin_work)
3875 intel_wait_for_vblank(dev, crtc->pipe);
3876
3877 return true;
3878 }
3879
3880 return false;
3881 }
3882
3883 static void page_flip_completed(struct intel_crtc *intel_crtc)
3884 {
3885 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3886 struct intel_unpin_work *work = intel_crtc->unpin_work;
3887
3888 /* ensure that the unpin work is consistent wrt ->pending. */
3889 smp_rmb();
3890 intel_crtc->unpin_work = NULL;
3891
3892 if (work->event)
3893 drm_send_vblank_event(intel_crtc->base.dev,
3894 intel_crtc->pipe,
3895 work->event);
3896
3897 drm_crtc_vblank_put(&intel_crtc->base);
3898
3899 wake_up_all(&dev_priv->pending_flip_queue);
3900 queue_work(dev_priv->wq, &work->work);
3901
3902 trace_i915_flip_complete(intel_crtc->plane,
3903 work->pending_flip_obj);
3904 }
3905
3906 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3907 {
3908 struct drm_device *dev = crtc->dev;
3909 struct drm_i915_private *dev_priv = dev->dev_private;
3910 long ret;
3911
3912 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3913
3914 ret = wait_event_interruptible_timeout(
3915 dev_priv->pending_flip_queue,
3916 !intel_crtc_has_pending_flip(crtc),
3917 60*HZ);
3918
3919 if (ret < 0)
3920 return ret;
3921
3922 if (ret == 0) {
3923 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3924
3925 spin_lock_irq(&dev->event_lock);
3926 if (intel_crtc->unpin_work) {
3927 WARN_ONCE(1, "Removing stuck page flip\n");
3928 page_flip_completed(intel_crtc);
3929 }
3930 spin_unlock_irq(&dev->event_lock);
3931 }
3932
3933 return 0;
3934 }
3935
3936 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3937 {
3938 u32 temp;
3939
3940 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3941
3942 mutex_lock(&dev_priv->sb_lock);
3943
3944 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3945 temp |= SBI_SSCCTL_DISABLE;
3946 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3947
3948 mutex_unlock(&dev_priv->sb_lock);
3949 }
3950
3951 /* Program iCLKIP clock to the desired frequency */
3952 static void lpt_program_iclkip(struct drm_crtc *crtc)
3953 {
3954 struct drm_device *dev = crtc->dev;
3955 struct drm_i915_private *dev_priv = dev->dev_private;
3956 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3957 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3958 u32 temp;
3959
3960 lpt_disable_iclkip(dev_priv);
3961
3962 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3963 if (clock == 20000) {
3964 auxdiv = 1;
3965 divsel = 0x41;
3966 phaseinc = 0x20;
3967 } else {
3968 /* The iCLK virtual clock root frequency is in MHz,
3969 * but the adjusted_mode->crtc_clock in in KHz. To get the
3970 * divisors, it is necessary to divide one by another, so we
3971 * convert the virtual clock precision to KHz here for higher
3972 * precision.
3973 */
3974 u32 iclk_virtual_root_freq = 172800 * 1000;
3975 u32 iclk_pi_range = 64;
3976 u32 desired_divisor, msb_divisor_value, pi_value;
3977
3978 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
3979 msb_divisor_value = desired_divisor / iclk_pi_range;
3980 pi_value = desired_divisor % iclk_pi_range;
3981
3982 auxdiv = 0;
3983 divsel = msb_divisor_value - 2;
3984 phaseinc = pi_value;
3985 }
3986
3987 /* This should not happen with any sane values */
3988 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3989 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3990 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3991 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3992
3993 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3994 clock,
3995 auxdiv,
3996 divsel,
3997 phasedir,
3998 phaseinc);
3999
4000 mutex_lock(&dev_priv->sb_lock);
4001
4002 /* Program SSCDIVINTPHASE6 */
4003 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4004 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4005 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4006 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4007 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4008 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4009 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4010 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4011
4012 /* Program SSCAUXDIV */
4013 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4014 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4015 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4016 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4017
4018 /* Enable modulator and associated divider */
4019 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4020 temp &= ~SBI_SSCCTL_DISABLE;
4021 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4022
4023 mutex_unlock(&dev_priv->sb_lock);
4024
4025 /* Wait for initialization time */
4026 udelay(24);
4027
4028 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4029 }
4030
4031 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4032 enum pipe pch_transcoder)
4033 {
4034 struct drm_device *dev = crtc->base.dev;
4035 struct drm_i915_private *dev_priv = dev->dev_private;
4036 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4037
4038 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4039 I915_READ(HTOTAL(cpu_transcoder)));
4040 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4041 I915_READ(HBLANK(cpu_transcoder)));
4042 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4043 I915_READ(HSYNC(cpu_transcoder)));
4044
4045 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4046 I915_READ(VTOTAL(cpu_transcoder)));
4047 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4048 I915_READ(VBLANK(cpu_transcoder)));
4049 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4050 I915_READ(VSYNC(cpu_transcoder)));
4051 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4052 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4053 }
4054
4055 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4056 {
4057 struct drm_i915_private *dev_priv = dev->dev_private;
4058 uint32_t temp;
4059
4060 temp = I915_READ(SOUTH_CHICKEN1);
4061 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4062 return;
4063
4064 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4065 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4066
4067 temp &= ~FDI_BC_BIFURCATION_SELECT;
4068 if (enable)
4069 temp |= FDI_BC_BIFURCATION_SELECT;
4070
4071 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4072 I915_WRITE(SOUTH_CHICKEN1, temp);
4073 POSTING_READ(SOUTH_CHICKEN1);
4074 }
4075
4076 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4077 {
4078 struct drm_device *dev = intel_crtc->base.dev;
4079
4080 switch (intel_crtc->pipe) {
4081 case PIPE_A:
4082 break;
4083 case PIPE_B:
4084 if (intel_crtc->config->fdi_lanes > 2)
4085 cpt_set_fdi_bc_bifurcation(dev, false);
4086 else
4087 cpt_set_fdi_bc_bifurcation(dev, true);
4088
4089 break;
4090 case PIPE_C:
4091 cpt_set_fdi_bc_bifurcation(dev, true);
4092
4093 break;
4094 default:
4095 BUG();
4096 }
4097 }
4098
4099 /* Return which DP Port should be selected for Transcoder DP control */
4100 static enum port
4101 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4102 {
4103 struct drm_device *dev = crtc->dev;
4104 struct intel_encoder *encoder;
4105
4106 for_each_encoder_on_crtc(dev, crtc, encoder) {
4107 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4108 encoder->type == INTEL_OUTPUT_EDP)
4109 return enc_to_dig_port(&encoder->base)->port;
4110 }
4111
4112 return -1;
4113 }
4114
4115 /*
4116 * Enable PCH resources required for PCH ports:
4117 * - PCH PLLs
4118 * - FDI training & RX/TX
4119 * - update transcoder timings
4120 * - DP transcoding bits
4121 * - transcoder
4122 */
4123 static void ironlake_pch_enable(struct drm_crtc *crtc)
4124 {
4125 struct drm_device *dev = crtc->dev;
4126 struct drm_i915_private *dev_priv = dev->dev_private;
4127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4128 int pipe = intel_crtc->pipe;
4129 u32 temp;
4130
4131 assert_pch_transcoder_disabled(dev_priv, pipe);
4132
4133 if (IS_IVYBRIDGE(dev))
4134 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4135
4136 /* Write the TU size bits before fdi link training, so that error
4137 * detection works. */
4138 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4139 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4140
4141 /*
4142 * Sometimes spurious CPU pipe underruns happen during FDI
4143 * training, at least with VGA+HDMI cloning. Suppress them.
4144 */
4145 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4146
4147 /* For PCH output, training FDI link */
4148 dev_priv->display.fdi_link_train(crtc);
4149
4150 /* We need to program the right clock selection before writing the pixel
4151 * mutliplier into the DPLL. */
4152 if (HAS_PCH_CPT(dev)) {
4153 u32 sel;
4154
4155 temp = I915_READ(PCH_DPLL_SEL);
4156 temp |= TRANS_DPLL_ENABLE(pipe);
4157 sel = TRANS_DPLLB_SEL(pipe);
4158 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4159 temp |= sel;
4160 else
4161 temp &= ~sel;
4162 I915_WRITE(PCH_DPLL_SEL, temp);
4163 }
4164
4165 /* XXX: pch pll's can be enabled any time before we enable the PCH
4166 * transcoder, and we actually should do this to not upset any PCH
4167 * transcoder that already use the clock when we share it.
4168 *
4169 * Note that enable_shared_dpll tries to do the right thing, but
4170 * get_shared_dpll unconditionally resets the pll - we need that to have
4171 * the right LVDS enable sequence. */
4172 intel_enable_shared_dpll(intel_crtc);
4173
4174 /* set transcoder timing, panel must allow it */
4175 assert_panel_unlocked(dev_priv, pipe);
4176 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4177
4178 intel_fdi_normal_train(crtc);
4179
4180 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4181
4182 /* For PCH DP, enable TRANS_DP_CTL */
4183 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4184 const struct drm_display_mode *adjusted_mode =
4185 &intel_crtc->config->base.adjusted_mode;
4186 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4187 i915_reg_t reg = TRANS_DP_CTL(pipe);
4188 temp = I915_READ(reg);
4189 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4190 TRANS_DP_SYNC_MASK |
4191 TRANS_DP_BPC_MASK);
4192 temp |= TRANS_DP_OUTPUT_ENABLE;
4193 temp |= bpc << 9; /* same format but at 11:9 */
4194
4195 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4196 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4197 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4198 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4199
4200 switch (intel_trans_dp_port_sel(crtc)) {
4201 case PORT_B:
4202 temp |= TRANS_DP_PORT_SEL_B;
4203 break;
4204 case PORT_C:
4205 temp |= TRANS_DP_PORT_SEL_C;
4206 break;
4207 case PORT_D:
4208 temp |= TRANS_DP_PORT_SEL_D;
4209 break;
4210 default:
4211 BUG();
4212 }
4213
4214 I915_WRITE(reg, temp);
4215 }
4216
4217 ironlake_enable_pch_transcoder(dev_priv, pipe);
4218 }
4219
4220 static void lpt_pch_enable(struct drm_crtc *crtc)
4221 {
4222 struct drm_device *dev = crtc->dev;
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4225 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4226
4227 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4228
4229 lpt_program_iclkip(crtc);
4230
4231 /* Set transcoder timing. */
4232 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4233
4234 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4235 }
4236
4237 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4238 struct intel_crtc_state *crtc_state)
4239 {
4240 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4241 struct intel_shared_dpll *pll;
4242 struct intel_shared_dpll_config *shared_dpll;
4243 enum intel_dpll_id i;
4244 int max = dev_priv->num_shared_dpll;
4245
4246 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4247
4248 if (HAS_PCH_IBX(dev_priv->dev)) {
4249 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4250 i = (enum intel_dpll_id) crtc->pipe;
4251 pll = &dev_priv->shared_dplls[i];
4252
4253 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4254 crtc->base.base.id, pll->name);
4255
4256 WARN_ON(shared_dpll[i].crtc_mask);
4257
4258 goto found;
4259 }
4260
4261 if (IS_BROXTON(dev_priv->dev)) {
4262 /* PLL is attached to port in bxt */
4263 struct intel_encoder *encoder;
4264 struct intel_digital_port *intel_dig_port;
4265
4266 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4267 if (WARN_ON(!encoder))
4268 return NULL;
4269
4270 intel_dig_port = enc_to_dig_port(&encoder->base);
4271 /* 1:1 mapping between ports and PLLs */
4272 i = (enum intel_dpll_id)intel_dig_port->port;
4273 pll = &dev_priv->shared_dplls[i];
4274 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4275 crtc->base.base.id, pll->name);
4276 WARN_ON(shared_dpll[i].crtc_mask);
4277
4278 goto found;
4279 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4280 /* Do not consider SPLL */
4281 max = 2;
4282
4283 for (i = 0; i < max; i++) {
4284 pll = &dev_priv->shared_dplls[i];
4285
4286 /* Only want to check enabled timings first */
4287 if (shared_dpll[i].crtc_mask == 0)
4288 continue;
4289
4290 if (memcmp(&crtc_state->dpll_hw_state,
4291 &shared_dpll[i].hw_state,
4292 sizeof(crtc_state->dpll_hw_state)) == 0) {
4293 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4294 crtc->base.base.id, pll->name,
4295 shared_dpll[i].crtc_mask,
4296 pll->active);
4297 goto found;
4298 }
4299 }
4300
4301 /* Ok no matching timings, maybe there's a free one? */
4302 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4303 pll = &dev_priv->shared_dplls[i];
4304 if (shared_dpll[i].crtc_mask == 0) {
4305 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4306 crtc->base.base.id, pll->name);
4307 goto found;
4308 }
4309 }
4310
4311 return NULL;
4312
4313 found:
4314 if (shared_dpll[i].crtc_mask == 0)
4315 shared_dpll[i].hw_state =
4316 crtc_state->dpll_hw_state;
4317
4318 crtc_state->shared_dpll = i;
4319 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4320 pipe_name(crtc->pipe));
4321
4322 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4323
4324 return pll;
4325 }
4326
4327 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4328 {
4329 struct drm_i915_private *dev_priv = to_i915(state->dev);
4330 struct intel_shared_dpll_config *shared_dpll;
4331 struct intel_shared_dpll *pll;
4332 enum intel_dpll_id i;
4333
4334 if (!to_intel_atomic_state(state)->dpll_set)
4335 return;
4336
4337 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4338 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4339 pll = &dev_priv->shared_dplls[i];
4340 pll->config = shared_dpll[i];
4341 }
4342 }
4343
4344 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4345 {
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4347 i915_reg_t dslreg = PIPEDSL(pipe);
4348 u32 temp;
4349
4350 temp = I915_READ(dslreg);
4351 udelay(500);
4352 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4353 if (wait_for(I915_READ(dslreg) != temp, 5))
4354 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4355 }
4356 }
4357
4358 static int
4359 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4360 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4361 int src_w, int src_h, int dst_w, int dst_h)
4362 {
4363 struct intel_crtc_scaler_state *scaler_state =
4364 &crtc_state->scaler_state;
4365 struct intel_crtc *intel_crtc =
4366 to_intel_crtc(crtc_state->base.crtc);
4367 int need_scaling;
4368
4369 need_scaling = intel_rotation_90_or_270(rotation) ?
4370 (src_h != dst_w || src_w != dst_h):
4371 (src_w != dst_w || src_h != dst_h);
4372
4373 /*
4374 * if plane is being disabled or scaler is no more required or force detach
4375 * - free scaler binded to this plane/crtc
4376 * - in order to do this, update crtc->scaler_usage
4377 *
4378 * Here scaler state in crtc_state is set free so that
4379 * scaler can be assigned to other user. Actual register
4380 * update to free the scaler is done in plane/panel-fit programming.
4381 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4382 */
4383 if (force_detach || !need_scaling) {
4384 if (*scaler_id >= 0) {
4385 scaler_state->scaler_users &= ~(1 << scaler_user);
4386 scaler_state->scalers[*scaler_id].in_use = 0;
4387
4388 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4389 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4390 intel_crtc->pipe, scaler_user, *scaler_id,
4391 scaler_state->scaler_users);
4392 *scaler_id = -1;
4393 }
4394 return 0;
4395 }
4396
4397 /* range checks */
4398 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4399 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4400
4401 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4402 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4403 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4404 "size is out of scaler range\n",
4405 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4406 return -EINVAL;
4407 }
4408
4409 /* mark this plane as a scaler user in crtc_state */
4410 scaler_state->scaler_users |= (1 << scaler_user);
4411 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4412 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4413 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4414 scaler_state->scaler_users);
4415
4416 return 0;
4417 }
4418
4419 /**
4420 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4421 *
4422 * @state: crtc's scaler state
4423 *
4424 * Return
4425 * 0 - scaler_usage updated successfully
4426 * error - requested scaling cannot be supported or other error condition
4427 */
4428 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4429 {
4430 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4431 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4432
4433 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4434 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4435
4436 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4437 &state->scaler_state.scaler_id, BIT(DRM_ROTATE_0),
4438 state->pipe_src_w, state->pipe_src_h,
4439 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4440 }
4441
4442 /**
4443 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4444 *
4445 * @state: crtc's scaler state
4446 * @plane_state: atomic plane state to update
4447 *
4448 * Return
4449 * 0 - scaler_usage updated successfully
4450 * error - requested scaling cannot be supported or other error condition
4451 */
4452 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4453 struct intel_plane_state *plane_state)
4454 {
4455
4456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4457 struct intel_plane *intel_plane =
4458 to_intel_plane(plane_state->base.plane);
4459 struct drm_framebuffer *fb = plane_state->base.fb;
4460 int ret;
4461
4462 bool force_detach = !fb || !plane_state->visible;
4463
4464 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4465 intel_plane->base.base.id, intel_crtc->pipe,
4466 drm_plane_index(&intel_plane->base));
4467
4468 ret = skl_update_scaler(crtc_state, force_detach,
4469 drm_plane_index(&intel_plane->base),
4470 &plane_state->scaler_id,
4471 plane_state->base.rotation,
4472 drm_rect_width(&plane_state->src) >> 16,
4473 drm_rect_height(&plane_state->src) >> 16,
4474 drm_rect_width(&plane_state->dst),
4475 drm_rect_height(&plane_state->dst));
4476
4477 if (ret || plane_state->scaler_id < 0)
4478 return ret;
4479
4480 /* check colorkey */
4481 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4482 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4483 intel_plane->base.base.id);
4484 return -EINVAL;
4485 }
4486
4487 /* Check src format */
4488 switch (fb->pixel_format) {
4489 case DRM_FORMAT_RGB565:
4490 case DRM_FORMAT_XBGR8888:
4491 case DRM_FORMAT_XRGB8888:
4492 case DRM_FORMAT_ABGR8888:
4493 case DRM_FORMAT_ARGB8888:
4494 case DRM_FORMAT_XRGB2101010:
4495 case DRM_FORMAT_XBGR2101010:
4496 case DRM_FORMAT_YUYV:
4497 case DRM_FORMAT_YVYU:
4498 case DRM_FORMAT_UYVY:
4499 case DRM_FORMAT_VYUY:
4500 break;
4501 default:
4502 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4503 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4504 return -EINVAL;
4505 }
4506
4507 return 0;
4508 }
4509
4510 static void skylake_scaler_disable(struct intel_crtc *crtc)
4511 {
4512 int i;
4513
4514 for (i = 0; i < crtc->num_scalers; i++)
4515 skl_detach_scaler(crtc, i);
4516 }
4517
4518 static void skylake_pfit_enable(struct intel_crtc *crtc)
4519 {
4520 struct drm_device *dev = crtc->base.dev;
4521 struct drm_i915_private *dev_priv = dev->dev_private;
4522 int pipe = crtc->pipe;
4523 struct intel_crtc_scaler_state *scaler_state =
4524 &crtc->config->scaler_state;
4525
4526 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4527
4528 if (crtc->config->pch_pfit.enabled) {
4529 int id;
4530
4531 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4532 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4533 return;
4534 }
4535
4536 id = scaler_state->scaler_id;
4537 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4538 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4539 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4540 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4541
4542 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4543 }
4544 }
4545
4546 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4547 {
4548 struct drm_device *dev = crtc->base.dev;
4549 struct drm_i915_private *dev_priv = dev->dev_private;
4550 int pipe = crtc->pipe;
4551
4552 if (crtc->config->pch_pfit.enabled) {
4553 /* Force use of hard-coded filter coefficients
4554 * as some pre-programmed values are broken,
4555 * e.g. x201.
4556 */
4557 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4558 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4559 PF_PIPE_SEL_IVB(pipe));
4560 else
4561 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4562 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4563 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4564 }
4565 }
4566
4567 void hsw_enable_ips(struct intel_crtc *crtc)
4568 {
4569 struct drm_device *dev = crtc->base.dev;
4570 struct drm_i915_private *dev_priv = dev->dev_private;
4571
4572 if (!crtc->config->ips_enabled)
4573 return;
4574
4575 /* We can only enable IPS after we enable a plane and wait for a vblank */
4576 intel_wait_for_vblank(dev, crtc->pipe);
4577
4578 assert_plane_enabled(dev_priv, crtc->plane);
4579 if (IS_BROADWELL(dev)) {
4580 mutex_lock(&dev_priv->rps.hw_lock);
4581 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4582 mutex_unlock(&dev_priv->rps.hw_lock);
4583 /* Quoting Art Runyan: "its not safe to expect any particular
4584 * value in IPS_CTL bit 31 after enabling IPS through the
4585 * mailbox." Moreover, the mailbox may return a bogus state,
4586 * so we need to just enable it and continue on.
4587 */
4588 } else {
4589 I915_WRITE(IPS_CTL, IPS_ENABLE);
4590 /* The bit only becomes 1 in the next vblank, so this wait here
4591 * is essentially intel_wait_for_vblank. If we don't have this
4592 * and don't wait for vblanks until the end of crtc_enable, then
4593 * the HW state readout code will complain that the expected
4594 * IPS_CTL value is not the one we read. */
4595 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4596 DRM_ERROR("Timed out waiting for IPS enable\n");
4597 }
4598 }
4599
4600 void hsw_disable_ips(struct intel_crtc *crtc)
4601 {
4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
4604
4605 if (!crtc->config->ips_enabled)
4606 return;
4607
4608 assert_plane_enabled(dev_priv, crtc->plane);
4609 if (IS_BROADWELL(dev)) {
4610 mutex_lock(&dev_priv->rps.hw_lock);
4611 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4612 mutex_unlock(&dev_priv->rps.hw_lock);
4613 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4614 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4615 DRM_ERROR("Timed out waiting for IPS disable\n");
4616 } else {
4617 I915_WRITE(IPS_CTL, 0);
4618 POSTING_READ(IPS_CTL);
4619 }
4620
4621 /* We need to wait for a vblank before we can disable the plane. */
4622 intel_wait_for_vblank(dev, crtc->pipe);
4623 }
4624
4625 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4626 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4627 {
4628 struct drm_device *dev = crtc->dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4631 enum pipe pipe = intel_crtc->pipe;
4632 int i;
4633 bool reenable_ips = false;
4634
4635 /* The clocks have to be on to load the palette. */
4636 if (!crtc->state->active)
4637 return;
4638
4639 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4640 if (intel_crtc->config->has_dsi_encoder)
4641 assert_dsi_pll_enabled(dev_priv);
4642 else
4643 assert_pll_enabled(dev_priv, pipe);
4644 }
4645
4646 /* Workaround : Do not read or write the pipe palette/gamma data while
4647 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4648 */
4649 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4650 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4651 GAMMA_MODE_MODE_SPLIT)) {
4652 hsw_disable_ips(intel_crtc);
4653 reenable_ips = true;
4654 }
4655
4656 for (i = 0; i < 256; i++) {
4657 i915_reg_t palreg;
4658
4659 if (HAS_GMCH_DISPLAY(dev))
4660 palreg = PALETTE(pipe, i);
4661 else
4662 palreg = LGC_PALETTE(pipe, i);
4663
4664 I915_WRITE(palreg,
4665 (intel_crtc->lut_r[i] << 16) |
4666 (intel_crtc->lut_g[i] << 8) |
4667 intel_crtc->lut_b[i]);
4668 }
4669
4670 if (reenable_ips)
4671 hsw_enable_ips(intel_crtc);
4672 }
4673
4674 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4675 {
4676 if (intel_crtc->overlay) {
4677 struct drm_device *dev = intel_crtc->base.dev;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679
4680 mutex_lock(&dev->struct_mutex);
4681 dev_priv->mm.interruptible = false;
4682 (void) intel_overlay_switch_off(intel_crtc->overlay);
4683 dev_priv->mm.interruptible = true;
4684 mutex_unlock(&dev->struct_mutex);
4685 }
4686
4687 /* Let userspace switch the overlay on again. In most cases userspace
4688 * has to recompute where to put it anyway.
4689 */
4690 }
4691
4692 /**
4693 * intel_post_enable_primary - Perform operations after enabling primary plane
4694 * @crtc: the CRTC whose primary plane was just enabled
4695 *
4696 * Performs potentially sleeping operations that must be done after the primary
4697 * plane is enabled, such as updating FBC and IPS. Note that this may be
4698 * called due to an explicit primary plane update, or due to an implicit
4699 * re-enable that is caused when a sprite plane is updated to no longer
4700 * completely hide the primary plane.
4701 */
4702 static void
4703 intel_post_enable_primary(struct drm_crtc *crtc)
4704 {
4705 struct drm_device *dev = crtc->dev;
4706 struct drm_i915_private *dev_priv = dev->dev_private;
4707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4708 int pipe = intel_crtc->pipe;
4709
4710 /*
4711 * FIXME IPS should be fine as long as one plane is
4712 * enabled, but in practice it seems to have problems
4713 * when going from primary only to sprite only and vice
4714 * versa.
4715 */
4716 hsw_enable_ips(intel_crtc);
4717
4718 /*
4719 * Gen2 reports pipe underruns whenever all planes are disabled.
4720 * So don't enable underrun reporting before at least some planes
4721 * are enabled.
4722 * FIXME: Need to fix the logic to work when we turn off all planes
4723 * but leave the pipe running.
4724 */
4725 if (IS_GEN2(dev))
4726 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4727
4728 /* Underruns don't always raise interrupts, so check manually. */
4729 intel_check_cpu_fifo_underruns(dev_priv);
4730 intel_check_pch_fifo_underruns(dev_priv);
4731 }
4732
4733 /**
4734 * intel_pre_disable_primary - Perform operations before disabling primary plane
4735 * @crtc: the CRTC whose primary plane is to be disabled
4736 *
4737 * Performs potentially sleeping operations that must be done before the
4738 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4739 * be called due to an explicit primary plane update, or due to an implicit
4740 * disable that is caused when a sprite plane completely hides the primary
4741 * plane.
4742 */
4743 static void
4744 intel_pre_disable_primary(struct drm_crtc *crtc)
4745 {
4746 struct drm_device *dev = crtc->dev;
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4749 int pipe = intel_crtc->pipe;
4750
4751 /*
4752 * Gen2 reports pipe underruns whenever all planes are disabled.
4753 * So diasble underrun reporting before all the planes get disabled.
4754 * FIXME: Need to fix the logic to work when we turn off all planes
4755 * but leave the pipe running.
4756 */
4757 if (IS_GEN2(dev))
4758 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4759
4760 /*
4761 * Vblank time updates from the shadow to live plane control register
4762 * are blocked if the memory self-refresh mode is active at that
4763 * moment. So to make sure the plane gets truly disabled, disable
4764 * first the self-refresh mode. The self-refresh enable bit in turn
4765 * will be checked/applied by the HW only at the next frame start
4766 * event which is after the vblank start event, so we need to have a
4767 * wait-for-vblank between disabling the plane and the pipe.
4768 */
4769 if (HAS_GMCH_DISPLAY(dev)) {
4770 intel_set_memory_cxsr(dev_priv, false);
4771 dev_priv->wm.vlv.cxsr = false;
4772 intel_wait_for_vblank(dev, pipe);
4773 }
4774
4775 /*
4776 * FIXME IPS should be fine as long as one plane is
4777 * enabled, but in practice it seems to have problems
4778 * when going from primary only to sprite only and vice
4779 * versa.
4780 */
4781 hsw_disable_ips(intel_crtc);
4782 }
4783
4784 static void intel_post_plane_update(struct intel_crtc *crtc)
4785 {
4786 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4787 struct intel_crtc_state *pipe_config =
4788 to_intel_crtc_state(crtc->base.state);
4789 struct drm_device *dev = crtc->base.dev;
4790
4791 if (atomic->wait_vblank)
4792 intel_wait_for_vblank(dev, crtc->pipe);
4793
4794 intel_frontbuffer_flip(dev, atomic->fb_bits);
4795
4796 crtc->wm.cxsr_allowed = true;
4797
4798 if (pipe_config->wm_changed && pipe_config->base.active)
4799 intel_update_watermarks(&crtc->base);
4800
4801 if (atomic->update_fbc)
4802 intel_fbc_post_update(crtc);
4803
4804 if (atomic->post_enable_primary)
4805 intel_post_enable_primary(&crtc->base);
4806
4807 memset(atomic, 0, sizeof(*atomic));
4808 }
4809
4810 static void intel_pre_plane_update(struct intel_crtc *crtc)
4811 {
4812 struct drm_device *dev = crtc->base.dev;
4813 struct drm_i915_private *dev_priv = dev->dev_private;
4814 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4815 struct intel_crtc_state *pipe_config =
4816 to_intel_crtc_state(crtc->base.state);
4817
4818 if (atomic->update_fbc)
4819 intel_fbc_pre_update(crtc);
4820
4821 if (crtc->atomic.disable_ips)
4822 hsw_disable_ips(crtc);
4823
4824 if (atomic->pre_disable_primary)
4825 intel_pre_disable_primary(&crtc->base);
4826
4827 if (pipe_config->disable_cxsr) {
4828 crtc->wm.cxsr_allowed = false;
4829 intel_set_memory_cxsr(dev_priv, false);
4830 }
4831
4832 if (!needs_modeset(&pipe_config->base) && pipe_config->wm_changed)
4833 intel_update_watermarks(&crtc->base);
4834 }
4835
4836 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4837 {
4838 struct drm_device *dev = crtc->dev;
4839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4840 struct drm_plane *p;
4841 int pipe = intel_crtc->pipe;
4842
4843 intel_crtc_dpms_overlay_disable(intel_crtc);
4844
4845 drm_for_each_plane_mask(p, dev, plane_mask)
4846 to_intel_plane(p)->disable_plane(p, crtc);
4847
4848 /*
4849 * FIXME: Once we grow proper nuclear flip support out of this we need
4850 * to compute the mask of flip planes precisely. For the time being
4851 * consider this a flip to a NULL plane.
4852 */
4853 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4854 }
4855
4856 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4857 {
4858 struct drm_device *dev = crtc->dev;
4859 struct drm_i915_private *dev_priv = dev->dev_private;
4860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4861 struct intel_encoder *encoder;
4862 int pipe = intel_crtc->pipe;
4863
4864 if (WARN_ON(intel_crtc->active))
4865 return;
4866
4867 if (intel_crtc->config->has_pch_encoder)
4868 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4869
4870 if (intel_crtc->config->has_pch_encoder)
4871 intel_prepare_shared_dpll(intel_crtc);
4872
4873 if (intel_crtc->config->has_dp_encoder)
4874 intel_dp_set_m_n(intel_crtc, M1_N1);
4875
4876 intel_set_pipe_timings(intel_crtc);
4877
4878 if (intel_crtc->config->has_pch_encoder) {
4879 intel_cpu_transcoder_set_m_n(intel_crtc,
4880 &intel_crtc->config->fdi_m_n, NULL);
4881 }
4882
4883 ironlake_set_pipeconf(crtc);
4884
4885 intel_crtc->active = true;
4886
4887 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4888
4889 for_each_encoder_on_crtc(dev, crtc, encoder)
4890 if (encoder->pre_enable)
4891 encoder->pre_enable(encoder);
4892
4893 if (intel_crtc->config->has_pch_encoder) {
4894 /* Note: FDI PLL enabling _must_ be done before we enable the
4895 * cpu pipes, hence this is separate from all the other fdi/pch
4896 * enabling. */
4897 ironlake_fdi_pll_enable(intel_crtc);
4898 } else {
4899 assert_fdi_tx_disabled(dev_priv, pipe);
4900 assert_fdi_rx_disabled(dev_priv, pipe);
4901 }
4902
4903 ironlake_pfit_enable(intel_crtc);
4904
4905 /*
4906 * On ILK+ LUT must be loaded before the pipe is running but with
4907 * clocks enabled
4908 */
4909 intel_crtc_load_lut(crtc);
4910
4911 intel_update_watermarks(crtc);
4912 intel_enable_pipe(intel_crtc);
4913
4914 if (intel_crtc->config->has_pch_encoder)
4915 ironlake_pch_enable(crtc);
4916
4917 assert_vblank_disabled(crtc);
4918 drm_crtc_vblank_on(crtc);
4919
4920 for_each_encoder_on_crtc(dev, crtc, encoder)
4921 encoder->enable(encoder);
4922
4923 if (HAS_PCH_CPT(dev))
4924 cpt_verify_modeset(dev, intel_crtc->pipe);
4925
4926 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4927 if (intel_crtc->config->has_pch_encoder)
4928 intel_wait_for_vblank(dev, pipe);
4929 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4930
4931 intel_fbc_enable(intel_crtc);
4932 }
4933
4934 /* IPS only exists on ULT machines and is tied to pipe A. */
4935 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4936 {
4937 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4938 }
4939
4940 static void haswell_crtc_enable(struct drm_crtc *crtc)
4941 {
4942 struct drm_device *dev = crtc->dev;
4943 struct drm_i915_private *dev_priv = dev->dev_private;
4944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4945 struct intel_encoder *encoder;
4946 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4947 struct intel_crtc_state *pipe_config =
4948 to_intel_crtc_state(crtc->state);
4949
4950 if (WARN_ON(intel_crtc->active))
4951 return;
4952
4953 if (intel_crtc->config->has_pch_encoder)
4954 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4955 false);
4956
4957 if (intel_crtc_to_shared_dpll(intel_crtc))
4958 intel_enable_shared_dpll(intel_crtc);
4959
4960 if (intel_crtc->config->has_dp_encoder)
4961 intel_dp_set_m_n(intel_crtc, M1_N1);
4962
4963 intel_set_pipe_timings(intel_crtc);
4964
4965 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4966 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4967 intel_crtc->config->pixel_multiplier - 1);
4968 }
4969
4970 if (intel_crtc->config->has_pch_encoder) {
4971 intel_cpu_transcoder_set_m_n(intel_crtc,
4972 &intel_crtc->config->fdi_m_n, NULL);
4973 }
4974
4975 haswell_set_pipeconf(crtc);
4976
4977 intel_set_pipe_csc(crtc);
4978
4979 intel_crtc->active = true;
4980
4981 if (intel_crtc->config->has_pch_encoder)
4982 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4983 else
4984 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4985
4986 for_each_encoder_on_crtc(dev, crtc, encoder) {
4987 if (encoder->pre_enable)
4988 encoder->pre_enable(encoder);
4989 }
4990
4991 if (intel_crtc->config->has_pch_encoder)
4992 dev_priv->display.fdi_link_train(crtc);
4993
4994 if (!intel_crtc->config->has_dsi_encoder)
4995 intel_ddi_enable_pipe_clock(intel_crtc);
4996
4997 if (INTEL_INFO(dev)->gen >= 9)
4998 skylake_pfit_enable(intel_crtc);
4999 else
5000 ironlake_pfit_enable(intel_crtc);
5001
5002 /*
5003 * On ILK+ LUT must be loaded before the pipe is running but with
5004 * clocks enabled
5005 */
5006 intel_crtc_load_lut(crtc);
5007
5008 intel_ddi_set_pipe_settings(crtc);
5009 if (!intel_crtc->config->has_dsi_encoder)
5010 intel_ddi_enable_transcoder_func(crtc);
5011
5012 intel_update_watermarks(crtc);
5013 intel_enable_pipe(intel_crtc);
5014
5015 if (intel_crtc->config->has_pch_encoder)
5016 lpt_pch_enable(crtc);
5017
5018 if (intel_crtc->config->dp_encoder_is_mst)
5019 intel_ddi_set_vc_payload_alloc(crtc, true);
5020
5021 assert_vblank_disabled(crtc);
5022 drm_crtc_vblank_on(crtc);
5023
5024 for_each_encoder_on_crtc(dev, crtc, encoder) {
5025 encoder->enable(encoder);
5026 intel_opregion_notify_encoder(encoder, true);
5027 }
5028
5029 if (intel_crtc->config->has_pch_encoder) {
5030 intel_wait_for_vblank(dev, pipe);
5031 intel_wait_for_vblank(dev, pipe);
5032 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5033 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5034 true);
5035 }
5036
5037 /* If we change the relative order between pipe/planes enabling, we need
5038 * to change the workaround. */
5039 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5040 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5041 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5042 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5043 }
5044
5045 intel_fbc_enable(intel_crtc);
5046 }
5047
5048 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5049 {
5050 struct drm_device *dev = crtc->base.dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
5052 int pipe = crtc->pipe;
5053
5054 /* To avoid upsetting the power well on haswell only disable the pfit if
5055 * it's in use. The hw state code will make sure we get this right. */
5056 if (force || crtc->config->pch_pfit.enabled) {
5057 I915_WRITE(PF_CTL(pipe), 0);
5058 I915_WRITE(PF_WIN_POS(pipe), 0);
5059 I915_WRITE(PF_WIN_SZ(pipe), 0);
5060 }
5061 }
5062
5063 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5064 {
5065 struct drm_device *dev = crtc->dev;
5066 struct drm_i915_private *dev_priv = dev->dev_private;
5067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5068 struct intel_encoder *encoder;
5069 int pipe = intel_crtc->pipe;
5070
5071 if (intel_crtc->config->has_pch_encoder)
5072 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5073
5074 for_each_encoder_on_crtc(dev, crtc, encoder)
5075 encoder->disable(encoder);
5076
5077 drm_crtc_vblank_off(crtc);
5078 assert_vblank_disabled(crtc);
5079
5080 /*
5081 * Sometimes spurious CPU pipe underruns happen when the
5082 * pipe is already disabled, but FDI RX/TX is still enabled.
5083 * Happens at least with VGA+HDMI cloning. Suppress them.
5084 */
5085 if (intel_crtc->config->has_pch_encoder)
5086 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5087
5088 intel_disable_pipe(intel_crtc);
5089
5090 ironlake_pfit_disable(intel_crtc, false);
5091
5092 if (intel_crtc->config->has_pch_encoder) {
5093 ironlake_fdi_disable(crtc);
5094 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5095 }
5096
5097 for_each_encoder_on_crtc(dev, crtc, encoder)
5098 if (encoder->post_disable)
5099 encoder->post_disable(encoder);
5100
5101 if (intel_crtc->config->has_pch_encoder) {
5102 ironlake_disable_pch_transcoder(dev_priv, pipe);
5103
5104 if (HAS_PCH_CPT(dev)) {
5105 i915_reg_t reg;
5106 u32 temp;
5107
5108 /* disable TRANS_DP_CTL */
5109 reg = TRANS_DP_CTL(pipe);
5110 temp = I915_READ(reg);
5111 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5112 TRANS_DP_PORT_SEL_MASK);
5113 temp |= TRANS_DP_PORT_SEL_NONE;
5114 I915_WRITE(reg, temp);
5115
5116 /* disable DPLL_SEL */
5117 temp = I915_READ(PCH_DPLL_SEL);
5118 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5119 I915_WRITE(PCH_DPLL_SEL, temp);
5120 }
5121
5122 ironlake_fdi_pll_disable(intel_crtc);
5123 }
5124
5125 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5126
5127 intel_fbc_disable(intel_crtc);
5128 }
5129
5130 static void haswell_crtc_disable(struct drm_crtc *crtc)
5131 {
5132 struct drm_device *dev = crtc->dev;
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5135 struct intel_encoder *encoder;
5136 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5137
5138 if (intel_crtc->config->has_pch_encoder)
5139 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5140 false);
5141
5142 for_each_encoder_on_crtc(dev, crtc, encoder) {
5143 intel_opregion_notify_encoder(encoder, false);
5144 encoder->disable(encoder);
5145 }
5146
5147 drm_crtc_vblank_off(crtc);
5148 assert_vblank_disabled(crtc);
5149
5150 intel_disable_pipe(intel_crtc);
5151
5152 if (intel_crtc->config->dp_encoder_is_mst)
5153 intel_ddi_set_vc_payload_alloc(crtc, false);
5154
5155 if (!intel_crtc->config->has_dsi_encoder)
5156 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5157
5158 if (INTEL_INFO(dev)->gen >= 9)
5159 skylake_scaler_disable(intel_crtc);
5160 else
5161 ironlake_pfit_disable(intel_crtc, false);
5162
5163 if (!intel_crtc->config->has_dsi_encoder)
5164 intel_ddi_disable_pipe_clock(intel_crtc);
5165
5166 for_each_encoder_on_crtc(dev, crtc, encoder)
5167 if (encoder->post_disable)
5168 encoder->post_disable(encoder);
5169
5170 if (intel_crtc->config->has_pch_encoder) {
5171 lpt_disable_pch_transcoder(dev_priv);
5172 lpt_disable_iclkip(dev_priv);
5173 intel_ddi_fdi_disable(crtc);
5174
5175 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5176 true);
5177 }
5178
5179 intel_fbc_disable(intel_crtc);
5180 }
5181
5182 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5183 {
5184 struct drm_device *dev = crtc->base.dev;
5185 struct drm_i915_private *dev_priv = dev->dev_private;
5186 struct intel_crtc_state *pipe_config = crtc->config;
5187
5188 if (!pipe_config->gmch_pfit.control)
5189 return;
5190
5191 /*
5192 * The panel fitter should only be adjusted whilst the pipe is disabled,
5193 * according to register description and PRM.
5194 */
5195 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5196 assert_pipe_disabled(dev_priv, crtc->pipe);
5197
5198 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5199 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5200
5201 /* Border color in case we don't scale up to the full screen. Black by
5202 * default, change to something else for debugging. */
5203 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5204 }
5205
5206 static enum intel_display_power_domain port_to_power_domain(enum port port)
5207 {
5208 switch (port) {
5209 case PORT_A:
5210 return POWER_DOMAIN_PORT_DDI_A_LANES;
5211 case PORT_B:
5212 return POWER_DOMAIN_PORT_DDI_B_LANES;
5213 case PORT_C:
5214 return POWER_DOMAIN_PORT_DDI_C_LANES;
5215 case PORT_D:
5216 return POWER_DOMAIN_PORT_DDI_D_LANES;
5217 case PORT_E:
5218 return POWER_DOMAIN_PORT_DDI_E_LANES;
5219 default:
5220 MISSING_CASE(port);
5221 return POWER_DOMAIN_PORT_OTHER;
5222 }
5223 }
5224
5225 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5226 {
5227 switch (port) {
5228 case PORT_A:
5229 return POWER_DOMAIN_AUX_A;
5230 case PORT_B:
5231 return POWER_DOMAIN_AUX_B;
5232 case PORT_C:
5233 return POWER_DOMAIN_AUX_C;
5234 case PORT_D:
5235 return POWER_DOMAIN_AUX_D;
5236 case PORT_E:
5237 /* FIXME: Check VBT for actual wiring of PORT E */
5238 return POWER_DOMAIN_AUX_D;
5239 default:
5240 MISSING_CASE(port);
5241 return POWER_DOMAIN_AUX_A;
5242 }
5243 }
5244
5245 enum intel_display_power_domain
5246 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5247 {
5248 struct drm_device *dev = intel_encoder->base.dev;
5249 struct intel_digital_port *intel_dig_port;
5250
5251 switch (intel_encoder->type) {
5252 case INTEL_OUTPUT_UNKNOWN:
5253 /* Only DDI platforms should ever use this output type */
5254 WARN_ON_ONCE(!HAS_DDI(dev));
5255 case INTEL_OUTPUT_DISPLAYPORT:
5256 case INTEL_OUTPUT_HDMI:
5257 case INTEL_OUTPUT_EDP:
5258 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5259 return port_to_power_domain(intel_dig_port->port);
5260 case INTEL_OUTPUT_DP_MST:
5261 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5262 return port_to_power_domain(intel_dig_port->port);
5263 case INTEL_OUTPUT_ANALOG:
5264 return POWER_DOMAIN_PORT_CRT;
5265 case INTEL_OUTPUT_DSI:
5266 return POWER_DOMAIN_PORT_DSI;
5267 default:
5268 return POWER_DOMAIN_PORT_OTHER;
5269 }
5270 }
5271
5272 enum intel_display_power_domain
5273 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5274 {
5275 struct drm_device *dev = intel_encoder->base.dev;
5276 struct intel_digital_port *intel_dig_port;
5277
5278 switch (intel_encoder->type) {
5279 case INTEL_OUTPUT_UNKNOWN:
5280 case INTEL_OUTPUT_HDMI:
5281 /*
5282 * Only DDI platforms should ever use these output types.
5283 * We can get here after the HDMI detect code has already set
5284 * the type of the shared encoder. Since we can't be sure
5285 * what's the status of the given connectors, play safe and
5286 * run the DP detection too.
5287 */
5288 WARN_ON_ONCE(!HAS_DDI(dev));
5289 case INTEL_OUTPUT_DISPLAYPORT:
5290 case INTEL_OUTPUT_EDP:
5291 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5292 return port_to_aux_power_domain(intel_dig_port->port);
5293 case INTEL_OUTPUT_DP_MST:
5294 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5295 return port_to_aux_power_domain(intel_dig_port->port);
5296 default:
5297 MISSING_CASE(intel_encoder->type);
5298 return POWER_DOMAIN_AUX_A;
5299 }
5300 }
5301
5302 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5303 {
5304 struct drm_device *dev = crtc->dev;
5305 struct intel_encoder *intel_encoder;
5306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5307 enum pipe pipe = intel_crtc->pipe;
5308 unsigned long mask;
5309 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5310
5311 if (!crtc->state->active)
5312 return 0;
5313
5314 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5315 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5316 if (intel_crtc->config->pch_pfit.enabled ||
5317 intel_crtc->config->pch_pfit.force_thru)
5318 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5319
5320 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5321 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5322
5323 return mask;
5324 }
5325
5326 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5327 {
5328 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5330 enum intel_display_power_domain domain;
5331 unsigned long domains, new_domains, old_domains;
5332
5333 old_domains = intel_crtc->enabled_power_domains;
5334 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5335
5336 domains = new_domains & ~old_domains;
5337
5338 for_each_power_domain(domain, domains)
5339 intel_display_power_get(dev_priv, domain);
5340
5341 return old_domains & ~new_domains;
5342 }
5343
5344 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5345 unsigned long domains)
5346 {
5347 enum intel_display_power_domain domain;
5348
5349 for_each_power_domain(domain, domains)
5350 intel_display_power_put(dev_priv, domain);
5351 }
5352
5353 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5354 {
5355 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5356 struct drm_device *dev = state->dev;
5357 struct drm_i915_private *dev_priv = dev->dev_private;
5358 unsigned long put_domains[I915_MAX_PIPES] = {};
5359 struct drm_crtc_state *crtc_state;
5360 struct drm_crtc *crtc;
5361 int i;
5362
5363 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5364 if (needs_modeset(crtc->state))
5365 put_domains[to_intel_crtc(crtc)->pipe] =
5366 modeset_get_crtc_power_domains(crtc);
5367 }
5368
5369 if (dev_priv->display.modeset_commit_cdclk &&
5370 intel_state->dev_cdclk != dev_priv->cdclk_freq)
5371 dev_priv->display.modeset_commit_cdclk(state);
5372
5373 for (i = 0; i < I915_MAX_PIPES; i++)
5374 if (put_domains[i])
5375 modeset_put_power_domains(dev_priv, put_domains[i]);
5376 }
5377
5378 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5379 {
5380 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5381
5382 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5383 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5384 return max_cdclk_freq;
5385 else if (IS_CHERRYVIEW(dev_priv))
5386 return max_cdclk_freq*95/100;
5387 else if (INTEL_INFO(dev_priv)->gen < 4)
5388 return 2*max_cdclk_freq*90/100;
5389 else
5390 return max_cdclk_freq*90/100;
5391 }
5392
5393 static void intel_update_max_cdclk(struct drm_device *dev)
5394 {
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396
5397 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5398 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5399
5400 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5401 dev_priv->max_cdclk_freq = 675000;
5402 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5403 dev_priv->max_cdclk_freq = 540000;
5404 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5405 dev_priv->max_cdclk_freq = 450000;
5406 else
5407 dev_priv->max_cdclk_freq = 337500;
5408 } else if (IS_BROADWELL(dev)) {
5409 /*
5410 * FIXME with extra cooling we can allow
5411 * 540 MHz for ULX and 675 Mhz for ULT.
5412 * How can we know if extra cooling is
5413 * available? PCI ID, VTB, something else?
5414 */
5415 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5416 dev_priv->max_cdclk_freq = 450000;
5417 else if (IS_BDW_ULX(dev))
5418 dev_priv->max_cdclk_freq = 450000;
5419 else if (IS_BDW_ULT(dev))
5420 dev_priv->max_cdclk_freq = 540000;
5421 else
5422 dev_priv->max_cdclk_freq = 675000;
5423 } else if (IS_CHERRYVIEW(dev)) {
5424 dev_priv->max_cdclk_freq = 320000;
5425 } else if (IS_VALLEYVIEW(dev)) {
5426 dev_priv->max_cdclk_freq = 400000;
5427 } else {
5428 /* otherwise assume cdclk is fixed */
5429 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5430 }
5431
5432 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5433
5434 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5435 dev_priv->max_cdclk_freq);
5436
5437 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5438 dev_priv->max_dotclk_freq);
5439 }
5440
5441 static void intel_update_cdclk(struct drm_device *dev)
5442 {
5443 struct drm_i915_private *dev_priv = dev->dev_private;
5444
5445 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5446 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5447 dev_priv->cdclk_freq);
5448
5449 /*
5450 * Program the gmbus_freq based on the cdclk frequency.
5451 * BSpec erroneously claims we should aim for 4MHz, but
5452 * in fact 1MHz is the correct frequency.
5453 */
5454 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5455 /*
5456 * Program the gmbus_freq based on the cdclk frequency.
5457 * BSpec erroneously claims we should aim for 4MHz, but
5458 * in fact 1MHz is the correct frequency.
5459 */
5460 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5461 }
5462
5463 if (dev_priv->max_cdclk_freq == 0)
5464 intel_update_max_cdclk(dev);
5465 }
5466
5467 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5468 {
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470 uint32_t divider;
5471 uint32_t ratio;
5472 uint32_t current_freq;
5473 int ret;
5474
5475 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5476 switch (frequency) {
5477 case 144000:
5478 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5479 ratio = BXT_DE_PLL_RATIO(60);
5480 break;
5481 case 288000:
5482 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5483 ratio = BXT_DE_PLL_RATIO(60);
5484 break;
5485 case 384000:
5486 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5487 ratio = BXT_DE_PLL_RATIO(60);
5488 break;
5489 case 576000:
5490 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5491 ratio = BXT_DE_PLL_RATIO(60);
5492 break;
5493 case 624000:
5494 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5495 ratio = BXT_DE_PLL_RATIO(65);
5496 break;
5497 case 19200:
5498 /*
5499 * Bypass frequency with DE PLL disabled. Init ratio, divider
5500 * to suppress GCC warning.
5501 */
5502 ratio = 0;
5503 divider = 0;
5504 break;
5505 default:
5506 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5507
5508 return;
5509 }
5510
5511 mutex_lock(&dev_priv->rps.hw_lock);
5512 /* Inform power controller of upcoming frequency change */
5513 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5514 0x80000000);
5515 mutex_unlock(&dev_priv->rps.hw_lock);
5516
5517 if (ret) {
5518 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5519 ret, frequency);
5520 return;
5521 }
5522
5523 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5524 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5525 current_freq = current_freq * 500 + 1000;
5526
5527 /*
5528 * DE PLL has to be disabled when
5529 * - setting to 19.2MHz (bypass, PLL isn't used)
5530 * - before setting to 624MHz (PLL needs toggling)
5531 * - before setting to any frequency from 624MHz (PLL needs toggling)
5532 */
5533 if (frequency == 19200 || frequency == 624000 ||
5534 current_freq == 624000) {
5535 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5536 /* Timeout 200us */
5537 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5538 1))
5539 DRM_ERROR("timout waiting for DE PLL unlock\n");
5540 }
5541
5542 if (frequency != 19200) {
5543 uint32_t val;
5544
5545 val = I915_READ(BXT_DE_PLL_CTL);
5546 val &= ~BXT_DE_PLL_RATIO_MASK;
5547 val |= ratio;
5548 I915_WRITE(BXT_DE_PLL_CTL, val);
5549
5550 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5551 /* Timeout 200us */
5552 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5553 DRM_ERROR("timeout waiting for DE PLL lock\n");
5554
5555 val = I915_READ(CDCLK_CTL);
5556 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5557 val |= divider;
5558 /*
5559 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5560 * enable otherwise.
5561 */
5562 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5563 if (frequency >= 500000)
5564 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5565
5566 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5567 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5568 val |= (frequency - 1000) / 500;
5569 I915_WRITE(CDCLK_CTL, val);
5570 }
5571
5572 mutex_lock(&dev_priv->rps.hw_lock);
5573 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5574 DIV_ROUND_UP(frequency, 25000));
5575 mutex_unlock(&dev_priv->rps.hw_lock);
5576
5577 if (ret) {
5578 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5579 ret, frequency);
5580 return;
5581 }
5582
5583 intel_update_cdclk(dev);
5584 }
5585
5586 void broxton_init_cdclk(struct drm_device *dev)
5587 {
5588 struct drm_i915_private *dev_priv = dev->dev_private;
5589 uint32_t val;
5590
5591 /*
5592 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5593 * or else the reset will hang because there is no PCH to respond.
5594 * Move the handshake programming to initialization sequence.
5595 * Previously was left up to BIOS.
5596 */
5597 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5598 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5599 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5600
5601 /* Enable PG1 for cdclk */
5602 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5603
5604 /* check if cd clock is enabled */
5605 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5606 DRM_DEBUG_KMS("Display already initialized\n");
5607 return;
5608 }
5609
5610 /*
5611 * FIXME:
5612 * - The initial CDCLK needs to be read from VBT.
5613 * Need to make this change after VBT has changes for BXT.
5614 * - check if setting the max (or any) cdclk freq is really necessary
5615 * here, it belongs to modeset time
5616 */
5617 broxton_set_cdclk(dev, 624000);
5618
5619 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5620 POSTING_READ(DBUF_CTL);
5621
5622 udelay(10);
5623
5624 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5625 DRM_ERROR("DBuf power enable timeout!\n");
5626 }
5627
5628 void broxton_uninit_cdclk(struct drm_device *dev)
5629 {
5630 struct drm_i915_private *dev_priv = dev->dev_private;
5631
5632 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5633 POSTING_READ(DBUF_CTL);
5634
5635 udelay(10);
5636
5637 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5638 DRM_ERROR("DBuf power disable timeout!\n");
5639
5640 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5641 broxton_set_cdclk(dev, 19200);
5642
5643 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5644 }
5645
5646 static const struct skl_cdclk_entry {
5647 unsigned int freq;
5648 unsigned int vco;
5649 } skl_cdclk_frequencies[] = {
5650 { .freq = 308570, .vco = 8640 },
5651 { .freq = 337500, .vco = 8100 },
5652 { .freq = 432000, .vco = 8640 },
5653 { .freq = 450000, .vco = 8100 },
5654 { .freq = 540000, .vco = 8100 },
5655 { .freq = 617140, .vco = 8640 },
5656 { .freq = 675000, .vco = 8100 },
5657 };
5658
5659 static unsigned int skl_cdclk_decimal(unsigned int freq)
5660 {
5661 return (freq - 1000) / 500;
5662 }
5663
5664 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5665 {
5666 unsigned int i;
5667
5668 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5669 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5670
5671 if (e->freq == freq)
5672 return e->vco;
5673 }
5674
5675 return 8100;
5676 }
5677
5678 static void
5679 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5680 {
5681 unsigned int min_freq;
5682 u32 val;
5683
5684 /* select the minimum CDCLK before enabling DPLL 0 */
5685 val = I915_READ(CDCLK_CTL);
5686 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5687 val |= CDCLK_FREQ_337_308;
5688
5689 if (required_vco == 8640)
5690 min_freq = 308570;
5691 else
5692 min_freq = 337500;
5693
5694 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5695
5696 I915_WRITE(CDCLK_CTL, val);
5697 POSTING_READ(CDCLK_CTL);
5698
5699 /*
5700 * We always enable DPLL0 with the lowest link rate possible, but still
5701 * taking into account the VCO required to operate the eDP panel at the
5702 * desired frequency. The usual DP link rates operate with a VCO of
5703 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5704 * The modeset code is responsible for the selection of the exact link
5705 * rate later on, with the constraint of choosing a frequency that
5706 * works with required_vco.
5707 */
5708 val = I915_READ(DPLL_CTRL1);
5709
5710 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5711 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5712 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5713 if (required_vco == 8640)
5714 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5715 SKL_DPLL0);
5716 else
5717 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5718 SKL_DPLL0);
5719
5720 I915_WRITE(DPLL_CTRL1, val);
5721 POSTING_READ(DPLL_CTRL1);
5722
5723 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5724
5725 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5726 DRM_ERROR("DPLL0 not locked\n");
5727 }
5728
5729 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5730 {
5731 int ret;
5732 u32 val;
5733
5734 /* inform PCU we want to change CDCLK */
5735 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5736 mutex_lock(&dev_priv->rps.hw_lock);
5737 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5738 mutex_unlock(&dev_priv->rps.hw_lock);
5739
5740 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5741 }
5742
5743 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5744 {
5745 unsigned int i;
5746
5747 for (i = 0; i < 15; i++) {
5748 if (skl_cdclk_pcu_ready(dev_priv))
5749 return true;
5750 udelay(10);
5751 }
5752
5753 return false;
5754 }
5755
5756 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5757 {
5758 struct drm_device *dev = dev_priv->dev;
5759 u32 freq_select, pcu_ack;
5760
5761 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5762
5763 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5764 DRM_ERROR("failed to inform PCU about cdclk change\n");
5765 return;
5766 }
5767
5768 /* set CDCLK_CTL */
5769 switch(freq) {
5770 case 450000:
5771 case 432000:
5772 freq_select = CDCLK_FREQ_450_432;
5773 pcu_ack = 1;
5774 break;
5775 case 540000:
5776 freq_select = CDCLK_FREQ_540;
5777 pcu_ack = 2;
5778 break;
5779 case 308570:
5780 case 337500:
5781 default:
5782 freq_select = CDCLK_FREQ_337_308;
5783 pcu_ack = 0;
5784 break;
5785 case 617140:
5786 case 675000:
5787 freq_select = CDCLK_FREQ_675_617;
5788 pcu_ack = 3;
5789 break;
5790 }
5791
5792 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5793 POSTING_READ(CDCLK_CTL);
5794
5795 /* inform PCU of the change */
5796 mutex_lock(&dev_priv->rps.hw_lock);
5797 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5798 mutex_unlock(&dev_priv->rps.hw_lock);
5799
5800 intel_update_cdclk(dev);
5801 }
5802
5803 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5804 {
5805 /* disable DBUF power */
5806 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5807 POSTING_READ(DBUF_CTL);
5808
5809 udelay(10);
5810
5811 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5812 DRM_ERROR("DBuf power disable timeout\n");
5813
5814 /* disable DPLL0 */
5815 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5816 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5817 DRM_ERROR("Couldn't disable DPLL0\n");
5818 }
5819
5820 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5821 {
5822 unsigned int required_vco;
5823
5824 /* DPLL0 not enabled (happens on early BIOS versions) */
5825 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5826 /* enable DPLL0 */
5827 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5828 skl_dpll0_enable(dev_priv, required_vco);
5829 }
5830
5831 /* set CDCLK to the frequency the BIOS chose */
5832 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5833
5834 /* enable DBUF power */
5835 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5836 POSTING_READ(DBUF_CTL);
5837
5838 udelay(10);
5839
5840 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5841 DRM_ERROR("DBuf power enable timeout\n");
5842 }
5843
5844 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5845 {
5846 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5847 uint32_t cdctl = I915_READ(CDCLK_CTL);
5848 int freq = dev_priv->skl_boot_cdclk;
5849
5850 /*
5851 * check if the pre-os intialized the display
5852 * There is SWF18 scratchpad register defined which is set by the
5853 * pre-os which can be used by the OS drivers to check the status
5854 */
5855 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5856 goto sanitize;
5857
5858 /* Is PLL enabled and locked ? */
5859 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5860 goto sanitize;
5861
5862 /* DPLL okay; verify the cdclock
5863 *
5864 * Noticed in some instances that the freq selection is correct but
5865 * decimal part is programmed wrong from BIOS where pre-os does not
5866 * enable display. Verify the same as well.
5867 */
5868 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5869 /* All well; nothing to sanitize */
5870 return false;
5871 sanitize:
5872 /*
5873 * As of now initialize with max cdclk till
5874 * we get dynamic cdclk support
5875 * */
5876 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5877 skl_init_cdclk(dev_priv);
5878
5879 /* we did have to sanitize */
5880 return true;
5881 }
5882
5883 /* Adjust CDclk dividers to allow high res or save power if possible */
5884 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5885 {
5886 struct drm_i915_private *dev_priv = dev->dev_private;
5887 u32 val, cmd;
5888
5889 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5890 != dev_priv->cdclk_freq);
5891
5892 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5893 cmd = 2;
5894 else if (cdclk == 266667)
5895 cmd = 1;
5896 else
5897 cmd = 0;
5898
5899 mutex_lock(&dev_priv->rps.hw_lock);
5900 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5901 val &= ~DSPFREQGUAR_MASK;
5902 val |= (cmd << DSPFREQGUAR_SHIFT);
5903 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5904 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5905 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5906 50)) {
5907 DRM_ERROR("timed out waiting for CDclk change\n");
5908 }
5909 mutex_unlock(&dev_priv->rps.hw_lock);
5910
5911 mutex_lock(&dev_priv->sb_lock);
5912
5913 if (cdclk == 400000) {
5914 u32 divider;
5915
5916 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5917
5918 /* adjust cdclk divider */
5919 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5920 val &= ~CCK_FREQUENCY_VALUES;
5921 val |= divider;
5922 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5923
5924 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5925 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5926 50))
5927 DRM_ERROR("timed out waiting for CDclk change\n");
5928 }
5929
5930 /* adjust self-refresh exit latency value */
5931 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5932 val &= ~0x7f;
5933
5934 /*
5935 * For high bandwidth configs, we set a higher latency in the bunit
5936 * so that the core display fetch happens in time to avoid underruns.
5937 */
5938 if (cdclk == 400000)
5939 val |= 4500 / 250; /* 4.5 usec */
5940 else
5941 val |= 3000 / 250; /* 3.0 usec */
5942 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5943
5944 mutex_unlock(&dev_priv->sb_lock);
5945
5946 intel_update_cdclk(dev);
5947 }
5948
5949 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5950 {
5951 struct drm_i915_private *dev_priv = dev->dev_private;
5952 u32 val, cmd;
5953
5954 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5955 != dev_priv->cdclk_freq);
5956
5957 switch (cdclk) {
5958 case 333333:
5959 case 320000:
5960 case 266667:
5961 case 200000:
5962 break;
5963 default:
5964 MISSING_CASE(cdclk);
5965 return;
5966 }
5967
5968 /*
5969 * Specs are full of misinformation, but testing on actual
5970 * hardware has shown that we just need to write the desired
5971 * CCK divider into the Punit register.
5972 */
5973 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5974
5975 mutex_lock(&dev_priv->rps.hw_lock);
5976 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5977 val &= ~DSPFREQGUAR_MASK_CHV;
5978 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5979 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5980 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5981 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5982 50)) {
5983 DRM_ERROR("timed out waiting for CDclk change\n");
5984 }
5985 mutex_unlock(&dev_priv->rps.hw_lock);
5986
5987 intel_update_cdclk(dev);
5988 }
5989
5990 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5991 int max_pixclk)
5992 {
5993 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5994 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5995
5996 /*
5997 * Really only a few cases to deal with, as only 4 CDclks are supported:
5998 * 200MHz
5999 * 267MHz
6000 * 320/333MHz (depends on HPLL freq)
6001 * 400MHz (VLV only)
6002 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6003 * of the lower bin and adjust if needed.
6004 *
6005 * We seem to get an unstable or solid color picture at 200MHz.
6006 * Not sure what's wrong. For now use 200MHz only when all pipes
6007 * are off.
6008 */
6009 if (!IS_CHERRYVIEW(dev_priv) &&
6010 max_pixclk > freq_320*limit/100)
6011 return 400000;
6012 else if (max_pixclk > 266667*limit/100)
6013 return freq_320;
6014 else if (max_pixclk > 0)
6015 return 266667;
6016 else
6017 return 200000;
6018 }
6019
6020 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6021 int max_pixclk)
6022 {
6023 /*
6024 * FIXME:
6025 * - remove the guardband, it's not needed on BXT
6026 * - set 19.2MHz bypass frequency if there are no active pipes
6027 */
6028 if (max_pixclk > 576000*9/10)
6029 return 624000;
6030 else if (max_pixclk > 384000*9/10)
6031 return 576000;
6032 else if (max_pixclk > 288000*9/10)
6033 return 384000;
6034 else if (max_pixclk > 144000*9/10)
6035 return 288000;
6036 else
6037 return 144000;
6038 }
6039
6040 /* Compute the max pixel clock for new configuration. Uses atomic state if
6041 * that's non-NULL, look at current state otherwise. */
6042 static int intel_mode_max_pixclk(struct drm_device *dev,
6043 struct drm_atomic_state *state)
6044 {
6045 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6046 struct drm_i915_private *dev_priv = dev->dev_private;
6047 struct drm_crtc *crtc;
6048 struct drm_crtc_state *crtc_state;
6049 unsigned max_pixclk = 0, i;
6050 enum pipe pipe;
6051
6052 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6053 sizeof(intel_state->min_pixclk));
6054
6055 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6056 int pixclk = 0;
6057
6058 if (crtc_state->enable)
6059 pixclk = crtc_state->adjusted_mode.crtc_clock;
6060
6061 intel_state->min_pixclk[i] = pixclk;
6062 }
6063
6064 if (!intel_state->active_crtcs)
6065 return 0;
6066
6067 for_each_pipe(dev_priv, pipe)
6068 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6069
6070 return max_pixclk;
6071 }
6072
6073 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6074 {
6075 struct drm_device *dev = state->dev;
6076 struct drm_i915_private *dev_priv = dev->dev_private;
6077 int max_pixclk = intel_mode_max_pixclk(dev, state);
6078 struct intel_atomic_state *intel_state =
6079 to_intel_atomic_state(state);
6080
6081 if (max_pixclk < 0)
6082 return max_pixclk;
6083
6084 intel_state->cdclk = intel_state->dev_cdclk =
6085 valleyview_calc_cdclk(dev_priv, max_pixclk);
6086
6087 if (!intel_state->active_crtcs)
6088 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6089
6090 return 0;
6091 }
6092
6093 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6094 {
6095 struct drm_device *dev = state->dev;
6096 struct drm_i915_private *dev_priv = dev->dev_private;
6097 int max_pixclk = intel_mode_max_pixclk(dev, state);
6098 struct intel_atomic_state *intel_state =
6099 to_intel_atomic_state(state);
6100
6101 if (max_pixclk < 0)
6102 return max_pixclk;
6103
6104 intel_state->cdclk = intel_state->dev_cdclk =
6105 broxton_calc_cdclk(dev_priv, max_pixclk);
6106
6107 if (!intel_state->active_crtcs)
6108 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6109
6110 return 0;
6111 }
6112
6113 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6114 {
6115 unsigned int credits, default_credits;
6116
6117 if (IS_CHERRYVIEW(dev_priv))
6118 default_credits = PFI_CREDIT(12);
6119 else
6120 default_credits = PFI_CREDIT(8);
6121
6122 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6123 /* CHV suggested value is 31 or 63 */
6124 if (IS_CHERRYVIEW(dev_priv))
6125 credits = PFI_CREDIT_63;
6126 else
6127 credits = PFI_CREDIT(15);
6128 } else {
6129 credits = default_credits;
6130 }
6131
6132 /*
6133 * WA - write default credits before re-programming
6134 * FIXME: should we also set the resend bit here?
6135 */
6136 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6137 default_credits);
6138
6139 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6140 credits | PFI_CREDIT_RESEND);
6141
6142 /*
6143 * FIXME is this guaranteed to clear
6144 * immediately or should we poll for it?
6145 */
6146 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6147 }
6148
6149 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6150 {
6151 struct drm_device *dev = old_state->dev;
6152 struct drm_i915_private *dev_priv = dev->dev_private;
6153 struct intel_atomic_state *old_intel_state =
6154 to_intel_atomic_state(old_state);
6155 unsigned req_cdclk = old_intel_state->dev_cdclk;
6156
6157 /*
6158 * FIXME: We can end up here with all power domains off, yet
6159 * with a CDCLK frequency other than the minimum. To account
6160 * for this take the PIPE-A power domain, which covers the HW
6161 * blocks needed for the following programming. This can be
6162 * removed once it's guaranteed that we get here either with
6163 * the minimum CDCLK set, or the required power domains
6164 * enabled.
6165 */
6166 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6167
6168 if (IS_CHERRYVIEW(dev))
6169 cherryview_set_cdclk(dev, req_cdclk);
6170 else
6171 valleyview_set_cdclk(dev, req_cdclk);
6172
6173 vlv_program_pfi_credits(dev_priv);
6174
6175 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6176 }
6177
6178 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6179 {
6180 struct drm_device *dev = crtc->dev;
6181 struct drm_i915_private *dev_priv = to_i915(dev);
6182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6183 struct intel_encoder *encoder;
6184 int pipe = intel_crtc->pipe;
6185
6186 if (WARN_ON(intel_crtc->active))
6187 return;
6188
6189 if (intel_crtc->config->has_dp_encoder)
6190 intel_dp_set_m_n(intel_crtc, M1_N1);
6191
6192 intel_set_pipe_timings(intel_crtc);
6193
6194 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6195 struct drm_i915_private *dev_priv = dev->dev_private;
6196
6197 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6198 I915_WRITE(CHV_CANVAS(pipe), 0);
6199 }
6200
6201 i9xx_set_pipeconf(intel_crtc);
6202
6203 intel_crtc->active = true;
6204
6205 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6206
6207 for_each_encoder_on_crtc(dev, crtc, encoder)
6208 if (encoder->pre_pll_enable)
6209 encoder->pre_pll_enable(encoder);
6210
6211 if (!intel_crtc->config->has_dsi_encoder) {
6212 if (IS_CHERRYVIEW(dev)) {
6213 chv_prepare_pll(intel_crtc, intel_crtc->config);
6214 chv_enable_pll(intel_crtc, intel_crtc->config);
6215 } else {
6216 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6217 vlv_enable_pll(intel_crtc, intel_crtc->config);
6218 }
6219 }
6220
6221 for_each_encoder_on_crtc(dev, crtc, encoder)
6222 if (encoder->pre_enable)
6223 encoder->pre_enable(encoder);
6224
6225 i9xx_pfit_enable(intel_crtc);
6226
6227 intel_crtc_load_lut(crtc);
6228
6229 intel_enable_pipe(intel_crtc);
6230
6231 assert_vblank_disabled(crtc);
6232 drm_crtc_vblank_on(crtc);
6233
6234 for_each_encoder_on_crtc(dev, crtc, encoder)
6235 encoder->enable(encoder);
6236 }
6237
6238 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6239 {
6240 struct drm_device *dev = crtc->base.dev;
6241 struct drm_i915_private *dev_priv = dev->dev_private;
6242
6243 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6244 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6245 }
6246
6247 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6248 {
6249 struct drm_device *dev = crtc->dev;
6250 struct drm_i915_private *dev_priv = to_i915(dev);
6251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6252 struct intel_encoder *encoder;
6253 int pipe = intel_crtc->pipe;
6254
6255 if (WARN_ON(intel_crtc->active))
6256 return;
6257
6258 i9xx_set_pll_dividers(intel_crtc);
6259
6260 if (intel_crtc->config->has_dp_encoder)
6261 intel_dp_set_m_n(intel_crtc, M1_N1);
6262
6263 intel_set_pipe_timings(intel_crtc);
6264
6265 i9xx_set_pipeconf(intel_crtc);
6266
6267 intel_crtc->active = true;
6268
6269 if (!IS_GEN2(dev))
6270 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6271
6272 for_each_encoder_on_crtc(dev, crtc, encoder)
6273 if (encoder->pre_enable)
6274 encoder->pre_enable(encoder);
6275
6276 i9xx_enable_pll(intel_crtc);
6277
6278 i9xx_pfit_enable(intel_crtc);
6279
6280 intel_crtc_load_lut(crtc);
6281
6282 intel_update_watermarks(crtc);
6283 intel_enable_pipe(intel_crtc);
6284
6285 assert_vblank_disabled(crtc);
6286 drm_crtc_vblank_on(crtc);
6287
6288 for_each_encoder_on_crtc(dev, crtc, encoder)
6289 encoder->enable(encoder);
6290
6291 intel_fbc_enable(intel_crtc);
6292 }
6293
6294 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6295 {
6296 struct drm_device *dev = crtc->base.dev;
6297 struct drm_i915_private *dev_priv = dev->dev_private;
6298
6299 if (!crtc->config->gmch_pfit.control)
6300 return;
6301
6302 assert_pipe_disabled(dev_priv, crtc->pipe);
6303
6304 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6305 I915_READ(PFIT_CONTROL));
6306 I915_WRITE(PFIT_CONTROL, 0);
6307 }
6308
6309 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6310 {
6311 struct drm_device *dev = crtc->dev;
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6314 struct intel_encoder *encoder;
6315 int pipe = intel_crtc->pipe;
6316
6317 /*
6318 * On gen2 planes are double buffered but the pipe isn't, so we must
6319 * wait for planes to fully turn off before disabling the pipe.
6320 * We also need to wait on all gmch platforms because of the
6321 * self-refresh mode constraint explained above.
6322 */
6323 intel_wait_for_vblank(dev, pipe);
6324
6325 for_each_encoder_on_crtc(dev, crtc, encoder)
6326 encoder->disable(encoder);
6327
6328 drm_crtc_vblank_off(crtc);
6329 assert_vblank_disabled(crtc);
6330
6331 intel_disable_pipe(intel_crtc);
6332
6333 i9xx_pfit_disable(intel_crtc);
6334
6335 for_each_encoder_on_crtc(dev, crtc, encoder)
6336 if (encoder->post_disable)
6337 encoder->post_disable(encoder);
6338
6339 if (!intel_crtc->config->has_dsi_encoder) {
6340 if (IS_CHERRYVIEW(dev))
6341 chv_disable_pll(dev_priv, pipe);
6342 else if (IS_VALLEYVIEW(dev))
6343 vlv_disable_pll(dev_priv, pipe);
6344 else
6345 i9xx_disable_pll(intel_crtc);
6346 }
6347
6348 for_each_encoder_on_crtc(dev, crtc, encoder)
6349 if (encoder->post_pll_disable)
6350 encoder->post_pll_disable(encoder);
6351
6352 if (!IS_GEN2(dev))
6353 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6354
6355 intel_fbc_disable(intel_crtc);
6356 }
6357
6358 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6359 {
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6362 enum intel_display_power_domain domain;
6363 unsigned long domains;
6364
6365 if (!intel_crtc->active)
6366 return;
6367
6368 if (to_intel_plane_state(crtc->primary->state)->visible) {
6369 WARN_ON(intel_crtc->unpin_work);
6370
6371 intel_pre_disable_primary(crtc);
6372
6373 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6374 to_intel_plane_state(crtc->primary->state)->visible = false;
6375 }
6376
6377 dev_priv->display.crtc_disable(crtc);
6378 intel_crtc->active = false;
6379 intel_update_watermarks(crtc);
6380 intel_disable_shared_dpll(intel_crtc);
6381
6382 domains = intel_crtc->enabled_power_domains;
6383 for_each_power_domain(domain, domains)
6384 intel_display_power_put(dev_priv, domain);
6385 intel_crtc->enabled_power_domains = 0;
6386
6387 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6388 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6389 }
6390
6391 /*
6392 * turn all crtc's off, but do not adjust state
6393 * This has to be paired with a call to intel_modeset_setup_hw_state.
6394 */
6395 int intel_display_suspend(struct drm_device *dev)
6396 {
6397 struct drm_mode_config *config = &dev->mode_config;
6398 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6399 struct drm_atomic_state *state;
6400 struct drm_crtc *crtc;
6401 unsigned crtc_mask = 0;
6402 int ret = 0;
6403
6404 if (WARN_ON(!ctx))
6405 return 0;
6406
6407 lockdep_assert_held(&ctx->ww_ctx);
6408 state = drm_atomic_state_alloc(dev);
6409 if (WARN_ON(!state))
6410 return -ENOMEM;
6411
6412 state->acquire_ctx = ctx;
6413 state->allow_modeset = true;
6414
6415 for_each_crtc(dev, crtc) {
6416 struct drm_crtc_state *crtc_state =
6417 drm_atomic_get_crtc_state(state, crtc);
6418
6419 ret = PTR_ERR_OR_ZERO(crtc_state);
6420 if (ret)
6421 goto free;
6422
6423 if (!crtc_state->active)
6424 continue;
6425
6426 crtc_state->active = false;
6427 crtc_mask |= 1 << drm_crtc_index(crtc);
6428 }
6429
6430 if (crtc_mask) {
6431 ret = drm_atomic_commit(state);
6432
6433 if (!ret) {
6434 for_each_crtc(dev, crtc)
6435 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6436 crtc->state->active = true;
6437
6438 return ret;
6439 }
6440 }
6441
6442 free:
6443 if (ret)
6444 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6445 drm_atomic_state_free(state);
6446 return ret;
6447 }
6448
6449 void intel_encoder_destroy(struct drm_encoder *encoder)
6450 {
6451 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6452
6453 drm_encoder_cleanup(encoder);
6454 kfree(intel_encoder);
6455 }
6456
6457 /* Cross check the actual hw state with our own modeset state tracking (and it's
6458 * internal consistency). */
6459 static void intel_connector_check_state(struct intel_connector *connector)
6460 {
6461 struct drm_crtc *crtc = connector->base.state->crtc;
6462
6463 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6464 connector->base.base.id,
6465 connector->base.name);
6466
6467 if (connector->get_hw_state(connector)) {
6468 struct intel_encoder *encoder = connector->encoder;
6469 struct drm_connector_state *conn_state = connector->base.state;
6470
6471 I915_STATE_WARN(!crtc,
6472 "connector enabled without attached crtc\n");
6473
6474 if (!crtc)
6475 return;
6476
6477 I915_STATE_WARN(!crtc->state->active,
6478 "connector is active, but attached crtc isn't\n");
6479
6480 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6481 return;
6482
6483 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6484 "atomic encoder doesn't match attached encoder\n");
6485
6486 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6487 "attached encoder crtc differs from connector crtc\n");
6488 } else {
6489 I915_STATE_WARN(crtc && crtc->state->active,
6490 "attached crtc is active, but connector isn't\n");
6491 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6492 "best encoder set without crtc!\n");
6493 }
6494 }
6495
6496 int intel_connector_init(struct intel_connector *connector)
6497 {
6498 drm_atomic_helper_connector_reset(&connector->base);
6499
6500 if (!connector->base.state)
6501 return -ENOMEM;
6502
6503 return 0;
6504 }
6505
6506 struct intel_connector *intel_connector_alloc(void)
6507 {
6508 struct intel_connector *connector;
6509
6510 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6511 if (!connector)
6512 return NULL;
6513
6514 if (intel_connector_init(connector) < 0) {
6515 kfree(connector);
6516 return NULL;
6517 }
6518
6519 return connector;
6520 }
6521
6522 /* Simple connector->get_hw_state implementation for encoders that support only
6523 * one connector and no cloning and hence the encoder state determines the state
6524 * of the connector. */
6525 bool intel_connector_get_hw_state(struct intel_connector *connector)
6526 {
6527 enum pipe pipe = 0;
6528 struct intel_encoder *encoder = connector->encoder;
6529
6530 return encoder->get_hw_state(encoder, &pipe);
6531 }
6532
6533 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6534 {
6535 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6536 return crtc_state->fdi_lanes;
6537
6538 return 0;
6539 }
6540
6541 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6542 struct intel_crtc_state *pipe_config)
6543 {
6544 struct drm_atomic_state *state = pipe_config->base.state;
6545 struct intel_crtc *other_crtc;
6546 struct intel_crtc_state *other_crtc_state;
6547
6548 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6549 pipe_name(pipe), pipe_config->fdi_lanes);
6550 if (pipe_config->fdi_lanes > 4) {
6551 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6552 pipe_name(pipe), pipe_config->fdi_lanes);
6553 return -EINVAL;
6554 }
6555
6556 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6557 if (pipe_config->fdi_lanes > 2) {
6558 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6559 pipe_config->fdi_lanes);
6560 return -EINVAL;
6561 } else {
6562 return 0;
6563 }
6564 }
6565
6566 if (INTEL_INFO(dev)->num_pipes == 2)
6567 return 0;
6568
6569 /* Ivybridge 3 pipe is really complicated */
6570 switch (pipe) {
6571 case PIPE_A:
6572 return 0;
6573 case PIPE_B:
6574 if (pipe_config->fdi_lanes <= 2)
6575 return 0;
6576
6577 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6578 other_crtc_state =
6579 intel_atomic_get_crtc_state(state, other_crtc);
6580 if (IS_ERR(other_crtc_state))
6581 return PTR_ERR(other_crtc_state);
6582
6583 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6584 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6585 pipe_name(pipe), pipe_config->fdi_lanes);
6586 return -EINVAL;
6587 }
6588 return 0;
6589 case PIPE_C:
6590 if (pipe_config->fdi_lanes > 2) {
6591 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6592 pipe_name(pipe), pipe_config->fdi_lanes);
6593 return -EINVAL;
6594 }
6595
6596 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6597 other_crtc_state =
6598 intel_atomic_get_crtc_state(state, other_crtc);
6599 if (IS_ERR(other_crtc_state))
6600 return PTR_ERR(other_crtc_state);
6601
6602 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6603 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6604 return -EINVAL;
6605 }
6606 return 0;
6607 default:
6608 BUG();
6609 }
6610 }
6611
6612 #define RETRY 1
6613 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6614 struct intel_crtc_state *pipe_config)
6615 {
6616 struct drm_device *dev = intel_crtc->base.dev;
6617 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6618 int lane, link_bw, fdi_dotclock, ret;
6619 bool needs_recompute = false;
6620
6621 retry:
6622 /* FDI is a binary signal running at ~2.7GHz, encoding
6623 * each output octet as 10 bits. The actual frequency
6624 * is stored as a divider into a 100MHz clock, and the
6625 * mode pixel clock is stored in units of 1KHz.
6626 * Hence the bw of each lane in terms of the mode signal
6627 * is:
6628 */
6629 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6630
6631 fdi_dotclock = adjusted_mode->crtc_clock;
6632
6633 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6634 pipe_config->pipe_bpp);
6635
6636 pipe_config->fdi_lanes = lane;
6637
6638 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6639 link_bw, &pipe_config->fdi_m_n);
6640
6641 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6642 intel_crtc->pipe, pipe_config);
6643 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6644 pipe_config->pipe_bpp -= 2*3;
6645 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6646 pipe_config->pipe_bpp);
6647 needs_recompute = true;
6648 pipe_config->bw_constrained = true;
6649
6650 goto retry;
6651 }
6652
6653 if (needs_recompute)
6654 return RETRY;
6655
6656 return ret;
6657 }
6658
6659 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6660 struct intel_crtc_state *pipe_config)
6661 {
6662 if (pipe_config->pipe_bpp > 24)
6663 return false;
6664
6665 /* HSW can handle pixel rate up to cdclk? */
6666 if (IS_HASWELL(dev_priv->dev))
6667 return true;
6668
6669 /*
6670 * We compare against max which means we must take
6671 * the increased cdclk requirement into account when
6672 * calculating the new cdclk.
6673 *
6674 * Should measure whether using a lower cdclk w/o IPS
6675 */
6676 return ilk_pipe_pixel_rate(pipe_config) <=
6677 dev_priv->max_cdclk_freq * 95 / 100;
6678 }
6679
6680 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6681 struct intel_crtc_state *pipe_config)
6682 {
6683 struct drm_device *dev = crtc->base.dev;
6684 struct drm_i915_private *dev_priv = dev->dev_private;
6685
6686 pipe_config->ips_enabled = i915.enable_ips &&
6687 hsw_crtc_supports_ips(crtc) &&
6688 pipe_config_supports_ips(dev_priv, pipe_config);
6689 }
6690
6691 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6692 {
6693 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6694
6695 /* GDG double wide on either pipe, otherwise pipe A only */
6696 return INTEL_INFO(dev_priv)->gen < 4 &&
6697 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6698 }
6699
6700 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6701 struct intel_crtc_state *pipe_config)
6702 {
6703 struct drm_device *dev = crtc->base.dev;
6704 struct drm_i915_private *dev_priv = dev->dev_private;
6705 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6706
6707 /* FIXME should check pixel clock limits on all platforms */
6708 if (INTEL_INFO(dev)->gen < 4) {
6709 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6710
6711 /*
6712 * Enable double wide mode when the dot clock
6713 * is > 90% of the (display) core speed.
6714 */
6715 if (intel_crtc_supports_double_wide(crtc) &&
6716 adjusted_mode->crtc_clock > clock_limit) {
6717 clock_limit *= 2;
6718 pipe_config->double_wide = true;
6719 }
6720
6721 if (adjusted_mode->crtc_clock > clock_limit) {
6722 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6723 adjusted_mode->crtc_clock, clock_limit,
6724 yesno(pipe_config->double_wide));
6725 return -EINVAL;
6726 }
6727 }
6728
6729 /*
6730 * Pipe horizontal size must be even in:
6731 * - DVO ganged mode
6732 * - LVDS dual channel mode
6733 * - Double wide pipe
6734 */
6735 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6736 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6737 pipe_config->pipe_src_w &= ~1;
6738
6739 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6740 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6741 */
6742 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6743 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6744 return -EINVAL;
6745
6746 if (HAS_IPS(dev))
6747 hsw_compute_ips_config(crtc, pipe_config);
6748
6749 if (pipe_config->has_pch_encoder)
6750 return ironlake_fdi_compute_config(crtc, pipe_config);
6751
6752 return 0;
6753 }
6754
6755 static int skylake_get_display_clock_speed(struct drm_device *dev)
6756 {
6757 struct drm_i915_private *dev_priv = to_i915(dev);
6758 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6759 uint32_t cdctl = I915_READ(CDCLK_CTL);
6760 uint32_t linkrate;
6761
6762 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6763 return 24000; /* 24MHz is the cd freq with NSSC ref */
6764
6765 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6766 return 540000;
6767
6768 linkrate = (I915_READ(DPLL_CTRL1) &
6769 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6770
6771 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6772 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6773 /* vco 8640 */
6774 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6775 case CDCLK_FREQ_450_432:
6776 return 432000;
6777 case CDCLK_FREQ_337_308:
6778 return 308570;
6779 case CDCLK_FREQ_675_617:
6780 return 617140;
6781 default:
6782 WARN(1, "Unknown cd freq selection\n");
6783 }
6784 } else {
6785 /* vco 8100 */
6786 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6787 case CDCLK_FREQ_450_432:
6788 return 450000;
6789 case CDCLK_FREQ_337_308:
6790 return 337500;
6791 case CDCLK_FREQ_675_617:
6792 return 675000;
6793 default:
6794 WARN(1, "Unknown cd freq selection\n");
6795 }
6796 }
6797
6798 /* error case, do as if DPLL0 isn't enabled */
6799 return 24000;
6800 }
6801
6802 static int broxton_get_display_clock_speed(struct drm_device *dev)
6803 {
6804 struct drm_i915_private *dev_priv = to_i915(dev);
6805 uint32_t cdctl = I915_READ(CDCLK_CTL);
6806 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6807 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6808 int cdclk;
6809
6810 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6811 return 19200;
6812
6813 cdclk = 19200 * pll_ratio / 2;
6814
6815 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6816 case BXT_CDCLK_CD2X_DIV_SEL_1:
6817 return cdclk; /* 576MHz or 624MHz */
6818 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6819 return cdclk * 2 / 3; /* 384MHz */
6820 case BXT_CDCLK_CD2X_DIV_SEL_2:
6821 return cdclk / 2; /* 288MHz */
6822 case BXT_CDCLK_CD2X_DIV_SEL_4:
6823 return cdclk / 4; /* 144MHz */
6824 }
6825
6826 /* error case, do as if DE PLL isn't enabled */
6827 return 19200;
6828 }
6829
6830 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6831 {
6832 struct drm_i915_private *dev_priv = dev->dev_private;
6833 uint32_t lcpll = I915_READ(LCPLL_CTL);
6834 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6835
6836 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6837 return 800000;
6838 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6839 return 450000;
6840 else if (freq == LCPLL_CLK_FREQ_450)
6841 return 450000;
6842 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6843 return 540000;
6844 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6845 return 337500;
6846 else
6847 return 675000;
6848 }
6849
6850 static int haswell_get_display_clock_speed(struct drm_device *dev)
6851 {
6852 struct drm_i915_private *dev_priv = dev->dev_private;
6853 uint32_t lcpll = I915_READ(LCPLL_CTL);
6854 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6855
6856 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6857 return 800000;
6858 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6859 return 450000;
6860 else if (freq == LCPLL_CLK_FREQ_450)
6861 return 450000;
6862 else if (IS_HSW_ULT(dev))
6863 return 337500;
6864 else
6865 return 540000;
6866 }
6867
6868 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6869 {
6870 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6871 CCK_DISPLAY_CLOCK_CONTROL);
6872 }
6873
6874 static int ilk_get_display_clock_speed(struct drm_device *dev)
6875 {
6876 return 450000;
6877 }
6878
6879 static int i945_get_display_clock_speed(struct drm_device *dev)
6880 {
6881 return 400000;
6882 }
6883
6884 static int i915_get_display_clock_speed(struct drm_device *dev)
6885 {
6886 return 333333;
6887 }
6888
6889 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6890 {
6891 return 200000;
6892 }
6893
6894 static int pnv_get_display_clock_speed(struct drm_device *dev)
6895 {
6896 u16 gcfgc = 0;
6897
6898 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6899
6900 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6901 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6902 return 266667;
6903 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6904 return 333333;
6905 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6906 return 444444;
6907 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6908 return 200000;
6909 default:
6910 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6911 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6912 return 133333;
6913 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6914 return 166667;
6915 }
6916 }
6917
6918 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6919 {
6920 u16 gcfgc = 0;
6921
6922 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6923
6924 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6925 return 133333;
6926 else {
6927 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6928 case GC_DISPLAY_CLOCK_333_MHZ:
6929 return 333333;
6930 default:
6931 case GC_DISPLAY_CLOCK_190_200_MHZ:
6932 return 190000;
6933 }
6934 }
6935 }
6936
6937 static int i865_get_display_clock_speed(struct drm_device *dev)
6938 {
6939 return 266667;
6940 }
6941
6942 static int i85x_get_display_clock_speed(struct drm_device *dev)
6943 {
6944 u16 hpllcc = 0;
6945
6946 /*
6947 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6948 * encoding is different :(
6949 * FIXME is this the right way to detect 852GM/852GMV?
6950 */
6951 if (dev->pdev->revision == 0x1)
6952 return 133333;
6953
6954 pci_bus_read_config_word(dev->pdev->bus,
6955 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6956
6957 /* Assume that the hardware is in the high speed state. This
6958 * should be the default.
6959 */
6960 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6961 case GC_CLOCK_133_200:
6962 case GC_CLOCK_133_200_2:
6963 case GC_CLOCK_100_200:
6964 return 200000;
6965 case GC_CLOCK_166_250:
6966 return 250000;
6967 case GC_CLOCK_100_133:
6968 return 133333;
6969 case GC_CLOCK_133_266:
6970 case GC_CLOCK_133_266_2:
6971 case GC_CLOCK_166_266:
6972 return 266667;
6973 }
6974
6975 /* Shouldn't happen */
6976 return 0;
6977 }
6978
6979 static int i830_get_display_clock_speed(struct drm_device *dev)
6980 {
6981 return 133333;
6982 }
6983
6984 static unsigned int intel_hpll_vco(struct drm_device *dev)
6985 {
6986 struct drm_i915_private *dev_priv = dev->dev_private;
6987 static const unsigned int blb_vco[8] = {
6988 [0] = 3200000,
6989 [1] = 4000000,
6990 [2] = 5333333,
6991 [3] = 4800000,
6992 [4] = 6400000,
6993 };
6994 static const unsigned int pnv_vco[8] = {
6995 [0] = 3200000,
6996 [1] = 4000000,
6997 [2] = 5333333,
6998 [3] = 4800000,
6999 [4] = 2666667,
7000 };
7001 static const unsigned int cl_vco[8] = {
7002 [0] = 3200000,
7003 [1] = 4000000,
7004 [2] = 5333333,
7005 [3] = 6400000,
7006 [4] = 3333333,
7007 [5] = 3566667,
7008 [6] = 4266667,
7009 };
7010 static const unsigned int elk_vco[8] = {
7011 [0] = 3200000,
7012 [1] = 4000000,
7013 [2] = 5333333,
7014 [3] = 4800000,
7015 };
7016 static const unsigned int ctg_vco[8] = {
7017 [0] = 3200000,
7018 [1] = 4000000,
7019 [2] = 5333333,
7020 [3] = 6400000,
7021 [4] = 2666667,
7022 [5] = 4266667,
7023 };
7024 const unsigned int *vco_table;
7025 unsigned int vco;
7026 uint8_t tmp = 0;
7027
7028 /* FIXME other chipsets? */
7029 if (IS_GM45(dev))
7030 vco_table = ctg_vco;
7031 else if (IS_G4X(dev))
7032 vco_table = elk_vco;
7033 else if (IS_CRESTLINE(dev))
7034 vco_table = cl_vco;
7035 else if (IS_PINEVIEW(dev))
7036 vco_table = pnv_vco;
7037 else if (IS_G33(dev))
7038 vco_table = blb_vco;
7039 else
7040 return 0;
7041
7042 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7043
7044 vco = vco_table[tmp & 0x7];
7045 if (vco == 0)
7046 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7047 else
7048 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7049
7050 return vco;
7051 }
7052
7053 static int gm45_get_display_clock_speed(struct drm_device *dev)
7054 {
7055 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7056 uint16_t tmp = 0;
7057
7058 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7059
7060 cdclk_sel = (tmp >> 12) & 0x1;
7061
7062 switch (vco) {
7063 case 2666667:
7064 case 4000000:
7065 case 5333333:
7066 return cdclk_sel ? 333333 : 222222;
7067 case 3200000:
7068 return cdclk_sel ? 320000 : 228571;
7069 default:
7070 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7071 return 222222;
7072 }
7073 }
7074
7075 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7076 {
7077 static const uint8_t div_3200[] = { 16, 10, 8 };
7078 static const uint8_t div_4000[] = { 20, 12, 10 };
7079 static const uint8_t div_5333[] = { 24, 16, 14 };
7080 const uint8_t *div_table;
7081 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7082 uint16_t tmp = 0;
7083
7084 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7085
7086 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7087
7088 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7089 goto fail;
7090
7091 switch (vco) {
7092 case 3200000:
7093 div_table = div_3200;
7094 break;
7095 case 4000000:
7096 div_table = div_4000;
7097 break;
7098 case 5333333:
7099 div_table = div_5333;
7100 break;
7101 default:
7102 goto fail;
7103 }
7104
7105 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7106
7107 fail:
7108 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7109 return 200000;
7110 }
7111
7112 static int g33_get_display_clock_speed(struct drm_device *dev)
7113 {
7114 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7115 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7116 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7117 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7118 const uint8_t *div_table;
7119 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7120 uint16_t tmp = 0;
7121
7122 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7123
7124 cdclk_sel = (tmp >> 4) & 0x7;
7125
7126 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7127 goto fail;
7128
7129 switch (vco) {
7130 case 3200000:
7131 div_table = div_3200;
7132 break;
7133 case 4000000:
7134 div_table = div_4000;
7135 break;
7136 case 4800000:
7137 div_table = div_4800;
7138 break;
7139 case 5333333:
7140 div_table = div_5333;
7141 break;
7142 default:
7143 goto fail;
7144 }
7145
7146 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7147
7148 fail:
7149 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7150 return 190476;
7151 }
7152
7153 static void
7154 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7155 {
7156 while (*num > DATA_LINK_M_N_MASK ||
7157 *den > DATA_LINK_M_N_MASK) {
7158 *num >>= 1;
7159 *den >>= 1;
7160 }
7161 }
7162
7163 static void compute_m_n(unsigned int m, unsigned int n,
7164 uint32_t *ret_m, uint32_t *ret_n)
7165 {
7166 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7167 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7168 intel_reduce_m_n_ratio(ret_m, ret_n);
7169 }
7170
7171 void
7172 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7173 int pixel_clock, int link_clock,
7174 struct intel_link_m_n *m_n)
7175 {
7176 m_n->tu = 64;
7177
7178 compute_m_n(bits_per_pixel * pixel_clock,
7179 link_clock * nlanes * 8,
7180 &m_n->gmch_m, &m_n->gmch_n);
7181
7182 compute_m_n(pixel_clock, link_clock,
7183 &m_n->link_m, &m_n->link_n);
7184 }
7185
7186 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7187 {
7188 if (i915.panel_use_ssc >= 0)
7189 return i915.panel_use_ssc != 0;
7190 return dev_priv->vbt.lvds_use_ssc
7191 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7192 }
7193
7194 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7195 int num_connectors)
7196 {
7197 struct drm_device *dev = crtc_state->base.crtc->dev;
7198 struct drm_i915_private *dev_priv = dev->dev_private;
7199 int refclk;
7200
7201 WARN_ON(!crtc_state->base.state);
7202
7203 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7204 refclk = 100000;
7205 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7206 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7207 refclk = dev_priv->vbt.lvds_ssc_freq;
7208 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7209 } else if (!IS_GEN2(dev)) {
7210 refclk = 96000;
7211 } else {
7212 refclk = 48000;
7213 }
7214
7215 return refclk;
7216 }
7217
7218 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7219 {
7220 return (1 << dpll->n) << 16 | dpll->m2;
7221 }
7222
7223 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7224 {
7225 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7226 }
7227
7228 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7229 struct intel_crtc_state *crtc_state,
7230 intel_clock_t *reduced_clock)
7231 {
7232 struct drm_device *dev = crtc->base.dev;
7233 u32 fp, fp2 = 0;
7234
7235 if (IS_PINEVIEW(dev)) {
7236 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7237 if (reduced_clock)
7238 fp2 = pnv_dpll_compute_fp(reduced_clock);
7239 } else {
7240 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7241 if (reduced_clock)
7242 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7243 }
7244
7245 crtc_state->dpll_hw_state.fp0 = fp;
7246
7247 crtc->lowfreq_avail = false;
7248 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7249 reduced_clock) {
7250 crtc_state->dpll_hw_state.fp1 = fp2;
7251 crtc->lowfreq_avail = true;
7252 } else {
7253 crtc_state->dpll_hw_state.fp1 = fp;
7254 }
7255 }
7256
7257 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7258 pipe)
7259 {
7260 u32 reg_val;
7261
7262 /*
7263 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7264 * and set it to a reasonable value instead.
7265 */
7266 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7267 reg_val &= 0xffffff00;
7268 reg_val |= 0x00000030;
7269 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7270
7271 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7272 reg_val &= 0x8cffffff;
7273 reg_val = 0x8c000000;
7274 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7275
7276 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7277 reg_val &= 0xffffff00;
7278 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7279
7280 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7281 reg_val &= 0x00ffffff;
7282 reg_val |= 0xb0000000;
7283 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7284 }
7285
7286 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7287 struct intel_link_m_n *m_n)
7288 {
7289 struct drm_device *dev = crtc->base.dev;
7290 struct drm_i915_private *dev_priv = dev->dev_private;
7291 int pipe = crtc->pipe;
7292
7293 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7294 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7295 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7296 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7297 }
7298
7299 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7300 struct intel_link_m_n *m_n,
7301 struct intel_link_m_n *m2_n2)
7302 {
7303 struct drm_device *dev = crtc->base.dev;
7304 struct drm_i915_private *dev_priv = dev->dev_private;
7305 int pipe = crtc->pipe;
7306 enum transcoder transcoder = crtc->config->cpu_transcoder;
7307
7308 if (INTEL_INFO(dev)->gen >= 5) {
7309 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7310 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7311 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7312 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7313 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7314 * for gen < 8) and if DRRS is supported (to make sure the
7315 * registers are not unnecessarily accessed).
7316 */
7317 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7318 crtc->config->has_drrs) {
7319 I915_WRITE(PIPE_DATA_M2(transcoder),
7320 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7321 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7322 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7323 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7324 }
7325 } else {
7326 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7327 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7328 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7329 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7330 }
7331 }
7332
7333 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7334 {
7335 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7336
7337 if (m_n == M1_N1) {
7338 dp_m_n = &crtc->config->dp_m_n;
7339 dp_m2_n2 = &crtc->config->dp_m2_n2;
7340 } else if (m_n == M2_N2) {
7341
7342 /*
7343 * M2_N2 registers are not supported. Hence m2_n2 divider value
7344 * needs to be programmed into M1_N1.
7345 */
7346 dp_m_n = &crtc->config->dp_m2_n2;
7347 } else {
7348 DRM_ERROR("Unsupported divider value\n");
7349 return;
7350 }
7351
7352 if (crtc->config->has_pch_encoder)
7353 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7354 else
7355 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7356 }
7357
7358 static void vlv_compute_dpll(struct intel_crtc *crtc,
7359 struct intel_crtc_state *pipe_config)
7360 {
7361 u32 dpll, dpll_md;
7362
7363 /*
7364 * Enable DPIO clock input. We should never disable the reference
7365 * clock for pipe B, since VGA hotplug / manual detection depends
7366 * on it.
7367 */
7368 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7369 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7370 /* We should never disable this, set it here for state tracking */
7371 if (crtc->pipe == PIPE_B)
7372 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7373 dpll |= DPLL_VCO_ENABLE;
7374 pipe_config->dpll_hw_state.dpll = dpll;
7375
7376 dpll_md = (pipe_config->pixel_multiplier - 1)
7377 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7378 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7379 }
7380
7381 static void vlv_prepare_pll(struct intel_crtc *crtc,
7382 const struct intel_crtc_state *pipe_config)
7383 {
7384 struct drm_device *dev = crtc->base.dev;
7385 struct drm_i915_private *dev_priv = dev->dev_private;
7386 int pipe = crtc->pipe;
7387 u32 mdiv;
7388 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7389 u32 coreclk, reg_val;
7390
7391 mutex_lock(&dev_priv->sb_lock);
7392
7393 bestn = pipe_config->dpll.n;
7394 bestm1 = pipe_config->dpll.m1;
7395 bestm2 = pipe_config->dpll.m2;
7396 bestp1 = pipe_config->dpll.p1;
7397 bestp2 = pipe_config->dpll.p2;
7398
7399 /* See eDP HDMI DPIO driver vbios notes doc */
7400
7401 /* PLL B needs special handling */
7402 if (pipe == PIPE_B)
7403 vlv_pllb_recal_opamp(dev_priv, pipe);
7404
7405 /* Set up Tx target for periodic Rcomp update */
7406 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7407
7408 /* Disable target IRef on PLL */
7409 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7410 reg_val &= 0x00ffffff;
7411 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7412
7413 /* Disable fast lock */
7414 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7415
7416 /* Set idtafcrecal before PLL is enabled */
7417 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7418 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7419 mdiv |= ((bestn << DPIO_N_SHIFT));
7420 mdiv |= (1 << DPIO_K_SHIFT);
7421
7422 /*
7423 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7424 * but we don't support that).
7425 * Note: don't use the DAC post divider as it seems unstable.
7426 */
7427 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7428 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7429
7430 mdiv |= DPIO_ENABLE_CALIBRATION;
7431 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7432
7433 /* Set HBR and RBR LPF coefficients */
7434 if (pipe_config->port_clock == 162000 ||
7435 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7436 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7437 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7438 0x009f0003);
7439 else
7440 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7441 0x00d0000f);
7442
7443 if (pipe_config->has_dp_encoder) {
7444 /* Use SSC source */
7445 if (pipe == PIPE_A)
7446 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7447 0x0df40000);
7448 else
7449 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7450 0x0df70000);
7451 } else { /* HDMI or VGA */
7452 /* Use bend source */
7453 if (pipe == PIPE_A)
7454 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7455 0x0df70000);
7456 else
7457 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7458 0x0df40000);
7459 }
7460
7461 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7462 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7463 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7464 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7465 coreclk |= 0x01000000;
7466 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7467
7468 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7469 mutex_unlock(&dev_priv->sb_lock);
7470 }
7471
7472 static void chv_compute_dpll(struct intel_crtc *crtc,
7473 struct intel_crtc_state *pipe_config)
7474 {
7475 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7476 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7477 DPLL_VCO_ENABLE;
7478 if (crtc->pipe != PIPE_A)
7479 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7480
7481 pipe_config->dpll_hw_state.dpll_md =
7482 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7483 }
7484
7485 static void chv_prepare_pll(struct intel_crtc *crtc,
7486 const struct intel_crtc_state *pipe_config)
7487 {
7488 struct drm_device *dev = crtc->base.dev;
7489 struct drm_i915_private *dev_priv = dev->dev_private;
7490 int pipe = crtc->pipe;
7491 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7492 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7493 u32 loopfilter, tribuf_calcntr;
7494 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7495 u32 dpio_val;
7496 int vco;
7497
7498 bestn = pipe_config->dpll.n;
7499 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7500 bestm1 = pipe_config->dpll.m1;
7501 bestm2 = pipe_config->dpll.m2 >> 22;
7502 bestp1 = pipe_config->dpll.p1;
7503 bestp2 = pipe_config->dpll.p2;
7504 vco = pipe_config->dpll.vco;
7505 dpio_val = 0;
7506 loopfilter = 0;
7507
7508 /*
7509 * Enable Refclk and SSC
7510 */
7511 I915_WRITE(dpll_reg,
7512 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7513
7514 mutex_lock(&dev_priv->sb_lock);
7515
7516 /* p1 and p2 divider */
7517 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7518 5 << DPIO_CHV_S1_DIV_SHIFT |
7519 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7520 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7521 1 << DPIO_CHV_K_DIV_SHIFT);
7522
7523 /* Feedback post-divider - m2 */
7524 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7525
7526 /* Feedback refclk divider - n and m1 */
7527 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7528 DPIO_CHV_M1_DIV_BY_2 |
7529 1 << DPIO_CHV_N_DIV_SHIFT);
7530
7531 /* M2 fraction division */
7532 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7533
7534 /* M2 fraction division enable */
7535 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7536 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7537 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7538 if (bestm2_frac)
7539 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7540 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7541
7542 /* Program digital lock detect threshold */
7543 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7544 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7545 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7546 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7547 if (!bestm2_frac)
7548 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7549 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7550
7551 /* Loop filter */
7552 if (vco == 5400000) {
7553 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7554 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7555 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7556 tribuf_calcntr = 0x9;
7557 } else if (vco <= 6200000) {
7558 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7559 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7560 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7561 tribuf_calcntr = 0x9;
7562 } else if (vco <= 6480000) {
7563 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7564 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7565 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7566 tribuf_calcntr = 0x8;
7567 } else {
7568 /* Not supported. Apply the same limits as in the max case */
7569 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7570 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7571 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7572 tribuf_calcntr = 0;
7573 }
7574 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7575
7576 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7577 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7578 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7579 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7580
7581 /* AFC Recal */
7582 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7583 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7584 DPIO_AFC_RECAL);
7585
7586 mutex_unlock(&dev_priv->sb_lock);
7587 }
7588
7589 /**
7590 * vlv_force_pll_on - forcibly enable just the PLL
7591 * @dev_priv: i915 private structure
7592 * @pipe: pipe PLL to enable
7593 * @dpll: PLL configuration
7594 *
7595 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7596 * in cases where we need the PLL enabled even when @pipe is not going to
7597 * be enabled.
7598 */
7599 int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7600 const struct dpll *dpll)
7601 {
7602 struct intel_crtc *crtc =
7603 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7604 struct intel_crtc_state *pipe_config;
7605
7606 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7607 if (!pipe_config)
7608 return -ENOMEM;
7609
7610 pipe_config->base.crtc = &crtc->base;
7611 pipe_config->pixel_multiplier = 1;
7612 pipe_config->dpll = *dpll;
7613
7614 if (IS_CHERRYVIEW(dev)) {
7615 chv_compute_dpll(crtc, pipe_config);
7616 chv_prepare_pll(crtc, pipe_config);
7617 chv_enable_pll(crtc, pipe_config);
7618 } else {
7619 vlv_compute_dpll(crtc, pipe_config);
7620 vlv_prepare_pll(crtc, pipe_config);
7621 vlv_enable_pll(crtc, pipe_config);
7622 }
7623
7624 kfree(pipe_config);
7625
7626 return 0;
7627 }
7628
7629 /**
7630 * vlv_force_pll_off - forcibly disable just the PLL
7631 * @dev_priv: i915 private structure
7632 * @pipe: pipe PLL to disable
7633 *
7634 * Disable the PLL for @pipe. To be used in cases where we need
7635 * the PLL enabled even when @pipe is not going to be enabled.
7636 */
7637 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7638 {
7639 if (IS_CHERRYVIEW(dev))
7640 chv_disable_pll(to_i915(dev), pipe);
7641 else
7642 vlv_disable_pll(to_i915(dev), pipe);
7643 }
7644
7645 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7646 struct intel_crtc_state *crtc_state,
7647 intel_clock_t *reduced_clock,
7648 int num_connectors)
7649 {
7650 struct drm_device *dev = crtc->base.dev;
7651 struct drm_i915_private *dev_priv = dev->dev_private;
7652 u32 dpll;
7653 bool is_sdvo;
7654 struct dpll *clock = &crtc_state->dpll;
7655
7656 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7657
7658 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7659 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7660
7661 dpll = DPLL_VGA_MODE_DIS;
7662
7663 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7664 dpll |= DPLLB_MODE_LVDS;
7665 else
7666 dpll |= DPLLB_MODE_DAC_SERIAL;
7667
7668 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7669 dpll |= (crtc_state->pixel_multiplier - 1)
7670 << SDVO_MULTIPLIER_SHIFT_HIRES;
7671 }
7672
7673 if (is_sdvo)
7674 dpll |= DPLL_SDVO_HIGH_SPEED;
7675
7676 if (crtc_state->has_dp_encoder)
7677 dpll |= DPLL_SDVO_HIGH_SPEED;
7678
7679 /* compute bitmask from p1 value */
7680 if (IS_PINEVIEW(dev))
7681 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7682 else {
7683 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7684 if (IS_G4X(dev) && reduced_clock)
7685 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7686 }
7687 switch (clock->p2) {
7688 case 5:
7689 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7690 break;
7691 case 7:
7692 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7693 break;
7694 case 10:
7695 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7696 break;
7697 case 14:
7698 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7699 break;
7700 }
7701 if (INTEL_INFO(dev)->gen >= 4)
7702 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7703
7704 if (crtc_state->sdvo_tv_clock)
7705 dpll |= PLL_REF_INPUT_TVCLKINBC;
7706 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7707 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7708 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7709 else
7710 dpll |= PLL_REF_INPUT_DREFCLK;
7711
7712 dpll |= DPLL_VCO_ENABLE;
7713 crtc_state->dpll_hw_state.dpll = dpll;
7714
7715 if (INTEL_INFO(dev)->gen >= 4) {
7716 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7717 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7718 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7719 }
7720 }
7721
7722 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7723 struct intel_crtc_state *crtc_state,
7724 intel_clock_t *reduced_clock,
7725 int num_connectors)
7726 {
7727 struct drm_device *dev = crtc->base.dev;
7728 struct drm_i915_private *dev_priv = dev->dev_private;
7729 u32 dpll;
7730 struct dpll *clock = &crtc_state->dpll;
7731
7732 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7733
7734 dpll = DPLL_VGA_MODE_DIS;
7735
7736 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7737 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7738 } else {
7739 if (clock->p1 == 2)
7740 dpll |= PLL_P1_DIVIDE_BY_TWO;
7741 else
7742 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7743 if (clock->p2 == 4)
7744 dpll |= PLL_P2_DIVIDE_BY_4;
7745 }
7746
7747 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7748 dpll |= DPLL_DVO_2X_MODE;
7749
7750 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7751 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7752 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7753 else
7754 dpll |= PLL_REF_INPUT_DREFCLK;
7755
7756 dpll |= DPLL_VCO_ENABLE;
7757 crtc_state->dpll_hw_state.dpll = dpll;
7758 }
7759
7760 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7761 {
7762 struct drm_device *dev = intel_crtc->base.dev;
7763 struct drm_i915_private *dev_priv = dev->dev_private;
7764 enum pipe pipe = intel_crtc->pipe;
7765 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7766 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7767 uint32_t crtc_vtotal, crtc_vblank_end;
7768 int vsyncshift = 0;
7769
7770 /* We need to be careful not to changed the adjusted mode, for otherwise
7771 * the hw state checker will get angry at the mismatch. */
7772 crtc_vtotal = adjusted_mode->crtc_vtotal;
7773 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7774
7775 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7776 /* the chip adds 2 halflines automatically */
7777 crtc_vtotal -= 1;
7778 crtc_vblank_end -= 1;
7779
7780 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7781 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7782 else
7783 vsyncshift = adjusted_mode->crtc_hsync_start -
7784 adjusted_mode->crtc_htotal / 2;
7785 if (vsyncshift < 0)
7786 vsyncshift += adjusted_mode->crtc_htotal;
7787 }
7788
7789 if (INTEL_INFO(dev)->gen > 3)
7790 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7791
7792 I915_WRITE(HTOTAL(cpu_transcoder),
7793 (adjusted_mode->crtc_hdisplay - 1) |
7794 ((adjusted_mode->crtc_htotal - 1) << 16));
7795 I915_WRITE(HBLANK(cpu_transcoder),
7796 (adjusted_mode->crtc_hblank_start - 1) |
7797 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7798 I915_WRITE(HSYNC(cpu_transcoder),
7799 (adjusted_mode->crtc_hsync_start - 1) |
7800 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7801
7802 I915_WRITE(VTOTAL(cpu_transcoder),
7803 (adjusted_mode->crtc_vdisplay - 1) |
7804 ((crtc_vtotal - 1) << 16));
7805 I915_WRITE(VBLANK(cpu_transcoder),
7806 (adjusted_mode->crtc_vblank_start - 1) |
7807 ((crtc_vblank_end - 1) << 16));
7808 I915_WRITE(VSYNC(cpu_transcoder),
7809 (adjusted_mode->crtc_vsync_start - 1) |
7810 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7811
7812 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7813 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7814 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7815 * bits. */
7816 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7817 (pipe == PIPE_B || pipe == PIPE_C))
7818 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7819
7820 /* pipesrc controls the size that is scaled from, which should
7821 * always be the user's requested size.
7822 */
7823 I915_WRITE(PIPESRC(pipe),
7824 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7825 (intel_crtc->config->pipe_src_h - 1));
7826 }
7827
7828 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7829 struct intel_crtc_state *pipe_config)
7830 {
7831 struct drm_device *dev = crtc->base.dev;
7832 struct drm_i915_private *dev_priv = dev->dev_private;
7833 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7834 uint32_t tmp;
7835
7836 tmp = I915_READ(HTOTAL(cpu_transcoder));
7837 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7838 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7839 tmp = I915_READ(HBLANK(cpu_transcoder));
7840 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7841 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7842 tmp = I915_READ(HSYNC(cpu_transcoder));
7843 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7844 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7845
7846 tmp = I915_READ(VTOTAL(cpu_transcoder));
7847 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7848 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7849 tmp = I915_READ(VBLANK(cpu_transcoder));
7850 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7851 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7852 tmp = I915_READ(VSYNC(cpu_transcoder));
7853 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7854 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7855
7856 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7857 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7858 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7859 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7860 }
7861
7862 tmp = I915_READ(PIPESRC(crtc->pipe));
7863 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7864 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7865
7866 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7867 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7868 }
7869
7870 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7871 struct intel_crtc_state *pipe_config)
7872 {
7873 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7874 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7875 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7876 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7877
7878 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7879 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7880 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7881 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7882
7883 mode->flags = pipe_config->base.adjusted_mode.flags;
7884 mode->type = DRM_MODE_TYPE_DRIVER;
7885
7886 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7887 mode->flags |= pipe_config->base.adjusted_mode.flags;
7888
7889 mode->hsync = drm_mode_hsync(mode);
7890 mode->vrefresh = drm_mode_vrefresh(mode);
7891 drm_mode_set_name(mode);
7892 }
7893
7894 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7895 {
7896 struct drm_device *dev = intel_crtc->base.dev;
7897 struct drm_i915_private *dev_priv = dev->dev_private;
7898 uint32_t pipeconf;
7899
7900 pipeconf = 0;
7901
7902 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7903 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7904 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7905
7906 if (intel_crtc->config->double_wide)
7907 pipeconf |= PIPECONF_DOUBLE_WIDE;
7908
7909 /* only g4x and later have fancy bpc/dither controls */
7910 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7911 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7912 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7913 pipeconf |= PIPECONF_DITHER_EN |
7914 PIPECONF_DITHER_TYPE_SP;
7915
7916 switch (intel_crtc->config->pipe_bpp) {
7917 case 18:
7918 pipeconf |= PIPECONF_6BPC;
7919 break;
7920 case 24:
7921 pipeconf |= PIPECONF_8BPC;
7922 break;
7923 case 30:
7924 pipeconf |= PIPECONF_10BPC;
7925 break;
7926 default:
7927 /* Case prevented by intel_choose_pipe_bpp_dither. */
7928 BUG();
7929 }
7930 }
7931
7932 if (HAS_PIPE_CXSR(dev)) {
7933 if (intel_crtc->lowfreq_avail) {
7934 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7935 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7936 } else {
7937 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7938 }
7939 }
7940
7941 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7942 if (INTEL_INFO(dev)->gen < 4 ||
7943 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7944 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7945 else
7946 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7947 } else
7948 pipeconf |= PIPECONF_PROGRESSIVE;
7949
7950 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
7951 intel_crtc->config->limited_color_range)
7952 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7953
7954 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7955 POSTING_READ(PIPECONF(intel_crtc->pipe));
7956 }
7957
7958 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7959 struct intel_crtc_state *crtc_state)
7960 {
7961 struct drm_device *dev = crtc->base.dev;
7962 struct drm_i915_private *dev_priv = dev->dev_private;
7963 int refclk, num_connectors = 0;
7964 intel_clock_t clock;
7965 bool ok;
7966 const intel_limit_t *limit;
7967 struct drm_atomic_state *state = crtc_state->base.state;
7968 struct drm_connector *connector;
7969 struct drm_connector_state *connector_state;
7970 int i;
7971
7972 memset(&crtc_state->dpll_hw_state, 0,
7973 sizeof(crtc_state->dpll_hw_state));
7974
7975 if (crtc_state->has_dsi_encoder)
7976 return 0;
7977
7978 for_each_connector_in_state(state, connector, connector_state, i) {
7979 if (connector_state->crtc == &crtc->base)
7980 num_connectors++;
7981 }
7982
7983 if (!crtc_state->clock_set) {
7984 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7985
7986 /*
7987 * Returns a set of divisors for the desired target clock with
7988 * the given refclk, or FALSE. The returned values represent
7989 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7990 * 2) / p1 / p2.
7991 */
7992 limit = intel_limit(crtc_state, refclk);
7993 ok = dev_priv->display.find_dpll(limit, crtc_state,
7994 crtc_state->port_clock,
7995 refclk, NULL, &clock);
7996 if (!ok) {
7997 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7998 return -EINVAL;
7999 }
8000
8001 /* Compat-code for transition, will disappear. */
8002 crtc_state->dpll.n = clock.n;
8003 crtc_state->dpll.m1 = clock.m1;
8004 crtc_state->dpll.m2 = clock.m2;
8005 crtc_state->dpll.p1 = clock.p1;
8006 crtc_state->dpll.p2 = clock.p2;
8007 }
8008
8009 if (IS_GEN2(dev)) {
8010 i8xx_compute_dpll(crtc, crtc_state, NULL,
8011 num_connectors);
8012 } else if (IS_CHERRYVIEW(dev)) {
8013 chv_compute_dpll(crtc, crtc_state);
8014 } else if (IS_VALLEYVIEW(dev)) {
8015 vlv_compute_dpll(crtc, crtc_state);
8016 } else {
8017 i9xx_compute_dpll(crtc, crtc_state, NULL,
8018 num_connectors);
8019 }
8020
8021 return 0;
8022 }
8023
8024 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8025 struct intel_crtc_state *pipe_config)
8026 {
8027 struct drm_device *dev = crtc->base.dev;
8028 struct drm_i915_private *dev_priv = dev->dev_private;
8029 uint32_t tmp;
8030
8031 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8032 return;
8033
8034 tmp = I915_READ(PFIT_CONTROL);
8035 if (!(tmp & PFIT_ENABLE))
8036 return;
8037
8038 /* Check whether the pfit is attached to our pipe. */
8039 if (INTEL_INFO(dev)->gen < 4) {
8040 if (crtc->pipe != PIPE_B)
8041 return;
8042 } else {
8043 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8044 return;
8045 }
8046
8047 pipe_config->gmch_pfit.control = tmp;
8048 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8049 if (INTEL_INFO(dev)->gen < 5)
8050 pipe_config->gmch_pfit.lvds_border_bits =
8051 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8052 }
8053
8054 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8055 struct intel_crtc_state *pipe_config)
8056 {
8057 struct drm_device *dev = crtc->base.dev;
8058 struct drm_i915_private *dev_priv = dev->dev_private;
8059 int pipe = pipe_config->cpu_transcoder;
8060 intel_clock_t clock;
8061 u32 mdiv;
8062 int refclk = 100000;
8063
8064 /* In case of MIPI DPLL will not even be used */
8065 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8066 return;
8067
8068 mutex_lock(&dev_priv->sb_lock);
8069 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8070 mutex_unlock(&dev_priv->sb_lock);
8071
8072 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8073 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8074 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8075 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8076 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8077
8078 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8079 }
8080
8081 static void
8082 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8083 struct intel_initial_plane_config *plane_config)
8084 {
8085 struct drm_device *dev = crtc->base.dev;
8086 struct drm_i915_private *dev_priv = dev->dev_private;
8087 u32 val, base, offset;
8088 int pipe = crtc->pipe, plane = crtc->plane;
8089 int fourcc, pixel_format;
8090 unsigned int aligned_height;
8091 struct drm_framebuffer *fb;
8092 struct intel_framebuffer *intel_fb;
8093
8094 val = I915_READ(DSPCNTR(plane));
8095 if (!(val & DISPLAY_PLANE_ENABLE))
8096 return;
8097
8098 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8099 if (!intel_fb) {
8100 DRM_DEBUG_KMS("failed to alloc fb\n");
8101 return;
8102 }
8103
8104 fb = &intel_fb->base;
8105
8106 if (INTEL_INFO(dev)->gen >= 4) {
8107 if (val & DISPPLANE_TILED) {
8108 plane_config->tiling = I915_TILING_X;
8109 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8110 }
8111 }
8112
8113 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8114 fourcc = i9xx_format_to_fourcc(pixel_format);
8115 fb->pixel_format = fourcc;
8116 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8117
8118 if (INTEL_INFO(dev)->gen >= 4) {
8119 if (plane_config->tiling)
8120 offset = I915_READ(DSPTILEOFF(plane));
8121 else
8122 offset = I915_READ(DSPLINOFF(plane));
8123 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8124 } else {
8125 base = I915_READ(DSPADDR(plane));
8126 }
8127 plane_config->base = base;
8128
8129 val = I915_READ(PIPESRC(pipe));
8130 fb->width = ((val >> 16) & 0xfff) + 1;
8131 fb->height = ((val >> 0) & 0xfff) + 1;
8132
8133 val = I915_READ(DSPSTRIDE(pipe));
8134 fb->pitches[0] = val & 0xffffffc0;
8135
8136 aligned_height = intel_fb_align_height(dev, fb->height,
8137 fb->pixel_format,
8138 fb->modifier[0]);
8139
8140 plane_config->size = fb->pitches[0] * aligned_height;
8141
8142 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8143 pipe_name(pipe), plane, fb->width, fb->height,
8144 fb->bits_per_pixel, base, fb->pitches[0],
8145 plane_config->size);
8146
8147 plane_config->fb = intel_fb;
8148 }
8149
8150 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8151 struct intel_crtc_state *pipe_config)
8152 {
8153 struct drm_device *dev = crtc->base.dev;
8154 struct drm_i915_private *dev_priv = dev->dev_private;
8155 int pipe = pipe_config->cpu_transcoder;
8156 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8157 intel_clock_t clock;
8158 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8159 int refclk = 100000;
8160
8161 mutex_lock(&dev_priv->sb_lock);
8162 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8163 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8164 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8165 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8166 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8167 mutex_unlock(&dev_priv->sb_lock);
8168
8169 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8170 clock.m2 = (pll_dw0 & 0xff) << 22;
8171 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8172 clock.m2 |= pll_dw2 & 0x3fffff;
8173 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8174 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8175 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8176
8177 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8178 }
8179
8180 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8181 struct intel_crtc_state *pipe_config)
8182 {
8183 struct drm_device *dev = crtc->base.dev;
8184 struct drm_i915_private *dev_priv = dev->dev_private;
8185 uint32_t tmp;
8186
8187 if (!intel_display_power_is_enabled(dev_priv,
8188 POWER_DOMAIN_PIPE(crtc->pipe)))
8189 return false;
8190
8191 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8192 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8193
8194 tmp = I915_READ(PIPECONF(crtc->pipe));
8195 if (!(tmp & PIPECONF_ENABLE))
8196 return false;
8197
8198 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8199 switch (tmp & PIPECONF_BPC_MASK) {
8200 case PIPECONF_6BPC:
8201 pipe_config->pipe_bpp = 18;
8202 break;
8203 case PIPECONF_8BPC:
8204 pipe_config->pipe_bpp = 24;
8205 break;
8206 case PIPECONF_10BPC:
8207 pipe_config->pipe_bpp = 30;
8208 break;
8209 default:
8210 break;
8211 }
8212 }
8213
8214 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8215 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8216 pipe_config->limited_color_range = true;
8217
8218 if (INTEL_INFO(dev)->gen < 4)
8219 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8220
8221 intel_get_pipe_timings(crtc, pipe_config);
8222
8223 i9xx_get_pfit_config(crtc, pipe_config);
8224
8225 if (INTEL_INFO(dev)->gen >= 4) {
8226 tmp = I915_READ(DPLL_MD(crtc->pipe));
8227 pipe_config->pixel_multiplier =
8228 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8229 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8230 pipe_config->dpll_hw_state.dpll_md = tmp;
8231 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8232 tmp = I915_READ(DPLL(crtc->pipe));
8233 pipe_config->pixel_multiplier =
8234 ((tmp & SDVO_MULTIPLIER_MASK)
8235 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8236 } else {
8237 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8238 * port and will be fixed up in the encoder->get_config
8239 * function. */
8240 pipe_config->pixel_multiplier = 1;
8241 }
8242 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8243 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8244 /*
8245 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8246 * on 830. Filter it out here so that we don't
8247 * report errors due to that.
8248 */
8249 if (IS_I830(dev))
8250 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8251
8252 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8253 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8254 } else {
8255 /* Mask out read-only status bits. */
8256 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8257 DPLL_PORTC_READY_MASK |
8258 DPLL_PORTB_READY_MASK);
8259 }
8260
8261 if (IS_CHERRYVIEW(dev))
8262 chv_crtc_clock_get(crtc, pipe_config);
8263 else if (IS_VALLEYVIEW(dev))
8264 vlv_crtc_clock_get(crtc, pipe_config);
8265 else
8266 i9xx_crtc_clock_get(crtc, pipe_config);
8267
8268 /*
8269 * Normally the dotclock is filled in by the encoder .get_config()
8270 * but in case the pipe is enabled w/o any ports we need a sane
8271 * default.
8272 */
8273 pipe_config->base.adjusted_mode.crtc_clock =
8274 pipe_config->port_clock / pipe_config->pixel_multiplier;
8275
8276 return true;
8277 }
8278
8279 static void ironlake_init_pch_refclk(struct drm_device *dev)
8280 {
8281 struct drm_i915_private *dev_priv = dev->dev_private;
8282 struct intel_encoder *encoder;
8283 u32 val, final;
8284 bool has_lvds = false;
8285 bool has_cpu_edp = false;
8286 bool has_panel = false;
8287 bool has_ck505 = false;
8288 bool can_ssc = false;
8289
8290 /* We need to take the global config into account */
8291 for_each_intel_encoder(dev, encoder) {
8292 switch (encoder->type) {
8293 case INTEL_OUTPUT_LVDS:
8294 has_panel = true;
8295 has_lvds = true;
8296 break;
8297 case INTEL_OUTPUT_EDP:
8298 has_panel = true;
8299 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8300 has_cpu_edp = true;
8301 break;
8302 default:
8303 break;
8304 }
8305 }
8306
8307 if (HAS_PCH_IBX(dev)) {
8308 has_ck505 = dev_priv->vbt.display_clock_mode;
8309 can_ssc = has_ck505;
8310 } else {
8311 has_ck505 = false;
8312 can_ssc = true;
8313 }
8314
8315 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8316 has_panel, has_lvds, has_ck505);
8317
8318 /* Ironlake: try to setup display ref clock before DPLL
8319 * enabling. This is only under driver's control after
8320 * PCH B stepping, previous chipset stepping should be
8321 * ignoring this setting.
8322 */
8323 val = I915_READ(PCH_DREF_CONTROL);
8324
8325 /* As we must carefully and slowly disable/enable each source in turn,
8326 * compute the final state we want first and check if we need to
8327 * make any changes at all.
8328 */
8329 final = val;
8330 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8331 if (has_ck505)
8332 final |= DREF_NONSPREAD_CK505_ENABLE;
8333 else
8334 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8335
8336 final &= ~DREF_SSC_SOURCE_MASK;
8337 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8338 final &= ~DREF_SSC1_ENABLE;
8339
8340 if (has_panel) {
8341 final |= DREF_SSC_SOURCE_ENABLE;
8342
8343 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8344 final |= DREF_SSC1_ENABLE;
8345
8346 if (has_cpu_edp) {
8347 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8348 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8349 else
8350 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8351 } else
8352 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8353 } else {
8354 final |= DREF_SSC_SOURCE_DISABLE;
8355 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8356 }
8357
8358 if (final == val)
8359 return;
8360
8361 /* Always enable nonspread source */
8362 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8363
8364 if (has_ck505)
8365 val |= DREF_NONSPREAD_CK505_ENABLE;
8366 else
8367 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8368
8369 if (has_panel) {
8370 val &= ~DREF_SSC_SOURCE_MASK;
8371 val |= DREF_SSC_SOURCE_ENABLE;
8372
8373 /* SSC must be turned on before enabling the CPU output */
8374 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8375 DRM_DEBUG_KMS("Using SSC on panel\n");
8376 val |= DREF_SSC1_ENABLE;
8377 } else
8378 val &= ~DREF_SSC1_ENABLE;
8379
8380 /* Get SSC going before enabling the outputs */
8381 I915_WRITE(PCH_DREF_CONTROL, val);
8382 POSTING_READ(PCH_DREF_CONTROL);
8383 udelay(200);
8384
8385 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8386
8387 /* Enable CPU source on CPU attached eDP */
8388 if (has_cpu_edp) {
8389 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8390 DRM_DEBUG_KMS("Using SSC on eDP\n");
8391 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8392 } else
8393 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8394 } else
8395 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8396
8397 I915_WRITE(PCH_DREF_CONTROL, val);
8398 POSTING_READ(PCH_DREF_CONTROL);
8399 udelay(200);
8400 } else {
8401 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8402
8403 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8404
8405 /* Turn off CPU output */
8406 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8407
8408 I915_WRITE(PCH_DREF_CONTROL, val);
8409 POSTING_READ(PCH_DREF_CONTROL);
8410 udelay(200);
8411
8412 /* Turn off the SSC source */
8413 val &= ~DREF_SSC_SOURCE_MASK;
8414 val |= DREF_SSC_SOURCE_DISABLE;
8415
8416 /* Turn off SSC1 */
8417 val &= ~DREF_SSC1_ENABLE;
8418
8419 I915_WRITE(PCH_DREF_CONTROL, val);
8420 POSTING_READ(PCH_DREF_CONTROL);
8421 udelay(200);
8422 }
8423
8424 BUG_ON(val != final);
8425 }
8426
8427 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8428 {
8429 uint32_t tmp;
8430
8431 tmp = I915_READ(SOUTH_CHICKEN2);
8432 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8433 I915_WRITE(SOUTH_CHICKEN2, tmp);
8434
8435 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8436 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8437 DRM_ERROR("FDI mPHY reset assert timeout\n");
8438
8439 tmp = I915_READ(SOUTH_CHICKEN2);
8440 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8441 I915_WRITE(SOUTH_CHICKEN2, tmp);
8442
8443 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8444 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8445 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8446 }
8447
8448 /* WaMPhyProgramming:hsw */
8449 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8450 {
8451 uint32_t tmp;
8452
8453 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8454 tmp &= ~(0xFF << 24);
8455 tmp |= (0x12 << 24);
8456 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8457
8458 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8459 tmp |= (1 << 11);
8460 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8461
8462 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8463 tmp |= (1 << 11);
8464 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8465
8466 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8467 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8468 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8469
8470 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8471 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8472 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8473
8474 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8475 tmp &= ~(7 << 13);
8476 tmp |= (5 << 13);
8477 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8478
8479 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8480 tmp &= ~(7 << 13);
8481 tmp |= (5 << 13);
8482 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8483
8484 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8485 tmp &= ~0xFF;
8486 tmp |= 0x1C;
8487 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8488
8489 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8490 tmp &= ~0xFF;
8491 tmp |= 0x1C;
8492 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8493
8494 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8495 tmp &= ~(0xFF << 16);
8496 tmp |= (0x1C << 16);
8497 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8498
8499 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8500 tmp &= ~(0xFF << 16);
8501 tmp |= (0x1C << 16);
8502 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8503
8504 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8505 tmp |= (1 << 27);
8506 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8507
8508 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8509 tmp |= (1 << 27);
8510 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8511
8512 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8513 tmp &= ~(0xF << 28);
8514 tmp |= (4 << 28);
8515 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8516
8517 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8518 tmp &= ~(0xF << 28);
8519 tmp |= (4 << 28);
8520 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8521 }
8522
8523 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8524 * Programming" based on the parameters passed:
8525 * - Sequence to enable CLKOUT_DP
8526 * - Sequence to enable CLKOUT_DP without spread
8527 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8528 */
8529 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8530 bool with_fdi)
8531 {
8532 struct drm_i915_private *dev_priv = dev->dev_private;
8533 uint32_t reg, tmp;
8534
8535 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8536 with_spread = true;
8537 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8538 with_fdi = false;
8539
8540 mutex_lock(&dev_priv->sb_lock);
8541
8542 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8543 tmp &= ~SBI_SSCCTL_DISABLE;
8544 tmp |= SBI_SSCCTL_PATHALT;
8545 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8546
8547 udelay(24);
8548
8549 if (with_spread) {
8550 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8551 tmp &= ~SBI_SSCCTL_PATHALT;
8552 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8553
8554 if (with_fdi) {
8555 lpt_reset_fdi_mphy(dev_priv);
8556 lpt_program_fdi_mphy(dev_priv);
8557 }
8558 }
8559
8560 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8561 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8562 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8563 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8564
8565 mutex_unlock(&dev_priv->sb_lock);
8566 }
8567
8568 /* Sequence to disable CLKOUT_DP */
8569 static void lpt_disable_clkout_dp(struct drm_device *dev)
8570 {
8571 struct drm_i915_private *dev_priv = dev->dev_private;
8572 uint32_t reg, tmp;
8573
8574 mutex_lock(&dev_priv->sb_lock);
8575
8576 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8577 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8578 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8579 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8580
8581 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8582 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8583 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8584 tmp |= SBI_SSCCTL_PATHALT;
8585 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8586 udelay(32);
8587 }
8588 tmp |= SBI_SSCCTL_DISABLE;
8589 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8590 }
8591
8592 mutex_unlock(&dev_priv->sb_lock);
8593 }
8594
8595 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8596
8597 static const uint16_t sscdivintphase[] = {
8598 [BEND_IDX( 50)] = 0x3B23,
8599 [BEND_IDX( 45)] = 0x3B23,
8600 [BEND_IDX( 40)] = 0x3C23,
8601 [BEND_IDX( 35)] = 0x3C23,
8602 [BEND_IDX( 30)] = 0x3D23,
8603 [BEND_IDX( 25)] = 0x3D23,
8604 [BEND_IDX( 20)] = 0x3E23,
8605 [BEND_IDX( 15)] = 0x3E23,
8606 [BEND_IDX( 10)] = 0x3F23,
8607 [BEND_IDX( 5)] = 0x3F23,
8608 [BEND_IDX( 0)] = 0x0025,
8609 [BEND_IDX( -5)] = 0x0025,
8610 [BEND_IDX(-10)] = 0x0125,
8611 [BEND_IDX(-15)] = 0x0125,
8612 [BEND_IDX(-20)] = 0x0225,
8613 [BEND_IDX(-25)] = 0x0225,
8614 [BEND_IDX(-30)] = 0x0325,
8615 [BEND_IDX(-35)] = 0x0325,
8616 [BEND_IDX(-40)] = 0x0425,
8617 [BEND_IDX(-45)] = 0x0425,
8618 [BEND_IDX(-50)] = 0x0525,
8619 };
8620
8621 /*
8622 * Bend CLKOUT_DP
8623 * steps -50 to 50 inclusive, in steps of 5
8624 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8625 * change in clock period = -(steps / 10) * 5.787 ps
8626 */
8627 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8628 {
8629 uint32_t tmp;
8630 int idx = BEND_IDX(steps);
8631
8632 if (WARN_ON(steps % 5 != 0))
8633 return;
8634
8635 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8636 return;
8637
8638 mutex_lock(&dev_priv->sb_lock);
8639
8640 if (steps % 10 != 0)
8641 tmp = 0xAAAAAAAB;
8642 else
8643 tmp = 0x00000000;
8644 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8645
8646 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8647 tmp &= 0xffff0000;
8648 tmp |= sscdivintphase[idx];
8649 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8650
8651 mutex_unlock(&dev_priv->sb_lock);
8652 }
8653
8654 #undef BEND_IDX
8655
8656 static void lpt_init_pch_refclk(struct drm_device *dev)
8657 {
8658 struct intel_encoder *encoder;
8659 bool has_vga = false;
8660
8661 for_each_intel_encoder(dev, encoder) {
8662 switch (encoder->type) {
8663 case INTEL_OUTPUT_ANALOG:
8664 has_vga = true;
8665 break;
8666 default:
8667 break;
8668 }
8669 }
8670
8671 if (has_vga) {
8672 lpt_bend_clkout_dp(to_i915(dev), 0);
8673 lpt_enable_clkout_dp(dev, true, true);
8674 } else {
8675 lpt_disable_clkout_dp(dev);
8676 }
8677 }
8678
8679 /*
8680 * Initialize reference clocks when the driver loads
8681 */
8682 void intel_init_pch_refclk(struct drm_device *dev)
8683 {
8684 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8685 ironlake_init_pch_refclk(dev);
8686 else if (HAS_PCH_LPT(dev))
8687 lpt_init_pch_refclk(dev);
8688 }
8689
8690 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8691 {
8692 struct drm_device *dev = crtc_state->base.crtc->dev;
8693 struct drm_i915_private *dev_priv = dev->dev_private;
8694 struct drm_atomic_state *state = crtc_state->base.state;
8695 struct drm_connector *connector;
8696 struct drm_connector_state *connector_state;
8697 struct intel_encoder *encoder;
8698 int num_connectors = 0, i;
8699 bool is_lvds = false;
8700
8701 for_each_connector_in_state(state, connector, connector_state, i) {
8702 if (connector_state->crtc != crtc_state->base.crtc)
8703 continue;
8704
8705 encoder = to_intel_encoder(connector_state->best_encoder);
8706
8707 switch (encoder->type) {
8708 case INTEL_OUTPUT_LVDS:
8709 is_lvds = true;
8710 break;
8711 default:
8712 break;
8713 }
8714 num_connectors++;
8715 }
8716
8717 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8718 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8719 dev_priv->vbt.lvds_ssc_freq);
8720 return dev_priv->vbt.lvds_ssc_freq;
8721 }
8722
8723 return 120000;
8724 }
8725
8726 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8727 {
8728 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8730 int pipe = intel_crtc->pipe;
8731 uint32_t val;
8732
8733 val = 0;
8734
8735 switch (intel_crtc->config->pipe_bpp) {
8736 case 18:
8737 val |= PIPECONF_6BPC;
8738 break;
8739 case 24:
8740 val |= PIPECONF_8BPC;
8741 break;
8742 case 30:
8743 val |= PIPECONF_10BPC;
8744 break;
8745 case 36:
8746 val |= PIPECONF_12BPC;
8747 break;
8748 default:
8749 /* Case prevented by intel_choose_pipe_bpp_dither. */
8750 BUG();
8751 }
8752
8753 if (intel_crtc->config->dither)
8754 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8755
8756 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8757 val |= PIPECONF_INTERLACED_ILK;
8758 else
8759 val |= PIPECONF_PROGRESSIVE;
8760
8761 if (intel_crtc->config->limited_color_range)
8762 val |= PIPECONF_COLOR_RANGE_SELECT;
8763
8764 I915_WRITE(PIPECONF(pipe), val);
8765 POSTING_READ(PIPECONF(pipe));
8766 }
8767
8768 /*
8769 * Set up the pipe CSC unit.
8770 *
8771 * Currently only full range RGB to limited range RGB conversion
8772 * is supported, but eventually this should handle various
8773 * RGB<->YCbCr scenarios as well.
8774 */
8775 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8776 {
8777 struct drm_device *dev = crtc->dev;
8778 struct drm_i915_private *dev_priv = dev->dev_private;
8779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8780 int pipe = intel_crtc->pipe;
8781 uint16_t coeff = 0x7800; /* 1.0 */
8782
8783 /*
8784 * TODO: Check what kind of values actually come out of the pipe
8785 * with these coeff/postoff values and adjust to get the best
8786 * accuracy. Perhaps we even need to take the bpc value into
8787 * consideration.
8788 */
8789
8790 if (intel_crtc->config->limited_color_range)
8791 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8792
8793 /*
8794 * GY/GU and RY/RU should be the other way around according
8795 * to BSpec, but reality doesn't agree. Just set them up in
8796 * a way that results in the correct picture.
8797 */
8798 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8799 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8800
8801 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8802 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8803
8804 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8805 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8806
8807 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8808 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8809 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8810
8811 if (INTEL_INFO(dev)->gen > 6) {
8812 uint16_t postoff = 0;
8813
8814 if (intel_crtc->config->limited_color_range)
8815 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8816
8817 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8818 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8819 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8820
8821 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8822 } else {
8823 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8824
8825 if (intel_crtc->config->limited_color_range)
8826 mode |= CSC_BLACK_SCREEN_OFFSET;
8827
8828 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8829 }
8830 }
8831
8832 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8833 {
8834 struct drm_device *dev = crtc->dev;
8835 struct drm_i915_private *dev_priv = dev->dev_private;
8836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8837 enum pipe pipe = intel_crtc->pipe;
8838 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8839 uint32_t val;
8840
8841 val = 0;
8842
8843 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8844 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8845
8846 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8847 val |= PIPECONF_INTERLACED_ILK;
8848 else
8849 val |= PIPECONF_PROGRESSIVE;
8850
8851 I915_WRITE(PIPECONF(cpu_transcoder), val);
8852 POSTING_READ(PIPECONF(cpu_transcoder));
8853
8854 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8855 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8856
8857 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8858 val = 0;
8859
8860 switch (intel_crtc->config->pipe_bpp) {
8861 case 18:
8862 val |= PIPEMISC_DITHER_6_BPC;
8863 break;
8864 case 24:
8865 val |= PIPEMISC_DITHER_8_BPC;
8866 break;
8867 case 30:
8868 val |= PIPEMISC_DITHER_10_BPC;
8869 break;
8870 case 36:
8871 val |= PIPEMISC_DITHER_12_BPC;
8872 break;
8873 default:
8874 /* Case prevented by pipe_config_set_bpp. */
8875 BUG();
8876 }
8877
8878 if (intel_crtc->config->dither)
8879 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8880
8881 I915_WRITE(PIPEMISC(pipe), val);
8882 }
8883 }
8884
8885 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8886 struct intel_crtc_state *crtc_state,
8887 intel_clock_t *clock,
8888 bool *has_reduced_clock,
8889 intel_clock_t *reduced_clock)
8890 {
8891 struct drm_device *dev = crtc->dev;
8892 struct drm_i915_private *dev_priv = dev->dev_private;
8893 int refclk;
8894 const intel_limit_t *limit;
8895 bool ret;
8896
8897 refclk = ironlake_get_refclk(crtc_state);
8898
8899 /*
8900 * Returns a set of divisors for the desired target clock with the given
8901 * refclk, or FALSE. The returned values represent the clock equation:
8902 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8903 */
8904 limit = intel_limit(crtc_state, refclk);
8905 ret = dev_priv->display.find_dpll(limit, crtc_state,
8906 crtc_state->port_clock,
8907 refclk, NULL, clock);
8908 if (!ret)
8909 return false;
8910
8911 return true;
8912 }
8913
8914 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8915 {
8916 /*
8917 * Account for spread spectrum to avoid
8918 * oversubscribing the link. Max center spread
8919 * is 2.5%; use 5% for safety's sake.
8920 */
8921 u32 bps = target_clock * bpp * 21 / 20;
8922 return DIV_ROUND_UP(bps, link_bw * 8);
8923 }
8924
8925 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8926 {
8927 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8928 }
8929
8930 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8931 struct intel_crtc_state *crtc_state,
8932 u32 *fp,
8933 intel_clock_t *reduced_clock, u32 *fp2)
8934 {
8935 struct drm_crtc *crtc = &intel_crtc->base;
8936 struct drm_device *dev = crtc->dev;
8937 struct drm_i915_private *dev_priv = dev->dev_private;
8938 struct drm_atomic_state *state = crtc_state->base.state;
8939 struct drm_connector *connector;
8940 struct drm_connector_state *connector_state;
8941 struct intel_encoder *encoder;
8942 uint32_t dpll;
8943 int factor, num_connectors = 0, i;
8944 bool is_lvds = false, is_sdvo = false;
8945
8946 for_each_connector_in_state(state, connector, connector_state, i) {
8947 if (connector_state->crtc != crtc_state->base.crtc)
8948 continue;
8949
8950 encoder = to_intel_encoder(connector_state->best_encoder);
8951
8952 switch (encoder->type) {
8953 case INTEL_OUTPUT_LVDS:
8954 is_lvds = true;
8955 break;
8956 case INTEL_OUTPUT_SDVO:
8957 case INTEL_OUTPUT_HDMI:
8958 is_sdvo = true;
8959 break;
8960 default:
8961 break;
8962 }
8963
8964 num_connectors++;
8965 }
8966
8967 /* Enable autotuning of the PLL clock (if permissible) */
8968 factor = 21;
8969 if (is_lvds) {
8970 if ((intel_panel_use_ssc(dev_priv) &&
8971 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8972 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8973 factor = 25;
8974 } else if (crtc_state->sdvo_tv_clock)
8975 factor = 20;
8976
8977 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8978 *fp |= FP_CB_TUNE;
8979
8980 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8981 *fp2 |= FP_CB_TUNE;
8982
8983 dpll = 0;
8984
8985 if (is_lvds)
8986 dpll |= DPLLB_MODE_LVDS;
8987 else
8988 dpll |= DPLLB_MODE_DAC_SERIAL;
8989
8990 dpll |= (crtc_state->pixel_multiplier - 1)
8991 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8992
8993 if (is_sdvo)
8994 dpll |= DPLL_SDVO_HIGH_SPEED;
8995 if (crtc_state->has_dp_encoder)
8996 dpll |= DPLL_SDVO_HIGH_SPEED;
8997
8998 /* compute bitmask from p1 value */
8999 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9000 /* also FPA1 */
9001 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9002
9003 switch (crtc_state->dpll.p2) {
9004 case 5:
9005 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9006 break;
9007 case 7:
9008 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9009 break;
9010 case 10:
9011 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9012 break;
9013 case 14:
9014 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9015 break;
9016 }
9017
9018 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9019 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9020 else
9021 dpll |= PLL_REF_INPUT_DREFCLK;
9022
9023 return dpll | DPLL_VCO_ENABLE;
9024 }
9025
9026 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9027 struct intel_crtc_state *crtc_state)
9028 {
9029 struct drm_device *dev = crtc->base.dev;
9030 intel_clock_t clock, reduced_clock;
9031 u32 dpll = 0, fp = 0, fp2 = 0;
9032 bool ok, has_reduced_clock = false;
9033 bool is_lvds = false;
9034 struct intel_shared_dpll *pll;
9035
9036 memset(&crtc_state->dpll_hw_state, 0,
9037 sizeof(crtc_state->dpll_hw_state));
9038
9039 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9040
9041 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9042 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9043
9044 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9045 &has_reduced_clock, &reduced_clock);
9046 if (!ok && !crtc_state->clock_set) {
9047 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9048 return -EINVAL;
9049 }
9050 /* Compat-code for transition, will disappear. */
9051 if (!crtc_state->clock_set) {
9052 crtc_state->dpll.n = clock.n;
9053 crtc_state->dpll.m1 = clock.m1;
9054 crtc_state->dpll.m2 = clock.m2;
9055 crtc_state->dpll.p1 = clock.p1;
9056 crtc_state->dpll.p2 = clock.p2;
9057 }
9058
9059 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9060 if (crtc_state->has_pch_encoder) {
9061 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9062 if (has_reduced_clock)
9063 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9064
9065 dpll = ironlake_compute_dpll(crtc, crtc_state,
9066 &fp, &reduced_clock,
9067 has_reduced_clock ? &fp2 : NULL);
9068
9069 crtc_state->dpll_hw_state.dpll = dpll;
9070 crtc_state->dpll_hw_state.fp0 = fp;
9071 if (has_reduced_clock)
9072 crtc_state->dpll_hw_state.fp1 = fp2;
9073 else
9074 crtc_state->dpll_hw_state.fp1 = fp;
9075
9076 pll = intel_get_shared_dpll(crtc, crtc_state);
9077 if (pll == NULL) {
9078 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9079 pipe_name(crtc->pipe));
9080 return -EINVAL;
9081 }
9082 }
9083
9084 if (is_lvds && has_reduced_clock)
9085 crtc->lowfreq_avail = true;
9086 else
9087 crtc->lowfreq_avail = false;
9088
9089 return 0;
9090 }
9091
9092 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9093 struct intel_link_m_n *m_n)
9094 {
9095 struct drm_device *dev = crtc->base.dev;
9096 struct drm_i915_private *dev_priv = dev->dev_private;
9097 enum pipe pipe = crtc->pipe;
9098
9099 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9100 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9101 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9102 & ~TU_SIZE_MASK;
9103 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9104 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9105 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9106 }
9107
9108 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9109 enum transcoder transcoder,
9110 struct intel_link_m_n *m_n,
9111 struct intel_link_m_n *m2_n2)
9112 {
9113 struct drm_device *dev = crtc->base.dev;
9114 struct drm_i915_private *dev_priv = dev->dev_private;
9115 enum pipe pipe = crtc->pipe;
9116
9117 if (INTEL_INFO(dev)->gen >= 5) {
9118 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9119 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9120 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9121 & ~TU_SIZE_MASK;
9122 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9123 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9124 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9125 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9126 * gen < 8) and if DRRS is supported (to make sure the
9127 * registers are not unnecessarily read).
9128 */
9129 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9130 crtc->config->has_drrs) {
9131 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9132 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9133 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9134 & ~TU_SIZE_MASK;
9135 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9136 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9137 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9138 }
9139 } else {
9140 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9141 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9142 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9143 & ~TU_SIZE_MASK;
9144 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9145 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9146 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9147 }
9148 }
9149
9150 void intel_dp_get_m_n(struct intel_crtc *crtc,
9151 struct intel_crtc_state *pipe_config)
9152 {
9153 if (pipe_config->has_pch_encoder)
9154 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9155 else
9156 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9157 &pipe_config->dp_m_n,
9158 &pipe_config->dp_m2_n2);
9159 }
9160
9161 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9162 struct intel_crtc_state *pipe_config)
9163 {
9164 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9165 &pipe_config->fdi_m_n, NULL);
9166 }
9167
9168 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9169 struct intel_crtc_state *pipe_config)
9170 {
9171 struct drm_device *dev = crtc->base.dev;
9172 struct drm_i915_private *dev_priv = dev->dev_private;
9173 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9174 uint32_t ps_ctrl = 0;
9175 int id = -1;
9176 int i;
9177
9178 /* find scaler attached to this pipe */
9179 for (i = 0; i < crtc->num_scalers; i++) {
9180 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9181 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9182 id = i;
9183 pipe_config->pch_pfit.enabled = true;
9184 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9185 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9186 break;
9187 }
9188 }
9189
9190 scaler_state->scaler_id = id;
9191 if (id >= 0) {
9192 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9193 } else {
9194 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9195 }
9196 }
9197
9198 static void
9199 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9200 struct intel_initial_plane_config *plane_config)
9201 {
9202 struct drm_device *dev = crtc->base.dev;
9203 struct drm_i915_private *dev_priv = dev->dev_private;
9204 u32 val, base, offset, stride_mult, tiling;
9205 int pipe = crtc->pipe;
9206 int fourcc, pixel_format;
9207 unsigned int aligned_height;
9208 struct drm_framebuffer *fb;
9209 struct intel_framebuffer *intel_fb;
9210
9211 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9212 if (!intel_fb) {
9213 DRM_DEBUG_KMS("failed to alloc fb\n");
9214 return;
9215 }
9216
9217 fb = &intel_fb->base;
9218
9219 val = I915_READ(PLANE_CTL(pipe, 0));
9220 if (!(val & PLANE_CTL_ENABLE))
9221 goto error;
9222
9223 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9224 fourcc = skl_format_to_fourcc(pixel_format,
9225 val & PLANE_CTL_ORDER_RGBX,
9226 val & PLANE_CTL_ALPHA_MASK);
9227 fb->pixel_format = fourcc;
9228 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9229
9230 tiling = val & PLANE_CTL_TILED_MASK;
9231 switch (tiling) {
9232 case PLANE_CTL_TILED_LINEAR:
9233 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9234 break;
9235 case PLANE_CTL_TILED_X:
9236 plane_config->tiling = I915_TILING_X;
9237 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9238 break;
9239 case PLANE_CTL_TILED_Y:
9240 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9241 break;
9242 case PLANE_CTL_TILED_YF:
9243 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9244 break;
9245 default:
9246 MISSING_CASE(tiling);
9247 goto error;
9248 }
9249
9250 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9251 plane_config->base = base;
9252
9253 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9254
9255 val = I915_READ(PLANE_SIZE(pipe, 0));
9256 fb->height = ((val >> 16) & 0xfff) + 1;
9257 fb->width = ((val >> 0) & 0x1fff) + 1;
9258
9259 val = I915_READ(PLANE_STRIDE(pipe, 0));
9260 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9261 fb->pixel_format);
9262 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9263
9264 aligned_height = intel_fb_align_height(dev, fb->height,
9265 fb->pixel_format,
9266 fb->modifier[0]);
9267
9268 plane_config->size = fb->pitches[0] * aligned_height;
9269
9270 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9271 pipe_name(pipe), fb->width, fb->height,
9272 fb->bits_per_pixel, base, fb->pitches[0],
9273 plane_config->size);
9274
9275 plane_config->fb = intel_fb;
9276 return;
9277
9278 error:
9279 kfree(fb);
9280 }
9281
9282 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9283 struct intel_crtc_state *pipe_config)
9284 {
9285 struct drm_device *dev = crtc->base.dev;
9286 struct drm_i915_private *dev_priv = dev->dev_private;
9287 uint32_t tmp;
9288
9289 tmp = I915_READ(PF_CTL(crtc->pipe));
9290
9291 if (tmp & PF_ENABLE) {
9292 pipe_config->pch_pfit.enabled = true;
9293 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9294 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9295
9296 /* We currently do not free assignements of panel fitters on
9297 * ivb/hsw (since we don't use the higher upscaling modes which
9298 * differentiates them) so just WARN about this case for now. */
9299 if (IS_GEN7(dev)) {
9300 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9301 PF_PIPE_SEL_IVB(crtc->pipe));
9302 }
9303 }
9304 }
9305
9306 static void
9307 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9308 struct intel_initial_plane_config *plane_config)
9309 {
9310 struct drm_device *dev = crtc->base.dev;
9311 struct drm_i915_private *dev_priv = dev->dev_private;
9312 u32 val, base, offset;
9313 int pipe = crtc->pipe;
9314 int fourcc, pixel_format;
9315 unsigned int aligned_height;
9316 struct drm_framebuffer *fb;
9317 struct intel_framebuffer *intel_fb;
9318
9319 val = I915_READ(DSPCNTR(pipe));
9320 if (!(val & DISPLAY_PLANE_ENABLE))
9321 return;
9322
9323 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9324 if (!intel_fb) {
9325 DRM_DEBUG_KMS("failed to alloc fb\n");
9326 return;
9327 }
9328
9329 fb = &intel_fb->base;
9330
9331 if (INTEL_INFO(dev)->gen >= 4) {
9332 if (val & DISPPLANE_TILED) {
9333 plane_config->tiling = I915_TILING_X;
9334 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9335 }
9336 }
9337
9338 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9339 fourcc = i9xx_format_to_fourcc(pixel_format);
9340 fb->pixel_format = fourcc;
9341 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9342
9343 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9344 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9345 offset = I915_READ(DSPOFFSET(pipe));
9346 } else {
9347 if (plane_config->tiling)
9348 offset = I915_READ(DSPTILEOFF(pipe));
9349 else
9350 offset = I915_READ(DSPLINOFF(pipe));
9351 }
9352 plane_config->base = base;
9353
9354 val = I915_READ(PIPESRC(pipe));
9355 fb->width = ((val >> 16) & 0xfff) + 1;
9356 fb->height = ((val >> 0) & 0xfff) + 1;
9357
9358 val = I915_READ(DSPSTRIDE(pipe));
9359 fb->pitches[0] = val & 0xffffffc0;
9360
9361 aligned_height = intel_fb_align_height(dev, fb->height,
9362 fb->pixel_format,
9363 fb->modifier[0]);
9364
9365 plane_config->size = fb->pitches[0] * aligned_height;
9366
9367 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9368 pipe_name(pipe), fb->width, fb->height,
9369 fb->bits_per_pixel, base, fb->pitches[0],
9370 plane_config->size);
9371
9372 plane_config->fb = intel_fb;
9373 }
9374
9375 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9376 struct intel_crtc_state *pipe_config)
9377 {
9378 struct drm_device *dev = crtc->base.dev;
9379 struct drm_i915_private *dev_priv = dev->dev_private;
9380 uint32_t tmp;
9381
9382 if (!intel_display_power_is_enabled(dev_priv,
9383 POWER_DOMAIN_PIPE(crtc->pipe)))
9384 return false;
9385
9386 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9387 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9388
9389 tmp = I915_READ(PIPECONF(crtc->pipe));
9390 if (!(tmp & PIPECONF_ENABLE))
9391 return false;
9392
9393 switch (tmp & PIPECONF_BPC_MASK) {
9394 case PIPECONF_6BPC:
9395 pipe_config->pipe_bpp = 18;
9396 break;
9397 case PIPECONF_8BPC:
9398 pipe_config->pipe_bpp = 24;
9399 break;
9400 case PIPECONF_10BPC:
9401 pipe_config->pipe_bpp = 30;
9402 break;
9403 case PIPECONF_12BPC:
9404 pipe_config->pipe_bpp = 36;
9405 break;
9406 default:
9407 break;
9408 }
9409
9410 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9411 pipe_config->limited_color_range = true;
9412
9413 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9414 struct intel_shared_dpll *pll;
9415
9416 pipe_config->has_pch_encoder = true;
9417
9418 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9419 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9420 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9421
9422 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9423
9424 if (HAS_PCH_IBX(dev_priv->dev)) {
9425 pipe_config->shared_dpll =
9426 (enum intel_dpll_id) crtc->pipe;
9427 } else {
9428 tmp = I915_READ(PCH_DPLL_SEL);
9429 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9430 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9431 else
9432 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9433 }
9434
9435 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9436
9437 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9438 &pipe_config->dpll_hw_state));
9439
9440 tmp = pipe_config->dpll_hw_state.dpll;
9441 pipe_config->pixel_multiplier =
9442 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9443 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9444
9445 ironlake_pch_clock_get(crtc, pipe_config);
9446 } else {
9447 pipe_config->pixel_multiplier = 1;
9448 }
9449
9450 intel_get_pipe_timings(crtc, pipe_config);
9451
9452 ironlake_get_pfit_config(crtc, pipe_config);
9453
9454 return true;
9455 }
9456
9457 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9458 {
9459 struct drm_device *dev = dev_priv->dev;
9460 struct intel_crtc *crtc;
9461
9462 for_each_intel_crtc(dev, crtc)
9463 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9464 pipe_name(crtc->pipe));
9465
9466 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9467 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9468 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9469 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9470 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9471 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9472 "CPU PWM1 enabled\n");
9473 if (IS_HASWELL(dev))
9474 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9475 "CPU PWM2 enabled\n");
9476 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9477 "PCH PWM1 enabled\n");
9478 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9479 "Utility pin enabled\n");
9480 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9481
9482 /*
9483 * In theory we can still leave IRQs enabled, as long as only the HPD
9484 * interrupts remain enabled. We used to check for that, but since it's
9485 * gen-specific and since we only disable LCPLL after we fully disable
9486 * the interrupts, the check below should be enough.
9487 */
9488 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9489 }
9490
9491 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9492 {
9493 struct drm_device *dev = dev_priv->dev;
9494
9495 if (IS_HASWELL(dev))
9496 return I915_READ(D_COMP_HSW);
9497 else
9498 return I915_READ(D_COMP_BDW);
9499 }
9500
9501 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9502 {
9503 struct drm_device *dev = dev_priv->dev;
9504
9505 if (IS_HASWELL(dev)) {
9506 mutex_lock(&dev_priv->rps.hw_lock);
9507 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9508 val))
9509 DRM_ERROR("Failed to write to D_COMP\n");
9510 mutex_unlock(&dev_priv->rps.hw_lock);
9511 } else {
9512 I915_WRITE(D_COMP_BDW, val);
9513 POSTING_READ(D_COMP_BDW);
9514 }
9515 }
9516
9517 /*
9518 * This function implements pieces of two sequences from BSpec:
9519 * - Sequence for display software to disable LCPLL
9520 * - Sequence for display software to allow package C8+
9521 * The steps implemented here are just the steps that actually touch the LCPLL
9522 * register. Callers should take care of disabling all the display engine
9523 * functions, doing the mode unset, fixing interrupts, etc.
9524 */
9525 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9526 bool switch_to_fclk, bool allow_power_down)
9527 {
9528 uint32_t val;
9529
9530 assert_can_disable_lcpll(dev_priv);
9531
9532 val = I915_READ(LCPLL_CTL);
9533
9534 if (switch_to_fclk) {
9535 val |= LCPLL_CD_SOURCE_FCLK;
9536 I915_WRITE(LCPLL_CTL, val);
9537
9538 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9539 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9540 DRM_ERROR("Switching to FCLK failed\n");
9541
9542 val = I915_READ(LCPLL_CTL);
9543 }
9544
9545 val |= LCPLL_PLL_DISABLE;
9546 I915_WRITE(LCPLL_CTL, val);
9547 POSTING_READ(LCPLL_CTL);
9548
9549 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9550 DRM_ERROR("LCPLL still locked\n");
9551
9552 val = hsw_read_dcomp(dev_priv);
9553 val |= D_COMP_COMP_DISABLE;
9554 hsw_write_dcomp(dev_priv, val);
9555 ndelay(100);
9556
9557 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9558 1))
9559 DRM_ERROR("D_COMP RCOMP still in progress\n");
9560
9561 if (allow_power_down) {
9562 val = I915_READ(LCPLL_CTL);
9563 val |= LCPLL_POWER_DOWN_ALLOW;
9564 I915_WRITE(LCPLL_CTL, val);
9565 POSTING_READ(LCPLL_CTL);
9566 }
9567 }
9568
9569 /*
9570 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9571 * source.
9572 */
9573 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9574 {
9575 uint32_t val;
9576
9577 val = I915_READ(LCPLL_CTL);
9578
9579 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9580 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9581 return;
9582
9583 /*
9584 * Make sure we're not on PC8 state before disabling PC8, otherwise
9585 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9586 */
9587 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9588
9589 if (val & LCPLL_POWER_DOWN_ALLOW) {
9590 val &= ~LCPLL_POWER_DOWN_ALLOW;
9591 I915_WRITE(LCPLL_CTL, val);
9592 POSTING_READ(LCPLL_CTL);
9593 }
9594
9595 val = hsw_read_dcomp(dev_priv);
9596 val |= D_COMP_COMP_FORCE;
9597 val &= ~D_COMP_COMP_DISABLE;
9598 hsw_write_dcomp(dev_priv, val);
9599
9600 val = I915_READ(LCPLL_CTL);
9601 val &= ~LCPLL_PLL_DISABLE;
9602 I915_WRITE(LCPLL_CTL, val);
9603
9604 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9605 DRM_ERROR("LCPLL not locked yet\n");
9606
9607 if (val & LCPLL_CD_SOURCE_FCLK) {
9608 val = I915_READ(LCPLL_CTL);
9609 val &= ~LCPLL_CD_SOURCE_FCLK;
9610 I915_WRITE(LCPLL_CTL, val);
9611
9612 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9613 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9614 DRM_ERROR("Switching back to LCPLL failed\n");
9615 }
9616
9617 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9618 intel_update_cdclk(dev_priv->dev);
9619 }
9620
9621 /*
9622 * Package states C8 and deeper are really deep PC states that can only be
9623 * reached when all the devices on the system allow it, so even if the graphics
9624 * device allows PC8+, it doesn't mean the system will actually get to these
9625 * states. Our driver only allows PC8+ when going into runtime PM.
9626 *
9627 * The requirements for PC8+ are that all the outputs are disabled, the power
9628 * well is disabled and most interrupts are disabled, and these are also
9629 * requirements for runtime PM. When these conditions are met, we manually do
9630 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9631 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9632 * hang the machine.
9633 *
9634 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9635 * the state of some registers, so when we come back from PC8+ we need to
9636 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9637 * need to take care of the registers kept by RC6. Notice that this happens even
9638 * if we don't put the device in PCI D3 state (which is what currently happens
9639 * because of the runtime PM support).
9640 *
9641 * For more, read "Display Sequences for Package C8" on the hardware
9642 * documentation.
9643 */
9644 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9645 {
9646 struct drm_device *dev = dev_priv->dev;
9647 uint32_t val;
9648
9649 DRM_DEBUG_KMS("Enabling package C8+\n");
9650
9651 if (HAS_PCH_LPT_LP(dev)) {
9652 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9653 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9654 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9655 }
9656
9657 lpt_disable_clkout_dp(dev);
9658 hsw_disable_lcpll(dev_priv, true, true);
9659 }
9660
9661 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9662 {
9663 struct drm_device *dev = dev_priv->dev;
9664 uint32_t val;
9665
9666 DRM_DEBUG_KMS("Disabling package C8+\n");
9667
9668 hsw_restore_lcpll(dev_priv);
9669 lpt_init_pch_refclk(dev);
9670
9671 if (HAS_PCH_LPT_LP(dev)) {
9672 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9673 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9674 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9675 }
9676 }
9677
9678 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9679 {
9680 struct drm_device *dev = old_state->dev;
9681 struct intel_atomic_state *old_intel_state =
9682 to_intel_atomic_state(old_state);
9683 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9684
9685 broxton_set_cdclk(dev, req_cdclk);
9686 }
9687
9688 /* compute the max rate for new configuration */
9689 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9690 {
9691 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9692 struct drm_i915_private *dev_priv = state->dev->dev_private;
9693 struct drm_crtc *crtc;
9694 struct drm_crtc_state *cstate;
9695 struct intel_crtc_state *crtc_state;
9696 unsigned max_pixel_rate = 0, i;
9697 enum pipe pipe;
9698
9699 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9700 sizeof(intel_state->min_pixclk));
9701
9702 for_each_crtc_in_state(state, crtc, cstate, i) {
9703 int pixel_rate;
9704
9705 crtc_state = to_intel_crtc_state(cstate);
9706 if (!crtc_state->base.enable) {
9707 intel_state->min_pixclk[i] = 0;
9708 continue;
9709 }
9710
9711 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9712
9713 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9714 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9715 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9716
9717 intel_state->min_pixclk[i] = pixel_rate;
9718 }
9719
9720 if (!intel_state->active_crtcs)
9721 return 0;
9722
9723 for_each_pipe(dev_priv, pipe)
9724 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9725
9726 return max_pixel_rate;
9727 }
9728
9729 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9730 {
9731 struct drm_i915_private *dev_priv = dev->dev_private;
9732 uint32_t val, data;
9733 int ret;
9734
9735 if (WARN((I915_READ(LCPLL_CTL) &
9736 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9737 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9738 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9739 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9740 "trying to change cdclk frequency with cdclk not enabled\n"))
9741 return;
9742
9743 mutex_lock(&dev_priv->rps.hw_lock);
9744 ret = sandybridge_pcode_write(dev_priv,
9745 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9746 mutex_unlock(&dev_priv->rps.hw_lock);
9747 if (ret) {
9748 DRM_ERROR("failed to inform pcode about cdclk change\n");
9749 return;
9750 }
9751
9752 val = I915_READ(LCPLL_CTL);
9753 val |= LCPLL_CD_SOURCE_FCLK;
9754 I915_WRITE(LCPLL_CTL, val);
9755
9756 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9757 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9758 DRM_ERROR("Switching to FCLK failed\n");
9759
9760 val = I915_READ(LCPLL_CTL);
9761 val &= ~LCPLL_CLK_FREQ_MASK;
9762
9763 switch (cdclk) {
9764 case 450000:
9765 val |= LCPLL_CLK_FREQ_450;
9766 data = 0;
9767 break;
9768 case 540000:
9769 val |= LCPLL_CLK_FREQ_54O_BDW;
9770 data = 1;
9771 break;
9772 case 337500:
9773 val |= LCPLL_CLK_FREQ_337_5_BDW;
9774 data = 2;
9775 break;
9776 case 675000:
9777 val |= LCPLL_CLK_FREQ_675_BDW;
9778 data = 3;
9779 break;
9780 default:
9781 WARN(1, "invalid cdclk frequency\n");
9782 return;
9783 }
9784
9785 I915_WRITE(LCPLL_CTL, val);
9786
9787 val = I915_READ(LCPLL_CTL);
9788 val &= ~LCPLL_CD_SOURCE_FCLK;
9789 I915_WRITE(LCPLL_CTL, val);
9790
9791 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9792 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9793 DRM_ERROR("Switching back to LCPLL failed\n");
9794
9795 mutex_lock(&dev_priv->rps.hw_lock);
9796 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9797 mutex_unlock(&dev_priv->rps.hw_lock);
9798
9799 intel_update_cdclk(dev);
9800
9801 WARN(cdclk != dev_priv->cdclk_freq,
9802 "cdclk requested %d kHz but got %d kHz\n",
9803 cdclk, dev_priv->cdclk_freq);
9804 }
9805
9806 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9807 {
9808 struct drm_i915_private *dev_priv = to_i915(state->dev);
9809 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9810 int max_pixclk = ilk_max_pixel_rate(state);
9811 int cdclk;
9812
9813 /*
9814 * FIXME should also account for plane ratio
9815 * once 64bpp pixel formats are supported.
9816 */
9817 if (max_pixclk > 540000)
9818 cdclk = 675000;
9819 else if (max_pixclk > 450000)
9820 cdclk = 540000;
9821 else if (max_pixclk > 337500)
9822 cdclk = 450000;
9823 else
9824 cdclk = 337500;
9825
9826 if (cdclk > dev_priv->max_cdclk_freq) {
9827 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9828 cdclk, dev_priv->max_cdclk_freq);
9829 return -EINVAL;
9830 }
9831
9832 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9833 if (!intel_state->active_crtcs)
9834 intel_state->dev_cdclk = 337500;
9835
9836 return 0;
9837 }
9838
9839 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9840 {
9841 struct drm_device *dev = old_state->dev;
9842 struct intel_atomic_state *old_intel_state =
9843 to_intel_atomic_state(old_state);
9844 unsigned req_cdclk = old_intel_state->dev_cdclk;
9845
9846 broadwell_set_cdclk(dev, req_cdclk);
9847 }
9848
9849 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9850 struct intel_crtc_state *crtc_state)
9851 {
9852 if (!intel_ddi_pll_select(crtc, crtc_state))
9853 return -EINVAL;
9854
9855 crtc->lowfreq_avail = false;
9856
9857 return 0;
9858 }
9859
9860 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9861 enum port port,
9862 struct intel_crtc_state *pipe_config)
9863 {
9864 switch (port) {
9865 case PORT_A:
9866 pipe_config->ddi_pll_sel = SKL_DPLL0;
9867 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9868 break;
9869 case PORT_B:
9870 pipe_config->ddi_pll_sel = SKL_DPLL1;
9871 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9872 break;
9873 case PORT_C:
9874 pipe_config->ddi_pll_sel = SKL_DPLL2;
9875 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9876 break;
9877 default:
9878 DRM_ERROR("Incorrect port type\n");
9879 }
9880 }
9881
9882 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9883 enum port port,
9884 struct intel_crtc_state *pipe_config)
9885 {
9886 u32 temp, dpll_ctl1;
9887
9888 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9889 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9890
9891 switch (pipe_config->ddi_pll_sel) {
9892 case SKL_DPLL0:
9893 /*
9894 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9895 * of the shared DPLL framework and thus needs to be read out
9896 * separately
9897 */
9898 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9899 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9900 break;
9901 case SKL_DPLL1:
9902 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9903 break;
9904 case SKL_DPLL2:
9905 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9906 break;
9907 case SKL_DPLL3:
9908 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9909 break;
9910 }
9911 }
9912
9913 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9914 enum port port,
9915 struct intel_crtc_state *pipe_config)
9916 {
9917 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9918
9919 switch (pipe_config->ddi_pll_sel) {
9920 case PORT_CLK_SEL_WRPLL1:
9921 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9922 break;
9923 case PORT_CLK_SEL_WRPLL2:
9924 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9925 break;
9926 case PORT_CLK_SEL_SPLL:
9927 pipe_config->shared_dpll = DPLL_ID_SPLL;
9928 break;
9929 }
9930 }
9931
9932 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9933 struct intel_crtc_state *pipe_config)
9934 {
9935 struct drm_device *dev = crtc->base.dev;
9936 struct drm_i915_private *dev_priv = dev->dev_private;
9937 struct intel_shared_dpll *pll;
9938 enum port port;
9939 uint32_t tmp;
9940
9941 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9942
9943 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9944
9945 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9946 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9947 else if (IS_BROXTON(dev))
9948 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9949 else
9950 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9951
9952 if (pipe_config->shared_dpll >= 0) {
9953 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9954
9955 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9956 &pipe_config->dpll_hw_state));
9957 }
9958
9959 /*
9960 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9961 * DDI E. So just check whether this pipe is wired to DDI E and whether
9962 * the PCH transcoder is on.
9963 */
9964 if (INTEL_INFO(dev)->gen < 9 &&
9965 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9966 pipe_config->has_pch_encoder = true;
9967
9968 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9969 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9970 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9971
9972 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9973 }
9974 }
9975
9976 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9977 struct intel_crtc_state *pipe_config)
9978 {
9979 struct drm_device *dev = crtc->base.dev;
9980 struct drm_i915_private *dev_priv = dev->dev_private;
9981 enum intel_display_power_domain pfit_domain;
9982 uint32_t tmp;
9983
9984 if (!intel_display_power_is_enabled(dev_priv,
9985 POWER_DOMAIN_PIPE(crtc->pipe)))
9986 return false;
9987
9988 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9989 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9990
9991 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9992 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9993 enum pipe trans_edp_pipe;
9994 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9995 default:
9996 WARN(1, "unknown pipe linked to edp transcoder\n");
9997 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9998 case TRANS_DDI_EDP_INPUT_A_ON:
9999 trans_edp_pipe = PIPE_A;
10000 break;
10001 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10002 trans_edp_pipe = PIPE_B;
10003 break;
10004 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10005 trans_edp_pipe = PIPE_C;
10006 break;
10007 }
10008
10009 if (trans_edp_pipe == crtc->pipe)
10010 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10011 }
10012
10013 if (!intel_display_power_is_enabled(dev_priv,
10014 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
10015 return false;
10016
10017 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10018 if (!(tmp & PIPECONF_ENABLE))
10019 return false;
10020
10021 haswell_get_ddi_port_state(crtc, pipe_config);
10022
10023 intel_get_pipe_timings(crtc, pipe_config);
10024
10025 if (INTEL_INFO(dev)->gen >= 9) {
10026 skl_init_scalers(dev, crtc, pipe_config);
10027 }
10028
10029 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10030
10031 if (INTEL_INFO(dev)->gen >= 9) {
10032 pipe_config->scaler_state.scaler_id = -1;
10033 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10034 }
10035
10036 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10037 if (INTEL_INFO(dev)->gen >= 9)
10038 skylake_get_pfit_config(crtc, pipe_config);
10039 else
10040 ironlake_get_pfit_config(crtc, pipe_config);
10041 }
10042
10043 if (IS_HASWELL(dev))
10044 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10045 (I915_READ(IPS_CTL) & IPS_ENABLE);
10046
10047 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10048 pipe_config->pixel_multiplier =
10049 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10050 } else {
10051 pipe_config->pixel_multiplier = 1;
10052 }
10053
10054 return true;
10055 }
10056
10057 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10058 const struct intel_plane_state *plane_state)
10059 {
10060 struct drm_device *dev = crtc->dev;
10061 struct drm_i915_private *dev_priv = dev->dev_private;
10062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10063 uint32_t cntl = 0, size = 0;
10064
10065 if (plane_state && plane_state->visible) {
10066 unsigned int width = plane_state->base.crtc_w;
10067 unsigned int height = plane_state->base.crtc_h;
10068 unsigned int stride = roundup_pow_of_two(width) * 4;
10069
10070 switch (stride) {
10071 default:
10072 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10073 width, stride);
10074 stride = 256;
10075 /* fallthrough */
10076 case 256:
10077 case 512:
10078 case 1024:
10079 case 2048:
10080 break;
10081 }
10082
10083 cntl |= CURSOR_ENABLE |
10084 CURSOR_GAMMA_ENABLE |
10085 CURSOR_FORMAT_ARGB |
10086 CURSOR_STRIDE(stride);
10087
10088 size = (height << 12) | width;
10089 }
10090
10091 if (intel_crtc->cursor_cntl != 0 &&
10092 (intel_crtc->cursor_base != base ||
10093 intel_crtc->cursor_size != size ||
10094 intel_crtc->cursor_cntl != cntl)) {
10095 /* On these chipsets we can only modify the base/size/stride
10096 * whilst the cursor is disabled.
10097 */
10098 I915_WRITE(CURCNTR(PIPE_A), 0);
10099 POSTING_READ(CURCNTR(PIPE_A));
10100 intel_crtc->cursor_cntl = 0;
10101 }
10102
10103 if (intel_crtc->cursor_base != base) {
10104 I915_WRITE(CURBASE(PIPE_A), base);
10105 intel_crtc->cursor_base = base;
10106 }
10107
10108 if (intel_crtc->cursor_size != size) {
10109 I915_WRITE(CURSIZE, size);
10110 intel_crtc->cursor_size = size;
10111 }
10112
10113 if (intel_crtc->cursor_cntl != cntl) {
10114 I915_WRITE(CURCNTR(PIPE_A), cntl);
10115 POSTING_READ(CURCNTR(PIPE_A));
10116 intel_crtc->cursor_cntl = cntl;
10117 }
10118 }
10119
10120 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10121 const struct intel_plane_state *plane_state)
10122 {
10123 struct drm_device *dev = crtc->dev;
10124 struct drm_i915_private *dev_priv = dev->dev_private;
10125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10126 int pipe = intel_crtc->pipe;
10127 uint32_t cntl = 0;
10128
10129 if (plane_state && plane_state->visible) {
10130 cntl = MCURSOR_GAMMA_ENABLE;
10131 switch (plane_state->base.crtc_w) {
10132 case 64:
10133 cntl |= CURSOR_MODE_64_ARGB_AX;
10134 break;
10135 case 128:
10136 cntl |= CURSOR_MODE_128_ARGB_AX;
10137 break;
10138 case 256:
10139 cntl |= CURSOR_MODE_256_ARGB_AX;
10140 break;
10141 default:
10142 MISSING_CASE(plane_state->base.crtc_w);
10143 return;
10144 }
10145 cntl |= pipe << 28; /* Connect to correct pipe */
10146
10147 if (HAS_DDI(dev))
10148 cntl |= CURSOR_PIPE_CSC_ENABLE;
10149
10150 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10151 cntl |= CURSOR_ROTATE_180;
10152 }
10153
10154 if (intel_crtc->cursor_cntl != cntl) {
10155 I915_WRITE(CURCNTR(pipe), cntl);
10156 POSTING_READ(CURCNTR(pipe));
10157 intel_crtc->cursor_cntl = cntl;
10158 }
10159
10160 /* and commit changes on next vblank */
10161 I915_WRITE(CURBASE(pipe), base);
10162 POSTING_READ(CURBASE(pipe));
10163
10164 intel_crtc->cursor_base = base;
10165 }
10166
10167 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10168 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10169 const struct intel_plane_state *plane_state)
10170 {
10171 struct drm_device *dev = crtc->dev;
10172 struct drm_i915_private *dev_priv = dev->dev_private;
10173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10174 int pipe = intel_crtc->pipe;
10175 u32 base = intel_crtc->cursor_addr;
10176 u32 pos = 0;
10177
10178 if (plane_state) {
10179 int x = plane_state->base.crtc_x;
10180 int y = plane_state->base.crtc_y;
10181
10182 if (x < 0) {
10183 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10184 x = -x;
10185 }
10186 pos |= x << CURSOR_X_SHIFT;
10187
10188 if (y < 0) {
10189 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10190 y = -y;
10191 }
10192 pos |= y << CURSOR_Y_SHIFT;
10193
10194 /* ILK+ do this automagically */
10195 if (HAS_GMCH_DISPLAY(dev) &&
10196 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10197 base += (plane_state->base.crtc_h *
10198 plane_state->base.crtc_w - 1) * 4;
10199 }
10200 }
10201
10202 I915_WRITE(CURPOS(pipe), pos);
10203
10204 if (IS_845G(dev) || IS_I865G(dev))
10205 i845_update_cursor(crtc, base, plane_state);
10206 else
10207 i9xx_update_cursor(crtc, base, plane_state);
10208 }
10209
10210 static bool cursor_size_ok(struct drm_device *dev,
10211 uint32_t width, uint32_t height)
10212 {
10213 if (width == 0 || height == 0)
10214 return false;
10215
10216 /*
10217 * 845g/865g are special in that they are only limited by
10218 * the width of their cursors, the height is arbitrary up to
10219 * the precision of the register. Everything else requires
10220 * square cursors, limited to a few power-of-two sizes.
10221 */
10222 if (IS_845G(dev) || IS_I865G(dev)) {
10223 if ((width & 63) != 0)
10224 return false;
10225
10226 if (width > (IS_845G(dev) ? 64 : 512))
10227 return false;
10228
10229 if (height > 1023)
10230 return false;
10231 } else {
10232 switch (width | height) {
10233 case 256:
10234 case 128:
10235 if (IS_GEN2(dev))
10236 return false;
10237 case 64:
10238 break;
10239 default:
10240 return false;
10241 }
10242 }
10243
10244 return true;
10245 }
10246
10247 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10248 u16 *blue, uint32_t start, uint32_t size)
10249 {
10250 int end = (start + size > 256) ? 256 : start + size, i;
10251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10252
10253 for (i = start; i < end; i++) {
10254 intel_crtc->lut_r[i] = red[i] >> 8;
10255 intel_crtc->lut_g[i] = green[i] >> 8;
10256 intel_crtc->lut_b[i] = blue[i] >> 8;
10257 }
10258
10259 intel_crtc_load_lut(crtc);
10260 }
10261
10262 /* VESA 640x480x72Hz mode to set on the pipe */
10263 static struct drm_display_mode load_detect_mode = {
10264 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10265 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10266 };
10267
10268 struct drm_framebuffer *
10269 __intel_framebuffer_create(struct drm_device *dev,
10270 struct drm_mode_fb_cmd2 *mode_cmd,
10271 struct drm_i915_gem_object *obj)
10272 {
10273 struct intel_framebuffer *intel_fb;
10274 int ret;
10275
10276 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10277 if (!intel_fb)
10278 return ERR_PTR(-ENOMEM);
10279
10280 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10281 if (ret)
10282 goto err;
10283
10284 return &intel_fb->base;
10285
10286 err:
10287 kfree(intel_fb);
10288 return ERR_PTR(ret);
10289 }
10290
10291 static struct drm_framebuffer *
10292 intel_framebuffer_create(struct drm_device *dev,
10293 struct drm_mode_fb_cmd2 *mode_cmd,
10294 struct drm_i915_gem_object *obj)
10295 {
10296 struct drm_framebuffer *fb;
10297 int ret;
10298
10299 ret = i915_mutex_lock_interruptible(dev);
10300 if (ret)
10301 return ERR_PTR(ret);
10302 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10303 mutex_unlock(&dev->struct_mutex);
10304
10305 return fb;
10306 }
10307
10308 static u32
10309 intel_framebuffer_pitch_for_width(int width, int bpp)
10310 {
10311 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10312 return ALIGN(pitch, 64);
10313 }
10314
10315 static u32
10316 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10317 {
10318 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10319 return PAGE_ALIGN(pitch * mode->vdisplay);
10320 }
10321
10322 static struct drm_framebuffer *
10323 intel_framebuffer_create_for_mode(struct drm_device *dev,
10324 struct drm_display_mode *mode,
10325 int depth, int bpp)
10326 {
10327 struct drm_framebuffer *fb;
10328 struct drm_i915_gem_object *obj;
10329 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10330
10331 obj = i915_gem_alloc_object(dev,
10332 intel_framebuffer_size_for_mode(mode, bpp));
10333 if (obj == NULL)
10334 return ERR_PTR(-ENOMEM);
10335
10336 mode_cmd.width = mode->hdisplay;
10337 mode_cmd.height = mode->vdisplay;
10338 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10339 bpp);
10340 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10341
10342 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10343 if (IS_ERR(fb))
10344 drm_gem_object_unreference_unlocked(&obj->base);
10345
10346 return fb;
10347 }
10348
10349 static struct drm_framebuffer *
10350 mode_fits_in_fbdev(struct drm_device *dev,
10351 struct drm_display_mode *mode)
10352 {
10353 #ifdef CONFIG_DRM_FBDEV_EMULATION
10354 struct drm_i915_private *dev_priv = dev->dev_private;
10355 struct drm_i915_gem_object *obj;
10356 struct drm_framebuffer *fb;
10357
10358 if (!dev_priv->fbdev)
10359 return NULL;
10360
10361 if (!dev_priv->fbdev->fb)
10362 return NULL;
10363
10364 obj = dev_priv->fbdev->fb->obj;
10365 BUG_ON(!obj);
10366
10367 fb = &dev_priv->fbdev->fb->base;
10368 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10369 fb->bits_per_pixel))
10370 return NULL;
10371
10372 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10373 return NULL;
10374
10375 return fb;
10376 #else
10377 return NULL;
10378 #endif
10379 }
10380
10381 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10382 struct drm_crtc *crtc,
10383 struct drm_display_mode *mode,
10384 struct drm_framebuffer *fb,
10385 int x, int y)
10386 {
10387 struct drm_plane_state *plane_state;
10388 int hdisplay, vdisplay;
10389 int ret;
10390
10391 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10392 if (IS_ERR(plane_state))
10393 return PTR_ERR(plane_state);
10394
10395 if (mode)
10396 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10397 else
10398 hdisplay = vdisplay = 0;
10399
10400 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10401 if (ret)
10402 return ret;
10403 drm_atomic_set_fb_for_plane(plane_state, fb);
10404 plane_state->crtc_x = 0;
10405 plane_state->crtc_y = 0;
10406 plane_state->crtc_w = hdisplay;
10407 plane_state->crtc_h = vdisplay;
10408 plane_state->src_x = x << 16;
10409 plane_state->src_y = y << 16;
10410 plane_state->src_w = hdisplay << 16;
10411 plane_state->src_h = vdisplay << 16;
10412
10413 return 0;
10414 }
10415
10416 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10417 struct drm_display_mode *mode,
10418 struct intel_load_detect_pipe *old,
10419 struct drm_modeset_acquire_ctx *ctx)
10420 {
10421 struct intel_crtc *intel_crtc;
10422 struct intel_encoder *intel_encoder =
10423 intel_attached_encoder(connector);
10424 struct drm_crtc *possible_crtc;
10425 struct drm_encoder *encoder = &intel_encoder->base;
10426 struct drm_crtc *crtc = NULL;
10427 struct drm_device *dev = encoder->dev;
10428 struct drm_framebuffer *fb;
10429 struct drm_mode_config *config = &dev->mode_config;
10430 struct drm_atomic_state *state = NULL;
10431 struct drm_connector_state *connector_state;
10432 struct intel_crtc_state *crtc_state;
10433 int ret, i = -1;
10434
10435 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10436 connector->base.id, connector->name,
10437 encoder->base.id, encoder->name);
10438
10439 retry:
10440 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10441 if (ret)
10442 goto fail;
10443
10444 /*
10445 * Algorithm gets a little messy:
10446 *
10447 * - if the connector already has an assigned crtc, use it (but make
10448 * sure it's on first)
10449 *
10450 * - try to find the first unused crtc that can drive this connector,
10451 * and use that if we find one
10452 */
10453
10454 /* See if we already have a CRTC for this connector */
10455 if (encoder->crtc) {
10456 crtc = encoder->crtc;
10457
10458 ret = drm_modeset_lock(&crtc->mutex, ctx);
10459 if (ret)
10460 goto fail;
10461 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10462 if (ret)
10463 goto fail;
10464
10465 old->dpms_mode = connector->dpms;
10466 old->load_detect_temp = false;
10467
10468 /* Make sure the crtc and connector are running */
10469 if (connector->dpms != DRM_MODE_DPMS_ON)
10470 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10471
10472 return true;
10473 }
10474
10475 /* Find an unused one (if possible) */
10476 for_each_crtc(dev, possible_crtc) {
10477 i++;
10478 if (!(encoder->possible_crtcs & (1 << i)))
10479 continue;
10480 if (possible_crtc->state->enable)
10481 continue;
10482
10483 crtc = possible_crtc;
10484 break;
10485 }
10486
10487 /*
10488 * If we didn't find an unused CRTC, don't use any.
10489 */
10490 if (!crtc) {
10491 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10492 goto fail;
10493 }
10494
10495 ret = drm_modeset_lock(&crtc->mutex, ctx);
10496 if (ret)
10497 goto fail;
10498 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10499 if (ret)
10500 goto fail;
10501
10502 intel_crtc = to_intel_crtc(crtc);
10503 old->dpms_mode = connector->dpms;
10504 old->load_detect_temp = true;
10505 old->release_fb = NULL;
10506
10507 state = drm_atomic_state_alloc(dev);
10508 if (!state)
10509 return false;
10510
10511 state->acquire_ctx = ctx;
10512
10513 connector_state = drm_atomic_get_connector_state(state, connector);
10514 if (IS_ERR(connector_state)) {
10515 ret = PTR_ERR(connector_state);
10516 goto fail;
10517 }
10518
10519 connector_state->crtc = crtc;
10520 connector_state->best_encoder = &intel_encoder->base;
10521
10522 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10523 if (IS_ERR(crtc_state)) {
10524 ret = PTR_ERR(crtc_state);
10525 goto fail;
10526 }
10527
10528 crtc_state->base.active = crtc_state->base.enable = true;
10529
10530 if (!mode)
10531 mode = &load_detect_mode;
10532
10533 /* We need a framebuffer large enough to accommodate all accesses
10534 * that the plane may generate whilst we perform load detection.
10535 * We can not rely on the fbcon either being present (we get called
10536 * during its initialisation to detect all boot displays, or it may
10537 * not even exist) or that it is large enough to satisfy the
10538 * requested mode.
10539 */
10540 fb = mode_fits_in_fbdev(dev, mode);
10541 if (fb == NULL) {
10542 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10543 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10544 old->release_fb = fb;
10545 } else
10546 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10547 if (IS_ERR(fb)) {
10548 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10549 goto fail;
10550 }
10551
10552 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10553 if (ret)
10554 goto fail;
10555
10556 drm_mode_copy(&crtc_state->base.mode, mode);
10557
10558 if (drm_atomic_commit(state)) {
10559 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10560 if (old->release_fb)
10561 old->release_fb->funcs->destroy(old->release_fb);
10562 goto fail;
10563 }
10564 crtc->primary->crtc = crtc;
10565
10566 /* let the connector get through one full cycle before testing */
10567 intel_wait_for_vblank(dev, intel_crtc->pipe);
10568 return true;
10569
10570 fail:
10571 drm_atomic_state_free(state);
10572 state = NULL;
10573
10574 if (ret == -EDEADLK) {
10575 drm_modeset_backoff(ctx);
10576 goto retry;
10577 }
10578
10579 return false;
10580 }
10581
10582 void intel_release_load_detect_pipe(struct drm_connector *connector,
10583 struct intel_load_detect_pipe *old,
10584 struct drm_modeset_acquire_ctx *ctx)
10585 {
10586 struct drm_device *dev = connector->dev;
10587 struct intel_encoder *intel_encoder =
10588 intel_attached_encoder(connector);
10589 struct drm_encoder *encoder = &intel_encoder->base;
10590 struct drm_crtc *crtc = encoder->crtc;
10591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10592 struct drm_atomic_state *state;
10593 struct drm_connector_state *connector_state;
10594 struct intel_crtc_state *crtc_state;
10595 int ret;
10596
10597 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10598 connector->base.id, connector->name,
10599 encoder->base.id, encoder->name);
10600
10601 if (old->load_detect_temp) {
10602 state = drm_atomic_state_alloc(dev);
10603 if (!state)
10604 goto fail;
10605
10606 state->acquire_ctx = ctx;
10607
10608 connector_state = drm_atomic_get_connector_state(state, connector);
10609 if (IS_ERR(connector_state))
10610 goto fail;
10611
10612 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10613 if (IS_ERR(crtc_state))
10614 goto fail;
10615
10616 connector_state->best_encoder = NULL;
10617 connector_state->crtc = NULL;
10618
10619 crtc_state->base.enable = crtc_state->base.active = false;
10620
10621 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10622 0, 0);
10623 if (ret)
10624 goto fail;
10625
10626 ret = drm_atomic_commit(state);
10627 if (ret)
10628 goto fail;
10629
10630 if (old->release_fb) {
10631 drm_framebuffer_unregister_private(old->release_fb);
10632 drm_framebuffer_unreference(old->release_fb);
10633 }
10634
10635 return;
10636 }
10637
10638 /* Switch crtc and encoder back off if necessary */
10639 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10640 connector->funcs->dpms(connector, old->dpms_mode);
10641
10642 return;
10643 fail:
10644 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10645 drm_atomic_state_free(state);
10646 }
10647
10648 static int i9xx_pll_refclk(struct drm_device *dev,
10649 const struct intel_crtc_state *pipe_config)
10650 {
10651 struct drm_i915_private *dev_priv = dev->dev_private;
10652 u32 dpll = pipe_config->dpll_hw_state.dpll;
10653
10654 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10655 return dev_priv->vbt.lvds_ssc_freq;
10656 else if (HAS_PCH_SPLIT(dev))
10657 return 120000;
10658 else if (!IS_GEN2(dev))
10659 return 96000;
10660 else
10661 return 48000;
10662 }
10663
10664 /* Returns the clock of the currently programmed mode of the given pipe. */
10665 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10666 struct intel_crtc_state *pipe_config)
10667 {
10668 struct drm_device *dev = crtc->base.dev;
10669 struct drm_i915_private *dev_priv = dev->dev_private;
10670 int pipe = pipe_config->cpu_transcoder;
10671 u32 dpll = pipe_config->dpll_hw_state.dpll;
10672 u32 fp;
10673 intel_clock_t clock;
10674 int port_clock;
10675 int refclk = i9xx_pll_refclk(dev, pipe_config);
10676
10677 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10678 fp = pipe_config->dpll_hw_state.fp0;
10679 else
10680 fp = pipe_config->dpll_hw_state.fp1;
10681
10682 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10683 if (IS_PINEVIEW(dev)) {
10684 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10685 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10686 } else {
10687 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10688 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10689 }
10690
10691 if (!IS_GEN2(dev)) {
10692 if (IS_PINEVIEW(dev))
10693 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10694 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10695 else
10696 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10697 DPLL_FPA01_P1_POST_DIV_SHIFT);
10698
10699 switch (dpll & DPLL_MODE_MASK) {
10700 case DPLLB_MODE_DAC_SERIAL:
10701 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10702 5 : 10;
10703 break;
10704 case DPLLB_MODE_LVDS:
10705 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10706 7 : 14;
10707 break;
10708 default:
10709 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10710 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10711 return;
10712 }
10713
10714 if (IS_PINEVIEW(dev))
10715 port_clock = pnv_calc_dpll_params(refclk, &clock);
10716 else
10717 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10718 } else {
10719 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10720 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10721
10722 if (is_lvds) {
10723 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10724 DPLL_FPA01_P1_POST_DIV_SHIFT);
10725
10726 if (lvds & LVDS_CLKB_POWER_UP)
10727 clock.p2 = 7;
10728 else
10729 clock.p2 = 14;
10730 } else {
10731 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10732 clock.p1 = 2;
10733 else {
10734 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10735 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10736 }
10737 if (dpll & PLL_P2_DIVIDE_BY_4)
10738 clock.p2 = 4;
10739 else
10740 clock.p2 = 2;
10741 }
10742
10743 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10744 }
10745
10746 /*
10747 * This value includes pixel_multiplier. We will use
10748 * port_clock to compute adjusted_mode.crtc_clock in the
10749 * encoder's get_config() function.
10750 */
10751 pipe_config->port_clock = port_clock;
10752 }
10753
10754 int intel_dotclock_calculate(int link_freq,
10755 const struct intel_link_m_n *m_n)
10756 {
10757 /*
10758 * The calculation for the data clock is:
10759 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10760 * But we want to avoid losing precison if possible, so:
10761 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10762 *
10763 * and the link clock is simpler:
10764 * link_clock = (m * link_clock) / n
10765 */
10766
10767 if (!m_n->link_n)
10768 return 0;
10769
10770 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10771 }
10772
10773 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10774 struct intel_crtc_state *pipe_config)
10775 {
10776 struct drm_device *dev = crtc->base.dev;
10777
10778 /* read out port_clock from the DPLL */
10779 i9xx_crtc_clock_get(crtc, pipe_config);
10780
10781 /*
10782 * This value does not include pixel_multiplier.
10783 * We will check that port_clock and adjusted_mode.crtc_clock
10784 * agree once we know their relationship in the encoder's
10785 * get_config() function.
10786 */
10787 pipe_config->base.adjusted_mode.crtc_clock =
10788 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10789 &pipe_config->fdi_m_n);
10790 }
10791
10792 /** Returns the currently programmed mode of the given pipe. */
10793 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10794 struct drm_crtc *crtc)
10795 {
10796 struct drm_i915_private *dev_priv = dev->dev_private;
10797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10798 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10799 struct drm_display_mode *mode;
10800 struct intel_crtc_state *pipe_config;
10801 int htot = I915_READ(HTOTAL(cpu_transcoder));
10802 int hsync = I915_READ(HSYNC(cpu_transcoder));
10803 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10804 int vsync = I915_READ(VSYNC(cpu_transcoder));
10805 enum pipe pipe = intel_crtc->pipe;
10806
10807 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10808 if (!mode)
10809 return NULL;
10810
10811 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10812 if (!pipe_config) {
10813 kfree(mode);
10814 return NULL;
10815 }
10816
10817 /*
10818 * Construct a pipe_config sufficient for getting the clock info
10819 * back out of crtc_clock_get.
10820 *
10821 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10822 * to use a real value here instead.
10823 */
10824 pipe_config->cpu_transcoder = (enum transcoder) pipe;
10825 pipe_config->pixel_multiplier = 1;
10826 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10827 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10828 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10829 i9xx_crtc_clock_get(intel_crtc, pipe_config);
10830
10831 mode->clock = pipe_config->port_clock / pipe_config->pixel_multiplier;
10832 mode->hdisplay = (htot & 0xffff) + 1;
10833 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10834 mode->hsync_start = (hsync & 0xffff) + 1;
10835 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10836 mode->vdisplay = (vtot & 0xffff) + 1;
10837 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10838 mode->vsync_start = (vsync & 0xffff) + 1;
10839 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10840
10841 drm_mode_set_name(mode);
10842
10843 kfree(pipe_config);
10844
10845 return mode;
10846 }
10847
10848 void intel_mark_busy(struct drm_device *dev)
10849 {
10850 struct drm_i915_private *dev_priv = dev->dev_private;
10851
10852 if (dev_priv->mm.busy)
10853 return;
10854
10855 intel_runtime_pm_get(dev_priv);
10856 i915_update_gfx_val(dev_priv);
10857 if (INTEL_INFO(dev)->gen >= 6)
10858 gen6_rps_busy(dev_priv);
10859 dev_priv->mm.busy = true;
10860 }
10861
10862 void intel_mark_idle(struct drm_device *dev)
10863 {
10864 struct drm_i915_private *dev_priv = dev->dev_private;
10865
10866 if (!dev_priv->mm.busy)
10867 return;
10868
10869 dev_priv->mm.busy = false;
10870
10871 if (INTEL_INFO(dev)->gen >= 6)
10872 gen6_rps_idle(dev->dev_private);
10873
10874 intel_runtime_pm_put(dev_priv);
10875 }
10876
10877 static void intel_crtc_destroy(struct drm_crtc *crtc)
10878 {
10879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10880 struct drm_device *dev = crtc->dev;
10881 struct intel_unpin_work *work;
10882
10883 spin_lock_irq(&dev->event_lock);
10884 work = intel_crtc->unpin_work;
10885 intel_crtc->unpin_work = NULL;
10886 spin_unlock_irq(&dev->event_lock);
10887
10888 if (work) {
10889 cancel_work_sync(&work->work);
10890 kfree(work);
10891 }
10892
10893 drm_crtc_cleanup(crtc);
10894
10895 kfree(intel_crtc);
10896 }
10897
10898 static void intel_unpin_work_fn(struct work_struct *__work)
10899 {
10900 struct intel_unpin_work *work =
10901 container_of(__work, struct intel_unpin_work, work);
10902 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10903 struct drm_device *dev = crtc->base.dev;
10904 struct drm_plane *primary = crtc->base.primary;
10905
10906 mutex_lock(&dev->struct_mutex);
10907 intel_unpin_fb_obj(work->old_fb, primary->state);
10908 drm_gem_object_unreference(&work->pending_flip_obj->base);
10909
10910 if (work->flip_queued_req)
10911 i915_gem_request_assign(&work->flip_queued_req, NULL);
10912 mutex_unlock(&dev->struct_mutex);
10913
10914 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10915 intel_fbc_post_update(crtc);
10916 drm_framebuffer_unreference(work->old_fb);
10917
10918 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10919 atomic_dec(&crtc->unpin_work_count);
10920
10921 kfree(work);
10922 }
10923
10924 static void do_intel_finish_page_flip(struct drm_device *dev,
10925 struct drm_crtc *crtc)
10926 {
10927 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10928 struct intel_unpin_work *work;
10929 unsigned long flags;
10930
10931 /* Ignore early vblank irqs */
10932 if (intel_crtc == NULL)
10933 return;
10934
10935 /*
10936 * This is called both by irq handlers and the reset code (to complete
10937 * lost pageflips) so needs the full irqsave spinlocks.
10938 */
10939 spin_lock_irqsave(&dev->event_lock, flags);
10940 work = intel_crtc->unpin_work;
10941
10942 /* Ensure we don't miss a work->pending update ... */
10943 smp_rmb();
10944
10945 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10946 spin_unlock_irqrestore(&dev->event_lock, flags);
10947 return;
10948 }
10949
10950 page_flip_completed(intel_crtc);
10951
10952 spin_unlock_irqrestore(&dev->event_lock, flags);
10953 }
10954
10955 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10956 {
10957 struct drm_i915_private *dev_priv = dev->dev_private;
10958 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10959
10960 do_intel_finish_page_flip(dev, crtc);
10961 }
10962
10963 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10964 {
10965 struct drm_i915_private *dev_priv = dev->dev_private;
10966 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10967
10968 do_intel_finish_page_flip(dev, crtc);
10969 }
10970
10971 /* Is 'a' after or equal to 'b'? */
10972 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10973 {
10974 return !((a - b) & 0x80000000);
10975 }
10976
10977 static bool page_flip_finished(struct intel_crtc *crtc)
10978 {
10979 struct drm_device *dev = crtc->base.dev;
10980 struct drm_i915_private *dev_priv = dev->dev_private;
10981
10982 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10983 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10984 return true;
10985
10986 /*
10987 * The relevant registers doen't exist on pre-ctg.
10988 * As the flip done interrupt doesn't trigger for mmio
10989 * flips on gmch platforms, a flip count check isn't
10990 * really needed there. But since ctg has the registers,
10991 * include it in the check anyway.
10992 */
10993 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10994 return true;
10995
10996 /*
10997 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10998 * used the same base address. In that case the mmio flip might
10999 * have completed, but the CS hasn't even executed the flip yet.
11000 *
11001 * A flip count check isn't enough as the CS might have updated
11002 * the base address just after start of vblank, but before we
11003 * managed to process the interrupt. This means we'd complete the
11004 * CS flip too soon.
11005 *
11006 * Combining both checks should get us a good enough result. It may
11007 * still happen that the CS flip has been executed, but has not
11008 * yet actually completed. But in case the base address is the same
11009 * anyway, we don't really care.
11010 */
11011 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11012 crtc->unpin_work->gtt_offset &&
11013 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11014 crtc->unpin_work->flip_count);
11015 }
11016
11017 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11018 {
11019 struct drm_i915_private *dev_priv = dev->dev_private;
11020 struct intel_crtc *intel_crtc =
11021 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11022 unsigned long flags;
11023
11024
11025 /*
11026 * This is called both by irq handlers and the reset code (to complete
11027 * lost pageflips) so needs the full irqsave spinlocks.
11028 *
11029 * NB: An MMIO update of the plane base pointer will also
11030 * generate a page-flip completion irq, i.e. every modeset
11031 * is also accompanied by a spurious intel_prepare_page_flip().
11032 */
11033 spin_lock_irqsave(&dev->event_lock, flags);
11034 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11035 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11036 spin_unlock_irqrestore(&dev->event_lock, flags);
11037 }
11038
11039 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11040 {
11041 /* Ensure that the work item is consistent when activating it ... */
11042 smp_wmb();
11043 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11044 /* and that it is marked active as soon as the irq could fire. */
11045 smp_wmb();
11046 }
11047
11048 static int intel_gen2_queue_flip(struct drm_device *dev,
11049 struct drm_crtc *crtc,
11050 struct drm_framebuffer *fb,
11051 struct drm_i915_gem_object *obj,
11052 struct drm_i915_gem_request *req,
11053 uint32_t flags)
11054 {
11055 struct intel_engine_cs *ring = req->ring;
11056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11057 u32 flip_mask;
11058 int ret;
11059
11060 ret = intel_ring_begin(req, 6);
11061 if (ret)
11062 return ret;
11063
11064 /* Can't queue multiple flips, so wait for the previous
11065 * one to finish before executing the next.
11066 */
11067 if (intel_crtc->plane)
11068 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11069 else
11070 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11071 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11072 intel_ring_emit(ring, MI_NOOP);
11073 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11074 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11075 intel_ring_emit(ring, fb->pitches[0]);
11076 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11077 intel_ring_emit(ring, 0); /* aux display base address, unused */
11078
11079 intel_mark_page_flip_active(intel_crtc->unpin_work);
11080 return 0;
11081 }
11082
11083 static int intel_gen3_queue_flip(struct drm_device *dev,
11084 struct drm_crtc *crtc,
11085 struct drm_framebuffer *fb,
11086 struct drm_i915_gem_object *obj,
11087 struct drm_i915_gem_request *req,
11088 uint32_t flags)
11089 {
11090 struct intel_engine_cs *ring = req->ring;
11091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11092 u32 flip_mask;
11093 int ret;
11094
11095 ret = intel_ring_begin(req, 6);
11096 if (ret)
11097 return ret;
11098
11099 if (intel_crtc->plane)
11100 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11101 else
11102 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11103 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11104 intel_ring_emit(ring, MI_NOOP);
11105 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11106 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11107 intel_ring_emit(ring, fb->pitches[0]);
11108 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11109 intel_ring_emit(ring, MI_NOOP);
11110
11111 intel_mark_page_flip_active(intel_crtc->unpin_work);
11112 return 0;
11113 }
11114
11115 static int intel_gen4_queue_flip(struct drm_device *dev,
11116 struct drm_crtc *crtc,
11117 struct drm_framebuffer *fb,
11118 struct drm_i915_gem_object *obj,
11119 struct drm_i915_gem_request *req,
11120 uint32_t flags)
11121 {
11122 struct intel_engine_cs *ring = req->ring;
11123 struct drm_i915_private *dev_priv = dev->dev_private;
11124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11125 uint32_t pf, pipesrc;
11126 int ret;
11127
11128 ret = intel_ring_begin(req, 4);
11129 if (ret)
11130 return ret;
11131
11132 /* i965+ uses the linear or tiled offsets from the
11133 * Display Registers (which do not change across a page-flip)
11134 * so we need only reprogram the base address.
11135 */
11136 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11137 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11138 intel_ring_emit(ring, fb->pitches[0]);
11139 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11140 obj->tiling_mode);
11141
11142 /* XXX Enabling the panel-fitter across page-flip is so far
11143 * untested on non-native modes, so ignore it for now.
11144 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11145 */
11146 pf = 0;
11147 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11148 intel_ring_emit(ring, pf | pipesrc);
11149
11150 intel_mark_page_flip_active(intel_crtc->unpin_work);
11151 return 0;
11152 }
11153
11154 static int intel_gen6_queue_flip(struct drm_device *dev,
11155 struct drm_crtc *crtc,
11156 struct drm_framebuffer *fb,
11157 struct drm_i915_gem_object *obj,
11158 struct drm_i915_gem_request *req,
11159 uint32_t flags)
11160 {
11161 struct intel_engine_cs *ring = req->ring;
11162 struct drm_i915_private *dev_priv = dev->dev_private;
11163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11164 uint32_t pf, pipesrc;
11165 int ret;
11166
11167 ret = intel_ring_begin(req, 4);
11168 if (ret)
11169 return ret;
11170
11171 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11172 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11173 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11174 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11175
11176 /* Contrary to the suggestions in the documentation,
11177 * "Enable Panel Fitter" does not seem to be required when page
11178 * flipping with a non-native mode, and worse causes a normal
11179 * modeset to fail.
11180 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11181 */
11182 pf = 0;
11183 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11184 intel_ring_emit(ring, pf | pipesrc);
11185
11186 intel_mark_page_flip_active(intel_crtc->unpin_work);
11187 return 0;
11188 }
11189
11190 static int intel_gen7_queue_flip(struct drm_device *dev,
11191 struct drm_crtc *crtc,
11192 struct drm_framebuffer *fb,
11193 struct drm_i915_gem_object *obj,
11194 struct drm_i915_gem_request *req,
11195 uint32_t flags)
11196 {
11197 struct intel_engine_cs *ring = req->ring;
11198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11199 uint32_t plane_bit = 0;
11200 int len, ret;
11201
11202 switch (intel_crtc->plane) {
11203 case PLANE_A:
11204 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11205 break;
11206 case PLANE_B:
11207 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11208 break;
11209 case PLANE_C:
11210 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11211 break;
11212 default:
11213 WARN_ONCE(1, "unknown plane in flip command\n");
11214 return -ENODEV;
11215 }
11216
11217 len = 4;
11218 if (ring->id == RCS) {
11219 len += 6;
11220 /*
11221 * On Gen 8, SRM is now taking an extra dword to accommodate
11222 * 48bits addresses, and we need a NOOP for the batch size to
11223 * stay even.
11224 */
11225 if (IS_GEN8(dev))
11226 len += 2;
11227 }
11228
11229 /*
11230 * BSpec MI_DISPLAY_FLIP for IVB:
11231 * "The full packet must be contained within the same cache line."
11232 *
11233 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11234 * cacheline, if we ever start emitting more commands before
11235 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11236 * then do the cacheline alignment, and finally emit the
11237 * MI_DISPLAY_FLIP.
11238 */
11239 ret = intel_ring_cacheline_align(req);
11240 if (ret)
11241 return ret;
11242
11243 ret = intel_ring_begin(req, len);
11244 if (ret)
11245 return ret;
11246
11247 /* Unmask the flip-done completion message. Note that the bspec says that
11248 * we should do this for both the BCS and RCS, and that we must not unmask
11249 * more than one flip event at any time (or ensure that one flip message
11250 * can be sent by waiting for flip-done prior to queueing new flips).
11251 * Experimentation says that BCS works despite DERRMR masking all
11252 * flip-done completion events and that unmasking all planes at once
11253 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11254 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11255 */
11256 if (ring->id == RCS) {
11257 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11258 intel_ring_emit_reg(ring, DERRMR);
11259 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11260 DERRMR_PIPEB_PRI_FLIP_DONE |
11261 DERRMR_PIPEC_PRI_FLIP_DONE));
11262 if (IS_GEN8(dev))
11263 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11264 MI_SRM_LRM_GLOBAL_GTT);
11265 else
11266 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11267 MI_SRM_LRM_GLOBAL_GTT);
11268 intel_ring_emit_reg(ring, DERRMR);
11269 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11270 if (IS_GEN8(dev)) {
11271 intel_ring_emit(ring, 0);
11272 intel_ring_emit(ring, MI_NOOP);
11273 }
11274 }
11275
11276 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11277 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11278 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11279 intel_ring_emit(ring, (MI_NOOP));
11280
11281 intel_mark_page_flip_active(intel_crtc->unpin_work);
11282 return 0;
11283 }
11284
11285 static bool use_mmio_flip(struct intel_engine_cs *ring,
11286 struct drm_i915_gem_object *obj)
11287 {
11288 /*
11289 * This is not being used for older platforms, because
11290 * non-availability of flip done interrupt forces us to use
11291 * CS flips. Older platforms derive flip done using some clever
11292 * tricks involving the flip_pending status bits and vblank irqs.
11293 * So using MMIO flips there would disrupt this mechanism.
11294 */
11295
11296 if (ring == NULL)
11297 return true;
11298
11299 if (INTEL_INFO(ring->dev)->gen < 5)
11300 return false;
11301
11302 if (i915.use_mmio_flip < 0)
11303 return false;
11304 else if (i915.use_mmio_flip > 0)
11305 return true;
11306 else if (i915.enable_execlists)
11307 return true;
11308 else if (obj->base.dma_buf &&
11309 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11310 false))
11311 return true;
11312 else
11313 return ring != i915_gem_request_get_ring(obj->last_write_req);
11314 }
11315
11316 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11317 unsigned int rotation,
11318 struct intel_unpin_work *work)
11319 {
11320 struct drm_device *dev = intel_crtc->base.dev;
11321 struct drm_i915_private *dev_priv = dev->dev_private;
11322 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11323 const enum pipe pipe = intel_crtc->pipe;
11324 u32 ctl, stride, tile_height;
11325
11326 ctl = I915_READ(PLANE_CTL(pipe, 0));
11327 ctl &= ~PLANE_CTL_TILED_MASK;
11328 switch (fb->modifier[0]) {
11329 case DRM_FORMAT_MOD_NONE:
11330 break;
11331 case I915_FORMAT_MOD_X_TILED:
11332 ctl |= PLANE_CTL_TILED_X;
11333 break;
11334 case I915_FORMAT_MOD_Y_TILED:
11335 ctl |= PLANE_CTL_TILED_Y;
11336 break;
11337 case I915_FORMAT_MOD_Yf_TILED:
11338 ctl |= PLANE_CTL_TILED_YF;
11339 break;
11340 default:
11341 MISSING_CASE(fb->modifier[0]);
11342 }
11343
11344 /*
11345 * The stride is either expressed as a multiple of 64 bytes chunks for
11346 * linear buffers or in number of tiles for tiled buffers.
11347 */
11348 if (intel_rotation_90_or_270(rotation)) {
11349 /* stride = Surface height in tiles */
11350 tile_height = intel_tile_height(dev_priv, fb->modifier[0], 0);
11351 stride = DIV_ROUND_UP(fb->height, tile_height);
11352 } else {
11353 stride = fb->pitches[0] /
11354 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11355 fb->pixel_format);
11356 }
11357
11358 /*
11359 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11360 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11361 */
11362 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11363 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11364
11365 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11366 POSTING_READ(PLANE_SURF(pipe, 0));
11367 }
11368
11369 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11370 struct intel_unpin_work *work)
11371 {
11372 struct drm_device *dev = intel_crtc->base.dev;
11373 struct drm_i915_private *dev_priv = dev->dev_private;
11374 struct intel_framebuffer *intel_fb =
11375 to_intel_framebuffer(intel_crtc->base.primary->fb);
11376 struct drm_i915_gem_object *obj = intel_fb->obj;
11377 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11378 u32 dspcntr;
11379
11380 dspcntr = I915_READ(reg);
11381
11382 if (obj->tiling_mode != I915_TILING_NONE)
11383 dspcntr |= DISPPLANE_TILED;
11384 else
11385 dspcntr &= ~DISPPLANE_TILED;
11386
11387 I915_WRITE(reg, dspcntr);
11388
11389 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11390 POSTING_READ(DSPSURF(intel_crtc->plane));
11391 }
11392
11393 /*
11394 * XXX: This is the temporary way to update the plane registers until we get
11395 * around to using the usual plane update functions for MMIO flips
11396 */
11397 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11398 {
11399 struct intel_crtc *crtc = mmio_flip->crtc;
11400 struct intel_unpin_work *work;
11401
11402 spin_lock_irq(&crtc->base.dev->event_lock);
11403 work = crtc->unpin_work;
11404 spin_unlock_irq(&crtc->base.dev->event_lock);
11405 if (work == NULL)
11406 return;
11407
11408 intel_mark_page_flip_active(work);
11409
11410 intel_pipe_update_start(crtc);
11411
11412 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11413 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11414 else
11415 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11416 ilk_do_mmio_flip(crtc, work);
11417
11418 intel_pipe_update_end(crtc);
11419 }
11420
11421 static void intel_mmio_flip_work_func(struct work_struct *work)
11422 {
11423 struct intel_mmio_flip *mmio_flip =
11424 container_of(work, struct intel_mmio_flip, work);
11425 struct intel_framebuffer *intel_fb =
11426 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11427 struct drm_i915_gem_object *obj = intel_fb->obj;
11428
11429 if (mmio_flip->req) {
11430 WARN_ON(__i915_wait_request(mmio_flip->req,
11431 mmio_flip->crtc->reset_counter,
11432 false, NULL,
11433 &mmio_flip->i915->rps.mmioflips));
11434 i915_gem_request_unreference__unlocked(mmio_flip->req);
11435 }
11436
11437 /* For framebuffer backed by dmabuf, wait for fence */
11438 if (obj->base.dma_buf)
11439 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11440 false, false,
11441 MAX_SCHEDULE_TIMEOUT) < 0);
11442
11443 intel_do_mmio_flip(mmio_flip);
11444 kfree(mmio_flip);
11445 }
11446
11447 static int intel_queue_mmio_flip(struct drm_device *dev,
11448 struct drm_crtc *crtc,
11449 struct drm_i915_gem_object *obj)
11450 {
11451 struct intel_mmio_flip *mmio_flip;
11452
11453 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11454 if (mmio_flip == NULL)
11455 return -ENOMEM;
11456
11457 mmio_flip->i915 = to_i915(dev);
11458 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11459 mmio_flip->crtc = to_intel_crtc(crtc);
11460 mmio_flip->rotation = crtc->primary->state->rotation;
11461
11462 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11463 schedule_work(&mmio_flip->work);
11464
11465 return 0;
11466 }
11467
11468 static int intel_default_queue_flip(struct drm_device *dev,
11469 struct drm_crtc *crtc,
11470 struct drm_framebuffer *fb,
11471 struct drm_i915_gem_object *obj,
11472 struct drm_i915_gem_request *req,
11473 uint32_t flags)
11474 {
11475 return -ENODEV;
11476 }
11477
11478 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11479 struct drm_crtc *crtc)
11480 {
11481 struct drm_i915_private *dev_priv = dev->dev_private;
11482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11483 struct intel_unpin_work *work = intel_crtc->unpin_work;
11484 u32 addr;
11485
11486 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11487 return true;
11488
11489 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11490 return false;
11491
11492 if (!work->enable_stall_check)
11493 return false;
11494
11495 if (work->flip_ready_vblank == 0) {
11496 if (work->flip_queued_req &&
11497 !i915_gem_request_completed(work->flip_queued_req, true))
11498 return false;
11499
11500 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11501 }
11502
11503 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11504 return false;
11505
11506 /* Potential stall - if we see that the flip has happened,
11507 * assume a missed interrupt. */
11508 if (INTEL_INFO(dev)->gen >= 4)
11509 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11510 else
11511 addr = I915_READ(DSPADDR(intel_crtc->plane));
11512
11513 /* There is a potential issue here with a false positive after a flip
11514 * to the same address. We could address this by checking for a
11515 * non-incrementing frame counter.
11516 */
11517 return addr == work->gtt_offset;
11518 }
11519
11520 void intel_check_page_flip(struct drm_device *dev, int pipe)
11521 {
11522 struct drm_i915_private *dev_priv = dev->dev_private;
11523 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11525 struct intel_unpin_work *work;
11526
11527 WARN_ON(!in_interrupt());
11528
11529 if (crtc == NULL)
11530 return;
11531
11532 spin_lock(&dev->event_lock);
11533 work = intel_crtc->unpin_work;
11534 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11535 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11536 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11537 page_flip_completed(intel_crtc);
11538 work = NULL;
11539 }
11540 if (work != NULL &&
11541 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11542 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11543 spin_unlock(&dev->event_lock);
11544 }
11545
11546 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11547 struct drm_framebuffer *fb,
11548 struct drm_pending_vblank_event *event,
11549 uint32_t page_flip_flags)
11550 {
11551 struct drm_device *dev = crtc->dev;
11552 struct drm_i915_private *dev_priv = dev->dev_private;
11553 struct drm_framebuffer *old_fb = crtc->primary->fb;
11554 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11556 struct drm_plane *primary = crtc->primary;
11557 enum pipe pipe = intel_crtc->pipe;
11558 struct intel_unpin_work *work;
11559 struct intel_engine_cs *ring;
11560 bool mmio_flip;
11561 struct drm_i915_gem_request *request = NULL;
11562 int ret;
11563
11564 /*
11565 * drm_mode_page_flip_ioctl() should already catch this, but double
11566 * check to be safe. In the future we may enable pageflipping from
11567 * a disabled primary plane.
11568 */
11569 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11570 return -EBUSY;
11571
11572 /* Can't change pixel format via MI display flips. */
11573 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11574 return -EINVAL;
11575
11576 /*
11577 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11578 * Note that pitch changes could also affect these register.
11579 */
11580 if (INTEL_INFO(dev)->gen > 3 &&
11581 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11582 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11583 return -EINVAL;
11584
11585 if (i915_terminally_wedged(&dev_priv->gpu_error))
11586 goto out_hang;
11587
11588 work = kzalloc(sizeof(*work), GFP_KERNEL);
11589 if (work == NULL)
11590 return -ENOMEM;
11591
11592 work->event = event;
11593 work->crtc = crtc;
11594 work->old_fb = old_fb;
11595 INIT_WORK(&work->work, intel_unpin_work_fn);
11596
11597 ret = drm_crtc_vblank_get(crtc);
11598 if (ret)
11599 goto free_work;
11600
11601 /* We borrow the event spin lock for protecting unpin_work */
11602 spin_lock_irq(&dev->event_lock);
11603 if (intel_crtc->unpin_work) {
11604 /* Before declaring the flip queue wedged, check if
11605 * the hardware completed the operation behind our backs.
11606 */
11607 if (__intel_pageflip_stall_check(dev, crtc)) {
11608 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11609 page_flip_completed(intel_crtc);
11610 } else {
11611 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11612 spin_unlock_irq(&dev->event_lock);
11613
11614 drm_crtc_vblank_put(crtc);
11615 kfree(work);
11616 return -EBUSY;
11617 }
11618 }
11619 intel_crtc->unpin_work = work;
11620 spin_unlock_irq(&dev->event_lock);
11621
11622 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11623 flush_workqueue(dev_priv->wq);
11624
11625 /* Reference the objects for the scheduled work. */
11626 drm_framebuffer_reference(work->old_fb);
11627 drm_gem_object_reference(&obj->base);
11628
11629 crtc->primary->fb = fb;
11630 update_state_fb(crtc->primary);
11631
11632 work->pending_flip_obj = obj;
11633
11634 ret = i915_mutex_lock_interruptible(dev);
11635 if (ret)
11636 goto cleanup;
11637
11638 atomic_inc(&intel_crtc->unpin_work_count);
11639 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11640
11641 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11642 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11643
11644 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11645 ring = &dev_priv->ring[BCS];
11646 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11647 /* vlv: DISPLAY_FLIP fails to change tiling */
11648 ring = NULL;
11649 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11650 ring = &dev_priv->ring[BCS];
11651 } else if (INTEL_INFO(dev)->gen >= 7) {
11652 ring = i915_gem_request_get_ring(obj->last_write_req);
11653 if (ring == NULL || ring->id != RCS)
11654 ring = &dev_priv->ring[BCS];
11655 } else {
11656 ring = &dev_priv->ring[RCS];
11657 }
11658
11659 mmio_flip = use_mmio_flip(ring, obj);
11660
11661 /* When using CS flips, we want to emit semaphores between rings.
11662 * However, when using mmio flips we will create a task to do the
11663 * synchronisation, so all we want here is to pin the framebuffer
11664 * into the display plane and skip any waits.
11665 */
11666 if (!mmio_flip) {
11667 ret = i915_gem_object_sync(obj, ring, &request);
11668 if (ret)
11669 goto cleanup_pending;
11670 }
11671
11672 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11673 crtc->primary->state);
11674 if (ret)
11675 goto cleanup_pending;
11676
11677 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11678 obj, 0);
11679 work->gtt_offset += intel_crtc->dspaddr_offset;
11680
11681 if (mmio_flip) {
11682 ret = intel_queue_mmio_flip(dev, crtc, obj);
11683 if (ret)
11684 goto cleanup_unpin;
11685
11686 i915_gem_request_assign(&work->flip_queued_req,
11687 obj->last_write_req);
11688 } else {
11689 if (!request) {
11690 request = i915_gem_request_alloc(ring, NULL);
11691 if (IS_ERR(request)) {
11692 ret = PTR_ERR(request);
11693 goto cleanup_unpin;
11694 }
11695 }
11696
11697 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11698 page_flip_flags);
11699 if (ret)
11700 goto cleanup_unpin;
11701
11702 i915_gem_request_assign(&work->flip_queued_req, request);
11703 }
11704
11705 if (request)
11706 i915_add_request_no_flush(request);
11707
11708 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11709 work->enable_stall_check = true;
11710
11711 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11712 to_intel_plane(primary)->frontbuffer_bit);
11713 mutex_unlock(&dev->struct_mutex);
11714
11715 intel_fbc_pre_update(intel_crtc);
11716 intel_frontbuffer_flip_prepare(dev,
11717 to_intel_plane(primary)->frontbuffer_bit);
11718
11719 trace_i915_flip_request(intel_crtc->plane, obj);
11720
11721 return 0;
11722
11723 cleanup_unpin:
11724 intel_unpin_fb_obj(fb, crtc->primary->state);
11725 cleanup_pending:
11726 if (!IS_ERR_OR_NULL(request))
11727 i915_gem_request_cancel(request);
11728 atomic_dec(&intel_crtc->unpin_work_count);
11729 mutex_unlock(&dev->struct_mutex);
11730 cleanup:
11731 crtc->primary->fb = old_fb;
11732 update_state_fb(crtc->primary);
11733
11734 drm_gem_object_unreference_unlocked(&obj->base);
11735 drm_framebuffer_unreference(work->old_fb);
11736
11737 spin_lock_irq(&dev->event_lock);
11738 intel_crtc->unpin_work = NULL;
11739 spin_unlock_irq(&dev->event_lock);
11740
11741 drm_crtc_vblank_put(crtc);
11742 free_work:
11743 kfree(work);
11744
11745 if (ret == -EIO) {
11746 struct drm_atomic_state *state;
11747 struct drm_plane_state *plane_state;
11748
11749 out_hang:
11750 state = drm_atomic_state_alloc(dev);
11751 if (!state)
11752 return -ENOMEM;
11753 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11754
11755 retry:
11756 plane_state = drm_atomic_get_plane_state(state, primary);
11757 ret = PTR_ERR_OR_ZERO(plane_state);
11758 if (!ret) {
11759 drm_atomic_set_fb_for_plane(plane_state, fb);
11760
11761 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11762 if (!ret)
11763 ret = drm_atomic_commit(state);
11764 }
11765
11766 if (ret == -EDEADLK) {
11767 drm_modeset_backoff(state->acquire_ctx);
11768 drm_atomic_state_clear(state);
11769 goto retry;
11770 }
11771
11772 if (ret)
11773 drm_atomic_state_free(state);
11774
11775 if (ret == 0 && event) {
11776 spin_lock_irq(&dev->event_lock);
11777 drm_send_vblank_event(dev, pipe, event);
11778 spin_unlock_irq(&dev->event_lock);
11779 }
11780 }
11781 return ret;
11782 }
11783
11784
11785 /**
11786 * intel_wm_need_update - Check whether watermarks need updating
11787 * @plane: drm plane
11788 * @state: new plane state
11789 *
11790 * Check current plane state versus the new one to determine whether
11791 * watermarks need to be recalculated.
11792 *
11793 * Returns true or false.
11794 */
11795 static bool intel_wm_need_update(struct drm_plane *plane,
11796 struct drm_plane_state *state)
11797 {
11798 struct intel_plane_state *new = to_intel_plane_state(state);
11799 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11800
11801 /* Update watermarks on tiling or size changes. */
11802 if (new->visible != cur->visible)
11803 return true;
11804
11805 if (!cur->base.fb || !new->base.fb)
11806 return false;
11807
11808 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11809 cur->base.rotation != new->base.rotation ||
11810 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11811 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11812 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11813 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11814 return true;
11815
11816 return false;
11817 }
11818
11819 static bool needs_scaling(struct intel_plane_state *state)
11820 {
11821 int src_w = drm_rect_width(&state->src) >> 16;
11822 int src_h = drm_rect_height(&state->src) >> 16;
11823 int dst_w = drm_rect_width(&state->dst);
11824 int dst_h = drm_rect_height(&state->dst);
11825
11826 return (src_w != dst_w || src_h != dst_h);
11827 }
11828
11829 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11830 struct drm_plane_state *plane_state)
11831 {
11832 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11833 struct drm_crtc *crtc = crtc_state->crtc;
11834 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11835 struct drm_plane *plane = plane_state->plane;
11836 struct drm_device *dev = crtc->dev;
11837 struct intel_plane_state *old_plane_state =
11838 to_intel_plane_state(plane->state);
11839 int idx = intel_crtc->base.base.id, ret;
11840 int i = drm_plane_index(plane);
11841 bool mode_changed = needs_modeset(crtc_state);
11842 bool was_crtc_enabled = crtc->state->active;
11843 bool is_crtc_enabled = crtc_state->active;
11844 bool turn_off, turn_on, visible, was_visible;
11845 struct drm_framebuffer *fb = plane_state->fb;
11846
11847 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11848 plane->type != DRM_PLANE_TYPE_CURSOR) {
11849 ret = skl_update_scaler_plane(
11850 to_intel_crtc_state(crtc_state),
11851 to_intel_plane_state(plane_state));
11852 if (ret)
11853 return ret;
11854 }
11855
11856 was_visible = old_plane_state->visible;
11857 visible = to_intel_plane_state(plane_state)->visible;
11858
11859 if (!was_crtc_enabled && WARN_ON(was_visible))
11860 was_visible = false;
11861
11862 /*
11863 * Visibility is calculated as if the crtc was on, but
11864 * after scaler setup everything depends on it being off
11865 * when the crtc isn't active.
11866 */
11867 if (!is_crtc_enabled)
11868 to_intel_plane_state(plane_state)->visible = visible = false;
11869
11870 if (!was_visible && !visible)
11871 return 0;
11872
11873 turn_off = was_visible && (!visible || mode_changed);
11874 turn_on = visible && (!was_visible || mode_changed);
11875
11876 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11877 plane->base.id, fb ? fb->base.id : -1);
11878
11879 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11880 plane->base.id, was_visible, visible,
11881 turn_off, turn_on, mode_changed);
11882
11883 if (turn_on || turn_off) {
11884 pipe_config->wm_changed = true;
11885
11886 /* must disable cxsr around plane enable/disable */
11887 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11888 if (is_crtc_enabled)
11889 intel_crtc->atomic.wait_vblank = true;
11890 pipe_config->disable_cxsr = true;
11891 }
11892 } else if (intel_wm_need_update(plane, plane_state)) {
11893 pipe_config->wm_changed = true;
11894 }
11895
11896 if (visible || was_visible)
11897 intel_crtc->atomic.fb_bits |=
11898 to_intel_plane(plane)->frontbuffer_bit;
11899
11900 switch (plane->type) {
11901 case DRM_PLANE_TYPE_PRIMARY:
11902 intel_crtc->atomic.pre_disable_primary = turn_off;
11903 intel_crtc->atomic.post_enable_primary = turn_on;
11904 intel_crtc->atomic.update_fbc = true;
11905
11906 if (turn_off) {
11907 /*
11908 * FIXME: Actually if we will still have any other
11909 * plane enabled on the pipe we could let IPS enabled
11910 * still, but for now lets consider that when we make
11911 * primary invisible by setting DSPCNTR to 0 on
11912 * update_primary_plane function IPS needs to be
11913 * disable.
11914 */
11915 intel_crtc->atomic.disable_ips = true;
11916 }
11917
11918 /*
11919 * BDW signals flip done immediately if the plane
11920 * is disabled, even if the plane enable is already
11921 * armed to occur at the next vblank :(
11922 */
11923 if (turn_on && IS_BROADWELL(dev))
11924 intel_crtc->atomic.wait_vblank = true;
11925
11926 break;
11927 case DRM_PLANE_TYPE_CURSOR:
11928 break;
11929 case DRM_PLANE_TYPE_OVERLAY:
11930 /*
11931 * WaCxSRDisabledForSpriteScaling:ivb
11932 *
11933 * cstate->update_wm was already set above, so this flag will
11934 * take effect when we commit and program watermarks.
11935 */
11936 if (IS_IVYBRIDGE(dev) &&
11937 needs_scaling(to_intel_plane_state(plane_state)) &&
11938 !needs_scaling(old_plane_state)) {
11939 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11940 } else if (turn_off && !mode_changed) {
11941 intel_crtc->atomic.wait_vblank = true;
11942 intel_crtc->atomic.update_sprite_watermarks |=
11943 1 << i;
11944 }
11945
11946 break;
11947 }
11948 return 0;
11949 }
11950
11951 static bool encoders_cloneable(const struct intel_encoder *a,
11952 const struct intel_encoder *b)
11953 {
11954 /* masks could be asymmetric, so check both ways */
11955 return a == b || (a->cloneable & (1 << b->type) &&
11956 b->cloneable & (1 << a->type));
11957 }
11958
11959 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11960 struct intel_crtc *crtc,
11961 struct intel_encoder *encoder)
11962 {
11963 struct intel_encoder *source_encoder;
11964 struct drm_connector *connector;
11965 struct drm_connector_state *connector_state;
11966 int i;
11967
11968 for_each_connector_in_state(state, connector, connector_state, i) {
11969 if (connector_state->crtc != &crtc->base)
11970 continue;
11971
11972 source_encoder =
11973 to_intel_encoder(connector_state->best_encoder);
11974 if (!encoders_cloneable(encoder, source_encoder))
11975 return false;
11976 }
11977
11978 return true;
11979 }
11980
11981 static bool check_encoder_cloning(struct drm_atomic_state *state,
11982 struct intel_crtc *crtc)
11983 {
11984 struct intel_encoder *encoder;
11985 struct drm_connector *connector;
11986 struct drm_connector_state *connector_state;
11987 int i;
11988
11989 for_each_connector_in_state(state, connector, connector_state, i) {
11990 if (connector_state->crtc != &crtc->base)
11991 continue;
11992
11993 encoder = to_intel_encoder(connector_state->best_encoder);
11994 if (!check_single_encoder_cloning(state, crtc, encoder))
11995 return false;
11996 }
11997
11998 return true;
11999 }
12000
12001 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12002 struct drm_crtc_state *crtc_state)
12003 {
12004 struct drm_device *dev = crtc->dev;
12005 struct drm_i915_private *dev_priv = dev->dev_private;
12006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12007 struct intel_crtc_state *pipe_config =
12008 to_intel_crtc_state(crtc_state);
12009 struct drm_atomic_state *state = crtc_state->state;
12010 int ret;
12011 bool mode_changed = needs_modeset(crtc_state);
12012
12013 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12014 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12015 return -EINVAL;
12016 }
12017
12018 if (mode_changed && !crtc_state->active)
12019 pipe_config->wm_changed = true;
12020
12021 if (mode_changed && crtc_state->enable &&
12022 dev_priv->display.crtc_compute_clock &&
12023 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12024 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12025 pipe_config);
12026 if (ret)
12027 return ret;
12028 }
12029
12030 ret = 0;
12031 if (dev_priv->display.compute_pipe_wm) {
12032 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12033 if (ret)
12034 return ret;
12035 }
12036
12037 if (INTEL_INFO(dev)->gen >= 9) {
12038 if (mode_changed)
12039 ret = skl_update_scaler_crtc(pipe_config);
12040
12041 if (!ret)
12042 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12043 pipe_config);
12044 }
12045
12046 return ret;
12047 }
12048
12049 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12050 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12051 .load_lut = intel_crtc_load_lut,
12052 .atomic_begin = intel_begin_crtc_commit,
12053 .atomic_flush = intel_finish_crtc_commit,
12054 .atomic_check = intel_crtc_atomic_check,
12055 };
12056
12057 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12058 {
12059 struct intel_connector *connector;
12060
12061 for_each_intel_connector(dev, connector) {
12062 if (connector->base.encoder) {
12063 connector->base.state->best_encoder =
12064 connector->base.encoder;
12065 connector->base.state->crtc =
12066 connector->base.encoder->crtc;
12067 } else {
12068 connector->base.state->best_encoder = NULL;
12069 connector->base.state->crtc = NULL;
12070 }
12071 }
12072 }
12073
12074 static void
12075 connected_sink_compute_bpp(struct intel_connector *connector,
12076 struct intel_crtc_state *pipe_config)
12077 {
12078 int bpp = pipe_config->pipe_bpp;
12079
12080 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12081 connector->base.base.id,
12082 connector->base.name);
12083
12084 /* Don't use an invalid EDID bpc value */
12085 if (connector->base.display_info.bpc &&
12086 connector->base.display_info.bpc * 3 < bpp) {
12087 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12088 bpp, connector->base.display_info.bpc*3);
12089 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12090 }
12091
12092 /* Clamp bpp to default limit on screens without EDID 1.4 */
12093 if (connector->base.display_info.bpc == 0) {
12094 int type = connector->base.connector_type;
12095 int clamp_bpp = 24;
12096
12097 /* Fall back to 18 bpp when DP sink capability is unknown. */
12098 if (type == DRM_MODE_CONNECTOR_DisplayPort ||
12099 type == DRM_MODE_CONNECTOR_eDP)
12100 clamp_bpp = 18;
12101
12102 if (bpp > clamp_bpp) {
12103 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of %d\n",
12104 bpp, clamp_bpp);
12105 pipe_config->pipe_bpp = clamp_bpp;
12106 }
12107 }
12108 }
12109
12110 static int
12111 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12112 struct intel_crtc_state *pipe_config)
12113 {
12114 struct drm_device *dev = crtc->base.dev;
12115 struct drm_atomic_state *state;
12116 struct drm_connector *connector;
12117 struct drm_connector_state *connector_state;
12118 int bpp, i;
12119
12120 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12121 bpp = 10*3;
12122 else if (INTEL_INFO(dev)->gen >= 5)
12123 bpp = 12*3;
12124 else
12125 bpp = 8*3;
12126
12127
12128 pipe_config->pipe_bpp = bpp;
12129
12130 state = pipe_config->base.state;
12131
12132 /* Clamp display bpp to EDID value */
12133 for_each_connector_in_state(state, connector, connector_state, i) {
12134 if (connector_state->crtc != &crtc->base)
12135 continue;
12136
12137 connected_sink_compute_bpp(to_intel_connector(connector),
12138 pipe_config);
12139 }
12140
12141 return bpp;
12142 }
12143
12144 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12145 {
12146 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12147 "type: 0x%x flags: 0x%x\n",
12148 mode->crtc_clock,
12149 mode->crtc_hdisplay, mode->crtc_hsync_start,
12150 mode->crtc_hsync_end, mode->crtc_htotal,
12151 mode->crtc_vdisplay, mode->crtc_vsync_start,
12152 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12153 }
12154
12155 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12156 struct intel_crtc_state *pipe_config,
12157 const char *context)
12158 {
12159 struct drm_device *dev = crtc->base.dev;
12160 struct drm_plane *plane;
12161 struct intel_plane *intel_plane;
12162 struct intel_plane_state *state;
12163 struct drm_framebuffer *fb;
12164
12165 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12166 context, pipe_config, pipe_name(crtc->pipe));
12167
12168 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12169 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12170 pipe_config->pipe_bpp, pipe_config->dither);
12171 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12172 pipe_config->has_pch_encoder,
12173 pipe_config->fdi_lanes,
12174 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12175 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12176 pipe_config->fdi_m_n.tu);
12177 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12178 pipe_config->has_dp_encoder,
12179 pipe_config->lane_count,
12180 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12181 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12182 pipe_config->dp_m_n.tu);
12183
12184 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12185 pipe_config->has_dp_encoder,
12186 pipe_config->lane_count,
12187 pipe_config->dp_m2_n2.gmch_m,
12188 pipe_config->dp_m2_n2.gmch_n,
12189 pipe_config->dp_m2_n2.link_m,
12190 pipe_config->dp_m2_n2.link_n,
12191 pipe_config->dp_m2_n2.tu);
12192
12193 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12194 pipe_config->has_audio,
12195 pipe_config->has_infoframe);
12196
12197 DRM_DEBUG_KMS("requested mode:\n");
12198 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12199 DRM_DEBUG_KMS("adjusted mode:\n");
12200 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12201 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12202 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12203 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12204 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12205 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12206 crtc->num_scalers,
12207 pipe_config->scaler_state.scaler_users,
12208 pipe_config->scaler_state.scaler_id);
12209 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12210 pipe_config->gmch_pfit.control,
12211 pipe_config->gmch_pfit.pgm_ratios,
12212 pipe_config->gmch_pfit.lvds_border_bits);
12213 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12214 pipe_config->pch_pfit.pos,
12215 pipe_config->pch_pfit.size,
12216 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12217 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12218 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12219
12220 if (IS_BROXTON(dev)) {
12221 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12222 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12223 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12224 pipe_config->ddi_pll_sel,
12225 pipe_config->dpll_hw_state.ebb0,
12226 pipe_config->dpll_hw_state.ebb4,
12227 pipe_config->dpll_hw_state.pll0,
12228 pipe_config->dpll_hw_state.pll1,
12229 pipe_config->dpll_hw_state.pll2,
12230 pipe_config->dpll_hw_state.pll3,
12231 pipe_config->dpll_hw_state.pll6,
12232 pipe_config->dpll_hw_state.pll8,
12233 pipe_config->dpll_hw_state.pll9,
12234 pipe_config->dpll_hw_state.pll10,
12235 pipe_config->dpll_hw_state.pcsdw12);
12236 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12237 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12238 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12239 pipe_config->ddi_pll_sel,
12240 pipe_config->dpll_hw_state.ctrl1,
12241 pipe_config->dpll_hw_state.cfgcr1,
12242 pipe_config->dpll_hw_state.cfgcr2);
12243 } else if (HAS_DDI(dev)) {
12244 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12245 pipe_config->ddi_pll_sel,
12246 pipe_config->dpll_hw_state.wrpll,
12247 pipe_config->dpll_hw_state.spll);
12248 } else {
12249 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12250 "fp0: 0x%x, fp1: 0x%x\n",
12251 pipe_config->dpll_hw_state.dpll,
12252 pipe_config->dpll_hw_state.dpll_md,
12253 pipe_config->dpll_hw_state.fp0,
12254 pipe_config->dpll_hw_state.fp1);
12255 }
12256
12257 DRM_DEBUG_KMS("planes on this crtc\n");
12258 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12259 intel_plane = to_intel_plane(plane);
12260 if (intel_plane->pipe != crtc->pipe)
12261 continue;
12262
12263 state = to_intel_plane_state(plane->state);
12264 fb = state->base.fb;
12265 if (!fb) {
12266 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12267 "disabled, scaler_id = %d\n",
12268 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12269 plane->base.id, intel_plane->pipe,
12270 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12271 drm_plane_index(plane), state->scaler_id);
12272 continue;
12273 }
12274
12275 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12276 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12277 plane->base.id, intel_plane->pipe,
12278 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12279 drm_plane_index(plane));
12280 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12281 fb->base.id, fb->width, fb->height, fb->pixel_format);
12282 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12283 state->scaler_id,
12284 state->src.x1 >> 16, state->src.y1 >> 16,
12285 drm_rect_width(&state->src) >> 16,
12286 drm_rect_height(&state->src) >> 16,
12287 state->dst.x1, state->dst.y1,
12288 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12289 }
12290 }
12291
12292 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12293 {
12294 struct drm_device *dev = state->dev;
12295 struct drm_connector *connector;
12296 unsigned int used_ports = 0;
12297
12298 /*
12299 * Walk the connector list instead of the encoder
12300 * list to detect the problem on ddi platforms
12301 * where there's just one encoder per digital port.
12302 */
12303 drm_for_each_connector(connector, dev) {
12304 struct drm_connector_state *connector_state;
12305 struct intel_encoder *encoder;
12306
12307 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12308 if (!connector_state)
12309 connector_state = connector->state;
12310
12311 if (!connector_state->best_encoder)
12312 continue;
12313
12314 encoder = to_intel_encoder(connector_state->best_encoder);
12315
12316 WARN_ON(!connector_state->crtc);
12317
12318 switch (encoder->type) {
12319 unsigned int port_mask;
12320 case INTEL_OUTPUT_UNKNOWN:
12321 if (WARN_ON(!HAS_DDI(dev)))
12322 break;
12323 case INTEL_OUTPUT_DISPLAYPORT:
12324 case INTEL_OUTPUT_HDMI:
12325 case INTEL_OUTPUT_EDP:
12326 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12327
12328 /* the same port mustn't appear more than once */
12329 if (used_ports & port_mask)
12330 return false;
12331
12332 used_ports |= port_mask;
12333 default:
12334 break;
12335 }
12336 }
12337
12338 return true;
12339 }
12340
12341 static void
12342 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12343 {
12344 struct drm_crtc_state tmp_state;
12345 struct intel_crtc_scaler_state scaler_state;
12346 struct intel_dpll_hw_state dpll_hw_state;
12347 enum intel_dpll_id shared_dpll;
12348 uint32_t ddi_pll_sel;
12349 bool force_thru;
12350
12351 /* FIXME: before the switch to atomic started, a new pipe_config was
12352 * kzalloc'd. Code that depends on any field being zero should be
12353 * fixed, so that the crtc_state can be safely duplicated. For now,
12354 * only fields that are know to not cause problems are preserved. */
12355
12356 tmp_state = crtc_state->base;
12357 scaler_state = crtc_state->scaler_state;
12358 shared_dpll = crtc_state->shared_dpll;
12359 dpll_hw_state = crtc_state->dpll_hw_state;
12360 ddi_pll_sel = crtc_state->ddi_pll_sel;
12361 force_thru = crtc_state->pch_pfit.force_thru;
12362
12363 memset(crtc_state, 0, sizeof *crtc_state);
12364
12365 crtc_state->base = tmp_state;
12366 crtc_state->scaler_state = scaler_state;
12367 crtc_state->shared_dpll = shared_dpll;
12368 crtc_state->dpll_hw_state = dpll_hw_state;
12369 crtc_state->ddi_pll_sel = ddi_pll_sel;
12370 crtc_state->pch_pfit.force_thru = force_thru;
12371 }
12372
12373 static int
12374 intel_modeset_pipe_config(struct drm_crtc *crtc,
12375 struct intel_crtc_state *pipe_config)
12376 {
12377 struct drm_atomic_state *state = pipe_config->base.state;
12378 struct intel_encoder *encoder;
12379 struct drm_connector *connector;
12380 struct drm_connector_state *connector_state;
12381 int base_bpp, ret = -EINVAL;
12382 int i;
12383 bool retry = true;
12384
12385 clear_intel_crtc_state(pipe_config);
12386
12387 pipe_config->cpu_transcoder =
12388 (enum transcoder) to_intel_crtc(crtc)->pipe;
12389
12390 /*
12391 * Sanitize sync polarity flags based on requested ones. If neither
12392 * positive or negative polarity is requested, treat this as meaning
12393 * negative polarity.
12394 */
12395 if (!(pipe_config->base.adjusted_mode.flags &
12396 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12397 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12398
12399 if (!(pipe_config->base.adjusted_mode.flags &
12400 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12401 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12402
12403 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12404 pipe_config);
12405 if (base_bpp < 0)
12406 goto fail;
12407
12408 /*
12409 * Determine the real pipe dimensions. Note that stereo modes can
12410 * increase the actual pipe size due to the frame doubling and
12411 * insertion of additional space for blanks between the frame. This
12412 * is stored in the crtc timings. We use the requested mode to do this
12413 * computation to clearly distinguish it from the adjusted mode, which
12414 * can be changed by the connectors in the below retry loop.
12415 */
12416 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12417 &pipe_config->pipe_src_w,
12418 &pipe_config->pipe_src_h);
12419
12420 encoder_retry:
12421 /* Ensure the port clock defaults are reset when retrying. */
12422 pipe_config->port_clock = 0;
12423 pipe_config->pixel_multiplier = 1;
12424
12425 /* Fill in default crtc timings, allow encoders to overwrite them. */
12426 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12427 CRTC_STEREO_DOUBLE);
12428
12429 /* Pass our mode to the connectors and the CRTC to give them a chance to
12430 * adjust it according to limitations or connector properties, and also
12431 * a chance to reject the mode entirely.
12432 */
12433 for_each_connector_in_state(state, connector, connector_state, i) {
12434 if (connector_state->crtc != crtc)
12435 continue;
12436
12437 encoder = to_intel_encoder(connector_state->best_encoder);
12438
12439 if (!(encoder->compute_config(encoder, pipe_config))) {
12440 DRM_DEBUG_KMS("Encoder config failure\n");
12441 goto fail;
12442 }
12443 }
12444
12445 /* Set default port clock if not overwritten by the encoder. Needs to be
12446 * done afterwards in case the encoder adjusts the mode. */
12447 if (!pipe_config->port_clock)
12448 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12449 * pipe_config->pixel_multiplier;
12450
12451 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12452 if (ret < 0) {
12453 DRM_DEBUG_KMS("CRTC fixup failed\n");
12454 goto fail;
12455 }
12456
12457 if (ret == RETRY) {
12458 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12459 ret = -EINVAL;
12460 goto fail;
12461 }
12462
12463 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12464 retry = false;
12465 goto encoder_retry;
12466 }
12467
12468 /* Dithering seems to not pass-through bits correctly when it should, so
12469 * only enable it on 6bpc panels. */
12470 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12471 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12472 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12473
12474 fail:
12475 return ret;
12476 }
12477
12478 static void
12479 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12480 {
12481 struct drm_crtc *crtc;
12482 struct drm_crtc_state *crtc_state;
12483 int i;
12484
12485 /* Double check state. */
12486 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12487 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12488
12489 /* Update hwmode for vblank functions */
12490 if (crtc->state->active)
12491 crtc->hwmode = crtc->state->adjusted_mode;
12492 else
12493 crtc->hwmode.crtc_clock = 0;
12494
12495 /*
12496 * Update legacy state to satisfy fbc code. This can
12497 * be removed when fbc uses the atomic state.
12498 */
12499 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12500 struct drm_plane_state *plane_state = crtc->primary->state;
12501
12502 crtc->primary->fb = plane_state->fb;
12503 crtc->x = plane_state->src_x >> 16;
12504 crtc->y = plane_state->src_y >> 16;
12505 }
12506 }
12507 }
12508
12509 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12510 {
12511 int diff;
12512
12513 if (clock1 == clock2)
12514 return true;
12515
12516 if (!clock1 || !clock2)
12517 return false;
12518
12519 diff = abs(clock1 - clock2);
12520
12521 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12522 return true;
12523
12524 return false;
12525 }
12526
12527 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12528 list_for_each_entry((intel_crtc), \
12529 &(dev)->mode_config.crtc_list, \
12530 base.head) \
12531 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12532
12533 static bool
12534 intel_compare_m_n(unsigned int m, unsigned int n,
12535 unsigned int m2, unsigned int n2,
12536 bool exact)
12537 {
12538 if (m == m2 && n == n2)
12539 return true;
12540
12541 if (exact || !m || !n || !m2 || !n2)
12542 return false;
12543
12544 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12545
12546 if (n > n2) {
12547 while (n > n2) {
12548 m2 <<= 1;
12549 n2 <<= 1;
12550 }
12551 } else if (n < n2) {
12552 while (n < n2) {
12553 m <<= 1;
12554 n <<= 1;
12555 }
12556 }
12557
12558 if (n != n2)
12559 return false;
12560
12561 return intel_fuzzy_clock_check(m, m2);
12562 }
12563
12564 static bool
12565 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12566 struct intel_link_m_n *m2_n2,
12567 bool adjust)
12568 {
12569 if (m_n->tu == m2_n2->tu &&
12570 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12571 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12572 intel_compare_m_n(m_n->link_m, m_n->link_n,
12573 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12574 if (adjust)
12575 *m2_n2 = *m_n;
12576
12577 return true;
12578 }
12579
12580 return false;
12581 }
12582
12583 static bool
12584 intel_pipe_config_compare(struct drm_device *dev,
12585 struct intel_crtc_state *current_config,
12586 struct intel_crtc_state *pipe_config,
12587 bool adjust)
12588 {
12589 bool ret = true;
12590
12591 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12592 do { \
12593 if (!adjust) \
12594 DRM_ERROR(fmt, ##__VA_ARGS__); \
12595 else \
12596 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12597 } while (0)
12598
12599 #define PIPE_CONF_CHECK_X(name) \
12600 if (current_config->name != pipe_config->name) { \
12601 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12602 "(expected 0x%08x, found 0x%08x)\n", \
12603 current_config->name, \
12604 pipe_config->name); \
12605 ret = false; \
12606 }
12607
12608 #define PIPE_CONF_CHECK_I(name) \
12609 if (current_config->name != pipe_config->name) { \
12610 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12611 "(expected %i, found %i)\n", \
12612 current_config->name, \
12613 pipe_config->name); \
12614 ret = false; \
12615 }
12616
12617 #define PIPE_CONF_CHECK_M_N(name) \
12618 if (!intel_compare_link_m_n(&current_config->name, \
12619 &pipe_config->name,\
12620 adjust)) { \
12621 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12622 "(expected tu %i gmch %i/%i link %i/%i, " \
12623 "found tu %i, gmch %i/%i link %i/%i)\n", \
12624 current_config->name.tu, \
12625 current_config->name.gmch_m, \
12626 current_config->name.gmch_n, \
12627 current_config->name.link_m, \
12628 current_config->name.link_n, \
12629 pipe_config->name.tu, \
12630 pipe_config->name.gmch_m, \
12631 pipe_config->name.gmch_n, \
12632 pipe_config->name.link_m, \
12633 pipe_config->name.link_n); \
12634 ret = false; \
12635 }
12636
12637 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12638 if (!intel_compare_link_m_n(&current_config->name, \
12639 &pipe_config->name, adjust) && \
12640 !intel_compare_link_m_n(&current_config->alt_name, \
12641 &pipe_config->name, adjust)) { \
12642 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12643 "(expected tu %i gmch %i/%i link %i/%i, " \
12644 "or tu %i gmch %i/%i link %i/%i, " \
12645 "found tu %i, gmch %i/%i link %i/%i)\n", \
12646 current_config->name.tu, \
12647 current_config->name.gmch_m, \
12648 current_config->name.gmch_n, \
12649 current_config->name.link_m, \
12650 current_config->name.link_n, \
12651 current_config->alt_name.tu, \
12652 current_config->alt_name.gmch_m, \
12653 current_config->alt_name.gmch_n, \
12654 current_config->alt_name.link_m, \
12655 current_config->alt_name.link_n, \
12656 pipe_config->name.tu, \
12657 pipe_config->name.gmch_m, \
12658 pipe_config->name.gmch_n, \
12659 pipe_config->name.link_m, \
12660 pipe_config->name.link_n); \
12661 ret = false; \
12662 }
12663
12664 /* This is required for BDW+ where there is only one set of registers for
12665 * switching between high and low RR.
12666 * This macro can be used whenever a comparison has to be made between one
12667 * hw state and multiple sw state variables.
12668 */
12669 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12670 if ((current_config->name != pipe_config->name) && \
12671 (current_config->alt_name != pipe_config->name)) { \
12672 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12673 "(expected %i or %i, found %i)\n", \
12674 current_config->name, \
12675 current_config->alt_name, \
12676 pipe_config->name); \
12677 ret = false; \
12678 }
12679
12680 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12681 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12682 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12683 "(expected %i, found %i)\n", \
12684 current_config->name & (mask), \
12685 pipe_config->name & (mask)); \
12686 ret = false; \
12687 }
12688
12689 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12690 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12691 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12692 "(expected %i, found %i)\n", \
12693 current_config->name, \
12694 pipe_config->name); \
12695 ret = false; \
12696 }
12697
12698 #define PIPE_CONF_QUIRK(quirk) \
12699 ((current_config->quirks | pipe_config->quirks) & (quirk))
12700
12701 PIPE_CONF_CHECK_I(cpu_transcoder);
12702
12703 PIPE_CONF_CHECK_I(has_pch_encoder);
12704 PIPE_CONF_CHECK_I(fdi_lanes);
12705 PIPE_CONF_CHECK_M_N(fdi_m_n);
12706
12707 PIPE_CONF_CHECK_I(has_dp_encoder);
12708 PIPE_CONF_CHECK_I(lane_count);
12709
12710 if (INTEL_INFO(dev)->gen < 8) {
12711 PIPE_CONF_CHECK_M_N(dp_m_n);
12712
12713 if (current_config->has_drrs)
12714 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12715 } else
12716 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12717
12718 PIPE_CONF_CHECK_I(has_dsi_encoder);
12719
12720 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12721 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12722 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12723 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12724 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12725 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12726
12727 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12728 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12729 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12730 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12731 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12732 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12733
12734 PIPE_CONF_CHECK_I(pixel_multiplier);
12735 PIPE_CONF_CHECK_I(has_hdmi_sink);
12736 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12737 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12738 PIPE_CONF_CHECK_I(limited_color_range);
12739 PIPE_CONF_CHECK_I(has_infoframe);
12740
12741 PIPE_CONF_CHECK_I(has_audio);
12742
12743 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12744 DRM_MODE_FLAG_INTERLACE);
12745
12746 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12747 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12748 DRM_MODE_FLAG_PHSYNC);
12749 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12750 DRM_MODE_FLAG_NHSYNC);
12751 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12752 DRM_MODE_FLAG_PVSYNC);
12753 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12754 DRM_MODE_FLAG_NVSYNC);
12755 }
12756
12757 PIPE_CONF_CHECK_X(gmch_pfit.control);
12758 /* pfit ratios are autocomputed by the hw on gen4+ */
12759 if (INTEL_INFO(dev)->gen < 4)
12760 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12761 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12762
12763 if (!adjust) {
12764 PIPE_CONF_CHECK_I(pipe_src_w);
12765 PIPE_CONF_CHECK_I(pipe_src_h);
12766
12767 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12768 if (current_config->pch_pfit.enabled) {
12769 PIPE_CONF_CHECK_X(pch_pfit.pos);
12770 PIPE_CONF_CHECK_X(pch_pfit.size);
12771 }
12772
12773 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12774 }
12775
12776 /* BDW+ don't expose a synchronous way to read the state */
12777 if (IS_HASWELL(dev))
12778 PIPE_CONF_CHECK_I(ips_enabled);
12779
12780 PIPE_CONF_CHECK_I(double_wide);
12781
12782 PIPE_CONF_CHECK_X(ddi_pll_sel);
12783
12784 PIPE_CONF_CHECK_I(shared_dpll);
12785 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12786 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12787 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12788 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12789 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12790 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12791 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12792 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12793 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12794
12795 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12796 PIPE_CONF_CHECK_I(pipe_bpp);
12797
12798 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12799 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12800
12801 #undef PIPE_CONF_CHECK_X
12802 #undef PIPE_CONF_CHECK_I
12803 #undef PIPE_CONF_CHECK_I_ALT
12804 #undef PIPE_CONF_CHECK_FLAGS
12805 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12806 #undef PIPE_CONF_QUIRK
12807 #undef INTEL_ERR_OR_DBG_KMS
12808
12809 return ret;
12810 }
12811
12812 static void check_wm_state(struct drm_device *dev)
12813 {
12814 struct drm_i915_private *dev_priv = dev->dev_private;
12815 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12816 struct intel_crtc *intel_crtc;
12817 int plane;
12818
12819 if (INTEL_INFO(dev)->gen < 9)
12820 return;
12821
12822 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12823 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12824
12825 for_each_intel_crtc(dev, intel_crtc) {
12826 struct skl_ddb_entry *hw_entry, *sw_entry;
12827 const enum pipe pipe = intel_crtc->pipe;
12828
12829 if (!intel_crtc->active)
12830 continue;
12831
12832 /* planes */
12833 for_each_plane(dev_priv, pipe, plane) {
12834 hw_entry = &hw_ddb.plane[pipe][plane];
12835 sw_entry = &sw_ddb->plane[pipe][plane];
12836
12837 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12838 continue;
12839
12840 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12841 "(expected (%u,%u), found (%u,%u))\n",
12842 pipe_name(pipe), plane + 1,
12843 sw_entry->start, sw_entry->end,
12844 hw_entry->start, hw_entry->end);
12845 }
12846
12847 /* cursor */
12848 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12849 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12850
12851 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12852 continue;
12853
12854 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12855 "(expected (%u,%u), found (%u,%u))\n",
12856 pipe_name(pipe),
12857 sw_entry->start, sw_entry->end,
12858 hw_entry->start, hw_entry->end);
12859 }
12860 }
12861
12862 static void
12863 check_connector_state(struct drm_device *dev,
12864 struct drm_atomic_state *old_state)
12865 {
12866 struct drm_connector_state *old_conn_state;
12867 struct drm_connector *connector;
12868 int i;
12869
12870 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12871 struct drm_encoder *encoder = connector->encoder;
12872 struct drm_connector_state *state = connector->state;
12873
12874 /* This also checks the encoder/connector hw state with the
12875 * ->get_hw_state callbacks. */
12876 intel_connector_check_state(to_intel_connector(connector));
12877
12878 I915_STATE_WARN(state->best_encoder != encoder,
12879 "connector's atomic encoder doesn't match legacy encoder\n");
12880 }
12881 }
12882
12883 static void
12884 check_encoder_state(struct drm_device *dev)
12885 {
12886 struct intel_encoder *encoder;
12887 struct intel_connector *connector;
12888
12889 for_each_intel_encoder(dev, encoder) {
12890 bool enabled = false;
12891 enum pipe pipe;
12892
12893 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12894 encoder->base.base.id,
12895 encoder->base.name);
12896
12897 for_each_intel_connector(dev, connector) {
12898 if (connector->base.state->best_encoder != &encoder->base)
12899 continue;
12900 enabled = true;
12901
12902 I915_STATE_WARN(connector->base.state->crtc !=
12903 encoder->base.crtc,
12904 "connector's crtc doesn't match encoder crtc\n");
12905 }
12906
12907 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12908 "encoder's enabled state mismatch "
12909 "(expected %i, found %i)\n",
12910 !!encoder->base.crtc, enabled);
12911
12912 if (!encoder->base.crtc) {
12913 bool active;
12914
12915 active = encoder->get_hw_state(encoder, &pipe);
12916 I915_STATE_WARN(active,
12917 "encoder detached but still enabled on pipe %c.\n",
12918 pipe_name(pipe));
12919 }
12920 }
12921 }
12922
12923 static void
12924 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12925 {
12926 struct drm_i915_private *dev_priv = dev->dev_private;
12927 struct intel_encoder *encoder;
12928 struct drm_crtc_state *old_crtc_state;
12929 struct drm_crtc *crtc;
12930 int i;
12931
12932 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12934 struct intel_crtc_state *pipe_config, *sw_config;
12935 bool active;
12936
12937 if (!needs_modeset(crtc->state) &&
12938 !to_intel_crtc_state(crtc->state)->update_pipe)
12939 continue;
12940
12941 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12942 pipe_config = to_intel_crtc_state(old_crtc_state);
12943 memset(pipe_config, 0, sizeof(*pipe_config));
12944 pipe_config->base.crtc = crtc;
12945 pipe_config->base.state = old_state;
12946
12947 DRM_DEBUG_KMS("[CRTC:%d]\n",
12948 crtc->base.id);
12949
12950 active = dev_priv->display.get_pipe_config(intel_crtc,
12951 pipe_config);
12952
12953 /* hw state is inconsistent with the pipe quirk */
12954 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12955 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12956 active = crtc->state->active;
12957
12958 I915_STATE_WARN(crtc->state->active != active,
12959 "crtc active state doesn't match with hw state "
12960 "(expected %i, found %i)\n", crtc->state->active, active);
12961
12962 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12963 "transitional active state does not match atomic hw state "
12964 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12965
12966 for_each_encoder_on_crtc(dev, crtc, encoder) {
12967 enum pipe pipe;
12968
12969 active = encoder->get_hw_state(encoder, &pipe);
12970 I915_STATE_WARN(active != crtc->state->active,
12971 "[ENCODER:%i] active %i with crtc active %i\n",
12972 encoder->base.base.id, active, crtc->state->active);
12973
12974 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12975 "Encoder connected to wrong pipe %c\n",
12976 pipe_name(pipe));
12977
12978 if (active)
12979 encoder->get_config(encoder, pipe_config);
12980 }
12981
12982 if (!crtc->state->active)
12983 continue;
12984
12985 sw_config = to_intel_crtc_state(crtc->state);
12986 if (!intel_pipe_config_compare(dev, sw_config,
12987 pipe_config, false)) {
12988 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12989 intel_dump_pipe_config(intel_crtc, pipe_config,
12990 "[hw state]");
12991 intel_dump_pipe_config(intel_crtc, sw_config,
12992 "[sw state]");
12993 }
12994 }
12995 }
12996
12997 static void
12998 check_shared_dpll_state(struct drm_device *dev)
12999 {
13000 struct drm_i915_private *dev_priv = dev->dev_private;
13001 struct intel_crtc *crtc;
13002 struct intel_dpll_hw_state dpll_hw_state;
13003 int i;
13004
13005 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13006 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13007 int enabled_crtcs = 0, active_crtcs = 0;
13008 bool active;
13009
13010 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13011
13012 DRM_DEBUG_KMS("%s\n", pll->name);
13013
13014 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13015
13016 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13017 "more active pll users than references: %i vs %i\n",
13018 pll->active, hweight32(pll->config.crtc_mask));
13019 I915_STATE_WARN(pll->active && !pll->on,
13020 "pll in active use but not on in sw tracking\n");
13021 I915_STATE_WARN(pll->on && !pll->active,
13022 "pll in on but not on in use in sw tracking\n");
13023 I915_STATE_WARN(pll->on != active,
13024 "pll on state mismatch (expected %i, found %i)\n",
13025 pll->on, active);
13026
13027 for_each_intel_crtc(dev, crtc) {
13028 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13029 enabled_crtcs++;
13030 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13031 active_crtcs++;
13032 }
13033 I915_STATE_WARN(pll->active != active_crtcs,
13034 "pll active crtcs mismatch (expected %i, found %i)\n",
13035 pll->active, active_crtcs);
13036 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13037 "pll enabled crtcs mismatch (expected %i, found %i)\n",
13038 hweight32(pll->config.crtc_mask), enabled_crtcs);
13039
13040 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13041 sizeof(dpll_hw_state)),
13042 "pll hw state mismatch\n");
13043 }
13044 }
13045
13046 static void
13047 intel_modeset_check_state(struct drm_device *dev,
13048 struct drm_atomic_state *old_state)
13049 {
13050 check_wm_state(dev);
13051 check_connector_state(dev, old_state);
13052 check_encoder_state(dev);
13053 check_crtc_state(dev, old_state);
13054 check_shared_dpll_state(dev);
13055 }
13056
13057 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13058 int dotclock)
13059 {
13060 /*
13061 * FDI already provided one idea for the dotclock.
13062 * Yell if the encoder disagrees.
13063 */
13064 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13065 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13066 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13067 }
13068
13069 static void update_scanline_offset(struct intel_crtc *crtc)
13070 {
13071 struct drm_device *dev = crtc->base.dev;
13072
13073 /*
13074 * The scanline counter increments at the leading edge of hsync.
13075 *
13076 * On most platforms it starts counting from vtotal-1 on the
13077 * first active line. That means the scanline counter value is
13078 * always one less than what we would expect. Ie. just after
13079 * start of vblank, which also occurs at start of hsync (on the
13080 * last active line), the scanline counter will read vblank_start-1.
13081 *
13082 * On gen2 the scanline counter starts counting from 1 instead
13083 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13084 * to keep the value positive), instead of adding one.
13085 *
13086 * On HSW+ the behaviour of the scanline counter depends on the output
13087 * type. For DP ports it behaves like most other platforms, but on HDMI
13088 * there's an extra 1 line difference. So we need to add two instead of
13089 * one to the value.
13090 */
13091 if (IS_GEN2(dev)) {
13092 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13093 int vtotal;
13094
13095 vtotal = adjusted_mode->crtc_vtotal;
13096 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13097 vtotal /= 2;
13098
13099 crtc->scanline_offset = vtotal - 1;
13100 } else if (HAS_DDI(dev) &&
13101 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13102 crtc->scanline_offset = 2;
13103 } else
13104 crtc->scanline_offset = 1;
13105 }
13106
13107 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13108 {
13109 struct drm_device *dev = state->dev;
13110 struct drm_i915_private *dev_priv = to_i915(dev);
13111 struct intel_shared_dpll_config *shared_dpll = NULL;
13112 struct intel_crtc *intel_crtc;
13113 struct intel_crtc_state *intel_crtc_state;
13114 struct drm_crtc *crtc;
13115 struct drm_crtc_state *crtc_state;
13116 int i;
13117
13118 if (!dev_priv->display.crtc_compute_clock)
13119 return;
13120
13121 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13122 int dpll;
13123
13124 intel_crtc = to_intel_crtc(crtc);
13125 intel_crtc_state = to_intel_crtc_state(crtc_state);
13126 dpll = intel_crtc_state->shared_dpll;
13127
13128 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13129 continue;
13130
13131 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13132
13133 if (!shared_dpll)
13134 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13135
13136 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13137 }
13138 }
13139
13140 /*
13141 * This implements the workaround described in the "notes" section of the mode
13142 * set sequence documentation. When going from no pipes or single pipe to
13143 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13144 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13145 */
13146 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13147 {
13148 struct drm_crtc_state *crtc_state;
13149 struct intel_crtc *intel_crtc;
13150 struct drm_crtc *crtc;
13151 struct intel_crtc_state *first_crtc_state = NULL;
13152 struct intel_crtc_state *other_crtc_state = NULL;
13153 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13154 int i;
13155
13156 /* look at all crtc's that are going to be enabled in during modeset */
13157 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13158 intel_crtc = to_intel_crtc(crtc);
13159
13160 if (!crtc_state->active || !needs_modeset(crtc_state))
13161 continue;
13162
13163 if (first_crtc_state) {
13164 other_crtc_state = to_intel_crtc_state(crtc_state);
13165 break;
13166 } else {
13167 first_crtc_state = to_intel_crtc_state(crtc_state);
13168 first_pipe = intel_crtc->pipe;
13169 }
13170 }
13171
13172 /* No workaround needed? */
13173 if (!first_crtc_state)
13174 return 0;
13175
13176 /* w/a possibly needed, check how many crtc's are already enabled. */
13177 for_each_intel_crtc(state->dev, intel_crtc) {
13178 struct intel_crtc_state *pipe_config;
13179
13180 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13181 if (IS_ERR(pipe_config))
13182 return PTR_ERR(pipe_config);
13183
13184 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13185
13186 if (!pipe_config->base.active ||
13187 needs_modeset(&pipe_config->base))
13188 continue;
13189
13190 /* 2 or more enabled crtcs means no need for w/a */
13191 if (enabled_pipe != INVALID_PIPE)
13192 return 0;
13193
13194 enabled_pipe = intel_crtc->pipe;
13195 }
13196
13197 if (enabled_pipe != INVALID_PIPE)
13198 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13199 else if (other_crtc_state)
13200 other_crtc_state->hsw_workaround_pipe = first_pipe;
13201
13202 return 0;
13203 }
13204
13205 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13206 {
13207 struct drm_crtc *crtc;
13208 struct drm_crtc_state *crtc_state;
13209 int ret = 0;
13210
13211 /* add all active pipes to the state */
13212 for_each_crtc(state->dev, crtc) {
13213 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13214 if (IS_ERR(crtc_state))
13215 return PTR_ERR(crtc_state);
13216
13217 if (!crtc_state->active || needs_modeset(crtc_state))
13218 continue;
13219
13220 crtc_state->mode_changed = true;
13221
13222 ret = drm_atomic_add_affected_connectors(state, crtc);
13223 if (ret)
13224 break;
13225
13226 ret = drm_atomic_add_affected_planes(state, crtc);
13227 if (ret)
13228 break;
13229 }
13230
13231 return ret;
13232 }
13233
13234 static int intel_modeset_checks(struct drm_atomic_state *state)
13235 {
13236 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13237 struct drm_i915_private *dev_priv = state->dev->dev_private;
13238 struct drm_crtc *crtc;
13239 struct drm_crtc_state *crtc_state;
13240 int ret = 0, i;
13241
13242 if (!check_digital_port_conflicts(state)) {
13243 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13244 return -EINVAL;
13245 }
13246
13247 intel_state->modeset = true;
13248 intel_state->active_crtcs = dev_priv->active_crtcs;
13249
13250 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13251 if (crtc_state->active)
13252 intel_state->active_crtcs |= 1 << i;
13253 else
13254 intel_state->active_crtcs &= ~(1 << i);
13255 }
13256
13257 /*
13258 * See if the config requires any additional preparation, e.g.
13259 * to adjust global state with pipes off. We need to do this
13260 * here so we can get the modeset_pipe updated config for the new
13261 * mode set on this crtc. For other crtcs we need to use the
13262 * adjusted_mode bits in the crtc directly.
13263 */
13264 if (dev_priv->display.modeset_calc_cdclk) {
13265 ret = dev_priv->display.modeset_calc_cdclk(state);
13266
13267 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13268 ret = intel_modeset_all_pipes(state);
13269
13270 if (ret < 0)
13271 return ret;
13272 } else
13273 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13274
13275 intel_modeset_clear_plls(state);
13276
13277 if (IS_HASWELL(dev_priv))
13278 return haswell_mode_set_planes_workaround(state);
13279
13280 return 0;
13281 }
13282
13283 /*
13284 * Handle calculation of various watermark data at the end of the atomic check
13285 * phase. The code here should be run after the per-crtc and per-plane 'check'
13286 * handlers to ensure that all derived state has been updated.
13287 */
13288 static void calc_watermark_data(struct drm_atomic_state *state)
13289 {
13290 struct drm_device *dev = state->dev;
13291 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13292 struct drm_crtc *crtc;
13293 struct drm_crtc_state *cstate;
13294 struct drm_plane *plane;
13295 struct drm_plane_state *pstate;
13296
13297 /*
13298 * Calculate watermark configuration details now that derived
13299 * plane/crtc state is all properly updated.
13300 */
13301 drm_for_each_crtc(crtc, dev) {
13302 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13303 crtc->state;
13304
13305 if (cstate->active)
13306 intel_state->wm_config.num_pipes_active++;
13307 }
13308 drm_for_each_legacy_plane(plane, dev) {
13309 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13310 plane->state;
13311
13312 if (!to_intel_plane_state(pstate)->visible)
13313 continue;
13314
13315 intel_state->wm_config.sprites_enabled = true;
13316 if (pstate->crtc_w != pstate->src_w >> 16 ||
13317 pstate->crtc_h != pstate->src_h >> 16)
13318 intel_state->wm_config.sprites_scaled = true;
13319 }
13320 }
13321
13322 /**
13323 * intel_atomic_check - validate state object
13324 * @dev: drm device
13325 * @state: state to validate
13326 */
13327 static int intel_atomic_check(struct drm_device *dev,
13328 struct drm_atomic_state *state)
13329 {
13330 struct drm_i915_private *dev_priv = to_i915(dev);
13331 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13332 struct drm_crtc *crtc;
13333 struct drm_crtc_state *crtc_state;
13334 int ret, i;
13335 bool any_ms = false;
13336
13337 ret = drm_atomic_helper_check_modeset(dev, state);
13338 if (ret)
13339 return ret;
13340
13341 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13342 struct intel_crtc_state *pipe_config =
13343 to_intel_crtc_state(crtc_state);
13344
13345 memset(&to_intel_crtc(crtc)->atomic, 0,
13346 sizeof(struct intel_crtc_atomic_commit));
13347
13348 /* Catch I915_MODE_FLAG_INHERITED */
13349 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13350 crtc_state->mode_changed = true;
13351
13352 if (!crtc_state->enable) {
13353 if (needs_modeset(crtc_state))
13354 any_ms = true;
13355 continue;
13356 }
13357
13358 if (!needs_modeset(crtc_state))
13359 continue;
13360
13361 /* FIXME: For only active_changed we shouldn't need to do any
13362 * state recomputation at all. */
13363
13364 ret = drm_atomic_add_affected_connectors(state, crtc);
13365 if (ret)
13366 return ret;
13367
13368 ret = intel_modeset_pipe_config(crtc, pipe_config);
13369 if (ret)
13370 return ret;
13371
13372 if (i915.fastboot &&
13373 intel_pipe_config_compare(dev,
13374 to_intel_crtc_state(crtc->state),
13375 pipe_config, true)) {
13376 crtc_state->mode_changed = false;
13377 to_intel_crtc_state(crtc_state)->update_pipe = true;
13378 }
13379
13380 if (needs_modeset(crtc_state)) {
13381 any_ms = true;
13382
13383 ret = drm_atomic_add_affected_planes(state, crtc);
13384 if (ret)
13385 return ret;
13386 }
13387
13388 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13389 needs_modeset(crtc_state) ?
13390 "[modeset]" : "[fastset]");
13391 }
13392
13393 if (any_ms) {
13394 ret = intel_modeset_checks(state);
13395
13396 if (ret)
13397 return ret;
13398 } else
13399 intel_state->cdclk = dev_priv->cdclk_freq;
13400
13401 ret = drm_atomic_helper_check_planes(dev, state);
13402 if (ret)
13403 return ret;
13404
13405 intel_fbc_choose_crtc(dev_priv, state);
13406 calc_watermark_data(state);
13407
13408 return 0;
13409 }
13410
13411 static int intel_atomic_prepare_commit(struct drm_device *dev,
13412 struct drm_atomic_state *state,
13413 bool async)
13414 {
13415 struct drm_i915_private *dev_priv = dev->dev_private;
13416 struct drm_plane_state *plane_state;
13417 struct drm_crtc_state *crtc_state;
13418 struct drm_plane *plane;
13419 struct drm_crtc *crtc;
13420 int i, ret;
13421
13422 if (async) {
13423 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13424 return -EINVAL;
13425 }
13426
13427 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13428 ret = intel_crtc_wait_for_pending_flips(crtc);
13429 if (ret)
13430 return ret;
13431
13432 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13433 flush_workqueue(dev_priv->wq);
13434 }
13435
13436 ret = mutex_lock_interruptible(&dev->struct_mutex);
13437 if (ret)
13438 return ret;
13439
13440 ret = drm_atomic_helper_prepare_planes(dev, state);
13441 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13442 u32 reset_counter;
13443
13444 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13445 mutex_unlock(&dev->struct_mutex);
13446
13447 for_each_plane_in_state(state, plane, plane_state, i) {
13448 struct intel_plane_state *intel_plane_state =
13449 to_intel_plane_state(plane_state);
13450
13451 if (!intel_plane_state->wait_req)
13452 continue;
13453
13454 ret = __i915_wait_request(intel_plane_state->wait_req,
13455 reset_counter, true,
13456 NULL, NULL);
13457
13458 /* Swallow -EIO errors to allow updates during hw lockup. */
13459 if (ret == -EIO)
13460 ret = 0;
13461
13462 if (ret)
13463 break;
13464 }
13465
13466 if (!ret)
13467 return 0;
13468
13469 mutex_lock(&dev->struct_mutex);
13470 drm_atomic_helper_cleanup_planes(dev, state);
13471 }
13472
13473 mutex_unlock(&dev->struct_mutex);
13474 return ret;
13475 }
13476
13477 /**
13478 * intel_atomic_commit - commit validated state object
13479 * @dev: DRM device
13480 * @state: the top-level driver state object
13481 * @async: asynchronous commit
13482 *
13483 * This function commits a top-level state object that has been validated
13484 * with drm_atomic_helper_check().
13485 *
13486 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13487 * we can only handle plane-related operations and do not yet support
13488 * asynchronous commit.
13489 *
13490 * RETURNS
13491 * Zero for success or -errno.
13492 */
13493 static int intel_atomic_commit(struct drm_device *dev,
13494 struct drm_atomic_state *state,
13495 bool async)
13496 {
13497 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13498 struct drm_i915_private *dev_priv = dev->dev_private;
13499 struct drm_crtc_state *crtc_state;
13500 struct drm_crtc *crtc;
13501 int ret = 0, i;
13502 bool hw_check = intel_state->modeset;
13503
13504 ret = intel_atomic_prepare_commit(dev, state, async);
13505 if (ret) {
13506 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13507 return ret;
13508 }
13509
13510 drm_atomic_helper_swap_state(dev, state);
13511 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13512
13513 if (intel_state->modeset) {
13514 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13515 sizeof(intel_state->min_pixclk));
13516 dev_priv->active_crtcs = intel_state->active_crtcs;
13517 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13518 }
13519
13520 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13522
13523 if (!needs_modeset(crtc->state))
13524 continue;
13525
13526 intel_pre_plane_update(intel_crtc);
13527
13528 if (crtc_state->active) {
13529 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13530 dev_priv->display.crtc_disable(crtc);
13531 intel_crtc->active = false;
13532 intel_disable_shared_dpll(intel_crtc);
13533
13534 /*
13535 * Underruns don't always raise
13536 * interrupts, so check manually.
13537 */
13538 intel_check_cpu_fifo_underruns(dev_priv);
13539 intel_check_pch_fifo_underruns(dev_priv);
13540
13541 if (!crtc->state->active)
13542 intel_update_watermarks(crtc);
13543 }
13544 }
13545
13546 /* Only after disabling all output pipelines that will be changed can we
13547 * update the the output configuration. */
13548 intel_modeset_update_crtc_state(state);
13549
13550 if (intel_state->modeset) {
13551 intel_shared_dpll_commit(state);
13552
13553 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13554 modeset_update_crtc_power_domains(state);
13555 }
13556
13557 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13558 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13560 bool modeset = needs_modeset(crtc->state);
13561 bool update_pipe = !modeset &&
13562 to_intel_crtc_state(crtc->state)->update_pipe;
13563 unsigned long put_domains = 0;
13564
13565 if (modeset)
13566 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13567
13568 if (modeset && crtc->state->active) {
13569 update_scanline_offset(to_intel_crtc(crtc));
13570 dev_priv->display.crtc_enable(crtc);
13571 }
13572
13573 if (update_pipe) {
13574 put_domains = modeset_get_crtc_power_domains(crtc);
13575
13576 /* make sure intel_modeset_check_state runs */
13577 hw_check = true;
13578 }
13579
13580 if (!modeset)
13581 intel_pre_plane_update(intel_crtc);
13582
13583 if (crtc->state->active &&
13584 (crtc->state->planes_changed || update_pipe))
13585 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13586
13587 if (put_domains)
13588 modeset_put_power_domains(dev_priv, put_domains);
13589
13590 intel_post_plane_update(intel_crtc);
13591
13592 if (modeset)
13593 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13594 }
13595
13596 /* FIXME: add subpixel order */
13597
13598 drm_atomic_helper_wait_for_vblanks(dev, state);
13599
13600 mutex_lock(&dev->struct_mutex);
13601 drm_atomic_helper_cleanup_planes(dev, state);
13602 mutex_unlock(&dev->struct_mutex);
13603
13604 if (hw_check)
13605 intel_modeset_check_state(dev, state);
13606
13607 drm_atomic_state_free(state);
13608
13609 /* As one of the primary mmio accessors, KMS has a high likelihood
13610 * of triggering bugs in unclaimed access. After we finish
13611 * modesetting, see if an error has been flagged, and if so
13612 * enable debugging for the next modeset - and hope we catch
13613 * the culprit.
13614 *
13615 * XXX note that we assume display power is on at this point.
13616 * This might hold true now but we need to add pm helper to check
13617 * unclaimed only when the hardware is on, as atomic commits
13618 * can happen also when the device is completely off.
13619 */
13620 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13621
13622 return 0;
13623 }
13624
13625 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13626 {
13627 struct drm_device *dev = crtc->dev;
13628 struct drm_atomic_state *state;
13629 struct drm_crtc_state *crtc_state;
13630 int ret;
13631
13632 state = drm_atomic_state_alloc(dev);
13633 if (!state) {
13634 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13635 crtc->base.id);
13636 return;
13637 }
13638
13639 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13640
13641 retry:
13642 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13643 ret = PTR_ERR_OR_ZERO(crtc_state);
13644 if (!ret) {
13645 if (!crtc_state->active)
13646 goto out;
13647
13648 crtc_state->mode_changed = true;
13649 ret = drm_atomic_commit(state);
13650 }
13651
13652 if (ret == -EDEADLK) {
13653 drm_atomic_state_clear(state);
13654 drm_modeset_backoff(state->acquire_ctx);
13655 goto retry;
13656 }
13657
13658 if (ret)
13659 out:
13660 drm_atomic_state_free(state);
13661 }
13662
13663 #undef for_each_intel_crtc_masked
13664
13665 static const struct drm_crtc_funcs intel_crtc_funcs = {
13666 .gamma_set = intel_crtc_gamma_set,
13667 .set_config = drm_atomic_helper_set_config,
13668 .destroy = intel_crtc_destroy,
13669 .page_flip = intel_crtc_page_flip,
13670 .atomic_duplicate_state = intel_crtc_duplicate_state,
13671 .atomic_destroy_state = intel_crtc_destroy_state,
13672 };
13673
13674 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13675 struct intel_shared_dpll *pll,
13676 struct intel_dpll_hw_state *hw_state)
13677 {
13678 uint32_t val;
13679
13680 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13681 return false;
13682
13683 val = I915_READ(PCH_DPLL(pll->id));
13684 hw_state->dpll = val;
13685 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13686 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13687
13688 return val & DPLL_VCO_ENABLE;
13689 }
13690
13691 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13692 struct intel_shared_dpll *pll)
13693 {
13694 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13695 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13696 }
13697
13698 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13699 struct intel_shared_dpll *pll)
13700 {
13701 /* PCH refclock must be enabled first */
13702 ibx_assert_pch_refclk_enabled(dev_priv);
13703
13704 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13705
13706 /* Wait for the clocks to stabilize. */
13707 POSTING_READ(PCH_DPLL(pll->id));
13708 udelay(150);
13709
13710 /* The pixel multiplier can only be updated once the
13711 * DPLL is enabled and the clocks are stable.
13712 *
13713 * So write it again.
13714 */
13715 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13716 POSTING_READ(PCH_DPLL(pll->id));
13717 udelay(200);
13718 }
13719
13720 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13721 struct intel_shared_dpll *pll)
13722 {
13723 struct drm_device *dev = dev_priv->dev;
13724 struct intel_crtc *crtc;
13725
13726 /* Make sure no transcoder isn't still depending on us. */
13727 for_each_intel_crtc(dev, crtc) {
13728 if (intel_crtc_to_shared_dpll(crtc) == pll)
13729 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13730 }
13731
13732 I915_WRITE(PCH_DPLL(pll->id), 0);
13733 POSTING_READ(PCH_DPLL(pll->id));
13734 udelay(200);
13735 }
13736
13737 static char *ibx_pch_dpll_names[] = {
13738 "PCH DPLL A",
13739 "PCH DPLL B",
13740 };
13741
13742 static void ibx_pch_dpll_init(struct drm_device *dev)
13743 {
13744 struct drm_i915_private *dev_priv = dev->dev_private;
13745 int i;
13746
13747 dev_priv->num_shared_dpll = 2;
13748
13749 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13750 dev_priv->shared_dplls[i].id = i;
13751 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13752 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13753 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13754 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13755 dev_priv->shared_dplls[i].get_hw_state =
13756 ibx_pch_dpll_get_hw_state;
13757 }
13758 }
13759
13760 static void intel_shared_dpll_init(struct drm_device *dev)
13761 {
13762 struct drm_i915_private *dev_priv = dev->dev_private;
13763
13764 if (HAS_DDI(dev))
13765 intel_ddi_pll_init(dev);
13766 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13767 ibx_pch_dpll_init(dev);
13768 else
13769 dev_priv->num_shared_dpll = 0;
13770
13771 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13772 }
13773
13774 /**
13775 * intel_prepare_plane_fb - Prepare fb for usage on plane
13776 * @plane: drm plane to prepare for
13777 * @fb: framebuffer to prepare for presentation
13778 *
13779 * Prepares a framebuffer for usage on a display plane. Generally this
13780 * involves pinning the underlying object and updating the frontbuffer tracking
13781 * bits. Some older platforms need special physical address handling for
13782 * cursor planes.
13783 *
13784 * Must be called with struct_mutex held.
13785 *
13786 * Returns 0 on success, negative error code on failure.
13787 */
13788 int
13789 intel_prepare_plane_fb(struct drm_plane *plane,
13790 const struct drm_plane_state *new_state)
13791 {
13792 struct drm_device *dev = plane->dev;
13793 struct drm_framebuffer *fb = new_state->fb;
13794 struct intel_plane *intel_plane = to_intel_plane(plane);
13795 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13796 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13797 int ret = 0;
13798
13799 if (!obj && !old_obj)
13800 return 0;
13801
13802 if (old_obj) {
13803 struct drm_crtc_state *crtc_state =
13804 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13805
13806 /* Big Hammer, we also need to ensure that any pending
13807 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13808 * current scanout is retired before unpinning the old
13809 * framebuffer. Note that we rely on userspace rendering
13810 * into the buffer attached to the pipe they are waiting
13811 * on. If not, userspace generates a GPU hang with IPEHR
13812 * point to the MI_WAIT_FOR_EVENT.
13813 *
13814 * This should only fail upon a hung GPU, in which case we
13815 * can safely continue.
13816 */
13817 if (needs_modeset(crtc_state))
13818 ret = i915_gem_object_wait_rendering(old_obj, true);
13819
13820 /* Swallow -EIO errors to allow updates during hw lockup. */
13821 if (ret && ret != -EIO)
13822 return ret;
13823 }
13824
13825 /* For framebuffer backed by dmabuf, wait for fence */
13826 if (obj && obj->base.dma_buf) {
13827 long lret;
13828
13829 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13830 false, true,
13831 MAX_SCHEDULE_TIMEOUT);
13832 if (lret == -ERESTARTSYS)
13833 return lret;
13834
13835 WARN(lret < 0, "waiting returns %li\n", lret);
13836 }
13837
13838 if (!obj) {
13839 ret = 0;
13840 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13841 INTEL_INFO(dev)->cursor_needs_physical) {
13842 int align = IS_I830(dev) ? 16 * 1024 : 256;
13843 ret = i915_gem_object_attach_phys(obj, align);
13844 if (ret)
13845 DRM_DEBUG_KMS("failed to attach phys object\n");
13846 } else {
13847 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13848 }
13849
13850 if (ret == 0) {
13851 if (obj) {
13852 struct intel_plane_state *plane_state =
13853 to_intel_plane_state(new_state);
13854
13855 i915_gem_request_assign(&plane_state->wait_req,
13856 obj->last_write_req);
13857 }
13858
13859 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13860 }
13861
13862 return ret;
13863 }
13864
13865 /**
13866 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13867 * @plane: drm plane to clean up for
13868 * @fb: old framebuffer that was on plane
13869 *
13870 * Cleans up a framebuffer that has just been removed from a plane.
13871 *
13872 * Must be called with struct_mutex held.
13873 */
13874 void
13875 intel_cleanup_plane_fb(struct drm_plane *plane,
13876 const struct drm_plane_state *old_state)
13877 {
13878 struct drm_device *dev = plane->dev;
13879 struct intel_plane *intel_plane = to_intel_plane(plane);
13880 struct intel_plane_state *old_intel_state;
13881 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13882 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13883
13884 old_intel_state = to_intel_plane_state(old_state);
13885
13886 if (!obj && !old_obj)
13887 return;
13888
13889 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13890 !INTEL_INFO(dev)->cursor_needs_physical))
13891 intel_unpin_fb_obj(old_state->fb, old_state);
13892
13893 /* prepare_fb aborted? */
13894 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13895 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13896 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13897
13898 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13899
13900 }
13901
13902 int
13903 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13904 {
13905 int max_scale;
13906 struct drm_device *dev;
13907 struct drm_i915_private *dev_priv;
13908 int crtc_clock, cdclk;
13909
13910 if (!intel_crtc || !crtc_state->base.enable)
13911 return DRM_PLANE_HELPER_NO_SCALING;
13912
13913 dev = intel_crtc->base.dev;
13914 dev_priv = dev->dev_private;
13915 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13916 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13917
13918 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13919 return DRM_PLANE_HELPER_NO_SCALING;
13920
13921 /*
13922 * skl max scale is lower of:
13923 * close to 3 but not 3, -1 is for that purpose
13924 * or
13925 * cdclk/crtc_clock
13926 */
13927 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13928
13929 return max_scale;
13930 }
13931
13932 static int
13933 intel_check_primary_plane(struct drm_plane *plane,
13934 struct intel_crtc_state *crtc_state,
13935 struct intel_plane_state *state)
13936 {
13937 struct drm_crtc *crtc = state->base.crtc;
13938 struct drm_framebuffer *fb = state->base.fb;
13939 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13940 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13941 bool can_position = false;
13942
13943 if (INTEL_INFO(plane->dev)->gen >= 9) {
13944 /* use scaler when colorkey is not required */
13945 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
13946 min_scale = 1;
13947 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13948 }
13949 can_position = true;
13950 }
13951
13952 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13953 &state->dst, &state->clip,
13954 min_scale, max_scale,
13955 can_position, true,
13956 &state->visible);
13957 }
13958
13959 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13960 struct drm_crtc_state *old_crtc_state)
13961 {
13962 struct drm_device *dev = crtc->dev;
13963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13964 struct intel_crtc_state *old_intel_state =
13965 to_intel_crtc_state(old_crtc_state);
13966 bool modeset = needs_modeset(crtc->state);
13967
13968 /* Perform vblank evasion around commit operation */
13969 intel_pipe_update_start(intel_crtc);
13970
13971 if (modeset)
13972 return;
13973
13974 if (to_intel_crtc_state(crtc->state)->update_pipe)
13975 intel_update_pipe_config(intel_crtc, old_intel_state);
13976 else if (INTEL_INFO(dev)->gen >= 9)
13977 skl_detach_scalers(intel_crtc);
13978 }
13979
13980 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13981 struct drm_crtc_state *old_crtc_state)
13982 {
13983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13984
13985 intel_pipe_update_end(intel_crtc);
13986 }
13987
13988 /**
13989 * intel_plane_destroy - destroy a plane
13990 * @plane: plane to destroy
13991 *
13992 * Common destruction function for all types of planes (primary, cursor,
13993 * sprite).
13994 */
13995 void intel_plane_destroy(struct drm_plane *plane)
13996 {
13997 struct intel_plane *intel_plane = to_intel_plane(plane);
13998 drm_plane_cleanup(plane);
13999 kfree(intel_plane);
14000 }
14001
14002 const struct drm_plane_funcs intel_plane_funcs = {
14003 .update_plane = drm_atomic_helper_update_plane,
14004 .disable_plane = drm_atomic_helper_disable_plane,
14005 .destroy = intel_plane_destroy,
14006 .set_property = drm_atomic_helper_plane_set_property,
14007 .atomic_get_property = intel_plane_atomic_get_property,
14008 .atomic_set_property = intel_plane_atomic_set_property,
14009 .atomic_duplicate_state = intel_plane_duplicate_state,
14010 .atomic_destroy_state = intel_plane_destroy_state,
14011
14012 };
14013
14014 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14015 int pipe)
14016 {
14017 struct intel_plane *primary;
14018 struct intel_plane_state *state;
14019 const uint32_t *intel_primary_formats;
14020 unsigned int num_formats;
14021
14022 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14023 if (primary == NULL)
14024 return NULL;
14025
14026 state = intel_create_plane_state(&primary->base);
14027 if (!state) {
14028 kfree(primary);
14029 return NULL;
14030 }
14031 primary->base.state = &state->base;
14032
14033 primary->can_scale = false;
14034 primary->max_downscale = 1;
14035 if (INTEL_INFO(dev)->gen >= 9) {
14036 primary->can_scale = true;
14037 state->scaler_id = -1;
14038 }
14039 primary->pipe = pipe;
14040 primary->plane = pipe;
14041 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14042 primary->check_plane = intel_check_primary_plane;
14043 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14044 primary->plane = !pipe;
14045
14046 if (INTEL_INFO(dev)->gen >= 9) {
14047 intel_primary_formats = skl_primary_formats;
14048 num_formats = ARRAY_SIZE(skl_primary_formats);
14049
14050 primary->update_plane = skylake_update_primary_plane;
14051 primary->disable_plane = skylake_disable_primary_plane;
14052 } else if (HAS_PCH_SPLIT(dev)) {
14053 intel_primary_formats = i965_primary_formats;
14054 num_formats = ARRAY_SIZE(i965_primary_formats);
14055
14056 primary->update_plane = ironlake_update_primary_plane;
14057 primary->disable_plane = i9xx_disable_primary_plane;
14058 } else if (INTEL_INFO(dev)->gen >= 4) {
14059 intel_primary_formats = i965_primary_formats;
14060 num_formats = ARRAY_SIZE(i965_primary_formats);
14061
14062 primary->update_plane = i9xx_update_primary_plane;
14063 primary->disable_plane = i9xx_disable_primary_plane;
14064 } else {
14065 intel_primary_formats = i8xx_primary_formats;
14066 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14067
14068 primary->update_plane = i9xx_update_primary_plane;
14069 primary->disable_plane = i9xx_disable_primary_plane;
14070 }
14071
14072 drm_universal_plane_init(dev, &primary->base, 0,
14073 &intel_plane_funcs,
14074 intel_primary_formats, num_formats,
14075 DRM_PLANE_TYPE_PRIMARY, NULL);
14076
14077 if (INTEL_INFO(dev)->gen >= 4)
14078 intel_create_rotation_property(dev, primary);
14079
14080 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14081
14082 return &primary->base;
14083 }
14084
14085 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14086 {
14087 if (!dev->mode_config.rotation_property) {
14088 unsigned long flags = BIT(DRM_ROTATE_0) |
14089 BIT(DRM_ROTATE_180);
14090
14091 if (INTEL_INFO(dev)->gen >= 9)
14092 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14093
14094 dev->mode_config.rotation_property =
14095 drm_mode_create_rotation_property(dev, flags);
14096 }
14097 if (dev->mode_config.rotation_property)
14098 drm_object_attach_property(&plane->base.base,
14099 dev->mode_config.rotation_property,
14100 plane->base.state->rotation);
14101 }
14102
14103 static int
14104 intel_check_cursor_plane(struct drm_plane *plane,
14105 struct intel_crtc_state *crtc_state,
14106 struct intel_plane_state *state)
14107 {
14108 struct drm_crtc *crtc = crtc_state->base.crtc;
14109 struct drm_framebuffer *fb = state->base.fb;
14110 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14111 enum pipe pipe = to_intel_plane(plane)->pipe;
14112 unsigned stride;
14113 int ret;
14114
14115 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14116 &state->dst, &state->clip,
14117 DRM_PLANE_HELPER_NO_SCALING,
14118 DRM_PLANE_HELPER_NO_SCALING,
14119 true, true, &state->visible);
14120 if (ret)
14121 return ret;
14122
14123 /* if we want to turn off the cursor ignore width and height */
14124 if (!obj)
14125 return 0;
14126
14127 /* Check for which cursor types we support */
14128 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14129 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14130 state->base.crtc_w, state->base.crtc_h);
14131 return -EINVAL;
14132 }
14133
14134 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14135 if (obj->base.size < stride * state->base.crtc_h) {
14136 DRM_DEBUG_KMS("buffer is too small\n");
14137 return -ENOMEM;
14138 }
14139
14140 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14141 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14142 return -EINVAL;
14143 }
14144
14145 /*
14146 * There's something wrong with the cursor on CHV pipe C.
14147 * If it straddles the left edge of the screen then
14148 * moving it away from the edge or disabling it often
14149 * results in a pipe underrun, and often that can lead to
14150 * dead pipe (constant underrun reported, and it scans
14151 * out just a solid color). To recover from that, the
14152 * display power well must be turned off and on again.
14153 * Refuse the put the cursor into that compromised position.
14154 */
14155 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14156 state->visible && state->base.crtc_x < 0) {
14157 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14158 return -EINVAL;
14159 }
14160
14161 return 0;
14162 }
14163
14164 static void
14165 intel_disable_cursor_plane(struct drm_plane *plane,
14166 struct drm_crtc *crtc)
14167 {
14168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14169
14170 intel_crtc->cursor_addr = 0;
14171 intel_crtc_update_cursor(crtc, NULL);
14172 }
14173
14174 static void
14175 intel_update_cursor_plane(struct drm_plane *plane,
14176 const struct intel_crtc_state *crtc_state,
14177 const struct intel_plane_state *state)
14178 {
14179 struct drm_crtc *crtc = crtc_state->base.crtc;
14180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14181 struct drm_device *dev = plane->dev;
14182 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14183 uint32_t addr;
14184
14185 if (!obj)
14186 addr = 0;
14187 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14188 addr = i915_gem_obj_ggtt_offset(obj);
14189 else
14190 addr = obj->phys_handle->busaddr;
14191
14192 intel_crtc->cursor_addr = addr;
14193 intel_crtc_update_cursor(crtc, state);
14194 }
14195
14196 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14197 int pipe)
14198 {
14199 struct intel_plane *cursor;
14200 struct intel_plane_state *state;
14201
14202 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14203 if (cursor == NULL)
14204 return NULL;
14205
14206 state = intel_create_plane_state(&cursor->base);
14207 if (!state) {
14208 kfree(cursor);
14209 return NULL;
14210 }
14211 cursor->base.state = &state->base;
14212
14213 cursor->can_scale = false;
14214 cursor->max_downscale = 1;
14215 cursor->pipe = pipe;
14216 cursor->plane = pipe;
14217 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14218 cursor->check_plane = intel_check_cursor_plane;
14219 cursor->update_plane = intel_update_cursor_plane;
14220 cursor->disable_plane = intel_disable_cursor_plane;
14221
14222 drm_universal_plane_init(dev, &cursor->base, 0,
14223 &intel_plane_funcs,
14224 intel_cursor_formats,
14225 ARRAY_SIZE(intel_cursor_formats),
14226 DRM_PLANE_TYPE_CURSOR, NULL);
14227
14228 if (INTEL_INFO(dev)->gen >= 4) {
14229 if (!dev->mode_config.rotation_property)
14230 dev->mode_config.rotation_property =
14231 drm_mode_create_rotation_property(dev,
14232 BIT(DRM_ROTATE_0) |
14233 BIT(DRM_ROTATE_180));
14234 if (dev->mode_config.rotation_property)
14235 drm_object_attach_property(&cursor->base.base,
14236 dev->mode_config.rotation_property,
14237 state->base.rotation);
14238 }
14239
14240 if (INTEL_INFO(dev)->gen >=9)
14241 state->scaler_id = -1;
14242
14243 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14244
14245 return &cursor->base;
14246 }
14247
14248 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14249 struct intel_crtc_state *crtc_state)
14250 {
14251 int i;
14252 struct intel_scaler *intel_scaler;
14253 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14254
14255 for (i = 0; i < intel_crtc->num_scalers; i++) {
14256 intel_scaler = &scaler_state->scalers[i];
14257 intel_scaler->in_use = 0;
14258 intel_scaler->mode = PS_SCALER_MODE_DYN;
14259 }
14260
14261 scaler_state->scaler_id = -1;
14262 }
14263
14264 static void intel_crtc_init(struct drm_device *dev, int pipe)
14265 {
14266 struct drm_i915_private *dev_priv = dev->dev_private;
14267 struct intel_crtc *intel_crtc;
14268 struct intel_crtc_state *crtc_state = NULL;
14269 struct drm_plane *primary = NULL;
14270 struct drm_plane *cursor = NULL;
14271 int i, ret;
14272
14273 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14274 if (intel_crtc == NULL)
14275 return;
14276
14277 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14278 if (!crtc_state)
14279 goto fail;
14280 intel_crtc->config = crtc_state;
14281 intel_crtc->base.state = &crtc_state->base;
14282 crtc_state->base.crtc = &intel_crtc->base;
14283
14284 /* initialize shared scalers */
14285 if (INTEL_INFO(dev)->gen >= 9) {
14286 if (pipe == PIPE_C)
14287 intel_crtc->num_scalers = 1;
14288 else
14289 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14290
14291 skl_init_scalers(dev, intel_crtc, crtc_state);
14292 }
14293
14294 primary = intel_primary_plane_create(dev, pipe);
14295 if (!primary)
14296 goto fail;
14297
14298 cursor = intel_cursor_plane_create(dev, pipe);
14299 if (!cursor)
14300 goto fail;
14301
14302 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14303 cursor, &intel_crtc_funcs, NULL);
14304 if (ret)
14305 goto fail;
14306
14307 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14308 for (i = 0; i < 256; i++) {
14309 intel_crtc->lut_r[i] = i;
14310 intel_crtc->lut_g[i] = i;
14311 intel_crtc->lut_b[i] = i;
14312 }
14313
14314 /*
14315 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14316 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14317 */
14318 intel_crtc->pipe = pipe;
14319 intel_crtc->plane = pipe;
14320 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14321 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14322 intel_crtc->plane = !pipe;
14323 }
14324
14325 intel_crtc->cursor_base = ~0;
14326 intel_crtc->cursor_cntl = ~0;
14327 intel_crtc->cursor_size = ~0;
14328
14329 intel_crtc->wm.cxsr_allowed = true;
14330
14331 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14332 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14333 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14334 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14335
14336 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14337
14338 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14339 return;
14340
14341 fail:
14342 if (primary)
14343 drm_plane_cleanup(primary);
14344 if (cursor)
14345 drm_plane_cleanup(cursor);
14346 kfree(crtc_state);
14347 kfree(intel_crtc);
14348 }
14349
14350 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14351 {
14352 struct drm_encoder *encoder = connector->base.encoder;
14353 struct drm_device *dev = connector->base.dev;
14354
14355 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14356
14357 if (!encoder || WARN_ON(!encoder->crtc))
14358 return INVALID_PIPE;
14359
14360 return to_intel_crtc(encoder->crtc)->pipe;
14361 }
14362
14363 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14364 struct drm_file *file)
14365 {
14366 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14367 struct drm_crtc *drmmode_crtc;
14368 struct intel_crtc *crtc;
14369
14370 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14371
14372 if (!drmmode_crtc) {
14373 DRM_ERROR("no such CRTC id\n");
14374 return -ENOENT;
14375 }
14376
14377 crtc = to_intel_crtc(drmmode_crtc);
14378 pipe_from_crtc_id->pipe = crtc->pipe;
14379
14380 return 0;
14381 }
14382
14383 static int intel_encoder_clones(struct intel_encoder *encoder)
14384 {
14385 struct drm_device *dev = encoder->base.dev;
14386 struct intel_encoder *source_encoder;
14387 int index_mask = 0;
14388 int entry = 0;
14389
14390 for_each_intel_encoder(dev, source_encoder) {
14391 if (encoders_cloneable(encoder, source_encoder))
14392 index_mask |= (1 << entry);
14393
14394 entry++;
14395 }
14396
14397 return index_mask;
14398 }
14399
14400 static bool has_edp_a(struct drm_device *dev)
14401 {
14402 struct drm_i915_private *dev_priv = dev->dev_private;
14403
14404 if (!IS_MOBILE(dev))
14405 return false;
14406
14407 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14408 return false;
14409
14410 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14411 return false;
14412
14413 return true;
14414 }
14415
14416 static bool intel_crt_present(struct drm_device *dev)
14417 {
14418 struct drm_i915_private *dev_priv = dev->dev_private;
14419
14420 if (INTEL_INFO(dev)->gen >= 9)
14421 return false;
14422
14423 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14424 return false;
14425
14426 if (IS_CHERRYVIEW(dev))
14427 return false;
14428
14429 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14430 return false;
14431
14432 /* DDI E can't be used if DDI A requires 4 lanes */
14433 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14434 return false;
14435
14436 if (!dev_priv->vbt.int_crt_support)
14437 return false;
14438
14439 return true;
14440 }
14441
14442 static void intel_setup_outputs(struct drm_device *dev)
14443 {
14444 struct drm_i915_private *dev_priv = dev->dev_private;
14445 struct intel_encoder *encoder;
14446 bool dpd_is_edp = false;
14447
14448 intel_lvds_init(dev);
14449
14450 if (intel_crt_present(dev))
14451 intel_crt_init(dev);
14452
14453 if (IS_BROXTON(dev)) {
14454 /*
14455 * FIXME: Broxton doesn't support port detection via the
14456 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14457 * detect the ports.
14458 */
14459 intel_ddi_init(dev, PORT_A);
14460 intel_ddi_init(dev, PORT_B);
14461 intel_ddi_init(dev, PORT_C);
14462 } else if (HAS_DDI(dev)) {
14463 int found;
14464
14465 /*
14466 * Haswell uses DDI functions to detect digital outputs.
14467 * On SKL pre-D0 the strap isn't connected, so we assume
14468 * it's there.
14469 */
14470 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14471 /* WaIgnoreDDIAStrap: skl */
14472 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14473 intel_ddi_init(dev, PORT_A);
14474
14475 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14476 * register */
14477 found = I915_READ(SFUSE_STRAP);
14478
14479 if (found & SFUSE_STRAP_DDIB_DETECTED)
14480 intel_ddi_init(dev, PORT_B);
14481 if (found & SFUSE_STRAP_DDIC_DETECTED)
14482 intel_ddi_init(dev, PORT_C);
14483 if (found & SFUSE_STRAP_DDID_DETECTED)
14484 intel_ddi_init(dev, PORT_D);
14485 /*
14486 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14487 */
14488 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14489 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14490 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14491 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14492 intel_ddi_init(dev, PORT_E);
14493
14494 } else if (HAS_PCH_SPLIT(dev)) {
14495 int found;
14496 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14497
14498 if (has_edp_a(dev))
14499 intel_dp_init(dev, DP_A, PORT_A);
14500
14501 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14502 /* PCH SDVOB multiplex with HDMIB */
14503 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14504 if (!found)
14505 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14506 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14507 intel_dp_init(dev, PCH_DP_B, PORT_B);
14508 }
14509
14510 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14511 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14512
14513 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14514 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14515
14516 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14517 intel_dp_init(dev, PCH_DP_C, PORT_C);
14518
14519 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14520 intel_dp_init(dev, PCH_DP_D, PORT_D);
14521 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14522 /*
14523 * The DP_DETECTED bit is the latched state of the DDC
14524 * SDA pin at boot. However since eDP doesn't require DDC
14525 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14526 * eDP ports may have been muxed to an alternate function.
14527 * Thus we can't rely on the DP_DETECTED bit alone to detect
14528 * eDP ports. Consult the VBT as well as DP_DETECTED to
14529 * detect eDP ports.
14530 */
14531 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14532 !intel_dp_is_edp(dev, PORT_B))
14533 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14534 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14535 intel_dp_is_edp(dev, PORT_B))
14536 intel_dp_init(dev, VLV_DP_B, PORT_B);
14537
14538 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14539 !intel_dp_is_edp(dev, PORT_C))
14540 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14541 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14542 intel_dp_is_edp(dev, PORT_C))
14543 intel_dp_init(dev, VLV_DP_C, PORT_C);
14544
14545 if (IS_CHERRYVIEW(dev)) {
14546 /* eDP not supported on port D, so don't check VBT */
14547 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14548 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14549 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14550 intel_dp_init(dev, CHV_DP_D, PORT_D);
14551 }
14552
14553 intel_dsi_init(dev);
14554 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14555 bool found = false;
14556
14557 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14558 DRM_DEBUG_KMS("probing SDVOB\n");
14559 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14560 if (!found && IS_G4X(dev)) {
14561 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14562 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14563 }
14564
14565 if (!found && IS_G4X(dev))
14566 intel_dp_init(dev, DP_B, PORT_B);
14567 }
14568
14569 /* Before G4X SDVOC doesn't have its own detect register */
14570
14571 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14572 DRM_DEBUG_KMS("probing SDVOC\n");
14573 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14574 }
14575
14576 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14577
14578 if (IS_G4X(dev)) {
14579 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14580 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14581 }
14582 if (IS_G4X(dev))
14583 intel_dp_init(dev, DP_C, PORT_C);
14584 }
14585
14586 if (IS_G4X(dev) &&
14587 (I915_READ(DP_D) & DP_DETECTED))
14588 intel_dp_init(dev, DP_D, PORT_D);
14589 } else if (IS_GEN2(dev))
14590 intel_dvo_init(dev);
14591
14592 if (SUPPORTS_TV(dev))
14593 intel_tv_init(dev);
14594
14595 intel_psr_init(dev);
14596
14597 for_each_intel_encoder(dev, encoder) {
14598 encoder->base.possible_crtcs = encoder->crtc_mask;
14599 encoder->base.possible_clones =
14600 intel_encoder_clones(encoder);
14601 }
14602
14603 intel_init_pch_refclk(dev);
14604
14605 drm_helper_move_panel_connectors_to_head(dev);
14606 }
14607
14608 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14609 {
14610 struct drm_device *dev = fb->dev;
14611 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14612
14613 drm_framebuffer_cleanup(fb);
14614 mutex_lock(&dev->struct_mutex);
14615 WARN_ON(!intel_fb->obj->framebuffer_references--);
14616 drm_gem_object_unreference(&intel_fb->obj->base);
14617 mutex_unlock(&dev->struct_mutex);
14618 kfree(intel_fb);
14619 }
14620
14621 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14622 struct drm_file *file,
14623 unsigned int *handle)
14624 {
14625 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14626 struct drm_i915_gem_object *obj = intel_fb->obj;
14627
14628 if (obj->userptr.mm) {
14629 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14630 return -EINVAL;
14631 }
14632
14633 return drm_gem_handle_create(file, &obj->base, handle);
14634 }
14635
14636 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14637 struct drm_file *file,
14638 unsigned flags, unsigned color,
14639 struct drm_clip_rect *clips,
14640 unsigned num_clips)
14641 {
14642 struct drm_device *dev = fb->dev;
14643 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14644 struct drm_i915_gem_object *obj = intel_fb->obj;
14645
14646 mutex_lock(&dev->struct_mutex);
14647 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14648 mutex_unlock(&dev->struct_mutex);
14649
14650 return 0;
14651 }
14652
14653 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14654 .destroy = intel_user_framebuffer_destroy,
14655 .create_handle = intel_user_framebuffer_create_handle,
14656 .dirty = intel_user_framebuffer_dirty,
14657 };
14658
14659 static
14660 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14661 uint32_t pixel_format)
14662 {
14663 u32 gen = INTEL_INFO(dev)->gen;
14664
14665 if (gen >= 9) {
14666 int cpp = drm_format_plane_cpp(pixel_format, 0);
14667
14668 /* "The stride in bytes must not exceed the of the size of 8K
14669 * pixels and 32K bytes."
14670 */
14671 return min(8192 * cpp, 32768);
14672 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14673 return 32*1024;
14674 } else if (gen >= 4) {
14675 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14676 return 16*1024;
14677 else
14678 return 32*1024;
14679 } else if (gen >= 3) {
14680 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14681 return 8*1024;
14682 else
14683 return 16*1024;
14684 } else {
14685 /* XXX DSPC is limited to 4k tiled */
14686 return 8*1024;
14687 }
14688 }
14689
14690 static int intel_framebuffer_init(struct drm_device *dev,
14691 struct intel_framebuffer *intel_fb,
14692 struct drm_mode_fb_cmd2 *mode_cmd,
14693 struct drm_i915_gem_object *obj)
14694 {
14695 struct drm_i915_private *dev_priv = to_i915(dev);
14696 unsigned int aligned_height;
14697 int ret;
14698 u32 pitch_limit, stride_alignment;
14699
14700 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14701
14702 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14703 /* Enforce that fb modifier and tiling mode match, but only for
14704 * X-tiled. This is needed for FBC. */
14705 if (!!(obj->tiling_mode == I915_TILING_X) !=
14706 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14707 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14708 return -EINVAL;
14709 }
14710 } else {
14711 if (obj->tiling_mode == I915_TILING_X)
14712 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14713 else if (obj->tiling_mode == I915_TILING_Y) {
14714 DRM_DEBUG("No Y tiling for legacy addfb\n");
14715 return -EINVAL;
14716 }
14717 }
14718
14719 /* Passed in modifier sanity checking. */
14720 switch (mode_cmd->modifier[0]) {
14721 case I915_FORMAT_MOD_Y_TILED:
14722 case I915_FORMAT_MOD_Yf_TILED:
14723 if (INTEL_INFO(dev)->gen < 9) {
14724 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14725 mode_cmd->modifier[0]);
14726 return -EINVAL;
14727 }
14728 case DRM_FORMAT_MOD_NONE:
14729 case I915_FORMAT_MOD_X_TILED:
14730 break;
14731 default:
14732 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14733 mode_cmd->modifier[0]);
14734 return -EINVAL;
14735 }
14736
14737 stride_alignment = intel_fb_stride_alignment(dev_priv,
14738 mode_cmd->modifier[0],
14739 mode_cmd->pixel_format);
14740 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14741 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14742 mode_cmd->pitches[0], stride_alignment);
14743 return -EINVAL;
14744 }
14745
14746 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14747 mode_cmd->pixel_format);
14748 if (mode_cmd->pitches[0] > pitch_limit) {
14749 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14750 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14751 "tiled" : "linear",
14752 mode_cmd->pitches[0], pitch_limit);
14753 return -EINVAL;
14754 }
14755
14756 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14757 mode_cmd->pitches[0] != obj->stride) {
14758 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14759 mode_cmd->pitches[0], obj->stride);
14760 return -EINVAL;
14761 }
14762
14763 /* Reject formats not supported by any plane early. */
14764 switch (mode_cmd->pixel_format) {
14765 case DRM_FORMAT_C8:
14766 case DRM_FORMAT_RGB565:
14767 case DRM_FORMAT_XRGB8888:
14768 case DRM_FORMAT_ARGB8888:
14769 break;
14770 case DRM_FORMAT_XRGB1555:
14771 if (INTEL_INFO(dev)->gen > 3) {
14772 DRM_DEBUG("unsupported pixel format: %s\n",
14773 drm_get_format_name(mode_cmd->pixel_format));
14774 return -EINVAL;
14775 }
14776 break;
14777 case DRM_FORMAT_ABGR8888:
14778 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14779 INTEL_INFO(dev)->gen < 9) {
14780 DRM_DEBUG("unsupported pixel format: %s\n",
14781 drm_get_format_name(mode_cmd->pixel_format));
14782 return -EINVAL;
14783 }
14784 break;
14785 case DRM_FORMAT_XBGR8888:
14786 case DRM_FORMAT_XRGB2101010:
14787 case DRM_FORMAT_XBGR2101010:
14788 if (INTEL_INFO(dev)->gen < 4) {
14789 DRM_DEBUG("unsupported pixel format: %s\n",
14790 drm_get_format_name(mode_cmd->pixel_format));
14791 return -EINVAL;
14792 }
14793 break;
14794 case DRM_FORMAT_ABGR2101010:
14795 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14796 DRM_DEBUG("unsupported pixel format: %s\n",
14797 drm_get_format_name(mode_cmd->pixel_format));
14798 return -EINVAL;
14799 }
14800 break;
14801 case DRM_FORMAT_YUYV:
14802 case DRM_FORMAT_UYVY:
14803 case DRM_FORMAT_YVYU:
14804 case DRM_FORMAT_VYUY:
14805 if (INTEL_INFO(dev)->gen < 5) {
14806 DRM_DEBUG("unsupported pixel format: %s\n",
14807 drm_get_format_name(mode_cmd->pixel_format));
14808 return -EINVAL;
14809 }
14810 break;
14811 default:
14812 DRM_DEBUG("unsupported pixel format: %s\n",
14813 drm_get_format_name(mode_cmd->pixel_format));
14814 return -EINVAL;
14815 }
14816
14817 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14818 if (mode_cmd->offsets[0] != 0)
14819 return -EINVAL;
14820
14821 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14822 mode_cmd->pixel_format,
14823 mode_cmd->modifier[0]);
14824 /* FIXME drm helper for size checks (especially planar formats)? */
14825 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14826 return -EINVAL;
14827
14828 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14829 intel_fb->obj = obj;
14830
14831 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14832 if (ret) {
14833 DRM_ERROR("framebuffer init failed %d\n", ret);
14834 return ret;
14835 }
14836
14837 intel_fb->obj->framebuffer_references++;
14838
14839 return 0;
14840 }
14841
14842 static struct drm_framebuffer *
14843 intel_user_framebuffer_create(struct drm_device *dev,
14844 struct drm_file *filp,
14845 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14846 {
14847 struct drm_framebuffer *fb;
14848 struct drm_i915_gem_object *obj;
14849 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14850
14851 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14852 mode_cmd.handles[0]));
14853 if (&obj->base == NULL)
14854 return ERR_PTR(-ENOENT);
14855
14856 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14857 if (IS_ERR(fb))
14858 drm_gem_object_unreference_unlocked(&obj->base);
14859
14860 return fb;
14861 }
14862
14863 #ifndef CONFIG_DRM_FBDEV_EMULATION
14864 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14865 {
14866 }
14867 #endif
14868
14869 static const struct drm_mode_config_funcs intel_mode_funcs = {
14870 .fb_create = intel_user_framebuffer_create,
14871 .output_poll_changed = intel_fbdev_output_poll_changed,
14872 .atomic_check = intel_atomic_check,
14873 .atomic_commit = intel_atomic_commit,
14874 .atomic_state_alloc = intel_atomic_state_alloc,
14875 .atomic_state_clear = intel_atomic_state_clear,
14876 };
14877
14878 /* Set up chip specific display functions */
14879 static void intel_init_display(struct drm_device *dev)
14880 {
14881 struct drm_i915_private *dev_priv = dev->dev_private;
14882
14883 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14884 dev_priv->display.find_dpll = g4x_find_best_dpll;
14885 else if (IS_CHERRYVIEW(dev))
14886 dev_priv->display.find_dpll = chv_find_best_dpll;
14887 else if (IS_VALLEYVIEW(dev))
14888 dev_priv->display.find_dpll = vlv_find_best_dpll;
14889 else if (IS_PINEVIEW(dev))
14890 dev_priv->display.find_dpll = pnv_find_best_dpll;
14891 else
14892 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14893
14894 if (INTEL_INFO(dev)->gen >= 9) {
14895 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14896 dev_priv->display.get_initial_plane_config =
14897 skylake_get_initial_plane_config;
14898 dev_priv->display.crtc_compute_clock =
14899 haswell_crtc_compute_clock;
14900 dev_priv->display.crtc_enable = haswell_crtc_enable;
14901 dev_priv->display.crtc_disable = haswell_crtc_disable;
14902 } else if (HAS_DDI(dev)) {
14903 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14904 dev_priv->display.get_initial_plane_config =
14905 ironlake_get_initial_plane_config;
14906 dev_priv->display.crtc_compute_clock =
14907 haswell_crtc_compute_clock;
14908 dev_priv->display.crtc_enable = haswell_crtc_enable;
14909 dev_priv->display.crtc_disable = haswell_crtc_disable;
14910 } else if (HAS_PCH_SPLIT(dev)) {
14911 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14912 dev_priv->display.get_initial_plane_config =
14913 ironlake_get_initial_plane_config;
14914 dev_priv->display.crtc_compute_clock =
14915 ironlake_crtc_compute_clock;
14916 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14917 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14918 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14919 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14920 dev_priv->display.get_initial_plane_config =
14921 i9xx_get_initial_plane_config;
14922 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14923 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14924 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14925 } else {
14926 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14927 dev_priv->display.get_initial_plane_config =
14928 i9xx_get_initial_plane_config;
14929 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14930 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14931 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14932 }
14933
14934 /* Returns the core display clock speed */
14935 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14936 dev_priv->display.get_display_clock_speed =
14937 skylake_get_display_clock_speed;
14938 else if (IS_BROXTON(dev))
14939 dev_priv->display.get_display_clock_speed =
14940 broxton_get_display_clock_speed;
14941 else if (IS_BROADWELL(dev))
14942 dev_priv->display.get_display_clock_speed =
14943 broadwell_get_display_clock_speed;
14944 else if (IS_HASWELL(dev))
14945 dev_priv->display.get_display_clock_speed =
14946 haswell_get_display_clock_speed;
14947 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
14948 dev_priv->display.get_display_clock_speed =
14949 valleyview_get_display_clock_speed;
14950 else if (IS_GEN5(dev))
14951 dev_priv->display.get_display_clock_speed =
14952 ilk_get_display_clock_speed;
14953 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14954 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14955 dev_priv->display.get_display_clock_speed =
14956 i945_get_display_clock_speed;
14957 else if (IS_GM45(dev))
14958 dev_priv->display.get_display_clock_speed =
14959 gm45_get_display_clock_speed;
14960 else if (IS_CRESTLINE(dev))
14961 dev_priv->display.get_display_clock_speed =
14962 i965gm_get_display_clock_speed;
14963 else if (IS_PINEVIEW(dev))
14964 dev_priv->display.get_display_clock_speed =
14965 pnv_get_display_clock_speed;
14966 else if (IS_G33(dev) || IS_G4X(dev))
14967 dev_priv->display.get_display_clock_speed =
14968 g33_get_display_clock_speed;
14969 else if (IS_I915G(dev))
14970 dev_priv->display.get_display_clock_speed =
14971 i915_get_display_clock_speed;
14972 else if (IS_I945GM(dev) || IS_845G(dev))
14973 dev_priv->display.get_display_clock_speed =
14974 i9xx_misc_get_display_clock_speed;
14975 else if (IS_I915GM(dev))
14976 dev_priv->display.get_display_clock_speed =
14977 i915gm_get_display_clock_speed;
14978 else if (IS_I865G(dev))
14979 dev_priv->display.get_display_clock_speed =
14980 i865_get_display_clock_speed;
14981 else if (IS_I85X(dev))
14982 dev_priv->display.get_display_clock_speed =
14983 i85x_get_display_clock_speed;
14984 else { /* 830 */
14985 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14986 dev_priv->display.get_display_clock_speed =
14987 i830_get_display_clock_speed;
14988 }
14989
14990 if (IS_GEN5(dev)) {
14991 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14992 } else if (IS_GEN6(dev)) {
14993 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14994 } else if (IS_IVYBRIDGE(dev)) {
14995 /* FIXME: detect B0+ stepping and use auto training */
14996 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14997 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14998 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14999 if (IS_BROADWELL(dev)) {
15000 dev_priv->display.modeset_commit_cdclk =
15001 broadwell_modeset_commit_cdclk;
15002 dev_priv->display.modeset_calc_cdclk =
15003 broadwell_modeset_calc_cdclk;
15004 }
15005 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15006 dev_priv->display.modeset_commit_cdclk =
15007 valleyview_modeset_commit_cdclk;
15008 dev_priv->display.modeset_calc_cdclk =
15009 valleyview_modeset_calc_cdclk;
15010 } else if (IS_BROXTON(dev)) {
15011 dev_priv->display.modeset_commit_cdclk =
15012 broxton_modeset_commit_cdclk;
15013 dev_priv->display.modeset_calc_cdclk =
15014 broxton_modeset_calc_cdclk;
15015 }
15016
15017 switch (INTEL_INFO(dev)->gen) {
15018 case 2:
15019 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15020 break;
15021
15022 case 3:
15023 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15024 break;
15025
15026 case 4:
15027 case 5:
15028 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15029 break;
15030
15031 case 6:
15032 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15033 break;
15034 case 7:
15035 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15036 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15037 break;
15038 case 9:
15039 /* Drop through - unsupported since execlist only. */
15040 default:
15041 /* Default just returns -ENODEV to indicate unsupported */
15042 dev_priv->display.queue_flip = intel_default_queue_flip;
15043 }
15044
15045 mutex_init(&dev_priv->pps_mutex);
15046 }
15047
15048 /*
15049 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15050 * resume, or other times. This quirk makes sure that's the case for
15051 * affected systems.
15052 */
15053 static void quirk_pipea_force(struct drm_device *dev)
15054 {
15055 struct drm_i915_private *dev_priv = dev->dev_private;
15056
15057 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15058 DRM_INFO("applying pipe a force quirk\n");
15059 }
15060
15061 static void quirk_pipeb_force(struct drm_device *dev)
15062 {
15063 struct drm_i915_private *dev_priv = dev->dev_private;
15064
15065 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15066 DRM_INFO("applying pipe b force quirk\n");
15067 }
15068
15069 /*
15070 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15071 */
15072 static void quirk_ssc_force_disable(struct drm_device *dev)
15073 {
15074 struct drm_i915_private *dev_priv = dev->dev_private;
15075 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15076 DRM_INFO("applying lvds SSC disable quirk\n");
15077 }
15078
15079 /*
15080 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15081 * brightness value
15082 */
15083 static void quirk_invert_brightness(struct drm_device *dev)
15084 {
15085 struct drm_i915_private *dev_priv = dev->dev_private;
15086 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15087 DRM_INFO("applying inverted panel brightness quirk\n");
15088 }
15089
15090 /* Some VBT's incorrectly indicate no backlight is present */
15091 static void quirk_backlight_present(struct drm_device *dev)
15092 {
15093 struct drm_i915_private *dev_priv = dev->dev_private;
15094 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15095 DRM_INFO("applying backlight present quirk\n");
15096 }
15097
15098 struct intel_quirk {
15099 int device;
15100 int subsystem_vendor;
15101 int subsystem_device;
15102 void (*hook)(struct drm_device *dev);
15103 };
15104
15105 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15106 struct intel_dmi_quirk {
15107 void (*hook)(struct drm_device *dev);
15108 const struct dmi_system_id (*dmi_id_list)[];
15109 };
15110
15111 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15112 {
15113 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15114 return 1;
15115 }
15116
15117 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15118 {
15119 .dmi_id_list = &(const struct dmi_system_id[]) {
15120 {
15121 .callback = intel_dmi_reverse_brightness,
15122 .ident = "NCR Corporation",
15123 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15124 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15125 },
15126 },
15127 { } /* terminating entry */
15128 },
15129 .hook = quirk_invert_brightness,
15130 },
15131 };
15132
15133 static struct intel_quirk intel_quirks[] = {
15134 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15135 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15136
15137 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15138 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15139
15140 /* 830 needs to leave pipe A & dpll A up */
15141 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15142
15143 /* 830 needs to leave pipe B & dpll B up */
15144 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15145
15146 /* Lenovo U160 cannot use SSC on LVDS */
15147 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15148
15149 /* Sony Vaio Y cannot use SSC on LVDS */
15150 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15151
15152 /* Acer Aspire 5734Z must invert backlight brightness */
15153 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15154
15155 /* Acer/eMachines G725 */
15156 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15157
15158 /* Acer/eMachines e725 */
15159 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15160
15161 /* Acer/Packard Bell NCL20 */
15162 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15163
15164 /* Acer Aspire 4736Z */
15165 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15166
15167 /* Acer Aspire 5336 */
15168 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15169
15170 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15171 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15172
15173 /* Acer C720 Chromebook (Core i3 4005U) */
15174 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15175
15176 /* Apple Macbook 2,1 (Core 2 T7400) */
15177 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15178
15179 /* Apple Macbook 4,1 */
15180 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15181
15182 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15183 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15184
15185 /* HP Chromebook 14 (Celeron 2955U) */
15186 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15187
15188 /* Dell Chromebook 11 */
15189 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15190
15191 /* Dell Chromebook 11 (2015 version) */
15192 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15193 };
15194
15195 static void intel_init_quirks(struct drm_device *dev)
15196 {
15197 struct pci_dev *d = dev->pdev;
15198 int i;
15199
15200 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15201 struct intel_quirk *q = &intel_quirks[i];
15202
15203 if (d->device == q->device &&
15204 (d->subsystem_vendor == q->subsystem_vendor ||
15205 q->subsystem_vendor == PCI_ANY_ID) &&
15206 (d->subsystem_device == q->subsystem_device ||
15207 q->subsystem_device == PCI_ANY_ID))
15208 q->hook(dev);
15209 }
15210 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15211 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15212 intel_dmi_quirks[i].hook(dev);
15213 }
15214 }
15215
15216 /* Disable the VGA plane that we never use */
15217 static void i915_disable_vga(struct drm_device *dev)
15218 {
15219 struct drm_i915_private *dev_priv = dev->dev_private;
15220 u8 sr1;
15221 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15222
15223 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15224 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15225 outb(SR01, VGA_SR_INDEX);
15226 sr1 = inb(VGA_SR_DATA);
15227 outb(sr1 | 1<<5, VGA_SR_DATA);
15228 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15229 udelay(300);
15230
15231 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15232 POSTING_READ(vga_reg);
15233 }
15234
15235 void intel_modeset_init_hw(struct drm_device *dev)
15236 {
15237 struct drm_i915_private *dev_priv = dev->dev_private;
15238
15239 intel_update_cdclk(dev);
15240
15241 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15242
15243 intel_init_clock_gating(dev);
15244 intel_enable_gt_powersave(dev);
15245 }
15246
15247 /*
15248 * Calculate what we think the watermarks should be for the state we've read
15249 * out of the hardware and then immediately program those watermarks so that
15250 * we ensure the hardware settings match our internal state.
15251 *
15252 * We can calculate what we think WM's should be by creating a duplicate of the
15253 * current state (which was constructed during hardware readout) and running it
15254 * through the atomic check code to calculate new watermark values in the
15255 * state object.
15256 */
15257 static void sanitize_watermarks(struct drm_device *dev)
15258 {
15259 struct drm_i915_private *dev_priv = to_i915(dev);
15260 struct drm_atomic_state *state;
15261 struct drm_crtc *crtc;
15262 struct drm_crtc_state *cstate;
15263 struct drm_modeset_acquire_ctx ctx;
15264 int ret;
15265 int i;
15266
15267 /* Only supported on platforms that use atomic watermark design */
15268 if (!dev_priv->display.program_watermarks)
15269 return;
15270
15271 /*
15272 * We need to hold connection_mutex before calling duplicate_state so
15273 * that the connector loop is protected.
15274 */
15275 drm_modeset_acquire_init(&ctx, 0);
15276 retry:
15277 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15278 if (ret == -EDEADLK) {
15279 drm_modeset_backoff(&ctx);
15280 goto retry;
15281 } else if (WARN_ON(ret)) {
15282 goto fail;
15283 }
15284
15285 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15286 if (WARN_ON(IS_ERR(state)))
15287 goto fail;
15288
15289 ret = intel_atomic_check(dev, state);
15290 if (ret) {
15291 /*
15292 * If we fail here, it means that the hardware appears to be
15293 * programmed in a way that shouldn't be possible, given our
15294 * understanding of watermark requirements. This might mean a
15295 * mistake in the hardware readout code or a mistake in the
15296 * watermark calculations for a given platform. Raise a WARN
15297 * so that this is noticeable.
15298 *
15299 * If this actually happens, we'll have to just leave the
15300 * BIOS-programmed watermarks untouched and hope for the best.
15301 */
15302 WARN(true, "Could not determine valid watermarks for inherited state\n");
15303 goto fail;
15304 }
15305
15306 /* Write calculated watermark values back */
15307 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15308 for_each_crtc_in_state(state, crtc, cstate, i) {
15309 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15310
15311 dev_priv->display.program_watermarks(cs);
15312 }
15313
15314 drm_atomic_state_free(state);
15315 fail:
15316 drm_modeset_drop_locks(&ctx);
15317 drm_modeset_acquire_fini(&ctx);
15318 }
15319
15320 void intel_modeset_init(struct drm_device *dev)
15321 {
15322 struct drm_i915_private *dev_priv = dev->dev_private;
15323 int sprite, ret;
15324 enum pipe pipe;
15325 struct intel_crtc *crtc;
15326
15327 drm_mode_config_init(dev);
15328
15329 dev->mode_config.min_width = 0;
15330 dev->mode_config.min_height = 0;
15331
15332 dev->mode_config.preferred_depth = 24;
15333 dev->mode_config.prefer_shadow = 1;
15334
15335 dev->mode_config.allow_fb_modifiers = true;
15336
15337 dev->mode_config.funcs = &intel_mode_funcs;
15338
15339 intel_init_quirks(dev);
15340
15341 intel_init_pm(dev);
15342
15343 if (INTEL_INFO(dev)->num_pipes == 0)
15344 return;
15345
15346 /*
15347 * There may be no VBT; and if the BIOS enabled SSC we can
15348 * just keep using it to avoid unnecessary flicker. Whereas if the
15349 * BIOS isn't using it, don't assume it will work even if the VBT
15350 * indicates as much.
15351 */
15352 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15353 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15354 DREF_SSC1_ENABLE);
15355
15356 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15357 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15358 bios_lvds_use_ssc ? "en" : "dis",
15359 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15360 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15361 }
15362 }
15363
15364 intel_init_display(dev);
15365 intel_init_audio(dev);
15366
15367 if (IS_GEN2(dev)) {
15368 dev->mode_config.max_width = 2048;
15369 dev->mode_config.max_height = 2048;
15370 } else if (IS_GEN3(dev)) {
15371 dev->mode_config.max_width = 4096;
15372 dev->mode_config.max_height = 4096;
15373 } else {
15374 dev->mode_config.max_width = 8192;
15375 dev->mode_config.max_height = 8192;
15376 }
15377
15378 if (IS_845G(dev) || IS_I865G(dev)) {
15379 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15380 dev->mode_config.cursor_height = 1023;
15381 } else if (IS_GEN2(dev)) {
15382 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15383 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15384 } else {
15385 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15386 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15387 }
15388
15389 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15390
15391 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15392 INTEL_INFO(dev)->num_pipes,
15393 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15394
15395 for_each_pipe(dev_priv, pipe) {
15396 intel_crtc_init(dev, pipe);
15397 for_each_sprite(dev_priv, pipe, sprite) {
15398 ret = intel_plane_init(dev, pipe, sprite);
15399 if (ret)
15400 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15401 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15402 }
15403 }
15404
15405 intel_update_czclk(dev_priv);
15406 intel_update_cdclk(dev);
15407
15408 intel_shared_dpll_init(dev);
15409
15410 /* Just disable it once at startup */
15411 i915_disable_vga(dev);
15412 intel_setup_outputs(dev);
15413
15414 drm_modeset_lock_all(dev);
15415 intel_modeset_setup_hw_state(dev);
15416 drm_modeset_unlock_all(dev);
15417
15418 for_each_intel_crtc(dev, crtc) {
15419 struct intel_initial_plane_config plane_config = {};
15420
15421 if (!crtc->active)
15422 continue;
15423
15424 /*
15425 * Note that reserving the BIOS fb up front prevents us
15426 * from stuffing other stolen allocations like the ring
15427 * on top. This prevents some ugliness at boot time, and
15428 * can even allow for smooth boot transitions if the BIOS
15429 * fb is large enough for the active pipe configuration.
15430 */
15431 dev_priv->display.get_initial_plane_config(crtc,
15432 &plane_config);
15433
15434 /*
15435 * If the fb is shared between multiple heads, we'll
15436 * just get the first one.
15437 */
15438 intel_find_initial_plane_obj(crtc, &plane_config);
15439 }
15440
15441 /*
15442 * Make sure hardware watermarks really match the state we read out.
15443 * Note that we need to do this after reconstructing the BIOS fb's
15444 * since the watermark calculation done here will use pstate->fb.
15445 */
15446 sanitize_watermarks(dev);
15447 }
15448
15449 static void intel_enable_pipe_a(struct drm_device *dev)
15450 {
15451 struct intel_connector *connector;
15452 struct drm_connector *crt = NULL;
15453 struct intel_load_detect_pipe load_detect_temp;
15454 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15455
15456 /* We can't just switch on the pipe A, we need to set things up with a
15457 * proper mode and output configuration. As a gross hack, enable pipe A
15458 * by enabling the load detect pipe once. */
15459 for_each_intel_connector(dev, connector) {
15460 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15461 crt = &connector->base;
15462 break;
15463 }
15464 }
15465
15466 if (!crt)
15467 return;
15468
15469 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15470 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15471 }
15472
15473 static bool
15474 intel_check_plane_mapping(struct intel_crtc *crtc)
15475 {
15476 struct drm_device *dev = crtc->base.dev;
15477 struct drm_i915_private *dev_priv = dev->dev_private;
15478 u32 val;
15479
15480 if (INTEL_INFO(dev)->num_pipes == 1)
15481 return true;
15482
15483 val = I915_READ(DSPCNTR(!crtc->plane));
15484
15485 if ((val & DISPLAY_PLANE_ENABLE) &&
15486 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15487 return false;
15488
15489 return true;
15490 }
15491
15492 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15493 {
15494 struct drm_device *dev = crtc->base.dev;
15495 struct intel_encoder *encoder;
15496
15497 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15498 return true;
15499
15500 return false;
15501 }
15502
15503 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15504 {
15505 struct drm_device *dev = crtc->base.dev;
15506 struct drm_i915_private *dev_priv = dev->dev_private;
15507 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15508
15509 /* Clear any frame start delays used for debugging left by the BIOS */
15510 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15511
15512 /* restore vblank interrupts to correct state */
15513 drm_crtc_vblank_reset(&crtc->base);
15514 if (crtc->active) {
15515 struct intel_plane *plane;
15516
15517 drm_crtc_vblank_on(&crtc->base);
15518
15519 /* Disable everything but the primary plane */
15520 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15521 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15522 continue;
15523
15524 plane->disable_plane(&plane->base, &crtc->base);
15525 }
15526 }
15527
15528 /* We need to sanitize the plane -> pipe mapping first because this will
15529 * disable the crtc (and hence change the state) if it is wrong. Note
15530 * that gen4+ has a fixed plane -> pipe mapping. */
15531 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15532 bool plane;
15533
15534 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15535 crtc->base.base.id);
15536
15537 /* Pipe has the wrong plane attached and the plane is active.
15538 * Temporarily change the plane mapping and disable everything
15539 * ... */
15540 plane = crtc->plane;
15541 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15542 crtc->plane = !plane;
15543 intel_crtc_disable_noatomic(&crtc->base);
15544 crtc->plane = plane;
15545 }
15546
15547 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15548 crtc->pipe == PIPE_A && !crtc->active) {
15549 /* BIOS forgot to enable pipe A, this mostly happens after
15550 * resume. Force-enable the pipe to fix this, the update_dpms
15551 * call below we restore the pipe to the right state, but leave
15552 * the required bits on. */
15553 intel_enable_pipe_a(dev);
15554 }
15555
15556 /* Adjust the state of the output pipe according to whether we
15557 * have active connectors/encoders. */
15558 if (!intel_crtc_has_encoders(crtc))
15559 intel_crtc_disable_noatomic(&crtc->base);
15560
15561 if (crtc->active != crtc->base.state->active) {
15562 struct intel_encoder *encoder;
15563
15564 /* This can happen either due to bugs in the get_hw_state
15565 * functions or because of calls to intel_crtc_disable_noatomic,
15566 * or because the pipe is force-enabled due to the
15567 * pipe A quirk. */
15568 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15569 crtc->base.base.id,
15570 crtc->base.state->enable ? "enabled" : "disabled",
15571 crtc->active ? "enabled" : "disabled");
15572
15573 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15574 crtc->base.state->active = crtc->active;
15575 crtc->base.enabled = crtc->active;
15576 crtc->base.state->connector_mask = 0;
15577
15578 /* Because we only establish the connector -> encoder ->
15579 * crtc links if something is active, this means the
15580 * crtc is now deactivated. Break the links. connector
15581 * -> encoder links are only establish when things are
15582 * actually up, hence no need to break them. */
15583 WARN_ON(crtc->active);
15584
15585 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15586 encoder->base.crtc = NULL;
15587 }
15588
15589 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15590 /*
15591 * We start out with underrun reporting disabled to avoid races.
15592 * For correct bookkeeping mark this on active crtcs.
15593 *
15594 * Also on gmch platforms we dont have any hardware bits to
15595 * disable the underrun reporting. Which means we need to start
15596 * out with underrun reporting disabled also on inactive pipes,
15597 * since otherwise we'll complain about the garbage we read when
15598 * e.g. coming up after runtime pm.
15599 *
15600 * No protection against concurrent access is required - at
15601 * worst a fifo underrun happens which also sets this to false.
15602 */
15603 crtc->cpu_fifo_underrun_disabled = true;
15604 crtc->pch_fifo_underrun_disabled = true;
15605 }
15606 }
15607
15608 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15609 {
15610 struct intel_connector *connector;
15611 struct drm_device *dev = encoder->base.dev;
15612 bool active = false;
15613
15614 /* We need to check both for a crtc link (meaning that the
15615 * encoder is active and trying to read from a pipe) and the
15616 * pipe itself being active. */
15617 bool has_active_crtc = encoder->base.crtc &&
15618 to_intel_crtc(encoder->base.crtc)->active;
15619
15620 for_each_intel_connector(dev, connector) {
15621 if (connector->base.encoder != &encoder->base)
15622 continue;
15623
15624 active = true;
15625 break;
15626 }
15627
15628 if (active && !has_active_crtc) {
15629 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15630 encoder->base.base.id,
15631 encoder->base.name);
15632
15633 /* Connector is active, but has no active pipe. This is
15634 * fallout from our resume register restoring. Disable
15635 * the encoder manually again. */
15636 if (encoder->base.crtc) {
15637 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15638 encoder->base.base.id,
15639 encoder->base.name);
15640 encoder->disable(encoder);
15641 if (encoder->post_disable)
15642 encoder->post_disable(encoder);
15643 }
15644 encoder->base.crtc = NULL;
15645
15646 /* Inconsistent output/port/pipe state happens presumably due to
15647 * a bug in one of the get_hw_state functions. Or someplace else
15648 * in our code, like the register restore mess on resume. Clamp
15649 * things to off as a safer default. */
15650 for_each_intel_connector(dev, connector) {
15651 if (connector->encoder != encoder)
15652 continue;
15653 connector->base.dpms = DRM_MODE_DPMS_OFF;
15654 connector->base.encoder = NULL;
15655 }
15656 }
15657 /* Enabled encoders without active connectors will be fixed in
15658 * the crtc fixup. */
15659 }
15660
15661 void i915_redisable_vga_power_on(struct drm_device *dev)
15662 {
15663 struct drm_i915_private *dev_priv = dev->dev_private;
15664 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15665
15666 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15667 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15668 i915_disable_vga(dev);
15669 }
15670 }
15671
15672 void i915_redisable_vga(struct drm_device *dev)
15673 {
15674 struct drm_i915_private *dev_priv = dev->dev_private;
15675
15676 /* This function can be called both from intel_modeset_setup_hw_state or
15677 * at a very early point in our resume sequence, where the power well
15678 * structures are not yet restored. Since this function is at a very
15679 * paranoid "someone might have enabled VGA while we were not looking"
15680 * level, just check if the power well is enabled instead of trying to
15681 * follow the "don't touch the power well if we don't need it" policy
15682 * the rest of the driver uses. */
15683 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15684 return;
15685
15686 i915_redisable_vga_power_on(dev);
15687 }
15688
15689 static bool primary_get_hw_state(struct intel_plane *plane)
15690 {
15691 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15692
15693 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15694 }
15695
15696 /* FIXME read out full plane state for all planes */
15697 static void readout_plane_state(struct intel_crtc *crtc)
15698 {
15699 struct drm_plane *primary = crtc->base.primary;
15700 struct intel_plane_state *plane_state =
15701 to_intel_plane_state(primary->state);
15702
15703 plane_state->visible = crtc->active &&
15704 primary_get_hw_state(to_intel_plane(primary));
15705
15706 if (plane_state->visible)
15707 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15708 }
15709
15710 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15711 {
15712 struct drm_i915_private *dev_priv = dev->dev_private;
15713 enum pipe pipe;
15714 struct intel_crtc *crtc;
15715 struct intel_encoder *encoder;
15716 struct intel_connector *connector;
15717 int i;
15718
15719 dev_priv->active_crtcs = 0;
15720
15721 for_each_intel_crtc(dev, crtc) {
15722 struct intel_crtc_state *crtc_state = crtc->config;
15723 int pixclk = 0;
15724
15725 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15726 memset(crtc_state, 0, sizeof(*crtc_state));
15727 crtc_state->base.crtc = &crtc->base;
15728
15729 crtc_state->base.active = crtc_state->base.enable =
15730 dev_priv->display.get_pipe_config(crtc, crtc_state);
15731
15732 crtc->base.enabled = crtc_state->base.enable;
15733 crtc->active = crtc_state->base.active;
15734
15735 if (crtc_state->base.active) {
15736 dev_priv->active_crtcs |= 1 << crtc->pipe;
15737
15738 if (IS_BROADWELL(dev_priv)) {
15739 pixclk = ilk_pipe_pixel_rate(crtc_state);
15740
15741 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15742 if (crtc_state->ips_enabled)
15743 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15744 } else if (IS_VALLEYVIEW(dev_priv) ||
15745 IS_CHERRYVIEW(dev_priv) ||
15746 IS_BROXTON(dev_priv))
15747 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15748 else
15749 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15750 }
15751
15752 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15753
15754 readout_plane_state(crtc);
15755
15756 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15757 crtc->base.base.id,
15758 crtc->active ? "enabled" : "disabled");
15759 }
15760
15761 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15762 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15763
15764 pll->on = pll->get_hw_state(dev_priv, pll,
15765 &pll->config.hw_state);
15766 pll->active = 0;
15767 pll->config.crtc_mask = 0;
15768 for_each_intel_crtc(dev, crtc) {
15769 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15770 pll->active++;
15771 pll->config.crtc_mask |= 1 << crtc->pipe;
15772 }
15773 }
15774
15775 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15776 pll->name, pll->config.crtc_mask, pll->on);
15777
15778 if (pll->config.crtc_mask)
15779 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15780 }
15781
15782 for_each_intel_encoder(dev, encoder) {
15783 pipe = 0;
15784
15785 if (encoder->get_hw_state(encoder, &pipe)) {
15786 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15787 encoder->base.crtc = &crtc->base;
15788 encoder->get_config(encoder, crtc->config);
15789 } else {
15790 encoder->base.crtc = NULL;
15791 }
15792
15793 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15794 encoder->base.base.id,
15795 encoder->base.name,
15796 encoder->base.crtc ? "enabled" : "disabled",
15797 pipe_name(pipe));
15798 }
15799
15800 for_each_intel_connector(dev, connector) {
15801 if (connector->get_hw_state(connector)) {
15802 connector->base.dpms = DRM_MODE_DPMS_ON;
15803
15804 encoder = connector->encoder;
15805 connector->base.encoder = &encoder->base;
15806
15807 if (encoder->base.crtc &&
15808 encoder->base.crtc->state->active) {
15809 /*
15810 * This has to be done during hardware readout
15811 * because anything calling .crtc_disable may
15812 * rely on the connector_mask being accurate.
15813 */
15814 encoder->base.crtc->state->connector_mask |=
15815 1 << drm_connector_index(&connector->base);
15816 }
15817
15818 } else {
15819 connector->base.dpms = DRM_MODE_DPMS_OFF;
15820 connector->base.encoder = NULL;
15821 }
15822 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15823 connector->base.base.id,
15824 connector->base.name,
15825 connector->base.encoder ? "enabled" : "disabled");
15826 }
15827
15828 for_each_intel_crtc(dev, crtc) {
15829 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15830
15831 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15832 if (crtc->base.state->active) {
15833 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15834 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15835 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15836
15837 /*
15838 * The initial mode needs to be set in order to keep
15839 * the atomic core happy. It wants a valid mode if the
15840 * crtc's enabled, so we do the above call.
15841 *
15842 * At this point some state updated by the connectors
15843 * in their ->detect() callback has not run yet, so
15844 * no recalculation can be done yet.
15845 *
15846 * Even if we could do a recalculation and modeset
15847 * right now it would cause a double modeset if
15848 * fbdev or userspace chooses a different initial mode.
15849 *
15850 * If that happens, someone indicated they wanted a
15851 * mode change, which means it's safe to do a full
15852 * recalculation.
15853 */
15854 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15855
15856 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15857 update_scanline_offset(crtc);
15858 }
15859 }
15860 }
15861
15862 /* Scan out the current hw modeset state,
15863 * and sanitizes it to the current state
15864 */
15865 static void
15866 intel_modeset_setup_hw_state(struct drm_device *dev)
15867 {
15868 struct drm_i915_private *dev_priv = dev->dev_private;
15869 enum pipe pipe;
15870 struct intel_crtc *crtc;
15871 struct intel_encoder *encoder;
15872 int i;
15873
15874 intel_modeset_readout_hw_state(dev);
15875
15876 /* HW state is read out, now we need to sanitize this mess. */
15877 for_each_intel_encoder(dev, encoder) {
15878 intel_sanitize_encoder(encoder);
15879 }
15880
15881 for_each_pipe(dev_priv, pipe) {
15882 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15883 intel_sanitize_crtc(crtc);
15884 intel_dump_pipe_config(crtc, crtc->config,
15885 "[setup_hw_state]");
15886 }
15887
15888 intel_modeset_update_connector_atomic_state(dev);
15889
15890 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15891 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15892
15893 if (!pll->on || pll->active)
15894 continue;
15895
15896 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15897
15898 pll->disable(dev_priv, pll);
15899 pll->on = false;
15900 }
15901
15902 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15903 vlv_wm_get_hw_state(dev);
15904 else if (IS_GEN9(dev))
15905 skl_wm_get_hw_state(dev);
15906 else if (HAS_PCH_SPLIT(dev))
15907 ilk_wm_get_hw_state(dev);
15908
15909 for_each_intel_crtc(dev, crtc) {
15910 unsigned long put_domains;
15911
15912 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15913 if (WARN_ON(put_domains))
15914 modeset_put_power_domains(dev_priv, put_domains);
15915 }
15916 intel_display_set_init_power(dev_priv, false);
15917
15918 intel_fbc_init_pipe_state(dev_priv);
15919 }
15920
15921 void intel_display_resume(struct drm_device *dev)
15922 {
15923 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15924 struct intel_connector *conn;
15925 struct intel_plane *plane;
15926 struct drm_crtc *crtc;
15927 int ret;
15928
15929 if (!state)
15930 return;
15931
15932 state->acquire_ctx = dev->mode_config.acquire_ctx;
15933
15934 /* preserve complete old state, including dpll */
15935 intel_atomic_get_shared_dpll_state(state);
15936
15937 for_each_crtc(dev, crtc) {
15938 struct drm_crtc_state *crtc_state =
15939 drm_atomic_get_crtc_state(state, crtc);
15940
15941 ret = PTR_ERR_OR_ZERO(crtc_state);
15942 if (ret)
15943 goto err;
15944
15945 /* force a restore */
15946 crtc_state->mode_changed = true;
15947 }
15948
15949 for_each_intel_plane(dev, plane) {
15950 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15951 if (ret)
15952 goto err;
15953 }
15954
15955 for_each_intel_connector(dev, conn) {
15956 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15957 if (ret)
15958 goto err;
15959 }
15960
15961 intel_modeset_setup_hw_state(dev);
15962
15963 i915_redisable_vga(dev);
15964 ret = drm_atomic_commit(state);
15965 if (!ret)
15966 return;
15967
15968 err:
15969 DRM_ERROR("Restoring old state failed with %i\n", ret);
15970 drm_atomic_state_free(state);
15971 }
15972
15973 void intel_modeset_gem_init(struct drm_device *dev)
15974 {
15975 struct drm_crtc *c;
15976 struct drm_i915_gem_object *obj;
15977 int ret;
15978
15979 mutex_lock(&dev->struct_mutex);
15980 intel_init_gt_powersave(dev);
15981 mutex_unlock(&dev->struct_mutex);
15982
15983 intel_modeset_init_hw(dev);
15984
15985 intel_setup_overlay(dev);
15986
15987 /*
15988 * Make sure any fbs we allocated at startup are properly
15989 * pinned & fenced. When we do the allocation it's too early
15990 * for this.
15991 */
15992 for_each_crtc(dev, c) {
15993 obj = intel_fb_obj(c->primary->fb);
15994 if (obj == NULL)
15995 continue;
15996
15997 mutex_lock(&dev->struct_mutex);
15998 ret = intel_pin_and_fence_fb_obj(c->primary,
15999 c->primary->fb,
16000 c->primary->state);
16001 mutex_unlock(&dev->struct_mutex);
16002 if (ret) {
16003 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16004 to_intel_crtc(c)->pipe);
16005 drm_framebuffer_unreference(c->primary->fb);
16006 c->primary->fb = NULL;
16007 c->primary->crtc = c->primary->state->crtc = NULL;
16008 update_state_fb(c->primary);
16009 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16010 }
16011 }
16012
16013 intel_backlight_register(dev);
16014 }
16015
16016 void intel_connector_unregister(struct intel_connector *intel_connector)
16017 {
16018 struct drm_connector *connector = &intel_connector->base;
16019
16020 intel_panel_destroy_backlight(connector);
16021 drm_connector_unregister(connector);
16022 }
16023
16024 void intel_modeset_cleanup(struct drm_device *dev)
16025 {
16026 struct drm_i915_private *dev_priv = dev->dev_private;
16027 struct intel_connector *connector;
16028
16029 intel_disable_gt_powersave(dev);
16030
16031 intel_backlight_unregister(dev);
16032
16033 /*
16034 * Interrupts and polling as the first thing to avoid creating havoc.
16035 * Too much stuff here (turning of connectors, ...) would
16036 * experience fancy races otherwise.
16037 */
16038 intel_irq_uninstall(dev_priv);
16039
16040 /*
16041 * Due to the hpd irq storm handling the hotplug work can re-arm the
16042 * poll handlers. Hence disable polling after hpd handling is shut down.
16043 */
16044 drm_kms_helper_poll_fini(dev);
16045
16046 intel_unregister_dsm_handler();
16047
16048 intel_fbc_global_disable(dev_priv);
16049
16050 /* flush any delayed tasks or pending work */
16051 flush_scheduled_work();
16052
16053 /* destroy the backlight and sysfs files before encoders/connectors */
16054 for_each_intel_connector(dev, connector)
16055 connector->unregister(connector);
16056
16057 drm_mode_config_cleanup(dev);
16058
16059 intel_cleanup_overlay(dev);
16060
16061 mutex_lock(&dev->struct_mutex);
16062 intel_cleanup_gt_powersave(dev);
16063 mutex_unlock(&dev->struct_mutex);
16064
16065 intel_teardown_gmbus(dev);
16066 }
16067
16068 /*
16069 * Return which encoder is currently attached for connector.
16070 */
16071 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16072 {
16073 return &intel_attached_encoder(connector)->base;
16074 }
16075
16076 void intel_connector_attach_encoder(struct intel_connector *connector,
16077 struct intel_encoder *encoder)
16078 {
16079 connector->encoder = encoder;
16080 drm_mode_connector_attach_encoder(&connector->base,
16081 &encoder->base);
16082 }
16083
16084 /*
16085 * set vga decode state - true == enable VGA decode
16086 */
16087 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16088 {
16089 struct drm_i915_private *dev_priv = dev->dev_private;
16090 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16091 u16 gmch_ctrl;
16092
16093 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16094 DRM_ERROR("failed to read control word\n");
16095 return -EIO;
16096 }
16097
16098 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16099 return 0;
16100
16101 if (state)
16102 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16103 else
16104 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16105
16106 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16107 DRM_ERROR("failed to write control word\n");
16108 return -EIO;
16109 }
16110
16111 return 0;
16112 }
16113
16114 struct intel_display_error_state {
16115
16116 u32 power_well_driver;
16117
16118 int num_transcoders;
16119
16120 struct intel_cursor_error_state {
16121 u32 control;
16122 u32 position;
16123 u32 base;
16124 u32 size;
16125 } cursor[I915_MAX_PIPES];
16126
16127 struct intel_pipe_error_state {
16128 bool power_domain_on;
16129 u32 source;
16130 u32 stat;
16131 } pipe[I915_MAX_PIPES];
16132
16133 struct intel_plane_error_state {
16134 u32 control;
16135 u32 stride;
16136 u32 size;
16137 u32 pos;
16138 u32 addr;
16139 u32 surface;
16140 u32 tile_offset;
16141 } plane[I915_MAX_PIPES];
16142
16143 struct intel_transcoder_error_state {
16144 bool power_domain_on;
16145 enum transcoder cpu_transcoder;
16146
16147 u32 conf;
16148
16149 u32 htotal;
16150 u32 hblank;
16151 u32 hsync;
16152 u32 vtotal;
16153 u32 vblank;
16154 u32 vsync;
16155 } transcoder[4];
16156 };
16157
16158 struct intel_display_error_state *
16159 intel_display_capture_error_state(struct drm_device *dev)
16160 {
16161 struct drm_i915_private *dev_priv = dev->dev_private;
16162 struct intel_display_error_state *error;
16163 int transcoders[] = {
16164 TRANSCODER_A,
16165 TRANSCODER_B,
16166 TRANSCODER_C,
16167 TRANSCODER_EDP,
16168 };
16169 int i;
16170
16171 if (INTEL_INFO(dev)->num_pipes == 0)
16172 return NULL;
16173
16174 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16175 if (error == NULL)
16176 return NULL;
16177
16178 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16179 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16180
16181 for_each_pipe(dev_priv, i) {
16182 error->pipe[i].power_domain_on =
16183 __intel_display_power_is_enabled(dev_priv,
16184 POWER_DOMAIN_PIPE(i));
16185 if (!error->pipe[i].power_domain_on)
16186 continue;
16187
16188 error->cursor[i].control = I915_READ(CURCNTR(i));
16189 error->cursor[i].position = I915_READ(CURPOS(i));
16190 error->cursor[i].base = I915_READ(CURBASE(i));
16191
16192 error->plane[i].control = I915_READ(DSPCNTR(i));
16193 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16194 if (INTEL_INFO(dev)->gen <= 3) {
16195 error->plane[i].size = I915_READ(DSPSIZE(i));
16196 error->plane[i].pos = I915_READ(DSPPOS(i));
16197 }
16198 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16199 error->plane[i].addr = I915_READ(DSPADDR(i));
16200 if (INTEL_INFO(dev)->gen >= 4) {
16201 error->plane[i].surface = I915_READ(DSPSURF(i));
16202 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16203 }
16204
16205 error->pipe[i].source = I915_READ(PIPESRC(i));
16206
16207 if (HAS_GMCH_DISPLAY(dev))
16208 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16209 }
16210
16211 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16212 if (HAS_DDI(dev_priv->dev))
16213 error->num_transcoders++; /* Account for eDP. */
16214
16215 for (i = 0; i < error->num_transcoders; i++) {
16216 enum transcoder cpu_transcoder = transcoders[i];
16217
16218 error->transcoder[i].power_domain_on =
16219 __intel_display_power_is_enabled(dev_priv,
16220 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16221 if (!error->transcoder[i].power_domain_on)
16222 continue;
16223
16224 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16225
16226 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16227 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16228 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16229 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16230 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16231 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16232 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16233 }
16234
16235 return error;
16236 }
16237
16238 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16239
16240 void
16241 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16242 struct drm_device *dev,
16243 struct intel_display_error_state *error)
16244 {
16245 struct drm_i915_private *dev_priv = dev->dev_private;
16246 int i;
16247
16248 if (!error)
16249 return;
16250
16251 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16252 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16253 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16254 error->power_well_driver);
16255 for_each_pipe(dev_priv, i) {
16256 err_printf(m, "Pipe [%d]:\n", i);
16257 err_printf(m, " Power: %s\n",
16258 onoff(error->pipe[i].power_domain_on));
16259 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16260 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16261
16262 err_printf(m, "Plane [%d]:\n", i);
16263 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16264 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16265 if (INTEL_INFO(dev)->gen <= 3) {
16266 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16267 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16268 }
16269 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16270 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16271 if (INTEL_INFO(dev)->gen >= 4) {
16272 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16273 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16274 }
16275
16276 err_printf(m, "Cursor [%d]:\n", i);
16277 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16278 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16279 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16280 }
16281
16282 for (i = 0; i < error->num_transcoders; i++) {
16283 err_printf(m, "CPU transcoder: %c\n",
16284 transcoder_name(error->transcoder[i].cpu_transcoder));
16285 err_printf(m, " Power: %s\n",
16286 onoff(error->transcoder[i].power_domain_on));
16287 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16288 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16289 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16290 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16291 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16292 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16293 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16294 }
16295 }
16296
16297 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16298 {
16299 struct intel_crtc *crtc;
16300
16301 for_each_intel_crtc(dev, crtc) {
16302 struct intel_unpin_work *work;
16303
16304 spin_lock_irq(&dev->event_lock);
16305
16306 work = crtc->unpin_work;
16307
16308 if (work && work->event &&
16309 work->event->base.file_priv == file) {
16310 kfree(work->event);
16311 work->event = NULL;
16312 }
16313
16314 spin_unlock_irq(&dev->event_lock);
16315 }
16316 }
Linux kernel - Deliverables
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