2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 908000, .max
= 1512000 },
94 .n
= { .min
= 2, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 908000, .max
= 1512000 },
107 .n
= { .min
= 2, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 908000, .max
= 1512000 },
120 .n
= { .min
= 2, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv
= {
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
319 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
320 .vco
= { .min
= 4000000, .max
= 6000000 },
321 .n
= { .min
= 1, .max
= 7 },
322 .m1
= { .min
= 2, .max
= 3 },
323 .m2
= { .min
= 11, .max
= 156 },
324 .p1
= { .min
= 2, .max
= 3 },
325 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
328 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
330 clock
->m
= clock
->m1
* clock
->m2
;
331 clock
->p
= clock
->p1
* clock
->p2
;
332 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
334 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
335 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
343 struct drm_device
*dev
= crtc
->dev
;
344 struct intel_encoder
*encoder
;
346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
347 if (encoder
->type
== type
)
353 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
356 struct drm_device
*dev
= crtc
->dev
;
357 const intel_limit_t
*limit
;
359 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
360 if (intel_is_dual_link_lvds(dev
)) {
361 if (refclk
== 100000)
362 limit
= &intel_limits_ironlake_dual_lvds_100m
;
364 limit
= &intel_limits_ironlake_dual_lvds
;
366 if (refclk
== 100000)
367 limit
= &intel_limits_ironlake_single_lvds_100m
;
369 limit
= &intel_limits_ironlake_single_lvds
;
372 limit
= &intel_limits_ironlake_dac
;
377 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
379 struct drm_device
*dev
= crtc
->dev
;
380 const intel_limit_t
*limit
;
382 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
383 if (intel_is_dual_link_lvds(dev
))
384 limit
= &intel_limits_g4x_dual_channel_lvds
;
386 limit
= &intel_limits_g4x_single_channel_lvds
;
387 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
388 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
389 limit
= &intel_limits_g4x_hdmi
;
390 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
391 limit
= &intel_limits_g4x_sdvo
;
392 } else /* The option is for other outputs */
393 limit
= &intel_limits_i9xx_sdvo
;
398 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
400 struct drm_device
*dev
= crtc
->dev
;
401 const intel_limit_t
*limit
;
403 if (HAS_PCH_SPLIT(dev
))
404 limit
= intel_ironlake_limit(crtc
, refclk
);
405 else if (IS_G4X(dev
)) {
406 limit
= intel_g4x_limit(crtc
);
407 } else if (IS_PINEVIEW(dev
)) {
408 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
409 limit
= &intel_limits_pineview_lvds
;
411 limit
= &intel_limits_pineview_sdvo
;
412 } else if (IS_VALLEYVIEW(dev
)) {
413 limit
= &intel_limits_vlv
;
414 } else if (!IS_GEN2(dev
)) {
415 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
416 limit
= &intel_limits_i9xx_lvds
;
418 limit
= &intel_limits_i9xx_sdvo
;
420 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
421 limit
= &intel_limits_i8xx_lvds
;
422 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
423 limit
= &intel_limits_i8xx_dvo
;
425 limit
= &intel_limits_i8xx_dac
;
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
433 clock
->m
= clock
->m2
+ 2;
434 clock
->p
= clock
->p1
* clock
->p2
;
435 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
437 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
438 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
441 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
443 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
446 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
448 clock
->m
= i9xx_dpll_compute_m(clock
);
449 clock
->p
= clock
->p1
* clock
->p2
;
450 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
452 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
453 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
462 static bool intel_PLL_is_valid(struct drm_device
*dev
,
463 const intel_limit_t
*limit
,
464 const intel_clock_t
*clock
)
466 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
467 INTELPllInvalid("n out of range\n");
468 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
469 INTELPllInvalid("p1 out of range\n");
470 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
473 INTELPllInvalid("m1 out of range\n");
475 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
476 if (clock
->m1
<= clock
->m2
)
477 INTELPllInvalid("m1 <= m2\n");
479 if (!IS_VALLEYVIEW(dev
)) {
480 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
481 INTELPllInvalid("p out of range\n");
482 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
483 INTELPllInvalid("m out of range\n");
486 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
487 INTELPllInvalid("vco out of range\n");
488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
491 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
492 INTELPllInvalid("dot out of range\n");
498 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
499 int target
, int refclk
, intel_clock_t
*match_clock
,
500 intel_clock_t
*best_clock
)
502 struct drm_device
*dev
= crtc
->dev
;
506 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
512 if (intel_is_dual_link_lvds(dev
))
513 clock
.p2
= limit
->p2
.p2_fast
;
515 clock
.p2
= limit
->p2
.p2_slow
;
517 if (target
< limit
->p2
.dot_limit
)
518 clock
.p2
= limit
->p2
.p2_slow
;
520 clock
.p2
= limit
->p2
.p2_fast
;
523 memset(best_clock
, 0, sizeof(*best_clock
));
525 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
527 for (clock
.m2
= limit
->m2
.min
;
528 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
529 if (clock
.m2
>= clock
.m1
)
531 for (clock
.n
= limit
->n
.min
;
532 clock
.n
<= limit
->n
.max
; clock
.n
++) {
533 for (clock
.p1
= limit
->p1
.min
;
534 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
537 i9xx_clock(refclk
, &clock
);
538 if (!intel_PLL_is_valid(dev
, limit
,
542 clock
.p
!= match_clock
->p
)
545 this_err
= abs(clock
.dot
- target
);
546 if (this_err
< err
) {
555 return (err
!= target
);
559 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
560 int target
, int refclk
, intel_clock_t
*match_clock
,
561 intel_clock_t
*best_clock
)
563 struct drm_device
*dev
= crtc
->dev
;
567 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
573 if (intel_is_dual_link_lvds(dev
))
574 clock
.p2
= limit
->p2
.p2_fast
;
576 clock
.p2
= limit
->p2
.p2_slow
;
578 if (target
< limit
->p2
.dot_limit
)
579 clock
.p2
= limit
->p2
.p2_slow
;
581 clock
.p2
= limit
->p2
.p2_fast
;
584 memset(best_clock
, 0, sizeof(*best_clock
));
586 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
588 for (clock
.m2
= limit
->m2
.min
;
589 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
590 for (clock
.n
= limit
->n
.min
;
591 clock
.n
<= limit
->n
.max
; clock
.n
++) {
592 for (clock
.p1
= limit
->p1
.min
;
593 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
596 pineview_clock(refclk
, &clock
);
597 if (!intel_PLL_is_valid(dev
, limit
,
601 clock
.p
!= match_clock
->p
)
604 this_err
= abs(clock
.dot
- target
);
605 if (this_err
< err
) {
614 return (err
!= target
);
618 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
619 int target
, int refclk
, intel_clock_t
*match_clock
,
620 intel_clock_t
*best_clock
)
622 struct drm_device
*dev
= crtc
->dev
;
626 /* approximately equals target * 0.00585 */
627 int err_most
= (target
>> 8) + (target
>> 9);
630 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
631 if (intel_is_dual_link_lvds(dev
))
632 clock
.p2
= limit
->p2
.p2_fast
;
634 clock
.p2
= limit
->p2
.p2_slow
;
636 if (target
< limit
->p2
.dot_limit
)
637 clock
.p2
= limit
->p2
.p2_slow
;
639 clock
.p2
= limit
->p2
.p2_fast
;
642 memset(best_clock
, 0, sizeof(*best_clock
));
643 max_n
= limit
->n
.max
;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock
.m1
= limit
->m1
.max
;
648 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
649 for (clock
.m2
= limit
->m2
.max
;
650 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
651 for (clock
.p1
= limit
->p1
.max
;
652 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
655 i9xx_clock(refclk
, &clock
);
656 if (!intel_PLL_is_valid(dev
, limit
,
660 this_err
= abs(clock
.dot
- target
);
661 if (this_err
< err_most
) {
675 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
676 int target
, int refclk
, intel_clock_t
*match_clock
,
677 intel_clock_t
*best_clock
)
679 struct drm_device
*dev
= crtc
->dev
;
681 unsigned int bestppm
= 1000000;
682 /* min update 19.2 MHz */
683 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
686 target
*= 5; /* fast clock */
688 memset(best_clock
, 0, sizeof(*best_clock
));
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
692 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
693 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
694 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
695 clock
.p
= clock
.p1
* clock
.p2
;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
698 unsigned int ppm
, diff
;
700 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
703 vlv_clock(refclk
, &clock
);
705 if (!intel_PLL_is_valid(dev
, limit
,
709 diff
= abs(clock
.dot
- target
);
710 ppm
= div_u64(1000000ULL * diff
, target
);
712 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
718 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
731 bool intel_crtc_active(struct drm_crtc
*crtc
)
733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
738 * We can ditch the adjusted_mode.crtc_clock check as soon
739 * as Haswell has gained clock readout/fastboot support.
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
744 return intel_crtc
->active
&& crtc
->fb
&&
745 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
748 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
751 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
752 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
754 return intel_crtc
->config
.cpu_transcoder
;
757 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
760 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
762 frame
= I915_READ(frame_reg
);
764 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
769 * intel_wait_for_vblank - wait for vblank on a given pipe
771 * @pipe: pipe to wait for
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
776 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
779 int pipestat_reg
= PIPESTAT(pipe
);
781 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
782 g4x_wait_for_vblank(dev
, pipe
);
786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
799 I915_WRITE(pipestat_reg
,
800 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
802 /* Wait for vblank interrupt bit to set */
803 if (wait_for(I915_READ(pipestat_reg
) &
804 PIPE_VBLANK_INTERRUPT_STATUS
,
806 DRM_DEBUG_KMS("vblank wait timed out\n");
809 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
811 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
812 u32 reg
= PIPEDSL(pipe
);
817 line_mask
= DSL_LINEMASK_GEN2
;
819 line_mask
= DSL_LINEMASK_GEN3
;
821 line1
= I915_READ(reg
) & line_mask
;
823 line2
= I915_READ(reg
) & line_mask
;
825 return line1
== line2
;
829 * intel_wait_for_pipe_off - wait for pipe to turn off
831 * @pipe: pipe to wait for
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
838 * wait for the pipe register state bit to turn off
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
845 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
848 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
851 if (INTEL_INFO(dev
)->gen
>= 4) {
852 int reg
= PIPECONF(cpu_transcoder
);
854 /* Wait for the Pipe State to go off */
855 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
857 WARN(1, "pipe_off wait timed out\n");
859 /* Wait for the display line to settle */
860 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
861 WARN(1, "pipe_off wait timed out\n");
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
870 * Returns true if @port is connected, false otherwise.
872 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
873 struct intel_digital_port
*port
)
877 if (HAS_PCH_IBX(dev_priv
->dev
)) {
880 bit
= SDE_PORTB_HOTPLUG
;
883 bit
= SDE_PORTC_HOTPLUG
;
886 bit
= SDE_PORTD_HOTPLUG
;
894 bit
= SDE_PORTB_HOTPLUG_CPT
;
897 bit
= SDE_PORTC_HOTPLUG_CPT
;
900 bit
= SDE_PORTD_HOTPLUG_CPT
;
907 return I915_READ(SDEISR
) & bit
;
910 static const char *state_string(bool enabled
)
912 return enabled
? "on" : "off";
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private
*dev_priv
,
917 enum pipe pipe
, bool state
)
924 val
= I915_READ(reg
);
925 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
926 WARN(cur_state
!= state
,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state
), state_string(cur_state
));
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
937 mutex_lock(&dev_priv
->dpio_lock
);
938 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
939 mutex_unlock(&dev_priv
->dpio_lock
);
941 cur_state
= val
& DSI_PLL_VCO_EN
;
942 WARN(cur_state
!= state
,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state
), state_string(cur_state
));
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
949 struct intel_shared_dpll
*
950 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
952 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
954 if (crtc
->config
.shared_dpll
< 0)
957 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
961 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
962 struct intel_shared_dpll
*pll
,
966 struct intel_dpll_hw_state hw_state
;
968 if (HAS_PCH_LPT(dev_priv
->dev
)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
974 "asserting DPLL %s with no DPLL\n", state_string(state
)))
977 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
978 WARN(cur_state
!= state
,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll
->name
, state_string(state
), state_string(cur_state
));
983 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
984 enum pipe pipe
, bool state
)
989 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
992 if (HAS_DDI(dev_priv
->dev
)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
995 val
= I915_READ(reg
);
996 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
998 reg
= FDI_TX_CTL(pipe
);
999 val
= I915_READ(reg
);
1000 cur_state
= !!(val
& FDI_TX_ENABLE
);
1002 WARN(cur_state
!= state
,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state
), state_string(cur_state
));
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1009 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1010 enum pipe pipe
, bool state
)
1016 reg
= FDI_RX_CTL(pipe
);
1017 val
= I915_READ(reg
);
1018 cur_state
= !!(val
& FDI_RX_ENABLE
);
1019 WARN(cur_state
!= state
,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state
), state_string(cur_state
));
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv
->info
->gen
== 5)
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv
->dev
))
1040 reg
= FDI_TX_CTL(pipe
);
1041 val
= I915_READ(reg
);
1042 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1045 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1046 enum pipe pipe
, bool state
)
1052 reg
= FDI_RX_CTL(pipe
);
1053 val
= I915_READ(reg
);
1054 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1055 WARN(cur_state
!= state
,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state
), state_string(cur_state
));
1060 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1063 int pp_reg
, lvds_reg
;
1065 enum pipe panel_pipe
= PIPE_A
;
1068 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1069 pp_reg
= PCH_PP_CONTROL
;
1070 lvds_reg
= PCH_LVDS
;
1072 pp_reg
= PP_CONTROL
;
1076 val
= I915_READ(pp_reg
);
1077 if (!(val
& PANEL_POWER_ON
) ||
1078 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1081 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1082 panel_pipe
= PIPE_B
;
1084 WARN(panel_pipe
== pipe
&& locked
,
1085 "panel assertion failure, pipe %c regs locked\n",
1089 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1090 enum pipe pipe
, bool state
)
1092 struct drm_device
*dev
= dev_priv
->dev
;
1095 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1096 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1097 else if (IS_845G(dev
) || IS_I865G(dev
))
1098 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1100 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1102 WARN(cur_state
!= state
,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1109 void assert_pipe(struct drm_i915_private
*dev_priv
,
1110 enum pipe pipe
, bool state
)
1115 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1122 if (!intel_display_power_enabled(dev_priv
->dev
,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1126 reg
= PIPECONF(cpu_transcoder
);
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& PIPECONF_ENABLE
);
1131 WARN(cur_state
!= state
,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1136 static void assert_plane(struct drm_i915_private
*dev_priv
,
1137 enum plane plane
, bool state
)
1143 reg
= DSPCNTR(plane
);
1144 val
= I915_READ(reg
);
1145 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1146 WARN(cur_state
!= state
,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane
), state_string(state
), state_string(cur_state
));
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1154 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1157 struct drm_device
*dev
= dev_priv
->dev
;
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev
)->gen
>= 4) {
1164 reg
= DSPCNTR(pipe
);
1165 val
= I915_READ(reg
);
1166 WARN((val
& DISPLAY_PLANE_ENABLE
),
1167 "plane %c assertion failure, should be disabled but not\n",
1172 /* Need to check both planes against the pipe */
1175 val
= I915_READ(reg
);
1176 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1177 DISPPLANE_SEL_PIPE_SHIFT
;
1178 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i
), pipe_name(pipe
));
1184 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1187 struct drm_device
*dev
= dev_priv
->dev
;
1191 if (IS_VALLEYVIEW(dev
)) {
1192 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1193 reg
= SPCNTR(pipe
, i
);
1194 val
= I915_READ(reg
);
1195 WARN((val
& SP_ENABLE
),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe
, i
), pipe_name(pipe
));
1199 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1201 val
= I915_READ(reg
);
1202 WARN((val
& SPRITE_ENABLE
),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe
), pipe_name(pipe
));
1205 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1206 reg
= DVSCNTR(pipe
);
1207 val
= I915_READ(reg
);
1208 WARN((val
& DVS_ENABLE
),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe
), pipe_name(pipe
));
1214 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1219 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1221 val
= I915_READ(PCH_DREF_CONTROL
);
1222 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1223 DREF_SUPERSPREAD_SOURCE_MASK
));
1224 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1227 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1234 reg
= PCH_TRANSCONF(pipe
);
1235 val
= I915_READ(reg
);
1236 enabled
= !!(val
& TRANS_ENABLE
);
1238 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1243 enum pipe pipe
, u32 port_sel
, u32 val
)
1245 if ((val
& DP_PORT_EN
) == 0)
1248 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1249 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1250 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1251 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1254 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1260 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1261 enum pipe pipe
, u32 val
)
1263 if ((val
& SDVO_ENABLE
) == 0)
1266 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1267 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1270 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1276 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1277 enum pipe pipe
, u32 val
)
1279 if ((val
& LVDS_PORT_EN
) == 0)
1282 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1283 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1286 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1292 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1293 enum pipe pipe
, u32 val
)
1295 if ((val
& ADPA_DAC_ENABLE
) == 0)
1297 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1298 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1301 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1307 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1308 enum pipe pipe
, int reg
, u32 port_sel
)
1310 u32 val
= I915_READ(reg
);
1311 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1312 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1313 reg
, pipe_name(pipe
));
1315 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1316 && (val
& DP_PIPEB_SELECT
),
1317 "IBX PCH dp port still using transcoder B\n");
1320 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1321 enum pipe pipe
, int reg
)
1323 u32 val
= I915_READ(reg
);
1324 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1325 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1326 reg
, pipe_name(pipe
));
1328 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1329 && (val
& SDVO_PIPE_B_SELECT
),
1330 "IBX PCH hdmi port still using transcoder B\n");
1333 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1339 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1340 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1341 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1344 val
= I915_READ(reg
);
1345 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1346 "PCH VGA enabled on transcoder %c, should be disabled\n",
1350 val
= I915_READ(reg
);
1351 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1352 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1355 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1356 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1357 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1360 static void intel_init_dpio(struct drm_device
*dev
)
1362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1364 if (!IS_VALLEYVIEW(dev
))
1367 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1370 static void intel_reset_dpio(struct drm_device
*dev
)
1372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1374 if (!IS_VALLEYVIEW(dev
))
1378 * Enable the CRI clock source so we can get at the display and the
1379 * reference clock for VGA hotplug / manual detection.
1381 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
1382 DPLL_REFA_CLK_ENABLE_VLV
|
1383 DPLL_INTEGRATED_CRI_CLK_VLV
);
1386 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1387 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1388 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1389 * b. The other bits such as sfr settings / modesel may all be set
1392 * This should only be done on init and resume from S3 with both
1393 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1395 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
1398 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1400 struct drm_device
*dev
= crtc
->base
.dev
;
1401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1402 int reg
= DPLL(crtc
->pipe
);
1403 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1405 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1407 /* No really, not for ILK+ */
1408 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1410 /* PLL is protected by panel, make sure we can write it */
1411 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1412 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1414 I915_WRITE(reg
, dpll
);
1418 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1419 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1421 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1422 POSTING_READ(DPLL_MD(crtc
->pipe
));
1424 /* We do this three times for luck */
1425 I915_WRITE(reg
, dpll
);
1427 udelay(150); /* wait for warmup */
1428 I915_WRITE(reg
, dpll
);
1430 udelay(150); /* wait for warmup */
1431 I915_WRITE(reg
, dpll
);
1433 udelay(150); /* wait for warmup */
1436 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1438 struct drm_device
*dev
= crtc
->base
.dev
;
1439 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1440 int reg
= DPLL(crtc
->pipe
);
1441 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1443 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1445 /* No really, not for ILK+ */
1446 BUG_ON(dev_priv
->info
->gen
>= 5);
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1450 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1452 I915_WRITE(reg
, dpll
);
1454 /* Wait for the clocks to stabilize. */
1458 if (INTEL_INFO(dev
)->gen
>= 4) {
1459 I915_WRITE(DPLL_MD(crtc
->pipe
),
1460 crtc
->config
.dpll_hw_state
.dpll_md
);
1462 /* The pixel multiplier can only be updated once the
1463 * DPLL is enabled and the clocks are stable.
1465 * So write it again.
1467 I915_WRITE(reg
, dpll
);
1470 /* We do this three times for luck */
1471 I915_WRITE(reg
, dpll
);
1473 udelay(150); /* wait for warmup */
1474 I915_WRITE(reg
, dpll
);
1476 udelay(150); /* wait for warmup */
1477 I915_WRITE(reg
, dpll
);
1479 udelay(150); /* wait for warmup */
1483 * i9xx_disable_pll - disable a PLL
1484 * @dev_priv: i915 private structure
1485 * @pipe: pipe PLL to disable
1487 * Disable the PLL for @pipe, making sure the pipe is off first.
1489 * Note! This is for pre-ILK only.
1491 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1493 /* Don't disable pipe A or pipe A PLLs if needed */
1494 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1497 /* Make sure the pipe isn't still relying on us */
1498 assert_pipe_disabled(dev_priv
, pipe
);
1500 I915_WRITE(DPLL(pipe
), 0);
1501 POSTING_READ(DPLL(pipe
));
1504 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv
, pipe
);
1512 * Leave integrated clock source and reference clock enabled for pipe B.
1513 * The latter is needed for VGA hotplug / manual detection.
1516 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1517 I915_WRITE(DPLL(pipe
), val
);
1518 POSTING_READ(DPLL(pipe
));
1521 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1522 struct intel_digital_port
*dport
)
1526 switch (dport
->port
) {
1528 port_mask
= DPLL_PORTB_READY_MASK
;
1531 port_mask
= DPLL_PORTC_READY_MASK
;
1537 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1538 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1539 port_name(dport
->port
), I915_READ(DPLL(0)));
1543 * ironlake_enable_shared_dpll - enable PCH PLL
1544 * @dev_priv: i915 private structure
1545 * @pipe: pipe PLL to enable
1547 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1548 * drives the transcoder clock.
1550 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1552 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1553 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1555 /* PCH PLLs only available on ILK, SNB and IVB */
1556 BUG_ON(dev_priv
->info
->gen
< 5);
1557 if (WARN_ON(pll
== NULL
))
1560 if (WARN_ON(pll
->refcount
== 0))
1563 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1564 pll
->name
, pll
->active
, pll
->on
,
1565 crtc
->base
.base
.id
);
1567 if (pll
->active
++) {
1569 assert_shared_dpll_enabled(dev_priv
, pll
);
1574 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1575 pll
->enable(dev_priv
, pll
);
1579 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1581 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1582 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1584 /* PCH only available on ILK+ */
1585 BUG_ON(dev_priv
->info
->gen
< 5);
1586 if (WARN_ON(pll
== NULL
))
1589 if (WARN_ON(pll
->refcount
== 0))
1592 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1593 pll
->name
, pll
->active
, pll
->on
,
1594 crtc
->base
.base
.id
);
1596 if (WARN_ON(pll
->active
== 0)) {
1597 assert_shared_dpll_disabled(dev_priv
, pll
);
1601 assert_shared_dpll_enabled(dev_priv
, pll
);
1606 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1607 pll
->disable(dev_priv
, pll
);
1611 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1614 struct drm_device
*dev
= dev_priv
->dev
;
1615 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1616 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1617 uint32_t reg
, val
, pipeconf_val
;
1619 /* PCH only available on ILK+ */
1620 BUG_ON(dev_priv
->info
->gen
< 5);
1622 /* Make sure PCH DPLL is enabled */
1623 assert_shared_dpll_enabled(dev_priv
,
1624 intel_crtc_to_shared_dpll(intel_crtc
));
1626 /* FDI must be feeding us bits for PCH ports */
1627 assert_fdi_tx_enabled(dev_priv
, pipe
);
1628 assert_fdi_rx_enabled(dev_priv
, pipe
);
1630 if (HAS_PCH_CPT(dev
)) {
1631 /* Workaround: Set the timing override bit before enabling the
1632 * pch transcoder. */
1633 reg
= TRANS_CHICKEN2(pipe
);
1634 val
= I915_READ(reg
);
1635 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1636 I915_WRITE(reg
, val
);
1639 reg
= PCH_TRANSCONF(pipe
);
1640 val
= I915_READ(reg
);
1641 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1643 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1645 * make the BPC in transcoder be consistent with
1646 * that in pipeconf reg.
1648 val
&= ~PIPECONF_BPC_MASK
;
1649 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1652 val
&= ~TRANS_INTERLACE_MASK
;
1653 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1654 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1655 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1656 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1658 val
|= TRANS_INTERLACED
;
1660 val
|= TRANS_PROGRESSIVE
;
1662 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1663 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1664 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1667 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1668 enum transcoder cpu_transcoder
)
1670 u32 val
, pipeconf_val
;
1672 /* PCH only available on ILK+ */
1673 BUG_ON(dev_priv
->info
->gen
< 5);
1675 /* FDI must be feeding us bits for PCH ports */
1676 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1677 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1679 /* Workaround: set timing override bit. */
1680 val
= I915_READ(_TRANSA_CHICKEN2
);
1681 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1682 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1685 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1687 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1688 PIPECONF_INTERLACED_ILK
)
1689 val
|= TRANS_INTERLACED
;
1691 val
|= TRANS_PROGRESSIVE
;
1693 I915_WRITE(LPT_TRANSCONF
, val
);
1694 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1695 DRM_ERROR("Failed to enable PCH transcoder\n");
1698 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1701 struct drm_device
*dev
= dev_priv
->dev
;
1704 /* FDI relies on the transcoder */
1705 assert_fdi_tx_disabled(dev_priv
, pipe
);
1706 assert_fdi_rx_disabled(dev_priv
, pipe
);
1708 /* Ports must be off as well */
1709 assert_pch_ports_disabled(dev_priv
, pipe
);
1711 reg
= PCH_TRANSCONF(pipe
);
1712 val
= I915_READ(reg
);
1713 val
&= ~TRANS_ENABLE
;
1714 I915_WRITE(reg
, val
);
1715 /* wait for PCH transcoder off, transcoder state */
1716 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1717 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1719 if (!HAS_PCH_IBX(dev
)) {
1720 /* Workaround: Clear the timing override chicken bit again. */
1721 reg
= TRANS_CHICKEN2(pipe
);
1722 val
= I915_READ(reg
);
1723 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1724 I915_WRITE(reg
, val
);
1728 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1732 val
= I915_READ(LPT_TRANSCONF
);
1733 val
&= ~TRANS_ENABLE
;
1734 I915_WRITE(LPT_TRANSCONF
, val
);
1735 /* wait for PCH transcoder off, transcoder state */
1736 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1737 DRM_ERROR("Failed to disable PCH transcoder\n");
1739 /* Workaround: clear timing override bit. */
1740 val
= I915_READ(_TRANSA_CHICKEN2
);
1741 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1742 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1746 * intel_enable_pipe - enable a pipe, asserting requirements
1747 * @dev_priv: i915 private structure
1748 * @pipe: pipe to enable
1749 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1751 * Enable @pipe, making sure that various hardware specific requirements
1752 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1754 * @pipe should be %PIPE_A or %PIPE_B.
1756 * Will wait until the pipe is actually running (i.e. first vblank) before
1759 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1760 bool pch_port
, bool dsi
)
1762 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1764 enum pipe pch_transcoder
;
1768 assert_planes_disabled(dev_priv
, pipe
);
1769 assert_cursor_disabled(dev_priv
, pipe
);
1770 assert_sprites_disabled(dev_priv
, pipe
);
1772 if (HAS_PCH_LPT(dev_priv
->dev
))
1773 pch_transcoder
= TRANSCODER_A
;
1775 pch_transcoder
= pipe
;
1778 * A pipe without a PLL won't actually be able to drive bits from
1779 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1782 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1784 assert_dsi_pll_enabled(dev_priv
);
1786 assert_pll_enabled(dev_priv
, pipe
);
1789 /* if driving the PCH, we need FDI enabled */
1790 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1791 assert_fdi_tx_pll_enabled(dev_priv
,
1792 (enum pipe
) cpu_transcoder
);
1794 /* FIXME: assert CPU port conditions for SNB+ */
1797 reg
= PIPECONF(cpu_transcoder
);
1798 val
= I915_READ(reg
);
1799 if (val
& PIPECONF_ENABLE
)
1802 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1803 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1807 * intel_disable_pipe - disable a pipe, asserting requirements
1808 * @dev_priv: i915 private structure
1809 * @pipe: pipe to disable
1811 * Disable @pipe, making sure that various hardware specific requirements
1812 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1814 * @pipe should be %PIPE_A or %PIPE_B.
1816 * Will wait until the pipe has shut down before returning.
1818 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1821 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1827 * Make sure planes won't keep trying to pump pixels to us,
1828 * or we might hang the display.
1830 assert_planes_disabled(dev_priv
, pipe
);
1831 assert_cursor_disabled(dev_priv
, pipe
);
1832 assert_sprites_disabled(dev_priv
, pipe
);
1834 /* Don't disable pipe A or pipe A PLLs if needed */
1835 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1838 reg
= PIPECONF(cpu_transcoder
);
1839 val
= I915_READ(reg
);
1840 if ((val
& PIPECONF_ENABLE
) == 0)
1843 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1844 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1848 * Plane regs are double buffered, going from enabled->disabled needs a
1849 * trigger in order to latch. The display address reg provides this.
1851 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
1854 u32 reg
= dev_priv
->info
->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
1856 I915_WRITE(reg
, I915_READ(reg
));
1861 * intel_enable_primary_plane - enable the primary plane on a given pipe
1862 * @dev_priv: i915 private structure
1863 * @plane: plane to enable
1864 * @pipe: pipe being fed
1866 * Enable @plane on @pipe, making sure that @pipe is running first.
1868 static void intel_enable_primary_plane(struct drm_i915_private
*dev_priv
,
1869 enum plane plane
, enum pipe pipe
)
1871 struct intel_crtc
*intel_crtc
=
1872 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1876 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1877 assert_pipe_enabled(dev_priv
, pipe
);
1879 WARN(intel_crtc
->primary_enabled
, "Primary plane already enabled\n");
1881 intel_crtc
->primary_enabled
= true;
1883 reg
= DSPCNTR(plane
);
1884 val
= I915_READ(reg
);
1885 if (val
& DISPLAY_PLANE_ENABLE
)
1888 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1889 intel_flush_primary_plane(dev_priv
, plane
);
1890 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1894 * intel_disable_primary_plane - disable the primary plane
1895 * @dev_priv: i915 private structure
1896 * @plane: plane to disable
1897 * @pipe: pipe consuming the data
1899 * Disable @plane; should be an independent operation.
1901 static void intel_disable_primary_plane(struct drm_i915_private
*dev_priv
,
1902 enum plane plane
, enum pipe pipe
)
1904 struct intel_crtc
*intel_crtc
=
1905 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
1909 WARN(!intel_crtc
->primary_enabled
, "Primary plane already disabled\n");
1911 intel_crtc
->primary_enabled
= false;
1913 reg
= DSPCNTR(plane
);
1914 val
= I915_READ(reg
);
1915 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1918 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1919 intel_flush_primary_plane(dev_priv
, plane
);
1920 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1923 static bool need_vtd_wa(struct drm_device
*dev
)
1925 #ifdef CONFIG_INTEL_IOMMU
1926 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1933 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1934 struct drm_i915_gem_object
*obj
,
1935 struct intel_ring_buffer
*pipelined
)
1937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1941 switch (obj
->tiling_mode
) {
1942 case I915_TILING_NONE
:
1943 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1944 alignment
= 128 * 1024;
1945 else if (INTEL_INFO(dev
)->gen
>= 4)
1946 alignment
= 4 * 1024;
1948 alignment
= 64 * 1024;
1951 /* pin() will align the object as required by fence */
1955 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1961 /* Note that the w/a also requires 64 PTE of padding following the
1962 * bo. We currently fill all unused PTE with the shadow page and so
1963 * we should always have valid PTE following the scanout preventing
1966 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1967 alignment
= 256 * 1024;
1969 dev_priv
->mm
.interruptible
= false;
1970 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1972 goto err_interruptible
;
1974 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1975 * fence, whereas 965+ only requires a fence if using
1976 * framebuffer compression. For simplicity, we always install
1977 * a fence as the cost is not that onerous.
1979 ret
= i915_gem_object_get_fence(obj
);
1983 i915_gem_object_pin_fence(obj
);
1985 dev_priv
->mm
.interruptible
= true;
1989 i915_gem_object_unpin_from_display_plane(obj
);
1991 dev_priv
->mm
.interruptible
= true;
1995 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1997 i915_gem_object_unpin_fence(obj
);
1998 i915_gem_object_unpin_from_display_plane(obj
);
2001 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2002 * is assumed to be a power-of-two. */
2003 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2004 unsigned int tiling_mode
,
2008 if (tiling_mode
!= I915_TILING_NONE
) {
2009 unsigned int tile_rows
, tiles
;
2014 tiles
= *x
/ (512/cpp
);
2017 return tile_rows
* pitch
* 8 + tiles
* 4096;
2019 unsigned int offset
;
2021 offset
= *y
* pitch
+ *x
* cpp
;
2023 *x
= (offset
& 4095) / cpp
;
2024 return offset
& -4096;
2028 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2031 struct drm_device
*dev
= crtc
->dev
;
2032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2033 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2034 struct intel_framebuffer
*intel_fb
;
2035 struct drm_i915_gem_object
*obj
;
2036 int plane
= intel_crtc
->plane
;
2037 unsigned long linear_offset
;
2046 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2050 intel_fb
= to_intel_framebuffer(fb
);
2051 obj
= intel_fb
->obj
;
2053 reg
= DSPCNTR(plane
);
2054 dspcntr
= I915_READ(reg
);
2055 /* Mask out pixel format bits in case we change it */
2056 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2057 switch (fb
->pixel_format
) {
2059 dspcntr
|= DISPPLANE_8BPP
;
2061 case DRM_FORMAT_XRGB1555
:
2062 case DRM_FORMAT_ARGB1555
:
2063 dspcntr
|= DISPPLANE_BGRX555
;
2065 case DRM_FORMAT_RGB565
:
2066 dspcntr
|= DISPPLANE_BGRX565
;
2068 case DRM_FORMAT_XRGB8888
:
2069 case DRM_FORMAT_ARGB8888
:
2070 dspcntr
|= DISPPLANE_BGRX888
;
2072 case DRM_FORMAT_XBGR8888
:
2073 case DRM_FORMAT_ABGR8888
:
2074 dspcntr
|= DISPPLANE_RGBX888
;
2076 case DRM_FORMAT_XRGB2101010
:
2077 case DRM_FORMAT_ARGB2101010
:
2078 dspcntr
|= DISPPLANE_BGRX101010
;
2080 case DRM_FORMAT_XBGR2101010
:
2081 case DRM_FORMAT_ABGR2101010
:
2082 dspcntr
|= DISPPLANE_RGBX101010
;
2088 if (INTEL_INFO(dev
)->gen
>= 4) {
2089 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2090 dspcntr
|= DISPPLANE_TILED
;
2092 dspcntr
&= ~DISPPLANE_TILED
;
2096 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2098 I915_WRITE(reg
, dspcntr
);
2100 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2102 if (INTEL_INFO(dev
)->gen
>= 4) {
2103 intel_crtc
->dspaddr_offset
=
2104 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2105 fb
->bits_per_pixel
/ 8,
2107 linear_offset
-= intel_crtc
->dspaddr_offset
;
2109 intel_crtc
->dspaddr_offset
= linear_offset
;
2112 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2113 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2115 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2116 if (INTEL_INFO(dev
)->gen
>= 4) {
2117 I915_WRITE(DSPSURF(plane
),
2118 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2119 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2120 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2122 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2128 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2129 struct drm_framebuffer
*fb
, int x
, int y
)
2131 struct drm_device
*dev
= crtc
->dev
;
2132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2133 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2134 struct intel_framebuffer
*intel_fb
;
2135 struct drm_i915_gem_object
*obj
;
2136 int plane
= intel_crtc
->plane
;
2137 unsigned long linear_offset
;
2147 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2151 intel_fb
= to_intel_framebuffer(fb
);
2152 obj
= intel_fb
->obj
;
2154 reg
= DSPCNTR(plane
);
2155 dspcntr
= I915_READ(reg
);
2156 /* Mask out pixel format bits in case we change it */
2157 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2158 switch (fb
->pixel_format
) {
2160 dspcntr
|= DISPPLANE_8BPP
;
2162 case DRM_FORMAT_RGB565
:
2163 dspcntr
|= DISPPLANE_BGRX565
;
2165 case DRM_FORMAT_XRGB8888
:
2166 case DRM_FORMAT_ARGB8888
:
2167 dspcntr
|= DISPPLANE_BGRX888
;
2169 case DRM_FORMAT_XBGR8888
:
2170 case DRM_FORMAT_ABGR8888
:
2171 dspcntr
|= DISPPLANE_RGBX888
;
2173 case DRM_FORMAT_XRGB2101010
:
2174 case DRM_FORMAT_ARGB2101010
:
2175 dspcntr
|= DISPPLANE_BGRX101010
;
2177 case DRM_FORMAT_XBGR2101010
:
2178 case DRM_FORMAT_ABGR2101010
:
2179 dspcntr
|= DISPPLANE_RGBX101010
;
2185 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2186 dspcntr
|= DISPPLANE_TILED
;
2188 dspcntr
&= ~DISPPLANE_TILED
;
2190 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2191 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2193 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2195 I915_WRITE(reg
, dspcntr
);
2197 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2198 intel_crtc
->dspaddr_offset
=
2199 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2200 fb
->bits_per_pixel
/ 8,
2202 linear_offset
-= intel_crtc
->dspaddr_offset
;
2204 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2205 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2207 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2208 I915_WRITE(DSPSURF(plane
),
2209 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2210 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2211 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2213 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2214 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2221 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2223 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2224 int x
, int y
, enum mode_set_atomic state
)
2226 struct drm_device
*dev
= crtc
->dev
;
2227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2229 if (dev_priv
->display
.disable_fbc
)
2230 dev_priv
->display
.disable_fbc(dev
);
2231 intel_increase_pllclock(crtc
);
2233 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2236 void intel_display_handle_reset(struct drm_device
*dev
)
2238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2239 struct drm_crtc
*crtc
;
2242 * Flips in the rings have been nuked by the reset,
2243 * so complete all pending flips so that user space
2244 * will get its events and not get stuck.
2246 * Also update the base address of all primary
2247 * planes to the the last fb to make sure we're
2248 * showing the correct fb after a reset.
2250 * Need to make two loops over the crtcs so that we
2251 * don't try to grab a crtc mutex before the
2252 * pending_flip_queue really got woken up.
2255 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2256 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2257 enum plane plane
= intel_crtc
->plane
;
2259 intel_prepare_page_flip(dev
, plane
);
2260 intel_finish_page_flip_plane(dev
, plane
);
2263 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2266 mutex_lock(&crtc
->mutex
);
2268 * FIXME: Once we have proper support for primary planes (and
2269 * disabling them without disabling the entire crtc) allow again
2272 if (intel_crtc
->active
&& crtc
->fb
)
2273 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2275 mutex_unlock(&crtc
->mutex
);
2280 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2282 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2283 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2284 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2287 /* Big Hammer, we also need to ensure that any pending
2288 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2289 * current scanout is retired before unpinning the old
2292 * This should only fail upon a hung GPU, in which case we
2293 * can safely continue.
2295 dev_priv
->mm
.interruptible
= false;
2296 ret
= i915_gem_object_finish_gpu(obj
);
2297 dev_priv
->mm
.interruptible
= was_interruptible
;
2302 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2304 struct drm_device
*dev
= crtc
->dev
;
2305 struct drm_i915_master_private
*master_priv
;
2306 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2308 if (!dev
->primary
->master
)
2311 master_priv
= dev
->primary
->master
->driver_priv
;
2312 if (!master_priv
->sarea_priv
)
2315 switch (intel_crtc
->pipe
) {
2317 master_priv
->sarea_priv
->pipeA_x
= x
;
2318 master_priv
->sarea_priv
->pipeA_y
= y
;
2321 master_priv
->sarea_priv
->pipeB_x
= x
;
2322 master_priv
->sarea_priv
->pipeB_y
= y
;
2330 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2331 struct drm_framebuffer
*fb
)
2333 struct drm_device
*dev
= crtc
->dev
;
2334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2335 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2336 struct drm_framebuffer
*old_fb
;
2341 DRM_ERROR("No FB bound\n");
2345 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2346 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2347 plane_name(intel_crtc
->plane
),
2348 INTEL_INFO(dev
)->num_pipes
);
2352 mutex_lock(&dev
->struct_mutex
);
2353 ret
= intel_pin_and_fence_fb_obj(dev
,
2354 to_intel_framebuffer(fb
)->obj
,
2357 mutex_unlock(&dev
->struct_mutex
);
2358 DRM_ERROR("pin & fence failed\n");
2363 * Update pipe size and adjust fitter if needed: the reason for this is
2364 * that in compute_mode_changes we check the native mode (not the pfit
2365 * mode) to see if we can flip rather than do a full mode set. In the
2366 * fastboot case, we'll flip, but if we don't update the pipesrc and
2367 * pfit state, we'll end up with a big fb scanned out into the wrong
2370 * To fix this properly, we need to hoist the checks up into
2371 * compute_mode_changes (or above), check the actual pfit state and
2372 * whether the platform allows pfit disable with pipe active, and only
2373 * then update the pipesrc and pfit state, even on the flip path.
2375 if (i915_fastboot
) {
2376 const struct drm_display_mode
*adjusted_mode
=
2377 &intel_crtc
->config
.adjusted_mode
;
2379 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2380 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2381 (adjusted_mode
->crtc_vdisplay
- 1));
2382 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2383 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2384 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2385 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2386 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2387 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2389 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2390 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2393 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2395 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2396 mutex_unlock(&dev
->struct_mutex
);
2397 DRM_ERROR("failed to update base address\n");
2407 if (intel_crtc
->active
&& old_fb
!= fb
)
2408 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2409 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2412 intel_update_fbc(dev
);
2413 intel_edp_psr_update(dev
);
2414 mutex_unlock(&dev
->struct_mutex
);
2416 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2421 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2423 struct drm_device
*dev
= crtc
->dev
;
2424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2425 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2426 int pipe
= intel_crtc
->pipe
;
2429 /* enable normal train */
2430 reg
= FDI_TX_CTL(pipe
);
2431 temp
= I915_READ(reg
);
2432 if (IS_IVYBRIDGE(dev
)) {
2433 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2434 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2436 temp
&= ~FDI_LINK_TRAIN_NONE
;
2437 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2439 I915_WRITE(reg
, temp
);
2441 reg
= FDI_RX_CTL(pipe
);
2442 temp
= I915_READ(reg
);
2443 if (HAS_PCH_CPT(dev
)) {
2444 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2445 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2447 temp
&= ~FDI_LINK_TRAIN_NONE
;
2448 temp
|= FDI_LINK_TRAIN_NONE
;
2450 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2452 /* wait one idle pattern time */
2456 /* IVB wants error correction enabled */
2457 if (IS_IVYBRIDGE(dev
))
2458 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2459 FDI_FE_ERRC_ENABLE
);
2462 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2464 return crtc
->base
.enabled
&& crtc
->active
&&
2465 crtc
->config
.has_pch_encoder
;
2468 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2471 struct intel_crtc
*pipe_B_crtc
=
2472 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2473 struct intel_crtc
*pipe_C_crtc
=
2474 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2478 * When everything is off disable fdi C so that we could enable fdi B
2479 * with all lanes. Note that we don't care about enabled pipes without
2480 * an enabled pch encoder.
2482 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2483 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2484 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2485 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2487 temp
= I915_READ(SOUTH_CHICKEN1
);
2488 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2489 DRM_DEBUG_KMS("disabling fdi C rx\n");
2490 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2494 /* The FDI link training functions for ILK/Ibexpeak. */
2495 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2497 struct drm_device
*dev
= crtc
->dev
;
2498 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2499 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2500 int pipe
= intel_crtc
->pipe
;
2501 int plane
= intel_crtc
->plane
;
2502 u32 reg
, temp
, tries
;
2504 /* FDI needs bits from pipe & plane first */
2505 assert_pipe_enabled(dev_priv
, pipe
);
2506 assert_plane_enabled(dev_priv
, plane
);
2508 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2510 reg
= FDI_RX_IMR(pipe
);
2511 temp
= I915_READ(reg
);
2512 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2513 temp
&= ~FDI_RX_BIT_LOCK
;
2514 I915_WRITE(reg
, temp
);
2518 /* enable CPU FDI TX and PCH FDI RX */
2519 reg
= FDI_TX_CTL(pipe
);
2520 temp
= I915_READ(reg
);
2521 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2522 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2523 temp
&= ~FDI_LINK_TRAIN_NONE
;
2524 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2525 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2527 reg
= FDI_RX_CTL(pipe
);
2528 temp
= I915_READ(reg
);
2529 temp
&= ~FDI_LINK_TRAIN_NONE
;
2530 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2531 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2536 /* Ironlake workaround, enable clock pointer after FDI enable*/
2537 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2538 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2539 FDI_RX_PHASE_SYNC_POINTER_EN
);
2541 reg
= FDI_RX_IIR(pipe
);
2542 for (tries
= 0; tries
< 5; tries
++) {
2543 temp
= I915_READ(reg
);
2544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2546 if ((temp
& FDI_RX_BIT_LOCK
)) {
2547 DRM_DEBUG_KMS("FDI train 1 done.\n");
2548 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2553 DRM_ERROR("FDI train 1 fail!\n");
2556 reg
= FDI_TX_CTL(pipe
);
2557 temp
= I915_READ(reg
);
2558 temp
&= ~FDI_LINK_TRAIN_NONE
;
2559 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2560 I915_WRITE(reg
, temp
);
2562 reg
= FDI_RX_CTL(pipe
);
2563 temp
= I915_READ(reg
);
2564 temp
&= ~FDI_LINK_TRAIN_NONE
;
2565 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2566 I915_WRITE(reg
, temp
);
2571 reg
= FDI_RX_IIR(pipe
);
2572 for (tries
= 0; tries
< 5; tries
++) {
2573 temp
= I915_READ(reg
);
2574 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2576 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2577 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2578 DRM_DEBUG_KMS("FDI train 2 done.\n");
2583 DRM_ERROR("FDI train 2 fail!\n");
2585 DRM_DEBUG_KMS("FDI train done\n");
2589 static const int snb_b_fdi_train_param
[] = {
2590 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2591 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2592 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2593 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2596 /* The FDI link training functions for SNB/Cougarpoint. */
2597 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2599 struct drm_device
*dev
= crtc
->dev
;
2600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2601 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2602 int pipe
= intel_crtc
->pipe
;
2603 u32 reg
, temp
, i
, retry
;
2605 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2607 reg
= FDI_RX_IMR(pipe
);
2608 temp
= I915_READ(reg
);
2609 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2610 temp
&= ~FDI_RX_BIT_LOCK
;
2611 I915_WRITE(reg
, temp
);
2616 /* enable CPU FDI TX and PCH FDI RX */
2617 reg
= FDI_TX_CTL(pipe
);
2618 temp
= I915_READ(reg
);
2619 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2620 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2621 temp
&= ~FDI_LINK_TRAIN_NONE
;
2622 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2623 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2625 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2626 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2628 I915_WRITE(FDI_RX_MISC(pipe
),
2629 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2631 reg
= FDI_RX_CTL(pipe
);
2632 temp
= I915_READ(reg
);
2633 if (HAS_PCH_CPT(dev
)) {
2634 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2635 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2637 temp
&= ~FDI_LINK_TRAIN_NONE
;
2638 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2640 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2645 for (i
= 0; i
< 4; i
++) {
2646 reg
= FDI_TX_CTL(pipe
);
2647 temp
= I915_READ(reg
);
2648 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2649 temp
|= snb_b_fdi_train_param
[i
];
2650 I915_WRITE(reg
, temp
);
2655 for (retry
= 0; retry
< 5; retry
++) {
2656 reg
= FDI_RX_IIR(pipe
);
2657 temp
= I915_READ(reg
);
2658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2659 if (temp
& FDI_RX_BIT_LOCK
) {
2660 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2661 DRM_DEBUG_KMS("FDI train 1 done.\n");
2670 DRM_ERROR("FDI train 1 fail!\n");
2673 reg
= FDI_TX_CTL(pipe
);
2674 temp
= I915_READ(reg
);
2675 temp
&= ~FDI_LINK_TRAIN_NONE
;
2676 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2678 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2680 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2682 I915_WRITE(reg
, temp
);
2684 reg
= FDI_RX_CTL(pipe
);
2685 temp
= I915_READ(reg
);
2686 if (HAS_PCH_CPT(dev
)) {
2687 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2688 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2690 temp
&= ~FDI_LINK_TRAIN_NONE
;
2691 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2693 I915_WRITE(reg
, temp
);
2698 for (i
= 0; i
< 4; i
++) {
2699 reg
= FDI_TX_CTL(pipe
);
2700 temp
= I915_READ(reg
);
2701 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2702 temp
|= snb_b_fdi_train_param
[i
];
2703 I915_WRITE(reg
, temp
);
2708 for (retry
= 0; retry
< 5; retry
++) {
2709 reg
= FDI_RX_IIR(pipe
);
2710 temp
= I915_READ(reg
);
2711 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2712 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2713 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2714 DRM_DEBUG_KMS("FDI train 2 done.\n");
2723 DRM_ERROR("FDI train 2 fail!\n");
2725 DRM_DEBUG_KMS("FDI train done.\n");
2728 /* Manual link training for Ivy Bridge A0 parts */
2729 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2731 struct drm_device
*dev
= crtc
->dev
;
2732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2734 int pipe
= intel_crtc
->pipe
;
2735 u32 reg
, temp
, i
, j
;
2737 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2739 reg
= FDI_RX_IMR(pipe
);
2740 temp
= I915_READ(reg
);
2741 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2742 temp
&= ~FDI_RX_BIT_LOCK
;
2743 I915_WRITE(reg
, temp
);
2748 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2749 I915_READ(FDI_RX_IIR(pipe
)));
2751 /* Try each vswing and preemphasis setting twice before moving on */
2752 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2753 /* disable first in case we need to retry */
2754 reg
= FDI_TX_CTL(pipe
);
2755 temp
= I915_READ(reg
);
2756 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2757 temp
&= ~FDI_TX_ENABLE
;
2758 I915_WRITE(reg
, temp
);
2760 reg
= FDI_RX_CTL(pipe
);
2761 temp
= I915_READ(reg
);
2762 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2763 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2764 temp
&= ~FDI_RX_ENABLE
;
2765 I915_WRITE(reg
, temp
);
2767 /* enable CPU FDI TX and PCH FDI RX */
2768 reg
= FDI_TX_CTL(pipe
);
2769 temp
= I915_READ(reg
);
2770 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2771 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2772 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2773 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2774 temp
|= snb_b_fdi_train_param
[j
/2];
2775 temp
|= FDI_COMPOSITE_SYNC
;
2776 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2778 I915_WRITE(FDI_RX_MISC(pipe
),
2779 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2781 reg
= FDI_RX_CTL(pipe
);
2782 temp
= I915_READ(reg
);
2783 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2784 temp
|= FDI_COMPOSITE_SYNC
;
2785 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2788 udelay(1); /* should be 0.5us */
2790 for (i
= 0; i
< 4; i
++) {
2791 reg
= FDI_RX_IIR(pipe
);
2792 temp
= I915_READ(reg
);
2793 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2795 if (temp
& FDI_RX_BIT_LOCK
||
2796 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2797 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2798 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2802 udelay(1); /* should be 0.5us */
2805 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2810 reg
= FDI_TX_CTL(pipe
);
2811 temp
= I915_READ(reg
);
2812 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2813 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2814 I915_WRITE(reg
, temp
);
2816 reg
= FDI_RX_CTL(pipe
);
2817 temp
= I915_READ(reg
);
2818 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2819 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2820 I915_WRITE(reg
, temp
);
2823 udelay(2); /* should be 1.5us */
2825 for (i
= 0; i
< 4; i
++) {
2826 reg
= FDI_RX_IIR(pipe
);
2827 temp
= I915_READ(reg
);
2828 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2830 if (temp
& FDI_RX_SYMBOL_LOCK
||
2831 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2832 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2833 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2837 udelay(2); /* should be 1.5us */
2840 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2844 DRM_DEBUG_KMS("FDI train done.\n");
2847 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2849 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2851 int pipe
= intel_crtc
->pipe
;
2855 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2856 reg
= FDI_RX_CTL(pipe
);
2857 temp
= I915_READ(reg
);
2858 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2859 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2860 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2861 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2866 /* Switch from Rawclk to PCDclk */
2867 temp
= I915_READ(reg
);
2868 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2873 /* Enable CPU FDI TX PLL, always on for Ironlake */
2874 reg
= FDI_TX_CTL(pipe
);
2875 temp
= I915_READ(reg
);
2876 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2877 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2884 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2886 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2888 int pipe
= intel_crtc
->pipe
;
2891 /* Switch from PCDclk to Rawclk */
2892 reg
= FDI_RX_CTL(pipe
);
2893 temp
= I915_READ(reg
);
2894 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2896 /* Disable CPU FDI TX PLL */
2897 reg
= FDI_TX_CTL(pipe
);
2898 temp
= I915_READ(reg
);
2899 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2904 reg
= FDI_RX_CTL(pipe
);
2905 temp
= I915_READ(reg
);
2906 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2908 /* Wait for the clocks to turn off. */
2913 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2915 struct drm_device
*dev
= crtc
->dev
;
2916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2918 int pipe
= intel_crtc
->pipe
;
2921 /* disable CPU FDI tx and PCH FDI rx */
2922 reg
= FDI_TX_CTL(pipe
);
2923 temp
= I915_READ(reg
);
2924 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2927 reg
= FDI_RX_CTL(pipe
);
2928 temp
= I915_READ(reg
);
2929 temp
&= ~(0x7 << 16);
2930 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2931 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2936 /* Ironlake workaround, disable clock pointer after downing FDI */
2937 if (HAS_PCH_IBX(dev
)) {
2938 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2941 /* still set train pattern 1 */
2942 reg
= FDI_TX_CTL(pipe
);
2943 temp
= I915_READ(reg
);
2944 temp
&= ~FDI_LINK_TRAIN_NONE
;
2945 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2946 I915_WRITE(reg
, temp
);
2948 reg
= FDI_RX_CTL(pipe
);
2949 temp
= I915_READ(reg
);
2950 if (HAS_PCH_CPT(dev
)) {
2951 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2952 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2954 temp
&= ~FDI_LINK_TRAIN_NONE
;
2955 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2957 /* BPC in FDI rx is consistent with that in PIPECONF */
2958 temp
&= ~(0x07 << 16);
2959 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2960 I915_WRITE(reg
, temp
);
2966 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2968 struct drm_device
*dev
= crtc
->dev
;
2969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2970 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2971 unsigned long flags
;
2974 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2975 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2978 spin_lock_irqsave(&dev
->event_lock
, flags
);
2979 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2980 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2985 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
2987 struct intel_crtc
*crtc
;
2989 /* Note that we don't need to be called with mode_config.lock here
2990 * as our list of CRTC objects is static for the lifetime of the
2991 * device and so cannot disappear as we iterate. Similarly, we can
2992 * happily treat the predicates as racy, atomic checks as userspace
2993 * cannot claim and pin a new fb without at least acquring the
2994 * struct_mutex and so serialising with us.
2996 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
2997 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3000 if (crtc
->unpin_work
)
3001 intel_wait_for_vblank(dev
, crtc
->pipe
);
3009 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3011 struct drm_device
*dev
= crtc
->dev
;
3012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3014 if (crtc
->fb
== NULL
)
3017 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3019 wait_event(dev_priv
->pending_flip_queue
,
3020 !intel_crtc_has_pending_flip(crtc
));
3022 mutex_lock(&dev
->struct_mutex
);
3023 intel_finish_fb(crtc
->fb
);
3024 mutex_unlock(&dev
->struct_mutex
);
3027 /* Program iCLKIP clock to the desired frequency */
3028 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3030 struct drm_device
*dev
= crtc
->dev
;
3031 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3032 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3033 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3036 mutex_lock(&dev_priv
->dpio_lock
);
3038 /* It is necessary to ungate the pixclk gate prior to programming
3039 * the divisors, and gate it back when it is done.
3041 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3043 /* Disable SSCCTL */
3044 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3045 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3049 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3050 if (clock
== 20000) {
3055 /* The iCLK virtual clock root frequency is in MHz,
3056 * but the adjusted_mode->crtc_clock in in KHz. To get the
3057 * divisors, it is necessary to divide one by another, so we
3058 * convert the virtual clock precision to KHz here for higher
3061 u32 iclk_virtual_root_freq
= 172800 * 1000;
3062 u32 iclk_pi_range
= 64;
3063 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3065 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3066 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3067 pi_value
= desired_divisor
% iclk_pi_range
;
3070 divsel
= msb_divisor_value
- 2;
3071 phaseinc
= pi_value
;
3074 /* This should not happen with any sane values */
3075 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3076 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3077 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3078 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3080 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3087 /* Program SSCDIVINTPHASE6 */
3088 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3089 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3090 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3091 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3092 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3093 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3094 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3095 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3097 /* Program SSCAUXDIV */
3098 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3099 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3100 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3101 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3103 /* Enable modulator and associated divider */
3104 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3105 temp
&= ~SBI_SSCCTL_DISABLE
;
3106 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3108 /* Wait for initialization time */
3111 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3113 mutex_unlock(&dev_priv
->dpio_lock
);
3116 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3117 enum pipe pch_transcoder
)
3119 struct drm_device
*dev
= crtc
->base
.dev
;
3120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3121 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3123 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3124 I915_READ(HTOTAL(cpu_transcoder
)));
3125 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3126 I915_READ(HBLANK(cpu_transcoder
)));
3127 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3128 I915_READ(HSYNC(cpu_transcoder
)));
3130 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3131 I915_READ(VTOTAL(cpu_transcoder
)));
3132 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3133 I915_READ(VBLANK(cpu_transcoder
)));
3134 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3135 I915_READ(VSYNC(cpu_transcoder
)));
3136 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3137 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3140 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3145 temp
= I915_READ(SOUTH_CHICKEN1
);
3146 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3149 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3150 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3152 temp
|= FDI_BC_BIFURCATION_SELECT
;
3153 DRM_DEBUG_KMS("enabling fdi C rx\n");
3154 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3155 POSTING_READ(SOUTH_CHICKEN1
);
3158 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3160 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3163 switch (intel_crtc
->pipe
) {
3167 if (intel_crtc
->config
.fdi_lanes
> 2)
3168 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3170 cpt_enable_fdi_bc_bifurcation(dev
);
3174 cpt_enable_fdi_bc_bifurcation(dev
);
3183 * Enable PCH resources required for PCH ports:
3185 * - FDI training & RX/TX
3186 * - update transcoder timings
3187 * - DP transcoding bits
3190 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3192 struct drm_device
*dev
= crtc
->dev
;
3193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3195 int pipe
= intel_crtc
->pipe
;
3198 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3200 if (IS_IVYBRIDGE(dev
))
3201 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3203 /* Write the TU size bits before fdi link training, so that error
3204 * detection works. */
3205 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3206 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3208 /* For PCH output, training FDI link */
3209 dev_priv
->display
.fdi_link_train(crtc
);
3211 /* We need to program the right clock selection before writing the pixel
3212 * mutliplier into the DPLL. */
3213 if (HAS_PCH_CPT(dev
)) {
3216 temp
= I915_READ(PCH_DPLL_SEL
);
3217 temp
|= TRANS_DPLL_ENABLE(pipe
);
3218 sel
= TRANS_DPLLB_SEL(pipe
);
3219 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3223 I915_WRITE(PCH_DPLL_SEL
, temp
);
3226 /* XXX: pch pll's can be enabled any time before we enable the PCH
3227 * transcoder, and we actually should do this to not upset any PCH
3228 * transcoder that already use the clock when we share it.
3230 * Note that enable_shared_dpll tries to do the right thing, but
3231 * get_shared_dpll unconditionally resets the pll - we need that to have
3232 * the right LVDS enable sequence. */
3233 ironlake_enable_shared_dpll(intel_crtc
);
3235 /* set transcoder timing, panel must allow it */
3236 assert_panel_unlocked(dev_priv
, pipe
);
3237 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3239 intel_fdi_normal_train(crtc
);
3241 /* For PCH DP, enable TRANS_DP_CTL */
3242 if (HAS_PCH_CPT(dev
) &&
3243 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3244 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3245 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3246 reg
= TRANS_DP_CTL(pipe
);
3247 temp
= I915_READ(reg
);
3248 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3249 TRANS_DP_SYNC_MASK
|
3251 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3252 TRANS_DP_ENH_FRAMING
);
3253 temp
|= bpc
<< 9; /* same format but at 11:9 */
3255 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3256 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3257 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3258 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3260 switch (intel_trans_dp_port_sel(crtc
)) {
3262 temp
|= TRANS_DP_PORT_SEL_B
;
3265 temp
|= TRANS_DP_PORT_SEL_C
;
3268 temp
|= TRANS_DP_PORT_SEL_D
;
3274 I915_WRITE(reg
, temp
);
3277 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3280 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3282 struct drm_device
*dev
= crtc
->dev
;
3283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3284 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3285 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3287 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3289 lpt_program_iclkip(crtc
);
3291 /* Set transcoder timing. */
3292 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3294 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3297 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3299 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3304 if (pll
->refcount
== 0) {
3305 WARN(1, "bad %s refcount\n", pll
->name
);
3309 if (--pll
->refcount
== 0) {
3311 WARN_ON(pll
->active
);
3314 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3317 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3319 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3320 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3321 enum intel_dpll_id i
;
3324 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3325 crtc
->base
.base
.id
, pll
->name
);
3326 intel_put_shared_dpll(crtc
);
3329 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3330 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3331 i
= (enum intel_dpll_id
) crtc
->pipe
;
3332 pll
= &dev_priv
->shared_dplls
[i
];
3334 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3335 crtc
->base
.base
.id
, pll
->name
);
3340 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3341 pll
= &dev_priv
->shared_dplls
[i
];
3343 /* Only want to check enabled timings first */
3344 if (pll
->refcount
== 0)
3347 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3348 sizeof(pll
->hw_state
)) == 0) {
3349 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3351 pll
->name
, pll
->refcount
, pll
->active
);
3357 /* Ok no matching timings, maybe there's a free one? */
3358 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3359 pll
= &dev_priv
->shared_dplls
[i
];
3360 if (pll
->refcount
== 0) {
3361 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3362 crtc
->base
.base
.id
, pll
->name
);
3370 crtc
->config
.shared_dpll
= i
;
3371 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3372 pipe_name(crtc
->pipe
));
3374 if (pll
->active
== 0) {
3375 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3376 sizeof(pll
->hw_state
));
3378 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3380 assert_shared_dpll_disabled(dev_priv
, pll
);
3382 pll
->mode_set(dev_priv
, pll
);
3389 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3392 int dslreg
= PIPEDSL(pipe
);
3395 temp
= I915_READ(dslreg
);
3397 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3398 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3399 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3403 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3405 struct drm_device
*dev
= crtc
->base
.dev
;
3406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3407 int pipe
= crtc
->pipe
;
3409 if (crtc
->config
.pch_pfit
.enabled
) {
3410 /* Force use of hard-coded filter coefficients
3411 * as some pre-programmed values are broken,
3414 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3415 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3416 PF_PIPE_SEL_IVB(pipe
));
3418 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3419 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3420 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3424 static void intel_enable_planes(struct drm_crtc
*crtc
)
3426 struct drm_device
*dev
= crtc
->dev
;
3427 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3428 struct intel_plane
*intel_plane
;
3430 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3431 if (intel_plane
->pipe
== pipe
)
3432 intel_plane_restore(&intel_plane
->base
);
3435 static void intel_disable_planes(struct drm_crtc
*crtc
)
3437 struct drm_device
*dev
= crtc
->dev
;
3438 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3439 struct intel_plane
*intel_plane
;
3441 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3442 if (intel_plane
->pipe
== pipe
)
3443 intel_plane_disable(&intel_plane
->base
);
3446 void hsw_enable_ips(struct intel_crtc
*crtc
)
3448 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3450 if (!crtc
->config
.ips_enabled
)
3453 /* We can only enable IPS after we enable a plane and wait for a vblank.
3454 * We guarantee that the plane is enabled by calling intel_enable_ips
3455 * only after intel_enable_plane. And intel_enable_plane already waits
3456 * for a vblank, so all we need to do here is to enable the IPS bit. */
3457 assert_plane_enabled(dev_priv
, crtc
->plane
);
3458 if (IS_BROADWELL(crtc
->base
.dev
)) {
3459 mutex_lock(&dev_priv
->rps
.hw_lock
);
3460 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3461 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3462 /* Quoting Art Runyan: "its not safe to expect any particular
3463 * value in IPS_CTL bit 31 after enabling IPS through the
3464 * mailbox." Moreover, the mailbox may return a bogus state,
3465 * so we need to just enable it and continue on.
3468 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3469 /* The bit only becomes 1 in the next vblank, so this wait here
3470 * is essentially intel_wait_for_vblank. If we don't have this
3471 * and don't wait for vblanks until the end of crtc_enable, then
3472 * the HW state readout code will complain that the expected
3473 * IPS_CTL value is not the one we read. */
3474 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3475 DRM_ERROR("Timed out waiting for IPS enable\n");
3479 void hsw_disable_ips(struct intel_crtc
*crtc
)
3481 struct drm_device
*dev
= crtc
->base
.dev
;
3482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3484 if (!crtc
->config
.ips_enabled
)
3487 assert_plane_enabled(dev_priv
, crtc
->plane
);
3488 if (IS_BROADWELL(crtc
->base
.dev
)) {
3489 mutex_lock(&dev_priv
->rps
.hw_lock
);
3490 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3491 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3493 I915_WRITE(IPS_CTL
, 0);
3494 POSTING_READ(IPS_CTL
);
3497 /* We need to wait for a vblank before we can disable the plane. */
3498 intel_wait_for_vblank(dev
, crtc
->pipe
);
3501 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3502 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3504 struct drm_device
*dev
= crtc
->dev
;
3505 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3506 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3507 enum pipe pipe
= intel_crtc
->pipe
;
3508 int palreg
= PALETTE(pipe
);
3510 bool reenable_ips
= false;
3512 /* The clocks have to be on to load the palette. */
3513 if (!crtc
->enabled
|| !intel_crtc
->active
)
3516 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3517 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3518 assert_dsi_pll_enabled(dev_priv
);
3520 assert_pll_enabled(dev_priv
, pipe
);
3523 /* use legacy palette for Ironlake */
3524 if (HAS_PCH_SPLIT(dev
))
3525 palreg
= LGC_PALETTE(pipe
);
3527 /* Workaround : Do not read or write the pipe palette/gamma data while
3528 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3530 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3531 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3532 GAMMA_MODE_MODE_SPLIT
)) {
3533 hsw_disable_ips(intel_crtc
);
3534 reenable_ips
= true;
3537 for (i
= 0; i
< 256; i
++) {
3538 I915_WRITE(palreg
+ 4 * i
,
3539 (intel_crtc
->lut_r
[i
] << 16) |
3540 (intel_crtc
->lut_g
[i
] << 8) |
3541 intel_crtc
->lut_b
[i
]);
3545 hsw_enable_ips(intel_crtc
);
3548 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3550 struct drm_device
*dev
= crtc
->dev
;
3551 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3552 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3553 struct intel_encoder
*encoder
;
3554 int pipe
= intel_crtc
->pipe
;
3555 int plane
= intel_crtc
->plane
;
3557 WARN_ON(!crtc
->enabled
);
3559 if (intel_crtc
->active
)
3562 intel_crtc
->active
= true;
3564 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3565 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3567 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3568 if (encoder
->pre_enable
)
3569 encoder
->pre_enable(encoder
);
3571 if (intel_crtc
->config
.has_pch_encoder
) {
3572 /* Note: FDI PLL enabling _must_ be done before we enable the
3573 * cpu pipes, hence this is separate from all the other fdi/pch
3575 ironlake_fdi_pll_enable(intel_crtc
);
3577 assert_fdi_tx_disabled(dev_priv
, pipe
);
3578 assert_fdi_rx_disabled(dev_priv
, pipe
);
3581 ironlake_pfit_enable(intel_crtc
);
3584 * On ILK+ LUT must be loaded before the pipe is running but with
3587 intel_crtc_load_lut(crtc
);
3589 intel_update_watermarks(crtc
);
3590 intel_enable_pipe(dev_priv
, pipe
,
3591 intel_crtc
->config
.has_pch_encoder
, false);
3592 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3593 intel_enable_planes(crtc
);
3594 intel_crtc_update_cursor(crtc
, true);
3596 if (intel_crtc
->config
.has_pch_encoder
)
3597 ironlake_pch_enable(crtc
);
3599 mutex_lock(&dev
->struct_mutex
);
3600 intel_update_fbc(dev
);
3601 mutex_unlock(&dev
->struct_mutex
);
3603 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3604 encoder
->enable(encoder
);
3606 if (HAS_PCH_CPT(dev
))
3607 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3610 * There seems to be a race in PCH platform hw (at least on some
3611 * outputs) where an enabled pipe still completes any pageflip right
3612 * away (as if the pipe is off) instead of waiting for vblank. As soon
3613 * as the first vblank happend, everything works as expected. Hence just
3614 * wait for one vblank before returning to avoid strange things
3617 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3620 /* IPS only exists on ULT machines and is tied to pipe A. */
3621 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3623 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3626 static void haswell_crtc_enable_planes(struct drm_crtc
*crtc
)
3628 struct drm_device
*dev
= crtc
->dev
;
3629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3630 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3631 int pipe
= intel_crtc
->pipe
;
3632 int plane
= intel_crtc
->plane
;
3634 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
3635 intel_enable_planes(crtc
);
3636 intel_crtc_update_cursor(crtc
, true);
3638 hsw_enable_ips(intel_crtc
);
3640 mutex_lock(&dev
->struct_mutex
);
3641 intel_update_fbc(dev
);
3642 mutex_unlock(&dev
->struct_mutex
);
3645 static void haswell_crtc_disable_planes(struct drm_crtc
*crtc
)
3647 struct drm_device
*dev
= crtc
->dev
;
3648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3649 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3650 int pipe
= intel_crtc
->pipe
;
3651 int plane
= intel_crtc
->plane
;
3653 intel_crtc_wait_for_pending_flips(crtc
);
3654 drm_vblank_off(dev
, pipe
);
3656 /* FBC must be disabled before disabling the plane on HSW. */
3657 if (dev_priv
->fbc
.plane
== plane
)
3658 intel_disable_fbc(dev
);
3660 hsw_disable_ips(intel_crtc
);
3662 intel_crtc_update_cursor(crtc
, false);
3663 intel_disable_planes(crtc
);
3664 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3668 * This implements the workaround described in the "notes" section of the mode
3669 * set sequence documentation. When going from no pipes or single pipe to
3670 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3671 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3673 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
3675 struct drm_device
*dev
= crtc
->base
.dev
;
3676 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
3678 /* We want to get the other_active_crtc only if there's only 1 other
3680 list_for_each_entry(crtc_it
, &dev
->mode_config
.crtc_list
, base
.head
) {
3681 if (!crtc_it
->active
|| crtc_it
== crtc
)
3684 if (other_active_crtc
)
3687 other_active_crtc
= crtc_it
;
3689 if (!other_active_crtc
)
3692 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3693 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
3696 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3698 struct drm_device
*dev
= crtc
->dev
;
3699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3700 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3701 struct intel_encoder
*encoder
;
3702 int pipe
= intel_crtc
->pipe
;
3704 WARN_ON(!crtc
->enabled
);
3706 if (intel_crtc
->active
)
3709 intel_crtc
->active
= true;
3711 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3712 if (intel_crtc
->config
.has_pch_encoder
)
3713 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3715 if (intel_crtc
->config
.has_pch_encoder
)
3716 dev_priv
->display
.fdi_link_train(crtc
);
3718 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3719 if (encoder
->pre_enable
)
3720 encoder
->pre_enable(encoder
);
3722 intel_ddi_enable_pipe_clock(intel_crtc
);
3724 ironlake_pfit_enable(intel_crtc
);
3727 * On ILK+ LUT must be loaded before the pipe is running but with
3730 intel_crtc_load_lut(crtc
);
3732 intel_ddi_set_pipe_settings(crtc
);
3733 intel_ddi_enable_transcoder_func(crtc
);
3735 intel_update_watermarks(crtc
);
3736 intel_enable_pipe(dev_priv
, pipe
,
3737 intel_crtc
->config
.has_pch_encoder
, false);
3739 if (intel_crtc
->config
.has_pch_encoder
)
3740 lpt_pch_enable(crtc
);
3742 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3743 encoder
->enable(encoder
);
3744 intel_opregion_notify_encoder(encoder
, true);
3747 /* If we change the relative order between pipe/planes enabling, we need
3748 * to change the workaround. */
3749 haswell_mode_set_planes_workaround(intel_crtc
);
3750 haswell_crtc_enable_planes(crtc
);
3753 * There seems to be a race in PCH platform hw (at least on some
3754 * outputs) where an enabled pipe still completes any pageflip right
3755 * away (as if the pipe is off) instead of waiting for vblank. As soon
3756 * as the first vblank happend, everything works as expected. Hence just
3757 * wait for one vblank before returning to avoid strange things
3760 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3763 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3765 struct drm_device
*dev
= crtc
->base
.dev
;
3766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3767 int pipe
= crtc
->pipe
;
3769 /* To avoid upsetting the power well on haswell only disable the pfit if
3770 * it's in use. The hw state code will make sure we get this right. */
3771 if (crtc
->config
.pch_pfit
.enabled
) {
3772 I915_WRITE(PF_CTL(pipe
), 0);
3773 I915_WRITE(PF_WIN_POS(pipe
), 0);
3774 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3778 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3780 struct drm_device
*dev
= crtc
->dev
;
3781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3782 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3783 struct intel_encoder
*encoder
;
3784 int pipe
= intel_crtc
->pipe
;
3785 int plane
= intel_crtc
->plane
;
3789 if (!intel_crtc
->active
)
3792 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3793 encoder
->disable(encoder
);
3795 intel_crtc_wait_for_pending_flips(crtc
);
3796 drm_vblank_off(dev
, pipe
);
3798 if (dev_priv
->fbc
.plane
== plane
)
3799 intel_disable_fbc(dev
);
3801 intel_crtc_update_cursor(crtc
, false);
3802 intel_disable_planes(crtc
);
3803 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
3805 if (intel_crtc
->config
.has_pch_encoder
)
3806 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3808 intel_disable_pipe(dev_priv
, pipe
);
3810 ironlake_pfit_disable(intel_crtc
);
3812 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3813 if (encoder
->post_disable
)
3814 encoder
->post_disable(encoder
);
3816 if (intel_crtc
->config
.has_pch_encoder
) {
3817 ironlake_fdi_disable(crtc
);
3819 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3820 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3822 if (HAS_PCH_CPT(dev
)) {
3823 /* disable TRANS_DP_CTL */
3824 reg
= TRANS_DP_CTL(pipe
);
3825 temp
= I915_READ(reg
);
3826 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3827 TRANS_DP_PORT_SEL_MASK
);
3828 temp
|= TRANS_DP_PORT_SEL_NONE
;
3829 I915_WRITE(reg
, temp
);
3831 /* disable DPLL_SEL */
3832 temp
= I915_READ(PCH_DPLL_SEL
);
3833 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3834 I915_WRITE(PCH_DPLL_SEL
, temp
);
3837 /* disable PCH DPLL */
3838 intel_disable_shared_dpll(intel_crtc
);
3840 ironlake_fdi_pll_disable(intel_crtc
);
3843 intel_crtc
->active
= false;
3844 intel_update_watermarks(crtc
);
3846 mutex_lock(&dev
->struct_mutex
);
3847 intel_update_fbc(dev
);
3848 mutex_unlock(&dev
->struct_mutex
);
3851 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3853 struct drm_device
*dev
= crtc
->dev
;
3854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3856 struct intel_encoder
*encoder
;
3857 int pipe
= intel_crtc
->pipe
;
3858 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3860 if (!intel_crtc
->active
)
3863 haswell_crtc_disable_planes(crtc
);
3865 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3866 intel_opregion_notify_encoder(encoder
, false);
3867 encoder
->disable(encoder
);
3870 if (intel_crtc
->config
.has_pch_encoder
)
3871 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3872 intel_disable_pipe(dev_priv
, pipe
);
3874 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3876 ironlake_pfit_disable(intel_crtc
);
3878 intel_ddi_disable_pipe_clock(intel_crtc
);
3880 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3881 if (encoder
->post_disable
)
3882 encoder
->post_disable(encoder
);
3884 if (intel_crtc
->config
.has_pch_encoder
) {
3885 lpt_disable_pch_transcoder(dev_priv
);
3886 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3887 intel_ddi_fdi_disable(crtc
);
3890 intel_crtc
->active
= false;
3891 intel_update_watermarks(crtc
);
3893 mutex_lock(&dev
->struct_mutex
);
3894 intel_update_fbc(dev
);
3895 mutex_unlock(&dev
->struct_mutex
);
3898 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3900 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3901 intel_put_shared_dpll(intel_crtc
);
3904 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3906 intel_ddi_put_crtc_pll(crtc
);
3909 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3911 if (!enable
&& intel_crtc
->overlay
) {
3912 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3913 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3915 mutex_lock(&dev
->struct_mutex
);
3916 dev_priv
->mm
.interruptible
= false;
3917 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3918 dev_priv
->mm
.interruptible
= true;
3919 mutex_unlock(&dev
->struct_mutex
);
3922 /* Let userspace switch the overlay on again. In most cases userspace
3923 * has to recompute where to put it anyway.
3928 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3929 * cursor plane briefly if not already running after enabling the display
3931 * This workaround avoids occasional blank screens when self refresh is
3935 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3937 u32 cntl
= I915_READ(CURCNTR(pipe
));
3939 if ((cntl
& CURSOR_MODE
) == 0) {
3940 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3942 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3943 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3944 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3945 I915_WRITE(CURCNTR(pipe
), cntl
);
3946 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3947 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3951 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3953 struct drm_device
*dev
= crtc
->base
.dev
;
3954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3955 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3957 if (!crtc
->config
.gmch_pfit
.control
)
3961 * The panel fitter should only be adjusted whilst the pipe is disabled,
3962 * according to register description and PRM.
3964 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3965 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3967 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3968 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3970 /* Border color in case we don't scale up to the full screen. Black by
3971 * default, change to something else for debugging. */
3972 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3975 int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
3977 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
3979 /* Obtain SKU information */
3980 mutex_lock(&dev_priv
->dpio_lock
);
3981 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
3982 CCK_FUSE_HPLL_FREQ_MASK
;
3983 mutex_unlock(&dev_priv
->dpio_lock
);
3985 return vco_freq
[hpll_freq
];
3988 /* Adjust CDclk dividers to allow high res or save power if possible */
3989 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
3991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3994 if (cdclk
>= 320) /* jump to highest voltage for 400MHz too */
3996 else if (cdclk
== 266)
4001 mutex_lock(&dev_priv
->rps
.hw_lock
);
4002 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4003 val
&= ~DSPFREQGUAR_MASK
;
4004 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4005 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4006 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4007 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4009 DRM_ERROR("timed out waiting for CDclk change\n");
4011 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4016 vco
= valleyview_get_vco(dev_priv
);
4017 divider
= ((vco
<< 1) / cdclk
) - 1;
4019 mutex_lock(&dev_priv
->dpio_lock
);
4020 /* adjust cdclk divider */
4021 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4024 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4025 mutex_unlock(&dev_priv
->dpio_lock
);
4028 mutex_lock(&dev_priv
->dpio_lock
);
4029 /* adjust self-refresh exit latency value */
4030 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4034 * For high bandwidth configs, we set a higher latency in the bunit
4035 * so that the core display fetch happens in time to avoid underruns.
4038 val
|= 4500 / 250; /* 4.5 usec */
4040 val
|= 3000 / 250; /* 3.0 usec */
4041 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4042 mutex_unlock(&dev_priv
->dpio_lock
);
4044 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4045 intel_i2c_reset(dev
);
4048 static int valleyview_cur_cdclk(struct drm_i915_private
*dev_priv
)
4053 vco
= valleyview_get_vco(dev_priv
);
4055 mutex_lock(&dev_priv
->dpio_lock
);
4056 divider
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4057 mutex_unlock(&dev_priv
->dpio_lock
);
4061 cur_cdclk
= (vco
<< 1) / (divider
+ 1);
4066 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4071 cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4074 * Really only a few cases to deal with, as only 4 CDclks are supported:
4079 * So we check to see whether we're above 90% of the lower bin and
4082 if (max_pixclk
> 288000) {
4084 } else if (max_pixclk
> 240000) {
4088 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4091 /* compute the max pixel clock for new configuration */
4092 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4094 struct drm_device
*dev
= dev_priv
->dev
;
4095 struct intel_crtc
*intel_crtc
;
4098 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
4100 if (intel_crtc
->new_enabled
)
4101 max_pixclk
= max(max_pixclk
,
4102 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4108 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4109 unsigned *prepare_pipes
)
4111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4112 struct intel_crtc
*intel_crtc
;
4113 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4114 int cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4116 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) == cur_cdclk
)
4119 /* disable/enable all currently active pipes while we change cdclk */
4120 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
4122 if (intel_crtc
->base
.enabled
)
4123 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4126 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4129 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4130 int cur_cdclk
= valleyview_cur_cdclk(dev_priv
);
4131 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4133 if (req_cdclk
!= cur_cdclk
)
4134 valleyview_set_cdclk(dev
, req_cdclk
);
4137 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4139 struct drm_device
*dev
= crtc
->dev
;
4140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4141 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4142 struct intel_encoder
*encoder
;
4143 int pipe
= intel_crtc
->pipe
;
4144 int plane
= intel_crtc
->plane
;
4147 WARN_ON(!crtc
->enabled
);
4149 if (intel_crtc
->active
)
4152 intel_crtc
->active
= true;
4154 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4155 if (encoder
->pre_pll_enable
)
4156 encoder
->pre_pll_enable(encoder
);
4158 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4161 vlv_enable_pll(intel_crtc
);
4163 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4164 if (encoder
->pre_enable
)
4165 encoder
->pre_enable(encoder
);
4167 i9xx_pfit_enable(intel_crtc
);
4169 intel_crtc_load_lut(crtc
);
4171 intel_update_watermarks(crtc
);
4172 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
4173 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
4174 intel_enable_planes(crtc
);
4175 intel_crtc_update_cursor(crtc
, true);
4177 intel_update_fbc(dev
);
4179 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4180 encoder
->enable(encoder
);
4183 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4185 struct drm_device
*dev
= crtc
->dev
;
4186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4187 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4188 struct intel_encoder
*encoder
;
4189 int pipe
= intel_crtc
->pipe
;
4190 int plane
= intel_crtc
->plane
;
4192 WARN_ON(!crtc
->enabled
);
4194 if (intel_crtc
->active
)
4197 intel_crtc
->active
= true;
4199 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4200 if (encoder
->pre_enable
)
4201 encoder
->pre_enable(encoder
);
4203 i9xx_enable_pll(intel_crtc
);
4205 i9xx_pfit_enable(intel_crtc
);
4207 intel_crtc_load_lut(crtc
);
4209 intel_update_watermarks(crtc
);
4210 intel_enable_pipe(dev_priv
, pipe
, false, false);
4211 intel_enable_primary_plane(dev_priv
, plane
, pipe
);
4212 intel_enable_planes(crtc
);
4213 /* The fixup needs to happen before cursor is enabled */
4215 g4x_fixup_plane(dev_priv
, pipe
);
4216 intel_crtc_update_cursor(crtc
, true);
4218 /* Give the overlay scaler a chance to enable if it's on this pipe */
4219 intel_crtc_dpms_overlay(intel_crtc
, true);
4221 intel_update_fbc(dev
);
4223 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4224 encoder
->enable(encoder
);
4227 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4229 struct drm_device
*dev
= crtc
->base
.dev
;
4230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4232 if (!crtc
->config
.gmch_pfit
.control
)
4235 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4237 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4238 I915_READ(PFIT_CONTROL
));
4239 I915_WRITE(PFIT_CONTROL
, 0);
4242 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4244 struct drm_device
*dev
= crtc
->dev
;
4245 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4246 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4247 struct intel_encoder
*encoder
;
4248 int pipe
= intel_crtc
->pipe
;
4249 int plane
= intel_crtc
->plane
;
4251 if (!intel_crtc
->active
)
4254 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4255 encoder
->disable(encoder
);
4257 /* Give the overlay scaler a chance to disable if it's on this pipe */
4258 intel_crtc_wait_for_pending_flips(crtc
);
4259 drm_vblank_off(dev
, pipe
);
4261 if (dev_priv
->fbc
.plane
== plane
)
4262 intel_disable_fbc(dev
);
4264 intel_crtc_dpms_overlay(intel_crtc
, false);
4265 intel_crtc_update_cursor(crtc
, false);
4266 intel_disable_planes(crtc
);
4267 intel_disable_primary_plane(dev_priv
, plane
, pipe
);
4269 intel_disable_pipe(dev_priv
, pipe
);
4271 i9xx_pfit_disable(intel_crtc
);
4273 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4274 if (encoder
->post_disable
)
4275 encoder
->post_disable(encoder
);
4277 if (IS_VALLEYVIEW(dev
) && !intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
4278 vlv_disable_pll(dev_priv
, pipe
);
4279 else if (!IS_VALLEYVIEW(dev
))
4280 i9xx_disable_pll(dev_priv
, pipe
);
4282 intel_crtc
->active
= false;
4283 intel_update_watermarks(crtc
);
4285 intel_update_fbc(dev
);
4288 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4292 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4295 struct drm_device
*dev
= crtc
->dev
;
4296 struct drm_i915_master_private
*master_priv
;
4297 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4298 int pipe
= intel_crtc
->pipe
;
4300 if (!dev
->primary
->master
)
4303 master_priv
= dev
->primary
->master
->driver_priv
;
4304 if (!master_priv
->sarea_priv
)
4309 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4310 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4313 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4314 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4317 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4323 * Sets the power management mode of the pipe and plane.
4325 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4327 struct drm_device
*dev
= crtc
->dev
;
4328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4329 struct intel_encoder
*intel_encoder
;
4330 bool enable
= false;
4332 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4333 enable
|= intel_encoder
->connectors_active
;
4336 dev_priv
->display
.crtc_enable(crtc
);
4338 dev_priv
->display
.crtc_disable(crtc
);
4340 intel_crtc_update_sarea(crtc
, enable
);
4343 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4345 struct drm_device
*dev
= crtc
->dev
;
4346 struct drm_connector
*connector
;
4347 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4348 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4350 /* crtc should still be enabled when we disable it. */
4351 WARN_ON(!crtc
->enabled
);
4353 dev_priv
->display
.crtc_disable(crtc
);
4354 intel_crtc
->eld_vld
= false;
4355 intel_crtc_update_sarea(crtc
, false);
4356 dev_priv
->display
.off(crtc
);
4358 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
4359 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
4360 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
4363 mutex_lock(&dev
->struct_mutex
);
4364 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
4365 mutex_unlock(&dev
->struct_mutex
);
4369 /* Update computed state. */
4370 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
4371 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
4374 if (connector
->encoder
->crtc
!= crtc
)
4377 connector
->dpms
= DRM_MODE_DPMS_OFF
;
4378 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
4382 void intel_encoder_destroy(struct drm_encoder
*encoder
)
4384 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4386 drm_encoder_cleanup(encoder
);
4387 kfree(intel_encoder
);
4390 /* Simple dpms helper for encoders with just one connector, no cloning and only
4391 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4392 * state of the entire output pipe. */
4393 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
4395 if (mode
== DRM_MODE_DPMS_ON
) {
4396 encoder
->connectors_active
= true;
4398 intel_crtc_update_dpms(encoder
->base
.crtc
);
4400 encoder
->connectors_active
= false;
4402 intel_crtc_update_dpms(encoder
->base
.crtc
);
4406 /* Cross check the actual hw state with our own modeset state tracking (and it's
4407 * internal consistency). */
4408 static void intel_connector_check_state(struct intel_connector
*connector
)
4410 if (connector
->get_hw_state(connector
)) {
4411 struct intel_encoder
*encoder
= connector
->encoder
;
4412 struct drm_crtc
*crtc
;
4413 bool encoder_enabled
;
4416 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4417 connector
->base
.base
.id
,
4418 drm_get_connector_name(&connector
->base
));
4420 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4421 "wrong connector dpms state\n");
4422 WARN(connector
->base
.encoder
!= &encoder
->base
,
4423 "active connector not linked to encoder\n");
4424 WARN(!encoder
->connectors_active
,
4425 "encoder->connectors_active not set\n");
4427 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4428 WARN(!encoder_enabled
, "encoder not enabled\n");
4429 if (WARN_ON(!encoder
->base
.crtc
))
4432 crtc
= encoder
->base
.crtc
;
4434 WARN(!crtc
->enabled
, "crtc not enabled\n");
4435 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4436 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4437 "encoder active on the wrong pipe\n");
4441 /* Even simpler default implementation, if there's really no special case to
4443 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4445 /* All the simple cases only support two dpms states. */
4446 if (mode
!= DRM_MODE_DPMS_ON
)
4447 mode
= DRM_MODE_DPMS_OFF
;
4449 if (mode
== connector
->dpms
)
4452 connector
->dpms
= mode
;
4454 /* Only need to change hw state when actually enabled */
4455 if (connector
->encoder
)
4456 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
4458 intel_modeset_check_state(connector
->dev
);
4461 /* Simple connector->get_hw_state implementation for encoders that support only
4462 * one connector and no cloning and hence the encoder state determines the state
4463 * of the connector. */
4464 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4467 struct intel_encoder
*encoder
= connector
->encoder
;
4469 return encoder
->get_hw_state(encoder
, &pipe
);
4472 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4473 struct intel_crtc_config
*pipe_config
)
4475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4476 struct intel_crtc
*pipe_B_crtc
=
4477 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4479 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4480 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4481 if (pipe_config
->fdi_lanes
> 4) {
4482 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4483 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4487 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
4488 if (pipe_config
->fdi_lanes
> 2) {
4489 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4490 pipe_config
->fdi_lanes
);
4497 if (INTEL_INFO(dev
)->num_pipes
== 2)
4500 /* Ivybridge 3 pipe is really complicated */
4505 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4506 pipe_config
->fdi_lanes
> 2) {
4507 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4508 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4513 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4514 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4515 if (pipe_config
->fdi_lanes
> 2) {
4516 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4517 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4521 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4531 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4532 struct intel_crtc_config
*pipe_config
)
4534 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4535 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4536 int lane
, link_bw
, fdi_dotclock
;
4537 bool setup_ok
, needs_recompute
= false;
4540 /* FDI is a binary signal running at ~2.7GHz, encoding
4541 * each output octet as 10 bits. The actual frequency
4542 * is stored as a divider into a 100MHz clock, and the
4543 * mode pixel clock is stored in units of 1KHz.
4544 * Hence the bw of each lane in terms of the mode signal
4547 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4549 fdi_dotclock
= adjusted_mode
->crtc_clock
;
4551 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4552 pipe_config
->pipe_bpp
);
4554 pipe_config
->fdi_lanes
= lane
;
4556 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4557 link_bw
, &pipe_config
->fdi_m_n
);
4559 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4560 intel_crtc
->pipe
, pipe_config
);
4561 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4562 pipe_config
->pipe_bpp
-= 2*3;
4563 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4564 pipe_config
->pipe_bpp
);
4565 needs_recompute
= true;
4566 pipe_config
->bw_constrained
= true;
4571 if (needs_recompute
)
4574 return setup_ok
? 0 : -EINVAL
;
4577 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4578 struct intel_crtc_config
*pipe_config
)
4580 pipe_config
->ips_enabled
= i915_enable_ips
&&
4581 hsw_crtc_supports_ips(crtc
) &&
4582 pipe_config
->pipe_bpp
<= 24;
4585 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4586 struct intel_crtc_config
*pipe_config
)
4588 struct drm_device
*dev
= crtc
->base
.dev
;
4589 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4591 /* FIXME should check pixel clock limits on all platforms */
4592 if (INTEL_INFO(dev
)->gen
< 4) {
4593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4595 dev_priv
->display
.get_display_clock_speed(dev
);
4598 * Enable pixel doubling when the dot clock
4599 * is > 90% of the (display) core speed.
4601 * GDG double wide on either pipe,
4602 * otherwise pipe A only.
4604 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4605 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
4607 pipe_config
->double_wide
= true;
4610 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
4615 * Pipe horizontal size must be even in:
4617 * - LVDS dual channel mode
4618 * - Double wide pipe
4620 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4621 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4622 pipe_config
->pipe_src_w
&= ~1;
4624 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4625 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4627 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4628 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4631 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4632 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4633 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4634 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4636 pipe_config
->pipe_bpp
= 8*3;
4640 hsw_compute_ips_config(crtc
, pipe_config
);
4642 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4643 * clock survives for now. */
4644 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4645 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4647 if (pipe_config
->has_pch_encoder
)
4648 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4653 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4655 return 400000; /* FIXME */
4658 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4663 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4668 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4673 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4677 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4679 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4680 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4682 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4684 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4686 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4689 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4690 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4692 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4697 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4701 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4703 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4706 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4707 case GC_DISPLAY_CLOCK_333_MHZ
:
4710 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4716 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4721 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4724 /* Assume that the hardware is in the high speed state. This
4725 * should be the default.
4727 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4728 case GC_CLOCK_133_200
:
4729 case GC_CLOCK_100_200
:
4731 case GC_CLOCK_166_250
:
4733 case GC_CLOCK_100_133
:
4737 /* Shouldn't happen */
4741 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4747 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4749 while (*num
> DATA_LINK_M_N_MASK
||
4750 *den
> DATA_LINK_M_N_MASK
) {
4756 static void compute_m_n(unsigned int m
, unsigned int n
,
4757 uint32_t *ret_m
, uint32_t *ret_n
)
4759 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4760 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4761 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4765 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4766 int pixel_clock
, int link_clock
,
4767 struct intel_link_m_n
*m_n
)
4771 compute_m_n(bits_per_pixel
* pixel_clock
,
4772 link_clock
* nlanes
* 8,
4773 &m_n
->gmch_m
, &m_n
->gmch_n
);
4775 compute_m_n(pixel_clock
, link_clock
,
4776 &m_n
->link_m
, &m_n
->link_n
);
4779 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4781 if (i915_panel_use_ssc
>= 0)
4782 return i915_panel_use_ssc
!= 0;
4783 return dev_priv
->vbt
.lvds_use_ssc
4784 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4787 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4789 struct drm_device
*dev
= crtc
->dev
;
4790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4793 if (IS_VALLEYVIEW(dev
)) {
4795 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4796 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4797 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
4798 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
4799 } else if (!IS_GEN2(dev
)) {
4808 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4810 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4813 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4815 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4818 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4819 intel_clock_t
*reduced_clock
)
4821 struct drm_device
*dev
= crtc
->base
.dev
;
4822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4823 int pipe
= crtc
->pipe
;
4826 if (IS_PINEVIEW(dev
)) {
4827 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4829 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4831 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4833 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4836 I915_WRITE(FP0(pipe
), fp
);
4837 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4839 crtc
->lowfreq_avail
= false;
4840 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4841 reduced_clock
&& i915_powersave
) {
4842 I915_WRITE(FP1(pipe
), fp2
);
4843 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4844 crtc
->lowfreq_avail
= true;
4846 I915_WRITE(FP1(pipe
), fp
);
4847 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4851 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4857 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4858 * and set it to a reasonable value instead.
4860 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
4861 reg_val
&= 0xffffff00;
4862 reg_val
|= 0x00000030;
4863 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
4865 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
4866 reg_val
&= 0x8cffffff;
4867 reg_val
= 0x8c000000;
4868 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
4870 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
4871 reg_val
&= 0xffffff00;
4872 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
4874 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
4875 reg_val
&= 0x00ffffff;
4876 reg_val
|= 0xb0000000;
4877 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
4880 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4881 struct intel_link_m_n
*m_n
)
4883 struct drm_device
*dev
= crtc
->base
.dev
;
4884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4885 int pipe
= crtc
->pipe
;
4887 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4888 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4889 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4890 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4893 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4894 struct intel_link_m_n
*m_n
)
4896 struct drm_device
*dev
= crtc
->base
.dev
;
4897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4898 int pipe
= crtc
->pipe
;
4899 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4901 if (INTEL_INFO(dev
)->gen
>= 5) {
4902 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4903 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4904 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4905 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4907 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4908 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4909 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4910 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4914 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4916 if (crtc
->config
.has_pch_encoder
)
4917 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4919 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4922 static void vlv_update_pll(struct intel_crtc
*crtc
)
4924 struct drm_device
*dev
= crtc
->base
.dev
;
4925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4926 int pipe
= crtc
->pipe
;
4928 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4929 u32 coreclk
, reg_val
, dpll_md
;
4931 mutex_lock(&dev_priv
->dpio_lock
);
4933 bestn
= crtc
->config
.dpll
.n
;
4934 bestm1
= crtc
->config
.dpll
.m1
;
4935 bestm2
= crtc
->config
.dpll
.m2
;
4936 bestp1
= crtc
->config
.dpll
.p1
;
4937 bestp2
= crtc
->config
.dpll
.p2
;
4939 /* See eDP HDMI DPIO driver vbios notes doc */
4941 /* PLL B needs special handling */
4943 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4945 /* Set up Tx target for periodic Rcomp update */
4946 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
4948 /* Disable target IRef on PLL */
4949 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
4950 reg_val
&= 0x00ffffff;
4951 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
4953 /* Disable fast lock */
4954 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
4956 /* Set idtafcrecal before PLL is enabled */
4957 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4958 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4959 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4960 mdiv
|= (1 << DPIO_K_SHIFT
);
4963 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4964 * but we don't support that).
4965 * Note: don't use the DAC post divider as it seems unstable.
4967 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4968 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
4970 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4971 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
4973 /* Set HBR and RBR LPF coefficients */
4974 if (crtc
->config
.port_clock
== 162000 ||
4975 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4976 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4977 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
4980 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
4983 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4984 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4985 /* Use SSC source */
4987 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4990 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4992 } else { /* HDMI or VGA */
4993 /* Use bend source */
4995 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
4998 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5002 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5003 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5004 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5005 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5006 coreclk
|= 0x01000000;
5007 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5009 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5012 * Enable DPIO clock input. We should never disable the reference
5013 * clock for pipe B, since VGA hotplug / manual detection depends
5016 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5017 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5018 /* We should never disable this, set it here for state tracking */
5020 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5021 dpll
|= DPLL_VCO_ENABLE
;
5022 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5024 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5025 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5026 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5028 if (crtc
->config
.has_dp_encoder
)
5029 intel_dp_set_m_n(crtc
);
5031 mutex_unlock(&dev_priv
->dpio_lock
);
5034 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5035 intel_clock_t
*reduced_clock
,
5038 struct drm_device
*dev
= crtc
->base
.dev
;
5039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5042 struct dpll
*clock
= &crtc
->config
.dpll
;
5044 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5046 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5047 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5049 dpll
= DPLL_VGA_MODE_DIS
;
5051 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5052 dpll
|= DPLLB_MODE_LVDS
;
5054 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5056 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5057 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5058 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5062 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5064 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5065 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5067 /* compute bitmask from p1 value */
5068 if (IS_PINEVIEW(dev
))
5069 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5071 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5072 if (IS_G4X(dev
) && reduced_clock
)
5073 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5075 switch (clock
->p2
) {
5077 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5080 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5083 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5086 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5089 if (INTEL_INFO(dev
)->gen
>= 4)
5090 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5092 if (crtc
->config
.sdvo_tv_clock
)
5093 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5094 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5095 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5096 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5098 dpll
|= PLL_REF_INPUT_DREFCLK
;
5100 dpll
|= DPLL_VCO_ENABLE
;
5101 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5103 if (INTEL_INFO(dev
)->gen
>= 4) {
5104 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5105 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5106 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5109 if (crtc
->config
.has_dp_encoder
)
5110 intel_dp_set_m_n(crtc
);
5113 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5114 intel_clock_t
*reduced_clock
,
5117 struct drm_device
*dev
= crtc
->base
.dev
;
5118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5120 struct dpll
*clock
= &crtc
->config
.dpll
;
5122 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5124 dpll
= DPLL_VGA_MODE_DIS
;
5126 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5127 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5130 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5132 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5134 dpll
|= PLL_P2_DIVIDE_BY_4
;
5137 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5138 dpll
|= DPLL_DVO_2X_MODE
;
5140 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5141 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5142 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5144 dpll
|= PLL_REF_INPUT_DREFCLK
;
5146 dpll
|= DPLL_VCO_ENABLE
;
5147 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5150 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5152 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5153 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5154 enum pipe pipe
= intel_crtc
->pipe
;
5155 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5156 struct drm_display_mode
*adjusted_mode
=
5157 &intel_crtc
->config
.adjusted_mode
;
5158 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
5160 /* We need to be careful not to changed the adjusted mode, for otherwise
5161 * the hw state checker will get angry at the mismatch. */
5162 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5163 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5165 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5166 /* the chip adds 2 halflines automatically */
5168 crtc_vblank_end
-= 1;
5169 vsyncshift
= adjusted_mode
->crtc_hsync_start
5170 - adjusted_mode
->crtc_htotal
/ 2;
5175 if (INTEL_INFO(dev
)->gen
> 3)
5176 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5178 I915_WRITE(HTOTAL(cpu_transcoder
),
5179 (adjusted_mode
->crtc_hdisplay
- 1) |
5180 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5181 I915_WRITE(HBLANK(cpu_transcoder
),
5182 (adjusted_mode
->crtc_hblank_start
- 1) |
5183 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5184 I915_WRITE(HSYNC(cpu_transcoder
),
5185 (adjusted_mode
->crtc_hsync_start
- 1) |
5186 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5188 I915_WRITE(VTOTAL(cpu_transcoder
),
5189 (adjusted_mode
->crtc_vdisplay
- 1) |
5190 ((crtc_vtotal
- 1) << 16));
5191 I915_WRITE(VBLANK(cpu_transcoder
),
5192 (adjusted_mode
->crtc_vblank_start
- 1) |
5193 ((crtc_vblank_end
- 1) << 16));
5194 I915_WRITE(VSYNC(cpu_transcoder
),
5195 (adjusted_mode
->crtc_vsync_start
- 1) |
5196 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5198 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5199 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5200 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5202 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5203 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5204 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5206 /* pipesrc controls the size that is scaled from, which should
5207 * always be the user's requested size.
5209 I915_WRITE(PIPESRC(pipe
),
5210 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5211 (intel_crtc
->config
.pipe_src_h
- 1));
5214 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5215 struct intel_crtc_config
*pipe_config
)
5217 struct drm_device
*dev
= crtc
->base
.dev
;
5218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5219 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5222 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5223 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5224 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5225 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5226 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5227 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5228 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5229 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5230 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5232 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5233 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5234 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5235 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5236 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5237 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5238 tmp
= I915_READ(VSYNC(cpu_transcoder
));
5239 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
5240 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5242 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
5243 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
5244 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
5245 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
5248 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
5249 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
5250 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
5252 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
5253 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
5256 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
5257 struct intel_crtc_config
*pipe_config
)
5259 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5261 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
5262 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
5263 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
5264 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
5266 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
5267 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
5268 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
5269 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
5271 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
5273 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.crtc_clock
;
5274 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
5277 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
5279 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5285 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
5286 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
5287 pipeconf
|= PIPECONF_ENABLE
;
5289 if (intel_crtc
->config
.double_wide
)
5290 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
5292 /* only g4x and later have fancy bpc/dither controls */
5293 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5294 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5295 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
5296 pipeconf
|= PIPECONF_DITHER_EN
|
5297 PIPECONF_DITHER_TYPE_SP
;
5299 switch (intel_crtc
->config
.pipe_bpp
) {
5301 pipeconf
|= PIPECONF_6BPC
;
5304 pipeconf
|= PIPECONF_8BPC
;
5307 pipeconf
|= PIPECONF_10BPC
;
5310 /* Case prevented by intel_choose_pipe_bpp_dither. */
5315 if (HAS_PIPE_CXSR(dev
)) {
5316 if (intel_crtc
->lowfreq_avail
) {
5317 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5318 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5320 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5324 if (!IS_GEN2(dev
) &&
5325 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5326 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5328 pipeconf
|= PIPECONF_PROGRESSIVE
;
5330 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
5331 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
5333 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
5334 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
5337 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5339 struct drm_framebuffer
*fb
)
5341 struct drm_device
*dev
= crtc
->dev
;
5342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5343 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5344 int pipe
= intel_crtc
->pipe
;
5345 int plane
= intel_crtc
->plane
;
5346 int refclk
, num_connectors
= 0;
5347 intel_clock_t clock
, reduced_clock
;
5349 bool ok
, has_reduced_clock
= false;
5350 bool is_lvds
= false, is_dsi
= false;
5351 struct intel_encoder
*encoder
;
5352 const intel_limit_t
*limit
;
5355 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5356 switch (encoder
->type
) {
5357 case INTEL_OUTPUT_LVDS
:
5360 case INTEL_OUTPUT_DSI
:
5371 if (!intel_crtc
->config
.clock_set
) {
5372 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5375 * Returns a set of divisors for the desired target clock with
5376 * the given refclk, or FALSE. The returned values represent
5377 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5380 limit
= intel_limit(crtc
, refclk
);
5381 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
5382 intel_crtc
->config
.port_clock
,
5383 refclk
, NULL
, &clock
);
5385 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5389 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5391 * Ensure we match the reduced clock's P to the target
5392 * clock. If the clocks don't match, we can't switch
5393 * the display clock by using the FP0/FP1. In such case
5394 * we will disable the LVDS downclock feature.
5397 dev_priv
->display
.find_dpll(limit
, crtc
,
5398 dev_priv
->lvds_downclock
,
5402 /* Compat-code for transition, will disappear. */
5403 intel_crtc
->config
.dpll
.n
= clock
.n
;
5404 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5405 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5406 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5407 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5411 i8xx_update_pll(intel_crtc
,
5412 has_reduced_clock
? &reduced_clock
: NULL
,
5414 } else if (IS_VALLEYVIEW(dev
)) {
5415 vlv_update_pll(intel_crtc
);
5417 i9xx_update_pll(intel_crtc
,
5418 has_reduced_clock
? &reduced_clock
: NULL
,
5423 /* Set up the display plane register */
5424 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5426 if (!IS_VALLEYVIEW(dev
)) {
5428 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5430 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5433 intel_set_pipe_timings(intel_crtc
);
5435 /* pipesrc and dspsize control the size that is scaled from,
5436 * which should always be the user's requested size.
5438 I915_WRITE(DSPSIZE(plane
),
5439 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5440 (intel_crtc
->config
.pipe_src_w
- 1));
5441 I915_WRITE(DSPPOS(plane
), 0);
5443 i9xx_set_pipeconf(intel_crtc
);
5445 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5446 POSTING_READ(DSPCNTR(plane
));
5448 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5453 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5454 struct intel_crtc_config
*pipe_config
)
5456 struct drm_device
*dev
= crtc
->base
.dev
;
5457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5460 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
5463 tmp
= I915_READ(PFIT_CONTROL
);
5464 if (!(tmp
& PFIT_ENABLE
))
5467 /* Check whether the pfit is attached to our pipe. */
5468 if (INTEL_INFO(dev
)->gen
< 4) {
5469 if (crtc
->pipe
!= PIPE_B
)
5472 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5476 pipe_config
->gmch_pfit
.control
= tmp
;
5477 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5478 if (INTEL_INFO(dev
)->gen
< 5)
5479 pipe_config
->gmch_pfit
.lvds_border_bits
=
5480 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5483 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
5484 struct intel_crtc_config
*pipe_config
)
5486 struct drm_device
*dev
= crtc
->base
.dev
;
5487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5488 int pipe
= pipe_config
->cpu_transcoder
;
5489 intel_clock_t clock
;
5491 int refclk
= 100000;
5493 mutex_lock(&dev_priv
->dpio_lock
);
5494 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
5495 mutex_unlock(&dev_priv
->dpio_lock
);
5497 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
5498 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
5499 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
5500 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
5501 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
5503 vlv_clock(refclk
, &clock
);
5505 /* clock.dot is the fast clock */
5506 pipe_config
->port_clock
= clock
.dot
/ 5;
5509 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5510 struct intel_crtc_config
*pipe_config
)
5512 struct drm_device
*dev
= crtc
->base
.dev
;
5513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5516 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5517 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5519 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5520 if (!(tmp
& PIPECONF_ENABLE
))
5523 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5524 switch (tmp
& PIPECONF_BPC_MASK
) {
5526 pipe_config
->pipe_bpp
= 18;
5529 pipe_config
->pipe_bpp
= 24;
5531 case PIPECONF_10BPC
:
5532 pipe_config
->pipe_bpp
= 30;
5539 if (INTEL_INFO(dev
)->gen
< 4)
5540 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5542 intel_get_pipe_timings(crtc
, pipe_config
);
5544 i9xx_get_pfit_config(crtc
, pipe_config
);
5546 if (INTEL_INFO(dev
)->gen
>= 4) {
5547 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5548 pipe_config
->pixel_multiplier
=
5549 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5550 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5551 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5552 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5553 tmp
= I915_READ(DPLL(crtc
->pipe
));
5554 pipe_config
->pixel_multiplier
=
5555 ((tmp
& SDVO_MULTIPLIER_MASK
)
5556 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5558 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5559 * port and will be fixed up in the encoder->get_config
5561 pipe_config
->pixel_multiplier
= 1;
5563 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5564 if (!IS_VALLEYVIEW(dev
)) {
5565 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5566 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5568 /* Mask out read-only status bits. */
5569 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5570 DPLL_PORTC_READY_MASK
|
5571 DPLL_PORTB_READY_MASK
);
5574 if (IS_VALLEYVIEW(dev
))
5575 vlv_crtc_clock_get(crtc
, pipe_config
);
5577 i9xx_crtc_clock_get(crtc
, pipe_config
);
5582 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5585 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5586 struct intel_encoder
*encoder
;
5588 bool has_lvds
= false;
5589 bool has_cpu_edp
= false;
5590 bool has_panel
= false;
5591 bool has_ck505
= false;
5592 bool can_ssc
= false;
5594 /* We need to take the global config into account */
5595 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5597 switch (encoder
->type
) {
5598 case INTEL_OUTPUT_LVDS
:
5602 case INTEL_OUTPUT_EDP
:
5604 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5610 if (HAS_PCH_IBX(dev
)) {
5611 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5612 can_ssc
= has_ck505
;
5618 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5619 has_panel
, has_lvds
, has_ck505
);
5621 /* Ironlake: try to setup display ref clock before DPLL
5622 * enabling. This is only under driver's control after
5623 * PCH B stepping, previous chipset stepping should be
5624 * ignoring this setting.
5626 val
= I915_READ(PCH_DREF_CONTROL
);
5628 /* As we must carefully and slowly disable/enable each source in turn,
5629 * compute the final state we want first and check if we need to
5630 * make any changes at all.
5633 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5635 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5637 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5639 final
&= ~DREF_SSC_SOURCE_MASK
;
5640 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5641 final
&= ~DREF_SSC1_ENABLE
;
5644 final
|= DREF_SSC_SOURCE_ENABLE
;
5646 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5647 final
|= DREF_SSC1_ENABLE
;
5650 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5651 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5653 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5655 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5657 final
|= DREF_SSC_SOURCE_DISABLE
;
5658 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5664 /* Always enable nonspread source */
5665 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5668 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5670 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5673 val
&= ~DREF_SSC_SOURCE_MASK
;
5674 val
|= DREF_SSC_SOURCE_ENABLE
;
5676 /* SSC must be turned on before enabling the CPU output */
5677 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5678 DRM_DEBUG_KMS("Using SSC on panel\n");
5679 val
|= DREF_SSC1_ENABLE
;
5681 val
&= ~DREF_SSC1_ENABLE
;
5683 /* Get SSC going before enabling the outputs */
5684 I915_WRITE(PCH_DREF_CONTROL
, val
);
5685 POSTING_READ(PCH_DREF_CONTROL
);
5688 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5690 /* Enable CPU source on CPU attached eDP */
5692 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5693 DRM_DEBUG_KMS("Using SSC on eDP\n");
5694 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5697 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5699 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5701 I915_WRITE(PCH_DREF_CONTROL
, val
);
5702 POSTING_READ(PCH_DREF_CONTROL
);
5705 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5707 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5709 /* Turn off CPU output */
5710 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5712 I915_WRITE(PCH_DREF_CONTROL
, val
);
5713 POSTING_READ(PCH_DREF_CONTROL
);
5716 /* Turn off the SSC source */
5717 val
&= ~DREF_SSC_SOURCE_MASK
;
5718 val
|= DREF_SSC_SOURCE_DISABLE
;
5721 val
&= ~DREF_SSC1_ENABLE
;
5723 I915_WRITE(PCH_DREF_CONTROL
, val
);
5724 POSTING_READ(PCH_DREF_CONTROL
);
5728 BUG_ON(val
!= final
);
5731 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5735 tmp
= I915_READ(SOUTH_CHICKEN2
);
5736 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5737 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5739 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5740 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5741 DRM_ERROR("FDI mPHY reset assert timeout\n");
5743 tmp
= I915_READ(SOUTH_CHICKEN2
);
5744 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5745 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5747 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5748 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5749 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5752 /* WaMPhyProgramming:hsw */
5753 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5757 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5758 tmp
&= ~(0xFF << 24);
5759 tmp
|= (0x12 << 24);
5760 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5762 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5764 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5766 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5768 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5770 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5771 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5772 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5774 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5775 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5776 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5778 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5781 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5783 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5786 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5788 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5791 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5793 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5796 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5798 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5799 tmp
&= ~(0xFF << 16);
5800 tmp
|= (0x1C << 16);
5801 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5803 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5804 tmp
&= ~(0xFF << 16);
5805 tmp
|= (0x1C << 16);
5806 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5808 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5810 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5812 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5814 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5816 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5817 tmp
&= ~(0xF << 28);
5819 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5821 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5822 tmp
&= ~(0xF << 28);
5824 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5827 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5828 * Programming" based on the parameters passed:
5829 * - Sequence to enable CLKOUT_DP
5830 * - Sequence to enable CLKOUT_DP without spread
5831 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5833 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5839 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5841 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5842 with_fdi
, "LP PCH doesn't have FDI\n"))
5845 mutex_lock(&dev_priv
->dpio_lock
);
5847 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5848 tmp
&= ~SBI_SSCCTL_DISABLE
;
5849 tmp
|= SBI_SSCCTL_PATHALT
;
5850 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5855 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5856 tmp
&= ~SBI_SSCCTL_PATHALT
;
5857 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5860 lpt_reset_fdi_mphy(dev_priv
);
5861 lpt_program_fdi_mphy(dev_priv
);
5865 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5866 SBI_GEN0
: SBI_DBUFF0
;
5867 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5868 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5869 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5871 mutex_unlock(&dev_priv
->dpio_lock
);
5874 /* Sequence to disable CLKOUT_DP */
5875 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5880 mutex_lock(&dev_priv
->dpio_lock
);
5882 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5883 SBI_GEN0
: SBI_DBUFF0
;
5884 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5885 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5886 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5888 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5889 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5890 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5891 tmp
|= SBI_SSCCTL_PATHALT
;
5892 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5895 tmp
|= SBI_SSCCTL_DISABLE
;
5896 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5899 mutex_unlock(&dev_priv
->dpio_lock
);
5902 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5904 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5905 struct intel_encoder
*encoder
;
5906 bool has_vga
= false;
5908 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5909 switch (encoder
->type
) {
5910 case INTEL_OUTPUT_ANALOG
:
5917 lpt_enable_clkout_dp(dev
, true, true);
5919 lpt_disable_clkout_dp(dev
);
5923 * Initialize reference clocks when the driver loads
5925 void intel_init_pch_refclk(struct drm_device
*dev
)
5927 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5928 ironlake_init_pch_refclk(dev
);
5929 else if (HAS_PCH_LPT(dev
))
5930 lpt_init_pch_refclk(dev
);
5933 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5935 struct drm_device
*dev
= crtc
->dev
;
5936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5937 struct intel_encoder
*encoder
;
5938 int num_connectors
= 0;
5939 bool is_lvds
= false;
5941 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5942 switch (encoder
->type
) {
5943 case INTEL_OUTPUT_LVDS
:
5950 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5951 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5952 dev_priv
->vbt
.lvds_ssc_freq
);
5953 return dev_priv
->vbt
.lvds_ssc_freq
;
5959 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5961 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5963 int pipe
= intel_crtc
->pipe
;
5968 switch (intel_crtc
->config
.pipe_bpp
) {
5970 val
|= PIPECONF_6BPC
;
5973 val
|= PIPECONF_8BPC
;
5976 val
|= PIPECONF_10BPC
;
5979 val
|= PIPECONF_12BPC
;
5982 /* Case prevented by intel_choose_pipe_bpp_dither. */
5986 if (intel_crtc
->config
.dither
)
5987 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5989 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5990 val
|= PIPECONF_INTERLACED_ILK
;
5992 val
|= PIPECONF_PROGRESSIVE
;
5994 if (intel_crtc
->config
.limited_color_range
)
5995 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5997 I915_WRITE(PIPECONF(pipe
), val
);
5998 POSTING_READ(PIPECONF(pipe
));
6002 * Set up the pipe CSC unit.
6004 * Currently only full range RGB to limited range RGB conversion
6005 * is supported, but eventually this should handle various
6006 * RGB<->YCbCr scenarios as well.
6008 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6010 struct drm_device
*dev
= crtc
->dev
;
6011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6012 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6013 int pipe
= intel_crtc
->pipe
;
6014 uint16_t coeff
= 0x7800; /* 1.0 */
6017 * TODO: Check what kind of values actually come out of the pipe
6018 * with these coeff/postoff values and adjust to get the best
6019 * accuracy. Perhaps we even need to take the bpc value into
6023 if (intel_crtc
->config
.limited_color_range
)
6024 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6027 * GY/GU and RY/RU should be the other way around according
6028 * to BSpec, but reality doesn't agree. Just set them up in
6029 * a way that results in the correct picture.
6031 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6032 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6034 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6035 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6037 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6038 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6040 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6041 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6042 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6044 if (INTEL_INFO(dev
)->gen
> 6) {
6045 uint16_t postoff
= 0;
6047 if (intel_crtc
->config
.limited_color_range
)
6048 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6050 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6051 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6052 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6054 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6056 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6058 if (intel_crtc
->config
.limited_color_range
)
6059 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6061 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6065 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6067 struct drm_device
*dev
= crtc
->dev
;
6068 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6069 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6070 enum pipe pipe
= intel_crtc
->pipe
;
6071 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6076 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6077 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6079 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6080 val
|= PIPECONF_INTERLACED_ILK
;
6082 val
|= PIPECONF_PROGRESSIVE
;
6084 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6085 POSTING_READ(PIPECONF(cpu_transcoder
));
6087 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6088 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6090 if (IS_BROADWELL(dev
)) {
6093 switch (intel_crtc
->config
.pipe_bpp
) {
6095 val
|= PIPEMISC_DITHER_6_BPC
;
6098 val
|= PIPEMISC_DITHER_8_BPC
;
6101 val
|= PIPEMISC_DITHER_10_BPC
;
6104 val
|= PIPEMISC_DITHER_12_BPC
;
6107 /* Case prevented by pipe_config_set_bpp. */
6111 if (intel_crtc
->config
.dither
)
6112 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6114 I915_WRITE(PIPEMISC(pipe
), val
);
6118 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6119 intel_clock_t
*clock
,
6120 bool *has_reduced_clock
,
6121 intel_clock_t
*reduced_clock
)
6123 struct drm_device
*dev
= crtc
->dev
;
6124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6125 struct intel_encoder
*intel_encoder
;
6127 const intel_limit_t
*limit
;
6128 bool ret
, is_lvds
= false;
6130 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6131 switch (intel_encoder
->type
) {
6132 case INTEL_OUTPUT_LVDS
:
6138 refclk
= ironlake_get_refclk(crtc
);
6141 * Returns a set of divisors for the desired target clock with the given
6142 * refclk, or FALSE. The returned values represent the clock equation:
6143 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6145 limit
= intel_limit(crtc
, refclk
);
6146 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6147 to_intel_crtc(crtc
)->config
.port_clock
,
6148 refclk
, NULL
, clock
);
6152 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6154 * Ensure we match the reduced clock's P to the target clock.
6155 * If the clocks don't match, we can't switch the display clock
6156 * by using the FP0/FP1. In such case we will disable the LVDS
6157 * downclock feature.
6159 *has_reduced_clock
=
6160 dev_priv
->display
.find_dpll(limit
, crtc
,
6161 dev_priv
->lvds_downclock
,
6169 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
6172 * Account for spread spectrum to avoid
6173 * oversubscribing the link. Max center spread
6174 * is 2.5%; use 5% for safety's sake.
6176 u32 bps
= target_clock
* bpp
* 21 / 20;
6177 return bps
/ (link_bw
* 8) + 1;
6180 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
6182 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
6185 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
6187 intel_clock_t
*reduced_clock
, u32
*fp2
)
6189 struct drm_crtc
*crtc
= &intel_crtc
->base
;
6190 struct drm_device
*dev
= crtc
->dev
;
6191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6192 struct intel_encoder
*intel_encoder
;
6194 int factor
, num_connectors
= 0;
6195 bool is_lvds
= false, is_sdvo
= false;
6197 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6198 switch (intel_encoder
->type
) {
6199 case INTEL_OUTPUT_LVDS
:
6202 case INTEL_OUTPUT_SDVO
:
6203 case INTEL_OUTPUT_HDMI
:
6211 /* Enable autotuning of the PLL clock (if permissible) */
6214 if ((intel_panel_use_ssc(dev_priv
) &&
6215 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
6216 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
6218 } else if (intel_crtc
->config
.sdvo_tv_clock
)
6221 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
6224 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
6230 dpll
|= DPLLB_MODE_LVDS
;
6232 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6234 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
6235 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
6238 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6239 if (intel_crtc
->config
.has_dp_encoder
)
6240 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6242 /* compute bitmask from p1 value */
6243 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6245 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6247 switch (intel_crtc
->config
.dpll
.p2
) {
6249 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6252 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6255 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6258 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6262 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6263 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6265 dpll
|= PLL_REF_INPUT_DREFCLK
;
6267 return dpll
| DPLL_VCO_ENABLE
;
6270 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
6272 struct drm_framebuffer
*fb
)
6274 struct drm_device
*dev
= crtc
->dev
;
6275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6276 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6277 int pipe
= intel_crtc
->pipe
;
6278 int plane
= intel_crtc
->plane
;
6279 int num_connectors
= 0;
6280 intel_clock_t clock
, reduced_clock
;
6281 u32 dpll
= 0, fp
= 0, fp2
= 0;
6282 bool ok
, has_reduced_clock
= false;
6283 bool is_lvds
= false;
6284 struct intel_encoder
*encoder
;
6285 struct intel_shared_dpll
*pll
;
6288 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6289 switch (encoder
->type
) {
6290 case INTEL_OUTPUT_LVDS
:
6298 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
6299 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
6301 ok
= ironlake_compute_clocks(crtc
, &clock
,
6302 &has_reduced_clock
, &reduced_clock
);
6303 if (!ok
&& !intel_crtc
->config
.clock_set
) {
6304 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6307 /* Compat-code for transition, will disappear. */
6308 if (!intel_crtc
->config
.clock_set
) {
6309 intel_crtc
->config
.dpll
.n
= clock
.n
;
6310 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6311 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6312 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6313 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6316 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6317 if (intel_crtc
->config
.has_pch_encoder
) {
6318 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
6319 if (has_reduced_clock
)
6320 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
6322 dpll
= ironlake_compute_dpll(intel_crtc
,
6323 &fp
, &reduced_clock
,
6324 has_reduced_clock
? &fp2
: NULL
);
6326 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
6327 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
6328 if (has_reduced_clock
)
6329 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
6331 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
6333 pll
= intel_get_shared_dpll(intel_crtc
);
6335 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6340 intel_put_shared_dpll(intel_crtc
);
6342 if (intel_crtc
->config
.has_dp_encoder
)
6343 intel_dp_set_m_n(intel_crtc
);
6345 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
6346 intel_crtc
->lowfreq_avail
= true;
6348 intel_crtc
->lowfreq_avail
= false;
6350 intel_set_pipe_timings(intel_crtc
);
6352 if (intel_crtc
->config
.has_pch_encoder
) {
6353 intel_cpu_transcoder_set_m_n(intel_crtc
,
6354 &intel_crtc
->config
.fdi_m_n
);
6357 ironlake_set_pipeconf(crtc
);
6359 /* Set up the display plane register */
6360 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
6361 POSTING_READ(DSPCNTR(plane
));
6363 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6368 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
6369 struct intel_link_m_n
*m_n
)
6371 struct drm_device
*dev
= crtc
->base
.dev
;
6372 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6373 enum pipe pipe
= crtc
->pipe
;
6375 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
6376 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
6377 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
6379 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
6380 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
6381 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6384 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
6385 enum transcoder transcoder
,
6386 struct intel_link_m_n
*m_n
)
6388 struct drm_device
*dev
= crtc
->base
.dev
;
6389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6390 enum pipe pipe
= crtc
->pipe
;
6392 if (INTEL_INFO(dev
)->gen
>= 5) {
6393 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
6394 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
6395 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
6397 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
6398 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
6399 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6401 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
6402 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
6403 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
6405 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
6406 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
6407 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6411 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6412 struct intel_crtc_config
*pipe_config
)
6414 if (crtc
->config
.has_pch_encoder
)
6415 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6417 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6418 &pipe_config
->dp_m_n
);
6421 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6422 struct intel_crtc_config
*pipe_config
)
6424 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6425 &pipe_config
->fdi_m_n
);
6428 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6429 struct intel_crtc_config
*pipe_config
)
6431 struct drm_device
*dev
= crtc
->base
.dev
;
6432 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6435 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6437 if (tmp
& PF_ENABLE
) {
6438 pipe_config
->pch_pfit
.enabled
= true;
6439 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6440 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6442 /* We currently do not free assignements of panel fitters on
6443 * ivb/hsw (since we don't use the higher upscaling modes which
6444 * differentiates them) so just WARN about this case for now. */
6446 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6447 PF_PIPE_SEL_IVB(crtc
->pipe
));
6452 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6453 struct intel_crtc_config
*pipe_config
)
6455 struct drm_device
*dev
= crtc
->base
.dev
;
6456 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6459 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6460 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6462 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6463 if (!(tmp
& PIPECONF_ENABLE
))
6466 switch (tmp
& PIPECONF_BPC_MASK
) {
6468 pipe_config
->pipe_bpp
= 18;
6471 pipe_config
->pipe_bpp
= 24;
6473 case PIPECONF_10BPC
:
6474 pipe_config
->pipe_bpp
= 30;
6476 case PIPECONF_12BPC
:
6477 pipe_config
->pipe_bpp
= 36;
6483 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6484 struct intel_shared_dpll
*pll
;
6486 pipe_config
->has_pch_encoder
= true;
6488 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6489 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6490 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6492 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6494 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6495 pipe_config
->shared_dpll
=
6496 (enum intel_dpll_id
) crtc
->pipe
;
6498 tmp
= I915_READ(PCH_DPLL_SEL
);
6499 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6500 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6502 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6505 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6507 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6508 &pipe_config
->dpll_hw_state
));
6510 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6511 pipe_config
->pixel_multiplier
=
6512 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6513 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6515 ironlake_pch_clock_get(crtc
, pipe_config
);
6517 pipe_config
->pixel_multiplier
= 1;
6520 intel_get_pipe_timings(crtc
, pipe_config
);
6522 ironlake_get_pfit_config(crtc
, pipe_config
);
6527 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6529 struct drm_device
*dev
= dev_priv
->dev
;
6530 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6531 struct intel_crtc
*crtc
;
6532 unsigned long irqflags
;
6535 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6536 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
6537 pipe_name(crtc
->pipe
));
6539 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6540 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6541 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6542 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6543 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6544 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6545 "CPU PWM1 enabled\n");
6546 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6547 "CPU PWM2 enabled\n");
6548 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6549 "PCH PWM1 enabled\n");
6550 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6551 "Utility pin enabled\n");
6552 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6554 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6555 val
= I915_READ(DEIMR
);
6556 WARN((val
| DE_PCH_EVENT_IVB
) != 0xffffffff,
6557 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6558 val
= I915_READ(SDEIMR
);
6559 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6560 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6561 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6565 * This function implements pieces of two sequences from BSpec:
6566 * - Sequence for display software to disable LCPLL
6567 * - Sequence for display software to allow package C8+
6568 * The steps implemented here are just the steps that actually touch the LCPLL
6569 * register. Callers should take care of disabling all the display engine
6570 * functions, doing the mode unset, fixing interrupts, etc.
6572 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6573 bool switch_to_fclk
, bool allow_power_down
)
6577 assert_can_disable_lcpll(dev_priv
);
6579 val
= I915_READ(LCPLL_CTL
);
6581 if (switch_to_fclk
) {
6582 val
|= LCPLL_CD_SOURCE_FCLK
;
6583 I915_WRITE(LCPLL_CTL
, val
);
6585 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6586 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6587 DRM_ERROR("Switching to FCLK failed\n");
6589 val
= I915_READ(LCPLL_CTL
);
6592 val
|= LCPLL_PLL_DISABLE
;
6593 I915_WRITE(LCPLL_CTL
, val
);
6594 POSTING_READ(LCPLL_CTL
);
6596 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6597 DRM_ERROR("LCPLL still locked\n");
6599 val
= I915_READ(D_COMP
);
6600 val
|= D_COMP_COMP_DISABLE
;
6601 mutex_lock(&dev_priv
->rps
.hw_lock
);
6602 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6603 DRM_ERROR("Failed to disable D_COMP\n");
6604 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6605 POSTING_READ(D_COMP
);
6608 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6609 DRM_ERROR("D_COMP RCOMP still in progress\n");
6611 if (allow_power_down
) {
6612 val
= I915_READ(LCPLL_CTL
);
6613 val
|= LCPLL_POWER_DOWN_ALLOW
;
6614 I915_WRITE(LCPLL_CTL
, val
);
6615 POSTING_READ(LCPLL_CTL
);
6620 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6623 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6627 val
= I915_READ(LCPLL_CTL
);
6629 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6630 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6633 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6634 * we'll hang the machine! */
6635 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
6637 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6638 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6639 I915_WRITE(LCPLL_CTL
, val
);
6640 POSTING_READ(LCPLL_CTL
);
6643 val
= I915_READ(D_COMP
);
6644 val
|= D_COMP_COMP_FORCE
;
6645 val
&= ~D_COMP_COMP_DISABLE
;
6646 mutex_lock(&dev_priv
->rps
.hw_lock
);
6647 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6648 DRM_ERROR("Failed to enable D_COMP\n");
6649 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6650 POSTING_READ(D_COMP
);
6652 val
= I915_READ(LCPLL_CTL
);
6653 val
&= ~LCPLL_PLL_DISABLE
;
6654 I915_WRITE(LCPLL_CTL
, val
);
6656 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6657 DRM_ERROR("LCPLL not locked yet\n");
6659 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6660 val
= I915_READ(LCPLL_CTL
);
6661 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6662 I915_WRITE(LCPLL_CTL
, val
);
6664 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6665 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6666 DRM_ERROR("Switching back to LCPLL failed\n");
6669 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
6672 void hsw_enable_pc8_work(struct work_struct
*__work
)
6674 struct drm_i915_private
*dev_priv
=
6675 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6677 struct drm_device
*dev
= dev_priv
->dev
;
6680 WARN_ON(!HAS_PC8(dev
));
6682 if (dev_priv
->pc8
.enabled
)
6685 DRM_DEBUG_KMS("Enabling package C8+\n");
6687 dev_priv
->pc8
.enabled
= true;
6689 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6690 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6691 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6692 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6695 lpt_disable_clkout_dp(dev
);
6696 hsw_pc8_disable_interrupts(dev
);
6697 hsw_disable_lcpll(dev_priv
, true, true);
6699 intel_runtime_pm_put(dev_priv
);
6702 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6704 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6705 WARN(dev_priv
->pc8
.disable_count
< 1,
6706 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6708 dev_priv
->pc8
.disable_count
--;
6709 if (dev_priv
->pc8
.disable_count
!= 0)
6712 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6713 msecs_to_jiffies(i915_pc8_timeout
));
6716 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6718 struct drm_device
*dev
= dev_priv
->dev
;
6721 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6722 WARN(dev_priv
->pc8
.disable_count
< 0,
6723 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6725 dev_priv
->pc8
.disable_count
++;
6726 if (dev_priv
->pc8
.disable_count
!= 1)
6729 WARN_ON(!HAS_PC8(dev
));
6731 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6732 if (!dev_priv
->pc8
.enabled
)
6735 DRM_DEBUG_KMS("Disabling package C8+\n");
6737 intel_runtime_pm_get(dev_priv
);
6739 hsw_restore_lcpll(dev_priv
);
6740 hsw_pc8_restore_interrupts(dev
);
6741 lpt_init_pch_refclk(dev
);
6743 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6744 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6745 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6746 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6749 intel_prepare_ddi(dev
);
6750 i915_gem_init_swizzling(dev
);
6751 mutex_lock(&dev_priv
->rps
.hw_lock
);
6752 gen6_update_ring_freq(dev
);
6753 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6754 dev_priv
->pc8
.enabled
= false;
6757 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6759 if (!HAS_PC8(dev_priv
->dev
))
6762 mutex_lock(&dev_priv
->pc8
.lock
);
6763 __hsw_enable_package_c8(dev_priv
);
6764 mutex_unlock(&dev_priv
->pc8
.lock
);
6767 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6769 if (!HAS_PC8(dev_priv
->dev
))
6772 mutex_lock(&dev_priv
->pc8
.lock
);
6773 __hsw_disable_package_c8(dev_priv
);
6774 mutex_unlock(&dev_priv
->pc8
.lock
);
6777 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6779 struct drm_device
*dev
= dev_priv
->dev
;
6780 struct intel_crtc
*crtc
;
6783 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6784 if (crtc
->base
.enabled
)
6787 /* This case is still possible since we have the i915.disable_power_well
6788 * parameter and also the KVMr or something else might be requesting the
6790 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6792 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6799 /* Since we're called from modeset_global_resources there's no way to
6800 * symmetrically increase and decrease the refcount, so we use
6801 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6804 static void hsw_update_package_c8(struct drm_device
*dev
)
6806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6809 if (!HAS_PC8(dev_priv
->dev
))
6812 if (!i915_enable_pc8
)
6815 mutex_lock(&dev_priv
->pc8
.lock
);
6817 allow
= hsw_can_enable_package_c8(dev_priv
);
6819 if (allow
== dev_priv
->pc8
.requirements_met
)
6822 dev_priv
->pc8
.requirements_met
= allow
;
6825 __hsw_enable_package_c8(dev_priv
);
6827 __hsw_disable_package_c8(dev_priv
);
6830 mutex_unlock(&dev_priv
->pc8
.lock
);
6833 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6835 if (!HAS_PC8(dev_priv
->dev
))
6838 mutex_lock(&dev_priv
->pc8
.lock
);
6839 if (!dev_priv
->pc8
.gpu_idle
) {
6840 dev_priv
->pc8
.gpu_idle
= true;
6841 __hsw_enable_package_c8(dev_priv
);
6843 mutex_unlock(&dev_priv
->pc8
.lock
);
6846 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6848 if (!HAS_PC8(dev_priv
->dev
))
6851 mutex_lock(&dev_priv
->pc8
.lock
);
6852 if (dev_priv
->pc8
.gpu_idle
) {
6853 dev_priv
->pc8
.gpu_idle
= false;
6854 __hsw_disable_package_c8(dev_priv
);
6856 mutex_unlock(&dev_priv
->pc8
.lock
);
6859 #define for_each_power_domain(domain, mask) \
6860 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6861 if ((1 << (domain)) & (mask))
6863 static unsigned long get_pipe_power_domains(struct drm_device
*dev
,
6864 enum pipe pipe
, bool pfit_enabled
)
6867 enum transcoder transcoder
;
6869 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
6871 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
6872 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
6874 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
6879 void intel_display_set_init_power(struct drm_device
*dev
, bool enable
)
6881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6883 if (dev_priv
->power_domains
.init_power_on
== enable
)
6887 intel_display_power_get(dev
, POWER_DOMAIN_INIT
);
6889 intel_display_power_put(dev
, POWER_DOMAIN_INIT
);
6891 dev_priv
->power_domains
.init_power_on
= enable
;
6894 static void modeset_update_power_wells(struct drm_device
*dev
)
6896 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
6897 struct intel_crtc
*crtc
;
6900 * First get all needed power domains, then put all unneeded, to avoid
6901 * any unnecessary toggling of the power wells.
6903 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6904 enum intel_display_power_domain domain
;
6906 if (!crtc
->base
.enabled
)
6909 pipe_domains
[crtc
->pipe
] = get_pipe_power_domains(dev
,
6911 crtc
->config
.pch_pfit
.enabled
);
6913 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
6914 intel_display_power_get(dev
, domain
);
6917 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6918 enum intel_display_power_domain domain
;
6920 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
6921 intel_display_power_put(dev
, domain
);
6923 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
6926 intel_display_set_init_power(dev
, false);
6929 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6931 modeset_update_power_wells(dev
);
6932 hsw_update_package_c8(dev
);
6935 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6937 struct drm_framebuffer
*fb
)
6939 struct drm_device
*dev
= crtc
->dev
;
6940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6941 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6942 int plane
= intel_crtc
->plane
;
6945 if (!intel_ddi_pll_select(intel_crtc
))
6947 intel_ddi_pll_enable(intel_crtc
);
6949 if (intel_crtc
->config
.has_dp_encoder
)
6950 intel_dp_set_m_n(intel_crtc
);
6952 intel_crtc
->lowfreq_avail
= false;
6954 intel_set_pipe_timings(intel_crtc
);
6956 if (intel_crtc
->config
.has_pch_encoder
) {
6957 intel_cpu_transcoder_set_m_n(intel_crtc
,
6958 &intel_crtc
->config
.fdi_m_n
);
6961 haswell_set_pipeconf(crtc
);
6963 intel_set_pipe_csc(crtc
);
6965 /* Set up the display plane register */
6966 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6967 POSTING_READ(DSPCNTR(plane
));
6969 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6974 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6975 struct intel_crtc_config
*pipe_config
)
6977 struct drm_device
*dev
= crtc
->base
.dev
;
6978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6979 enum intel_display_power_domain pfit_domain
;
6982 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6983 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6985 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6986 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6987 enum pipe trans_edp_pipe
;
6988 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6990 WARN(1, "unknown pipe linked to edp transcoder\n");
6991 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6992 case TRANS_DDI_EDP_INPUT_A_ON
:
6993 trans_edp_pipe
= PIPE_A
;
6995 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6996 trans_edp_pipe
= PIPE_B
;
6998 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6999 trans_edp_pipe
= PIPE_C
;
7003 if (trans_edp_pipe
== crtc
->pipe
)
7004 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7007 if (!intel_display_power_enabled(dev
,
7008 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7011 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7012 if (!(tmp
& PIPECONF_ENABLE
))
7016 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7017 * DDI E. So just check whether this pipe is wired to DDI E and whether
7018 * the PCH transcoder is on.
7020 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7021 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
7022 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7023 pipe_config
->has_pch_encoder
= true;
7025 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7026 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7027 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7029 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7032 intel_get_pipe_timings(crtc
, pipe_config
);
7034 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7035 if (intel_display_power_enabled(dev
, pfit_domain
))
7036 ironlake_get_pfit_config(crtc
, pipe_config
);
7038 if (IS_HASWELL(dev
))
7039 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7040 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7042 pipe_config
->pixel_multiplier
= 1;
7047 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
7049 struct drm_framebuffer
*fb
)
7051 struct drm_device
*dev
= crtc
->dev
;
7052 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7053 struct intel_encoder
*encoder
;
7054 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7055 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
7056 int pipe
= intel_crtc
->pipe
;
7059 drm_vblank_pre_modeset(dev
, pipe
);
7061 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
7063 drm_vblank_post_modeset(dev
, pipe
);
7068 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7069 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7070 encoder
->base
.base
.id
,
7071 drm_get_encoder_name(&encoder
->base
),
7072 mode
->base
.id
, mode
->name
);
7073 encoder
->mode_set(encoder
);
7082 } hdmi_audio_clock
[] = {
7083 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7084 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7085 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7086 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7087 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7088 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7089 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7090 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7091 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7092 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7095 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7096 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7100 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7101 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7105 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7106 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7110 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7111 hdmi_audio_clock
[i
].clock
,
7112 hdmi_audio_clock
[i
].config
);
7114 return hdmi_audio_clock
[i
].config
;
7117 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7118 int reg_eldv
, uint32_t bits_eldv
,
7119 int reg_elda
, uint32_t bits_elda
,
7122 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7123 uint8_t *eld
= connector
->eld
;
7126 i
= I915_READ(reg_eldv
);
7135 i
= I915_READ(reg_elda
);
7137 I915_WRITE(reg_elda
, i
);
7139 for (i
= 0; i
< eld
[2]; i
++)
7140 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7146 static void g4x_write_eld(struct drm_connector
*connector
,
7147 struct drm_crtc
*crtc
,
7148 struct drm_display_mode
*mode
)
7150 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7151 uint8_t *eld
= connector
->eld
;
7156 i
= I915_READ(G4X_AUD_VID_DID
);
7158 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7159 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7161 eldv
= G4X_ELDV_DEVCTG
;
7163 if (intel_eld_uptodate(connector
,
7164 G4X_AUD_CNTL_ST
, eldv
,
7165 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7166 G4X_HDMIW_HDMIEDID
))
7169 i
= I915_READ(G4X_AUD_CNTL_ST
);
7170 i
&= ~(eldv
| G4X_ELD_ADDR
);
7171 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7172 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7177 len
= min_t(uint8_t, eld
[2], len
);
7178 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7179 for (i
= 0; i
< len
; i
++)
7180 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7182 i
= I915_READ(G4X_AUD_CNTL_ST
);
7184 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7187 static void haswell_write_eld(struct drm_connector
*connector
,
7188 struct drm_crtc
*crtc
,
7189 struct drm_display_mode
*mode
)
7191 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7192 uint8_t *eld
= connector
->eld
;
7193 struct drm_device
*dev
= crtc
->dev
;
7194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7198 int pipe
= to_intel_crtc(crtc
)->pipe
;
7201 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7202 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7203 int aud_config
= HSW_AUD_CFG(pipe
);
7204 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7207 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7209 /* Audio output enable */
7210 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7211 tmp
= I915_READ(aud_cntrl_st2
);
7212 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7213 I915_WRITE(aud_cntrl_st2
, tmp
);
7215 /* Wait for 1 vertical blank */
7216 intel_wait_for_vblank(dev
, pipe
);
7218 /* Set ELD valid state */
7219 tmp
= I915_READ(aud_cntrl_st2
);
7220 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7221 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7222 I915_WRITE(aud_cntrl_st2
, tmp
);
7223 tmp
= I915_READ(aud_cntrl_st2
);
7224 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7226 /* Enable HDMI mode */
7227 tmp
= I915_READ(aud_config
);
7228 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7229 /* clear N_programing_enable and N_value_index */
7230 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7231 I915_WRITE(aud_config
, tmp
);
7233 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7235 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7236 intel_crtc
->eld_vld
= true;
7238 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7239 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7240 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7241 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7243 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7246 if (intel_eld_uptodate(connector
,
7247 aud_cntrl_st2
, eldv
,
7248 aud_cntl_st
, IBX_ELD_ADDRESS
,
7252 i
= I915_READ(aud_cntrl_st2
);
7254 I915_WRITE(aud_cntrl_st2
, i
);
7259 i
= I915_READ(aud_cntl_st
);
7260 i
&= ~IBX_ELD_ADDRESS
;
7261 I915_WRITE(aud_cntl_st
, i
);
7262 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7263 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7265 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7266 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7267 for (i
= 0; i
< len
; i
++)
7268 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7270 i
= I915_READ(aud_cntrl_st2
);
7272 I915_WRITE(aud_cntrl_st2
, i
);
7276 static void ironlake_write_eld(struct drm_connector
*connector
,
7277 struct drm_crtc
*crtc
,
7278 struct drm_display_mode
*mode
)
7280 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7281 uint8_t *eld
= connector
->eld
;
7289 int pipe
= to_intel_crtc(crtc
)->pipe
;
7291 if (HAS_PCH_IBX(connector
->dev
)) {
7292 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
7293 aud_config
= IBX_AUD_CFG(pipe
);
7294 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
7295 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
7296 } else if (IS_VALLEYVIEW(connector
->dev
)) {
7297 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
7298 aud_config
= VLV_AUD_CFG(pipe
);
7299 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
7300 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
7302 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
7303 aud_config
= CPT_AUD_CFG(pipe
);
7304 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
7305 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
7308 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7310 if (IS_VALLEYVIEW(connector
->dev
)) {
7311 struct intel_encoder
*intel_encoder
;
7312 struct intel_digital_port
*intel_dig_port
;
7314 intel_encoder
= intel_attached_encoder(connector
);
7315 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
7316 i
= intel_dig_port
->port
;
7318 i
= I915_READ(aud_cntl_st
);
7319 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
7320 /* DIP_Port_Select, 0x1 = PortB */
7324 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7325 /* operate blindly on all ports */
7326 eldv
= IBX_ELD_VALIDB
;
7327 eldv
|= IBX_ELD_VALIDB
<< 4;
7328 eldv
|= IBX_ELD_VALIDB
<< 8;
7330 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
7331 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
7334 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7335 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7336 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7337 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7339 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7342 if (intel_eld_uptodate(connector
,
7343 aud_cntrl_st2
, eldv
,
7344 aud_cntl_st
, IBX_ELD_ADDRESS
,
7348 i
= I915_READ(aud_cntrl_st2
);
7350 I915_WRITE(aud_cntrl_st2
, i
);
7355 i
= I915_READ(aud_cntl_st
);
7356 i
&= ~IBX_ELD_ADDRESS
;
7357 I915_WRITE(aud_cntl_st
, i
);
7359 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7360 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7361 for (i
= 0; i
< len
; i
++)
7362 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7364 i
= I915_READ(aud_cntrl_st2
);
7366 I915_WRITE(aud_cntrl_st2
, i
);
7369 void intel_write_eld(struct drm_encoder
*encoder
,
7370 struct drm_display_mode
*mode
)
7372 struct drm_crtc
*crtc
= encoder
->crtc
;
7373 struct drm_connector
*connector
;
7374 struct drm_device
*dev
= encoder
->dev
;
7375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7377 connector
= drm_select_eld(encoder
, mode
);
7381 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7383 drm_get_connector_name(connector
),
7384 connector
->encoder
->base
.id
,
7385 drm_get_encoder_name(connector
->encoder
));
7387 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
7389 if (dev_priv
->display
.write_eld
)
7390 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
7393 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7395 struct drm_device
*dev
= crtc
->dev
;
7396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7397 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7398 bool visible
= base
!= 0;
7401 if (intel_crtc
->cursor_visible
== visible
)
7404 cntl
= I915_READ(_CURACNTR
);
7406 /* On these chipsets we can only modify the base whilst
7407 * the cursor is disabled.
7409 I915_WRITE(_CURABASE
, base
);
7411 cntl
&= ~(CURSOR_FORMAT_MASK
);
7412 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7413 cntl
|= CURSOR_ENABLE
|
7414 CURSOR_GAMMA_ENABLE
|
7417 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
7418 I915_WRITE(_CURACNTR
, cntl
);
7420 intel_crtc
->cursor_visible
= visible
;
7423 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7425 struct drm_device
*dev
= crtc
->dev
;
7426 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7427 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7428 int pipe
= intel_crtc
->pipe
;
7429 bool visible
= base
!= 0;
7431 if (intel_crtc
->cursor_visible
!= visible
) {
7432 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
7434 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
7435 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7436 cntl
|= pipe
<< 28; /* Connect to correct pipe */
7438 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7439 cntl
|= CURSOR_MODE_DISABLE
;
7441 I915_WRITE(CURCNTR(pipe
), cntl
);
7443 intel_crtc
->cursor_visible
= visible
;
7445 /* and commit changes on next vblank */
7446 POSTING_READ(CURCNTR(pipe
));
7447 I915_WRITE(CURBASE(pipe
), base
);
7448 POSTING_READ(CURBASE(pipe
));
7451 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
7453 struct drm_device
*dev
= crtc
->dev
;
7454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7455 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7456 int pipe
= intel_crtc
->pipe
;
7457 bool visible
= base
!= 0;
7459 if (intel_crtc
->cursor_visible
!= visible
) {
7460 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
7462 cntl
&= ~CURSOR_MODE
;
7463 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
7465 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
7466 cntl
|= CURSOR_MODE_DISABLE
;
7468 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7469 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
7470 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
7472 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
7474 intel_crtc
->cursor_visible
= visible
;
7476 /* and commit changes on next vblank */
7477 POSTING_READ(CURCNTR_IVB(pipe
));
7478 I915_WRITE(CURBASE_IVB(pipe
), base
);
7479 POSTING_READ(CURBASE_IVB(pipe
));
7482 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7483 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
7486 struct drm_device
*dev
= crtc
->dev
;
7487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7488 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7489 int pipe
= intel_crtc
->pipe
;
7490 int x
= intel_crtc
->cursor_x
;
7491 int y
= intel_crtc
->cursor_y
;
7492 u32 base
= 0, pos
= 0;
7496 base
= intel_crtc
->cursor_addr
;
7498 if (x
>= intel_crtc
->config
.pipe_src_w
)
7501 if (y
>= intel_crtc
->config
.pipe_src_h
)
7505 if (x
+ intel_crtc
->cursor_width
<= 0)
7508 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
7511 pos
|= x
<< CURSOR_X_SHIFT
;
7514 if (y
+ intel_crtc
->cursor_height
<= 0)
7517 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
7520 pos
|= y
<< CURSOR_Y_SHIFT
;
7522 visible
= base
!= 0;
7523 if (!visible
&& !intel_crtc
->cursor_visible
)
7526 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7527 I915_WRITE(CURPOS_IVB(pipe
), pos
);
7528 ivb_update_cursor(crtc
, base
);
7530 I915_WRITE(CURPOS(pipe
), pos
);
7531 if (IS_845G(dev
) || IS_I865G(dev
))
7532 i845_update_cursor(crtc
, base
);
7534 i9xx_update_cursor(crtc
, base
);
7538 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
7539 struct drm_file
*file
,
7541 uint32_t width
, uint32_t height
)
7543 struct drm_device
*dev
= crtc
->dev
;
7544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7545 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7546 struct drm_i915_gem_object
*obj
;
7550 /* if we want to turn off the cursor ignore width and height */
7552 DRM_DEBUG_KMS("cursor off\n");
7555 mutex_lock(&dev
->struct_mutex
);
7559 /* Currently we only support 64x64 cursors */
7560 if (width
!= 64 || height
!= 64) {
7561 DRM_ERROR("we currently only support 64x64 cursors\n");
7565 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7566 if (&obj
->base
== NULL
)
7569 if (obj
->base
.size
< width
* height
* 4) {
7570 DRM_ERROR("buffer is to small\n");
7575 /* we only need to pin inside GTT if cursor is non-phy */
7576 mutex_lock(&dev
->struct_mutex
);
7577 if (!dev_priv
->info
->cursor_needs_physical
) {
7580 if (obj
->tiling_mode
) {
7581 DRM_ERROR("cursor cannot be tiled\n");
7586 /* Note that the w/a also requires 2 PTE of padding following
7587 * the bo. We currently fill all unused PTE with the shadow
7588 * page and so we should always have valid PTE following the
7589 * cursor preventing the VT-d warning.
7592 if (need_vtd_wa(dev
))
7593 alignment
= 64*1024;
7595 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7597 DRM_ERROR("failed to move cursor bo into the GTT\n");
7601 ret
= i915_gem_object_put_fence(obj
);
7603 DRM_ERROR("failed to release fence for cursor");
7607 addr
= i915_gem_obj_ggtt_offset(obj
);
7609 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7610 ret
= i915_gem_attach_phys_object(dev
, obj
,
7611 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7614 DRM_ERROR("failed to attach phys object\n");
7617 addr
= obj
->phys_obj
->handle
->busaddr
;
7621 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7624 if (intel_crtc
->cursor_bo
) {
7625 if (dev_priv
->info
->cursor_needs_physical
) {
7626 if (intel_crtc
->cursor_bo
!= obj
)
7627 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7629 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7630 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7633 mutex_unlock(&dev
->struct_mutex
);
7635 intel_crtc
->cursor_addr
= addr
;
7636 intel_crtc
->cursor_bo
= obj
;
7637 intel_crtc
->cursor_width
= width
;
7638 intel_crtc
->cursor_height
= height
;
7640 if (intel_crtc
->active
)
7641 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7645 i915_gem_object_unpin_from_display_plane(obj
);
7647 mutex_unlock(&dev
->struct_mutex
);
7649 drm_gem_object_unreference_unlocked(&obj
->base
);
7653 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7657 intel_crtc
->cursor_x
= clamp_t(int, x
, SHRT_MIN
, SHRT_MAX
);
7658 intel_crtc
->cursor_y
= clamp_t(int, y
, SHRT_MIN
, SHRT_MAX
);
7660 if (intel_crtc
->active
)
7661 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7666 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7667 u16
*blue
, uint32_t start
, uint32_t size
)
7669 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7670 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7672 for (i
= start
; i
< end
; i
++) {
7673 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7674 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7675 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7678 intel_crtc_load_lut(crtc
);
7681 /* VESA 640x480x72Hz mode to set on the pipe */
7682 static struct drm_display_mode load_detect_mode
= {
7683 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7684 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7687 static struct drm_framebuffer
*
7688 intel_framebuffer_create(struct drm_device
*dev
,
7689 struct drm_mode_fb_cmd2
*mode_cmd
,
7690 struct drm_i915_gem_object
*obj
)
7692 struct intel_framebuffer
*intel_fb
;
7695 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7697 drm_gem_object_unreference_unlocked(&obj
->base
);
7698 return ERR_PTR(-ENOMEM
);
7701 ret
= i915_mutex_lock_interruptible(dev
);
7705 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7706 mutex_unlock(&dev
->struct_mutex
);
7710 return &intel_fb
->base
;
7712 drm_gem_object_unreference_unlocked(&obj
->base
);
7715 return ERR_PTR(ret
);
7719 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7721 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7722 return ALIGN(pitch
, 64);
7726 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7728 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7729 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7732 static struct drm_framebuffer
*
7733 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7734 struct drm_display_mode
*mode
,
7737 struct drm_i915_gem_object
*obj
;
7738 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7740 obj
= i915_gem_alloc_object(dev
,
7741 intel_framebuffer_size_for_mode(mode
, bpp
));
7743 return ERR_PTR(-ENOMEM
);
7745 mode_cmd
.width
= mode
->hdisplay
;
7746 mode_cmd
.height
= mode
->vdisplay
;
7747 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7749 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7751 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7754 static struct drm_framebuffer
*
7755 mode_fits_in_fbdev(struct drm_device
*dev
,
7756 struct drm_display_mode
*mode
)
7758 #ifdef CONFIG_DRM_I915_FBDEV
7759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7760 struct drm_i915_gem_object
*obj
;
7761 struct drm_framebuffer
*fb
;
7763 if (dev_priv
->fbdev
== NULL
)
7766 obj
= dev_priv
->fbdev
->ifb
.obj
;
7770 fb
= &dev_priv
->fbdev
->ifb
.base
;
7771 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7772 fb
->bits_per_pixel
))
7775 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7784 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7785 struct drm_display_mode
*mode
,
7786 struct intel_load_detect_pipe
*old
)
7788 struct intel_crtc
*intel_crtc
;
7789 struct intel_encoder
*intel_encoder
=
7790 intel_attached_encoder(connector
);
7791 struct drm_crtc
*possible_crtc
;
7792 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7793 struct drm_crtc
*crtc
= NULL
;
7794 struct drm_device
*dev
= encoder
->dev
;
7795 struct drm_framebuffer
*fb
;
7798 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7799 connector
->base
.id
, drm_get_connector_name(connector
),
7800 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7803 * Algorithm gets a little messy:
7805 * - if the connector already has an assigned crtc, use it (but make
7806 * sure it's on first)
7808 * - try to find the first unused crtc that can drive this connector,
7809 * and use that if we find one
7812 /* See if we already have a CRTC for this connector */
7813 if (encoder
->crtc
) {
7814 crtc
= encoder
->crtc
;
7816 mutex_lock(&crtc
->mutex
);
7818 old
->dpms_mode
= connector
->dpms
;
7819 old
->load_detect_temp
= false;
7821 /* Make sure the crtc and connector are running */
7822 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7823 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7828 /* Find an unused one (if possible) */
7829 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7831 if (!(encoder
->possible_crtcs
& (1 << i
)))
7833 if (!possible_crtc
->enabled
) {
7834 crtc
= possible_crtc
;
7840 * If we didn't find an unused CRTC, don't use any.
7843 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7847 mutex_lock(&crtc
->mutex
);
7848 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7849 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7851 intel_crtc
= to_intel_crtc(crtc
);
7852 old
->dpms_mode
= connector
->dpms
;
7853 old
->load_detect_temp
= true;
7854 old
->release_fb
= NULL
;
7857 mode
= &load_detect_mode
;
7859 /* We need a framebuffer large enough to accommodate all accesses
7860 * that the plane may generate whilst we perform load detection.
7861 * We can not rely on the fbcon either being present (we get called
7862 * during its initialisation to detect all boot displays, or it may
7863 * not even exist) or that it is large enough to satisfy the
7866 fb
= mode_fits_in_fbdev(dev
, mode
);
7868 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7869 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7870 old
->release_fb
= fb
;
7872 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7874 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7875 mutex_unlock(&crtc
->mutex
);
7879 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7880 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7881 if (old
->release_fb
)
7882 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7883 mutex_unlock(&crtc
->mutex
);
7887 /* let the connector get through one full cycle before testing */
7888 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7892 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7893 struct intel_load_detect_pipe
*old
)
7895 struct intel_encoder
*intel_encoder
=
7896 intel_attached_encoder(connector
);
7897 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7898 struct drm_crtc
*crtc
= encoder
->crtc
;
7900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7901 connector
->base
.id
, drm_get_connector_name(connector
),
7902 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7904 if (old
->load_detect_temp
) {
7905 to_intel_connector(connector
)->new_encoder
= NULL
;
7906 intel_encoder
->new_crtc
= NULL
;
7907 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7909 if (old
->release_fb
) {
7910 drm_framebuffer_unregister_private(old
->release_fb
);
7911 drm_framebuffer_unreference(old
->release_fb
);
7914 mutex_unlock(&crtc
->mutex
);
7918 /* Switch crtc and encoder back off if necessary */
7919 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7920 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7922 mutex_unlock(&crtc
->mutex
);
7925 static int i9xx_pll_refclk(struct drm_device
*dev
,
7926 const struct intel_crtc_config
*pipe_config
)
7928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7929 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7931 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7932 return dev_priv
->vbt
.lvds_ssc_freq
;
7933 else if (HAS_PCH_SPLIT(dev
))
7935 else if (!IS_GEN2(dev
))
7941 /* Returns the clock of the currently programmed mode of the given pipe. */
7942 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7943 struct intel_crtc_config
*pipe_config
)
7945 struct drm_device
*dev
= crtc
->base
.dev
;
7946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7947 int pipe
= pipe_config
->cpu_transcoder
;
7948 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7950 intel_clock_t clock
;
7951 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7953 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7954 fp
= pipe_config
->dpll_hw_state
.fp0
;
7956 fp
= pipe_config
->dpll_hw_state
.fp1
;
7958 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7959 if (IS_PINEVIEW(dev
)) {
7960 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7961 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7963 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7964 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7967 if (!IS_GEN2(dev
)) {
7968 if (IS_PINEVIEW(dev
))
7969 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7970 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7972 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7973 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7975 switch (dpll
& DPLL_MODE_MASK
) {
7976 case DPLLB_MODE_DAC_SERIAL
:
7977 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7980 case DPLLB_MODE_LVDS
:
7981 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7985 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7986 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7990 if (IS_PINEVIEW(dev
))
7991 pineview_clock(refclk
, &clock
);
7993 i9xx_clock(refclk
, &clock
);
7995 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
7996 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
7999 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8000 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8002 if (lvds
& LVDS_CLKB_POWER_UP
)
8007 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8010 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8011 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8013 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8019 i9xx_clock(refclk
, &clock
);
8023 * This value includes pixel_multiplier. We will use
8024 * port_clock to compute adjusted_mode.crtc_clock in the
8025 * encoder's get_config() function.
8027 pipe_config
->port_clock
= clock
.dot
;
8030 int intel_dotclock_calculate(int link_freq
,
8031 const struct intel_link_m_n
*m_n
)
8034 * The calculation for the data clock is:
8035 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8036 * But we want to avoid losing precison if possible, so:
8037 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8039 * and the link clock is simpler:
8040 * link_clock = (m * link_clock) / n
8046 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8049 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8050 struct intel_crtc_config
*pipe_config
)
8052 struct drm_device
*dev
= crtc
->base
.dev
;
8054 /* read out port_clock from the DPLL */
8055 i9xx_crtc_clock_get(crtc
, pipe_config
);
8058 * This value does not include pixel_multiplier.
8059 * We will check that port_clock and adjusted_mode.crtc_clock
8060 * agree once we know their relationship in the encoder's
8061 * get_config() function.
8063 pipe_config
->adjusted_mode
.crtc_clock
=
8064 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8065 &pipe_config
->fdi_m_n
);
8068 /** Returns the currently programmed mode of the given pipe. */
8069 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8070 struct drm_crtc
*crtc
)
8072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8073 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8074 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8075 struct drm_display_mode
*mode
;
8076 struct intel_crtc_config pipe_config
;
8077 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8078 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8079 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8080 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8081 enum pipe pipe
= intel_crtc
->pipe
;
8083 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8088 * Construct a pipe_config sufficient for getting the clock info
8089 * back out of crtc_clock_get.
8091 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8092 * to use a real value here instead.
8094 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8095 pipe_config
.pixel_multiplier
= 1;
8096 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8097 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8098 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8099 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8101 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8102 mode
->hdisplay
= (htot
& 0xffff) + 1;
8103 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8104 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8105 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8106 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8107 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8108 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8109 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8111 drm_mode_set_name(mode
);
8116 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
8118 struct drm_device
*dev
= crtc
->dev
;
8119 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8120 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8121 int pipe
= intel_crtc
->pipe
;
8122 int dpll_reg
= DPLL(pipe
);
8125 if (HAS_PCH_SPLIT(dev
))
8128 if (!dev_priv
->lvds_downclock_avail
)
8131 dpll
= I915_READ(dpll_reg
);
8132 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8133 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8135 assert_panel_unlocked(dev_priv
, pipe
);
8137 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8138 I915_WRITE(dpll_reg
, dpll
);
8139 intel_wait_for_vblank(dev
, pipe
);
8141 dpll
= I915_READ(dpll_reg
);
8142 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8143 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8147 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8149 struct drm_device
*dev
= crtc
->dev
;
8150 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8151 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8153 if (HAS_PCH_SPLIT(dev
))
8156 if (!dev_priv
->lvds_downclock_avail
)
8160 * Since this is called by a timer, we should never get here in
8163 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8164 int pipe
= intel_crtc
->pipe
;
8165 int dpll_reg
= DPLL(pipe
);
8168 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8170 assert_panel_unlocked(dev_priv
, pipe
);
8172 dpll
= I915_READ(dpll_reg
);
8173 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8174 I915_WRITE(dpll_reg
, dpll
);
8175 intel_wait_for_vblank(dev
, pipe
);
8176 dpll
= I915_READ(dpll_reg
);
8177 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8178 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8183 void intel_mark_busy(struct drm_device
*dev
)
8185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8187 hsw_package_c8_gpu_busy(dev_priv
);
8188 i915_update_gfx_val(dev_priv
);
8191 void intel_mark_idle(struct drm_device
*dev
)
8193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8194 struct drm_crtc
*crtc
;
8196 hsw_package_c8_gpu_idle(dev_priv
);
8198 if (!i915_powersave
)
8201 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8205 intel_decrease_pllclock(crtc
);
8208 if (dev_priv
->info
->gen
>= 6)
8209 gen6_rps_idle(dev
->dev_private
);
8212 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
8213 struct intel_ring_buffer
*ring
)
8215 struct drm_device
*dev
= obj
->base
.dev
;
8216 struct drm_crtc
*crtc
;
8218 if (!i915_powersave
)
8221 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8225 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
8228 intel_increase_pllclock(crtc
);
8229 if (ring
&& intel_fbc_enabled(dev
))
8230 ring
->fbc_dirty
= true;
8234 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
8236 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8237 struct drm_device
*dev
= crtc
->dev
;
8238 struct intel_unpin_work
*work
;
8239 unsigned long flags
;
8241 spin_lock_irqsave(&dev
->event_lock
, flags
);
8242 work
= intel_crtc
->unpin_work
;
8243 intel_crtc
->unpin_work
= NULL
;
8244 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8247 cancel_work_sync(&work
->work
);
8251 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
8253 drm_crtc_cleanup(crtc
);
8258 static void intel_unpin_work_fn(struct work_struct
*__work
)
8260 struct intel_unpin_work
*work
=
8261 container_of(__work
, struct intel_unpin_work
, work
);
8262 struct drm_device
*dev
= work
->crtc
->dev
;
8264 mutex_lock(&dev
->struct_mutex
);
8265 intel_unpin_fb_obj(work
->old_fb_obj
);
8266 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
8267 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8269 intel_update_fbc(dev
);
8270 mutex_unlock(&dev
->struct_mutex
);
8272 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
8273 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
8278 static void do_intel_finish_page_flip(struct drm_device
*dev
,
8279 struct drm_crtc
*crtc
)
8281 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8282 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8283 struct intel_unpin_work
*work
;
8284 unsigned long flags
;
8286 /* Ignore early vblank irqs */
8287 if (intel_crtc
== NULL
)
8290 spin_lock_irqsave(&dev
->event_lock
, flags
);
8291 work
= intel_crtc
->unpin_work
;
8293 /* Ensure we don't miss a work->pending update ... */
8296 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
8297 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8301 /* and that the unpin work is consistent wrt ->pending. */
8304 intel_crtc
->unpin_work
= NULL
;
8307 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
8309 drm_vblank_put(dev
, intel_crtc
->pipe
);
8311 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8313 wake_up_all(&dev_priv
->pending_flip_queue
);
8315 queue_work(dev_priv
->wq
, &work
->work
);
8317 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
8320 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
8322 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8323 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
8325 do_intel_finish_page_flip(dev
, crtc
);
8328 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
8330 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8331 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
8333 do_intel_finish_page_flip(dev
, crtc
);
8336 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
8338 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8339 struct intel_crtc
*intel_crtc
=
8340 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
8341 unsigned long flags
;
8343 /* NB: An MMIO update of the plane base pointer will also
8344 * generate a page-flip completion irq, i.e. every modeset
8345 * is also accompanied by a spurious intel_prepare_page_flip().
8347 spin_lock_irqsave(&dev
->event_lock
, flags
);
8348 if (intel_crtc
->unpin_work
)
8349 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
8350 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8353 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
8355 /* Ensure that the work item is consistent when activating it ... */
8357 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
8358 /* and that it is marked active as soon as the irq could fire. */
8362 static int intel_gen2_queue_flip(struct drm_device
*dev
,
8363 struct drm_crtc
*crtc
,
8364 struct drm_framebuffer
*fb
,
8365 struct drm_i915_gem_object
*obj
,
8368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8371 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8374 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8378 ret
= intel_ring_begin(ring
, 6);
8382 /* Can't queue multiple flips, so wait for the previous
8383 * one to finish before executing the next.
8385 if (intel_crtc
->plane
)
8386 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
8388 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
8389 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
8390 intel_ring_emit(ring
, MI_NOOP
);
8391 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8392 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8393 intel_ring_emit(ring
, fb
->pitches
[0]);
8394 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8395 intel_ring_emit(ring
, 0); /* aux display base address, unused */
8397 intel_mark_page_flip_active(intel_crtc
);
8398 __intel_ring_advance(ring
);
8402 intel_unpin_fb_obj(obj
);
8407 static int intel_gen3_queue_flip(struct drm_device
*dev
,
8408 struct drm_crtc
*crtc
,
8409 struct drm_framebuffer
*fb
,
8410 struct drm_i915_gem_object
*obj
,
8413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8416 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8419 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8423 ret
= intel_ring_begin(ring
, 6);
8427 if (intel_crtc
->plane
)
8428 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
8430 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
8431 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
8432 intel_ring_emit(ring
, MI_NOOP
);
8433 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
8434 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8435 intel_ring_emit(ring
, fb
->pitches
[0]);
8436 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8437 intel_ring_emit(ring
, MI_NOOP
);
8439 intel_mark_page_flip_active(intel_crtc
);
8440 __intel_ring_advance(ring
);
8444 intel_unpin_fb_obj(obj
);
8449 static int intel_gen4_queue_flip(struct drm_device
*dev
,
8450 struct drm_crtc
*crtc
,
8451 struct drm_framebuffer
*fb
,
8452 struct drm_i915_gem_object
*obj
,
8455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8456 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8457 uint32_t pf
, pipesrc
;
8458 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8461 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8465 ret
= intel_ring_begin(ring
, 4);
8469 /* i965+ uses the linear or tiled offsets from the
8470 * Display Registers (which do not change across a page-flip)
8471 * so we need only reprogram the base address.
8473 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8474 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8475 intel_ring_emit(ring
, fb
->pitches
[0]);
8476 intel_ring_emit(ring
,
8477 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
8480 /* XXX Enabling the panel-fitter across page-flip is so far
8481 * untested on non-native modes, so ignore it for now.
8482 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8485 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8486 intel_ring_emit(ring
, pf
| pipesrc
);
8488 intel_mark_page_flip_active(intel_crtc
);
8489 __intel_ring_advance(ring
);
8493 intel_unpin_fb_obj(obj
);
8498 static int intel_gen6_queue_flip(struct drm_device
*dev
,
8499 struct drm_crtc
*crtc
,
8500 struct drm_framebuffer
*fb
,
8501 struct drm_i915_gem_object
*obj
,
8504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8505 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8506 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
8507 uint32_t pf
, pipesrc
;
8510 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8514 ret
= intel_ring_begin(ring
, 4);
8518 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
8519 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
8520 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
8521 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8523 /* Contrary to the suggestions in the documentation,
8524 * "Enable Panel Fitter" does not seem to be required when page
8525 * flipping with a non-native mode, and worse causes a normal
8527 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8530 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
8531 intel_ring_emit(ring
, pf
| pipesrc
);
8533 intel_mark_page_flip_active(intel_crtc
);
8534 __intel_ring_advance(ring
);
8538 intel_unpin_fb_obj(obj
);
8543 static int intel_gen7_queue_flip(struct drm_device
*dev
,
8544 struct drm_crtc
*crtc
,
8545 struct drm_framebuffer
*fb
,
8546 struct drm_i915_gem_object
*obj
,
8549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8550 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8551 struct intel_ring_buffer
*ring
;
8552 uint32_t plane_bit
= 0;
8556 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
8557 ring
= &dev_priv
->ring
[BCS
];
8559 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8563 switch(intel_crtc
->plane
) {
8565 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
8568 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
8571 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
8574 WARN_ONCE(1, "unknown plane in flip command\n");
8580 if (ring
->id
== RCS
)
8583 ret
= intel_ring_begin(ring
, len
);
8587 /* Unmask the flip-done completion message. Note that the bspec says that
8588 * we should do this for both the BCS and RCS, and that we must not unmask
8589 * more than one flip event at any time (or ensure that one flip message
8590 * can be sent by waiting for flip-done prior to queueing new flips).
8591 * Experimentation says that BCS works despite DERRMR masking all
8592 * flip-done completion events and that unmasking all planes at once
8593 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8594 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8596 if (ring
->id
== RCS
) {
8597 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8598 intel_ring_emit(ring
, DERRMR
);
8599 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8600 DERRMR_PIPEB_PRI_FLIP_DONE
|
8601 DERRMR_PIPEC_PRI_FLIP_DONE
));
8602 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
8603 MI_SRM_LRM_GLOBAL_GTT
);
8604 intel_ring_emit(ring
, DERRMR
);
8605 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8608 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8609 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8610 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8611 intel_ring_emit(ring
, (MI_NOOP
));
8613 intel_mark_page_flip_active(intel_crtc
);
8614 __intel_ring_advance(ring
);
8618 intel_unpin_fb_obj(obj
);
8623 static int intel_default_queue_flip(struct drm_device
*dev
,
8624 struct drm_crtc
*crtc
,
8625 struct drm_framebuffer
*fb
,
8626 struct drm_i915_gem_object
*obj
,
8632 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8633 struct drm_framebuffer
*fb
,
8634 struct drm_pending_vblank_event
*event
,
8635 uint32_t page_flip_flags
)
8637 struct drm_device
*dev
= crtc
->dev
;
8638 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8639 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8640 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8641 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8642 struct intel_unpin_work
*work
;
8643 unsigned long flags
;
8646 /* Can't change pixel format via MI display flips. */
8647 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8651 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8652 * Note that pitch changes could also affect these register.
8654 if (INTEL_INFO(dev
)->gen
> 3 &&
8655 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8656 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8659 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8663 work
->event
= event
;
8665 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8666 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8668 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8672 /* We borrow the event spin lock for protecting unpin_work */
8673 spin_lock_irqsave(&dev
->event_lock
, flags
);
8674 if (intel_crtc
->unpin_work
) {
8675 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8677 drm_vblank_put(dev
, intel_crtc
->pipe
);
8679 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8682 intel_crtc
->unpin_work
= work
;
8683 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8685 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8686 flush_workqueue(dev_priv
->wq
);
8688 ret
= i915_mutex_lock_interruptible(dev
);
8692 /* Reference the objects for the scheduled work. */
8693 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8694 drm_gem_object_reference(&obj
->base
);
8698 work
->pending_flip_obj
= obj
;
8700 work
->enable_stall_check
= true;
8702 atomic_inc(&intel_crtc
->unpin_work_count
);
8703 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8705 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8707 goto cleanup_pending
;
8709 intel_disable_fbc(dev
);
8710 intel_mark_fb_busy(obj
, NULL
);
8711 mutex_unlock(&dev
->struct_mutex
);
8713 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8718 atomic_dec(&intel_crtc
->unpin_work_count
);
8720 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8721 drm_gem_object_unreference(&obj
->base
);
8722 mutex_unlock(&dev
->struct_mutex
);
8725 spin_lock_irqsave(&dev
->event_lock
, flags
);
8726 intel_crtc
->unpin_work
= NULL
;
8727 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8729 drm_vblank_put(dev
, intel_crtc
->pipe
);
8736 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8737 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8738 .load_lut
= intel_crtc_load_lut
,
8741 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8742 struct drm_crtc
*crtc
)
8744 struct drm_device
*dev
;
8745 struct drm_crtc
*tmp
;
8748 WARN(!crtc
, "checking null crtc?\n");
8752 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8758 if (encoder
->possible_crtcs
& crtc_mask
)
8764 * intel_modeset_update_staged_output_state
8766 * Updates the staged output configuration state, e.g. after we've read out the
8769 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8771 struct intel_crtc
*crtc
;
8772 struct intel_encoder
*encoder
;
8773 struct intel_connector
*connector
;
8775 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8777 connector
->new_encoder
=
8778 to_intel_encoder(connector
->base
.encoder
);
8781 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8784 to_intel_crtc(encoder
->base
.crtc
);
8787 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8789 crtc
->new_enabled
= crtc
->base
.enabled
;
8794 * intel_modeset_commit_output_state
8796 * This function copies the stage display pipe configuration to the real one.
8798 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8800 struct intel_crtc
*crtc
;
8801 struct intel_encoder
*encoder
;
8802 struct intel_connector
*connector
;
8804 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8806 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8809 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8811 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8814 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8816 crtc
->base
.enabled
= crtc
->new_enabled
;
8821 connected_sink_compute_bpp(struct intel_connector
* connector
,
8822 struct intel_crtc_config
*pipe_config
)
8824 int bpp
= pipe_config
->pipe_bpp
;
8826 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8827 connector
->base
.base
.id
,
8828 drm_get_connector_name(&connector
->base
));
8830 /* Don't use an invalid EDID bpc value */
8831 if (connector
->base
.display_info
.bpc
&&
8832 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8833 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8834 bpp
, connector
->base
.display_info
.bpc
*3);
8835 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8838 /* Clamp bpp to 8 on screens without EDID 1.4 */
8839 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8840 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8842 pipe_config
->pipe_bpp
= 24;
8847 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8848 struct drm_framebuffer
*fb
,
8849 struct intel_crtc_config
*pipe_config
)
8851 struct drm_device
*dev
= crtc
->base
.dev
;
8852 struct intel_connector
*connector
;
8855 switch (fb
->pixel_format
) {
8857 bpp
= 8*3; /* since we go through a colormap */
8859 case DRM_FORMAT_XRGB1555
:
8860 case DRM_FORMAT_ARGB1555
:
8861 /* checked in intel_framebuffer_init already */
8862 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8864 case DRM_FORMAT_RGB565
:
8865 bpp
= 6*3; /* min is 18bpp */
8867 case DRM_FORMAT_XBGR8888
:
8868 case DRM_FORMAT_ABGR8888
:
8869 /* checked in intel_framebuffer_init already */
8870 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8872 case DRM_FORMAT_XRGB8888
:
8873 case DRM_FORMAT_ARGB8888
:
8876 case DRM_FORMAT_XRGB2101010
:
8877 case DRM_FORMAT_ARGB2101010
:
8878 case DRM_FORMAT_XBGR2101010
:
8879 case DRM_FORMAT_ABGR2101010
:
8880 /* checked in intel_framebuffer_init already */
8881 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8885 /* TODO: gen4+ supports 16 bpc floating point, too. */
8887 DRM_DEBUG_KMS("unsupported depth\n");
8891 pipe_config
->pipe_bpp
= bpp
;
8893 /* Clamp display bpp to EDID value */
8894 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8896 if (!connector
->new_encoder
||
8897 connector
->new_encoder
->new_crtc
!= crtc
)
8900 connected_sink_compute_bpp(connector
, pipe_config
);
8906 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8908 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8909 "type: 0x%x flags: 0x%x\n",
8911 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8912 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8913 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8914 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8917 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8918 struct intel_crtc_config
*pipe_config
,
8919 const char *context
)
8921 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8922 context
, pipe_name(crtc
->pipe
));
8924 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8925 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8926 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8927 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8928 pipe_config
->has_pch_encoder
,
8929 pipe_config
->fdi_lanes
,
8930 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8931 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8932 pipe_config
->fdi_m_n
.tu
);
8933 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8934 pipe_config
->has_dp_encoder
,
8935 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8936 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8937 pipe_config
->dp_m_n
.tu
);
8938 DRM_DEBUG_KMS("requested mode:\n");
8939 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8940 DRM_DEBUG_KMS("adjusted mode:\n");
8941 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8942 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8943 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8944 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8945 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8946 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8947 pipe_config
->gmch_pfit
.control
,
8948 pipe_config
->gmch_pfit
.pgm_ratios
,
8949 pipe_config
->gmch_pfit
.lvds_border_bits
);
8950 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8951 pipe_config
->pch_pfit
.pos
,
8952 pipe_config
->pch_pfit
.size
,
8953 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8954 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8955 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8958 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8960 int num_encoders
= 0;
8961 bool uncloneable_encoders
= false;
8962 struct intel_encoder
*encoder
;
8964 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8966 if (&encoder
->new_crtc
->base
!= crtc
)
8970 if (!encoder
->cloneable
)
8971 uncloneable_encoders
= true;
8974 return !(num_encoders
> 1 && uncloneable_encoders
);
8977 static struct intel_crtc_config
*
8978 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8979 struct drm_framebuffer
*fb
,
8980 struct drm_display_mode
*mode
)
8982 struct drm_device
*dev
= crtc
->dev
;
8983 struct intel_encoder
*encoder
;
8984 struct intel_crtc_config
*pipe_config
;
8985 int plane_bpp
, ret
= -EINVAL
;
8988 if (!check_encoder_cloning(crtc
)) {
8989 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8990 return ERR_PTR(-EINVAL
);
8993 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8995 return ERR_PTR(-ENOMEM
);
8997 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8998 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
9000 pipe_config
->cpu_transcoder
=
9001 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
9002 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9005 * Sanitize sync polarity flags based on requested ones. If neither
9006 * positive or negative polarity is requested, treat this as meaning
9007 * negative polarity.
9009 if (!(pipe_config
->adjusted_mode
.flags
&
9010 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
9011 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
9013 if (!(pipe_config
->adjusted_mode
.flags
&
9014 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
9015 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
9017 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9018 * plane pixel format and any sink constraints into account. Returns the
9019 * source plane bpp so that dithering can be selected on mismatches
9020 * after encoders and crtc also have had their say. */
9021 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
9027 * Determine the real pipe dimensions. Note that stereo modes can
9028 * increase the actual pipe size due to the frame doubling and
9029 * insertion of additional space for blanks between the frame. This
9030 * is stored in the crtc timings. We use the requested mode to do this
9031 * computation to clearly distinguish it from the adjusted mode, which
9032 * can be changed by the connectors in the below retry loop.
9034 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
9035 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
9036 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
9039 /* Ensure the port clock defaults are reset when retrying. */
9040 pipe_config
->port_clock
= 0;
9041 pipe_config
->pixel_multiplier
= 1;
9043 /* Fill in default crtc timings, allow encoders to overwrite them. */
9044 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
9046 /* Pass our mode to the connectors and the CRTC to give them a chance to
9047 * adjust it according to limitations or connector properties, and also
9048 * a chance to reject the mode entirely.
9050 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9053 if (&encoder
->new_crtc
->base
!= crtc
)
9056 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
9057 DRM_DEBUG_KMS("Encoder config failure\n");
9062 /* Set default port clock if not overwritten by the encoder. Needs to be
9063 * done afterwards in case the encoder adjusts the mode. */
9064 if (!pipe_config
->port_clock
)
9065 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
9066 * pipe_config
->pixel_multiplier
;
9068 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
9070 DRM_DEBUG_KMS("CRTC fixup failed\n");
9075 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
9080 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9085 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
9086 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9087 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
9092 return ERR_PTR(ret
);
9095 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9096 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9098 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
9099 unsigned *prepare_pipes
, unsigned *disable_pipes
)
9101 struct intel_crtc
*intel_crtc
;
9102 struct drm_device
*dev
= crtc
->dev
;
9103 struct intel_encoder
*encoder
;
9104 struct intel_connector
*connector
;
9105 struct drm_crtc
*tmp_crtc
;
9107 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
9109 /* Check which crtcs have changed outputs connected to them, these need
9110 * to be part of the prepare_pipes mask. We don't (yet) support global
9111 * modeset across multiple crtcs, so modeset_pipes will only have one
9112 * bit set at most. */
9113 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9115 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
9118 if (connector
->base
.encoder
) {
9119 tmp_crtc
= connector
->base
.encoder
->crtc
;
9121 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
9124 if (connector
->new_encoder
)
9126 1 << connector
->new_encoder
->new_crtc
->pipe
;
9129 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9131 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
9134 if (encoder
->base
.crtc
) {
9135 tmp_crtc
= encoder
->base
.crtc
;
9137 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
9140 if (encoder
->new_crtc
)
9141 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
9144 /* Check for pipes that will be enabled/disabled ... */
9145 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
9147 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
9150 if (!intel_crtc
->new_enabled
)
9151 *disable_pipes
|= 1 << intel_crtc
->pipe
;
9153 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
9157 /* set_mode is also used to update properties on life display pipes. */
9158 intel_crtc
= to_intel_crtc(crtc
);
9159 if (intel_crtc
->new_enabled
)
9160 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
9163 * For simplicity do a full modeset on any pipe where the output routing
9164 * changed. We could be more clever, but that would require us to be
9165 * more careful with calling the relevant encoder->mode_set functions.
9168 *modeset_pipes
= *prepare_pipes
;
9170 /* ... and mask these out. */
9171 *modeset_pipes
&= ~(*disable_pipes
);
9172 *prepare_pipes
&= ~(*disable_pipes
);
9175 * HACK: We don't (yet) fully support global modesets. intel_set_config
9176 * obies this rule, but the modeset restore mode of
9177 * intel_modeset_setup_hw_state does not.
9179 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
9180 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
9182 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9183 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
9186 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
9188 struct drm_encoder
*encoder
;
9189 struct drm_device
*dev
= crtc
->dev
;
9191 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
9192 if (encoder
->crtc
== crtc
)
9199 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
9201 struct intel_encoder
*intel_encoder
;
9202 struct intel_crtc
*intel_crtc
;
9203 struct drm_connector
*connector
;
9205 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
9207 if (!intel_encoder
->base
.crtc
)
9210 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
9212 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
9213 intel_encoder
->connectors_active
= false;
9216 intel_modeset_commit_output_state(dev
);
9218 /* Double check state. */
9219 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
9221 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
9222 WARN_ON(intel_crtc
->new_config
!= &intel_crtc
->config
);
9225 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9226 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
9229 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
9231 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
9232 struct drm_property
*dpms_property
=
9233 dev
->mode_config
.dpms_property
;
9235 connector
->dpms
= DRM_MODE_DPMS_ON
;
9236 drm_object_property_set_value(&connector
->base
,
9240 intel_encoder
= to_intel_encoder(connector
->encoder
);
9241 intel_encoder
->connectors_active
= true;
9247 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
9251 if (clock1
== clock2
)
9254 if (!clock1
|| !clock2
)
9257 diff
= abs(clock1
- clock2
);
9259 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
9265 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9266 list_for_each_entry((intel_crtc), \
9267 &(dev)->mode_config.crtc_list, \
9269 if (mask & (1 <<(intel_crtc)->pipe))
9272 intel_pipe_config_compare(struct drm_device
*dev
,
9273 struct intel_crtc_config
*current_config
,
9274 struct intel_crtc_config
*pipe_config
)
9276 #define PIPE_CONF_CHECK_X(name) \
9277 if (current_config->name != pipe_config->name) { \
9278 DRM_ERROR("mismatch in " #name " " \
9279 "(expected 0x%08x, found 0x%08x)\n", \
9280 current_config->name, \
9281 pipe_config->name); \
9285 #define PIPE_CONF_CHECK_I(name) \
9286 if (current_config->name != pipe_config->name) { \
9287 DRM_ERROR("mismatch in " #name " " \
9288 "(expected %i, found %i)\n", \
9289 current_config->name, \
9290 pipe_config->name); \
9294 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9295 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9296 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9297 "(expected %i, found %i)\n", \
9298 current_config->name & (mask), \
9299 pipe_config->name & (mask)); \
9303 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9304 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9305 DRM_ERROR("mismatch in " #name " " \
9306 "(expected %i, found %i)\n", \
9307 current_config->name, \
9308 pipe_config->name); \
9312 #define PIPE_CONF_QUIRK(quirk) \
9313 ((current_config->quirks | pipe_config->quirks) & (quirk))
9315 PIPE_CONF_CHECK_I(cpu_transcoder
);
9317 PIPE_CONF_CHECK_I(has_pch_encoder
);
9318 PIPE_CONF_CHECK_I(fdi_lanes
);
9319 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
9320 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
9321 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
9322 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
9323 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
9325 PIPE_CONF_CHECK_I(has_dp_encoder
);
9326 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
9327 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
9328 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
9329 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
9330 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
9332 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
9333 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
9334 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
9335 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
9336 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
9337 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
9339 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
9340 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
9341 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
9342 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
9343 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
9344 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
9346 PIPE_CONF_CHECK_I(pixel_multiplier
);
9348 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9349 DRM_MODE_FLAG_INTERLACE
);
9351 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
9352 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9353 DRM_MODE_FLAG_PHSYNC
);
9354 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9355 DRM_MODE_FLAG_NHSYNC
);
9356 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9357 DRM_MODE_FLAG_PVSYNC
);
9358 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
9359 DRM_MODE_FLAG_NVSYNC
);
9362 PIPE_CONF_CHECK_I(pipe_src_w
);
9363 PIPE_CONF_CHECK_I(pipe_src_h
);
9365 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
9366 /* pfit ratios are autocomputed by the hw on gen4+ */
9367 if (INTEL_INFO(dev
)->gen
< 4)
9368 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
9369 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
9370 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
9371 if (current_config
->pch_pfit
.enabled
) {
9372 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
9373 PIPE_CONF_CHECK_I(pch_pfit
.size
);
9376 /* BDW+ don't expose a synchronous way to read the state */
9377 if (IS_HASWELL(dev
))
9378 PIPE_CONF_CHECK_I(ips_enabled
);
9380 PIPE_CONF_CHECK_I(double_wide
);
9382 PIPE_CONF_CHECK_I(shared_dpll
);
9383 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
9384 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
9385 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
9386 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
9388 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
9389 PIPE_CONF_CHECK_I(pipe_bpp
);
9391 if (!HAS_DDI(dev
)) {
9392 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
9393 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
9396 #undef PIPE_CONF_CHECK_X
9397 #undef PIPE_CONF_CHECK_I
9398 #undef PIPE_CONF_CHECK_FLAGS
9399 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9400 #undef PIPE_CONF_QUIRK
9406 check_connector_state(struct drm_device
*dev
)
9408 struct intel_connector
*connector
;
9410 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9412 /* This also checks the encoder/connector hw state with the
9413 * ->get_hw_state callbacks. */
9414 intel_connector_check_state(connector
);
9416 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
9417 "connector's staged encoder doesn't match current encoder\n");
9422 check_encoder_state(struct drm_device
*dev
)
9424 struct intel_encoder
*encoder
;
9425 struct intel_connector
*connector
;
9427 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9429 bool enabled
= false;
9430 bool active
= false;
9431 enum pipe pipe
, tracked_pipe
;
9433 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9434 encoder
->base
.base
.id
,
9435 drm_get_encoder_name(&encoder
->base
));
9437 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
9438 "encoder's stage crtc doesn't match current crtc\n");
9439 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
9440 "encoder's active_connectors set, but no crtc\n");
9442 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9444 if (connector
->base
.encoder
!= &encoder
->base
)
9447 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
9450 WARN(!!encoder
->base
.crtc
!= enabled
,
9451 "encoder's enabled state mismatch "
9452 "(expected %i, found %i)\n",
9453 !!encoder
->base
.crtc
, enabled
);
9454 WARN(active
&& !encoder
->base
.crtc
,
9455 "active encoder with no crtc\n");
9457 WARN(encoder
->connectors_active
!= active
,
9458 "encoder's computed active state doesn't match tracked active state "
9459 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
9461 active
= encoder
->get_hw_state(encoder
, &pipe
);
9462 WARN(active
!= encoder
->connectors_active
,
9463 "encoder's hw state doesn't match sw tracking "
9464 "(expected %i, found %i)\n",
9465 encoder
->connectors_active
, active
);
9467 if (!encoder
->base
.crtc
)
9470 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
9471 WARN(active
&& pipe
!= tracked_pipe
,
9472 "active encoder's pipe doesn't match"
9473 "(expected %i, found %i)\n",
9474 tracked_pipe
, pipe
);
9480 check_crtc_state(struct drm_device
*dev
)
9482 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9483 struct intel_crtc
*crtc
;
9484 struct intel_encoder
*encoder
;
9485 struct intel_crtc_config pipe_config
;
9487 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9489 bool enabled
= false;
9490 bool active
= false;
9492 memset(&pipe_config
, 0, sizeof(pipe_config
));
9494 DRM_DEBUG_KMS("[CRTC:%d]\n",
9495 crtc
->base
.base
.id
);
9497 WARN(crtc
->active
&& !crtc
->base
.enabled
,
9498 "active crtc, but not enabled in sw tracking\n");
9500 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9502 if (encoder
->base
.crtc
!= &crtc
->base
)
9505 if (encoder
->connectors_active
)
9509 WARN(active
!= crtc
->active
,
9510 "crtc's computed active state doesn't match tracked active state "
9511 "(expected %i, found %i)\n", active
, crtc
->active
);
9512 WARN(enabled
!= crtc
->base
.enabled
,
9513 "crtc's computed enabled state doesn't match tracked enabled state "
9514 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
9516 active
= dev_priv
->display
.get_pipe_config(crtc
,
9519 /* hw state is inconsistent with the pipe A quirk */
9520 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
9521 active
= crtc
->active
;
9523 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9526 if (encoder
->base
.crtc
!= &crtc
->base
)
9528 if (encoder
->get_hw_state(encoder
, &pipe
))
9529 encoder
->get_config(encoder
, &pipe_config
);
9532 WARN(crtc
->active
!= active
,
9533 "crtc active state doesn't match with hw state "
9534 "(expected %i, found %i)\n", crtc
->active
, active
);
9537 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
9538 WARN(1, "pipe state doesn't match!\n");
9539 intel_dump_pipe_config(crtc
, &pipe_config
,
9541 intel_dump_pipe_config(crtc
, &crtc
->config
,
9548 check_shared_dpll_state(struct drm_device
*dev
)
9550 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9551 struct intel_crtc
*crtc
;
9552 struct intel_dpll_hw_state dpll_hw_state
;
9555 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9556 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
9557 int enabled_crtcs
= 0, active_crtcs
= 0;
9560 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
9562 DRM_DEBUG_KMS("%s\n", pll
->name
);
9564 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
9566 WARN(pll
->active
> pll
->refcount
,
9567 "more active pll users than references: %i vs %i\n",
9568 pll
->active
, pll
->refcount
);
9569 WARN(pll
->active
&& !pll
->on
,
9570 "pll in active use but not on in sw tracking\n");
9571 WARN(pll
->on
&& !pll
->active
,
9572 "pll in on but not on in use in sw tracking\n");
9573 WARN(pll
->on
!= active
,
9574 "pll on state mismatch (expected %i, found %i)\n",
9577 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9579 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9581 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9584 WARN(pll
->active
!= active_crtcs
,
9585 "pll active crtcs mismatch (expected %i, found %i)\n",
9586 pll
->active
, active_crtcs
);
9587 WARN(pll
->refcount
!= enabled_crtcs
,
9588 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9589 pll
->refcount
, enabled_crtcs
);
9591 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
9592 sizeof(dpll_hw_state
)),
9593 "pll hw state mismatch\n");
9598 intel_modeset_check_state(struct drm_device
*dev
)
9600 check_connector_state(dev
);
9601 check_encoder_state(dev
);
9602 check_crtc_state(dev
);
9603 check_shared_dpll_state(dev
);
9606 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9610 * FDI already provided one idea for the dotclock.
9611 * Yell if the encoder disagrees.
9613 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
9614 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9615 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
9618 static int __intel_set_mode(struct drm_crtc
*crtc
,
9619 struct drm_display_mode
*mode
,
9620 int x
, int y
, struct drm_framebuffer
*fb
)
9622 struct drm_device
*dev
= crtc
->dev
;
9623 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9624 struct drm_display_mode
*saved_mode
;
9625 struct intel_crtc_config
*pipe_config
= NULL
;
9626 struct intel_crtc
*intel_crtc
;
9627 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9630 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
9634 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9635 &prepare_pipes
, &disable_pipes
);
9637 *saved_mode
= crtc
->mode
;
9639 /* Hack: Because we don't (yet) support global modeset on multiple
9640 * crtcs, we don't keep track of the new mode for more than one crtc.
9641 * Hence simply check whether any bit is set in modeset_pipes in all the
9642 * pieces of code that are not yet converted to deal with mutliple crtcs
9643 * changing their mode at the same time. */
9644 if (modeset_pipes
) {
9645 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9646 if (IS_ERR(pipe_config
)) {
9647 ret
= PTR_ERR(pipe_config
);
9652 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9654 to_intel_crtc(crtc
)->new_config
= pipe_config
;
9658 * See if the config requires any additional preparation, e.g.
9659 * to adjust global state with pipes off. We need to do this
9660 * here so we can get the modeset_pipe updated config for the new
9661 * mode set on this crtc. For other crtcs we need to use the
9662 * adjusted_mode bits in the crtc directly.
9664 if (IS_VALLEYVIEW(dev
)) {
9665 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
9667 /* may have added more to prepare_pipes than we should */
9668 prepare_pipes
&= ~disable_pipes
;
9671 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9672 intel_crtc_disable(&intel_crtc
->base
);
9674 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9675 if (intel_crtc
->base
.enabled
)
9676 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9679 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9680 * to set it here already despite that we pass it down the callchain.
9682 if (modeset_pipes
) {
9684 /* mode_set/enable/disable functions rely on a correct pipe
9686 to_intel_crtc(crtc
)->config
= *pipe_config
;
9687 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
9690 * Calculate and store various constants which
9691 * are later needed by vblank and swap-completion
9692 * timestamping. They are derived from true hwmode.
9694 drm_calc_timestamping_constants(crtc
,
9695 &pipe_config
->adjusted_mode
);
9698 /* Only after disabling all output pipelines that will be changed can we
9699 * update the the output configuration. */
9700 intel_modeset_update_state(dev
, prepare_pipes
);
9702 if (dev_priv
->display
.modeset_global_resources
)
9703 dev_priv
->display
.modeset_global_resources(dev
);
9705 /* Set up the DPLL and any encoders state that needs to adjust or depend
9708 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9709 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9715 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9716 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9717 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9719 /* FIXME: add subpixel order */
9721 if (ret
&& crtc
->enabled
)
9722 crtc
->mode
= *saved_mode
;
9730 static int intel_set_mode(struct drm_crtc
*crtc
,
9731 struct drm_display_mode
*mode
,
9732 int x
, int y
, struct drm_framebuffer
*fb
)
9736 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9739 intel_modeset_check_state(crtc
->dev
);
9744 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9746 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9749 #undef for_each_intel_crtc_masked
9751 static void intel_set_config_free(struct intel_set_config
*config
)
9756 kfree(config
->save_connector_encoders
);
9757 kfree(config
->save_encoder_crtcs
);
9758 kfree(config
->save_crtc_enabled
);
9762 static int intel_set_config_save_state(struct drm_device
*dev
,
9763 struct intel_set_config
*config
)
9765 struct drm_crtc
*crtc
;
9766 struct drm_encoder
*encoder
;
9767 struct drm_connector
*connector
;
9770 config
->save_crtc_enabled
=
9771 kcalloc(dev
->mode_config
.num_crtc
,
9772 sizeof(bool), GFP_KERNEL
);
9773 if (!config
->save_crtc_enabled
)
9776 config
->save_encoder_crtcs
=
9777 kcalloc(dev
->mode_config
.num_encoder
,
9778 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9779 if (!config
->save_encoder_crtcs
)
9782 config
->save_connector_encoders
=
9783 kcalloc(dev
->mode_config
.num_connector
,
9784 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9785 if (!config
->save_connector_encoders
)
9788 /* Copy data. Note that driver private data is not affected.
9789 * Should anything bad happen only the expected state is
9790 * restored, not the drivers personal bookkeeping.
9793 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9794 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
9798 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9799 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9803 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9804 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9810 static void intel_set_config_restore_state(struct drm_device
*dev
,
9811 struct intel_set_config
*config
)
9813 struct intel_crtc
*crtc
;
9814 struct intel_encoder
*encoder
;
9815 struct intel_connector
*connector
;
9819 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9820 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
9824 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9826 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9830 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9831 connector
->new_encoder
=
9832 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9837 is_crtc_connector_off(struct drm_mode_set
*set
)
9841 if (set
->num_connectors
== 0)
9844 if (WARN_ON(set
->connectors
== NULL
))
9847 for (i
= 0; i
< set
->num_connectors
; i
++)
9848 if (set
->connectors
[i
]->encoder
&&
9849 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9850 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9857 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9858 struct intel_set_config
*config
)
9861 /* We should be able to check here if the fb has the same properties
9862 * and then just flip_or_move it */
9863 if (is_crtc_connector_off(set
)) {
9864 config
->mode_changed
= true;
9865 } else if (set
->crtc
->fb
!= set
->fb
) {
9866 /* If we have no fb then treat it as a full mode set */
9867 if (set
->crtc
->fb
== NULL
) {
9868 struct intel_crtc
*intel_crtc
=
9869 to_intel_crtc(set
->crtc
);
9871 if (intel_crtc
->active
&& i915_fastboot
) {
9872 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9873 config
->fb_changed
= true;
9875 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9876 config
->mode_changed
= true;
9878 } else if (set
->fb
== NULL
) {
9879 config
->mode_changed
= true;
9880 } else if (set
->fb
->pixel_format
!=
9881 set
->crtc
->fb
->pixel_format
) {
9882 config
->mode_changed
= true;
9884 config
->fb_changed
= true;
9888 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9889 config
->fb_changed
= true;
9891 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9892 DRM_DEBUG_KMS("modes are different, full mode set\n");
9893 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9894 drm_mode_debug_printmodeline(set
->mode
);
9895 config
->mode_changed
= true;
9898 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9899 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9903 intel_modeset_stage_output_state(struct drm_device
*dev
,
9904 struct drm_mode_set
*set
,
9905 struct intel_set_config
*config
)
9907 struct intel_connector
*connector
;
9908 struct intel_encoder
*encoder
;
9909 struct intel_crtc
*crtc
;
9912 /* The upper layers ensure that we either disable a crtc or have a list
9913 * of connectors. For paranoia, double-check this. */
9914 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9915 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9917 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9919 /* Otherwise traverse passed in connector list and get encoders
9921 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9922 if (set
->connectors
[ro
] == &connector
->base
) {
9923 connector
->new_encoder
= connector
->encoder
;
9928 /* If we disable the crtc, disable all its connectors. Also, if
9929 * the connector is on the changing crtc but not on the new
9930 * connector list, disable it. */
9931 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9932 connector
->base
.encoder
&&
9933 connector
->base
.encoder
->crtc
== set
->crtc
) {
9934 connector
->new_encoder
= NULL
;
9936 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9937 connector
->base
.base
.id
,
9938 drm_get_connector_name(&connector
->base
));
9942 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9943 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9944 config
->mode_changed
= true;
9947 /* connector->new_encoder is now updated for all connectors. */
9949 /* Update crtc of enabled connectors. */
9950 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9952 struct drm_crtc
*new_crtc
;
9954 if (!connector
->new_encoder
)
9957 new_crtc
= connector
->new_encoder
->base
.crtc
;
9959 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9960 if (set
->connectors
[ro
] == &connector
->base
)
9961 new_crtc
= set
->crtc
;
9964 /* Make sure the new CRTC will work with the encoder */
9965 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9969 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9971 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9972 connector
->base
.base
.id
,
9973 drm_get_connector_name(&connector
->base
),
9977 /* Check for any encoders that needs to be disabled. */
9978 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9980 int num_connectors
= 0;
9981 list_for_each_entry(connector
,
9982 &dev
->mode_config
.connector_list
,
9984 if (connector
->new_encoder
== encoder
) {
9985 WARN_ON(!connector
->new_encoder
->new_crtc
);
9990 if (num_connectors
== 0)
9991 encoder
->new_crtc
= NULL
;
9992 else if (num_connectors
> 1)
9995 /* Only now check for crtc changes so we don't miss encoders
9996 * that will be disabled. */
9997 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9998 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9999 config
->mode_changed
= true;
10002 /* Now we've also updated encoder->new_crtc for all encoders. */
10004 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10006 crtc
->new_enabled
= false;
10008 list_for_each_entry(encoder
,
10009 &dev
->mode_config
.encoder_list
,
10011 if (encoder
->new_crtc
== crtc
) {
10012 crtc
->new_enabled
= true;
10017 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
10018 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10019 crtc
->new_enabled
? "en" : "dis");
10020 config
->mode_changed
= true;
10027 static int intel_crtc_set_config(struct drm_mode_set
*set
)
10029 struct drm_device
*dev
;
10030 struct drm_mode_set save_set
;
10031 struct intel_set_config
*config
;
10035 BUG_ON(!set
->crtc
);
10036 BUG_ON(!set
->crtc
->helper_private
);
10038 /* Enforce sane interface api - has been abused by the fb helper. */
10039 BUG_ON(!set
->mode
&& set
->fb
);
10040 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
10043 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10044 set
->crtc
->base
.id
, set
->fb
->base
.id
,
10045 (int)set
->num_connectors
, set
->x
, set
->y
);
10047 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
10050 dev
= set
->crtc
->dev
;
10053 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
10057 ret
= intel_set_config_save_state(dev
, config
);
10061 save_set
.crtc
= set
->crtc
;
10062 save_set
.mode
= &set
->crtc
->mode
;
10063 save_set
.x
= set
->crtc
->x
;
10064 save_set
.y
= set
->crtc
->y
;
10065 save_set
.fb
= set
->crtc
->fb
;
10067 /* Compute whether we need a full modeset, only an fb base update or no
10068 * change at all. In the future we might also check whether only the
10069 * mode changed, e.g. for LVDS where we only change the panel fitter in
10071 intel_set_config_compute_mode_changes(set
, config
);
10073 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
10077 if (config
->mode_changed
) {
10078 ret
= intel_set_mode(set
->crtc
, set
->mode
,
10079 set
->x
, set
->y
, set
->fb
);
10080 } else if (config
->fb_changed
) {
10081 intel_crtc_wait_for_pending_flips(set
->crtc
);
10083 ret
= intel_pipe_set_base(set
->crtc
,
10084 set
->x
, set
->y
, set
->fb
);
10086 * In the fastboot case this may be our only check of the
10087 * state after boot. It would be better to only do it on
10088 * the first update, but we don't have a nice way of doing that
10089 * (and really, set_config isn't used much for high freq page
10090 * flipping, so increasing its cost here shouldn't be a big
10093 if (i915_fastboot
&& ret
== 0)
10094 intel_modeset_check_state(set
->crtc
->dev
);
10098 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10099 set
->crtc
->base
.id
, ret
);
10101 intel_set_config_restore_state(dev
, config
);
10103 /* Try to restore the config */
10104 if (config
->mode_changed
&&
10105 intel_set_mode(save_set
.crtc
, save_set
.mode
,
10106 save_set
.x
, save_set
.y
, save_set
.fb
))
10107 DRM_ERROR("failed to restore config after modeset failure\n");
10111 intel_set_config_free(config
);
10115 static const struct drm_crtc_funcs intel_crtc_funcs
= {
10116 .cursor_set
= intel_crtc_cursor_set
,
10117 .cursor_move
= intel_crtc_cursor_move
,
10118 .gamma_set
= intel_crtc_gamma_set
,
10119 .set_config
= intel_crtc_set_config
,
10120 .destroy
= intel_crtc_destroy
,
10121 .page_flip
= intel_crtc_page_flip
,
10124 static void intel_cpu_pll_init(struct drm_device
*dev
)
10127 intel_ddi_pll_init(dev
);
10130 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
10131 struct intel_shared_dpll
*pll
,
10132 struct intel_dpll_hw_state
*hw_state
)
10136 val
= I915_READ(PCH_DPLL(pll
->id
));
10137 hw_state
->dpll
= val
;
10138 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
10139 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
10141 return val
& DPLL_VCO_ENABLE
;
10144 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
10145 struct intel_shared_dpll
*pll
)
10147 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
10148 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
10151 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
10152 struct intel_shared_dpll
*pll
)
10154 /* PCH refclock must be enabled first */
10155 ibx_assert_pch_refclk_enabled(dev_priv
);
10157 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
10159 /* Wait for the clocks to stabilize. */
10160 POSTING_READ(PCH_DPLL(pll
->id
));
10163 /* The pixel multiplier can only be updated once the
10164 * DPLL is enabled and the clocks are stable.
10166 * So write it again.
10168 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
10169 POSTING_READ(PCH_DPLL(pll
->id
));
10173 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
10174 struct intel_shared_dpll
*pll
)
10176 struct drm_device
*dev
= dev_priv
->dev
;
10177 struct intel_crtc
*crtc
;
10179 /* Make sure no transcoder isn't still depending on us. */
10180 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
10181 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
10182 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
10185 I915_WRITE(PCH_DPLL(pll
->id
), 0);
10186 POSTING_READ(PCH_DPLL(pll
->id
));
10190 static char *ibx_pch_dpll_names
[] = {
10195 static void ibx_pch_dpll_init(struct drm_device
*dev
)
10197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10200 dev_priv
->num_shared_dpll
= 2;
10202 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10203 dev_priv
->shared_dplls
[i
].id
= i
;
10204 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
10205 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
10206 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
10207 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
10208 dev_priv
->shared_dplls
[i
].get_hw_state
=
10209 ibx_pch_dpll_get_hw_state
;
10213 static void intel_shared_dpll_init(struct drm_device
*dev
)
10215 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10217 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
10218 ibx_pch_dpll_init(dev
);
10220 dev_priv
->num_shared_dpll
= 0;
10222 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
10225 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
10227 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10228 struct intel_crtc
*intel_crtc
;
10231 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
10232 if (intel_crtc
== NULL
)
10235 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
10237 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
10238 for (i
= 0; i
< 256; i
++) {
10239 intel_crtc
->lut_r
[i
] = i
;
10240 intel_crtc
->lut_g
[i
] = i
;
10241 intel_crtc
->lut_b
[i
] = i
;
10245 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10246 * is hooked to plane B. Hence we want plane A feeding pipe B.
10248 intel_crtc
->pipe
= pipe
;
10249 intel_crtc
->plane
= pipe
;
10250 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
10251 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10252 intel_crtc
->plane
= !pipe
;
10255 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
10256 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
10257 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
10258 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
10260 intel_crtc
->new_config
= &intel_crtc
->config
;
10262 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
10265 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
10267 struct drm_encoder
*encoder
= connector
->base
.encoder
;
10269 WARN_ON(!mutex_is_locked(&connector
->base
.dev
->mode_config
.mutex
));
10272 return INVALID_PIPE
;
10274 return to_intel_crtc(encoder
->crtc
)->pipe
;
10277 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
10278 struct drm_file
*file
)
10280 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
10281 struct drm_mode_object
*drmmode_obj
;
10282 struct intel_crtc
*crtc
;
10284 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
10287 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
10288 DRM_MODE_OBJECT_CRTC
);
10290 if (!drmmode_obj
) {
10291 DRM_ERROR("no such CRTC id\n");
10295 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
10296 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
10301 static int intel_encoder_clones(struct intel_encoder
*encoder
)
10303 struct drm_device
*dev
= encoder
->base
.dev
;
10304 struct intel_encoder
*source_encoder
;
10305 int index_mask
= 0;
10308 list_for_each_entry(source_encoder
,
10309 &dev
->mode_config
.encoder_list
, base
.head
) {
10311 if (encoder
== source_encoder
)
10312 index_mask
|= (1 << entry
);
10314 /* Intel hw has only one MUX where enocoders could be cloned. */
10315 if (encoder
->cloneable
&& source_encoder
->cloneable
)
10316 index_mask
|= (1 << entry
);
10324 static bool has_edp_a(struct drm_device
*dev
)
10326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10328 if (!IS_MOBILE(dev
))
10331 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
10334 if (IS_GEN5(dev
) &&
10335 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
10341 const char *intel_output_name(int output
)
10343 static const char *names
[] = {
10344 [INTEL_OUTPUT_UNUSED
] = "Unused",
10345 [INTEL_OUTPUT_ANALOG
] = "Analog",
10346 [INTEL_OUTPUT_DVO
] = "DVO",
10347 [INTEL_OUTPUT_SDVO
] = "SDVO",
10348 [INTEL_OUTPUT_LVDS
] = "LVDS",
10349 [INTEL_OUTPUT_TVOUT
] = "TV",
10350 [INTEL_OUTPUT_HDMI
] = "HDMI",
10351 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
10352 [INTEL_OUTPUT_EDP
] = "eDP",
10353 [INTEL_OUTPUT_DSI
] = "DSI",
10354 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
10357 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
10360 return names
[output
];
10363 static void intel_setup_outputs(struct drm_device
*dev
)
10365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10366 struct intel_encoder
*encoder
;
10367 bool dpd_is_edp
= false;
10369 intel_lvds_init(dev
);
10372 intel_crt_init(dev
);
10374 if (HAS_DDI(dev
)) {
10377 /* Haswell uses DDI functions to detect digital outputs */
10378 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
10379 /* DDI A only supports eDP */
10381 intel_ddi_init(dev
, PORT_A
);
10383 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10385 found
= I915_READ(SFUSE_STRAP
);
10387 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
10388 intel_ddi_init(dev
, PORT_B
);
10389 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
10390 intel_ddi_init(dev
, PORT_C
);
10391 if (found
& SFUSE_STRAP_DDID_DETECTED
)
10392 intel_ddi_init(dev
, PORT_D
);
10393 } else if (HAS_PCH_SPLIT(dev
)) {
10395 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
10397 if (has_edp_a(dev
))
10398 intel_dp_init(dev
, DP_A
, PORT_A
);
10400 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
10401 /* PCH SDVOB multiplex with HDMIB */
10402 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
10404 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
10405 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
10406 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
10409 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
10410 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
10412 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
10413 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
10415 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
10416 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
10418 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
10419 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
10420 } else if (IS_VALLEYVIEW(dev
)) {
10421 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
10422 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
10424 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
10425 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
10428 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
10429 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
10431 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
10432 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
10435 intel_dsi_init(dev
);
10436 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
10437 bool found
= false;
10439 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
10440 DRM_DEBUG_KMS("probing SDVOB\n");
10441 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
10442 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
10443 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10444 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
10447 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
10448 intel_dp_init(dev
, DP_B
, PORT_B
);
10451 /* Before G4X SDVOC doesn't have its own detect register */
10453 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
10454 DRM_DEBUG_KMS("probing SDVOC\n");
10455 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
10458 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
10460 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
10461 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10462 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
10464 if (SUPPORTS_INTEGRATED_DP(dev
))
10465 intel_dp_init(dev
, DP_C
, PORT_C
);
10468 if (SUPPORTS_INTEGRATED_DP(dev
) &&
10469 (I915_READ(DP_D
) & DP_DETECTED
))
10470 intel_dp_init(dev
, DP_D
, PORT_D
);
10471 } else if (IS_GEN2(dev
))
10472 intel_dvo_init(dev
);
10474 if (SUPPORTS_TV(dev
))
10475 intel_tv_init(dev
);
10477 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
10478 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
10479 encoder
->base
.possible_clones
=
10480 intel_encoder_clones(encoder
);
10483 intel_init_pch_refclk(dev
);
10485 drm_helper_move_panel_connectors_to_head(dev
);
10488 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
10490 drm_framebuffer_cleanup(&fb
->base
);
10491 WARN_ON(!fb
->obj
->framebuffer_references
--);
10492 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
10495 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
10497 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
10499 intel_framebuffer_fini(intel_fb
);
10503 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
10504 struct drm_file
*file
,
10505 unsigned int *handle
)
10507 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
10508 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10510 return drm_gem_handle_create(file
, &obj
->base
, handle
);
10513 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
10514 .destroy
= intel_user_framebuffer_destroy
,
10515 .create_handle
= intel_user_framebuffer_create_handle
,
10518 int intel_framebuffer_init(struct drm_device
*dev
,
10519 struct intel_framebuffer
*intel_fb
,
10520 struct drm_mode_fb_cmd2
*mode_cmd
,
10521 struct drm_i915_gem_object
*obj
)
10523 int aligned_height
, tile_height
;
10527 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
10529 if (obj
->tiling_mode
== I915_TILING_Y
) {
10530 DRM_DEBUG("hardware does not support tiling Y\n");
10534 if (mode_cmd
->pitches
[0] & 63) {
10535 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10536 mode_cmd
->pitches
[0]);
10540 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
10541 pitch_limit
= 32*1024;
10542 } else if (INTEL_INFO(dev
)->gen
>= 4) {
10543 if (obj
->tiling_mode
)
10544 pitch_limit
= 16*1024;
10546 pitch_limit
= 32*1024;
10547 } else if (INTEL_INFO(dev
)->gen
>= 3) {
10548 if (obj
->tiling_mode
)
10549 pitch_limit
= 8*1024;
10551 pitch_limit
= 16*1024;
10553 /* XXX DSPC is limited to 4k tiled */
10554 pitch_limit
= 8*1024;
10556 if (mode_cmd
->pitches
[0] > pitch_limit
) {
10557 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10558 obj
->tiling_mode
? "tiled" : "linear",
10559 mode_cmd
->pitches
[0], pitch_limit
);
10563 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
10564 mode_cmd
->pitches
[0] != obj
->stride
) {
10565 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10566 mode_cmd
->pitches
[0], obj
->stride
);
10570 /* Reject formats not supported by any plane early. */
10571 switch (mode_cmd
->pixel_format
) {
10572 case DRM_FORMAT_C8
:
10573 case DRM_FORMAT_RGB565
:
10574 case DRM_FORMAT_XRGB8888
:
10575 case DRM_FORMAT_ARGB8888
:
10577 case DRM_FORMAT_XRGB1555
:
10578 case DRM_FORMAT_ARGB1555
:
10579 if (INTEL_INFO(dev
)->gen
> 3) {
10580 DRM_DEBUG("unsupported pixel format: %s\n",
10581 drm_get_format_name(mode_cmd
->pixel_format
));
10585 case DRM_FORMAT_XBGR8888
:
10586 case DRM_FORMAT_ABGR8888
:
10587 case DRM_FORMAT_XRGB2101010
:
10588 case DRM_FORMAT_ARGB2101010
:
10589 case DRM_FORMAT_XBGR2101010
:
10590 case DRM_FORMAT_ABGR2101010
:
10591 if (INTEL_INFO(dev
)->gen
< 4) {
10592 DRM_DEBUG("unsupported pixel format: %s\n",
10593 drm_get_format_name(mode_cmd
->pixel_format
));
10597 case DRM_FORMAT_YUYV
:
10598 case DRM_FORMAT_UYVY
:
10599 case DRM_FORMAT_YVYU
:
10600 case DRM_FORMAT_VYUY
:
10601 if (INTEL_INFO(dev
)->gen
< 5) {
10602 DRM_DEBUG("unsupported pixel format: %s\n",
10603 drm_get_format_name(mode_cmd
->pixel_format
));
10608 DRM_DEBUG("unsupported pixel format: %s\n",
10609 drm_get_format_name(mode_cmd
->pixel_format
));
10613 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10614 if (mode_cmd
->offsets
[0] != 0)
10617 tile_height
= IS_GEN2(dev
) ? 16 : 8;
10618 aligned_height
= ALIGN(mode_cmd
->height
,
10619 obj
->tiling_mode
? tile_height
: 1);
10620 /* FIXME drm helper for size checks (especially planar formats)? */
10621 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
10624 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
10625 intel_fb
->obj
= obj
;
10626 intel_fb
->obj
->framebuffer_references
++;
10628 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
10630 DRM_ERROR("framebuffer init failed %d\n", ret
);
10637 static struct drm_framebuffer
*
10638 intel_user_framebuffer_create(struct drm_device
*dev
,
10639 struct drm_file
*filp
,
10640 struct drm_mode_fb_cmd2
*mode_cmd
)
10642 struct drm_i915_gem_object
*obj
;
10644 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
10645 mode_cmd
->handles
[0]));
10646 if (&obj
->base
== NULL
)
10647 return ERR_PTR(-ENOENT
);
10649 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
10652 #ifndef CONFIG_DRM_I915_FBDEV
10653 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
10658 static const struct drm_mode_config_funcs intel_mode_funcs
= {
10659 .fb_create
= intel_user_framebuffer_create
,
10660 .output_poll_changed
= intel_fbdev_output_poll_changed
,
10663 /* Set up chip specific display functions */
10664 static void intel_init_display(struct drm_device
*dev
)
10666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10668 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
10669 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
10670 else if (IS_VALLEYVIEW(dev
))
10671 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
10672 else if (IS_PINEVIEW(dev
))
10673 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
10675 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
10677 if (HAS_DDI(dev
)) {
10678 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
10679 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
10680 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
10681 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
10682 dev_priv
->display
.off
= haswell_crtc_off
;
10683 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10684 } else if (HAS_PCH_SPLIT(dev
)) {
10685 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
10686 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
10687 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
10688 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
10689 dev_priv
->display
.off
= ironlake_crtc_off
;
10690 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10691 } else if (IS_VALLEYVIEW(dev
)) {
10692 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10693 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10694 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
10695 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10696 dev_priv
->display
.off
= i9xx_crtc_off
;
10697 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10699 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10700 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10701 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
10702 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10703 dev_priv
->display
.off
= i9xx_crtc_off
;
10704 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10707 /* Returns the core display clock speed */
10708 if (IS_VALLEYVIEW(dev
))
10709 dev_priv
->display
.get_display_clock_speed
=
10710 valleyview_get_display_clock_speed
;
10711 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
10712 dev_priv
->display
.get_display_clock_speed
=
10713 i945_get_display_clock_speed
;
10714 else if (IS_I915G(dev
))
10715 dev_priv
->display
.get_display_clock_speed
=
10716 i915_get_display_clock_speed
;
10717 else if (IS_I945GM(dev
) || IS_845G(dev
))
10718 dev_priv
->display
.get_display_clock_speed
=
10719 i9xx_misc_get_display_clock_speed
;
10720 else if (IS_PINEVIEW(dev
))
10721 dev_priv
->display
.get_display_clock_speed
=
10722 pnv_get_display_clock_speed
;
10723 else if (IS_I915GM(dev
))
10724 dev_priv
->display
.get_display_clock_speed
=
10725 i915gm_get_display_clock_speed
;
10726 else if (IS_I865G(dev
))
10727 dev_priv
->display
.get_display_clock_speed
=
10728 i865_get_display_clock_speed
;
10729 else if (IS_I85X(dev
))
10730 dev_priv
->display
.get_display_clock_speed
=
10731 i855_get_display_clock_speed
;
10732 else /* 852, 830 */
10733 dev_priv
->display
.get_display_clock_speed
=
10734 i830_get_display_clock_speed
;
10736 if (HAS_PCH_SPLIT(dev
)) {
10737 if (IS_GEN5(dev
)) {
10738 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10739 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10740 } else if (IS_GEN6(dev
)) {
10741 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10742 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10743 } else if (IS_IVYBRIDGE(dev
)) {
10744 /* FIXME: detect B0+ stepping and use auto training */
10745 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10746 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10747 dev_priv
->display
.modeset_global_resources
=
10748 ivb_modeset_global_resources
;
10749 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
10750 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10751 dev_priv
->display
.write_eld
= haswell_write_eld
;
10752 dev_priv
->display
.modeset_global_resources
=
10753 haswell_modeset_global_resources
;
10755 } else if (IS_G4X(dev
)) {
10756 dev_priv
->display
.write_eld
= g4x_write_eld
;
10757 } else if (IS_VALLEYVIEW(dev
)) {
10758 dev_priv
->display
.modeset_global_resources
=
10759 valleyview_modeset_global_resources
;
10760 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10763 /* Default just returns -ENODEV to indicate unsupported */
10764 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10766 switch (INTEL_INFO(dev
)->gen
) {
10768 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10772 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10777 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10781 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10784 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10785 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10789 intel_panel_init_backlight_funcs(dev
);
10793 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10794 * resume, or other times. This quirk makes sure that's the case for
10795 * affected systems.
10797 static void quirk_pipea_force(struct drm_device
*dev
)
10799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10801 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10802 DRM_INFO("applying pipe a force quirk\n");
10806 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10808 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10811 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10812 DRM_INFO("applying lvds SSC disable quirk\n");
10816 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10819 static void quirk_invert_brightness(struct drm_device
*dev
)
10821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10822 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10823 DRM_INFO("applying inverted panel brightness quirk\n");
10826 struct intel_quirk
{
10828 int subsystem_vendor
;
10829 int subsystem_device
;
10830 void (*hook
)(struct drm_device
*dev
);
10833 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10834 struct intel_dmi_quirk
{
10835 void (*hook
)(struct drm_device
*dev
);
10836 const struct dmi_system_id (*dmi_id_list
)[];
10839 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10841 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10845 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10847 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10849 .callback
= intel_dmi_reverse_brightness
,
10850 .ident
= "NCR Corporation",
10851 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10852 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10855 { } /* terminating entry */
10857 .hook
= quirk_invert_brightness
,
10861 static struct intel_quirk intel_quirks
[] = {
10862 /* HP Mini needs pipe A force quirk (LP: #322104) */
10863 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10865 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10866 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10868 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10869 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10871 /* 830 needs to leave pipe A & dpll A up */
10872 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10874 /* Lenovo U160 cannot use SSC on LVDS */
10875 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10877 /* Sony Vaio Y cannot use SSC on LVDS */
10878 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10880 /* Acer Aspire 5734Z must invert backlight brightness */
10881 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
10883 /* Acer/eMachines G725 */
10884 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
10886 /* Acer/eMachines e725 */
10887 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
10889 /* Acer/Packard Bell NCL20 */
10890 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
10892 /* Acer Aspire 4736Z */
10893 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
10896 static void intel_init_quirks(struct drm_device
*dev
)
10898 struct pci_dev
*d
= dev
->pdev
;
10901 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10902 struct intel_quirk
*q
= &intel_quirks
[i
];
10904 if (d
->device
== q
->device
&&
10905 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10906 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10907 (d
->subsystem_device
== q
->subsystem_device
||
10908 q
->subsystem_device
== PCI_ANY_ID
))
10911 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10912 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10913 intel_dmi_quirks
[i
].hook(dev
);
10917 /* Disable the VGA plane that we never use */
10918 static void i915_disable_vga(struct drm_device
*dev
)
10920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10922 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10924 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10925 outb(SR01
, VGA_SR_INDEX
);
10926 sr1
= inb(VGA_SR_DATA
);
10927 outb(sr1
| 1<<5, VGA_SR_DATA
);
10928 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10931 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10932 POSTING_READ(vga_reg
);
10935 void intel_modeset_init_hw(struct drm_device
*dev
)
10937 intel_prepare_ddi(dev
);
10939 intel_init_clock_gating(dev
);
10941 intel_reset_dpio(dev
);
10943 mutex_lock(&dev
->struct_mutex
);
10944 intel_enable_gt_powersave(dev
);
10945 mutex_unlock(&dev
->struct_mutex
);
10948 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10950 intel_suspend_hw(dev
);
10953 void intel_modeset_init(struct drm_device
*dev
)
10955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10958 drm_mode_config_init(dev
);
10960 dev
->mode_config
.min_width
= 0;
10961 dev
->mode_config
.min_height
= 0;
10963 dev
->mode_config
.preferred_depth
= 24;
10964 dev
->mode_config
.prefer_shadow
= 1;
10966 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10968 intel_init_quirks(dev
);
10970 intel_init_pm(dev
);
10972 if (INTEL_INFO(dev
)->num_pipes
== 0)
10975 intel_init_display(dev
);
10977 if (IS_GEN2(dev
)) {
10978 dev
->mode_config
.max_width
= 2048;
10979 dev
->mode_config
.max_height
= 2048;
10980 } else if (IS_GEN3(dev
)) {
10981 dev
->mode_config
.max_width
= 4096;
10982 dev
->mode_config
.max_height
= 4096;
10984 dev
->mode_config
.max_width
= 8192;
10985 dev
->mode_config
.max_height
= 8192;
10987 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10989 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10990 INTEL_INFO(dev
)->num_pipes
,
10991 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10994 intel_crtc_init(dev
, i
);
10995 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10996 ret
= intel_plane_init(dev
, i
, j
);
10998 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10999 pipe_name(i
), sprite_name(i
, j
), ret
);
11003 intel_init_dpio(dev
);
11004 intel_reset_dpio(dev
);
11006 intel_cpu_pll_init(dev
);
11007 intel_shared_dpll_init(dev
);
11009 /* Just disable it once at startup */
11010 i915_disable_vga(dev
);
11011 intel_setup_outputs(dev
);
11013 /* Just in case the BIOS is doing something questionable. */
11014 intel_disable_fbc(dev
);
11018 intel_connector_break_all_links(struct intel_connector
*connector
)
11020 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
11021 connector
->base
.encoder
= NULL
;
11022 connector
->encoder
->connectors_active
= false;
11023 connector
->encoder
->base
.crtc
= NULL
;
11026 static void intel_enable_pipe_a(struct drm_device
*dev
)
11028 struct intel_connector
*connector
;
11029 struct drm_connector
*crt
= NULL
;
11030 struct intel_load_detect_pipe load_detect_temp
;
11032 /* We can't just switch on the pipe A, we need to set things up with a
11033 * proper mode and output configuration. As a gross hack, enable pipe A
11034 * by enabling the load detect pipe once. */
11035 list_for_each_entry(connector
,
11036 &dev
->mode_config
.connector_list
,
11038 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
11039 crt
= &connector
->base
;
11047 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
11048 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
11054 intel_check_plane_mapping(struct intel_crtc
*crtc
)
11056 struct drm_device
*dev
= crtc
->base
.dev
;
11057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11060 if (INTEL_INFO(dev
)->num_pipes
== 1)
11063 reg
= DSPCNTR(!crtc
->plane
);
11064 val
= I915_READ(reg
);
11066 if ((val
& DISPLAY_PLANE_ENABLE
) &&
11067 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
11073 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
11075 struct drm_device
*dev
= crtc
->base
.dev
;
11076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11079 /* Clear any frame start delays used for debugging left by the BIOS */
11080 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
11081 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
11083 /* We need to sanitize the plane -> pipe mapping first because this will
11084 * disable the crtc (and hence change the state) if it is wrong. Note
11085 * that gen4+ has a fixed plane -> pipe mapping. */
11086 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
11087 struct intel_connector
*connector
;
11090 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11091 crtc
->base
.base
.id
);
11093 /* Pipe has the wrong plane attached and the plane is active.
11094 * Temporarily change the plane mapping and disable everything
11096 plane
= crtc
->plane
;
11097 crtc
->plane
= !plane
;
11098 dev_priv
->display
.crtc_disable(&crtc
->base
);
11099 crtc
->plane
= plane
;
11101 /* ... and break all links. */
11102 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11104 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
11107 intel_connector_break_all_links(connector
);
11110 WARN_ON(crtc
->active
);
11111 crtc
->base
.enabled
= false;
11114 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
11115 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
11116 /* BIOS forgot to enable pipe A, this mostly happens after
11117 * resume. Force-enable the pipe to fix this, the update_dpms
11118 * call below we restore the pipe to the right state, but leave
11119 * the required bits on. */
11120 intel_enable_pipe_a(dev
);
11123 /* Adjust the state of the output pipe according to whether we
11124 * have active connectors/encoders. */
11125 intel_crtc_update_dpms(&crtc
->base
);
11127 if (crtc
->active
!= crtc
->base
.enabled
) {
11128 struct intel_encoder
*encoder
;
11130 /* This can happen either due to bugs in the get_hw_state
11131 * functions or because the pipe is force-enabled due to the
11133 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11134 crtc
->base
.base
.id
,
11135 crtc
->base
.enabled
? "enabled" : "disabled",
11136 crtc
->active
? "enabled" : "disabled");
11138 crtc
->base
.enabled
= crtc
->active
;
11140 /* Because we only establish the connector -> encoder ->
11141 * crtc links if something is active, this means the
11142 * crtc is now deactivated. Break the links. connector
11143 * -> encoder links are only establish when things are
11144 * actually up, hence no need to break them. */
11145 WARN_ON(crtc
->active
);
11147 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
11148 WARN_ON(encoder
->connectors_active
);
11149 encoder
->base
.crtc
= NULL
;
11154 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
11156 struct intel_connector
*connector
;
11157 struct drm_device
*dev
= encoder
->base
.dev
;
11159 /* We need to check both for a crtc link (meaning that the
11160 * encoder is active and trying to read from a pipe) and the
11161 * pipe itself being active. */
11162 bool has_active_crtc
= encoder
->base
.crtc
&&
11163 to_intel_crtc(encoder
->base
.crtc
)->active
;
11165 if (encoder
->connectors_active
&& !has_active_crtc
) {
11166 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11167 encoder
->base
.base
.id
,
11168 drm_get_encoder_name(&encoder
->base
));
11170 /* Connector is active, but has no active pipe. This is
11171 * fallout from our resume register restoring. Disable
11172 * the encoder manually again. */
11173 if (encoder
->base
.crtc
) {
11174 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11175 encoder
->base
.base
.id
,
11176 drm_get_encoder_name(&encoder
->base
));
11177 encoder
->disable(encoder
);
11180 /* Inconsistent output/port/pipe state happens presumably due to
11181 * a bug in one of the get_hw_state functions. Or someplace else
11182 * in our code, like the register restore mess on resume. Clamp
11183 * things to off as a safer default. */
11184 list_for_each_entry(connector
,
11185 &dev
->mode_config
.connector_list
,
11187 if (connector
->encoder
!= encoder
)
11190 intel_connector_break_all_links(connector
);
11193 /* Enabled encoders without active connectors will be fixed in
11194 * the crtc fixup. */
11197 void i915_redisable_vga(struct drm_device
*dev
)
11199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11200 u32 vga_reg
= i915_vgacntrl_reg(dev
);
11202 /* This function can be called both from intel_modeset_setup_hw_state or
11203 * at a very early point in our resume sequence, where the power well
11204 * structures are not yet restored. Since this function is at a very
11205 * paranoid "someone might have enabled VGA while we were not looking"
11206 * level, just check if the power well is enabled instead of trying to
11207 * follow the "don't touch the power well if we don't need it" policy
11208 * the rest of the driver uses. */
11209 if ((IS_HASWELL(dev
) || IS_BROADWELL(dev
)) &&
11210 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
11213 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
11214 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11215 i915_disable_vga(dev
);
11219 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
11221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11223 struct intel_crtc
*crtc
;
11224 struct intel_encoder
*encoder
;
11225 struct intel_connector
*connector
;
11228 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11230 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
11232 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
11235 crtc
->base
.enabled
= crtc
->active
;
11236 crtc
->primary_enabled
= crtc
->active
;
11238 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11239 crtc
->base
.base
.id
,
11240 crtc
->active
? "enabled" : "disabled");
11243 /* FIXME: Smash this into the new shared dpll infrastructure. */
11245 intel_ddi_setup_hw_pll_state(dev
);
11247 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11248 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11250 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
11252 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11254 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11257 pll
->refcount
= pll
->active
;
11259 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11260 pll
->name
, pll
->refcount
, pll
->on
);
11263 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
11267 if (encoder
->get_hw_state(encoder
, &pipe
)) {
11268 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
11269 encoder
->base
.crtc
= &crtc
->base
;
11270 encoder
->get_config(encoder
, &crtc
->config
);
11272 encoder
->base
.crtc
= NULL
;
11275 encoder
->connectors_active
= false;
11276 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11277 encoder
->base
.base
.id
,
11278 drm_get_encoder_name(&encoder
->base
),
11279 encoder
->base
.crtc
? "enabled" : "disabled",
11283 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11285 if (connector
->get_hw_state(connector
)) {
11286 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
11287 connector
->encoder
->connectors_active
= true;
11288 connector
->base
.encoder
= &connector
->encoder
->base
;
11290 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
11291 connector
->base
.encoder
= NULL
;
11293 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11294 connector
->base
.base
.id
,
11295 drm_get_connector_name(&connector
->base
),
11296 connector
->base
.encoder
? "enabled" : "disabled");
11300 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11301 * and i915 state tracking structures. */
11302 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
11303 bool force_restore
)
11305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11307 struct intel_crtc
*crtc
;
11308 struct intel_encoder
*encoder
;
11311 intel_modeset_readout_hw_state(dev
);
11314 * Now that we have the config, copy it to each CRTC struct
11315 * Note that this could go away if we move to using crtc_config
11316 * checking everywhere.
11318 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
11320 if (crtc
->active
&& i915_fastboot
) {
11321 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
11323 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11324 crtc
->base
.base
.id
);
11325 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
11329 /* HW state is read out, now we need to sanitize this mess. */
11330 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
11332 intel_sanitize_encoder(encoder
);
11335 for_each_pipe(pipe
) {
11336 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
11337 intel_sanitize_crtc(crtc
);
11338 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
11341 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11342 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11344 if (!pll
->on
|| pll
->active
)
11347 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
11349 pll
->disable(dev_priv
, pll
);
11353 if (HAS_PCH_SPLIT(dev
))
11354 ilk_wm_get_hw_state(dev
);
11356 if (force_restore
) {
11357 i915_redisable_vga(dev
);
11360 * We need to use raw interfaces for restoring state to avoid
11361 * checking (bogus) intermediate states.
11363 for_each_pipe(pipe
) {
11364 struct drm_crtc
*crtc
=
11365 dev_priv
->pipe_to_crtc_mapping
[pipe
];
11367 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
11371 intel_modeset_update_staged_output_state(dev
);
11374 intel_modeset_check_state(dev
);
11377 void intel_modeset_gem_init(struct drm_device
*dev
)
11379 intel_modeset_init_hw(dev
);
11381 intel_setup_overlay(dev
);
11383 mutex_lock(&dev
->mode_config
.mutex
);
11384 drm_mode_config_reset(dev
);
11385 intel_modeset_setup_hw_state(dev
, false);
11386 mutex_unlock(&dev
->mode_config
.mutex
);
11389 void intel_modeset_cleanup(struct drm_device
*dev
)
11391 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11392 struct drm_crtc
*crtc
;
11393 struct drm_connector
*connector
;
11396 * Interrupts and polling as the first thing to avoid creating havoc.
11397 * Too much stuff here (turning of rps, connectors, ...) would
11398 * experience fancy races otherwise.
11400 drm_irq_uninstall(dev
);
11401 cancel_work_sync(&dev_priv
->hotplug_work
);
11403 * Due to the hpd irq storm handling the hotplug work can re-arm the
11404 * poll handlers. Hence disable polling after hpd handling is shut down.
11406 drm_kms_helper_poll_fini(dev
);
11408 mutex_lock(&dev
->struct_mutex
);
11410 intel_unregister_dsm_handler();
11412 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
11413 /* Skip inactive CRTCs */
11417 intel_increase_pllclock(crtc
);
11420 intel_disable_fbc(dev
);
11422 intel_disable_gt_powersave(dev
);
11424 ironlake_teardown_rc6(dev
);
11426 mutex_unlock(&dev
->struct_mutex
);
11428 /* flush any delayed tasks or pending work */
11429 flush_scheduled_work();
11431 /* destroy the backlight and sysfs files before encoders/connectors */
11432 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11433 intel_panel_destroy_backlight(connector
);
11434 drm_sysfs_connector_remove(connector
);
11437 drm_mode_config_cleanup(dev
);
11439 intel_cleanup_overlay(dev
);
11443 * Return which encoder is currently attached for connector.
11445 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
11447 return &intel_attached_encoder(connector
)->base
;
11450 void intel_connector_attach_encoder(struct intel_connector
*connector
,
11451 struct intel_encoder
*encoder
)
11453 connector
->encoder
= encoder
;
11454 drm_mode_connector_attach_encoder(&connector
->base
,
11459 * set vga decode state - true == enable VGA decode
11461 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
11463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11464 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
11467 pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
);
11469 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
11471 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
11472 pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
);
11476 struct intel_display_error_state
{
11478 u32 power_well_driver
;
11480 int num_transcoders
;
11482 struct intel_cursor_error_state
{
11487 } cursor
[I915_MAX_PIPES
];
11489 struct intel_pipe_error_state
{
11490 bool power_domain_on
;
11492 } pipe
[I915_MAX_PIPES
];
11494 struct intel_plane_error_state
{
11502 } plane
[I915_MAX_PIPES
];
11504 struct intel_transcoder_error_state
{
11505 bool power_domain_on
;
11506 enum transcoder cpu_transcoder
;
11519 struct intel_display_error_state
*
11520 intel_display_capture_error_state(struct drm_device
*dev
)
11522 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
11523 struct intel_display_error_state
*error
;
11524 int transcoders
[] = {
11532 if (INTEL_INFO(dev
)->num_pipes
== 0)
11535 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
11539 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
11540 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
11543 error
->pipe
[i
].power_domain_on
=
11544 intel_display_power_enabled_sw(dev
, POWER_DOMAIN_PIPE(i
));
11545 if (!error
->pipe
[i
].power_domain_on
)
11548 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
11549 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
11550 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
11551 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
11553 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
11554 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
11555 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
11558 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
11559 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
11560 if (INTEL_INFO(dev
)->gen
<= 3) {
11561 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
11562 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
11564 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11565 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
11566 if (INTEL_INFO(dev
)->gen
>= 4) {
11567 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
11568 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
11571 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
11574 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
11575 if (HAS_DDI(dev_priv
->dev
))
11576 error
->num_transcoders
++; /* Account for eDP. */
11578 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11579 enum transcoder cpu_transcoder
= transcoders
[i
];
11581 error
->transcoder
[i
].power_domain_on
=
11582 intel_display_power_enabled_sw(dev
,
11583 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
11584 if (!error
->transcoder
[i
].power_domain_on
)
11587 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
11589 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
11590 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
11591 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
11592 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
11593 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
11594 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
11595 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
11601 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11604 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
11605 struct drm_device
*dev
,
11606 struct intel_display_error_state
*error
)
11613 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
11614 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
11615 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
11616 error
->power_well_driver
);
11618 err_printf(m
, "Pipe [%d]:\n", i
);
11619 err_printf(m
, " Power: %s\n",
11620 error
->pipe
[i
].power_domain_on
? "on" : "off");
11621 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
11623 err_printf(m
, "Plane [%d]:\n", i
);
11624 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
11625 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
11626 if (INTEL_INFO(dev
)->gen
<= 3) {
11627 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
11628 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
11630 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
11631 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
11632 if (INTEL_INFO(dev
)->gen
>= 4) {
11633 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
11634 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
11637 err_printf(m
, "Cursor [%d]:\n", i
);
11638 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
11639 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
11640 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
11643 for (i
= 0; i
< error
->num_transcoders
; i
++) {
11644 err_printf(m
, "CPU transcoder: %c\n",
11645 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
11646 err_printf(m
, " Power: %s\n",
11647 error
->transcoder
[i
].power_domain_on
? "on" : "off");
11648 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
11649 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
11650 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
11651 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
11652 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
11653 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
11654 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);