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d2b752dd0aafa3768a4c52dd2c2f8d8ca6032a44
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_device *dev,
80 enum pipe pipe);
81 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
82
83 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
84 struct intel_crtc_config *pipe_config);
85 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
86 struct intel_crtc_config *pipe_config);
87
88 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
89 int x, int y, struct drm_framebuffer *old_fb);
90 static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
94 static void intel_dp_set_m_n(struct intel_crtc *crtc);
95 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
97 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
98 struct intel_link_m_n *m_n);
99 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
100 static void haswell_set_pipeconf(struct drm_crtc *crtc);
101 static void intel_set_pipe_csc(struct drm_crtc *crtc);
102 static void vlv_prepare_pll(struct intel_crtc *crtc);
103
104 typedef struct {
105 int min, max;
106 } intel_range_t;
107
108 typedef struct {
109 int dot_limit;
110 int p2_slow, p2_fast;
111 } intel_p2_t;
112
113 typedef struct intel_limit intel_limit_t;
114 struct intel_limit {
115 intel_range_t dot, vco, n, m, m1, m2, p, p1;
116 intel_p2_t p2;
117 };
118
119 int
120 intel_pch_rawclk(struct drm_device *dev)
121 {
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 WARN_ON(!HAS_PCH_SPLIT(dev));
125
126 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
127 }
128
129 static inline u32 /* units of 100MHz */
130 intel_fdi_link_freq(struct drm_device *dev)
131 {
132 if (IS_GEN5(dev)) {
133 struct drm_i915_private *dev_priv = dev->dev_private;
134 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
135 } else
136 return 27;
137 }
138
139 static const intel_limit_t intel_limits_i8xx_dac = {
140 .dot = { .min = 25000, .max = 350000 },
141 .vco = { .min = 908000, .max = 1512000 },
142 .n = { .min = 2, .max = 16 },
143 .m = { .min = 96, .max = 140 },
144 .m1 = { .min = 18, .max = 26 },
145 .m2 = { .min = 6, .max = 16 },
146 .p = { .min = 4, .max = 128 },
147 .p1 = { .min = 2, .max = 33 },
148 .p2 = { .dot_limit = 165000,
149 .p2_slow = 4, .p2_fast = 2 },
150 };
151
152 static const intel_limit_t intel_limits_i8xx_dvo = {
153 .dot = { .min = 25000, .max = 350000 },
154 .vco = { .min = 908000, .max = 1512000 },
155 .n = { .min = 2, .max = 16 },
156 .m = { .min = 96, .max = 140 },
157 .m1 = { .min = 18, .max = 26 },
158 .m2 = { .min = 6, .max = 16 },
159 .p = { .min = 4, .max = 128 },
160 .p1 = { .min = 2, .max = 33 },
161 .p2 = { .dot_limit = 165000,
162 .p2_slow = 4, .p2_fast = 4 },
163 };
164
165 static const intel_limit_t intel_limits_i8xx_lvds = {
166 .dot = { .min = 25000, .max = 350000 },
167 .vco = { .min = 908000, .max = 1512000 },
168 .n = { .min = 2, .max = 16 },
169 .m = { .min = 96, .max = 140 },
170 .m1 = { .min = 18, .max = 26 },
171 .m2 = { .min = 6, .max = 16 },
172 .p = { .min = 4, .max = 128 },
173 .p1 = { .min = 1, .max = 6 },
174 .p2 = { .dot_limit = 165000,
175 .p2_slow = 14, .p2_fast = 7 },
176 };
177
178 static const intel_limit_t intel_limits_i9xx_sdvo = {
179 .dot = { .min = 20000, .max = 400000 },
180 .vco = { .min = 1400000, .max = 2800000 },
181 .n = { .min = 1, .max = 6 },
182 .m = { .min = 70, .max = 120 },
183 .m1 = { .min = 8, .max = 18 },
184 .m2 = { .min = 3, .max = 7 },
185 .p = { .min = 5, .max = 80 },
186 .p1 = { .min = 1, .max = 8 },
187 .p2 = { .dot_limit = 200000,
188 .p2_slow = 10, .p2_fast = 5 },
189 };
190
191 static const intel_limit_t intel_limits_i9xx_lvds = {
192 .dot = { .min = 20000, .max = 400000 },
193 .vco = { .min = 1400000, .max = 2800000 },
194 .n = { .min = 1, .max = 6 },
195 .m = { .min = 70, .max = 120 },
196 .m1 = { .min = 8, .max = 18 },
197 .m2 = { .min = 3, .max = 7 },
198 .p = { .min = 7, .max = 98 },
199 .p1 = { .min = 1, .max = 8 },
200 .p2 = { .dot_limit = 112000,
201 .p2_slow = 14, .p2_fast = 7 },
202 };
203
204
205 static const intel_limit_t intel_limits_g4x_sdvo = {
206 .dot = { .min = 25000, .max = 270000 },
207 .vco = { .min = 1750000, .max = 3500000},
208 .n = { .min = 1, .max = 4 },
209 .m = { .min = 104, .max = 138 },
210 .m1 = { .min = 17, .max = 23 },
211 .m2 = { .min = 5, .max = 11 },
212 .p = { .min = 10, .max = 30 },
213 .p1 = { .min = 1, .max = 3},
214 .p2 = { .dot_limit = 270000,
215 .p2_slow = 10,
216 .p2_fast = 10
217 },
218 };
219
220 static const intel_limit_t intel_limits_g4x_hdmi = {
221 .dot = { .min = 22000, .max = 400000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 16, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 5, .max = 80 },
228 .p1 = { .min = 1, .max = 8},
229 .p2 = { .dot_limit = 165000,
230 .p2_slow = 10, .p2_fast = 5 },
231 };
232
233 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
234 .dot = { .min = 20000, .max = 115000 },
235 .vco = { .min = 1750000, .max = 3500000 },
236 .n = { .min = 1, .max = 3 },
237 .m = { .min = 104, .max = 138 },
238 .m1 = { .min = 17, .max = 23 },
239 .m2 = { .min = 5, .max = 11 },
240 .p = { .min = 28, .max = 112 },
241 .p1 = { .min = 2, .max = 8 },
242 .p2 = { .dot_limit = 0,
243 .p2_slow = 14, .p2_fast = 14
244 },
245 };
246
247 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
248 .dot = { .min = 80000, .max = 224000 },
249 .vco = { .min = 1750000, .max = 3500000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 104, .max = 138 },
252 .m1 = { .min = 17, .max = 23 },
253 .m2 = { .min = 5, .max = 11 },
254 .p = { .min = 14, .max = 42 },
255 .p1 = { .min = 2, .max = 6 },
256 .p2 = { .dot_limit = 0,
257 .p2_slow = 7, .p2_fast = 7
258 },
259 };
260
261 static const intel_limit_t intel_limits_pineview_sdvo = {
262 .dot = { .min = 20000, .max = 400000},
263 .vco = { .min = 1700000, .max = 3500000 },
264 /* Pineview's Ncounter is a ring counter */
265 .n = { .min = 3, .max = 6 },
266 .m = { .min = 2, .max = 256 },
267 /* Pineview only has one combined m divider, which we treat as m2. */
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 5, .max = 80 },
271 .p1 = { .min = 1, .max = 8 },
272 .p2 = { .dot_limit = 200000,
273 .p2_slow = 10, .p2_fast = 5 },
274 };
275
276 static const intel_limit_t intel_limits_pineview_lvds = {
277 .dot = { .min = 20000, .max = 400000 },
278 .vco = { .min = 1700000, .max = 3500000 },
279 .n = { .min = 3, .max = 6 },
280 .m = { .min = 2, .max = 256 },
281 .m1 = { .min = 0, .max = 0 },
282 .m2 = { .min = 0, .max = 254 },
283 .p = { .min = 7, .max = 112 },
284 .p1 = { .min = 1, .max = 8 },
285 .p2 = { .dot_limit = 112000,
286 .p2_slow = 14, .p2_fast = 14 },
287 };
288
289 /* Ironlake / Sandybridge
290 *
291 * We calculate clock using (register_value + 2) for N/M1/M2, so here
292 * the range value for them is (actual_value - 2).
293 */
294 static const intel_limit_t intel_limits_ironlake_dac = {
295 .dot = { .min = 25000, .max = 350000 },
296 .vco = { .min = 1760000, .max = 3510000 },
297 .n = { .min = 1, .max = 5 },
298 .m = { .min = 79, .max = 127 },
299 .m1 = { .min = 12, .max = 22 },
300 .m2 = { .min = 5, .max = 9 },
301 .p = { .min = 5, .max = 80 },
302 .p1 = { .min = 1, .max = 8 },
303 .p2 = { .dot_limit = 225000,
304 .p2_slow = 10, .p2_fast = 5 },
305 };
306
307 static const intel_limit_t intel_limits_ironlake_single_lvds = {
308 .dot = { .min = 25000, .max = 350000 },
309 .vco = { .min = 1760000, .max = 3510000 },
310 .n = { .min = 1, .max = 3 },
311 .m = { .min = 79, .max = 118 },
312 .m1 = { .min = 12, .max = 22 },
313 .m2 = { .min = 5, .max = 9 },
314 .p = { .min = 28, .max = 112 },
315 .p1 = { .min = 2, .max = 8 },
316 .p2 = { .dot_limit = 225000,
317 .p2_slow = 14, .p2_fast = 14 },
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 };
332
333 /* LVDS 100mhz refclk limits. */
334 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 2 },
338 .m = { .min = 79, .max = 126 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 28, .max = 112 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 14, .p2_fast = 14 },
345 };
346
347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
355 .p1 = { .min = 2, .max = 6 },
356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
358 };
359
360 static const intel_limit_t intel_limits_vlv = {
361 /*
362 * These are the data rate limits (measured in fast clocks)
363 * since those are the strictest limits we have. The fast
364 * clock and actual rate limits are more relaxed, so checking
365 * them would make no difference.
366 */
367 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
368 .vco = { .min = 4000000, .max = 6000000 },
369 .n = { .min = 1, .max = 7 },
370 .m1 = { .min = 2, .max = 3 },
371 .m2 = { .min = 11, .max = 156 },
372 .p1 = { .min = 2, .max = 3 },
373 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
374 };
375
376 static const intel_limit_t intel_limits_chv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 540000 * 5},
384 .vco = { .min = 4860000, .max = 6700000 },
385 .n = { .min = 1, .max = 1 },
386 .m1 = { .min = 2, .max = 2 },
387 .m2 = { .min = 24 << 22, .max = 175 << 22 },
388 .p1 = { .min = 2, .max = 4 },
389 .p2 = { .p2_slow = 1, .p2_fast = 14 },
390 };
391
392 static void vlv_clock(int refclk, intel_clock_t *clock)
393 {
394 clock->m = clock->m1 * clock->m2;
395 clock->p = clock->p1 * clock->p2;
396 if (WARN_ON(clock->n == 0 || clock->p == 0))
397 return;
398 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
399 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
400 }
401
402 /**
403 * Returns whether any output on the specified pipe is of the specified type
404 */
405 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
406 {
407 struct drm_device *dev = crtc->dev;
408 struct intel_encoder *encoder;
409
410 for_each_encoder_on_crtc(dev, crtc, encoder)
411 if (encoder->type == type)
412 return true;
413
414 return false;
415 }
416
417 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
418 int refclk)
419 {
420 struct drm_device *dev = crtc->dev;
421 const intel_limit_t *limit;
422
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
424 if (intel_is_dual_link_lvds(dev)) {
425 if (refclk == 100000)
426 limit = &intel_limits_ironlake_dual_lvds_100m;
427 else
428 limit = &intel_limits_ironlake_dual_lvds;
429 } else {
430 if (refclk == 100000)
431 limit = &intel_limits_ironlake_single_lvds_100m;
432 else
433 limit = &intel_limits_ironlake_single_lvds;
434 }
435 } else
436 limit = &intel_limits_ironlake_dac;
437
438 return limit;
439 }
440
441 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
442 {
443 struct drm_device *dev = crtc->dev;
444 const intel_limit_t *limit;
445
446 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
447 if (intel_is_dual_link_lvds(dev))
448 limit = &intel_limits_g4x_dual_channel_lvds;
449 else
450 limit = &intel_limits_g4x_single_channel_lvds;
451 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
452 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
453 limit = &intel_limits_g4x_hdmi;
454 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
455 limit = &intel_limits_g4x_sdvo;
456 } else /* The option is for other outputs */
457 limit = &intel_limits_i9xx_sdvo;
458
459 return limit;
460 }
461
462 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
463 {
464 struct drm_device *dev = crtc->dev;
465 const intel_limit_t *limit;
466
467 if (HAS_PCH_SPLIT(dev))
468 limit = intel_ironlake_limit(crtc, refclk);
469 else if (IS_G4X(dev)) {
470 limit = intel_g4x_limit(crtc);
471 } else if (IS_PINEVIEW(dev)) {
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
473 limit = &intel_limits_pineview_lvds;
474 else
475 limit = &intel_limits_pineview_sdvo;
476 } else if (IS_CHERRYVIEW(dev)) {
477 limit = &intel_limits_chv;
478 } else if (IS_VALLEYVIEW(dev)) {
479 limit = &intel_limits_vlv;
480 } else if (!IS_GEN2(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
482 limit = &intel_limits_i9xx_lvds;
483 else
484 limit = &intel_limits_i9xx_sdvo;
485 } else {
486 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
487 limit = &intel_limits_i8xx_lvds;
488 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
489 limit = &intel_limits_i8xx_dvo;
490 else
491 limit = &intel_limits_i8xx_dac;
492 }
493 return limit;
494 }
495
496 /* m1 is reserved as 0 in Pineview, n is a ring counter */
497 static void pineview_clock(int refclk, intel_clock_t *clock)
498 {
499 clock->m = clock->m2 + 2;
500 clock->p = clock->p1 * clock->p2;
501 if (WARN_ON(clock->n == 0 || clock->p == 0))
502 return;
503 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
504 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
505 }
506
507 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
508 {
509 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
510 }
511
512 static void i9xx_clock(int refclk, intel_clock_t *clock)
513 {
514 clock->m = i9xx_dpll_compute_m(clock);
515 clock->p = clock->p1 * clock->p2;
516 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
517 return;
518 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
519 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
520 }
521
522 static void chv_clock(int refclk, intel_clock_t *clock)
523 {
524 clock->m = clock->m1 * clock->m2;
525 clock->p = clock->p1 * clock->p2;
526 if (WARN_ON(clock->n == 0 || clock->p == 0))
527 return;
528 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
529 clock->n << 22);
530 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
531 }
532
533 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
534 /**
535 * Returns whether the given set of divisors are valid for a given refclk with
536 * the given connectors.
537 */
538
539 static bool intel_PLL_is_valid(struct drm_device *dev,
540 const intel_limit_t *limit,
541 const intel_clock_t *clock)
542 {
543 if (clock->n < limit->n.min || limit->n.max < clock->n)
544 INTELPllInvalid("n out of range\n");
545 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
546 INTELPllInvalid("p1 out of range\n");
547 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
548 INTELPllInvalid("m2 out of range\n");
549 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
550 INTELPllInvalid("m1 out of range\n");
551
552 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
553 if (clock->m1 <= clock->m2)
554 INTELPllInvalid("m1 <= m2\n");
555
556 if (!IS_VALLEYVIEW(dev)) {
557 if (clock->p < limit->p.min || limit->p.max < clock->p)
558 INTELPllInvalid("p out of range\n");
559 if (clock->m < limit->m.min || limit->m.max < clock->m)
560 INTELPllInvalid("m out of range\n");
561 }
562
563 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
564 INTELPllInvalid("vco out of range\n");
565 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
566 * connector, etc., rather than just a single range.
567 */
568 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
569 INTELPllInvalid("dot out of range\n");
570
571 return true;
572 }
573
574 static bool
575 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
576 int target, int refclk, intel_clock_t *match_clock,
577 intel_clock_t *best_clock)
578 {
579 struct drm_device *dev = crtc->dev;
580 intel_clock_t clock;
581 int err = target;
582
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
584 /*
585 * For LVDS just rely on its current settings for dual-channel.
586 * We haven't figured out how to reliably set up different
587 * single/dual channel state, if we even can.
588 */
589 if (intel_is_dual_link_lvds(dev))
590 clock.p2 = limit->p2.p2_fast;
591 else
592 clock.p2 = limit->p2.p2_slow;
593 } else {
594 if (target < limit->p2.dot_limit)
595 clock.p2 = limit->p2.p2_slow;
596 else
597 clock.p2 = limit->p2.p2_fast;
598 }
599
600 memset(best_clock, 0, sizeof(*best_clock));
601
602 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
603 clock.m1++) {
604 for (clock.m2 = limit->m2.min;
605 clock.m2 <= limit->m2.max; clock.m2++) {
606 if (clock.m2 >= clock.m1)
607 break;
608 for (clock.n = limit->n.min;
609 clock.n <= limit->n.max; clock.n++) {
610 for (clock.p1 = limit->p1.min;
611 clock.p1 <= limit->p1.max; clock.p1++) {
612 int this_err;
613
614 i9xx_clock(refclk, &clock);
615 if (!intel_PLL_is_valid(dev, limit,
616 &clock))
617 continue;
618 if (match_clock &&
619 clock.p != match_clock->p)
620 continue;
621
622 this_err = abs(clock.dot - target);
623 if (this_err < err) {
624 *best_clock = clock;
625 err = this_err;
626 }
627 }
628 }
629 }
630 }
631
632 return (err != target);
633 }
634
635 static bool
636 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
637 int target, int refclk, intel_clock_t *match_clock,
638 intel_clock_t *best_clock)
639 {
640 struct drm_device *dev = crtc->dev;
641 intel_clock_t clock;
642 int err = target;
643
644 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
645 /*
646 * For LVDS just rely on its current settings for dual-channel.
647 * We haven't figured out how to reliably set up different
648 * single/dual channel state, if we even can.
649 */
650 if (intel_is_dual_link_lvds(dev))
651 clock.p2 = limit->p2.p2_fast;
652 else
653 clock.p2 = limit->p2.p2_slow;
654 } else {
655 if (target < limit->p2.dot_limit)
656 clock.p2 = limit->p2.p2_slow;
657 else
658 clock.p2 = limit->p2.p2_fast;
659 }
660
661 memset(best_clock, 0, sizeof(*best_clock));
662
663 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
664 clock.m1++) {
665 for (clock.m2 = limit->m2.min;
666 clock.m2 <= limit->m2.max; clock.m2++) {
667 for (clock.n = limit->n.min;
668 clock.n <= limit->n.max; clock.n++) {
669 for (clock.p1 = limit->p1.min;
670 clock.p1 <= limit->p1.max; clock.p1++) {
671 int this_err;
672
673 pineview_clock(refclk, &clock);
674 if (!intel_PLL_is_valid(dev, limit,
675 &clock))
676 continue;
677 if (match_clock &&
678 clock.p != match_clock->p)
679 continue;
680
681 this_err = abs(clock.dot - target);
682 if (this_err < err) {
683 *best_clock = clock;
684 err = this_err;
685 }
686 }
687 }
688 }
689 }
690
691 return (err != target);
692 }
693
694 static bool
695 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
696 int target, int refclk, intel_clock_t *match_clock,
697 intel_clock_t *best_clock)
698 {
699 struct drm_device *dev = crtc->dev;
700 intel_clock_t clock;
701 int max_n;
702 bool found;
703 /* approximately equals target * 0.00585 */
704 int err_most = (target >> 8) + (target >> 9);
705 found = false;
706
707 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
708 if (intel_is_dual_link_lvds(dev))
709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
721 /* based on hardware requirement, prefer smaller n to precision */
722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
723 /* based on hardware requirement, prefere larger m1,m2 */
724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
732 i9xx_clock(refclk, &clock);
733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err_most) {
739 *best_clock = clock;
740 err_most = this_err;
741 max_n = clock.n;
742 found = true;
743 }
744 }
745 }
746 }
747 }
748 return found;
749 }
750
751 static bool
752 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
753 int target, int refclk, intel_clock_t *match_clock,
754 intel_clock_t *best_clock)
755 {
756 struct drm_device *dev = crtc->dev;
757 intel_clock_t clock;
758 unsigned int bestppm = 1000000;
759 /* min update 19.2 MHz */
760 int max_n = min(limit->n.max, refclk / 19200);
761 bool found = false;
762
763 target *= 5; /* fast clock */
764
765 memset(best_clock, 0, sizeof(*best_clock));
766
767 /* based on hardware requirement, prefer smaller n to precision */
768 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
769 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
770 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
771 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
772 clock.p = clock.p1 * clock.p2;
773 /* based on hardware requirement, prefer bigger m1,m2 values */
774 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
775 unsigned int ppm, diff;
776
777 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
778 refclk * clock.m1);
779
780 vlv_clock(refclk, &clock);
781
782 if (!intel_PLL_is_valid(dev, limit,
783 &clock))
784 continue;
785
786 diff = abs(clock.dot - target);
787 ppm = div_u64(1000000ULL * diff, target);
788
789 if (ppm < 100 && clock.p > best_clock->p) {
790 bestppm = 0;
791 *best_clock = clock;
792 found = true;
793 }
794
795 if (bestppm >= 10 && ppm < bestppm - 10) {
796 bestppm = ppm;
797 *best_clock = clock;
798 found = true;
799 }
800 }
801 }
802 }
803 }
804
805 return found;
806 }
807
808 static bool
809 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
812 {
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
815 uint64_t m2;
816 int found = false;
817
818 memset(best_clock, 0, sizeof(*best_clock));
819
820 /*
821 * Based on hardware doc, the n always set to 1, and m1 always
822 * set to 2. If requires to support 200Mhz refclk, we need to
823 * revisit this because n may not 1 anymore.
824 */
825 clock.n = 1, clock.m1 = 2;
826 target *= 5; /* fast clock */
827
828 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
829 for (clock.p2 = limit->p2.p2_fast;
830 clock.p2 >= limit->p2.p2_slow;
831 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
832
833 clock.p = clock.p1 * clock.p2;
834
835 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
836 clock.n) << 22, refclk * clock.m1);
837
838 if (m2 > INT_MAX/clock.m1)
839 continue;
840
841 clock.m2 = m2;
842
843 chv_clock(refclk, &clock);
844
845 if (!intel_PLL_is_valid(dev, limit, &clock))
846 continue;
847
848 /* based on hardware requirement, prefer bigger p
849 */
850 if (clock.p > best_clock->p) {
851 *best_clock = clock;
852 found = true;
853 }
854 }
855 }
856
857 return found;
858 }
859
860 bool intel_crtc_active(struct drm_crtc *crtc)
861 {
862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
863
864 /* Be paranoid as we can arrive here with only partial
865 * state retrieved from the hardware during setup.
866 *
867 * We can ditch the adjusted_mode.crtc_clock check as soon
868 * as Haswell has gained clock readout/fastboot support.
869 *
870 * We can ditch the crtc->primary->fb check as soon as we can
871 * properly reconstruct framebuffers.
872 */
873 return intel_crtc->active && crtc->primary->fb &&
874 intel_crtc->config.adjusted_mode.crtc_clock;
875 }
876
877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879 {
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
882
883 return intel_crtc->config.cpu_transcoder;
884 }
885
886 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
887 {
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
890
891 frame = I915_READ(frame_reg);
892
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 WARN(1, "vblank wait timed out\n");
895 }
896
897 /**
898 * intel_wait_for_vblank - wait for vblank on a given pipe
899 * @dev: drm device
900 * @pipe: pipe to wait for
901 *
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
903 * mode setting code.
904 */
905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 int pipestat_reg = PIPESTAT(pipe);
909
910 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
911 g4x_wait_for_vblank(dev, pipe);
912 return;
913 }
914
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
917 *
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
924 * vblanks...
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
927 */
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
930
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
934 50))
935 DRM_DEBUG_KMS("vblank wait timed out\n");
936 }
937
938 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
939 {
940 struct drm_i915_private *dev_priv = dev->dev_private;
941 u32 reg = PIPEDSL(pipe);
942 u32 line1, line2;
943 u32 line_mask;
944
945 if (IS_GEN2(dev))
946 line_mask = DSL_LINEMASK_GEN2;
947 else
948 line_mask = DSL_LINEMASK_GEN3;
949
950 line1 = I915_READ(reg) & line_mask;
951 mdelay(5);
952 line2 = I915_READ(reg) & line_mask;
953
954 return line1 == line2;
955 }
956
957 /*
958 * intel_wait_for_pipe_off - wait for pipe to turn off
959 * @dev: drm device
960 * @pipe: pipe to wait for
961 *
962 * After disabling a pipe, we can't wait for vblank in the usual way,
963 * spinning on the vblank interrupt status bit, since we won't actually
964 * see an interrupt when the pipe is disabled.
965 *
966 * On Gen4 and above:
967 * wait for the pipe register state bit to turn off
968 *
969 * Otherwise:
970 * wait for the display line value to settle (it usually
971 * ends up stopping at the start of the next frame).
972 *
973 */
974 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
975 {
976 struct drm_i915_private *dev_priv = dev->dev_private;
977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
978 pipe);
979
980 if (INTEL_INFO(dev)->gen >= 4) {
981 int reg = PIPECONF(cpu_transcoder);
982
983 /* Wait for the Pipe State to go off */
984 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
985 100))
986 WARN(1, "pipe_off wait timed out\n");
987 } else {
988 /* Wait for the display line to settle */
989 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
990 WARN(1, "pipe_off wait timed out\n");
991 }
992 }
993
994 /*
995 * ibx_digital_port_connected - is the specified port connected?
996 * @dev_priv: i915 private structure
997 * @port: the port to test
998 *
999 * Returns true if @port is connected, false otherwise.
1000 */
1001 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1002 struct intel_digital_port *port)
1003 {
1004 u32 bit;
1005
1006 if (HAS_PCH_IBX(dev_priv->dev)) {
1007 switch (port->port) {
1008 case PORT_B:
1009 bit = SDE_PORTB_HOTPLUG;
1010 break;
1011 case PORT_C:
1012 bit = SDE_PORTC_HOTPLUG;
1013 break;
1014 case PORT_D:
1015 bit = SDE_PORTD_HOTPLUG;
1016 break;
1017 default:
1018 return true;
1019 }
1020 } else {
1021 switch (port->port) {
1022 case PORT_B:
1023 bit = SDE_PORTB_HOTPLUG_CPT;
1024 break;
1025 case PORT_C:
1026 bit = SDE_PORTC_HOTPLUG_CPT;
1027 break;
1028 case PORT_D:
1029 bit = SDE_PORTD_HOTPLUG_CPT;
1030 break;
1031 default:
1032 return true;
1033 }
1034 }
1035
1036 return I915_READ(SDEISR) & bit;
1037 }
1038
1039 static const char *state_string(bool enabled)
1040 {
1041 return enabled ? "on" : "off";
1042 }
1043
1044 /* Only for pre-ILK configs */
1045 void assert_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = DPLL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & DPLL_VCO_ENABLE);
1055 WARN(cur_state != state,
1056 "PLL state assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 /* XXX: the dsi pll is shared between MIPI DSI ports */
1061 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1062 {
1063 u32 val;
1064 bool cur_state;
1065
1066 mutex_lock(&dev_priv->dpio_lock);
1067 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1068 mutex_unlock(&dev_priv->dpio_lock);
1069
1070 cur_state = val & DSI_PLL_VCO_EN;
1071 WARN(cur_state != state,
1072 "DSI PLL state assertion failure (expected %s, current %s)\n",
1073 state_string(state), state_string(cur_state));
1074 }
1075 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1076 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1077
1078 struct intel_shared_dpll *
1079 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1080 {
1081 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1082
1083 if (crtc->config.shared_dpll < 0)
1084 return NULL;
1085
1086 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1087 }
1088
1089 /* For ILK+ */
1090 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1091 struct intel_shared_dpll *pll,
1092 bool state)
1093 {
1094 bool cur_state;
1095 struct intel_dpll_hw_state hw_state;
1096
1097 if (WARN (!pll,
1098 "asserting DPLL %s with no DPLL\n", state_string(state)))
1099 return;
1100
1101 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1102 WARN(cur_state != state,
1103 "%s assertion failure (expected %s, current %s)\n",
1104 pll->name, state_string(state), state_string(cur_state));
1105 }
1106
1107 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1108 enum pipe pipe, bool state)
1109 {
1110 int reg;
1111 u32 val;
1112 bool cur_state;
1113 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1114 pipe);
1115
1116 if (HAS_DDI(dev_priv->dev)) {
1117 /* DDI does not have a specific FDI_TX register */
1118 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1119 val = I915_READ(reg);
1120 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1121 } else {
1122 reg = FDI_TX_CTL(pipe);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & FDI_TX_ENABLE);
1125 }
1126 WARN(cur_state != state,
1127 "FDI TX state assertion failure (expected %s, current %s)\n",
1128 state_string(state), state_string(cur_state));
1129 }
1130 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1131 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1132
1133 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1134 enum pipe pipe, bool state)
1135 {
1136 int reg;
1137 u32 val;
1138 bool cur_state;
1139
1140 reg = FDI_RX_CTL(pipe);
1141 val = I915_READ(reg);
1142 cur_state = !!(val & FDI_RX_ENABLE);
1143 WARN(cur_state != state,
1144 "FDI RX state assertion failure (expected %s, current %s)\n",
1145 state_string(state), state_string(cur_state));
1146 }
1147 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1148 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1149
1150 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1151 enum pipe pipe)
1152 {
1153 int reg;
1154 u32 val;
1155
1156 /* ILK FDI PLL is always enabled */
1157 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1158 return;
1159
1160 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1161 if (HAS_DDI(dev_priv->dev))
1162 return;
1163
1164 reg = FDI_TX_CTL(pipe);
1165 val = I915_READ(reg);
1166 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1167 }
1168
1169 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1170 enum pipe pipe, bool state)
1171 {
1172 int reg;
1173 u32 val;
1174 bool cur_state;
1175
1176 reg = FDI_RX_CTL(pipe);
1177 val = I915_READ(reg);
1178 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1179 WARN(cur_state != state,
1180 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1181 state_string(state), state_string(cur_state));
1182 }
1183
1184 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186 {
1187 int pp_reg, lvds_reg;
1188 u32 val;
1189 enum pipe panel_pipe = PIPE_A;
1190 bool locked = true;
1191
1192 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1193 pp_reg = PCH_PP_CONTROL;
1194 lvds_reg = PCH_LVDS;
1195 } else {
1196 pp_reg = PP_CONTROL;
1197 lvds_reg = LVDS;
1198 }
1199
1200 val = I915_READ(pp_reg);
1201 if (!(val & PANEL_POWER_ON) ||
1202 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1203 locked = false;
1204
1205 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1206 panel_pipe = PIPE_B;
1207
1208 WARN(panel_pipe == pipe && locked,
1209 "panel assertion failure, pipe %c regs locked\n",
1210 pipe_name(pipe));
1211 }
1212
1213 static void assert_cursor(struct drm_i915_private *dev_priv,
1214 enum pipe pipe, bool state)
1215 {
1216 struct drm_device *dev = dev_priv->dev;
1217 bool cur_state;
1218
1219 if (IS_845G(dev) || IS_I865G(dev))
1220 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1221 else
1222 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1223
1224 WARN(cur_state != state,
1225 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1226 pipe_name(pipe), state_string(state), state_string(cur_state));
1227 }
1228 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1229 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1230
1231 void assert_pipe(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
1233 {
1234 int reg;
1235 u32 val;
1236 bool cur_state;
1237 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1238 pipe);
1239
1240 /* if we need the pipe A quirk it must be always on */
1241 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1242 state = true;
1243
1244 if (!intel_display_power_enabled(dev_priv,
1245 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1246 cur_state = false;
1247 } else {
1248 reg = PIPECONF(cpu_transcoder);
1249 val = I915_READ(reg);
1250 cur_state = !!(val & PIPECONF_ENABLE);
1251 }
1252
1253 WARN(cur_state != state,
1254 "pipe %c assertion failure (expected %s, current %s)\n",
1255 pipe_name(pipe), state_string(state), state_string(cur_state));
1256 }
1257
1258 static void assert_plane(struct drm_i915_private *dev_priv,
1259 enum plane plane, bool state)
1260 {
1261 int reg;
1262 u32 val;
1263 bool cur_state;
1264
1265 reg = DSPCNTR(plane);
1266 val = I915_READ(reg);
1267 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1268 WARN(cur_state != state,
1269 "plane %c assertion failure (expected %s, current %s)\n",
1270 plane_name(plane), state_string(state), state_string(cur_state));
1271 }
1272
1273 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1274 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1275
1276 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1277 enum pipe pipe)
1278 {
1279 struct drm_device *dev = dev_priv->dev;
1280 int reg, i;
1281 u32 val;
1282 int cur_pipe;
1283
1284 /* Primary planes are fixed to pipes on gen4+ */
1285 if (INTEL_INFO(dev)->gen >= 4) {
1286 reg = DSPCNTR(pipe);
1287 val = I915_READ(reg);
1288 WARN(val & DISPLAY_PLANE_ENABLE,
1289 "plane %c assertion failure, should be disabled but not\n",
1290 plane_name(pipe));
1291 return;
1292 }
1293
1294 /* Need to check both planes against the pipe */
1295 for_each_pipe(i) {
1296 reg = DSPCNTR(i);
1297 val = I915_READ(reg);
1298 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1299 DISPPLANE_SEL_PIPE_SHIFT;
1300 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1301 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1302 plane_name(i), pipe_name(pipe));
1303 }
1304 }
1305
1306 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe)
1308 {
1309 struct drm_device *dev = dev_priv->dev;
1310 int reg, sprite;
1311 u32 val;
1312
1313 if (IS_VALLEYVIEW(dev)) {
1314 for_each_sprite(pipe, sprite) {
1315 reg = SPCNTR(pipe, sprite);
1316 val = I915_READ(reg);
1317 WARN(val & SP_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 sprite_name(pipe, sprite), pipe_name(pipe));
1320 }
1321 } else if (INTEL_INFO(dev)->gen >= 7) {
1322 reg = SPRCTL(pipe);
1323 val = I915_READ(reg);
1324 WARN(val & SPRITE_ENABLE,
1325 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(pipe), pipe_name(pipe));
1327 } else if (INTEL_INFO(dev)->gen >= 5) {
1328 reg = DVSCNTR(pipe);
1329 val = I915_READ(reg);
1330 WARN(val & DVS_ENABLE,
1331 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1332 plane_name(pipe), pipe_name(pipe));
1333 }
1334 }
1335
1336 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1337 {
1338 u32 val;
1339 bool enabled;
1340
1341 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1342
1343 val = I915_READ(PCH_DREF_CONTROL);
1344 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1345 DREF_SUPERSPREAD_SOURCE_MASK));
1346 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1347 }
1348
1349 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe)
1351 {
1352 int reg;
1353 u32 val;
1354 bool enabled;
1355
1356 reg = PCH_TRANSCONF(pipe);
1357 val = I915_READ(reg);
1358 enabled = !!(val & TRANS_ENABLE);
1359 WARN(enabled,
1360 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1361 pipe_name(pipe));
1362 }
1363
1364 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1365 enum pipe pipe, u32 port_sel, u32 val)
1366 {
1367 if ((val & DP_PORT_EN) == 0)
1368 return false;
1369
1370 if (HAS_PCH_CPT(dev_priv->dev)) {
1371 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1372 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1373 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1374 return false;
1375 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1376 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1377 return false;
1378 } else {
1379 if ((val & DP_PIPE_MASK) != (pipe << 30))
1380 return false;
1381 }
1382 return true;
1383 }
1384
1385 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe, u32 val)
1387 {
1388 if ((val & SDVO_ENABLE) == 0)
1389 return false;
1390
1391 if (HAS_PCH_CPT(dev_priv->dev)) {
1392 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1393 return false;
1394 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1395 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1396 return false;
1397 } else {
1398 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1399 return false;
1400 }
1401 return true;
1402 }
1403
1404 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1405 enum pipe pipe, u32 val)
1406 {
1407 if ((val & LVDS_PORT_EN) == 0)
1408 return false;
1409
1410 if (HAS_PCH_CPT(dev_priv->dev)) {
1411 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1412 return false;
1413 } else {
1414 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1415 return false;
1416 }
1417 return true;
1418 }
1419
1420 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, u32 val)
1422 {
1423 if ((val & ADPA_DAC_ENABLE) == 0)
1424 return false;
1425 if (HAS_PCH_CPT(dev_priv->dev)) {
1426 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1427 return false;
1428 } else {
1429 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1430 return false;
1431 }
1432 return true;
1433 }
1434
1435 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1436 enum pipe pipe, int reg, u32 port_sel)
1437 {
1438 u32 val = I915_READ(reg);
1439 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1440 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1441 reg, pipe_name(pipe));
1442
1443 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1444 && (val & DP_PIPEB_SELECT),
1445 "IBX PCH dp port still using transcoder B\n");
1446 }
1447
1448 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1449 enum pipe pipe, int reg)
1450 {
1451 u32 val = I915_READ(reg);
1452 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1453 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1454 reg, pipe_name(pipe));
1455
1456 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1457 && (val & SDVO_PIPE_B_SELECT),
1458 "IBX PCH hdmi port still using transcoder B\n");
1459 }
1460
1461 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1462 enum pipe pipe)
1463 {
1464 int reg;
1465 u32 val;
1466
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1469 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1470
1471 reg = PCH_ADPA;
1472 val = I915_READ(reg);
1473 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1474 "PCH VGA enabled on transcoder %c, should be disabled\n",
1475 pipe_name(pipe));
1476
1477 reg = PCH_LVDS;
1478 val = I915_READ(reg);
1479 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1480 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1485 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1486 }
1487
1488 static void intel_init_dpio(struct drm_device *dev)
1489 {
1490 struct drm_i915_private *dev_priv = dev->dev_private;
1491
1492 if (!IS_VALLEYVIEW(dev))
1493 return;
1494
1495 /*
1496 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1497 * CHV x1 PHY (DP/HDMI D)
1498 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1499 */
1500 if (IS_CHERRYVIEW(dev)) {
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1502 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1503 } else {
1504 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1505 }
1506 }
1507
1508 static void intel_reset_dpio(struct drm_device *dev)
1509 {
1510 struct drm_i915_private *dev_priv = dev->dev_private;
1511
1512 if (IS_CHERRYVIEW(dev)) {
1513 enum dpio_phy phy;
1514 u32 val;
1515
1516 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1517 /* Poll for phypwrgood signal */
1518 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1519 PHY_POWERGOOD(phy), 1))
1520 DRM_ERROR("Display PHY %d is not power up\n", phy);
1521
1522 /*
1523 * Deassert common lane reset for PHY.
1524 *
1525 * This should only be done on init and resume from S3
1526 * with both PLLs disabled, or we risk losing DPIO and
1527 * PLL synchronization.
1528 */
1529 val = I915_READ(DISPLAY_PHY_CONTROL);
1530 I915_WRITE(DISPLAY_PHY_CONTROL,
1531 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1532 }
1533 }
1534 }
1535
1536 static void vlv_enable_pll(struct intel_crtc *crtc)
1537 {
1538 struct drm_device *dev = crtc->base.dev;
1539 struct drm_i915_private *dev_priv = dev->dev_private;
1540 int reg = DPLL(crtc->pipe);
1541 u32 dpll = crtc->config.dpll_hw_state.dpll;
1542
1543 assert_pipe_disabled(dev_priv, crtc->pipe);
1544
1545 /* No really, not for ILK+ */
1546 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1547
1548 /* PLL is protected by panel, make sure we can write it */
1549 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1550 assert_panel_unlocked(dev_priv, crtc->pipe);
1551
1552 I915_WRITE(reg, dpll);
1553 POSTING_READ(reg);
1554 udelay(150);
1555
1556 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1557 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1558
1559 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1560 POSTING_READ(DPLL_MD(crtc->pipe));
1561
1562 /* We do this three times for luck */
1563 I915_WRITE(reg, dpll);
1564 POSTING_READ(reg);
1565 udelay(150); /* wait for warmup */
1566 I915_WRITE(reg, dpll);
1567 POSTING_READ(reg);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg, dpll);
1570 POSTING_READ(reg);
1571 udelay(150); /* wait for warmup */
1572 }
1573
1574 static void chv_enable_pll(struct intel_crtc *crtc)
1575 {
1576 struct drm_device *dev = crtc->base.dev;
1577 struct drm_i915_private *dev_priv = dev->dev_private;
1578 int pipe = crtc->pipe;
1579 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1580 u32 tmp;
1581
1582 assert_pipe_disabled(dev_priv, crtc->pipe);
1583
1584 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1585
1586 mutex_lock(&dev_priv->dpio_lock);
1587
1588 /* Enable back the 10bit clock to display controller */
1589 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1590 tmp |= DPIO_DCLKP_EN;
1591 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1592
1593 /*
1594 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1595 */
1596 udelay(1);
1597
1598 /* Enable PLL */
1599 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1600
1601 /* Check PLL is locked */
1602 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1603 DRM_ERROR("PLL %d failed to lock\n", pipe);
1604
1605 /* not sure when this should be written */
1606 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1607 POSTING_READ(DPLL_MD(pipe));
1608
1609 mutex_unlock(&dev_priv->dpio_lock);
1610 }
1611
1612 static void i9xx_enable_pll(struct intel_crtc *crtc)
1613 {
1614 struct drm_device *dev = crtc->base.dev;
1615 struct drm_i915_private *dev_priv = dev->dev_private;
1616 int reg = DPLL(crtc->pipe);
1617 u32 dpll = crtc->config.dpll_hw_state.dpll;
1618
1619 assert_pipe_disabled(dev_priv, crtc->pipe);
1620
1621 /* No really, not for ILK+ */
1622 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1623
1624 /* PLL is protected by panel, make sure we can write it */
1625 if (IS_MOBILE(dev) && !IS_I830(dev))
1626 assert_panel_unlocked(dev_priv, crtc->pipe);
1627
1628 I915_WRITE(reg, dpll);
1629
1630 /* Wait for the clocks to stabilize. */
1631 POSTING_READ(reg);
1632 udelay(150);
1633
1634 if (INTEL_INFO(dev)->gen >= 4) {
1635 I915_WRITE(DPLL_MD(crtc->pipe),
1636 crtc->config.dpll_hw_state.dpll_md);
1637 } else {
1638 /* The pixel multiplier can only be updated once the
1639 * DPLL is enabled and the clocks are stable.
1640 *
1641 * So write it again.
1642 */
1643 I915_WRITE(reg, dpll);
1644 }
1645
1646 /* We do this three times for luck */
1647 I915_WRITE(reg, dpll);
1648 POSTING_READ(reg);
1649 udelay(150); /* wait for warmup */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg, dpll);
1654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656 }
1657
1658 /**
1659 * i9xx_disable_pll - disable a PLL
1660 * @dev_priv: i915 private structure
1661 * @pipe: pipe PLL to disable
1662 *
1663 * Disable the PLL for @pipe, making sure the pipe is off first.
1664 *
1665 * Note! This is for pre-ILK only.
1666 */
1667 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1668 {
1669 /* Don't disable pipe A or pipe A PLLs if needed */
1670 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1671 return;
1672
1673 /* Make sure the pipe isn't still relying on us */
1674 assert_pipe_disabled(dev_priv, pipe);
1675
1676 I915_WRITE(DPLL(pipe), 0);
1677 POSTING_READ(DPLL(pipe));
1678 }
1679
1680 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1681 {
1682 u32 val = 0;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
1687 /*
1688 * Leave integrated clock source and reference clock enabled for pipe B.
1689 * The latter is needed for VGA hotplug / manual detection.
1690 */
1691 if (pipe == PIPE_B)
1692 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1693 I915_WRITE(DPLL(pipe), val);
1694 POSTING_READ(DPLL(pipe));
1695
1696 }
1697
1698 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1699 {
1700 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1701 u32 val;
1702
1703 /* Make sure the pipe isn't still relying on us */
1704 assert_pipe_disabled(dev_priv, pipe);
1705
1706 /* Set PLL en = 0 */
1707 val = DPLL_SSC_REF_CLOCK_CHV;
1708 if (pipe != PIPE_A)
1709 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1710 I915_WRITE(DPLL(pipe), val);
1711 POSTING_READ(DPLL(pipe));
1712
1713 mutex_lock(&dev_priv->dpio_lock);
1714
1715 /* Disable 10bit clock to display controller */
1716 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1717 val &= ~DPIO_DCLKP_EN;
1718 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1719
1720 /* disable left/right clock distribution */
1721 if (pipe != PIPE_B) {
1722 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1723 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1724 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1725 } else {
1726 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1727 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1728 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1729 }
1730
1731 mutex_unlock(&dev_priv->dpio_lock);
1732 }
1733
1734 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1735 struct intel_digital_port *dport)
1736 {
1737 u32 port_mask;
1738 int dpll_reg;
1739
1740 switch (dport->port) {
1741 case PORT_B:
1742 port_mask = DPLL_PORTB_READY_MASK;
1743 dpll_reg = DPLL(0);
1744 break;
1745 case PORT_C:
1746 port_mask = DPLL_PORTC_READY_MASK;
1747 dpll_reg = DPLL(0);
1748 break;
1749 case PORT_D:
1750 port_mask = DPLL_PORTD_READY_MASK;
1751 dpll_reg = DPIO_PHY_STATUS;
1752 break;
1753 default:
1754 BUG();
1755 }
1756
1757 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1758 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1759 port_name(dport->port), I915_READ(dpll_reg));
1760 }
1761
1762 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1763 {
1764 struct drm_device *dev = crtc->base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1767
1768 if (WARN_ON(pll == NULL))
1769 return;
1770
1771 WARN_ON(!pll->refcount);
1772 if (pll->active == 0) {
1773 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1774 WARN_ON(pll->on);
1775 assert_shared_dpll_disabled(dev_priv, pll);
1776
1777 pll->mode_set(dev_priv, pll);
1778 }
1779 }
1780
1781 /**
1782 * intel_enable_shared_dpll - enable PCH PLL
1783 * @dev_priv: i915 private structure
1784 * @pipe: pipe PLL to enable
1785 *
1786 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1787 * drives the transcoder clock.
1788 */
1789 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1790 {
1791 struct drm_device *dev = crtc->base.dev;
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1793 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1794
1795 if (WARN_ON(pll == NULL))
1796 return;
1797
1798 if (WARN_ON(pll->refcount == 0))
1799 return;
1800
1801 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1802 pll->name, pll->active, pll->on,
1803 crtc->base.base.id);
1804
1805 if (pll->active++) {
1806 WARN_ON(!pll->on);
1807 assert_shared_dpll_enabled(dev_priv, pll);
1808 return;
1809 }
1810 WARN_ON(pll->on);
1811
1812 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1813
1814 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1815 pll->enable(dev_priv, pll);
1816 pll->on = true;
1817 }
1818
1819 void intel_disable_shared_dpll(struct intel_crtc *crtc)
1820 {
1821 struct drm_device *dev = crtc->base.dev;
1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1824
1825 /* PCH only available on ILK+ */
1826 BUG_ON(INTEL_INFO(dev)->gen < 5);
1827 if (WARN_ON(pll == NULL))
1828 return;
1829
1830 if (WARN_ON(pll->refcount == 0))
1831 return;
1832
1833 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1834 pll->name, pll->active, pll->on,
1835 crtc->base.base.id);
1836
1837 if (WARN_ON(pll->active == 0)) {
1838 assert_shared_dpll_disabled(dev_priv, pll);
1839 return;
1840 }
1841
1842 assert_shared_dpll_enabled(dev_priv, pll);
1843 WARN_ON(!pll->on);
1844 if (--pll->active)
1845 return;
1846
1847 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1848 pll->disable(dev_priv, pll);
1849 pll->on = false;
1850
1851 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1852 }
1853
1854 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1855 enum pipe pipe)
1856 {
1857 struct drm_device *dev = dev_priv->dev;
1858 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1860 uint32_t reg, val, pipeconf_val;
1861
1862 /* PCH only available on ILK+ */
1863 BUG_ON(INTEL_INFO(dev)->gen < 5);
1864
1865 /* Make sure PCH DPLL is enabled */
1866 assert_shared_dpll_enabled(dev_priv,
1867 intel_crtc_to_shared_dpll(intel_crtc));
1868
1869 /* FDI must be feeding us bits for PCH ports */
1870 assert_fdi_tx_enabled(dev_priv, pipe);
1871 assert_fdi_rx_enabled(dev_priv, pipe);
1872
1873 if (HAS_PCH_CPT(dev)) {
1874 /* Workaround: Set the timing override bit before enabling the
1875 * pch transcoder. */
1876 reg = TRANS_CHICKEN2(pipe);
1877 val = I915_READ(reg);
1878 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1879 I915_WRITE(reg, val);
1880 }
1881
1882 reg = PCH_TRANSCONF(pipe);
1883 val = I915_READ(reg);
1884 pipeconf_val = I915_READ(PIPECONF(pipe));
1885
1886 if (HAS_PCH_IBX(dev_priv->dev)) {
1887 /*
1888 * make the BPC in transcoder be consistent with
1889 * that in pipeconf reg.
1890 */
1891 val &= ~PIPECONF_BPC_MASK;
1892 val |= pipeconf_val & PIPECONF_BPC_MASK;
1893 }
1894
1895 val &= ~TRANS_INTERLACE_MASK;
1896 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1897 if (HAS_PCH_IBX(dev_priv->dev) &&
1898 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1899 val |= TRANS_LEGACY_INTERLACED_ILK;
1900 else
1901 val |= TRANS_INTERLACED;
1902 else
1903 val |= TRANS_PROGRESSIVE;
1904
1905 I915_WRITE(reg, val | TRANS_ENABLE);
1906 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1907 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1908 }
1909
1910 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1911 enum transcoder cpu_transcoder)
1912 {
1913 u32 val, pipeconf_val;
1914
1915 /* PCH only available on ILK+ */
1916 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1917
1918 /* FDI must be feeding us bits for PCH ports */
1919 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1920 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1921
1922 /* Workaround: set timing override bit. */
1923 val = I915_READ(_TRANSA_CHICKEN2);
1924 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1925 I915_WRITE(_TRANSA_CHICKEN2, val);
1926
1927 val = TRANS_ENABLE;
1928 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1929
1930 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1931 PIPECONF_INTERLACED_ILK)
1932 val |= TRANS_INTERLACED;
1933 else
1934 val |= TRANS_PROGRESSIVE;
1935
1936 I915_WRITE(LPT_TRANSCONF, val);
1937 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1938 DRM_ERROR("Failed to enable PCH transcoder\n");
1939 }
1940
1941 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1942 enum pipe pipe)
1943 {
1944 struct drm_device *dev = dev_priv->dev;
1945 uint32_t reg, val;
1946
1947 /* FDI relies on the transcoder */
1948 assert_fdi_tx_disabled(dev_priv, pipe);
1949 assert_fdi_rx_disabled(dev_priv, pipe);
1950
1951 /* Ports must be off as well */
1952 assert_pch_ports_disabled(dev_priv, pipe);
1953
1954 reg = PCH_TRANSCONF(pipe);
1955 val = I915_READ(reg);
1956 val &= ~TRANS_ENABLE;
1957 I915_WRITE(reg, val);
1958 /* wait for PCH transcoder off, transcoder state */
1959 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1960 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1961
1962 if (!HAS_PCH_IBX(dev)) {
1963 /* Workaround: Clear the timing override chicken bit again. */
1964 reg = TRANS_CHICKEN2(pipe);
1965 val = I915_READ(reg);
1966 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1967 I915_WRITE(reg, val);
1968 }
1969 }
1970
1971 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1972 {
1973 u32 val;
1974
1975 val = I915_READ(LPT_TRANSCONF);
1976 val &= ~TRANS_ENABLE;
1977 I915_WRITE(LPT_TRANSCONF, val);
1978 /* wait for PCH transcoder off, transcoder state */
1979 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1980 DRM_ERROR("Failed to disable PCH transcoder\n");
1981
1982 /* Workaround: clear timing override bit. */
1983 val = I915_READ(_TRANSA_CHICKEN2);
1984 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1985 I915_WRITE(_TRANSA_CHICKEN2, val);
1986 }
1987
1988 /**
1989 * intel_enable_pipe - enable a pipe, asserting requirements
1990 * @crtc: crtc responsible for the pipe
1991 *
1992 * Enable @crtc's pipe, making sure that various hardware specific requirements
1993 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1994 */
1995 static void intel_enable_pipe(struct intel_crtc *crtc)
1996 {
1997 struct drm_device *dev = crtc->base.dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 enum pipe pipe = crtc->pipe;
2000 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2001 pipe);
2002 enum pipe pch_transcoder;
2003 int reg;
2004 u32 val;
2005
2006 assert_planes_disabled(dev_priv, pipe);
2007 assert_cursor_disabled(dev_priv, pipe);
2008 assert_sprites_disabled(dev_priv, pipe);
2009
2010 if (HAS_PCH_LPT(dev_priv->dev))
2011 pch_transcoder = TRANSCODER_A;
2012 else
2013 pch_transcoder = pipe;
2014
2015 /*
2016 * A pipe without a PLL won't actually be able to drive bits from
2017 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2018 * need the check.
2019 */
2020 if (!HAS_PCH_SPLIT(dev_priv->dev))
2021 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2022 assert_dsi_pll_enabled(dev_priv);
2023 else
2024 assert_pll_enabled(dev_priv, pipe);
2025 else {
2026 if (crtc->config.has_pch_encoder) {
2027 /* if driving the PCH, we need FDI enabled */
2028 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2029 assert_fdi_tx_pll_enabled(dev_priv,
2030 (enum pipe) cpu_transcoder);
2031 }
2032 /* FIXME: assert CPU port conditions for SNB+ */
2033 }
2034
2035 reg = PIPECONF(cpu_transcoder);
2036 val = I915_READ(reg);
2037 if (val & PIPECONF_ENABLE) {
2038 WARN_ON(!(pipe == PIPE_A &&
2039 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2040 return;
2041 }
2042
2043 I915_WRITE(reg, val | PIPECONF_ENABLE);
2044 POSTING_READ(reg);
2045 }
2046
2047 /**
2048 * intel_disable_pipe - disable a pipe, asserting requirements
2049 * @dev_priv: i915 private structure
2050 * @pipe: pipe to disable
2051 *
2052 * Disable @pipe, making sure that various hardware specific requirements
2053 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2054 *
2055 * @pipe should be %PIPE_A or %PIPE_B.
2056 *
2057 * Will wait until the pipe has shut down before returning.
2058 */
2059 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
2061 {
2062 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2063 pipe);
2064 int reg;
2065 u32 val;
2066
2067 /*
2068 * Make sure planes won't keep trying to pump pixels to us,
2069 * or we might hang the display.
2070 */
2071 assert_planes_disabled(dev_priv, pipe);
2072 assert_cursor_disabled(dev_priv, pipe);
2073 assert_sprites_disabled(dev_priv, pipe);
2074
2075 /* Don't disable pipe A or pipe A PLLs if needed */
2076 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2077 return;
2078
2079 reg = PIPECONF(cpu_transcoder);
2080 val = I915_READ(reg);
2081 if ((val & PIPECONF_ENABLE) == 0)
2082 return;
2083
2084 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2085 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2086 }
2087
2088 /*
2089 * Plane regs are double buffered, going from enabled->disabled needs a
2090 * trigger in order to latch. The display address reg provides this.
2091 */
2092 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2093 enum plane plane)
2094 {
2095 struct drm_device *dev = dev_priv->dev;
2096 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2097
2098 I915_WRITE(reg, I915_READ(reg));
2099 POSTING_READ(reg);
2100 }
2101
2102 /**
2103 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2104 * @dev_priv: i915 private structure
2105 * @plane: plane to enable
2106 * @pipe: pipe being fed
2107 *
2108 * Enable @plane on @pipe, making sure that @pipe is running first.
2109 */
2110 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane, enum pipe pipe)
2112 {
2113 struct drm_device *dev = dev_priv->dev;
2114 struct intel_crtc *intel_crtc =
2115 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2116 int reg;
2117 u32 val;
2118
2119 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2120 assert_pipe_enabled(dev_priv, pipe);
2121
2122 if (intel_crtc->primary_enabled)
2123 return;
2124
2125 intel_crtc->primary_enabled = true;
2126
2127 reg = DSPCNTR(plane);
2128 val = I915_READ(reg);
2129 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2130
2131 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2132 intel_flush_primary_plane(dev_priv, plane);
2133
2134 /*
2135 * BDW signals flip done immediately if the plane
2136 * is disabled, even if the plane enable is already
2137 * armed to occur at the next vblank :(
2138 */
2139 if (IS_BROADWELL(dev))
2140 intel_wait_for_vblank(dev, intel_crtc->pipe);
2141 }
2142
2143 /**
2144 * intel_disable_primary_hw_plane - disable the primary hardware plane
2145 * @dev_priv: i915 private structure
2146 * @plane: plane to disable
2147 * @pipe: pipe consuming the data
2148 *
2149 * Disable @plane; should be an independent operation.
2150 */
2151 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2152 enum plane plane, enum pipe pipe)
2153 {
2154 struct intel_crtc *intel_crtc =
2155 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2156 int reg;
2157 u32 val;
2158
2159 if (!intel_crtc->primary_enabled)
2160 return;
2161
2162 intel_crtc->primary_enabled = false;
2163
2164 reg = DSPCNTR(plane);
2165 val = I915_READ(reg);
2166 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2167
2168 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2169 intel_flush_primary_plane(dev_priv, plane);
2170 }
2171
2172 static bool need_vtd_wa(struct drm_device *dev)
2173 {
2174 #ifdef CONFIG_INTEL_IOMMU
2175 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2176 return true;
2177 #endif
2178 return false;
2179 }
2180
2181 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2182 {
2183 int tile_height;
2184
2185 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2186 return ALIGN(height, tile_height);
2187 }
2188
2189 int
2190 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2191 struct drm_i915_gem_object *obj,
2192 struct intel_engine_cs *pipelined)
2193 {
2194 struct drm_i915_private *dev_priv = dev->dev_private;
2195 u32 alignment;
2196 int ret;
2197
2198 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2199
2200 switch (obj->tiling_mode) {
2201 case I915_TILING_NONE:
2202 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2203 alignment = 128 * 1024;
2204 else if (INTEL_INFO(dev)->gen >= 4)
2205 alignment = 4 * 1024;
2206 else
2207 alignment = 64 * 1024;
2208 break;
2209 case I915_TILING_X:
2210 /* pin() will align the object as required by fence */
2211 alignment = 0;
2212 break;
2213 case I915_TILING_Y:
2214 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2215 return -EINVAL;
2216 default:
2217 BUG();
2218 }
2219
2220 /* Note that the w/a also requires 64 PTE of padding following the
2221 * bo. We currently fill all unused PTE with the shadow page and so
2222 * we should always have valid PTE following the scanout preventing
2223 * the VT-d warning.
2224 */
2225 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2226 alignment = 256 * 1024;
2227
2228 dev_priv->mm.interruptible = false;
2229 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2230 if (ret)
2231 goto err_interruptible;
2232
2233 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2234 * fence, whereas 965+ only requires a fence if using
2235 * framebuffer compression. For simplicity, we always install
2236 * a fence as the cost is not that onerous.
2237 */
2238 ret = i915_gem_object_get_fence(obj);
2239 if (ret)
2240 goto err_unpin;
2241
2242 i915_gem_object_pin_fence(obj);
2243
2244 dev_priv->mm.interruptible = true;
2245 return 0;
2246
2247 err_unpin:
2248 i915_gem_object_unpin_from_display_plane(obj);
2249 err_interruptible:
2250 dev_priv->mm.interruptible = true;
2251 return ret;
2252 }
2253
2254 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2255 {
2256 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2257
2258 i915_gem_object_unpin_fence(obj);
2259 i915_gem_object_unpin_from_display_plane(obj);
2260 }
2261
2262 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2263 * is assumed to be a power-of-two. */
2264 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2265 unsigned int tiling_mode,
2266 unsigned int cpp,
2267 unsigned int pitch)
2268 {
2269 if (tiling_mode != I915_TILING_NONE) {
2270 unsigned int tile_rows, tiles;
2271
2272 tile_rows = *y / 8;
2273 *y %= 8;
2274
2275 tiles = *x / (512/cpp);
2276 *x %= 512/cpp;
2277
2278 return tile_rows * pitch * 8 + tiles * 4096;
2279 } else {
2280 unsigned int offset;
2281
2282 offset = *y * pitch + *x * cpp;
2283 *y = 0;
2284 *x = (offset & 4095) / cpp;
2285 return offset & -4096;
2286 }
2287 }
2288
2289 int intel_format_to_fourcc(int format)
2290 {
2291 switch (format) {
2292 case DISPPLANE_8BPP:
2293 return DRM_FORMAT_C8;
2294 case DISPPLANE_BGRX555:
2295 return DRM_FORMAT_XRGB1555;
2296 case DISPPLANE_BGRX565:
2297 return DRM_FORMAT_RGB565;
2298 default:
2299 case DISPPLANE_BGRX888:
2300 return DRM_FORMAT_XRGB8888;
2301 case DISPPLANE_RGBX888:
2302 return DRM_FORMAT_XBGR8888;
2303 case DISPPLANE_BGRX101010:
2304 return DRM_FORMAT_XRGB2101010;
2305 case DISPPLANE_RGBX101010:
2306 return DRM_FORMAT_XBGR2101010;
2307 }
2308 }
2309
2310 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2311 struct intel_plane_config *plane_config)
2312 {
2313 struct drm_device *dev = crtc->base.dev;
2314 struct drm_i915_gem_object *obj = NULL;
2315 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2316 u32 base = plane_config->base;
2317
2318 if (plane_config->size == 0)
2319 return false;
2320
2321 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2322 plane_config->size);
2323 if (!obj)
2324 return false;
2325
2326 if (plane_config->tiled) {
2327 obj->tiling_mode = I915_TILING_X;
2328 obj->stride = crtc->base.primary->fb->pitches[0];
2329 }
2330
2331 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2332 mode_cmd.width = crtc->base.primary->fb->width;
2333 mode_cmd.height = crtc->base.primary->fb->height;
2334 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2335
2336 mutex_lock(&dev->struct_mutex);
2337
2338 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2339 &mode_cmd, obj)) {
2340 DRM_DEBUG_KMS("intel fb init failed\n");
2341 goto out_unref_obj;
2342 }
2343
2344 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2345 mutex_unlock(&dev->struct_mutex);
2346
2347 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2348 return true;
2349
2350 out_unref_obj:
2351 drm_gem_object_unreference(&obj->base);
2352 mutex_unlock(&dev->struct_mutex);
2353 return false;
2354 }
2355
2356 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2357 struct intel_plane_config *plane_config)
2358 {
2359 struct drm_device *dev = intel_crtc->base.dev;
2360 struct drm_crtc *c;
2361 struct intel_crtc *i;
2362 struct drm_i915_gem_object *obj;
2363
2364 if (!intel_crtc->base.primary->fb)
2365 return;
2366
2367 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2368 return;
2369
2370 kfree(intel_crtc->base.primary->fb);
2371 intel_crtc->base.primary->fb = NULL;
2372
2373 /*
2374 * Failed to alloc the obj, check to see if we should share
2375 * an fb with another CRTC instead
2376 */
2377 for_each_crtc(dev, c) {
2378 i = to_intel_crtc(c);
2379
2380 if (c == &intel_crtc->base)
2381 continue;
2382
2383 if (!i->active)
2384 continue;
2385
2386 obj = intel_fb_obj(c->primary->fb);
2387 if (obj == NULL)
2388 continue;
2389
2390 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2391 drm_framebuffer_reference(c->primary->fb);
2392 intel_crtc->base.primary->fb = c->primary->fb;
2393 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2394 break;
2395 }
2396 }
2397 }
2398
2399 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2400 struct drm_framebuffer *fb,
2401 int x, int y)
2402 {
2403 struct drm_device *dev = crtc->dev;
2404 struct drm_i915_private *dev_priv = dev->dev_private;
2405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2406 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2407 int plane = intel_crtc->plane;
2408 unsigned long linear_offset;
2409 u32 dspcntr;
2410 u32 reg;
2411
2412 reg = DSPCNTR(plane);
2413 dspcntr = I915_READ(reg);
2414 /* Mask out pixel format bits in case we change it */
2415 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2416 switch (fb->pixel_format) {
2417 case DRM_FORMAT_C8:
2418 dspcntr |= DISPPLANE_8BPP;
2419 break;
2420 case DRM_FORMAT_XRGB1555:
2421 case DRM_FORMAT_ARGB1555:
2422 dspcntr |= DISPPLANE_BGRX555;
2423 break;
2424 case DRM_FORMAT_RGB565:
2425 dspcntr |= DISPPLANE_BGRX565;
2426 break;
2427 case DRM_FORMAT_XRGB8888:
2428 case DRM_FORMAT_ARGB8888:
2429 dspcntr |= DISPPLANE_BGRX888;
2430 break;
2431 case DRM_FORMAT_XBGR8888:
2432 case DRM_FORMAT_ABGR8888:
2433 dspcntr |= DISPPLANE_RGBX888;
2434 break;
2435 case DRM_FORMAT_XRGB2101010:
2436 case DRM_FORMAT_ARGB2101010:
2437 dspcntr |= DISPPLANE_BGRX101010;
2438 break;
2439 case DRM_FORMAT_XBGR2101010:
2440 case DRM_FORMAT_ABGR2101010:
2441 dspcntr |= DISPPLANE_RGBX101010;
2442 break;
2443 default:
2444 BUG();
2445 }
2446
2447 if (INTEL_INFO(dev)->gen >= 4) {
2448 if (obj->tiling_mode != I915_TILING_NONE)
2449 dspcntr |= DISPPLANE_TILED;
2450 else
2451 dspcntr &= ~DISPPLANE_TILED;
2452 }
2453
2454 if (IS_G4X(dev))
2455 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2456
2457 I915_WRITE(reg, dspcntr);
2458
2459 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2460
2461 if (INTEL_INFO(dev)->gen >= 4) {
2462 intel_crtc->dspaddr_offset =
2463 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2464 fb->bits_per_pixel / 8,
2465 fb->pitches[0]);
2466 linear_offset -= intel_crtc->dspaddr_offset;
2467 } else {
2468 intel_crtc->dspaddr_offset = linear_offset;
2469 }
2470
2471 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2472 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2473 fb->pitches[0]);
2474 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2475 if (INTEL_INFO(dev)->gen >= 4) {
2476 I915_WRITE(DSPSURF(plane),
2477 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2478 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2479 I915_WRITE(DSPLINOFF(plane), linear_offset);
2480 } else
2481 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2482 POSTING_READ(reg);
2483 }
2484
2485 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2486 struct drm_framebuffer *fb,
2487 int x, int y)
2488 {
2489 struct drm_device *dev = crtc->dev;
2490 struct drm_i915_private *dev_priv = dev->dev_private;
2491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2492 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2493 int plane = intel_crtc->plane;
2494 unsigned long linear_offset;
2495 u32 dspcntr;
2496 u32 reg;
2497
2498 reg = DSPCNTR(plane);
2499 dspcntr = I915_READ(reg);
2500 /* Mask out pixel format bits in case we change it */
2501 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2502 switch (fb->pixel_format) {
2503 case DRM_FORMAT_C8:
2504 dspcntr |= DISPPLANE_8BPP;
2505 break;
2506 case DRM_FORMAT_RGB565:
2507 dspcntr |= DISPPLANE_BGRX565;
2508 break;
2509 case DRM_FORMAT_XRGB8888:
2510 case DRM_FORMAT_ARGB8888:
2511 dspcntr |= DISPPLANE_BGRX888;
2512 break;
2513 case DRM_FORMAT_XBGR8888:
2514 case DRM_FORMAT_ABGR8888:
2515 dspcntr |= DISPPLANE_RGBX888;
2516 break;
2517 case DRM_FORMAT_XRGB2101010:
2518 case DRM_FORMAT_ARGB2101010:
2519 dspcntr |= DISPPLANE_BGRX101010;
2520 break;
2521 case DRM_FORMAT_XBGR2101010:
2522 case DRM_FORMAT_ABGR2101010:
2523 dspcntr |= DISPPLANE_RGBX101010;
2524 break;
2525 default:
2526 BUG();
2527 }
2528
2529 if (obj->tiling_mode != I915_TILING_NONE)
2530 dspcntr |= DISPPLANE_TILED;
2531 else
2532 dspcntr &= ~DISPPLANE_TILED;
2533
2534 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2535 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2536 else
2537 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2538
2539 I915_WRITE(reg, dspcntr);
2540
2541 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2542 intel_crtc->dspaddr_offset =
2543 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2544 fb->bits_per_pixel / 8,
2545 fb->pitches[0]);
2546 linear_offset -= intel_crtc->dspaddr_offset;
2547
2548 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2549 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2550 fb->pitches[0]);
2551 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2555 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2556 } else {
2557 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2558 I915_WRITE(DSPLINOFF(plane), linear_offset);
2559 }
2560 POSTING_READ(reg);
2561 }
2562
2563 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2564 static int
2565 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2566 int x, int y, enum mode_set_atomic state)
2567 {
2568 struct drm_device *dev = crtc->dev;
2569 struct drm_i915_private *dev_priv = dev->dev_private;
2570
2571 if (dev_priv->display.disable_fbc)
2572 dev_priv->display.disable_fbc(dev);
2573 intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe);
2574
2575 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2576
2577 return 0;
2578 }
2579
2580 void intel_display_handle_reset(struct drm_device *dev)
2581 {
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583 struct drm_crtc *crtc;
2584
2585 /*
2586 * Flips in the rings have been nuked by the reset,
2587 * so complete all pending flips so that user space
2588 * will get its events and not get stuck.
2589 *
2590 * Also update the base address of all primary
2591 * planes to the the last fb to make sure we're
2592 * showing the correct fb after a reset.
2593 *
2594 * Need to make two loops over the crtcs so that we
2595 * don't try to grab a crtc mutex before the
2596 * pending_flip_queue really got woken up.
2597 */
2598
2599 for_each_crtc(dev, crtc) {
2600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2601 enum plane plane = intel_crtc->plane;
2602
2603 intel_prepare_page_flip(dev, plane);
2604 intel_finish_page_flip_plane(dev, plane);
2605 }
2606
2607 for_each_crtc(dev, crtc) {
2608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2609
2610 drm_modeset_lock(&crtc->mutex, NULL);
2611 /*
2612 * FIXME: Once we have proper support for primary planes (and
2613 * disabling them without disabling the entire crtc) allow again
2614 * a NULL crtc->primary->fb.
2615 */
2616 if (intel_crtc->active && crtc->primary->fb)
2617 dev_priv->display.update_primary_plane(crtc,
2618 crtc->primary->fb,
2619 crtc->x,
2620 crtc->y);
2621 drm_modeset_unlock(&crtc->mutex);
2622 }
2623 }
2624
2625 static int
2626 intel_finish_fb(struct drm_framebuffer *old_fb)
2627 {
2628 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2629 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2630 bool was_interruptible = dev_priv->mm.interruptible;
2631 int ret;
2632
2633 /* Big Hammer, we also need to ensure that any pending
2634 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2635 * current scanout is retired before unpinning the old
2636 * framebuffer.
2637 *
2638 * This should only fail upon a hung GPU, in which case we
2639 * can safely continue.
2640 */
2641 dev_priv->mm.interruptible = false;
2642 ret = i915_gem_object_finish_gpu(obj);
2643 dev_priv->mm.interruptible = was_interruptible;
2644
2645 return ret;
2646 }
2647
2648 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2649 {
2650 struct drm_device *dev = crtc->dev;
2651 struct drm_i915_private *dev_priv = dev->dev_private;
2652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2653 unsigned long flags;
2654 bool pending;
2655
2656 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2657 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2658 return false;
2659
2660 spin_lock_irqsave(&dev->event_lock, flags);
2661 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2662 spin_unlock_irqrestore(&dev->event_lock, flags);
2663
2664 return pending;
2665 }
2666
2667 static int
2668 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2669 struct drm_framebuffer *fb)
2670 {
2671 struct drm_device *dev = crtc->dev;
2672 struct drm_i915_private *dev_priv = dev->dev_private;
2673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2674 enum pipe pipe = intel_crtc->pipe;
2675 struct drm_framebuffer *old_fb = crtc->primary->fb;
2676 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2677 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2678 int ret;
2679
2680 if (intel_crtc_has_pending_flip(crtc)) {
2681 DRM_ERROR("pipe is still busy with an old pageflip\n");
2682 return -EBUSY;
2683 }
2684
2685 /* no fb bound */
2686 if (!fb) {
2687 DRM_ERROR("No FB bound\n");
2688 return 0;
2689 }
2690
2691 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2692 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2693 plane_name(intel_crtc->plane),
2694 INTEL_INFO(dev)->num_pipes);
2695 return -EINVAL;
2696 }
2697
2698 mutex_lock(&dev->struct_mutex);
2699 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
2700 if (ret == 0)
2701 i915_gem_track_fb(old_obj, obj,
2702 INTEL_FRONTBUFFER_PRIMARY(pipe));
2703 mutex_unlock(&dev->struct_mutex);
2704 if (ret != 0) {
2705 DRM_ERROR("pin & fence failed\n");
2706 return ret;
2707 }
2708
2709 /*
2710 * Update pipe size and adjust fitter if needed: the reason for this is
2711 * that in compute_mode_changes we check the native mode (not the pfit
2712 * mode) to see if we can flip rather than do a full mode set. In the
2713 * fastboot case, we'll flip, but if we don't update the pipesrc and
2714 * pfit state, we'll end up with a big fb scanned out into the wrong
2715 * sized surface.
2716 *
2717 * To fix this properly, we need to hoist the checks up into
2718 * compute_mode_changes (or above), check the actual pfit state and
2719 * whether the platform allows pfit disable with pipe active, and only
2720 * then update the pipesrc and pfit state, even on the flip path.
2721 */
2722 if (i915.fastboot) {
2723 const struct drm_display_mode *adjusted_mode =
2724 &intel_crtc->config.adjusted_mode;
2725
2726 I915_WRITE(PIPESRC(intel_crtc->pipe),
2727 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2728 (adjusted_mode->crtc_vdisplay - 1));
2729 if (!intel_crtc->config.pch_pfit.enabled &&
2730 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2731 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2732 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2733 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2734 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2735 }
2736 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2737 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2738 }
2739
2740 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2741
2742 if (intel_crtc->active)
2743 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2744
2745 crtc->primary->fb = fb;
2746 crtc->x = x;
2747 crtc->y = y;
2748
2749 if (old_fb) {
2750 if (intel_crtc->active && old_fb != fb)
2751 intel_wait_for_vblank(dev, intel_crtc->pipe);
2752 mutex_lock(&dev->struct_mutex);
2753 intel_unpin_fb_obj(old_obj);
2754 mutex_unlock(&dev->struct_mutex);
2755 }
2756
2757 mutex_lock(&dev->struct_mutex);
2758 intel_update_fbc(dev);
2759 mutex_unlock(&dev->struct_mutex);
2760
2761 return 0;
2762 }
2763
2764 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2765 {
2766 struct drm_device *dev = crtc->dev;
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2769 int pipe = intel_crtc->pipe;
2770 u32 reg, temp;
2771
2772 /* enable normal train */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 if (IS_IVYBRIDGE(dev)) {
2776 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2777 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2778 } else {
2779 temp &= ~FDI_LINK_TRAIN_NONE;
2780 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2781 }
2782 I915_WRITE(reg, temp);
2783
2784 reg = FDI_RX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 if (HAS_PCH_CPT(dev)) {
2787 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2788 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2789 } else {
2790 temp &= ~FDI_LINK_TRAIN_NONE;
2791 temp |= FDI_LINK_TRAIN_NONE;
2792 }
2793 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2794
2795 /* wait one idle pattern time */
2796 POSTING_READ(reg);
2797 udelay(1000);
2798
2799 /* IVB wants error correction enabled */
2800 if (IS_IVYBRIDGE(dev))
2801 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2802 FDI_FE_ERRC_ENABLE);
2803 }
2804
2805 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2806 {
2807 return crtc->base.enabled && crtc->active &&
2808 crtc->config.has_pch_encoder;
2809 }
2810
2811 static void ivb_modeset_global_resources(struct drm_device *dev)
2812 {
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *pipe_B_crtc =
2815 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2816 struct intel_crtc *pipe_C_crtc =
2817 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2818 uint32_t temp;
2819
2820 /*
2821 * When everything is off disable fdi C so that we could enable fdi B
2822 * with all lanes. Note that we don't care about enabled pipes without
2823 * an enabled pch encoder.
2824 */
2825 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2826 !pipe_has_enabled_pch(pipe_C_crtc)) {
2827 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2828 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2829
2830 temp = I915_READ(SOUTH_CHICKEN1);
2831 temp &= ~FDI_BC_BIFURCATION_SELECT;
2832 DRM_DEBUG_KMS("disabling fdi C rx\n");
2833 I915_WRITE(SOUTH_CHICKEN1, temp);
2834 }
2835 }
2836
2837 /* The FDI link training functions for ILK/Ibexpeak. */
2838 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2839 {
2840 struct drm_device *dev = crtc->dev;
2841 struct drm_i915_private *dev_priv = dev->dev_private;
2842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2843 int pipe = intel_crtc->pipe;
2844 u32 reg, temp, tries;
2845
2846 /* FDI needs bits from pipe first */
2847 assert_pipe_enabled(dev_priv, pipe);
2848
2849 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2850 for train result */
2851 reg = FDI_RX_IMR(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_RX_SYMBOL_LOCK;
2854 temp &= ~FDI_RX_BIT_LOCK;
2855 I915_WRITE(reg, temp);
2856 I915_READ(reg);
2857 udelay(150);
2858
2859 /* enable CPU FDI TX and PCH FDI RX */
2860 reg = FDI_TX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2863 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2864 temp &= ~FDI_LINK_TRAIN_NONE;
2865 temp |= FDI_LINK_TRAIN_PATTERN_1;
2866 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2867
2868 reg = FDI_RX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 temp &= ~FDI_LINK_TRAIN_NONE;
2871 temp |= FDI_LINK_TRAIN_PATTERN_1;
2872 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2873
2874 POSTING_READ(reg);
2875 udelay(150);
2876
2877 /* Ironlake workaround, enable clock pointer after FDI enable*/
2878 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2879 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2880 FDI_RX_PHASE_SYNC_POINTER_EN);
2881
2882 reg = FDI_RX_IIR(pipe);
2883 for (tries = 0; tries < 5; tries++) {
2884 temp = I915_READ(reg);
2885 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2886
2887 if ((temp & FDI_RX_BIT_LOCK)) {
2888 DRM_DEBUG_KMS("FDI train 1 done.\n");
2889 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2890 break;
2891 }
2892 }
2893 if (tries == 5)
2894 DRM_ERROR("FDI train 1 fail!\n");
2895
2896 /* Train 2 */
2897 reg = FDI_TX_CTL(pipe);
2898 temp = I915_READ(reg);
2899 temp &= ~FDI_LINK_TRAIN_NONE;
2900 temp |= FDI_LINK_TRAIN_PATTERN_2;
2901 I915_WRITE(reg, temp);
2902
2903 reg = FDI_RX_CTL(pipe);
2904 temp = I915_READ(reg);
2905 temp &= ~FDI_LINK_TRAIN_NONE;
2906 temp |= FDI_LINK_TRAIN_PATTERN_2;
2907 I915_WRITE(reg, temp);
2908
2909 POSTING_READ(reg);
2910 udelay(150);
2911
2912 reg = FDI_RX_IIR(pipe);
2913 for (tries = 0; tries < 5; tries++) {
2914 temp = I915_READ(reg);
2915 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2916
2917 if (temp & FDI_RX_SYMBOL_LOCK) {
2918 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2919 DRM_DEBUG_KMS("FDI train 2 done.\n");
2920 break;
2921 }
2922 }
2923 if (tries == 5)
2924 DRM_ERROR("FDI train 2 fail!\n");
2925
2926 DRM_DEBUG_KMS("FDI train done\n");
2927
2928 }
2929
2930 static const int snb_b_fdi_train_param[] = {
2931 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2932 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2933 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2934 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2935 };
2936
2937 /* The FDI link training functions for SNB/Cougarpoint. */
2938 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2939 {
2940 struct drm_device *dev = crtc->dev;
2941 struct drm_i915_private *dev_priv = dev->dev_private;
2942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2943 int pipe = intel_crtc->pipe;
2944 u32 reg, temp, i, retry;
2945
2946 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2947 for train result */
2948 reg = FDI_RX_IMR(pipe);
2949 temp = I915_READ(reg);
2950 temp &= ~FDI_RX_SYMBOL_LOCK;
2951 temp &= ~FDI_RX_BIT_LOCK;
2952 I915_WRITE(reg, temp);
2953
2954 POSTING_READ(reg);
2955 udelay(150);
2956
2957 /* enable CPU FDI TX and PCH FDI RX */
2958 reg = FDI_TX_CTL(pipe);
2959 temp = I915_READ(reg);
2960 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2961 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2962 temp &= ~FDI_LINK_TRAIN_NONE;
2963 temp |= FDI_LINK_TRAIN_PATTERN_1;
2964 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2965 /* SNB-B */
2966 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2967 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2968
2969 I915_WRITE(FDI_RX_MISC(pipe),
2970 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2971
2972 reg = FDI_RX_CTL(pipe);
2973 temp = I915_READ(reg);
2974 if (HAS_PCH_CPT(dev)) {
2975 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2976 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2977 } else {
2978 temp &= ~FDI_LINK_TRAIN_NONE;
2979 temp |= FDI_LINK_TRAIN_PATTERN_1;
2980 }
2981 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2982
2983 POSTING_READ(reg);
2984 udelay(150);
2985
2986 for (i = 0; i < 4; i++) {
2987 reg = FDI_TX_CTL(pipe);
2988 temp = I915_READ(reg);
2989 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2990 temp |= snb_b_fdi_train_param[i];
2991 I915_WRITE(reg, temp);
2992
2993 POSTING_READ(reg);
2994 udelay(500);
2995
2996 for (retry = 0; retry < 5; retry++) {
2997 reg = FDI_RX_IIR(pipe);
2998 temp = I915_READ(reg);
2999 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3000 if (temp & FDI_RX_BIT_LOCK) {
3001 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3002 DRM_DEBUG_KMS("FDI train 1 done.\n");
3003 break;
3004 }
3005 udelay(50);
3006 }
3007 if (retry < 5)
3008 break;
3009 }
3010 if (i == 4)
3011 DRM_ERROR("FDI train 1 fail!\n");
3012
3013 /* Train 2 */
3014 reg = FDI_TX_CTL(pipe);
3015 temp = I915_READ(reg);
3016 temp &= ~FDI_LINK_TRAIN_NONE;
3017 temp |= FDI_LINK_TRAIN_PATTERN_2;
3018 if (IS_GEN6(dev)) {
3019 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3020 /* SNB-B */
3021 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3022 }
3023 I915_WRITE(reg, temp);
3024
3025 reg = FDI_RX_CTL(pipe);
3026 temp = I915_READ(reg);
3027 if (HAS_PCH_CPT(dev)) {
3028 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3029 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3030 } else {
3031 temp &= ~FDI_LINK_TRAIN_NONE;
3032 temp |= FDI_LINK_TRAIN_PATTERN_2;
3033 }
3034 I915_WRITE(reg, temp);
3035
3036 POSTING_READ(reg);
3037 udelay(150);
3038
3039 for (i = 0; i < 4; i++) {
3040 reg = FDI_TX_CTL(pipe);
3041 temp = I915_READ(reg);
3042 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3043 temp |= snb_b_fdi_train_param[i];
3044 I915_WRITE(reg, temp);
3045
3046 POSTING_READ(reg);
3047 udelay(500);
3048
3049 for (retry = 0; retry < 5; retry++) {
3050 reg = FDI_RX_IIR(pipe);
3051 temp = I915_READ(reg);
3052 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3053 if (temp & FDI_RX_SYMBOL_LOCK) {
3054 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3055 DRM_DEBUG_KMS("FDI train 2 done.\n");
3056 break;
3057 }
3058 udelay(50);
3059 }
3060 if (retry < 5)
3061 break;
3062 }
3063 if (i == 4)
3064 DRM_ERROR("FDI train 2 fail!\n");
3065
3066 DRM_DEBUG_KMS("FDI train done.\n");
3067 }
3068
3069 /* Manual link training for Ivy Bridge A0 parts */
3070 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3071 {
3072 struct drm_device *dev = crtc->dev;
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3075 int pipe = intel_crtc->pipe;
3076 u32 reg, temp, i, j;
3077
3078 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3079 for train result */
3080 reg = FDI_RX_IMR(pipe);
3081 temp = I915_READ(reg);
3082 temp &= ~FDI_RX_SYMBOL_LOCK;
3083 temp &= ~FDI_RX_BIT_LOCK;
3084 I915_WRITE(reg, temp);
3085
3086 POSTING_READ(reg);
3087 udelay(150);
3088
3089 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3090 I915_READ(FDI_RX_IIR(pipe)));
3091
3092 /* Try each vswing and preemphasis setting twice before moving on */
3093 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3094 /* disable first in case we need to retry */
3095 reg = FDI_TX_CTL(pipe);
3096 temp = I915_READ(reg);
3097 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3098 temp &= ~FDI_TX_ENABLE;
3099 I915_WRITE(reg, temp);
3100
3101 reg = FDI_RX_CTL(pipe);
3102 temp = I915_READ(reg);
3103 temp &= ~FDI_LINK_TRAIN_AUTO;
3104 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3105 temp &= ~FDI_RX_ENABLE;
3106 I915_WRITE(reg, temp);
3107
3108 /* enable CPU FDI TX and PCH FDI RX */
3109 reg = FDI_TX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3112 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3113 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3114 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3115 temp |= snb_b_fdi_train_param[j/2];
3116 temp |= FDI_COMPOSITE_SYNC;
3117 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3118
3119 I915_WRITE(FDI_RX_MISC(pipe),
3120 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3121
3122 reg = FDI_RX_CTL(pipe);
3123 temp = I915_READ(reg);
3124 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3125 temp |= FDI_COMPOSITE_SYNC;
3126 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3127
3128 POSTING_READ(reg);
3129 udelay(1); /* should be 0.5us */
3130
3131 for (i = 0; i < 4; i++) {
3132 reg = FDI_RX_IIR(pipe);
3133 temp = I915_READ(reg);
3134 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3135
3136 if (temp & FDI_RX_BIT_LOCK ||
3137 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3138 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3139 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3140 i);
3141 break;
3142 }
3143 udelay(1); /* should be 0.5us */
3144 }
3145 if (i == 4) {
3146 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3147 continue;
3148 }
3149
3150 /* Train 2 */
3151 reg = FDI_TX_CTL(pipe);
3152 temp = I915_READ(reg);
3153 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3154 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3155 I915_WRITE(reg, temp);
3156
3157 reg = FDI_RX_CTL(pipe);
3158 temp = I915_READ(reg);
3159 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3160 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3161 I915_WRITE(reg, temp);
3162
3163 POSTING_READ(reg);
3164 udelay(2); /* should be 1.5us */
3165
3166 for (i = 0; i < 4; i++) {
3167 reg = FDI_RX_IIR(pipe);
3168 temp = I915_READ(reg);
3169 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3170
3171 if (temp & FDI_RX_SYMBOL_LOCK ||
3172 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3173 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3174 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3175 i);
3176 goto train_done;
3177 }
3178 udelay(2); /* should be 1.5us */
3179 }
3180 if (i == 4)
3181 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3182 }
3183
3184 train_done:
3185 DRM_DEBUG_KMS("FDI train done.\n");
3186 }
3187
3188 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3189 {
3190 struct drm_device *dev = intel_crtc->base.dev;
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 int pipe = intel_crtc->pipe;
3193 u32 reg, temp;
3194
3195
3196 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3197 reg = FDI_RX_CTL(pipe);
3198 temp = I915_READ(reg);
3199 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3200 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3201 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3202 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3203
3204 POSTING_READ(reg);
3205 udelay(200);
3206
3207 /* Switch from Rawclk to PCDclk */
3208 temp = I915_READ(reg);
3209 I915_WRITE(reg, temp | FDI_PCDCLK);
3210
3211 POSTING_READ(reg);
3212 udelay(200);
3213
3214 /* Enable CPU FDI TX PLL, always on for Ironlake */
3215 reg = FDI_TX_CTL(pipe);
3216 temp = I915_READ(reg);
3217 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3218 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3219
3220 POSTING_READ(reg);
3221 udelay(100);
3222 }
3223 }
3224
3225 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3226 {
3227 struct drm_device *dev = intel_crtc->base.dev;
3228 struct drm_i915_private *dev_priv = dev->dev_private;
3229 int pipe = intel_crtc->pipe;
3230 u32 reg, temp;
3231
3232 /* Switch from PCDclk to Rawclk */
3233 reg = FDI_RX_CTL(pipe);
3234 temp = I915_READ(reg);
3235 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3236
3237 /* Disable CPU FDI TX PLL */
3238 reg = FDI_TX_CTL(pipe);
3239 temp = I915_READ(reg);
3240 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3241
3242 POSTING_READ(reg);
3243 udelay(100);
3244
3245 reg = FDI_RX_CTL(pipe);
3246 temp = I915_READ(reg);
3247 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3248
3249 /* Wait for the clocks to turn off. */
3250 POSTING_READ(reg);
3251 udelay(100);
3252 }
3253
3254 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3255 {
3256 struct drm_device *dev = crtc->dev;
3257 struct drm_i915_private *dev_priv = dev->dev_private;
3258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3259 int pipe = intel_crtc->pipe;
3260 u32 reg, temp;
3261
3262 /* disable CPU FDI tx and PCH FDI rx */
3263 reg = FDI_TX_CTL(pipe);
3264 temp = I915_READ(reg);
3265 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3266 POSTING_READ(reg);
3267
3268 reg = FDI_RX_CTL(pipe);
3269 temp = I915_READ(reg);
3270 temp &= ~(0x7 << 16);
3271 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3272 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3273
3274 POSTING_READ(reg);
3275 udelay(100);
3276
3277 /* Ironlake workaround, disable clock pointer after downing FDI */
3278 if (HAS_PCH_IBX(dev))
3279 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3280
3281 /* still set train pattern 1 */
3282 reg = FDI_TX_CTL(pipe);
3283 temp = I915_READ(reg);
3284 temp &= ~FDI_LINK_TRAIN_NONE;
3285 temp |= FDI_LINK_TRAIN_PATTERN_1;
3286 I915_WRITE(reg, temp);
3287
3288 reg = FDI_RX_CTL(pipe);
3289 temp = I915_READ(reg);
3290 if (HAS_PCH_CPT(dev)) {
3291 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3292 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3293 } else {
3294 temp &= ~FDI_LINK_TRAIN_NONE;
3295 temp |= FDI_LINK_TRAIN_PATTERN_1;
3296 }
3297 /* BPC in FDI rx is consistent with that in PIPECONF */
3298 temp &= ~(0x07 << 16);
3299 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3300 I915_WRITE(reg, temp);
3301
3302 POSTING_READ(reg);
3303 udelay(100);
3304 }
3305
3306 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3307 {
3308 struct intel_crtc *crtc;
3309
3310 /* Note that we don't need to be called with mode_config.lock here
3311 * as our list of CRTC objects is static for the lifetime of the
3312 * device and so cannot disappear as we iterate. Similarly, we can
3313 * happily treat the predicates as racy, atomic checks as userspace
3314 * cannot claim and pin a new fb without at least acquring the
3315 * struct_mutex and so serialising with us.
3316 */
3317 for_each_intel_crtc(dev, crtc) {
3318 if (atomic_read(&crtc->unpin_work_count) == 0)
3319 continue;
3320
3321 if (crtc->unpin_work)
3322 intel_wait_for_vblank(dev, crtc->pipe);
3323
3324 return true;
3325 }
3326
3327 return false;
3328 }
3329
3330 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3331 {
3332 struct drm_device *dev = crtc->dev;
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334
3335 if (crtc->primary->fb == NULL)
3336 return;
3337
3338 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3339
3340 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3341 !intel_crtc_has_pending_flip(crtc),
3342 60*HZ) == 0);
3343
3344 mutex_lock(&dev->struct_mutex);
3345 intel_finish_fb(crtc->primary->fb);
3346 mutex_unlock(&dev->struct_mutex);
3347 }
3348
3349 /* Program iCLKIP clock to the desired frequency */
3350 static void lpt_program_iclkip(struct drm_crtc *crtc)
3351 {
3352 struct drm_device *dev = crtc->dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3355 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3356 u32 temp;
3357
3358 mutex_lock(&dev_priv->dpio_lock);
3359
3360 /* It is necessary to ungate the pixclk gate prior to programming
3361 * the divisors, and gate it back when it is done.
3362 */
3363 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3364
3365 /* Disable SSCCTL */
3366 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3367 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3368 SBI_SSCCTL_DISABLE,
3369 SBI_ICLK);
3370
3371 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3372 if (clock == 20000) {
3373 auxdiv = 1;
3374 divsel = 0x41;
3375 phaseinc = 0x20;
3376 } else {
3377 /* The iCLK virtual clock root frequency is in MHz,
3378 * but the adjusted_mode->crtc_clock in in KHz. To get the
3379 * divisors, it is necessary to divide one by another, so we
3380 * convert the virtual clock precision to KHz here for higher
3381 * precision.
3382 */
3383 u32 iclk_virtual_root_freq = 172800 * 1000;
3384 u32 iclk_pi_range = 64;
3385 u32 desired_divisor, msb_divisor_value, pi_value;
3386
3387 desired_divisor = (iclk_virtual_root_freq / clock);
3388 msb_divisor_value = desired_divisor / iclk_pi_range;
3389 pi_value = desired_divisor % iclk_pi_range;
3390
3391 auxdiv = 0;
3392 divsel = msb_divisor_value - 2;
3393 phaseinc = pi_value;
3394 }
3395
3396 /* This should not happen with any sane values */
3397 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3398 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3399 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3400 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3401
3402 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3403 clock,
3404 auxdiv,
3405 divsel,
3406 phasedir,
3407 phaseinc);
3408
3409 /* Program SSCDIVINTPHASE6 */
3410 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3411 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3412 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3413 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3414 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3415 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3416 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3417 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3418
3419 /* Program SSCAUXDIV */
3420 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3421 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3422 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3423 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3424
3425 /* Enable modulator and associated divider */
3426 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3427 temp &= ~SBI_SSCCTL_DISABLE;
3428 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3429
3430 /* Wait for initialization time */
3431 udelay(24);
3432
3433 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3434
3435 mutex_unlock(&dev_priv->dpio_lock);
3436 }
3437
3438 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3439 enum pipe pch_transcoder)
3440 {
3441 struct drm_device *dev = crtc->base.dev;
3442 struct drm_i915_private *dev_priv = dev->dev_private;
3443 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3444
3445 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3446 I915_READ(HTOTAL(cpu_transcoder)));
3447 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3448 I915_READ(HBLANK(cpu_transcoder)));
3449 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3450 I915_READ(HSYNC(cpu_transcoder)));
3451
3452 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3453 I915_READ(VTOTAL(cpu_transcoder)));
3454 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3455 I915_READ(VBLANK(cpu_transcoder)));
3456 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3457 I915_READ(VSYNC(cpu_transcoder)));
3458 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3459 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3460 }
3461
3462 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3463 {
3464 struct drm_i915_private *dev_priv = dev->dev_private;
3465 uint32_t temp;
3466
3467 temp = I915_READ(SOUTH_CHICKEN1);
3468 if (temp & FDI_BC_BIFURCATION_SELECT)
3469 return;
3470
3471 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3472 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3473
3474 temp |= FDI_BC_BIFURCATION_SELECT;
3475 DRM_DEBUG_KMS("enabling fdi C rx\n");
3476 I915_WRITE(SOUTH_CHICKEN1, temp);
3477 POSTING_READ(SOUTH_CHICKEN1);
3478 }
3479
3480 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3481 {
3482 struct drm_device *dev = intel_crtc->base.dev;
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484
3485 switch (intel_crtc->pipe) {
3486 case PIPE_A:
3487 break;
3488 case PIPE_B:
3489 if (intel_crtc->config.fdi_lanes > 2)
3490 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3491 else
3492 cpt_enable_fdi_bc_bifurcation(dev);
3493
3494 break;
3495 case PIPE_C:
3496 cpt_enable_fdi_bc_bifurcation(dev);
3497
3498 break;
3499 default:
3500 BUG();
3501 }
3502 }
3503
3504 /*
3505 * Enable PCH resources required for PCH ports:
3506 * - PCH PLLs
3507 * - FDI training & RX/TX
3508 * - update transcoder timings
3509 * - DP transcoding bits
3510 * - transcoder
3511 */
3512 static void ironlake_pch_enable(struct drm_crtc *crtc)
3513 {
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 int pipe = intel_crtc->pipe;
3518 u32 reg, temp;
3519
3520 assert_pch_transcoder_disabled(dev_priv, pipe);
3521
3522 if (IS_IVYBRIDGE(dev))
3523 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3524
3525 /* Write the TU size bits before fdi link training, so that error
3526 * detection works. */
3527 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3528 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3529
3530 /* For PCH output, training FDI link */
3531 dev_priv->display.fdi_link_train(crtc);
3532
3533 /* We need to program the right clock selection before writing the pixel
3534 * mutliplier into the DPLL. */
3535 if (HAS_PCH_CPT(dev)) {
3536 u32 sel;
3537
3538 temp = I915_READ(PCH_DPLL_SEL);
3539 temp |= TRANS_DPLL_ENABLE(pipe);
3540 sel = TRANS_DPLLB_SEL(pipe);
3541 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3542 temp |= sel;
3543 else
3544 temp &= ~sel;
3545 I915_WRITE(PCH_DPLL_SEL, temp);
3546 }
3547
3548 /* XXX: pch pll's can be enabled any time before we enable the PCH
3549 * transcoder, and we actually should do this to not upset any PCH
3550 * transcoder that already use the clock when we share it.
3551 *
3552 * Note that enable_shared_dpll tries to do the right thing, but
3553 * get_shared_dpll unconditionally resets the pll - we need that to have
3554 * the right LVDS enable sequence. */
3555 intel_enable_shared_dpll(intel_crtc);
3556
3557 /* set transcoder timing, panel must allow it */
3558 assert_panel_unlocked(dev_priv, pipe);
3559 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3560
3561 intel_fdi_normal_train(crtc);
3562
3563 /* For PCH DP, enable TRANS_DP_CTL */
3564 if (HAS_PCH_CPT(dev) &&
3565 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3566 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3567 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3568 reg = TRANS_DP_CTL(pipe);
3569 temp = I915_READ(reg);
3570 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3571 TRANS_DP_SYNC_MASK |
3572 TRANS_DP_BPC_MASK);
3573 temp |= (TRANS_DP_OUTPUT_ENABLE |
3574 TRANS_DP_ENH_FRAMING);
3575 temp |= bpc << 9; /* same format but at 11:9 */
3576
3577 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3578 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3579 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3580 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3581
3582 switch (intel_trans_dp_port_sel(crtc)) {
3583 case PCH_DP_B:
3584 temp |= TRANS_DP_PORT_SEL_B;
3585 break;
3586 case PCH_DP_C:
3587 temp |= TRANS_DP_PORT_SEL_C;
3588 break;
3589 case PCH_DP_D:
3590 temp |= TRANS_DP_PORT_SEL_D;
3591 break;
3592 default:
3593 BUG();
3594 }
3595
3596 I915_WRITE(reg, temp);
3597 }
3598
3599 ironlake_enable_pch_transcoder(dev_priv, pipe);
3600 }
3601
3602 static void lpt_pch_enable(struct drm_crtc *crtc)
3603 {
3604 struct drm_device *dev = crtc->dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3607 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3608
3609 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3610
3611 lpt_program_iclkip(crtc);
3612
3613 /* Set transcoder timing. */
3614 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3615
3616 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3617 }
3618
3619 void intel_put_shared_dpll(struct intel_crtc *crtc)
3620 {
3621 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3622
3623 if (pll == NULL)
3624 return;
3625
3626 if (pll->refcount == 0) {
3627 WARN(1, "bad %s refcount\n", pll->name);
3628 return;
3629 }
3630
3631 if (--pll->refcount == 0) {
3632 WARN_ON(pll->on);
3633 WARN_ON(pll->active);
3634 }
3635
3636 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3637 }
3638
3639 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3640 {
3641 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3642 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3643 enum intel_dpll_id i;
3644
3645 if (pll) {
3646 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3647 crtc->base.base.id, pll->name);
3648 intel_put_shared_dpll(crtc);
3649 }
3650
3651 if (HAS_PCH_IBX(dev_priv->dev)) {
3652 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3653 i = (enum intel_dpll_id) crtc->pipe;
3654 pll = &dev_priv->shared_dplls[i];
3655
3656 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3657 crtc->base.base.id, pll->name);
3658
3659 WARN_ON(pll->refcount);
3660
3661 goto found;
3662 }
3663
3664 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3665 pll = &dev_priv->shared_dplls[i];
3666
3667 /* Only want to check enabled timings first */
3668 if (pll->refcount == 0)
3669 continue;
3670
3671 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3672 sizeof(pll->hw_state)) == 0) {
3673 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3674 crtc->base.base.id,
3675 pll->name, pll->refcount, pll->active);
3676
3677 goto found;
3678 }
3679 }
3680
3681 /* Ok no matching timings, maybe there's a free one? */
3682 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3683 pll = &dev_priv->shared_dplls[i];
3684 if (pll->refcount == 0) {
3685 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3686 crtc->base.base.id, pll->name);
3687 goto found;
3688 }
3689 }
3690
3691 return NULL;
3692
3693 found:
3694 if (pll->refcount == 0)
3695 pll->hw_state = crtc->config.dpll_hw_state;
3696
3697 crtc->config.shared_dpll = i;
3698 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3699 pipe_name(crtc->pipe));
3700
3701 pll->refcount++;
3702
3703 return pll;
3704 }
3705
3706 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3707 {
3708 struct drm_i915_private *dev_priv = dev->dev_private;
3709 int dslreg = PIPEDSL(pipe);
3710 u32 temp;
3711
3712 temp = I915_READ(dslreg);
3713 udelay(500);
3714 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3715 if (wait_for(I915_READ(dslreg) != temp, 5))
3716 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3717 }
3718 }
3719
3720 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3721 {
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 int pipe = crtc->pipe;
3725
3726 if (crtc->config.pch_pfit.enabled) {
3727 /* Force use of hard-coded filter coefficients
3728 * as some pre-programmed values are broken,
3729 * e.g. x201.
3730 */
3731 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3732 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3733 PF_PIPE_SEL_IVB(pipe));
3734 else
3735 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3736 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3737 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3738 }
3739 }
3740
3741 static void intel_enable_planes(struct drm_crtc *crtc)
3742 {
3743 struct drm_device *dev = crtc->dev;
3744 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3745 struct drm_plane *plane;
3746 struct intel_plane *intel_plane;
3747
3748 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3749 intel_plane = to_intel_plane(plane);
3750 if (intel_plane->pipe == pipe)
3751 intel_plane_restore(&intel_plane->base);
3752 }
3753 }
3754
3755 static void intel_disable_planes(struct drm_crtc *crtc)
3756 {
3757 struct drm_device *dev = crtc->dev;
3758 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3759 struct drm_plane *plane;
3760 struct intel_plane *intel_plane;
3761
3762 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3763 intel_plane = to_intel_plane(plane);
3764 if (intel_plane->pipe == pipe)
3765 intel_plane_disable(&intel_plane->base);
3766 }
3767 }
3768
3769 void hsw_enable_ips(struct intel_crtc *crtc)
3770 {
3771 struct drm_device *dev = crtc->base.dev;
3772 struct drm_i915_private *dev_priv = dev->dev_private;
3773
3774 if (!crtc->config.ips_enabled)
3775 return;
3776
3777 /* We can only enable IPS after we enable a plane and wait for a vblank */
3778 intel_wait_for_vblank(dev, crtc->pipe);
3779
3780 assert_plane_enabled(dev_priv, crtc->plane);
3781 if (IS_BROADWELL(dev)) {
3782 mutex_lock(&dev_priv->rps.hw_lock);
3783 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3784 mutex_unlock(&dev_priv->rps.hw_lock);
3785 /* Quoting Art Runyan: "its not safe to expect any particular
3786 * value in IPS_CTL bit 31 after enabling IPS through the
3787 * mailbox." Moreover, the mailbox may return a bogus state,
3788 * so we need to just enable it and continue on.
3789 */
3790 } else {
3791 I915_WRITE(IPS_CTL, IPS_ENABLE);
3792 /* The bit only becomes 1 in the next vblank, so this wait here
3793 * is essentially intel_wait_for_vblank. If we don't have this
3794 * and don't wait for vblanks until the end of crtc_enable, then
3795 * the HW state readout code will complain that the expected
3796 * IPS_CTL value is not the one we read. */
3797 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3798 DRM_ERROR("Timed out waiting for IPS enable\n");
3799 }
3800 }
3801
3802 void hsw_disable_ips(struct intel_crtc *crtc)
3803 {
3804 struct drm_device *dev = crtc->base.dev;
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806
3807 if (!crtc->config.ips_enabled)
3808 return;
3809
3810 assert_plane_enabled(dev_priv, crtc->plane);
3811 if (IS_BROADWELL(dev)) {
3812 mutex_lock(&dev_priv->rps.hw_lock);
3813 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3814 mutex_unlock(&dev_priv->rps.hw_lock);
3815 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3816 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3817 DRM_ERROR("Timed out waiting for IPS disable\n");
3818 } else {
3819 I915_WRITE(IPS_CTL, 0);
3820 POSTING_READ(IPS_CTL);
3821 }
3822
3823 /* We need to wait for a vblank before we can disable the plane. */
3824 intel_wait_for_vblank(dev, crtc->pipe);
3825 }
3826
3827 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3828 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3829 {
3830 struct drm_device *dev = crtc->dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3833 enum pipe pipe = intel_crtc->pipe;
3834 int palreg = PALETTE(pipe);
3835 int i;
3836 bool reenable_ips = false;
3837
3838 /* The clocks have to be on to load the palette. */
3839 if (!crtc->enabled || !intel_crtc->active)
3840 return;
3841
3842 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3843 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3844 assert_dsi_pll_enabled(dev_priv);
3845 else
3846 assert_pll_enabled(dev_priv, pipe);
3847 }
3848
3849 /* use legacy palette for Ironlake */
3850 if (HAS_PCH_SPLIT(dev))
3851 palreg = LGC_PALETTE(pipe);
3852
3853 /* Workaround : Do not read or write the pipe palette/gamma data while
3854 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3855 */
3856 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3857 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3858 GAMMA_MODE_MODE_SPLIT)) {
3859 hsw_disable_ips(intel_crtc);
3860 reenable_ips = true;
3861 }
3862
3863 for (i = 0; i < 256; i++) {
3864 I915_WRITE(palreg + 4 * i,
3865 (intel_crtc->lut_r[i] << 16) |
3866 (intel_crtc->lut_g[i] << 8) |
3867 intel_crtc->lut_b[i]);
3868 }
3869
3870 if (reenable_ips)
3871 hsw_enable_ips(intel_crtc);
3872 }
3873
3874 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3875 {
3876 if (!enable && intel_crtc->overlay) {
3877 struct drm_device *dev = intel_crtc->base.dev;
3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879
3880 mutex_lock(&dev->struct_mutex);
3881 dev_priv->mm.interruptible = false;
3882 (void) intel_overlay_switch_off(intel_crtc->overlay);
3883 dev_priv->mm.interruptible = true;
3884 mutex_unlock(&dev->struct_mutex);
3885 }
3886
3887 /* Let userspace switch the overlay on again. In most cases userspace
3888 * has to recompute where to put it anyway.
3889 */
3890 }
3891
3892 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3893 {
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897 int pipe = intel_crtc->pipe;
3898 int plane = intel_crtc->plane;
3899
3900 drm_vblank_on(dev, pipe);
3901
3902 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3903 intel_enable_planes(crtc);
3904 intel_crtc_update_cursor(crtc, true);
3905 intel_crtc_dpms_overlay(intel_crtc, true);
3906
3907 hsw_enable_ips(intel_crtc);
3908
3909 mutex_lock(&dev->struct_mutex);
3910 intel_update_fbc(dev);
3911 mutex_unlock(&dev->struct_mutex);
3912
3913 /*
3914 * FIXME: Once we grow proper nuclear flip support out of this we need
3915 * to compute the mask of flip planes precisely. For the time being
3916 * consider this a flip from a NULL plane.
3917 */
3918 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3919 }
3920
3921 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3922 {
3923 struct drm_device *dev = crtc->dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3926 int pipe = intel_crtc->pipe;
3927 int plane = intel_crtc->plane;
3928
3929 intel_crtc_wait_for_pending_flips(crtc);
3930
3931 if (dev_priv->fbc.plane == plane)
3932 intel_disable_fbc(dev);
3933
3934 hsw_disable_ips(intel_crtc);
3935
3936 intel_crtc_dpms_overlay(intel_crtc, false);
3937 intel_crtc_update_cursor(crtc, false);
3938 intel_disable_planes(crtc);
3939 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3940
3941 /*
3942 * FIXME: Once we grow proper nuclear flip support out of this we need
3943 * to compute the mask of flip planes precisely. For the time being
3944 * consider this a flip to a NULL plane.
3945 */
3946 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
3947
3948 drm_vblank_off(dev, pipe);
3949 }
3950
3951 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3952 {
3953 struct drm_device *dev = crtc->dev;
3954 struct drm_i915_private *dev_priv = dev->dev_private;
3955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3956 struct intel_encoder *encoder;
3957 int pipe = intel_crtc->pipe;
3958 enum plane plane = intel_crtc->plane;
3959
3960 WARN_ON(!crtc->enabled);
3961
3962 if (intel_crtc->active)
3963 return;
3964
3965 if (intel_crtc->config.has_pch_encoder)
3966 intel_prepare_shared_dpll(intel_crtc);
3967
3968 if (intel_crtc->config.has_dp_encoder)
3969 intel_dp_set_m_n(intel_crtc);
3970
3971 intel_set_pipe_timings(intel_crtc);
3972
3973 if (intel_crtc->config.has_pch_encoder) {
3974 intel_cpu_transcoder_set_m_n(intel_crtc,
3975 &intel_crtc->config.fdi_m_n);
3976 }
3977
3978 ironlake_set_pipeconf(crtc);
3979
3980 /* Set up the display plane register */
3981 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3982 POSTING_READ(DSPCNTR(plane));
3983
3984 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3985 crtc->x, crtc->y);
3986
3987 intel_crtc->active = true;
3988
3989 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3990 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3991
3992 for_each_encoder_on_crtc(dev, crtc, encoder)
3993 if (encoder->pre_enable)
3994 encoder->pre_enable(encoder);
3995
3996 if (intel_crtc->config.has_pch_encoder) {
3997 /* Note: FDI PLL enabling _must_ be done before we enable the
3998 * cpu pipes, hence this is separate from all the other fdi/pch
3999 * enabling. */
4000 ironlake_fdi_pll_enable(intel_crtc);
4001 } else {
4002 assert_fdi_tx_disabled(dev_priv, pipe);
4003 assert_fdi_rx_disabled(dev_priv, pipe);
4004 }
4005
4006 ironlake_pfit_enable(intel_crtc);
4007
4008 /*
4009 * On ILK+ LUT must be loaded before the pipe is running but with
4010 * clocks enabled
4011 */
4012 intel_crtc_load_lut(crtc);
4013
4014 intel_update_watermarks(crtc);
4015 intel_enable_pipe(intel_crtc);
4016
4017 if (intel_crtc->config.has_pch_encoder)
4018 ironlake_pch_enable(crtc);
4019
4020 for_each_encoder_on_crtc(dev, crtc, encoder)
4021 encoder->enable(encoder);
4022
4023 if (HAS_PCH_CPT(dev))
4024 cpt_verify_modeset(dev, intel_crtc->pipe);
4025
4026 intel_crtc_enable_planes(crtc);
4027 }
4028
4029 /* IPS only exists on ULT machines and is tied to pipe A. */
4030 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4031 {
4032 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4033 }
4034
4035 /*
4036 * This implements the workaround described in the "notes" section of the mode
4037 * set sequence documentation. When going from no pipes or single pipe to
4038 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4039 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4040 */
4041 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4042 {
4043 struct drm_device *dev = crtc->base.dev;
4044 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4045
4046 /* We want to get the other_active_crtc only if there's only 1 other
4047 * active crtc. */
4048 for_each_intel_crtc(dev, crtc_it) {
4049 if (!crtc_it->active || crtc_it == crtc)
4050 continue;
4051
4052 if (other_active_crtc)
4053 return;
4054
4055 other_active_crtc = crtc_it;
4056 }
4057 if (!other_active_crtc)
4058 return;
4059
4060 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4061 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4062 }
4063
4064 static void haswell_crtc_enable(struct drm_crtc *crtc)
4065 {
4066 struct drm_device *dev = crtc->dev;
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069 struct intel_encoder *encoder;
4070 int pipe = intel_crtc->pipe;
4071 enum plane plane = intel_crtc->plane;
4072
4073 WARN_ON(!crtc->enabled);
4074
4075 if (intel_crtc->active)
4076 return;
4077
4078 if (intel_crtc_to_shared_dpll(intel_crtc))
4079 intel_enable_shared_dpll(intel_crtc);
4080
4081 if (intel_crtc->config.has_dp_encoder)
4082 intel_dp_set_m_n(intel_crtc);
4083
4084 intel_set_pipe_timings(intel_crtc);
4085
4086 if (intel_crtc->config.has_pch_encoder) {
4087 intel_cpu_transcoder_set_m_n(intel_crtc,
4088 &intel_crtc->config.fdi_m_n);
4089 }
4090
4091 haswell_set_pipeconf(crtc);
4092
4093 intel_set_pipe_csc(crtc);
4094
4095 /* Set up the display plane register */
4096 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4097 POSTING_READ(DSPCNTR(plane));
4098
4099 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4100 crtc->x, crtc->y);
4101
4102 intel_crtc->active = true;
4103
4104 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4105 for_each_encoder_on_crtc(dev, crtc, encoder)
4106 if (encoder->pre_enable)
4107 encoder->pre_enable(encoder);
4108
4109 if (intel_crtc->config.has_pch_encoder) {
4110 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4111 dev_priv->display.fdi_link_train(crtc);
4112 }
4113
4114 intel_ddi_enable_pipe_clock(intel_crtc);
4115
4116 ironlake_pfit_enable(intel_crtc);
4117
4118 /*
4119 * On ILK+ LUT must be loaded before the pipe is running but with
4120 * clocks enabled
4121 */
4122 intel_crtc_load_lut(crtc);
4123
4124 intel_ddi_set_pipe_settings(crtc);
4125 intel_ddi_enable_transcoder_func(crtc);
4126
4127 intel_update_watermarks(crtc);
4128 intel_enable_pipe(intel_crtc);
4129
4130 if (intel_crtc->config.has_pch_encoder)
4131 lpt_pch_enable(crtc);
4132
4133 for_each_encoder_on_crtc(dev, crtc, encoder) {
4134 encoder->enable(encoder);
4135 intel_opregion_notify_encoder(encoder, true);
4136 }
4137
4138 /* If we change the relative order between pipe/planes enabling, we need
4139 * to change the workaround. */
4140 haswell_mode_set_planes_workaround(intel_crtc);
4141 intel_crtc_enable_planes(crtc);
4142 }
4143
4144 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4145 {
4146 struct drm_device *dev = crtc->base.dev;
4147 struct drm_i915_private *dev_priv = dev->dev_private;
4148 int pipe = crtc->pipe;
4149
4150 /* To avoid upsetting the power well on haswell only disable the pfit if
4151 * it's in use. The hw state code will make sure we get this right. */
4152 if (crtc->config.pch_pfit.enabled) {
4153 I915_WRITE(PF_CTL(pipe), 0);
4154 I915_WRITE(PF_WIN_POS(pipe), 0);
4155 I915_WRITE(PF_WIN_SZ(pipe), 0);
4156 }
4157 }
4158
4159 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4160 {
4161 struct drm_device *dev = crtc->dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4164 struct intel_encoder *encoder;
4165 int pipe = intel_crtc->pipe;
4166 u32 reg, temp;
4167
4168 if (!intel_crtc->active)
4169 return;
4170
4171 intel_crtc_disable_planes(crtc);
4172
4173 for_each_encoder_on_crtc(dev, crtc, encoder)
4174 encoder->disable(encoder);
4175
4176 if (intel_crtc->config.has_pch_encoder)
4177 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4178
4179 intel_disable_pipe(dev_priv, pipe);
4180
4181 ironlake_pfit_disable(intel_crtc);
4182
4183 for_each_encoder_on_crtc(dev, crtc, encoder)
4184 if (encoder->post_disable)
4185 encoder->post_disable(encoder);
4186
4187 if (intel_crtc->config.has_pch_encoder) {
4188 ironlake_fdi_disable(crtc);
4189
4190 ironlake_disable_pch_transcoder(dev_priv, pipe);
4191 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4192
4193 if (HAS_PCH_CPT(dev)) {
4194 /* disable TRANS_DP_CTL */
4195 reg = TRANS_DP_CTL(pipe);
4196 temp = I915_READ(reg);
4197 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4198 TRANS_DP_PORT_SEL_MASK);
4199 temp |= TRANS_DP_PORT_SEL_NONE;
4200 I915_WRITE(reg, temp);
4201
4202 /* disable DPLL_SEL */
4203 temp = I915_READ(PCH_DPLL_SEL);
4204 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4205 I915_WRITE(PCH_DPLL_SEL, temp);
4206 }
4207
4208 /* disable PCH DPLL */
4209 intel_disable_shared_dpll(intel_crtc);
4210
4211 ironlake_fdi_pll_disable(intel_crtc);
4212 }
4213
4214 intel_crtc->active = false;
4215 intel_update_watermarks(crtc);
4216
4217 mutex_lock(&dev->struct_mutex);
4218 intel_update_fbc(dev);
4219 mutex_unlock(&dev->struct_mutex);
4220 }
4221
4222 static void haswell_crtc_disable(struct drm_crtc *crtc)
4223 {
4224 struct drm_device *dev = crtc->dev;
4225 struct drm_i915_private *dev_priv = dev->dev_private;
4226 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4227 struct intel_encoder *encoder;
4228 int pipe = intel_crtc->pipe;
4229 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4230
4231 if (!intel_crtc->active)
4232 return;
4233
4234 intel_crtc_disable_planes(crtc);
4235
4236 for_each_encoder_on_crtc(dev, crtc, encoder) {
4237 intel_opregion_notify_encoder(encoder, false);
4238 encoder->disable(encoder);
4239 }
4240
4241 if (intel_crtc->config.has_pch_encoder)
4242 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4243 intel_disable_pipe(dev_priv, pipe);
4244
4245 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4246
4247 ironlake_pfit_disable(intel_crtc);
4248
4249 intel_ddi_disable_pipe_clock(intel_crtc);
4250
4251 if (intel_crtc->config.has_pch_encoder) {
4252 lpt_disable_pch_transcoder(dev_priv);
4253 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4254 intel_ddi_fdi_disable(crtc);
4255 }
4256
4257 for_each_encoder_on_crtc(dev, crtc, encoder)
4258 if (encoder->post_disable)
4259 encoder->post_disable(encoder);
4260
4261 intel_crtc->active = false;
4262 intel_update_watermarks(crtc);
4263
4264 mutex_lock(&dev->struct_mutex);
4265 intel_update_fbc(dev);
4266 mutex_unlock(&dev->struct_mutex);
4267
4268 if (intel_crtc_to_shared_dpll(intel_crtc))
4269 intel_disable_shared_dpll(intel_crtc);
4270 }
4271
4272 static void ironlake_crtc_off(struct drm_crtc *crtc)
4273 {
4274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4275 intel_put_shared_dpll(intel_crtc);
4276 }
4277
4278
4279 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4280 {
4281 struct drm_device *dev = crtc->base.dev;
4282 struct drm_i915_private *dev_priv = dev->dev_private;
4283 struct intel_crtc_config *pipe_config = &crtc->config;
4284
4285 if (!crtc->config.gmch_pfit.control)
4286 return;
4287
4288 /*
4289 * The panel fitter should only be adjusted whilst the pipe is disabled,
4290 * according to register description and PRM.
4291 */
4292 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4293 assert_pipe_disabled(dev_priv, crtc->pipe);
4294
4295 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4296 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4297
4298 /* Border color in case we don't scale up to the full screen. Black by
4299 * default, change to something else for debugging. */
4300 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4301 }
4302
4303 #define for_each_power_domain(domain, mask) \
4304 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4305 if ((1 << (domain)) & (mask))
4306
4307 enum intel_display_power_domain
4308 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4309 {
4310 struct drm_device *dev = intel_encoder->base.dev;
4311 struct intel_digital_port *intel_dig_port;
4312
4313 switch (intel_encoder->type) {
4314 case INTEL_OUTPUT_UNKNOWN:
4315 /* Only DDI platforms should ever use this output type */
4316 WARN_ON_ONCE(!HAS_DDI(dev));
4317 case INTEL_OUTPUT_DISPLAYPORT:
4318 case INTEL_OUTPUT_HDMI:
4319 case INTEL_OUTPUT_EDP:
4320 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4321 switch (intel_dig_port->port) {
4322 case PORT_A:
4323 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4324 case PORT_B:
4325 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4326 case PORT_C:
4327 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4328 case PORT_D:
4329 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4330 default:
4331 WARN_ON_ONCE(1);
4332 return POWER_DOMAIN_PORT_OTHER;
4333 }
4334 case INTEL_OUTPUT_ANALOG:
4335 return POWER_DOMAIN_PORT_CRT;
4336 case INTEL_OUTPUT_DSI:
4337 return POWER_DOMAIN_PORT_DSI;
4338 default:
4339 return POWER_DOMAIN_PORT_OTHER;
4340 }
4341 }
4342
4343 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4344 {
4345 struct drm_device *dev = crtc->dev;
4346 struct intel_encoder *intel_encoder;
4347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4348 enum pipe pipe = intel_crtc->pipe;
4349 unsigned long mask;
4350 enum transcoder transcoder;
4351
4352 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4353
4354 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4355 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4356 if (intel_crtc->config.pch_pfit.enabled ||
4357 intel_crtc->config.pch_pfit.force_thru)
4358 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4359
4360 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4361 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4362
4363 return mask;
4364 }
4365
4366 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4367 bool enable)
4368 {
4369 if (dev_priv->power_domains.init_power_on == enable)
4370 return;
4371
4372 if (enable)
4373 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4374 else
4375 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4376
4377 dev_priv->power_domains.init_power_on = enable;
4378 }
4379
4380 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4381 {
4382 struct drm_i915_private *dev_priv = dev->dev_private;
4383 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4384 struct intel_crtc *crtc;
4385
4386 /*
4387 * First get all needed power domains, then put all unneeded, to avoid
4388 * any unnecessary toggling of the power wells.
4389 */
4390 for_each_intel_crtc(dev, crtc) {
4391 enum intel_display_power_domain domain;
4392
4393 if (!crtc->base.enabled)
4394 continue;
4395
4396 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4397
4398 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4399 intel_display_power_get(dev_priv, domain);
4400 }
4401
4402 for_each_intel_crtc(dev, crtc) {
4403 enum intel_display_power_domain domain;
4404
4405 for_each_power_domain(domain, crtc->enabled_power_domains)
4406 intel_display_power_put(dev_priv, domain);
4407
4408 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4409 }
4410
4411 intel_display_set_init_power(dev_priv, false);
4412 }
4413
4414 /* returns HPLL frequency in kHz */
4415 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4416 {
4417 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4418
4419 /* Obtain SKU information */
4420 mutex_lock(&dev_priv->dpio_lock);
4421 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4422 CCK_FUSE_HPLL_FREQ_MASK;
4423 mutex_unlock(&dev_priv->dpio_lock);
4424
4425 return vco_freq[hpll_freq] * 1000;
4426 }
4427
4428 static void vlv_update_cdclk(struct drm_device *dev)
4429 {
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431
4432 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4433 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4434 dev_priv->vlv_cdclk_freq);
4435
4436 /*
4437 * Program the gmbus_freq based on the cdclk frequency.
4438 * BSpec erroneously claims we should aim for 4MHz, but
4439 * in fact 1MHz is the correct frequency.
4440 */
4441 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4442 }
4443
4444 /* Adjust CDclk dividers to allow high res or save power if possible */
4445 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4446 {
4447 struct drm_i915_private *dev_priv = dev->dev_private;
4448 u32 val, cmd;
4449
4450 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4451
4452 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4453 cmd = 2;
4454 else if (cdclk == 266667)
4455 cmd = 1;
4456 else
4457 cmd = 0;
4458
4459 mutex_lock(&dev_priv->rps.hw_lock);
4460 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4461 val &= ~DSPFREQGUAR_MASK;
4462 val |= (cmd << DSPFREQGUAR_SHIFT);
4463 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4464 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4465 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4466 50)) {
4467 DRM_ERROR("timed out waiting for CDclk change\n");
4468 }
4469 mutex_unlock(&dev_priv->rps.hw_lock);
4470
4471 if (cdclk == 400000) {
4472 u32 divider, vco;
4473
4474 vco = valleyview_get_vco(dev_priv);
4475 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4476
4477 mutex_lock(&dev_priv->dpio_lock);
4478 /* adjust cdclk divider */
4479 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4480 val &= ~DISPLAY_FREQUENCY_VALUES;
4481 val |= divider;
4482 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4483
4484 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4485 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4486 50))
4487 DRM_ERROR("timed out waiting for CDclk change\n");
4488 mutex_unlock(&dev_priv->dpio_lock);
4489 }
4490
4491 mutex_lock(&dev_priv->dpio_lock);
4492 /* adjust self-refresh exit latency value */
4493 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4494 val &= ~0x7f;
4495
4496 /*
4497 * For high bandwidth configs, we set a higher latency in the bunit
4498 * so that the core display fetch happens in time to avoid underruns.
4499 */
4500 if (cdclk == 400000)
4501 val |= 4500 / 250; /* 4.5 usec */
4502 else
4503 val |= 3000 / 250; /* 3.0 usec */
4504 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4505 mutex_unlock(&dev_priv->dpio_lock);
4506
4507 vlv_update_cdclk(dev);
4508 }
4509
4510 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4511 int max_pixclk)
4512 {
4513 int vco = valleyview_get_vco(dev_priv);
4514 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4515
4516 /*
4517 * Really only a few cases to deal with, as only 4 CDclks are supported:
4518 * 200MHz
4519 * 267MHz
4520 * 320/333MHz (depends on HPLL freq)
4521 * 400MHz
4522 * So we check to see whether we're above 90% of the lower bin and
4523 * adjust if needed.
4524 *
4525 * We seem to get an unstable or solid color picture at 200MHz.
4526 * Not sure what's wrong. For now use 200MHz only when all pipes
4527 * are off.
4528 */
4529 if (max_pixclk > freq_320*9/10)
4530 return 400000;
4531 else if (max_pixclk > 266667*9/10)
4532 return freq_320;
4533 else if (max_pixclk > 0)
4534 return 266667;
4535 else
4536 return 200000;
4537 }
4538
4539 /* compute the max pixel clock for new configuration */
4540 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4541 {
4542 struct drm_device *dev = dev_priv->dev;
4543 struct intel_crtc *intel_crtc;
4544 int max_pixclk = 0;
4545
4546 for_each_intel_crtc(dev, intel_crtc) {
4547 if (intel_crtc->new_enabled)
4548 max_pixclk = max(max_pixclk,
4549 intel_crtc->new_config->adjusted_mode.crtc_clock);
4550 }
4551
4552 return max_pixclk;
4553 }
4554
4555 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4556 unsigned *prepare_pipes)
4557 {
4558 struct drm_i915_private *dev_priv = dev->dev_private;
4559 struct intel_crtc *intel_crtc;
4560 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4561
4562 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4563 dev_priv->vlv_cdclk_freq)
4564 return;
4565
4566 /* disable/enable all currently active pipes while we change cdclk */
4567 for_each_intel_crtc(dev, intel_crtc)
4568 if (intel_crtc->base.enabled)
4569 *prepare_pipes |= (1 << intel_crtc->pipe);
4570 }
4571
4572 static void valleyview_modeset_global_resources(struct drm_device *dev)
4573 {
4574 struct drm_i915_private *dev_priv = dev->dev_private;
4575 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4576 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4577
4578 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4579 valleyview_set_cdclk(dev, req_cdclk);
4580 modeset_update_crtc_power_domains(dev);
4581 }
4582
4583 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4584 {
4585 struct drm_device *dev = crtc->dev;
4586 struct drm_i915_private *dev_priv = dev->dev_private;
4587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4588 struct intel_encoder *encoder;
4589 int pipe = intel_crtc->pipe;
4590 int plane = intel_crtc->plane;
4591 bool is_dsi;
4592 u32 dspcntr;
4593
4594 WARN_ON(!crtc->enabled);
4595
4596 if (intel_crtc->active)
4597 return;
4598
4599 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4600
4601 if (!is_dsi && !IS_CHERRYVIEW(dev))
4602 vlv_prepare_pll(intel_crtc);
4603
4604 /* Set up the display plane register */
4605 dspcntr = DISPPLANE_GAMMA_ENABLE;
4606
4607 if (intel_crtc->config.has_dp_encoder)
4608 intel_dp_set_m_n(intel_crtc);
4609
4610 intel_set_pipe_timings(intel_crtc);
4611
4612 /* pipesrc and dspsize control the size that is scaled from,
4613 * which should always be the user's requested size.
4614 */
4615 I915_WRITE(DSPSIZE(plane),
4616 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4617 (intel_crtc->config.pipe_src_w - 1));
4618 I915_WRITE(DSPPOS(plane), 0);
4619
4620 i9xx_set_pipeconf(intel_crtc);
4621
4622 I915_WRITE(DSPCNTR(plane), dspcntr);
4623 POSTING_READ(DSPCNTR(plane));
4624
4625 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4626 crtc->x, crtc->y);
4627
4628 intel_crtc->active = true;
4629
4630 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4631
4632 for_each_encoder_on_crtc(dev, crtc, encoder)
4633 if (encoder->pre_pll_enable)
4634 encoder->pre_pll_enable(encoder);
4635
4636 if (!is_dsi) {
4637 if (IS_CHERRYVIEW(dev))
4638 chv_enable_pll(intel_crtc);
4639 else
4640 vlv_enable_pll(intel_crtc);
4641 }
4642
4643 for_each_encoder_on_crtc(dev, crtc, encoder)
4644 if (encoder->pre_enable)
4645 encoder->pre_enable(encoder);
4646
4647 i9xx_pfit_enable(intel_crtc);
4648
4649 intel_crtc_load_lut(crtc);
4650
4651 intel_update_watermarks(crtc);
4652 intel_enable_pipe(intel_crtc);
4653
4654 for_each_encoder_on_crtc(dev, crtc, encoder)
4655 encoder->enable(encoder);
4656
4657 intel_crtc_enable_planes(crtc);
4658
4659 /* Underruns don't raise interrupts, so check manually. */
4660 i9xx_check_fifo_underruns(dev);
4661 }
4662
4663 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4664 {
4665 struct drm_device *dev = crtc->base.dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667
4668 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4669 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4670 }
4671
4672 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4673 {
4674 struct drm_device *dev = crtc->dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4677 struct intel_encoder *encoder;
4678 int pipe = intel_crtc->pipe;
4679 int plane = intel_crtc->plane;
4680 u32 dspcntr;
4681
4682 WARN_ON(!crtc->enabled);
4683
4684 if (intel_crtc->active)
4685 return;
4686
4687 i9xx_set_pll_dividers(intel_crtc);
4688
4689 /* Set up the display plane register */
4690 dspcntr = DISPPLANE_GAMMA_ENABLE;
4691
4692 if (pipe == 0)
4693 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4694 else
4695 dspcntr |= DISPPLANE_SEL_PIPE_B;
4696
4697 if (intel_crtc->config.has_dp_encoder)
4698 intel_dp_set_m_n(intel_crtc);
4699
4700 intel_set_pipe_timings(intel_crtc);
4701
4702 /* pipesrc and dspsize control the size that is scaled from,
4703 * which should always be the user's requested size.
4704 */
4705 I915_WRITE(DSPSIZE(plane),
4706 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4707 (intel_crtc->config.pipe_src_w - 1));
4708 I915_WRITE(DSPPOS(plane), 0);
4709
4710 i9xx_set_pipeconf(intel_crtc);
4711
4712 I915_WRITE(DSPCNTR(plane), dspcntr);
4713 POSTING_READ(DSPCNTR(plane));
4714
4715 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4716 crtc->x, crtc->y);
4717
4718 intel_crtc->active = true;
4719
4720 if (!IS_GEN2(dev))
4721 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4722
4723 for_each_encoder_on_crtc(dev, crtc, encoder)
4724 if (encoder->pre_enable)
4725 encoder->pre_enable(encoder);
4726
4727 i9xx_enable_pll(intel_crtc);
4728
4729 i9xx_pfit_enable(intel_crtc);
4730
4731 intel_crtc_load_lut(crtc);
4732
4733 intel_update_watermarks(crtc);
4734 intel_enable_pipe(intel_crtc);
4735
4736 for_each_encoder_on_crtc(dev, crtc, encoder)
4737 encoder->enable(encoder);
4738
4739 intel_crtc_enable_planes(crtc);
4740
4741 /*
4742 * Gen2 reports pipe underruns whenever all planes are disabled.
4743 * So don't enable underrun reporting before at least some planes
4744 * are enabled.
4745 * FIXME: Need to fix the logic to work when we turn off all planes
4746 * but leave the pipe running.
4747 */
4748 if (IS_GEN2(dev))
4749 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4750
4751 /* Underruns don't raise interrupts, so check manually. */
4752 i9xx_check_fifo_underruns(dev);
4753 }
4754
4755 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4756 {
4757 struct drm_device *dev = crtc->base.dev;
4758 struct drm_i915_private *dev_priv = dev->dev_private;
4759
4760 if (!crtc->config.gmch_pfit.control)
4761 return;
4762
4763 assert_pipe_disabled(dev_priv, crtc->pipe);
4764
4765 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4766 I915_READ(PFIT_CONTROL));
4767 I915_WRITE(PFIT_CONTROL, 0);
4768 }
4769
4770 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4771 {
4772 struct drm_device *dev = crtc->dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4775 struct intel_encoder *encoder;
4776 int pipe = intel_crtc->pipe;
4777
4778 if (!intel_crtc->active)
4779 return;
4780
4781 /*
4782 * Gen2 reports pipe underruns whenever all planes are disabled.
4783 * So diasble underrun reporting before all the planes get disabled.
4784 * FIXME: Need to fix the logic to work when we turn off all planes
4785 * but leave the pipe running.
4786 */
4787 if (IS_GEN2(dev))
4788 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4789
4790 /*
4791 * Vblank time updates from the shadow to live plane control register
4792 * are blocked if the memory self-refresh mode is active at that
4793 * moment. So to make sure the plane gets truly disabled, disable
4794 * first the self-refresh mode. The self-refresh enable bit in turn
4795 * will be checked/applied by the HW only at the next frame start
4796 * event which is after the vblank start event, so we need to have a
4797 * wait-for-vblank between disabling the plane and the pipe.
4798 */
4799 intel_set_memory_cxsr(dev_priv, false);
4800 intel_crtc_disable_planes(crtc);
4801
4802 for_each_encoder_on_crtc(dev, crtc, encoder)
4803 encoder->disable(encoder);
4804
4805 /*
4806 * On gen2 planes are double buffered but the pipe isn't, so we must
4807 * wait for planes to fully turn off before disabling the pipe.
4808 * We also need to wait on all gmch platforms because of the
4809 * self-refresh mode constraint explained above.
4810 */
4811 intel_wait_for_vblank(dev, pipe);
4812
4813 intel_disable_pipe(dev_priv, pipe);
4814
4815 i9xx_pfit_disable(intel_crtc);
4816
4817 for_each_encoder_on_crtc(dev, crtc, encoder)
4818 if (encoder->post_disable)
4819 encoder->post_disable(encoder);
4820
4821 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4822 if (IS_CHERRYVIEW(dev))
4823 chv_disable_pll(dev_priv, pipe);
4824 else if (IS_VALLEYVIEW(dev))
4825 vlv_disable_pll(dev_priv, pipe);
4826 else
4827 i9xx_disable_pll(dev_priv, pipe);
4828 }
4829
4830 if (!IS_GEN2(dev))
4831 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4832
4833 intel_crtc->active = false;
4834 intel_update_watermarks(crtc);
4835
4836 mutex_lock(&dev->struct_mutex);
4837 intel_update_fbc(dev);
4838 mutex_unlock(&dev->struct_mutex);
4839 }
4840
4841 static void i9xx_crtc_off(struct drm_crtc *crtc)
4842 {
4843 }
4844
4845 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4846 bool enabled)
4847 {
4848 struct drm_device *dev = crtc->dev;
4849 struct drm_i915_master_private *master_priv;
4850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4851 int pipe = intel_crtc->pipe;
4852
4853 if (!dev->primary->master)
4854 return;
4855
4856 master_priv = dev->primary->master->driver_priv;
4857 if (!master_priv->sarea_priv)
4858 return;
4859
4860 switch (pipe) {
4861 case 0:
4862 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4863 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4864 break;
4865 case 1:
4866 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4867 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4868 break;
4869 default:
4870 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4871 break;
4872 }
4873 }
4874
4875 /**
4876 * Sets the power management mode of the pipe and plane.
4877 */
4878 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4879 {
4880 struct drm_device *dev = crtc->dev;
4881 struct drm_i915_private *dev_priv = dev->dev_private;
4882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4883 struct intel_encoder *intel_encoder;
4884 enum intel_display_power_domain domain;
4885 unsigned long domains;
4886 bool enable = false;
4887
4888 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4889 enable |= intel_encoder->connectors_active;
4890
4891 if (enable) {
4892 if (!intel_crtc->active) {
4893 domains = get_crtc_power_domains(crtc);
4894 for_each_power_domain(domain, domains)
4895 intel_display_power_get(dev_priv, domain);
4896 intel_crtc->enabled_power_domains = domains;
4897
4898 dev_priv->display.crtc_enable(crtc);
4899 }
4900 } else {
4901 if (intel_crtc->active) {
4902 dev_priv->display.crtc_disable(crtc);
4903
4904 domains = intel_crtc->enabled_power_domains;
4905 for_each_power_domain(domain, domains)
4906 intel_display_power_put(dev_priv, domain);
4907 intel_crtc->enabled_power_domains = 0;
4908 }
4909 }
4910
4911 intel_crtc_update_sarea(crtc, enable);
4912 }
4913
4914 static void intel_crtc_disable(struct drm_crtc *crtc)
4915 {
4916 struct drm_device *dev = crtc->dev;
4917 struct drm_connector *connector;
4918 struct drm_i915_private *dev_priv = dev->dev_private;
4919 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
4920 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4921
4922 /* crtc should still be enabled when we disable it. */
4923 WARN_ON(!crtc->enabled);
4924
4925 dev_priv->display.crtc_disable(crtc);
4926 intel_crtc_update_sarea(crtc, false);
4927 dev_priv->display.off(crtc);
4928
4929 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4930 assert_cursor_disabled(dev_priv, pipe);
4931 assert_pipe_disabled(dev->dev_private, pipe);
4932
4933 if (crtc->primary->fb) {
4934 mutex_lock(&dev->struct_mutex);
4935 intel_unpin_fb_obj(old_obj);
4936 i915_gem_track_fb(old_obj, NULL,
4937 INTEL_FRONTBUFFER_PRIMARY(pipe));
4938 mutex_unlock(&dev->struct_mutex);
4939 crtc->primary->fb = NULL;
4940 }
4941
4942 /* Update computed state. */
4943 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4944 if (!connector->encoder || !connector->encoder->crtc)
4945 continue;
4946
4947 if (connector->encoder->crtc != crtc)
4948 continue;
4949
4950 connector->dpms = DRM_MODE_DPMS_OFF;
4951 to_intel_encoder(connector->encoder)->connectors_active = false;
4952 }
4953 }
4954
4955 void intel_encoder_destroy(struct drm_encoder *encoder)
4956 {
4957 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4958
4959 drm_encoder_cleanup(encoder);
4960 kfree(intel_encoder);
4961 }
4962
4963 /* Simple dpms helper for encoders with just one connector, no cloning and only
4964 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4965 * state of the entire output pipe. */
4966 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4967 {
4968 if (mode == DRM_MODE_DPMS_ON) {
4969 encoder->connectors_active = true;
4970
4971 intel_crtc_update_dpms(encoder->base.crtc);
4972 } else {
4973 encoder->connectors_active = false;
4974
4975 intel_crtc_update_dpms(encoder->base.crtc);
4976 }
4977 }
4978
4979 /* Cross check the actual hw state with our own modeset state tracking (and it's
4980 * internal consistency). */
4981 static void intel_connector_check_state(struct intel_connector *connector)
4982 {
4983 if (connector->get_hw_state(connector)) {
4984 struct intel_encoder *encoder = connector->encoder;
4985 struct drm_crtc *crtc;
4986 bool encoder_enabled;
4987 enum pipe pipe;
4988
4989 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4990 connector->base.base.id,
4991 connector->base.name);
4992
4993 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4994 "wrong connector dpms state\n");
4995 WARN(connector->base.encoder != &encoder->base,
4996 "active connector not linked to encoder\n");
4997 WARN(!encoder->connectors_active,
4998 "encoder->connectors_active not set\n");
4999
5000 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5001 WARN(!encoder_enabled, "encoder not enabled\n");
5002 if (WARN_ON(!encoder->base.crtc))
5003 return;
5004
5005 crtc = encoder->base.crtc;
5006
5007 WARN(!crtc->enabled, "crtc not enabled\n");
5008 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5009 WARN(pipe != to_intel_crtc(crtc)->pipe,
5010 "encoder active on the wrong pipe\n");
5011 }
5012 }
5013
5014 /* Even simpler default implementation, if there's really no special case to
5015 * consider. */
5016 void intel_connector_dpms(struct drm_connector *connector, int mode)
5017 {
5018 /* All the simple cases only support two dpms states. */
5019 if (mode != DRM_MODE_DPMS_ON)
5020 mode = DRM_MODE_DPMS_OFF;
5021
5022 if (mode == connector->dpms)
5023 return;
5024
5025 connector->dpms = mode;
5026
5027 /* Only need to change hw state when actually enabled */
5028 if (connector->encoder)
5029 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5030
5031 intel_modeset_check_state(connector->dev);
5032 }
5033
5034 /* Simple connector->get_hw_state implementation for encoders that support only
5035 * one connector and no cloning and hence the encoder state determines the state
5036 * of the connector. */
5037 bool intel_connector_get_hw_state(struct intel_connector *connector)
5038 {
5039 enum pipe pipe = 0;
5040 struct intel_encoder *encoder = connector->encoder;
5041
5042 return encoder->get_hw_state(encoder, &pipe);
5043 }
5044
5045 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5046 struct intel_crtc_config *pipe_config)
5047 {
5048 struct drm_i915_private *dev_priv = dev->dev_private;
5049 struct intel_crtc *pipe_B_crtc =
5050 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5051
5052 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5053 pipe_name(pipe), pipe_config->fdi_lanes);
5054 if (pipe_config->fdi_lanes > 4) {
5055 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5056 pipe_name(pipe), pipe_config->fdi_lanes);
5057 return false;
5058 }
5059
5060 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5061 if (pipe_config->fdi_lanes > 2) {
5062 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5063 pipe_config->fdi_lanes);
5064 return false;
5065 } else {
5066 return true;
5067 }
5068 }
5069
5070 if (INTEL_INFO(dev)->num_pipes == 2)
5071 return true;
5072
5073 /* Ivybridge 3 pipe is really complicated */
5074 switch (pipe) {
5075 case PIPE_A:
5076 return true;
5077 case PIPE_B:
5078 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5079 pipe_config->fdi_lanes > 2) {
5080 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5081 pipe_name(pipe), pipe_config->fdi_lanes);
5082 return false;
5083 }
5084 return true;
5085 case PIPE_C:
5086 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5087 pipe_B_crtc->config.fdi_lanes <= 2) {
5088 if (pipe_config->fdi_lanes > 2) {
5089 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5090 pipe_name(pipe), pipe_config->fdi_lanes);
5091 return false;
5092 }
5093 } else {
5094 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5095 return false;
5096 }
5097 return true;
5098 default:
5099 BUG();
5100 }
5101 }
5102
5103 #define RETRY 1
5104 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5105 struct intel_crtc_config *pipe_config)
5106 {
5107 struct drm_device *dev = intel_crtc->base.dev;
5108 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5109 int lane, link_bw, fdi_dotclock;
5110 bool setup_ok, needs_recompute = false;
5111
5112 retry:
5113 /* FDI is a binary signal running at ~2.7GHz, encoding
5114 * each output octet as 10 bits. The actual frequency
5115 * is stored as a divider into a 100MHz clock, and the
5116 * mode pixel clock is stored in units of 1KHz.
5117 * Hence the bw of each lane in terms of the mode signal
5118 * is:
5119 */
5120 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5121
5122 fdi_dotclock = adjusted_mode->crtc_clock;
5123
5124 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5125 pipe_config->pipe_bpp);
5126
5127 pipe_config->fdi_lanes = lane;
5128
5129 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5130 link_bw, &pipe_config->fdi_m_n);
5131
5132 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5133 intel_crtc->pipe, pipe_config);
5134 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5135 pipe_config->pipe_bpp -= 2*3;
5136 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5137 pipe_config->pipe_bpp);
5138 needs_recompute = true;
5139 pipe_config->bw_constrained = true;
5140
5141 goto retry;
5142 }
5143
5144 if (needs_recompute)
5145 return RETRY;
5146
5147 return setup_ok ? 0 : -EINVAL;
5148 }
5149
5150 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5151 struct intel_crtc_config *pipe_config)
5152 {
5153 pipe_config->ips_enabled = i915.enable_ips &&
5154 hsw_crtc_supports_ips(crtc) &&
5155 pipe_config->pipe_bpp <= 24;
5156 }
5157
5158 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5159 struct intel_crtc_config *pipe_config)
5160 {
5161 struct drm_device *dev = crtc->base.dev;
5162 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5163
5164 /* FIXME should check pixel clock limits on all platforms */
5165 if (INTEL_INFO(dev)->gen < 4) {
5166 struct drm_i915_private *dev_priv = dev->dev_private;
5167 int clock_limit =
5168 dev_priv->display.get_display_clock_speed(dev);
5169
5170 /*
5171 * Enable pixel doubling when the dot clock
5172 * is > 90% of the (display) core speed.
5173 *
5174 * GDG double wide on either pipe,
5175 * otherwise pipe A only.
5176 */
5177 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5178 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5179 clock_limit *= 2;
5180 pipe_config->double_wide = true;
5181 }
5182
5183 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5184 return -EINVAL;
5185 }
5186
5187 /*
5188 * Pipe horizontal size must be even in:
5189 * - DVO ganged mode
5190 * - LVDS dual channel mode
5191 * - Double wide pipe
5192 */
5193 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5194 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5195 pipe_config->pipe_src_w &= ~1;
5196
5197 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5198 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5199 */
5200 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5201 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5202 return -EINVAL;
5203
5204 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5205 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5206 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5207 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5208 * for lvds. */
5209 pipe_config->pipe_bpp = 8*3;
5210 }
5211
5212 if (HAS_IPS(dev))
5213 hsw_compute_ips_config(crtc, pipe_config);
5214
5215 /*
5216 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5217 * old clock survives for now.
5218 */
5219 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev))
5220 pipe_config->shared_dpll = crtc->config.shared_dpll;
5221
5222 if (pipe_config->has_pch_encoder)
5223 return ironlake_fdi_compute_config(crtc, pipe_config);
5224
5225 return 0;
5226 }
5227
5228 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5229 {
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5231 int vco = valleyview_get_vco(dev_priv);
5232 u32 val;
5233 int divider;
5234
5235 mutex_lock(&dev_priv->dpio_lock);
5236 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5237 mutex_unlock(&dev_priv->dpio_lock);
5238
5239 divider = val & DISPLAY_FREQUENCY_VALUES;
5240
5241 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5242 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5243 "cdclk change in progress\n");
5244
5245 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5246 }
5247
5248 static int i945_get_display_clock_speed(struct drm_device *dev)
5249 {
5250 return 400000;
5251 }
5252
5253 static int i915_get_display_clock_speed(struct drm_device *dev)
5254 {
5255 return 333000;
5256 }
5257
5258 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5259 {
5260 return 200000;
5261 }
5262
5263 static int pnv_get_display_clock_speed(struct drm_device *dev)
5264 {
5265 u16 gcfgc = 0;
5266
5267 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5268
5269 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5270 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5271 return 267000;
5272 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5273 return 333000;
5274 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5275 return 444000;
5276 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5277 return 200000;
5278 default:
5279 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5280 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5281 return 133000;
5282 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5283 return 167000;
5284 }
5285 }
5286
5287 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5288 {
5289 u16 gcfgc = 0;
5290
5291 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5292
5293 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5294 return 133000;
5295 else {
5296 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5297 case GC_DISPLAY_CLOCK_333_MHZ:
5298 return 333000;
5299 default:
5300 case GC_DISPLAY_CLOCK_190_200_MHZ:
5301 return 190000;
5302 }
5303 }
5304 }
5305
5306 static int i865_get_display_clock_speed(struct drm_device *dev)
5307 {
5308 return 266000;
5309 }
5310
5311 static int i855_get_display_clock_speed(struct drm_device *dev)
5312 {
5313 u16 hpllcc = 0;
5314 /* Assume that the hardware is in the high speed state. This
5315 * should be the default.
5316 */
5317 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5318 case GC_CLOCK_133_200:
5319 case GC_CLOCK_100_200:
5320 return 200000;
5321 case GC_CLOCK_166_250:
5322 return 250000;
5323 case GC_CLOCK_100_133:
5324 return 133000;
5325 }
5326
5327 /* Shouldn't happen */
5328 return 0;
5329 }
5330
5331 static int i830_get_display_clock_speed(struct drm_device *dev)
5332 {
5333 return 133000;
5334 }
5335
5336 static void
5337 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5338 {
5339 while (*num > DATA_LINK_M_N_MASK ||
5340 *den > DATA_LINK_M_N_MASK) {
5341 *num >>= 1;
5342 *den >>= 1;
5343 }
5344 }
5345
5346 static void compute_m_n(unsigned int m, unsigned int n,
5347 uint32_t *ret_m, uint32_t *ret_n)
5348 {
5349 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5350 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5351 intel_reduce_m_n_ratio(ret_m, ret_n);
5352 }
5353
5354 void
5355 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5356 int pixel_clock, int link_clock,
5357 struct intel_link_m_n *m_n)
5358 {
5359 m_n->tu = 64;
5360
5361 compute_m_n(bits_per_pixel * pixel_clock,
5362 link_clock * nlanes * 8,
5363 &m_n->gmch_m, &m_n->gmch_n);
5364
5365 compute_m_n(pixel_clock, link_clock,
5366 &m_n->link_m, &m_n->link_n);
5367 }
5368
5369 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5370 {
5371 if (i915.panel_use_ssc >= 0)
5372 return i915.panel_use_ssc != 0;
5373 return dev_priv->vbt.lvds_use_ssc
5374 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5375 }
5376
5377 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5378 {
5379 struct drm_device *dev = crtc->dev;
5380 struct drm_i915_private *dev_priv = dev->dev_private;
5381 int refclk;
5382
5383 if (IS_VALLEYVIEW(dev)) {
5384 refclk = 100000;
5385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5386 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5387 refclk = dev_priv->vbt.lvds_ssc_freq;
5388 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5389 } else if (!IS_GEN2(dev)) {
5390 refclk = 96000;
5391 } else {
5392 refclk = 48000;
5393 }
5394
5395 return refclk;
5396 }
5397
5398 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5399 {
5400 return (1 << dpll->n) << 16 | dpll->m2;
5401 }
5402
5403 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5404 {
5405 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5406 }
5407
5408 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5409 intel_clock_t *reduced_clock)
5410 {
5411 struct drm_device *dev = crtc->base.dev;
5412 u32 fp, fp2 = 0;
5413
5414 if (IS_PINEVIEW(dev)) {
5415 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5416 if (reduced_clock)
5417 fp2 = pnv_dpll_compute_fp(reduced_clock);
5418 } else {
5419 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5420 if (reduced_clock)
5421 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5422 }
5423
5424 crtc->config.dpll_hw_state.fp0 = fp;
5425
5426 crtc->lowfreq_avail = false;
5427 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5428 reduced_clock && i915.powersave) {
5429 crtc->config.dpll_hw_state.fp1 = fp2;
5430 crtc->lowfreq_avail = true;
5431 } else {
5432 crtc->config.dpll_hw_state.fp1 = fp;
5433 }
5434 }
5435
5436 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5437 pipe)
5438 {
5439 u32 reg_val;
5440
5441 /*
5442 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5443 * and set it to a reasonable value instead.
5444 */
5445 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5446 reg_val &= 0xffffff00;
5447 reg_val |= 0x00000030;
5448 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5449
5450 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5451 reg_val &= 0x8cffffff;
5452 reg_val = 0x8c000000;
5453 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5454
5455 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5456 reg_val &= 0xffffff00;
5457 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5458
5459 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5460 reg_val &= 0x00ffffff;
5461 reg_val |= 0xb0000000;
5462 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5463 }
5464
5465 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5466 struct intel_link_m_n *m_n)
5467 {
5468 struct drm_device *dev = crtc->base.dev;
5469 struct drm_i915_private *dev_priv = dev->dev_private;
5470 int pipe = crtc->pipe;
5471
5472 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5473 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5474 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5475 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5476 }
5477
5478 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5479 struct intel_link_m_n *m_n)
5480 {
5481 struct drm_device *dev = crtc->base.dev;
5482 struct drm_i915_private *dev_priv = dev->dev_private;
5483 int pipe = crtc->pipe;
5484 enum transcoder transcoder = crtc->config.cpu_transcoder;
5485
5486 if (INTEL_INFO(dev)->gen >= 5) {
5487 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5488 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5489 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5490 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5491 } else {
5492 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5493 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5494 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5495 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5496 }
5497 }
5498
5499 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5500 {
5501 if (crtc->config.has_pch_encoder)
5502 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5503 else
5504 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5505 }
5506
5507 static void vlv_update_pll(struct intel_crtc *crtc)
5508 {
5509 u32 dpll, dpll_md;
5510
5511 /*
5512 * Enable DPIO clock input. We should never disable the reference
5513 * clock for pipe B, since VGA hotplug / manual detection depends
5514 * on it.
5515 */
5516 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5517 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5518 /* We should never disable this, set it here for state tracking */
5519 if (crtc->pipe == PIPE_B)
5520 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5521 dpll |= DPLL_VCO_ENABLE;
5522 crtc->config.dpll_hw_state.dpll = dpll;
5523
5524 dpll_md = (crtc->config.pixel_multiplier - 1)
5525 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5526 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5527 }
5528
5529 static void vlv_prepare_pll(struct intel_crtc *crtc)
5530 {
5531 struct drm_device *dev = crtc->base.dev;
5532 struct drm_i915_private *dev_priv = dev->dev_private;
5533 int pipe = crtc->pipe;
5534 u32 mdiv;
5535 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5536 u32 coreclk, reg_val;
5537
5538 mutex_lock(&dev_priv->dpio_lock);
5539
5540 bestn = crtc->config.dpll.n;
5541 bestm1 = crtc->config.dpll.m1;
5542 bestm2 = crtc->config.dpll.m2;
5543 bestp1 = crtc->config.dpll.p1;
5544 bestp2 = crtc->config.dpll.p2;
5545
5546 /* See eDP HDMI DPIO driver vbios notes doc */
5547
5548 /* PLL B needs special handling */
5549 if (pipe == PIPE_B)
5550 vlv_pllb_recal_opamp(dev_priv, pipe);
5551
5552 /* Set up Tx target for periodic Rcomp update */
5553 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5554
5555 /* Disable target IRef on PLL */
5556 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5557 reg_val &= 0x00ffffff;
5558 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5559
5560 /* Disable fast lock */
5561 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5562
5563 /* Set idtafcrecal before PLL is enabled */
5564 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5565 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5566 mdiv |= ((bestn << DPIO_N_SHIFT));
5567 mdiv |= (1 << DPIO_K_SHIFT);
5568
5569 /*
5570 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5571 * but we don't support that).
5572 * Note: don't use the DAC post divider as it seems unstable.
5573 */
5574 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5575 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5576
5577 mdiv |= DPIO_ENABLE_CALIBRATION;
5578 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5579
5580 /* Set HBR and RBR LPF coefficients */
5581 if (crtc->config.port_clock == 162000 ||
5582 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5583 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5585 0x009f0003);
5586 else
5587 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5588 0x00d0000f);
5589
5590 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5591 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5592 /* Use SSC source */
5593 if (pipe == PIPE_A)
5594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5595 0x0df40000);
5596 else
5597 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5598 0x0df70000);
5599 } else { /* HDMI or VGA */
5600 /* Use bend source */
5601 if (pipe == PIPE_A)
5602 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5603 0x0df70000);
5604 else
5605 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5606 0x0df40000);
5607 }
5608
5609 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5610 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5611 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5612 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5613 coreclk |= 0x01000000;
5614 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5615
5616 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5617 mutex_unlock(&dev_priv->dpio_lock);
5618 }
5619
5620 static void chv_update_pll(struct intel_crtc *crtc)
5621 {
5622 struct drm_device *dev = crtc->base.dev;
5623 struct drm_i915_private *dev_priv = dev->dev_private;
5624 int pipe = crtc->pipe;
5625 int dpll_reg = DPLL(crtc->pipe);
5626 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5627 u32 loopfilter, intcoeff;
5628 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5629 int refclk;
5630
5631 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5632 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5633 DPLL_VCO_ENABLE;
5634 if (pipe != PIPE_A)
5635 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5636
5637 crtc->config.dpll_hw_state.dpll_md =
5638 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5639
5640 bestn = crtc->config.dpll.n;
5641 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5642 bestm1 = crtc->config.dpll.m1;
5643 bestm2 = crtc->config.dpll.m2 >> 22;
5644 bestp1 = crtc->config.dpll.p1;
5645 bestp2 = crtc->config.dpll.p2;
5646
5647 /*
5648 * Enable Refclk and SSC
5649 */
5650 I915_WRITE(dpll_reg,
5651 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5652
5653 mutex_lock(&dev_priv->dpio_lock);
5654
5655 /* p1 and p2 divider */
5656 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5657 5 << DPIO_CHV_S1_DIV_SHIFT |
5658 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5659 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5660 1 << DPIO_CHV_K_DIV_SHIFT);
5661
5662 /* Feedback post-divider - m2 */
5663 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5664
5665 /* Feedback refclk divider - n and m1 */
5666 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5667 DPIO_CHV_M1_DIV_BY_2 |
5668 1 << DPIO_CHV_N_DIV_SHIFT);
5669
5670 /* M2 fraction division */
5671 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5672
5673 /* M2 fraction division enable */
5674 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5675 DPIO_CHV_FRAC_DIV_EN |
5676 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5677
5678 /* Loop filter */
5679 refclk = i9xx_get_refclk(&crtc->base, 0);
5680 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5681 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5682 if (refclk == 100000)
5683 intcoeff = 11;
5684 else if (refclk == 38400)
5685 intcoeff = 10;
5686 else
5687 intcoeff = 9;
5688 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5689 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5690
5691 /* AFC Recal */
5692 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5693 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5694 DPIO_AFC_RECAL);
5695
5696 mutex_unlock(&dev_priv->dpio_lock);
5697 }
5698
5699 static void i9xx_update_pll(struct intel_crtc *crtc,
5700 intel_clock_t *reduced_clock,
5701 int num_connectors)
5702 {
5703 struct drm_device *dev = crtc->base.dev;
5704 struct drm_i915_private *dev_priv = dev->dev_private;
5705 u32 dpll;
5706 bool is_sdvo;
5707 struct dpll *clock = &crtc->config.dpll;
5708
5709 i9xx_update_pll_dividers(crtc, reduced_clock);
5710
5711 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5712 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5713
5714 dpll = DPLL_VGA_MODE_DIS;
5715
5716 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5717 dpll |= DPLLB_MODE_LVDS;
5718 else
5719 dpll |= DPLLB_MODE_DAC_SERIAL;
5720
5721 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5722 dpll |= (crtc->config.pixel_multiplier - 1)
5723 << SDVO_MULTIPLIER_SHIFT_HIRES;
5724 }
5725
5726 if (is_sdvo)
5727 dpll |= DPLL_SDVO_HIGH_SPEED;
5728
5729 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5730 dpll |= DPLL_SDVO_HIGH_SPEED;
5731
5732 /* compute bitmask from p1 value */
5733 if (IS_PINEVIEW(dev))
5734 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5735 else {
5736 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5737 if (IS_G4X(dev) && reduced_clock)
5738 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5739 }
5740 switch (clock->p2) {
5741 case 5:
5742 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5743 break;
5744 case 7:
5745 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5746 break;
5747 case 10:
5748 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5749 break;
5750 case 14:
5751 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5752 break;
5753 }
5754 if (INTEL_INFO(dev)->gen >= 4)
5755 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5756
5757 if (crtc->config.sdvo_tv_clock)
5758 dpll |= PLL_REF_INPUT_TVCLKINBC;
5759 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5760 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5761 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5762 else
5763 dpll |= PLL_REF_INPUT_DREFCLK;
5764
5765 dpll |= DPLL_VCO_ENABLE;
5766 crtc->config.dpll_hw_state.dpll = dpll;
5767
5768 if (INTEL_INFO(dev)->gen >= 4) {
5769 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5770 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5771 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5772 }
5773 }
5774
5775 static void i8xx_update_pll(struct intel_crtc *crtc,
5776 intel_clock_t *reduced_clock,
5777 int num_connectors)
5778 {
5779 struct drm_device *dev = crtc->base.dev;
5780 struct drm_i915_private *dev_priv = dev->dev_private;
5781 u32 dpll;
5782 struct dpll *clock = &crtc->config.dpll;
5783
5784 i9xx_update_pll_dividers(crtc, reduced_clock);
5785
5786 dpll = DPLL_VGA_MODE_DIS;
5787
5788 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5789 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5790 } else {
5791 if (clock->p1 == 2)
5792 dpll |= PLL_P1_DIVIDE_BY_TWO;
5793 else
5794 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5795 if (clock->p2 == 4)
5796 dpll |= PLL_P2_DIVIDE_BY_4;
5797 }
5798
5799 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5800 dpll |= DPLL_DVO_2X_MODE;
5801
5802 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5803 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5804 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5805 else
5806 dpll |= PLL_REF_INPUT_DREFCLK;
5807
5808 dpll |= DPLL_VCO_ENABLE;
5809 crtc->config.dpll_hw_state.dpll = dpll;
5810 }
5811
5812 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5813 {
5814 struct drm_device *dev = intel_crtc->base.dev;
5815 struct drm_i915_private *dev_priv = dev->dev_private;
5816 enum pipe pipe = intel_crtc->pipe;
5817 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5818 struct drm_display_mode *adjusted_mode =
5819 &intel_crtc->config.adjusted_mode;
5820 uint32_t crtc_vtotal, crtc_vblank_end;
5821 int vsyncshift = 0;
5822
5823 /* We need to be careful not to changed the adjusted mode, for otherwise
5824 * the hw state checker will get angry at the mismatch. */
5825 crtc_vtotal = adjusted_mode->crtc_vtotal;
5826 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5827
5828 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5829 /* the chip adds 2 halflines automatically */
5830 crtc_vtotal -= 1;
5831 crtc_vblank_end -= 1;
5832
5833 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5834 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5835 else
5836 vsyncshift = adjusted_mode->crtc_hsync_start -
5837 adjusted_mode->crtc_htotal / 2;
5838 if (vsyncshift < 0)
5839 vsyncshift += adjusted_mode->crtc_htotal;
5840 }
5841
5842 if (INTEL_INFO(dev)->gen > 3)
5843 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5844
5845 I915_WRITE(HTOTAL(cpu_transcoder),
5846 (adjusted_mode->crtc_hdisplay - 1) |
5847 ((adjusted_mode->crtc_htotal - 1) << 16));
5848 I915_WRITE(HBLANK(cpu_transcoder),
5849 (adjusted_mode->crtc_hblank_start - 1) |
5850 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5851 I915_WRITE(HSYNC(cpu_transcoder),
5852 (adjusted_mode->crtc_hsync_start - 1) |
5853 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5854
5855 I915_WRITE(VTOTAL(cpu_transcoder),
5856 (adjusted_mode->crtc_vdisplay - 1) |
5857 ((crtc_vtotal - 1) << 16));
5858 I915_WRITE(VBLANK(cpu_transcoder),
5859 (adjusted_mode->crtc_vblank_start - 1) |
5860 ((crtc_vblank_end - 1) << 16));
5861 I915_WRITE(VSYNC(cpu_transcoder),
5862 (adjusted_mode->crtc_vsync_start - 1) |
5863 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5864
5865 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5866 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5867 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5868 * bits. */
5869 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5870 (pipe == PIPE_B || pipe == PIPE_C))
5871 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5872
5873 /* pipesrc controls the size that is scaled from, which should
5874 * always be the user's requested size.
5875 */
5876 I915_WRITE(PIPESRC(pipe),
5877 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5878 (intel_crtc->config.pipe_src_h - 1));
5879 }
5880
5881 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5882 struct intel_crtc_config *pipe_config)
5883 {
5884 struct drm_device *dev = crtc->base.dev;
5885 struct drm_i915_private *dev_priv = dev->dev_private;
5886 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5887 uint32_t tmp;
5888
5889 tmp = I915_READ(HTOTAL(cpu_transcoder));
5890 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5891 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5892 tmp = I915_READ(HBLANK(cpu_transcoder));
5893 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5894 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5895 tmp = I915_READ(HSYNC(cpu_transcoder));
5896 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5897 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5898
5899 tmp = I915_READ(VTOTAL(cpu_transcoder));
5900 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5901 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5902 tmp = I915_READ(VBLANK(cpu_transcoder));
5903 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5904 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5905 tmp = I915_READ(VSYNC(cpu_transcoder));
5906 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5907 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5908
5909 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5910 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5911 pipe_config->adjusted_mode.crtc_vtotal += 1;
5912 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5913 }
5914
5915 tmp = I915_READ(PIPESRC(crtc->pipe));
5916 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5917 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5918
5919 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5920 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5921 }
5922
5923 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5924 struct intel_crtc_config *pipe_config)
5925 {
5926 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5927 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5928 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5929 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5930
5931 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5932 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5933 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5934 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5935
5936 mode->flags = pipe_config->adjusted_mode.flags;
5937
5938 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5939 mode->flags |= pipe_config->adjusted_mode.flags;
5940 }
5941
5942 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5943 {
5944 struct drm_device *dev = intel_crtc->base.dev;
5945 struct drm_i915_private *dev_priv = dev->dev_private;
5946 uint32_t pipeconf;
5947
5948 pipeconf = 0;
5949
5950 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5951 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5952 pipeconf |= PIPECONF_ENABLE;
5953
5954 if (intel_crtc->config.double_wide)
5955 pipeconf |= PIPECONF_DOUBLE_WIDE;
5956
5957 /* only g4x and later have fancy bpc/dither controls */
5958 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5959 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5960 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5961 pipeconf |= PIPECONF_DITHER_EN |
5962 PIPECONF_DITHER_TYPE_SP;
5963
5964 switch (intel_crtc->config.pipe_bpp) {
5965 case 18:
5966 pipeconf |= PIPECONF_6BPC;
5967 break;
5968 case 24:
5969 pipeconf |= PIPECONF_8BPC;
5970 break;
5971 case 30:
5972 pipeconf |= PIPECONF_10BPC;
5973 break;
5974 default:
5975 /* Case prevented by intel_choose_pipe_bpp_dither. */
5976 BUG();
5977 }
5978 }
5979
5980 if (HAS_PIPE_CXSR(dev)) {
5981 if (intel_crtc->lowfreq_avail) {
5982 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5983 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5984 } else {
5985 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5986 }
5987 }
5988
5989 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5990 if (INTEL_INFO(dev)->gen < 4 ||
5991 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5992 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5993 else
5994 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5995 } else
5996 pipeconf |= PIPECONF_PROGRESSIVE;
5997
5998 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5999 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6000
6001 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6002 POSTING_READ(PIPECONF(intel_crtc->pipe));
6003 }
6004
6005 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
6006 int x, int y,
6007 struct drm_framebuffer *fb)
6008 {
6009 struct drm_device *dev = crtc->dev;
6010 struct drm_i915_private *dev_priv = dev->dev_private;
6011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6012 int refclk, num_connectors = 0;
6013 intel_clock_t clock, reduced_clock;
6014 bool ok, has_reduced_clock = false;
6015 bool is_lvds = false, is_dsi = false;
6016 struct intel_encoder *encoder;
6017 const intel_limit_t *limit;
6018
6019 for_each_encoder_on_crtc(dev, crtc, encoder) {
6020 switch (encoder->type) {
6021 case INTEL_OUTPUT_LVDS:
6022 is_lvds = true;
6023 break;
6024 case INTEL_OUTPUT_DSI:
6025 is_dsi = true;
6026 break;
6027 }
6028
6029 num_connectors++;
6030 }
6031
6032 if (is_dsi)
6033 return 0;
6034
6035 if (!intel_crtc->config.clock_set) {
6036 refclk = i9xx_get_refclk(crtc, num_connectors);
6037
6038 /*
6039 * Returns a set of divisors for the desired target clock with
6040 * the given refclk, or FALSE. The returned values represent
6041 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6042 * 2) / p1 / p2.
6043 */
6044 limit = intel_limit(crtc, refclk);
6045 ok = dev_priv->display.find_dpll(limit, crtc,
6046 intel_crtc->config.port_clock,
6047 refclk, NULL, &clock);
6048 if (!ok) {
6049 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6050 return -EINVAL;
6051 }
6052
6053 if (is_lvds && dev_priv->lvds_downclock_avail) {
6054 /*
6055 * Ensure we match the reduced clock's P to the target
6056 * clock. If the clocks don't match, we can't switch
6057 * the display clock by using the FP0/FP1. In such case
6058 * we will disable the LVDS downclock feature.
6059 */
6060 has_reduced_clock =
6061 dev_priv->display.find_dpll(limit, crtc,
6062 dev_priv->lvds_downclock,
6063 refclk, &clock,
6064 &reduced_clock);
6065 }
6066 /* Compat-code for transition, will disappear. */
6067 intel_crtc->config.dpll.n = clock.n;
6068 intel_crtc->config.dpll.m1 = clock.m1;
6069 intel_crtc->config.dpll.m2 = clock.m2;
6070 intel_crtc->config.dpll.p1 = clock.p1;
6071 intel_crtc->config.dpll.p2 = clock.p2;
6072 }
6073
6074 if (IS_GEN2(dev)) {
6075 i8xx_update_pll(intel_crtc,
6076 has_reduced_clock ? &reduced_clock : NULL,
6077 num_connectors);
6078 } else if (IS_CHERRYVIEW(dev)) {
6079 chv_update_pll(intel_crtc);
6080 } else if (IS_VALLEYVIEW(dev)) {
6081 vlv_update_pll(intel_crtc);
6082 } else {
6083 i9xx_update_pll(intel_crtc,
6084 has_reduced_clock ? &reduced_clock : NULL,
6085 num_connectors);
6086 }
6087
6088 return 0;
6089 }
6090
6091 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6092 struct intel_crtc_config *pipe_config)
6093 {
6094 struct drm_device *dev = crtc->base.dev;
6095 struct drm_i915_private *dev_priv = dev->dev_private;
6096 uint32_t tmp;
6097
6098 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6099 return;
6100
6101 tmp = I915_READ(PFIT_CONTROL);
6102 if (!(tmp & PFIT_ENABLE))
6103 return;
6104
6105 /* Check whether the pfit is attached to our pipe. */
6106 if (INTEL_INFO(dev)->gen < 4) {
6107 if (crtc->pipe != PIPE_B)
6108 return;
6109 } else {
6110 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6111 return;
6112 }
6113
6114 pipe_config->gmch_pfit.control = tmp;
6115 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6116 if (INTEL_INFO(dev)->gen < 5)
6117 pipe_config->gmch_pfit.lvds_border_bits =
6118 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6119 }
6120
6121 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6122 struct intel_crtc_config *pipe_config)
6123 {
6124 struct drm_device *dev = crtc->base.dev;
6125 struct drm_i915_private *dev_priv = dev->dev_private;
6126 int pipe = pipe_config->cpu_transcoder;
6127 intel_clock_t clock;
6128 u32 mdiv;
6129 int refclk = 100000;
6130
6131 mutex_lock(&dev_priv->dpio_lock);
6132 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6133 mutex_unlock(&dev_priv->dpio_lock);
6134
6135 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6136 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6137 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6138 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6139 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6140
6141 vlv_clock(refclk, &clock);
6142
6143 /* clock.dot is the fast clock */
6144 pipe_config->port_clock = clock.dot / 5;
6145 }
6146
6147 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6148 struct intel_plane_config *plane_config)
6149 {
6150 struct drm_device *dev = crtc->base.dev;
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152 u32 val, base, offset;
6153 int pipe = crtc->pipe, plane = crtc->plane;
6154 int fourcc, pixel_format;
6155 int aligned_height;
6156
6157 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6158 if (!crtc->base.primary->fb) {
6159 DRM_DEBUG_KMS("failed to alloc fb\n");
6160 return;
6161 }
6162
6163 val = I915_READ(DSPCNTR(plane));
6164
6165 if (INTEL_INFO(dev)->gen >= 4)
6166 if (val & DISPPLANE_TILED)
6167 plane_config->tiled = true;
6168
6169 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6170 fourcc = intel_format_to_fourcc(pixel_format);
6171 crtc->base.primary->fb->pixel_format = fourcc;
6172 crtc->base.primary->fb->bits_per_pixel =
6173 drm_format_plane_cpp(fourcc, 0) * 8;
6174
6175 if (INTEL_INFO(dev)->gen >= 4) {
6176 if (plane_config->tiled)
6177 offset = I915_READ(DSPTILEOFF(plane));
6178 else
6179 offset = I915_READ(DSPLINOFF(plane));
6180 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6181 } else {
6182 base = I915_READ(DSPADDR(plane));
6183 }
6184 plane_config->base = base;
6185
6186 val = I915_READ(PIPESRC(pipe));
6187 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6188 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6189
6190 val = I915_READ(DSPSTRIDE(pipe));
6191 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6192
6193 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6194 plane_config->tiled);
6195
6196 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6197 aligned_height);
6198
6199 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6200 pipe, plane, crtc->base.primary->fb->width,
6201 crtc->base.primary->fb->height,
6202 crtc->base.primary->fb->bits_per_pixel, base,
6203 crtc->base.primary->fb->pitches[0],
6204 plane_config->size);
6205
6206 }
6207
6208 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6209 struct intel_crtc_config *pipe_config)
6210 {
6211 struct drm_device *dev = crtc->base.dev;
6212 struct drm_i915_private *dev_priv = dev->dev_private;
6213 int pipe = pipe_config->cpu_transcoder;
6214 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6215 intel_clock_t clock;
6216 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6217 int refclk = 100000;
6218
6219 mutex_lock(&dev_priv->dpio_lock);
6220 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6221 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6222 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6223 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6224 mutex_unlock(&dev_priv->dpio_lock);
6225
6226 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6227 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6228 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6229 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6230 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6231
6232 chv_clock(refclk, &clock);
6233
6234 /* clock.dot is the fast clock */
6235 pipe_config->port_clock = clock.dot / 5;
6236 }
6237
6238 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6239 struct intel_crtc_config *pipe_config)
6240 {
6241 struct drm_device *dev = crtc->base.dev;
6242 struct drm_i915_private *dev_priv = dev->dev_private;
6243 uint32_t tmp;
6244
6245 if (!intel_display_power_enabled(dev_priv,
6246 POWER_DOMAIN_PIPE(crtc->pipe)))
6247 return false;
6248
6249 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6250 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6251
6252 tmp = I915_READ(PIPECONF(crtc->pipe));
6253 if (!(tmp & PIPECONF_ENABLE))
6254 return false;
6255
6256 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6257 switch (tmp & PIPECONF_BPC_MASK) {
6258 case PIPECONF_6BPC:
6259 pipe_config->pipe_bpp = 18;
6260 break;
6261 case PIPECONF_8BPC:
6262 pipe_config->pipe_bpp = 24;
6263 break;
6264 case PIPECONF_10BPC:
6265 pipe_config->pipe_bpp = 30;
6266 break;
6267 default:
6268 break;
6269 }
6270 }
6271
6272 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6273 pipe_config->limited_color_range = true;
6274
6275 if (INTEL_INFO(dev)->gen < 4)
6276 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6277
6278 intel_get_pipe_timings(crtc, pipe_config);
6279
6280 i9xx_get_pfit_config(crtc, pipe_config);
6281
6282 if (INTEL_INFO(dev)->gen >= 4) {
6283 tmp = I915_READ(DPLL_MD(crtc->pipe));
6284 pipe_config->pixel_multiplier =
6285 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6286 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6287 pipe_config->dpll_hw_state.dpll_md = tmp;
6288 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6289 tmp = I915_READ(DPLL(crtc->pipe));
6290 pipe_config->pixel_multiplier =
6291 ((tmp & SDVO_MULTIPLIER_MASK)
6292 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6293 } else {
6294 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6295 * port and will be fixed up in the encoder->get_config
6296 * function. */
6297 pipe_config->pixel_multiplier = 1;
6298 }
6299 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6300 if (!IS_VALLEYVIEW(dev)) {
6301 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6302 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6303 } else {
6304 /* Mask out read-only status bits. */
6305 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6306 DPLL_PORTC_READY_MASK |
6307 DPLL_PORTB_READY_MASK);
6308 }
6309
6310 if (IS_CHERRYVIEW(dev))
6311 chv_crtc_clock_get(crtc, pipe_config);
6312 else if (IS_VALLEYVIEW(dev))
6313 vlv_crtc_clock_get(crtc, pipe_config);
6314 else
6315 i9xx_crtc_clock_get(crtc, pipe_config);
6316
6317 return true;
6318 }
6319
6320 static void ironlake_init_pch_refclk(struct drm_device *dev)
6321 {
6322 struct drm_i915_private *dev_priv = dev->dev_private;
6323 struct drm_mode_config *mode_config = &dev->mode_config;
6324 struct intel_encoder *encoder;
6325 u32 val, final;
6326 bool has_lvds = false;
6327 bool has_cpu_edp = false;
6328 bool has_panel = false;
6329 bool has_ck505 = false;
6330 bool can_ssc = false;
6331
6332 /* We need to take the global config into account */
6333 list_for_each_entry(encoder, &mode_config->encoder_list,
6334 base.head) {
6335 switch (encoder->type) {
6336 case INTEL_OUTPUT_LVDS:
6337 has_panel = true;
6338 has_lvds = true;
6339 break;
6340 case INTEL_OUTPUT_EDP:
6341 has_panel = true;
6342 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6343 has_cpu_edp = true;
6344 break;
6345 }
6346 }
6347
6348 if (HAS_PCH_IBX(dev)) {
6349 has_ck505 = dev_priv->vbt.display_clock_mode;
6350 can_ssc = has_ck505;
6351 } else {
6352 has_ck505 = false;
6353 can_ssc = true;
6354 }
6355
6356 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6357 has_panel, has_lvds, has_ck505);
6358
6359 /* Ironlake: try to setup display ref clock before DPLL
6360 * enabling. This is only under driver's control after
6361 * PCH B stepping, previous chipset stepping should be
6362 * ignoring this setting.
6363 */
6364 val = I915_READ(PCH_DREF_CONTROL);
6365
6366 /* As we must carefully and slowly disable/enable each source in turn,
6367 * compute the final state we want first and check if we need to
6368 * make any changes at all.
6369 */
6370 final = val;
6371 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6372 if (has_ck505)
6373 final |= DREF_NONSPREAD_CK505_ENABLE;
6374 else
6375 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6376
6377 final &= ~DREF_SSC_SOURCE_MASK;
6378 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6379 final &= ~DREF_SSC1_ENABLE;
6380
6381 if (has_panel) {
6382 final |= DREF_SSC_SOURCE_ENABLE;
6383
6384 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6385 final |= DREF_SSC1_ENABLE;
6386
6387 if (has_cpu_edp) {
6388 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6389 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6390 else
6391 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6392 } else
6393 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6394 } else {
6395 final |= DREF_SSC_SOURCE_DISABLE;
6396 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6397 }
6398
6399 if (final == val)
6400 return;
6401
6402 /* Always enable nonspread source */
6403 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6404
6405 if (has_ck505)
6406 val |= DREF_NONSPREAD_CK505_ENABLE;
6407 else
6408 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6409
6410 if (has_panel) {
6411 val &= ~DREF_SSC_SOURCE_MASK;
6412 val |= DREF_SSC_SOURCE_ENABLE;
6413
6414 /* SSC must be turned on before enabling the CPU output */
6415 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6416 DRM_DEBUG_KMS("Using SSC on panel\n");
6417 val |= DREF_SSC1_ENABLE;
6418 } else
6419 val &= ~DREF_SSC1_ENABLE;
6420
6421 /* Get SSC going before enabling the outputs */
6422 I915_WRITE(PCH_DREF_CONTROL, val);
6423 POSTING_READ(PCH_DREF_CONTROL);
6424 udelay(200);
6425
6426 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6427
6428 /* Enable CPU source on CPU attached eDP */
6429 if (has_cpu_edp) {
6430 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6431 DRM_DEBUG_KMS("Using SSC on eDP\n");
6432 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6433 } else
6434 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6435 } else
6436 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6437
6438 I915_WRITE(PCH_DREF_CONTROL, val);
6439 POSTING_READ(PCH_DREF_CONTROL);
6440 udelay(200);
6441 } else {
6442 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6443
6444 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6445
6446 /* Turn off CPU output */
6447 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6448
6449 I915_WRITE(PCH_DREF_CONTROL, val);
6450 POSTING_READ(PCH_DREF_CONTROL);
6451 udelay(200);
6452
6453 /* Turn off the SSC source */
6454 val &= ~DREF_SSC_SOURCE_MASK;
6455 val |= DREF_SSC_SOURCE_DISABLE;
6456
6457 /* Turn off SSC1 */
6458 val &= ~DREF_SSC1_ENABLE;
6459
6460 I915_WRITE(PCH_DREF_CONTROL, val);
6461 POSTING_READ(PCH_DREF_CONTROL);
6462 udelay(200);
6463 }
6464
6465 BUG_ON(val != final);
6466 }
6467
6468 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6469 {
6470 uint32_t tmp;
6471
6472 tmp = I915_READ(SOUTH_CHICKEN2);
6473 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6474 I915_WRITE(SOUTH_CHICKEN2, tmp);
6475
6476 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6477 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6478 DRM_ERROR("FDI mPHY reset assert timeout\n");
6479
6480 tmp = I915_READ(SOUTH_CHICKEN2);
6481 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6482 I915_WRITE(SOUTH_CHICKEN2, tmp);
6483
6484 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6485 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6486 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6487 }
6488
6489 /* WaMPhyProgramming:hsw */
6490 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6491 {
6492 uint32_t tmp;
6493
6494 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6495 tmp &= ~(0xFF << 24);
6496 tmp |= (0x12 << 24);
6497 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6498
6499 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6500 tmp |= (1 << 11);
6501 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6502
6503 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6504 tmp |= (1 << 11);
6505 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6506
6507 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6508 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6509 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6510
6511 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6512 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6513 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6514
6515 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6516 tmp &= ~(7 << 13);
6517 tmp |= (5 << 13);
6518 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6519
6520 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6521 tmp &= ~(7 << 13);
6522 tmp |= (5 << 13);
6523 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6524
6525 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6526 tmp &= ~0xFF;
6527 tmp |= 0x1C;
6528 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6529
6530 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6531 tmp &= ~0xFF;
6532 tmp |= 0x1C;
6533 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6534
6535 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6536 tmp &= ~(0xFF << 16);
6537 tmp |= (0x1C << 16);
6538 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6539
6540 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6541 tmp &= ~(0xFF << 16);
6542 tmp |= (0x1C << 16);
6543 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6544
6545 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6546 tmp |= (1 << 27);
6547 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6548
6549 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6550 tmp |= (1 << 27);
6551 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6552
6553 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6554 tmp &= ~(0xF << 28);
6555 tmp |= (4 << 28);
6556 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6557
6558 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6559 tmp &= ~(0xF << 28);
6560 tmp |= (4 << 28);
6561 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6562 }
6563
6564 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6565 * Programming" based on the parameters passed:
6566 * - Sequence to enable CLKOUT_DP
6567 * - Sequence to enable CLKOUT_DP without spread
6568 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6569 */
6570 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6571 bool with_fdi)
6572 {
6573 struct drm_i915_private *dev_priv = dev->dev_private;
6574 uint32_t reg, tmp;
6575
6576 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6577 with_spread = true;
6578 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6579 with_fdi, "LP PCH doesn't have FDI\n"))
6580 with_fdi = false;
6581
6582 mutex_lock(&dev_priv->dpio_lock);
6583
6584 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6585 tmp &= ~SBI_SSCCTL_DISABLE;
6586 tmp |= SBI_SSCCTL_PATHALT;
6587 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6588
6589 udelay(24);
6590
6591 if (with_spread) {
6592 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6593 tmp &= ~SBI_SSCCTL_PATHALT;
6594 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6595
6596 if (with_fdi) {
6597 lpt_reset_fdi_mphy(dev_priv);
6598 lpt_program_fdi_mphy(dev_priv);
6599 }
6600 }
6601
6602 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6603 SBI_GEN0 : SBI_DBUFF0;
6604 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6605 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6606 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6607
6608 mutex_unlock(&dev_priv->dpio_lock);
6609 }
6610
6611 /* Sequence to disable CLKOUT_DP */
6612 static void lpt_disable_clkout_dp(struct drm_device *dev)
6613 {
6614 struct drm_i915_private *dev_priv = dev->dev_private;
6615 uint32_t reg, tmp;
6616
6617 mutex_lock(&dev_priv->dpio_lock);
6618
6619 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6620 SBI_GEN0 : SBI_DBUFF0;
6621 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6622 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6623 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6624
6625 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6626 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6627 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6628 tmp |= SBI_SSCCTL_PATHALT;
6629 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6630 udelay(32);
6631 }
6632 tmp |= SBI_SSCCTL_DISABLE;
6633 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6634 }
6635
6636 mutex_unlock(&dev_priv->dpio_lock);
6637 }
6638
6639 static void lpt_init_pch_refclk(struct drm_device *dev)
6640 {
6641 struct drm_mode_config *mode_config = &dev->mode_config;
6642 struct intel_encoder *encoder;
6643 bool has_vga = false;
6644
6645 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6646 switch (encoder->type) {
6647 case INTEL_OUTPUT_ANALOG:
6648 has_vga = true;
6649 break;
6650 }
6651 }
6652
6653 if (has_vga)
6654 lpt_enable_clkout_dp(dev, true, true);
6655 else
6656 lpt_disable_clkout_dp(dev);
6657 }
6658
6659 /*
6660 * Initialize reference clocks when the driver loads
6661 */
6662 void intel_init_pch_refclk(struct drm_device *dev)
6663 {
6664 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6665 ironlake_init_pch_refclk(dev);
6666 else if (HAS_PCH_LPT(dev))
6667 lpt_init_pch_refclk(dev);
6668 }
6669
6670 static int ironlake_get_refclk(struct drm_crtc *crtc)
6671 {
6672 struct drm_device *dev = crtc->dev;
6673 struct drm_i915_private *dev_priv = dev->dev_private;
6674 struct intel_encoder *encoder;
6675 int num_connectors = 0;
6676 bool is_lvds = false;
6677
6678 for_each_encoder_on_crtc(dev, crtc, encoder) {
6679 switch (encoder->type) {
6680 case INTEL_OUTPUT_LVDS:
6681 is_lvds = true;
6682 break;
6683 }
6684 num_connectors++;
6685 }
6686
6687 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6688 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6689 dev_priv->vbt.lvds_ssc_freq);
6690 return dev_priv->vbt.lvds_ssc_freq;
6691 }
6692
6693 return 120000;
6694 }
6695
6696 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6697 {
6698 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6699 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6700 int pipe = intel_crtc->pipe;
6701 uint32_t val;
6702
6703 val = 0;
6704
6705 switch (intel_crtc->config.pipe_bpp) {
6706 case 18:
6707 val |= PIPECONF_6BPC;
6708 break;
6709 case 24:
6710 val |= PIPECONF_8BPC;
6711 break;
6712 case 30:
6713 val |= PIPECONF_10BPC;
6714 break;
6715 case 36:
6716 val |= PIPECONF_12BPC;
6717 break;
6718 default:
6719 /* Case prevented by intel_choose_pipe_bpp_dither. */
6720 BUG();
6721 }
6722
6723 if (intel_crtc->config.dither)
6724 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6725
6726 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6727 val |= PIPECONF_INTERLACED_ILK;
6728 else
6729 val |= PIPECONF_PROGRESSIVE;
6730
6731 if (intel_crtc->config.limited_color_range)
6732 val |= PIPECONF_COLOR_RANGE_SELECT;
6733
6734 I915_WRITE(PIPECONF(pipe), val);
6735 POSTING_READ(PIPECONF(pipe));
6736 }
6737
6738 /*
6739 * Set up the pipe CSC unit.
6740 *
6741 * Currently only full range RGB to limited range RGB conversion
6742 * is supported, but eventually this should handle various
6743 * RGB<->YCbCr scenarios as well.
6744 */
6745 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6746 {
6747 struct drm_device *dev = crtc->dev;
6748 struct drm_i915_private *dev_priv = dev->dev_private;
6749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6750 int pipe = intel_crtc->pipe;
6751 uint16_t coeff = 0x7800; /* 1.0 */
6752
6753 /*
6754 * TODO: Check what kind of values actually come out of the pipe
6755 * with these coeff/postoff values and adjust to get the best
6756 * accuracy. Perhaps we even need to take the bpc value into
6757 * consideration.
6758 */
6759
6760 if (intel_crtc->config.limited_color_range)
6761 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6762
6763 /*
6764 * GY/GU and RY/RU should be the other way around according
6765 * to BSpec, but reality doesn't agree. Just set them up in
6766 * a way that results in the correct picture.
6767 */
6768 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6769 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6770
6771 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6772 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6773
6774 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6775 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6776
6777 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6778 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6779 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6780
6781 if (INTEL_INFO(dev)->gen > 6) {
6782 uint16_t postoff = 0;
6783
6784 if (intel_crtc->config.limited_color_range)
6785 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6786
6787 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6788 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6789 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6790
6791 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6792 } else {
6793 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6794
6795 if (intel_crtc->config.limited_color_range)
6796 mode |= CSC_BLACK_SCREEN_OFFSET;
6797
6798 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6799 }
6800 }
6801
6802 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6803 {
6804 struct drm_device *dev = crtc->dev;
6805 struct drm_i915_private *dev_priv = dev->dev_private;
6806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6807 enum pipe pipe = intel_crtc->pipe;
6808 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6809 uint32_t val;
6810
6811 val = 0;
6812
6813 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6814 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6815
6816 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6817 val |= PIPECONF_INTERLACED_ILK;
6818 else
6819 val |= PIPECONF_PROGRESSIVE;
6820
6821 I915_WRITE(PIPECONF(cpu_transcoder), val);
6822 POSTING_READ(PIPECONF(cpu_transcoder));
6823
6824 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6825 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6826
6827 if (IS_BROADWELL(dev)) {
6828 val = 0;
6829
6830 switch (intel_crtc->config.pipe_bpp) {
6831 case 18:
6832 val |= PIPEMISC_DITHER_6_BPC;
6833 break;
6834 case 24:
6835 val |= PIPEMISC_DITHER_8_BPC;
6836 break;
6837 case 30:
6838 val |= PIPEMISC_DITHER_10_BPC;
6839 break;
6840 case 36:
6841 val |= PIPEMISC_DITHER_12_BPC;
6842 break;
6843 default:
6844 /* Case prevented by pipe_config_set_bpp. */
6845 BUG();
6846 }
6847
6848 if (intel_crtc->config.dither)
6849 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6850
6851 I915_WRITE(PIPEMISC(pipe), val);
6852 }
6853 }
6854
6855 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6856 intel_clock_t *clock,
6857 bool *has_reduced_clock,
6858 intel_clock_t *reduced_clock)
6859 {
6860 struct drm_device *dev = crtc->dev;
6861 struct drm_i915_private *dev_priv = dev->dev_private;
6862 struct intel_encoder *intel_encoder;
6863 int refclk;
6864 const intel_limit_t *limit;
6865 bool ret, is_lvds = false;
6866
6867 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6868 switch (intel_encoder->type) {
6869 case INTEL_OUTPUT_LVDS:
6870 is_lvds = true;
6871 break;
6872 }
6873 }
6874
6875 refclk = ironlake_get_refclk(crtc);
6876
6877 /*
6878 * Returns a set of divisors for the desired target clock with the given
6879 * refclk, or FALSE. The returned values represent the clock equation:
6880 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6881 */
6882 limit = intel_limit(crtc, refclk);
6883 ret = dev_priv->display.find_dpll(limit, crtc,
6884 to_intel_crtc(crtc)->config.port_clock,
6885 refclk, NULL, clock);
6886 if (!ret)
6887 return false;
6888
6889 if (is_lvds && dev_priv->lvds_downclock_avail) {
6890 /*
6891 * Ensure we match the reduced clock's P to the target clock.
6892 * If the clocks don't match, we can't switch the display clock
6893 * by using the FP0/FP1. In such case we will disable the LVDS
6894 * downclock feature.
6895 */
6896 *has_reduced_clock =
6897 dev_priv->display.find_dpll(limit, crtc,
6898 dev_priv->lvds_downclock,
6899 refclk, clock,
6900 reduced_clock);
6901 }
6902
6903 return true;
6904 }
6905
6906 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6907 {
6908 /*
6909 * Account for spread spectrum to avoid
6910 * oversubscribing the link. Max center spread
6911 * is 2.5%; use 5% for safety's sake.
6912 */
6913 u32 bps = target_clock * bpp * 21 / 20;
6914 return DIV_ROUND_UP(bps, link_bw * 8);
6915 }
6916
6917 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6918 {
6919 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6920 }
6921
6922 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6923 u32 *fp,
6924 intel_clock_t *reduced_clock, u32 *fp2)
6925 {
6926 struct drm_crtc *crtc = &intel_crtc->base;
6927 struct drm_device *dev = crtc->dev;
6928 struct drm_i915_private *dev_priv = dev->dev_private;
6929 struct intel_encoder *intel_encoder;
6930 uint32_t dpll;
6931 int factor, num_connectors = 0;
6932 bool is_lvds = false, is_sdvo = false;
6933
6934 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6935 switch (intel_encoder->type) {
6936 case INTEL_OUTPUT_LVDS:
6937 is_lvds = true;
6938 break;
6939 case INTEL_OUTPUT_SDVO:
6940 case INTEL_OUTPUT_HDMI:
6941 is_sdvo = true;
6942 break;
6943 }
6944
6945 num_connectors++;
6946 }
6947
6948 /* Enable autotuning of the PLL clock (if permissible) */
6949 factor = 21;
6950 if (is_lvds) {
6951 if ((intel_panel_use_ssc(dev_priv) &&
6952 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6953 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6954 factor = 25;
6955 } else if (intel_crtc->config.sdvo_tv_clock)
6956 factor = 20;
6957
6958 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6959 *fp |= FP_CB_TUNE;
6960
6961 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6962 *fp2 |= FP_CB_TUNE;
6963
6964 dpll = 0;
6965
6966 if (is_lvds)
6967 dpll |= DPLLB_MODE_LVDS;
6968 else
6969 dpll |= DPLLB_MODE_DAC_SERIAL;
6970
6971 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6972 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6973
6974 if (is_sdvo)
6975 dpll |= DPLL_SDVO_HIGH_SPEED;
6976 if (intel_crtc->config.has_dp_encoder)
6977 dpll |= DPLL_SDVO_HIGH_SPEED;
6978
6979 /* compute bitmask from p1 value */
6980 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6981 /* also FPA1 */
6982 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6983
6984 switch (intel_crtc->config.dpll.p2) {
6985 case 5:
6986 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6987 break;
6988 case 7:
6989 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6990 break;
6991 case 10:
6992 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6993 break;
6994 case 14:
6995 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6996 break;
6997 }
6998
6999 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7000 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7001 else
7002 dpll |= PLL_REF_INPUT_DREFCLK;
7003
7004 return dpll | DPLL_VCO_ENABLE;
7005 }
7006
7007 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
7008 int x, int y,
7009 struct drm_framebuffer *fb)
7010 {
7011 struct drm_device *dev = crtc->dev;
7012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7013 int num_connectors = 0;
7014 intel_clock_t clock, reduced_clock;
7015 u32 dpll = 0, fp = 0, fp2 = 0;
7016 bool ok, has_reduced_clock = false;
7017 bool is_lvds = false;
7018 struct intel_encoder *encoder;
7019 struct intel_shared_dpll *pll;
7020
7021 for_each_encoder_on_crtc(dev, crtc, encoder) {
7022 switch (encoder->type) {
7023 case INTEL_OUTPUT_LVDS:
7024 is_lvds = true;
7025 break;
7026 }
7027
7028 num_connectors++;
7029 }
7030
7031 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7032 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7033
7034 ok = ironlake_compute_clocks(crtc, &clock,
7035 &has_reduced_clock, &reduced_clock);
7036 if (!ok && !intel_crtc->config.clock_set) {
7037 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7038 return -EINVAL;
7039 }
7040 /* Compat-code for transition, will disappear. */
7041 if (!intel_crtc->config.clock_set) {
7042 intel_crtc->config.dpll.n = clock.n;
7043 intel_crtc->config.dpll.m1 = clock.m1;
7044 intel_crtc->config.dpll.m2 = clock.m2;
7045 intel_crtc->config.dpll.p1 = clock.p1;
7046 intel_crtc->config.dpll.p2 = clock.p2;
7047 }
7048
7049 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7050 if (intel_crtc->config.has_pch_encoder) {
7051 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7052 if (has_reduced_clock)
7053 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7054
7055 dpll = ironlake_compute_dpll(intel_crtc,
7056 &fp, &reduced_clock,
7057 has_reduced_clock ? &fp2 : NULL);
7058
7059 intel_crtc->config.dpll_hw_state.dpll = dpll;
7060 intel_crtc->config.dpll_hw_state.fp0 = fp;
7061 if (has_reduced_clock)
7062 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7063 else
7064 intel_crtc->config.dpll_hw_state.fp1 = fp;
7065
7066 pll = intel_get_shared_dpll(intel_crtc);
7067 if (pll == NULL) {
7068 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7069 pipe_name(intel_crtc->pipe));
7070 return -EINVAL;
7071 }
7072 } else
7073 intel_put_shared_dpll(intel_crtc);
7074
7075 if (is_lvds && has_reduced_clock && i915.powersave)
7076 intel_crtc->lowfreq_avail = true;
7077 else
7078 intel_crtc->lowfreq_avail = false;
7079
7080 return 0;
7081 }
7082
7083 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7084 struct intel_link_m_n *m_n)
7085 {
7086 struct drm_device *dev = crtc->base.dev;
7087 struct drm_i915_private *dev_priv = dev->dev_private;
7088 enum pipe pipe = crtc->pipe;
7089
7090 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7091 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7092 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7093 & ~TU_SIZE_MASK;
7094 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7095 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7096 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7097 }
7098
7099 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7100 enum transcoder transcoder,
7101 struct intel_link_m_n *m_n)
7102 {
7103 struct drm_device *dev = crtc->base.dev;
7104 struct drm_i915_private *dev_priv = dev->dev_private;
7105 enum pipe pipe = crtc->pipe;
7106
7107 if (INTEL_INFO(dev)->gen >= 5) {
7108 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7109 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7110 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7111 & ~TU_SIZE_MASK;
7112 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7113 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7114 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7115 } else {
7116 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7117 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7118 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7119 & ~TU_SIZE_MASK;
7120 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7121 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7122 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7123 }
7124 }
7125
7126 void intel_dp_get_m_n(struct intel_crtc *crtc,
7127 struct intel_crtc_config *pipe_config)
7128 {
7129 if (crtc->config.has_pch_encoder)
7130 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7131 else
7132 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7133 &pipe_config->dp_m_n);
7134 }
7135
7136 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7137 struct intel_crtc_config *pipe_config)
7138 {
7139 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7140 &pipe_config->fdi_m_n);
7141 }
7142
7143 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7144 struct intel_crtc_config *pipe_config)
7145 {
7146 struct drm_device *dev = crtc->base.dev;
7147 struct drm_i915_private *dev_priv = dev->dev_private;
7148 uint32_t tmp;
7149
7150 tmp = I915_READ(PF_CTL(crtc->pipe));
7151
7152 if (tmp & PF_ENABLE) {
7153 pipe_config->pch_pfit.enabled = true;
7154 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7155 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7156
7157 /* We currently do not free assignements of panel fitters on
7158 * ivb/hsw (since we don't use the higher upscaling modes which
7159 * differentiates them) so just WARN about this case for now. */
7160 if (IS_GEN7(dev)) {
7161 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7162 PF_PIPE_SEL_IVB(crtc->pipe));
7163 }
7164 }
7165 }
7166
7167 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7168 struct intel_plane_config *plane_config)
7169 {
7170 struct drm_device *dev = crtc->base.dev;
7171 struct drm_i915_private *dev_priv = dev->dev_private;
7172 u32 val, base, offset;
7173 int pipe = crtc->pipe, plane = crtc->plane;
7174 int fourcc, pixel_format;
7175 int aligned_height;
7176
7177 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7178 if (!crtc->base.primary->fb) {
7179 DRM_DEBUG_KMS("failed to alloc fb\n");
7180 return;
7181 }
7182
7183 val = I915_READ(DSPCNTR(plane));
7184
7185 if (INTEL_INFO(dev)->gen >= 4)
7186 if (val & DISPPLANE_TILED)
7187 plane_config->tiled = true;
7188
7189 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7190 fourcc = intel_format_to_fourcc(pixel_format);
7191 crtc->base.primary->fb->pixel_format = fourcc;
7192 crtc->base.primary->fb->bits_per_pixel =
7193 drm_format_plane_cpp(fourcc, 0) * 8;
7194
7195 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7196 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7197 offset = I915_READ(DSPOFFSET(plane));
7198 } else {
7199 if (plane_config->tiled)
7200 offset = I915_READ(DSPTILEOFF(plane));
7201 else
7202 offset = I915_READ(DSPLINOFF(plane));
7203 }
7204 plane_config->base = base;
7205
7206 val = I915_READ(PIPESRC(pipe));
7207 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7208 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7209
7210 val = I915_READ(DSPSTRIDE(pipe));
7211 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7212
7213 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7214 plane_config->tiled);
7215
7216 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7217 aligned_height);
7218
7219 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7220 pipe, plane, crtc->base.primary->fb->width,
7221 crtc->base.primary->fb->height,
7222 crtc->base.primary->fb->bits_per_pixel, base,
7223 crtc->base.primary->fb->pitches[0],
7224 plane_config->size);
7225 }
7226
7227 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7228 struct intel_crtc_config *pipe_config)
7229 {
7230 struct drm_device *dev = crtc->base.dev;
7231 struct drm_i915_private *dev_priv = dev->dev_private;
7232 uint32_t tmp;
7233
7234 if (!intel_display_power_enabled(dev_priv,
7235 POWER_DOMAIN_PIPE(crtc->pipe)))
7236 return false;
7237
7238 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7239 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7240
7241 tmp = I915_READ(PIPECONF(crtc->pipe));
7242 if (!(tmp & PIPECONF_ENABLE))
7243 return false;
7244
7245 switch (tmp & PIPECONF_BPC_MASK) {
7246 case PIPECONF_6BPC:
7247 pipe_config->pipe_bpp = 18;
7248 break;
7249 case PIPECONF_8BPC:
7250 pipe_config->pipe_bpp = 24;
7251 break;
7252 case PIPECONF_10BPC:
7253 pipe_config->pipe_bpp = 30;
7254 break;
7255 case PIPECONF_12BPC:
7256 pipe_config->pipe_bpp = 36;
7257 break;
7258 default:
7259 break;
7260 }
7261
7262 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7263 pipe_config->limited_color_range = true;
7264
7265 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7266 struct intel_shared_dpll *pll;
7267
7268 pipe_config->has_pch_encoder = true;
7269
7270 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7271 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7272 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7273
7274 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7275
7276 if (HAS_PCH_IBX(dev_priv->dev)) {
7277 pipe_config->shared_dpll =
7278 (enum intel_dpll_id) crtc->pipe;
7279 } else {
7280 tmp = I915_READ(PCH_DPLL_SEL);
7281 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7282 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7283 else
7284 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7285 }
7286
7287 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7288
7289 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7290 &pipe_config->dpll_hw_state));
7291
7292 tmp = pipe_config->dpll_hw_state.dpll;
7293 pipe_config->pixel_multiplier =
7294 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7295 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7296
7297 ironlake_pch_clock_get(crtc, pipe_config);
7298 } else {
7299 pipe_config->pixel_multiplier = 1;
7300 }
7301
7302 intel_get_pipe_timings(crtc, pipe_config);
7303
7304 ironlake_get_pfit_config(crtc, pipe_config);
7305
7306 return true;
7307 }
7308
7309 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7310 {
7311 struct drm_device *dev = dev_priv->dev;
7312 struct intel_crtc *crtc;
7313
7314 for_each_intel_crtc(dev, crtc)
7315 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7316 pipe_name(crtc->pipe));
7317
7318 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7319 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7320 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7321 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7322 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7323 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7324 "CPU PWM1 enabled\n");
7325 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7326 "CPU PWM2 enabled\n");
7327 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7328 "PCH PWM1 enabled\n");
7329 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7330 "Utility pin enabled\n");
7331 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7332
7333 /*
7334 * In theory we can still leave IRQs enabled, as long as only the HPD
7335 * interrupts remain enabled. We used to check for that, but since it's
7336 * gen-specific and since we only disable LCPLL after we fully disable
7337 * the interrupts, the check below should be enough.
7338 */
7339 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7340 }
7341
7342 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7343 {
7344 struct drm_device *dev = dev_priv->dev;
7345
7346 if (IS_HASWELL(dev))
7347 return I915_READ(D_COMP_HSW);
7348 else
7349 return I915_READ(D_COMP_BDW);
7350 }
7351
7352 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7353 {
7354 struct drm_device *dev = dev_priv->dev;
7355
7356 if (IS_HASWELL(dev)) {
7357 mutex_lock(&dev_priv->rps.hw_lock);
7358 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7359 val))
7360 DRM_ERROR("Failed to write to D_COMP\n");
7361 mutex_unlock(&dev_priv->rps.hw_lock);
7362 } else {
7363 I915_WRITE(D_COMP_BDW, val);
7364 POSTING_READ(D_COMP_BDW);
7365 }
7366 }
7367
7368 /*
7369 * This function implements pieces of two sequences from BSpec:
7370 * - Sequence for display software to disable LCPLL
7371 * - Sequence for display software to allow package C8+
7372 * The steps implemented here are just the steps that actually touch the LCPLL
7373 * register. Callers should take care of disabling all the display engine
7374 * functions, doing the mode unset, fixing interrupts, etc.
7375 */
7376 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7377 bool switch_to_fclk, bool allow_power_down)
7378 {
7379 uint32_t val;
7380
7381 assert_can_disable_lcpll(dev_priv);
7382
7383 val = I915_READ(LCPLL_CTL);
7384
7385 if (switch_to_fclk) {
7386 val |= LCPLL_CD_SOURCE_FCLK;
7387 I915_WRITE(LCPLL_CTL, val);
7388
7389 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7390 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7391 DRM_ERROR("Switching to FCLK failed\n");
7392
7393 val = I915_READ(LCPLL_CTL);
7394 }
7395
7396 val |= LCPLL_PLL_DISABLE;
7397 I915_WRITE(LCPLL_CTL, val);
7398 POSTING_READ(LCPLL_CTL);
7399
7400 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7401 DRM_ERROR("LCPLL still locked\n");
7402
7403 val = hsw_read_dcomp(dev_priv);
7404 val |= D_COMP_COMP_DISABLE;
7405 hsw_write_dcomp(dev_priv, val);
7406 ndelay(100);
7407
7408 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7409 1))
7410 DRM_ERROR("D_COMP RCOMP still in progress\n");
7411
7412 if (allow_power_down) {
7413 val = I915_READ(LCPLL_CTL);
7414 val |= LCPLL_POWER_DOWN_ALLOW;
7415 I915_WRITE(LCPLL_CTL, val);
7416 POSTING_READ(LCPLL_CTL);
7417 }
7418 }
7419
7420 /*
7421 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7422 * source.
7423 */
7424 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7425 {
7426 uint32_t val;
7427 unsigned long irqflags;
7428
7429 val = I915_READ(LCPLL_CTL);
7430
7431 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7432 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7433 return;
7434
7435 /*
7436 * Make sure we're not on PC8 state before disabling PC8, otherwise
7437 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7438 *
7439 * The other problem is that hsw_restore_lcpll() is called as part of
7440 * the runtime PM resume sequence, so we can't just call
7441 * gen6_gt_force_wake_get() because that function calls
7442 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7443 * while we are on the resume sequence. So to solve this problem we have
7444 * to call special forcewake code that doesn't touch runtime PM and
7445 * doesn't enable the forcewake delayed work.
7446 */
7447 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7448 if (dev_priv->uncore.forcewake_count++ == 0)
7449 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7450 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7451
7452 if (val & LCPLL_POWER_DOWN_ALLOW) {
7453 val &= ~LCPLL_POWER_DOWN_ALLOW;
7454 I915_WRITE(LCPLL_CTL, val);
7455 POSTING_READ(LCPLL_CTL);
7456 }
7457
7458 val = hsw_read_dcomp(dev_priv);
7459 val |= D_COMP_COMP_FORCE;
7460 val &= ~D_COMP_COMP_DISABLE;
7461 hsw_write_dcomp(dev_priv, val);
7462
7463 val = I915_READ(LCPLL_CTL);
7464 val &= ~LCPLL_PLL_DISABLE;
7465 I915_WRITE(LCPLL_CTL, val);
7466
7467 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7468 DRM_ERROR("LCPLL not locked yet\n");
7469
7470 if (val & LCPLL_CD_SOURCE_FCLK) {
7471 val = I915_READ(LCPLL_CTL);
7472 val &= ~LCPLL_CD_SOURCE_FCLK;
7473 I915_WRITE(LCPLL_CTL, val);
7474
7475 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7476 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7477 DRM_ERROR("Switching back to LCPLL failed\n");
7478 }
7479
7480 /* See the big comment above. */
7481 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7482 if (--dev_priv->uncore.forcewake_count == 0)
7483 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7484 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7485 }
7486
7487 /*
7488 * Package states C8 and deeper are really deep PC states that can only be
7489 * reached when all the devices on the system allow it, so even if the graphics
7490 * device allows PC8+, it doesn't mean the system will actually get to these
7491 * states. Our driver only allows PC8+ when going into runtime PM.
7492 *
7493 * The requirements for PC8+ are that all the outputs are disabled, the power
7494 * well is disabled and most interrupts are disabled, and these are also
7495 * requirements for runtime PM. When these conditions are met, we manually do
7496 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7497 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7498 * hang the machine.
7499 *
7500 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7501 * the state of some registers, so when we come back from PC8+ we need to
7502 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7503 * need to take care of the registers kept by RC6. Notice that this happens even
7504 * if we don't put the device in PCI D3 state (which is what currently happens
7505 * because of the runtime PM support).
7506 *
7507 * For more, read "Display Sequences for Package C8" on the hardware
7508 * documentation.
7509 */
7510 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7511 {
7512 struct drm_device *dev = dev_priv->dev;
7513 uint32_t val;
7514
7515 DRM_DEBUG_KMS("Enabling package C8+\n");
7516
7517 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7518 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7519 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7520 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7521 }
7522
7523 lpt_disable_clkout_dp(dev);
7524 hsw_disable_lcpll(dev_priv, true, true);
7525 }
7526
7527 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7528 {
7529 struct drm_device *dev = dev_priv->dev;
7530 uint32_t val;
7531
7532 DRM_DEBUG_KMS("Disabling package C8+\n");
7533
7534 hsw_restore_lcpll(dev_priv);
7535 lpt_init_pch_refclk(dev);
7536
7537 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7538 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7539 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7540 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7541 }
7542
7543 intel_prepare_ddi(dev);
7544 }
7545
7546 static void snb_modeset_global_resources(struct drm_device *dev)
7547 {
7548 modeset_update_crtc_power_domains(dev);
7549 }
7550
7551 static void haswell_modeset_global_resources(struct drm_device *dev)
7552 {
7553 modeset_update_crtc_power_domains(dev);
7554 }
7555
7556 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7557 int x, int y,
7558 struct drm_framebuffer *fb)
7559 {
7560 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7561
7562 if (!intel_ddi_pll_select(intel_crtc))
7563 return -EINVAL;
7564
7565 intel_crtc->lowfreq_avail = false;
7566
7567 return 0;
7568 }
7569
7570 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7571 struct intel_crtc_config *pipe_config)
7572 {
7573 struct drm_device *dev = crtc->base.dev;
7574 struct drm_i915_private *dev_priv = dev->dev_private;
7575 struct intel_shared_dpll *pll;
7576 enum port port;
7577 uint32_t tmp;
7578
7579 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7580
7581 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7582
7583 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7584
7585 switch (pipe_config->ddi_pll_sel) {
7586 case PORT_CLK_SEL_WRPLL1:
7587 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7588 break;
7589 case PORT_CLK_SEL_WRPLL2:
7590 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7591 break;
7592 }
7593
7594 if (pipe_config->shared_dpll >= 0) {
7595 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7596
7597 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7598 &pipe_config->dpll_hw_state));
7599 }
7600
7601 /*
7602 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7603 * DDI E. So just check whether this pipe is wired to DDI E and whether
7604 * the PCH transcoder is on.
7605 */
7606 if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7607 pipe_config->has_pch_encoder = true;
7608
7609 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7610 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7611 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7612
7613 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7614 }
7615 }
7616
7617 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7618 struct intel_crtc_config *pipe_config)
7619 {
7620 struct drm_device *dev = crtc->base.dev;
7621 struct drm_i915_private *dev_priv = dev->dev_private;
7622 enum intel_display_power_domain pfit_domain;
7623 uint32_t tmp;
7624
7625 if (!intel_display_power_enabled(dev_priv,
7626 POWER_DOMAIN_PIPE(crtc->pipe)))
7627 return false;
7628
7629 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7630 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7631
7632 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7633 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7634 enum pipe trans_edp_pipe;
7635 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7636 default:
7637 WARN(1, "unknown pipe linked to edp transcoder\n");
7638 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7639 case TRANS_DDI_EDP_INPUT_A_ON:
7640 trans_edp_pipe = PIPE_A;
7641 break;
7642 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7643 trans_edp_pipe = PIPE_B;
7644 break;
7645 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7646 trans_edp_pipe = PIPE_C;
7647 break;
7648 }
7649
7650 if (trans_edp_pipe == crtc->pipe)
7651 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7652 }
7653
7654 if (!intel_display_power_enabled(dev_priv,
7655 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7656 return false;
7657
7658 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7659 if (!(tmp & PIPECONF_ENABLE))
7660 return false;
7661
7662 haswell_get_ddi_port_state(crtc, pipe_config);
7663
7664 intel_get_pipe_timings(crtc, pipe_config);
7665
7666 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7667 if (intel_display_power_enabled(dev_priv, pfit_domain))
7668 ironlake_get_pfit_config(crtc, pipe_config);
7669
7670 if (IS_HASWELL(dev))
7671 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7672 (I915_READ(IPS_CTL) & IPS_ENABLE);
7673
7674 pipe_config->pixel_multiplier = 1;
7675
7676 return true;
7677 }
7678
7679 static struct {
7680 int clock;
7681 u32 config;
7682 } hdmi_audio_clock[] = {
7683 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7684 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7685 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7686 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7687 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7688 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7689 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7690 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7691 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7692 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7693 };
7694
7695 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7696 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7697 {
7698 int i;
7699
7700 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7701 if (mode->clock == hdmi_audio_clock[i].clock)
7702 break;
7703 }
7704
7705 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7706 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7707 i = 1;
7708 }
7709
7710 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7711 hdmi_audio_clock[i].clock,
7712 hdmi_audio_clock[i].config);
7713
7714 return hdmi_audio_clock[i].config;
7715 }
7716
7717 static bool intel_eld_uptodate(struct drm_connector *connector,
7718 int reg_eldv, uint32_t bits_eldv,
7719 int reg_elda, uint32_t bits_elda,
7720 int reg_edid)
7721 {
7722 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7723 uint8_t *eld = connector->eld;
7724 uint32_t i;
7725
7726 i = I915_READ(reg_eldv);
7727 i &= bits_eldv;
7728
7729 if (!eld[0])
7730 return !i;
7731
7732 if (!i)
7733 return false;
7734
7735 i = I915_READ(reg_elda);
7736 i &= ~bits_elda;
7737 I915_WRITE(reg_elda, i);
7738
7739 for (i = 0; i < eld[2]; i++)
7740 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7741 return false;
7742
7743 return true;
7744 }
7745
7746 static void g4x_write_eld(struct drm_connector *connector,
7747 struct drm_crtc *crtc,
7748 struct drm_display_mode *mode)
7749 {
7750 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7751 uint8_t *eld = connector->eld;
7752 uint32_t eldv;
7753 uint32_t len;
7754 uint32_t i;
7755
7756 i = I915_READ(G4X_AUD_VID_DID);
7757
7758 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7759 eldv = G4X_ELDV_DEVCL_DEVBLC;
7760 else
7761 eldv = G4X_ELDV_DEVCTG;
7762
7763 if (intel_eld_uptodate(connector,
7764 G4X_AUD_CNTL_ST, eldv,
7765 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7766 G4X_HDMIW_HDMIEDID))
7767 return;
7768
7769 i = I915_READ(G4X_AUD_CNTL_ST);
7770 i &= ~(eldv | G4X_ELD_ADDR);
7771 len = (i >> 9) & 0x1f; /* ELD buffer size */
7772 I915_WRITE(G4X_AUD_CNTL_ST, i);
7773
7774 if (!eld[0])
7775 return;
7776
7777 len = min_t(uint8_t, eld[2], len);
7778 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7779 for (i = 0; i < len; i++)
7780 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7781
7782 i = I915_READ(G4X_AUD_CNTL_ST);
7783 i |= eldv;
7784 I915_WRITE(G4X_AUD_CNTL_ST, i);
7785 }
7786
7787 static void haswell_write_eld(struct drm_connector *connector,
7788 struct drm_crtc *crtc,
7789 struct drm_display_mode *mode)
7790 {
7791 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7792 uint8_t *eld = connector->eld;
7793 uint32_t eldv;
7794 uint32_t i;
7795 int len;
7796 int pipe = to_intel_crtc(crtc)->pipe;
7797 int tmp;
7798
7799 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7800 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7801 int aud_config = HSW_AUD_CFG(pipe);
7802 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7803
7804 /* Audio output enable */
7805 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7806 tmp = I915_READ(aud_cntrl_st2);
7807 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7808 I915_WRITE(aud_cntrl_st2, tmp);
7809 POSTING_READ(aud_cntrl_st2);
7810
7811 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7812
7813 /* Set ELD valid state */
7814 tmp = I915_READ(aud_cntrl_st2);
7815 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7816 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7817 I915_WRITE(aud_cntrl_st2, tmp);
7818 tmp = I915_READ(aud_cntrl_st2);
7819 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7820
7821 /* Enable HDMI mode */
7822 tmp = I915_READ(aud_config);
7823 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7824 /* clear N_programing_enable and N_value_index */
7825 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7826 I915_WRITE(aud_config, tmp);
7827
7828 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7829
7830 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7831
7832 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7833 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7834 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7835 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7836 } else {
7837 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7838 }
7839
7840 if (intel_eld_uptodate(connector,
7841 aud_cntrl_st2, eldv,
7842 aud_cntl_st, IBX_ELD_ADDRESS,
7843 hdmiw_hdmiedid))
7844 return;
7845
7846 i = I915_READ(aud_cntrl_st2);
7847 i &= ~eldv;
7848 I915_WRITE(aud_cntrl_st2, i);
7849
7850 if (!eld[0])
7851 return;
7852
7853 i = I915_READ(aud_cntl_st);
7854 i &= ~IBX_ELD_ADDRESS;
7855 I915_WRITE(aud_cntl_st, i);
7856 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7857 DRM_DEBUG_DRIVER("port num:%d\n", i);
7858
7859 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7860 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7861 for (i = 0; i < len; i++)
7862 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7863
7864 i = I915_READ(aud_cntrl_st2);
7865 i |= eldv;
7866 I915_WRITE(aud_cntrl_st2, i);
7867
7868 }
7869
7870 static void ironlake_write_eld(struct drm_connector *connector,
7871 struct drm_crtc *crtc,
7872 struct drm_display_mode *mode)
7873 {
7874 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7875 uint8_t *eld = connector->eld;
7876 uint32_t eldv;
7877 uint32_t i;
7878 int len;
7879 int hdmiw_hdmiedid;
7880 int aud_config;
7881 int aud_cntl_st;
7882 int aud_cntrl_st2;
7883 int pipe = to_intel_crtc(crtc)->pipe;
7884
7885 if (HAS_PCH_IBX(connector->dev)) {
7886 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7887 aud_config = IBX_AUD_CFG(pipe);
7888 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7889 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7890 } else if (IS_VALLEYVIEW(connector->dev)) {
7891 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7892 aud_config = VLV_AUD_CFG(pipe);
7893 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7894 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7895 } else {
7896 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7897 aud_config = CPT_AUD_CFG(pipe);
7898 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7899 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7900 }
7901
7902 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7903
7904 if (IS_VALLEYVIEW(connector->dev)) {
7905 struct intel_encoder *intel_encoder;
7906 struct intel_digital_port *intel_dig_port;
7907
7908 intel_encoder = intel_attached_encoder(connector);
7909 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7910 i = intel_dig_port->port;
7911 } else {
7912 i = I915_READ(aud_cntl_st);
7913 i = (i >> 29) & DIP_PORT_SEL_MASK;
7914 /* DIP_Port_Select, 0x1 = PortB */
7915 }
7916
7917 if (!i) {
7918 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7919 /* operate blindly on all ports */
7920 eldv = IBX_ELD_VALIDB;
7921 eldv |= IBX_ELD_VALIDB << 4;
7922 eldv |= IBX_ELD_VALIDB << 8;
7923 } else {
7924 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7925 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7926 }
7927
7928 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7929 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7930 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7931 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7932 } else {
7933 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7934 }
7935
7936 if (intel_eld_uptodate(connector,
7937 aud_cntrl_st2, eldv,
7938 aud_cntl_st, IBX_ELD_ADDRESS,
7939 hdmiw_hdmiedid))
7940 return;
7941
7942 i = I915_READ(aud_cntrl_st2);
7943 i &= ~eldv;
7944 I915_WRITE(aud_cntrl_st2, i);
7945
7946 if (!eld[0])
7947 return;
7948
7949 i = I915_READ(aud_cntl_st);
7950 i &= ~IBX_ELD_ADDRESS;
7951 I915_WRITE(aud_cntl_st, i);
7952
7953 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7954 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7955 for (i = 0; i < len; i++)
7956 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7957
7958 i = I915_READ(aud_cntrl_st2);
7959 i |= eldv;
7960 I915_WRITE(aud_cntrl_st2, i);
7961 }
7962
7963 void intel_write_eld(struct drm_encoder *encoder,
7964 struct drm_display_mode *mode)
7965 {
7966 struct drm_crtc *crtc = encoder->crtc;
7967 struct drm_connector *connector;
7968 struct drm_device *dev = encoder->dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7970
7971 connector = drm_select_eld(encoder, mode);
7972 if (!connector)
7973 return;
7974
7975 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7976 connector->base.id,
7977 connector->name,
7978 connector->encoder->base.id,
7979 connector->encoder->name);
7980
7981 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7982
7983 if (dev_priv->display.write_eld)
7984 dev_priv->display.write_eld(connector, crtc, mode);
7985 }
7986
7987 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7988 {
7989 struct drm_device *dev = crtc->dev;
7990 struct drm_i915_private *dev_priv = dev->dev_private;
7991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7992 uint32_t cntl;
7993
7994 if (base != intel_crtc->cursor_base) {
7995 /* On these chipsets we can only modify the base whilst
7996 * the cursor is disabled.
7997 */
7998 if (intel_crtc->cursor_cntl) {
7999 I915_WRITE(_CURACNTR, 0);
8000 POSTING_READ(_CURACNTR);
8001 intel_crtc->cursor_cntl = 0;
8002 }
8003
8004 I915_WRITE(_CURABASE, base);
8005 POSTING_READ(_CURABASE);
8006 }
8007
8008 /* XXX width must be 64, stride 256 => 0x00 << 28 */
8009 cntl = 0;
8010 if (base)
8011 cntl = (CURSOR_ENABLE |
8012 CURSOR_GAMMA_ENABLE |
8013 CURSOR_FORMAT_ARGB);
8014 if (intel_crtc->cursor_cntl != cntl) {
8015 I915_WRITE(_CURACNTR, cntl);
8016 POSTING_READ(_CURACNTR);
8017 intel_crtc->cursor_cntl = cntl;
8018 }
8019 }
8020
8021 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8022 {
8023 struct drm_device *dev = crtc->dev;
8024 struct drm_i915_private *dev_priv = dev->dev_private;
8025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8026 int pipe = intel_crtc->pipe;
8027 uint32_t cntl;
8028
8029 cntl = 0;
8030 if (base) {
8031 cntl = MCURSOR_GAMMA_ENABLE;
8032 switch (intel_crtc->cursor_width) {
8033 case 64:
8034 cntl |= CURSOR_MODE_64_ARGB_AX;
8035 break;
8036 case 128:
8037 cntl |= CURSOR_MODE_128_ARGB_AX;
8038 break;
8039 case 256:
8040 cntl |= CURSOR_MODE_256_ARGB_AX;
8041 break;
8042 default:
8043 WARN_ON(1);
8044 return;
8045 }
8046 cntl |= pipe << 28; /* Connect to correct pipe */
8047 }
8048 if (intel_crtc->cursor_cntl != cntl) {
8049 I915_WRITE(CURCNTR(pipe), cntl);
8050 POSTING_READ(CURCNTR(pipe));
8051 intel_crtc->cursor_cntl = cntl;
8052 }
8053
8054 /* and commit changes on next vblank */
8055 I915_WRITE(CURBASE(pipe), base);
8056 POSTING_READ(CURBASE(pipe));
8057 }
8058
8059 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8060 {
8061 struct drm_device *dev = crtc->dev;
8062 struct drm_i915_private *dev_priv = dev->dev_private;
8063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8064 int pipe = intel_crtc->pipe;
8065 uint32_t cntl;
8066
8067 cntl = 0;
8068 if (base) {
8069 cntl = MCURSOR_GAMMA_ENABLE;
8070 switch (intel_crtc->cursor_width) {
8071 case 64:
8072 cntl |= CURSOR_MODE_64_ARGB_AX;
8073 break;
8074 case 128:
8075 cntl |= CURSOR_MODE_128_ARGB_AX;
8076 break;
8077 case 256:
8078 cntl |= CURSOR_MODE_256_ARGB_AX;
8079 break;
8080 default:
8081 WARN_ON(1);
8082 return;
8083 }
8084 }
8085 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8086 cntl |= CURSOR_PIPE_CSC_ENABLE;
8087
8088 if (intel_crtc->cursor_cntl != cntl) {
8089 I915_WRITE(CURCNTR(pipe), cntl);
8090 POSTING_READ(CURCNTR(pipe));
8091 intel_crtc->cursor_cntl = cntl;
8092 }
8093
8094 /* and commit changes on next vblank */
8095 I915_WRITE(CURBASE(pipe), base);
8096 POSTING_READ(CURBASE(pipe));
8097 }
8098
8099 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8100 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8101 bool on)
8102 {
8103 struct drm_device *dev = crtc->dev;
8104 struct drm_i915_private *dev_priv = dev->dev_private;
8105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8106 int pipe = intel_crtc->pipe;
8107 int x = crtc->cursor_x;
8108 int y = crtc->cursor_y;
8109 u32 base = 0, pos = 0;
8110
8111 if (on)
8112 base = intel_crtc->cursor_addr;
8113
8114 if (x >= intel_crtc->config.pipe_src_w)
8115 base = 0;
8116
8117 if (y >= intel_crtc->config.pipe_src_h)
8118 base = 0;
8119
8120 if (x < 0) {
8121 if (x + intel_crtc->cursor_width <= 0)
8122 base = 0;
8123
8124 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8125 x = -x;
8126 }
8127 pos |= x << CURSOR_X_SHIFT;
8128
8129 if (y < 0) {
8130 if (y + intel_crtc->cursor_height <= 0)
8131 base = 0;
8132
8133 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8134 y = -y;
8135 }
8136 pos |= y << CURSOR_Y_SHIFT;
8137
8138 if (base == 0 && intel_crtc->cursor_base == 0)
8139 return;
8140
8141 I915_WRITE(CURPOS(pipe), pos);
8142
8143 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8144 ivb_update_cursor(crtc, base);
8145 else if (IS_845G(dev) || IS_I865G(dev))
8146 i845_update_cursor(crtc, base);
8147 else
8148 i9xx_update_cursor(crtc, base);
8149 intel_crtc->cursor_base = base;
8150 }
8151
8152 /*
8153 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8154 *
8155 * Note that the object's reference will be consumed if the update fails. If
8156 * the update succeeds, the reference of the old object (if any) will be
8157 * consumed.
8158 */
8159 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8160 struct drm_i915_gem_object *obj,
8161 uint32_t width, uint32_t height)
8162 {
8163 struct drm_device *dev = crtc->dev;
8164 struct drm_i915_private *dev_priv = dev->dev_private;
8165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8166 enum pipe pipe = intel_crtc->pipe;
8167 unsigned old_width;
8168 uint32_t addr;
8169 int ret;
8170
8171 /* if we want to turn off the cursor ignore width and height */
8172 if (!obj) {
8173 DRM_DEBUG_KMS("cursor off\n");
8174 addr = 0;
8175 obj = NULL;
8176 mutex_lock(&dev->struct_mutex);
8177 goto finish;
8178 }
8179
8180 /* Check for which cursor types we support */
8181 if (!((width == 64 && height == 64) ||
8182 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8183 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8184 DRM_DEBUG("Cursor dimension not supported\n");
8185 return -EINVAL;
8186 }
8187
8188 if (obj->base.size < width * height * 4) {
8189 DRM_DEBUG_KMS("buffer is too small\n");
8190 ret = -ENOMEM;
8191 goto fail;
8192 }
8193
8194 /* we only need to pin inside GTT if cursor is non-phy */
8195 mutex_lock(&dev->struct_mutex);
8196 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8197 unsigned alignment;
8198
8199 if (obj->tiling_mode) {
8200 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8201 ret = -EINVAL;
8202 goto fail_locked;
8203 }
8204
8205 /* Note that the w/a also requires 2 PTE of padding following
8206 * the bo. We currently fill all unused PTE with the shadow
8207 * page and so we should always have valid PTE following the
8208 * cursor preventing the VT-d warning.
8209 */
8210 alignment = 0;
8211 if (need_vtd_wa(dev))
8212 alignment = 64*1024;
8213
8214 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8215 if (ret) {
8216 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8217 goto fail_locked;
8218 }
8219
8220 ret = i915_gem_object_put_fence(obj);
8221 if (ret) {
8222 DRM_DEBUG_KMS("failed to release fence for cursor");
8223 goto fail_unpin;
8224 }
8225
8226 addr = i915_gem_obj_ggtt_offset(obj);
8227 } else {
8228 int align = IS_I830(dev) ? 16 * 1024 : 256;
8229 ret = i915_gem_object_attach_phys(obj, align);
8230 if (ret) {
8231 DRM_DEBUG_KMS("failed to attach phys object\n");
8232 goto fail_locked;
8233 }
8234 addr = obj->phys_handle->busaddr;
8235 }
8236
8237 if (IS_GEN2(dev))
8238 I915_WRITE(CURSIZE, (height << 12) | width);
8239
8240 finish:
8241 if (intel_crtc->cursor_bo) {
8242 if (!INTEL_INFO(dev)->cursor_needs_physical)
8243 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8244 }
8245
8246 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8247 INTEL_FRONTBUFFER_CURSOR(pipe));
8248 mutex_unlock(&dev->struct_mutex);
8249
8250 old_width = intel_crtc->cursor_width;
8251
8252 intel_crtc->cursor_addr = addr;
8253 intel_crtc->cursor_bo = obj;
8254 intel_crtc->cursor_width = width;
8255 intel_crtc->cursor_height = height;
8256
8257 if (intel_crtc->active) {
8258 if (old_width != width)
8259 intel_update_watermarks(crtc);
8260 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8261 }
8262
8263 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8264
8265 return 0;
8266 fail_unpin:
8267 i915_gem_object_unpin_from_display_plane(obj);
8268 fail_locked:
8269 mutex_unlock(&dev->struct_mutex);
8270 fail:
8271 drm_gem_object_unreference_unlocked(&obj->base);
8272 return ret;
8273 }
8274
8275 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8276 u16 *blue, uint32_t start, uint32_t size)
8277 {
8278 int end = (start + size > 256) ? 256 : start + size, i;
8279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8280
8281 for (i = start; i < end; i++) {
8282 intel_crtc->lut_r[i] = red[i] >> 8;
8283 intel_crtc->lut_g[i] = green[i] >> 8;
8284 intel_crtc->lut_b[i] = blue[i] >> 8;
8285 }
8286
8287 intel_crtc_load_lut(crtc);
8288 }
8289
8290 /* VESA 640x480x72Hz mode to set on the pipe */
8291 static struct drm_display_mode load_detect_mode = {
8292 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8293 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8294 };
8295
8296 struct drm_framebuffer *
8297 __intel_framebuffer_create(struct drm_device *dev,
8298 struct drm_mode_fb_cmd2 *mode_cmd,
8299 struct drm_i915_gem_object *obj)
8300 {
8301 struct intel_framebuffer *intel_fb;
8302 int ret;
8303
8304 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8305 if (!intel_fb) {
8306 drm_gem_object_unreference_unlocked(&obj->base);
8307 return ERR_PTR(-ENOMEM);
8308 }
8309
8310 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8311 if (ret)
8312 goto err;
8313
8314 return &intel_fb->base;
8315 err:
8316 drm_gem_object_unreference_unlocked(&obj->base);
8317 kfree(intel_fb);
8318
8319 return ERR_PTR(ret);
8320 }
8321
8322 static struct drm_framebuffer *
8323 intel_framebuffer_create(struct drm_device *dev,
8324 struct drm_mode_fb_cmd2 *mode_cmd,
8325 struct drm_i915_gem_object *obj)
8326 {
8327 struct drm_framebuffer *fb;
8328 int ret;
8329
8330 ret = i915_mutex_lock_interruptible(dev);
8331 if (ret)
8332 return ERR_PTR(ret);
8333 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8334 mutex_unlock(&dev->struct_mutex);
8335
8336 return fb;
8337 }
8338
8339 static u32
8340 intel_framebuffer_pitch_for_width(int width, int bpp)
8341 {
8342 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8343 return ALIGN(pitch, 64);
8344 }
8345
8346 static u32
8347 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8348 {
8349 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8350 return PAGE_ALIGN(pitch * mode->vdisplay);
8351 }
8352
8353 static struct drm_framebuffer *
8354 intel_framebuffer_create_for_mode(struct drm_device *dev,
8355 struct drm_display_mode *mode,
8356 int depth, int bpp)
8357 {
8358 struct drm_i915_gem_object *obj;
8359 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8360
8361 obj = i915_gem_alloc_object(dev,
8362 intel_framebuffer_size_for_mode(mode, bpp));
8363 if (obj == NULL)
8364 return ERR_PTR(-ENOMEM);
8365
8366 mode_cmd.width = mode->hdisplay;
8367 mode_cmd.height = mode->vdisplay;
8368 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8369 bpp);
8370 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8371
8372 return intel_framebuffer_create(dev, &mode_cmd, obj);
8373 }
8374
8375 static struct drm_framebuffer *
8376 mode_fits_in_fbdev(struct drm_device *dev,
8377 struct drm_display_mode *mode)
8378 {
8379 #ifdef CONFIG_DRM_I915_FBDEV
8380 struct drm_i915_private *dev_priv = dev->dev_private;
8381 struct drm_i915_gem_object *obj;
8382 struct drm_framebuffer *fb;
8383
8384 if (!dev_priv->fbdev)
8385 return NULL;
8386
8387 if (!dev_priv->fbdev->fb)
8388 return NULL;
8389
8390 obj = dev_priv->fbdev->fb->obj;
8391 BUG_ON(!obj);
8392
8393 fb = &dev_priv->fbdev->fb->base;
8394 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8395 fb->bits_per_pixel))
8396 return NULL;
8397
8398 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8399 return NULL;
8400
8401 return fb;
8402 #else
8403 return NULL;
8404 #endif
8405 }
8406
8407 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8408 struct drm_display_mode *mode,
8409 struct intel_load_detect_pipe *old,
8410 struct drm_modeset_acquire_ctx *ctx)
8411 {
8412 struct intel_crtc *intel_crtc;
8413 struct intel_encoder *intel_encoder =
8414 intel_attached_encoder(connector);
8415 struct drm_crtc *possible_crtc;
8416 struct drm_encoder *encoder = &intel_encoder->base;
8417 struct drm_crtc *crtc = NULL;
8418 struct drm_device *dev = encoder->dev;
8419 struct drm_framebuffer *fb;
8420 struct drm_mode_config *config = &dev->mode_config;
8421 int ret, i = -1;
8422
8423 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8424 connector->base.id, connector->name,
8425 encoder->base.id, encoder->name);
8426
8427 drm_modeset_acquire_init(ctx, 0);
8428
8429 retry:
8430 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8431 if (ret)
8432 goto fail_unlock;
8433
8434 /*
8435 * Algorithm gets a little messy:
8436 *
8437 * - if the connector already has an assigned crtc, use it (but make
8438 * sure it's on first)
8439 *
8440 * - try to find the first unused crtc that can drive this connector,
8441 * and use that if we find one
8442 */
8443
8444 /* See if we already have a CRTC for this connector */
8445 if (encoder->crtc) {
8446 crtc = encoder->crtc;
8447
8448 ret = drm_modeset_lock(&crtc->mutex, ctx);
8449 if (ret)
8450 goto fail_unlock;
8451
8452 old->dpms_mode = connector->dpms;
8453 old->load_detect_temp = false;
8454
8455 /* Make sure the crtc and connector are running */
8456 if (connector->dpms != DRM_MODE_DPMS_ON)
8457 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8458
8459 return true;
8460 }
8461
8462 /* Find an unused one (if possible) */
8463 for_each_crtc(dev, possible_crtc) {
8464 i++;
8465 if (!(encoder->possible_crtcs & (1 << i)))
8466 continue;
8467 if (!possible_crtc->enabled) {
8468 crtc = possible_crtc;
8469 break;
8470 }
8471 }
8472
8473 /*
8474 * If we didn't find an unused CRTC, don't use any.
8475 */
8476 if (!crtc) {
8477 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8478 goto fail_unlock;
8479 }
8480
8481 ret = drm_modeset_lock(&crtc->mutex, ctx);
8482 if (ret)
8483 goto fail_unlock;
8484 intel_encoder->new_crtc = to_intel_crtc(crtc);
8485 to_intel_connector(connector)->new_encoder = intel_encoder;
8486
8487 intel_crtc = to_intel_crtc(crtc);
8488 intel_crtc->new_enabled = true;
8489 intel_crtc->new_config = &intel_crtc->config;
8490 old->dpms_mode = connector->dpms;
8491 old->load_detect_temp = true;
8492 old->release_fb = NULL;
8493
8494 if (!mode)
8495 mode = &load_detect_mode;
8496
8497 /* We need a framebuffer large enough to accommodate all accesses
8498 * that the plane may generate whilst we perform load detection.
8499 * We can not rely on the fbcon either being present (we get called
8500 * during its initialisation to detect all boot displays, or it may
8501 * not even exist) or that it is large enough to satisfy the
8502 * requested mode.
8503 */
8504 fb = mode_fits_in_fbdev(dev, mode);
8505 if (fb == NULL) {
8506 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8507 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8508 old->release_fb = fb;
8509 } else
8510 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8511 if (IS_ERR(fb)) {
8512 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8513 goto fail;
8514 }
8515
8516 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8517 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8518 if (old->release_fb)
8519 old->release_fb->funcs->destroy(old->release_fb);
8520 goto fail;
8521 }
8522
8523 /* let the connector get through one full cycle before testing */
8524 intel_wait_for_vblank(dev, intel_crtc->pipe);
8525 return true;
8526
8527 fail:
8528 intel_crtc->new_enabled = crtc->enabled;
8529 if (intel_crtc->new_enabled)
8530 intel_crtc->new_config = &intel_crtc->config;
8531 else
8532 intel_crtc->new_config = NULL;
8533 fail_unlock:
8534 if (ret == -EDEADLK) {
8535 drm_modeset_backoff(ctx);
8536 goto retry;
8537 }
8538
8539 drm_modeset_drop_locks(ctx);
8540 drm_modeset_acquire_fini(ctx);
8541
8542 return false;
8543 }
8544
8545 void intel_release_load_detect_pipe(struct drm_connector *connector,
8546 struct intel_load_detect_pipe *old,
8547 struct drm_modeset_acquire_ctx *ctx)
8548 {
8549 struct intel_encoder *intel_encoder =
8550 intel_attached_encoder(connector);
8551 struct drm_encoder *encoder = &intel_encoder->base;
8552 struct drm_crtc *crtc = encoder->crtc;
8553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8554
8555 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8556 connector->base.id, connector->name,
8557 encoder->base.id, encoder->name);
8558
8559 if (old->load_detect_temp) {
8560 to_intel_connector(connector)->new_encoder = NULL;
8561 intel_encoder->new_crtc = NULL;
8562 intel_crtc->new_enabled = false;
8563 intel_crtc->new_config = NULL;
8564 intel_set_mode(crtc, NULL, 0, 0, NULL);
8565
8566 if (old->release_fb) {
8567 drm_framebuffer_unregister_private(old->release_fb);
8568 drm_framebuffer_unreference(old->release_fb);
8569 }
8570
8571 goto unlock;
8572 return;
8573 }
8574
8575 /* Switch crtc and encoder back off if necessary */
8576 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8577 connector->funcs->dpms(connector, old->dpms_mode);
8578
8579 unlock:
8580 drm_modeset_drop_locks(ctx);
8581 drm_modeset_acquire_fini(ctx);
8582 }
8583
8584 static int i9xx_pll_refclk(struct drm_device *dev,
8585 const struct intel_crtc_config *pipe_config)
8586 {
8587 struct drm_i915_private *dev_priv = dev->dev_private;
8588 u32 dpll = pipe_config->dpll_hw_state.dpll;
8589
8590 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8591 return dev_priv->vbt.lvds_ssc_freq;
8592 else if (HAS_PCH_SPLIT(dev))
8593 return 120000;
8594 else if (!IS_GEN2(dev))
8595 return 96000;
8596 else
8597 return 48000;
8598 }
8599
8600 /* Returns the clock of the currently programmed mode of the given pipe. */
8601 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8602 struct intel_crtc_config *pipe_config)
8603 {
8604 struct drm_device *dev = crtc->base.dev;
8605 struct drm_i915_private *dev_priv = dev->dev_private;
8606 int pipe = pipe_config->cpu_transcoder;
8607 u32 dpll = pipe_config->dpll_hw_state.dpll;
8608 u32 fp;
8609 intel_clock_t clock;
8610 int refclk = i9xx_pll_refclk(dev, pipe_config);
8611
8612 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8613 fp = pipe_config->dpll_hw_state.fp0;
8614 else
8615 fp = pipe_config->dpll_hw_state.fp1;
8616
8617 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8618 if (IS_PINEVIEW(dev)) {
8619 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8620 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8621 } else {
8622 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8623 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8624 }
8625
8626 if (!IS_GEN2(dev)) {
8627 if (IS_PINEVIEW(dev))
8628 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8629 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8630 else
8631 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8632 DPLL_FPA01_P1_POST_DIV_SHIFT);
8633
8634 switch (dpll & DPLL_MODE_MASK) {
8635 case DPLLB_MODE_DAC_SERIAL:
8636 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8637 5 : 10;
8638 break;
8639 case DPLLB_MODE_LVDS:
8640 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8641 7 : 14;
8642 break;
8643 default:
8644 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8645 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8646 return;
8647 }
8648
8649 if (IS_PINEVIEW(dev))
8650 pineview_clock(refclk, &clock);
8651 else
8652 i9xx_clock(refclk, &clock);
8653 } else {
8654 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8655 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8656
8657 if (is_lvds) {
8658 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8659 DPLL_FPA01_P1_POST_DIV_SHIFT);
8660
8661 if (lvds & LVDS_CLKB_POWER_UP)
8662 clock.p2 = 7;
8663 else
8664 clock.p2 = 14;
8665 } else {
8666 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8667 clock.p1 = 2;
8668 else {
8669 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8670 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8671 }
8672 if (dpll & PLL_P2_DIVIDE_BY_4)
8673 clock.p2 = 4;
8674 else
8675 clock.p2 = 2;
8676 }
8677
8678 i9xx_clock(refclk, &clock);
8679 }
8680
8681 /*
8682 * This value includes pixel_multiplier. We will use
8683 * port_clock to compute adjusted_mode.crtc_clock in the
8684 * encoder's get_config() function.
8685 */
8686 pipe_config->port_clock = clock.dot;
8687 }
8688
8689 int intel_dotclock_calculate(int link_freq,
8690 const struct intel_link_m_n *m_n)
8691 {
8692 /*
8693 * The calculation for the data clock is:
8694 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8695 * But we want to avoid losing precison if possible, so:
8696 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8697 *
8698 * and the link clock is simpler:
8699 * link_clock = (m * link_clock) / n
8700 */
8701
8702 if (!m_n->link_n)
8703 return 0;
8704
8705 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8706 }
8707
8708 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8709 struct intel_crtc_config *pipe_config)
8710 {
8711 struct drm_device *dev = crtc->base.dev;
8712
8713 /* read out port_clock from the DPLL */
8714 i9xx_crtc_clock_get(crtc, pipe_config);
8715
8716 /*
8717 * This value does not include pixel_multiplier.
8718 * We will check that port_clock and adjusted_mode.crtc_clock
8719 * agree once we know their relationship in the encoder's
8720 * get_config() function.
8721 */
8722 pipe_config->adjusted_mode.crtc_clock =
8723 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8724 &pipe_config->fdi_m_n);
8725 }
8726
8727 /** Returns the currently programmed mode of the given pipe. */
8728 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8729 struct drm_crtc *crtc)
8730 {
8731 struct drm_i915_private *dev_priv = dev->dev_private;
8732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8733 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8734 struct drm_display_mode *mode;
8735 struct intel_crtc_config pipe_config;
8736 int htot = I915_READ(HTOTAL(cpu_transcoder));
8737 int hsync = I915_READ(HSYNC(cpu_transcoder));
8738 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8739 int vsync = I915_READ(VSYNC(cpu_transcoder));
8740 enum pipe pipe = intel_crtc->pipe;
8741
8742 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8743 if (!mode)
8744 return NULL;
8745
8746 /*
8747 * Construct a pipe_config sufficient for getting the clock info
8748 * back out of crtc_clock_get.
8749 *
8750 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8751 * to use a real value here instead.
8752 */
8753 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8754 pipe_config.pixel_multiplier = 1;
8755 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8756 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8757 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8758 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8759
8760 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8761 mode->hdisplay = (htot & 0xffff) + 1;
8762 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8763 mode->hsync_start = (hsync & 0xffff) + 1;
8764 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8765 mode->vdisplay = (vtot & 0xffff) + 1;
8766 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8767 mode->vsync_start = (vsync & 0xffff) + 1;
8768 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8769
8770 drm_mode_set_name(mode);
8771
8772 return mode;
8773 }
8774
8775 static void intel_increase_pllclock(struct drm_device *dev,
8776 enum pipe pipe)
8777 {
8778 struct drm_i915_private *dev_priv = dev->dev_private;
8779 int dpll_reg = DPLL(pipe);
8780 int dpll;
8781
8782 if (HAS_PCH_SPLIT(dev))
8783 return;
8784
8785 if (!dev_priv->lvds_downclock_avail)
8786 return;
8787
8788 dpll = I915_READ(dpll_reg);
8789 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8790 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8791
8792 assert_panel_unlocked(dev_priv, pipe);
8793
8794 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8795 I915_WRITE(dpll_reg, dpll);
8796 intel_wait_for_vblank(dev, pipe);
8797
8798 dpll = I915_READ(dpll_reg);
8799 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8800 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8801 }
8802 }
8803
8804 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8805 {
8806 struct drm_device *dev = crtc->dev;
8807 struct drm_i915_private *dev_priv = dev->dev_private;
8808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8809
8810 if (HAS_PCH_SPLIT(dev))
8811 return;
8812
8813 if (!dev_priv->lvds_downclock_avail)
8814 return;
8815
8816 /*
8817 * Since this is called by a timer, we should never get here in
8818 * the manual case.
8819 */
8820 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8821 int pipe = intel_crtc->pipe;
8822 int dpll_reg = DPLL(pipe);
8823 int dpll;
8824
8825 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8826
8827 assert_panel_unlocked(dev_priv, pipe);
8828
8829 dpll = I915_READ(dpll_reg);
8830 dpll |= DISPLAY_RATE_SELECT_FPA1;
8831 I915_WRITE(dpll_reg, dpll);
8832 intel_wait_for_vblank(dev, pipe);
8833 dpll = I915_READ(dpll_reg);
8834 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8835 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8836 }
8837
8838 }
8839
8840 void intel_mark_busy(struct drm_device *dev)
8841 {
8842 struct drm_i915_private *dev_priv = dev->dev_private;
8843
8844 if (dev_priv->mm.busy)
8845 return;
8846
8847 intel_runtime_pm_get(dev_priv);
8848 i915_update_gfx_val(dev_priv);
8849 dev_priv->mm.busy = true;
8850 }
8851
8852 void intel_mark_idle(struct drm_device *dev)
8853 {
8854 struct drm_i915_private *dev_priv = dev->dev_private;
8855 struct drm_crtc *crtc;
8856
8857 if (!dev_priv->mm.busy)
8858 return;
8859
8860 dev_priv->mm.busy = false;
8861
8862 if (!i915.powersave)
8863 goto out;
8864
8865 for_each_crtc(dev, crtc) {
8866 if (!crtc->primary->fb)
8867 continue;
8868
8869 intel_decrease_pllclock(crtc);
8870 }
8871
8872 if (INTEL_INFO(dev)->gen >= 6)
8873 gen6_rps_idle(dev->dev_private);
8874
8875 out:
8876 intel_runtime_pm_put(dev_priv);
8877 }
8878
8879
8880 /**
8881 * intel_mark_fb_busy - mark given planes as busy
8882 * @dev: DRM device
8883 * @frontbuffer_bits: bits for the affected planes
8884 * @ring: optional ring for asynchronous commands
8885 *
8886 * This function gets called every time the screen contents change. It can be
8887 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
8888 */
8889 static void intel_mark_fb_busy(struct drm_device *dev,
8890 unsigned frontbuffer_bits,
8891 struct intel_engine_cs *ring)
8892 {
8893 enum pipe pipe;
8894
8895 if (!i915.powersave)
8896 return;
8897
8898 for_each_pipe(pipe) {
8899 if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)))
8900 continue;
8901
8902 intel_increase_pllclock(dev, pipe);
8903 if (ring && intel_fbc_enabled(dev))
8904 ring->fbc_dirty = true;
8905 }
8906 }
8907
8908 /**
8909 * intel_fb_obj_invalidate - invalidate frontbuffer object
8910 * @obj: GEM object to invalidate
8911 * @ring: set for asynchronous rendering
8912 *
8913 * This function gets called every time rendering on the given object starts and
8914 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
8915 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
8916 * until the rendering completes or a flip on this frontbuffer plane is
8917 * scheduled.
8918 */
8919 void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
8920 struct intel_engine_cs *ring)
8921 {
8922 struct drm_device *dev = obj->base.dev;
8923 struct drm_i915_private *dev_priv = dev->dev_private;
8924
8925 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8926
8927 if (!obj->frontbuffer_bits)
8928 return;
8929
8930 if (ring) {
8931 mutex_lock(&dev_priv->fb_tracking.lock);
8932 dev_priv->fb_tracking.busy_bits
8933 |= obj->frontbuffer_bits;
8934 dev_priv->fb_tracking.flip_bits
8935 &= ~obj->frontbuffer_bits;
8936 mutex_unlock(&dev_priv->fb_tracking.lock);
8937 }
8938
8939 intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
8940
8941 intel_edp_psr_exit(dev);
8942 }
8943
8944 /**
8945 * intel_frontbuffer_flush - flush frontbuffer
8946 * @dev: DRM device
8947 * @frontbuffer_bits: frontbuffer plane tracking bits
8948 *
8949 * This function gets called every time rendering on the given planes has
8950 * completed and frontbuffer caching can be started again. Flushes will get
8951 * delayed if they're blocked by some oustanding asynchronous rendering.
8952 *
8953 * Can be called without any locks held.
8954 */
8955 void intel_frontbuffer_flush(struct drm_device *dev,
8956 unsigned frontbuffer_bits)
8957 {
8958 struct drm_i915_private *dev_priv = dev->dev_private;
8959
8960 /* Delay flushing when rings are still busy.*/
8961 mutex_lock(&dev_priv->fb_tracking.lock);
8962 frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits;
8963 mutex_unlock(&dev_priv->fb_tracking.lock);
8964
8965 intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
8966
8967 intel_edp_psr_exit(dev);
8968 }
8969
8970 /**
8971 * intel_fb_obj_flush - flush frontbuffer object
8972 * @obj: GEM object to flush
8973 * @retire: set when retiring asynchronous rendering
8974 *
8975 * This function gets called every time rendering on the given object has
8976 * completed and frontbuffer caching can be started again. If @retire is true
8977 * then any delayed flushes will be unblocked.
8978 */
8979 void intel_fb_obj_flush(struct drm_i915_gem_object *obj,
8980 bool retire)
8981 {
8982 struct drm_device *dev = obj->base.dev;
8983 struct drm_i915_private *dev_priv = dev->dev_private;
8984 unsigned frontbuffer_bits;
8985
8986 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
8987
8988 if (!obj->frontbuffer_bits)
8989 return;
8990
8991 frontbuffer_bits = obj->frontbuffer_bits;
8992
8993 if (retire) {
8994 mutex_lock(&dev_priv->fb_tracking.lock);
8995 /* Filter out new bits since rendering started. */
8996 frontbuffer_bits &= dev_priv->fb_tracking.busy_bits;
8997
8998 dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits;
8999 mutex_unlock(&dev_priv->fb_tracking.lock);
9000 }
9001
9002 intel_frontbuffer_flush(dev, frontbuffer_bits);
9003 }
9004
9005 /**
9006 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9007 * @dev: DRM device
9008 * @frontbuffer_bits: frontbuffer plane tracking bits
9009 *
9010 * This function gets called after scheduling a flip on @obj. The actual
9011 * frontbuffer flushing will be delayed until completion is signalled with
9012 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9013 * flush will be cancelled.
9014 *
9015 * Can be called without any locks held.
9016 */
9017 void intel_frontbuffer_flip_prepare(struct drm_device *dev,
9018 unsigned frontbuffer_bits)
9019 {
9020 struct drm_i915_private *dev_priv = dev->dev_private;
9021
9022 mutex_lock(&dev_priv->fb_tracking.lock);
9023 dev_priv->fb_tracking.flip_bits
9024 |= frontbuffer_bits;
9025 mutex_unlock(&dev_priv->fb_tracking.lock);
9026 }
9027
9028 /**
9029 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9030 * @dev: DRM device
9031 * @frontbuffer_bits: frontbuffer plane tracking bits
9032 *
9033 * This function gets called after the flip has been latched and will complete
9034 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9035 *
9036 * Can be called without any locks held.
9037 */
9038 void intel_frontbuffer_flip_complete(struct drm_device *dev,
9039 unsigned frontbuffer_bits)
9040 {
9041 struct drm_i915_private *dev_priv = dev->dev_private;
9042
9043 mutex_lock(&dev_priv->fb_tracking.lock);
9044 /* Mask any cancelled flips. */
9045 frontbuffer_bits &= dev_priv->fb_tracking.flip_bits;
9046 dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits;
9047 mutex_unlock(&dev_priv->fb_tracking.lock);
9048
9049 intel_frontbuffer_flush(dev, frontbuffer_bits);
9050 }
9051
9052 static void intel_crtc_destroy(struct drm_crtc *crtc)
9053 {
9054 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9055 struct drm_device *dev = crtc->dev;
9056 struct intel_unpin_work *work;
9057 unsigned long flags;
9058
9059 spin_lock_irqsave(&dev->event_lock, flags);
9060 work = intel_crtc->unpin_work;
9061 intel_crtc->unpin_work = NULL;
9062 spin_unlock_irqrestore(&dev->event_lock, flags);
9063
9064 if (work) {
9065 cancel_work_sync(&work->work);
9066 kfree(work);
9067 }
9068
9069 drm_crtc_cleanup(crtc);
9070
9071 kfree(intel_crtc);
9072 }
9073
9074 static void intel_unpin_work_fn(struct work_struct *__work)
9075 {
9076 struct intel_unpin_work *work =
9077 container_of(__work, struct intel_unpin_work, work);
9078 struct drm_device *dev = work->crtc->dev;
9079 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9080
9081 mutex_lock(&dev->struct_mutex);
9082 intel_unpin_fb_obj(work->old_fb_obj);
9083 drm_gem_object_unreference(&work->pending_flip_obj->base);
9084 drm_gem_object_unreference(&work->old_fb_obj->base);
9085
9086 intel_update_fbc(dev);
9087 mutex_unlock(&dev->struct_mutex);
9088
9089 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9090
9091 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9092 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9093
9094 kfree(work);
9095 }
9096
9097 static void do_intel_finish_page_flip(struct drm_device *dev,
9098 struct drm_crtc *crtc)
9099 {
9100 struct drm_i915_private *dev_priv = dev->dev_private;
9101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9102 struct intel_unpin_work *work;
9103 unsigned long flags;
9104
9105 /* Ignore early vblank irqs */
9106 if (intel_crtc == NULL)
9107 return;
9108
9109 spin_lock_irqsave(&dev->event_lock, flags);
9110 work = intel_crtc->unpin_work;
9111
9112 /* Ensure we don't miss a work->pending update ... */
9113 smp_rmb();
9114
9115 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9116 spin_unlock_irqrestore(&dev->event_lock, flags);
9117 return;
9118 }
9119
9120 /* and that the unpin work is consistent wrt ->pending. */
9121 smp_rmb();
9122
9123 intel_crtc->unpin_work = NULL;
9124
9125 if (work->event)
9126 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
9127
9128 drm_crtc_vblank_put(crtc);
9129
9130 spin_unlock_irqrestore(&dev->event_lock, flags);
9131
9132 wake_up_all(&dev_priv->pending_flip_queue);
9133
9134 queue_work(dev_priv->wq, &work->work);
9135
9136 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
9137 }
9138
9139 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9140 {
9141 struct drm_i915_private *dev_priv = dev->dev_private;
9142 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9143
9144 do_intel_finish_page_flip(dev, crtc);
9145 }
9146
9147 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9148 {
9149 struct drm_i915_private *dev_priv = dev->dev_private;
9150 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9151
9152 do_intel_finish_page_flip(dev, crtc);
9153 }
9154
9155 /* Is 'a' after or equal to 'b'? */
9156 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9157 {
9158 return !((a - b) & 0x80000000);
9159 }
9160
9161 static bool page_flip_finished(struct intel_crtc *crtc)
9162 {
9163 struct drm_device *dev = crtc->base.dev;
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165
9166 /*
9167 * The relevant registers doen't exist on pre-ctg.
9168 * As the flip done interrupt doesn't trigger for mmio
9169 * flips on gmch platforms, a flip count check isn't
9170 * really needed there. But since ctg has the registers,
9171 * include it in the check anyway.
9172 */
9173 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9174 return true;
9175
9176 /*
9177 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9178 * used the same base address. In that case the mmio flip might
9179 * have completed, but the CS hasn't even executed the flip yet.
9180 *
9181 * A flip count check isn't enough as the CS might have updated
9182 * the base address just after start of vblank, but before we
9183 * managed to process the interrupt. This means we'd complete the
9184 * CS flip too soon.
9185 *
9186 * Combining both checks should get us a good enough result. It may
9187 * still happen that the CS flip has been executed, but has not
9188 * yet actually completed. But in case the base address is the same
9189 * anyway, we don't really care.
9190 */
9191 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9192 crtc->unpin_work->gtt_offset &&
9193 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9194 crtc->unpin_work->flip_count);
9195 }
9196
9197 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9198 {
9199 struct drm_i915_private *dev_priv = dev->dev_private;
9200 struct intel_crtc *intel_crtc =
9201 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9202 unsigned long flags;
9203
9204 /* NB: An MMIO update of the plane base pointer will also
9205 * generate a page-flip completion irq, i.e. every modeset
9206 * is also accompanied by a spurious intel_prepare_page_flip().
9207 */
9208 spin_lock_irqsave(&dev->event_lock, flags);
9209 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9210 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9211 spin_unlock_irqrestore(&dev->event_lock, flags);
9212 }
9213
9214 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9215 {
9216 /* Ensure that the work item is consistent when activating it ... */
9217 smp_wmb();
9218 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9219 /* and that it is marked active as soon as the irq could fire. */
9220 smp_wmb();
9221 }
9222
9223 static int intel_gen2_queue_flip(struct drm_device *dev,
9224 struct drm_crtc *crtc,
9225 struct drm_framebuffer *fb,
9226 struct drm_i915_gem_object *obj,
9227 struct intel_engine_cs *ring,
9228 uint32_t flags)
9229 {
9230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9231 u32 flip_mask;
9232 int ret;
9233
9234 ret = intel_ring_begin(ring, 6);
9235 if (ret)
9236 return ret;
9237
9238 /* Can't queue multiple flips, so wait for the previous
9239 * one to finish before executing the next.
9240 */
9241 if (intel_crtc->plane)
9242 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9243 else
9244 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9245 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9246 intel_ring_emit(ring, MI_NOOP);
9247 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9248 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9249 intel_ring_emit(ring, fb->pitches[0]);
9250 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9251 intel_ring_emit(ring, 0); /* aux display base address, unused */
9252
9253 intel_mark_page_flip_active(intel_crtc);
9254 __intel_ring_advance(ring);
9255 return 0;
9256 }
9257
9258 static int intel_gen3_queue_flip(struct drm_device *dev,
9259 struct drm_crtc *crtc,
9260 struct drm_framebuffer *fb,
9261 struct drm_i915_gem_object *obj,
9262 struct intel_engine_cs *ring,
9263 uint32_t flags)
9264 {
9265 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9266 u32 flip_mask;
9267 int ret;
9268
9269 ret = intel_ring_begin(ring, 6);
9270 if (ret)
9271 return ret;
9272
9273 if (intel_crtc->plane)
9274 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9275 else
9276 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9277 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9278 intel_ring_emit(ring, MI_NOOP);
9279 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9280 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9281 intel_ring_emit(ring, fb->pitches[0]);
9282 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9283 intel_ring_emit(ring, MI_NOOP);
9284
9285 intel_mark_page_flip_active(intel_crtc);
9286 __intel_ring_advance(ring);
9287 return 0;
9288 }
9289
9290 static int intel_gen4_queue_flip(struct drm_device *dev,
9291 struct drm_crtc *crtc,
9292 struct drm_framebuffer *fb,
9293 struct drm_i915_gem_object *obj,
9294 struct intel_engine_cs *ring,
9295 uint32_t flags)
9296 {
9297 struct drm_i915_private *dev_priv = dev->dev_private;
9298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9299 uint32_t pf, pipesrc;
9300 int ret;
9301
9302 ret = intel_ring_begin(ring, 4);
9303 if (ret)
9304 return ret;
9305
9306 /* i965+ uses the linear or tiled offsets from the
9307 * Display Registers (which do not change across a page-flip)
9308 * so we need only reprogram the base address.
9309 */
9310 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9311 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9312 intel_ring_emit(ring, fb->pitches[0]);
9313 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9314 obj->tiling_mode);
9315
9316 /* XXX Enabling the panel-fitter across page-flip is so far
9317 * untested on non-native modes, so ignore it for now.
9318 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9319 */
9320 pf = 0;
9321 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9322 intel_ring_emit(ring, pf | pipesrc);
9323
9324 intel_mark_page_flip_active(intel_crtc);
9325 __intel_ring_advance(ring);
9326 return 0;
9327 }
9328
9329 static int intel_gen6_queue_flip(struct drm_device *dev,
9330 struct drm_crtc *crtc,
9331 struct drm_framebuffer *fb,
9332 struct drm_i915_gem_object *obj,
9333 struct intel_engine_cs *ring,
9334 uint32_t flags)
9335 {
9336 struct drm_i915_private *dev_priv = dev->dev_private;
9337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9338 uint32_t pf, pipesrc;
9339 int ret;
9340
9341 ret = intel_ring_begin(ring, 4);
9342 if (ret)
9343 return ret;
9344
9345 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9346 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9347 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9348 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9349
9350 /* Contrary to the suggestions in the documentation,
9351 * "Enable Panel Fitter" does not seem to be required when page
9352 * flipping with a non-native mode, and worse causes a normal
9353 * modeset to fail.
9354 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9355 */
9356 pf = 0;
9357 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9358 intel_ring_emit(ring, pf | pipesrc);
9359
9360 intel_mark_page_flip_active(intel_crtc);
9361 __intel_ring_advance(ring);
9362 return 0;
9363 }
9364
9365 static int intel_gen7_queue_flip(struct drm_device *dev,
9366 struct drm_crtc *crtc,
9367 struct drm_framebuffer *fb,
9368 struct drm_i915_gem_object *obj,
9369 struct intel_engine_cs *ring,
9370 uint32_t flags)
9371 {
9372 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9373 uint32_t plane_bit = 0;
9374 int len, ret;
9375
9376 switch (intel_crtc->plane) {
9377 case PLANE_A:
9378 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9379 break;
9380 case PLANE_B:
9381 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9382 break;
9383 case PLANE_C:
9384 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9385 break;
9386 default:
9387 WARN_ONCE(1, "unknown plane in flip command\n");
9388 return -ENODEV;
9389 }
9390
9391 len = 4;
9392 if (ring->id == RCS) {
9393 len += 6;
9394 /*
9395 * On Gen 8, SRM is now taking an extra dword to accommodate
9396 * 48bits addresses, and we need a NOOP for the batch size to
9397 * stay even.
9398 */
9399 if (IS_GEN8(dev))
9400 len += 2;
9401 }
9402
9403 /*
9404 * BSpec MI_DISPLAY_FLIP for IVB:
9405 * "The full packet must be contained within the same cache line."
9406 *
9407 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9408 * cacheline, if we ever start emitting more commands before
9409 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9410 * then do the cacheline alignment, and finally emit the
9411 * MI_DISPLAY_FLIP.
9412 */
9413 ret = intel_ring_cacheline_align(ring);
9414 if (ret)
9415 return ret;
9416
9417 ret = intel_ring_begin(ring, len);
9418 if (ret)
9419 return ret;
9420
9421 /* Unmask the flip-done completion message. Note that the bspec says that
9422 * we should do this for both the BCS and RCS, and that we must not unmask
9423 * more than one flip event at any time (or ensure that one flip message
9424 * can be sent by waiting for flip-done prior to queueing new flips).
9425 * Experimentation says that BCS works despite DERRMR masking all
9426 * flip-done completion events and that unmasking all planes at once
9427 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9428 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9429 */
9430 if (ring->id == RCS) {
9431 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9432 intel_ring_emit(ring, DERRMR);
9433 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9434 DERRMR_PIPEB_PRI_FLIP_DONE |
9435 DERRMR_PIPEC_PRI_FLIP_DONE));
9436 if (IS_GEN8(dev))
9437 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9438 MI_SRM_LRM_GLOBAL_GTT);
9439 else
9440 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9441 MI_SRM_LRM_GLOBAL_GTT);
9442 intel_ring_emit(ring, DERRMR);
9443 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9444 if (IS_GEN8(dev)) {
9445 intel_ring_emit(ring, 0);
9446 intel_ring_emit(ring, MI_NOOP);
9447 }
9448 }
9449
9450 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9451 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9452 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9453 intel_ring_emit(ring, (MI_NOOP));
9454
9455 intel_mark_page_flip_active(intel_crtc);
9456 __intel_ring_advance(ring);
9457 return 0;
9458 }
9459
9460 static bool use_mmio_flip(struct intel_engine_cs *ring,
9461 struct drm_i915_gem_object *obj)
9462 {
9463 /*
9464 * This is not being used for older platforms, because
9465 * non-availability of flip done interrupt forces us to use
9466 * CS flips. Older platforms derive flip done using some clever
9467 * tricks involving the flip_pending status bits and vblank irqs.
9468 * So using MMIO flips there would disrupt this mechanism.
9469 */
9470
9471 if (ring == NULL)
9472 return true;
9473
9474 if (INTEL_INFO(ring->dev)->gen < 5)
9475 return false;
9476
9477 if (i915.use_mmio_flip < 0)
9478 return false;
9479 else if (i915.use_mmio_flip > 0)
9480 return true;
9481 else
9482 return ring != obj->ring;
9483 }
9484
9485 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9486 {
9487 struct drm_device *dev = intel_crtc->base.dev;
9488 struct drm_i915_private *dev_priv = dev->dev_private;
9489 struct intel_framebuffer *intel_fb =
9490 to_intel_framebuffer(intel_crtc->base.primary->fb);
9491 struct drm_i915_gem_object *obj = intel_fb->obj;
9492 u32 dspcntr;
9493 u32 reg;
9494
9495 intel_mark_page_flip_active(intel_crtc);
9496
9497 reg = DSPCNTR(intel_crtc->plane);
9498 dspcntr = I915_READ(reg);
9499
9500 if (INTEL_INFO(dev)->gen >= 4) {
9501 if (obj->tiling_mode != I915_TILING_NONE)
9502 dspcntr |= DISPPLANE_TILED;
9503 else
9504 dspcntr &= ~DISPPLANE_TILED;
9505 }
9506 I915_WRITE(reg, dspcntr);
9507
9508 I915_WRITE(DSPSURF(intel_crtc->plane),
9509 intel_crtc->unpin_work->gtt_offset);
9510 POSTING_READ(DSPSURF(intel_crtc->plane));
9511 }
9512
9513 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9514 {
9515 struct intel_engine_cs *ring;
9516 int ret;
9517
9518 lockdep_assert_held(&obj->base.dev->struct_mutex);
9519
9520 if (!obj->last_write_seqno)
9521 return 0;
9522
9523 ring = obj->ring;
9524
9525 if (i915_seqno_passed(ring->get_seqno(ring, true),
9526 obj->last_write_seqno))
9527 return 0;
9528
9529 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9530 if (ret)
9531 return ret;
9532
9533 if (WARN_ON(!ring->irq_get(ring)))
9534 return 0;
9535
9536 return 1;
9537 }
9538
9539 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9540 {
9541 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9542 struct intel_crtc *intel_crtc;
9543 unsigned long irq_flags;
9544 u32 seqno;
9545
9546 seqno = ring->get_seqno(ring, false);
9547
9548 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9549 for_each_intel_crtc(ring->dev, intel_crtc) {
9550 struct intel_mmio_flip *mmio_flip;
9551
9552 mmio_flip = &intel_crtc->mmio_flip;
9553 if (mmio_flip->seqno == 0)
9554 continue;
9555
9556 if (ring->id != mmio_flip->ring_id)
9557 continue;
9558
9559 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9560 intel_do_mmio_flip(intel_crtc);
9561 mmio_flip->seqno = 0;
9562 ring->irq_put(ring);
9563 }
9564 }
9565 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9566 }
9567
9568 static int intel_queue_mmio_flip(struct drm_device *dev,
9569 struct drm_crtc *crtc,
9570 struct drm_framebuffer *fb,
9571 struct drm_i915_gem_object *obj,
9572 struct intel_engine_cs *ring,
9573 uint32_t flags)
9574 {
9575 struct drm_i915_private *dev_priv = dev->dev_private;
9576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9577 unsigned long irq_flags;
9578 int ret;
9579
9580 if (WARN_ON(intel_crtc->mmio_flip.seqno))
9581 return -EBUSY;
9582
9583 ret = intel_postpone_flip(obj);
9584 if (ret < 0)
9585 return ret;
9586 if (ret == 0) {
9587 intel_do_mmio_flip(intel_crtc);
9588 return 0;
9589 }
9590
9591 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9592 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9593 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9594 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9595
9596 /*
9597 * Double check to catch cases where irq fired before
9598 * mmio flip data was ready
9599 */
9600 intel_notify_mmio_flip(obj->ring);
9601 return 0;
9602 }
9603
9604 static int intel_default_queue_flip(struct drm_device *dev,
9605 struct drm_crtc *crtc,
9606 struct drm_framebuffer *fb,
9607 struct drm_i915_gem_object *obj,
9608 struct intel_engine_cs *ring,
9609 uint32_t flags)
9610 {
9611 return -ENODEV;
9612 }
9613
9614 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9615 struct drm_framebuffer *fb,
9616 struct drm_pending_vblank_event *event,
9617 uint32_t page_flip_flags)
9618 {
9619 struct drm_device *dev = crtc->dev;
9620 struct drm_i915_private *dev_priv = dev->dev_private;
9621 struct drm_framebuffer *old_fb = crtc->primary->fb;
9622 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9624 enum pipe pipe = intel_crtc->pipe;
9625 struct intel_unpin_work *work;
9626 struct intel_engine_cs *ring;
9627 unsigned long flags;
9628 int ret;
9629
9630 /*
9631 * drm_mode_page_flip_ioctl() should already catch this, but double
9632 * check to be safe. In the future we may enable pageflipping from
9633 * a disabled primary plane.
9634 */
9635 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9636 return -EBUSY;
9637
9638 /* Can't change pixel format via MI display flips. */
9639 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9640 return -EINVAL;
9641
9642 /*
9643 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9644 * Note that pitch changes could also affect these register.
9645 */
9646 if (INTEL_INFO(dev)->gen > 3 &&
9647 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9648 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9649 return -EINVAL;
9650
9651 if (i915_terminally_wedged(&dev_priv->gpu_error))
9652 goto out_hang;
9653
9654 work = kzalloc(sizeof(*work), GFP_KERNEL);
9655 if (work == NULL)
9656 return -ENOMEM;
9657
9658 work->event = event;
9659 work->crtc = crtc;
9660 work->old_fb_obj = intel_fb_obj(old_fb);
9661 INIT_WORK(&work->work, intel_unpin_work_fn);
9662
9663 ret = drm_crtc_vblank_get(crtc);
9664 if (ret)
9665 goto free_work;
9666
9667 /* We borrow the event spin lock for protecting unpin_work */
9668 spin_lock_irqsave(&dev->event_lock, flags);
9669 if (intel_crtc->unpin_work) {
9670 spin_unlock_irqrestore(&dev->event_lock, flags);
9671 kfree(work);
9672 drm_crtc_vblank_put(crtc);
9673
9674 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9675 return -EBUSY;
9676 }
9677 intel_crtc->unpin_work = work;
9678 spin_unlock_irqrestore(&dev->event_lock, flags);
9679
9680 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9681 flush_workqueue(dev_priv->wq);
9682
9683 ret = i915_mutex_lock_interruptible(dev);
9684 if (ret)
9685 goto cleanup;
9686
9687 /* Reference the objects for the scheduled work. */
9688 drm_gem_object_reference(&work->old_fb_obj->base);
9689 drm_gem_object_reference(&obj->base);
9690
9691 crtc->primary->fb = fb;
9692
9693 work->pending_flip_obj = obj;
9694
9695 work->enable_stall_check = true;
9696
9697 atomic_inc(&intel_crtc->unpin_work_count);
9698 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9699
9700 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9701 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9702
9703 if (IS_VALLEYVIEW(dev)) {
9704 ring = &dev_priv->ring[BCS];
9705 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9706 /* vlv: DISPLAY_FLIP fails to change tiling */
9707 ring = NULL;
9708 } else if (IS_IVYBRIDGE(dev)) {
9709 ring = &dev_priv->ring[BCS];
9710 } else if (INTEL_INFO(dev)->gen >= 7) {
9711 ring = obj->ring;
9712 if (ring == NULL || ring->id != RCS)
9713 ring = &dev_priv->ring[BCS];
9714 } else {
9715 ring = &dev_priv->ring[RCS];
9716 }
9717
9718 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9719 if (ret)
9720 goto cleanup_pending;
9721
9722 work->gtt_offset =
9723 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9724
9725 if (use_mmio_flip(ring, obj))
9726 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9727 page_flip_flags);
9728 else
9729 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9730 page_flip_flags);
9731 if (ret)
9732 goto cleanup_unpin;
9733
9734 i915_gem_track_fb(work->old_fb_obj, obj,
9735 INTEL_FRONTBUFFER_PRIMARY(pipe));
9736
9737 intel_disable_fbc(dev);
9738 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9739 mutex_unlock(&dev->struct_mutex);
9740
9741 trace_i915_flip_request(intel_crtc->plane, obj);
9742
9743 return 0;
9744
9745 cleanup_unpin:
9746 intel_unpin_fb_obj(obj);
9747 cleanup_pending:
9748 atomic_dec(&intel_crtc->unpin_work_count);
9749 crtc->primary->fb = old_fb;
9750 drm_gem_object_unreference(&work->old_fb_obj->base);
9751 drm_gem_object_unreference(&obj->base);
9752 mutex_unlock(&dev->struct_mutex);
9753
9754 cleanup:
9755 spin_lock_irqsave(&dev->event_lock, flags);
9756 intel_crtc->unpin_work = NULL;
9757 spin_unlock_irqrestore(&dev->event_lock, flags);
9758
9759 drm_crtc_vblank_put(crtc);
9760 free_work:
9761 kfree(work);
9762
9763 if (ret == -EIO) {
9764 out_hang:
9765 intel_crtc_wait_for_pending_flips(crtc);
9766 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9767 if (ret == 0 && event)
9768 drm_send_vblank_event(dev, pipe, event);
9769 }
9770 return ret;
9771 }
9772
9773 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9774 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9775 .load_lut = intel_crtc_load_lut,
9776 };
9777
9778 /**
9779 * intel_modeset_update_staged_output_state
9780 *
9781 * Updates the staged output configuration state, e.g. after we've read out the
9782 * current hw state.
9783 */
9784 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9785 {
9786 struct intel_crtc *crtc;
9787 struct intel_encoder *encoder;
9788 struct intel_connector *connector;
9789
9790 list_for_each_entry(connector, &dev->mode_config.connector_list,
9791 base.head) {
9792 connector->new_encoder =
9793 to_intel_encoder(connector->base.encoder);
9794 }
9795
9796 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9797 base.head) {
9798 encoder->new_crtc =
9799 to_intel_crtc(encoder->base.crtc);
9800 }
9801
9802 for_each_intel_crtc(dev, crtc) {
9803 crtc->new_enabled = crtc->base.enabled;
9804
9805 if (crtc->new_enabled)
9806 crtc->new_config = &crtc->config;
9807 else
9808 crtc->new_config = NULL;
9809 }
9810 }
9811
9812 /**
9813 * intel_modeset_commit_output_state
9814 *
9815 * This function copies the stage display pipe configuration to the real one.
9816 */
9817 static void intel_modeset_commit_output_state(struct drm_device *dev)
9818 {
9819 struct intel_crtc *crtc;
9820 struct intel_encoder *encoder;
9821 struct intel_connector *connector;
9822
9823 list_for_each_entry(connector, &dev->mode_config.connector_list,
9824 base.head) {
9825 connector->base.encoder = &connector->new_encoder->base;
9826 }
9827
9828 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9829 base.head) {
9830 encoder->base.crtc = &encoder->new_crtc->base;
9831 }
9832
9833 for_each_intel_crtc(dev, crtc) {
9834 crtc->base.enabled = crtc->new_enabled;
9835 }
9836 }
9837
9838 static void
9839 connected_sink_compute_bpp(struct intel_connector *connector,
9840 struct intel_crtc_config *pipe_config)
9841 {
9842 int bpp = pipe_config->pipe_bpp;
9843
9844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9845 connector->base.base.id,
9846 connector->base.name);
9847
9848 /* Don't use an invalid EDID bpc value */
9849 if (connector->base.display_info.bpc &&
9850 connector->base.display_info.bpc * 3 < bpp) {
9851 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9852 bpp, connector->base.display_info.bpc*3);
9853 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9854 }
9855
9856 /* Clamp bpp to 8 on screens without EDID 1.4 */
9857 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9858 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9859 bpp);
9860 pipe_config->pipe_bpp = 24;
9861 }
9862 }
9863
9864 static int
9865 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9866 struct drm_framebuffer *fb,
9867 struct intel_crtc_config *pipe_config)
9868 {
9869 struct drm_device *dev = crtc->base.dev;
9870 struct intel_connector *connector;
9871 int bpp;
9872
9873 switch (fb->pixel_format) {
9874 case DRM_FORMAT_C8:
9875 bpp = 8*3; /* since we go through a colormap */
9876 break;
9877 case DRM_FORMAT_XRGB1555:
9878 case DRM_FORMAT_ARGB1555:
9879 /* checked in intel_framebuffer_init already */
9880 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9881 return -EINVAL;
9882 case DRM_FORMAT_RGB565:
9883 bpp = 6*3; /* min is 18bpp */
9884 break;
9885 case DRM_FORMAT_XBGR8888:
9886 case DRM_FORMAT_ABGR8888:
9887 /* checked in intel_framebuffer_init already */
9888 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9889 return -EINVAL;
9890 case DRM_FORMAT_XRGB8888:
9891 case DRM_FORMAT_ARGB8888:
9892 bpp = 8*3;
9893 break;
9894 case DRM_FORMAT_XRGB2101010:
9895 case DRM_FORMAT_ARGB2101010:
9896 case DRM_FORMAT_XBGR2101010:
9897 case DRM_FORMAT_ABGR2101010:
9898 /* checked in intel_framebuffer_init already */
9899 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9900 return -EINVAL;
9901 bpp = 10*3;
9902 break;
9903 /* TODO: gen4+ supports 16 bpc floating point, too. */
9904 default:
9905 DRM_DEBUG_KMS("unsupported depth\n");
9906 return -EINVAL;
9907 }
9908
9909 pipe_config->pipe_bpp = bpp;
9910
9911 /* Clamp display bpp to EDID value */
9912 list_for_each_entry(connector, &dev->mode_config.connector_list,
9913 base.head) {
9914 if (!connector->new_encoder ||
9915 connector->new_encoder->new_crtc != crtc)
9916 continue;
9917
9918 connected_sink_compute_bpp(connector, pipe_config);
9919 }
9920
9921 return bpp;
9922 }
9923
9924 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9925 {
9926 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9927 "type: 0x%x flags: 0x%x\n",
9928 mode->crtc_clock,
9929 mode->crtc_hdisplay, mode->crtc_hsync_start,
9930 mode->crtc_hsync_end, mode->crtc_htotal,
9931 mode->crtc_vdisplay, mode->crtc_vsync_start,
9932 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9933 }
9934
9935 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9936 struct intel_crtc_config *pipe_config,
9937 const char *context)
9938 {
9939 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9940 context, pipe_name(crtc->pipe));
9941
9942 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9943 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9944 pipe_config->pipe_bpp, pipe_config->dither);
9945 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9946 pipe_config->has_pch_encoder,
9947 pipe_config->fdi_lanes,
9948 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9949 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9950 pipe_config->fdi_m_n.tu);
9951 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9952 pipe_config->has_dp_encoder,
9953 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9954 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9955 pipe_config->dp_m_n.tu);
9956 DRM_DEBUG_KMS("requested mode:\n");
9957 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9958 DRM_DEBUG_KMS("adjusted mode:\n");
9959 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9960 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9961 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9962 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9963 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9964 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9965 pipe_config->gmch_pfit.control,
9966 pipe_config->gmch_pfit.pgm_ratios,
9967 pipe_config->gmch_pfit.lvds_border_bits);
9968 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9969 pipe_config->pch_pfit.pos,
9970 pipe_config->pch_pfit.size,
9971 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9972 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9973 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9974 }
9975
9976 static bool encoders_cloneable(const struct intel_encoder *a,
9977 const struct intel_encoder *b)
9978 {
9979 /* masks could be asymmetric, so check both ways */
9980 return a == b || (a->cloneable & (1 << b->type) &&
9981 b->cloneable & (1 << a->type));
9982 }
9983
9984 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9985 struct intel_encoder *encoder)
9986 {
9987 struct drm_device *dev = crtc->base.dev;
9988 struct intel_encoder *source_encoder;
9989
9990 list_for_each_entry(source_encoder,
9991 &dev->mode_config.encoder_list, base.head) {
9992 if (source_encoder->new_crtc != crtc)
9993 continue;
9994
9995 if (!encoders_cloneable(encoder, source_encoder))
9996 return false;
9997 }
9998
9999 return true;
10000 }
10001
10002 static bool check_encoder_cloning(struct intel_crtc *crtc)
10003 {
10004 struct drm_device *dev = crtc->base.dev;
10005 struct intel_encoder *encoder;
10006
10007 list_for_each_entry(encoder,
10008 &dev->mode_config.encoder_list, base.head) {
10009 if (encoder->new_crtc != crtc)
10010 continue;
10011
10012 if (!check_single_encoder_cloning(crtc, encoder))
10013 return false;
10014 }
10015
10016 return true;
10017 }
10018
10019 static struct intel_crtc_config *
10020 intel_modeset_pipe_config(struct drm_crtc *crtc,
10021 struct drm_framebuffer *fb,
10022 struct drm_display_mode *mode)
10023 {
10024 struct drm_device *dev = crtc->dev;
10025 struct intel_encoder *encoder;
10026 struct intel_crtc_config *pipe_config;
10027 int plane_bpp, ret = -EINVAL;
10028 bool retry = true;
10029
10030 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10031 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10032 return ERR_PTR(-EINVAL);
10033 }
10034
10035 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10036 if (!pipe_config)
10037 return ERR_PTR(-ENOMEM);
10038
10039 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10040 drm_mode_copy(&pipe_config->requested_mode, mode);
10041
10042 pipe_config->cpu_transcoder =
10043 (enum transcoder) to_intel_crtc(crtc)->pipe;
10044 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10045
10046 /*
10047 * Sanitize sync polarity flags based on requested ones. If neither
10048 * positive or negative polarity is requested, treat this as meaning
10049 * negative polarity.
10050 */
10051 if (!(pipe_config->adjusted_mode.flags &
10052 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10053 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10054
10055 if (!(pipe_config->adjusted_mode.flags &
10056 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10057 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10058
10059 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10060 * plane pixel format and any sink constraints into account. Returns the
10061 * source plane bpp so that dithering can be selected on mismatches
10062 * after encoders and crtc also have had their say. */
10063 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10064 fb, pipe_config);
10065 if (plane_bpp < 0)
10066 goto fail;
10067
10068 /*
10069 * Determine the real pipe dimensions. Note that stereo modes can
10070 * increase the actual pipe size due to the frame doubling and
10071 * insertion of additional space for blanks between the frame. This
10072 * is stored in the crtc timings. We use the requested mode to do this
10073 * computation to clearly distinguish it from the adjusted mode, which
10074 * can be changed by the connectors in the below retry loop.
10075 */
10076 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10077 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10078 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10079
10080 encoder_retry:
10081 /* Ensure the port clock defaults are reset when retrying. */
10082 pipe_config->port_clock = 0;
10083 pipe_config->pixel_multiplier = 1;
10084
10085 /* Fill in default crtc timings, allow encoders to overwrite them. */
10086 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10087
10088 /* Pass our mode to the connectors and the CRTC to give them a chance to
10089 * adjust it according to limitations or connector properties, and also
10090 * a chance to reject the mode entirely.
10091 */
10092 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10093 base.head) {
10094
10095 if (&encoder->new_crtc->base != crtc)
10096 continue;
10097
10098 if (!(encoder->compute_config(encoder, pipe_config))) {
10099 DRM_DEBUG_KMS("Encoder config failure\n");
10100 goto fail;
10101 }
10102 }
10103
10104 /* Set default port clock if not overwritten by the encoder. Needs to be
10105 * done afterwards in case the encoder adjusts the mode. */
10106 if (!pipe_config->port_clock)
10107 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10108 * pipe_config->pixel_multiplier;
10109
10110 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10111 if (ret < 0) {
10112 DRM_DEBUG_KMS("CRTC fixup failed\n");
10113 goto fail;
10114 }
10115
10116 if (ret == RETRY) {
10117 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10118 ret = -EINVAL;
10119 goto fail;
10120 }
10121
10122 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10123 retry = false;
10124 goto encoder_retry;
10125 }
10126
10127 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10128 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10129 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10130
10131 return pipe_config;
10132 fail:
10133 kfree(pipe_config);
10134 return ERR_PTR(ret);
10135 }
10136
10137 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10138 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10139 static void
10140 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10141 unsigned *prepare_pipes, unsigned *disable_pipes)
10142 {
10143 struct intel_crtc *intel_crtc;
10144 struct drm_device *dev = crtc->dev;
10145 struct intel_encoder *encoder;
10146 struct intel_connector *connector;
10147 struct drm_crtc *tmp_crtc;
10148
10149 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10150
10151 /* Check which crtcs have changed outputs connected to them, these need
10152 * to be part of the prepare_pipes mask. We don't (yet) support global
10153 * modeset across multiple crtcs, so modeset_pipes will only have one
10154 * bit set at most. */
10155 list_for_each_entry(connector, &dev->mode_config.connector_list,
10156 base.head) {
10157 if (connector->base.encoder == &connector->new_encoder->base)
10158 continue;
10159
10160 if (connector->base.encoder) {
10161 tmp_crtc = connector->base.encoder->crtc;
10162
10163 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10164 }
10165
10166 if (connector->new_encoder)
10167 *prepare_pipes |=
10168 1 << connector->new_encoder->new_crtc->pipe;
10169 }
10170
10171 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10172 base.head) {
10173 if (encoder->base.crtc == &encoder->new_crtc->base)
10174 continue;
10175
10176 if (encoder->base.crtc) {
10177 tmp_crtc = encoder->base.crtc;
10178
10179 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10180 }
10181
10182 if (encoder->new_crtc)
10183 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10184 }
10185
10186 /* Check for pipes that will be enabled/disabled ... */
10187 for_each_intel_crtc(dev, intel_crtc) {
10188 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10189 continue;
10190
10191 if (!intel_crtc->new_enabled)
10192 *disable_pipes |= 1 << intel_crtc->pipe;
10193 else
10194 *prepare_pipes |= 1 << intel_crtc->pipe;
10195 }
10196
10197
10198 /* set_mode is also used to update properties on life display pipes. */
10199 intel_crtc = to_intel_crtc(crtc);
10200 if (intel_crtc->new_enabled)
10201 *prepare_pipes |= 1 << intel_crtc->pipe;
10202
10203 /*
10204 * For simplicity do a full modeset on any pipe where the output routing
10205 * changed. We could be more clever, but that would require us to be
10206 * more careful with calling the relevant encoder->mode_set functions.
10207 */
10208 if (*prepare_pipes)
10209 *modeset_pipes = *prepare_pipes;
10210
10211 /* ... and mask these out. */
10212 *modeset_pipes &= ~(*disable_pipes);
10213 *prepare_pipes &= ~(*disable_pipes);
10214
10215 /*
10216 * HACK: We don't (yet) fully support global modesets. intel_set_config
10217 * obies this rule, but the modeset restore mode of
10218 * intel_modeset_setup_hw_state does not.
10219 */
10220 *modeset_pipes &= 1 << intel_crtc->pipe;
10221 *prepare_pipes &= 1 << intel_crtc->pipe;
10222
10223 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10224 *modeset_pipes, *prepare_pipes, *disable_pipes);
10225 }
10226
10227 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10228 {
10229 struct drm_encoder *encoder;
10230 struct drm_device *dev = crtc->dev;
10231
10232 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10233 if (encoder->crtc == crtc)
10234 return true;
10235
10236 return false;
10237 }
10238
10239 static void
10240 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10241 {
10242 struct intel_encoder *intel_encoder;
10243 struct intel_crtc *intel_crtc;
10244 struct drm_connector *connector;
10245
10246 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
10247 base.head) {
10248 if (!intel_encoder->base.crtc)
10249 continue;
10250
10251 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10252
10253 if (prepare_pipes & (1 << intel_crtc->pipe))
10254 intel_encoder->connectors_active = false;
10255 }
10256
10257 intel_modeset_commit_output_state(dev);
10258
10259 /* Double check state. */
10260 for_each_intel_crtc(dev, intel_crtc) {
10261 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10262 WARN_ON(intel_crtc->new_config &&
10263 intel_crtc->new_config != &intel_crtc->config);
10264 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10265 }
10266
10267 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10268 if (!connector->encoder || !connector->encoder->crtc)
10269 continue;
10270
10271 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10272
10273 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10274 struct drm_property *dpms_property =
10275 dev->mode_config.dpms_property;
10276
10277 connector->dpms = DRM_MODE_DPMS_ON;
10278 drm_object_property_set_value(&connector->base,
10279 dpms_property,
10280 DRM_MODE_DPMS_ON);
10281
10282 intel_encoder = to_intel_encoder(connector->encoder);
10283 intel_encoder->connectors_active = true;
10284 }
10285 }
10286
10287 }
10288
10289 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10290 {
10291 int diff;
10292
10293 if (clock1 == clock2)
10294 return true;
10295
10296 if (!clock1 || !clock2)
10297 return false;
10298
10299 diff = abs(clock1 - clock2);
10300
10301 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10302 return true;
10303
10304 return false;
10305 }
10306
10307 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10308 list_for_each_entry((intel_crtc), \
10309 &(dev)->mode_config.crtc_list, \
10310 base.head) \
10311 if (mask & (1 <<(intel_crtc)->pipe))
10312
10313 static bool
10314 intel_pipe_config_compare(struct drm_device *dev,
10315 struct intel_crtc_config *current_config,
10316 struct intel_crtc_config *pipe_config)
10317 {
10318 #define PIPE_CONF_CHECK_X(name) \
10319 if (current_config->name != pipe_config->name) { \
10320 DRM_ERROR("mismatch in " #name " " \
10321 "(expected 0x%08x, found 0x%08x)\n", \
10322 current_config->name, \
10323 pipe_config->name); \
10324 return false; \
10325 }
10326
10327 #define PIPE_CONF_CHECK_I(name) \
10328 if (current_config->name != pipe_config->name) { \
10329 DRM_ERROR("mismatch in " #name " " \
10330 "(expected %i, found %i)\n", \
10331 current_config->name, \
10332 pipe_config->name); \
10333 return false; \
10334 }
10335
10336 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10337 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10338 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10339 "(expected %i, found %i)\n", \
10340 current_config->name & (mask), \
10341 pipe_config->name & (mask)); \
10342 return false; \
10343 }
10344
10345 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10346 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10347 DRM_ERROR("mismatch in " #name " " \
10348 "(expected %i, found %i)\n", \
10349 current_config->name, \
10350 pipe_config->name); \
10351 return false; \
10352 }
10353
10354 #define PIPE_CONF_QUIRK(quirk) \
10355 ((current_config->quirks | pipe_config->quirks) & (quirk))
10356
10357 PIPE_CONF_CHECK_I(cpu_transcoder);
10358
10359 PIPE_CONF_CHECK_I(has_pch_encoder);
10360 PIPE_CONF_CHECK_I(fdi_lanes);
10361 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10362 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10363 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10364 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10365 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10366
10367 PIPE_CONF_CHECK_I(has_dp_encoder);
10368 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10369 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10370 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10371 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10372 PIPE_CONF_CHECK_I(dp_m_n.tu);
10373
10374 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10375 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10376 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10377 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10378 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10379 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10380
10381 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10382 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10383 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10384 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10385 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10386 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10387
10388 PIPE_CONF_CHECK_I(pixel_multiplier);
10389 PIPE_CONF_CHECK_I(has_hdmi_sink);
10390 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10391 IS_VALLEYVIEW(dev))
10392 PIPE_CONF_CHECK_I(limited_color_range);
10393
10394 PIPE_CONF_CHECK_I(has_audio);
10395
10396 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10397 DRM_MODE_FLAG_INTERLACE);
10398
10399 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10400 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10401 DRM_MODE_FLAG_PHSYNC);
10402 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10403 DRM_MODE_FLAG_NHSYNC);
10404 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10405 DRM_MODE_FLAG_PVSYNC);
10406 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10407 DRM_MODE_FLAG_NVSYNC);
10408 }
10409
10410 PIPE_CONF_CHECK_I(pipe_src_w);
10411 PIPE_CONF_CHECK_I(pipe_src_h);
10412
10413 /*
10414 * FIXME: BIOS likes to set up a cloned config with lvds+external
10415 * screen. Since we don't yet re-compute the pipe config when moving
10416 * just the lvds port away to another pipe the sw tracking won't match.
10417 *
10418 * Proper atomic modesets with recomputed global state will fix this.
10419 * Until then just don't check gmch state for inherited modes.
10420 */
10421 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10422 PIPE_CONF_CHECK_I(gmch_pfit.control);
10423 /* pfit ratios are autocomputed by the hw on gen4+ */
10424 if (INTEL_INFO(dev)->gen < 4)
10425 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10426 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10427 }
10428
10429 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10430 if (current_config->pch_pfit.enabled) {
10431 PIPE_CONF_CHECK_I(pch_pfit.pos);
10432 PIPE_CONF_CHECK_I(pch_pfit.size);
10433 }
10434
10435 /* BDW+ don't expose a synchronous way to read the state */
10436 if (IS_HASWELL(dev))
10437 PIPE_CONF_CHECK_I(ips_enabled);
10438
10439 PIPE_CONF_CHECK_I(double_wide);
10440
10441 PIPE_CONF_CHECK_X(ddi_pll_sel);
10442
10443 PIPE_CONF_CHECK_I(shared_dpll);
10444 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10445 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10446 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10447 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10448 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10449
10450 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10451 PIPE_CONF_CHECK_I(pipe_bpp);
10452
10453 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10454 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10455
10456 #undef PIPE_CONF_CHECK_X
10457 #undef PIPE_CONF_CHECK_I
10458 #undef PIPE_CONF_CHECK_FLAGS
10459 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10460 #undef PIPE_CONF_QUIRK
10461
10462 return true;
10463 }
10464
10465 static void
10466 check_connector_state(struct drm_device *dev)
10467 {
10468 struct intel_connector *connector;
10469
10470 list_for_each_entry(connector, &dev->mode_config.connector_list,
10471 base.head) {
10472 /* This also checks the encoder/connector hw state with the
10473 * ->get_hw_state callbacks. */
10474 intel_connector_check_state(connector);
10475
10476 WARN(&connector->new_encoder->base != connector->base.encoder,
10477 "connector's staged encoder doesn't match current encoder\n");
10478 }
10479 }
10480
10481 static void
10482 check_encoder_state(struct drm_device *dev)
10483 {
10484 struct intel_encoder *encoder;
10485 struct intel_connector *connector;
10486
10487 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10488 base.head) {
10489 bool enabled = false;
10490 bool active = false;
10491 enum pipe pipe, tracked_pipe;
10492
10493 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10494 encoder->base.base.id,
10495 encoder->base.name);
10496
10497 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10498 "encoder's stage crtc doesn't match current crtc\n");
10499 WARN(encoder->connectors_active && !encoder->base.crtc,
10500 "encoder's active_connectors set, but no crtc\n");
10501
10502 list_for_each_entry(connector, &dev->mode_config.connector_list,
10503 base.head) {
10504 if (connector->base.encoder != &encoder->base)
10505 continue;
10506 enabled = true;
10507 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10508 active = true;
10509 }
10510 WARN(!!encoder->base.crtc != enabled,
10511 "encoder's enabled state mismatch "
10512 "(expected %i, found %i)\n",
10513 !!encoder->base.crtc, enabled);
10514 WARN(active && !encoder->base.crtc,
10515 "active encoder with no crtc\n");
10516
10517 WARN(encoder->connectors_active != active,
10518 "encoder's computed active state doesn't match tracked active state "
10519 "(expected %i, found %i)\n", active, encoder->connectors_active);
10520
10521 active = encoder->get_hw_state(encoder, &pipe);
10522 WARN(active != encoder->connectors_active,
10523 "encoder's hw state doesn't match sw tracking "
10524 "(expected %i, found %i)\n",
10525 encoder->connectors_active, active);
10526
10527 if (!encoder->base.crtc)
10528 continue;
10529
10530 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10531 WARN(active && pipe != tracked_pipe,
10532 "active encoder's pipe doesn't match"
10533 "(expected %i, found %i)\n",
10534 tracked_pipe, pipe);
10535
10536 }
10537 }
10538
10539 static void
10540 check_crtc_state(struct drm_device *dev)
10541 {
10542 struct drm_i915_private *dev_priv = dev->dev_private;
10543 struct intel_crtc *crtc;
10544 struct intel_encoder *encoder;
10545 struct intel_crtc_config pipe_config;
10546
10547 for_each_intel_crtc(dev, crtc) {
10548 bool enabled = false;
10549 bool active = false;
10550
10551 memset(&pipe_config, 0, sizeof(pipe_config));
10552
10553 DRM_DEBUG_KMS("[CRTC:%d]\n",
10554 crtc->base.base.id);
10555
10556 WARN(crtc->active && !crtc->base.enabled,
10557 "active crtc, but not enabled in sw tracking\n");
10558
10559 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10560 base.head) {
10561 if (encoder->base.crtc != &crtc->base)
10562 continue;
10563 enabled = true;
10564 if (encoder->connectors_active)
10565 active = true;
10566 }
10567
10568 WARN(active != crtc->active,
10569 "crtc's computed active state doesn't match tracked active state "
10570 "(expected %i, found %i)\n", active, crtc->active);
10571 WARN(enabled != crtc->base.enabled,
10572 "crtc's computed enabled state doesn't match tracked enabled state "
10573 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10574
10575 active = dev_priv->display.get_pipe_config(crtc,
10576 &pipe_config);
10577
10578 /* hw state is inconsistent with the pipe A quirk */
10579 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10580 active = crtc->active;
10581
10582 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10583 base.head) {
10584 enum pipe pipe;
10585 if (encoder->base.crtc != &crtc->base)
10586 continue;
10587 if (encoder->get_hw_state(encoder, &pipe))
10588 encoder->get_config(encoder, &pipe_config);
10589 }
10590
10591 WARN(crtc->active != active,
10592 "crtc active state doesn't match with hw state "
10593 "(expected %i, found %i)\n", crtc->active, active);
10594
10595 if (active &&
10596 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10597 WARN(1, "pipe state doesn't match!\n");
10598 intel_dump_pipe_config(crtc, &pipe_config,
10599 "[hw state]");
10600 intel_dump_pipe_config(crtc, &crtc->config,
10601 "[sw state]");
10602 }
10603 }
10604 }
10605
10606 static void
10607 check_shared_dpll_state(struct drm_device *dev)
10608 {
10609 struct drm_i915_private *dev_priv = dev->dev_private;
10610 struct intel_crtc *crtc;
10611 struct intel_dpll_hw_state dpll_hw_state;
10612 int i;
10613
10614 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10615 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10616 int enabled_crtcs = 0, active_crtcs = 0;
10617 bool active;
10618
10619 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10620
10621 DRM_DEBUG_KMS("%s\n", pll->name);
10622
10623 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10624
10625 WARN(pll->active > pll->refcount,
10626 "more active pll users than references: %i vs %i\n",
10627 pll->active, pll->refcount);
10628 WARN(pll->active && !pll->on,
10629 "pll in active use but not on in sw tracking\n");
10630 WARN(pll->on && !pll->active,
10631 "pll in on but not on in use in sw tracking\n");
10632 WARN(pll->on != active,
10633 "pll on state mismatch (expected %i, found %i)\n",
10634 pll->on, active);
10635
10636 for_each_intel_crtc(dev, crtc) {
10637 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10638 enabled_crtcs++;
10639 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10640 active_crtcs++;
10641 }
10642 WARN(pll->active != active_crtcs,
10643 "pll active crtcs mismatch (expected %i, found %i)\n",
10644 pll->active, active_crtcs);
10645 WARN(pll->refcount != enabled_crtcs,
10646 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10647 pll->refcount, enabled_crtcs);
10648
10649 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10650 sizeof(dpll_hw_state)),
10651 "pll hw state mismatch\n");
10652 }
10653 }
10654
10655 void
10656 intel_modeset_check_state(struct drm_device *dev)
10657 {
10658 check_connector_state(dev);
10659 check_encoder_state(dev);
10660 check_crtc_state(dev);
10661 check_shared_dpll_state(dev);
10662 }
10663
10664 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10665 int dotclock)
10666 {
10667 /*
10668 * FDI already provided one idea for the dotclock.
10669 * Yell if the encoder disagrees.
10670 */
10671 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10672 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10673 pipe_config->adjusted_mode.crtc_clock, dotclock);
10674 }
10675
10676 static void update_scanline_offset(struct intel_crtc *crtc)
10677 {
10678 struct drm_device *dev = crtc->base.dev;
10679
10680 /*
10681 * The scanline counter increments at the leading edge of hsync.
10682 *
10683 * On most platforms it starts counting from vtotal-1 on the
10684 * first active line. That means the scanline counter value is
10685 * always one less than what we would expect. Ie. just after
10686 * start of vblank, which also occurs at start of hsync (on the
10687 * last active line), the scanline counter will read vblank_start-1.
10688 *
10689 * On gen2 the scanline counter starts counting from 1 instead
10690 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10691 * to keep the value positive), instead of adding one.
10692 *
10693 * On HSW+ the behaviour of the scanline counter depends on the output
10694 * type. For DP ports it behaves like most other platforms, but on HDMI
10695 * there's an extra 1 line difference. So we need to add two instead of
10696 * one to the value.
10697 */
10698 if (IS_GEN2(dev)) {
10699 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10700 int vtotal;
10701
10702 vtotal = mode->crtc_vtotal;
10703 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10704 vtotal /= 2;
10705
10706 crtc->scanline_offset = vtotal - 1;
10707 } else if (HAS_DDI(dev) &&
10708 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10709 crtc->scanline_offset = 2;
10710 } else
10711 crtc->scanline_offset = 1;
10712 }
10713
10714 static int __intel_set_mode(struct drm_crtc *crtc,
10715 struct drm_display_mode *mode,
10716 int x, int y, struct drm_framebuffer *fb)
10717 {
10718 struct drm_device *dev = crtc->dev;
10719 struct drm_i915_private *dev_priv = dev->dev_private;
10720 struct drm_display_mode *saved_mode;
10721 struct intel_crtc_config *pipe_config = NULL;
10722 struct intel_crtc *intel_crtc;
10723 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10724 int ret = 0;
10725
10726 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10727 if (!saved_mode)
10728 return -ENOMEM;
10729
10730 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10731 &prepare_pipes, &disable_pipes);
10732
10733 *saved_mode = crtc->mode;
10734
10735 /* Hack: Because we don't (yet) support global modeset on multiple
10736 * crtcs, we don't keep track of the new mode for more than one crtc.
10737 * Hence simply check whether any bit is set in modeset_pipes in all the
10738 * pieces of code that are not yet converted to deal with mutliple crtcs
10739 * changing their mode at the same time. */
10740 if (modeset_pipes) {
10741 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10742 if (IS_ERR(pipe_config)) {
10743 ret = PTR_ERR(pipe_config);
10744 pipe_config = NULL;
10745
10746 goto out;
10747 }
10748 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10749 "[modeset]");
10750 to_intel_crtc(crtc)->new_config = pipe_config;
10751 }
10752
10753 /*
10754 * See if the config requires any additional preparation, e.g.
10755 * to adjust global state with pipes off. We need to do this
10756 * here so we can get the modeset_pipe updated config for the new
10757 * mode set on this crtc. For other crtcs we need to use the
10758 * adjusted_mode bits in the crtc directly.
10759 */
10760 if (IS_VALLEYVIEW(dev)) {
10761 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10762
10763 /* may have added more to prepare_pipes than we should */
10764 prepare_pipes &= ~disable_pipes;
10765 }
10766
10767 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10768 intel_crtc_disable(&intel_crtc->base);
10769
10770 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10771 if (intel_crtc->base.enabled)
10772 dev_priv->display.crtc_disable(&intel_crtc->base);
10773 }
10774
10775 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10776 * to set it here already despite that we pass it down the callchain.
10777 */
10778 if (modeset_pipes) {
10779 crtc->mode = *mode;
10780 /* mode_set/enable/disable functions rely on a correct pipe
10781 * config. */
10782 to_intel_crtc(crtc)->config = *pipe_config;
10783 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10784
10785 /*
10786 * Calculate and store various constants which
10787 * are later needed by vblank and swap-completion
10788 * timestamping. They are derived from true hwmode.
10789 */
10790 drm_calc_timestamping_constants(crtc,
10791 &pipe_config->adjusted_mode);
10792 }
10793
10794 /* Only after disabling all output pipelines that will be changed can we
10795 * update the the output configuration. */
10796 intel_modeset_update_state(dev, prepare_pipes);
10797
10798 if (dev_priv->display.modeset_global_resources)
10799 dev_priv->display.modeset_global_resources(dev);
10800
10801 /* Set up the DPLL and any encoders state that needs to adjust or depend
10802 * on the DPLL.
10803 */
10804 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10805 struct drm_framebuffer *old_fb = crtc->primary->fb;
10806 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10807 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10808
10809 mutex_lock(&dev->struct_mutex);
10810 ret = intel_pin_and_fence_fb_obj(dev,
10811 obj,
10812 NULL);
10813 if (ret != 0) {
10814 DRM_ERROR("pin & fence failed\n");
10815 mutex_unlock(&dev->struct_mutex);
10816 goto done;
10817 }
10818 if (old_fb)
10819 intel_unpin_fb_obj(old_obj);
10820 i915_gem_track_fb(old_obj, obj,
10821 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10822 mutex_unlock(&dev->struct_mutex);
10823
10824 crtc->primary->fb = fb;
10825 crtc->x = x;
10826 crtc->y = y;
10827
10828 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10829 x, y, fb);
10830 if (ret)
10831 goto done;
10832 }
10833
10834 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10835 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10836 update_scanline_offset(intel_crtc);
10837
10838 dev_priv->display.crtc_enable(&intel_crtc->base);
10839 }
10840
10841 /* FIXME: add subpixel order */
10842 done:
10843 if (ret && crtc->enabled)
10844 crtc->mode = *saved_mode;
10845
10846 out:
10847 kfree(pipe_config);
10848 kfree(saved_mode);
10849 return ret;
10850 }
10851
10852 static int intel_set_mode(struct drm_crtc *crtc,
10853 struct drm_display_mode *mode,
10854 int x, int y, struct drm_framebuffer *fb)
10855 {
10856 int ret;
10857
10858 ret = __intel_set_mode(crtc, mode, x, y, fb);
10859
10860 if (ret == 0)
10861 intel_modeset_check_state(crtc->dev);
10862
10863 return ret;
10864 }
10865
10866 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10867 {
10868 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10869 }
10870
10871 #undef for_each_intel_crtc_masked
10872
10873 static void intel_set_config_free(struct intel_set_config *config)
10874 {
10875 if (!config)
10876 return;
10877
10878 kfree(config->save_connector_encoders);
10879 kfree(config->save_encoder_crtcs);
10880 kfree(config->save_crtc_enabled);
10881 kfree(config);
10882 }
10883
10884 static int intel_set_config_save_state(struct drm_device *dev,
10885 struct intel_set_config *config)
10886 {
10887 struct drm_crtc *crtc;
10888 struct drm_encoder *encoder;
10889 struct drm_connector *connector;
10890 int count;
10891
10892 config->save_crtc_enabled =
10893 kcalloc(dev->mode_config.num_crtc,
10894 sizeof(bool), GFP_KERNEL);
10895 if (!config->save_crtc_enabled)
10896 return -ENOMEM;
10897
10898 config->save_encoder_crtcs =
10899 kcalloc(dev->mode_config.num_encoder,
10900 sizeof(struct drm_crtc *), GFP_KERNEL);
10901 if (!config->save_encoder_crtcs)
10902 return -ENOMEM;
10903
10904 config->save_connector_encoders =
10905 kcalloc(dev->mode_config.num_connector,
10906 sizeof(struct drm_encoder *), GFP_KERNEL);
10907 if (!config->save_connector_encoders)
10908 return -ENOMEM;
10909
10910 /* Copy data. Note that driver private data is not affected.
10911 * Should anything bad happen only the expected state is
10912 * restored, not the drivers personal bookkeeping.
10913 */
10914 count = 0;
10915 for_each_crtc(dev, crtc) {
10916 config->save_crtc_enabled[count++] = crtc->enabled;
10917 }
10918
10919 count = 0;
10920 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10921 config->save_encoder_crtcs[count++] = encoder->crtc;
10922 }
10923
10924 count = 0;
10925 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10926 config->save_connector_encoders[count++] = connector->encoder;
10927 }
10928
10929 return 0;
10930 }
10931
10932 static void intel_set_config_restore_state(struct drm_device *dev,
10933 struct intel_set_config *config)
10934 {
10935 struct intel_crtc *crtc;
10936 struct intel_encoder *encoder;
10937 struct intel_connector *connector;
10938 int count;
10939
10940 count = 0;
10941 for_each_intel_crtc(dev, crtc) {
10942 crtc->new_enabled = config->save_crtc_enabled[count++];
10943
10944 if (crtc->new_enabled)
10945 crtc->new_config = &crtc->config;
10946 else
10947 crtc->new_config = NULL;
10948 }
10949
10950 count = 0;
10951 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10952 encoder->new_crtc =
10953 to_intel_crtc(config->save_encoder_crtcs[count++]);
10954 }
10955
10956 count = 0;
10957 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10958 connector->new_encoder =
10959 to_intel_encoder(config->save_connector_encoders[count++]);
10960 }
10961 }
10962
10963 static bool
10964 is_crtc_connector_off(struct drm_mode_set *set)
10965 {
10966 int i;
10967
10968 if (set->num_connectors == 0)
10969 return false;
10970
10971 if (WARN_ON(set->connectors == NULL))
10972 return false;
10973
10974 for (i = 0; i < set->num_connectors; i++)
10975 if (set->connectors[i]->encoder &&
10976 set->connectors[i]->encoder->crtc == set->crtc &&
10977 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10978 return true;
10979
10980 return false;
10981 }
10982
10983 static void
10984 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10985 struct intel_set_config *config)
10986 {
10987
10988 /* We should be able to check here if the fb has the same properties
10989 * and then just flip_or_move it */
10990 if (is_crtc_connector_off(set)) {
10991 config->mode_changed = true;
10992 } else if (set->crtc->primary->fb != set->fb) {
10993 /*
10994 * If we have no fb, we can only flip as long as the crtc is
10995 * active, otherwise we need a full mode set. The crtc may
10996 * be active if we've only disabled the primary plane, or
10997 * in fastboot situations.
10998 */
10999 if (set->crtc->primary->fb == NULL) {
11000 struct intel_crtc *intel_crtc =
11001 to_intel_crtc(set->crtc);
11002
11003 if (intel_crtc->active) {
11004 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11005 config->fb_changed = true;
11006 } else {
11007 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11008 config->mode_changed = true;
11009 }
11010 } else if (set->fb == NULL) {
11011 config->mode_changed = true;
11012 } else if (set->fb->pixel_format !=
11013 set->crtc->primary->fb->pixel_format) {
11014 config->mode_changed = true;
11015 } else {
11016 config->fb_changed = true;
11017 }
11018 }
11019
11020 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11021 config->fb_changed = true;
11022
11023 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11024 DRM_DEBUG_KMS("modes are different, full mode set\n");
11025 drm_mode_debug_printmodeline(&set->crtc->mode);
11026 drm_mode_debug_printmodeline(set->mode);
11027 config->mode_changed = true;
11028 }
11029
11030 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11031 set->crtc->base.id, config->mode_changed, config->fb_changed);
11032 }
11033
11034 static int
11035 intel_modeset_stage_output_state(struct drm_device *dev,
11036 struct drm_mode_set *set,
11037 struct intel_set_config *config)
11038 {
11039 struct intel_connector *connector;
11040 struct intel_encoder *encoder;
11041 struct intel_crtc *crtc;
11042 int ro;
11043
11044 /* The upper layers ensure that we either disable a crtc or have a list
11045 * of connectors. For paranoia, double-check this. */
11046 WARN_ON(!set->fb && (set->num_connectors != 0));
11047 WARN_ON(set->fb && (set->num_connectors == 0));
11048
11049 list_for_each_entry(connector, &dev->mode_config.connector_list,
11050 base.head) {
11051 /* Otherwise traverse passed in connector list and get encoders
11052 * for them. */
11053 for (ro = 0; ro < set->num_connectors; ro++) {
11054 if (set->connectors[ro] == &connector->base) {
11055 connector->new_encoder = connector->encoder;
11056 break;
11057 }
11058 }
11059
11060 /* If we disable the crtc, disable all its connectors. Also, if
11061 * the connector is on the changing crtc but not on the new
11062 * connector list, disable it. */
11063 if ((!set->fb || ro == set->num_connectors) &&
11064 connector->base.encoder &&
11065 connector->base.encoder->crtc == set->crtc) {
11066 connector->new_encoder = NULL;
11067
11068 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11069 connector->base.base.id,
11070 connector->base.name);
11071 }
11072
11073
11074 if (&connector->new_encoder->base != connector->base.encoder) {
11075 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11076 config->mode_changed = true;
11077 }
11078 }
11079 /* connector->new_encoder is now updated for all connectors. */
11080
11081 /* Update crtc of enabled connectors. */
11082 list_for_each_entry(connector, &dev->mode_config.connector_list,
11083 base.head) {
11084 struct drm_crtc *new_crtc;
11085
11086 if (!connector->new_encoder)
11087 continue;
11088
11089 new_crtc = connector->new_encoder->base.crtc;
11090
11091 for (ro = 0; ro < set->num_connectors; ro++) {
11092 if (set->connectors[ro] == &connector->base)
11093 new_crtc = set->crtc;
11094 }
11095
11096 /* Make sure the new CRTC will work with the encoder */
11097 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11098 new_crtc)) {
11099 return -EINVAL;
11100 }
11101 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
11102
11103 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11104 connector->base.base.id,
11105 connector->base.name,
11106 new_crtc->base.id);
11107 }
11108
11109 /* Check for any encoders that needs to be disabled. */
11110 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11111 base.head) {
11112 int num_connectors = 0;
11113 list_for_each_entry(connector,
11114 &dev->mode_config.connector_list,
11115 base.head) {
11116 if (connector->new_encoder == encoder) {
11117 WARN_ON(!connector->new_encoder->new_crtc);
11118 num_connectors++;
11119 }
11120 }
11121
11122 if (num_connectors == 0)
11123 encoder->new_crtc = NULL;
11124 else if (num_connectors > 1)
11125 return -EINVAL;
11126
11127 /* Only now check for crtc changes so we don't miss encoders
11128 * that will be disabled. */
11129 if (&encoder->new_crtc->base != encoder->base.crtc) {
11130 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11131 config->mode_changed = true;
11132 }
11133 }
11134 /* Now we've also updated encoder->new_crtc for all encoders. */
11135
11136 for_each_intel_crtc(dev, crtc) {
11137 crtc->new_enabled = false;
11138
11139 list_for_each_entry(encoder,
11140 &dev->mode_config.encoder_list,
11141 base.head) {
11142 if (encoder->new_crtc == crtc) {
11143 crtc->new_enabled = true;
11144 break;
11145 }
11146 }
11147
11148 if (crtc->new_enabled != crtc->base.enabled) {
11149 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11150 crtc->new_enabled ? "en" : "dis");
11151 config->mode_changed = true;
11152 }
11153
11154 if (crtc->new_enabled)
11155 crtc->new_config = &crtc->config;
11156 else
11157 crtc->new_config = NULL;
11158 }
11159
11160 return 0;
11161 }
11162
11163 static void disable_crtc_nofb(struct intel_crtc *crtc)
11164 {
11165 struct drm_device *dev = crtc->base.dev;
11166 struct intel_encoder *encoder;
11167 struct intel_connector *connector;
11168
11169 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11170 pipe_name(crtc->pipe));
11171
11172 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11173 if (connector->new_encoder &&
11174 connector->new_encoder->new_crtc == crtc)
11175 connector->new_encoder = NULL;
11176 }
11177
11178 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11179 if (encoder->new_crtc == crtc)
11180 encoder->new_crtc = NULL;
11181 }
11182
11183 crtc->new_enabled = false;
11184 crtc->new_config = NULL;
11185 }
11186
11187 static int intel_crtc_set_config(struct drm_mode_set *set)
11188 {
11189 struct drm_device *dev;
11190 struct drm_mode_set save_set;
11191 struct intel_set_config *config;
11192 int ret;
11193
11194 BUG_ON(!set);
11195 BUG_ON(!set->crtc);
11196 BUG_ON(!set->crtc->helper_private);
11197
11198 /* Enforce sane interface api - has been abused by the fb helper. */
11199 BUG_ON(!set->mode && set->fb);
11200 BUG_ON(set->fb && set->num_connectors == 0);
11201
11202 if (set->fb) {
11203 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11204 set->crtc->base.id, set->fb->base.id,
11205 (int)set->num_connectors, set->x, set->y);
11206 } else {
11207 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11208 }
11209
11210 dev = set->crtc->dev;
11211
11212 ret = -ENOMEM;
11213 config = kzalloc(sizeof(*config), GFP_KERNEL);
11214 if (!config)
11215 goto out_config;
11216
11217 ret = intel_set_config_save_state(dev, config);
11218 if (ret)
11219 goto out_config;
11220
11221 save_set.crtc = set->crtc;
11222 save_set.mode = &set->crtc->mode;
11223 save_set.x = set->crtc->x;
11224 save_set.y = set->crtc->y;
11225 save_set.fb = set->crtc->primary->fb;
11226
11227 /* Compute whether we need a full modeset, only an fb base update or no
11228 * change at all. In the future we might also check whether only the
11229 * mode changed, e.g. for LVDS where we only change the panel fitter in
11230 * such cases. */
11231 intel_set_config_compute_mode_changes(set, config);
11232
11233 ret = intel_modeset_stage_output_state(dev, set, config);
11234 if (ret)
11235 goto fail;
11236
11237 if (config->mode_changed) {
11238 ret = intel_set_mode(set->crtc, set->mode,
11239 set->x, set->y, set->fb);
11240 } else if (config->fb_changed) {
11241 struct drm_i915_private *dev_priv = dev->dev_private;
11242 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11243
11244 intel_crtc_wait_for_pending_flips(set->crtc);
11245
11246 ret = intel_pipe_set_base(set->crtc,
11247 set->x, set->y, set->fb);
11248
11249 /*
11250 * We need to make sure the primary plane is re-enabled if it
11251 * has previously been turned off.
11252 */
11253 if (!intel_crtc->primary_enabled && ret == 0) {
11254 WARN_ON(!intel_crtc->active);
11255 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11256 intel_crtc->pipe);
11257 }
11258
11259 /*
11260 * In the fastboot case this may be our only check of the
11261 * state after boot. It would be better to only do it on
11262 * the first update, but we don't have a nice way of doing that
11263 * (and really, set_config isn't used much for high freq page
11264 * flipping, so increasing its cost here shouldn't be a big
11265 * deal).
11266 */
11267 if (i915.fastboot && ret == 0)
11268 intel_modeset_check_state(set->crtc->dev);
11269 }
11270
11271 if (ret) {
11272 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11273 set->crtc->base.id, ret);
11274 fail:
11275 intel_set_config_restore_state(dev, config);
11276
11277 /*
11278 * HACK: if the pipe was on, but we didn't have a framebuffer,
11279 * force the pipe off to avoid oopsing in the modeset code
11280 * due to fb==NULL. This should only happen during boot since
11281 * we don't yet reconstruct the FB from the hardware state.
11282 */
11283 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11284 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11285
11286 /* Try to restore the config */
11287 if (config->mode_changed &&
11288 intel_set_mode(save_set.crtc, save_set.mode,
11289 save_set.x, save_set.y, save_set.fb))
11290 DRM_ERROR("failed to restore config after modeset failure\n");
11291 }
11292
11293 out_config:
11294 intel_set_config_free(config);
11295 return ret;
11296 }
11297
11298 static const struct drm_crtc_funcs intel_crtc_funcs = {
11299 .gamma_set = intel_crtc_gamma_set,
11300 .set_config = intel_crtc_set_config,
11301 .destroy = intel_crtc_destroy,
11302 .page_flip = intel_crtc_page_flip,
11303 };
11304
11305 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11306 struct intel_shared_dpll *pll,
11307 struct intel_dpll_hw_state *hw_state)
11308 {
11309 uint32_t val;
11310
11311 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS))
11312 return false;
11313
11314 val = I915_READ(PCH_DPLL(pll->id));
11315 hw_state->dpll = val;
11316 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11317 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11318
11319 return val & DPLL_VCO_ENABLE;
11320 }
11321
11322 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11323 struct intel_shared_dpll *pll)
11324 {
11325 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
11326 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
11327 }
11328
11329 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11330 struct intel_shared_dpll *pll)
11331 {
11332 /* PCH refclock must be enabled first */
11333 ibx_assert_pch_refclk_enabled(dev_priv);
11334
11335 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11336
11337 /* Wait for the clocks to stabilize. */
11338 POSTING_READ(PCH_DPLL(pll->id));
11339 udelay(150);
11340
11341 /* The pixel multiplier can only be updated once the
11342 * DPLL is enabled and the clocks are stable.
11343 *
11344 * So write it again.
11345 */
11346 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
11347 POSTING_READ(PCH_DPLL(pll->id));
11348 udelay(200);
11349 }
11350
11351 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11352 struct intel_shared_dpll *pll)
11353 {
11354 struct drm_device *dev = dev_priv->dev;
11355 struct intel_crtc *crtc;
11356
11357 /* Make sure no transcoder isn't still depending on us. */
11358 for_each_intel_crtc(dev, crtc) {
11359 if (intel_crtc_to_shared_dpll(crtc) == pll)
11360 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11361 }
11362
11363 I915_WRITE(PCH_DPLL(pll->id), 0);
11364 POSTING_READ(PCH_DPLL(pll->id));
11365 udelay(200);
11366 }
11367
11368 static char *ibx_pch_dpll_names[] = {
11369 "PCH DPLL A",
11370 "PCH DPLL B",
11371 };
11372
11373 static void ibx_pch_dpll_init(struct drm_device *dev)
11374 {
11375 struct drm_i915_private *dev_priv = dev->dev_private;
11376 int i;
11377
11378 dev_priv->num_shared_dpll = 2;
11379
11380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11381 dev_priv->shared_dplls[i].id = i;
11382 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11383 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11384 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11385 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11386 dev_priv->shared_dplls[i].get_hw_state =
11387 ibx_pch_dpll_get_hw_state;
11388 }
11389 }
11390
11391 static void intel_shared_dpll_init(struct drm_device *dev)
11392 {
11393 struct drm_i915_private *dev_priv = dev->dev_private;
11394
11395 if (HAS_DDI(dev))
11396 intel_ddi_pll_init(dev);
11397 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11398 ibx_pch_dpll_init(dev);
11399 else
11400 dev_priv->num_shared_dpll = 0;
11401
11402 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11403 }
11404
11405 static int
11406 intel_primary_plane_disable(struct drm_plane *plane)
11407 {
11408 struct drm_device *dev = plane->dev;
11409 struct drm_i915_private *dev_priv = dev->dev_private;
11410 struct intel_plane *intel_plane = to_intel_plane(plane);
11411 struct intel_crtc *intel_crtc;
11412
11413 if (!plane->fb)
11414 return 0;
11415
11416 BUG_ON(!plane->crtc);
11417
11418 intel_crtc = to_intel_crtc(plane->crtc);
11419
11420 /*
11421 * Even though we checked plane->fb above, it's still possible that
11422 * the primary plane has been implicitly disabled because the crtc
11423 * coordinates given weren't visible, or because we detected
11424 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11425 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11426 * In either case, we need to unpin the FB and let the fb pointer get
11427 * updated, but otherwise we don't need to touch the hardware.
11428 */
11429 if (!intel_crtc->primary_enabled)
11430 goto disable_unpin;
11431
11432 intel_crtc_wait_for_pending_flips(plane->crtc);
11433 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11434 intel_plane->pipe);
11435 disable_unpin:
11436 mutex_lock(&dev->struct_mutex);
11437 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11438 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11439 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11440 mutex_unlock(&dev->struct_mutex);
11441 plane->fb = NULL;
11442
11443 return 0;
11444 }
11445
11446 static int
11447 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11448 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11449 unsigned int crtc_w, unsigned int crtc_h,
11450 uint32_t src_x, uint32_t src_y,
11451 uint32_t src_w, uint32_t src_h)
11452 {
11453 struct drm_device *dev = crtc->dev;
11454 struct drm_i915_private *dev_priv = dev->dev_private;
11455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11456 struct intel_plane *intel_plane = to_intel_plane(plane);
11457 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11458 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11459 struct drm_rect dest = {
11460 /* integer pixels */
11461 .x1 = crtc_x,
11462 .y1 = crtc_y,
11463 .x2 = crtc_x + crtc_w,
11464 .y2 = crtc_y + crtc_h,
11465 };
11466 struct drm_rect src = {
11467 /* 16.16 fixed point */
11468 .x1 = src_x,
11469 .y1 = src_y,
11470 .x2 = src_x + src_w,
11471 .y2 = src_y + src_h,
11472 };
11473 const struct drm_rect clip = {
11474 /* integer pixels */
11475 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11476 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11477 };
11478 bool visible;
11479 int ret;
11480
11481 ret = drm_plane_helper_check_update(plane, crtc, fb,
11482 &src, &dest, &clip,
11483 DRM_PLANE_HELPER_NO_SCALING,
11484 DRM_PLANE_HELPER_NO_SCALING,
11485 false, true, &visible);
11486
11487 if (ret)
11488 return ret;
11489
11490 /*
11491 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11492 * updating the fb pointer, and returning without touching the
11493 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11494 * turn on the display with all planes setup as desired.
11495 */
11496 if (!crtc->enabled) {
11497 mutex_lock(&dev->struct_mutex);
11498
11499 /*
11500 * If we already called setplane while the crtc was disabled,
11501 * we may have an fb pinned; unpin it.
11502 */
11503 if (plane->fb)
11504 intel_unpin_fb_obj(old_obj);
11505
11506 i915_gem_track_fb(old_obj, obj,
11507 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11508
11509 /* Pin and return without programming hardware */
11510 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11511 mutex_unlock(&dev->struct_mutex);
11512
11513 return ret;
11514 }
11515
11516 intel_crtc_wait_for_pending_flips(crtc);
11517
11518 /*
11519 * If clipping results in a non-visible primary plane, we'll disable
11520 * the primary plane. Note that this is a bit different than what
11521 * happens if userspace explicitly disables the plane by passing fb=0
11522 * because plane->fb still gets set and pinned.
11523 */
11524 if (!visible) {
11525 mutex_lock(&dev->struct_mutex);
11526
11527 /*
11528 * Try to pin the new fb first so that we can bail out if we
11529 * fail.
11530 */
11531 if (plane->fb != fb) {
11532 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
11533 if (ret) {
11534 mutex_unlock(&dev->struct_mutex);
11535 return ret;
11536 }
11537 }
11538
11539 i915_gem_track_fb(old_obj, obj,
11540 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11541
11542 if (intel_crtc->primary_enabled)
11543 intel_disable_primary_hw_plane(dev_priv,
11544 intel_plane->plane,
11545 intel_plane->pipe);
11546
11547
11548 if (plane->fb != fb)
11549 if (plane->fb)
11550 intel_unpin_fb_obj(old_obj);
11551
11552 mutex_unlock(&dev->struct_mutex);
11553
11554 return 0;
11555 }
11556
11557 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11558 if (ret)
11559 return ret;
11560
11561 if (!intel_crtc->primary_enabled)
11562 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11563 intel_crtc->pipe);
11564
11565 return 0;
11566 }
11567
11568 /* Common destruction function for both primary and cursor planes */
11569 static void intel_plane_destroy(struct drm_plane *plane)
11570 {
11571 struct intel_plane *intel_plane = to_intel_plane(plane);
11572 drm_plane_cleanup(plane);
11573 kfree(intel_plane);
11574 }
11575
11576 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11577 .update_plane = intel_primary_plane_setplane,
11578 .disable_plane = intel_primary_plane_disable,
11579 .destroy = intel_plane_destroy,
11580 };
11581
11582 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11583 int pipe)
11584 {
11585 struct intel_plane *primary;
11586 const uint32_t *intel_primary_formats;
11587 int num_formats;
11588
11589 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11590 if (primary == NULL)
11591 return NULL;
11592
11593 primary->can_scale = false;
11594 primary->max_downscale = 1;
11595 primary->pipe = pipe;
11596 primary->plane = pipe;
11597 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11598 primary->plane = !pipe;
11599
11600 if (INTEL_INFO(dev)->gen <= 3) {
11601 intel_primary_formats = intel_primary_formats_gen2;
11602 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11603 } else {
11604 intel_primary_formats = intel_primary_formats_gen4;
11605 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11606 }
11607
11608 drm_universal_plane_init(dev, &primary->base, 0,
11609 &intel_primary_plane_funcs,
11610 intel_primary_formats, num_formats,
11611 DRM_PLANE_TYPE_PRIMARY);
11612 return &primary->base;
11613 }
11614
11615 static int
11616 intel_cursor_plane_disable(struct drm_plane *plane)
11617 {
11618 if (!plane->fb)
11619 return 0;
11620
11621 BUG_ON(!plane->crtc);
11622
11623 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11624 }
11625
11626 static int
11627 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11628 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11629 unsigned int crtc_w, unsigned int crtc_h,
11630 uint32_t src_x, uint32_t src_y,
11631 uint32_t src_w, uint32_t src_h)
11632 {
11633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11634 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11635 struct drm_i915_gem_object *obj = intel_fb->obj;
11636 struct drm_rect dest = {
11637 /* integer pixels */
11638 .x1 = crtc_x,
11639 .y1 = crtc_y,
11640 .x2 = crtc_x + crtc_w,
11641 .y2 = crtc_y + crtc_h,
11642 };
11643 struct drm_rect src = {
11644 /* 16.16 fixed point */
11645 .x1 = src_x,
11646 .y1 = src_y,
11647 .x2 = src_x + src_w,
11648 .y2 = src_y + src_h,
11649 };
11650 const struct drm_rect clip = {
11651 /* integer pixels */
11652 .x2 = intel_crtc->config.pipe_src_w,
11653 .y2 = intel_crtc->config.pipe_src_h,
11654 };
11655 bool visible;
11656 int ret;
11657
11658 ret = drm_plane_helper_check_update(plane, crtc, fb,
11659 &src, &dest, &clip,
11660 DRM_PLANE_HELPER_NO_SCALING,
11661 DRM_PLANE_HELPER_NO_SCALING,
11662 true, true, &visible);
11663 if (ret)
11664 return ret;
11665
11666 crtc->cursor_x = crtc_x;
11667 crtc->cursor_y = crtc_y;
11668 if (fb != crtc->cursor->fb) {
11669 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11670 } else {
11671 intel_crtc_update_cursor(crtc, visible);
11672 return 0;
11673 }
11674 }
11675 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11676 .update_plane = intel_cursor_plane_update,
11677 .disable_plane = intel_cursor_plane_disable,
11678 .destroy = intel_plane_destroy,
11679 };
11680
11681 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11682 int pipe)
11683 {
11684 struct intel_plane *cursor;
11685
11686 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11687 if (cursor == NULL)
11688 return NULL;
11689
11690 cursor->can_scale = false;
11691 cursor->max_downscale = 1;
11692 cursor->pipe = pipe;
11693 cursor->plane = pipe;
11694
11695 drm_universal_plane_init(dev, &cursor->base, 0,
11696 &intel_cursor_plane_funcs,
11697 intel_cursor_formats,
11698 ARRAY_SIZE(intel_cursor_formats),
11699 DRM_PLANE_TYPE_CURSOR);
11700 return &cursor->base;
11701 }
11702
11703 static void intel_crtc_init(struct drm_device *dev, int pipe)
11704 {
11705 struct drm_i915_private *dev_priv = dev->dev_private;
11706 struct intel_crtc *intel_crtc;
11707 struct drm_plane *primary = NULL;
11708 struct drm_plane *cursor = NULL;
11709 int i, ret;
11710
11711 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11712 if (intel_crtc == NULL)
11713 return;
11714
11715 primary = intel_primary_plane_create(dev, pipe);
11716 if (!primary)
11717 goto fail;
11718
11719 cursor = intel_cursor_plane_create(dev, pipe);
11720 if (!cursor)
11721 goto fail;
11722
11723 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11724 cursor, &intel_crtc_funcs);
11725 if (ret)
11726 goto fail;
11727
11728 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11729 for (i = 0; i < 256; i++) {
11730 intel_crtc->lut_r[i] = i;
11731 intel_crtc->lut_g[i] = i;
11732 intel_crtc->lut_b[i] = i;
11733 }
11734
11735 /*
11736 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11737 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11738 */
11739 intel_crtc->pipe = pipe;
11740 intel_crtc->plane = pipe;
11741 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11742 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11743 intel_crtc->plane = !pipe;
11744 }
11745
11746 intel_crtc->cursor_base = ~0;
11747 intel_crtc->cursor_cntl = ~0;
11748
11749 init_waitqueue_head(&intel_crtc->vbl_wait);
11750
11751 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11752 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11753 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11754 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11755
11756 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11757
11758 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11759 return;
11760
11761 fail:
11762 if (primary)
11763 drm_plane_cleanup(primary);
11764 if (cursor)
11765 drm_plane_cleanup(cursor);
11766 kfree(intel_crtc);
11767 }
11768
11769 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11770 {
11771 struct drm_encoder *encoder = connector->base.encoder;
11772 struct drm_device *dev = connector->base.dev;
11773
11774 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11775
11776 if (!encoder)
11777 return INVALID_PIPE;
11778
11779 return to_intel_crtc(encoder->crtc)->pipe;
11780 }
11781
11782 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11783 struct drm_file *file)
11784 {
11785 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11786 struct drm_mode_object *drmmode_obj;
11787 struct intel_crtc *crtc;
11788
11789 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11790 return -ENODEV;
11791
11792 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11793 DRM_MODE_OBJECT_CRTC);
11794
11795 if (!drmmode_obj) {
11796 DRM_ERROR("no such CRTC id\n");
11797 return -ENOENT;
11798 }
11799
11800 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11801 pipe_from_crtc_id->pipe = crtc->pipe;
11802
11803 return 0;
11804 }
11805
11806 static int intel_encoder_clones(struct intel_encoder *encoder)
11807 {
11808 struct drm_device *dev = encoder->base.dev;
11809 struct intel_encoder *source_encoder;
11810 int index_mask = 0;
11811 int entry = 0;
11812
11813 list_for_each_entry(source_encoder,
11814 &dev->mode_config.encoder_list, base.head) {
11815 if (encoders_cloneable(encoder, source_encoder))
11816 index_mask |= (1 << entry);
11817
11818 entry++;
11819 }
11820
11821 return index_mask;
11822 }
11823
11824 static bool has_edp_a(struct drm_device *dev)
11825 {
11826 struct drm_i915_private *dev_priv = dev->dev_private;
11827
11828 if (!IS_MOBILE(dev))
11829 return false;
11830
11831 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11832 return false;
11833
11834 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11835 return false;
11836
11837 return true;
11838 }
11839
11840 const char *intel_output_name(int output)
11841 {
11842 static const char *names[] = {
11843 [INTEL_OUTPUT_UNUSED] = "Unused",
11844 [INTEL_OUTPUT_ANALOG] = "Analog",
11845 [INTEL_OUTPUT_DVO] = "DVO",
11846 [INTEL_OUTPUT_SDVO] = "SDVO",
11847 [INTEL_OUTPUT_LVDS] = "LVDS",
11848 [INTEL_OUTPUT_TVOUT] = "TV",
11849 [INTEL_OUTPUT_HDMI] = "HDMI",
11850 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11851 [INTEL_OUTPUT_EDP] = "eDP",
11852 [INTEL_OUTPUT_DSI] = "DSI",
11853 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11854 };
11855
11856 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11857 return "Invalid";
11858
11859 return names[output];
11860 }
11861
11862 static bool intel_crt_present(struct drm_device *dev)
11863 {
11864 struct drm_i915_private *dev_priv = dev->dev_private;
11865
11866 if (IS_ULT(dev))
11867 return false;
11868
11869 if (IS_CHERRYVIEW(dev))
11870 return false;
11871
11872 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
11873 return false;
11874
11875 return true;
11876 }
11877
11878 static void intel_setup_outputs(struct drm_device *dev)
11879 {
11880 struct drm_i915_private *dev_priv = dev->dev_private;
11881 struct intel_encoder *encoder;
11882 bool dpd_is_edp = false;
11883
11884 intel_lvds_init(dev);
11885
11886 if (intel_crt_present(dev))
11887 intel_crt_init(dev);
11888
11889 if (HAS_DDI(dev)) {
11890 int found;
11891
11892 /* Haswell uses DDI functions to detect digital outputs */
11893 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11894 /* DDI A only supports eDP */
11895 if (found)
11896 intel_ddi_init(dev, PORT_A);
11897
11898 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11899 * register */
11900 found = I915_READ(SFUSE_STRAP);
11901
11902 if (found & SFUSE_STRAP_DDIB_DETECTED)
11903 intel_ddi_init(dev, PORT_B);
11904 if (found & SFUSE_STRAP_DDIC_DETECTED)
11905 intel_ddi_init(dev, PORT_C);
11906 if (found & SFUSE_STRAP_DDID_DETECTED)
11907 intel_ddi_init(dev, PORT_D);
11908 } else if (HAS_PCH_SPLIT(dev)) {
11909 int found;
11910 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11911
11912 if (has_edp_a(dev))
11913 intel_dp_init(dev, DP_A, PORT_A);
11914
11915 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11916 /* PCH SDVOB multiplex with HDMIB */
11917 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11918 if (!found)
11919 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11920 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11921 intel_dp_init(dev, PCH_DP_B, PORT_B);
11922 }
11923
11924 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11925 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11926
11927 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11928 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11929
11930 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11931 intel_dp_init(dev, PCH_DP_C, PORT_C);
11932
11933 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11934 intel_dp_init(dev, PCH_DP_D, PORT_D);
11935 } else if (IS_VALLEYVIEW(dev)) {
11936 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11937 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11938 PORT_B);
11939 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11940 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11941 }
11942
11943 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11944 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11945 PORT_C);
11946 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11947 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11948 }
11949
11950 if (IS_CHERRYVIEW(dev)) {
11951 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11952 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11953 PORT_D);
11954 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11955 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11956 }
11957 }
11958
11959 intel_dsi_init(dev);
11960 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11961 bool found = false;
11962
11963 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11964 DRM_DEBUG_KMS("probing SDVOB\n");
11965 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11966 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11967 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11968 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11969 }
11970
11971 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11972 intel_dp_init(dev, DP_B, PORT_B);
11973 }
11974
11975 /* Before G4X SDVOC doesn't have its own detect register */
11976
11977 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11978 DRM_DEBUG_KMS("probing SDVOC\n");
11979 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11980 }
11981
11982 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11983
11984 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11985 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11986 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11987 }
11988 if (SUPPORTS_INTEGRATED_DP(dev))
11989 intel_dp_init(dev, DP_C, PORT_C);
11990 }
11991
11992 if (SUPPORTS_INTEGRATED_DP(dev) &&
11993 (I915_READ(DP_D) & DP_DETECTED))
11994 intel_dp_init(dev, DP_D, PORT_D);
11995 } else if (IS_GEN2(dev))
11996 intel_dvo_init(dev);
11997
11998 if (SUPPORTS_TV(dev))
11999 intel_tv_init(dev);
12000
12001 intel_edp_psr_init(dev);
12002
12003 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
12004 encoder->base.possible_crtcs = encoder->crtc_mask;
12005 encoder->base.possible_clones =
12006 intel_encoder_clones(encoder);
12007 }
12008
12009 intel_init_pch_refclk(dev);
12010
12011 drm_helper_move_panel_connectors_to_head(dev);
12012 }
12013
12014 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12015 {
12016 struct drm_device *dev = fb->dev;
12017 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12018
12019 drm_framebuffer_cleanup(fb);
12020 mutex_lock(&dev->struct_mutex);
12021 WARN_ON(!intel_fb->obj->framebuffer_references--);
12022 drm_gem_object_unreference(&intel_fb->obj->base);
12023 mutex_unlock(&dev->struct_mutex);
12024 kfree(intel_fb);
12025 }
12026
12027 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12028 struct drm_file *file,
12029 unsigned int *handle)
12030 {
12031 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12032 struct drm_i915_gem_object *obj = intel_fb->obj;
12033
12034 return drm_gem_handle_create(file, &obj->base, handle);
12035 }
12036
12037 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12038 .destroy = intel_user_framebuffer_destroy,
12039 .create_handle = intel_user_framebuffer_create_handle,
12040 };
12041
12042 static int intel_framebuffer_init(struct drm_device *dev,
12043 struct intel_framebuffer *intel_fb,
12044 struct drm_mode_fb_cmd2 *mode_cmd,
12045 struct drm_i915_gem_object *obj)
12046 {
12047 int aligned_height;
12048 int pitch_limit;
12049 int ret;
12050
12051 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12052
12053 if (obj->tiling_mode == I915_TILING_Y) {
12054 DRM_DEBUG("hardware does not support tiling Y\n");
12055 return -EINVAL;
12056 }
12057
12058 if (mode_cmd->pitches[0] & 63) {
12059 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12060 mode_cmd->pitches[0]);
12061 return -EINVAL;
12062 }
12063
12064 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12065 pitch_limit = 32*1024;
12066 } else if (INTEL_INFO(dev)->gen >= 4) {
12067 if (obj->tiling_mode)
12068 pitch_limit = 16*1024;
12069 else
12070 pitch_limit = 32*1024;
12071 } else if (INTEL_INFO(dev)->gen >= 3) {
12072 if (obj->tiling_mode)
12073 pitch_limit = 8*1024;
12074 else
12075 pitch_limit = 16*1024;
12076 } else
12077 /* XXX DSPC is limited to 4k tiled */
12078 pitch_limit = 8*1024;
12079
12080 if (mode_cmd->pitches[0] > pitch_limit) {
12081 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12082 obj->tiling_mode ? "tiled" : "linear",
12083 mode_cmd->pitches[0], pitch_limit);
12084 return -EINVAL;
12085 }
12086
12087 if (obj->tiling_mode != I915_TILING_NONE &&
12088 mode_cmd->pitches[0] != obj->stride) {
12089 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12090 mode_cmd->pitches[0], obj->stride);
12091 return -EINVAL;
12092 }
12093
12094 /* Reject formats not supported by any plane early. */
12095 switch (mode_cmd->pixel_format) {
12096 case DRM_FORMAT_C8:
12097 case DRM_FORMAT_RGB565:
12098 case DRM_FORMAT_XRGB8888:
12099 case DRM_FORMAT_ARGB8888:
12100 break;
12101 case DRM_FORMAT_XRGB1555:
12102 case DRM_FORMAT_ARGB1555:
12103 if (INTEL_INFO(dev)->gen > 3) {
12104 DRM_DEBUG("unsupported pixel format: %s\n",
12105 drm_get_format_name(mode_cmd->pixel_format));
12106 return -EINVAL;
12107 }
12108 break;
12109 case DRM_FORMAT_XBGR8888:
12110 case DRM_FORMAT_ABGR8888:
12111 case DRM_FORMAT_XRGB2101010:
12112 case DRM_FORMAT_ARGB2101010:
12113 case DRM_FORMAT_XBGR2101010:
12114 case DRM_FORMAT_ABGR2101010:
12115 if (INTEL_INFO(dev)->gen < 4) {
12116 DRM_DEBUG("unsupported pixel format: %s\n",
12117 drm_get_format_name(mode_cmd->pixel_format));
12118 return -EINVAL;
12119 }
12120 break;
12121 case DRM_FORMAT_YUYV:
12122 case DRM_FORMAT_UYVY:
12123 case DRM_FORMAT_YVYU:
12124 case DRM_FORMAT_VYUY:
12125 if (INTEL_INFO(dev)->gen < 5) {
12126 DRM_DEBUG("unsupported pixel format: %s\n",
12127 drm_get_format_name(mode_cmd->pixel_format));
12128 return -EINVAL;
12129 }
12130 break;
12131 default:
12132 DRM_DEBUG("unsupported pixel format: %s\n",
12133 drm_get_format_name(mode_cmd->pixel_format));
12134 return -EINVAL;
12135 }
12136
12137 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12138 if (mode_cmd->offsets[0] != 0)
12139 return -EINVAL;
12140
12141 aligned_height = intel_align_height(dev, mode_cmd->height,
12142 obj->tiling_mode);
12143 /* FIXME drm helper for size checks (especially planar formats)? */
12144 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12145 return -EINVAL;
12146
12147 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12148 intel_fb->obj = obj;
12149 intel_fb->obj->framebuffer_references++;
12150
12151 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12152 if (ret) {
12153 DRM_ERROR("framebuffer init failed %d\n", ret);
12154 return ret;
12155 }
12156
12157 return 0;
12158 }
12159
12160 static struct drm_framebuffer *
12161 intel_user_framebuffer_create(struct drm_device *dev,
12162 struct drm_file *filp,
12163 struct drm_mode_fb_cmd2 *mode_cmd)
12164 {
12165 struct drm_i915_gem_object *obj;
12166
12167 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12168 mode_cmd->handles[0]));
12169 if (&obj->base == NULL)
12170 return ERR_PTR(-ENOENT);
12171
12172 return intel_framebuffer_create(dev, mode_cmd, obj);
12173 }
12174
12175 #ifndef CONFIG_DRM_I915_FBDEV
12176 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12177 {
12178 }
12179 #endif
12180
12181 static const struct drm_mode_config_funcs intel_mode_funcs = {
12182 .fb_create = intel_user_framebuffer_create,
12183 .output_poll_changed = intel_fbdev_output_poll_changed,
12184 };
12185
12186 /* Set up chip specific display functions */
12187 static void intel_init_display(struct drm_device *dev)
12188 {
12189 struct drm_i915_private *dev_priv = dev->dev_private;
12190
12191 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12192 dev_priv->display.find_dpll = g4x_find_best_dpll;
12193 else if (IS_CHERRYVIEW(dev))
12194 dev_priv->display.find_dpll = chv_find_best_dpll;
12195 else if (IS_VALLEYVIEW(dev))
12196 dev_priv->display.find_dpll = vlv_find_best_dpll;
12197 else if (IS_PINEVIEW(dev))
12198 dev_priv->display.find_dpll = pnv_find_best_dpll;
12199 else
12200 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12201
12202 if (HAS_DDI(dev)) {
12203 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12204 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12205 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
12206 dev_priv->display.crtc_enable = haswell_crtc_enable;
12207 dev_priv->display.crtc_disable = haswell_crtc_disable;
12208 dev_priv->display.off = ironlake_crtc_off;
12209 dev_priv->display.update_primary_plane =
12210 ironlake_update_primary_plane;
12211 } else if (HAS_PCH_SPLIT(dev)) {
12212 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12213 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12214 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
12215 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12216 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12217 dev_priv->display.off = ironlake_crtc_off;
12218 dev_priv->display.update_primary_plane =
12219 ironlake_update_primary_plane;
12220 } else if (IS_VALLEYVIEW(dev)) {
12221 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12222 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12223 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12224 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12225 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12226 dev_priv->display.off = i9xx_crtc_off;
12227 dev_priv->display.update_primary_plane =
12228 i9xx_update_primary_plane;
12229 } else {
12230 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12231 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12232 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
12233 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12234 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12235 dev_priv->display.off = i9xx_crtc_off;
12236 dev_priv->display.update_primary_plane =
12237 i9xx_update_primary_plane;
12238 }
12239
12240 /* Returns the core display clock speed */
12241 if (IS_VALLEYVIEW(dev))
12242 dev_priv->display.get_display_clock_speed =
12243 valleyview_get_display_clock_speed;
12244 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12245 dev_priv->display.get_display_clock_speed =
12246 i945_get_display_clock_speed;
12247 else if (IS_I915G(dev))
12248 dev_priv->display.get_display_clock_speed =
12249 i915_get_display_clock_speed;
12250 else if (IS_I945GM(dev) || IS_845G(dev))
12251 dev_priv->display.get_display_clock_speed =
12252 i9xx_misc_get_display_clock_speed;
12253 else if (IS_PINEVIEW(dev))
12254 dev_priv->display.get_display_clock_speed =
12255 pnv_get_display_clock_speed;
12256 else if (IS_I915GM(dev))
12257 dev_priv->display.get_display_clock_speed =
12258 i915gm_get_display_clock_speed;
12259 else if (IS_I865G(dev))
12260 dev_priv->display.get_display_clock_speed =
12261 i865_get_display_clock_speed;
12262 else if (IS_I85X(dev))
12263 dev_priv->display.get_display_clock_speed =
12264 i855_get_display_clock_speed;
12265 else /* 852, 830 */
12266 dev_priv->display.get_display_clock_speed =
12267 i830_get_display_clock_speed;
12268
12269 if (HAS_PCH_SPLIT(dev)) {
12270 if (IS_GEN5(dev)) {
12271 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12272 dev_priv->display.write_eld = ironlake_write_eld;
12273 } else if (IS_GEN6(dev)) {
12274 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12275 dev_priv->display.write_eld = ironlake_write_eld;
12276 dev_priv->display.modeset_global_resources =
12277 snb_modeset_global_resources;
12278 } else if (IS_IVYBRIDGE(dev)) {
12279 /* FIXME: detect B0+ stepping and use auto training */
12280 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12281 dev_priv->display.write_eld = ironlake_write_eld;
12282 dev_priv->display.modeset_global_resources =
12283 ivb_modeset_global_resources;
12284 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
12285 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12286 dev_priv->display.write_eld = haswell_write_eld;
12287 dev_priv->display.modeset_global_resources =
12288 haswell_modeset_global_resources;
12289 }
12290 } else if (IS_G4X(dev)) {
12291 dev_priv->display.write_eld = g4x_write_eld;
12292 } else if (IS_VALLEYVIEW(dev)) {
12293 dev_priv->display.modeset_global_resources =
12294 valleyview_modeset_global_resources;
12295 dev_priv->display.write_eld = ironlake_write_eld;
12296 }
12297
12298 /* Default just returns -ENODEV to indicate unsupported */
12299 dev_priv->display.queue_flip = intel_default_queue_flip;
12300
12301 switch (INTEL_INFO(dev)->gen) {
12302 case 2:
12303 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12304 break;
12305
12306 case 3:
12307 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12308 break;
12309
12310 case 4:
12311 case 5:
12312 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12313 break;
12314
12315 case 6:
12316 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12317 break;
12318 case 7:
12319 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12320 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12321 break;
12322 }
12323
12324 intel_panel_init_backlight_funcs(dev);
12325 }
12326
12327 /*
12328 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12329 * resume, or other times. This quirk makes sure that's the case for
12330 * affected systems.
12331 */
12332 static void quirk_pipea_force(struct drm_device *dev)
12333 {
12334 struct drm_i915_private *dev_priv = dev->dev_private;
12335
12336 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12337 DRM_INFO("applying pipe a force quirk\n");
12338 }
12339
12340 /*
12341 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12342 */
12343 static void quirk_ssc_force_disable(struct drm_device *dev)
12344 {
12345 struct drm_i915_private *dev_priv = dev->dev_private;
12346 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12347 DRM_INFO("applying lvds SSC disable quirk\n");
12348 }
12349
12350 /*
12351 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12352 * brightness value
12353 */
12354 static void quirk_invert_brightness(struct drm_device *dev)
12355 {
12356 struct drm_i915_private *dev_priv = dev->dev_private;
12357 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12358 DRM_INFO("applying inverted panel brightness quirk\n");
12359 }
12360
12361 struct intel_quirk {
12362 int device;
12363 int subsystem_vendor;
12364 int subsystem_device;
12365 void (*hook)(struct drm_device *dev);
12366 };
12367
12368 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12369 struct intel_dmi_quirk {
12370 void (*hook)(struct drm_device *dev);
12371 const struct dmi_system_id (*dmi_id_list)[];
12372 };
12373
12374 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12375 {
12376 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12377 return 1;
12378 }
12379
12380 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12381 {
12382 .dmi_id_list = &(const struct dmi_system_id[]) {
12383 {
12384 .callback = intel_dmi_reverse_brightness,
12385 .ident = "NCR Corporation",
12386 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12387 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12388 },
12389 },
12390 { } /* terminating entry */
12391 },
12392 .hook = quirk_invert_brightness,
12393 },
12394 };
12395
12396 static struct intel_quirk intel_quirks[] = {
12397 /* HP Mini needs pipe A force quirk (LP: #322104) */
12398 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12399
12400 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12401 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12402
12403 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12404 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12405
12406 /* Lenovo U160 cannot use SSC on LVDS */
12407 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12408
12409 /* Sony Vaio Y cannot use SSC on LVDS */
12410 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12411
12412 /* Acer Aspire 5734Z must invert backlight brightness */
12413 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12414
12415 /* Acer/eMachines G725 */
12416 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12417
12418 /* Acer/eMachines e725 */
12419 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12420
12421 /* Acer/Packard Bell NCL20 */
12422 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12423
12424 /* Acer Aspire 4736Z */
12425 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12426
12427 /* Acer Aspire 5336 */
12428 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12429 };
12430
12431 static void intel_init_quirks(struct drm_device *dev)
12432 {
12433 struct pci_dev *d = dev->pdev;
12434 int i;
12435
12436 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12437 struct intel_quirk *q = &intel_quirks[i];
12438
12439 if (d->device == q->device &&
12440 (d->subsystem_vendor == q->subsystem_vendor ||
12441 q->subsystem_vendor == PCI_ANY_ID) &&
12442 (d->subsystem_device == q->subsystem_device ||
12443 q->subsystem_device == PCI_ANY_ID))
12444 q->hook(dev);
12445 }
12446 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12447 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12448 intel_dmi_quirks[i].hook(dev);
12449 }
12450 }
12451
12452 /* Disable the VGA plane that we never use */
12453 static void i915_disable_vga(struct drm_device *dev)
12454 {
12455 struct drm_i915_private *dev_priv = dev->dev_private;
12456 u8 sr1;
12457 u32 vga_reg = i915_vgacntrl_reg(dev);
12458
12459 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12460 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12461 outb(SR01, VGA_SR_INDEX);
12462 sr1 = inb(VGA_SR_DATA);
12463 outb(sr1 | 1<<5, VGA_SR_DATA);
12464 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12465 udelay(300);
12466
12467 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12468 POSTING_READ(vga_reg);
12469 }
12470
12471 void intel_modeset_init_hw(struct drm_device *dev)
12472 {
12473 intel_prepare_ddi(dev);
12474
12475 if (IS_VALLEYVIEW(dev))
12476 vlv_update_cdclk(dev);
12477
12478 intel_init_clock_gating(dev);
12479
12480 intel_reset_dpio(dev);
12481
12482 intel_enable_gt_powersave(dev);
12483 }
12484
12485 void intel_modeset_suspend_hw(struct drm_device *dev)
12486 {
12487 intel_suspend_hw(dev);
12488 }
12489
12490 void intel_modeset_init(struct drm_device *dev)
12491 {
12492 struct drm_i915_private *dev_priv = dev->dev_private;
12493 int sprite, ret;
12494 enum pipe pipe;
12495 struct intel_crtc *crtc;
12496
12497 drm_mode_config_init(dev);
12498
12499 dev->mode_config.min_width = 0;
12500 dev->mode_config.min_height = 0;
12501
12502 dev->mode_config.preferred_depth = 24;
12503 dev->mode_config.prefer_shadow = 1;
12504
12505 dev->mode_config.funcs = &intel_mode_funcs;
12506
12507 intel_init_quirks(dev);
12508
12509 intel_init_pm(dev);
12510
12511 if (INTEL_INFO(dev)->num_pipes == 0)
12512 return;
12513
12514 intel_init_display(dev);
12515
12516 if (IS_GEN2(dev)) {
12517 dev->mode_config.max_width = 2048;
12518 dev->mode_config.max_height = 2048;
12519 } else if (IS_GEN3(dev)) {
12520 dev->mode_config.max_width = 4096;
12521 dev->mode_config.max_height = 4096;
12522 } else {
12523 dev->mode_config.max_width = 8192;
12524 dev->mode_config.max_height = 8192;
12525 }
12526
12527 if (IS_GEN2(dev)) {
12528 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12529 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12530 } else {
12531 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12532 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12533 }
12534
12535 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12536
12537 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12538 INTEL_INFO(dev)->num_pipes,
12539 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12540
12541 for_each_pipe(pipe) {
12542 intel_crtc_init(dev, pipe);
12543 for_each_sprite(pipe, sprite) {
12544 ret = intel_plane_init(dev, pipe, sprite);
12545 if (ret)
12546 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12547 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12548 }
12549 }
12550
12551 intel_init_dpio(dev);
12552 intel_reset_dpio(dev);
12553
12554 intel_shared_dpll_init(dev);
12555
12556 /* Just disable it once at startup */
12557 i915_disable_vga(dev);
12558 intel_setup_outputs(dev);
12559
12560 /* Just in case the BIOS is doing something questionable. */
12561 intel_disable_fbc(dev);
12562
12563 drm_modeset_lock_all(dev);
12564 intel_modeset_setup_hw_state(dev, false);
12565 drm_modeset_unlock_all(dev);
12566
12567 for_each_intel_crtc(dev, crtc) {
12568 if (!crtc->active)
12569 continue;
12570
12571 /*
12572 * Note that reserving the BIOS fb up front prevents us
12573 * from stuffing other stolen allocations like the ring
12574 * on top. This prevents some ugliness at boot time, and
12575 * can even allow for smooth boot transitions if the BIOS
12576 * fb is large enough for the active pipe configuration.
12577 */
12578 if (dev_priv->display.get_plane_config) {
12579 dev_priv->display.get_plane_config(crtc,
12580 &crtc->plane_config);
12581 /*
12582 * If the fb is shared between multiple heads, we'll
12583 * just get the first one.
12584 */
12585 intel_find_plane_obj(crtc, &crtc->plane_config);
12586 }
12587 }
12588 }
12589
12590 static void intel_enable_pipe_a(struct drm_device *dev)
12591 {
12592 struct intel_connector *connector;
12593 struct drm_connector *crt = NULL;
12594 struct intel_load_detect_pipe load_detect_temp;
12595 struct drm_modeset_acquire_ctx ctx;
12596
12597 /* We can't just switch on the pipe A, we need to set things up with a
12598 * proper mode and output configuration. As a gross hack, enable pipe A
12599 * by enabling the load detect pipe once. */
12600 list_for_each_entry(connector,
12601 &dev->mode_config.connector_list,
12602 base.head) {
12603 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12604 crt = &connector->base;
12605 break;
12606 }
12607 }
12608
12609 if (!crt)
12610 return;
12611
12612 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12613 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12614
12615
12616 }
12617
12618 static bool
12619 intel_check_plane_mapping(struct intel_crtc *crtc)
12620 {
12621 struct drm_device *dev = crtc->base.dev;
12622 struct drm_i915_private *dev_priv = dev->dev_private;
12623 u32 reg, val;
12624
12625 if (INTEL_INFO(dev)->num_pipes == 1)
12626 return true;
12627
12628 reg = DSPCNTR(!crtc->plane);
12629 val = I915_READ(reg);
12630
12631 if ((val & DISPLAY_PLANE_ENABLE) &&
12632 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12633 return false;
12634
12635 return true;
12636 }
12637
12638 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12639 {
12640 struct drm_device *dev = crtc->base.dev;
12641 struct drm_i915_private *dev_priv = dev->dev_private;
12642 u32 reg;
12643
12644 /* Clear any frame start delays used for debugging left by the BIOS */
12645 reg = PIPECONF(crtc->config.cpu_transcoder);
12646 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12647
12648 /* restore vblank interrupts to correct state */
12649 if (crtc->active)
12650 drm_vblank_on(dev, crtc->pipe);
12651 else
12652 drm_vblank_off(dev, crtc->pipe);
12653
12654 /* We need to sanitize the plane -> pipe mapping first because this will
12655 * disable the crtc (and hence change the state) if it is wrong. Note
12656 * that gen4+ has a fixed plane -> pipe mapping. */
12657 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12658 struct intel_connector *connector;
12659 bool plane;
12660
12661 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12662 crtc->base.base.id);
12663
12664 /* Pipe has the wrong plane attached and the plane is active.
12665 * Temporarily change the plane mapping and disable everything
12666 * ... */
12667 plane = crtc->plane;
12668 crtc->plane = !plane;
12669 dev_priv->display.crtc_disable(&crtc->base);
12670 crtc->plane = plane;
12671
12672 /* ... and break all links. */
12673 list_for_each_entry(connector, &dev->mode_config.connector_list,
12674 base.head) {
12675 if (connector->encoder->base.crtc != &crtc->base)
12676 continue;
12677
12678 connector->base.dpms = DRM_MODE_DPMS_OFF;
12679 connector->base.encoder = NULL;
12680 }
12681 /* multiple connectors may have the same encoder:
12682 * handle them and break crtc link separately */
12683 list_for_each_entry(connector, &dev->mode_config.connector_list,
12684 base.head)
12685 if (connector->encoder->base.crtc == &crtc->base) {
12686 connector->encoder->base.crtc = NULL;
12687 connector->encoder->connectors_active = false;
12688 }
12689
12690 WARN_ON(crtc->active);
12691 crtc->base.enabled = false;
12692 }
12693
12694 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12695 crtc->pipe == PIPE_A && !crtc->active) {
12696 /* BIOS forgot to enable pipe A, this mostly happens after
12697 * resume. Force-enable the pipe to fix this, the update_dpms
12698 * call below we restore the pipe to the right state, but leave
12699 * the required bits on. */
12700 intel_enable_pipe_a(dev);
12701 }
12702
12703 /* Adjust the state of the output pipe according to whether we
12704 * have active connectors/encoders. */
12705 intel_crtc_update_dpms(&crtc->base);
12706
12707 if (crtc->active != crtc->base.enabled) {
12708 struct intel_encoder *encoder;
12709
12710 /* This can happen either due to bugs in the get_hw_state
12711 * functions or because the pipe is force-enabled due to the
12712 * pipe A quirk. */
12713 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12714 crtc->base.base.id,
12715 crtc->base.enabled ? "enabled" : "disabled",
12716 crtc->active ? "enabled" : "disabled");
12717
12718 crtc->base.enabled = crtc->active;
12719
12720 /* Because we only establish the connector -> encoder ->
12721 * crtc links if something is active, this means the
12722 * crtc is now deactivated. Break the links. connector
12723 * -> encoder links are only establish when things are
12724 * actually up, hence no need to break them. */
12725 WARN_ON(crtc->active);
12726
12727 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12728 WARN_ON(encoder->connectors_active);
12729 encoder->base.crtc = NULL;
12730 }
12731 }
12732
12733 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12734 /*
12735 * We start out with underrun reporting disabled to avoid races.
12736 * For correct bookkeeping mark this on active crtcs.
12737 *
12738 * Also on gmch platforms we dont have any hardware bits to
12739 * disable the underrun reporting. Which means we need to start
12740 * out with underrun reporting disabled also on inactive pipes,
12741 * since otherwise we'll complain about the garbage we read when
12742 * e.g. coming up after runtime pm.
12743 *
12744 * No protection against concurrent access is required - at
12745 * worst a fifo underrun happens which also sets this to false.
12746 */
12747 crtc->cpu_fifo_underrun_disabled = true;
12748 crtc->pch_fifo_underrun_disabled = true;
12749
12750 update_scanline_offset(crtc);
12751 }
12752 }
12753
12754 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12755 {
12756 struct intel_connector *connector;
12757 struct drm_device *dev = encoder->base.dev;
12758
12759 /* We need to check both for a crtc link (meaning that the
12760 * encoder is active and trying to read from a pipe) and the
12761 * pipe itself being active. */
12762 bool has_active_crtc = encoder->base.crtc &&
12763 to_intel_crtc(encoder->base.crtc)->active;
12764
12765 if (encoder->connectors_active && !has_active_crtc) {
12766 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12767 encoder->base.base.id,
12768 encoder->base.name);
12769
12770 /* Connector is active, but has no active pipe. This is
12771 * fallout from our resume register restoring. Disable
12772 * the encoder manually again. */
12773 if (encoder->base.crtc) {
12774 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12775 encoder->base.base.id,
12776 encoder->base.name);
12777 encoder->disable(encoder);
12778 if (encoder->post_disable)
12779 encoder->post_disable(encoder);
12780 }
12781 encoder->base.crtc = NULL;
12782 encoder->connectors_active = false;
12783
12784 /* Inconsistent output/port/pipe state happens presumably due to
12785 * a bug in one of the get_hw_state functions. Or someplace else
12786 * in our code, like the register restore mess on resume. Clamp
12787 * things to off as a safer default. */
12788 list_for_each_entry(connector,
12789 &dev->mode_config.connector_list,
12790 base.head) {
12791 if (connector->encoder != encoder)
12792 continue;
12793 connector->base.dpms = DRM_MODE_DPMS_OFF;
12794 connector->base.encoder = NULL;
12795 }
12796 }
12797 /* Enabled encoders without active connectors will be fixed in
12798 * the crtc fixup. */
12799 }
12800
12801 void i915_redisable_vga_power_on(struct drm_device *dev)
12802 {
12803 struct drm_i915_private *dev_priv = dev->dev_private;
12804 u32 vga_reg = i915_vgacntrl_reg(dev);
12805
12806 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12807 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12808 i915_disable_vga(dev);
12809 }
12810 }
12811
12812 void i915_redisable_vga(struct drm_device *dev)
12813 {
12814 struct drm_i915_private *dev_priv = dev->dev_private;
12815
12816 /* This function can be called both from intel_modeset_setup_hw_state or
12817 * at a very early point in our resume sequence, where the power well
12818 * structures are not yet restored. Since this function is at a very
12819 * paranoid "someone might have enabled VGA while we were not looking"
12820 * level, just check if the power well is enabled instead of trying to
12821 * follow the "don't touch the power well if we don't need it" policy
12822 * the rest of the driver uses. */
12823 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12824 return;
12825
12826 i915_redisable_vga_power_on(dev);
12827 }
12828
12829 static bool primary_get_hw_state(struct intel_crtc *crtc)
12830 {
12831 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12832
12833 if (!crtc->active)
12834 return false;
12835
12836 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12837 }
12838
12839 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12840 {
12841 struct drm_i915_private *dev_priv = dev->dev_private;
12842 enum pipe pipe;
12843 struct intel_crtc *crtc;
12844 struct intel_encoder *encoder;
12845 struct intel_connector *connector;
12846 int i;
12847
12848 for_each_intel_crtc(dev, crtc) {
12849 memset(&crtc->config, 0, sizeof(crtc->config));
12850
12851 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12852
12853 crtc->active = dev_priv->display.get_pipe_config(crtc,
12854 &crtc->config);
12855
12856 crtc->base.enabled = crtc->active;
12857 crtc->primary_enabled = primary_get_hw_state(crtc);
12858
12859 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12860 crtc->base.base.id,
12861 crtc->active ? "enabled" : "disabled");
12862 }
12863
12864 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12865 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12866
12867 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12868 pll->active = 0;
12869 for_each_intel_crtc(dev, crtc) {
12870 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12871 pll->active++;
12872 }
12873 pll->refcount = pll->active;
12874
12875 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12876 pll->name, pll->refcount, pll->on);
12877
12878 if (pll->refcount)
12879 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
12880 }
12881
12882 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12883 base.head) {
12884 pipe = 0;
12885
12886 if (encoder->get_hw_state(encoder, &pipe)) {
12887 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12888 encoder->base.crtc = &crtc->base;
12889 encoder->get_config(encoder, &crtc->config);
12890 } else {
12891 encoder->base.crtc = NULL;
12892 }
12893
12894 encoder->connectors_active = false;
12895 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12896 encoder->base.base.id,
12897 encoder->base.name,
12898 encoder->base.crtc ? "enabled" : "disabled",
12899 pipe_name(pipe));
12900 }
12901
12902 list_for_each_entry(connector, &dev->mode_config.connector_list,
12903 base.head) {
12904 if (connector->get_hw_state(connector)) {
12905 connector->base.dpms = DRM_MODE_DPMS_ON;
12906 connector->encoder->connectors_active = true;
12907 connector->base.encoder = &connector->encoder->base;
12908 } else {
12909 connector->base.dpms = DRM_MODE_DPMS_OFF;
12910 connector->base.encoder = NULL;
12911 }
12912 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12913 connector->base.base.id,
12914 connector->base.name,
12915 connector->base.encoder ? "enabled" : "disabled");
12916 }
12917 }
12918
12919 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12920 * and i915 state tracking structures. */
12921 void intel_modeset_setup_hw_state(struct drm_device *dev,
12922 bool force_restore)
12923 {
12924 struct drm_i915_private *dev_priv = dev->dev_private;
12925 enum pipe pipe;
12926 struct intel_crtc *crtc;
12927 struct intel_encoder *encoder;
12928 int i;
12929
12930 intel_modeset_readout_hw_state(dev);
12931
12932 /*
12933 * Now that we have the config, copy it to each CRTC struct
12934 * Note that this could go away if we move to using crtc_config
12935 * checking everywhere.
12936 */
12937 for_each_intel_crtc(dev, crtc) {
12938 if (crtc->active && i915.fastboot) {
12939 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12940 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12941 crtc->base.base.id);
12942 drm_mode_debug_printmodeline(&crtc->base.mode);
12943 }
12944 }
12945
12946 /* HW state is read out, now we need to sanitize this mess. */
12947 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12948 base.head) {
12949 intel_sanitize_encoder(encoder);
12950 }
12951
12952 for_each_pipe(pipe) {
12953 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12954 intel_sanitize_crtc(crtc);
12955 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12956 }
12957
12958 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12959 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12960
12961 if (!pll->on || pll->active)
12962 continue;
12963
12964 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12965
12966 pll->disable(dev_priv, pll);
12967 pll->on = false;
12968 }
12969
12970 if (HAS_PCH_SPLIT(dev))
12971 ilk_wm_get_hw_state(dev);
12972
12973 if (force_restore) {
12974 i915_redisable_vga(dev);
12975
12976 /*
12977 * We need to use raw interfaces for restoring state to avoid
12978 * checking (bogus) intermediate states.
12979 */
12980 for_each_pipe(pipe) {
12981 struct drm_crtc *crtc =
12982 dev_priv->pipe_to_crtc_mapping[pipe];
12983
12984 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12985 crtc->primary->fb);
12986 }
12987 } else {
12988 intel_modeset_update_staged_output_state(dev);
12989 }
12990
12991 intel_modeset_check_state(dev);
12992 }
12993
12994 void intel_modeset_gem_init(struct drm_device *dev)
12995 {
12996 struct drm_crtc *c;
12997 struct drm_i915_gem_object *obj;
12998
12999 mutex_lock(&dev->struct_mutex);
13000 intel_init_gt_powersave(dev);
13001 mutex_unlock(&dev->struct_mutex);
13002
13003 intel_modeset_init_hw(dev);
13004
13005 intel_setup_overlay(dev);
13006
13007 /*
13008 * Make sure any fbs we allocated at startup are properly
13009 * pinned & fenced. When we do the allocation it's too early
13010 * for this.
13011 */
13012 mutex_lock(&dev->struct_mutex);
13013 for_each_crtc(dev, c) {
13014 obj = intel_fb_obj(c->primary->fb);
13015 if (obj == NULL)
13016 continue;
13017
13018 if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) {
13019 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13020 to_intel_crtc(c)->pipe);
13021 drm_framebuffer_unreference(c->primary->fb);
13022 c->primary->fb = NULL;
13023 }
13024 }
13025 mutex_unlock(&dev->struct_mutex);
13026 }
13027
13028 void intel_connector_unregister(struct intel_connector *intel_connector)
13029 {
13030 struct drm_connector *connector = &intel_connector->base;
13031
13032 intel_panel_destroy_backlight(connector);
13033 drm_sysfs_connector_remove(connector);
13034 }
13035
13036 void intel_modeset_cleanup(struct drm_device *dev)
13037 {
13038 struct drm_i915_private *dev_priv = dev->dev_private;
13039 struct drm_connector *connector;
13040
13041 /*
13042 * Interrupts and polling as the first thing to avoid creating havoc.
13043 * Too much stuff here (turning of rps, connectors, ...) would
13044 * experience fancy races otherwise.
13045 */
13046 drm_irq_uninstall(dev);
13047 cancel_work_sync(&dev_priv->hotplug_work);
13048 /*
13049 * Due to the hpd irq storm handling the hotplug work can re-arm the
13050 * poll handlers. Hence disable polling after hpd handling is shut down.
13051 */
13052 drm_kms_helper_poll_fini(dev);
13053
13054 mutex_lock(&dev->struct_mutex);
13055
13056 intel_unregister_dsm_handler();
13057
13058 intel_disable_fbc(dev);
13059
13060 intel_disable_gt_powersave(dev);
13061
13062 ironlake_teardown_rc6(dev);
13063
13064 mutex_unlock(&dev->struct_mutex);
13065
13066 /* flush any delayed tasks or pending work */
13067 flush_scheduled_work();
13068
13069 /* destroy the backlight and sysfs files before encoders/connectors */
13070 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13071 struct intel_connector *intel_connector;
13072
13073 intel_connector = to_intel_connector(connector);
13074 intel_connector->unregister(intel_connector);
13075 }
13076
13077 drm_mode_config_cleanup(dev);
13078
13079 intel_cleanup_overlay(dev);
13080
13081 mutex_lock(&dev->struct_mutex);
13082 intel_cleanup_gt_powersave(dev);
13083 mutex_unlock(&dev->struct_mutex);
13084 }
13085
13086 /*
13087 * Return which encoder is currently attached for connector.
13088 */
13089 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13090 {
13091 return &intel_attached_encoder(connector)->base;
13092 }
13093
13094 void intel_connector_attach_encoder(struct intel_connector *connector,
13095 struct intel_encoder *encoder)
13096 {
13097 connector->encoder = encoder;
13098 drm_mode_connector_attach_encoder(&connector->base,
13099 &encoder->base);
13100 }
13101
13102 /*
13103 * set vga decode state - true == enable VGA decode
13104 */
13105 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13106 {
13107 struct drm_i915_private *dev_priv = dev->dev_private;
13108 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13109 u16 gmch_ctrl;
13110
13111 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13112 DRM_ERROR("failed to read control word\n");
13113 return -EIO;
13114 }
13115
13116 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13117 return 0;
13118
13119 if (state)
13120 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13121 else
13122 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13123
13124 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13125 DRM_ERROR("failed to write control word\n");
13126 return -EIO;
13127 }
13128
13129 return 0;
13130 }
13131
13132 struct intel_display_error_state {
13133
13134 u32 power_well_driver;
13135
13136 int num_transcoders;
13137
13138 struct intel_cursor_error_state {
13139 u32 control;
13140 u32 position;
13141 u32 base;
13142 u32 size;
13143 } cursor[I915_MAX_PIPES];
13144
13145 struct intel_pipe_error_state {
13146 bool power_domain_on;
13147 u32 source;
13148 u32 stat;
13149 } pipe[I915_MAX_PIPES];
13150
13151 struct intel_plane_error_state {
13152 u32 control;
13153 u32 stride;
13154 u32 size;
13155 u32 pos;
13156 u32 addr;
13157 u32 surface;
13158 u32 tile_offset;
13159 } plane[I915_MAX_PIPES];
13160
13161 struct intel_transcoder_error_state {
13162 bool power_domain_on;
13163 enum transcoder cpu_transcoder;
13164
13165 u32 conf;
13166
13167 u32 htotal;
13168 u32 hblank;
13169 u32 hsync;
13170 u32 vtotal;
13171 u32 vblank;
13172 u32 vsync;
13173 } transcoder[4];
13174 };
13175
13176 struct intel_display_error_state *
13177 intel_display_capture_error_state(struct drm_device *dev)
13178 {
13179 struct drm_i915_private *dev_priv = dev->dev_private;
13180 struct intel_display_error_state *error;
13181 int transcoders[] = {
13182 TRANSCODER_A,
13183 TRANSCODER_B,
13184 TRANSCODER_C,
13185 TRANSCODER_EDP,
13186 };
13187 int i;
13188
13189 if (INTEL_INFO(dev)->num_pipes == 0)
13190 return NULL;
13191
13192 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13193 if (error == NULL)
13194 return NULL;
13195
13196 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13197 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13198
13199 for_each_pipe(i) {
13200 error->pipe[i].power_domain_on =
13201 intel_display_power_enabled_unlocked(dev_priv,
13202 POWER_DOMAIN_PIPE(i));
13203 if (!error->pipe[i].power_domain_on)
13204 continue;
13205
13206 error->cursor[i].control = I915_READ(CURCNTR(i));
13207 error->cursor[i].position = I915_READ(CURPOS(i));
13208 error->cursor[i].base = I915_READ(CURBASE(i));
13209
13210 error->plane[i].control = I915_READ(DSPCNTR(i));
13211 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13212 if (INTEL_INFO(dev)->gen <= 3) {
13213 error->plane[i].size = I915_READ(DSPSIZE(i));
13214 error->plane[i].pos = I915_READ(DSPPOS(i));
13215 }
13216 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13217 error->plane[i].addr = I915_READ(DSPADDR(i));
13218 if (INTEL_INFO(dev)->gen >= 4) {
13219 error->plane[i].surface = I915_READ(DSPSURF(i));
13220 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13221 }
13222
13223 error->pipe[i].source = I915_READ(PIPESRC(i));
13224
13225 if (!HAS_PCH_SPLIT(dev))
13226 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13227 }
13228
13229 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13230 if (HAS_DDI(dev_priv->dev))
13231 error->num_transcoders++; /* Account for eDP. */
13232
13233 for (i = 0; i < error->num_transcoders; i++) {
13234 enum transcoder cpu_transcoder = transcoders[i];
13235
13236 error->transcoder[i].power_domain_on =
13237 intel_display_power_enabled_unlocked(dev_priv,
13238 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13239 if (!error->transcoder[i].power_domain_on)
13240 continue;
13241
13242 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13243
13244 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13245 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13246 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13247 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13248 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13249 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13250 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13251 }
13252
13253 return error;
13254 }
13255
13256 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13257
13258 void
13259 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13260 struct drm_device *dev,
13261 struct intel_display_error_state *error)
13262 {
13263 int i;
13264
13265 if (!error)
13266 return;
13267
13268 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13269 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13270 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13271 error->power_well_driver);
13272 for_each_pipe(i) {
13273 err_printf(m, "Pipe [%d]:\n", i);
13274 err_printf(m, " Power: %s\n",
13275 error->pipe[i].power_domain_on ? "on" : "off");
13276 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13277 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13278
13279 err_printf(m, "Plane [%d]:\n", i);
13280 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13281 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13282 if (INTEL_INFO(dev)->gen <= 3) {
13283 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13284 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13285 }
13286 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13287 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13288 if (INTEL_INFO(dev)->gen >= 4) {
13289 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13290 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13291 }
13292
13293 err_printf(m, "Cursor [%d]:\n", i);
13294 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13295 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13296 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13297 }
13298
13299 for (i = 0; i < error->num_transcoders; i++) {
13300 err_printf(m, "CPU transcoder: %c\n",
13301 transcoder_name(error->transcoder[i].cpu_transcoder));
13302 err_printf(m, " Power: %s\n",
13303 error->transcoder[i].power_domain_on ? "on" : "off");
13304 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13305 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13306 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13307 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13308 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13309 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13310 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13311 }
13312 }
Linux kernel - Deliverables
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