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Staging: Merge branch 'tidspbridge-for-2.6.39' of git://dev.omapzoom.org/pub/scm...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
32 #include <linux/vgaarb.h>
33 #include "drmP.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "i915_trace.h"
38 #include "drm_dp_helper.h"
39
40 #include "drm_crtc_helper.h"
41
42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43
44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
45 static void intel_update_watermarks(struct drm_device *dev);
46 static void intel_increase_pllclock(struct drm_crtc *crtc);
47 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
48
49 typedef struct {
50 /* given values */
51 int n;
52 int m1, m2;
53 int p1, p2;
54 /* derived values */
55 int dot;
56 int vco;
57 int m;
58 int p;
59 } intel_clock_t;
60
61 typedef struct {
62 int min, max;
63 } intel_range_t;
64
65 typedef struct {
66 int dot_limit;
67 int p2_slow, p2_fast;
68 } intel_p2_t;
69
70 #define INTEL_P2_NUM 2
71 typedef struct intel_limit intel_limit_t;
72 struct intel_limit {
73 intel_range_t dot, vco, n, m, m1, m2, p, p1;
74 intel_p2_t p2;
75 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
76 int, int, intel_clock_t *);
77 };
78
79 #define I8XX_DOT_MIN 25000
80 #define I8XX_DOT_MAX 350000
81 #define I8XX_VCO_MIN 930000
82 #define I8XX_VCO_MAX 1400000
83 #define I8XX_N_MIN 3
84 #define I8XX_N_MAX 16
85 #define I8XX_M_MIN 96
86 #define I8XX_M_MAX 140
87 #define I8XX_M1_MIN 18
88 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MIN 6
90 #define I8XX_M2_MAX 16
91 #define I8XX_P_MIN 4
92 #define I8XX_P_MAX 128
93 #define I8XX_P1_MIN 2
94 #define I8XX_P1_MAX 33
95 #define I8XX_P1_LVDS_MIN 1
96 #define I8XX_P1_LVDS_MAX 6
97 #define I8XX_P2_SLOW 4
98 #define I8XX_P2_FAST 2
99 #define I8XX_P2_LVDS_SLOW 14
100 #define I8XX_P2_LVDS_FAST 7
101 #define I8XX_P2_SLOW_LIMIT 165000
102
103 #define I9XX_DOT_MIN 20000
104 #define I9XX_DOT_MAX 400000
105 #define I9XX_VCO_MIN 1400000
106 #define I9XX_VCO_MAX 2800000
107 #define PINEVIEW_VCO_MIN 1700000
108 #define PINEVIEW_VCO_MAX 3500000
109 #define I9XX_N_MIN 1
110 #define I9XX_N_MAX 6
111 /* Pineview's Ncounter is a ring counter */
112 #define PINEVIEW_N_MIN 3
113 #define PINEVIEW_N_MAX 6
114 #define I9XX_M_MIN 70
115 #define I9XX_M_MAX 120
116 #define PINEVIEW_M_MIN 2
117 #define PINEVIEW_M_MAX 256
118 #define I9XX_M1_MIN 10
119 #define I9XX_M1_MAX 22
120 #define I9XX_M2_MIN 5
121 #define I9XX_M2_MAX 9
122 /* Pineview M1 is reserved, and must be 0 */
123 #define PINEVIEW_M1_MIN 0
124 #define PINEVIEW_M1_MAX 0
125 #define PINEVIEW_M2_MIN 0
126 #define PINEVIEW_M2_MAX 254
127 #define I9XX_P_SDVO_DAC_MIN 5
128 #define I9XX_P_SDVO_DAC_MAX 80
129 #define I9XX_P_LVDS_MIN 7
130 #define I9XX_P_LVDS_MAX 98
131 #define PINEVIEW_P_LVDS_MIN 7
132 #define PINEVIEW_P_LVDS_MAX 112
133 #define I9XX_P1_MIN 1
134 #define I9XX_P1_MAX 8
135 #define I9XX_P2_SDVO_DAC_SLOW 10
136 #define I9XX_P2_SDVO_DAC_FAST 5
137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
138 #define I9XX_P2_LVDS_SLOW 14
139 #define I9XX_P2_LVDS_FAST 7
140 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141
142 /*The parameter is for SDVO on G4x platform*/
143 #define G4X_DOT_SDVO_MIN 25000
144 #define G4X_DOT_SDVO_MAX 270000
145 #define G4X_VCO_MIN 1750000
146 #define G4X_VCO_MAX 3500000
147 #define G4X_N_SDVO_MIN 1
148 #define G4X_N_SDVO_MAX 4
149 #define G4X_M_SDVO_MIN 104
150 #define G4X_M_SDVO_MAX 138
151 #define G4X_M1_SDVO_MIN 17
152 #define G4X_M1_SDVO_MAX 23
153 #define G4X_M2_SDVO_MIN 5
154 #define G4X_M2_SDVO_MAX 11
155 #define G4X_P_SDVO_MIN 10
156 #define G4X_P_SDVO_MAX 30
157 #define G4X_P1_SDVO_MIN 1
158 #define G4X_P1_SDVO_MAX 3
159 #define G4X_P2_SDVO_SLOW 10
160 #define G4X_P2_SDVO_FAST 10
161 #define G4X_P2_SDVO_LIMIT 270000
162
163 /*The parameter is for HDMI_DAC on G4x platform*/
164 #define G4X_DOT_HDMI_DAC_MIN 22000
165 #define G4X_DOT_HDMI_DAC_MAX 400000
166 #define G4X_N_HDMI_DAC_MIN 1
167 #define G4X_N_HDMI_DAC_MAX 4
168 #define G4X_M_HDMI_DAC_MIN 104
169 #define G4X_M_HDMI_DAC_MAX 138
170 #define G4X_M1_HDMI_DAC_MIN 16
171 #define G4X_M1_HDMI_DAC_MAX 23
172 #define G4X_M2_HDMI_DAC_MIN 5
173 #define G4X_M2_HDMI_DAC_MAX 11
174 #define G4X_P_HDMI_DAC_MIN 5
175 #define G4X_P_HDMI_DAC_MAX 80
176 #define G4X_P1_HDMI_DAC_MIN 1
177 #define G4X_P1_HDMI_DAC_MAX 8
178 #define G4X_P2_HDMI_DAC_SLOW 10
179 #define G4X_P2_HDMI_DAC_FAST 5
180 #define G4X_P2_HDMI_DAC_LIMIT 165000
181
182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200
201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219
220 /*The parameter is for DISPLAY PORT on G4x platform*/
221 #define G4X_DOT_DISPLAY_PORT_MIN 161670
222 #define G4X_DOT_DISPLAY_PORT_MAX 227000
223 #define G4X_N_DISPLAY_PORT_MIN 1
224 #define G4X_N_DISPLAY_PORT_MAX 2
225 #define G4X_M_DISPLAY_PORT_MIN 97
226 #define G4X_M_DISPLAY_PORT_MAX 108
227 #define G4X_M1_DISPLAY_PORT_MIN 0x10
228 #define G4X_M1_DISPLAY_PORT_MAX 0x12
229 #define G4X_M2_DISPLAY_PORT_MIN 0x05
230 #define G4X_M2_DISPLAY_PORT_MAX 0x06
231 #define G4X_P_DISPLAY_PORT_MIN 10
232 #define G4X_P_DISPLAY_PORT_MAX 20
233 #define G4X_P1_DISPLAY_PORT_MIN 1
234 #define G4X_P1_DISPLAY_PORT_MAX 2
235 #define G4X_P2_DISPLAY_PORT_SLOW 10
236 #define G4X_P2_DISPLAY_PORT_FAST 10
237 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238
239 /* Ironlake / Sandybridge */
240 /* as we calculate clock using (register_value + 2) for
241 N/M1/M2, so here the range value for them is (actual_value-2).
242 */
243 #define IRONLAKE_DOT_MIN 25000
244 #define IRONLAKE_DOT_MAX 350000
245 #define IRONLAKE_VCO_MIN 1760000
246 #define IRONLAKE_VCO_MAX 3510000
247 #define IRONLAKE_M1_MIN 12
248 #define IRONLAKE_M1_MAX 22
249 #define IRONLAKE_M2_MIN 5
250 #define IRONLAKE_M2_MAX 9
251 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252
253 /* We have parameter ranges for different type of outputs. */
254
255 /* DAC & HDMI Refclk 120Mhz */
256 #define IRONLAKE_DAC_N_MIN 1
257 #define IRONLAKE_DAC_N_MAX 5
258 #define IRONLAKE_DAC_M_MIN 79
259 #define IRONLAKE_DAC_M_MAX 127
260 #define IRONLAKE_DAC_P_MIN 5
261 #define IRONLAKE_DAC_P_MAX 80
262 #define IRONLAKE_DAC_P1_MIN 1
263 #define IRONLAKE_DAC_P1_MAX 8
264 #define IRONLAKE_DAC_P2_SLOW 10
265 #define IRONLAKE_DAC_P2_FAST 5
266
267 /* LVDS single-channel 120Mhz refclk */
268 #define IRONLAKE_LVDS_S_N_MIN 1
269 #define IRONLAKE_LVDS_S_N_MAX 3
270 #define IRONLAKE_LVDS_S_M_MIN 79
271 #define IRONLAKE_LVDS_S_M_MAX 118
272 #define IRONLAKE_LVDS_S_P_MIN 28
273 #define IRONLAKE_LVDS_S_P_MAX 112
274 #define IRONLAKE_LVDS_S_P1_MIN 2
275 #define IRONLAKE_LVDS_S_P1_MAX 8
276 #define IRONLAKE_LVDS_S_P2_SLOW 14
277 #define IRONLAKE_LVDS_S_P2_FAST 14
278
279 /* LVDS dual-channel 120Mhz refclk */
280 #define IRONLAKE_LVDS_D_N_MIN 1
281 #define IRONLAKE_LVDS_D_N_MAX 3
282 #define IRONLAKE_LVDS_D_M_MIN 79
283 #define IRONLAKE_LVDS_D_M_MAX 127
284 #define IRONLAKE_LVDS_D_P_MIN 14
285 #define IRONLAKE_LVDS_D_P_MAX 56
286 #define IRONLAKE_LVDS_D_P1_MIN 2
287 #define IRONLAKE_LVDS_D_P1_MAX 8
288 #define IRONLAKE_LVDS_D_P2_SLOW 7
289 #define IRONLAKE_LVDS_D_P2_FAST 7
290
291 /* LVDS single-channel 100Mhz refclk */
292 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
293 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
294 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
295 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
296 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
297 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
298 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
299 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
301 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302
303 /* LVDS dual-channel 100Mhz refclk */
304 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
305 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
306 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
307 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
308 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
309 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
310 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
311 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
313 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
314
315 /* DisplayPort */
316 #define IRONLAKE_DP_N_MIN 1
317 #define IRONLAKE_DP_N_MAX 2
318 #define IRONLAKE_DP_M_MIN 81
319 #define IRONLAKE_DP_M_MAX 90
320 #define IRONLAKE_DP_P_MIN 10
321 #define IRONLAKE_DP_P_MAX 20
322 #define IRONLAKE_DP_P2_FAST 10
323 #define IRONLAKE_DP_P2_SLOW 10
324 #define IRONLAKE_DP_P2_LIMIT 0
325 #define IRONLAKE_DP_P1_MIN 1
326 #define IRONLAKE_DP_P1_MAX 2
327
328 /* FDI */
329 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
330
331 static bool
332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
333 int target, int refclk, intel_clock_t *best_clock);
334 static bool
335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
336 int target, int refclk, intel_clock_t *best_clock);
337
338 static bool
339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
340 int target, int refclk, intel_clock_t *best_clock);
341 static bool
342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
343 int target, int refclk, intel_clock_t *best_clock);
344
345 static inline u32 /* units of 100MHz */
346 intel_fdi_link_freq(struct drm_device *dev)
347 {
348 if (IS_GEN5(dev)) {
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
351 } else
352 return 27;
353 }
354
355 static const intel_limit_t intel_limits_i8xx_dvo = {
356 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
357 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
358 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
359 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
360 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
361 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
362 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
363 .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
364 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
365 .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
366 .find_pll = intel_find_best_PLL,
367 };
368
369 static const intel_limit_t intel_limits_i8xx_lvds = {
370 .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
371 .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
372 .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
373 .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
374 .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
375 .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
376 .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
377 .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
378 .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
379 .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
380 .find_pll = intel_find_best_PLL,
381 };
382
383 static const intel_limit_t intel_limits_i9xx_sdvo = {
384 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
385 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
386 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
387 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
388 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
389 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
390 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
391 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
392 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
393 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
394 .find_pll = intel_find_best_PLL,
395 };
396
397 static const intel_limit_t intel_limits_i9xx_lvds = {
398 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
399 .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
400 .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
401 .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
402 .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
403 .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
404 .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
405 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
406 /* The single-channel range is 25-112Mhz, and dual-channel
407 * is 80-224Mhz. Prefer single channel as much as possible.
408 */
409 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
410 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
411 .find_pll = intel_find_best_PLL,
412 };
413
414 /* below parameter and function is for G4X Chipset Family*/
415 static const intel_limit_t intel_limits_g4x_sdvo = {
416 .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
417 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
418 .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
419 .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
420 .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
421 .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
422 .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
423 .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
424 .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
425 .p2_slow = G4X_P2_SDVO_SLOW,
426 .p2_fast = G4X_P2_SDVO_FAST
427 },
428 .find_pll = intel_g4x_find_best_PLL,
429 };
430
431 static const intel_limit_t intel_limits_g4x_hdmi = {
432 .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
433 .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
434 .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
435 .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
436 .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
437 .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
438 .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
439 .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
440 .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
441 .p2_slow = G4X_P2_HDMI_DAC_SLOW,
442 .p2_fast = G4X_P2_HDMI_DAC_FAST
443 },
444 .find_pll = intel_g4x_find_best_PLL,
445 };
446
447 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
448 .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
449 .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
450 .vco = { .min = G4X_VCO_MIN,
451 .max = G4X_VCO_MAX },
452 .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
453 .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
454 .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
455 .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
456 .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
457 .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
458 .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
459 .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
460 .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
461 .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
462 .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
463 .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
464 .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
465 .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
466 .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
467 },
468 .find_pll = intel_g4x_find_best_PLL,
469 };
470
471 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
472 .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
473 .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
474 .vco = { .min = G4X_VCO_MIN,
475 .max = G4X_VCO_MAX },
476 .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
477 .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
478 .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
479 .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
480 .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
481 .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
482 .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
483 .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
484 .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
485 .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
486 .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
487 .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
488 .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
489 .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
490 .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
491 },
492 .find_pll = intel_g4x_find_best_PLL,
493 };
494
495 static const intel_limit_t intel_limits_g4x_display_port = {
496 .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
497 .max = G4X_DOT_DISPLAY_PORT_MAX },
498 .vco = { .min = G4X_VCO_MIN,
499 .max = G4X_VCO_MAX},
500 .n = { .min = G4X_N_DISPLAY_PORT_MIN,
501 .max = G4X_N_DISPLAY_PORT_MAX },
502 .m = { .min = G4X_M_DISPLAY_PORT_MIN,
503 .max = G4X_M_DISPLAY_PORT_MAX },
504 .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
505 .max = G4X_M1_DISPLAY_PORT_MAX },
506 .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
507 .max = G4X_M2_DISPLAY_PORT_MAX },
508 .p = { .min = G4X_P_DISPLAY_PORT_MIN,
509 .max = G4X_P_DISPLAY_PORT_MAX },
510 .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
511 .max = G4X_P1_DISPLAY_PORT_MAX},
512 .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
513 .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
514 .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
515 .find_pll = intel_find_pll_g4x_dp,
516 };
517
518 static const intel_limit_t intel_limits_pineview_sdvo = {
519 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
520 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
521 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
522 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
523 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
524 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
525 .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
526 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
527 .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
528 .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
529 .find_pll = intel_find_best_PLL,
530 };
531
532 static const intel_limit_t intel_limits_pineview_lvds = {
533 .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
534 .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
535 .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
536 .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
537 .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
538 .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
539 .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
540 .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
541 /* Pineview only supports single-channel mode. */
542 .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
543 .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
544 .find_pll = intel_find_best_PLL,
545 };
546
547 static const intel_limit_t intel_limits_ironlake_dac = {
548 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
549 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
550 .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
551 .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
552 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
553 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
554 .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
555 .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
556 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
557 .p2_slow = IRONLAKE_DAC_P2_SLOW,
558 .p2_fast = IRONLAKE_DAC_P2_FAST },
559 .find_pll = intel_g4x_find_best_PLL,
560 };
561
562 static const intel_limit_t intel_limits_ironlake_single_lvds = {
563 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
564 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
565 .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
566 .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
567 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
568 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
569 .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
570 .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
571 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
572 .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
573 .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
574 .find_pll = intel_g4x_find_best_PLL,
575 };
576
577 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
578 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
579 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
580 .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
581 .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
582 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
583 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
584 .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
585 .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
586 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
587 .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
588 .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
589 .find_pll = intel_g4x_find_best_PLL,
590 };
591
592 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
593 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
594 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
595 .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
596 .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
597 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
598 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
599 .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
600 .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
601 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
602 .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
603 .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
604 .find_pll = intel_g4x_find_best_PLL,
605 };
606
607 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
608 .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
609 .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
610 .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
611 .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
612 .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
613 .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
614 .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
615 .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
616 .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
617 .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
618 .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
619 .find_pll = intel_g4x_find_best_PLL,
620 };
621
622 static const intel_limit_t intel_limits_ironlake_display_port = {
623 .dot = { .min = IRONLAKE_DOT_MIN,
624 .max = IRONLAKE_DOT_MAX },
625 .vco = { .min = IRONLAKE_VCO_MIN,
626 .max = IRONLAKE_VCO_MAX},
627 .n = { .min = IRONLAKE_DP_N_MIN,
628 .max = IRONLAKE_DP_N_MAX },
629 .m = { .min = IRONLAKE_DP_M_MIN,
630 .max = IRONLAKE_DP_M_MAX },
631 .m1 = { .min = IRONLAKE_M1_MIN,
632 .max = IRONLAKE_M1_MAX },
633 .m2 = { .min = IRONLAKE_M2_MIN,
634 .max = IRONLAKE_M2_MAX },
635 .p = { .min = IRONLAKE_DP_P_MIN,
636 .max = IRONLAKE_DP_P_MAX },
637 .p1 = { .min = IRONLAKE_DP_P1_MIN,
638 .max = IRONLAKE_DP_P1_MAX},
639 .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
640 .p2_slow = IRONLAKE_DP_P2_SLOW,
641 .p2_fast = IRONLAKE_DP_P2_FAST },
642 .find_pll = intel_find_pll_ironlake_dp,
643 };
644
645 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
646 int refclk)
647 {
648 struct drm_device *dev = crtc->dev;
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 const intel_limit_t *limit;
651
652 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
653 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
654 LVDS_CLKB_POWER_UP) {
655 /* LVDS dual channel */
656 if (refclk == 100000)
657 limit = &intel_limits_ironlake_dual_lvds_100m;
658 else
659 limit = &intel_limits_ironlake_dual_lvds;
660 } else {
661 if (refclk == 100000)
662 limit = &intel_limits_ironlake_single_lvds_100m;
663 else
664 limit = &intel_limits_ironlake_single_lvds;
665 }
666 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
667 HAS_eDP)
668 limit = &intel_limits_ironlake_display_port;
669 else
670 limit = &intel_limits_ironlake_dac;
671
672 return limit;
673 }
674
675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
676 {
677 struct drm_device *dev = crtc->dev;
678 struct drm_i915_private *dev_priv = dev->dev_private;
679 const intel_limit_t *limit;
680
681 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
682 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
683 LVDS_CLKB_POWER_UP)
684 /* LVDS with dual channel */
685 limit = &intel_limits_g4x_dual_channel_lvds;
686 else
687 /* LVDS with dual channel */
688 limit = &intel_limits_g4x_single_channel_lvds;
689 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
690 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
691 limit = &intel_limits_g4x_hdmi;
692 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
693 limit = &intel_limits_g4x_sdvo;
694 } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
695 limit = &intel_limits_g4x_display_port;
696 } else /* The option is for other outputs */
697 limit = &intel_limits_i9xx_sdvo;
698
699 return limit;
700 }
701
702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
703 {
704 struct drm_device *dev = crtc->dev;
705 const intel_limit_t *limit;
706
707 if (HAS_PCH_SPLIT(dev))
708 limit = intel_ironlake_limit(crtc, refclk);
709 else if (IS_G4X(dev)) {
710 limit = intel_g4x_limit(crtc);
711 } else if (IS_PINEVIEW(dev)) {
712 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
713 limit = &intel_limits_pineview_lvds;
714 else
715 limit = &intel_limits_pineview_sdvo;
716 } else if (!IS_GEN2(dev)) {
717 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
718 limit = &intel_limits_i9xx_lvds;
719 else
720 limit = &intel_limits_i9xx_sdvo;
721 } else {
722 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
723 limit = &intel_limits_i8xx_lvds;
724 else
725 limit = &intel_limits_i8xx_dvo;
726 }
727 return limit;
728 }
729
730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
731 static void pineview_clock(int refclk, intel_clock_t *clock)
732 {
733 clock->m = clock->m2 + 2;
734 clock->p = clock->p1 * clock->p2;
735 clock->vco = refclk * clock->m / clock->n;
736 clock->dot = clock->vco / clock->p;
737 }
738
739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
740 {
741 if (IS_PINEVIEW(dev)) {
742 pineview_clock(refclk, clock);
743 return;
744 }
745 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
746 clock->p = clock->p1 * clock->p2;
747 clock->vco = refclk * clock->m / (clock->n + 2);
748 clock->dot = clock->vco / clock->p;
749 }
750
751 /**
752 * Returns whether any output on the specified pipe is of the specified type
753 */
754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
755 {
756 struct drm_device *dev = crtc->dev;
757 struct drm_mode_config *mode_config = &dev->mode_config;
758 struct intel_encoder *encoder;
759
760 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
761 if (encoder->base.crtc == crtc && encoder->type == type)
762 return true;
763
764 return false;
765 }
766
767 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
768 /**
769 * Returns whether the given set of divisors are valid for a given refclk with
770 * the given connectors.
771 */
772
773 static bool intel_PLL_is_valid(struct drm_device *dev,
774 const intel_limit_t *limit,
775 const intel_clock_t *clock)
776 {
777 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
778 INTELPllInvalid ("p1 out of range\n");
779 if (clock->p < limit->p.min || limit->p.max < clock->p)
780 INTELPllInvalid ("p out of range\n");
781 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
782 INTELPllInvalid ("m2 out of range\n");
783 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
784 INTELPllInvalid ("m1 out of range\n");
785 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
786 INTELPllInvalid ("m1 <= m2\n");
787 if (clock->m < limit->m.min || limit->m.max < clock->m)
788 INTELPllInvalid ("m out of range\n");
789 if (clock->n < limit->n.min || limit->n.max < clock->n)
790 INTELPllInvalid ("n out of range\n");
791 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
792 INTELPllInvalid ("vco out of range\n");
793 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
794 * connector, etc., rather than just a single range.
795 */
796 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
797 INTELPllInvalid ("dot out of range\n");
798
799 return true;
800 }
801
802 static bool
803 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
804 int target, int refclk, intel_clock_t *best_clock)
805
806 {
807 struct drm_device *dev = crtc->dev;
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 intel_clock_t clock;
810 int err = target;
811
812 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
813 (I915_READ(LVDS)) != 0) {
814 /*
815 * For LVDS, if the panel is on, just rely on its current
816 * settings for dual-channel. We haven't figured out how to
817 * reliably set up different single/dual channel state, if we
818 * even can.
819 */
820 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
821 LVDS_CLKB_POWER_UP)
822 clock.p2 = limit->p2.p2_fast;
823 else
824 clock.p2 = limit->p2.p2_slow;
825 } else {
826 if (target < limit->p2.dot_limit)
827 clock.p2 = limit->p2.p2_slow;
828 else
829 clock.p2 = limit->p2.p2_fast;
830 }
831
832 memset (best_clock, 0, sizeof (*best_clock));
833
834 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
835 clock.m1++) {
836 for (clock.m2 = limit->m2.min;
837 clock.m2 <= limit->m2.max; clock.m2++) {
838 /* m1 is always 0 in Pineview */
839 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
840 break;
841 for (clock.n = limit->n.min;
842 clock.n <= limit->n.max; clock.n++) {
843 for (clock.p1 = limit->p1.min;
844 clock.p1 <= limit->p1.max; clock.p1++) {
845 int this_err;
846
847 intel_clock(dev, refclk, &clock);
848 if (!intel_PLL_is_valid(dev, limit,
849 &clock))
850 continue;
851
852 this_err = abs(clock.dot - target);
853 if (this_err < err) {
854 *best_clock = clock;
855 err = this_err;
856 }
857 }
858 }
859 }
860 }
861
862 return (err != target);
863 }
864
865 static bool
866 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
867 int target, int refclk, intel_clock_t *best_clock)
868 {
869 struct drm_device *dev = crtc->dev;
870 struct drm_i915_private *dev_priv = dev->dev_private;
871 intel_clock_t clock;
872 int max_n;
873 bool found;
874 /* approximately equals target * 0.00585 */
875 int err_most = (target >> 8) + (target >> 9);
876 found = false;
877
878 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
879 int lvds_reg;
880
881 if (HAS_PCH_SPLIT(dev))
882 lvds_reg = PCH_LVDS;
883 else
884 lvds_reg = LVDS;
885 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
886 LVDS_CLKB_POWER_UP)
887 clock.p2 = limit->p2.p2_fast;
888 else
889 clock.p2 = limit->p2.p2_slow;
890 } else {
891 if (target < limit->p2.dot_limit)
892 clock.p2 = limit->p2.p2_slow;
893 else
894 clock.p2 = limit->p2.p2_fast;
895 }
896
897 memset(best_clock, 0, sizeof(*best_clock));
898 max_n = limit->n.max;
899 /* based on hardware requirement, prefer smaller n to precision */
900 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
901 /* based on hardware requirement, prefere larger m1,m2 */
902 for (clock.m1 = limit->m1.max;
903 clock.m1 >= limit->m1.min; clock.m1--) {
904 for (clock.m2 = limit->m2.max;
905 clock.m2 >= limit->m2.min; clock.m2--) {
906 for (clock.p1 = limit->p1.max;
907 clock.p1 >= limit->p1.min; clock.p1--) {
908 int this_err;
909
910 intel_clock(dev, refclk, &clock);
911 if (!intel_PLL_is_valid(dev, limit,
912 &clock))
913 continue;
914
915 this_err = abs(clock.dot - target);
916 if (this_err < err_most) {
917 *best_clock = clock;
918 err_most = this_err;
919 max_n = clock.n;
920 found = true;
921 }
922 }
923 }
924 }
925 }
926 return found;
927 }
928
929 static bool
930 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
931 int target, int refclk, intel_clock_t *best_clock)
932 {
933 struct drm_device *dev = crtc->dev;
934 intel_clock_t clock;
935
936 if (target < 200000) {
937 clock.n = 1;
938 clock.p1 = 2;
939 clock.p2 = 10;
940 clock.m1 = 12;
941 clock.m2 = 9;
942 } else {
943 clock.n = 2;
944 clock.p1 = 1;
945 clock.p2 = 10;
946 clock.m1 = 14;
947 clock.m2 = 8;
948 }
949 intel_clock(dev, refclk, &clock);
950 memcpy(best_clock, &clock, sizeof(intel_clock_t));
951 return true;
952 }
953
954 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
955 static bool
956 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
957 int target, int refclk, intel_clock_t *best_clock)
958 {
959 intel_clock_t clock;
960 if (target < 200000) {
961 clock.p1 = 2;
962 clock.p2 = 10;
963 clock.n = 2;
964 clock.m1 = 23;
965 clock.m2 = 8;
966 } else {
967 clock.p1 = 1;
968 clock.p2 = 10;
969 clock.n = 1;
970 clock.m1 = 14;
971 clock.m2 = 2;
972 }
973 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
974 clock.p = (clock.p1 * clock.p2);
975 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
976 clock.vco = 0;
977 memcpy(best_clock, &clock, sizeof(intel_clock_t));
978 return true;
979 }
980
981 /**
982 * intel_wait_for_vblank - wait for vblank on a given pipe
983 * @dev: drm device
984 * @pipe: pipe to wait for
985 *
986 * Wait for vblank to occur on a given pipe. Needed for various bits of
987 * mode setting code.
988 */
989 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
990 {
991 struct drm_i915_private *dev_priv = dev->dev_private;
992 int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
993
994 /* Clear existing vblank status. Note this will clear any other
995 * sticky status fields as well.
996 *
997 * This races with i915_driver_irq_handler() with the result
998 * that either function could miss a vblank event. Here it is not
999 * fatal, as we will either wait upon the next vblank interrupt or
1000 * timeout. Generally speaking intel_wait_for_vblank() is only
1001 * called during modeset at which time the GPU should be idle and
1002 * should *not* be performing page flips and thus not waiting on
1003 * vblanks...
1004 * Currently, the result of us stealing a vblank from the irq
1005 * handler is that a single frame will be skipped during swapbuffers.
1006 */
1007 I915_WRITE(pipestat_reg,
1008 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1009
1010 /* Wait for vblank interrupt bit to set */
1011 if (wait_for(I915_READ(pipestat_reg) &
1012 PIPE_VBLANK_INTERRUPT_STATUS,
1013 50))
1014 DRM_DEBUG_KMS("vblank wait timed out\n");
1015 }
1016
1017 /*
1018 * intel_wait_for_pipe_off - wait for pipe to turn off
1019 * @dev: drm device
1020 * @pipe: pipe to wait for
1021 *
1022 * After disabling a pipe, we can't wait for vblank in the usual way,
1023 * spinning on the vblank interrupt status bit, since we won't actually
1024 * see an interrupt when the pipe is disabled.
1025 *
1026 * On Gen4 and above:
1027 * wait for the pipe register state bit to turn off
1028 *
1029 * Otherwise:
1030 * wait for the display line value to settle (it usually
1031 * ends up stopping at the start of the next frame).
1032 *
1033 */
1034 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1035 {
1036 struct drm_i915_private *dev_priv = dev->dev_private;
1037
1038 if (INTEL_INFO(dev)->gen >= 4) {
1039 int reg = PIPECONF(pipe);
1040
1041 /* Wait for the Pipe State to go off */
1042 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1043 100))
1044 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1045 } else {
1046 u32 last_line;
1047 int reg = PIPEDSL(pipe);
1048 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1049
1050 /* Wait for the display line to settle */
1051 do {
1052 last_line = I915_READ(reg) & DSL_LINEMASK;
1053 mdelay(5);
1054 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
1055 time_after(timeout, jiffies));
1056 if (time_after(jiffies, timeout))
1057 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1058 }
1059 }
1060
1061 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1062 {
1063 struct drm_device *dev = crtc->dev;
1064 struct drm_i915_private *dev_priv = dev->dev_private;
1065 struct drm_framebuffer *fb = crtc->fb;
1066 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1067 struct drm_i915_gem_object *obj = intel_fb->obj;
1068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1069 int plane, i;
1070 u32 fbc_ctl, fbc_ctl2;
1071
1072 if (fb->pitch == dev_priv->cfb_pitch &&
1073 obj->fence_reg == dev_priv->cfb_fence &&
1074 intel_crtc->plane == dev_priv->cfb_plane &&
1075 I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1076 return;
1077
1078 i8xx_disable_fbc(dev);
1079
1080 dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1081
1082 if (fb->pitch < dev_priv->cfb_pitch)
1083 dev_priv->cfb_pitch = fb->pitch;
1084
1085 /* FBC_CTL wants 64B units */
1086 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1087 dev_priv->cfb_fence = obj->fence_reg;
1088 dev_priv->cfb_plane = intel_crtc->plane;
1089 plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1090
1091 /* Clear old tags */
1092 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1093 I915_WRITE(FBC_TAG + (i * 4), 0);
1094
1095 /* Set it up... */
1096 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1097 if (obj->tiling_mode != I915_TILING_NONE)
1098 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1099 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1100 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1101
1102 /* enable it... */
1103 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1104 if (IS_I945GM(dev))
1105 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1106 fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1107 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1108 if (obj->tiling_mode != I915_TILING_NONE)
1109 fbc_ctl |= dev_priv->cfb_fence;
1110 I915_WRITE(FBC_CONTROL, fbc_ctl);
1111
1112 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1113 dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1114 }
1115
1116 void i8xx_disable_fbc(struct drm_device *dev)
1117 {
1118 struct drm_i915_private *dev_priv = dev->dev_private;
1119 u32 fbc_ctl;
1120
1121 /* Disable compression */
1122 fbc_ctl = I915_READ(FBC_CONTROL);
1123 if ((fbc_ctl & FBC_CTL_EN) == 0)
1124 return;
1125
1126 fbc_ctl &= ~FBC_CTL_EN;
1127 I915_WRITE(FBC_CONTROL, fbc_ctl);
1128
1129 /* Wait for compressing bit to clear */
1130 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1131 DRM_DEBUG_KMS("FBC idle timed out\n");
1132 return;
1133 }
1134
1135 DRM_DEBUG_KMS("disabled FBC\n");
1136 }
1137
1138 static bool i8xx_fbc_enabled(struct drm_device *dev)
1139 {
1140 struct drm_i915_private *dev_priv = dev->dev_private;
1141
1142 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1143 }
1144
1145 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1146 {
1147 struct drm_device *dev = crtc->dev;
1148 struct drm_i915_private *dev_priv = dev->dev_private;
1149 struct drm_framebuffer *fb = crtc->fb;
1150 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1151 struct drm_i915_gem_object *obj = intel_fb->obj;
1152 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1153 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1154 unsigned long stall_watermark = 200;
1155 u32 dpfc_ctl;
1156
1157 dpfc_ctl = I915_READ(DPFC_CONTROL);
1158 if (dpfc_ctl & DPFC_CTL_EN) {
1159 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1160 dev_priv->cfb_fence == obj->fence_reg &&
1161 dev_priv->cfb_plane == intel_crtc->plane &&
1162 dev_priv->cfb_y == crtc->y)
1163 return;
1164
1165 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1166 POSTING_READ(DPFC_CONTROL);
1167 intel_wait_for_vblank(dev, intel_crtc->pipe);
1168 }
1169
1170 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1171 dev_priv->cfb_fence = obj->fence_reg;
1172 dev_priv->cfb_plane = intel_crtc->plane;
1173 dev_priv->cfb_y = crtc->y;
1174
1175 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1176 if (obj->tiling_mode != I915_TILING_NONE) {
1177 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1178 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1179 } else {
1180 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1181 }
1182
1183 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1184 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1185 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1186 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1187
1188 /* enable it... */
1189 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1190
1191 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1192 }
1193
1194 void g4x_disable_fbc(struct drm_device *dev)
1195 {
1196 struct drm_i915_private *dev_priv = dev->dev_private;
1197 u32 dpfc_ctl;
1198
1199 /* Disable compression */
1200 dpfc_ctl = I915_READ(DPFC_CONTROL);
1201 if (dpfc_ctl & DPFC_CTL_EN) {
1202 dpfc_ctl &= ~DPFC_CTL_EN;
1203 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1204
1205 DRM_DEBUG_KMS("disabled FBC\n");
1206 }
1207 }
1208
1209 static bool g4x_fbc_enabled(struct drm_device *dev)
1210 {
1211 struct drm_i915_private *dev_priv = dev->dev_private;
1212
1213 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1214 }
1215
1216 static void sandybridge_blit_fbc_update(struct drm_device *dev)
1217 {
1218 struct drm_i915_private *dev_priv = dev->dev_private;
1219 u32 blt_ecoskpd;
1220
1221 /* Make sure blitter notifies FBC of writes */
1222 __gen6_force_wake_get(dev_priv);
1223 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1224 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1225 GEN6_BLITTER_LOCK_SHIFT;
1226 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1227 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1228 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1229 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1230 GEN6_BLITTER_LOCK_SHIFT);
1231 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1232 POSTING_READ(GEN6_BLITTER_ECOSKPD);
1233 __gen6_force_wake_put(dev_priv);
1234 }
1235
1236 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1237 {
1238 struct drm_device *dev = crtc->dev;
1239 struct drm_i915_private *dev_priv = dev->dev_private;
1240 struct drm_framebuffer *fb = crtc->fb;
1241 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1242 struct drm_i915_gem_object *obj = intel_fb->obj;
1243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1244 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1245 unsigned long stall_watermark = 200;
1246 u32 dpfc_ctl;
1247
1248 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1249 if (dpfc_ctl & DPFC_CTL_EN) {
1250 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1251 dev_priv->cfb_fence == obj->fence_reg &&
1252 dev_priv->cfb_plane == intel_crtc->plane &&
1253 dev_priv->cfb_offset == obj->gtt_offset &&
1254 dev_priv->cfb_y == crtc->y)
1255 return;
1256
1257 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1258 POSTING_READ(ILK_DPFC_CONTROL);
1259 intel_wait_for_vblank(dev, intel_crtc->pipe);
1260 }
1261
1262 dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1263 dev_priv->cfb_fence = obj->fence_reg;
1264 dev_priv->cfb_plane = intel_crtc->plane;
1265 dev_priv->cfb_offset = obj->gtt_offset;
1266 dev_priv->cfb_y = crtc->y;
1267
1268 dpfc_ctl &= DPFC_RESERVED;
1269 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1270 if (obj->tiling_mode != I915_TILING_NONE) {
1271 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1272 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1273 } else {
1274 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1275 }
1276
1277 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1278 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1279 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1280 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1281 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
1282 /* enable it... */
1283 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1284
1285 if (IS_GEN6(dev)) {
1286 I915_WRITE(SNB_DPFC_CTL_SA,
1287 SNB_CPU_FENCE_ENABLE | dev_priv->cfb_fence);
1288 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
1289 sandybridge_blit_fbc_update(dev);
1290 }
1291
1292 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1293 }
1294
1295 void ironlake_disable_fbc(struct drm_device *dev)
1296 {
1297 struct drm_i915_private *dev_priv = dev->dev_private;
1298 u32 dpfc_ctl;
1299
1300 /* Disable compression */
1301 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1302 if (dpfc_ctl & DPFC_CTL_EN) {
1303 dpfc_ctl &= ~DPFC_CTL_EN;
1304 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1305
1306 DRM_DEBUG_KMS("disabled FBC\n");
1307 }
1308 }
1309
1310 static bool ironlake_fbc_enabled(struct drm_device *dev)
1311 {
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313
1314 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1315 }
1316
1317 bool intel_fbc_enabled(struct drm_device *dev)
1318 {
1319 struct drm_i915_private *dev_priv = dev->dev_private;
1320
1321 if (!dev_priv->display.fbc_enabled)
1322 return false;
1323
1324 return dev_priv->display.fbc_enabled(dev);
1325 }
1326
1327 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1328 {
1329 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1330
1331 if (!dev_priv->display.enable_fbc)
1332 return;
1333
1334 dev_priv->display.enable_fbc(crtc, interval);
1335 }
1336
1337 void intel_disable_fbc(struct drm_device *dev)
1338 {
1339 struct drm_i915_private *dev_priv = dev->dev_private;
1340
1341 if (!dev_priv->display.disable_fbc)
1342 return;
1343
1344 dev_priv->display.disable_fbc(dev);
1345 }
1346
1347 /**
1348 * intel_update_fbc - enable/disable FBC as needed
1349 * @dev: the drm_device
1350 *
1351 * Set up the framebuffer compression hardware at mode set time. We
1352 * enable it if possible:
1353 * - plane A only (on pre-965)
1354 * - no pixel mulitply/line duplication
1355 * - no alpha buffer discard
1356 * - no dual wide
1357 * - framebuffer <= 2048 in width, 1536 in height
1358 *
1359 * We can't assume that any compression will take place (worst case),
1360 * so the compressed buffer has to be the same size as the uncompressed
1361 * one. It also must reside (along with the line length buffer) in
1362 * stolen memory.
1363 *
1364 * We need to enable/disable FBC on a global basis.
1365 */
1366 static void intel_update_fbc(struct drm_device *dev)
1367 {
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 struct drm_crtc *crtc = NULL, *tmp_crtc;
1370 struct intel_crtc *intel_crtc;
1371 struct drm_framebuffer *fb;
1372 struct intel_framebuffer *intel_fb;
1373 struct drm_i915_gem_object *obj;
1374
1375 DRM_DEBUG_KMS("\n");
1376
1377 if (!i915_powersave)
1378 return;
1379
1380 if (!I915_HAS_FBC(dev))
1381 return;
1382
1383 /*
1384 * If FBC is already on, we just have to verify that we can
1385 * keep it that way...
1386 * Need to disable if:
1387 * - more than one pipe is active
1388 * - changing FBC params (stride, fence, mode)
1389 * - new fb is too large to fit in compressed buffer
1390 * - going to an unsupported config (interlace, pixel multiply, etc.)
1391 */
1392 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1393 if (tmp_crtc->enabled) {
1394 if (crtc) {
1395 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1396 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1397 goto out_disable;
1398 }
1399 crtc = tmp_crtc;
1400 }
1401 }
1402
1403 if (!crtc || crtc->fb == NULL) {
1404 DRM_DEBUG_KMS("no output, disabling\n");
1405 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1406 goto out_disable;
1407 }
1408
1409 intel_crtc = to_intel_crtc(crtc);
1410 fb = crtc->fb;
1411 intel_fb = to_intel_framebuffer(fb);
1412 obj = intel_fb->obj;
1413
1414 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
1415 DRM_DEBUG_KMS("framebuffer too large, disabling "
1416 "compression\n");
1417 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1418 goto out_disable;
1419 }
1420 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1421 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1422 DRM_DEBUG_KMS("mode incompatible with compression, "
1423 "disabling\n");
1424 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1425 goto out_disable;
1426 }
1427 if ((crtc->mode.hdisplay > 2048) ||
1428 (crtc->mode.vdisplay > 1536)) {
1429 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1430 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1431 goto out_disable;
1432 }
1433 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1434 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1435 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1436 goto out_disable;
1437 }
1438 if (obj->tiling_mode != I915_TILING_X) {
1439 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1440 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1441 goto out_disable;
1442 }
1443
1444 /* If the kernel debugger is active, always disable compression */
1445 if (in_dbg_master())
1446 goto out_disable;
1447
1448 intel_enable_fbc(crtc, 500);
1449 return;
1450
1451 out_disable:
1452 /* Multiple disables should be harmless */
1453 if (intel_fbc_enabled(dev)) {
1454 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1455 intel_disable_fbc(dev);
1456 }
1457 }
1458
1459 int
1460 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1461 struct drm_i915_gem_object *obj,
1462 struct intel_ring_buffer *pipelined)
1463 {
1464 u32 alignment;
1465 int ret;
1466
1467 switch (obj->tiling_mode) {
1468 case I915_TILING_NONE:
1469 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1470 alignment = 128 * 1024;
1471 else if (INTEL_INFO(dev)->gen >= 4)
1472 alignment = 4 * 1024;
1473 else
1474 alignment = 64 * 1024;
1475 break;
1476 case I915_TILING_X:
1477 /* pin() will align the object as required by fence */
1478 alignment = 0;
1479 break;
1480 case I915_TILING_Y:
1481 /* FIXME: Is this true? */
1482 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1483 return -EINVAL;
1484 default:
1485 BUG();
1486 }
1487
1488 ret = i915_gem_object_pin(obj, alignment, true);
1489 if (ret)
1490 return ret;
1491
1492 ret = i915_gem_object_set_to_display_plane(obj, pipelined);
1493 if (ret)
1494 goto err_unpin;
1495
1496 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1497 * fence, whereas 965+ only requires a fence if using
1498 * framebuffer compression. For simplicity, we always install
1499 * a fence as the cost is not that onerous.
1500 */
1501 if (obj->tiling_mode != I915_TILING_NONE) {
1502 ret = i915_gem_object_get_fence(obj, pipelined, false);
1503 if (ret)
1504 goto err_unpin;
1505 }
1506
1507 return 0;
1508
1509 err_unpin:
1510 i915_gem_object_unpin(obj);
1511 return ret;
1512 }
1513
1514 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1515 static int
1516 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1517 int x, int y, enum mode_set_atomic state)
1518 {
1519 struct drm_device *dev = crtc->dev;
1520 struct drm_i915_private *dev_priv = dev->dev_private;
1521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1522 struct intel_framebuffer *intel_fb;
1523 struct drm_i915_gem_object *obj;
1524 int plane = intel_crtc->plane;
1525 unsigned long Start, Offset;
1526 u32 dspcntr;
1527 u32 reg;
1528
1529 switch (plane) {
1530 case 0:
1531 case 1:
1532 break;
1533 default:
1534 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1535 return -EINVAL;
1536 }
1537
1538 intel_fb = to_intel_framebuffer(fb);
1539 obj = intel_fb->obj;
1540
1541 reg = DSPCNTR(plane);
1542 dspcntr = I915_READ(reg);
1543 /* Mask out pixel format bits in case we change it */
1544 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1545 switch (fb->bits_per_pixel) {
1546 case 8:
1547 dspcntr |= DISPPLANE_8BPP;
1548 break;
1549 case 16:
1550 if (fb->depth == 15)
1551 dspcntr |= DISPPLANE_15_16BPP;
1552 else
1553 dspcntr |= DISPPLANE_16BPP;
1554 break;
1555 case 24:
1556 case 32:
1557 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1558 break;
1559 default:
1560 DRM_ERROR("Unknown color depth\n");
1561 return -EINVAL;
1562 }
1563 if (INTEL_INFO(dev)->gen >= 4) {
1564 if (obj->tiling_mode != I915_TILING_NONE)
1565 dspcntr |= DISPPLANE_TILED;
1566 else
1567 dspcntr &= ~DISPPLANE_TILED;
1568 }
1569
1570 if (HAS_PCH_SPLIT(dev))
1571 /* must disable */
1572 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1573
1574 I915_WRITE(reg, dspcntr);
1575
1576 Start = obj->gtt_offset;
1577 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1578
1579 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1580 Start, Offset, x, y, fb->pitch);
1581 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1582 if (INTEL_INFO(dev)->gen >= 4) {
1583 I915_WRITE(DSPSURF(plane), Start);
1584 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1585 I915_WRITE(DSPADDR(plane), Offset);
1586 } else
1587 I915_WRITE(DSPADDR(plane), Start + Offset);
1588 POSTING_READ(reg);
1589
1590 intel_update_fbc(dev);
1591 intel_increase_pllclock(crtc);
1592
1593 return 0;
1594 }
1595
1596 static int
1597 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1598 struct drm_framebuffer *old_fb)
1599 {
1600 struct drm_device *dev = crtc->dev;
1601 struct drm_i915_master_private *master_priv;
1602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1603 int ret;
1604
1605 /* no fb bound */
1606 if (!crtc->fb) {
1607 DRM_DEBUG_KMS("No FB bound\n");
1608 return 0;
1609 }
1610
1611 switch (intel_crtc->plane) {
1612 case 0:
1613 case 1:
1614 break;
1615 default:
1616 return -EINVAL;
1617 }
1618
1619 mutex_lock(&dev->struct_mutex);
1620 ret = intel_pin_and_fence_fb_obj(dev,
1621 to_intel_framebuffer(crtc->fb)->obj,
1622 NULL);
1623 if (ret != 0) {
1624 mutex_unlock(&dev->struct_mutex);
1625 return ret;
1626 }
1627
1628 if (old_fb) {
1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
1631
1632 wait_event(dev_priv->pending_flip_queue,
1633 atomic_read(&obj->pending_flip) == 0);
1634
1635 /* Big Hammer, we also need to ensure that any pending
1636 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1637 * current scanout is retired before unpinning the old
1638 * framebuffer.
1639 */
1640 ret = i915_gem_object_flush_gpu(obj, false);
1641 if (ret) {
1642 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1643 mutex_unlock(&dev->struct_mutex);
1644 return ret;
1645 }
1646 }
1647
1648 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
1649 LEAVE_ATOMIC_MODE_SET);
1650 if (ret) {
1651 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
1652 mutex_unlock(&dev->struct_mutex);
1653 return ret;
1654 }
1655
1656 if (old_fb) {
1657 intel_wait_for_vblank(dev, intel_crtc->pipe);
1658 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
1659 }
1660
1661 mutex_unlock(&dev->struct_mutex);
1662
1663 if (!dev->primary->master)
1664 return 0;
1665
1666 master_priv = dev->primary->master->driver_priv;
1667 if (!master_priv->sarea_priv)
1668 return 0;
1669
1670 if (intel_crtc->pipe) {
1671 master_priv->sarea_priv->pipeB_x = x;
1672 master_priv->sarea_priv->pipeB_y = y;
1673 } else {
1674 master_priv->sarea_priv->pipeA_x = x;
1675 master_priv->sarea_priv->pipeA_y = y;
1676 }
1677
1678 return 0;
1679 }
1680
1681 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1682 {
1683 struct drm_device *dev = crtc->dev;
1684 struct drm_i915_private *dev_priv = dev->dev_private;
1685 u32 dpa_ctl;
1686
1687 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1688 dpa_ctl = I915_READ(DP_A);
1689 dpa_ctl &= ~DP_PLL_FREQ_MASK;
1690
1691 if (clock < 200000) {
1692 u32 temp;
1693 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1694 /* workaround for 160Mhz:
1695 1) program 0x4600c bits 15:0 = 0x8124
1696 2) program 0x46010 bit 0 = 1
1697 3) program 0x46034 bit 24 = 1
1698 4) program 0x64000 bit 14 = 1
1699 */
1700 temp = I915_READ(0x4600c);
1701 temp &= 0xffff0000;
1702 I915_WRITE(0x4600c, temp | 0x8124);
1703
1704 temp = I915_READ(0x46010);
1705 I915_WRITE(0x46010, temp | 1);
1706
1707 temp = I915_READ(0x46034);
1708 I915_WRITE(0x46034, temp | (1 << 24));
1709 } else {
1710 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1711 }
1712 I915_WRITE(DP_A, dpa_ctl);
1713
1714 POSTING_READ(DP_A);
1715 udelay(500);
1716 }
1717
1718 static void intel_fdi_normal_train(struct drm_crtc *crtc)
1719 {
1720 struct drm_device *dev = crtc->dev;
1721 struct drm_i915_private *dev_priv = dev->dev_private;
1722 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1723 int pipe = intel_crtc->pipe;
1724 u32 reg, temp;
1725
1726 /* enable normal train */
1727 reg = FDI_TX_CTL(pipe);
1728 temp = I915_READ(reg);
1729 temp &= ~FDI_LINK_TRAIN_NONE;
1730 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
1731 I915_WRITE(reg, temp);
1732
1733 reg = FDI_RX_CTL(pipe);
1734 temp = I915_READ(reg);
1735 if (HAS_PCH_CPT(dev)) {
1736 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1737 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
1738 } else {
1739 temp &= ~FDI_LINK_TRAIN_NONE;
1740 temp |= FDI_LINK_TRAIN_NONE;
1741 }
1742 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
1743
1744 /* wait one idle pattern time */
1745 POSTING_READ(reg);
1746 udelay(1000);
1747 }
1748
1749 /* The FDI link training functions for ILK/Ibexpeak. */
1750 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1751 {
1752 struct drm_device *dev = crtc->dev;
1753 struct drm_i915_private *dev_priv = dev->dev_private;
1754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1755 int pipe = intel_crtc->pipe;
1756 u32 reg, temp, tries;
1757
1758 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1759 for train result */
1760 reg = FDI_RX_IMR(pipe);
1761 temp = I915_READ(reg);
1762 temp &= ~FDI_RX_SYMBOL_LOCK;
1763 temp &= ~FDI_RX_BIT_LOCK;
1764 I915_WRITE(reg, temp);
1765 I915_READ(reg);
1766 udelay(150);
1767
1768 /* enable CPU FDI TX and PCH FDI RX */
1769 reg = FDI_TX_CTL(pipe);
1770 temp = I915_READ(reg);
1771 temp &= ~(7 << 19);
1772 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1773 temp &= ~FDI_LINK_TRAIN_NONE;
1774 temp |= FDI_LINK_TRAIN_PATTERN_1;
1775 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1776
1777 reg = FDI_RX_CTL(pipe);
1778 temp = I915_READ(reg);
1779 temp &= ~FDI_LINK_TRAIN_NONE;
1780 temp |= FDI_LINK_TRAIN_PATTERN_1;
1781 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1782
1783 POSTING_READ(reg);
1784 udelay(150);
1785
1786 /* Ironlake workaround, enable clock pointer after FDI enable*/
1787 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_ENABLE);
1788
1789 reg = FDI_RX_IIR(pipe);
1790 for (tries = 0; tries < 5; tries++) {
1791 temp = I915_READ(reg);
1792 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1793
1794 if ((temp & FDI_RX_BIT_LOCK)) {
1795 DRM_DEBUG_KMS("FDI train 1 done.\n");
1796 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1797 break;
1798 }
1799 }
1800 if (tries == 5)
1801 DRM_ERROR("FDI train 1 fail!\n");
1802
1803 /* Train 2 */
1804 reg = FDI_TX_CTL(pipe);
1805 temp = I915_READ(reg);
1806 temp &= ~FDI_LINK_TRAIN_NONE;
1807 temp |= FDI_LINK_TRAIN_PATTERN_2;
1808 I915_WRITE(reg, temp);
1809
1810 reg = FDI_RX_CTL(pipe);
1811 temp = I915_READ(reg);
1812 temp &= ~FDI_LINK_TRAIN_NONE;
1813 temp |= FDI_LINK_TRAIN_PATTERN_2;
1814 I915_WRITE(reg, temp);
1815
1816 POSTING_READ(reg);
1817 udelay(150);
1818
1819 reg = FDI_RX_IIR(pipe);
1820 for (tries = 0; tries < 5; tries++) {
1821 temp = I915_READ(reg);
1822 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1823
1824 if (temp & FDI_RX_SYMBOL_LOCK) {
1825 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1826 DRM_DEBUG_KMS("FDI train 2 done.\n");
1827 break;
1828 }
1829 }
1830 if (tries == 5)
1831 DRM_ERROR("FDI train 2 fail!\n");
1832
1833 DRM_DEBUG_KMS("FDI train done\n");
1834
1835 }
1836
1837 static const int const snb_b_fdi_train_param [] = {
1838 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1839 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1840 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1841 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1842 };
1843
1844 /* The FDI link training functions for SNB/Cougarpoint. */
1845 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1846 {
1847 struct drm_device *dev = crtc->dev;
1848 struct drm_i915_private *dev_priv = dev->dev_private;
1849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1850 int pipe = intel_crtc->pipe;
1851 u32 reg, temp, i;
1852
1853 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1854 for train result */
1855 reg = FDI_RX_IMR(pipe);
1856 temp = I915_READ(reg);
1857 temp &= ~FDI_RX_SYMBOL_LOCK;
1858 temp &= ~FDI_RX_BIT_LOCK;
1859 I915_WRITE(reg, temp);
1860
1861 POSTING_READ(reg);
1862 udelay(150);
1863
1864 /* enable CPU FDI TX and PCH FDI RX */
1865 reg = FDI_TX_CTL(pipe);
1866 temp = I915_READ(reg);
1867 temp &= ~(7 << 19);
1868 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1869 temp &= ~FDI_LINK_TRAIN_NONE;
1870 temp |= FDI_LINK_TRAIN_PATTERN_1;
1871 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1872 /* SNB-B */
1873 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1874 I915_WRITE(reg, temp | FDI_TX_ENABLE);
1875
1876 reg = FDI_RX_CTL(pipe);
1877 temp = I915_READ(reg);
1878 if (HAS_PCH_CPT(dev)) {
1879 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1880 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1881 } else {
1882 temp &= ~FDI_LINK_TRAIN_NONE;
1883 temp |= FDI_LINK_TRAIN_PATTERN_1;
1884 }
1885 I915_WRITE(reg, temp | FDI_RX_ENABLE);
1886
1887 POSTING_READ(reg);
1888 udelay(150);
1889
1890 for (i = 0; i < 4; i++ ) {
1891 reg = FDI_TX_CTL(pipe);
1892 temp = I915_READ(reg);
1893 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1894 temp |= snb_b_fdi_train_param[i];
1895 I915_WRITE(reg, temp);
1896
1897 POSTING_READ(reg);
1898 udelay(500);
1899
1900 reg = FDI_RX_IIR(pipe);
1901 temp = I915_READ(reg);
1902 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1903
1904 if (temp & FDI_RX_BIT_LOCK) {
1905 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1906 DRM_DEBUG_KMS("FDI train 1 done.\n");
1907 break;
1908 }
1909 }
1910 if (i == 4)
1911 DRM_ERROR("FDI train 1 fail!\n");
1912
1913 /* Train 2 */
1914 reg = FDI_TX_CTL(pipe);
1915 temp = I915_READ(reg);
1916 temp &= ~FDI_LINK_TRAIN_NONE;
1917 temp |= FDI_LINK_TRAIN_PATTERN_2;
1918 if (IS_GEN6(dev)) {
1919 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1920 /* SNB-B */
1921 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1922 }
1923 I915_WRITE(reg, temp);
1924
1925 reg = FDI_RX_CTL(pipe);
1926 temp = I915_READ(reg);
1927 if (HAS_PCH_CPT(dev)) {
1928 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1929 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1930 } else {
1931 temp &= ~FDI_LINK_TRAIN_NONE;
1932 temp |= FDI_LINK_TRAIN_PATTERN_2;
1933 }
1934 I915_WRITE(reg, temp);
1935
1936 POSTING_READ(reg);
1937 udelay(150);
1938
1939 for (i = 0; i < 4; i++ ) {
1940 reg = FDI_TX_CTL(pipe);
1941 temp = I915_READ(reg);
1942 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1943 temp |= snb_b_fdi_train_param[i];
1944 I915_WRITE(reg, temp);
1945
1946 POSTING_READ(reg);
1947 udelay(500);
1948
1949 reg = FDI_RX_IIR(pipe);
1950 temp = I915_READ(reg);
1951 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1952
1953 if (temp & FDI_RX_SYMBOL_LOCK) {
1954 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1955 DRM_DEBUG_KMS("FDI train 2 done.\n");
1956 break;
1957 }
1958 }
1959 if (i == 4)
1960 DRM_ERROR("FDI train 2 fail!\n");
1961
1962 DRM_DEBUG_KMS("FDI train done.\n");
1963 }
1964
1965 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1966 {
1967 struct drm_device *dev = crtc->dev;
1968 struct drm_i915_private *dev_priv = dev->dev_private;
1969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1970 int pipe = intel_crtc->pipe;
1971 u32 reg, temp;
1972
1973 /* Write the TU size bits so error detection works */
1974 I915_WRITE(FDI_RX_TUSIZE1(pipe),
1975 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1976
1977 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1978 reg = FDI_RX_CTL(pipe);
1979 temp = I915_READ(reg);
1980 temp &= ~((0x7 << 19) | (0x7 << 16));
1981 temp |= (intel_crtc->fdi_lanes - 1) << 19;
1982 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1983 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1984
1985 POSTING_READ(reg);
1986 udelay(200);
1987
1988 /* Switch from Rawclk to PCDclk */
1989 temp = I915_READ(reg);
1990 I915_WRITE(reg, temp | FDI_PCDCLK);
1991
1992 POSTING_READ(reg);
1993 udelay(200);
1994
1995 /* Enable CPU FDI TX PLL, always on for Ironlake */
1996 reg = FDI_TX_CTL(pipe);
1997 temp = I915_READ(reg);
1998 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1999 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2000
2001 POSTING_READ(reg);
2002 udelay(100);
2003 }
2004 }
2005
2006 static void intel_flush_display_plane(struct drm_device *dev,
2007 int plane)
2008 {
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 u32 reg = DSPADDR(plane);
2011 I915_WRITE(reg, I915_READ(reg));
2012 }
2013
2014 /*
2015 * When we disable a pipe, we need to clear any pending scanline wait events
2016 * to avoid hanging the ring, which we assume we are waiting on.
2017 */
2018 static void intel_clear_scanline_wait(struct drm_device *dev)
2019 {
2020 struct drm_i915_private *dev_priv = dev->dev_private;
2021 struct intel_ring_buffer *ring;
2022 u32 tmp;
2023
2024 if (IS_GEN2(dev))
2025 /* Can't break the hang on i8xx */
2026 return;
2027
2028 ring = LP_RING(dev_priv);
2029 tmp = I915_READ_CTL(ring);
2030 if (tmp & RING_WAIT)
2031 I915_WRITE_CTL(ring, tmp);
2032 }
2033
2034 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2035 {
2036 struct drm_i915_gem_object *obj;
2037 struct drm_i915_private *dev_priv;
2038
2039 if (crtc->fb == NULL)
2040 return;
2041
2042 obj = to_intel_framebuffer(crtc->fb)->obj;
2043 dev_priv = crtc->dev->dev_private;
2044 wait_event(dev_priv->pending_flip_queue,
2045 atomic_read(&obj->pending_flip) == 0);
2046 }
2047
2048 static void ironlake_crtc_enable(struct drm_crtc *crtc)
2049 {
2050 struct drm_device *dev = crtc->dev;
2051 struct drm_i915_private *dev_priv = dev->dev_private;
2052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2053 int pipe = intel_crtc->pipe;
2054 int plane = intel_crtc->plane;
2055 u32 reg, temp;
2056
2057 if (intel_crtc->active)
2058 return;
2059
2060 intel_crtc->active = true;
2061 intel_update_watermarks(dev);
2062
2063 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2064 temp = I915_READ(PCH_LVDS);
2065 if ((temp & LVDS_PORT_EN) == 0)
2066 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2067 }
2068
2069 ironlake_fdi_enable(crtc);
2070
2071 /* Enable panel fitting for LVDS */
2072 if (dev_priv->pch_pf_size &&
2073 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
2074 /* Force use of hard-coded filter coefficients
2075 * as some pre-programmed values are broken,
2076 * e.g. x201.
2077 */
2078 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
2079 PF_ENABLE | PF_FILTER_MED_3x3);
2080 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
2081 dev_priv->pch_pf_pos);
2082 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
2083 dev_priv->pch_pf_size);
2084 }
2085
2086 /* Enable CPU pipe */
2087 reg = PIPECONF(pipe);
2088 temp = I915_READ(reg);
2089 if ((temp & PIPECONF_ENABLE) == 0) {
2090 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2091 POSTING_READ(reg);
2092 intel_wait_for_vblank(dev, intel_crtc->pipe);
2093 }
2094
2095 /* configure and enable CPU plane */
2096 reg = DSPCNTR(plane);
2097 temp = I915_READ(reg);
2098 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2099 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2100 intel_flush_display_plane(dev, plane);
2101 }
2102
2103 /* For PCH output, training FDI link */
2104 if (IS_GEN6(dev))
2105 gen6_fdi_link_train(crtc);
2106 else
2107 ironlake_fdi_link_train(crtc);
2108
2109 /* enable PCH DPLL */
2110 reg = PCH_DPLL(pipe);
2111 temp = I915_READ(reg);
2112 if ((temp & DPLL_VCO_ENABLE) == 0) {
2113 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2114 POSTING_READ(reg);
2115 udelay(200);
2116 }
2117
2118 if (HAS_PCH_CPT(dev)) {
2119 /* Be sure PCH DPLL SEL is set */
2120 temp = I915_READ(PCH_DPLL_SEL);
2121 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
2122 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2123 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2124 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2125 I915_WRITE(PCH_DPLL_SEL, temp);
2126 }
2127
2128 /* set transcoder timing */
2129 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2130 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2131 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
2132
2133 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2134 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2135 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
2136
2137 intel_fdi_normal_train(crtc);
2138
2139 /* For PCH DP, enable TRANS_DP_CTL */
2140 if (HAS_PCH_CPT(dev) &&
2141 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2142 reg = TRANS_DP_CTL(pipe);
2143 temp = I915_READ(reg);
2144 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2145 TRANS_DP_SYNC_MASK |
2146 TRANS_DP_BPC_MASK);
2147 temp |= (TRANS_DP_OUTPUT_ENABLE |
2148 TRANS_DP_ENH_FRAMING);
2149 temp |= TRANS_DP_8BPC;
2150
2151 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2152 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2153 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2154 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2155
2156 switch (intel_trans_dp_port_sel(crtc)) {
2157 case PCH_DP_B:
2158 temp |= TRANS_DP_PORT_SEL_B;
2159 break;
2160 case PCH_DP_C:
2161 temp |= TRANS_DP_PORT_SEL_C;
2162 break;
2163 case PCH_DP_D:
2164 temp |= TRANS_DP_PORT_SEL_D;
2165 break;
2166 default:
2167 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2168 temp |= TRANS_DP_PORT_SEL_B;
2169 break;
2170 }
2171
2172 I915_WRITE(reg, temp);
2173 }
2174
2175 /* enable PCH transcoder */
2176 reg = TRANSCONF(pipe);
2177 temp = I915_READ(reg);
2178 /*
2179 * make the BPC in transcoder be consistent with
2180 * that in pipeconf reg.
2181 */
2182 temp &= ~PIPE_BPC_MASK;
2183 temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2184 I915_WRITE(reg, temp | TRANS_ENABLE);
2185 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2186 DRM_ERROR("failed to enable transcoder %d\n", pipe);
2187
2188 intel_crtc_load_lut(crtc);
2189 intel_update_fbc(dev);
2190 intel_crtc_update_cursor(crtc, true);
2191 }
2192
2193 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2194 {
2195 struct drm_device *dev = crtc->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
2197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2198 int pipe = intel_crtc->pipe;
2199 int plane = intel_crtc->plane;
2200 u32 reg, temp;
2201
2202 if (!intel_crtc->active)
2203 return;
2204
2205 intel_crtc_wait_for_pending_flips(crtc);
2206 drm_vblank_off(dev, pipe);
2207 intel_crtc_update_cursor(crtc, false);
2208
2209 /* Disable display plane */
2210 reg = DSPCNTR(plane);
2211 temp = I915_READ(reg);
2212 if (temp & DISPLAY_PLANE_ENABLE) {
2213 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2214 intel_flush_display_plane(dev, plane);
2215 }
2216
2217 if (dev_priv->cfb_plane == plane &&
2218 dev_priv->display.disable_fbc)
2219 dev_priv->display.disable_fbc(dev);
2220
2221 /* disable cpu pipe, disable after all planes disabled */
2222 reg = PIPECONF(pipe);
2223 temp = I915_READ(reg);
2224 if (temp & PIPECONF_ENABLE) {
2225 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2226 POSTING_READ(reg);
2227 /* wait for cpu pipe off, pipe state */
2228 intel_wait_for_pipe_off(dev, intel_crtc->pipe);
2229 }
2230
2231 /* Disable PF */
2232 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2233 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2234
2235 /* disable CPU FDI tx and PCH FDI rx */
2236 reg = FDI_TX_CTL(pipe);
2237 temp = I915_READ(reg);
2238 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2239 POSTING_READ(reg);
2240
2241 reg = FDI_RX_CTL(pipe);
2242 temp = I915_READ(reg);
2243 temp &= ~(0x7 << 16);
2244 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2245 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2246
2247 POSTING_READ(reg);
2248 udelay(100);
2249
2250 /* Ironlake workaround, disable clock pointer after downing FDI */
2251 if (HAS_PCH_IBX(dev))
2252 I915_WRITE(FDI_RX_CHICKEN(pipe),
2253 I915_READ(FDI_RX_CHICKEN(pipe) &
2254 ~FDI_RX_PHASE_SYNC_POINTER_ENABLE));
2255
2256 /* still set train pattern 1 */
2257 reg = FDI_TX_CTL(pipe);
2258 temp = I915_READ(reg);
2259 temp &= ~FDI_LINK_TRAIN_NONE;
2260 temp |= FDI_LINK_TRAIN_PATTERN_1;
2261 I915_WRITE(reg, temp);
2262
2263 reg = FDI_RX_CTL(pipe);
2264 temp = I915_READ(reg);
2265 if (HAS_PCH_CPT(dev)) {
2266 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2267 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2268 } else {
2269 temp &= ~FDI_LINK_TRAIN_NONE;
2270 temp |= FDI_LINK_TRAIN_PATTERN_1;
2271 }
2272 /* BPC in FDI rx is consistent with that in PIPECONF */
2273 temp &= ~(0x07 << 16);
2274 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2275 I915_WRITE(reg, temp);
2276
2277 POSTING_READ(reg);
2278 udelay(100);
2279
2280 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2281 temp = I915_READ(PCH_LVDS);
2282 if (temp & LVDS_PORT_EN) {
2283 I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2284 POSTING_READ(PCH_LVDS);
2285 udelay(100);
2286 }
2287 }
2288
2289 /* disable PCH transcoder */
2290 reg = TRANSCONF(plane);
2291 temp = I915_READ(reg);
2292 if (temp & TRANS_ENABLE) {
2293 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2294 /* wait for PCH transcoder off, transcoder state */
2295 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2296 DRM_ERROR("failed to disable transcoder\n");
2297 }
2298
2299 if (HAS_PCH_CPT(dev)) {
2300 /* disable TRANS_DP_CTL */
2301 reg = TRANS_DP_CTL(pipe);
2302 temp = I915_READ(reg);
2303 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2304 I915_WRITE(reg, temp);
2305
2306 /* disable DPLL_SEL */
2307 temp = I915_READ(PCH_DPLL_SEL);
2308 if (pipe == 0)
2309 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2310 else
2311 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2312 I915_WRITE(PCH_DPLL_SEL, temp);
2313 }
2314
2315 /* disable PCH DPLL */
2316 reg = PCH_DPLL(pipe);
2317 temp = I915_READ(reg);
2318 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2319
2320 /* Switch from PCDclk to Rawclk */
2321 reg = FDI_RX_CTL(pipe);
2322 temp = I915_READ(reg);
2323 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2324
2325 /* Disable CPU FDI TX PLL */
2326 reg = FDI_TX_CTL(pipe);
2327 temp = I915_READ(reg);
2328 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2329
2330 POSTING_READ(reg);
2331 udelay(100);
2332
2333 reg = FDI_RX_CTL(pipe);
2334 temp = I915_READ(reg);
2335 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2336
2337 /* Wait for the clocks to turn off. */
2338 POSTING_READ(reg);
2339 udelay(100);
2340
2341 intel_crtc->active = false;
2342 intel_update_watermarks(dev);
2343 intel_update_fbc(dev);
2344 intel_clear_scanline_wait(dev);
2345 }
2346
2347 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2348 {
2349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2350 int pipe = intel_crtc->pipe;
2351 int plane = intel_crtc->plane;
2352
2353 /* XXX: When our outputs are all unaware of DPMS modes other than off
2354 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2355 */
2356 switch (mode) {
2357 case DRM_MODE_DPMS_ON:
2358 case DRM_MODE_DPMS_STANDBY:
2359 case DRM_MODE_DPMS_SUSPEND:
2360 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2361 ironlake_crtc_enable(crtc);
2362 break;
2363
2364 case DRM_MODE_DPMS_OFF:
2365 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2366 ironlake_crtc_disable(crtc);
2367 break;
2368 }
2369 }
2370
2371 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2372 {
2373 if (!enable && intel_crtc->overlay) {
2374 struct drm_device *dev = intel_crtc->base.dev;
2375
2376 mutex_lock(&dev->struct_mutex);
2377 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2378 mutex_unlock(&dev->struct_mutex);
2379 }
2380
2381 /* Let userspace switch the overlay on again. In most cases userspace
2382 * has to recompute where to put it anyway.
2383 */
2384 }
2385
2386 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2387 {
2388 struct drm_device *dev = crtc->dev;
2389 struct drm_i915_private *dev_priv = dev->dev_private;
2390 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2391 int pipe = intel_crtc->pipe;
2392 int plane = intel_crtc->plane;
2393 u32 reg, temp;
2394
2395 if (intel_crtc->active)
2396 return;
2397
2398 intel_crtc->active = true;
2399 intel_update_watermarks(dev);
2400
2401 /* Enable the DPLL */
2402 reg = DPLL(pipe);
2403 temp = I915_READ(reg);
2404 if ((temp & DPLL_VCO_ENABLE) == 0) {
2405 I915_WRITE(reg, temp);
2406
2407 /* Wait for the clocks to stabilize. */
2408 POSTING_READ(reg);
2409 udelay(150);
2410
2411 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2412
2413 /* Wait for the clocks to stabilize. */
2414 POSTING_READ(reg);
2415 udelay(150);
2416
2417 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2418
2419 /* Wait for the clocks to stabilize. */
2420 POSTING_READ(reg);
2421 udelay(150);
2422 }
2423
2424 /* Enable the pipe */
2425 reg = PIPECONF(pipe);
2426 temp = I915_READ(reg);
2427 if ((temp & PIPECONF_ENABLE) == 0)
2428 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2429
2430 /* Enable the plane */
2431 reg = DSPCNTR(plane);
2432 temp = I915_READ(reg);
2433 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2434 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2435 intel_flush_display_plane(dev, plane);
2436 }
2437
2438 intel_crtc_load_lut(crtc);
2439 intel_update_fbc(dev);
2440
2441 /* Give the overlay scaler a chance to enable if it's on this pipe */
2442 intel_crtc_dpms_overlay(intel_crtc, true);
2443 intel_crtc_update_cursor(crtc, true);
2444 }
2445
2446 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2447 {
2448 struct drm_device *dev = crtc->dev;
2449 struct drm_i915_private *dev_priv = dev->dev_private;
2450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2451 int pipe = intel_crtc->pipe;
2452 int plane = intel_crtc->plane;
2453 u32 reg, temp;
2454
2455 if (!intel_crtc->active)
2456 return;
2457
2458 /* Give the overlay scaler a chance to disable if it's on this pipe */
2459 intel_crtc_wait_for_pending_flips(crtc);
2460 drm_vblank_off(dev, pipe);
2461 intel_crtc_dpms_overlay(intel_crtc, false);
2462 intel_crtc_update_cursor(crtc, false);
2463
2464 if (dev_priv->cfb_plane == plane &&
2465 dev_priv->display.disable_fbc)
2466 dev_priv->display.disable_fbc(dev);
2467
2468 /* Disable display plane */
2469 reg = DSPCNTR(plane);
2470 temp = I915_READ(reg);
2471 if (temp & DISPLAY_PLANE_ENABLE) {
2472 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2473 /* Flush the plane changes */
2474 intel_flush_display_plane(dev, plane);
2475
2476 /* Wait for vblank for the disable to take effect */
2477 if (IS_GEN2(dev))
2478 intel_wait_for_vblank(dev, pipe);
2479 }
2480
2481 /* Don't disable pipe A or pipe A PLLs if needed */
2482 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2483 goto done;
2484
2485 /* Next, disable display pipes */
2486 reg = PIPECONF(pipe);
2487 temp = I915_READ(reg);
2488 if (temp & PIPECONF_ENABLE) {
2489 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2490
2491 /* Wait for the pipe to turn off */
2492 POSTING_READ(reg);
2493 intel_wait_for_pipe_off(dev, pipe);
2494 }
2495
2496 reg = DPLL(pipe);
2497 temp = I915_READ(reg);
2498 if (temp & DPLL_VCO_ENABLE) {
2499 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2500
2501 /* Wait for the clocks to turn off. */
2502 POSTING_READ(reg);
2503 udelay(150);
2504 }
2505
2506 done:
2507 intel_crtc->active = false;
2508 intel_update_fbc(dev);
2509 intel_update_watermarks(dev);
2510 intel_clear_scanline_wait(dev);
2511 }
2512
2513 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2514 {
2515 /* XXX: When our outputs are all unaware of DPMS modes other than off
2516 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2517 */
2518 switch (mode) {
2519 case DRM_MODE_DPMS_ON:
2520 case DRM_MODE_DPMS_STANDBY:
2521 case DRM_MODE_DPMS_SUSPEND:
2522 i9xx_crtc_enable(crtc);
2523 break;
2524 case DRM_MODE_DPMS_OFF:
2525 i9xx_crtc_disable(crtc);
2526 break;
2527 }
2528 }
2529
2530 /**
2531 * Sets the power management mode of the pipe and plane.
2532 */
2533 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2534 {
2535 struct drm_device *dev = crtc->dev;
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537 struct drm_i915_master_private *master_priv;
2538 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2539 int pipe = intel_crtc->pipe;
2540 bool enabled;
2541
2542 if (intel_crtc->dpms_mode == mode)
2543 return;
2544
2545 intel_crtc->dpms_mode = mode;
2546
2547 dev_priv->display.dpms(crtc, mode);
2548
2549 if (!dev->primary->master)
2550 return;
2551
2552 master_priv = dev->primary->master->driver_priv;
2553 if (!master_priv->sarea_priv)
2554 return;
2555
2556 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2557
2558 switch (pipe) {
2559 case 0:
2560 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2561 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2562 break;
2563 case 1:
2564 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2565 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2566 break;
2567 default:
2568 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2569 break;
2570 }
2571 }
2572
2573 static void intel_crtc_disable(struct drm_crtc *crtc)
2574 {
2575 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2576 struct drm_device *dev = crtc->dev;
2577
2578 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2579
2580 if (crtc->fb) {
2581 mutex_lock(&dev->struct_mutex);
2582 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
2583 mutex_unlock(&dev->struct_mutex);
2584 }
2585 }
2586
2587 /* Prepare for a mode set.
2588 *
2589 * Note we could be a lot smarter here. We need to figure out which outputs
2590 * will be enabled, which disabled (in short, how the config will changes)
2591 * and perform the minimum necessary steps to accomplish that, e.g. updating
2592 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2593 * panel fitting is in the proper state, etc.
2594 */
2595 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2596 {
2597 i9xx_crtc_disable(crtc);
2598 }
2599
2600 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2601 {
2602 i9xx_crtc_enable(crtc);
2603 }
2604
2605 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2606 {
2607 ironlake_crtc_disable(crtc);
2608 }
2609
2610 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2611 {
2612 ironlake_crtc_enable(crtc);
2613 }
2614
2615 void intel_encoder_prepare (struct drm_encoder *encoder)
2616 {
2617 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2618 /* lvds has its own version of prepare see intel_lvds_prepare */
2619 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2620 }
2621
2622 void intel_encoder_commit (struct drm_encoder *encoder)
2623 {
2624 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2625 /* lvds has its own version of commit see intel_lvds_commit */
2626 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2627 }
2628
2629 void intel_encoder_destroy(struct drm_encoder *encoder)
2630 {
2631 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2632
2633 drm_encoder_cleanup(encoder);
2634 kfree(intel_encoder);
2635 }
2636
2637 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2638 struct drm_display_mode *mode,
2639 struct drm_display_mode *adjusted_mode)
2640 {
2641 struct drm_device *dev = crtc->dev;
2642
2643 if (HAS_PCH_SPLIT(dev)) {
2644 /* FDI link clock is fixed at 2.7G */
2645 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2646 return false;
2647 }
2648
2649 /* XXX some encoders set the crtcinfo, others don't.
2650 * Obviously we need some form of conflict resolution here...
2651 */
2652 if (adjusted_mode->crtc_htotal == 0)
2653 drm_mode_set_crtcinfo(adjusted_mode, 0);
2654
2655 return true;
2656 }
2657
2658 static int i945_get_display_clock_speed(struct drm_device *dev)
2659 {
2660 return 400000;
2661 }
2662
2663 static int i915_get_display_clock_speed(struct drm_device *dev)
2664 {
2665 return 333000;
2666 }
2667
2668 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2669 {
2670 return 200000;
2671 }
2672
2673 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2674 {
2675 u16 gcfgc = 0;
2676
2677 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2678
2679 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2680 return 133000;
2681 else {
2682 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2683 case GC_DISPLAY_CLOCK_333_MHZ:
2684 return 333000;
2685 default:
2686 case GC_DISPLAY_CLOCK_190_200_MHZ:
2687 return 190000;
2688 }
2689 }
2690 }
2691
2692 static int i865_get_display_clock_speed(struct drm_device *dev)
2693 {
2694 return 266000;
2695 }
2696
2697 static int i855_get_display_clock_speed(struct drm_device *dev)
2698 {
2699 u16 hpllcc = 0;
2700 /* Assume that the hardware is in the high speed state. This
2701 * should be the default.
2702 */
2703 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2704 case GC_CLOCK_133_200:
2705 case GC_CLOCK_100_200:
2706 return 200000;
2707 case GC_CLOCK_166_250:
2708 return 250000;
2709 case GC_CLOCK_100_133:
2710 return 133000;
2711 }
2712
2713 /* Shouldn't happen */
2714 return 0;
2715 }
2716
2717 static int i830_get_display_clock_speed(struct drm_device *dev)
2718 {
2719 return 133000;
2720 }
2721
2722 struct fdi_m_n {
2723 u32 tu;
2724 u32 gmch_m;
2725 u32 gmch_n;
2726 u32 link_m;
2727 u32 link_n;
2728 };
2729
2730 static void
2731 fdi_reduce_ratio(u32 *num, u32 *den)
2732 {
2733 while (*num > 0xffffff || *den > 0xffffff) {
2734 *num >>= 1;
2735 *den >>= 1;
2736 }
2737 }
2738
2739 static void
2740 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2741 int link_clock, struct fdi_m_n *m_n)
2742 {
2743 m_n->tu = 64; /* default size */
2744
2745 /* BUG_ON(pixel_clock > INT_MAX / 36); */
2746 m_n->gmch_m = bits_per_pixel * pixel_clock;
2747 m_n->gmch_n = link_clock * nlanes * 8;
2748 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2749
2750 m_n->link_m = pixel_clock;
2751 m_n->link_n = link_clock;
2752 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2753 }
2754
2755
2756 struct intel_watermark_params {
2757 unsigned long fifo_size;
2758 unsigned long max_wm;
2759 unsigned long default_wm;
2760 unsigned long guard_size;
2761 unsigned long cacheline_size;
2762 };
2763
2764 /* Pineview has different values for various configs */
2765 static struct intel_watermark_params pineview_display_wm = {
2766 PINEVIEW_DISPLAY_FIFO,
2767 PINEVIEW_MAX_WM,
2768 PINEVIEW_DFT_WM,
2769 PINEVIEW_GUARD_WM,
2770 PINEVIEW_FIFO_LINE_SIZE
2771 };
2772 static struct intel_watermark_params pineview_display_hplloff_wm = {
2773 PINEVIEW_DISPLAY_FIFO,
2774 PINEVIEW_MAX_WM,
2775 PINEVIEW_DFT_HPLLOFF_WM,
2776 PINEVIEW_GUARD_WM,
2777 PINEVIEW_FIFO_LINE_SIZE
2778 };
2779 static struct intel_watermark_params pineview_cursor_wm = {
2780 PINEVIEW_CURSOR_FIFO,
2781 PINEVIEW_CURSOR_MAX_WM,
2782 PINEVIEW_CURSOR_DFT_WM,
2783 PINEVIEW_CURSOR_GUARD_WM,
2784 PINEVIEW_FIFO_LINE_SIZE,
2785 };
2786 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2787 PINEVIEW_CURSOR_FIFO,
2788 PINEVIEW_CURSOR_MAX_WM,
2789 PINEVIEW_CURSOR_DFT_WM,
2790 PINEVIEW_CURSOR_GUARD_WM,
2791 PINEVIEW_FIFO_LINE_SIZE
2792 };
2793 static struct intel_watermark_params g4x_wm_info = {
2794 G4X_FIFO_SIZE,
2795 G4X_MAX_WM,
2796 G4X_MAX_WM,
2797 2,
2798 G4X_FIFO_LINE_SIZE,
2799 };
2800 static struct intel_watermark_params g4x_cursor_wm_info = {
2801 I965_CURSOR_FIFO,
2802 I965_CURSOR_MAX_WM,
2803 I965_CURSOR_DFT_WM,
2804 2,
2805 G4X_FIFO_LINE_SIZE,
2806 };
2807 static struct intel_watermark_params i965_cursor_wm_info = {
2808 I965_CURSOR_FIFO,
2809 I965_CURSOR_MAX_WM,
2810 I965_CURSOR_DFT_WM,
2811 2,
2812 I915_FIFO_LINE_SIZE,
2813 };
2814 static struct intel_watermark_params i945_wm_info = {
2815 I945_FIFO_SIZE,
2816 I915_MAX_WM,
2817 1,
2818 2,
2819 I915_FIFO_LINE_SIZE
2820 };
2821 static struct intel_watermark_params i915_wm_info = {
2822 I915_FIFO_SIZE,
2823 I915_MAX_WM,
2824 1,
2825 2,
2826 I915_FIFO_LINE_SIZE
2827 };
2828 static struct intel_watermark_params i855_wm_info = {
2829 I855GM_FIFO_SIZE,
2830 I915_MAX_WM,
2831 1,
2832 2,
2833 I830_FIFO_LINE_SIZE
2834 };
2835 static struct intel_watermark_params i830_wm_info = {
2836 I830_FIFO_SIZE,
2837 I915_MAX_WM,
2838 1,
2839 2,
2840 I830_FIFO_LINE_SIZE
2841 };
2842
2843 static struct intel_watermark_params ironlake_display_wm_info = {
2844 ILK_DISPLAY_FIFO,
2845 ILK_DISPLAY_MAXWM,
2846 ILK_DISPLAY_DFTWM,
2847 2,
2848 ILK_FIFO_LINE_SIZE
2849 };
2850
2851 static struct intel_watermark_params ironlake_cursor_wm_info = {
2852 ILK_CURSOR_FIFO,
2853 ILK_CURSOR_MAXWM,
2854 ILK_CURSOR_DFTWM,
2855 2,
2856 ILK_FIFO_LINE_SIZE
2857 };
2858
2859 static struct intel_watermark_params ironlake_display_srwm_info = {
2860 ILK_DISPLAY_SR_FIFO,
2861 ILK_DISPLAY_MAX_SRWM,
2862 ILK_DISPLAY_DFT_SRWM,
2863 2,
2864 ILK_FIFO_LINE_SIZE
2865 };
2866
2867 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2868 ILK_CURSOR_SR_FIFO,
2869 ILK_CURSOR_MAX_SRWM,
2870 ILK_CURSOR_DFT_SRWM,
2871 2,
2872 ILK_FIFO_LINE_SIZE
2873 };
2874
2875 static struct intel_watermark_params sandybridge_display_wm_info = {
2876 SNB_DISPLAY_FIFO,
2877 SNB_DISPLAY_MAXWM,
2878 SNB_DISPLAY_DFTWM,
2879 2,
2880 SNB_FIFO_LINE_SIZE
2881 };
2882
2883 static struct intel_watermark_params sandybridge_cursor_wm_info = {
2884 SNB_CURSOR_FIFO,
2885 SNB_CURSOR_MAXWM,
2886 SNB_CURSOR_DFTWM,
2887 2,
2888 SNB_FIFO_LINE_SIZE
2889 };
2890
2891 static struct intel_watermark_params sandybridge_display_srwm_info = {
2892 SNB_DISPLAY_SR_FIFO,
2893 SNB_DISPLAY_MAX_SRWM,
2894 SNB_DISPLAY_DFT_SRWM,
2895 2,
2896 SNB_FIFO_LINE_SIZE
2897 };
2898
2899 static struct intel_watermark_params sandybridge_cursor_srwm_info = {
2900 SNB_CURSOR_SR_FIFO,
2901 SNB_CURSOR_MAX_SRWM,
2902 SNB_CURSOR_DFT_SRWM,
2903 2,
2904 SNB_FIFO_LINE_SIZE
2905 };
2906
2907
2908 /**
2909 * intel_calculate_wm - calculate watermark level
2910 * @clock_in_khz: pixel clock
2911 * @wm: chip FIFO params
2912 * @pixel_size: display pixel size
2913 * @latency_ns: memory latency for the platform
2914 *
2915 * Calculate the watermark level (the level at which the display plane will
2916 * start fetching from memory again). Each chip has a different display
2917 * FIFO size and allocation, so the caller needs to figure that out and pass
2918 * in the correct intel_watermark_params structure.
2919 *
2920 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2921 * on the pixel size. When it reaches the watermark level, it'll start
2922 * fetching FIFO line sized based chunks from memory until the FIFO fills
2923 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2924 * will occur, and a display engine hang could result.
2925 */
2926 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2927 struct intel_watermark_params *wm,
2928 int pixel_size,
2929 unsigned long latency_ns)
2930 {
2931 long entries_required, wm_size;
2932
2933 /*
2934 * Note: we need to make sure we don't overflow for various clock &
2935 * latency values.
2936 * clocks go from a few thousand to several hundred thousand.
2937 * latency is usually a few thousand
2938 */
2939 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2940 1000;
2941 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2942
2943 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2944
2945 wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2946
2947 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2948
2949 /* Don't promote wm_size to unsigned... */
2950 if (wm_size > (long)wm->max_wm)
2951 wm_size = wm->max_wm;
2952 if (wm_size <= 0)
2953 wm_size = wm->default_wm;
2954 return wm_size;
2955 }
2956
2957 struct cxsr_latency {
2958 int is_desktop;
2959 int is_ddr3;
2960 unsigned long fsb_freq;
2961 unsigned long mem_freq;
2962 unsigned long display_sr;
2963 unsigned long display_hpll_disable;
2964 unsigned long cursor_sr;
2965 unsigned long cursor_hpll_disable;
2966 };
2967
2968 static const struct cxsr_latency cxsr_latency_table[] = {
2969 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2970 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2971 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2972 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2973 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2974
2975 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2976 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2977 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2978 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2979 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2980
2981 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2982 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2983 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2984 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2985 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2986
2987 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2988 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2989 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2990 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2991 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2992
2993 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2994 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2995 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2996 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2997 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2998
2999 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3000 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3001 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3002 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3003 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3004 };
3005
3006 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3007 int is_ddr3,
3008 int fsb,
3009 int mem)
3010 {
3011 const struct cxsr_latency *latency;
3012 int i;
3013
3014 if (fsb == 0 || mem == 0)
3015 return NULL;
3016
3017 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3018 latency = &cxsr_latency_table[i];
3019 if (is_desktop == latency->is_desktop &&
3020 is_ddr3 == latency->is_ddr3 &&
3021 fsb == latency->fsb_freq && mem == latency->mem_freq)
3022 return latency;
3023 }
3024
3025 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3026
3027 return NULL;
3028 }
3029
3030 static void pineview_disable_cxsr(struct drm_device *dev)
3031 {
3032 struct drm_i915_private *dev_priv = dev->dev_private;
3033
3034 /* deactivate cxsr */
3035 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
3036 }
3037
3038 /*
3039 * Latency for FIFO fetches is dependent on several factors:
3040 * - memory configuration (speed, channels)
3041 * - chipset
3042 * - current MCH state
3043 * It can be fairly high in some situations, so here we assume a fairly
3044 * pessimal value. It's a tradeoff between extra memory fetches (if we
3045 * set this value too high, the FIFO will fetch frequently to stay full)
3046 * and power consumption (set it too low to save power and we might see
3047 * FIFO underruns and display "flicker").
3048 *
3049 * A value of 5us seems to be a good balance; safe for very low end
3050 * platforms but not overly aggressive on lower latency configs.
3051 */
3052 static const int latency_ns = 5000;
3053
3054 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
3055 {
3056 struct drm_i915_private *dev_priv = dev->dev_private;
3057 uint32_t dsparb = I915_READ(DSPARB);
3058 int size;
3059
3060 size = dsparb & 0x7f;
3061 if (plane)
3062 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
3063
3064 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3065 plane ? "B" : "A", size);
3066
3067 return size;
3068 }
3069
3070 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3071 {
3072 struct drm_i915_private *dev_priv = dev->dev_private;
3073 uint32_t dsparb = I915_READ(DSPARB);
3074 int size;
3075
3076 size = dsparb & 0x1ff;
3077 if (plane)
3078 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
3079 size >>= 1; /* Convert to cachelines */
3080
3081 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3082 plane ? "B" : "A", size);
3083
3084 return size;
3085 }
3086
3087 static int i845_get_fifo_size(struct drm_device *dev, int plane)
3088 {
3089 struct drm_i915_private *dev_priv = dev->dev_private;
3090 uint32_t dsparb = I915_READ(DSPARB);
3091 int size;
3092
3093 size = dsparb & 0x7f;
3094 size >>= 2; /* Convert to cachelines */
3095
3096 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3097 plane ? "B" : "A",
3098 size);
3099
3100 return size;
3101 }
3102
3103 static int i830_get_fifo_size(struct drm_device *dev, int plane)
3104 {
3105 struct drm_i915_private *dev_priv = dev->dev_private;
3106 uint32_t dsparb = I915_READ(DSPARB);
3107 int size;
3108
3109 size = dsparb & 0x7f;
3110 size >>= 1; /* Convert to cachelines */
3111
3112 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3113 plane ? "B" : "A", size);
3114
3115 return size;
3116 }
3117
3118 static void pineview_update_wm(struct drm_device *dev, int planea_clock,
3119 int planeb_clock, int sr_hdisplay, int unused,
3120 int pixel_size)
3121 {
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3123 const struct cxsr_latency *latency;
3124 u32 reg;
3125 unsigned long wm;
3126 int sr_clock;
3127
3128 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3129 dev_priv->fsb_freq, dev_priv->mem_freq);
3130 if (!latency) {
3131 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3132 pineview_disable_cxsr(dev);
3133 return;
3134 }
3135
3136 if (!planea_clock || !planeb_clock) {
3137 sr_clock = planea_clock ? planea_clock : planeb_clock;
3138
3139 /* Display SR */
3140 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3141 pixel_size, latency->display_sr);
3142 reg = I915_READ(DSPFW1);
3143 reg &= ~DSPFW_SR_MASK;
3144 reg |= wm << DSPFW_SR_SHIFT;
3145 I915_WRITE(DSPFW1, reg);
3146 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3147
3148 /* cursor SR */
3149 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3150 pixel_size, latency->cursor_sr);
3151 reg = I915_READ(DSPFW3);
3152 reg &= ~DSPFW_CURSOR_SR_MASK;
3153 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3154 I915_WRITE(DSPFW3, reg);
3155
3156 /* Display HPLL off SR */
3157 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3158 pixel_size, latency->display_hpll_disable);
3159 reg = I915_READ(DSPFW3);
3160 reg &= ~DSPFW_HPLL_SR_MASK;
3161 reg |= wm & DSPFW_HPLL_SR_MASK;
3162 I915_WRITE(DSPFW3, reg);
3163
3164 /* cursor HPLL off SR */
3165 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3166 pixel_size, latency->cursor_hpll_disable);
3167 reg = I915_READ(DSPFW3);
3168 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3169 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3170 I915_WRITE(DSPFW3, reg);
3171 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3172
3173 /* activate cxsr */
3174 I915_WRITE(DSPFW3,
3175 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3176 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3177 } else {
3178 pineview_disable_cxsr(dev);
3179 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3180 }
3181 }
3182
3183 static void g4x_update_wm(struct drm_device *dev, int planea_clock,
3184 int planeb_clock, int sr_hdisplay, int sr_htotal,
3185 int pixel_size)
3186 {
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 int total_size, cacheline_size;
3189 int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3190 struct intel_watermark_params planea_params, planeb_params;
3191 unsigned long line_time_us;
3192 int sr_clock, sr_entries = 0, entries_required;
3193
3194 /* Create copies of the base settings for each pipe */
3195 planea_params = planeb_params = g4x_wm_info;
3196
3197 /* Grab a couple of global values before we overwrite them */
3198 total_size = planea_params.fifo_size;
3199 cacheline_size = planea_params.cacheline_size;
3200
3201 /*
3202 * Note: we need to make sure we don't overflow for various clock &
3203 * latency values.
3204 * clocks go from a few thousand to several hundred thousand.
3205 * latency is usually a few thousand
3206 */
3207 entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3208 1000;
3209 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3210 planea_wm = entries_required + planea_params.guard_size;
3211
3212 entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3213 1000;
3214 entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3215 planeb_wm = entries_required + planeb_params.guard_size;
3216
3217 cursora_wm = cursorb_wm = 16;
3218 cursor_sr = 32;
3219
3220 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3221
3222 /* Calc sr entries for one plane configs */
3223 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3224 /* self-refresh has much higher latency */
3225 static const int sr_latency_ns = 12000;
3226
3227 sr_clock = planea_clock ? planea_clock : planeb_clock;
3228 line_time_us = ((sr_htotal * 1000) / sr_clock);
3229
3230 /* Use ns/us then divide to preserve precision */
3231 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3232 pixel_size * sr_hdisplay;
3233 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3234
3235 entries_required = (((sr_latency_ns / line_time_us) +
3236 1000) / 1000) * pixel_size * 64;
3237 entries_required = DIV_ROUND_UP(entries_required,
3238 g4x_cursor_wm_info.cacheline_size);
3239 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3240
3241 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3242 cursor_sr = g4x_cursor_wm_info.max_wm;
3243 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3244 "cursor %d\n", sr_entries, cursor_sr);
3245
3246 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3247 } else {
3248 /* Turn off self refresh if both pipes are enabled */
3249 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3250 & ~FW_BLC_SELF_EN);
3251 }
3252
3253 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3254 planea_wm, planeb_wm, sr_entries);
3255
3256 planea_wm &= 0x3f;
3257 planeb_wm &= 0x3f;
3258
3259 I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3260 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3261 (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3262 I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3263 (cursora_wm << DSPFW_CURSORA_SHIFT));
3264 /* HPLL off in SR has some issues on G4x... disable it */
3265 I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3266 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3267 }
3268
3269 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3270 int planeb_clock, int sr_hdisplay, int sr_htotal,
3271 int pixel_size)
3272 {
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 unsigned long line_time_us;
3275 int sr_clock, sr_entries, srwm = 1;
3276 int cursor_sr = 16;
3277
3278 /* Calc sr entries for one plane configs */
3279 if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3280 /* self-refresh has much higher latency */
3281 static const int sr_latency_ns = 12000;
3282
3283 sr_clock = planea_clock ? planea_clock : planeb_clock;
3284 line_time_us = ((sr_htotal * 1000) / sr_clock);
3285
3286 /* Use ns/us then divide to preserve precision */
3287 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3288 pixel_size * sr_hdisplay;
3289 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3290 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3291 srwm = I965_FIFO_SIZE - sr_entries;
3292 if (srwm < 0)
3293 srwm = 1;
3294 srwm &= 0x1ff;
3295
3296 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3297 pixel_size * 64;
3298 sr_entries = DIV_ROUND_UP(sr_entries,
3299 i965_cursor_wm_info.cacheline_size);
3300 cursor_sr = i965_cursor_wm_info.fifo_size -
3301 (sr_entries + i965_cursor_wm_info.guard_size);
3302
3303 if (cursor_sr > i965_cursor_wm_info.max_wm)
3304 cursor_sr = i965_cursor_wm_info.max_wm;
3305
3306 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3307 "cursor %d\n", srwm, cursor_sr);
3308
3309 if (IS_CRESTLINE(dev))
3310 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3311 } else {
3312 /* Turn off self refresh if both pipes are enabled */
3313 if (IS_CRESTLINE(dev))
3314 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3315 & ~FW_BLC_SELF_EN);
3316 }
3317
3318 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3319 srwm);
3320
3321 /* 965 has limitations... */
3322 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3323 (8 << 0));
3324 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3325 /* update cursor SR watermark */
3326 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3327 }
3328
3329 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3330 int planeb_clock, int sr_hdisplay, int sr_htotal,
3331 int pixel_size)
3332 {
3333 struct drm_i915_private *dev_priv = dev->dev_private;
3334 uint32_t fwater_lo;
3335 uint32_t fwater_hi;
3336 int total_size, cacheline_size, cwm, srwm = 1;
3337 int planea_wm, planeb_wm;
3338 struct intel_watermark_params planea_params, planeb_params;
3339 unsigned long line_time_us;
3340 int sr_clock, sr_entries = 0;
3341
3342 /* Create copies of the base settings for each pipe */
3343 if (IS_CRESTLINE(dev) || IS_I945GM(dev))
3344 planea_params = planeb_params = i945_wm_info;
3345 else if (!IS_GEN2(dev))
3346 planea_params = planeb_params = i915_wm_info;
3347 else
3348 planea_params = planeb_params = i855_wm_info;
3349
3350 /* Grab a couple of global values before we overwrite them */
3351 total_size = planea_params.fifo_size;
3352 cacheline_size = planea_params.cacheline_size;
3353
3354 /* Update per-plane FIFO sizes */
3355 planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3356 planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3357
3358 planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3359 pixel_size, latency_ns);
3360 planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3361 pixel_size, latency_ns);
3362 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3363
3364 /*
3365 * Overlay gets an aggressive default since video jitter is bad.
3366 */
3367 cwm = 2;
3368
3369 /* Calc sr entries for one plane configs */
3370 if (HAS_FW_BLC(dev) && sr_hdisplay &&
3371 (!planea_clock || !planeb_clock)) {
3372 /* self-refresh has much higher latency */
3373 static const int sr_latency_ns = 6000;
3374
3375 sr_clock = planea_clock ? planea_clock : planeb_clock;
3376 line_time_us = ((sr_htotal * 1000) / sr_clock);
3377
3378 /* Use ns/us then divide to preserve precision */
3379 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3380 pixel_size * sr_hdisplay;
3381 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3382 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3383 srwm = total_size - sr_entries;
3384 if (srwm < 0)
3385 srwm = 1;
3386
3387 if (IS_I945G(dev) || IS_I945GM(dev))
3388 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3389 else if (IS_I915GM(dev)) {
3390 /* 915M has a smaller SRWM field */
3391 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3392 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3393 }
3394 } else {
3395 /* Turn off self refresh if both pipes are enabled */
3396 if (IS_I945G(dev) || IS_I945GM(dev)) {
3397 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3398 & ~FW_BLC_SELF_EN);
3399 } else if (IS_I915GM(dev)) {
3400 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3401 }
3402 }
3403
3404 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3405 planea_wm, planeb_wm, cwm, srwm);
3406
3407 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3408 fwater_hi = (cwm & 0x1f);
3409
3410 /* Set request length to 8 cachelines per fetch */
3411 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3412 fwater_hi = fwater_hi | (1 << 8);
3413
3414 I915_WRITE(FW_BLC, fwater_lo);
3415 I915_WRITE(FW_BLC2, fwater_hi);
3416 }
3417
3418 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3419 int unused2, int unused3, int pixel_size)
3420 {
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422 uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3423 int planea_wm;
3424
3425 i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3426
3427 planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3428 pixel_size, latency_ns);
3429 fwater_lo |= (3<<8) | planea_wm;
3430
3431 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3432
3433 I915_WRITE(FW_BLC, fwater_lo);
3434 }
3435
3436 #define ILK_LP0_PLANE_LATENCY 700
3437 #define ILK_LP0_CURSOR_LATENCY 1300
3438
3439 static bool ironlake_compute_wm0(struct drm_device *dev,
3440 int pipe,
3441 const struct intel_watermark_params *display,
3442 int display_latency_ns,
3443 const struct intel_watermark_params *cursor,
3444 int cursor_latency_ns,
3445 int *plane_wm,
3446 int *cursor_wm)
3447 {
3448 struct drm_crtc *crtc;
3449 int htotal, hdisplay, clock, pixel_size;
3450 int line_time_us, line_count;
3451 int entries, tlb_miss;
3452
3453 crtc = intel_get_crtc_for_pipe(dev, pipe);
3454 if (crtc->fb == NULL || !crtc->enabled)
3455 return false;
3456
3457 htotal = crtc->mode.htotal;
3458 hdisplay = crtc->mode.hdisplay;
3459 clock = crtc->mode.clock;
3460 pixel_size = crtc->fb->bits_per_pixel / 8;
3461
3462 /* Use the small buffer method to calculate plane watermark */
3463 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3464 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3465 if (tlb_miss > 0)
3466 entries += tlb_miss;
3467 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3468 *plane_wm = entries + display->guard_size;
3469 if (*plane_wm > (int)display->max_wm)
3470 *plane_wm = display->max_wm;
3471
3472 /* Use the large buffer method to calculate cursor watermark */
3473 line_time_us = ((htotal * 1000) / clock);
3474 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3475 entries = line_count * 64 * pixel_size;
3476 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3477 if (tlb_miss > 0)
3478 entries += tlb_miss;
3479 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3480 *cursor_wm = entries + cursor->guard_size;
3481 if (*cursor_wm > (int)cursor->max_wm)
3482 *cursor_wm = (int)cursor->max_wm;
3483
3484 return true;
3485 }
3486
3487 /*
3488 * Check the wm result.
3489 *
3490 * If any calculated watermark values is larger than the maximum value that
3491 * can be programmed into the associated watermark register, that watermark
3492 * must be disabled.
3493 */
3494 static bool ironlake_check_srwm(struct drm_device *dev, int level,
3495 int fbc_wm, int display_wm, int cursor_wm,
3496 const struct intel_watermark_params *display,
3497 const struct intel_watermark_params *cursor)
3498 {
3499 struct drm_i915_private *dev_priv = dev->dev_private;
3500
3501 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
3502 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
3503
3504 if (fbc_wm > SNB_FBC_MAX_SRWM) {
3505 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
3506 fbc_wm, SNB_FBC_MAX_SRWM, level);
3507
3508 /* fbc has it's own way to disable FBC WM */
3509 I915_WRITE(DISP_ARB_CTL,
3510 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
3511 return false;
3512 }
3513
3514 if (display_wm > display->max_wm) {
3515 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
3516 display_wm, SNB_DISPLAY_MAX_SRWM, level);
3517 return false;
3518 }
3519
3520 if (cursor_wm > cursor->max_wm) {
3521 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
3522 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
3523 return false;
3524 }
3525
3526 if (!(fbc_wm || display_wm || cursor_wm)) {
3527 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
3528 return false;
3529 }
3530
3531 return true;
3532 }
3533
3534 /*
3535 * Compute watermark values of WM[1-3],
3536 */
3537 static bool ironlake_compute_srwm(struct drm_device *dev, int level,
3538 int hdisplay, int htotal,
3539 int pixel_size, int clock, int latency_ns,
3540 const struct intel_watermark_params *display,
3541 const struct intel_watermark_params *cursor,
3542 int *fbc_wm, int *display_wm, int *cursor_wm)
3543 {
3544
3545 unsigned long line_time_us;
3546 int line_count, line_size;
3547 int small, large;
3548 int entries;
3549
3550 if (!latency_ns) {
3551 *fbc_wm = *display_wm = *cursor_wm = 0;
3552 return false;
3553 }
3554
3555 line_time_us = (htotal * 1000) / clock;
3556 line_count = (latency_ns / line_time_us + 1000) / 1000;
3557 line_size = hdisplay * pixel_size;
3558
3559 /* Use the minimum of the small and large buffer method for primary */
3560 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3561 large = line_count * line_size;
3562
3563 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3564 *display_wm = entries + display->guard_size;
3565
3566 /*
3567 * Spec says:
3568 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
3569 */
3570 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
3571
3572 /* calculate the self-refresh watermark for display cursor */
3573 entries = line_count * pixel_size * 64;
3574 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3575 *cursor_wm = entries + cursor->guard_size;
3576
3577 return ironlake_check_srwm(dev, level,
3578 *fbc_wm, *display_wm, *cursor_wm,
3579 display, cursor);
3580 }
3581
3582 static void ironlake_update_wm(struct drm_device *dev,
3583 int planea_clock, int planeb_clock,
3584 int hdisplay, int htotal,
3585 int pixel_size)
3586 {
3587 struct drm_i915_private *dev_priv = dev->dev_private;
3588 int fbc_wm, plane_wm, cursor_wm, enabled;
3589 int clock;
3590
3591 enabled = 0;
3592 if (ironlake_compute_wm0(dev, 0,
3593 &ironlake_display_wm_info,
3594 ILK_LP0_PLANE_LATENCY,
3595 &ironlake_cursor_wm_info,
3596 ILK_LP0_CURSOR_LATENCY,
3597 &plane_wm, &cursor_wm)) {
3598 I915_WRITE(WM0_PIPEA_ILK,
3599 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3600 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3601 " plane %d, " "cursor: %d\n",
3602 plane_wm, cursor_wm);
3603 enabled++;
3604 }
3605
3606 if (ironlake_compute_wm0(dev, 1,
3607 &ironlake_display_wm_info,
3608 ILK_LP0_PLANE_LATENCY,
3609 &ironlake_cursor_wm_info,
3610 ILK_LP0_CURSOR_LATENCY,
3611 &plane_wm, &cursor_wm)) {
3612 I915_WRITE(WM0_PIPEB_ILK,
3613 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3614 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3615 " plane %d, cursor: %d\n",
3616 plane_wm, cursor_wm);
3617 enabled++;
3618 }
3619
3620 /*
3621 * Calculate and update the self-refresh watermark only when one
3622 * display plane is used.
3623 */
3624 I915_WRITE(WM3_LP_ILK, 0);
3625 I915_WRITE(WM2_LP_ILK, 0);
3626 I915_WRITE(WM1_LP_ILK, 0);
3627
3628 if (enabled != 1)
3629 return;
3630
3631 clock = planea_clock ? planea_clock : planeb_clock;
3632
3633 /* WM1 */
3634 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3635 clock, ILK_READ_WM1_LATENCY() * 500,
3636 &ironlake_display_srwm_info,
3637 &ironlake_cursor_srwm_info,
3638 &fbc_wm, &plane_wm, &cursor_wm))
3639 return;
3640
3641 I915_WRITE(WM1_LP_ILK,
3642 WM1_LP_SR_EN |
3643 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3644 (fbc_wm << WM1_LP_FBC_SHIFT) |
3645 (plane_wm << WM1_LP_SR_SHIFT) |
3646 cursor_wm);
3647
3648 /* WM2 */
3649 if (!ironlake_compute_srwm(dev, 2, hdisplay, htotal, pixel_size,
3650 clock, ILK_READ_WM2_LATENCY() * 500,
3651 &ironlake_display_srwm_info,
3652 &ironlake_cursor_srwm_info,
3653 &fbc_wm, &plane_wm, &cursor_wm))
3654 return;
3655
3656 I915_WRITE(WM2_LP_ILK,
3657 WM2_LP_EN |
3658 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3659 (fbc_wm << WM1_LP_FBC_SHIFT) |
3660 (plane_wm << WM1_LP_SR_SHIFT) |
3661 cursor_wm);
3662
3663 /*
3664 * WM3 is unsupported on ILK, probably because we don't have latency
3665 * data for that power state
3666 */
3667 }
3668
3669 static void sandybridge_update_wm(struct drm_device *dev,
3670 int planea_clock, int planeb_clock,
3671 int hdisplay, int htotal,
3672 int pixel_size)
3673 {
3674 struct drm_i915_private *dev_priv = dev->dev_private;
3675 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
3676 int fbc_wm, plane_wm, cursor_wm, enabled;
3677 int clock;
3678
3679 enabled = 0;
3680 if (ironlake_compute_wm0(dev, 0,
3681 &sandybridge_display_wm_info, latency,
3682 &sandybridge_cursor_wm_info, latency,
3683 &plane_wm, &cursor_wm)) {
3684 I915_WRITE(WM0_PIPEA_ILK,
3685 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3686 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3687 " plane %d, " "cursor: %d\n",
3688 plane_wm, cursor_wm);
3689 enabled++;
3690 }
3691
3692 if (ironlake_compute_wm0(dev, 1,
3693 &sandybridge_display_wm_info, latency,
3694 &sandybridge_cursor_wm_info, latency,
3695 &plane_wm, &cursor_wm)) {
3696 I915_WRITE(WM0_PIPEB_ILK,
3697 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3698 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3699 " plane %d, cursor: %d\n",
3700 plane_wm, cursor_wm);
3701 enabled++;
3702 }
3703
3704 /*
3705 * Calculate and update the self-refresh watermark only when one
3706 * display plane is used.
3707 *
3708 * SNB support 3 levels of watermark.
3709 *
3710 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
3711 * and disabled in the descending order
3712 *
3713 */
3714 I915_WRITE(WM3_LP_ILK, 0);
3715 I915_WRITE(WM2_LP_ILK, 0);
3716 I915_WRITE(WM1_LP_ILK, 0);
3717
3718 if (enabled != 1)
3719 return;
3720
3721 clock = planea_clock ? planea_clock : planeb_clock;
3722
3723 /* WM1 */
3724 if (!ironlake_compute_srwm(dev, 1, hdisplay, htotal, pixel_size,
3725 clock, SNB_READ_WM1_LATENCY() * 500,
3726 &sandybridge_display_srwm_info,
3727 &sandybridge_cursor_srwm_info,
3728 &fbc_wm, &plane_wm, &cursor_wm))
3729 return;
3730
3731 I915_WRITE(WM1_LP_ILK,
3732 WM1_LP_SR_EN |
3733 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3734 (fbc_wm << WM1_LP_FBC_SHIFT) |
3735 (plane_wm << WM1_LP_SR_SHIFT) |
3736 cursor_wm);
3737
3738 /* WM2 */
3739 if (!ironlake_compute_srwm(dev, 2,
3740 hdisplay, htotal, pixel_size,
3741 clock, SNB_READ_WM2_LATENCY() * 500,
3742 &sandybridge_display_srwm_info,
3743 &sandybridge_cursor_srwm_info,
3744 &fbc_wm, &plane_wm, &cursor_wm))
3745 return;
3746
3747 I915_WRITE(WM2_LP_ILK,
3748 WM2_LP_EN |
3749 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3750 (fbc_wm << WM1_LP_FBC_SHIFT) |
3751 (plane_wm << WM1_LP_SR_SHIFT) |
3752 cursor_wm);
3753
3754 /* WM3 */
3755 if (!ironlake_compute_srwm(dev, 3,
3756 hdisplay, htotal, pixel_size,
3757 clock, SNB_READ_WM3_LATENCY() * 500,
3758 &sandybridge_display_srwm_info,
3759 &sandybridge_cursor_srwm_info,
3760 &fbc_wm, &plane_wm, &cursor_wm))
3761 return;
3762
3763 I915_WRITE(WM3_LP_ILK,
3764 WM3_LP_EN |
3765 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
3766 (fbc_wm << WM1_LP_FBC_SHIFT) |
3767 (plane_wm << WM1_LP_SR_SHIFT) |
3768 cursor_wm);
3769 }
3770
3771 /**
3772 * intel_update_watermarks - update FIFO watermark values based on current modes
3773 *
3774 * Calculate watermark values for the various WM regs based on current mode
3775 * and plane configuration.
3776 *
3777 * There are several cases to deal with here:
3778 * - normal (i.e. non-self-refresh)
3779 * - self-refresh (SR) mode
3780 * - lines are large relative to FIFO size (buffer can hold up to 2)
3781 * - lines are small relative to FIFO size (buffer can hold more than 2
3782 * lines), so need to account for TLB latency
3783 *
3784 * The normal calculation is:
3785 * watermark = dotclock * bytes per pixel * latency
3786 * where latency is platform & configuration dependent (we assume pessimal
3787 * values here).
3788 *
3789 * The SR calculation is:
3790 * watermark = (trunc(latency/line time)+1) * surface width *
3791 * bytes per pixel
3792 * where
3793 * line time = htotal / dotclock
3794 * surface width = hdisplay for normal plane and 64 for cursor
3795 * and latency is assumed to be high, as above.
3796 *
3797 * The final value programmed to the register should always be rounded up,
3798 * and include an extra 2 entries to account for clock crossings.
3799 *
3800 * We don't use the sprite, so we can ignore that. And on Crestline we have
3801 * to set the non-SR watermarks to 8.
3802 */
3803 static void intel_update_watermarks(struct drm_device *dev)
3804 {
3805 struct drm_i915_private *dev_priv = dev->dev_private;
3806 struct drm_crtc *crtc;
3807 int sr_hdisplay = 0;
3808 unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3809 int enabled = 0, pixel_size = 0;
3810 int sr_htotal = 0;
3811
3812 if (!dev_priv->display.update_wm)
3813 return;
3814
3815 /* Get the clock config from both planes */
3816 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3818 if (intel_crtc->active) {
3819 enabled++;
3820 if (intel_crtc->plane == 0) {
3821 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3822 intel_crtc->pipe, crtc->mode.clock);
3823 planea_clock = crtc->mode.clock;
3824 } else {
3825 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3826 intel_crtc->pipe, crtc->mode.clock);
3827 planeb_clock = crtc->mode.clock;
3828 }
3829 sr_hdisplay = crtc->mode.hdisplay;
3830 sr_clock = crtc->mode.clock;
3831 sr_htotal = crtc->mode.htotal;
3832 if (crtc->fb)
3833 pixel_size = crtc->fb->bits_per_pixel / 8;
3834 else
3835 pixel_size = 4; /* by default */
3836 }
3837 }
3838
3839 if (enabled <= 0)
3840 return;
3841
3842 dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3843 sr_hdisplay, sr_htotal, pixel_size);
3844 }
3845
3846 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3847 {
3848 return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
3849 }
3850
3851 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3852 struct drm_display_mode *mode,
3853 struct drm_display_mode *adjusted_mode,
3854 int x, int y,
3855 struct drm_framebuffer *old_fb)
3856 {
3857 struct drm_device *dev = crtc->dev;
3858 struct drm_i915_private *dev_priv = dev->dev_private;
3859 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3860 int pipe = intel_crtc->pipe;
3861 int plane = intel_crtc->plane;
3862 u32 fp_reg, dpll_reg;
3863 int refclk, num_connectors = 0;
3864 intel_clock_t clock, reduced_clock;
3865 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3866 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3867 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3868 struct intel_encoder *has_edp_encoder = NULL;
3869 struct drm_mode_config *mode_config = &dev->mode_config;
3870 struct intel_encoder *encoder;
3871 const intel_limit_t *limit;
3872 int ret;
3873 struct fdi_m_n m_n = {0};
3874 u32 reg, temp;
3875 int target_clock;
3876
3877 drm_vblank_pre_modeset(dev, pipe);
3878
3879 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3880 if (encoder->base.crtc != crtc)
3881 continue;
3882
3883 switch (encoder->type) {
3884 case INTEL_OUTPUT_LVDS:
3885 is_lvds = true;
3886 break;
3887 case INTEL_OUTPUT_SDVO:
3888 case INTEL_OUTPUT_HDMI:
3889 is_sdvo = true;
3890 if (encoder->needs_tv_clock)
3891 is_tv = true;
3892 break;
3893 case INTEL_OUTPUT_DVO:
3894 is_dvo = true;
3895 break;
3896 case INTEL_OUTPUT_TVOUT:
3897 is_tv = true;
3898 break;
3899 case INTEL_OUTPUT_ANALOG:
3900 is_crt = true;
3901 break;
3902 case INTEL_OUTPUT_DISPLAYPORT:
3903 is_dp = true;
3904 break;
3905 case INTEL_OUTPUT_EDP:
3906 has_edp_encoder = encoder;
3907 break;
3908 }
3909
3910 num_connectors++;
3911 }
3912
3913 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3914 refclk = dev_priv->lvds_ssc_freq * 1000;
3915 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3916 refclk / 1000);
3917 } else if (!IS_GEN2(dev)) {
3918 refclk = 96000;
3919 if (HAS_PCH_SPLIT(dev) &&
3920 (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
3921 refclk = 120000; /* 120Mhz refclk */
3922 } else {
3923 refclk = 48000;
3924 }
3925
3926 /*
3927 * Returns a set of divisors for the desired target clock with the given
3928 * refclk, or FALSE. The returned values represent the clock equation:
3929 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3930 */
3931 limit = intel_limit(crtc, refclk);
3932 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3933 if (!ok) {
3934 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3935 drm_vblank_post_modeset(dev, pipe);
3936 return -EINVAL;
3937 }
3938
3939 /* Ensure that the cursor is valid for the new mode before changing... */
3940 intel_crtc_update_cursor(crtc, true);
3941
3942 if (is_lvds && dev_priv->lvds_downclock_avail) {
3943 has_reduced_clock = limit->find_pll(limit, crtc,
3944 dev_priv->lvds_downclock,
3945 refclk,
3946 &reduced_clock);
3947 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3948 /*
3949 * If the different P is found, it means that we can't
3950 * switch the display clock by using the FP0/FP1.
3951 * In such case we will disable the LVDS downclock
3952 * feature.
3953 */
3954 DRM_DEBUG_KMS("Different P is found for "
3955 "LVDS clock/downclock\n");
3956 has_reduced_clock = 0;
3957 }
3958 }
3959 /* SDVO TV has fixed PLL values depend on its clock range,
3960 this mirrors vbios setting. */
3961 if (is_sdvo && is_tv) {
3962 if (adjusted_mode->clock >= 100000
3963 && adjusted_mode->clock < 140500) {
3964 clock.p1 = 2;
3965 clock.p2 = 10;
3966 clock.n = 3;
3967 clock.m1 = 16;
3968 clock.m2 = 8;
3969 } else if (adjusted_mode->clock >= 140500
3970 && adjusted_mode->clock <= 200000) {
3971 clock.p1 = 1;
3972 clock.p2 = 10;
3973 clock.n = 6;
3974 clock.m1 = 12;
3975 clock.m2 = 8;
3976 }
3977 }
3978
3979 /* FDI link */
3980 if (HAS_PCH_SPLIT(dev)) {
3981 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3982 int lane = 0, link_bw, bpp;
3983 /* CPU eDP doesn't require FDI link, so just set DP M/N
3984 according to current link config */
3985 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
3986 target_clock = mode->clock;
3987 intel_edp_link_config(has_edp_encoder,
3988 &lane, &link_bw);
3989 } else {
3990 /* [e]DP over FDI requires target mode clock
3991 instead of link clock */
3992 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
3993 target_clock = mode->clock;
3994 else
3995 target_clock = adjusted_mode->clock;
3996
3997 /* FDI is a binary signal running at ~2.7GHz, encoding
3998 * each output octet as 10 bits. The actual frequency
3999 * is stored as a divider into a 100MHz clock, and the
4000 * mode pixel clock is stored in units of 1KHz.
4001 * Hence the bw of each lane in terms of the mode signal
4002 * is:
4003 */
4004 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4005 }
4006
4007 /* determine panel color depth */
4008 temp = I915_READ(PIPECONF(pipe));
4009 temp &= ~PIPE_BPC_MASK;
4010 if (is_lvds) {
4011 /* the BPC will be 6 if it is 18-bit LVDS panel */
4012 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
4013 temp |= PIPE_8BPC;
4014 else
4015 temp |= PIPE_6BPC;
4016 } else if (has_edp_encoder) {
4017 switch (dev_priv->edp.bpp/3) {
4018 case 8:
4019 temp |= PIPE_8BPC;
4020 break;
4021 case 10:
4022 temp |= PIPE_10BPC;
4023 break;
4024 case 6:
4025 temp |= PIPE_6BPC;
4026 break;
4027 case 12:
4028 temp |= PIPE_12BPC;
4029 break;
4030 }
4031 } else
4032 temp |= PIPE_8BPC;
4033 I915_WRITE(PIPECONF(pipe), temp);
4034
4035 switch (temp & PIPE_BPC_MASK) {
4036 case PIPE_8BPC:
4037 bpp = 24;
4038 break;
4039 case PIPE_10BPC:
4040 bpp = 30;
4041 break;
4042 case PIPE_6BPC:
4043 bpp = 18;
4044 break;
4045 case PIPE_12BPC:
4046 bpp = 36;
4047 break;
4048 default:
4049 DRM_ERROR("unknown pipe bpc value\n");
4050 bpp = 24;
4051 }
4052
4053 if (!lane) {
4054 /*
4055 * Account for spread spectrum to avoid
4056 * oversubscribing the link. Max center spread
4057 * is 2.5%; use 5% for safety's sake.
4058 */
4059 u32 bps = target_clock * bpp * 21 / 20;
4060 lane = bps / (link_bw * 8) + 1;
4061 }
4062
4063 intel_crtc->fdi_lanes = lane;
4064
4065 if (pixel_multiplier > 1)
4066 link_bw *= pixel_multiplier;
4067 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
4068 }
4069
4070 /* Ironlake: try to setup display ref clock before DPLL
4071 * enabling. This is only under driver's control after
4072 * PCH B stepping, previous chipset stepping should be
4073 * ignoring this setting.
4074 */
4075 if (HAS_PCH_SPLIT(dev)) {
4076 temp = I915_READ(PCH_DREF_CONTROL);
4077 /* Always enable nonspread source */
4078 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4079 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4080 temp &= ~DREF_SSC_SOURCE_MASK;
4081 temp |= DREF_SSC_SOURCE_ENABLE;
4082 I915_WRITE(PCH_DREF_CONTROL, temp);
4083
4084 POSTING_READ(PCH_DREF_CONTROL);
4085 udelay(200);
4086
4087 if (has_edp_encoder) {
4088 if (intel_panel_use_ssc(dev_priv)) {
4089 temp |= DREF_SSC1_ENABLE;
4090 I915_WRITE(PCH_DREF_CONTROL, temp);
4091
4092 POSTING_READ(PCH_DREF_CONTROL);
4093 udelay(200);
4094 }
4095 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4096
4097 /* Enable CPU source on CPU attached eDP */
4098 if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4099 if (intel_panel_use_ssc(dev_priv))
4100 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4101 else
4102 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4103 } else {
4104 /* Enable SSC on PCH eDP if needed */
4105 if (intel_panel_use_ssc(dev_priv)) {
4106 DRM_ERROR("enabling SSC on PCH\n");
4107 temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
4108 }
4109 }
4110 I915_WRITE(PCH_DREF_CONTROL, temp);
4111 POSTING_READ(PCH_DREF_CONTROL);
4112 udelay(200);
4113 }
4114 }
4115
4116 if (IS_PINEVIEW(dev)) {
4117 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
4118 if (has_reduced_clock)
4119 fp2 = (1 << reduced_clock.n) << 16 |
4120 reduced_clock.m1 << 8 | reduced_clock.m2;
4121 } else {
4122 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4123 if (has_reduced_clock)
4124 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4125 reduced_clock.m2;
4126 }
4127
4128 /* Enable autotuning of the PLL clock (if permissible) */
4129 if (HAS_PCH_SPLIT(dev)) {
4130 int factor = 21;
4131
4132 if (is_lvds) {
4133 if ((intel_panel_use_ssc(dev_priv) &&
4134 dev_priv->lvds_ssc_freq == 100) ||
4135 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4136 factor = 25;
4137 } else if (is_sdvo && is_tv)
4138 factor = 20;
4139
4140 if (clock.m1 < factor * clock.n)
4141 fp |= FP_CB_TUNE;
4142 }
4143
4144 dpll = 0;
4145 if (!HAS_PCH_SPLIT(dev))
4146 dpll = DPLL_VGA_MODE_DIS;
4147
4148 if (!IS_GEN2(dev)) {
4149 if (is_lvds)
4150 dpll |= DPLLB_MODE_LVDS;
4151 else
4152 dpll |= DPLLB_MODE_DAC_SERIAL;
4153 if (is_sdvo) {
4154 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4155 if (pixel_multiplier > 1) {
4156 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4157 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4158 else if (HAS_PCH_SPLIT(dev))
4159 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
4160 }
4161 dpll |= DPLL_DVO_HIGH_SPEED;
4162 }
4163 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
4164 dpll |= DPLL_DVO_HIGH_SPEED;
4165
4166 /* compute bitmask from p1 value */
4167 if (IS_PINEVIEW(dev))
4168 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4169 else {
4170 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4171 /* also FPA1 */
4172 if (HAS_PCH_SPLIT(dev))
4173 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4174 if (IS_G4X(dev) && has_reduced_clock)
4175 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4176 }
4177 switch (clock.p2) {
4178 case 5:
4179 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4180 break;
4181 case 7:
4182 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4183 break;
4184 case 10:
4185 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4186 break;
4187 case 14:
4188 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4189 break;
4190 }
4191 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
4192 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4193 } else {
4194 if (is_lvds) {
4195 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4196 } else {
4197 if (clock.p1 == 2)
4198 dpll |= PLL_P1_DIVIDE_BY_TWO;
4199 else
4200 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4201 if (clock.p2 == 4)
4202 dpll |= PLL_P2_DIVIDE_BY_4;
4203 }
4204 }
4205
4206 if (is_sdvo && is_tv)
4207 dpll |= PLL_REF_INPUT_TVCLKINBC;
4208 else if (is_tv)
4209 /* XXX: just matching BIOS for now */
4210 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4211 dpll |= 3;
4212 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4213 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4214 else
4215 dpll |= PLL_REF_INPUT_DREFCLK;
4216
4217 /* setup pipeconf */
4218 pipeconf = I915_READ(PIPECONF(pipe));
4219
4220 /* Set up the display plane register */
4221 dspcntr = DISPPLANE_GAMMA_ENABLE;
4222
4223 /* Ironlake's plane is forced to pipe, bit 24 is to
4224 enable color space conversion */
4225 if (!HAS_PCH_SPLIT(dev)) {
4226 if (pipe == 0)
4227 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4228 else
4229 dspcntr |= DISPPLANE_SEL_PIPE_B;
4230 }
4231
4232 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4233 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4234 * core speed.
4235 *
4236 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4237 * pipe == 0 check?
4238 */
4239 if (mode->clock >
4240 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4241 pipeconf |= PIPECONF_DOUBLE_WIDE;
4242 else
4243 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4244 }
4245
4246 dspcntr |= DISPLAY_PLANE_ENABLE;
4247 pipeconf |= PIPECONF_ENABLE;
4248 dpll |= DPLL_VCO_ENABLE;
4249
4250 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4251 drm_mode_debug_printmodeline(mode);
4252
4253 /* assign to Ironlake registers */
4254 if (HAS_PCH_SPLIT(dev)) {
4255 fp_reg = PCH_FP0(pipe);
4256 dpll_reg = PCH_DPLL(pipe);
4257 } else {
4258 fp_reg = FP0(pipe);
4259 dpll_reg = DPLL(pipe);
4260 }
4261
4262 /* PCH eDP needs FDI, but CPU eDP does not */
4263 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4264 I915_WRITE(fp_reg, fp);
4265 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
4266
4267 POSTING_READ(dpll_reg);
4268 udelay(150);
4269 }
4270
4271 /* enable transcoder DPLL */
4272 if (HAS_PCH_CPT(dev)) {
4273 temp = I915_READ(PCH_DPLL_SEL);
4274 if (pipe == 0)
4275 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
4276 else
4277 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
4278 I915_WRITE(PCH_DPLL_SEL, temp);
4279
4280 POSTING_READ(PCH_DPLL_SEL);
4281 udelay(150);
4282 }
4283
4284 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4285 * This is an exception to the general rule that mode_set doesn't turn
4286 * things on.
4287 */
4288 if (is_lvds) {
4289 reg = LVDS;
4290 if (HAS_PCH_SPLIT(dev))
4291 reg = PCH_LVDS;
4292
4293 temp = I915_READ(reg);
4294 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4295 if (pipe == 1) {
4296 if (HAS_PCH_CPT(dev))
4297 temp |= PORT_TRANS_B_SEL_CPT;
4298 else
4299 temp |= LVDS_PIPEB_SELECT;
4300 } else {
4301 if (HAS_PCH_CPT(dev))
4302 temp &= ~PORT_TRANS_SEL_MASK;
4303 else
4304 temp &= ~LVDS_PIPEB_SELECT;
4305 }
4306 /* set the corresponsding LVDS_BORDER bit */
4307 temp |= dev_priv->lvds_border_bits;
4308 /* Set the B0-B3 data pairs corresponding to whether we're going to
4309 * set the DPLLs for dual-channel mode or not.
4310 */
4311 if (clock.p2 == 7)
4312 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4313 else
4314 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4315
4316 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4317 * appropriately here, but we need to look more thoroughly into how
4318 * panels behave in the two modes.
4319 */
4320 /* set the dithering flag on non-PCH LVDS as needed */
4321 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4322 if (dev_priv->lvds_dither)
4323 temp |= LVDS_ENABLE_DITHER;
4324 else
4325 temp &= ~LVDS_ENABLE_DITHER;
4326 }
4327 I915_WRITE(reg, temp);
4328 }
4329
4330 /* set the dithering flag and clear for anything other than a panel. */
4331 if (HAS_PCH_SPLIT(dev)) {
4332 pipeconf &= ~PIPECONF_DITHER_EN;
4333 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
4334 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
4335 pipeconf |= PIPECONF_DITHER_EN;
4336 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
4337 }
4338 }
4339
4340 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4341 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4342 } else if (HAS_PCH_SPLIT(dev)) {
4343 /* For non-DP output, clear any trans DP clock recovery setting.*/
4344 if (pipe == 0) {
4345 I915_WRITE(TRANSA_DATA_M1, 0);
4346 I915_WRITE(TRANSA_DATA_N1, 0);
4347 I915_WRITE(TRANSA_DP_LINK_M1, 0);
4348 I915_WRITE(TRANSA_DP_LINK_N1, 0);
4349 } else {
4350 I915_WRITE(TRANSB_DATA_M1, 0);
4351 I915_WRITE(TRANSB_DATA_N1, 0);
4352 I915_WRITE(TRANSB_DP_LINK_M1, 0);
4353 I915_WRITE(TRANSB_DP_LINK_N1, 0);
4354 }
4355 }
4356
4357 if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4358 I915_WRITE(dpll_reg, dpll);
4359
4360 /* Wait for the clocks to stabilize. */
4361 POSTING_READ(dpll_reg);
4362 udelay(150);
4363
4364 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
4365 temp = 0;
4366 if (is_sdvo) {
4367 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4368 if (temp > 1)
4369 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4370 else
4371 temp = 0;
4372 }
4373 I915_WRITE(DPLL_MD(pipe), temp);
4374 } else {
4375 /* The pixel multiplier can only be updated once the
4376 * DPLL is enabled and the clocks are stable.
4377 *
4378 * So write it again.
4379 */
4380 I915_WRITE(dpll_reg, dpll);
4381 }
4382 }
4383
4384 intel_crtc->lowfreq_avail = false;
4385 if (is_lvds && has_reduced_clock && i915_powersave) {
4386 I915_WRITE(fp_reg + 4, fp2);
4387 intel_crtc->lowfreq_avail = true;
4388 if (HAS_PIPE_CXSR(dev)) {
4389 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4390 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4391 }
4392 } else {
4393 I915_WRITE(fp_reg + 4, fp);
4394 if (HAS_PIPE_CXSR(dev)) {
4395 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4396 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4397 }
4398 }
4399
4400 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4401 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4402 /* the chip adds 2 halflines automatically */
4403 adjusted_mode->crtc_vdisplay -= 1;
4404 adjusted_mode->crtc_vtotal -= 1;
4405 adjusted_mode->crtc_vblank_start -= 1;
4406 adjusted_mode->crtc_vblank_end -= 1;
4407 adjusted_mode->crtc_vsync_end -= 1;
4408 adjusted_mode->crtc_vsync_start -= 1;
4409 } else
4410 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4411
4412 I915_WRITE(HTOTAL(pipe),
4413 (adjusted_mode->crtc_hdisplay - 1) |
4414 ((adjusted_mode->crtc_htotal - 1) << 16));
4415 I915_WRITE(HBLANK(pipe),
4416 (adjusted_mode->crtc_hblank_start - 1) |
4417 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4418 I915_WRITE(HSYNC(pipe),
4419 (adjusted_mode->crtc_hsync_start - 1) |
4420 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4421
4422 I915_WRITE(VTOTAL(pipe),
4423 (adjusted_mode->crtc_vdisplay - 1) |
4424 ((adjusted_mode->crtc_vtotal - 1) << 16));
4425 I915_WRITE(VBLANK(pipe),
4426 (adjusted_mode->crtc_vblank_start - 1) |
4427 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4428 I915_WRITE(VSYNC(pipe),
4429 (adjusted_mode->crtc_vsync_start - 1) |
4430 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4431
4432 /* pipesrc and dspsize control the size that is scaled from,
4433 * which should always be the user's requested size.
4434 */
4435 if (!HAS_PCH_SPLIT(dev)) {
4436 I915_WRITE(DSPSIZE(plane),
4437 ((mode->vdisplay - 1) << 16) |
4438 (mode->hdisplay - 1));
4439 I915_WRITE(DSPPOS(plane), 0);
4440 }
4441 I915_WRITE(PIPESRC(pipe),
4442 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4443
4444 if (HAS_PCH_SPLIT(dev)) {
4445 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4446 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4447 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4448 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4449
4450 if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
4451 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4452 }
4453 }
4454
4455 I915_WRITE(PIPECONF(pipe), pipeconf);
4456 POSTING_READ(PIPECONF(pipe));
4457
4458 intel_wait_for_vblank(dev, pipe);
4459
4460 if (IS_GEN5(dev)) {
4461 /* enable address swizzle for tiling buffer */
4462 temp = I915_READ(DISP_ARB_CTL);
4463 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4464 }
4465
4466 I915_WRITE(DSPCNTR(plane), dspcntr);
4467
4468 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4469
4470 intel_update_watermarks(dev);
4471
4472 drm_vblank_post_modeset(dev, pipe);
4473
4474 return ret;
4475 }
4476
4477 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4478 void intel_crtc_load_lut(struct drm_crtc *crtc)
4479 {
4480 struct drm_device *dev = crtc->dev;
4481 struct drm_i915_private *dev_priv = dev->dev_private;
4482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4483 int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4484 int i;
4485
4486 /* The clocks have to be on to load the palette. */
4487 if (!crtc->enabled)
4488 return;
4489
4490 /* use legacy palette for Ironlake */
4491 if (HAS_PCH_SPLIT(dev))
4492 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4493 LGC_PALETTE_B;
4494
4495 for (i = 0; i < 256; i++) {
4496 I915_WRITE(palreg + 4 * i,
4497 (intel_crtc->lut_r[i] << 16) |
4498 (intel_crtc->lut_g[i] << 8) |
4499 intel_crtc->lut_b[i]);
4500 }
4501 }
4502
4503 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4504 {
4505 struct drm_device *dev = crtc->dev;
4506 struct drm_i915_private *dev_priv = dev->dev_private;
4507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4508 bool visible = base != 0;
4509 u32 cntl;
4510
4511 if (intel_crtc->cursor_visible == visible)
4512 return;
4513
4514 cntl = I915_READ(CURACNTR);
4515 if (visible) {
4516 /* On these chipsets we can only modify the base whilst
4517 * the cursor is disabled.
4518 */
4519 I915_WRITE(CURABASE, base);
4520
4521 cntl &= ~(CURSOR_FORMAT_MASK);
4522 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4523 cntl |= CURSOR_ENABLE |
4524 CURSOR_GAMMA_ENABLE |
4525 CURSOR_FORMAT_ARGB;
4526 } else
4527 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4528 I915_WRITE(CURACNTR, cntl);
4529
4530 intel_crtc->cursor_visible = visible;
4531 }
4532
4533 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4534 {
4535 struct drm_device *dev = crtc->dev;
4536 struct drm_i915_private *dev_priv = dev->dev_private;
4537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4538 int pipe = intel_crtc->pipe;
4539 bool visible = base != 0;
4540
4541 if (intel_crtc->cursor_visible != visible) {
4542 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4543 if (base) {
4544 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4545 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4546 cntl |= pipe << 28; /* Connect to correct pipe */
4547 } else {
4548 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4549 cntl |= CURSOR_MODE_DISABLE;
4550 }
4551 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4552
4553 intel_crtc->cursor_visible = visible;
4554 }
4555 /* and commit changes on next vblank */
4556 I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4557 }
4558
4559 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4560 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
4561 bool on)
4562 {
4563 struct drm_device *dev = crtc->dev;
4564 struct drm_i915_private *dev_priv = dev->dev_private;
4565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4566 int pipe = intel_crtc->pipe;
4567 int x = intel_crtc->cursor_x;
4568 int y = intel_crtc->cursor_y;
4569 u32 base, pos;
4570 bool visible;
4571
4572 pos = 0;
4573
4574 if (on && crtc->enabled && crtc->fb) {
4575 base = intel_crtc->cursor_addr;
4576 if (x > (int) crtc->fb->width)
4577 base = 0;
4578
4579 if (y > (int) crtc->fb->height)
4580 base = 0;
4581 } else
4582 base = 0;
4583
4584 if (x < 0) {
4585 if (x + intel_crtc->cursor_width < 0)
4586 base = 0;
4587
4588 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4589 x = -x;
4590 }
4591 pos |= x << CURSOR_X_SHIFT;
4592
4593 if (y < 0) {
4594 if (y + intel_crtc->cursor_height < 0)
4595 base = 0;
4596
4597 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4598 y = -y;
4599 }
4600 pos |= y << CURSOR_Y_SHIFT;
4601
4602 visible = base != 0;
4603 if (!visible && !intel_crtc->cursor_visible)
4604 return;
4605
4606 I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4607 if (IS_845G(dev) || IS_I865G(dev))
4608 i845_update_cursor(crtc, base);
4609 else
4610 i9xx_update_cursor(crtc, base);
4611
4612 if (visible)
4613 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4614 }
4615
4616 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4617 struct drm_file *file,
4618 uint32_t handle,
4619 uint32_t width, uint32_t height)
4620 {
4621 struct drm_device *dev = crtc->dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4624 struct drm_i915_gem_object *obj;
4625 uint32_t addr;
4626 int ret;
4627
4628 DRM_DEBUG_KMS("\n");
4629
4630 /* if we want to turn off the cursor ignore width and height */
4631 if (!handle) {
4632 DRM_DEBUG_KMS("cursor off\n");
4633 addr = 0;
4634 obj = NULL;
4635 mutex_lock(&dev->struct_mutex);
4636 goto finish;
4637 }
4638
4639 /* Currently we only support 64x64 cursors */
4640 if (width != 64 || height != 64) {
4641 DRM_ERROR("we currently only support 64x64 cursors\n");
4642 return -EINVAL;
4643 }
4644
4645 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
4646 if (!obj)
4647 return -ENOENT;
4648
4649 if (obj->base.size < width * height * 4) {
4650 DRM_ERROR("buffer is to small\n");
4651 ret = -ENOMEM;
4652 goto fail;
4653 }
4654
4655 /* we only need to pin inside GTT if cursor is non-phy */
4656 mutex_lock(&dev->struct_mutex);
4657 if (!dev_priv->info->cursor_needs_physical) {
4658 if (obj->tiling_mode) {
4659 DRM_ERROR("cursor cannot be tiled\n");
4660 ret = -EINVAL;
4661 goto fail_locked;
4662 }
4663
4664 ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
4665 if (ret) {
4666 DRM_ERROR("failed to pin cursor bo\n");
4667 goto fail_locked;
4668 }
4669
4670 ret = i915_gem_object_set_to_gtt_domain(obj, 0);
4671 if (ret) {
4672 DRM_ERROR("failed to move cursor bo into the GTT\n");
4673 goto fail_unpin;
4674 }
4675
4676 ret = i915_gem_object_put_fence(obj);
4677 if (ret) {
4678 DRM_ERROR("failed to move cursor bo into the GTT\n");
4679 goto fail_unpin;
4680 }
4681
4682 addr = obj->gtt_offset;
4683 } else {
4684 int align = IS_I830(dev) ? 16 * 1024 : 256;
4685 ret = i915_gem_attach_phys_object(dev, obj,
4686 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4687 align);
4688 if (ret) {
4689 DRM_ERROR("failed to attach phys object\n");
4690 goto fail_locked;
4691 }
4692 addr = obj->phys_obj->handle->busaddr;
4693 }
4694
4695 if (IS_GEN2(dev))
4696 I915_WRITE(CURSIZE, (height << 12) | width);
4697
4698 finish:
4699 if (intel_crtc->cursor_bo) {
4700 if (dev_priv->info->cursor_needs_physical) {
4701 if (intel_crtc->cursor_bo != obj)
4702 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4703 } else
4704 i915_gem_object_unpin(intel_crtc->cursor_bo);
4705 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
4706 }
4707
4708 mutex_unlock(&dev->struct_mutex);
4709
4710 intel_crtc->cursor_addr = addr;
4711 intel_crtc->cursor_bo = obj;
4712 intel_crtc->cursor_width = width;
4713 intel_crtc->cursor_height = height;
4714
4715 intel_crtc_update_cursor(crtc, true);
4716
4717 return 0;
4718 fail_unpin:
4719 i915_gem_object_unpin(obj);
4720 fail_locked:
4721 mutex_unlock(&dev->struct_mutex);
4722 fail:
4723 drm_gem_object_unreference_unlocked(&obj->base);
4724 return ret;
4725 }
4726
4727 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4728 {
4729 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4730
4731 intel_crtc->cursor_x = x;
4732 intel_crtc->cursor_y = y;
4733
4734 intel_crtc_update_cursor(crtc, true);
4735
4736 return 0;
4737 }
4738
4739 /** Sets the color ramps on behalf of RandR */
4740 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4741 u16 blue, int regno)
4742 {
4743 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4744
4745 intel_crtc->lut_r[regno] = red >> 8;
4746 intel_crtc->lut_g[regno] = green >> 8;
4747 intel_crtc->lut_b[regno] = blue >> 8;
4748 }
4749
4750 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4751 u16 *blue, int regno)
4752 {
4753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4754
4755 *red = intel_crtc->lut_r[regno] << 8;
4756 *green = intel_crtc->lut_g[regno] << 8;
4757 *blue = intel_crtc->lut_b[regno] << 8;
4758 }
4759
4760 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4761 u16 *blue, uint32_t start, uint32_t size)
4762 {
4763 int end = (start + size > 256) ? 256 : start + size, i;
4764 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4765
4766 for (i = start; i < end; i++) {
4767 intel_crtc->lut_r[i] = red[i] >> 8;
4768 intel_crtc->lut_g[i] = green[i] >> 8;
4769 intel_crtc->lut_b[i] = blue[i] >> 8;
4770 }
4771
4772 intel_crtc_load_lut(crtc);
4773 }
4774
4775 /**
4776 * Get a pipe with a simple mode set on it for doing load-based monitor
4777 * detection.
4778 *
4779 * It will be up to the load-detect code to adjust the pipe as appropriate for
4780 * its requirements. The pipe will be connected to no other encoders.
4781 *
4782 * Currently this code will only succeed if there is a pipe with no encoders
4783 * configured for it. In the future, it could choose to temporarily disable
4784 * some outputs to free up a pipe for its use.
4785 *
4786 * \return crtc, or NULL if no pipes are available.
4787 */
4788
4789 /* VESA 640x480x72Hz mode to set on the pipe */
4790 static struct drm_display_mode load_detect_mode = {
4791 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4792 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4793 };
4794
4795 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4796 struct drm_connector *connector,
4797 struct drm_display_mode *mode,
4798 int *dpms_mode)
4799 {
4800 struct intel_crtc *intel_crtc;
4801 struct drm_crtc *possible_crtc;
4802 struct drm_crtc *supported_crtc =NULL;
4803 struct drm_encoder *encoder = &intel_encoder->base;
4804 struct drm_crtc *crtc = NULL;
4805 struct drm_device *dev = encoder->dev;
4806 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4807 struct drm_crtc_helper_funcs *crtc_funcs;
4808 int i = -1;
4809
4810 /*
4811 * Algorithm gets a little messy:
4812 * - if the connector already has an assigned crtc, use it (but make
4813 * sure it's on first)
4814 * - try to find the first unused crtc that can drive this connector,
4815 * and use that if we find one
4816 * - if there are no unused crtcs available, try to use the first
4817 * one we found that supports the connector
4818 */
4819
4820 /* See if we already have a CRTC for this connector */
4821 if (encoder->crtc) {
4822 crtc = encoder->crtc;
4823 /* Make sure the crtc and connector are running */
4824 intel_crtc = to_intel_crtc(crtc);
4825 *dpms_mode = intel_crtc->dpms_mode;
4826 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4827 crtc_funcs = crtc->helper_private;
4828 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4829 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4830 }
4831 return crtc;
4832 }
4833
4834 /* Find an unused one (if possible) */
4835 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4836 i++;
4837 if (!(encoder->possible_crtcs & (1 << i)))
4838 continue;
4839 if (!possible_crtc->enabled) {
4840 crtc = possible_crtc;
4841 break;
4842 }
4843 if (!supported_crtc)
4844 supported_crtc = possible_crtc;
4845 }
4846
4847 /*
4848 * If we didn't find an unused CRTC, don't use any.
4849 */
4850 if (!crtc) {
4851 return NULL;
4852 }
4853
4854 encoder->crtc = crtc;
4855 connector->encoder = encoder;
4856 intel_encoder->load_detect_temp = true;
4857
4858 intel_crtc = to_intel_crtc(crtc);
4859 *dpms_mode = intel_crtc->dpms_mode;
4860
4861 if (!crtc->enabled) {
4862 if (!mode)
4863 mode = &load_detect_mode;
4864 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4865 } else {
4866 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4867 crtc_funcs = crtc->helper_private;
4868 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4869 }
4870
4871 /* Add this connector to the crtc */
4872 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4873 encoder_funcs->commit(encoder);
4874 }
4875 /* let the connector get through one full cycle before testing */
4876 intel_wait_for_vblank(dev, intel_crtc->pipe);
4877
4878 return crtc;
4879 }
4880
4881 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4882 struct drm_connector *connector, int dpms_mode)
4883 {
4884 struct drm_encoder *encoder = &intel_encoder->base;
4885 struct drm_device *dev = encoder->dev;
4886 struct drm_crtc *crtc = encoder->crtc;
4887 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4888 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4889
4890 if (intel_encoder->load_detect_temp) {
4891 encoder->crtc = NULL;
4892 connector->encoder = NULL;
4893 intel_encoder->load_detect_temp = false;
4894 crtc->enabled = drm_helper_crtc_in_use(crtc);
4895 drm_helper_disable_unused_functions(dev);
4896 }
4897
4898 /* Switch crtc and encoder back off if necessary */
4899 if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4900 if (encoder->crtc == crtc)
4901 encoder_funcs->dpms(encoder, dpms_mode);
4902 crtc_funcs->dpms(crtc, dpms_mode);
4903 }
4904 }
4905
4906 /* Returns the clock of the currently programmed mode of the given pipe. */
4907 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4908 {
4909 struct drm_i915_private *dev_priv = dev->dev_private;
4910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4911 int pipe = intel_crtc->pipe;
4912 u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4913 u32 fp;
4914 intel_clock_t clock;
4915
4916 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4917 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4918 else
4919 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4920
4921 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4922 if (IS_PINEVIEW(dev)) {
4923 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4924 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4925 } else {
4926 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4927 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4928 }
4929
4930 if (!IS_GEN2(dev)) {
4931 if (IS_PINEVIEW(dev))
4932 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4933 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4934 else
4935 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4936 DPLL_FPA01_P1_POST_DIV_SHIFT);
4937
4938 switch (dpll & DPLL_MODE_MASK) {
4939 case DPLLB_MODE_DAC_SERIAL:
4940 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4941 5 : 10;
4942 break;
4943 case DPLLB_MODE_LVDS:
4944 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4945 7 : 14;
4946 break;
4947 default:
4948 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4949 "mode\n", (int)(dpll & DPLL_MODE_MASK));
4950 return 0;
4951 }
4952
4953 /* XXX: Handle the 100Mhz refclk */
4954 intel_clock(dev, 96000, &clock);
4955 } else {
4956 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4957
4958 if (is_lvds) {
4959 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4960 DPLL_FPA01_P1_POST_DIV_SHIFT);
4961 clock.p2 = 14;
4962
4963 if ((dpll & PLL_REF_INPUT_MASK) ==
4964 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4965 /* XXX: might not be 66MHz */
4966 intel_clock(dev, 66000, &clock);
4967 } else
4968 intel_clock(dev, 48000, &clock);
4969 } else {
4970 if (dpll & PLL_P1_DIVIDE_BY_TWO)
4971 clock.p1 = 2;
4972 else {
4973 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4974 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4975 }
4976 if (dpll & PLL_P2_DIVIDE_BY_4)
4977 clock.p2 = 4;
4978 else
4979 clock.p2 = 2;
4980
4981 intel_clock(dev, 48000, &clock);
4982 }
4983 }
4984
4985 /* XXX: It would be nice to validate the clocks, but we can't reuse
4986 * i830PllIsValid() because it relies on the xf86_config connector
4987 * configuration being accurate, which it isn't necessarily.
4988 */
4989
4990 return clock.dot;
4991 }
4992
4993 /** Returns the currently programmed mode of the given pipe. */
4994 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4995 struct drm_crtc *crtc)
4996 {
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4999 int pipe = intel_crtc->pipe;
5000 struct drm_display_mode *mode;
5001 int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
5002 int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
5003 int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
5004 int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
5005
5006 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5007 if (!mode)
5008 return NULL;
5009
5010 mode->clock = intel_crtc_clock_get(dev, crtc);
5011 mode->hdisplay = (htot & 0xffff) + 1;
5012 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5013 mode->hsync_start = (hsync & 0xffff) + 1;
5014 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5015 mode->vdisplay = (vtot & 0xffff) + 1;
5016 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5017 mode->vsync_start = (vsync & 0xffff) + 1;
5018 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5019
5020 drm_mode_set_name(mode);
5021 drm_mode_set_crtcinfo(mode, 0);
5022
5023 return mode;
5024 }
5025
5026 #define GPU_IDLE_TIMEOUT 500 /* ms */
5027
5028 /* When this timer fires, we've been idle for awhile */
5029 static void intel_gpu_idle_timer(unsigned long arg)
5030 {
5031 struct drm_device *dev = (struct drm_device *)arg;
5032 drm_i915_private_t *dev_priv = dev->dev_private;
5033
5034 if (!list_empty(&dev_priv->mm.active_list)) {
5035 /* Still processing requests, so just re-arm the timer. */
5036 mod_timer(&dev_priv->idle_timer, jiffies +
5037 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5038 return;
5039 }
5040
5041 dev_priv->busy = false;
5042 queue_work(dev_priv->wq, &dev_priv->idle_work);
5043 }
5044
5045 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5046
5047 static void intel_crtc_idle_timer(unsigned long arg)
5048 {
5049 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5050 struct drm_crtc *crtc = &intel_crtc->base;
5051 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
5052 struct intel_framebuffer *intel_fb;
5053
5054 intel_fb = to_intel_framebuffer(crtc->fb);
5055 if (intel_fb && intel_fb->obj->active) {
5056 /* The framebuffer is still being accessed by the GPU. */
5057 mod_timer(&intel_crtc->idle_timer, jiffies +
5058 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5059 return;
5060 }
5061
5062 intel_crtc->busy = false;
5063 queue_work(dev_priv->wq, &dev_priv->idle_work);
5064 }
5065
5066 static void intel_increase_pllclock(struct drm_crtc *crtc)
5067 {
5068 struct drm_device *dev = crtc->dev;
5069 drm_i915_private_t *dev_priv = dev->dev_private;
5070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5071 int pipe = intel_crtc->pipe;
5072 int dpll_reg = DPLL(pipe);
5073 int dpll;
5074
5075 if (HAS_PCH_SPLIT(dev))
5076 return;
5077
5078 if (!dev_priv->lvds_downclock_avail)
5079 return;
5080
5081 dpll = I915_READ(dpll_reg);
5082 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
5083 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5084
5085 /* Unlock panel regs */
5086 I915_WRITE(PP_CONTROL,
5087 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
5088
5089 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5090 I915_WRITE(dpll_reg, dpll);
5091 POSTING_READ(dpll_reg);
5092 intel_wait_for_vblank(dev, pipe);
5093
5094 dpll = I915_READ(dpll_reg);
5095 if (dpll & DISPLAY_RATE_SELECT_FPA1)
5096 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5097
5098 /* ...and lock them again */
5099 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5100 }
5101
5102 /* Schedule downclock */
5103 mod_timer(&intel_crtc->idle_timer, jiffies +
5104 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5105 }
5106
5107 static void intel_decrease_pllclock(struct drm_crtc *crtc)
5108 {
5109 struct drm_device *dev = crtc->dev;
5110 drm_i915_private_t *dev_priv = dev->dev_private;
5111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5112 int pipe = intel_crtc->pipe;
5113 int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
5114 int dpll = I915_READ(dpll_reg);
5115
5116 if (HAS_PCH_SPLIT(dev))
5117 return;
5118
5119 if (!dev_priv->lvds_downclock_avail)
5120 return;
5121
5122 /*
5123 * Since this is called by a timer, we should never get here in
5124 * the manual case.
5125 */
5126 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
5127 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5128
5129 /* Unlock panel regs */
5130 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
5131 PANEL_UNLOCK_REGS);
5132
5133 dpll |= DISPLAY_RATE_SELECT_FPA1;
5134 I915_WRITE(dpll_reg, dpll);
5135 dpll = I915_READ(dpll_reg);
5136 intel_wait_for_vblank(dev, pipe);
5137 dpll = I915_READ(dpll_reg);
5138 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
5139 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5140
5141 /* ...and lock them again */
5142 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
5143 }
5144
5145 }
5146
5147 /**
5148 * intel_idle_update - adjust clocks for idleness
5149 * @work: work struct
5150 *
5151 * Either the GPU or display (or both) went idle. Check the busy status
5152 * here and adjust the CRTC and GPU clocks as necessary.
5153 */
5154 static void intel_idle_update(struct work_struct *work)
5155 {
5156 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5157 idle_work);
5158 struct drm_device *dev = dev_priv->dev;
5159 struct drm_crtc *crtc;
5160 struct intel_crtc *intel_crtc;
5161 int enabled = 0;
5162
5163 if (!i915_powersave)
5164 return;
5165
5166 mutex_lock(&dev->struct_mutex);
5167
5168 i915_update_gfx_val(dev_priv);
5169
5170 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5171 /* Skip inactive CRTCs */
5172 if (!crtc->fb)
5173 continue;
5174
5175 enabled++;
5176 intel_crtc = to_intel_crtc(crtc);
5177 if (!intel_crtc->busy)
5178 intel_decrease_pllclock(crtc);
5179 }
5180
5181 if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
5182 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
5183 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
5184 }
5185
5186 mutex_unlock(&dev->struct_mutex);
5187 }
5188
5189 /**
5190 * intel_mark_busy - mark the GPU and possibly the display busy
5191 * @dev: drm device
5192 * @obj: object we're operating on
5193 *
5194 * Callers can use this function to indicate that the GPU is busy processing
5195 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
5196 * buffer), we'll also mark the display as busy, so we know to increase its
5197 * clock frequency.
5198 */
5199 void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
5200 {
5201 drm_i915_private_t *dev_priv = dev->dev_private;
5202 struct drm_crtc *crtc = NULL;
5203 struct intel_framebuffer *intel_fb;
5204 struct intel_crtc *intel_crtc;
5205
5206 if (!drm_core_check_feature(dev, DRIVER_MODESET))
5207 return;
5208
5209 if (!dev_priv->busy) {
5210 if (IS_I945G(dev) || IS_I945GM(dev)) {
5211 u32 fw_blc_self;
5212
5213 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5214 fw_blc_self = I915_READ(FW_BLC_SELF);
5215 fw_blc_self &= ~FW_BLC_SELF_EN;
5216 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5217 }
5218 dev_priv->busy = true;
5219 } else
5220 mod_timer(&dev_priv->idle_timer, jiffies +
5221 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5222
5223 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5224 if (!crtc->fb)
5225 continue;
5226
5227 intel_crtc = to_intel_crtc(crtc);
5228 intel_fb = to_intel_framebuffer(crtc->fb);
5229 if (intel_fb->obj == obj) {
5230 if (!intel_crtc->busy) {
5231 if (IS_I945G(dev) || IS_I945GM(dev)) {
5232 u32 fw_blc_self;
5233
5234 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
5235 fw_blc_self = I915_READ(FW_BLC_SELF);
5236 fw_blc_self &= ~FW_BLC_SELF_EN;
5237 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
5238 }
5239 /* Non-busy -> busy, upclock */
5240 intel_increase_pllclock(crtc);
5241 intel_crtc->busy = true;
5242 } else {
5243 /* Busy -> busy, put off timer */
5244 mod_timer(&intel_crtc->idle_timer, jiffies +
5245 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5246 }
5247 }
5248 }
5249 }
5250
5251 static void intel_crtc_destroy(struct drm_crtc *crtc)
5252 {
5253 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5254 struct drm_device *dev = crtc->dev;
5255 struct intel_unpin_work *work;
5256 unsigned long flags;
5257
5258 spin_lock_irqsave(&dev->event_lock, flags);
5259 work = intel_crtc->unpin_work;
5260 intel_crtc->unpin_work = NULL;
5261 spin_unlock_irqrestore(&dev->event_lock, flags);
5262
5263 if (work) {
5264 cancel_work_sync(&work->work);
5265 kfree(work);
5266 }
5267
5268 drm_crtc_cleanup(crtc);
5269
5270 kfree(intel_crtc);
5271 }
5272
5273 static void intel_unpin_work_fn(struct work_struct *__work)
5274 {
5275 struct intel_unpin_work *work =
5276 container_of(__work, struct intel_unpin_work, work);
5277
5278 mutex_lock(&work->dev->struct_mutex);
5279 i915_gem_object_unpin(work->old_fb_obj);
5280 drm_gem_object_unreference(&work->pending_flip_obj->base);
5281 drm_gem_object_unreference(&work->old_fb_obj->base);
5282
5283 mutex_unlock(&work->dev->struct_mutex);
5284 kfree(work);
5285 }
5286
5287 static void do_intel_finish_page_flip(struct drm_device *dev,
5288 struct drm_crtc *crtc)
5289 {
5290 drm_i915_private_t *dev_priv = dev->dev_private;
5291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5292 struct intel_unpin_work *work;
5293 struct drm_i915_gem_object *obj;
5294 struct drm_pending_vblank_event *e;
5295 struct timeval tnow, tvbl;
5296 unsigned long flags;
5297
5298 /* Ignore early vblank irqs */
5299 if (intel_crtc == NULL)
5300 return;
5301
5302 do_gettimeofday(&tnow);
5303
5304 spin_lock_irqsave(&dev->event_lock, flags);
5305 work = intel_crtc->unpin_work;
5306 if (work == NULL || !work->pending) {
5307 spin_unlock_irqrestore(&dev->event_lock, flags);
5308 return;
5309 }
5310
5311 intel_crtc->unpin_work = NULL;
5312
5313 if (work->event) {
5314 e = work->event;
5315 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
5316
5317 /* Called before vblank count and timestamps have
5318 * been updated for the vblank interval of flip
5319 * completion? Need to increment vblank count and
5320 * add one videorefresh duration to returned timestamp
5321 * to account for this. We assume this happened if we
5322 * get called over 0.9 frame durations after the last
5323 * timestamped vblank.
5324 *
5325 * This calculation can not be used with vrefresh rates
5326 * below 5Hz (10Hz to be on the safe side) without
5327 * promoting to 64 integers.
5328 */
5329 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
5330 9 * crtc->framedur_ns) {
5331 e->event.sequence++;
5332 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
5333 crtc->framedur_ns);
5334 }
5335
5336 e->event.tv_sec = tvbl.tv_sec;
5337 e->event.tv_usec = tvbl.tv_usec;
5338
5339 list_add_tail(&e->base.link,
5340 &e->base.file_priv->event_list);
5341 wake_up_interruptible(&e->base.file_priv->event_wait);
5342 }
5343
5344 drm_vblank_put(dev, intel_crtc->pipe);
5345
5346 spin_unlock_irqrestore(&dev->event_lock, flags);
5347
5348 obj = work->old_fb_obj;
5349
5350 atomic_clear_mask(1 << intel_crtc->plane,
5351 &obj->pending_flip.counter);
5352 if (atomic_read(&obj->pending_flip) == 0)
5353 wake_up(&dev_priv->pending_flip_queue);
5354
5355 schedule_work(&work->work);
5356
5357 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
5358 }
5359
5360 void intel_finish_page_flip(struct drm_device *dev, int pipe)
5361 {
5362 drm_i915_private_t *dev_priv = dev->dev_private;
5363 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
5364
5365 do_intel_finish_page_flip(dev, crtc);
5366 }
5367
5368 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
5369 {
5370 drm_i915_private_t *dev_priv = dev->dev_private;
5371 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
5372
5373 do_intel_finish_page_flip(dev, crtc);
5374 }
5375
5376 void intel_prepare_page_flip(struct drm_device *dev, int plane)
5377 {
5378 drm_i915_private_t *dev_priv = dev->dev_private;
5379 struct intel_crtc *intel_crtc =
5380 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5381 unsigned long flags;
5382
5383 spin_lock_irqsave(&dev->event_lock, flags);
5384 if (intel_crtc->unpin_work) {
5385 if ((++intel_crtc->unpin_work->pending) > 1)
5386 DRM_ERROR("Prepared flip multiple times\n");
5387 } else {
5388 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5389 }
5390 spin_unlock_irqrestore(&dev->event_lock, flags);
5391 }
5392
5393 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5394 struct drm_framebuffer *fb,
5395 struct drm_pending_vblank_event *event)
5396 {
5397 struct drm_device *dev = crtc->dev;
5398 struct drm_i915_private *dev_priv = dev->dev_private;
5399 struct intel_framebuffer *intel_fb;
5400 struct drm_i915_gem_object *obj;
5401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5402 struct intel_unpin_work *work;
5403 unsigned long flags, offset;
5404 int pipe = intel_crtc->pipe;
5405 u32 pf, pipesrc;
5406 int ret;
5407
5408 work = kzalloc(sizeof *work, GFP_KERNEL);
5409 if (work == NULL)
5410 return -ENOMEM;
5411
5412 work->event = event;
5413 work->dev = crtc->dev;
5414 intel_fb = to_intel_framebuffer(crtc->fb);
5415 work->old_fb_obj = intel_fb->obj;
5416 INIT_WORK(&work->work, intel_unpin_work_fn);
5417
5418 /* We borrow the event spin lock for protecting unpin_work */
5419 spin_lock_irqsave(&dev->event_lock, flags);
5420 if (intel_crtc->unpin_work) {
5421 spin_unlock_irqrestore(&dev->event_lock, flags);
5422 kfree(work);
5423
5424 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5425 return -EBUSY;
5426 }
5427 intel_crtc->unpin_work = work;
5428 spin_unlock_irqrestore(&dev->event_lock, flags);
5429
5430 intel_fb = to_intel_framebuffer(fb);
5431 obj = intel_fb->obj;
5432
5433 mutex_lock(&dev->struct_mutex);
5434 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
5435 if (ret)
5436 goto cleanup_work;
5437
5438 /* Reference the objects for the scheduled work. */
5439 drm_gem_object_reference(&work->old_fb_obj->base);
5440 drm_gem_object_reference(&obj->base);
5441
5442 crtc->fb = fb;
5443
5444 ret = drm_vblank_get(dev, intel_crtc->pipe);
5445 if (ret)
5446 goto cleanup_objs;
5447
5448 if (IS_GEN3(dev) || IS_GEN2(dev)) {
5449 u32 flip_mask;
5450
5451 /* Can't queue multiple flips, so wait for the previous
5452 * one to finish before executing the next.
5453 */
5454 ret = BEGIN_LP_RING(2);
5455 if (ret)
5456 goto cleanup_objs;
5457
5458 if (intel_crtc->plane)
5459 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5460 else
5461 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5462 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5463 OUT_RING(MI_NOOP);
5464 ADVANCE_LP_RING();
5465 }
5466
5467 work->pending_flip_obj = obj;
5468
5469 work->enable_stall_check = true;
5470
5471 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5472 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5473
5474 ret = BEGIN_LP_RING(4);
5475 if (ret)
5476 goto cleanup_objs;
5477
5478 /* Block clients from rendering to the new back buffer until
5479 * the flip occurs and the object is no longer visible.
5480 */
5481 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
5482
5483 switch (INTEL_INFO(dev)->gen) {
5484 case 2:
5485 OUT_RING(MI_DISPLAY_FLIP |
5486 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5487 OUT_RING(fb->pitch);
5488 OUT_RING(obj->gtt_offset + offset);
5489 OUT_RING(MI_NOOP);
5490 break;
5491
5492 case 3:
5493 OUT_RING(MI_DISPLAY_FLIP_I915 |
5494 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5495 OUT_RING(fb->pitch);
5496 OUT_RING(obj->gtt_offset + offset);
5497 OUT_RING(MI_NOOP);
5498 break;
5499
5500 case 4:
5501 case 5:
5502 /* i965+ uses the linear or tiled offsets from the
5503 * Display Registers (which do not change across a page-flip)
5504 * so we need only reprogram the base address.
5505 */
5506 OUT_RING(MI_DISPLAY_FLIP |
5507 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5508 OUT_RING(fb->pitch);
5509 OUT_RING(obj->gtt_offset | obj->tiling_mode);
5510
5511 /* XXX Enabling the panel-fitter across page-flip is so far
5512 * untested on non-native modes, so ignore it for now.
5513 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5514 */
5515 pf = 0;
5516 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5517 OUT_RING(pf | pipesrc);
5518 break;
5519
5520 case 6:
5521 OUT_RING(MI_DISPLAY_FLIP |
5522 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5523 OUT_RING(fb->pitch | obj->tiling_mode);
5524 OUT_RING(obj->gtt_offset);
5525
5526 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5527 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5528 OUT_RING(pf | pipesrc);
5529 break;
5530 }
5531 ADVANCE_LP_RING();
5532
5533 mutex_unlock(&dev->struct_mutex);
5534
5535 trace_i915_flip_request(intel_crtc->plane, obj);
5536
5537 return 0;
5538
5539 cleanup_objs:
5540 drm_gem_object_unreference(&work->old_fb_obj->base);
5541 drm_gem_object_unreference(&obj->base);
5542 cleanup_work:
5543 mutex_unlock(&dev->struct_mutex);
5544
5545 spin_lock_irqsave(&dev->event_lock, flags);
5546 intel_crtc->unpin_work = NULL;
5547 spin_unlock_irqrestore(&dev->event_lock, flags);
5548
5549 kfree(work);
5550
5551 return ret;
5552 }
5553
5554 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5555 .dpms = intel_crtc_dpms,
5556 .mode_fixup = intel_crtc_mode_fixup,
5557 .mode_set = intel_crtc_mode_set,
5558 .mode_set_base = intel_pipe_set_base,
5559 .mode_set_base_atomic = intel_pipe_set_base_atomic,
5560 .load_lut = intel_crtc_load_lut,
5561 .disable = intel_crtc_disable,
5562 };
5563
5564 static const struct drm_crtc_funcs intel_crtc_funcs = {
5565 .cursor_set = intel_crtc_cursor_set,
5566 .cursor_move = intel_crtc_cursor_move,
5567 .gamma_set = intel_crtc_gamma_set,
5568 .set_config = drm_crtc_helper_set_config,
5569 .destroy = intel_crtc_destroy,
5570 .page_flip = intel_crtc_page_flip,
5571 };
5572
5573 static void intel_sanitize_modesetting(struct drm_device *dev,
5574 int pipe, int plane)
5575 {
5576 struct drm_i915_private *dev_priv = dev->dev_private;
5577 u32 reg, val;
5578
5579 if (HAS_PCH_SPLIT(dev))
5580 return;
5581
5582 /* Who knows what state these registers were left in by the BIOS or
5583 * grub?
5584 *
5585 * If we leave the registers in a conflicting state (e.g. with the
5586 * display plane reading from the other pipe than the one we intend
5587 * to use) then when we attempt to teardown the active mode, we will
5588 * not disable the pipes and planes in the correct order -- leaving
5589 * a plane reading from a disabled pipe and possibly leading to
5590 * undefined behaviour.
5591 */
5592
5593 reg = DSPCNTR(plane);
5594 val = I915_READ(reg);
5595
5596 if ((val & DISPLAY_PLANE_ENABLE) == 0)
5597 return;
5598 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
5599 return;
5600
5601 /* This display plane is active and attached to the other CPU pipe. */
5602 pipe = !pipe;
5603
5604 /* Disable the plane and wait for it to stop reading from the pipe. */
5605 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
5606 intel_flush_display_plane(dev, plane);
5607
5608 if (IS_GEN2(dev))
5609 intel_wait_for_vblank(dev, pipe);
5610
5611 if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
5612 return;
5613
5614 /* Switch off the pipe. */
5615 reg = PIPECONF(pipe);
5616 val = I915_READ(reg);
5617 if (val & PIPECONF_ENABLE) {
5618 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
5619 intel_wait_for_pipe_off(dev, pipe);
5620 }
5621 }
5622
5623 static void intel_crtc_init(struct drm_device *dev, int pipe)
5624 {
5625 drm_i915_private_t *dev_priv = dev->dev_private;
5626 struct intel_crtc *intel_crtc;
5627 int i;
5628
5629 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5630 if (intel_crtc == NULL)
5631 return;
5632
5633 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5634
5635 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5636 for (i = 0; i < 256; i++) {
5637 intel_crtc->lut_r[i] = i;
5638 intel_crtc->lut_g[i] = i;
5639 intel_crtc->lut_b[i] = i;
5640 }
5641
5642 /* Swap pipes & planes for FBC on pre-965 */
5643 intel_crtc->pipe = pipe;
5644 intel_crtc->plane = pipe;
5645 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
5646 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5647 intel_crtc->plane = !pipe;
5648 }
5649
5650 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5651 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5652 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5653 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5654
5655 intel_crtc->cursor_addr = 0;
5656 intel_crtc->dpms_mode = -1;
5657 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5658
5659 if (HAS_PCH_SPLIT(dev)) {
5660 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5661 intel_helper_funcs.commit = ironlake_crtc_commit;
5662 } else {
5663 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5664 intel_helper_funcs.commit = i9xx_crtc_commit;
5665 }
5666
5667 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5668
5669 intel_crtc->busy = false;
5670
5671 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5672 (unsigned long)intel_crtc);
5673
5674 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
5675 }
5676
5677 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5678 struct drm_file *file)
5679 {
5680 drm_i915_private_t *dev_priv = dev->dev_private;
5681 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5682 struct drm_mode_object *drmmode_obj;
5683 struct intel_crtc *crtc;
5684
5685 if (!dev_priv) {
5686 DRM_ERROR("called with no initialization\n");
5687 return -EINVAL;
5688 }
5689
5690 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5691 DRM_MODE_OBJECT_CRTC);
5692
5693 if (!drmmode_obj) {
5694 DRM_ERROR("no such CRTC id\n");
5695 return -EINVAL;
5696 }
5697
5698 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5699 pipe_from_crtc_id->pipe = crtc->pipe;
5700
5701 return 0;
5702 }
5703
5704 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5705 {
5706 struct intel_encoder *encoder;
5707 int index_mask = 0;
5708 int entry = 0;
5709
5710 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5711 if (type_mask & encoder->clone_mask)
5712 index_mask |= (1 << entry);
5713 entry++;
5714 }
5715
5716 return index_mask;
5717 }
5718
5719 static bool has_edp_a(struct drm_device *dev)
5720 {
5721 struct drm_i915_private *dev_priv = dev->dev_private;
5722
5723 if (!IS_MOBILE(dev))
5724 return false;
5725
5726 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
5727 return false;
5728
5729 if (IS_GEN5(dev) &&
5730 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
5731 return false;
5732
5733 return true;
5734 }
5735
5736 static void intel_setup_outputs(struct drm_device *dev)
5737 {
5738 struct drm_i915_private *dev_priv = dev->dev_private;
5739 struct intel_encoder *encoder;
5740 bool dpd_is_edp = false;
5741 bool has_lvds = false;
5742
5743 if (IS_MOBILE(dev) && !IS_I830(dev))
5744 has_lvds = intel_lvds_init(dev);
5745 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
5746 /* disable the panel fitter on everything but LVDS */
5747 I915_WRITE(PFIT_CONTROL, 0);
5748 }
5749
5750 if (HAS_PCH_SPLIT(dev)) {
5751 dpd_is_edp = intel_dpd_is_edp(dev);
5752
5753 if (has_edp_a(dev))
5754 intel_dp_init(dev, DP_A);
5755
5756 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5757 intel_dp_init(dev, PCH_DP_D);
5758 }
5759
5760 intel_crt_init(dev);
5761
5762 if (HAS_PCH_SPLIT(dev)) {
5763 int found;
5764
5765 if (I915_READ(HDMIB) & PORT_DETECTED) {
5766 /* PCH SDVOB multiplex with HDMIB */
5767 found = intel_sdvo_init(dev, PCH_SDVOB);
5768 if (!found)
5769 intel_hdmi_init(dev, HDMIB);
5770 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5771 intel_dp_init(dev, PCH_DP_B);
5772 }
5773
5774 if (I915_READ(HDMIC) & PORT_DETECTED)
5775 intel_hdmi_init(dev, HDMIC);
5776
5777 if (I915_READ(HDMID) & PORT_DETECTED)
5778 intel_hdmi_init(dev, HDMID);
5779
5780 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5781 intel_dp_init(dev, PCH_DP_C);
5782
5783 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5784 intel_dp_init(dev, PCH_DP_D);
5785
5786 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5787 bool found = false;
5788
5789 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5790 DRM_DEBUG_KMS("probing SDVOB\n");
5791 found = intel_sdvo_init(dev, SDVOB);
5792 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5793 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5794 intel_hdmi_init(dev, SDVOB);
5795 }
5796
5797 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5798 DRM_DEBUG_KMS("probing DP_B\n");
5799 intel_dp_init(dev, DP_B);
5800 }
5801 }
5802
5803 /* Before G4X SDVOC doesn't have its own detect register */
5804
5805 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5806 DRM_DEBUG_KMS("probing SDVOC\n");
5807 found = intel_sdvo_init(dev, SDVOC);
5808 }
5809
5810 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5811
5812 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5813 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5814 intel_hdmi_init(dev, SDVOC);
5815 }
5816 if (SUPPORTS_INTEGRATED_DP(dev)) {
5817 DRM_DEBUG_KMS("probing DP_C\n");
5818 intel_dp_init(dev, DP_C);
5819 }
5820 }
5821
5822 if (SUPPORTS_INTEGRATED_DP(dev) &&
5823 (I915_READ(DP_D) & DP_DETECTED)) {
5824 DRM_DEBUG_KMS("probing DP_D\n");
5825 intel_dp_init(dev, DP_D);
5826 }
5827 } else if (IS_GEN2(dev))
5828 intel_dvo_init(dev);
5829
5830 if (SUPPORTS_TV(dev))
5831 intel_tv_init(dev);
5832
5833 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5834 encoder->base.possible_crtcs = encoder->crtc_mask;
5835 encoder->base.possible_clones =
5836 intel_encoder_clones(dev, encoder->clone_mask);
5837 }
5838
5839 intel_panel_setup_backlight(dev);
5840 }
5841
5842 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5843 {
5844 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5845
5846 drm_framebuffer_cleanup(fb);
5847 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
5848
5849 kfree(intel_fb);
5850 }
5851
5852 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5853 struct drm_file *file,
5854 unsigned int *handle)
5855 {
5856 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5857 struct drm_i915_gem_object *obj = intel_fb->obj;
5858
5859 return drm_gem_handle_create(file, &obj->base, handle);
5860 }
5861
5862 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5863 .destroy = intel_user_framebuffer_destroy,
5864 .create_handle = intel_user_framebuffer_create_handle,
5865 };
5866
5867 int intel_framebuffer_init(struct drm_device *dev,
5868 struct intel_framebuffer *intel_fb,
5869 struct drm_mode_fb_cmd *mode_cmd,
5870 struct drm_i915_gem_object *obj)
5871 {
5872 int ret;
5873
5874 if (obj->tiling_mode == I915_TILING_Y)
5875 return -EINVAL;
5876
5877 if (mode_cmd->pitch & 63)
5878 return -EINVAL;
5879
5880 switch (mode_cmd->bpp) {
5881 case 8:
5882 case 16:
5883 case 24:
5884 case 32:
5885 break;
5886 default:
5887 return -EINVAL;
5888 }
5889
5890 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5891 if (ret) {
5892 DRM_ERROR("framebuffer init failed %d\n", ret);
5893 return ret;
5894 }
5895
5896 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5897 intel_fb->obj = obj;
5898 return 0;
5899 }
5900
5901 static struct drm_framebuffer *
5902 intel_user_framebuffer_create(struct drm_device *dev,
5903 struct drm_file *filp,
5904 struct drm_mode_fb_cmd *mode_cmd)
5905 {
5906 struct drm_i915_gem_object *obj;
5907 struct intel_framebuffer *intel_fb;
5908 int ret;
5909
5910 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
5911 if (!obj)
5912 return ERR_PTR(-ENOENT);
5913
5914 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5915 if (!intel_fb)
5916 return ERR_PTR(-ENOMEM);
5917
5918 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5919 if (ret) {
5920 drm_gem_object_unreference_unlocked(&obj->base);
5921 kfree(intel_fb);
5922 return ERR_PTR(ret);
5923 }
5924
5925 return &intel_fb->base;
5926 }
5927
5928 static const struct drm_mode_config_funcs intel_mode_funcs = {
5929 .fb_create = intel_user_framebuffer_create,
5930 .output_poll_changed = intel_fb_output_poll_changed,
5931 };
5932
5933 static struct drm_i915_gem_object *
5934 intel_alloc_context_page(struct drm_device *dev)
5935 {
5936 struct drm_i915_gem_object *ctx;
5937 int ret;
5938
5939 ctx = i915_gem_alloc_object(dev, 4096);
5940 if (!ctx) {
5941 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5942 return NULL;
5943 }
5944
5945 mutex_lock(&dev->struct_mutex);
5946 ret = i915_gem_object_pin(ctx, 4096, true);
5947 if (ret) {
5948 DRM_ERROR("failed to pin power context: %d\n", ret);
5949 goto err_unref;
5950 }
5951
5952 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5953 if (ret) {
5954 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5955 goto err_unpin;
5956 }
5957 mutex_unlock(&dev->struct_mutex);
5958
5959 return ctx;
5960
5961 err_unpin:
5962 i915_gem_object_unpin(ctx);
5963 err_unref:
5964 drm_gem_object_unreference(&ctx->base);
5965 mutex_unlock(&dev->struct_mutex);
5966 return NULL;
5967 }
5968
5969 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5970 {
5971 struct drm_i915_private *dev_priv = dev->dev_private;
5972 u16 rgvswctl;
5973
5974 rgvswctl = I915_READ16(MEMSWCTL);
5975 if (rgvswctl & MEMCTL_CMD_STS) {
5976 DRM_DEBUG("gpu busy, RCS change rejected\n");
5977 return false; /* still busy with another command */
5978 }
5979
5980 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5981 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5982 I915_WRITE16(MEMSWCTL, rgvswctl);
5983 POSTING_READ16(MEMSWCTL);
5984
5985 rgvswctl |= MEMCTL_CMD_STS;
5986 I915_WRITE16(MEMSWCTL, rgvswctl);
5987
5988 return true;
5989 }
5990
5991 void ironlake_enable_drps(struct drm_device *dev)
5992 {
5993 struct drm_i915_private *dev_priv = dev->dev_private;
5994 u32 rgvmodectl = I915_READ(MEMMODECTL);
5995 u8 fmax, fmin, fstart, vstart;
5996
5997 /* Enable temp reporting */
5998 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5999 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
6000
6001 /* 100ms RC evaluation intervals */
6002 I915_WRITE(RCUPEI, 100000);
6003 I915_WRITE(RCDNEI, 100000);
6004
6005 /* Set max/min thresholds to 90ms and 80ms respectively */
6006 I915_WRITE(RCBMAXAVG, 90000);
6007 I915_WRITE(RCBMINAVG, 80000);
6008
6009 I915_WRITE(MEMIHYST, 1);
6010
6011 /* Set up min, max, and cur for interrupt handling */
6012 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
6013 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
6014 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
6015 MEMMODE_FSTART_SHIFT;
6016
6017 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
6018 PXVFREQ_PX_SHIFT;
6019
6020 dev_priv->fmax = fmax; /* IPS callback will increase this */
6021 dev_priv->fstart = fstart;
6022
6023 dev_priv->max_delay = fstart;
6024 dev_priv->min_delay = fmin;
6025 dev_priv->cur_delay = fstart;
6026
6027 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
6028 fmax, fmin, fstart);
6029
6030 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
6031
6032 /*
6033 * Interrupts will be enabled in ironlake_irq_postinstall
6034 */
6035
6036 I915_WRITE(VIDSTART, vstart);
6037 POSTING_READ(VIDSTART);
6038
6039 rgvmodectl |= MEMMODE_SWMODE_EN;
6040 I915_WRITE(MEMMODECTL, rgvmodectl);
6041
6042 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
6043 DRM_ERROR("stuck trying to change perf mode\n");
6044 msleep(1);
6045
6046 ironlake_set_drps(dev, fstart);
6047
6048 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
6049 I915_READ(0x112e0);
6050 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
6051 dev_priv->last_count2 = I915_READ(0x112f4);
6052 getrawmonotonic(&dev_priv->last_time2);
6053 }
6054
6055 void ironlake_disable_drps(struct drm_device *dev)
6056 {
6057 struct drm_i915_private *dev_priv = dev->dev_private;
6058 u16 rgvswctl = I915_READ16(MEMSWCTL);
6059
6060 /* Ack interrupts, disable EFC interrupt */
6061 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
6062 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
6063 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
6064 I915_WRITE(DEIIR, DE_PCU_EVENT);
6065 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
6066
6067 /* Go back to the starting frequency */
6068 ironlake_set_drps(dev, dev_priv->fstart);
6069 msleep(1);
6070 rgvswctl |= MEMCTL_CMD_STS;
6071 I915_WRITE(MEMSWCTL, rgvswctl);
6072 msleep(1);
6073
6074 }
6075
6076 void gen6_set_rps(struct drm_device *dev, u8 val)
6077 {
6078 struct drm_i915_private *dev_priv = dev->dev_private;
6079 u32 swreq;
6080
6081 swreq = (val & 0x3ff) << 25;
6082 I915_WRITE(GEN6_RPNSWREQ, swreq);
6083 }
6084
6085 void gen6_disable_rps(struct drm_device *dev)
6086 {
6087 struct drm_i915_private *dev_priv = dev->dev_private;
6088
6089 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
6090 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
6091 I915_WRITE(GEN6_PMIER, 0);
6092 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
6093 }
6094
6095 static unsigned long intel_pxfreq(u32 vidfreq)
6096 {
6097 unsigned long freq;
6098 int div = (vidfreq & 0x3f0000) >> 16;
6099 int post = (vidfreq & 0x3000) >> 12;
6100 int pre = (vidfreq & 0x7);
6101
6102 if (!pre)
6103 return 0;
6104
6105 freq = ((div * 133333) / ((1<<post) * pre));
6106
6107 return freq;
6108 }
6109
6110 void intel_init_emon(struct drm_device *dev)
6111 {
6112 struct drm_i915_private *dev_priv = dev->dev_private;
6113 u32 lcfuse;
6114 u8 pxw[16];
6115 int i;
6116
6117 /* Disable to program */
6118 I915_WRITE(ECR, 0);
6119 POSTING_READ(ECR);
6120
6121 /* Program energy weights for various events */
6122 I915_WRITE(SDEW, 0x15040d00);
6123 I915_WRITE(CSIEW0, 0x007f0000);
6124 I915_WRITE(CSIEW1, 0x1e220004);
6125 I915_WRITE(CSIEW2, 0x04000004);
6126
6127 for (i = 0; i < 5; i++)
6128 I915_WRITE(PEW + (i * 4), 0);
6129 for (i = 0; i < 3; i++)
6130 I915_WRITE(DEW + (i * 4), 0);
6131
6132 /* Program P-state weights to account for frequency power adjustment */
6133 for (i = 0; i < 16; i++) {
6134 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6135 unsigned long freq = intel_pxfreq(pxvidfreq);
6136 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6137 PXVFREQ_PX_SHIFT;
6138 unsigned long val;
6139
6140 val = vid * vid;
6141 val *= (freq / 1000);
6142 val *= 255;
6143 val /= (127*127*900);
6144 if (val > 0xff)
6145 DRM_ERROR("bad pxval: %ld\n", val);
6146 pxw[i] = val;
6147 }
6148 /* Render standby states get 0 weight */
6149 pxw[14] = 0;
6150 pxw[15] = 0;
6151
6152 for (i = 0; i < 4; i++) {
6153 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6154 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6155 I915_WRITE(PXW + (i * 4), val);
6156 }
6157
6158 /* Adjust magic regs to magic values (more experimental results) */
6159 I915_WRITE(OGW0, 0);
6160 I915_WRITE(OGW1, 0);
6161 I915_WRITE(EG0, 0x00007f00);
6162 I915_WRITE(EG1, 0x0000000e);
6163 I915_WRITE(EG2, 0x000e0000);
6164 I915_WRITE(EG3, 0x68000300);
6165 I915_WRITE(EG4, 0x42000000);
6166 I915_WRITE(EG5, 0x00140031);
6167 I915_WRITE(EG6, 0);
6168 I915_WRITE(EG7, 0);
6169
6170 for (i = 0; i < 8; i++)
6171 I915_WRITE(PXWL + (i * 4), 0);
6172
6173 /* Enable PMON + select events */
6174 I915_WRITE(ECR, 0x80000019);
6175
6176 lcfuse = I915_READ(LCFUSE02);
6177
6178 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
6179 }
6180
6181 void gen6_enable_rps(struct drm_i915_private *dev_priv)
6182 {
6183 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
6184 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
6185 u32 pcu_mbox;
6186 int cur_freq, min_freq, max_freq;
6187 int i;
6188
6189 /* Here begins a magic sequence of register writes to enable
6190 * auto-downclocking.
6191 *
6192 * Perhaps there might be some value in exposing these to
6193 * userspace...
6194 */
6195 I915_WRITE(GEN6_RC_STATE, 0);
6196 __gen6_force_wake_get(dev_priv);
6197
6198 /* disable the counters and set deterministic thresholds */
6199 I915_WRITE(GEN6_RC_CONTROL, 0);
6200
6201 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
6202 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
6203 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
6204 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6205 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6206
6207 for (i = 0; i < I915_NUM_RINGS; i++)
6208 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
6209
6210 I915_WRITE(GEN6_RC_SLEEP, 0);
6211 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
6212 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
6213 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
6214 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
6215
6216 I915_WRITE(GEN6_RC_CONTROL,
6217 GEN6_RC_CTL_RC6p_ENABLE |
6218 GEN6_RC_CTL_RC6_ENABLE |
6219 GEN6_RC_CTL_EI_MODE(1) |
6220 GEN6_RC_CTL_HW_ENABLE);
6221
6222 I915_WRITE(GEN6_RPNSWREQ,
6223 GEN6_FREQUENCY(10) |
6224 GEN6_OFFSET(0) |
6225 GEN6_AGGRESSIVE_TURBO);
6226 I915_WRITE(GEN6_RC_VIDEO_FREQ,
6227 GEN6_FREQUENCY(12));
6228
6229 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
6230 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
6231 18 << 24 |
6232 6 << 16);
6233 I915_WRITE(GEN6_RP_UP_THRESHOLD, 90000);
6234 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 100000);
6235 I915_WRITE(GEN6_RP_UP_EI, 100000);
6236 I915_WRITE(GEN6_RP_DOWN_EI, 300000);
6237 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6238 I915_WRITE(GEN6_RP_CONTROL,
6239 GEN6_RP_MEDIA_TURBO |
6240 GEN6_RP_USE_NORMAL_FREQ |
6241 GEN6_RP_MEDIA_IS_GFX |
6242 GEN6_RP_ENABLE |
6243 GEN6_RP_UP_BUSY_MAX |
6244 GEN6_RP_DOWN_BUSY_MIN);
6245
6246 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6247 500))
6248 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6249
6250 I915_WRITE(GEN6_PCODE_DATA, 0);
6251 I915_WRITE(GEN6_PCODE_MAILBOX,
6252 GEN6_PCODE_READY |
6253 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
6254 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6255 500))
6256 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6257
6258 min_freq = (rp_state_cap & 0xff0000) >> 16;
6259 max_freq = rp_state_cap & 0xff;
6260 cur_freq = (gt_perf_status & 0xff00) >> 8;
6261
6262 /* Check for overclock support */
6263 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6264 500))
6265 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
6266 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
6267 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
6268 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6269 500))
6270 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
6271 if (pcu_mbox & (1<<31)) { /* OC supported */
6272 max_freq = pcu_mbox & 0xff;
6273 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 100);
6274 }
6275
6276 /* In units of 100MHz */
6277 dev_priv->max_delay = max_freq;
6278 dev_priv->min_delay = min_freq;
6279 dev_priv->cur_delay = cur_freq;
6280
6281 /* requires MSI enabled */
6282 I915_WRITE(GEN6_PMIER,
6283 GEN6_PM_MBOX_EVENT |
6284 GEN6_PM_THERMAL_EVENT |
6285 GEN6_PM_RP_DOWN_TIMEOUT |
6286 GEN6_PM_RP_UP_THRESHOLD |
6287 GEN6_PM_RP_DOWN_THRESHOLD |
6288 GEN6_PM_RP_UP_EI_EXPIRED |
6289 GEN6_PM_RP_DOWN_EI_EXPIRED);
6290 I915_WRITE(GEN6_PMIMR, 0);
6291 /* enable all PM interrupts */
6292 I915_WRITE(GEN6_PMINTRMSK, 0);
6293
6294 __gen6_force_wake_put(dev_priv);
6295 }
6296
6297 void intel_enable_clock_gating(struct drm_device *dev)
6298 {
6299 struct drm_i915_private *dev_priv = dev->dev_private;
6300
6301 /*
6302 * Disable clock gating reported to work incorrectly according to the
6303 * specs, but enable as much else as we can.
6304 */
6305 if (HAS_PCH_SPLIT(dev)) {
6306 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
6307
6308 if (IS_GEN5(dev)) {
6309 /* Required for FBC */
6310 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
6311 DPFCRUNIT_CLOCK_GATE_DISABLE |
6312 DPFDUNIT_CLOCK_GATE_DISABLE;
6313 /* Required for CxSR */
6314 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
6315
6316 I915_WRITE(PCH_3DCGDIS0,
6317 MARIUNIT_CLOCK_GATE_DISABLE |
6318 SVSMUNIT_CLOCK_GATE_DISABLE);
6319 I915_WRITE(PCH_3DCGDIS1,
6320 VFMUNIT_CLOCK_GATE_DISABLE);
6321 }
6322
6323 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
6324
6325 /*
6326 * On Ibex Peak and Cougar Point, we need to disable clock
6327 * gating for the panel power sequencer or it will fail to
6328 * start up when no ports are active.
6329 */
6330 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6331
6332 /*
6333 * According to the spec the following bits should be set in
6334 * order to enable memory self-refresh
6335 * The bit 22/21 of 0x42004
6336 * The bit 5 of 0x42020
6337 * The bit 15 of 0x45000
6338 */
6339 if (IS_GEN5(dev)) {
6340 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6341 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6342 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6343 I915_WRITE(ILK_DSPCLK_GATE,
6344 (I915_READ(ILK_DSPCLK_GATE) |
6345 ILK_DPARB_CLK_GATE));
6346 I915_WRITE(DISP_ARB_CTL,
6347 (I915_READ(DISP_ARB_CTL) |
6348 DISP_FBC_WM_DIS));
6349 I915_WRITE(WM3_LP_ILK, 0);
6350 I915_WRITE(WM2_LP_ILK, 0);
6351 I915_WRITE(WM1_LP_ILK, 0);
6352 }
6353 /*
6354 * Based on the document from hardware guys the following bits
6355 * should be set unconditionally in order to enable FBC.
6356 * The bit 22 of 0x42000
6357 * The bit 22 of 0x42004
6358 * The bit 7,8,9 of 0x42020.
6359 */
6360 if (IS_IRONLAKE_M(dev)) {
6361 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6362 I915_READ(ILK_DISPLAY_CHICKEN1) |
6363 ILK_FBCQ_DIS);
6364 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6365 I915_READ(ILK_DISPLAY_CHICKEN2) |
6366 ILK_DPARB_GATE);
6367 I915_WRITE(ILK_DSPCLK_GATE,
6368 I915_READ(ILK_DSPCLK_GATE) |
6369 ILK_DPFC_DIS1 |
6370 ILK_DPFC_DIS2 |
6371 ILK_CLK_FBC);
6372 }
6373
6374 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6375 I915_READ(ILK_DISPLAY_CHICKEN2) |
6376 ILK_ELPIN_409_SELECT);
6377
6378 if (IS_GEN5(dev)) {
6379 I915_WRITE(_3D_CHICKEN2,
6380 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6381 _3D_CHICKEN2_WM_READ_PIPELINED);
6382 }
6383
6384 if (IS_GEN6(dev)) {
6385 I915_WRITE(WM3_LP_ILK, 0);
6386 I915_WRITE(WM2_LP_ILK, 0);
6387 I915_WRITE(WM1_LP_ILK, 0);
6388
6389 /*
6390 * According to the spec the following bits should be
6391 * set in order to enable memory self-refresh and fbc:
6392 * The bit21 and bit22 of 0x42000
6393 * The bit21 and bit22 of 0x42004
6394 * The bit5 and bit7 of 0x42020
6395 * The bit14 of 0x70180
6396 * The bit14 of 0x71180
6397 */
6398 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6399 I915_READ(ILK_DISPLAY_CHICKEN1) |
6400 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6401 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6402 I915_READ(ILK_DISPLAY_CHICKEN2) |
6403 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6404 I915_WRITE(ILK_DSPCLK_GATE,
6405 I915_READ(ILK_DSPCLK_GATE) |
6406 ILK_DPARB_CLK_GATE |
6407 ILK_DPFD_CLK_GATE);
6408
6409 I915_WRITE(DSPACNTR,
6410 I915_READ(DSPACNTR) |
6411 DISPPLANE_TRICKLE_FEED_DISABLE);
6412 I915_WRITE(DSPBCNTR,
6413 I915_READ(DSPBCNTR) |
6414 DISPPLANE_TRICKLE_FEED_DISABLE);
6415 }
6416 } else if (IS_G4X(dev)) {
6417 uint32_t dspclk_gate;
6418 I915_WRITE(RENCLK_GATE_D1, 0);
6419 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6420 GS_UNIT_CLOCK_GATE_DISABLE |
6421 CL_UNIT_CLOCK_GATE_DISABLE);
6422 I915_WRITE(RAMCLK_GATE_D, 0);
6423 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6424 OVRUNIT_CLOCK_GATE_DISABLE |
6425 OVCUNIT_CLOCK_GATE_DISABLE;
6426 if (IS_GM45(dev))
6427 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6428 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6429 } else if (IS_CRESTLINE(dev)) {
6430 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6431 I915_WRITE(RENCLK_GATE_D2, 0);
6432 I915_WRITE(DSPCLK_GATE_D, 0);
6433 I915_WRITE(RAMCLK_GATE_D, 0);
6434 I915_WRITE16(DEUC, 0);
6435 } else if (IS_BROADWATER(dev)) {
6436 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6437 I965_RCC_CLOCK_GATE_DISABLE |
6438 I965_RCPB_CLOCK_GATE_DISABLE |
6439 I965_ISC_CLOCK_GATE_DISABLE |
6440 I965_FBC_CLOCK_GATE_DISABLE);
6441 I915_WRITE(RENCLK_GATE_D2, 0);
6442 } else if (IS_GEN3(dev)) {
6443 u32 dstate = I915_READ(D_STATE);
6444
6445 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6446 DSTATE_DOT_CLOCK_GATING;
6447 I915_WRITE(D_STATE, dstate);
6448 } else if (IS_I85X(dev) || IS_I865G(dev)) {
6449 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6450 } else if (IS_I830(dev)) {
6451 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6452 }
6453 }
6454
6455 void intel_disable_clock_gating(struct drm_device *dev)
6456 {
6457 struct drm_i915_private *dev_priv = dev->dev_private;
6458
6459 if (dev_priv->renderctx) {
6460 struct drm_i915_gem_object *obj = dev_priv->renderctx;
6461
6462 I915_WRITE(CCID, 0);
6463 POSTING_READ(CCID);
6464
6465 i915_gem_object_unpin(obj);
6466 drm_gem_object_unreference(&obj->base);
6467 dev_priv->renderctx = NULL;
6468 }
6469
6470 if (dev_priv->pwrctx) {
6471 struct drm_i915_gem_object *obj = dev_priv->pwrctx;
6472
6473 I915_WRITE(PWRCTXA, 0);
6474 POSTING_READ(PWRCTXA);
6475
6476 i915_gem_object_unpin(obj);
6477 drm_gem_object_unreference(&obj->base);
6478 dev_priv->pwrctx = NULL;
6479 }
6480 }
6481
6482 static void ironlake_disable_rc6(struct drm_device *dev)
6483 {
6484 struct drm_i915_private *dev_priv = dev->dev_private;
6485
6486 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
6487 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
6488 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
6489 10);
6490 POSTING_READ(CCID);
6491 I915_WRITE(PWRCTXA, 0);
6492 POSTING_READ(PWRCTXA);
6493 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6494 POSTING_READ(RSTDBYCTL);
6495 i915_gem_object_unpin(dev_priv->renderctx);
6496 drm_gem_object_unreference(&dev_priv->renderctx->base);
6497 dev_priv->renderctx = NULL;
6498 i915_gem_object_unpin(dev_priv->pwrctx);
6499 drm_gem_object_unreference(&dev_priv->pwrctx->base);
6500 dev_priv->pwrctx = NULL;
6501 }
6502
6503 void ironlake_enable_rc6(struct drm_device *dev)
6504 {
6505 struct drm_i915_private *dev_priv = dev->dev_private;
6506 int ret;
6507
6508 /*
6509 * GPU can automatically power down the render unit if given a page
6510 * to save state.
6511 */
6512 ret = BEGIN_LP_RING(6);
6513 if (ret) {
6514 ironlake_disable_rc6(dev);
6515 return;
6516 }
6517 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
6518 OUT_RING(MI_SET_CONTEXT);
6519 OUT_RING(dev_priv->renderctx->gtt_offset |
6520 MI_MM_SPACE_GTT |
6521 MI_SAVE_EXT_STATE_EN |
6522 MI_RESTORE_EXT_STATE_EN |
6523 MI_RESTORE_INHIBIT);
6524 OUT_RING(MI_SUSPEND_FLUSH);
6525 OUT_RING(MI_NOOP);
6526 OUT_RING(MI_FLUSH);
6527 ADVANCE_LP_RING();
6528
6529 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
6530 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
6531 }
6532
6533 /* Set up chip specific display functions */
6534 static void intel_init_display(struct drm_device *dev)
6535 {
6536 struct drm_i915_private *dev_priv = dev->dev_private;
6537
6538 /* We always want a DPMS function */
6539 if (HAS_PCH_SPLIT(dev))
6540 dev_priv->display.dpms = ironlake_crtc_dpms;
6541 else
6542 dev_priv->display.dpms = i9xx_crtc_dpms;
6543
6544 if (I915_HAS_FBC(dev)) {
6545 if (HAS_PCH_SPLIT(dev)) {
6546 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
6547 dev_priv->display.enable_fbc = ironlake_enable_fbc;
6548 dev_priv->display.disable_fbc = ironlake_disable_fbc;
6549 } else if (IS_GM45(dev)) {
6550 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
6551 dev_priv->display.enable_fbc = g4x_enable_fbc;
6552 dev_priv->display.disable_fbc = g4x_disable_fbc;
6553 } else if (IS_CRESTLINE(dev)) {
6554 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
6555 dev_priv->display.enable_fbc = i8xx_enable_fbc;
6556 dev_priv->display.disable_fbc = i8xx_disable_fbc;
6557 }
6558 /* 855GM needs testing */
6559 }
6560
6561 /* Returns the core display clock speed */
6562 if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
6563 dev_priv->display.get_display_clock_speed =
6564 i945_get_display_clock_speed;
6565 else if (IS_I915G(dev))
6566 dev_priv->display.get_display_clock_speed =
6567 i915_get_display_clock_speed;
6568 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
6569 dev_priv->display.get_display_clock_speed =
6570 i9xx_misc_get_display_clock_speed;
6571 else if (IS_I915GM(dev))
6572 dev_priv->display.get_display_clock_speed =
6573 i915gm_get_display_clock_speed;
6574 else if (IS_I865G(dev))
6575 dev_priv->display.get_display_clock_speed =
6576 i865_get_display_clock_speed;
6577 else if (IS_I85X(dev))
6578 dev_priv->display.get_display_clock_speed =
6579 i855_get_display_clock_speed;
6580 else /* 852, 830 */
6581 dev_priv->display.get_display_clock_speed =
6582 i830_get_display_clock_speed;
6583
6584 /* For FIFO watermark updates */
6585 if (HAS_PCH_SPLIT(dev)) {
6586 if (IS_GEN5(dev)) {
6587 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
6588 dev_priv->display.update_wm = ironlake_update_wm;
6589 else {
6590 DRM_DEBUG_KMS("Failed to get proper latency. "
6591 "Disable CxSR\n");
6592 dev_priv->display.update_wm = NULL;
6593 }
6594 } else if (IS_GEN6(dev)) {
6595 if (SNB_READ_WM0_LATENCY()) {
6596 dev_priv->display.update_wm = sandybridge_update_wm;
6597 } else {
6598 DRM_DEBUG_KMS("Failed to read display plane latency. "
6599 "Disable CxSR\n");
6600 dev_priv->display.update_wm = NULL;
6601 }
6602 } else
6603 dev_priv->display.update_wm = NULL;
6604 } else if (IS_PINEVIEW(dev)) {
6605 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6606 dev_priv->is_ddr3,
6607 dev_priv->fsb_freq,
6608 dev_priv->mem_freq)) {
6609 DRM_INFO("failed to find known CxSR latency "
6610 "(found ddr%s fsb freq %d, mem freq %d), "
6611 "disabling CxSR\n",
6612 (dev_priv->is_ddr3 == 1) ? "3": "2",
6613 dev_priv->fsb_freq, dev_priv->mem_freq);
6614 /* Disable CxSR and never update its watermark again */
6615 pineview_disable_cxsr(dev);
6616 dev_priv->display.update_wm = NULL;
6617 } else
6618 dev_priv->display.update_wm = pineview_update_wm;
6619 } else if (IS_G4X(dev))
6620 dev_priv->display.update_wm = g4x_update_wm;
6621 else if (IS_GEN4(dev))
6622 dev_priv->display.update_wm = i965_update_wm;
6623 else if (IS_GEN3(dev)) {
6624 dev_priv->display.update_wm = i9xx_update_wm;
6625 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6626 } else if (IS_I85X(dev)) {
6627 dev_priv->display.update_wm = i9xx_update_wm;
6628 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6629 } else {
6630 dev_priv->display.update_wm = i830_update_wm;
6631 if (IS_845G(dev))
6632 dev_priv->display.get_fifo_size = i845_get_fifo_size;
6633 else
6634 dev_priv->display.get_fifo_size = i830_get_fifo_size;
6635 }
6636 }
6637
6638 /*
6639 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
6640 * resume, or other times. This quirk makes sure that's the case for
6641 * affected systems.
6642 */
6643 static void quirk_pipea_force (struct drm_device *dev)
6644 {
6645 struct drm_i915_private *dev_priv = dev->dev_private;
6646
6647 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
6648 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
6649 }
6650
6651 struct intel_quirk {
6652 int device;
6653 int subsystem_vendor;
6654 int subsystem_device;
6655 void (*hook)(struct drm_device *dev);
6656 };
6657
6658 struct intel_quirk intel_quirks[] = {
6659 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
6660 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
6661 /* HP Mini needs pipe A force quirk (LP: #322104) */
6662 { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
6663
6664 /* Thinkpad R31 needs pipe A force quirk */
6665 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
6666 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
6667 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
6668
6669 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
6670 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
6671 /* ThinkPad X40 needs pipe A force quirk */
6672
6673 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
6674 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
6675
6676 /* 855 & before need to leave pipe A & dpll A up */
6677 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6678 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
6679 };
6680
6681 static void intel_init_quirks(struct drm_device *dev)
6682 {
6683 struct pci_dev *d = dev->pdev;
6684 int i;
6685
6686 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6687 struct intel_quirk *q = &intel_quirks[i];
6688
6689 if (d->device == q->device &&
6690 (d->subsystem_vendor == q->subsystem_vendor ||
6691 q->subsystem_vendor == PCI_ANY_ID) &&
6692 (d->subsystem_device == q->subsystem_device ||
6693 q->subsystem_device == PCI_ANY_ID))
6694 q->hook(dev);
6695 }
6696 }
6697
6698 /* Disable the VGA plane that we never use */
6699 static void i915_disable_vga(struct drm_device *dev)
6700 {
6701 struct drm_i915_private *dev_priv = dev->dev_private;
6702 u8 sr1;
6703 u32 vga_reg;
6704
6705 if (HAS_PCH_SPLIT(dev))
6706 vga_reg = CPU_VGACNTRL;
6707 else
6708 vga_reg = VGACNTRL;
6709
6710 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6711 outb(1, VGA_SR_INDEX);
6712 sr1 = inb(VGA_SR_DATA);
6713 outb(sr1 | 1<<5, VGA_SR_DATA);
6714 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6715 udelay(300);
6716
6717 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6718 POSTING_READ(vga_reg);
6719 }
6720
6721 void intel_modeset_init(struct drm_device *dev)
6722 {
6723 struct drm_i915_private *dev_priv = dev->dev_private;
6724 int i;
6725
6726 drm_mode_config_init(dev);
6727
6728 dev->mode_config.min_width = 0;
6729 dev->mode_config.min_height = 0;
6730
6731 dev->mode_config.funcs = (void *)&intel_mode_funcs;
6732
6733 intel_init_quirks(dev);
6734
6735 intel_init_display(dev);
6736
6737 if (IS_GEN2(dev)) {
6738 dev->mode_config.max_width = 2048;
6739 dev->mode_config.max_height = 2048;
6740 } else if (IS_GEN3(dev)) {
6741 dev->mode_config.max_width = 4096;
6742 dev->mode_config.max_height = 4096;
6743 } else {
6744 dev->mode_config.max_width = 8192;
6745 dev->mode_config.max_height = 8192;
6746 }
6747 dev->mode_config.fb_base = dev->agp->base;
6748
6749 if (IS_MOBILE(dev) || !IS_GEN2(dev))
6750 dev_priv->num_pipe = 2;
6751 else
6752 dev_priv->num_pipe = 1;
6753 DRM_DEBUG_KMS("%d display pipe%s available.\n",
6754 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6755
6756 for (i = 0; i < dev_priv->num_pipe; i++) {
6757 intel_crtc_init(dev, i);
6758 }
6759
6760 intel_setup_outputs(dev);
6761
6762 intel_enable_clock_gating(dev);
6763
6764 /* Just disable it once at startup */
6765 i915_disable_vga(dev);
6766
6767 if (IS_IRONLAKE_M(dev)) {
6768 ironlake_enable_drps(dev);
6769 intel_init_emon(dev);
6770 }
6771
6772 if (IS_GEN6(dev))
6773 gen6_enable_rps(dev_priv);
6774
6775 if (IS_IRONLAKE_M(dev)) {
6776 dev_priv->renderctx = intel_alloc_context_page(dev);
6777 if (!dev_priv->renderctx)
6778 goto skip_rc6;
6779 dev_priv->pwrctx = intel_alloc_context_page(dev);
6780 if (!dev_priv->pwrctx) {
6781 i915_gem_object_unpin(dev_priv->renderctx);
6782 drm_gem_object_unreference(&dev_priv->renderctx->base);
6783 dev_priv->renderctx = NULL;
6784 goto skip_rc6;
6785 }
6786 ironlake_enable_rc6(dev);
6787 }
6788
6789 skip_rc6:
6790 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6791 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6792 (unsigned long)dev);
6793
6794 intel_setup_overlay(dev);
6795 }
6796
6797 void intel_modeset_cleanup(struct drm_device *dev)
6798 {
6799 struct drm_i915_private *dev_priv = dev->dev_private;
6800 struct drm_crtc *crtc;
6801 struct intel_crtc *intel_crtc;
6802
6803 drm_kms_helper_poll_fini(dev);
6804 mutex_lock(&dev->struct_mutex);
6805
6806 intel_unregister_dsm_handler();
6807
6808
6809 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6810 /* Skip inactive CRTCs */
6811 if (!crtc->fb)
6812 continue;
6813
6814 intel_crtc = to_intel_crtc(crtc);
6815 intel_increase_pllclock(crtc);
6816 }
6817
6818 if (dev_priv->display.disable_fbc)
6819 dev_priv->display.disable_fbc(dev);
6820
6821 if (IS_IRONLAKE_M(dev))
6822 ironlake_disable_drps(dev);
6823 if (IS_GEN6(dev))
6824 gen6_disable_rps(dev);
6825
6826 if (IS_IRONLAKE_M(dev))
6827 ironlake_disable_rc6(dev);
6828
6829 mutex_unlock(&dev->struct_mutex);
6830
6831 /* Disable the irq before mode object teardown, for the irq might
6832 * enqueue unpin/hotplug work. */
6833 drm_irq_uninstall(dev);
6834 cancel_work_sync(&dev_priv->hotplug_work);
6835
6836 /* Shut off idle work before the crtcs get freed. */
6837 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6838 intel_crtc = to_intel_crtc(crtc);
6839 del_timer_sync(&intel_crtc->idle_timer);
6840 }
6841 del_timer_sync(&dev_priv->idle_timer);
6842 cancel_work_sync(&dev_priv->idle_work);
6843
6844 drm_mode_config_cleanup(dev);
6845 }
6846
6847 /*
6848 * Return which encoder is currently attached for connector.
6849 */
6850 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6851 {
6852 return &intel_attached_encoder(connector)->base;
6853 }
6854
6855 void intel_connector_attach_encoder(struct intel_connector *connector,
6856 struct intel_encoder *encoder)
6857 {
6858 connector->encoder = encoder;
6859 drm_mode_connector_attach_encoder(&connector->base,
6860 &encoder->base);
6861 }
6862
6863 /*
6864 * set vga decode state - true == enable VGA decode
6865 */
6866 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6867 {
6868 struct drm_i915_private *dev_priv = dev->dev_private;
6869 u16 gmch_ctrl;
6870
6871 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6872 if (state)
6873 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6874 else
6875 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6876 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6877 return 0;
6878 }
6879
6880 #ifdef CONFIG_DEBUG_FS
6881 #include <linux/seq_file.h>
6882
6883 struct intel_display_error_state {
6884 struct intel_cursor_error_state {
6885 u32 control;
6886 u32 position;
6887 u32 base;
6888 u32 size;
6889 } cursor[2];
6890
6891 struct intel_pipe_error_state {
6892 u32 conf;
6893 u32 source;
6894
6895 u32 htotal;
6896 u32 hblank;
6897 u32 hsync;
6898 u32 vtotal;
6899 u32 vblank;
6900 u32 vsync;
6901 } pipe[2];
6902
6903 struct intel_plane_error_state {
6904 u32 control;
6905 u32 stride;
6906 u32 size;
6907 u32 pos;
6908 u32 addr;
6909 u32 surface;
6910 u32 tile_offset;
6911 } plane[2];
6912 };
6913
6914 struct intel_display_error_state *
6915 intel_display_capture_error_state(struct drm_device *dev)
6916 {
6917 drm_i915_private_t *dev_priv = dev->dev_private;
6918 struct intel_display_error_state *error;
6919 int i;
6920
6921 error = kmalloc(sizeof(*error), GFP_ATOMIC);
6922 if (error == NULL)
6923 return NULL;
6924
6925 for (i = 0; i < 2; i++) {
6926 error->cursor[i].control = I915_READ(CURCNTR(i));
6927 error->cursor[i].position = I915_READ(CURPOS(i));
6928 error->cursor[i].base = I915_READ(CURBASE(i));
6929
6930 error->plane[i].control = I915_READ(DSPCNTR(i));
6931 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
6932 error->plane[i].size = I915_READ(DSPSIZE(i));
6933 error->plane[i].pos= I915_READ(DSPPOS(i));
6934 error->plane[i].addr = I915_READ(DSPADDR(i));
6935 if (INTEL_INFO(dev)->gen >= 4) {
6936 error->plane[i].surface = I915_READ(DSPSURF(i));
6937 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
6938 }
6939
6940 error->pipe[i].conf = I915_READ(PIPECONF(i));
6941 error->pipe[i].source = I915_READ(PIPESRC(i));
6942 error->pipe[i].htotal = I915_READ(HTOTAL(i));
6943 error->pipe[i].hblank = I915_READ(HBLANK(i));
6944 error->pipe[i].hsync = I915_READ(HSYNC(i));
6945 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
6946 error->pipe[i].vblank = I915_READ(VBLANK(i));
6947 error->pipe[i].vsync = I915_READ(VSYNC(i));
6948 }
6949
6950 return error;
6951 }
6952
6953 void
6954 intel_display_print_error_state(struct seq_file *m,
6955 struct drm_device *dev,
6956 struct intel_display_error_state *error)
6957 {
6958 int i;
6959
6960 for (i = 0; i < 2; i++) {
6961 seq_printf(m, "Pipe [%d]:\n", i);
6962 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
6963 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
6964 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
6965 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
6966 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
6967 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
6968 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
6969 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
6970
6971 seq_printf(m, "Plane [%d]:\n", i);
6972 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
6973 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
6974 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
6975 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
6976 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
6977 if (INTEL_INFO(dev)->gen >= 4) {
6978 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
6979 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
6980 }
6981
6982 seq_printf(m, "Cursor [%d]:\n", i);
6983 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
6984 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
6985 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
6986 }
6987 }
6988 #endif
Linux kernel - Deliverables
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