2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
52 DRM_FORMAT_XRGB8888, \
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2
[] = {
57 COMMON_PRIMARY_FORMATS
,
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4
[] = {
64 COMMON_PRIMARY_FORMATS
, \
67 DRM_FORMAT_XRGB2101010
,
68 DRM_FORMAT_ARGB2101010
,
69 DRM_FORMAT_XBGR2101010
,
70 DRM_FORMAT_ABGR2101010
,
74 static const uint32_t intel_cursor_formats
[] = {
78 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
80 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_state
*pipe_config
);
82 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
83 struct intel_crtc_state
*pipe_config
);
85 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
86 int x
, int y
, struct drm_framebuffer
*old_fb
,
87 struct drm_atomic_state
*state
);
88 static int intel_framebuffer_init(struct drm_device
*dev
,
89 struct intel_framebuffer
*ifb
,
90 struct drm_mode_fb_cmd2
*mode_cmd
,
91 struct drm_i915_gem_object
*obj
);
92 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
93 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
95 struct intel_link_m_n
*m_n
,
96 struct intel_link_m_n
*m2_n2
);
97 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
98 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
99 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
100 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
101 const struct intel_crtc_state
*pipe_config
);
102 static void chv_prepare_pll(struct intel_crtc
*crtc
,
103 const struct intel_crtc_state
*pipe_config
);
104 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
105 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
107 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
109 if (!connector
->mst_port
)
110 return connector
->encoder
;
112 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
121 int p2_slow
, p2_fast
;
124 typedef struct intel_limit intel_limit_t
;
126 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
131 intel_pch_rawclk(struct drm_device
*dev
)
133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 WARN_ON(!HAS_PCH_SPLIT(dev
));
137 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
140 static inline u32
/* units of 100MHz */
141 intel_fdi_link_freq(struct drm_device
*dev
)
144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
145 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
150 static const intel_limit_t intel_limits_i8xx_dac
= {
151 .dot
= { .min
= 25000, .max
= 350000 },
152 .vco
= { .min
= 908000, .max
= 1512000 },
153 .n
= { .min
= 2, .max
= 16 },
154 .m
= { .min
= 96, .max
= 140 },
155 .m1
= { .min
= 18, .max
= 26 },
156 .m2
= { .min
= 6, .max
= 16 },
157 .p
= { .min
= 4, .max
= 128 },
158 .p1
= { .min
= 2, .max
= 33 },
159 .p2
= { .dot_limit
= 165000,
160 .p2_slow
= 4, .p2_fast
= 2 },
163 static const intel_limit_t intel_limits_i8xx_dvo
= {
164 .dot
= { .min
= 25000, .max
= 350000 },
165 .vco
= { .min
= 908000, .max
= 1512000 },
166 .n
= { .min
= 2, .max
= 16 },
167 .m
= { .min
= 96, .max
= 140 },
168 .m1
= { .min
= 18, .max
= 26 },
169 .m2
= { .min
= 6, .max
= 16 },
170 .p
= { .min
= 4, .max
= 128 },
171 .p1
= { .min
= 2, .max
= 33 },
172 .p2
= { .dot_limit
= 165000,
173 .p2_slow
= 4, .p2_fast
= 4 },
176 static const intel_limit_t intel_limits_i8xx_lvds
= {
177 .dot
= { .min
= 25000, .max
= 350000 },
178 .vco
= { .min
= 908000, .max
= 1512000 },
179 .n
= { .min
= 2, .max
= 16 },
180 .m
= { .min
= 96, .max
= 140 },
181 .m1
= { .min
= 18, .max
= 26 },
182 .m2
= { .min
= 6, .max
= 16 },
183 .p
= { .min
= 4, .max
= 128 },
184 .p1
= { .min
= 1, .max
= 6 },
185 .p2
= { .dot_limit
= 165000,
186 .p2_slow
= 14, .p2_fast
= 7 },
189 static const intel_limit_t intel_limits_i9xx_sdvo
= {
190 .dot
= { .min
= 20000, .max
= 400000 },
191 .vco
= { .min
= 1400000, .max
= 2800000 },
192 .n
= { .min
= 1, .max
= 6 },
193 .m
= { .min
= 70, .max
= 120 },
194 .m1
= { .min
= 8, .max
= 18 },
195 .m2
= { .min
= 3, .max
= 7 },
196 .p
= { .min
= 5, .max
= 80 },
197 .p1
= { .min
= 1, .max
= 8 },
198 .p2
= { .dot_limit
= 200000,
199 .p2_slow
= 10, .p2_fast
= 5 },
202 static const intel_limit_t intel_limits_i9xx_lvds
= {
203 .dot
= { .min
= 20000, .max
= 400000 },
204 .vco
= { .min
= 1400000, .max
= 2800000 },
205 .n
= { .min
= 1, .max
= 6 },
206 .m
= { .min
= 70, .max
= 120 },
207 .m1
= { .min
= 8, .max
= 18 },
208 .m2
= { .min
= 3, .max
= 7 },
209 .p
= { .min
= 7, .max
= 98 },
210 .p1
= { .min
= 1, .max
= 8 },
211 .p2
= { .dot_limit
= 112000,
212 .p2_slow
= 14, .p2_fast
= 7 },
216 static const intel_limit_t intel_limits_g4x_sdvo
= {
217 .dot
= { .min
= 25000, .max
= 270000 },
218 .vco
= { .min
= 1750000, .max
= 3500000},
219 .n
= { .min
= 1, .max
= 4 },
220 .m
= { .min
= 104, .max
= 138 },
221 .m1
= { .min
= 17, .max
= 23 },
222 .m2
= { .min
= 5, .max
= 11 },
223 .p
= { .min
= 10, .max
= 30 },
224 .p1
= { .min
= 1, .max
= 3},
225 .p2
= { .dot_limit
= 270000,
231 static const intel_limit_t intel_limits_g4x_hdmi
= {
232 .dot
= { .min
= 22000, .max
= 400000 },
233 .vco
= { .min
= 1750000, .max
= 3500000},
234 .n
= { .min
= 1, .max
= 4 },
235 .m
= { .min
= 104, .max
= 138 },
236 .m1
= { .min
= 16, .max
= 23 },
237 .m2
= { .min
= 5, .max
= 11 },
238 .p
= { .min
= 5, .max
= 80 },
239 .p1
= { .min
= 1, .max
= 8},
240 .p2
= { .dot_limit
= 165000,
241 .p2_slow
= 10, .p2_fast
= 5 },
244 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
245 .dot
= { .min
= 20000, .max
= 115000 },
246 .vco
= { .min
= 1750000, .max
= 3500000 },
247 .n
= { .min
= 1, .max
= 3 },
248 .m
= { .min
= 104, .max
= 138 },
249 .m1
= { .min
= 17, .max
= 23 },
250 .m2
= { .min
= 5, .max
= 11 },
251 .p
= { .min
= 28, .max
= 112 },
252 .p1
= { .min
= 2, .max
= 8 },
253 .p2
= { .dot_limit
= 0,
254 .p2_slow
= 14, .p2_fast
= 14
258 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
259 .dot
= { .min
= 80000, .max
= 224000 },
260 .vco
= { .min
= 1750000, .max
= 3500000 },
261 .n
= { .min
= 1, .max
= 3 },
262 .m
= { .min
= 104, .max
= 138 },
263 .m1
= { .min
= 17, .max
= 23 },
264 .m2
= { .min
= 5, .max
= 11 },
265 .p
= { .min
= 14, .max
= 42 },
266 .p1
= { .min
= 2, .max
= 6 },
267 .p2
= { .dot_limit
= 0,
268 .p2_slow
= 7, .p2_fast
= 7
272 static const intel_limit_t intel_limits_pineview_sdvo
= {
273 .dot
= { .min
= 20000, .max
= 400000},
274 .vco
= { .min
= 1700000, .max
= 3500000 },
275 /* Pineview's Ncounter is a ring counter */
276 .n
= { .min
= 3, .max
= 6 },
277 .m
= { .min
= 2, .max
= 256 },
278 /* Pineview only has one combined m divider, which we treat as m2. */
279 .m1
= { .min
= 0, .max
= 0 },
280 .m2
= { .min
= 0, .max
= 254 },
281 .p
= { .min
= 5, .max
= 80 },
282 .p1
= { .min
= 1, .max
= 8 },
283 .p2
= { .dot_limit
= 200000,
284 .p2_slow
= 10, .p2_fast
= 5 },
287 static const intel_limit_t intel_limits_pineview_lvds
= {
288 .dot
= { .min
= 20000, .max
= 400000 },
289 .vco
= { .min
= 1700000, .max
= 3500000 },
290 .n
= { .min
= 3, .max
= 6 },
291 .m
= { .min
= 2, .max
= 256 },
292 .m1
= { .min
= 0, .max
= 0 },
293 .m2
= { .min
= 0, .max
= 254 },
294 .p
= { .min
= 7, .max
= 112 },
295 .p1
= { .min
= 1, .max
= 8 },
296 .p2
= { .dot_limit
= 112000,
297 .p2_slow
= 14, .p2_fast
= 14 },
300 /* Ironlake / Sandybridge
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
305 static const intel_limit_t intel_limits_ironlake_dac
= {
306 .dot
= { .min
= 25000, .max
= 350000 },
307 .vco
= { .min
= 1760000, .max
= 3510000 },
308 .n
= { .min
= 1, .max
= 5 },
309 .m
= { .min
= 79, .max
= 127 },
310 .m1
= { .min
= 12, .max
= 22 },
311 .m2
= { .min
= 5, .max
= 9 },
312 .p
= { .min
= 5, .max
= 80 },
313 .p1
= { .min
= 1, .max
= 8 },
314 .p2
= { .dot_limit
= 225000,
315 .p2_slow
= 10, .p2_fast
= 5 },
318 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
319 .dot
= { .min
= 25000, .max
= 350000 },
320 .vco
= { .min
= 1760000, .max
= 3510000 },
321 .n
= { .min
= 1, .max
= 3 },
322 .m
= { .min
= 79, .max
= 118 },
323 .m1
= { .min
= 12, .max
= 22 },
324 .m2
= { .min
= 5, .max
= 9 },
325 .p
= { .min
= 28, .max
= 112 },
326 .p1
= { .min
= 2, .max
= 8 },
327 .p2
= { .dot_limit
= 225000,
328 .p2_slow
= 14, .p2_fast
= 14 },
331 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
332 .dot
= { .min
= 25000, .max
= 350000 },
333 .vco
= { .min
= 1760000, .max
= 3510000 },
334 .n
= { .min
= 1, .max
= 3 },
335 .m
= { .min
= 79, .max
= 127 },
336 .m1
= { .min
= 12, .max
= 22 },
337 .m2
= { .min
= 5, .max
= 9 },
338 .p
= { .min
= 14, .max
= 56 },
339 .p1
= { .min
= 2, .max
= 8 },
340 .p2
= { .dot_limit
= 225000,
341 .p2_slow
= 7, .p2_fast
= 7 },
344 /* LVDS 100mhz refclk limits. */
345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
346 .dot
= { .min
= 25000, .max
= 350000 },
347 .vco
= { .min
= 1760000, .max
= 3510000 },
348 .n
= { .min
= 1, .max
= 2 },
349 .m
= { .min
= 79, .max
= 126 },
350 .m1
= { .min
= 12, .max
= 22 },
351 .m2
= { .min
= 5, .max
= 9 },
352 .p
= { .min
= 28, .max
= 112 },
353 .p1
= { .min
= 2, .max
= 8 },
354 .p2
= { .dot_limit
= 225000,
355 .p2_slow
= 14, .p2_fast
= 14 },
358 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
359 .dot
= { .min
= 25000, .max
= 350000 },
360 .vco
= { .min
= 1760000, .max
= 3510000 },
361 .n
= { .min
= 1, .max
= 3 },
362 .m
= { .min
= 79, .max
= 126 },
363 .m1
= { .min
= 12, .max
= 22 },
364 .m2
= { .min
= 5, .max
= 9 },
365 .p
= { .min
= 14, .max
= 42 },
366 .p1
= { .min
= 2, .max
= 6 },
367 .p2
= { .dot_limit
= 225000,
368 .p2_slow
= 7, .p2_fast
= 7 },
371 static const intel_limit_t intel_limits_vlv
= {
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
378 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
379 .vco
= { .min
= 4000000, .max
= 6000000 },
380 .n
= { .min
= 1, .max
= 7 },
381 .m1
= { .min
= 2, .max
= 3 },
382 .m2
= { .min
= 11, .max
= 156 },
383 .p1
= { .min
= 2, .max
= 3 },
384 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
387 static const intel_limit_t intel_limits_chv
= {
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
394 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
395 .vco
= { .min
= 4800000, .max
= 6480000 },
396 .n
= { .min
= 1, .max
= 1 },
397 .m1
= { .min
= 2, .max
= 2 },
398 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
399 .p1
= { .min
= 2, .max
= 4 },
400 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
403 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
405 clock
->m
= clock
->m1
* clock
->m2
;
406 clock
->p
= clock
->p1
* clock
->p2
;
407 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
409 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
410 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
414 * Returns whether any output on the specified pipe is of the specified type
416 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
418 struct drm_device
*dev
= crtc
->base
.dev
;
419 struct intel_encoder
*encoder
;
421 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
422 if (encoder
->type
== type
)
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
434 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
437 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
438 struct drm_connector_state
*connector_state
;
439 struct intel_encoder
*encoder
;
440 int i
, num_connectors
= 0;
442 for (i
= 0; i
< state
->num_connector
; i
++) {
443 if (!state
->connectors
[i
])
446 connector_state
= state
->connector_states
[i
];
447 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
452 encoder
= to_intel_encoder(connector_state
->best_encoder
);
453 if (encoder
->type
== type
)
457 WARN_ON(num_connectors
== 0);
462 static const intel_limit_t
*
463 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
465 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
466 const intel_limit_t
*limit
;
468 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
469 if (intel_is_dual_link_lvds(dev
)) {
470 if (refclk
== 100000)
471 limit
= &intel_limits_ironlake_dual_lvds_100m
;
473 limit
= &intel_limits_ironlake_dual_lvds
;
475 if (refclk
== 100000)
476 limit
= &intel_limits_ironlake_single_lvds_100m
;
478 limit
= &intel_limits_ironlake_single_lvds
;
481 limit
= &intel_limits_ironlake_dac
;
486 static const intel_limit_t
*
487 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
489 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
490 const intel_limit_t
*limit
;
492 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
493 if (intel_is_dual_link_lvds(dev
))
494 limit
= &intel_limits_g4x_dual_channel_lvds
;
496 limit
= &intel_limits_g4x_single_channel_lvds
;
497 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
498 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
499 limit
= &intel_limits_g4x_hdmi
;
500 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
501 limit
= &intel_limits_g4x_sdvo
;
502 } else /* The option is for other outputs */
503 limit
= &intel_limits_i9xx_sdvo
;
508 static const intel_limit_t
*
509 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
511 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
512 const intel_limit_t
*limit
;
514 if (HAS_PCH_SPLIT(dev
))
515 limit
= intel_ironlake_limit(crtc_state
, refclk
);
516 else if (IS_G4X(dev
)) {
517 limit
= intel_g4x_limit(crtc_state
);
518 } else if (IS_PINEVIEW(dev
)) {
519 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
520 limit
= &intel_limits_pineview_lvds
;
522 limit
= &intel_limits_pineview_sdvo
;
523 } else if (IS_CHERRYVIEW(dev
)) {
524 limit
= &intel_limits_chv
;
525 } else if (IS_VALLEYVIEW(dev
)) {
526 limit
= &intel_limits_vlv
;
527 } else if (!IS_GEN2(dev
)) {
528 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
529 limit
= &intel_limits_i9xx_lvds
;
531 limit
= &intel_limits_i9xx_sdvo
;
533 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
534 limit
= &intel_limits_i8xx_lvds
;
535 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
536 limit
= &intel_limits_i8xx_dvo
;
538 limit
= &intel_limits_i8xx_dac
;
543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
544 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
546 clock
->m
= clock
->m2
+ 2;
547 clock
->p
= clock
->p1
* clock
->p2
;
548 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
550 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
551 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
554 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
556 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
559 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
561 clock
->m
= i9xx_dpll_compute_m(clock
);
562 clock
->p
= clock
->p1
* clock
->p2
;
563 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
565 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
566 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
569 static void chv_clock(int refclk
, intel_clock_t
*clock
)
571 clock
->m
= clock
->m1
* clock
->m2
;
572 clock
->p
= clock
->p1
* clock
->p2
;
573 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
575 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
577 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
580 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
582 * Returns whether the given set of divisors are valid for a given refclk with
583 * the given connectors.
586 static bool intel_PLL_is_valid(struct drm_device
*dev
,
587 const intel_limit_t
*limit
,
588 const intel_clock_t
*clock
)
590 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
591 INTELPllInvalid("n out of range\n");
592 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
593 INTELPllInvalid("p1 out of range\n");
594 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
595 INTELPllInvalid("m2 out of range\n");
596 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
597 INTELPllInvalid("m1 out of range\n");
599 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
600 if (clock
->m1
<= clock
->m2
)
601 INTELPllInvalid("m1 <= m2\n");
603 if (!IS_VALLEYVIEW(dev
)) {
604 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
605 INTELPllInvalid("p out of range\n");
606 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
607 INTELPllInvalid("m out of range\n");
610 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
611 INTELPllInvalid("vco out of range\n");
612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
615 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
616 INTELPllInvalid("dot out of range\n");
622 i9xx_find_best_dpll(const intel_limit_t
*limit
,
623 struct intel_crtc_state
*crtc_state
,
624 int target
, int refclk
, intel_clock_t
*match_clock
,
625 intel_clock_t
*best_clock
)
627 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
628 struct drm_device
*dev
= crtc
->base
.dev
;
632 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
634 * For LVDS just rely on its current settings for dual-channel.
635 * We haven't figured out how to reliably set up different
636 * single/dual channel state, if we even can.
638 if (intel_is_dual_link_lvds(dev
))
639 clock
.p2
= limit
->p2
.p2_fast
;
641 clock
.p2
= limit
->p2
.p2_slow
;
643 if (target
< limit
->p2
.dot_limit
)
644 clock
.p2
= limit
->p2
.p2_slow
;
646 clock
.p2
= limit
->p2
.p2_fast
;
649 memset(best_clock
, 0, sizeof(*best_clock
));
651 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
653 for (clock
.m2
= limit
->m2
.min
;
654 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
655 if (clock
.m2
>= clock
.m1
)
657 for (clock
.n
= limit
->n
.min
;
658 clock
.n
<= limit
->n
.max
; clock
.n
++) {
659 for (clock
.p1
= limit
->p1
.min
;
660 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
663 i9xx_clock(refclk
, &clock
);
664 if (!intel_PLL_is_valid(dev
, limit
,
668 clock
.p
!= match_clock
->p
)
671 this_err
= abs(clock
.dot
- target
);
672 if (this_err
< err
) {
681 return (err
!= target
);
685 pnv_find_best_dpll(const intel_limit_t
*limit
,
686 struct intel_crtc_state
*crtc_state
,
687 int target
, int refclk
, intel_clock_t
*match_clock
,
688 intel_clock_t
*best_clock
)
690 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
691 struct drm_device
*dev
= crtc
->base
.dev
;
695 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
697 * For LVDS just rely on its current settings for dual-channel.
698 * We haven't figured out how to reliably set up different
699 * single/dual channel state, if we even can.
701 if (intel_is_dual_link_lvds(dev
))
702 clock
.p2
= limit
->p2
.p2_fast
;
704 clock
.p2
= limit
->p2
.p2_slow
;
706 if (target
< limit
->p2
.dot_limit
)
707 clock
.p2
= limit
->p2
.p2_slow
;
709 clock
.p2
= limit
->p2
.p2_fast
;
712 memset(best_clock
, 0, sizeof(*best_clock
));
714 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
716 for (clock
.m2
= limit
->m2
.min
;
717 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
718 for (clock
.n
= limit
->n
.min
;
719 clock
.n
<= limit
->n
.max
; clock
.n
++) {
720 for (clock
.p1
= limit
->p1
.min
;
721 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
724 pineview_clock(refclk
, &clock
);
725 if (!intel_PLL_is_valid(dev
, limit
,
729 clock
.p
!= match_clock
->p
)
732 this_err
= abs(clock
.dot
- target
);
733 if (this_err
< err
) {
742 return (err
!= target
);
746 g4x_find_best_dpll(const intel_limit_t
*limit
,
747 struct intel_crtc_state
*crtc_state
,
748 int target
, int refclk
, intel_clock_t
*match_clock
,
749 intel_clock_t
*best_clock
)
751 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
752 struct drm_device
*dev
= crtc
->base
.dev
;
756 /* approximately equals target * 0.00585 */
757 int err_most
= (target
>> 8) + (target
>> 9);
760 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
761 if (intel_is_dual_link_lvds(dev
))
762 clock
.p2
= limit
->p2
.p2_fast
;
764 clock
.p2
= limit
->p2
.p2_slow
;
766 if (target
< limit
->p2
.dot_limit
)
767 clock
.p2
= limit
->p2
.p2_slow
;
769 clock
.p2
= limit
->p2
.p2_fast
;
772 memset(best_clock
, 0, sizeof(*best_clock
));
773 max_n
= limit
->n
.max
;
774 /* based on hardware requirement, prefer smaller n to precision */
775 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
776 /* based on hardware requirement, prefere larger m1,m2 */
777 for (clock
.m1
= limit
->m1
.max
;
778 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
779 for (clock
.m2
= limit
->m2
.max
;
780 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
781 for (clock
.p1
= limit
->p1
.max
;
782 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
785 i9xx_clock(refclk
, &clock
);
786 if (!intel_PLL_is_valid(dev
, limit
,
790 this_err
= abs(clock
.dot
- target
);
791 if (this_err
< err_most
) {
805 * Check if the calculated PLL configuration is more optimal compared to the
806 * best configuration and error found so far. Return the calculated error.
808 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
809 const intel_clock_t
*calculated_clock
,
810 const intel_clock_t
*best_clock
,
811 unsigned int best_error_ppm
,
812 unsigned int *error_ppm
)
815 * For CHV ignore the error and consider only the P value.
816 * Prefer a bigger P value based on HW requirements.
818 if (IS_CHERRYVIEW(dev
)) {
821 return calculated_clock
->p
> best_clock
->p
;
824 if (WARN_ON_ONCE(!target_freq
))
827 *error_ppm
= div_u64(1000000ULL *
828 abs(target_freq
- calculated_clock
->dot
),
831 * Prefer a better P value over a better (smaller) error if the error
832 * is small. Ensure this preference for future configurations too by
833 * setting the error to 0.
835 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
841 return *error_ppm
+ 10 < best_error_ppm
;
845 vlv_find_best_dpll(const intel_limit_t
*limit
,
846 struct intel_crtc_state
*crtc_state
,
847 int target
, int refclk
, intel_clock_t
*match_clock
,
848 intel_clock_t
*best_clock
)
850 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
851 struct drm_device
*dev
= crtc
->base
.dev
;
853 unsigned int bestppm
= 1000000;
854 /* min update 19.2 MHz */
855 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
858 target
*= 5; /* fast clock */
860 memset(best_clock
, 0, sizeof(*best_clock
));
862 /* based on hardware requirement, prefer smaller n to precision */
863 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
864 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
865 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
866 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
867 clock
.p
= clock
.p1
* clock
.p2
;
868 /* based on hardware requirement, prefer bigger m1,m2 values */
869 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
872 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
875 vlv_clock(refclk
, &clock
);
877 if (!intel_PLL_is_valid(dev
, limit
,
881 if (!vlv_PLL_is_optimal(dev
, target
,
899 chv_find_best_dpll(const intel_limit_t
*limit
,
900 struct intel_crtc_state
*crtc_state
,
901 int target
, int refclk
, intel_clock_t
*match_clock
,
902 intel_clock_t
*best_clock
)
904 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
905 struct drm_device
*dev
= crtc
->base
.dev
;
906 unsigned int best_error_ppm
;
911 memset(best_clock
, 0, sizeof(*best_clock
));
912 best_error_ppm
= 1000000;
915 * Based on hardware doc, the n always set to 1, and m1 always
916 * set to 2. If requires to support 200Mhz refclk, we need to
917 * revisit this because n may not 1 anymore.
919 clock
.n
= 1, clock
.m1
= 2;
920 target
*= 5; /* fast clock */
922 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
923 for (clock
.p2
= limit
->p2
.p2_fast
;
924 clock
.p2
>= limit
->p2
.p2_slow
;
925 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
926 unsigned int error_ppm
;
928 clock
.p
= clock
.p1
* clock
.p2
;
930 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
931 clock
.n
) << 22, refclk
* clock
.m1
);
933 if (m2
> INT_MAX
/clock
.m1
)
938 chv_clock(refclk
, &clock
);
940 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
943 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
944 best_error_ppm
, &error_ppm
))
948 best_error_ppm
= error_ppm
;
956 bool intel_crtc_active(struct drm_crtc
*crtc
)
958 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
960 /* Be paranoid as we can arrive here with only partial
961 * state retrieved from the hardware during setup.
963 * We can ditch the adjusted_mode.crtc_clock check as soon
964 * as Haswell has gained clock readout/fastboot support.
966 * We can ditch the crtc->primary->fb check as soon as we can
967 * properly reconstruct framebuffers.
969 * FIXME: The intel_crtc->active here should be switched to
970 * crtc->state->active once we have proper CRTC states wired up
973 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
974 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
977 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
980 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
981 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
983 return intel_crtc
->config
->cpu_transcoder
;
986 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
989 u32 reg
= PIPEDSL(pipe
);
994 line_mask
= DSL_LINEMASK_GEN2
;
996 line_mask
= DSL_LINEMASK_GEN3
;
998 line1
= I915_READ(reg
) & line_mask
;
1000 line2
= I915_READ(reg
) & line_mask
;
1002 return line1
== line2
;
1006 * intel_wait_for_pipe_off - wait for pipe to turn off
1007 * @crtc: crtc whose pipe to wait for
1009 * After disabling a pipe, we can't wait for vblank in the usual way,
1010 * spinning on the vblank interrupt status bit, since we won't actually
1011 * see an interrupt when the pipe is disabled.
1013 * On Gen4 and above:
1014 * wait for the pipe register state bit to turn off
1017 * wait for the display line value to settle (it usually
1018 * ends up stopping at the start of the next frame).
1021 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1023 struct drm_device
*dev
= crtc
->base
.dev
;
1024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1025 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1026 enum pipe pipe
= crtc
->pipe
;
1028 if (INTEL_INFO(dev
)->gen
>= 4) {
1029 int reg
= PIPECONF(cpu_transcoder
);
1031 /* Wait for the Pipe State to go off */
1032 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1034 WARN(1, "pipe_off wait timed out\n");
1036 /* Wait for the display line to settle */
1037 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1038 WARN(1, "pipe_off wait timed out\n");
1043 * ibx_digital_port_connected - is the specified port connected?
1044 * @dev_priv: i915 private structure
1045 * @port: the port to test
1047 * Returns true if @port is connected, false otherwise.
1049 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1050 struct intel_digital_port
*port
)
1054 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1055 switch (port
->port
) {
1057 bit
= SDE_PORTB_HOTPLUG
;
1060 bit
= SDE_PORTC_HOTPLUG
;
1063 bit
= SDE_PORTD_HOTPLUG
;
1069 switch (port
->port
) {
1071 bit
= SDE_PORTB_HOTPLUG_CPT
;
1074 bit
= SDE_PORTC_HOTPLUG_CPT
;
1077 bit
= SDE_PORTD_HOTPLUG_CPT
;
1084 return I915_READ(SDEISR
) & bit
;
1087 static const char *state_string(bool enabled
)
1089 return enabled
? "on" : "off";
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private
*dev_priv
,
1094 enum pipe pipe
, bool state
)
1101 val
= I915_READ(reg
);
1102 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1103 I915_STATE_WARN(cur_state
!= state
,
1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 state_string(state
), state_string(cur_state
));
1108 /* XXX: the dsi pll is shared between MIPI DSI ports */
1109 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1114 mutex_lock(&dev_priv
->dpio_lock
);
1115 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1116 mutex_unlock(&dev_priv
->dpio_lock
);
1118 cur_state
= val
& DSI_PLL_VCO_EN
;
1119 I915_STATE_WARN(cur_state
!= state
,
1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 state_string(state
), state_string(cur_state
));
1123 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1126 struct intel_shared_dpll
*
1127 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1129 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1131 if (crtc
->config
->shared_dpll
< 0)
1134 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1138 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1139 struct intel_shared_dpll
*pll
,
1143 struct intel_dpll_hw_state hw_state
;
1146 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1149 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1150 I915_STATE_WARN(cur_state
!= state
,
1151 "%s assertion failure (expected %s, current %s)\n",
1152 pll
->name
, state_string(state
), state_string(cur_state
));
1155 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1156 enum pipe pipe
, bool state
)
1161 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1164 if (HAS_DDI(dev_priv
->dev
)) {
1165 /* DDI does not have a specific FDI_TX register */
1166 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1167 val
= I915_READ(reg
);
1168 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1170 reg
= FDI_TX_CTL(pipe
);
1171 val
= I915_READ(reg
);
1172 cur_state
= !!(val
& FDI_TX_ENABLE
);
1174 I915_STATE_WARN(cur_state
!= state
,
1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 state_string(state
), state_string(cur_state
));
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1181 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1182 enum pipe pipe
, bool state
)
1188 reg
= FDI_RX_CTL(pipe
);
1189 val
= I915_READ(reg
);
1190 cur_state
= !!(val
& FDI_RX_ENABLE
);
1191 I915_STATE_WARN(cur_state
!= state
,
1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 state_string(state
), state_string(cur_state
));
1195 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1204 /* ILK FDI PLL is always enabled */
1205 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209 if (HAS_DDI(dev_priv
->dev
))
1212 reg
= FDI_TX_CTL(pipe
);
1213 val
= I915_READ(reg
);
1214 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1217 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1224 reg
= FDI_RX_CTL(pipe
);
1225 val
= I915_READ(reg
);
1226 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1227 I915_STATE_WARN(cur_state
!= state
,
1228 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229 state_string(state
), state_string(cur_state
));
1232 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1235 struct drm_device
*dev
= dev_priv
->dev
;
1238 enum pipe panel_pipe
= PIPE_A
;
1241 if (WARN_ON(HAS_DDI(dev
)))
1244 if (HAS_PCH_SPLIT(dev
)) {
1247 pp_reg
= PCH_PP_CONTROL
;
1248 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1250 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1251 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1252 panel_pipe
= PIPE_B
;
1253 /* XXX: else fix for eDP */
1254 } else if (IS_VALLEYVIEW(dev
)) {
1255 /* presumably write lock depends on pipe, not port select */
1256 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1259 pp_reg
= PP_CONTROL
;
1260 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1261 panel_pipe
= PIPE_B
;
1264 val
= I915_READ(pp_reg
);
1265 if (!(val
& PANEL_POWER_ON
) ||
1266 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1269 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1270 "panel assertion failure, pipe %c regs locked\n",
1274 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1275 enum pipe pipe
, bool state
)
1277 struct drm_device
*dev
= dev_priv
->dev
;
1280 if (IS_845G(dev
) || IS_I865G(dev
))
1281 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1283 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1285 I915_STATE_WARN(cur_state
!= state
,
1286 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1289 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1292 void assert_pipe(struct drm_i915_private
*dev_priv
,
1293 enum pipe pipe
, bool state
)
1298 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1303 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1306 if (!intel_display_power_is_enabled(dev_priv
,
1307 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1310 reg
= PIPECONF(cpu_transcoder
);
1311 val
= I915_READ(reg
);
1312 cur_state
= !!(val
& PIPECONF_ENABLE
);
1315 I915_STATE_WARN(cur_state
!= state
,
1316 "pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1320 static void assert_plane(struct drm_i915_private
*dev_priv
,
1321 enum plane plane
, bool state
)
1327 reg
= DSPCNTR(plane
);
1328 val
= I915_READ(reg
);
1329 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1330 I915_STATE_WARN(cur_state
!= state
,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane
), state_string(state
), state_string(cur_state
));
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1338 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1341 struct drm_device
*dev
= dev_priv
->dev
;
1346 /* Primary planes are fixed to pipes on gen4+ */
1347 if (INTEL_INFO(dev
)->gen
>= 4) {
1348 reg
= DSPCNTR(pipe
);
1349 val
= I915_READ(reg
);
1350 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1351 "plane %c assertion failure, should be disabled but not\n",
1356 /* Need to check both planes against the pipe */
1357 for_each_pipe(dev_priv
, i
) {
1359 val
= I915_READ(reg
);
1360 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1361 DISPPLANE_SEL_PIPE_SHIFT
;
1362 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1363 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(i
), pipe_name(pipe
));
1368 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1371 struct drm_device
*dev
= dev_priv
->dev
;
1375 if (INTEL_INFO(dev
)->gen
>= 9) {
1376 for_each_sprite(dev_priv
, pipe
, sprite
) {
1377 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1378 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1379 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380 sprite
, pipe_name(pipe
));
1382 } else if (IS_VALLEYVIEW(dev
)) {
1383 for_each_sprite(dev_priv
, pipe
, sprite
) {
1384 reg
= SPCNTR(pipe
, sprite
);
1385 val
= I915_READ(reg
);
1386 I915_STATE_WARN(val
& SP_ENABLE
,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1390 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1392 val
= I915_READ(reg
);
1393 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1394 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1395 plane_name(pipe
), pipe_name(pipe
));
1396 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1397 reg
= DVSCNTR(pipe
);
1398 val
= I915_READ(reg
);
1399 I915_STATE_WARN(val
& DVS_ENABLE
,
1400 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1401 plane_name(pipe
), pipe_name(pipe
));
1405 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1408 drm_crtc_vblank_put(crtc
);
1411 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1418 val
= I915_READ(PCH_DREF_CONTROL
);
1419 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1420 DREF_SUPERSPREAD_SOURCE_MASK
));
1421 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1424 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1431 reg
= PCH_TRANSCONF(pipe
);
1432 val
= I915_READ(reg
);
1433 enabled
= !!(val
& TRANS_ENABLE
);
1434 I915_STATE_WARN(enabled
,
1435 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1439 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1440 enum pipe pipe
, u32 port_sel
, u32 val
)
1442 if ((val
& DP_PORT_EN
) == 0)
1445 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1446 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1447 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1448 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1450 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1451 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1454 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1460 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1461 enum pipe pipe
, u32 val
)
1463 if ((val
& SDVO_ENABLE
) == 0)
1466 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1467 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1469 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1470 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1473 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1479 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1480 enum pipe pipe
, u32 val
)
1482 if ((val
& LVDS_PORT_EN
) == 0)
1485 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1486 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1489 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1495 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1496 enum pipe pipe
, u32 val
)
1498 if ((val
& ADPA_DAC_ENABLE
) == 0)
1500 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1501 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1504 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1510 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1511 enum pipe pipe
, int reg
, u32 port_sel
)
1513 u32 val
= I915_READ(reg
);
1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1516 reg
, pipe_name(pipe
));
1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1519 && (val
& DP_PIPEB_SELECT
),
1520 "IBX PCH dp port still using transcoder B\n");
1523 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1524 enum pipe pipe
, int reg
)
1526 u32 val
= I915_READ(reg
);
1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1529 reg
, pipe_name(pipe
));
1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1532 && (val
& SDVO_PIPE_B_SELECT
),
1533 "IBX PCH hdmi port still using transcoder B\n");
1536 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1542 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1543 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1544 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1547 val
= I915_READ(reg
);
1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1549 "PCH VGA enabled on transcoder %c, should be disabled\n",
1553 val
= I915_READ(reg
);
1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1555 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1558 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1559 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1560 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1563 static void intel_init_dpio(struct drm_device
*dev
)
1565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1567 if (!IS_VALLEYVIEW(dev
))
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572 * CHV x1 PHY (DP/HDMI D)
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1575 if (IS_CHERRYVIEW(dev
)) {
1576 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1577 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1583 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1584 const struct intel_crtc_state
*pipe_config
)
1586 struct drm_device
*dev
= crtc
->base
.dev
;
1587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1588 int reg
= DPLL(crtc
->pipe
);
1589 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1591 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1593 /* No really, not for ILK+ */
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1596 /* PLL is protected by panel, make sure we can write it */
1597 if (IS_MOBILE(dev_priv
->dev
))
1598 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1600 I915_WRITE(reg
, dpll
);
1604 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1607 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1608 POSTING_READ(DPLL_MD(crtc
->pipe
));
1610 /* We do this three times for luck */
1611 I915_WRITE(reg
, dpll
);
1613 udelay(150); /* wait for warmup */
1614 I915_WRITE(reg
, dpll
);
1616 udelay(150); /* wait for warmup */
1617 I915_WRITE(reg
, dpll
);
1619 udelay(150); /* wait for warmup */
1622 static void chv_enable_pll(struct intel_crtc
*crtc
,
1623 const struct intel_crtc_state
*pipe_config
)
1625 struct drm_device
*dev
= crtc
->base
.dev
;
1626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1627 int pipe
= crtc
->pipe
;
1628 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1631 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1635 mutex_lock(&dev_priv
->dpio_lock
);
1637 /* Enable back the 10bit clock to display controller */
1638 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1639 tmp
|= DPIO_DCLKP_EN
;
1640 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1643 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1648 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1650 /* Check PLL is locked */
1651 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1652 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1654 /* not sure when this should be written */
1655 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1656 POSTING_READ(DPLL_MD(pipe
));
1658 mutex_unlock(&dev_priv
->dpio_lock
);
1661 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1663 struct intel_crtc
*crtc
;
1666 for_each_intel_crtc(dev
, crtc
)
1667 count
+= crtc
->active
&&
1668 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1673 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1675 struct drm_device
*dev
= crtc
->base
.dev
;
1676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1677 int reg
= DPLL(crtc
->pipe
);
1678 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1680 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1682 /* No really, not for ILK+ */
1683 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1685 /* PLL is protected by panel, make sure we can write it */
1686 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1687 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1689 /* Enable DVO 2x clock on both PLLs if necessary */
1690 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1692 * It appears to be important that we don't enable this
1693 * for the current pipe before otherwise configuring the
1694 * PLL. No idea how this should be handled if multiple
1695 * DVO outputs are enabled simultaneosly.
1697 dpll
|= DPLL_DVO_2X_MODE
;
1698 I915_WRITE(DPLL(!crtc
->pipe
),
1699 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1702 /* Wait for the clocks to stabilize. */
1706 if (INTEL_INFO(dev
)->gen
>= 4) {
1707 I915_WRITE(DPLL_MD(crtc
->pipe
),
1708 crtc
->config
->dpll_hw_state
.dpll_md
);
1710 /* The pixel multiplier can only be updated once the
1711 * DPLL is enabled and the clocks are stable.
1713 * So write it again.
1715 I915_WRITE(reg
, dpll
);
1718 /* We do this three times for luck */
1719 I915_WRITE(reg
, dpll
);
1721 udelay(150); /* wait for warmup */
1722 I915_WRITE(reg
, dpll
);
1724 udelay(150); /* wait for warmup */
1725 I915_WRITE(reg
, dpll
);
1727 udelay(150); /* wait for warmup */
1731 * i9xx_disable_pll - disable a PLL
1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe PLL to disable
1735 * Disable the PLL for @pipe, making sure the pipe is off first.
1737 * Note! This is for pre-ILK only.
1739 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1741 struct drm_device
*dev
= crtc
->base
.dev
;
1742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1743 enum pipe pipe
= crtc
->pipe
;
1745 /* Disable DVO 2x clock on both PLLs if necessary */
1747 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1748 intel_num_dvo_pipes(dev
) == 1) {
1749 I915_WRITE(DPLL(PIPE_B
),
1750 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1751 I915_WRITE(DPLL(PIPE_A
),
1752 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1755 /* Don't disable pipe or pipe PLLs if needed */
1756 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1757 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv
, pipe
);
1763 I915_WRITE(DPLL(pipe
), 0);
1764 POSTING_READ(DPLL(pipe
));
1767 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1771 /* Make sure the pipe isn't still relying on us */
1772 assert_pipe_disabled(dev_priv
, pipe
);
1775 * Leave integrated clock source and reference clock enabled for pipe B.
1776 * The latter is needed for VGA hotplug / manual detection.
1779 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1780 I915_WRITE(DPLL(pipe
), val
);
1781 POSTING_READ(DPLL(pipe
));
1785 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1787 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv
, pipe
);
1793 /* Set PLL en = 0 */
1794 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1796 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1797 I915_WRITE(DPLL(pipe
), val
);
1798 POSTING_READ(DPLL(pipe
));
1800 mutex_lock(&dev_priv
->dpio_lock
);
1802 /* Disable 10bit clock to display controller */
1803 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1804 val
&= ~DPIO_DCLKP_EN
;
1805 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1807 /* disable left/right clock distribution */
1808 if (pipe
!= PIPE_B
) {
1809 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1810 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1811 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1813 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1814 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1815 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1818 mutex_unlock(&dev_priv
->dpio_lock
);
1821 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1822 struct intel_digital_port
*dport
)
1827 switch (dport
->port
) {
1829 port_mask
= DPLL_PORTB_READY_MASK
;
1833 port_mask
= DPLL_PORTC_READY_MASK
;
1837 port_mask
= DPLL_PORTD_READY_MASK
;
1838 dpll_reg
= DPIO_PHY_STATUS
;
1844 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1845 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1846 port_name(dport
->port
), I915_READ(dpll_reg
));
1849 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1851 struct drm_device
*dev
= crtc
->base
.dev
;
1852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1855 if (WARN_ON(pll
== NULL
))
1858 WARN_ON(!pll
->config
.crtc_mask
);
1859 if (pll
->active
== 0) {
1860 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1862 assert_shared_dpll_disabled(dev_priv
, pll
);
1864 pll
->mode_set(dev_priv
, pll
);
1869 * intel_enable_shared_dpll - enable PCH PLL
1870 * @dev_priv: i915 private structure
1871 * @pipe: pipe PLL to enable
1873 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874 * drives the transcoder clock.
1876 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1878 struct drm_device
*dev
= crtc
->base
.dev
;
1879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1880 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1882 if (WARN_ON(pll
== NULL
))
1885 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1888 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1889 pll
->name
, pll
->active
, pll
->on
,
1890 crtc
->base
.base
.id
);
1892 if (pll
->active
++) {
1894 assert_shared_dpll_enabled(dev_priv
, pll
);
1899 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1901 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1902 pll
->enable(dev_priv
, pll
);
1906 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1908 struct drm_device
*dev
= crtc
->base
.dev
;
1909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1910 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1912 /* PCH only available on ILK+ */
1913 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1914 if (WARN_ON(pll
== NULL
))
1917 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1920 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921 pll
->name
, pll
->active
, pll
->on
,
1922 crtc
->base
.base
.id
);
1924 if (WARN_ON(pll
->active
== 0)) {
1925 assert_shared_dpll_disabled(dev_priv
, pll
);
1929 assert_shared_dpll_enabled(dev_priv
, pll
);
1934 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1935 pll
->disable(dev_priv
, pll
);
1938 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1941 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1944 struct drm_device
*dev
= dev_priv
->dev
;
1945 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1947 uint32_t reg
, val
, pipeconf_val
;
1949 /* PCH only available on ILK+ */
1950 BUG_ON(!HAS_PCH_SPLIT(dev
));
1952 /* Make sure PCH DPLL is enabled */
1953 assert_shared_dpll_enabled(dev_priv
,
1954 intel_crtc_to_shared_dpll(intel_crtc
));
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv
, pipe
);
1958 assert_fdi_rx_enabled(dev_priv
, pipe
);
1960 if (HAS_PCH_CPT(dev
)) {
1961 /* Workaround: Set the timing override bit before enabling the
1962 * pch transcoder. */
1963 reg
= TRANS_CHICKEN2(pipe
);
1964 val
= I915_READ(reg
);
1965 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1966 I915_WRITE(reg
, val
);
1969 reg
= PCH_TRANSCONF(pipe
);
1970 val
= I915_READ(reg
);
1971 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1973 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1975 * make the BPC in transcoder be consistent with
1976 * that in pipeconf reg.
1978 val
&= ~PIPECONF_BPC_MASK
;
1979 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1982 val
&= ~TRANS_INTERLACE_MASK
;
1983 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1984 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1985 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1986 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1988 val
|= TRANS_INTERLACED
;
1990 val
|= TRANS_PROGRESSIVE
;
1992 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1993 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1994 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1997 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1998 enum transcoder cpu_transcoder
)
2000 u32 val
, pipeconf_val
;
2002 /* PCH only available on ILK+ */
2003 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2005 /* FDI must be feeding us bits for PCH ports */
2006 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2007 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2009 /* Workaround: set timing override bit. */
2010 val
= I915_READ(_TRANSA_CHICKEN2
);
2011 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2012 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2015 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2017 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2018 PIPECONF_INTERLACED_ILK
)
2019 val
|= TRANS_INTERLACED
;
2021 val
|= TRANS_PROGRESSIVE
;
2023 I915_WRITE(LPT_TRANSCONF
, val
);
2024 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2025 DRM_ERROR("Failed to enable PCH transcoder\n");
2028 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2031 struct drm_device
*dev
= dev_priv
->dev
;
2034 /* FDI relies on the transcoder */
2035 assert_fdi_tx_disabled(dev_priv
, pipe
);
2036 assert_fdi_rx_disabled(dev_priv
, pipe
);
2038 /* Ports must be off as well */
2039 assert_pch_ports_disabled(dev_priv
, pipe
);
2041 reg
= PCH_TRANSCONF(pipe
);
2042 val
= I915_READ(reg
);
2043 val
&= ~TRANS_ENABLE
;
2044 I915_WRITE(reg
, val
);
2045 /* wait for PCH transcoder off, transcoder state */
2046 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2047 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2049 if (!HAS_PCH_IBX(dev
)) {
2050 /* Workaround: Clear the timing override chicken bit again. */
2051 reg
= TRANS_CHICKEN2(pipe
);
2052 val
= I915_READ(reg
);
2053 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2054 I915_WRITE(reg
, val
);
2058 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2062 val
= I915_READ(LPT_TRANSCONF
);
2063 val
&= ~TRANS_ENABLE
;
2064 I915_WRITE(LPT_TRANSCONF
, val
);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2067 DRM_ERROR("Failed to disable PCH transcoder\n");
2069 /* Workaround: clear timing override bit. */
2070 val
= I915_READ(_TRANSA_CHICKEN2
);
2071 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2072 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2076 * intel_enable_pipe - enable a pipe, asserting requirements
2077 * @crtc: crtc responsible for the pipe
2079 * Enable @crtc's pipe, making sure that various hardware specific requirements
2080 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2082 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2084 struct drm_device
*dev
= crtc
->base
.dev
;
2085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2086 enum pipe pipe
= crtc
->pipe
;
2087 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2089 enum pipe pch_transcoder
;
2093 assert_planes_disabled(dev_priv
, pipe
);
2094 assert_cursor_disabled(dev_priv
, pipe
);
2095 assert_sprites_disabled(dev_priv
, pipe
);
2097 if (HAS_PCH_LPT(dev_priv
->dev
))
2098 pch_transcoder
= TRANSCODER_A
;
2100 pch_transcoder
= pipe
;
2103 * A pipe without a PLL won't actually be able to drive bits from
2104 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2107 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2108 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2109 assert_dsi_pll_enabled(dev_priv
);
2111 assert_pll_enabled(dev_priv
, pipe
);
2113 if (crtc
->config
->has_pch_encoder
) {
2114 /* if driving the PCH, we need FDI enabled */
2115 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2116 assert_fdi_tx_pll_enabled(dev_priv
,
2117 (enum pipe
) cpu_transcoder
);
2119 /* FIXME: assert CPU port conditions for SNB+ */
2122 reg
= PIPECONF(cpu_transcoder
);
2123 val
= I915_READ(reg
);
2124 if (val
& PIPECONF_ENABLE
) {
2125 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2126 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2130 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2135 * intel_disable_pipe - disable a pipe, asserting requirements
2136 * @crtc: crtc whose pipes is to be disabled
2138 * Disable the pipe of @crtc, making sure that various hardware
2139 * specific requirements are met, if applicable, e.g. plane
2140 * disabled, panel fitter off, etc.
2142 * Will wait until the pipe has shut down before returning.
2144 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2146 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2147 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2148 enum pipe pipe
= crtc
->pipe
;
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2156 assert_planes_disabled(dev_priv
, pipe
);
2157 assert_cursor_disabled(dev_priv
, pipe
);
2158 assert_sprites_disabled(dev_priv
, pipe
);
2160 reg
= PIPECONF(cpu_transcoder
);
2161 val
= I915_READ(reg
);
2162 if ((val
& PIPECONF_ENABLE
) == 0)
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2169 if (crtc
->config
->double_wide
)
2170 val
&= ~PIPECONF_DOUBLE_WIDE
;
2172 /* Don't disable pipe or pipe PLLs if needed */
2173 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2174 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2175 val
&= ~PIPECONF_ENABLE
;
2177 I915_WRITE(reg
, val
);
2178 if ((val
& PIPECONF_ENABLE
) == 0)
2179 intel_wait_for_pipe_off(crtc
);
2183 * Plane regs are double buffered, going from enabled->disabled needs a
2184 * trigger in order to latch. The display address reg provides this.
2186 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2189 struct drm_device
*dev
= dev_priv
->dev
;
2190 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2192 I915_WRITE(reg
, I915_READ(reg
));
2197 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2198 * @plane: plane to be enabled
2199 * @crtc: crtc for the plane
2201 * Enable @plane on @crtc, making sure that the pipe is running first.
2203 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2204 struct drm_crtc
*crtc
)
2206 struct drm_device
*dev
= plane
->dev
;
2207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2208 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2210 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2211 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2213 if (intel_crtc
->primary_enabled
)
2216 intel_crtc
->primary_enabled
= true;
2218 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2222 * BDW signals flip done immediately if the plane
2223 * is disabled, even if the plane enable is already
2224 * armed to occur at the next vblank :(
2226 if (IS_BROADWELL(dev
))
2227 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2231 * intel_disable_primary_hw_plane - disable the primary hardware plane
2232 * @plane: plane to be disabled
2233 * @crtc: crtc for the plane
2235 * Disable @plane on @crtc, making sure that the pipe is running first.
2237 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2238 struct drm_crtc
*crtc
)
2240 struct drm_device
*dev
= plane
->dev
;
2241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2244 if (WARN_ON(!intel_crtc
->active
))
2247 if (!intel_crtc
->primary_enabled
)
2250 intel_crtc
->primary_enabled
= false;
2252 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2256 static bool need_vtd_wa(struct drm_device
*dev
)
2258 #ifdef CONFIG_INTEL_IOMMU
2259 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2266 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2267 uint64_t fb_format_modifier
)
2269 unsigned int tile_height
;
2270 uint32_t pixel_bytes
;
2272 switch (fb_format_modifier
) {
2273 case DRM_FORMAT_MOD_NONE
:
2276 case I915_FORMAT_MOD_X_TILED
:
2277 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2279 case I915_FORMAT_MOD_Y_TILED
:
2282 case I915_FORMAT_MOD_Yf_TILED
:
2283 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2284 switch (pixel_bytes
) {
2298 "128-bit pixels are not supported for display!");
2304 MISSING_CASE(fb_format_modifier
);
2313 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2314 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2316 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2317 fb_format_modifier
));
2321 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2322 const struct drm_plane_state
*plane_state
)
2324 struct intel_rotation_info
*info
= &view
->rotation_info
;
2326 *view
= i915_ggtt_view_normal
;
2331 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2334 *view
= i915_ggtt_view_rotated
;
2336 info
->height
= fb
->height
;
2337 info
->pixel_format
= fb
->pixel_format
;
2338 info
->pitch
= fb
->pitches
[0];
2339 info
->fb_modifier
= fb
->modifier
[0];
2345 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2346 struct drm_framebuffer
*fb
,
2347 const struct drm_plane_state
*plane_state
,
2348 struct intel_engine_cs
*pipelined
)
2350 struct drm_device
*dev
= fb
->dev
;
2351 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2352 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2353 struct i915_ggtt_view view
;
2357 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2359 switch (fb
->modifier
[0]) {
2360 case DRM_FORMAT_MOD_NONE
:
2361 if (INTEL_INFO(dev
)->gen
>= 9)
2362 alignment
= 256 * 1024;
2363 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2364 alignment
= 128 * 1024;
2365 else if (INTEL_INFO(dev
)->gen
>= 4)
2366 alignment
= 4 * 1024;
2368 alignment
= 64 * 1024;
2370 case I915_FORMAT_MOD_X_TILED
:
2371 if (INTEL_INFO(dev
)->gen
>= 9)
2372 alignment
= 256 * 1024;
2374 /* pin() will align the object as required by fence */
2378 case I915_FORMAT_MOD_Y_TILED
:
2379 case I915_FORMAT_MOD_Yf_TILED
:
2380 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2381 "Y tiling bo slipped through, driver bug!\n"))
2383 alignment
= 1 * 1024 * 1024;
2386 MISSING_CASE(fb
->modifier
[0]);
2390 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2394 /* Note that the w/a also requires 64 PTE of padding following the
2395 * bo. We currently fill all unused PTE with the shadow page and so
2396 * we should always have valid PTE following the scanout preventing
2399 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2400 alignment
= 256 * 1024;
2403 * Global gtt pte registers are special registers which actually forward
2404 * writes to a chunk of system memory. Which means that there is no risk
2405 * that the register values disappear as soon as we call
2406 * intel_runtime_pm_put(), so it is correct to wrap only the
2407 * pin/unpin/fence and not more.
2409 intel_runtime_pm_get(dev_priv
);
2411 dev_priv
->mm
.interruptible
= false;
2412 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2415 goto err_interruptible
;
2417 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2418 * fence, whereas 965+ only requires a fence if using
2419 * framebuffer compression. For simplicity, we always install
2420 * a fence as the cost is not that onerous.
2422 ret
= i915_gem_object_get_fence(obj
);
2426 i915_gem_object_pin_fence(obj
);
2428 dev_priv
->mm
.interruptible
= true;
2429 intel_runtime_pm_put(dev_priv
);
2433 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2435 dev_priv
->mm
.interruptible
= true;
2436 intel_runtime_pm_put(dev_priv
);
2440 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2441 const struct drm_plane_state
*plane_state
)
2443 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2444 struct i915_ggtt_view view
;
2447 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2449 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2450 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2452 i915_gem_object_unpin_fence(obj
);
2453 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2456 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2457 * is assumed to be a power-of-two. */
2458 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2459 unsigned int tiling_mode
,
2463 if (tiling_mode
!= I915_TILING_NONE
) {
2464 unsigned int tile_rows
, tiles
;
2469 tiles
= *x
/ (512/cpp
);
2472 return tile_rows
* pitch
* 8 + tiles
* 4096;
2474 unsigned int offset
;
2476 offset
= *y
* pitch
+ *x
* cpp
;
2478 *x
= (offset
& 4095) / cpp
;
2479 return offset
& -4096;
2483 static int i9xx_format_to_fourcc(int format
)
2486 case DISPPLANE_8BPP
:
2487 return DRM_FORMAT_C8
;
2488 case DISPPLANE_BGRX555
:
2489 return DRM_FORMAT_XRGB1555
;
2490 case DISPPLANE_BGRX565
:
2491 return DRM_FORMAT_RGB565
;
2493 case DISPPLANE_BGRX888
:
2494 return DRM_FORMAT_XRGB8888
;
2495 case DISPPLANE_RGBX888
:
2496 return DRM_FORMAT_XBGR8888
;
2497 case DISPPLANE_BGRX101010
:
2498 return DRM_FORMAT_XRGB2101010
;
2499 case DISPPLANE_RGBX101010
:
2500 return DRM_FORMAT_XBGR2101010
;
2504 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2507 case PLANE_CTL_FORMAT_RGB_565
:
2508 return DRM_FORMAT_RGB565
;
2510 case PLANE_CTL_FORMAT_XRGB_8888
:
2513 return DRM_FORMAT_ABGR8888
;
2515 return DRM_FORMAT_XBGR8888
;
2518 return DRM_FORMAT_ARGB8888
;
2520 return DRM_FORMAT_XRGB8888
;
2522 case PLANE_CTL_FORMAT_XRGB_2101010
:
2524 return DRM_FORMAT_XBGR2101010
;
2526 return DRM_FORMAT_XRGB2101010
;
2531 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2532 struct intel_initial_plane_config
*plane_config
)
2534 struct drm_device
*dev
= crtc
->base
.dev
;
2535 struct drm_i915_gem_object
*obj
= NULL
;
2536 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2537 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2538 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2539 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2542 size_aligned
-= base_aligned
;
2544 if (plane_config
->size
== 0)
2547 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2554 obj
->tiling_mode
= plane_config
->tiling
;
2555 if (obj
->tiling_mode
== I915_TILING_X
)
2556 obj
->stride
= fb
->pitches
[0];
2558 mode_cmd
.pixel_format
= fb
->pixel_format
;
2559 mode_cmd
.width
= fb
->width
;
2560 mode_cmd
.height
= fb
->height
;
2561 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2562 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2563 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2565 mutex_lock(&dev
->struct_mutex
);
2566 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2568 DRM_DEBUG_KMS("intel fb init failed\n");
2571 mutex_unlock(&dev
->struct_mutex
);
2573 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2577 drm_gem_object_unreference(&obj
->base
);
2578 mutex_unlock(&dev
->struct_mutex
);
2582 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2584 update_state_fb(struct drm_plane
*plane
)
2586 if (plane
->fb
== plane
->state
->fb
)
2589 if (plane
->state
->fb
)
2590 drm_framebuffer_unreference(plane
->state
->fb
);
2591 plane
->state
->fb
= plane
->fb
;
2592 if (plane
->state
->fb
)
2593 drm_framebuffer_reference(plane
->state
->fb
);
2597 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2598 struct intel_initial_plane_config
*plane_config
)
2600 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2603 struct intel_crtc
*i
;
2604 struct drm_i915_gem_object
*obj
;
2605 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2606 struct drm_framebuffer
*fb
;
2608 if (!plane_config
->fb
)
2611 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2612 fb
= &plane_config
->fb
->base
;
2616 kfree(plane_config
->fb
);
2619 * Failed to alloc the obj, check to see if we should share
2620 * an fb with another CRTC instead
2622 for_each_crtc(dev
, c
) {
2623 i
= to_intel_crtc(c
);
2625 if (c
== &intel_crtc
->base
)
2631 fb
= c
->primary
->fb
;
2635 obj
= intel_fb_obj(fb
);
2636 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2637 drm_framebuffer_reference(fb
);
2645 obj
= intel_fb_obj(fb
);
2646 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2647 dev_priv
->preserve_bios_swizzle
= true;
2650 primary
->state
->crtc
= &intel_crtc
->base
;
2651 primary
->crtc
= &intel_crtc
->base
;
2652 update_state_fb(primary
);
2653 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2656 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2657 struct drm_framebuffer
*fb
,
2660 struct drm_device
*dev
= crtc
->dev
;
2661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2662 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2663 struct drm_i915_gem_object
*obj
;
2664 int plane
= intel_crtc
->plane
;
2665 unsigned long linear_offset
;
2667 u32 reg
= DSPCNTR(plane
);
2670 if (!intel_crtc
->primary_enabled
) {
2672 if (INTEL_INFO(dev
)->gen
>= 4)
2673 I915_WRITE(DSPSURF(plane
), 0);
2675 I915_WRITE(DSPADDR(plane
), 0);
2680 obj
= intel_fb_obj(fb
);
2681 if (WARN_ON(obj
== NULL
))
2684 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2686 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2688 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2690 if (INTEL_INFO(dev
)->gen
< 4) {
2691 if (intel_crtc
->pipe
== PIPE_B
)
2692 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2694 /* pipesrc and dspsize control the size that is scaled from,
2695 * which should always be the user's requested size.
2697 I915_WRITE(DSPSIZE(plane
),
2698 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2699 (intel_crtc
->config
->pipe_src_w
- 1));
2700 I915_WRITE(DSPPOS(plane
), 0);
2701 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2702 I915_WRITE(PRIMSIZE(plane
),
2703 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2704 (intel_crtc
->config
->pipe_src_w
- 1));
2705 I915_WRITE(PRIMPOS(plane
), 0);
2706 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2709 switch (fb
->pixel_format
) {
2711 dspcntr
|= DISPPLANE_8BPP
;
2713 case DRM_FORMAT_XRGB1555
:
2714 case DRM_FORMAT_ARGB1555
:
2715 dspcntr
|= DISPPLANE_BGRX555
;
2717 case DRM_FORMAT_RGB565
:
2718 dspcntr
|= DISPPLANE_BGRX565
;
2720 case DRM_FORMAT_XRGB8888
:
2721 case DRM_FORMAT_ARGB8888
:
2722 dspcntr
|= DISPPLANE_BGRX888
;
2724 case DRM_FORMAT_XBGR8888
:
2725 case DRM_FORMAT_ABGR8888
:
2726 dspcntr
|= DISPPLANE_RGBX888
;
2728 case DRM_FORMAT_XRGB2101010
:
2729 case DRM_FORMAT_ARGB2101010
:
2730 dspcntr
|= DISPPLANE_BGRX101010
;
2732 case DRM_FORMAT_XBGR2101010
:
2733 case DRM_FORMAT_ABGR2101010
:
2734 dspcntr
|= DISPPLANE_RGBX101010
;
2740 if (INTEL_INFO(dev
)->gen
>= 4 &&
2741 obj
->tiling_mode
!= I915_TILING_NONE
)
2742 dspcntr
|= DISPPLANE_TILED
;
2745 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2747 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2749 if (INTEL_INFO(dev
)->gen
>= 4) {
2750 intel_crtc
->dspaddr_offset
=
2751 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2754 linear_offset
-= intel_crtc
->dspaddr_offset
;
2756 intel_crtc
->dspaddr_offset
= linear_offset
;
2759 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2760 dspcntr
|= DISPPLANE_ROTATE_180
;
2762 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2763 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2765 /* Finding the last pixel of the last line of the display
2766 data and adding to linear_offset*/
2768 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2769 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2772 I915_WRITE(reg
, dspcntr
);
2774 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2775 if (INTEL_INFO(dev
)->gen
>= 4) {
2776 I915_WRITE(DSPSURF(plane
),
2777 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2778 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2779 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2781 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2785 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2786 struct drm_framebuffer
*fb
,
2789 struct drm_device
*dev
= crtc
->dev
;
2790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2791 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2792 struct drm_i915_gem_object
*obj
;
2793 int plane
= intel_crtc
->plane
;
2794 unsigned long linear_offset
;
2796 u32 reg
= DSPCNTR(plane
);
2799 if (!intel_crtc
->primary_enabled
) {
2801 I915_WRITE(DSPSURF(plane
), 0);
2806 obj
= intel_fb_obj(fb
);
2807 if (WARN_ON(obj
== NULL
))
2810 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2812 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2814 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2816 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2817 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2819 switch (fb
->pixel_format
) {
2821 dspcntr
|= DISPPLANE_8BPP
;
2823 case DRM_FORMAT_RGB565
:
2824 dspcntr
|= DISPPLANE_BGRX565
;
2826 case DRM_FORMAT_XRGB8888
:
2827 case DRM_FORMAT_ARGB8888
:
2828 dspcntr
|= DISPPLANE_BGRX888
;
2830 case DRM_FORMAT_XBGR8888
:
2831 case DRM_FORMAT_ABGR8888
:
2832 dspcntr
|= DISPPLANE_RGBX888
;
2834 case DRM_FORMAT_XRGB2101010
:
2835 case DRM_FORMAT_ARGB2101010
:
2836 dspcntr
|= DISPPLANE_BGRX101010
;
2838 case DRM_FORMAT_XBGR2101010
:
2839 case DRM_FORMAT_ABGR2101010
:
2840 dspcntr
|= DISPPLANE_RGBX101010
;
2846 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2847 dspcntr
|= DISPPLANE_TILED
;
2849 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2850 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2852 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2853 intel_crtc
->dspaddr_offset
=
2854 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2857 linear_offset
-= intel_crtc
->dspaddr_offset
;
2858 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2859 dspcntr
|= DISPPLANE_ROTATE_180
;
2861 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2862 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2863 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2865 /* Finding the last pixel of the last line of the display
2866 data and adding to linear_offset*/
2868 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2869 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2873 I915_WRITE(reg
, dspcntr
);
2875 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2876 I915_WRITE(DSPSURF(plane
),
2877 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2878 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2879 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2881 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2882 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2887 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2888 uint32_t pixel_format
)
2890 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2893 * The stride is either expressed as a multiple of 64 bytes
2894 * chunks for linear buffers or in number of tiles for tiled
2897 switch (fb_modifier
) {
2898 case DRM_FORMAT_MOD_NONE
:
2900 case I915_FORMAT_MOD_X_TILED
:
2901 if (INTEL_INFO(dev
)->gen
== 2)
2904 case I915_FORMAT_MOD_Y_TILED
:
2905 /* No need to check for old gens and Y tiling since this is
2906 * about the display engine and those will be blocked before
2910 case I915_FORMAT_MOD_Yf_TILED
:
2911 if (bits_per_pixel
== 8)
2916 MISSING_CASE(fb_modifier
);
2921 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2922 struct drm_i915_gem_object
*obj
)
2924 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2926 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2927 view
= &i915_ggtt_view_rotated
;
2929 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2932 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2933 struct drm_framebuffer
*fb
,
2936 struct drm_device
*dev
= crtc
->dev
;
2937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2938 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2939 struct drm_i915_gem_object
*obj
;
2940 int pipe
= intel_crtc
->pipe
;
2941 u32 plane_ctl
, stride_div
, stride
;
2942 u32 tile_height
, plane_offset
, plane_size
;
2943 unsigned int rotation
;
2944 int x_offset
, y_offset
;
2945 unsigned long surf_addr
;
2946 struct drm_plane
*plane
;
2948 if (!intel_crtc
->primary_enabled
) {
2949 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2950 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2951 POSTING_READ(PLANE_CTL(pipe
, 0));
2955 plane_ctl
= PLANE_CTL_ENABLE
|
2956 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2957 PLANE_CTL_PIPE_CSC_ENABLE
;
2959 switch (fb
->pixel_format
) {
2960 case DRM_FORMAT_RGB565
:
2961 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2963 case DRM_FORMAT_XRGB8888
:
2964 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2966 case DRM_FORMAT_ARGB8888
:
2967 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2968 plane_ctl
|= PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2970 case DRM_FORMAT_XBGR8888
:
2971 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2972 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2974 case DRM_FORMAT_ABGR8888
:
2975 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2976 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2977 plane_ctl
|= PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2979 case DRM_FORMAT_XRGB2101010
:
2980 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2982 case DRM_FORMAT_XBGR2101010
:
2983 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2984 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2990 switch (fb
->modifier
[0]) {
2991 case DRM_FORMAT_MOD_NONE
:
2993 case I915_FORMAT_MOD_X_TILED
:
2994 plane_ctl
|= PLANE_CTL_TILED_X
;
2996 case I915_FORMAT_MOD_Y_TILED
:
2997 plane_ctl
|= PLANE_CTL_TILED_Y
;
2999 case I915_FORMAT_MOD_Yf_TILED
:
3000 plane_ctl
|= PLANE_CTL_TILED_YF
;
3003 MISSING_CASE(fb
->modifier
[0]);
3006 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3008 plane
= crtc
->primary
;
3009 rotation
= plane
->state
->rotation
;
3011 case BIT(DRM_ROTATE_90
):
3012 plane_ctl
|= PLANE_CTL_ROTATE_90
;
3015 case BIT(DRM_ROTATE_180
):
3016 plane_ctl
|= PLANE_CTL_ROTATE_180
;
3019 case BIT(DRM_ROTATE_270
):
3020 plane_ctl
|= PLANE_CTL_ROTATE_270
;
3024 obj
= intel_fb_obj(fb
);
3025 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3027 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3029 if (intel_rotation_90_or_270(rotation
)) {
3030 /* stride = Surface height in tiles */
3031 tile_height
= intel_tile_height(dev
, fb
->bits_per_pixel
,
3033 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3034 x_offset
= stride
* tile_height
- y
- (plane
->state
->src_h
>> 16);
3036 plane_size
= ((plane
->state
->src_w
>> 16) - 1) << 16 |
3037 ((plane
->state
->src_h
>> 16) - 1);
3039 stride
= fb
->pitches
[0] / stride_div
;
3042 plane_size
= ((plane
->state
->src_h
>> 16) - 1) << 16 |
3043 ((plane
->state
->src_w
>> 16) - 1);
3045 plane_offset
= y_offset
<< 16 | x_offset
;
3047 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3048 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3049 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3050 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3051 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3052 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3054 POSTING_READ(PLANE_SURF(pipe
, 0));
3057 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3059 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3060 int x
, int y
, enum mode_set_atomic state
)
3062 struct drm_device
*dev
= crtc
->dev
;
3063 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3065 if (dev_priv
->display
.disable_fbc
)
3066 dev_priv
->display
.disable_fbc(dev
);
3068 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3073 static void intel_complete_page_flips(struct drm_device
*dev
)
3075 struct drm_crtc
*crtc
;
3077 for_each_crtc(dev
, crtc
) {
3078 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3079 enum plane plane
= intel_crtc
->plane
;
3081 intel_prepare_page_flip(dev
, plane
);
3082 intel_finish_page_flip_plane(dev
, plane
);
3086 static void intel_update_primary_planes(struct drm_device
*dev
)
3088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3089 struct drm_crtc
*crtc
;
3091 for_each_crtc(dev
, crtc
) {
3092 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3094 drm_modeset_lock(&crtc
->mutex
, NULL
);
3096 * FIXME: Once we have proper support for primary planes (and
3097 * disabling them without disabling the entire crtc) allow again
3098 * a NULL crtc->primary->fb.
3100 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3101 dev_priv
->display
.update_primary_plane(crtc
,
3105 drm_modeset_unlock(&crtc
->mutex
);
3109 void intel_prepare_reset(struct drm_device
*dev
)
3111 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3112 struct intel_crtc
*crtc
;
3114 /* no reset support for gen2 */
3118 /* reset doesn't touch the display */
3119 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3122 drm_modeset_lock_all(dev
);
3125 * Disabling the crtcs gracefully seems nicer. Also the
3126 * g33 docs say we should at least disable all the planes.
3128 for_each_intel_crtc(dev
, crtc
) {
3130 dev_priv
->display
.crtc_disable(&crtc
->base
);
3134 void intel_finish_reset(struct drm_device
*dev
)
3136 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3139 * Flips in the rings will be nuked by the reset,
3140 * so complete all pending flips so that user space
3141 * will get its events and not get stuck.
3143 intel_complete_page_flips(dev
);
3145 /* no reset support for gen2 */
3149 /* reset doesn't touch the display */
3150 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3152 * Flips in the rings have been nuked by the reset,
3153 * so update the base address of all primary
3154 * planes to the the last fb to make sure we're
3155 * showing the correct fb after a reset.
3157 intel_update_primary_planes(dev
);
3162 * The display has been reset as well,
3163 * so need a full re-initialization.
3165 intel_runtime_pm_disable_interrupts(dev_priv
);
3166 intel_runtime_pm_enable_interrupts(dev_priv
);
3168 intel_modeset_init_hw(dev
);
3170 spin_lock_irq(&dev_priv
->irq_lock
);
3171 if (dev_priv
->display
.hpd_irq_setup
)
3172 dev_priv
->display
.hpd_irq_setup(dev
);
3173 spin_unlock_irq(&dev_priv
->irq_lock
);
3175 intel_modeset_setup_hw_state(dev
, true);
3177 intel_hpd_init(dev_priv
);
3179 drm_modeset_unlock_all(dev
);
3183 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3185 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3186 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3187 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3190 /* Big Hammer, we also need to ensure that any pending
3191 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3192 * current scanout is retired before unpinning the old
3195 * This should only fail upon a hung GPU, in which case we
3196 * can safely continue.
3198 dev_priv
->mm
.interruptible
= false;
3199 ret
= i915_gem_object_finish_gpu(obj
);
3200 dev_priv
->mm
.interruptible
= was_interruptible
;
3205 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3207 struct drm_device
*dev
= crtc
->dev
;
3208 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3209 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3212 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3213 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3216 spin_lock_irq(&dev
->event_lock
);
3217 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3218 spin_unlock_irq(&dev
->event_lock
);
3223 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3225 struct drm_device
*dev
= crtc
->base
.dev
;
3226 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3227 const struct drm_display_mode
*adjusted_mode
;
3233 * Update pipe size and adjust fitter if needed: the reason for this is
3234 * that in compute_mode_changes we check the native mode (not the pfit
3235 * mode) to see if we can flip rather than do a full mode set. In the
3236 * fastboot case, we'll flip, but if we don't update the pipesrc and
3237 * pfit state, we'll end up with a big fb scanned out into the wrong
3240 * To fix this properly, we need to hoist the checks up into
3241 * compute_mode_changes (or above), check the actual pfit state and
3242 * whether the platform allows pfit disable with pipe active, and only
3243 * then update the pipesrc and pfit state, even on the flip path.
3246 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3248 I915_WRITE(PIPESRC(crtc
->pipe
),
3249 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3250 (adjusted_mode
->crtc_vdisplay
- 1));
3251 if (!crtc
->config
->pch_pfit
.enabled
&&
3252 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3253 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3254 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3255 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3256 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3258 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3259 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3262 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3264 struct drm_device
*dev
= crtc
->dev
;
3265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3266 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3267 int pipe
= intel_crtc
->pipe
;
3270 /* enable normal train */
3271 reg
= FDI_TX_CTL(pipe
);
3272 temp
= I915_READ(reg
);
3273 if (IS_IVYBRIDGE(dev
)) {
3274 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3275 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3277 temp
&= ~FDI_LINK_TRAIN_NONE
;
3278 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3280 I915_WRITE(reg
, temp
);
3282 reg
= FDI_RX_CTL(pipe
);
3283 temp
= I915_READ(reg
);
3284 if (HAS_PCH_CPT(dev
)) {
3285 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3286 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3288 temp
&= ~FDI_LINK_TRAIN_NONE
;
3289 temp
|= FDI_LINK_TRAIN_NONE
;
3291 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3293 /* wait one idle pattern time */
3297 /* IVB wants error correction enabled */
3298 if (IS_IVYBRIDGE(dev
))
3299 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3300 FDI_FE_ERRC_ENABLE
);
3303 /* The FDI link training functions for ILK/Ibexpeak. */
3304 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3306 struct drm_device
*dev
= crtc
->dev
;
3307 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3309 int pipe
= intel_crtc
->pipe
;
3310 u32 reg
, temp
, tries
;
3312 /* FDI needs bits from pipe first */
3313 assert_pipe_enabled(dev_priv
, pipe
);
3315 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3317 reg
= FDI_RX_IMR(pipe
);
3318 temp
= I915_READ(reg
);
3319 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3320 temp
&= ~FDI_RX_BIT_LOCK
;
3321 I915_WRITE(reg
, temp
);
3325 /* enable CPU FDI TX and PCH FDI RX */
3326 reg
= FDI_TX_CTL(pipe
);
3327 temp
= I915_READ(reg
);
3328 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3329 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3330 temp
&= ~FDI_LINK_TRAIN_NONE
;
3331 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3332 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3334 reg
= FDI_RX_CTL(pipe
);
3335 temp
= I915_READ(reg
);
3336 temp
&= ~FDI_LINK_TRAIN_NONE
;
3337 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3338 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3343 /* Ironlake workaround, enable clock pointer after FDI enable*/
3344 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3345 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3346 FDI_RX_PHASE_SYNC_POINTER_EN
);
3348 reg
= FDI_RX_IIR(pipe
);
3349 for (tries
= 0; tries
< 5; tries
++) {
3350 temp
= I915_READ(reg
);
3351 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3353 if ((temp
& FDI_RX_BIT_LOCK
)) {
3354 DRM_DEBUG_KMS("FDI train 1 done.\n");
3355 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3360 DRM_ERROR("FDI train 1 fail!\n");
3363 reg
= FDI_TX_CTL(pipe
);
3364 temp
= I915_READ(reg
);
3365 temp
&= ~FDI_LINK_TRAIN_NONE
;
3366 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3367 I915_WRITE(reg
, temp
);
3369 reg
= FDI_RX_CTL(pipe
);
3370 temp
= I915_READ(reg
);
3371 temp
&= ~FDI_LINK_TRAIN_NONE
;
3372 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3373 I915_WRITE(reg
, temp
);
3378 reg
= FDI_RX_IIR(pipe
);
3379 for (tries
= 0; tries
< 5; tries
++) {
3380 temp
= I915_READ(reg
);
3381 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3383 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3384 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3385 DRM_DEBUG_KMS("FDI train 2 done.\n");
3390 DRM_ERROR("FDI train 2 fail!\n");
3392 DRM_DEBUG_KMS("FDI train done\n");
3396 static const int snb_b_fdi_train_param
[] = {
3397 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3398 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3399 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3400 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3403 /* The FDI link training functions for SNB/Cougarpoint. */
3404 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3406 struct drm_device
*dev
= crtc
->dev
;
3407 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3408 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3409 int pipe
= intel_crtc
->pipe
;
3410 u32 reg
, temp
, i
, retry
;
3412 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3414 reg
= FDI_RX_IMR(pipe
);
3415 temp
= I915_READ(reg
);
3416 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3417 temp
&= ~FDI_RX_BIT_LOCK
;
3418 I915_WRITE(reg
, temp
);
3423 /* enable CPU FDI TX and PCH FDI RX */
3424 reg
= FDI_TX_CTL(pipe
);
3425 temp
= I915_READ(reg
);
3426 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3427 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3428 temp
&= ~FDI_LINK_TRAIN_NONE
;
3429 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3430 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3432 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3433 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3435 I915_WRITE(FDI_RX_MISC(pipe
),
3436 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3438 reg
= FDI_RX_CTL(pipe
);
3439 temp
= I915_READ(reg
);
3440 if (HAS_PCH_CPT(dev
)) {
3441 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3442 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3444 temp
&= ~FDI_LINK_TRAIN_NONE
;
3445 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3447 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3452 for (i
= 0; i
< 4; i
++) {
3453 reg
= FDI_TX_CTL(pipe
);
3454 temp
= I915_READ(reg
);
3455 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3456 temp
|= snb_b_fdi_train_param
[i
];
3457 I915_WRITE(reg
, temp
);
3462 for (retry
= 0; retry
< 5; retry
++) {
3463 reg
= FDI_RX_IIR(pipe
);
3464 temp
= I915_READ(reg
);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3466 if (temp
& FDI_RX_BIT_LOCK
) {
3467 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3468 DRM_DEBUG_KMS("FDI train 1 done.\n");
3477 DRM_ERROR("FDI train 1 fail!\n");
3480 reg
= FDI_TX_CTL(pipe
);
3481 temp
= I915_READ(reg
);
3482 temp
&= ~FDI_LINK_TRAIN_NONE
;
3483 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3485 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3487 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3489 I915_WRITE(reg
, temp
);
3491 reg
= FDI_RX_CTL(pipe
);
3492 temp
= I915_READ(reg
);
3493 if (HAS_PCH_CPT(dev
)) {
3494 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3495 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3497 temp
&= ~FDI_LINK_TRAIN_NONE
;
3498 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3500 I915_WRITE(reg
, temp
);
3505 for (i
= 0; i
< 4; i
++) {
3506 reg
= FDI_TX_CTL(pipe
);
3507 temp
= I915_READ(reg
);
3508 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3509 temp
|= snb_b_fdi_train_param
[i
];
3510 I915_WRITE(reg
, temp
);
3515 for (retry
= 0; retry
< 5; retry
++) {
3516 reg
= FDI_RX_IIR(pipe
);
3517 temp
= I915_READ(reg
);
3518 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3519 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3520 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3521 DRM_DEBUG_KMS("FDI train 2 done.\n");
3530 DRM_ERROR("FDI train 2 fail!\n");
3532 DRM_DEBUG_KMS("FDI train done.\n");
3535 /* Manual link training for Ivy Bridge A0 parts */
3536 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3538 struct drm_device
*dev
= crtc
->dev
;
3539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3540 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3541 int pipe
= intel_crtc
->pipe
;
3542 u32 reg
, temp
, i
, j
;
3544 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3546 reg
= FDI_RX_IMR(pipe
);
3547 temp
= I915_READ(reg
);
3548 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3549 temp
&= ~FDI_RX_BIT_LOCK
;
3550 I915_WRITE(reg
, temp
);
3555 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3556 I915_READ(FDI_RX_IIR(pipe
)));
3558 /* Try each vswing and preemphasis setting twice before moving on */
3559 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3560 /* disable first in case we need to retry */
3561 reg
= FDI_TX_CTL(pipe
);
3562 temp
= I915_READ(reg
);
3563 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3564 temp
&= ~FDI_TX_ENABLE
;
3565 I915_WRITE(reg
, temp
);
3567 reg
= FDI_RX_CTL(pipe
);
3568 temp
= I915_READ(reg
);
3569 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3570 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3571 temp
&= ~FDI_RX_ENABLE
;
3572 I915_WRITE(reg
, temp
);
3574 /* enable CPU FDI TX and PCH FDI RX */
3575 reg
= FDI_TX_CTL(pipe
);
3576 temp
= I915_READ(reg
);
3577 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3578 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3579 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3580 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3581 temp
|= snb_b_fdi_train_param
[j
/2];
3582 temp
|= FDI_COMPOSITE_SYNC
;
3583 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3585 I915_WRITE(FDI_RX_MISC(pipe
),
3586 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3588 reg
= FDI_RX_CTL(pipe
);
3589 temp
= I915_READ(reg
);
3590 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3591 temp
|= FDI_COMPOSITE_SYNC
;
3592 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3595 udelay(1); /* should be 0.5us */
3597 for (i
= 0; i
< 4; i
++) {
3598 reg
= FDI_RX_IIR(pipe
);
3599 temp
= I915_READ(reg
);
3600 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3602 if (temp
& FDI_RX_BIT_LOCK
||
3603 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3604 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3605 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3609 udelay(1); /* should be 0.5us */
3612 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3617 reg
= FDI_TX_CTL(pipe
);
3618 temp
= I915_READ(reg
);
3619 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3620 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3621 I915_WRITE(reg
, temp
);
3623 reg
= FDI_RX_CTL(pipe
);
3624 temp
= I915_READ(reg
);
3625 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3626 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3627 I915_WRITE(reg
, temp
);
3630 udelay(2); /* should be 1.5us */
3632 for (i
= 0; i
< 4; i
++) {
3633 reg
= FDI_RX_IIR(pipe
);
3634 temp
= I915_READ(reg
);
3635 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3637 if (temp
& FDI_RX_SYMBOL_LOCK
||
3638 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3639 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3640 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3644 udelay(2); /* should be 1.5us */
3647 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3651 DRM_DEBUG_KMS("FDI train done.\n");
3654 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3656 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3658 int pipe
= intel_crtc
->pipe
;
3662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3663 reg
= FDI_RX_CTL(pipe
);
3664 temp
= I915_READ(reg
);
3665 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3666 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3667 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3668 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3673 /* Switch from Rawclk to PCDclk */
3674 temp
= I915_READ(reg
);
3675 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3680 /* Enable CPU FDI TX PLL, always on for Ironlake */
3681 reg
= FDI_TX_CTL(pipe
);
3682 temp
= I915_READ(reg
);
3683 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3684 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3691 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3693 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3694 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3695 int pipe
= intel_crtc
->pipe
;
3698 /* Switch from PCDclk to Rawclk */
3699 reg
= FDI_RX_CTL(pipe
);
3700 temp
= I915_READ(reg
);
3701 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3703 /* Disable CPU FDI TX PLL */
3704 reg
= FDI_TX_CTL(pipe
);
3705 temp
= I915_READ(reg
);
3706 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3711 reg
= FDI_RX_CTL(pipe
);
3712 temp
= I915_READ(reg
);
3713 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3715 /* Wait for the clocks to turn off. */
3720 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3722 struct drm_device
*dev
= crtc
->dev
;
3723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3724 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3725 int pipe
= intel_crtc
->pipe
;
3728 /* disable CPU FDI tx and PCH FDI rx */
3729 reg
= FDI_TX_CTL(pipe
);
3730 temp
= I915_READ(reg
);
3731 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3734 reg
= FDI_RX_CTL(pipe
);
3735 temp
= I915_READ(reg
);
3736 temp
&= ~(0x7 << 16);
3737 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3738 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3743 /* Ironlake workaround, disable clock pointer after downing FDI */
3744 if (HAS_PCH_IBX(dev
))
3745 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3747 /* still set train pattern 1 */
3748 reg
= FDI_TX_CTL(pipe
);
3749 temp
= I915_READ(reg
);
3750 temp
&= ~FDI_LINK_TRAIN_NONE
;
3751 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3752 I915_WRITE(reg
, temp
);
3754 reg
= FDI_RX_CTL(pipe
);
3755 temp
= I915_READ(reg
);
3756 if (HAS_PCH_CPT(dev
)) {
3757 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3758 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3760 temp
&= ~FDI_LINK_TRAIN_NONE
;
3761 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3763 /* BPC in FDI rx is consistent with that in PIPECONF */
3764 temp
&= ~(0x07 << 16);
3765 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3766 I915_WRITE(reg
, temp
);
3772 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3774 struct intel_crtc
*crtc
;
3776 /* Note that we don't need to be called with mode_config.lock here
3777 * as our list of CRTC objects is static for the lifetime of the
3778 * device and so cannot disappear as we iterate. Similarly, we can
3779 * happily treat the predicates as racy, atomic checks as userspace
3780 * cannot claim and pin a new fb without at least acquring the
3781 * struct_mutex and so serialising with us.
3783 for_each_intel_crtc(dev
, crtc
) {
3784 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3787 if (crtc
->unpin_work
)
3788 intel_wait_for_vblank(dev
, crtc
->pipe
);
3796 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3798 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3799 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3801 /* ensure that the unpin work is consistent wrt ->pending. */
3803 intel_crtc
->unpin_work
= NULL
;
3806 drm_send_vblank_event(intel_crtc
->base
.dev
,
3810 drm_crtc_vblank_put(&intel_crtc
->base
);
3812 wake_up_all(&dev_priv
->pending_flip_queue
);
3813 queue_work(dev_priv
->wq
, &work
->work
);
3815 trace_i915_flip_complete(intel_crtc
->plane
,
3816 work
->pending_flip_obj
);
3819 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3821 struct drm_device
*dev
= crtc
->dev
;
3822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3824 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3825 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3826 !intel_crtc_has_pending_flip(crtc
),
3828 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3830 spin_lock_irq(&dev
->event_lock
);
3831 if (intel_crtc
->unpin_work
) {
3832 WARN_ONCE(1, "Removing stuck page flip\n");
3833 page_flip_completed(intel_crtc
);
3835 spin_unlock_irq(&dev
->event_lock
);
3838 if (crtc
->primary
->fb
) {
3839 mutex_lock(&dev
->struct_mutex
);
3840 intel_finish_fb(crtc
->primary
->fb
);
3841 mutex_unlock(&dev
->struct_mutex
);
3845 /* Program iCLKIP clock to the desired frequency */
3846 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3848 struct drm_device
*dev
= crtc
->dev
;
3849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3850 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3851 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3854 mutex_lock(&dev_priv
->dpio_lock
);
3856 /* It is necessary to ungate the pixclk gate prior to programming
3857 * the divisors, and gate it back when it is done.
3859 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3861 /* Disable SSCCTL */
3862 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3863 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3867 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3868 if (clock
== 20000) {
3873 /* The iCLK virtual clock root frequency is in MHz,
3874 * but the adjusted_mode->crtc_clock in in KHz. To get the
3875 * divisors, it is necessary to divide one by another, so we
3876 * convert the virtual clock precision to KHz here for higher
3879 u32 iclk_virtual_root_freq
= 172800 * 1000;
3880 u32 iclk_pi_range
= 64;
3881 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3883 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3884 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3885 pi_value
= desired_divisor
% iclk_pi_range
;
3888 divsel
= msb_divisor_value
- 2;
3889 phaseinc
= pi_value
;
3892 /* This should not happen with any sane values */
3893 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3894 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3895 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3896 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3898 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3905 /* Program SSCDIVINTPHASE6 */
3906 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3907 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3908 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3909 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3910 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3911 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3912 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3913 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3915 /* Program SSCAUXDIV */
3916 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3917 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3918 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3919 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3921 /* Enable modulator and associated divider */
3922 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3923 temp
&= ~SBI_SSCCTL_DISABLE
;
3924 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3926 /* Wait for initialization time */
3929 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3931 mutex_unlock(&dev_priv
->dpio_lock
);
3934 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3935 enum pipe pch_transcoder
)
3937 struct drm_device
*dev
= crtc
->base
.dev
;
3938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3939 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3941 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3942 I915_READ(HTOTAL(cpu_transcoder
)));
3943 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3944 I915_READ(HBLANK(cpu_transcoder
)));
3945 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3946 I915_READ(HSYNC(cpu_transcoder
)));
3948 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3949 I915_READ(VTOTAL(cpu_transcoder
)));
3950 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3951 I915_READ(VBLANK(cpu_transcoder
)));
3952 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3953 I915_READ(VSYNC(cpu_transcoder
)));
3954 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3955 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3958 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
3960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3963 temp
= I915_READ(SOUTH_CHICKEN1
);
3964 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
3967 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3968 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3970 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3972 temp
|= FDI_BC_BIFURCATION_SELECT
;
3974 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
3975 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3976 POSTING_READ(SOUTH_CHICKEN1
);
3979 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3981 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3983 switch (intel_crtc
->pipe
) {
3987 if (intel_crtc
->config
->fdi_lanes
> 2)
3988 cpt_set_fdi_bc_bifurcation(dev
, false);
3990 cpt_set_fdi_bc_bifurcation(dev
, true);
3994 cpt_set_fdi_bc_bifurcation(dev
, true);
4003 * Enable PCH resources required for PCH ports:
4005 * - FDI training & RX/TX
4006 * - update transcoder timings
4007 * - DP transcoding bits
4010 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4012 struct drm_device
*dev
= crtc
->dev
;
4013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4014 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4015 int pipe
= intel_crtc
->pipe
;
4018 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4020 if (IS_IVYBRIDGE(dev
))
4021 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4023 /* Write the TU size bits before fdi link training, so that error
4024 * detection works. */
4025 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4026 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4028 /* For PCH output, training FDI link */
4029 dev_priv
->display
.fdi_link_train(crtc
);
4031 /* We need to program the right clock selection before writing the pixel
4032 * mutliplier into the DPLL. */
4033 if (HAS_PCH_CPT(dev
)) {
4036 temp
= I915_READ(PCH_DPLL_SEL
);
4037 temp
|= TRANS_DPLL_ENABLE(pipe
);
4038 sel
= TRANS_DPLLB_SEL(pipe
);
4039 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4043 I915_WRITE(PCH_DPLL_SEL
, temp
);
4046 /* XXX: pch pll's can be enabled any time before we enable the PCH
4047 * transcoder, and we actually should do this to not upset any PCH
4048 * transcoder that already use the clock when we share it.
4050 * Note that enable_shared_dpll tries to do the right thing, but
4051 * get_shared_dpll unconditionally resets the pll - we need that to have
4052 * the right LVDS enable sequence. */
4053 intel_enable_shared_dpll(intel_crtc
);
4055 /* set transcoder timing, panel must allow it */
4056 assert_panel_unlocked(dev_priv
, pipe
);
4057 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4059 intel_fdi_normal_train(crtc
);
4061 /* For PCH DP, enable TRANS_DP_CTL */
4062 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4063 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4064 reg
= TRANS_DP_CTL(pipe
);
4065 temp
= I915_READ(reg
);
4066 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4067 TRANS_DP_SYNC_MASK
|
4069 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
4070 TRANS_DP_ENH_FRAMING
);
4071 temp
|= bpc
<< 9; /* same format but at 11:9 */
4073 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4074 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4075 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4076 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4078 switch (intel_trans_dp_port_sel(crtc
)) {
4080 temp
|= TRANS_DP_PORT_SEL_B
;
4083 temp
|= TRANS_DP_PORT_SEL_C
;
4086 temp
|= TRANS_DP_PORT_SEL_D
;
4092 I915_WRITE(reg
, temp
);
4095 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4098 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4100 struct drm_device
*dev
= crtc
->dev
;
4101 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4102 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4103 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4105 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4107 lpt_program_iclkip(crtc
);
4109 /* Set transcoder timing. */
4110 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4112 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4115 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
4117 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4122 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4123 WARN(1, "bad %s crtc mask\n", pll
->name
);
4127 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4128 if (pll
->config
.crtc_mask
== 0) {
4130 WARN_ON(pll
->active
);
4133 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4136 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4137 struct intel_crtc_state
*crtc_state
)
4139 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4140 struct intel_shared_dpll
*pll
;
4141 enum intel_dpll_id i
;
4143 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4144 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4145 i
= (enum intel_dpll_id
) crtc
->pipe
;
4146 pll
= &dev_priv
->shared_dplls
[i
];
4148 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4149 crtc
->base
.base
.id
, pll
->name
);
4151 WARN_ON(pll
->new_config
->crtc_mask
);
4156 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4157 pll
= &dev_priv
->shared_dplls
[i
];
4159 /* Only want to check enabled timings first */
4160 if (pll
->new_config
->crtc_mask
== 0)
4163 if (memcmp(&crtc_state
->dpll_hw_state
,
4164 &pll
->new_config
->hw_state
,
4165 sizeof(pll
->new_config
->hw_state
)) == 0) {
4166 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4167 crtc
->base
.base
.id
, pll
->name
,
4168 pll
->new_config
->crtc_mask
,
4174 /* Ok no matching timings, maybe there's a free one? */
4175 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4176 pll
= &dev_priv
->shared_dplls
[i
];
4177 if (pll
->new_config
->crtc_mask
== 0) {
4178 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4179 crtc
->base
.base
.id
, pll
->name
);
4187 if (pll
->new_config
->crtc_mask
== 0)
4188 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4190 crtc_state
->shared_dpll
= i
;
4191 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4192 pipe_name(crtc
->pipe
));
4194 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4200 * intel_shared_dpll_start_config - start a new PLL staged config
4201 * @dev_priv: DRM device
4202 * @clear_pipes: mask of pipes that will have their PLLs freed
4204 * Starts a new PLL staged config, copying the current config but
4205 * releasing the references of pipes specified in clear_pipes.
4207 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4208 unsigned clear_pipes
)
4210 struct intel_shared_dpll
*pll
;
4211 enum intel_dpll_id i
;
4213 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4214 pll
= &dev_priv
->shared_dplls
[i
];
4216 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4218 if (!pll
->new_config
)
4221 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4228 pll
= &dev_priv
->shared_dplls
[i
];
4229 kfree(pll
->new_config
);
4230 pll
->new_config
= NULL
;
4236 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4238 struct intel_shared_dpll
*pll
;
4239 enum intel_dpll_id i
;
4241 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4242 pll
= &dev_priv
->shared_dplls
[i
];
4244 WARN_ON(pll
->new_config
== &pll
->config
);
4246 pll
->config
= *pll
->new_config
;
4247 kfree(pll
->new_config
);
4248 pll
->new_config
= NULL
;
4252 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4254 struct intel_shared_dpll
*pll
;
4255 enum intel_dpll_id i
;
4257 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4258 pll
= &dev_priv
->shared_dplls
[i
];
4260 WARN_ON(pll
->new_config
== &pll
->config
);
4262 kfree(pll
->new_config
);
4263 pll
->new_config
= NULL
;
4267 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4270 int dslreg
= PIPEDSL(pipe
);
4273 temp
= I915_READ(dslreg
);
4275 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4276 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4277 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4281 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4283 struct drm_device
*dev
= crtc
->base
.dev
;
4284 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4285 int pipe
= crtc
->pipe
;
4287 if (crtc
->config
->pch_pfit
.enabled
) {
4288 I915_WRITE(PS_CTL(pipe
), PS_ENABLE
);
4289 I915_WRITE(PS_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4290 I915_WRITE(PS_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4294 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4296 struct drm_device
*dev
= crtc
->base
.dev
;
4297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4298 int pipe
= crtc
->pipe
;
4300 if (crtc
->config
->pch_pfit
.enabled
) {
4301 /* Force use of hard-coded filter coefficients
4302 * as some pre-programmed values are broken,
4305 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4306 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4307 PF_PIPE_SEL_IVB(pipe
));
4309 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4310 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4311 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4315 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4317 struct drm_device
*dev
= crtc
->dev
;
4318 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4319 struct drm_plane
*plane
;
4320 struct intel_plane
*intel_plane
;
4322 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4323 intel_plane
= to_intel_plane(plane
);
4324 if (intel_plane
->pipe
== pipe
)
4325 intel_plane_restore(&intel_plane
->base
);
4330 * Disable a plane internally without actually modifying the plane's state.
4331 * This will allow us to easily restore the plane later by just reprogramming
4334 static void disable_plane_internal(struct drm_plane
*plane
)
4336 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
4337 struct drm_plane_state
*state
=
4338 plane
->funcs
->atomic_duplicate_state(plane
);
4339 struct intel_plane_state
*intel_state
= to_intel_plane_state(state
);
4341 intel_state
->visible
= false;
4342 intel_plane
->commit_plane(plane
, intel_state
);
4344 intel_plane_destroy_state(plane
, state
);
4347 static void intel_disable_sprite_planes(struct drm_crtc
*crtc
)
4349 struct drm_device
*dev
= crtc
->dev
;
4350 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4351 struct drm_plane
*plane
;
4352 struct intel_plane
*intel_plane
;
4354 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4355 intel_plane
= to_intel_plane(plane
);
4356 if (plane
->fb
&& intel_plane
->pipe
== pipe
)
4357 disable_plane_internal(plane
);
4361 void hsw_enable_ips(struct intel_crtc
*crtc
)
4363 struct drm_device
*dev
= crtc
->base
.dev
;
4364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4366 if (!crtc
->config
->ips_enabled
)
4369 /* We can only enable IPS after we enable a plane and wait for a vblank */
4370 intel_wait_for_vblank(dev
, crtc
->pipe
);
4372 assert_plane_enabled(dev_priv
, crtc
->plane
);
4373 if (IS_BROADWELL(dev
)) {
4374 mutex_lock(&dev_priv
->rps
.hw_lock
);
4375 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4376 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4377 /* Quoting Art Runyan: "its not safe to expect any particular
4378 * value in IPS_CTL bit 31 after enabling IPS through the
4379 * mailbox." Moreover, the mailbox may return a bogus state,
4380 * so we need to just enable it and continue on.
4383 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4384 /* The bit only becomes 1 in the next vblank, so this wait here
4385 * is essentially intel_wait_for_vblank. If we don't have this
4386 * and don't wait for vblanks until the end of crtc_enable, then
4387 * the HW state readout code will complain that the expected
4388 * IPS_CTL value is not the one we read. */
4389 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4390 DRM_ERROR("Timed out waiting for IPS enable\n");
4394 void hsw_disable_ips(struct intel_crtc
*crtc
)
4396 struct drm_device
*dev
= crtc
->base
.dev
;
4397 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4399 if (!crtc
->config
->ips_enabled
)
4402 assert_plane_enabled(dev_priv
, crtc
->plane
);
4403 if (IS_BROADWELL(dev
)) {
4404 mutex_lock(&dev_priv
->rps
.hw_lock
);
4405 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4406 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4407 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4408 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4409 DRM_ERROR("Timed out waiting for IPS disable\n");
4411 I915_WRITE(IPS_CTL
, 0);
4412 POSTING_READ(IPS_CTL
);
4415 /* We need to wait for a vblank before we can disable the plane. */
4416 intel_wait_for_vblank(dev
, crtc
->pipe
);
4419 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4420 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4422 struct drm_device
*dev
= crtc
->dev
;
4423 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4424 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4425 enum pipe pipe
= intel_crtc
->pipe
;
4426 int palreg
= PALETTE(pipe
);
4428 bool reenable_ips
= false;
4430 /* The clocks have to be on to load the palette. */
4431 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4434 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4435 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4436 assert_dsi_pll_enabled(dev_priv
);
4438 assert_pll_enabled(dev_priv
, pipe
);
4441 /* use legacy palette for Ironlake */
4442 if (!HAS_GMCH_DISPLAY(dev
))
4443 palreg
= LGC_PALETTE(pipe
);
4445 /* Workaround : Do not read or write the pipe palette/gamma data while
4446 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4448 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4449 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4450 GAMMA_MODE_MODE_SPLIT
)) {
4451 hsw_disable_ips(intel_crtc
);
4452 reenable_ips
= true;
4455 for (i
= 0; i
< 256; i
++) {
4456 I915_WRITE(palreg
+ 4 * i
,
4457 (intel_crtc
->lut_r
[i
] << 16) |
4458 (intel_crtc
->lut_g
[i
] << 8) |
4459 intel_crtc
->lut_b
[i
]);
4463 hsw_enable_ips(intel_crtc
);
4466 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4468 if (!enable
&& intel_crtc
->overlay
) {
4469 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4470 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4472 mutex_lock(&dev
->struct_mutex
);
4473 dev_priv
->mm
.interruptible
= false;
4474 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4475 dev_priv
->mm
.interruptible
= true;
4476 mutex_unlock(&dev
->struct_mutex
);
4479 /* Let userspace switch the overlay on again. In most cases userspace
4480 * has to recompute where to put it anyway.
4484 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4486 struct drm_device
*dev
= crtc
->dev
;
4487 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4488 int pipe
= intel_crtc
->pipe
;
4490 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4491 intel_enable_sprite_planes(crtc
);
4492 intel_crtc_update_cursor(crtc
, true);
4493 intel_crtc_dpms_overlay(intel_crtc
, true);
4495 hsw_enable_ips(intel_crtc
);
4497 mutex_lock(&dev
->struct_mutex
);
4498 intel_fbc_update(dev
);
4499 mutex_unlock(&dev
->struct_mutex
);
4502 * FIXME: Once we grow proper nuclear flip support out of this we need
4503 * to compute the mask of flip planes precisely. For the time being
4504 * consider this a flip from a NULL plane.
4506 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4509 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4511 struct drm_device
*dev
= crtc
->dev
;
4512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4514 int pipe
= intel_crtc
->pipe
;
4516 intel_crtc_wait_for_pending_flips(crtc
);
4518 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4519 intel_fbc_disable(dev
);
4521 hsw_disable_ips(intel_crtc
);
4523 intel_crtc_dpms_overlay(intel_crtc
, false);
4524 intel_crtc_update_cursor(crtc
, false);
4525 intel_disable_sprite_planes(crtc
);
4526 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4529 * FIXME: Once we grow proper nuclear flip support out of this we need
4530 * to compute the mask of flip planes precisely. For the time being
4531 * consider this a flip to a NULL plane.
4533 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4536 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4538 struct drm_device
*dev
= crtc
->dev
;
4539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4540 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4541 struct intel_encoder
*encoder
;
4542 int pipe
= intel_crtc
->pipe
;
4544 WARN_ON(!crtc
->state
->enable
);
4546 if (intel_crtc
->active
)
4549 if (intel_crtc
->config
->has_pch_encoder
)
4550 intel_prepare_shared_dpll(intel_crtc
);
4552 if (intel_crtc
->config
->has_dp_encoder
)
4553 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4555 intel_set_pipe_timings(intel_crtc
);
4557 if (intel_crtc
->config
->has_pch_encoder
) {
4558 intel_cpu_transcoder_set_m_n(intel_crtc
,
4559 &intel_crtc
->config
->fdi_m_n
, NULL
);
4562 ironlake_set_pipeconf(crtc
);
4564 intel_crtc
->active
= true;
4566 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4567 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4569 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4570 if (encoder
->pre_enable
)
4571 encoder
->pre_enable(encoder
);
4573 if (intel_crtc
->config
->has_pch_encoder
) {
4574 /* Note: FDI PLL enabling _must_ be done before we enable the
4575 * cpu pipes, hence this is separate from all the other fdi/pch
4577 ironlake_fdi_pll_enable(intel_crtc
);
4579 assert_fdi_tx_disabled(dev_priv
, pipe
);
4580 assert_fdi_rx_disabled(dev_priv
, pipe
);
4583 ironlake_pfit_enable(intel_crtc
);
4586 * On ILK+ LUT must be loaded before the pipe is running but with
4589 intel_crtc_load_lut(crtc
);
4591 intel_update_watermarks(crtc
);
4592 intel_enable_pipe(intel_crtc
);
4594 if (intel_crtc
->config
->has_pch_encoder
)
4595 ironlake_pch_enable(crtc
);
4597 assert_vblank_disabled(crtc
);
4598 drm_crtc_vblank_on(crtc
);
4600 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4601 encoder
->enable(encoder
);
4603 if (HAS_PCH_CPT(dev
))
4604 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4606 intel_crtc_enable_planes(crtc
);
4609 /* IPS only exists on ULT machines and is tied to pipe A. */
4610 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4612 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4616 * This implements the workaround described in the "notes" section of the mode
4617 * set sequence documentation. When going from no pipes or single pipe to
4618 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4619 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4621 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4623 struct drm_device
*dev
= crtc
->base
.dev
;
4624 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4626 /* We want to get the other_active_crtc only if there's only 1 other
4628 for_each_intel_crtc(dev
, crtc_it
) {
4629 if (!crtc_it
->active
|| crtc_it
== crtc
)
4632 if (other_active_crtc
)
4635 other_active_crtc
= crtc_it
;
4637 if (!other_active_crtc
)
4640 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4641 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4644 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4646 struct drm_device
*dev
= crtc
->dev
;
4647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4648 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4649 struct intel_encoder
*encoder
;
4650 int pipe
= intel_crtc
->pipe
;
4652 WARN_ON(!crtc
->state
->enable
);
4654 if (intel_crtc
->active
)
4657 if (intel_crtc_to_shared_dpll(intel_crtc
))
4658 intel_enable_shared_dpll(intel_crtc
);
4660 if (intel_crtc
->config
->has_dp_encoder
)
4661 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4663 intel_set_pipe_timings(intel_crtc
);
4665 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4666 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4667 intel_crtc
->config
->pixel_multiplier
- 1);
4670 if (intel_crtc
->config
->has_pch_encoder
) {
4671 intel_cpu_transcoder_set_m_n(intel_crtc
,
4672 &intel_crtc
->config
->fdi_m_n
, NULL
);
4675 haswell_set_pipeconf(crtc
);
4677 intel_set_pipe_csc(crtc
);
4679 intel_crtc
->active
= true;
4681 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4682 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4683 if (encoder
->pre_enable
)
4684 encoder
->pre_enable(encoder
);
4686 if (intel_crtc
->config
->has_pch_encoder
) {
4687 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4689 dev_priv
->display
.fdi_link_train(crtc
);
4692 intel_ddi_enable_pipe_clock(intel_crtc
);
4694 if (IS_SKYLAKE(dev
))
4695 skylake_pfit_enable(intel_crtc
);
4697 ironlake_pfit_enable(intel_crtc
);
4700 * On ILK+ LUT must be loaded before the pipe is running but with
4703 intel_crtc_load_lut(crtc
);
4705 intel_ddi_set_pipe_settings(crtc
);
4706 intel_ddi_enable_transcoder_func(crtc
);
4708 intel_update_watermarks(crtc
);
4709 intel_enable_pipe(intel_crtc
);
4711 if (intel_crtc
->config
->has_pch_encoder
)
4712 lpt_pch_enable(crtc
);
4714 if (intel_crtc
->config
->dp_encoder_is_mst
)
4715 intel_ddi_set_vc_payload_alloc(crtc
, true);
4717 assert_vblank_disabled(crtc
);
4718 drm_crtc_vblank_on(crtc
);
4720 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4721 encoder
->enable(encoder
);
4722 intel_opregion_notify_encoder(encoder
, true);
4725 /* If we change the relative order between pipe/planes enabling, we need
4726 * to change the workaround. */
4727 haswell_mode_set_planes_workaround(intel_crtc
);
4728 intel_crtc_enable_planes(crtc
);
4731 static void skylake_pfit_disable(struct intel_crtc
*crtc
)
4733 struct drm_device
*dev
= crtc
->base
.dev
;
4734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4735 int pipe
= crtc
->pipe
;
4737 /* To avoid upsetting the power well on haswell only disable the pfit if
4738 * it's in use. The hw state code will make sure we get this right. */
4739 if (crtc
->config
->pch_pfit
.enabled
) {
4740 I915_WRITE(PS_CTL(pipe
), 0);
4741 I915_WRITE(PS_WIN_POS(pipe
), 0);
4742 I915_WRITE(PS_WIN_SZ(pipe
), 0);
4746 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4748 struct drm_device
*dev
= crtc
->base
.dev
;
4749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4750 int pipe
= crtc
->pipe
;
4752 /* To avoid upsetting the power well on haswell only disable the pfit if
4753 * it's in use. The hw state code will make sure we get this right. */
4754 if (crtc
->config
->pch_pfit
.enabled
) {
4755 I915_WRITE(PF_CTL(pipe
), 0);
4756 I915_WRITE(PF_WIN_POS(pipe
), 0);
4757 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4761 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4763 struct drm_device
*dev
= crtc
->dev
;
4764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4765 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4766 struct intel_encoder
*encoder
;
4767 int pipe
= intel_crtc
->pipe
;
4770 if (!intel_crtc
->active
)
4773 intel_crtc_disable_planes(crtc
);
4775 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4776 encoder
->disable(encoder
);
4778 drm_crtc_vblank_off(crtc
);
4779 assert_vblank_disabled(crtc
);
4781 if (intel_crtc
->config
->has_pch_encoder
)
4782 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4784 intel_disable_pipe(intel_crtc
);
4786 ironlake_pfit_disable(intel_crtc
);
4788 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4789 if (encoder
->post_disable
)
4790 encoder
->post_disable(encoder
);
4792 if (intel_crtc
->config
->has_pch_encoder
) {
4793 ironlake_fdi_disable(crtc
);
4795 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4797 if (HAS_PCH_CPT(dev
)) {
4798 /* disable TRANS_DP_CTL */
4799 reg
= TRANS_DP_CTL(pipe
);
4800 temp
= I915_READ(reg
);
4801 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4802 TRANS_DP_PORT_SEL_MASK
);
4803 temp
|= TRANS_DP_PORT_SEL_NONE
;
4804 I915_WRITE(reg
, temp
);
4806 /* disable DPLL_SEL */
4807 temp
= I915_READ(PCH_DPLL_SEL
);
4808 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4809 I915_WRITE(PCH_DPLL_SEL
, temp
);
4812 /* disable PCH DPLL */
4813 intel_disable_shared_dpll(intel_crtc
);
4815 ironlake_fdi_pll_disable(intel_crtc
);
4818 intel_crtc
->active
= false;
4819 intel_update_watermarks(crtc
);
4821 mutex_lock(&dev
->struct_mutex
);
4822 intel_fbc_update(dev
);
4823 mutex_unlock(&dev
->struct_mutex
);
4826 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4828 struct drm_device
*dev
= crtc
->dev
;
4829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4830 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4831 struct intel_encoder
*encoder
;
4832 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4834 if (!intel_crtc
->active
)
4837 intel_crtc_disable_planes(crtc
);
4839 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4840 intel_opregion_notify_encoder(encoder
, false);
4841 encoder
->disable(encoder
);
4844 drm_crtc_vblank_off(crtc
);
4845 assert_vblank_disabled(crtc
);
4847 if (intel_crtc
->config
->has_pch_encoder
)
4848 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4850 intel_disable_pipe(intel_crtc
);
4852 if (intel_crtc
->config
->dp_encoder_is_mst
)
4853 intel_ddi_set_vc_payload_alloc(crtc
, false);
4855 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4857 if (IS_SKYLAKE(dev
))
4858 skylake_pfit_disable(intel_crtc
);
4860 ironlake_pfit_disable(intel_crtc
);
4862 intel_ddi_disable_pipe_clock(intel_crtc
);
4864 if (intel_crtc
->config
->has_pch_encoder
) {
4865 lpt_disable_pch_transcoder(dev_priv
);
4866 intel_ddi_fdi_disable(crtc
);
4869 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4870 if (encoder
->post_disable
)
4871 encoder
->post_disable(encoder
);
4873 intel_crtc
->active
= false;
4874 intel_update_watermarks(crtc
);
4876 mutex_lock(&dev
->struct_mutex
);
4877 intel_fbc_update(dev
);
4878 mutex_unlock(&dev
->struct_mutex
);
4880 if (intel_crtc_to_shared_dpll(intel_crtc
))
4881 intel_disable_shared_dpll(intel_crtc
);
4884 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4886 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4887 intel_put_shared_dpll(intel_crtc
);
4891 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4893 struct drm_device
*dev
= crtc
->base
.dev
;
4894 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4895 struct intel_crtc_state
*pipe_config
= crtc
->config
;
4897 if (!pipe_config
->gmch_pfit
.control
)
4901 * The panel fitter should only be adjusted whilst the pipe is disabled,
4902 * according to register description and PRM.
4904 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4905 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4907 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4908 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4910 /* Border color in case we don't scale up to the full screen. Black by
4911 * default, change to something else for debugging. */
4912 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4915 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4919 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4921 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4923 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4925 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4928 return POWER_DOMAIN_PORT_OTHER
;
4932 #define for_each_power_domain(domain, mask) \
4933 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4934 if ((1 << (domain)) & (mask))
4936 enum intel_display_power_domain
4937 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4939 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4940 struct intel_digital_port
*intel_dig_port
;
4942 switch (intel_encoder
->type
) {
4943 case INTEL_OUTPUT_UNKNOWN
:
4944 /* Only DDI platforms should ever use this output type */
4945 WARN_ON_ONCE(!HAS_DDI(dev
));
4946 case INTEL_OUTPUT_DISPLAYPORT
:
4947 case INTEL_OUTPUT_HDMI
:
4948 case INTEL_OUTPUT_EDP
:
4949 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4950 return port_to_power_domain(intel_dig_port
->port
);
4951 case INTEL_OUTPUT_DP_MST
:
4952 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4953 return port_to_power_domain(intel_dig_port
->port
);
4954 case INTEL_OUTPUT_ANALOG
:
4955 return POWER_DOMAIN_PORT_CRT
;
4956 case INTEL_OUTPUT_DSI
:
4957 return POWER_DOMAIN_PORT_DSI
;
4959 return POWER_DOMAIN_PORT_OTHER
;
4963 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4965 struct drm_device
*dev
= crtc
->dev
;
4966 struct intel_encoder
*intel_encoder
;
4967 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4968 enum pipe pipe
= intel_crtc
->pipe
;
4970 enum transcoder transcoder
;
4972 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4974 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4975 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4976 if (intel_crtc
->config
->pch_pfit
.enabled
||
4977 intel_crtc
->config
->pch_pfit
.force_thru
)
4978 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4980 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4981 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4986 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
4988 struct drm_device
*dev
= state
->dev
;
4989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4990 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4991 struct intel_crtc
*crtc
;
4994 * First get all needed power domains, then put all unneeded, to avoid
4995 * any unnecessary toggling of the power wells.
4997 for_each_intel_crtc(dev
, crtc
) {
4998 enum intel_display_power_domain domain
;
5000 if (!crtc
->base
.state
->enable
)
5003 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
5005 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
5006 intel_display_power_get(dev_priv
, domain
);
5009 if (dev_priv
->display
.modeset_global_resources
)
5010 dev_priv
->display
.modeset_global_resources(state
);
5012 for_each_intel_crtc(dev
, crtc
) {
5013 enum intel_display_power_domain domain
;
5015 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
5016 intel_display_power_put(dev_priv
, domain
);
5018 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
5021 intel_display_set_init_power(dev_priv
, false);
5024 /* returns HPLL frequency in kHz */
5025 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5027 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5029 /* Obtain SKU information */
5030 mutex_lock(&dev_priv
->dpio_lock
);
5031 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5032 CCK_FUSE_HPLL_FREQ_MASK
;
5033 mutex_unlock(&dev_priv
->dpio_lock
);
5035 return vco_freq
[hpll_freq
] * 1000;
5038 static void vlv_update_cdclk(struct drm_device
*dev
)
5040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5042 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5043 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5044 dev_priv
->vlv_cdclk_freq
);
5047 * Program the gmbus_freq based on the cdclk frequency.
5048 * BSpec erroneously claims we should aim for 4MHz, but
5049 * in fact 1MHz is the correct frequency.
5051 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->vlv_cdclk_freq
, 1000));
5054 /* Adjust CDclk dividers to allow high res or save power if possible */
5055 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5060 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
5062 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5064 else if (cdclk
== 266667)
5069 mutex_lock(&dev_priv
->rps
.hw_lock
);
5070 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5071 val
&= ~DSPFREQGUAR_MASK
;
5072 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5073 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5074 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5075 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5077 DRM_ERROR("timed out waiting for CDclk change\n");
5079 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5081 if (cdclk
== 400000) {
5084 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5086 mutex_lock(&dev_priv
->dpio_lock
);
5087 /* adjust cdclk divider */
5088 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5089 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5091 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5093 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5094 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5096 DRM_ERROR("timed out waiting for CDclk change\n");
5097 mutex_unlock(&dev_priv
->dpio_lock
);
5100 mutex_lock(&dev_priv
->dpio_lock
);
5101 /* adjust self-refresh exit latency value */
5102 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5106 * For high bandwidth configs, we set a higher latency in the bunit
5107 * so that the core display fetch happens in time to avoid underruns.
5109 if (cdclk
== 400000)
5110 val
|= 4500 / 250; /* 4.5 usec */
5112 val
|= 3000 / 250; /* 3.0 usec */
5113 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5114 mutex_unlock(&dev_priv
->dpio_lock
);
5116 vlv_update_cdclk(dev
);
5119 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5124 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
5133 MISSING_CASE(cdclk
);
5138 * Specs are full of misinformation, but testing on actual
5139 * hardware has shown that we just need to write the desired
5140 * CCK divider into the Punit register.
5142 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5144 mutex_lock(&dev_priv
->rps
.hw_lock
);
5145 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5146 val
&= ~DSPFREQGUAR_MASK_CHV
;
5147 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5148 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5149 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5150 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5152 DRM_ERROR("timed out waiting for CDclk change\n");
5154 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5156 vlv_update_cdclk(dev
);
5159 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5162 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5163 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5166 * Really only a few cases to deal with, as only 4 CDclks are supported:
5169 * 320/333MHz (depends on HPLL freq)
5171 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5172 * of the lower bin and adjust if needed.
5174 * We seem to get an unstable or solid color picture at 200MHz.
5175 * Not sure what's wrong. For now use 200MHz only when all pipes
5178 if (!IS_CHERRYVIEW(dev_priv
) &&
5179 max_pixclk
> freq_320
*limit
/100)
5181 else if (max_pixclk
> 266667*limit
/100)
5183 else if (max_pixclk
> 0)
5189 /* compute the max pixel clock for new configuration */
5190 static int intel_mode_max_pixclk(struct drm_atomic_state
*state
)
5192 struct drm_device
*dev
= state
->dev
;
5193 struct intel_crtc
*intel_crtc
;
5194 struct intel_crtc_state
*crtc_state
;
5197 for_each_intel_crtc(dev
, intel_crtc
) {
5198 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
5199 if (IS_ERR(crtc_state
))
5200 return PTR_ERR(crtc_state
);
5202 if (!crtc_state
->base
.enable
)
5205 max_pixclk
= max(max_pixclk
,
5206 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5212 static int valleyview_modeset_global_pipes(struct drm_atomic_state
*state
,
5213 unsigned *prepare_pipes
)
5215 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
5216 struct intel_crtc
*intel_crtc
;
5217 int max_pixclk
= intel_mode_max_pixclk(state
);
5222 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
5223 dev_priv
->vlv_cdclk_freq
)
5226 /* disable/enable all currently active pipes while we change cdclk */
5227 for_each_intel_crtc(state
->dev
, intel_crtc
)
5228 if (intel_crtc
->base
.state
->enable
)
5229 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
5234 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5236 unsigned int credits
, default_credits
;
5238 if (IS_CHERRYVIEW(dev_priv
))
5239 default_credits
= PFI_CREDIT(12);
5241 default_credits
= PFI_CREDIT(8);
5243 if (DIV_ROUND_CLOSEST(dev_priv
->vlv_cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5244 /* CHV suggested value is 31 or 63 */
5245 if (IS_CHERRYVIEW(dev_priv
))
5246 credits
= PFI_CREDIT_31
;
5248 credits
= PFI_CREDIT(15);
5250 credits
= default_credits
;
5254 * WA - write default credits before re-programming
5255 * FIXME: should we also set the resend bit here?
5257 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5260 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5261 credits
| PFI_CREDIT_RESEND
);
5264 * FIXME is this guaranteed to clear
5265 * immediately or should we poll for it?
5267 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
5270 static void valleyview_modeset_global_resources(struct drm_atomic_state
*state
)
5272 struct drm_device
*dev
= state
->dev
;
5273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5274 int max_pixclk
= intel_mode_max_pixclk(state
);
5277 /* The only reason this can fail is if we fail to add the crtc_state
5278 * to the atomic state. But that can't happen since the call to
5279 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5280 * can't have failed otherwise the mode set would be aborted) added all
5281 * the states already. */
5282 if (WARN_ON(max_pixclk
< 0))
5285 req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5287 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
5289 * FIXME: We can end up here with all power domains off, yet
5290 * with a CDCLK frequency other than the minimum. To account
5291 * for this take the PIPE-A power domain, which covers the HW
5292 * blocks needed for the following programming. This can be
5293 * removed once it's guaranteed that we get here either with
5294 * the minimum CDCLK set, or the required power domains
5297 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5299 if (IS_CHERRYVIEW(dev
))
5300 cherryview_set_cdclk(dev
, req_cdclk
);
5302 valleyview_set_cdclk(dev
, req_cdclk
);
5304 vlv_program_pfi_credits(dev_priv
);
5306 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5310 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5312 struct drm_device
*dev
= crtc
->dev
;
5313 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5314 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5315 struct intel_encoder
*encoder
;
5316 int pipe
= intel_crtc
->pipe
;
5319 WARN_ON(!crtc
->state
->enable
);
5321 if (intel_crtc
->active
)
5324 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5327 if (IS_CHERRYVIEW(dev
))
5328 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5330 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5333 if (intel_crtc
->config
->has_dp_encoder
)
5334 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5336 intel_set_pipe_timings(intel_crtc
);
5338 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5341 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5342 I915_WRITE(CHV_CANVAS(pipe
), 0);
5345 i9xx_set_pipeconf(intel_crtc
);
5347 intel_crtc
->active
= true;
5349 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5351 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5352 if (encoder
->pre_pll_enable
)
5353 encoder
->pre_pll_enable(encoder
);
5356 if (IS_CHERRYVIEW(dev
))
5357 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5359 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5362 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5363 if (encoder
->pre_enable
)
5364 encoder
->pre_enable(encoder
);
5366 i9xx_pfit_enable(intel_crtc
);
5368 intel_crtc_load_lut(crtc
);
5370 intel_update_watermarks(crtc
);
5371 intel_enable_pipe(intel_crtc
);
5373 assert_vblank_disabled(crtc
);
5374 drm_crtc_vblank_on(crtc
);
5376 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5377 encoder
->enable(encoder
);
5379 intel_crtc_enable_planes(crtc
);
5381 /* Underruns don't raise interrupts, so check manually. */
5382 i9xx_check_fifo_underruns(dev_priv
);
5385 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5387 struct drm_device
*dev
= crtc
->base
.dev
;
5388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5390 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5391 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5394 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5396 struct drm_device
*dev
= crtc
->dev
;
5397 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5398 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5399 struct intel_encoder
*encoder
;
5400 int pipe
= intel_crtc
->pipe
;
5402 WARN_ON(!crtc
->state
->enable
);
5404 if (intel_crtc
->active
)
5407 i9xx_set_pll_dividers(intel_crtc
);
5409 if (intel_crtc
->config
->has_dp_encoder
)
5410 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5412 intel_set_pipe_timings(intel_crtc
);
5414 i9xx_set_pipeconf(intel_crtc
);
5416 intel_crtc
->active
= true;
5419 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5421 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5422 if (encoder
->pre_enable
)
5423 encoder
->pre_enable(encoder
);
5425 i9xx_enable_pll(intel_crtc
);
5427 i9xx_pfit_enable(intel_crtc
);
5429 intel_crtc_load_lut(crtc
);
5431 intel_update_watermarks(crtc
);
5432 intel_enable_pipe(intel_crtc
);
5434 assert_vblank_disabled(crtc
);
5435 drm_crtc_vblank_on(crtc
);
5437 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5438 encoder
->enable(encoder
);
5440 intel_crtc_enable_planes(crtc
);
5443 * Gen2 reports pipe underruns whenever all planes are disabled.
5444 * So don't enable underrun reporting before at least some planes
5446 * FIXME: Need to fix the logic to work when we turn off all planes
5447 * but leave the pipe running.
5450 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5452 /* Underruns don't raise interrupts, so check manually. */
5453 i9xx_check_fifo_underruns(dev_priv
);
5456 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5458 struct drm_device
*dev
= crtc
->base
.dev
;
5459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5461 if (!crtc
->config
->gmch_pfit
.control
)
5464 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5466 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5467 I915_READ(PFIT_CONTROL
));
5468 I915_WRITE(PFIT_CONTROL
, 0);
5471 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5473 struct drm_device
*dev
= crtc
->dev
;
5474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5475 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5476 struct intel_encoder
*encoder
;
5477 int pipe
= intel_crtc
->pipe
;
5479 if (!intel_crtc
->active
)
5483 * Gen2 reports pipe underruns whenever all planes are disabled.
5484 * So diasble underrun reporting before all the planes get disabled.
5485 * FIXME: Need to fix the logic to work when we turn off all planes
5486 * but leave the pipe running.
5489 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5492 * Vblank time updates from the shadow to live plane control register
5493 * are blocked if the memory self-refresh mode is active at that
5494 * moment. So to make sure the plane gets truly disabled, disable
5495 * first the self-refresh mode. The self-refresh enable bit in turn
5496 * will be checked/applied by the HW only at the next frame start
5497 * event which is after the vblank start event, so we need to have a
5498 * wait-for-vblank between disabling the plane and the pipe.
5500 intel_set_memory_cxsr(dev_priv
, false);
5501 intel_crtc_disable_planes(crtc
);
5504 * On gen2 planes are double buffered but the pipe isn't, so we must
5505 * wait for planes to fully turn off before disabling the pipe.
5506 * We also need to wait on all gmch platforms because of the
5507 * self-refresh mode constraint explained above.
5509 intel_wait_for_vblank(dev
, pipe
);
5511 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5512 encoder
->disable(encoder
);
5514 drm_crtc_vblank_off(crtc
);
5515 assert_vblank_disabled(crtc
);
5517 intel_disable_pipe(intel_crtc
);
5519 i9xx_pfit_disable(intel_crtc
);
5521 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5522 if (encoder
->post_disable
)
5523 encoder
->post_disable(encoder
);
5525 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5526 if (IS_CHERRYVIEW(dev
))
5527 chv_disable_pll(dev_priv
, pipe
);
5528 else if (IS_VALLEYVIEW(dev
))
5529 vlv_disable_pll(dev_priv
, pipe
);
5531 i9xx_disable_pll(intel_crtc
);
5535 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5537 intel_crtc
->active
= false;
5538 intel_update_watermarks(crtc
);
5540 mutex_lock(&dev
->struct_mutex
);
5541 intel_fbc_update(dev
);
5542 mutex_unlock(&dev
->struct_mutex
);
5545 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5549 /* Master function to enable/disable CRTC and corresponding power wells */
5550 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5552 struct drm_device
*dev
= crtc
->dev
;
5553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5554 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5555 enum intel_display_power_domain domain
;
5556 unsigned long domains
;
5559 if (!intel_crtc
->active
) {
5560 domains
= get_crtc_power_domains(crtc
);
5561 for_each_power_domain(domain
, domains
)
5562 intel_display_power_get(dev_priv
, domain
);
5563 intel_crtc
->enabled_power_domains
= domains
;
5565 dev_priv
->display
.crtc_enable(crtc
);
5568 if (intel_crtc
->active
) {
5569 dev_priv
->display
.crtc_disable(crtc
);
5571 domains
= intel_crtc
->enabled_power_domains
;
5572 for_each_power_domain(domain
, domains
)
5573 intel_display_power_put(dev_priv
, domain
);
5574 intel_crtc
->enabled_power_domains
= 0;
5580 * Sets the power management mode of the pipe and plane.
5582 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5584 struct drm_device
*dev
= crtc
->dev
;
5585 struct intel_encoder
*intel_encoder
;
5586 bool enable
= false;
5588 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5589 enable
|= intel_encoder
->connectors_active
;
5591 intel_crtc_control(crtc
, enable
);
5594 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5596 struct drm_device
*dev
= crtc
->dev
;
5597 struct drm_connector
*connector
;
5598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5600 /* crtc should still be enabled when we disable it. */
5601 WARN_ON(!crtc
->state
->enable
);
5603 dev_priv
->display
.crtc_disable(crtc
);
5604 dev_priv
->display
.off(crtc
);
5606 drm_plane_helper_disable(crtc
->primary
);
5608 /* Update computed state. */
5609 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5610 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5613 if (connector
->encoder
->crtc
!= crtc
)
5616 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5617 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5621 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5623 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5625 drm_encoder_cleanup(encoder
);
5626 kfree(intel_encoder
);
5629 /* Simple dpms helper for encoders with just one connector, no cloning and only
5630 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5631 * state of the entire output pipe. */
5632 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5634 if (mode
== DRM_MODE_DPMS_ON
) {
5635 encoder
->connectors_active
= true;
5637 intel_crtc_update_dpms(encoder
->base
.crtc
);
5639 encoder
->connectors_active
= false;
5641 intel_crtc_update_dpms(encoder
->base
.crtc
);
5645 /* Cross check the actual hw state with our own modeset state tracking (and it's
5646 * internal consistency). */
5647 static void intel_connector_check_state(struct intel_connector
*connector
)
5649 if (connector
->get_hw_state(connector
)) {
5650 struct intel_encoder
*encoder
= connector
->encoder
;
5651 struct drm_crtc
*crtc
;
5652 bool encoder_enabled
;
5655 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5656 connector
->base
.base
.id
,
5657 connector
->base
.name
);
5659 /* there is no real hw state for MST connectors */
5660 if (connector
->mst_port
)
5663 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5664 "wrong connector dpms state\n");
5665 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
5666 "active connector not linked to encoder\n");
5669 I915_STATE_WARN(!encoder
->connectors_active
,
5670 "encoder->connectors_active not set\n");
5672 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5673 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
5674 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
5677 crtc
= encoder
->base
.crtc
;
5679 I915_STATE_WARN(!crtc
->state
->enable
,
5680 "crtc not enabled\n");
5681 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5682 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5683 "encoder active on the wrong pipe\n");
5688 int intel_connector_init(struct intel_connector
*connector
)
5690 struct drm_connector_state
*connector_state
;
5692 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
5693 if (!connector_state
)
5696 connector
->base
.state
= connector_state
;
5700 struct intel_connector
*intel_connector_alloc(void)
5702 struct intel_connector
*connector
;
5704 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
5708 if (intel_connector_init(connector
) < 0) {
5716 /* Even simpler default implementation, if there's really no special case to
5718 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5720 /* All the simple cases only support two dpms states. */
5721 if (mode
!= DRM_MODE_DPMS_ON
)
5722 mode
= DRM_MODE_DPMS_OFF
;
5724 if (mode
== connector
->dpms
)
5727 connector
->dpms
= mode
;
5729 /* Only need to change hw state when actually enabled */
5730 if (connector
->encoder
)
5731 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5733 intel_modeset_check_state(connector
->dev
);
5736 /* Simple connector->get_hw_state implementation for encoders that support only
5737 * one connector and no cloning and hence the encoder state determines the state
5738 * of the connector. */
5739 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5742 struct intel_encoder
*encoder
= connector
->encoder
;
5744 return encoder
->get_hw_state(encoder
, &pipe
);
5747 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
5749 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
5750 return crtc_state
->fdi_lanes
;
5755 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5756 struct intel_crtc_state
*pipe_config
)
5758 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
5759 struct intel_crtc
*other_crtc
;
5760 struct intel_crtc_state
*other_crtc_state
;
5762 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5763 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5764 if (pipe_config
->fdi_lanes
> 4) {
5765 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5766 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5770 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5771 if (pipe_config
->fdi_lanes
> 2) {
5772 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5773 pipe_config
->fdi_lanes
);
5780 if (INTEL_INFO(dev
)->num_pipes
== 2)
5783 /* Ivybridge 3 pipe is really complicated */
5788 if (pipe_config
->fdi_lanes
<= 2)
5791 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
5793 intel_atomic_get_crtc_state(state
, other_crtc
);
5794 if (IS_ERR(other_crtc_state
))
5795 return PTR_ERR(other_crtc_state
);
5797 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
5798 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5799 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5804 if (pipe_config
->fdi_lanes
> 2) {
5805 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5806 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5810 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
5812 intel_atomic_get_crtc_state(state
, other_crtc
);
5813 if (IS_ERR(other_crtc_state
))
5814 return PTR_ERR(other_crtc_state
);
5816 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
5817 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5827 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5828 struct intel_crtc_state
*pipe_config
)
5830 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5831 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5832 int lane
, link_bw
, fdi_dotclock
, ret
;
5833 bool needs_recompute
= false;
5836 /* FDI is a binary signal running at ~2.7GHz, encoding
5837 * each output octet as 10 bits. The actual frequency
5838 * is stored as a divider into a 100MHz clock, and the
5839 * mode pixel clock is stored in units of 1KHz.
5840 * Hence the bw of each lane in terms of the mode signal
5843 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5845 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5847 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5848 pipe_config
->pipe_bpp
);
5850 pipe_config
->fdi_lanes
= lane
;
5852 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5853 link_bw
, &pipe_config
->fdi_m_n
);
5855 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5856 intel_crtc
->pipe
, pipe_config
);
5857 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
5858 pipe_config
->pipe_bpp
-= 2*3;
5859 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5860 pipe_config
->pipe_bpp
);
5861 needs_recompute
= true;
5862 pipe_config
->bw_constrained
= true;
5867 if (needs_recompute
)
5873 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5874 struct intel_crtc_state
*pipe_config
)
5876 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5877 hsw_crtc_supports_ips(crtc
) &&
5878 pipe_config
->pipe_bpp
<= 24;
5881 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5882 struct intel_crtc_state
*pipe_config
)
5884 struct drm_device
*dev
= crtc
->base
.dev
;
5885 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5886 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5888 /* FIXME should check pixel clock limits on all platforms */
5889 if (INTEL_INFO(dev
)->gen
< 4) {
5891 dev_priv
->display
.get_display_clock_speed(dev
);
5894 * Enable pixel doubling when the dot clock
5895 * is > 90% of the (display) core speed.
5897 * GDG double wide on either pipe,
5898 * otherwise pipe A only.
5900 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5901 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5903 pipe_config
->double_wide
= true;
5906 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5911 * Pipe horizontal size must be even in:
5913 * - LVDS dual channel mode
5914 * - Double wide pipe
5916 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
5917 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5918 pipe_config
->pipe_src_w
&= ~1;
5920 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5921 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5923 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5924 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5927 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5928 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5929 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5930 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5932 pipe_config
->pipe_bpp
= 8*3;
5936 hsw_compute_ips_config(crtc
, pipe_config
);
5938 if (pipe_config
->has_pch_encoder
)
5939 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5944 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
5946 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5947 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
5948 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
5951 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
5952 WARN(1, "LCPLL1 not enabled\n");
5953 return 24000; /* 24MHz is the cd freq with NSSC ref */
5956 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
5959 linkrate
= (I915_READ(DPLL_CTRL1
) &
5960 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
5962 if (linkrate
== DPLL_CRTL1_LINK_RATE_2160
||
5963 linkrate
== DPLL_CRTL1_LINK_RATE_1080
) {
5965 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
5966 case CDCLK_FREQ_450_432
:
5968 case CDCLK_FREQ_337_308
:
5970 case CDCLK_FREQ_675_617
:
5973 WARN(1, "Unknown cd freq selection\n");
5977 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
5978 case CDCLK_FREQ_450_432
:
5980 case CDCLK_FREQ_337_308
:
5982 case CDCLK_FREQ_675_617
:
5985 WARN(1, "Unknown cd freq selection\n");
5989 /* error case, do as if DPLL0 isn't enabled */
5993 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
5995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5996 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
5997 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
5999 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6001 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6003 else if (freq
== LCPLL_CLK_FREQ_450
)
6005 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6007 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6013 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6015 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6016 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6017 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6019 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6021 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6023 else if (freq
== LCPLL_CLK_FREQ_450
)
6025 else if (IS_HSW_ULT(dev
))
6031 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6037 if (dev_priv
->hpll_freq
== 0)
6038 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6040 mutex_lock(&dev_priv
->dpio_lock
);
6041 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6042 mutex_unlock(&dev_priv
->dpio_lock
);
6044 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6046 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6047 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6048 "cdclk change in progress\n");
6050 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6053 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6058 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6063 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6068 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6073 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6077 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6079 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6080 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6082 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6084 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6086 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6089 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6090 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6092 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6097 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6101 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6103 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6106 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6107 case GC_DISPLAY_CLOCK_333_MHZ
:
6110 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6116 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6121 static int i855_get_display_clock_speed(struct drm_device
*dev
)
6124 /* Assume that the hardware is in the high speed state. This
6125 * should be the default.
6127 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6128 case GC_CLOCK_133_200
:
6129 case GC_CLOCK_100_200
:
6131 case GC_CLOCK_166_250
:
6133 case GC_CLOCK_100_133
:
6137 /* Shouldn't happen */
6141 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6147 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6149 while (*num
> DATA_LINK_M_N_MASK
||
6150 *den
> DATA_LINK_M_N_MASK
) {
6156 static void compute_m_n(unsigned int m
, unsigned int n
,
6157 uint32_t *ret_m
, uint32_t *ret_n
)
6159 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6160 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6161 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6165 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6166 int pixel_clock
, int link_clock
,
6167 struct intel_link_m_n
*m_n
)
6171 compute_m_n(bits_per_pixel
* pixel_clock
,
6172 link_clock
* nlanes
* 8,
6173 &m_n
->gmch_m
, &m_n
->gmch_n
);
6175 compute_m_n(pixel_clock
, link_clock
,
6176 &m_n
->link_m
, &m_n
->link_n
);
6179 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6181 if (i915
.panel_use_ssc
>= 0)
6182 return i915
.panel_use_ssc
!= 0;
6183 return dev_priv
->vbt
.lvds_use_ssc
6184 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6187 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
6190 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
6191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6194 WARN_ON(!crtc_state
->base
.state
);
6196 if (IS_VALLEYVIEW(dev
)) {
6198 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6199 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6200 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
6201 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
6202 } else if (!IS_GEN2(dev
)) {
6211 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6213 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6216 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6218 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6221 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6222 struct intel_crtc_state
*crtc_state
,
6223 intel_clock_t
*reduced_clock
)
6225 struct drm_device
*dev
= crtc
->base
.dev
;
6228 if (IS_PINEVIEW(dev
)) {
6229 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6231 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6233 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6235 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6238 crtc_state
->dpll_hw_state
.fp0
= fp
;
6240 crtc
->lowfreq_avail
= false;
6241 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6243 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6244 crtc
->lowfreq_avail
= true;
6246 crtc_state
->dpll_hw_state
.fp1
= fp
;
6250 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6256 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6257 * and set it to a reasonable value instead.
6259 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6260 reg_val
&= 0xffffff00;
6261 reg_val
|= 0x00000030;
6262 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6264 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6265 reg_val
&= 0x8cffffff;
6266 reg_val
= 0x8c000000;
6267 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6269 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6270 reg_val
&= 0xffffff00;
6271 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6273 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6274 reg_val
&= 0x00ffffff;
6275 reg_val
|= 0xb0000000;
6276 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6279 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6280 struct intel_link_m_n
*m_n
)
6282 struct drm_device
*dev
= crtc
->base
.dev
;
6283 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6284 int pipe
= crtc
->pipe
;
6286 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6287 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6288 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6289 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6292 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6293 struct intel_link_m_n
*m_n
,
6294 struct intel_link_m_n
*m2_n2
)
6296 struct drm_device
*dev
= crtc
->base
.dev
;
6297 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6298 int pipe
= crtc
->pipe
;
6299 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
6301 if (INTEL_INFO(dev
)->gen
>= 5) {
6302 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6303 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
6304 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
6305 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
6306 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6307 * for gen < 8) and if DRRS is supported (to make sure the
6308 * registers are not unnecessarily accessed).
6310 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
6311 crtc
->config
->has_drrs
) {
6312 I915_WRITE(PIPE_DATA_M2(transcoder
),
6313 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
6314 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
6315 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
6316 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
6319 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6320 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
6321 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
6322 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
6326 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
6328 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
6331 dp_m_n
= &crtc
->config
->dp_m_n
;
6332 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
6333 } else if (m_n
== M2_N2
) {
6336 * M2_N2 registers are not supported. Hence m2_n2 divider value
6337 * needs to be programmed into M1_N1.
6339 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6341 DRM_ERROR("Unsupported divider value\n");
6345 if (crtc
->config
->has_pch_encoder
)
6346 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6348 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6351 static void vlv_update_pll(struct intel_crtc
*crtc
,
6352 struct intel_crtc_state
*pipe_config
)
6357 * Enable DPIO clock input. We should never disable the reference
6358 * clock for pipe B, since VGA hotplug / manual detection depends
6361 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
6362 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
6363 /* We should never disable this, set it here for state tracking */
6364 if (crtc
->pipe
== PIPE_B
)
6365 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6366 dpll
|= DPLL_VCO_ENABLE
;
6367 pipe_config
->dpll_hw_state
.dpll
= dpll
;
6369 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
6370 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6371 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6374 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6375 const struct intel_crtc_state
*pipe_config
)
6377 struct drm_device
*dev
= crtc
->base
.dev
;
6378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6379 int pipe
= crtc
->pipe
;
6381 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6382 u32 coreclk
, reg_val
;
6384 mutex_lock(&dev_priv
->dpio_lock
);
6386 bestn
= pipe_config
->dpll
.n
;
6387 bestm1
= pipe_config
->dpll
.m1
;
6388 bestm2
= pipe_config
->dpll
.m2
;
6389 bestp1
= pipe_config
->dpll
.p1
;
6390 bestp2
= pipe_config
->dpll
.p2
;
6392 /* See eDP HDMI DPIO driver vbios notes doc */
6394 /* PLL B needs special handling */
6396 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6398 /* Set up Tx target for periodic Rcomp update */
6399 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6401 /* Disable target IRef on PLL */
6402 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6403 reg_val
&= 0x00ffffff;
6404 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6406 /* Disable fast lock */
6407 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6409 /* Set idtafcrecal before PLL is enabled */
6410 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6411 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6412 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6413 mdiv
|= (1 << DPIO_K_SHIFT
);
6416 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6417 * but we don't support that).
6418 * Note: don't use the DAC post divider as it seems unstable.
6420 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6421 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6423 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6424 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6426 /* Set HBR and RBR LPF coefficients */
6427 if (pipe_config
->port_clock
== 162000 ||
6428 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
6429 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
6430 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6433 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6436 if (pipe_config
->has_dp_encoder
) {
6437 /* Use SSC source */
6439 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6442 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6444 } else { /* HDMI or VGA */
6445 /* Use bend source */
6447 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6450 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6454 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6455 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6456 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6457 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6458 coreclk
|= 0x01000000;
6459 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6461 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6462 mutex_unlock(&dev_priv
->dpio_lock
);
6465 static void chv_update_pll(struct intel_crtc
*crtc
,
6466 struct intel_crtc_state
*pipe_config
)
6468 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
6469 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
6471 if (crtc
->pipe
!= PIPE_A
)
6472 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6474 pipe_config
->dpll_hw_state
.dpll_md
=
6475 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6478 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6479 const struct intel_crtc_state
*pipe_config
)
6481 struct drm_device
*dev
= crtc
->base
.dev
;
6482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6483 int pipe
= crtc
->pipe
;
6484 int dpll_reg
= DPLL(crtc
->pipe
);
6485 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6486 u32 loopfilter
, tribuf_calcntr
;
6487 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
6491 bestn
= pipe_config
->dpll
.n
;
6492 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
6493 bestm1
= pipe_config
->dpll
.m1
;
6494 bestm2
= pipe_config
->dpll
.m2
>> 22;
6495 bestp1
= pipe_config
->dpll
.p1
;
6496 bestp2
= pipe_config
->dpll
.p2
;
6497 vco
= pipe_config
->dpll
.vco
;
6502 * Enable Refclk and SSC
6504 I915_WRITE(dpll_reg
,
6505 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
6507 mutex_lock(&dev_priv
->dpio_lock
);
6509 /* p1 and p2 divider */
6510 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6511 5 << DPIO_CHV_S1_DIV_SHIFT
|
6512 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6513 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6514 1 << DPIO_CHV_K_DIV_SHIFT
);
6516 /* Feedback post-divider - m2 */
6517 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6519 /* Feedback refclk divider - n and m1 */
6520 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6521 DPIO_CHV_M1_DIV_BY_2
|
6522 1 << DPIO_CHV_N_DIV_SHIFT
);
6524 /* M2 fraction division */
6526 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6528 /* M2 fraction division enable */
6529 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
6530 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
6531 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
6533 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
6534 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
6536 /* Program digital lock detect threshold */
6537 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
6538 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
6539 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
6540 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
6542 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
6543 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
6546 if (vco
== 5400000) {
6547 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
6548 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
6549 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6550 tribuf_calcntr
= 0x9;
6551 } else if (vco
<= 6200000) {
6552 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
6553 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
6554 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6555 tribuf_calcntr
= 0x9;
6556 } else if (vco
<= 6480000) {
6557 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
6558 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
6559 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6560 tribuf_calcntr
= 0x8;
6562 /* Not supported. Apply the same limits as in the max case */
6563 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
6564 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
6565 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6568 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6570 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
6571 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
6572 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
6573 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
6576 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6577 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6580 mutex_unlock(&dev_priv
->dpio_lock
);
6584 * vlv_force_pll_on - forcibly enable just the PLL
6585 * @dev_priv: i915 private structure
6586 * @pipe: pipe PLL to enable
6587 * @dpll: PLL configuration
6589 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6590 * in cases where we need the PLL enabled even when @pipe is not going to
6593 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6594 const struct dpll
*dpll
)
6596 struct intel_crtc
*crtc
=
6597 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6598 struct intel_crtc_state pipe_config
= {
6599 .base
.crtc
= &crtc
->base
,
6600 .pixel_multiplier
= 1,
6604 if (IS_CHERRYVIEW(dev
)) {
6605 chv_update_pll(crtc
, &pipe_config
);
6606 chv_prepare_pll(crtc
, &pipe_config
);
6607 chv_enable_pll(crtc
, &pipe_config
);
6609 vlv_update_pll(crtc
, &pipe_config
);
6610 vlv_prepare_pll(crtc
, &pipe_config
);
6611 vlv_enable_pll(crtc
, &pipe_config
);
6616 * vlv_force_pll_off - forcibly disable just the PLL
6617 * @dev_priv: i915 private structure
6618 * @pipe: pipe PLL to disable
6620 * Disable the PLL for @pipe. To be used in cases where we need
6621 * the PLL enabled even when @pipe is not going to be enabled.
6623 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6625 if (IS_CHERRYVIEW(dev
))
6626 chv_disable_pll(to_i915(dev
), pipe
);
6628 vlv_disable_pll(to_i915(dev
), pipe
);
6631 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6632 struct intel_crtc_state
*crtc_state
,
6633 intel_clock_t
*reduced_clock
,
6636 struct drm_device
*dev
= crtc
->base
.dev
;
6637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6640 struct dpll
*clock
= &crtc_state
->dpll
;
6642 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6644 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
6645 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
6647 dpll
= DPLL_VGA_MODE_DIS
;
6649 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
6650 dpll
|= DPLLB_MODE_LVDS
;
6652 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6654 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6655 dpll
|= (crtc_state
->pixel_multiplier
- 1)
6656 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6660 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6662 if (crtc_state
->has_dp_encoder
)
6663 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6665 /* compute bitmask from p1 value */
6666 if (IS_PINEVIEW(dev
))
6667 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6669 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6670 if (IS_G4X(dev
) && reduced_clock
)
6671 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6673 switch (clock
->p2
) {
6675 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6678 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6681 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6684 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6687 if (INTEL_INFO(dev
)->gen
>= 4)
6688 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6690 if (crtc_state
->sdvo_tv_clock
)
6691 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6692 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6693 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6694 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6696 dpll
|= PLL_REF_INPUT_DREFCLK
;
6698 dpll
|= DPLL_VCO_ENABLE
;
6699 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6701 if (INTEL_INFO(dev
)->gen
>= 4) {
6702 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
6703 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6704 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
6708 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6709 struct intel_crtc_state
*crtc_state
,
6710 intel_clock_t
*reduced_clock
,
6713 struct drm_device
*dev
= crtc
->base
.dev
;
6714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6716 struct dpll
*clock
= &crtc_state
->dpll
;
6718 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6720 dpll
= DPLL_VGA_MODE_DIS
;
6722 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
6723 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6726 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6728 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6730 dpll
|= PLL_P2_DIVIDE_BY_4
;
6733 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
6734 dpll
|= DPLL_DVO_2X_MODE
;
6736 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6737 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6738 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6740 dpll
|= PLL_REF_INPUT_DREFCLK
;
6742 dpll
|= DPLL_VCO_ENABLE
;
6743 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6746 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6748 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6750 enum pipe pipe
= intel_crtc
->pipe
;
6751 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
6752 struct drm_display_mode
*adjusted_mode
=
6753 &intel_crtc
->config
->base
.adjusted_mode
;
6754 uint32_t crtc_vtotal
, crtc_vblank_end
;
6757 /* We need to be careful not to changed the adjusted mode, for otherwise
6758 * the hw state checker will get angry at the mismatch. */
6759 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6760 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6762 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6763 /* the chip adds 2 halflines automatically */
6765 crtc_vblank_end
-= 1;
6767 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6768 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6770 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6771 adjusted_mode
->crtc_htotal
/ 2;
6773 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6776 if (INTEL_INFO(dev
)->gen
> 3)
6777 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6779 I915_WRITE(HTOTAL(cpu_transcoder
),
6780 (adjusted_mode
->crtc_hdisplay
- 1) |
6781 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6782 I915_WRITE(HBLANK(cpu_transcoder
),
6783 (adjusted_mode
->crtc_hblank_start
- 1) |
6784 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6785 I915_WRITE(HSYNC(cpu_transcoder
),
6786 (adjusted_mode
->crtc_hsync_start
- 1) |
6787 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6789 I915_WRITE(VTOTAL(cpu_transcoder
),
6790 (adjusted_mode
->crtc_vdisplay
- 1) |
6791 ((crtc_vtotal
- 1) << 16));
6792 I915_WRITE(VBLANK(cpu_transcoder
),
6793 (adjusted_mode
->crtc_vblank_start
- 1) |
6794 ((crtc_vblank_end
- 1) << 16));
6795 I915_WRITE(VSYNC(cpu_transcoder
),
6796 (adjusted_mode
->crtc_vsync_start
- 1) |
6797 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6799 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6800 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6801 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6803 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6804 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6805 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6807 /* pipesrc controls the size that is scaled from, which should
6808 * always be the user's requested size.
6810 I915_WRITE(PIPESRC(pipe
),
6811 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
6812 (intel_crtc
->config
->pipe_src_h
- 1));
6815 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6816 struct intel_crtc_state
*pipe_config
)
6818 struct drm_device
*dev
= crtc
->base
.dev
;
6819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6820 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6823 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6824 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6825 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6826 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6827 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6828 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6829 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6830 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6831 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6833 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6834 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6835 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6836 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6837 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6838 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6839 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6840 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6841 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6843 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6844 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6845 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
6846 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
6849 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6850 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6851 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6853 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
6854 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
6857 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6858 struct intel_crtc_state
*pipe_config
)
6860 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
6861 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
6862 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
6863 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
6865 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
6866 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
6867 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
6868 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
6870 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
6872 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6873 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
6876 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6878 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6884 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6885 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6886 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6888 if (intel_crtc
->config
->double_wide
)
6889 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6891 /* only g4x and later have fancy bpc/dither controls */
6892 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6893 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6894 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
6895 pipeconf
|= PIPECONF_DITHER_EN
|
6896 PIPECONF_DITHER_TYPE_SP
;
6898 switch (intel_crtc
->config
->pipe_bpp
) {
6900 pipeconf
|= PIPECONF_6BPC
;
6903 pipeconf
|= PIPECONF_8BPC
;
6906 pipeconf
|= PIPECONF_10BPC
;
6909 /* Case prevented by intel_choose_pipe_bpp_dither. */
6914 if (HAS_PIPE_CXSR(dev
)) {
6915 if (intel_crtc
->lowfreq_avail
) {
6916 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6917 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6919 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6923 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6924 if (INTEL_INFO(dev
)->gen
< 4 ||
6925 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6926 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6928 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6930 pipeconf
|= PIPECONF_PROGRESSIVE
;
6932 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
6933 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6935 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6936 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6939 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
6940 struct intel_crtc_state
*crtc_state
)
6942 struct drm_device
*dev
= crtc
->base
.dev
;
6943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6944 int refclk
, num_connectors
= 0;
6945 intel_clock_t clock
, reduced_clock
;
6946 bool ok
, has_reduced_clock
= false;
6947 bool is_lvds
= false, is_dsi
= false;
6948 struct intel_encoder
*encoder
;
6949 const intel_limit_t
*limit
;
6950 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
6951 struct drm_connector_state
*connector_state
;
6954 for (i
= 0; i
< state
->num_connector
; i
++) {
6955 if (!state
->connectors
[i
])
6958 connector_state
= state
->connector_states
[i
];
6959 if (connector_state
->crtc
!= &crtc
->base
)
6962 encoder
= to_intel_encoder(connector_state
->best_encoder
);
6964 switch (encoder
->type
) {
6965 case INTEL_OUTPUT_LVDS
:
6968 case INTEL_OUTPUT_DSI
:
6981 if (!crtc_state
->clock_set
) {
6982 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
6985 * Returns a set of divisors for the desired target clock with
6986 * the given refclk, or FALSE. The returned values represent
6987 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6990 limit
= intel_limit(crtc_state
, refclk
);
6991 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
6992 crtc_state
->port_clock
,
6993 refclk
, NULL
, &clock
);
6995 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6999 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7001 * Ensure we match the reduced clock's P to the target
7002 * clock. If the clocks don't match, we can't switch
7003 * the display clock by using the FP0/FP1. In such case
7004 * we will disable the LVDS downclock feature.
7007 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7008 dev_priv
->lvds_downclock
,
7012 /* Compat-code for transition, will disappear. */
7013 crtc_state
->dpll
.n
= clock
.n
;
7014 crtc_state
->dpll
.m1
= clock
.m1
;
7015 crtc_state
->dpll
.m2
= clock
.m2
;
7016 crtc_state
->dpll
.p1
= clock
.p1
;
7017 crtc_state
->dpll
.p2
= clock
.p2
;
7021 i8xx_update_pll(crtc
, crtc_state
,
7022 has_reduced_clock
? &reduced_clock
: NULL
,
7024 } else if (IS_CHERRYVIEW(dev
)) {
7025 chv_update_pll(crtc
, crtc_state
);
7026 } else if (IS_VALLEYVIEW(dev
)) {
7027 vlv_update_pll(crtc
, crtc_state
);
7029 i9xx_update_pll(crtc
, crtc_state
,
7030 has_reduced_clock
? &reduced_clock
: NULL
,
7037 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7038 struct intel_crtc_state
*pipe_config
)
7040 struct drm_device
*dev
= crtc
->base
.dev
;
7041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7044 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7047 tmp
= I915_READ(PFIT_CONTROL
);
7048 if (!(tmp
& PFIT_ENABLE
))
7051 /* Check whether the pfit is attached to our pipe. */
7052 if (INTEL_INFO(dev
)->gen
< 4) {
7053 if (crtc
->pipe
!= PIPE_B
)
7056 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7060 pipe_config
->gmch_pfit
.control
= tmp
;
7061 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7062 if (INTEL_INFO(dev
)->gen
< 5)
7063 pipe_config
->gmch_pfit
.lvds_border_bits
=
7064 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7067 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7068 struct intel_crtc_state
*pipe_config
)
7070 struct drm_device
*dev
= crtc
->base
.dev
;
7071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7072 int pipe
= pipe_config
->cpu_transcoder
;
7073 intel_clock_t clock
;
7075 int refclk
= 100000;
7077 /* In case of MIPI DPLL will not even be used */
7078 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7081 mutex_lock(&dev_priv
->dpio_lock
);
7082 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7083 mutex_unlock(&dev_priv
->dpio_lock
);
7085 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7086 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7087 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7088 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7089 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7091 vlv_clock(refclk
, &clock
);
7093 /* clock.dot is the fast clock */
7094 pipe_config
->port_clock
= clock
.dot
/ 5;
7098 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7099 struct intel_initial_plane_config
*plane_config
)
7101 struct drm_device
*dev
= crtc
->base
.dev
;
7102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7103 u32 val
, base
, offset
;
7104 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7105 int fourcc
, pixel_format
;
7106 unsigned int aligned_height
;
7107 struct drm_framebuffer
*fb
;
7108 struct intel_framebuffer
*intel_fb
;
7110 val
= I915_READ(DSPCNTR(plane
));
7111 if (!(val
& DISPLAY_PLANE_ENABLE
))
7114 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7116 DRM_DEBUG_KMS("failed to alloc fb\n");
7120 fb
= &intel_fb
->base
;
7122 if (INTEL_INFO(dev
)->gen
>= 4) {
7123 if (val
& DISPPLANE_TILED
) {
7124 plane_config
->tiling
= I915_TILING_X
;
7125 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7129 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7130 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7131 fb
->pixel_format
= fourcc
;
7132 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7134 if (INTEL_INFO(dev
)->gen
>= 4) {
7135 if (plane_config
->tiling
)
7136 offset
= I915_READ(DSPTILEOFF(plane
));
7138 offset
= I915_READ(DSPLINOFF(plane
));
7139 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7141 base
= I915_READ(DSPADDR(plane
));
7143 plane_config
->base
= base
;
7145 val
= I915_READ(PIPESRC(pipe
));
7146 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7147 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7149 val
= I915_READ(DSPSTRIDE(pipe
));
7150 fb
->pitches
[0] = val
& 0xffffffc0;
7152 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7156 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7158 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7159 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7160 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7161 plane_config
->size
);
7163 plane_config
->fb
= intel_fb
;
7166 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7167 struct intel_crtc_state
*pipe_config
)
7169 struct drm_device
*dev
= crtc
->base
.dev
;
7170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7171 int pipe
= pipe_config
->cpu_transcoder
;
7172 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7173 intel_clock_t clock
;
7174 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
7175 int refclk
= 100000;
7177 mutex_lock(&dev_priv
->dpio_lock
);
7178 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7179 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7180 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7181 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7182 mutex_unlock(&dev_priv
->dpio_lock
);
7184 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7185 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
7186 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7187 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7188 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7190 chv_clock(refclk
, &clock
);
7192 /* clock.dot is the fast clock */
7193 pipe_config
->port_clock
= clock
.dot
/ 5;
7196 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7197 struct intel_crtc_state
*pipe_config
)
7199 struct drm_device
*dev
= crtc
->base
.dev
;
7200 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7203 if (!intel_display_power_is_enabled(dev_priv
,
7204 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7207 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7208 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7210 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7211 if (!(tmp
& PIPECONF_ENABLE
))
7214 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7215 switch (tmp
& PIPECONF_BPC_MASK
) {
7217 pipe_config
->pipe_bpp
= 18;
7220 pipe_config
->pipe_bpp
= 24;
7222 case PIPECONF_10BPC
:
7223 pipe_config
->pipe_bpp
= 30;
7230 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7231 pipe_config
->limited_color_range
= true;
7233 if (INTEL_INFO(dev
)->gen
< 4)
7234 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7236 intel_get_pipe_timings(crtc
, pipe_config
);
7238 i9xx_get_pfit_config(crtc
, pipe_config
);
7240 if (INTEL_INFO(dev
)->gen
>= 4) {
7241 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7242 pipe_config
->pixel_multiplier
=
7243 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7244 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7245 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7246 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7247 tmp
= I915_READ(DPLL(crtc
->pipe
));
7248 pipe_config
->pixel_multiplier
=
7249 ((tmp
& SDVO_MULTIPLIER_MASK
)
7250 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7252 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7253 * port and will be fixed up in the encoder->get_config
7255 pipe_config
->pixel_multiplier
= 1;
7257 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7258 if (!IS_VALLEYVIEW(dev
)) {
7260 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7261 * on 830. Filter it out here so that we don't
7262 * report errors due to that.
7265 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7267 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7268 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7270 /* Mask out read-only status bits. */
7271 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7272 DPLL_PORTC_READY_MASK
|
7273 DPLL_PORTB_READY_MASK
);
7276 if (IS_CHERRYVIEW(dev
))
7277 chv_crtc_clock_get(crtc
, pipe_config
);
7278 else if (IS_VALLEYVIEW(dev
))
7279 vlv_crtc_clock_get(crtc
, pipe_config
);
7281 i9xx_crtc_clock_get(crtc
, pipe_config
);
7286 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
7288 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7289 struct intel_encoder
*encoder
;
7291 bool has_lvds
= false;
7292 bool has_cpu_edp
= false;
7293 bool has_panel
= false;
7294 bool has_ck505
= false;
7295 bool can_ssc
= false;
7297 /* We need to take the global config into account */
7298 for_each_intel_encoder(dev
, encoder
) {
7299 switch (encoder
->type
) {
7300 case INTEL_OUTPUT_LVDS
:
7304 case INTEL_OUTPUT_EDP
:
7306 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
7314 if (HAS_PCH_IBX(dev
)) {
7315 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
7316 can_ssc
= has_ck505
;
7322 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7323 has_panel
, has_lvds
, has_ck505
);
7325 /* Ironlake: try to setup display ref clock before DPLL
7326 * enabling. This is only under driver's control after
7327 * PCH B stepping, previous chipset stepping should be
7328 * ignoring this setting.
7330 val
= I915_READ(PCH_DREF_CONTROL
);
7332 /* As we must carefully and slowly disable/enable each source in turn,
7333 * compute the final state we want first and check if we need to
7334 * make any changes at all.
7337 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7339 final
|= DREF_NONSPREAD_CK505_ENABLE
;
7341 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7343 final
&= ~DREF_SSC_SOURCE_MASK
;
7344 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7345 final
&= ~DREF_SSC1_ENABLE
;
7348 final
|= DREF_SSC_SOURCE_ENABLE
;
7350 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7351 final
|= DREF_SSC1_ENABLE
;
7354 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7355 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7357 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7359 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7361 final
|= DREF_SSC_SOURCE_DISABLE
;
7362 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7368 /* Always enable nonspread source */
7369 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7372 val
|= DREF_NONSPREAD_CK505_ENABLE
;
7374 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7377 val
&= ~DREF_SSC_SOURCE_MASK
;
7378 val
|= DREF_SSC_SOURCE_ENABLE
;
7380 /* SSC must be turned on before enabling the CPU output */
7381 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7382 DRM_DEBUG_KMS("Using SSC on panel\n");
7383 val
|= DREF_SSC1_ENABLE
;
7385 val
&= ~DREF_SSC1_ENABLE
;
7387 /* Get SSC going before enabling the outputs */
7388 I915_WRITE(PCH_DREF_CONTROL
, val
);
7389 POSTING_READ(PCH_DREF_CONTROL
);
7392 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7394 /* Enable CPU source on CPU attached eDP */
7396 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7397 DRM_DEBUG_KMS("Using SSC on eDP\n");
7398 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7400 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7402 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7404 I915_WRITE(PCH_DREF_CONTROL
, val
);
7405 POSTING_READ(PCH_DREF_CONTROL
);
7408 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7410 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7412 /* Turn off CPU output */
7413 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7415 I915_WRITE(PCH_DREF_CONTROL
, val
);
7416 POSTING_READ(PCH_DREF_CONTROL
);
7419 /* Turn off the SSC source */
7420 val
&= ~DREF_SSC_SOURCE_MASK
;
7421 val
|= DREF_SSC_SOURCE_DISABLE
;
7424 val
&= ~DREF_SSC1_ENABLE
;
7426 I915_WRITE(PCH_DREF_CONTROL
, val
);
7427 POSTING_READ(PCH_DREF_CONTROL
);
7431 BUG_ON(val
!= final
);
7434 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7438 tmp
= I915_READ(SOUTH_CHICKEN2
);
7439 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7440 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7442 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
7443 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7444 DRM_ERROR("FDI mPHY reset assert timeout\n");
7446 tmp
= I915_READ(SOUTH_CHICKEN2
);
7447 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7448 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7450 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
7451 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7452 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7455 /* WaMPhyProgramming:hsw */
7456 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7460 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7461 tmp
&= ~(0xFF << 24);
7462 tmp
|= (0x12 << 24);
7463 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7465 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7467 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7469 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
7471 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
7473 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
7474 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7475 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
7477 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
7478 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7479 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
7481 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
7484 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
7486 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
7489 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
7491 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
7494 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
7496 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
7499 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
7501 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
7502 tmp
&= ~(0xFF << 16);
7503 tmp
|= (0x1C << 16);
7504 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
7506 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
7507 tmp
&= ~(0xFF << 16);
7508 tmp
|= (0x1C << 16);
7509 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
7511 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
7513 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
7515 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
7517 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
7519 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
7520 tmp
&= ~(0xF << 28);
7522 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
7524 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
7525 tmp
&= ~(0xF << 28);
7527 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
7530 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7531 * Programming" based on the parameters passed:
7532 * - Sequence to enable CLKOUT_DP
7533 * - Sequence to enable CLKOUT_DP without spread
7534 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7536 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
7539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7542 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
7544 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
7545 with_fdi
, "LP PCH doesn't have FDI\n"))
7548 mutex_lock(&dev_priv
->dpio_lock
);
7550 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7551 tmp
&= ~SBI_SSCCTL_DISABLE
;
7552 tmp
|= SBI_SSCCTL_PATHALT
;
7553 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7558 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7559 tmp
&= ~SBI_SSCCTL_PATHALT
;
7560 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7563 lpt_reset_fdi_mphy(dev_priv
);
7564 lpt_program_fdi_mphy(dev_priv
);
7568 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7569 SBI_GEN0
: SBI_DBUFF0
;
7570 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7571 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7572 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7574 mutex_unlock(&dev_priv
->dpio_lock
);
7577 /* Sequence to disable CLKOUT_DP */
7578 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7583 mutex_lock(&dev_priv
->dpio_lock
);
7585 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7586 SBI_GEN0
: SBI_DBUFF0
;
7587 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7588 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7589 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7591 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7592 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7593 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7594 tmp
|= SBI_SSCCTL_PATHALT
;
7595 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7598 tmp
|= SBI_SSCCTL_DISABLE
;
7599 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7602 mutex_unlock(&dev_priv
->dpio_lock
);
7605 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7607 struct intel_encoder
*encoder
;
7608 bool has_vga
= false;
7610 for_each_intel_encoder(dev
, encoder
) {
7611 switch (encoder
->type
) {
7612 case INTEL_OUTPUT_ANALOG
:
7621 lpt_enable_clkout_dp(dev
, true, true);
7623 lpt_disable_clkout_dp(dev
);
7627 * Initialize reference clocks when the driver loads
7629 void intel_init_pch_refclk(struct drm_device
*dev
)
7631 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7632 ironlake_init_pch_refclk(dev
);
7633 else if (HAS_PCH_LPT(dev
))
7634 lpt_init_pch_refclk(dev
);
7637 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
7639 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
7640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7641 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7642 struct drm_connector_state
*connector_state
;
7643 struct intel_encoder
*encoder
;
7644 int num_connectors
= 0, i
;
7645 bool is_lvds
= false;
7647 for (i
= 0; i
< state
->num_connector
; i
++) {
7648 if (!state
->connectors
[i
])
7651 connector_state
= state
->connector_states
[i
];
7652 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
7655 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7657 switch (encoder
->type
) {
7658 case INTEL_OUTPUT_LVDS
:
7667 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7668 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7669 dev_priv
->vbt
.lvds_ssc_freq
);
7670 return dev_priv
->vbt
.lvds_ssc_freq
;
7676 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7678 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7679 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7680 int pipe
= intel_crtc
->pipe
;
7685 switch (intel_crtc
->config
->pipe_bpp
) {
7687 val
|= PIPECONF_6BPC
;
7690 val
|= PIPECONF_8BPC
;
7693 val
|= PIPECONF_10BPC
;
7696 val
|= PIPECONF_12BPC
;
7699 /* Case prevented by intel_choose_pipe_bpp_dither. */
7703 if (intel_crtc
->config
->dither
)
7704 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7706 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7707 val
|= PIPECONF_INTERLACED_ILK
;
7709 val
|= PIPECONF_PROGRESSIVE
;
7711 if (intel_crtc
->config
->limited_color_range
)
7712 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7714 I915_WRITE(PIPECONF(pipe
), val
);
7715 POSTING_READ(PIPECONF(pipe
));
7719 * Set up the pipe CSC unit.
7721 * Currently only full range RGB to limited range RGB conversion
7722 * is supported, but eventually this should handle various
7723 * RGB<->YCbCr scenarios as well.
7725 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7727 struct drm_device
*dev
= crtc
->dev
;
7728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7729 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7730 int pipe
= intel_crtc
->pipe
;
7731 uint16_t coeff
= 0x7800; /* 1.0 */
7734 * TODO: Check what kind of values actually come out of the pipe
7735 * with these coeff/postoff values and adjust to get the best
7736 * accuracy. Perhaps we even need to take the bpc value into
7740 if (intel_crtc
->config
->limited_color_range
)
7741 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7744 * GY/GU and RY/RU should be the other way around according
7745 * to BSpec, but reality doesn't agree. Just set them up in
7746 * a way that results in the correct picture.
7748 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7749 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7751 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7752 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7754 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7755 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7757 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7758 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7759 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7761 if (INTEL_INFO(dev
)->gen
> 6) {
7762 uint16_t postoff
= 0;
7764 if (intel_crtc
->config
->limited_color_range
)
7765 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7767 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7768 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7769 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7771 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7773 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7775 if (intel_crtc
->config
->limited_color_range
)
7776 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7778 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7782 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7784 struct drm_device
*dev
= crtc
->dev
;
7785 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7786 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7787 enum pipe pipe
= intel_crtc
->pipe
;
7788 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7793 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
7794 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7796 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7797 val
|= PIPECONF_INTERLACED_ILK
;
7799 val
|= PIPECONF_PROGRESSIVE
;
7801 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7802 POSTING_READ(PIPECONF(cpu_transcoder
));
7804 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7805 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7807 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7810 switch (intel_crtc
->config
->pipe_bpp
) {
7812 val
|= PIPEMISC_DITHER_6_BPC
;
7815 val
|= PIPEMISC_DITHER_8_BPC
;
7818 val
|= PIPEMISC_DITHER_10_BPC
;
7821 val
|= PIPEMISC_DITHER_12_BPC
;
7824 /* Case prevented by pipe_config_set_bpp. */
7828 if (intel_crtc
->config
->dither
)
7829 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7831 I915_WRITE(PIPEMISC(pipe
), val
);
7835 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7836 struct intel_crtc_state
*crtc_state
,
7837 intel_clock_t
*clock
,
7838 bool *has_reduced_clock
,
7839 intel_clock_t
*reduced_clock
)
7841 struct drm_device
*dev
= crtc
->dev
;
7842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7844 const intel_limit_t
*limit
;
7845 bool ret
, is_lvds
= false;
7847 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
7849 refclk
= ironlake_get_refclk(crtc_state
);
7852 * Returns a set of divisors for the desired target clock with the given
7853 * refclk, or FALSE. The returned values represent the clock equation:
7854 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7856 limit
= intel_limit(crtc_state
, refclk
);
7857 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7858 crtc_state
->port_clock
,
7859 refclk
, NULL
, clock
);
7863 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7865 * Ensure we match the reduced clock's P to the target clock.
7866 * If the clocks don't match, we can't switch the display clock
7867 * by using the FP0/FP1. In such case we will disable the LVDS
7868 * downclock feature.
7870 *has_reduced_clock
=
7871 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7872 dev_priv
->lvds_downclock
,
7880 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7883 * Account for spread spectrum to avoid
7884 * oversubscribing the link. Max center spread
7885 * is 2.5%; use 5% for safety's sake.
7887 u32 bps
= target_clock
* bpp
* 21 / 20;
7888 return DIV_ROUND_UP(bps
, link_bw
* 8);
7891 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7893 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7896 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7897 struct intel_crtc_state
*crtc_state
,
7899 intel_clock_t
*reduced_clock
, u32
*fp2
)
7901 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7902 struct drm_device
*dev
= crtc
->dev
;
7903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7904 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7905 struct drm_connector_state
*connector_state
;
7906 struct intel_encoder
*encoder
;
7908 int factor
, num_connectors
= 0, i
;
7909 bool is_lvds
= false, is_sdvo
= false;
7911 for (i
= 0; i
< state
->num_connector
; i
++) {
7912 if (!state
->connectors
[i
])
7915 connector_state
= state
->connector_states
[i
];
7916 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
7919 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7921 switch (encoder
->type
) {
7922 case INTEL_OUTPUT_LVDS
:
7925 case INTEL_OUTPUT_SDVO
:
7926 case INTEL_OUTPUT_HDMI
:
7936 /* Enable autotuning of the PLL clock (if permissible) */
7939 if ((intel_panel_use_ssc(dev_priv
) &&
7940 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7941 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7943 } else if (crtc_state
->sdvo_tv_clock
)
7946 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
7949 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7955 dpll
|= DPLLB_MODE_LVDS
;
7957 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7959 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7960 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7963 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7964 if (crtc_state
->has_dp_encoder
)
7965 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7967 /* compute bitmask from p1 value */
7968 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7970 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7972 switch (crtc_state
->dpll
.p2
) {
7974 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7977 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7980 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7983 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7987 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7988 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7990 dpll
|= PLL_REF_INPUT_DREFCLK
;
7992 return dpll
| DPLL_VCO_ENABLE
;
7995 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
7996 struct intel_crtc_state
*crtc_state
)
7998 struct drm_device
*dev
= crtc
->base
.dev
;
7999 intel_clock_t clock
, reduced_clock
;
8000 u32 dpll
= 0, fp
= 0, fp2
= 0;
8001 bool ok
, has_reduced_clock
= false;
8002 bool is_lvds
= false;
8003 struct intel_shared_dpll
*pll
;
8005 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8007 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8008 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8010 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8011 &has_reduced_clock
, &reduced_clock
);
8012 if (!ok
&& !crtc_state
->clock_set
) {
8013 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8016 /* Compat-code for transition, will disappear. */
8017 if (!crtc_state
->clock_set
) {
8018 crtc_state
->dpll
.n
= clock
.n
;
8019 crtc_state
->dpll
.m1
= clock
.m1
;
8020 crtc_state
->dpll
.m2
= clock
.m2
;
8021 crtc_state
->dpll
.p1
= clock
.p1
;
8022 crtc_state
->dpll
.p2
= clock
.p2
;
8025 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8026 if (crtc_state
->has_pch_encoder
) {
8027 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8028 if (has_reduced_clock
)
8029 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8031 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8032 &fp
, &reduced_clock
,
8033 has_reduced_clock
? &fp2
: NULL
);
8035 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8036 crtc_state
->dpll_hw_state
.fp0
= fp
;
8037 if (has_reduced_clock
)
8038 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8040 crtc_state
->dpll_hw_state
.fp1
= fp
;
8042 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8044 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8045 pipe_name(crtc
->pipe
));
8050 if (is_lvds
&& has_reduced_clock
)
8051 crtc
->lowfreq_avail
= true;
8053 crtc
->lowfreq_avail
= false;
8058 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8059 struct intel_link_m_n
*m_n
)
8061 struct drm_device
*dev
= crtc
->base
.dev
;
8062 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8063 enum pipe pipe
= crtc
->pipe
;
8065 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8066 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8067 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8069 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8070 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8071 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8074 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8075 enum transcoder transcoder
,
8076 struct intel_link_m_n
*m_n
,
8077 struct intel_link_m_n
*m2_n2
)
8079 struct drm_device
*dev
= crtc
->base
.dev
;
8080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8081 enum pipe pipe
= crtc
->pipe
;
8083 if (INTEL_INFO(dev
)->gen
>= 5) {
8084 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8085 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8086 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8088 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8089 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8090 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8091 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8092 * gen < 8) and if DRRS is supported (to make sure the
8093 * registers are not unnecessarily read).
8095 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8096 crtc
->config
->has_drrs
) {
8097 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8098 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8099 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8101 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8102 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8103 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8106 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8107 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8108 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8110 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8111 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8112 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8116 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8117 struct intel_crtc_state
*pipe_config
)
8119 if (pipe_config
->has_pch_encoder
)
8120 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8122 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8123 &pipe_config
->dp_m_n
,
8124 &pipe_config
->dp_m2_n2
);
8127 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8128 struct intel_crtc_state
*pipe_config
)
8130 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8131 &pipe_config
->fdi_m_n
, NULL
);
8134 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8135 struct intel_crtc_state
*pipe_config
)
8137 struct drm_device
*dev
= crtc
->base
.dev
;
8138 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8141 tmp
= I915_READ(PS_CTL(crtc
->pipe
));
8143 if (tmp
& PS_ENABLE
) {
8144 pipe_config
->pch_pfit
.enabled
= true;
8145 pipe_config
->pch_pfit
.pos
= I915_READ(PS_WIN_POS(crtc
->pipe
));
8146 pipe_config
->pch_pfit
.size
= I915_READ(PS_WIN_SZ(crtc
->pipe
));
8151 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8152 struct intel_initial_plane_config
*plane_config
)
8154 struct drm_device
*dev
= crtc
->base
.dev
;
8155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8156 u32 val
, base
, offset
, stride_mult
, tiling
;
8157 int pipe
= crtc
->pipe
;
8158 int fourcc
, pixel_format
;
8159 unsigned int aligned_height
;
8160 struct drm_framebuffer
*fb
;
8161 struct intel_framebuffer
*intel_fb
;
8163 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8165 DRM_DEBUG_KMS("failed to alloc fb\n");
8169 fb
= &intel_fb
->base
;
8171 val
= I915_READ(PLANE_CTL(pipe
, 0));
8172 if (!(val
& PLANE_CTL_ENABLE
))
8175 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8176 fourcc
= skl_format_to_fourcc(pixel_format
,
8177 val
& PLANE_CTL_ORDER_RGBX
,
8178 val
& PLANE_CTL_ALPHA_MASK
);
8179 fb
->pixel_format
= fourcc
;
8180 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8182 tiling
= val
& PLANE_CTL_TILED_MASK
;
8184 case PLANE_CTL_TILED_LINEAR
:
8185 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
8187 case PLANE_CTL_TILED_X
:
8188 plane_config
->tiling
= I915_TILING_X
;
8189 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8191 case PLANE_CTL_TILED_Y
:
8192 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
8194 case PLANE_CTL_TILED_YF
:
8195 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
8198 MISSING_CASE(tiling
);
8202 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8203 plane_config
->base
= base
;
8205 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8207 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8208 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8209 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8211 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8212 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
8214 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8216 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8220 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8222 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8223 pipe_name(pipe
), fb
->width
, fb
->height
,
8224 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8225 plane_config
->size
);
8227 plane_config
->fb
= intel_fb
;
8234 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8235 struct intel_crtc_state
*pipe_config
)
8237 struct drm_device
*dev
= crtc
->base
.dev
;
8238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8241 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8243 if (tmp
& PF_ENABLE
) {
8244 pipe_config
->pch_pfit
.enabled
= true;
8245 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8246 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8248 /* We currently do not free assignements of panel fitters on
8249 * ivb/hsw (since we don't use the higher upscaling modes which
8250 * differentiates them) so just WARN about this case for now. */
8252 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8253 PF_PIPE_SEL_IVB(crtc
->pipe
));
8259 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8260 struct intel_initial_plane_config
*plane_config
)
8262 struct drm_device
*dev
= crtc
->base
.dev
;
8263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8264 u32 val
, base
, offset
;
8265 int pipe
= crtc
->pipe
;
8266 int fourcc
, pixel_format
;
8267 unsigned int aligned_height
;
8268 struct drm_framebuffer
*fb
;
8269 struct intel_framebuffer
*intel_fb
;
8271 val
= I915_READ(DSPCNTR(pipe
));
8272 if (!(val
& DISPLAY_PLANE_ENABLE
))
8275 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8277 DRM_DEBUG_KMS("failed to alloc fb\n");
8281 fb
= &intel_fb
->base
;
8283 if (INTEL_INFO(dev
)->gen
>= 4) {
8284 if (val
& DISPPLANE_TILED
) {
8285 plane_config
->tiling
= I915_TILING_X
;
8286 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8290 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8291 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8292 fb
->pixel_format
= fourcc
;
8293 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8295 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
8296 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
8297 offset
= I915_READ(DSPOFFSET(pipe
));
8299 if (plane_config
->tiling
)
8300 offset
= I915_READ(DSPTILEOFF(pipe
));
8302 offset
= I915_READ(DSPLINOFF(pipe
));
8304 plane_config
->base
= base
;
8306 val
= I915_READ(PIPESRC(pipe
));
8307 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8308 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8310 val
= I915_READ(DSPSTRIDE(pipe
));
8311 fb
->pitches
[0] = val
& 0xffffffc0;
8313 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8317 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8319 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8320 pipe_name(pipe
), fb
->width
, fb
->height
,
8321 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8322 plane_config
->size
);
8324 plane_config
->fb
= intel_fb
;
8327 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
8328 struct intel_crtc_state
*pipe_config
)
8330 struct drm_device
*dev
= crtc
->base
.dev
;
8331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8334 if (!intel_display_power_is_enabled(dev_priv
,
8335 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8338 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8339 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8341 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8342 if (!(tmp
& PIPECONF_ENABLE
))
8345 switch (tmp
& PIPECONF_BPC_MASK
) {
8347 pipe_config
->pipe_bpp
= 18;
8350 pipe_config
->pipe_bpp
= 24;
8352 case PIPECONF_10BPC
:
8353 pipe_config
->pipe_bpp
= 30;
8355 case PIPECONF_12BPC
:
8356 pipe_config
->pipe_bpp
= 36;
8362 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
8363 pipe_config
->limited_color_range
= true;
8365 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
8366 struct intel_shared_dpll
*pll
;
8368 pipe_config
->has_pch_encoder
= true;
8370 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
8371 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8372 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8374 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8376 if (HAS_PCH_IBX(dev_priv
->dev
)) {
8377 pipe_config
->shared_dpll
=
8378 (enum intel_dpll_id
) crtc
->pipe
;
8380 tmp
= I915_READ(PCH_DPLL_SEL
);
8381 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
8382 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
8384 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
8387 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8389 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8390 &pipe_config
->dpll_hw_state
));
8392 tmp
= pipe_config
->dpll_hw_state
.dpll
;
8393 pipe_config
->pixel_multiplier
=
8394 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
8395 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
8397 ironlake_pch_clock_get(crtc
, pipe_config
);
8399 pipe_config
->pixel_multiplier
= 1;
8402 intel_get_pipe_timings(crtc
, pipe_config
);
8404 ironlake_get_pfit_config(crtc
, pipe_config
);
8409 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8411 struct drm_device
*dev
= dev_priv
->dev
;
8412 struct intel_crtc
*crtc
;
8414 for_each_intel_crtc(dev
, crtc
)
8415 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8416 pipe_name(crtc
->pipe
));
8418 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
8419 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8420 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8421 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8422 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
8423 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8424 "CPU PWM1 enabled\n");
8425 if (IS_HASWELL(dev
))
8426 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8427 "CPU PWM2 enabled\n");
8428 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8429 "PCH PWM1 enabled\n");
8430 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8431 "Utility pin enabled\n");
8432 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8435 * In theory we can still leave IRQs enabled, as long as only the HPD
8436 * interrupts remain enabled. We used to check for that, but since it's
8437 * gen-specific and since we only disable LCPLL after we fully disable
8438 * the interrupts, the check below should be enough.
8440 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8443 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8445 struct drm_device
*dev
= dev_priv
->dev
;
8447 if (IS_HASWELL(dev
))
8448 return I915_READ(D_COMP_HSW
);
8450 return I915_READ(D_COMP_BDW
);
8453 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8455 struct drm_device
*dev
= dev_priv
->dev
;
8457 if (IS_HASWELL(dev
)) {
8458 mutex_lock(&dev_priv
->rps
.hw_lock
);
8459 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8461 DRM_ERROR("Failed to write to D_COMP\n");
8462 mutex_unlock(&dev_priv
->rps
.hw_lock
);
8464 I915_WRITE(D_COMP_BDW
, val
);
8465 POSTING_READ(D_COMP_BDW
);
8470 * This function implements pieces of two sequences from BSpec:
8471 * - Sequence for display software to disable LCPLL
8472 * - Sequence for display software to allow package C8+
8473 * The steps implemented here are just the steps that actually touch the LCPLL
8474 * register. Callers should take care of disabling all the display engine
8475 * functions, doing the mode unset, fixing interrupts, etc.
8477 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
8478 bool switch_to_fclk
, bool allow_power_down
)
8482 assert_can_disable_lcpll(dev_priv
);
8484 val
= I915_READ(LCPLL_CTL
);
8486 if (switch_to_fclk
) {
8487 val
|= LCPLL_CD_SOURCE_FCLK
;
8488 I915_WRITE(LCPLL_CTL
, val
);
8490 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
8491 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
8492 DRM_ERROR("Switching to FCLK failed\n");
8494 val
= I915_READ(LCPLL_CTL
);
8497 val
|= LCPLL_PLL_DISABLE
;
8498 I915_WRITE(LCPLL_CTL
, val
);
8499 POSTING_READ(LCPLL_CTL
);
8501 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
8502 DRM_ERROR("LCPLL still locked\n");
8504 val
= hsw_read_dcomp(dev_priv
);
8505 val
|= D_COMP_COMP_DISABLE
;
8506 hsw_write_dcomp(dev_priv
, val
);
8509 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
8511 DRM_ERROR("D_COMP RCOMP still in progress\n");
8513 if (allow_power_down
) {
8514 val
= I915_READ(LCPLL_CTL
);
8515 val
|= LCPLL_POWER_DOWN_ALLOW
;
8516 I915_WRITE(LCPLL_CTL
, val
);
8517 POSTING_READ(LCPLL_CTL
);
8522 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8525 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
8529 val
= I915_READ(LCPLL_CTL
);
8531 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
8532 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
8536 * Make sure we're not on PC8 state before disabling PC8, otherwise
8537 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8539 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
8541 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
8542 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
8543 I915_WRITE(LCPLL_CTL
, val
);
8544 POSTING_READ(LCPLL_CTL
);
8547 val
= hsw_read_dcomp(dev_priv
);
8548 val
|= D_COMP_COMP_FORCE
;
8549 val
&= ~D_COMP_COMP_DISABLE
;
8550 hsw_write_dcomp(dev_priv
, val
);
8552 val
= I915_READ(LCPLL_CTL
);
8553 val
&= ~LCPLL_PLL_DISABLE
;
8554 I915_WRITE(LCPLL_CTL
, val
);
8556 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
8557 DRM_ERROR("LCPLL not locked yet\n");
8559 if (val
& LCPLL_CD_SOURCE_FCLK
) {
8560 val
= I915_READ(LCPLL_CTL
);
8561 val
&= ~LCPLL_CD_SOURCE_FCLK
;
8562 I915_WRITE(LCPLL_CTL
, val
);
8564 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
8565 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
8566 DRM_ERROR("Switching back to LCPLL failed\n");
8569 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
8573 * Package states C8 and deeper are really deep PC states that can only be
8574 * reached when all the devices on the system allow it, so even if the graphics
8575 * device allows PC8+, it doesn't mean the system will actually get to these
8576 * states. Our driver only allows PC8+ when going into runtime PM.
8578 * The requirements for PC8+ are that all the outputs are disabled, the power
8579 * well is disabled and most interrupts are disabled, and these are also
8580 * requirements for runtime PM. When these conditions are met, we manually do
8581 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8582 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8585 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8586 * the state of some registers, so when we come back from PC8+ we need to
8587 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8588 * need to take care of the registers kept by RC6. Notice that this happens even
8589 * if we don't put the device in PCI D3 state (which is what currently happens
8590 * because of the runtime PM support).
8592 * For more, read "Display Sequences for Package C8" on the hardware
8595 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
8597 struct drm_device
*dev
= dev_priv
->dev
;
8600 DRM_DEBUG_KMS("Enabling package C8+\n");
8602 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8603 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8604 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8605 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8608 lpt_disable_clkout_dp(dev
);
8609 hsw_disable_lcpll(dev_priv
, true, true);
8612 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
8614 struct drm_device
*dev
= dev_priv
->dev
;
8617 DRM_DEBUG_KMS("Disabling package C8+\n");
8619 hsw_restore_lcpll(dev_priv
);
8620 lpt_init_pch_refclk(dev
);
8622 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8623 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8624 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
8625 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8628 intel_prepare_ddi(dev
);
8631 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
8632 struct intel_crtc_state
*crtc_state
)
8634 if (!intel_ddi_pll_select(crtc
, crtc_state
))
8637 crtc
->lowfreq_avail
= false;
8642 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8644 struct intel_crtc_state
*pipe_config
)
8646 u32 temp
, dpll_ctl1
;
8648 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
8649 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
8651 switch (pipe_config
->ddi_pll_sel
) {
8654 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8655 * of the shared DPLL framework and thus needs to be read out
8658 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
8659 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
8662 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
8665 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
8668 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
8673 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8675 struct intel_crtc_state
*pipe_config
)
8677 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
8679 switch (pipe_config
->ddi_pll_sel
) {
8680 case PORT_CLK_SEL_WRPLL1
:
8681 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
8683 case PORT_CLK_SEL_WRPLL2
:
8684 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
8689 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
8690 struct intel_crtc_state
*pipe_config
)
8692 struct drm_device
*dev
= crtc
->base
.dev
;
8693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8694 struct intel_shared_dpll
*pll
;
8698 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
8700 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
8702 if (IS_SKYLAKE(dev
))
8703 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
8705 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
8707 if (pipe_config
->shared_dpll
>= 0) {
8708 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8710 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8711 &pipe_config
->dpll_hw_state
));
8715 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8716 * DDI E. So just check whether this pipe is wired to DDI E and whether
8717 * the PCH transcoder is on.
8719 if (INTEL_INFO(dev
)->gen
< 9 &&
8720 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8721 pipe_config
->has_pch_encoder
= true;
8723 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8724 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8725 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8727 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8731 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8732 struct intel_crtc_state
*pipe_config
)
8734 struct drm_device
*dev
= crtc
->base
.dev
;
8735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8736 enum intel_display_power_domain pfit_domain
;
8739 if (!intel_display_power_is_enabled(dev_priv
,
8740 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8743 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8744 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8746 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8747 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8748 enum pipe trans_edp_pipe
;
8749 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8751 WARN(1, "unknown pipe linked to edp transcoder\n");
8752 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8753 case TRANS_DDI_EDP_INPUT_A_ON
:
8754 trans_edp_pipe
= PIPE_A
;
8756 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8757 trans_edp_pipe
= PIPE_B
;
8759 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8760 trans_edp_pipe
= PIPE_C
;
8764 if (trans_edp_pipe
== crtc
->pipe
)
8765 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8768 if (!intel_display_power_is_enabled(dev_priv
,
8769 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8772 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8773 if (!(tmp
& PIPECONF_ENABLE
))
8776 haswell_get_ddi_port_state(crtc
, pipe_config
);
8778 intel_get_pipe_timings(crtc
, pipe_config
);
8780 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8781 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
8782 if (IS_SKYLAKE(dev
))
8783 skylake_get_pfit_config(crtc
, pipe_config
);
8785 ironlake_get_pfit_config(crtc
, pipe_config
);
8788 if (IS_HASWELL(dev
))
8789 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8790 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8792 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8793 pipe_config
->pixel_multiplier
=
8794 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8796 pipe_config
->pixel_multiplier
= 1;
8802 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8804 struct drm_device
*dev
= crtc
->dev
;
8805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8807 uint32_t cntl
= 0, size
= 0;
8810 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
8811 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
8812 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8816 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8827 cntl
|= CURSOR_ENABLE
|
8828 CURSOR_GAMMA_ENABLE
|
8829 CURSOR_FORMAT_ARGB
|
8830 CURSOR_STRIDE(stride
);
8832 size
= (height
<< 12) | width
;
8835 if (intel_crtc
->cursor_cntl
!= 0 &&
8836 (intel_crtc
->cursor_base
!= base
||
8837 intel_crtc
->cursor_size
!= size
||
8838 intel_crtc
->cursor_cntl
!= cntl
)) {
8839 /* On these chipsets we can only modify the base/size/stride
8840 * whilst the cursor is disabled.
8842 I915_WRITE(_CURACNTR
, 0);
8843 POSTING_READ(_CURACNTR
);
8844 intel_crtc
->cursor_cntl
= 0;
8847 if (intel_crtc
->cursor_base
!= base
) {
8848 I915_WRITE(_CURABASE
, base
);
8849 intel_crtc
->cursor_base
= base
;
8852 if (intel_crtc
->cursor_size
!= size
) {
8853 I915_WRITE(CURSIZE
, size
);
8854 intel_crtc
->cursor_size
= size
;
8857 if (intel_crtc
->cursor_cntl
!= cntl
) {
8858 I915_WRITE(_CURACNTR
, cntl
);
8859 POSTING_READ(_CURACNTR
);
8860 intel_crtc
->cursor_cntl
= cntl
;
8864 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8866 struct drm_device
*dev
= crtc
->dev
;
8867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8868 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8869 int pipe
= intel_crtc
->pipe
;
8874 cntl
= MCURSOR_GAMMA_ENABLE
;
8875 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
8877 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8880 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8883 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8886 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
8889 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8891 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8892 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8895 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
8896 cntl
|= CURSOR_ROTATE_180
;
8898 if (intel_crtc
->cursor_cntl
!= cntl
) {
8899 I915_WRITE(CURCNTR(pipe
), cntl
);
8900 POSTING_READ(CURCNTR(pipe
));
8901 intel_crtc
->cursor_cntl
= cntl
;
8904 /* and commit changes on next vblank */
8905 I915_WRITE(CURBASE(pipe
), base
);
8906 POSTING_READ(CURBASE(pipe
));
8908 intel_crtc
->cursor_base
= base
;
8911 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8912 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8915 struct drm_device
*dev
= crtc
->dev
;
8916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8918 int pipe
= intel_crtc
->pipe
;
8919 int x
= crtc
->cursor_x
;
8920 int y
= crtc
->cursor_y
;
8921 u32 base
= 0, pos
= 0;
8924 base
= intel_crtc
->cursor_addr
;
8926 if (x
>= intel_crtc
->config
->pipe_src_w
)
8929 if (y
>= intel_crtc
->config
->pipe_src_h
)
8933 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
8936 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8939 pos
|= x
<< CURSOR_X_SHIFT
;
8942 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
8945 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8948 pos
|= y
<< CURSOR_Y_SHIFT
;
8950 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8953 I915_WRITE(CURPOS(pipe
), pos
);
8955 /* ILK+ do this automagically */
8956 if (HAS_GMCH_DISPLAY(dev
) &&
8957 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
8958 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
8959 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
8962 if (IS_845G(dev
) || IS_I865G(dev
))
8963 i845_update_cursor(crtc
, base
);
8965 i9xx_update_cursor(crtc
, base
);
8968 static bool cursor_size_ok(struct drm_device
*dev
,
8969 uint32_t width
, uint32_t height
)
8971 if (width
== 0 || height
== 0)
8975 * 845g/865g are special in that they are only limited by
8976 * the width of their cursors, the height is arbitrary up to
8977 * the precision of the register. Everything else requires
8978 * square cursors, limited to a few power-of-two sizes.
8980 if (IS_845G(dev
) || IS_I865G(dev
)) {
8981 if ((width
& 63) != 0)
8984 if (width
> (IS_845G(dev
) ? 64 : 512))
8990 switch (width
| height
) {
9005 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
9006 u16
*blue
, uint32_t start
, uint32_t size
)
9008 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
9009 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9011 for (i
= start
; i
< end
; i
++) {
9012 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
9013 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
9014 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
9017 intel_crtc_load_lut(crtc
);
9020 /* VESA 640x480x72Hz mode to set on the pipe */
9021 static struct drm_display_mode load_detect_mode
= {
9022 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
9023 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
9026 struct drm_framebuffer
*
9027 __intel_framebuffer_create(struct drm_device
*dev
,
9028 struct drm_mode_fb_cmd2
*mode_cmd
,
9029 struct drm_i915_gem_object
*obj
)
9031 struct intel_framebuffer
*intel_fb
;
9034 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9036 drm_gem_object_unreference(&obj
->base
);
9037 return ERR_PTR(-ENOMEM
);
9040 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
9044 return &intel_fb
->base
;
9046 drm_gem_object_unreference(&obj
->base
);
9049 return ERR_PTR(ret
);
9052 static struct drm_framebuffer
*
9053 intel_framebuffer_create(struct drm_device
*dev
,
9054 struct drm_mode_fb_cmd2
*mode_cmd
,
9055 struct drm_i915_gem_object
*obj
)
9057 struct drm_framebuffer
*fb
;
9060 ret
= i915_mutex_lock_interruptible(dev
);
9062 return ERR_PTR(ret
);
9063 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
9064 mutex_unlock(&dev
->struct_mutex
);
9070 intel_framebuffer_pitch_for_width(int width
, int bpp
)
9072 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
9073 return ALIGN(pitch
, 64);
9077 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
9079 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9080 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9083 static struct drm_framebuffer
*
9084 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9085 struct drm_display_mode
*mode
,
9088 struct drm_i915_gem_object
*obj
;
9089 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9091 obj
= i915_gem_alloc_object(dev
,
9092 intel_framebuffer_size_for_mode(mode
, bpp
));
9094 return ERR_PTR(-ENOMEM
);
9096 mode_cmd
.width
= mode
->hdisplay
;
9097 mode_cmd
.height
= mode
->vdisplay
;
9098 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9100 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9102 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
9105 static struct drm_framebuffer
*
9106 mode_fits_in_fbdev(struct drm_device
*dev
,
9107 struct drm_display_mode
*mode
)
9109 #ifdef CONFIG_DRM_I915_FBDEV
9110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9111 struct drm_i915_gem_object
*obj
;
9112 struct drm_framebuffer
*fb
;
9114 if (!dev_priv
->fbdev
)
9117 if (!dev_priv
->fbdev
->fb
)
9120 obj
= dev_priv
->fbdev
->fb
->obj
;
9123 fb
= &dev_priv
->fbdev
->fb
->base
;
9124 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9125 fb
->bits_per_pixel
))
9128 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9137 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
9138 struct drm_display_mode
*mode
,
9139 struct intel_load_detect_pipe
*old
,
9140 struct drm_modeset_acquire_ctx
*ctx
)
9142 struct intel_crtc
*intel_crtc
;
9143 struct intel_encoder
*intel_encoder
=
9144 intel_attached_encoder(connector
);
9145 struct drm_crtc
*possible_crtc
;
9146 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9147 struct drm_crtc
*crtc
= NULL
;
9148 struct drm_device
*dev
= encoder
->dev
;
9149 struct drm_framebuffer
*fb
;
9150 struct drm_mode_config
*config
= &dev
->mode_config
;
9151 struct drm_atomic_state
*state
= NULL
;
9152 struct drm_connector_state
*connector_state
;
9155 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9156 connector
->base
.id
, connector
->name
,
9157 encoder
->base
.id
, encoder
->name
);
9160 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
9165 * Algorithm gets a little messy:
9167 * - if the connector already has an assigned crtc, use it (but make
9168 * sure it's on first)
9170 * - try to find the first unused crtc that can drive this connector,
9171 * and use that if we find one
9174 /* See if we already have a CRTC for this connector */
9175 if (encoder
->crtc
) {
9176 crtc
= encoder
->crtc
;
9178 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9181 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9185 old
->dpms_mode
= connector
->dpms
;
9186 old
->load_detect_temp
= false;
9188 /* Make sure the crtc and connector are running */
9189 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
9190 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
9195 /* Find an unused one (if possible) */
9196 for_each_crtc(dev
, possible_crtc
) {
9198 if (!(encoder
->possible_crtcs
& (1 << i
)))
9200 if (possible_crtc
->state
->enable
)
9202 /* This can occur when applying the pipe A quirk on resume. */
9203 if (to_intel_crtc(possible_crtc
)->new_enabled
)
9206 crtc
= possible_crtc
;
9211 * If we didn't find an unused CRTC, don't use any.
9214 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9218 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9221 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9224 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
9225 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
9227 intel_crtc
= to_intel_crtc(crtc
);
9228 intel_crtc
->new_enabled
= true;
9229 old
->dpms_mode
= connector
->dpms
;
9230 old
->load_detect_temp
= true;
9231 old
->release_fb
= NULL
;
9233 state
= drm_atomic_state_alloc(dev
);
9237 state
->acquire_ctx
= ctx
;
9239 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9240 if (IS_ERR(connector_state
)) {
9241 ret
= PTR_ERR(connector_state
);
9245 connector_state
->crtc
= crtc
;
9246 connector_state
->best_encoder
= &intel_encoder
->base
;
9249 mode
= &load_detect_mode
;
9251 /* We need a framebuffer large enough to accommodate all accesses
9252 * that the plane may generate whilst we perform load detection.
9253 * We can not rely on the fbcon either being present (we get called
9254 * during its initialisation to detect all boot displays, or it may
9255 * not even exist) or that it is large enough to satisfy the
9258 fb
= mode_fits_in_fbdev(dev
, mode
);
9260 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9261 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
9262 old
->release_fb
= fb
;
9264 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9266 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9270 if (intel_set_mode(crtc
, mode
, 0, 0, fb
, state
)) {
9271 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9272 if (old
->release_fb
)
9273 old
->release_fb
->funcs
->destroy(old
->release_fb
);
9276 crtc
->primary
->crtc
= crtc
;
9278 /* let the connector get through one full cycle before testing */
9279 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
9283 intel_crtc
->new_enabled
= crtc
->state
->enable
;
9286 drm_atomic_state_free(state
);
9290 if (ret
== -EDEADLK
) {
9291 drm_modeset_backoff(ctx
);
9298 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
9299 struct intel_load_detect_pipe
*old
,
9300 struct drm_modeset_acquire_ctx
*ctx
)
9302 struct drm_device
*dev
= connector
->dev
;
9303 struct intel_encoder
*intel_encoder
=
9304 intel_attached_encoder(connector
);
9305 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9306 struct drm_crtc
*crtc
= encoder
->crtc
;
9307 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9308 struct drm_atomic_state
*state
;
9309 struct drm_connector_state
*connector_state
;
9311 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9312 connector
->base
.id
, connector
->name
,
9313 encoder
->base
.id
, encoder
->name
);
9315 if (old
->load_detect_temp
) {
9316 state
= drm_atomic_state_alloc(dev
);
9320 state
->acquire_ctx
= ctx
;
9322 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9323 if (IS_ERR(connector_state
))
9326 to_intel_connector(connector
)->new_encoder
= NULL
;
9327 intel_encoder
->new_crtc
= NULL
;
9328 intel_crtc
->new_enabled
= false;
9330 connector_state
->best_encoder
= NULL
;
9331 connector_state
->crtc
= NULL
;
9333 intel_set_mode(crtc
, NULL
, 0, 0, NULL
, state
);
9335 drm_atomic_state_free(state
);
9337 if (old
->release_fb
) {
9338 drm_framebuffer_unregister_private(old
->release_fb
);
9339 drm_framebuffer_unreference(old
->release_fb
);
9345 /* Switch crtc and encoder back off if necessary */
9346 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
9347 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
9351 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9352 drm_atomic_state_free(state
);
9355 static int i9xx_pll_refclk(struct drm_device
*dev
,
9356 const struct intel_crtc_state
*pipe_config
)
9358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9359 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9361 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
9362 return dev_priv
->vbt
.lvds_ssc_freq
;
9363 else if (HAS_PCH_SPLIT(dev
))
9365 else if (!IS_GEN2(dev
))
9371 /* Returns the clock of the currently programmed mode of the given pipe. */
9372 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
9373 struct intel_crtc_state
*pipe_config
)
9375 struct drm_device
*dev
= crtc
->base
.dev
;
9376 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9377 int pipe
= pipe_config
->cpu_transcoder
;
9378 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9380 intel_clock_t clock
;
9381 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
9383 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
9384 fp
= pipe_config
->dpll_hw_state
.fp0
;
9386 fp
= pipe_config
->dpll_hw_state
.fp1
;
9388 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
9389 if (IS_PINEVIEW(dev
)) {
9390 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
9391 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
9393 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
9394 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
9397 if (!IS_GEN2(dev
)) {
9398 if (IS_PINEVIEW(dev
))
9399 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
9400 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
9402 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
9403 DPLL_FPA01_P1_POST_DIV_SHIFT
);
9405 switch (dpll
& DPLL_MODE_MASK
) {
9406 case DPLLB_MODE_DAC_SERIAL
:
9407 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
9410 case DPLLB_MODE_LVDS
:
9411 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
9415 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9416 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
9420 if (IS_PINEVIEW(dev
))
9421 pineview_clock(refclk
, &clock
);
9423 i9xx_clock(refclk
, &clock
);
9425 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
9426 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
9429 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
9430 DPLL_FPA01_P1_POST_DIV_SHIFT
);
9432 if (lvds
& LVDS_CLKB_POWER_UP
)
9437 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
9440 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
9441 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
9443 if (dpll
& PLL_P2_DIVIDE_BY_4
)
9449 i9xx_clock(refclk
, &clock
);
9453 * This value includes pixel_multiplier. We will use
9454 * port_clock to compute adjusted_mode.crtc_clock in the
9455 * encoder's get_config() function.
9457 pipe_config
->port_clock
= clock
.dot
;
9460 int intel_dotclock_calculate(int link_freq
,
9461 const struct intel_link_m_n
*m_n
)
9464 * The calculation for the data clock is:
9465 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9466 * But we want to avoid losing precison if possible, so:
9467 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9469 * and the link clock is simpler:
9470 * link_clock = (m * link_clock) / n
9476 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
9479 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
9480 struct intel_crtc_state
*pipe_config
)
9482 struct drm_device
*dev
= crtc
->base
.dev
;
9484 /* read out port_clock from the DPLL */
9485 i9xx_crtc_clock_get(crtc
, pipe_config
);
9488 * This value does not include pixel_multiplier.
9489 * We will check that port_clock and adjusted_mode.crtc_clock
9490 * agree once we know their relationship in the encoder's
9491 * get_config() function.
9493 pipe_config
->base
.adjusted_mode
.crtc_clock
=
9494 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
9495 &pipe_config
->fdi_m_n
);
9498 /** Returns the currently programmed mode of the given pipe. */
9499 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
9500 struct drm_crtc
*crtc
)
9502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9503 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9504 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
9505 struct drm_display_mode
*mode
;
9506 struct intel_crtc_state pipe_config
;
9507 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
9508 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
9509 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
9510 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
9511 enum pipe pipe
= intel_crtc
->pipe
;
9513 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
9518 * Construct a pipe_config sufficient for getting the clock info
9519 * back out of crtc_clock_get.
9521 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9522 * to use a real value here instead.
9524 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
9525 pipe_config
.pixel_multiplier
= 1;
9526 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
9527 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
9528 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
9529 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
9531 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
9532 mode
->hdisplay
= (htot
& 0xffff) + 1;
9533 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
9534 mode
->hsync_start
= (hsync
& 0xffff) + 1;
9535 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
9536 mode
->vdisplay
= (vtot
& 0xffff) + 1;
9537 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
9538 mode
->vsync_start
= (vsync
& 0xffff) + 1;
9539 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
9541 drm_mode_set_name(mode
);
9546 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
9548 struct drm_device
*dev
= crtc
->dev
;
9549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9550 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9552 if (!HAS_GMCH_DISPLAY(dev
))
9555 if (!dev_priv
->lvds_downclock_avail
)
9559 * Since this is called by a timer, we should never get here in
9562 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9563 int pipe
= intel_crtc
->pipe
;
9564 int dpll_reg
= DPLL(pipe
);
9567 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9569 assert_panel_unlocked(dev_priv
, pipe
);
9571 dpll
= I915_READ(dpll_reg
);
9572 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9573 I915_WRITE(dpll_reg
, dpll
);
9574 intel_wait_for_vblank(dev
, pipe
);
9575 dpll
= I915_READ(dpll_reg
);
9576 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9577 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9582 void intel_mark_busy(struct drm_device
*dev
)
9584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9586 if (dev_priv
->mm
.busy
)
9589 intel_runtime_pm_get(dev_priv
);
9590 i915_update_gfx_val(dev_priv
);
9591 if (INTEL_INFO(dev
)->gen
>= 6)
9592 gen6_rps_busy(dev_priv
);
9593 dev_priv
->mm
.busy
= true;
9596 void intel_mark_idle(struct drm_device
*dev
)
9598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9599 struct drm_crtc
*crtc
;
9601 if (!dev_priv
->mm
.busy
)
9604 dev_priv
->mm
.busy
= false;
9606 for_each_crtc(dev
, crtc
) {
9607 if (!crtc
->primary
->fb
)
9610 intel_decrease_pllclock(crtc
);
9613 if (INTEL_INFO(dev
)->gen
>= 6)
9614 gen6_rps_idle(dev
->dev_private
);
9616 intel_runtime_pm_put(dev_priv
);
9619 static void intel_crtc_set_state(struct intel_crtc
*crtc
,
9620 struct intel_crtc_state
*crtc_state
)
9622 kfree(crtc
->config
);
9623 crtc
->config
= crtc_state
;
9624 crtc
->base
.state
= &crtc_state
->base
;
9627 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9629 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9630 struct drm_device
*dev
= crtc
->dev
;
9631 struct intel_unpin_work
*work
;
9633 spin_lock_irq(&dev
->event_lock
);
9634 work
= intel_crtc
->unpin_work
;
9635 intel_crtc
->unpin_work
= NULL
;
9636 spin_unlock_irq(&dev
->event_lock
);
9639 cancel_work_sync(&work
->work
);
9643 intel_crtc_set_state(intel_crtc
, NULL
);
9644 drm_crtc_cleanup(crtc
);
9649 static void intel_unpin_work_fn(struct work_struct
*__work
)
9651 struct intel_unpin_work
*work
=
9652 container_of(__work
, struct intel_unpin_work
, work
);
9653 struct drm_device
*dev
= work
->crtc
->dev
;
9654 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9656 mutex_lock(&dev
->struct_mutex
);
9657 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
9658 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9660 intel_fbc_update(dev
);
9662 if (work
->flip_queued_req
)
9663 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
9664 mutex_unlock(&dev
->struct_mutex
);
9666 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9667 drm_framebuffer_unreference(work
->old_fb
);
9669 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9670 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9675 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9676 struct drm_crtc
*crtc
)
9678 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9679 struct intel_unpin_work
*work
;
9680 unsigned long flags
;
9682 /* Ignore early vblank irqs */
9683 if (intel_crtc
== NULL
)
9687 * This is called both by irq handlers and the reset code (to complete
9688 * lost pageflips) so needs the full irqsave spinlocks.
9690 spin_lock_irqsave(&dev
->event_lock
, flags
);
9691 work
= intel_crtc
->unpin_work
;
9693 /* Ensure we don't miss a work->pending update ... */
9696 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9697 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9701 page_flip_completed(intel_crtc
);
9703 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9706 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9709 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9711 do_intel_finish_page_flip(dev
, crtc
);
9714 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9717 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9719 do_intel_finish_page_flip(dev
, crtc
);
9722 /* Is 'a' after or equal to 'b'? */
9723 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9725 return !((a
- b
) & 0x80000000);
9728 static bool page_flip_finished(struct intel_crtc
*crtc
)
9730 struct drm_device
*dev
= crtc
->base
.dev
;
9731 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9733 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
9734 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
9738 * The relevant registers doen't exist on pre-ctg.
9739 * As the flip done interrupt doesn't trigger for mmio
9740 * flips on gmch platforms, a flip count check isn't
9741 * really needed there. But since ctg has the registers,
9742 * include it in the check anyway.
9744 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9748 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9749 * used the same base address. In that case the mmio flip might
9750 * have completed, but the CS hasn't even executed the flip yet.
9752 * A flip count check isn't enough as the CS might have updated
9753 * the base address just after start of vblank, but before we
9754 * managed to process the interrupt. This means we'd complete the
9757 * Combining both checks should get us a good enough result. It may
9758 * still happen that the CS flip has been executed, but has not
9759 * yet actually completed. But in case the base address is the same
9760 * anyway, we don't really care.
9762 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9763 crtc
->unpin_work
->gtt_offset
&&
9764 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9765 crtc
->unpin_work
->flip_count
);
9768 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9771 struct intel_crtc
*intel_crtc
=
9772 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9773 unsigned long flags
;
9777 * This is called both by irq handlers and the reset code (to complete
9778 * lost pageflips) so needs the full irqsave spinlocks.
9780 * NB: An MMIO update of the plane base pointer will also
9781 * generate a page-flip completion irq, i.e. every modeset
9782 * is also accompanied by a spurious intel_prepare_page_flip().
9784 spin_lock_irqsave(&dev
->event_lock
, flags
);
9785 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9786 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9787 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9790 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9792 /* Ensure that the work item is consistent when activating it ... */
9794 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9795 /* and that it is marked active as soon as the irq could fire. */
9799 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9800 struct drm_crtc
*crtc
,
9801 struct drm_framebuffer
*fb
,
9802 struct drm_i915_gem_object
*obj
,
9803 struct intel_engine_cs
*ring
,
9806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9810 ret
= intel_ring_begin(ring
, 6);
9814 /* Can't queue multiple flips, so wait for the previous
9815 * one to finish before executing the next.
9817 if (intel_crtc
->plane
)
9818 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9820 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9821 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9822 intel_ring_emit(ring
, MI_NOOP
);
9823 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9824 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9825 intel_ring_emit(ring
, fb
->pitches
[0]);
9826 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9827 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9829 intel_mark_page_flip_active(intel_crtc
);
9830 __intel_ring_advance(ring
);
9834 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9835 struct drm_crtc
*crtc
,
9836 struct drm_framebuffer
*fb
,
9837 struct drm_i915_gem_object
*obj
,
9838 struct intel_engine_cs
*ring
,
9841 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9845 ret
= intel_ring_begin(ring
, 6);
9849 if (intel_crtc
->plane
)
9850 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9852 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9853 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9854 intel_ring_emit(ring
, MI_NOOP
);
9855 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9856 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9857 intel_ring_emit(ring
, fb
->pitches
[0]);
9858 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9859 intel_ring_emit(ring
, MI_NOOP
);
9861 intel_mark_page_flip_active(intel_crtc
);
9862 __intel_ring_advance(ring
);
9866 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9867 struct drm_crtc
*crtc
,
9868 struct drm_framebuffer
*fb
,
9869 struct drm_i915_gem_object
*obj
,
9870 struct intel_engine_cs
*ring
,
9873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9874 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9875 uint32_t pf
, pipesrc
;
9878 ret
= intel_ring_begin(ring
, 4);
9882 /* i965+ uses the linear or tiled offsets from the
9883 * Display Registers (which do not change across a page-flip)
9884 * so we need only reprogram the base address.
9886 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9887 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9888 intel_ring_emit(ring
, fb
->pitches
[0]);
9889 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9892 /* XXX Enabling the panel-fitter across page-flip is so far
9893 * untested on non-native modes, so ignore it for now.
9894 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9897 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9898 intel_ring_emit(ring
, pf
| pipesrc
);
9900 intel_mark_page_flip_active(intel_crtc
);
9901 __intel_ring_advance(ring
);
9905 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9906 struct drm_crtc
*crtc
,
9907 struct drm_framebuffer
*fb
,
9908 struct drm_i915_gem_object
*obj
,
9909 struct intel_engine_cs
*ring
,
9912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9913 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9914 uint32_t pf
, pipesrc
;
9917 ret
= intel_ring_begin(ring
, 4);
9921 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9922 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9923 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9924 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9926 /* Contrary to the suggestions in the documentation,
9927 * "Enable Panel Fitter" does not seem to be required when page
9928 * flipping with a non-native mode, and worse causes a normal
9930 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9933 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9934 intel_ring_emit(ring
, pf
| pipesrc
);
9936 intel_mark_page_flip_active(intel_crtc
);
9937 __intel_ring_advance(ring
);
9941 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9942 struct drm_crtc
*crtc
,
9943 struct drm_framebuffer
*fb
,
9944 struct drm_i915_gem_object
*obj
,
9945 struct intel_engine_cs
*ring
,
9948 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9949 uint32_t plane_bit
= 0;
9952 switch (intel_crtc
->plane
) {
9954 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9957 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9960 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9963 WARN_ONCE(1, "unknown plane in flip command\n");
9968 if (ring
->id
== RCS
) {
9971 * On Gen 8, SRM is now taking an extra dword to accommodate
9972 * 48bits addresses, and we need a NOOP for the batch size to
9980 * BSpec MI_DISPLAY_FLIP for IVB:
9981 * "The full packet must be contained within the same cache line."
9983 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9984 * cacheline, if we ever start emitting more commands before
9985 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9986 * then do the cacheline alignment, and finally emit the
9989 ret
= intel_ring_cacheline_align(ring
);
9993 ret
= intel_ring_begin(ring
, len
);
9997 /* Unmask the flip-done completion message. Note that the bspec says that
9998 * we should do this for both the BCS and RCS, and that we must not unmask
9999 * more than one flip event at any time (or ensure that one flip message
10000 * can be sent by waiting for flip-done prior to queueing new flips).
10001 * Experimentation says that BCS works despite DERRMR masking all
10002 * flip-done completion events and that unmasking all planes at once
10003 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10004 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10006 if (ring
->id
== RCS
) {
10007 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
10008 intel_ring_emit(ring
, DERRMR
);
10009 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
10010 DERRMR_PIPEB_PRI_FLIP_DONE
|
10011 DERRMR_PIPEC_PRI_FLIP_DONE
));
10013 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
10014 MI_SRM_LRM_GLOBAL_GTT
);
10016 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
10017 MI_SRM_LRM_GLOBAL_GTT
);
10018 intel_ring_emit(ring
, DERRMR
);
10019 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
10020 if (IS_GEN8(dev
)) {
10021 intel_ring_emit(ring
, 0);
10022 intel_ring_emit(ring
, MI_NOOP
);
10026 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
10027 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
10028 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10029 intel_ring_emit(ring
, (MI_NOOP
));
10031 intel_mark_page_flip_active(intel_crtc
);
10032 __intel_ring_advance(ring
);
10036 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
10037 struct drm_i915_gem_object
*obj
)
10040 * This is not being used for older platforms, because
10041 * non-availability of flip done interrupt forces us to use
10042 * CS flips. Older platforms derive flip done using some clever
10043 * tricks involving the flip_pending status bits and vblank irqs.
10044 * So using MMIO flips there would disrupt this mechanism.
10050 if (INTEL_INFO(ring
->dev
)->gen
< 5)
10053 if (i915
.use_mmio_flip
< 0)
10055 else if (i915
.use_mmio_flip
> 0)
10057 else if (i915
.enable_execlists
)
10060 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
10063 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10065 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10067 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
10068 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
10069 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10070 const enum pipe pipe
= intel_crtc
->pipe
;
10073 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
10074 ctl
&= ~PLANE_CTL_TILED_MASK
;
10075 if (obj
->tiling_mode
== I915_TILING_X
)
10076 ctl
|= PLANE_CTL_TILED_X
;
10079 * The stride is either expressed as a multiple of 64 bytes chunks for
10080 * linear buffers or in number of tiles for tiled buffers.
10082 stride
= fb
->pitches
[0] >> 6;
10083 if (obj
->tiling_mode
== I915_TILING_X
)
10084 stride
= fb
->pitches
[0] >> 9; /* X tiles are 512 bytes wide */
10087 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10088 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10090 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
10091 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
10093 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
10094 POSTING_READ(PLANE_SURF(pipe
, 0));
10097 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10099 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10101 struct intel_framebuffer
*intel_fb
=
10102 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
10103 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10107 reg
= DSPCNTR(intel_crtc
->plane
);
10108 dspcntr
= I915_READ(reg
);
10110 if (obj
->tiling_mode
!= I915_TILING_NONE
)
10111 dspcntr
|= DISPPLANE_TILED
;
10113 dspcntr
&= ~DISPPLANE_TILED
;
10115 I915_WRITE(reg
, dspcntr
);
10117 I915_WRITE(DSPSURF(intel_crtc
->plane
),
10118 intel_crtc
->unpin_work
->gtt_offset
);
10119 POSTING_READ(DSPSURF(intel_crtc
->plane
));
10124 * XXX: This is the temporary way to update the plane registers until we get
10125 * around to using the usual plane update functions for MMIO flips
10127 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10129 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10130 bool atomic_update
;
10131 u32 start_vbl_count
;
10133 intel_mark_page_flip_active(intel_crtc
);
10135 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
10137 if (INTEL_INFO(dev
)->gen
>= 9)
10138 skl_do_mmio_flip(intel_crtc
);
10140 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10141 ilk_do_mmio_flip(intel_crtc
);
10144 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
10147 static void intel_mmio_flip_work_func(struct work_struct
*work
)
10149 struct intel_crtc
*crtc
=
10150 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
10151 struct intel_mmio_flip
*mmio_flip
;
10153 mmio_flip
= &crtc
->mmio_flip
;
10154 if (mmio_flip
->req
)
10155 WARN_ON(__i915_wait_request(mmio_flip
->req
,
10156 crtc
->reset_counter
,
10157 false, NULL
, NULL
) != 0);
10159 intel_do_mmio_flip(crtc
);
10160 if (mmio_flip
->req
) {
10161 mutex_lock(&crtc
->base
.dev
->struct_mutex
);
10162 i915_gem_request_assign(&mmio_flip
->req
, NULL
);
10163 mutex_unlock(&crtc
->base
.dev
->struct_mutex
);
10167 static int intel_queue_mmio_flip(struct drm_device
*dev
,
10168 struct drm_crtc
*crtc
,
10169 struct drm_framebuffer
*fb
,
10170 struct drm_i915_gem_object
*obj
,
10171 struct intel_engine_cs
*ring
,
10174 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10176 i915_gem_request_assign(&intel_crtc
->mmio_flip
.req
,
10177 obj
->last_write_req
);
10179 schedule_work(&intel_crtc
->mmio_flip
.work
);
10184 static int intel_default_queue_flip(struct drm_device
*dev
,
10185 struct drm_crtc
*crtc
,
10186 struct drm_framebuffer
*fb
,
10187 struct drm_i915_gem_object
*obj
,
10188 struct intel_engine_cs
*ring
,
10194 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
10195 struct drm_crtc
*crtc
)
10197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10199 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
10202 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
10205 if (!work
->enable_stall_check
)
10208 if (work
->flip_ready_vblank
== 0) {
10209 if (work
->flip_queued_req
&&
10210 !i915_gem_request_completed(work
->flip_queued_req
, true))
10213 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
10216 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
10219 /* Potential stall - if we see that the flip has happened,
10220 * assume a missed interrupt. */
10221 if (INTEL_INFO(dev
)->gen
>= 4)
10222 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
10224 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
10226 /* There is a potential issue here with a false positive after a flip
10227 * to the same address. We could address this by checking for a
10228 * non-incrementing frame counter.
10230 return addr
== work
->gtt_offset
;
10233 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
10235 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10236 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10237 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10238 struct intel_unpin_work
*work
;
10240 WARN_ON(!in_interrupt());
10245 spin_lock(&dev
->event_lock
);
10246 work
= intel_crtc
->unpin_work
;
10247 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
10248 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10249 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
10250 page_flip_completed(intel_crtc
);
10253 if (work
!= NULL
&&
10254 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
10255 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
10256 spin_unlock(&dev
->event_lock
);
10259 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
10260 struct drm_framebuffer
*fb
,
10261 struct drm_pending_vblank_event
*event
,
10262 uint32_t page_flip_flags
)
10264 struct drm_device
*dev
= crtc
->dev
;
10265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10266 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10267 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10268 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10269 struct drm_plane
*primary
= crtc
->primary
;
10270 enum pipe pipe
= intel_crtc
->pipe
;
10271 struct intel_unpin_work
*work
;
10272 struct intel_engine_cs
*ring
;
10277 * drm_mode_page_flip_ioctl() should already catch this, but double
10278 * check to be safe. In the future we may enable pageflipping from
10279 * a disabled primary plane.
10281 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
10284 /* Can't change pixel format via MI display flips. */
10285 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
10289 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10290 * Note that pitch changes could also affect these register.
10292 if (INTEL_INFO(dev
)->gen
> 3 &&
10293 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
10294 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
10297 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
10300 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
10304 work
->event
= event
;
10306 work
->old_fb
= old_fb
;
10307 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
10309 ret
= drm_crtc_vblank_get(crtc
);
10313 /* We borrow the event spin lock for protecting unpin_work */
10314 spin_lock_irq(&dev
->event_lock
);
10315 if (intel_crtc
->unpin_work
) {
10316 /* Before declaring the flip queue wedged, check if
10317 * the hardware completed the operation behind our backs.
10319 if (__intel_pageflip_stall_check(dev
, crtc
)) {
10320 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10321 page_flip_completed(intel_crtc
);
10323 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10324 spin_unlock_irq(&dev
->event_lock
);
10326 drm_crtc_vblank_put(crtc
);
10331 intel_crtc
->unpin_work
= work
;
10332 spin_unlock_irq(&dev
->event_lock
);
10334 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
10335 flush_workqueue(dev_priv
->wq
);
10337 /* Reference the objects for the scheduled work. */
10338 drm_framebuffer_reference(work
->old_fb
);
10339 drm_gem_object_reference(&obj
->base
);
10341 crtc
->primary
->fb
= fb
;
10342 update_state_fb(crtc
->primary
);
10344 work
->pending_flip_obj
= obj
;
10346 ret
= i915_mutex_lock_interruptible(dev
);
10350 atomic_inc(&intel_crtc
->unpin_work_count
);
10351 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
10353 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
10354 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
10356 if (IS_VALLEYVIEW(dev
)) {
10357 ring
= &dev_priv
->ring
[BCS
];
10358 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
10359 /* vlv: DISPLAY_FLIP fails to change tiling */
10361 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
10362 ring
= &dev_priv
->ring
[BCS
];
10363 } else if (INTEL_INFO(dev
)->gen
>= 7) {
10364 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
10365 if (ring
== NULL
|| ring
->id
!= RCS
)
10366 ring
= &dev_priv
->ring
[BCS
];
10368 ring
= &dev_priv
->ring
[RCS
];
10371 mmio_flip
= use_mmio_flip(ring
, obj
);
10373 /* When using CS flips, we want to emit semaphores between rings.
10374 * However, when using mmio flips we will create a task to do the
10375 * synchronisation, so all we want here is to pin the framebuffer
10376 * into the display plane and skip any waits.
10378 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
10379 crtc
->primary
->state
,
10380 mmio_flip
? i915_gem_request_get_ring(obj
->last_read_req
) : ring
);
10382 goto cleanup_pending
;
10384 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
10385 + intel_crtc
->dspaddr_offset
;
10388 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
10391 goto cleanup_unpin
;
10393 i915_gem_request_assign(&work
->flip_queued_req
,
10394 obj
->last_write_req
);
10396 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
10399 goto cleanup_unpin
;
10401 i915_gem_request_assign(&work
->flip_queued_req
,
10402 intel_ring_get_request(ring
));
10405 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
10406 work
->enable_stall_check
= true;
10408 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
10409 INTEL_FRONTBUFFER_PRIMARY(pipe
));
10411 intel_fbc_disable(dev
);
10412 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10413 mutex_unlock(&dev
->struct_mutex
);
10415 trace_i915_flip_request(intel_crtc
->plane
, obj
);
10420 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
10422 atomic_dec(&intel_crtc
->unpin_work_count
);
10423 mutex_unlock(&dev
->struct_mutex
);
10425 crtc
->primary
->fb
= old_fb
;
10426 update_state_fb(crtc
->primary
);
10428 drm_gem_object_unreference_unlocked(&obj
->base
);
10429 drm_framebuffer_unreference(work
->old_fb
);
10431 spin_lock_irq(&dev
->event_lock
);
10432 intel_crtc
->unpin_work
= NULL
;
10433 spin_unlock_irq(&dev
->event_lock
);
10435 drm_crtc_vblank_put(crtc
);
10441 ret
= intel_plane_restore(primary
);
10442 if (ret
== 0 && event
) {
10443 spin_lock_irq(&dev
->event_lock
);
10444 drm_send_vblank_event(dev
, pipe
, event
);
10445 spin_unlock_irq(&dev
->event_lock
);
10451 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
10452 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
10453 .load_lut
= intel_crtc_load_lut
,
10454 .atomic_begin
= intel_begin_crtc_commit
,
10455 .atomic_flush
= intel_finish_crtc_commit
,
10459 * intel_modeset_update_staged_output_state
10461 * Updates the staged output configuration state, e.g. after we've read out the
10462 * current hw state.
10464 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
10466 struct intel_crtc
*crtc
;
10467 struct intel_encoder
*encoder
;
10468 struct intel_connector
*connector
;
10470 for_each_intel_connector(dev
, connector
) {
10471 connector
->new_encoder
=
10472 to_intel_encoder(connector
->base
.encoder
);
10475 for_each_intel_encoder(dev
, encoder
) {
10476 encoder
->new_crtc
=
10477 to_intel_crtc(encoder
->base
.crtc
);
10480 for_each_intel_crtc(dev
, crtc
) {
10481 crtc
->new_enabled
= crtc
->base
.state
->enable
;
10485 /* Transitional helper to copy current connector/encoder state to
10486 * connector->state. This is needed so that code that is partially
10487 * converted to atomic does the right thing.
10489 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
10491 struct intel_connector
*connector
;
10493 for_each_intel_connector(dev
, connector
) {
10494 if (connector
->base
.encoder
) {
10495 connector
->base
.state
->best_encoder
=
10496 connector
->base
.encoder
;
10497 connector
->base
.state
->crtc
=
10498 connector
->base
.encoder
->crtc
;
10500 connector
->base
.state
->best_encoder
= NULL
;
10501 connector
->base
.state
->crtc
= NULL
;
10507 * intel_modeset_commit_output_state
10509 * This function copies the stage display pipe configuration to the real one.
10511 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
10513 struct intel_crtc
*crtc
;
10514 struct intel_encoder
*encoder
;
10515 struct intel_connector
*connector
;
10517 for_each_intel_connector(dev
, connector
) {
10518 connector
->base
.encoder
= &connector
->new_encoder
->base
;
10521 for_each_intel_encoder(dev
, encoder
) {
10522 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
10525 for_each_intel_crtc(dev
, crtc
) {
10526 crtc
->base
.state
->enable
= crtc
->new_enabled
;
10527 crtc
->base
.enabled
= crtc
->new_enabled
;
10530 intel_modeset_update_connector_atomic_state(dev
);
10534 connected_sink_compute_bpp(struct intel_connector
*connector
,
10535 struct intel_crtc_state
*pipe_config
)
10537 int bpp
= pipe_config
->pipe_bpp
;
10539 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10540 connector
->base
.base
.id
,
10541 connector
->base
.name
);
10543 /* Don't use an invalid EDID bpc value */
10544 if (connector
->base
.display_info
.bpc
&&
10545 connector
->base
.display_info
.bpc
* 3 < bpp
) {
10546 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10547 bpp
, connector
->base
.display_info
.bpc
*3);
10548 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
10551 /* Clamp bpp to 8 on screens without EDID 1.4 */
10552 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
10553 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10555 pipe_config
->pipe_bpp
= 24;
10560 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10561 struct drm_framebuffer
*fb
,
10562 struct intel_crtc_state
*pipe_config
)
10564 struct drm_device
*dev
= crtc
->base
.dev
;
10565 struct drm_atomic_state
*state
;
10566 struct intel_connector
*connector
;
10569 switch (fb
->pixel_format
) {
10570 case DRM_FORMAT_C8
:
10571 bpp
= 8*3; /* since we go through a colormap */
10573 case DRM_FORMAT_XRGB1555
:
10574 case DRM_FORMAT_ARGB1555
:
10575 /* checked in intel_framebuffer_init already */
10576 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10578 case DRM_FORMAT_RGB565
:
10579 bpp
= 6*3; /* min is 18bpp */
10581 case DRM_FORMAT_XBGR8888
:
10582 case DRM_FORMAT_ABGR8888
:
10583 /* checked in intel_framebuffer_init already */
10584 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10586 case DRM_FORMAT_XRGB8888
:
10587 case DRM_FORMAT_ARGB8888
:
10590 case DRM_FORMAT_XRGB2101010
:
10591 case DRM_FORMAT_ARGB2101010
:
10592 case DRM_FORMAT_XBGR2101010
:
10593 case DRM_FORMAT_ABGR2101010
:
10594 /* checked in intel_framebuffer_init already */
10595 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10599 /* TODO: gen4+ supports 16 bpc floating point, too. */
10601 DRM_DEBUG_KMS("unsupported depth\n");
10605 pipe_config
->pipe_bpp
= bpp
;
10607 state
= pipe_config
->base
.state
;
10609 /* Clamp display bpp to EDID value */
10610 for (i
= 0; i
< state
->num_connector
; i
++) {
10611 if (!state
->connectors
[i
])
10614 connector
= to_intel_connector(state
->connectors
[i
]);
10615 if (state
->connector_states
[i
]->crtc
!= &crtc
->base
)
10618 connected_sink_compute_bpp(connector
, pipe_config
);
10624 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10626 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10627 "type: 0x%x flags: 0x%x\n",
10629 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10630 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10631 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10632 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10635 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10636 struct intel_crtc_state
*pipe_config
,
10637 const char *context
)
10639 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10640 context
, pipe_name(crtc
->pipe
));
10642 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10643 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10644 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10645 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10646 pipe_config
->has_pch_encoder
,
10647 pipe_config
->fdi_lanes
,
10648 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10649 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10650 pipe_config
->fdi_m_n
.tu
);
10651 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10652 pipe_config
->has_dp_encoder
,
10653 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10654 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10655 pipe_config
->dp_m_n
.tu
);
10657 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10658 pipe_config
->has_dp_encoder
,
10659 pipe_config
->dp_m2_n2
.gmch_m
,
10660 pipe_config
->dp_m2_n2
.gmch_n
,
10661 pipe_config
->dp_m2_n2
.link_m
,
10662 pipe_config
->dp_m2_n2
.link_n
,
10663 pipe_config
->dp_m2_n2
.tu
);
10665 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10666 pipe_config
->has_audio
,
10667 pipe_config
->has_infoframe
);
10669 DRM_DEBUG_KMS("requested mode:\n");
10670 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
10671 DRM_DEBUG_KMS("adjusted mode:\n");
10672 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
10673 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
10674 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10675 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10676 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10677 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10678 pipe_config
->gmch_pfit
.control
,
10679 pipe_config
->gmch_pfit
.pgm_ratios
,
10680 pipe_config
->gmch_pfit
.lvds_border_bits
);
10681 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10682 pipe_config
->pch_pfit
.pos
,
10683 pipe_config
->pch_pfit
.size
,
10684 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10685 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10686 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10689 static bool encoders_cloneable(const struct intel_encoder
*a
,
10690 const struct intel_encoder
*b
)
10692 /* masks could be asymmetric, so check both ways */
10693 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10694 b
->cloneable
& (1 << a
->type
));
10697 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
10698 struct intel_crtc
*crtc
,
10699 struct intel_encoder
*encoder
)
10701 struct intel_encoder
*source_encoder
;
10702 struct drm_connector_state
*connector_state
;
10705 for (i
= 0; i
< state
->num_connector
; i
++) {
10706 if (!state
->connectors
[i
])
10709 connector_state
= state
->connector_states
[i
];
10710 if (connector_state
->crtc
!= &crtc
->base
)
10714 to_intel_encoder(connector_state
->best_encoder
);
10715 if (!encoders_cloneable(encoder
, source_encoder
))
10722 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
10723 struct intel_crtc
*crtc
)
10725 struct intel_encoder
*encoder
;
10726 struct drm_connector_state
*connector_state
;
10729 for (i
= 0; i
< state
->num_connector
; i
++) {
10730 if (!state
->connectors
[i
])
10733 connector_state
= state
->connector_states
[i
];
10734 if (connector_state
->crtc
!= &crtc
->base
)
10737 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10738 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
10745 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
10747 struct drm_device
*dev
= state
->dev
;
10748 struct intel_encoder
*encoder
;
10749 struct drm_connector_state
*connector_state
;
10750 unsigned int used_ports
= 0;
10754 * Walk the connector list instead of the encoder
10755 * list to detect the problem on ddi platforms
10756 * where there's just one encoder per digital port.
10758 for (i
= 0; i
< state
->num_connector
; i
++) {
10759 if (!state
->connectors
[i
])
10762 connector_state
= state
->connector_states
[i
];
10763 if (!connector_state
->best_encoder
)
10766 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10768 WARN_ON(!connector_state
->crtc
);
10770 switch (encoder
->type
) {
10771 unsigned int port_mask
;
10772 case INTEL_OUTPUT_UNKNOWN
:
10773 if (WARN_ON(!HAS_DDI(dev
)))
10775 case INTEL_OUTPUT_DISPLAYPORT
:
10776 case INTEL_OUTPUT_HDMI
:
10777 case INTEL_OUTPUT_EDP
:
10778 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10780 /* the same port mustn't appear more than once */
10781 if (used_ports
& port_mask
)
10784 used_ports
|= port_mask
;
10794 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
10796 struct drm_crtc_state tmp_state
;
10798 /* Clear only the intel specific part of the crtc state */
10799 tmp_state
= crtc_state
->base
;
10800 memset(crtc_state
, 0, sizeof *crtc_state
);
10801 crtc_state
->base
= tmp_state
;
10804 static struct intel_crtc_state
*
10805 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10806 struct drm_framebuffer
*fb
,
10807 struct drm_display_mode
*mode
,
10808 struct drm_atomic_state
*state
)
10810 struct intel_encoder
*encoder
;
10811 struct intel_connector
*connector
;
10812 struct drm_connector_state
*connector_state
;
10813 struct intel_crtc_state
*pipe_config
;
10814 int plane_bpp
, ret
= -EINVAL
;
10818 if (!check_encoder_cloning(state
, to_intel_crtc(crtc
))) {
10819 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10820 return ERR_PTR(-EINVAL
);
10823 if (!check_digital_port_conflicts(state
)) {
10824 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10825 return ERR_PTR(-EINVAL
);
10828 pipe_config
= intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));
10829 if (IS_ERR(pipe_config
))
10830 return pipe_config
;
10832 clear_intel_crtc_state(pipe_config
);
10834 pipe_config
->base
.crtc
= crtc
;
10835 drm_mode_copy(&pipe_config
->base
.adjusted_mode
, mode
);
10836 drm_mode_copy(&pipe_config
->base
.mode
, mode
);
10838 pipe_config
->cpu_transcoder
=
10839 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10840 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10843 * Sanitize sync polarity flags based on requested ones. If neither
10844 * positive or negative polarity is requested, treat this as meaning
10845 * negative polarity.
10847 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10848 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10849 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10851 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10852 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10853 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10855 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10856 * plane pixel format and any sink constraints into account. Returns the
10857 * source plane bpp so that dithering can be selected on mismatches
10858 * after encoders and crtc also have had their say. */
10859 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10865 * Determine the real pipe dimensions. Note that stereo modes can
10866 * increase the actual pipe size due to the frame doubling and
10867 * insertion of additional space for blanks between the frame. This
10868 * is stored in the crtc timings. We use the requested mode to do this
10869 * computation to clearly distinguish it from the adjusted mode, which
10870 * can be changed by the connectors in the below retry loop.
10872 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
10873 &pipe_config
->pipe_src_w
,
10874 &pipe_config
->pipe_src_h
);
10877 /* Ensure the port clock defaults are reset when retrying. */
10878 pipe_config
->port_clock
= 0;
10879 pipe_config
->pixel_multiplier
= 1;
10881 /* Fill in default crtc timings, allow encoders to overwrite them. */
10882 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
10883 CRTC_STEREO_DOUBLE
);
10885 /* Pass our mode to the connectors and the CRTC to give them a chance to
10886 * adjust it according to limitations or connector properties, and also
10887 * a chance to reject the mode entirely.
10889 for (i
= 0; i
< state
->num_connector
; i
++) {
10890 connector
= to_intel_connector(state
->connectors
[i
]);
10894 connector_state
= state
->connector_states
[i
];
10895 if (connector_state
->crtc
!= crtc
)
10898 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10900 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10901 DRM_DEBUG_KMS("Encoder config failure\n");
10906 /* Set default port clock if not overwritten by the encoder. Needs to be
10907 * done afterwards in case the encoder adjusts the mode. */
10908 if (!pipe_config
->port_clock
)
10909 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
10910 * pipe_config
->pixel_multiplier
;
10912 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10914 DRM_DEBUG_KMS("CRTC fixup failed\n");
10918 if (ret
== RETRY
) {
10919 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10924 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10926 goto encoder_retry
;
10929 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10930 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10931 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10933 return pipe_config
;
10935 return ERR_PTR(ret
);
10938 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10939 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10941 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10942 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10944 struct intel_crtc
*intel_crtc
;
10945 struct drm_device
*dev
= crtc
->dev
;
10946 struct intel_encoder
*encoder
;
10947 struct intel_connector
*connector
;
10948 struct drm_crtc
*tmp_crtc
;
10950 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10952 /* Check which crtcs have changed outputs connected to them, these need
10953 * to be part of the prepare_pipes mask. We don't (yet) support global
10954 * modeset across multiple crtcs, so modeset_pipes will only have one
10955 * bit set at most. */
10956 for_each_intel_connector(dev
, connector
) {
10957 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10960 if (connector
->base
.encoder
) {
10961 tmp_crtc
= connector
->base
.encoder
->crtc
;
10963 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10966 if (connector
->new_encoder
)
10968 1 << connector
->new_encoder
->new_crtc
->pipe
;
10971 for_each_intel_encoder(dev
, encoder
) {
10972 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10975 if (encoder
->base
.crtc
) {
10976 tmp_crtc
= encoder
->base
.crtc
;
10978 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10981 if (encoder
->new_crtc
)
10982 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10985 /* Check for pipes that will be enabled/disabled ... */
10986 for_each_intel_crtc(dev
, intel_crtc
) {
10987 if (intel_crtc
->base
.state
->enable
== intel_crtc
->new_enabled
)
10990 if (!intel_crtc
->new_enabled
)
10991 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10993 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10997 /* set_mode is also used to update properties on life display pipes. */
10998 intel_crtc
= to_intel_crtc(crtc
);
10999 if (intel_crtc
->new_enabled
)
11000 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
11003 * For simplicity do a full modeset on any pipe where the output routing
11004 * changed. We could be more clever, but that would require us to be
11005 * more careful with calling the relevant encoder->mode_set functions.
11007 if (*prepare_pipes
)
11008 *modeset_pipes
= *prepare_pipes
;
11010 /* ... and mask these out. */
11011 *modeset_pipes
&= ~(*disable_pipes
);
11012 *prepare_pipes
&= ~(*disable_pipes
);
11015 * HACK: We don't (yet) fully support global modesets. intel_set_config
11016 * obies this rule, but the modeset restore mode of
11017 * intel_modeset_setup_hw_state does not.
11019 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
11020 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
11022 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11023 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
11026 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
11028 struct drm_encoder
*encoder
;
11029 struct drm_device
*dev
= crtc
->dev
;
11031 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
11032 if (encoder
->crtc
== crtc
)
11039 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
11041 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11042 struct intel_encoder
*intel_encoder
;
11043 struct intel_crtc
*intel_crtc
;
11044 struct drm_connector
*connector
;
11046 intel_shared_dpll_commit(dev_priv
);
11048 for_each_intel_encoder(dev
, intel_encoder
) {
11049 if (!intel_encoder
->base
.crtc
)
11052 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
11054 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
11055 intel_encoder
->connectors_active
= false;
11058 intel_modeset_commit_output_state(dev
);
11060 /* Double check state. */
11061 for_each_intel_crtc(dev
, intel_crtc
) {
11062 WARN_ON(intel_crtc
->base
.state
->enable
!= intel_crtc_in_use(&intel_crtc
->base
));
11065 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11066 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
11069 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
11071 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
11072 struct drm_property
*dpms_property
=
11073 dev
->mode_config
.dpms_property
;
11075 connector
->dpms
= DRM_MODE_DPMS_ON
;
11076 drm_object_property_set_value(&connector
->base
,
11080 intel_encoder
= to_intel_encoder(connector
->encoder
);
11081 intel_encoder
->connectors_active
= true;
11087 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
11091 if (clock1
== clock2
)
11094 if (!clock1
|| !clock2
)
11097 diff
= abs(clock1
- clock2
);
11099 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11105 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11106 list_for_each_entry((intel_crtc), \
11107 &(dev)->mode_config.crtc_list, \
11109 if (mask & (1 <<(intel_crtc)->pipe))
11112 intel_pipe_config_compare(struct drm_device
*dev
,
11113 struct intel_crtc_state
*current_config
,
11114 struct intel_crtc_state
*pipe_config
)
11116 #define PIPE_CONF_CHECK_X(name) \
11117 if (current_config->name != pipe_config->name) { \
11118 DRM_ERROR("mismatch in " #name " " \
11119 "(expected 0x%08x, found 0x%08x)\n", \
11120 current_config->name, \
11121 pipe_config->name); \
11125 #define PIPE_CONF_CHECK_I(name) \
11126 if (current_config->name != pipe_config->name) { \
11127 DRM_ERROR("mismatch in " #name " " \
11128 "(expected %i, found %i)\n", \
11129 current_config->name, \
11130 pipe_config->name); \
11134 /* This is required for BDW+ where there is only one set of registers for
11135 * switching between high and low RR.
11136 * This macro can be used whenever a comparison has to be made between one
11137 * hw state and multiple sw state variables.
11139 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11140 if ((current_config->name != pipe_config->name) && \
11141 (current_config->alt_name != pipe_config->name)) { \
11142 DRM_ERROR("mismatch in " #name " " \
11143 "(expected %i or %i, found %i)\n", \
11144 current_config->name, \
11145 current_config->alt_name, \
11146 pipe_config->name); \
11150 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11151 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11152 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11153 "(expected %i, found %i)\n", \
11154 current_config->name & (mask), \
11155 pipe_config->name & (mask)); \
11159 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11160 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11161 DRM_ERROR("mismatch in " #name " " \
11162 "(expected %i, found %i)\n", \
11163 current_config->name, \
11164 pipe_config->name); \
11168 #define PIPE_CONF_QUIRK(quirk) \
11169 ((current_config->quirks | pipe_config->quirks) & (quirk))
11171 PIPE_CONF_CHECK_I(cpu_transcoder
);
11173 PIPE_CONF_CHECK_I(has_pch_encoder
);
11174 PIPE_CONF_CHECK_I(fdi_lanes
);
11175 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
11176 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
11177 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
11178 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
11179 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
11181 PIPE_CONF_CHECK_I(has_dp_encoder
);
11183 if (INTEL_INFO(dev
)->gen
< 8) {
11184 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
11185 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
11186 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
11187 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
11188 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
11190 if (current_config
->has_drrs
) {
11191 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
11192 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
11193 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
11194 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
11195 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
11198 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
11199 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
11200 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
11201 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
11202 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
11205 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
11206 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
11207 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
11208 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
11209 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
11210 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
11212 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
11213 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
11214 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
11215 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
11216 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
11217 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
11219 PIPE_CONF_CHECK_I(pixel_multiplier
);
11220 PIPE_CONF_CHECK_I(has_hdmi_sink
);
11221 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
11222 IS_VALLEYVIEW(dev
))
11223 PIPE_CONF_CHECK_I(limited_color_range
);
11224 PIPE_CONF_CHECK_I(has_infoframe
);
11226 PIPE_CONF_CHECK_I(has_audio
);
11228 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11229 DRM_MODE_FLAG_INTERLACE
);
11231 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
11232 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11233 DRM_MODE_FLAG_PHSYNC
);
11234 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11235 DRM_MODE_FLAG_NHSYNC
);
11236 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11237 DRM_MODE_FLAG_PVSYNC
);
11238 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11239 DRM_MODE_FLAG_NVSYNC
);
11242 PIPE_CONF_CHECK_I(pipe_src_w
);
11243 PIPE_CONF_CHECK_I(pipe_src_h
);
11246 * FIXME: BIOS likes to set up a cloned config with lvds+external
11247 * screen. Since we don't yet re-compute the pipe config when moving
11248 * just the lvds port away to another pipe the sw tracking won't match.
11250 * Proper atomic modesets with recomputed global state will fix this.
11251 * Until then just don't check gmch state for inherited modes.
11253 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
11254 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
11255 /* pfit ratios are autocomputed by the hw on gen4+ */
11256 if (INTEL_INFO(dev
)->gen
< 4)
11257 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
11258 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
11261 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
11262 if (current_config
->pch_pfit
.enabled
) {
11263 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
11264 PIPE_CONF_CHECK_I(pch_pfit
.size
);
11267 /* BDW+ don't expose a synchronous way to read the state */
11268 if (IS_HASWELL(dev
))
11269 PIPE_CONF_CHECK_I(ips_enabled
);
11271 PIPE_CONF_CHECK_I(double_wide
);
11273 PIPE_CONF_CHECK_X(ddi_pll_sel
);
11275 PIPE_CONF_CHECK_I(shared_dpll
);
11276 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
11277 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
11278 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
11279 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
11280 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
11281 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
11282 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
11283 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
11285 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
11286 PIPE_CONF_CHECK_I(pipe_bpp
);
11288 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
11289 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
11291 #undef PIPE_CONF_CHECK_X
11292 #undef PIPE_CONF_CHECK_I
11293 #undef PIPE_CONF_CHECK_I_ALT
11294 #undef PIPE_CONF_CHECK_FLAGS
11295 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11296 #undef PIPE_CONF_QUIRK
11301 static void check_wm_state(struct drm_device
*dev
)
11303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11304 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
11305 struct intel_crtc
*intel_crtc
;
11308 if (INTEL_INFO(dev
)->gen
< 9)
11311 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
11312 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
11314 for_each_intel_crtc(dev
, intel_crtc
) {
11315 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
11316 const enum pipe pipe
= intel_crtc
->pipe
;
11318 if (!intel_crtc
->active
)
11322 for_each_plane(dev_priv
, pipe
, plane
) {
11323 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
11324 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
11326 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11329 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11330 "(expected (%u,%u), found (%u,%u))\n",
11331 pipe_name(pipe
), plane
+ 1,
11332 sw_entry
->start
, sw_entry
->end
,
11333 hw_entry
->start
, hw_entry
->end
);
11337 hw_entry
= &hw_ddb
.cursor
[pipe
];
11338 sw_entry
= &sw_ddb
->cursor
[pipe
];
11340 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11343 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11344 "(expected (%u,%u), found (%u,%u))\n",
11346 sw_entry
->start
, sw_entry
->end
,
11347 hw_entry
->start
, hw_entry
->end
);
11352 check_connector_state(struct drm_device
*dev
)
11354 struct intel_connector
*connector
;
11356 for_each_intel_connector(dev
, connector
) {
11357 /* This also checks the encoder/connector hw state with the
11358 * ->get_hw_state callbacks. */
11359 intel_connector_check_state(connector
);
11361 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
11362 "connector's staged encoder doesn't match current encoder\n");
11367 check_encoder_state(struct drm_device
*dev
)
11369 struct intel_encoder
*encoder
;
11370 struct intel_connector
*connector
;
11372 for_each_intel_encoder(dev
, encoder
) {
11373 bool enabled
= false;
11374 bool active
= false;
11375 enum pipe pipe
, tracked_pipe
;
11377 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11378 encoder
->base
.base
.id
,
11379 encoder
->base
.name
);
11381 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
11382 "encoder's stage crtc doesn't match current crtc\n");
11383 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
11384 "encoder's active_connectors set, but no crtc\n");
11386 for_each_intel_connector(dev
, connector
) {
11387 if (connector
->base
.encoder
!= &encoder
->base
)
11390 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
11394 * for MST connectors if we unplug the connector is gone
11395 * away but the encoder is still connected to a crtc
11396 * until a modeset happens in response to the hotplug.
11398 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
11401 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
11402 "encoder's enabled state mismatch "
11403 "(expected %i, found %i)\n",
11404 !!encoder
->base
.crtc
, enabled
);
11405 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
11406 "active encoder with no crtc\n");
11408 I915_STATE_WARN(encoder
->connectors_active
!= active
,
11409 "encoder's computed active state doesn't match tracked active state "
11410 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
11412 active
= encoder
->get_hw_state(encoder
, &pipe
);
11413 I915_STATE_WARN(active
!= encoder
->connectors_active
,
11414 "encoder's hw state doesn't match sw tracking "
11415 "(expected %i, found %i)\n",
11416 encoder
->connectors_active
, active
);
11418 if (!encoder
->base
.crtc
)
11421 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
11422 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
11423 "active encoder's pipe doesn't match"
11424 "(expected %i, found %i)\n",
11425 tracked_pipe
, pipe
);
11431 check_crtc_state(struct drm_device
*dev
)
11433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11434 struct intel_crtc
*crtc
;
11435 struct intel_encoder
*encoder
;
11436 struct intel_crtc_state pipe_config
;
11438 for_each_intel_crtc(dev
, crtc
) {
11439 bool enabled
= false;
11440 bool active
= false;
11442 memset(&pipe_config
, 0, sizeof(pipe_config
));
11444 DRM_DEBUG_KMS("[CRTC:%d]\n",
11445 crtc
->base
.base
.id
);
11447 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
11448 "active crtc, but not enabled in sw tracking\n");
11450 for_each_intel_encoder(dev
, encoder
) {
11451 if (encoder
->base
.crtc
!= &crtc
->base
)
11454 if (encoder
->connectors_active
)
11458 I915_STATE_WARN(active
!= crtc
->active
,
11459 "crtc's computed active state doesn't match tracked active state "
11460 "(expected %i, found %i)\n", active
, crtc
->active
);
11461 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
11462 "crtc's computed enabled state doesn't match tracked enabled state "
11463 "(expected %i, found %i)\n", enabled
,
11464 crtc
->base
.state
->enable
);
11466 active
= dev_priv
->display
.get_pipe_config(crtc
,
11469 /* hw state is inconsistent with the pipe quirk */
11470 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
11471 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
11472 active
= crtc
->active
;
11474 for_each_intel_encoder(dev
, encoder
) {
11476 if (encoder
->base
.crtc
!= &crtc
->base
)
11478 if (encoder
->get_hw_state(encoder
, &pipe
))
11479 encoder
->get_config(encoder
, &pipe_config
);
11482 I915_STATE_WARN(crtc
->active
!= active
,
11483 "crtc active state doesn't match with hw state "
11484 "(expected %i, found %i)\n", crtc
->active
, active
);
11487 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
11488 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11489 intel_dump_pipe_config(crtc
, &pipe_config
,
11491 intel_dump_pipe_config(crtc
, crtc
->config
,
11498 check_shared_dpll_state(struct drm_device
*dev
)
11500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11501 struct intel_crtc
*crtc
;
11502 struct intel_dpll_hw_state dpll_hw_state
;
11505 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11506 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11507 int enabled_crtcs
= 0, active_crtcs
= 0;
11510 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
11512 DRM_DEBUG_KMS("%s\n", pll
->name
);
11514 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
11516 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
11517 "more active pll users than references: %i vs %i\n",
11518 pll
->active
, hweight32(pll
->config
.crtc_mask
));
11519 I915_STATE_WARN(pll
->active
&& !pll
->on
,
11520 "pll in active use but not on in sw tracking\n");
11521 I915_STATE_WARN(pll
->on
&& !pll
->active
,
11522 "pll in on but not on in use in sw tracking\n");
11523 I915_STATE_WARN(pll
->on
!= active
,
11524 "pll on state mismatch (expected %i, found %i)\n",
11527 for_each_intel_crtc(dev
, crtc
) {
11528 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11530 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11533 I915_STATE_WARN(pll
->active
!= active_crtcs
,
11534 "pll active crtcs mismatch (expected %i, found %i)\n",
11535 pll
->active
, active_crtcs
);
11536 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
11537 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11538 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
11540 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
11541 sizeof(dpll_hw_state
)),
11542 "pll hw state mismatch\n");
11547 intel_modeset_check_state(struct drm_device
*dev
)
11549 check_wm_state(dev
);
11550 check_connector_state(dev
);
11551 check_encoder_state(dev
);
11552 check_crtc_state(dev
);
11553 check_shared_dpll_state(dev
);
11556 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
11560 * FDI already provided one idea for the dotclock.
11561 * Yell if the encoder disagrees.
11563 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
11564 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11565 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
11568 static void update_scanline_offset(struct intel_crtc
*crtc
)
11570 struct drm_device
*dev
= crtc
->base
.dev
;
11573 * The scanline counter increments at the leading edge of hsync.
11575 * On most platforms it starts counting from vtotal-1 on the
11576 * first active line. That means the scanline counter value is
11577 * always one less than what we would expect. Ie. just after
11578 * start of vblank, which also occurs at start of hsync (on the
11579 * last active line), the scanline counter will read vblank_start-1.
11581 * On gen2 the scanline counter starts counting from 1 instead
11582 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11583 * to keep the value positive), instead of adding one.
11585 * On HSW+ the behaviour of the scanline counter depends on the output
11586 * type. For DP ports it behaves like most other platforms, but on HDMI
11587 * there's an extra 1 line difference. So we need to add two instead of
11588 * one to the value.
11590 if (IS_GEN2(dev
)) {
11591 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
11594 vtotal
= mode
->crtc_vtotal
;
11595 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11598 crtc
->scanline_offset
= vtotal
- 1;
11599 } else if (HAS_DDI(dev
) &&
11600 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
11601 crtc
->scanline_offset
= 2;
11603 crtc
->scanline_offset
= 1;
11606 static struct intel_crtc_state
*
11607 intel_modeset_compute_config(struct drm_crtc
*crtc
,
11608 struct drm_display_mode
*mode
,
11609 struct drm_framebuffer
*fb
,
11610 struct drm_atomic_state
*state
,
11611 unsigned *modeset_pipes
,
11612 unsigned *prepare_pipes
,
11613 unsigned *disable_pipes
)
11615 struct drm_device
*dev
= crtc
->dev
;
11616 struct intel_crtc_state
*pipe_config
= NULL
;
11617 struct intel_crtc
*intel_crtc
;
11620 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
11622 return ERR_PTR(ret
);
11624 intel_modeset_affected_pipes(crtc
, modeset_pipes
,
11625 prepare_pipes
, disable_pipes
);
11627 for_each_intel_crtc_masked(dev
, *disable_pipes
, intel_crtc
) {
11628 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
11629 if (IS_ERR(pipe_config
))
11630 return pipe_config
;
11632 pipe_config
->base
.enable
= false;
11636 * Note this needs changes when we start tracking multiple modes
11637 * and crtcs. At that point we'll need to compute the whole config
11638 * (i.e. one pipe_config for each crtc) rather than just the one
11641 for_each_intel_crtc_masked(dev
, *modeset_pipes
, intel_crtc
) {
11642 /* FIXME: For now we still expect modeset_pipes has at most
11644 if (WARN_ON(&intel_crtc
->base
!= crtc
))
11647 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
, state
);
11648 if (IS_ERR(pipe_config
))
11649 return pipe_config
;
11651 pipe_config
->base
.enable
= true;
11653 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11657 return intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));;
11660 static int __intel_set_mode_setup_plls(struct drm_atomic_state
*state
,
11661 unsigned modeset_pipes
,
11662 unsigned disable_pipes
)
11664 struct drm_device
*dev
= state
->dev
;
11665 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11666 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
11667 struct intel_crtc
*intel_crtc
;
11670 if (!dev_priv
->display
.crtc_compute_clock
)
11673 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
11677 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11678 struct intel_crtc_state
*crtc_state
=
11679 intel_atomic_get_crtc_state(state
, intel_crtc
);
11681 /* Modeset pipes should have a new state by now */
11682 if (WARN_ON(IS_ERR(crtc_state
)))
11685 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11688 intel_shared_dpll_abort_config(dev_priv
);
11697 static int __intel_set_mode(struct drm_crtc
*crtc
,
11698 struct drm_display_mode
*mode
,
11699 int x
, int y
, struct drm_framebuffer
*fb
,
11700 struct intel_crtc_state
*pipe_config
,
11701 unsigned modeset_pipes
,
11702 unsigned prepare_pipes
,
11703 unsigned disable_pipes
)
11705 struct drm_device
*dev
= crtc
->dev
;
11706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11707 struct drm_display_mode
*saved_mode
;
11708 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
11709 struct intel_crtc_state
*crtc_state_copy
= NULL
;
11710 struct intel_crtc
*intel_crtc
;
11713 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11717 crtc_state_copy
= kmalloc(sizeof(*crtc_state_copy
), GFP_KERNEL
);
11718 if (!crtc_state_copy
) {
11723 *saved_mode
= crtc
->mode
;
11726 * See if the config requires any additional preparation, e.g.
11727 * to adjust global state with pipes off. We need to do this
11728 * here so we can get the modeset_pipe updated config for the new
11729 * mode set on this crtc. For other crtcs we need to use the
11730 * adjusted_mode bits in the crtc directly.
11732 if (IS_VALLEYVIEW(dev
)) {
11733 ret
= valleyview_modeset_global_pipes(state
, &prepare_pipes
);
11737 /* may have added more to prepare_pipes than we should */
11738 prepare_pipes
&= ~disable_pipes
;
11741 ret
= __intel_set_mode_setup_plls(state
, modeset_pipes
, disable_pipes
);
11745 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11746 intel_crtc_disable(&intel_crtc
->base
);
11748 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11749 if (intel_crtc
->base
.state
->enable
)
11750 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11753 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11754 * to set it here already despite that we pass it down the callchain.
11756 * Note we'll need to fix this up when we start tracking multiple
11757 * pipes; here we assume a single modeset_pipe and only track the
11758 * single crtc and mode.
11760 if (modeset_pipes
) {
11761 crtc
->mode
= *mode
;
11762 /* mode_set/enable/disable functions rely on a correct pipe
11764 intel_crtc_set_state(to_intel_crtc(crtc
), pipe_config
);
11767 * Calculate and store various constants which
11768 * are later needed by vblank and swap-completion
11769 * timestamping. They are derived from true hwmode.
11771 drm_calc_timestamping_constants(crtc
,
11772 &pipe_config
->base
.adjusted_mode
);
11775 /* Only after disabling all output pipelines that will be changed can we
11776 * update the the output configuration. */
11777 intel_modeset_update_state(dev
, prepare_pipes
);
11779 modeset_update_crtc_power_domains(state
);
11781 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11782 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
11783 int vdisplay
, hdisplay
;
11785 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
11786 ret
= drm_plane_helper_update(primary
, &intel_crtc
->base
,
11788 hdisplay
, vdisplay
,
11790 hdisplay
<< 16, vdisplay
<< 16);
11793 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11794 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11795 update_scanline_offset(intel_crtc
);
11797 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11800 /* FIXME: add subpixel order */
11802 if (ret
&& crtc
->state
->enable
)
11803 crtc
->mode
= *saved_mode
;
11805 if (ret
== 0 && pipe_config
) {
11806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11808 /* The pipe_config will be freed with the atomic state, so
11810 memcpy(crtc_state_copy
, intel_crtc
->config
,
11811 sizeof *crtc_state_copy
);
11812 intel_crtc
->config
= crtc_state_copy
;
11813 intel_crtc
->base
.state
= &crtc_state_copy
->base
;
11815 kfree(crtc_state_copy
);
11822 static int intel_set_mode_pipes(struct drm_crtc
*crtc
,
11823 struct drm_display_mode
*mode
,
11824 int x
, int y
, struct drm_framebuffer
*fb
,
11825 struct intel_crtc_state
*pipe_config
,
11826 unsigned modeset_pipes
,
11827 unsigned prepare_pipes
,
11828 unsigned disable_pipes
)
11832 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
, modeset_pipes
,
11833 prepare_pipes
, disable_pipes
);
11836 intel_modeset_check_state(crtc
->dev
);
11841 static int intel_set_mode(struct drm_crtc
*crtc
,
11842 struct drm_display_mode
*mode
,
11843 int x
, int y
, struct drm_framebuffer
*fb
,
11844 struct drm_atomic_state
*state
)
11846 struct intel_crtc_state
*pipe_config
;
11847 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11850 pipe_config
= intel_modeset_compute_config(crtc
, mode
, fb
, state
,
11855 if (IS_ERR(pipe_config
)) {
11856 ret
= PTR_ERR(pipe_config
);
11860 ret
= intel_set_mode_pipes(crtc
, mode
, x
, y
, fb
, pipe_config
,
11861 modeset_pipes
, prepare_pipes
,
11870 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11872 struct drm_device
*dev
= crtc
->dev
;
11873 struct drm_atomic_state
*state
;
11874 struct intel_encoder
*encoder
;
11875 struct intel_connector
*connector
;
11876 struct drm_connector_state
*connector_state
;
11878 state
= drm_atomic_state_alloc(dev
);
11880 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11885 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
11887 /* The force restore path in the HW readout code relies on the staged
11888 * config still keeping the user requested config while the actual
11889 * state has been overwritten by the configuration read from HW. We
11890 * need to copy the staged config to the atomic state, otherwise the
11891 * mode set will just reapply the state the HW is already in. */
11892 for_each_intel_encoder(dev
, encoder
) {
11893 if (&encoder
->new_crtc
->base
!= crtc
)
11896 for_each_intel_connector(dev
, connector
) {
11897 if (connector
->new_encoder
!= encoder
)
11900 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
11901 if (IS_ERR(connector_state
)) {
11902 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11903 connector
->base
.base
.id
,
11904 connector
->base
.name
,
11905 PTR_ERR(connector_state
));
11909 connector_state
->crtc
= crtc
;
11910 connector_state
->best_encoder
= &encoder
->base
;
11914 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
,
11917 drm_atomic_state_free(state
);
11920 #undef for_each_intel_crtc_masked
11922 static void intel_set_config_free(struct intel_set_config
*config
)
11927 kfree(config
->save_connector_encoders
);
11928 kfree(config
->save_encoder_crtcs
);
11929 kfree(config
->save_crtc_enabled
);
11933 static int intel_set_config_save_state(struct drm_device
*dev
,
11934 struct intel_set_config
*config
)
11936 struct drm_crtc
*crtc
;
11937 struct drm_encoder
*encoder
;
11938 struct drm_connector
*connector
;
11941 config
->save_crtc_enabled
=
11942 kcalloc(dev
->mode_config
.num_crtc
,
11943 sizeof(bool), GFP_KERNEL
);
11944 if (!config
->save_crtc_enabled
)
11947 config
->save_encoder_crtcs
=
11948 kcalloc(dev
->mode_config
.num_encoder
,
11949 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11950 if (!config
->save_encoder_crtcs
)
11953 config
->save_connector_encoders
=
11954 kcalloc(dev
->mode_config
.num_connector
,
11955 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11956 if (!config
->save_connector_encoders
)
11959 /* Copy data. Note that driver private data is not affected.
11960 * Should anything bad happen only the expected state is
11961 * restored, not the drivers personal bookkeeping.
11964 for_each_crtc(dev
, crtc
) {
11965 config
->save_crtc_enabled
[count
++] = crtc
->state
->enable
;
11969 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11970 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11974 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11975 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11981 static void intel_set_config_restore_state(struct drm_device
*dev
,
11982 struct intel_set_config
*config
)
11984 struct intel_crtc
*crtc
;
11985 struct intel_encoder
*encoder
;
11986 struct intel_connector
*connector
;
11990 for_each_intel_crtc(dev
, crtc
) {
11991 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11995 for_each_intel_encoder(dev
, encoder
) {
11996 encoder
->new_crtc
=
11997 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
12001 for_each_intel_connector(dev
, connector
) {
12002 connector
->new_encoder
=
12003 to_intel_encoder(config
->save_connector_encoders
[count
++]);
12008 is_crtc_connector_off(struct drm_mode_set
*set
)
12012 if (set
->num_connectors
== 0)
12015 if (WARN_ON(set
->connectors
== NULL
))
12018 for (i
= 0; i
< set
->num_connectors
; i
++)
12019 if (set
->connectors
[i
]->encoder
&&
12020 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
12021 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
12028 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
12029 struct intel_set_config
*config
)
12032 /* We should be able to check here if the fb has the same properties
12033 * and then just flip_or_move it */
12034 if (is_crtc_connector_off(set
)) {
12035 config
->mode_changed
= true;
12036 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
12038 * If we have no fb, we can only flip as long as the crtc is
12039 * active, otherwise we need a full mode set. The crtc may
12040 * be active if we've only disabled the primary plane, or
12041 * in fastboot situations.
12043 if (set
->crtc
->primary
->fb
== NULL
) {
12044 struct intel_crtc
*intel_crtc
=
12045 to_intel_crtc(set
->crtc
);
12047 if (intel_crtc
->active
) {
12048 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12049 config
->fb_changed
= true;
12051 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12052 config
->mode_changed
= true;
12054 } else if (set
->fb
== NULL
) {
12055 config
->mode_changed
= true;
12056 } else if (set
->fb
->pixel_format
!=
12057 set
->crtc
->primary
->fb
->pixel_format
) {
12058 config
->mode_changed
= true;
12060 config
->fb_changed
= true;
12064 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
12065 config
->fb_changed
= true;
12067 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
12068 DRM_DEBUG_KMS("modes are different, full mode set\n");
12069 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
12070 drm_mode_debug_printmodeline(set
->mode
);
12071 config
->mode_changed
= true;
12074 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12075 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
12079 intel_modeset_stage_output_state(struct drm_device
*dev
,
12080 struct drm_mode_set
*set
,
12081 struct intel_set_config
*config
,
12082 struct drm_atomic_state
*state
)
12084 struct intel_connector
*connector
;
12085 struct drm_connector_state
*connector_state
;
12086 struct intel_encoder
*encoder
;
12087 struct intel_crtc
*crtc
;
12090 /* The upper layers ensure that we either disable a crtc or have a list
12091 * of connectors. For paranoia, double-check this. */
12092 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
12093 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
12095 for_each_intel_connector(dev
, connector
) {
12096 /* Otherwise traverse passed in connector list and get encoders
12098 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
12099 if (set
->connectors
[ro
] == &connector
->base
) {
12100 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
12105 /* If we disable the crtc, disable all its connectors. Also, if
12106 * the connector is on the changing crtc but not on the new
12107 * connector list, disable it. */
12108 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
12109 connector
->base
.encoder
&&
12110 connector
->base
.encoder
->crtc
== set
->crtc
) {
12111 connector
->new_encoder
= NULL
;
12113 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12114 connector
->base
.base
.id
,
12115 connector
->base
.name
);
12119 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
12120 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12121 connector
->base
.base
.id
,
12122 connector
->base
.name
);
12123 config
->mode_changed
= true;
12126 /* connector->new_encoder is now updated for all connectors. */
12128 /* Update crtc of enabled connectors. */
12129 for_each_intel_connector(dev
, connector
) {
12130 struct drm_crtc
*new_crtc
;
12132 if (!connector
->new_encoder
)
12135 new_crtc
= connector
->new_encoder
->base
.crtc
;
12137 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
12138 if (set
->connectors
[ro
] == &connector
->base
)
12139 new_crtc
= set
->crtc
;
12142 /* Make sure the new CRTC will work with the encoder */
12143 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
12147 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
12150 drm_atomic_get_connector_state(state
, &connector
->base
);
12151 if (IS_ERR(connector_state
))
12152 return PTR_ERR(connector_state
);
12154 connector_state
->crtc
= new_crtc
;
12155 connector_state
->best_encoder
= &connector
->new_encoder
->base
;
12157 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12158 connector
->base
.base
.id
,
12159 connector
->base
.name
,
12160 new_crtc
->base
.id
);
12163 /* Check for any encoders that needs to be disabled. */
12164 for_each_intel_encoder(dev
, encoder
) {
12165 int num_connectors
= 0;
12166 for_each_intel_connector(dev
, connector
) {
12167 if (connector
->new_encoder
== encoder
) {
12168 WARN_ON(!connector
->new_encoder
->new_crtc
);
12173 if (num_connectors
== 0)
12174 encoder
->new_crtc
= NULL
;
12175 else if (num_connectors
> 1)
12178 /* Only now check for crtc changes so we don't miss encoders
12179 * that will be disabled. */
12180 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
12181 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12182 encoder
->base
.base
.id
,
12183 encoder
->base
.name
);
12184 config
->mode_changed
= true;
12187 /* Now we've also updated encoder->new_crtc for all encoders. */
12188 for_each_intel_connector(dev
, connector
) {
12190 drm_atomic_get_connector_state(state
, &connector
->base
);
12191 if (IS_ERR(connector_state
))
12192 return PTR_ERR(connector_state
);
12194 if (connector
->new_encoder
) {
12195 if (connector
->new_encoder
!= connector
->encoder
)
12196 connector
->encoder
= connector
->new_encoder
;
12198 connector_state
->crtc
= NULL
;
12199 connector_state
->best_encoder
= NULL
;
12202 for_each_intel_crtc(dev
, crtc
) {
12203 crtc
->new_enabled
= false;
12205 for_each_intel_encoder(dev
, encoder
) {
12206 if (encoder
->new_crtc
== crtc
) {
12207 crtc
->new_enabled
= true;
12212 if (crtc
->new_enabled
!= crtc
->base
.state
->enable
) {
12213 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12214 crtc
->base
.base
.id
,
12215 crtc
->new_enabled
? "en" : "dis");
12216 config
->mode_changed
= true;
12223 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
12225 struct drm_device
*dev
= crtc
->base
.dev
;
12226 struct intel_encoder
*encoder
;
12227 struct intel_connector
*connector
;
12229 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12230 pipe_name(crtc
->pipe
));
12232 for_each_intel_connector(dev
, connector
) {
12233 if (connector
->new_encoder
&&
12234 connector
->new_encoder
->new_crtc
== crtc
)
12235 connector
->new_encoder
= NULL
;
12238 for_each_intel_encoder(dev
, encoder
) {
12239 if (encoder
->new_crtc
== crtc
)
12240 encoder
->new_crtc
= NULL
;
12243 crtc
->new_enabled
= false;
12246 static int intel_crtc_set_config(struct drm_mode_set
*set
)
12248 struct drm_device
*dev
;
12249 struct drm_mode_set save_set
;
12250 struct drm_atomic_state
*state
= NULL
;
12251 struct intel_set_config
*config
;
12252 struct intel_crtc_state
*pipe_config
;
12253 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
12257 BUG_ON(!set
->crtc
);
12258 BUG_ON(!set
->crtc
->helper_private
);
12260 /* Enforce sane interface api - has been abused by the fb helper. */
12261 BUG_ON(!set
->mode
&& set
->fb
);
12262 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
12265 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12266 set
->crtc
->base
.id
, set
->fb
->base
.id
,
12267 (int)set
->num_connectors
, set
->x
, set
->y
);
12269 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
12272 dev
= set
->crtc
->dev
;
12275 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
12279 ret
= intel_set_config_save_state(dev
, config
);
12283 save_set
.crtc
= set
->crtc
;
12284 save_set
.mode
= &set
->crtc
->mode
;
12285 save_set
.x
= set
->crtc
->x
;
12286 save_set
.y
= set
->crtc
->y
;
12287 save_set
.fb
= set
->crtc
->primary
->fb
;
12289 /* Compute whether we need a full modeset, only an fb base update or no
12290 * change at all. In the future we might also check whether only the
12291 * mode changed, e.g. for LVDS where we only change the panel fitter in
12293 intel_set_config_compute_mode_changes(set
, config
);
12295 state
= drm_atomic_state_alloc(dev
);
12301 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12303 ret
= intel_modeset_stage_output_state(dev
, set
, config
, state
);
12307 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
12312 if (IS_ERR(pipe_config
)) {
12313 ret
= PTR_ERR(pipe_config
);
12315 } else if (pipe_config
) {
12316 if (pipe_config
->has_audio
!=
12317 to_intel_crtc(set
->crtc
)->config
->has_audio
)
12318 config
->mode_changed
= true;
12321 * Note we have an issue here with infoframes: current code
12322 * only updates them on the full mode set path per hw
12323 * requirements. So here we should be checking for any
12324 * required changes and forcing a mode set.
12328 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
12330 if (config
->mode_changed
) {
12331 ret
= intel_set_mode_pipes(set
->crtc
, set
->mode
,
12332 set
->x
, set
->y
, set
->fb
, pipe_config
,
12333 modeset_pipes
, prepare_pipes
,
12335 } else if (config
->fb_changed
) {
12336 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
12337 struct drm_plane
*primary
= set
->crtc
->primary
;
12338 int vdisplay
, hdisplay
;
12340 drm_crtc_get_hv_timing(set
->mode
, &hdisplay
, &vdisplay
);
12341 ret
= drm_plane_helper_update(primary
, set
->crtc
, set
->fb
,
12342 0, 0, hdisplay
, vdisplay
,
12343 set
->x
<< 16, set
->y
<< 16,
12344 hdisplay
<< 16, vdisplay
<< 16);
12347 * We need to make sure the primary plane is re-enabled if it
12348 * has previously been turned off.
12350 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
12351 WARN_ON(!intel_crtc
->active
);
12352 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
12356 * In the fastboot case this may be our only check of the
12357 * state after boot. It would be better to only do it on
12358 * the first update, but we don't have a nice way of doing that
12359 * (and really, set_config isn't used much for high freq page
12360 * flipping, so increasing its cost here shouldn't be a big
12363 if (i915
.fastboot
&& ret
== 0)
12364 intel_modeset_check_state(set
->crtc
->dev
);
12368 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12369 set
->crtc
->base
.id
, ret
);
12371 intel_set_config_restore_state(dev
, config
);
12373 drm_atomic_state_clear(state
);
12376 * HACK: if the pipe was on, but we didn't have a framebuffer,
12377 * force the pipe off to avoid oopsing in the modeset code
12378 * due to fb==NULL. This should only happen during boot since
12379 * we don't yet reconstruct the FB from the hardware state.
12381 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
12382 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
12384 /* Try to restore the config */
12385 if (config
->mode_changed
&&
12386 intel_set_mode(save_set
.crtc
, save_set
.mode
,
12387 save_set
.x
, save_set
.y
, save_set
.fb
,
12389 DRM_ERROR("failed to restore config after modeset failure\n");
12394 drm_atomic_state_free(state
);
12396 intel_set_config_free(config
);
12400 static const struct drm_crtc_funcs intel_crtc_funcs
= {
12401 .gamma_set
= intel_crtc_gamma_set
,
12402 .set_config
= intel_crtc_set_config
,
12403 .destroy
= intel_crtc_destroy
,
12404 .page_flip
= intel_crtc_page_flip
,
12405 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
12406 .atomic_destroy_state
= intel_crtc_destroy_state
,
12409 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
12410 struct intel_shared_dpll
*pll
,
12411 struct intel_dpll_hw_state
*hw_state
)
12415 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
12418 val
= I915_READ(PCH_DPLL(pll
->id
));
12419 hw_state
->dpll
= val
;
12420 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
12421 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
12423 return val
& DPLL_VCO_ENABLE
;
12426 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
12427 struct intel_shared_dpll
*pll
)
12429 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
12430 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
12433 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
12434 struct intel_shared_dpll
*pll
)
12436 /* PCH refclock must be enabled first */
12437 ibx_assert_pch_refclk_enabled(dev_priv
);
12439 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
12441 /* Wait for the clocks to stabilize. */
12442 POSTING_READ(PCH_DPLL(pll
->id
));
12445 /* The pixel multiplier can only be updated once the
12446 * DPLL is enabled and the clocks are stable.
12448 * So write it again.
12450 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
12451 POSTING_READ(PCH_DPLL(pll
->id
));
12455 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
12456 struct intel_shared_dpll
*pll
)
12458 struct drm_device
*dev
= dev_priv
->dev
;
12459 struct intel_crtc
*crtc
;
12461 /* Make sure no transcoder isn't still depending on us. */
12462 for_each_intel_crtc(dev
, crtc
) {
12463 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
12464 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
12467 I915_WRITE(PCH_DPLL(pll
->id
), 0);
12468 POSTING_READ(PCH_DPLL(pll
->id
));
12472 static char *ibx_pch_dpll_names
[] = {
12477 static void ibx_pch_dpll_init(struct drm_device
*dev
)
12479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12482 dev_priv
->num_shared_dpll
= 2;
12484 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12485 dev_priv
->shared_dplls
[i
].id
= i
;
12486 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
12487 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
12488 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
12489 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
12490 dev_priv
->shared_dplls
[i
].get_hw_state
=
12491 ibx_pch_dpll_get_hw_state
;
12495 static void intel_shared_dpll_init(struct drm_device
*dev
)
12497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12500 intel_ddi_pll_init(dev
);
12501 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
12502 ibx_pch_dpll_init(dev
);
12504 dev_priv
->num_shared_dpll
= 0;
12506 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
12510 * intel_wm_need_update - Check whether watermarks need updating
12511 * @plane: drm plane
12512 * @state: new plane state
12514 * Check current plane state versus the new one to determine whether
12515 * watermarks need to be recalculated.
12517 * Returns true or false.
12519 bool intel_wm_need_update(struct drm_plane
*plane
,
12520 struct drm_plane_state
*state
)
12522 /* Update watermarks on tiling changes. */
12523 if (!plane
->state
->fb
|| !state
->fb
||
12524 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
12525 plane
->state
->rotation
!= state
->rotation
)
12532 * intel_prepare_plane_fb - Prepare fb for usage on plane
12533 * @plane: drm plane to prepare for
12534 * @fb: framebuffer to prepare for presentation
12536 * Prepares a framebuffer for usage on a display plane. Generally this
12537 * involves pinning the underlying object and updating the frontbuffer tracking
12538 * bits. Some older platforms need special physical address handling for
12541 * Returns 0 on success, negative error code on failure.
12544 intel_prepare_plane_fb(struct drm_plane
*plane
,
12545 struct drm_framebuffer
*fb
,
12546 const struct drm_plane_state
*new_state
)
12548 struct drm_device
*dev
= plane
->dev
;
12549 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12550 enum pipe pipe
= intel_plane
->pipe
;
12551 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12552 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
12553 unsigned frontbuffer_bits
= 0;
12559 switch (plane
->type
) {
12560 case DRM_PLANE_TYPE_PRIMARY
:
12561 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
12563 case DRM_PLANE_TYPE_CURSOR
:
12564 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
12566 case DRM_PLANE_TYPE_OVERLAY
:
12567 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
12571 mutex_lock(&dev
->struct_mutex
);
12573 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
12574 INTEL_INFO(dev
)->cursor_needs_physical
) {
12575 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
12576 ret
= i915_gem_object_attach_phys(obj
, align
);
12578 DRM_DEBUG_KMS("failed to attach phys object\n");
12580 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
12584 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
12586 mutex_unlock(&dev
->struct_mutex
);
12592 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12593 * @plane: drm plane to clean up for
12594 * @fb: old framebuffer that was on plane
12596 * Cleans up a framebuffer that has just been removed from a plane.
12599 intel_cleanup_plane_fb(struct drm_plane
*plane
,
12600 struct drm_framebuffer
*fb
,
12601 const struct drm_plane_state
*old_state
)
12603 struct drm_device
*dev
= plane
->dev
;
12604 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12609 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
12610 !INTEL_INFO(dev
)->cursor_needs_physical
) {
12611 mutex_lock(&dev
->struct_mutex
);
12612 intel_unpin_fb_obj(fb
, old_state
);
12613 mutex_unlock(&dev
->struct_mutex
);
12618 intel_check_primary_plane(struct drm_plane
*plane
,
12619 struct intel_plane_state
*state
)
12621 struct drm_device
*dev
= plane
->dev
;
12622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12623 struct drm_crtc
*crtc
= state
->base
.crtc
;
12624 struct intel_crtc
*intel_crtc
;
12625 struct drm_framebuffer
*fb
= state
->base
.fb
;
12626 struct drm_rect
*dest
= &state
->dst
;
12627 struct drm_rect
*src
= &state
->src
;
12628 const struct drm_rect
*clip
= &state
->clip
;
12629 bool can_position
= false;
12632 crtc
= crtc
? crtc
: plane
->crtc
;
12633 intel_crtc
= to_intel_crtc(crtc
);
12635 if (INTEL_INFO(dev
)->gen
>= 9)
12636 can_position
= true;
12638 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12640 DRM_PLANE_HELPER_NO_SCALING
,
12641 DRM_PLANE_HELPER_NO_SCALING
,
12642 can_position
, true,
12647 if (intel_crtc
->active
) {
12648 intel_crtc
->atomic
.wait_for_flips
= true;
12651 * FBC does not work on some platforms for rotated
12652 * planes, so disable it when rotation is not 0 and
12653 * update it when rotation is set back to 0.
12655 * FIXME: This is redundant with the fbc update done in
12656 * the primary plane enable function except that that
12657 * one is done too late. We eventually need to unify
12660 if (intel_crtc
->primary_enabled
&&
12661 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
12662 dev_priv
->fbc
.crtc
== intel_crtc
&&
12663 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
12664 intel_crtc
->atomic
.disable_fbc
= true;
12667 if (state
->visible
) {
12669 * BDW signals flip done immediately if the plane
12670 * is disabled, even if the plane enable is already
12671 * armed to occur at the next vblank :(
12673 if (IS_BROADWELL(dev
) && !intel_crtc
->primary_enabled
)
12674 intel_crtc
->atomic
.wait_vblank
= true;
12677 intel_crtc
->atomic
.fb_bits
|=
12678 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
12680 intel_crtc
->atomic
.update_fbc
= true;
12682 if (intel_wm_need_update(plane
, &state
->base
))
12683 intel_crtc
->atomic
.update_wm
= true;
12690 intel_commit_primary_plane(struct drm_plane
*plane
,
12691 struct intel_plane_state
*state
)
12693 struct drm_crtc
*crtc
= state
->base
.crtc
;
12694 struct drm_framebuffer
*fb
= state
->base
.fb
;
12695 struct drm_device
*dev
= plane
->dev
;
12696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12697 struct intel_crtc
*intel_crtc
;
12698 struct drm_rect
*src
= &state
->src
;
12700 crtc
= crtc
? crtc
: plane
->crtc
;
12701 intel_crtc
= to_intel_crtc(crtc
);
12704 crtc
->x
= src
->x1
>> 16;
12705 crtc
->y
= src
->y1
>> 16;
12707 if (intel_crtc
->active
) {
12708 if (state
->visible
) {
12709 /* FIXME: kill this fastboot hack */
12710 intel_update_pipe_size(intel_crtc
);
12712 intel_crtc
->primary_enabled
= true;
12714 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
12718 * If clipping results in a non-visible primary plane,
12719 * we'll disable the primary plane. Note that this is
12720 * a bit different than what happens if userspace
12721 * explicitly disables the plane by passing fb=0
12722 * because plane->fb still gets set and pinned.
12724 intel_disable_primary_hw_plane(plane
, crtc
);
12729 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
12731 struct drm_device
*dev
= crtc
->dev
;
12732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12734 struct intel_plane
*intel_plane
;
12735 struct drm_plane
*p
;
12736 unsigned fb_bits
= 0;
12738 /* Track fb's for any planes being disabled */
12739 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
12740 intel_plane
= to_intel_plane(p
);
12742 if (intel_crtc
->atomic
.disabled_planes
&
12743 (1 << drm_plane_index(p
))) {
12745 case DRM_PLANE_TYPE_PRIMARY
:
12746 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
12748 case DRM_PLANE_TYPE_CURSOR
:
12749 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
12751 case DRM_PLANE_TYPE_OVERLAY
:
12752 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
12756 mutex_lock(&dev
->struct_mutex
);
12757 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
12758 mutex_unlock(&dev
->struct_mutex
);
12762 if (intel_crtc
->atomic
.wait_for_flips
)
12763 intel_crtc_wait_for_pending_flips(crtc
);
12765 if (intel_crtc
->atomic
.disable_fbc
)
12766 intel_fbc_disable(dev
);
12768 if (intel_crtc
->atomic
.pre_disable_primary
)
12769 intel_pre_disable_primary(crtc
);
12771 if (intel_crtc
->atomic
.update_wm
)
12772 intel_update_watermarks(crtc
);
12774 intel_runtime_pm_get(dev_priv
);
12776 /* Perform vblank evasion around commit operation */
12777 if (intel_crtc
->active
)
12778 intel_crtc
->atomic
.evade
=
12779 intel_pipe_update_start(intel_crtc
,
12780 &intel_crtc
->atomic
.start_vbl_count
);
12783 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
12785 struct drm_device
*dev
= crtc
->dev
;
12786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12787 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12788 struct drm_plane
*p
;
12790 if (intel_crtc
->atomic
.evade
)
12791 intel_pipe_update_end(intel_crtc
,
12792 intel_crtc
->atomic
.start_vbl_count
);
12794 intel_runtime_pm_put(dev_priv
);
12796 if (intel_crtc
->atomic
.wait_vblank
)
12797 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
12799 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
12801 if (intel_crtc
->atomic
.update_fbc
) {
12802 mutex_lock(&dev
->struct_mutex
);
12803 intel_fbc_update(dev
);
12804 mutex_unlock(&dev
->struct_mutex
);
12807 if (intel_crtc
->atomic
.post_enable_primary
)
12808 intel_post_enable_primary(crtc
);
12810 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
12811 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
12812 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
12815 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
12819 * intel_plane_destroy - destroy a plane
12820 * @plane: plane to destroy
12822 * Common destruction function for all types of planes (primary, cursor,
12825 void intel_plane_destroy(struct drm_plane
*plane
)
12827 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12828 drm_plane_cleanup(plane
);
12829 kfree(intel_plane
);
12832 const struct drm_plane_funcs intel_plane_funcs
= {
12833 .update_plane
= drm_atomic_helper_update_plane
,
12834 .disable_plane
= drm_atomic_helper_disable_plane
,
12835 .destroy
= intel_plane_destroy
,
12836 .set_property
= drm_atomic_helper_plane_set_property
,
12837 .atomic_get_property
= intel_plane_atomic_get_property
,
12838 .atomic_set_property
= intel_plane_atomic_set_property
,
12839 .atomic_duplicate_state
= intel_plane_duplicate_state
,
12840 .atomic_destroy_state
= intel_plane_destroy_state
,
12844 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
12847 struct intel_plane
*primary
;
12848 struct intel_plane_state
*state
;
12849 const uint32_t *intel_primary_formats
;
12852 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
12853 if (primary
== NULL
)
12856 state
= intel_create_plane_state(&primary
->base
);
12861 primary
->base
.state
= &state
->base
;
12863 primary
->can_scale
= false;
12864 primary
->max_downscale
= 1;
12865 primary
->pipe
= pipe
;
12866 primary
->plane
= pipe
;
12867 primary
->check_plane
= intel_check_primary_plane
;
12868 primary
->commit_plane
= intel_commit_primary_plane
;
12869 primary
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
12870 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
12871 primary
->plane
= !pipe
;
12873 if (INTEL_INFO(dev
)->gen
<= 3) {
12874 intel_primary_formats
= intel_primary_formats_gen2
;
12875 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
12877 intel_primary_formats
= intel_primary_formats_gen4
;
12878 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
12881 drm_universal_plane_init(dev
, &primary
->base
, 0,
12882 &intel_plane_funcs
,
12883 intel_primary_formats
, num_formats
,
12884 DRM_PLANE_TYPE_PRIMARY
);
12886 if (INTEL_INFO(dev
)->gen
>= 4)
12887 intel_create_rotation_property(dev
, primary
);
12889 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
12891 return &primary
->base
;
12894 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
12896 if (!dev
->mode_config
.rotation_property
) {
12897 unsigned long flags
= BIT(DRM_ROTATE_0
) |
12898 BIT(DRM_ROTATE_180
);
12900 if (INTEL_INFO(dev
)->gen
>= 9)
12901 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
12903 dev
->mode_config
.rotation_property
=
12904 drm_mode_create_rotation_property(dev
, flags
);
12906 if (dev
->mode_config
.rotation_property
)
12907 drm_object_attach_property(&plane
->base
.base
,
12908 dev
->mode_config
.rotation_property
,
12909 plane
->base
.state
->rotation
);
12913 intel_check_cursor_plane(struct drm_plane
*plane
,
12914 struct intel_plane_state
*state
)
12916 struct drm_crtc
*crtc
= state
->base
.crtc
;
12917 struct drm_device
*dev
= plane
->dev
;
12918 struct drm_framebuffer
*fb
= state
->base
.fb
;
12919 struct drm_rect
*dest
= &state
->dst
;
12920 struct drm_rect
*src
= &state
->src
;
12921 const struct drm_rect
*clip
= &state
->clip
;
12922 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12923 struct intel_crtc
*intel_crtc
;
12927 crtc
= crtc
? crtc
: plane
->crtc
;
12928 intel_crtc
= to_intel_crtc(crtc
);
12930 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12932 DRM_PLANE_HELPER_NO_SCALING
,
12933 DRM_PLANE_HELPER_NO_SCALING
,
12934 true, true, &state
->visible
);
12939 /* if we want to turn off the cursor ignore width and height */
12943 /* Check for which cursor types we support */
12944 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
12945 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12946 state
->base
.crtc_w
, state
->base
.crtc_h
);
12950 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
12951 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
12952 DRM_DEBUG_KMS("buffer is too small\n");
12956 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
12957 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12962 if (intel_crtc
->active
) {
12963 if (plane
->state
->crtc_w
!= state
->base
.crtc_w
)
12964 intel_crtc
->atomic
.update_wm
= true;
12966 intel_crtc
->atomic
.fb_bits
|=
12967 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
12974 intel_commit_cursor_plane(struct drm_plane
*plane
,
12975 struct intel_plane_state
*state
)
12977 struct drm_crtc
*crtc
= state
->base
.crtc
;
12978 struct drm_device
*dev
= plane
->dev
;
12979 struct intel_crtc
*intel_crtc
;
12980 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
12983 crtc
= crtc
? crtc
: plane
->crtc
;
12984 intel_crtc
= to_intel_crtc(crtc
);
12986 plane
->fb
= state
->base
.fb
;
12987 crtc
->cursor_x
= state
->base
.crtc_x
;
12988 crtc
->cursor_y
= state
->base
.crtc_y
;
12990 if (intel_crtc
->cursor_bo
== obj
)
12995 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
12996 addr
= i915_gem_obj_ggtt_offset(obj
);
12998 addr
= obj
->phys_handle
->busaddr
;
13000 intel_crtc
->cursor_addr
= addr
;
13001 intel_crtc
->cursor_bo
= obj
;
13004 if (intel_crtc
->active
)
13005 intel_crtc_update_cursor(crtc
, state
->visible
);
13008 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13011 struct intel_plane
*cursor
;
13012 struct intel_plane_state
*state
;
13014 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13015 if (cursor
== NULL
)
13018 state
= intel_create_plane_state(&cursor
->base
);
13023 cursor
->base
.state
= &state
->base
;
13025 cursor
->can_scale
= false;
13026 cursor
->max_downscale
= 1;
13027 cursor
->pipe
= pipe
;
13028 cursor
->plane
= pipe
;
13029 cursor
->check_plane
= intel_check_cursor_plane
;
13030 cursor
->commit_plane
= intel_commit_cursor_plane
;
13032 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13033 &intel_plane_funcs
,
13034 intel_cursor_formats
,
13035 ARRAY_SIZE(intel_cursor_formats
),
13036 DRM_PLANE_TYPE_CURSOR
);
13038 if (INTEL_INFO(dev
)->gen
>= 4) {
13039 if (!dev
->mode_config
.rotation_property
)
13040 dev
->mode_config
.rotation_property
=
13041 drm_mode_create_rotation_property(dev
,
13042 BIT(DRM_ROTATE_0
) |
13043 BIT(DRM_ROTATE_180
));
13044 if (dev
->mode_config
.rotation_property
)
13045 drm_object_attach_property(&cursor
->base
.base
,
13046 dev
->mode_config
.rotation_property
,
13047 state
->base
.rotation
);
13050 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13052 return &cursor
->base
;
13055 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13057 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13058 struct intel_crtc
*intel_crtc
;
13059 struct intel_crtc_state
*crtc_state
= NULL
;
13060 struct drm_plane
*primary
= NULL
;
13061 struct drm_plane
*cursor
= NULL
;
13064 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13065 if (intel_crtc
== NULL
)
13068 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13071 intel_crtc_set_state(intel_crtc
, crtc_state
);
13072 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13074 primary
= intel_primary_plane_create(dev
, pipe
);
13078 cursor
= intel_cursor_plane_create(dev
, pipe
);
13082 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13083 cursor
, &intel_crtc_funcs
);
13087 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13088 for (i
= 0; i
< 256; i
++) {
13089 intel_crtc
->lut_r
[i
] = i
;
13090 intel_crtc
->lut_g
[i
] = i
;
13091 intel_crtc
->lut_b
[i
] = i
;
13095 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13096 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13098 intel_crtc
->pipe
= pipe
;
13099 intel_crtc
->plane
= pipe
;
13100 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13101 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13102 intel_crtc
->plane
= !pipe
;
13105 intel_crtc
->cursor_base
= ~0;
13106 intel_crtc
->cursor_cntl
= ~0;
13107 intel_crtc
->cursor_size
= ~0;
13109 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13110 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13111 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13112 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13114 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
13116 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13118 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13123 drm_plane_cleanup(primary
);
13125 drm_plane_cleanup(cursor
);
13130 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13132 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13133 struct drm_device
*dev
= connector
->base
.dev
;
13135 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13137 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13138 return INVALID_PIPE
;
13140 return to_intel_crtc(encoder
->crtc
)->pipe
;
13143 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13144 struct drm_file
*file
)
13146 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13147 struct drm_crtc
*drmmode_crtc
;
13148 struct intel_crtc
*crtc
;
13150 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13152 if (!drmmode_crtc
) {
13153 DRM_ERROR("no such CRTC id\n");
13157 crtc
= to_intel_crtc(drmmode_crtc
);
13158 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13163 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13165 struct drm_device
*dev
= encoder
->base
.dev
;
13166 struct intel_encoder
*source_encoder
;
13167 int index_mask
= 0;
13170 for_each_intel_encoder(dev
, source_encoder
) {
13171 if (encoders_cloneable(encoder
, source_encoder
))
13172 index_mask
|= (1 << entry
);
13180 static bool has_edp_a(struct drm_device
*dev
)
13182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13184 if (!IS_MOBILE(dev
))
13187 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13190 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13196 static bool intel_crt_present(struct drm_device
*dev
)
13198 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13200 if (INTEL_INFO(dev
)->gen
>= 9)
13203 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13206 if (IS_CHERRYVIEW(dev
))
13209 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13215 static void intel_setup_outputs(struct drm_device
*dev
)
13217 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13218 struct intel_encoder
*encoder
;
13219 bool dpd_is_edp
= false;
13221 intel_lvds_init(dev
);
13223 if (intel_crt_present(dev
))
13224 intel_crt_init(dev
);
13226 if (HAS_DDI(dev
)) {
13230 * Haswell uses DDI functions to detect digital outputs.
13231 * On SKL pre-D0 the strap isn't connected, so we assume
13234 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13235 /* WaIgnoreDDIAStrap: skl */
13237 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
13238 intel_ddi_init(dev
, PORT_A
);
13240 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13242 found
= I915_READ(SFUSE_STRAP
);
13244 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13245 intel_ddi_init(dev
, PORT_B
);
13246 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13247 intel_ddi_init(dev
, PORT_C
);
13248 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13249 intel_ddi_init(dev
, PORT_D
);
13250 } else if (HAS_PCH_SPLIT(dev
)) {
13252 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
13254 if (has_edp_a(dev
))
13255 intel_dp_init(dev
, DP_A
, PORT_A
);
13257 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13258 /* PCH SDVOB multiplex with HDMIB */
13259 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
13261 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
13262 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13263 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
13266 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13267 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
13269 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13270 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
13272 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13273 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
13275 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13276 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
13277 } else if (IS_VALLEYVIEW(dev
)) {
13279 * The DP_DETECTED bit is the latched state of the DDC
13280 * SDA pin at boot. However since eDP doesn't require DDC
13281 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13282 * eDP ports may have been muxed to an alternate function.
13283 * Thus we can't rely on the DP_DETECTED bit alone to detect
13284 * eDP ports. Consult the VBT as well as DP_DETECTED to
13285 * detect eDP ports.
13287 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
13288 !intel_dp_is_edp(dev
, PORT_B
))
13289 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
13291 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
13292 intel_dp_is_edp(dev
, PORT_B
))
13293 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
13295 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
13296 !intel_dp_is_edp(dev
, PORT_C
))
13297 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
13299 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
13300 intel_dp_is_edp(dev
, PORT_C
))
13301 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
13303 if (IS_CHERRYVIEW(dev
)) {
13304 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
13305 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
13307 /* eDP not supported on port D, so don't check VBT */
13308 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
13309 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
13312 intel_dsi_init(dev
);
13313 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
13314 bool found
= false;
13316 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13317 DRM_DEBUG_KMS("probing SDVOB\n");
13318 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
13319 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
13320 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13321 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
13324 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
13325 intel_dp_init(dev
, DP_B
, PORT_B
);
13328 /* Before G4X SDVOC doesn't have its own detect register */
13330 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13331 DRM_DEBUG_KMS("probing SDVOC\n");
13332 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
13335 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
13337 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
13338 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13339 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
13341 if (SUPPORTS_INTEGRATED_DP(dev
))
13342 intel_dp_init(dev
, DP_C
, PORT_C
);
13345 if (SUPPORTS_INTEGRATED_DP(dev
) &&
13346 (I915_READ(DP_D
) & DP_DETECTED
))
13347 intel_dp_init(dev
, DP_D
, PORT_D
);
13348 } else if (IS_GEN2(dev
))
13349 intel_dvo_init(dev
);
13351 if (SUPPORTS_TV(dev
))
13352 intel_tv_init(dev
);
13354 intel_psr_init(dev
);
13356 for_each_intel_encoder(dev
, encoder
) {
13357 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
13358 encoder
->base
.possible_clones
=
13359 intel_encoder_clones(encoder
);
13362 intel_init_pch_refclk(dev
);
13364 drm_helper_move_panel_connectors_to_head(dev
);
13367 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
13369 struct drm_device
*dev
= fb
->dev
;
13370 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13372 drm_framebuffer_cleanup(fb
);
13373 mutex_lock(&dev
->struct_mutex
);
13374 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
13375 drm_gem_object_unreference(&intel_fb
->obj
->base
);
13376 mutex_unlock(&dev
->struct_mutex
);
13380 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
13381 struct drm_file
*file
,
13382 unsigned int *handle
)
13384 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13385 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
13387 return drm_gem_handle_create(file
, &obj
->base
, handle
);
13390 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
13391 .destroy
= intel_user_framebuffer_destroy
,
13392 .create_handle
= intel_user_framebuffer_create_handle
,
13396 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
13397 uint32_t pixel_format
)
13399 u32 gen
= INTEL_INFO(dev
)->gen
;
13402 /* "The stride in bytes must not exceed the of the size of 8K
13403 * pixels and 32K bytes."
13405 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
13406 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
13408 } else if (gen
>= 4) {
13409 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13413 } else if (gen
>= 3) {
13414 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13419 /* XXX DSPC is limited to 4k tiled */
13424 static int intel_framebuffer_init(struct drm_device
*dev
,
13425 struct intel_framebuffer
*intel_fb
,
13426 struct drm_mode_fb_cmd2
*mode_cmd
,
13427 struct drm_i915_gem_object
*obj
)
13429 unsigned int aligned_height
;
13431 u32 pitch_limit
, stride_alignment
;
13433 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
13435 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
13436 /* Enforce that fb modifier and tiling mode match, but only for
13437 * X-tiled. This is needed for FBC. */
13438 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
13439 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
13440 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13444 if (obj
->tiling_mode
== I915_TILING_X
)
13445 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
13446 else if (obj
->tiling_mode
== I915_TILING_Y
) {
13447 DRM_DEBUG("No Y tiling for legacy addfb\n");
13452 /* Passed in modifier sanity checking. */
13453 switch (mode_cmd
->modifier
[0]) {
13454 case I915_FORMAT_MOD_Y_TILED
:
13455 case I915_FORMAT_MOD_Yf_TILED
:
13456 if (INTEL_INFO(dev
)->gen
< 9) {
13457 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13458 mode_cmd
->modifier
[0]);
13461 case DRM_FORMAT_MOD_NONE
:
13462 case I915_FORMAT_MOD_X_TILED
:
13465 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13466 mode_cmd
->modifier
[0]);
13470 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
13471 mode_cmd
->pixel_format
);
13472 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
13473 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13474 mode_cmd
->pitches
[0], stride_alignment
);
13478 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
13479 mode_cmd
->pixel_format
);
13480 if (mode_cmd
->pitches
[0] > pitch_limit
) {
13481 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13482 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
13483 "tiled" : "linear",
13484 mode_cmd
->pitches
[0], pitch_limit
);
13488 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
13489 mode_cmd
->pitches
[0] != obj
->stride
) {
13490 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13491 mode_cmd
->pitches
[0], obj
->stride
);
13495 /* Reject formats not supported by any plane early. */
13496 switch (mode_cmd
->pixel_format
) {
13497 case DRM_FORMAT_C8
:
13498 case DRM_FORMAT_RGB565
:
13499 case DRM_FORMAT_XRGB8888
:
13500 case DRM_FORMAT_ARGB8888
:
13502 case DRM_FORMAT_XRGB1555
:
13503 case DRM_FORMAT_ARGB1555
:
13504 if (INTEL_INFO(dev
)->gen
> 3) {
13505 DRM_DEBUG("unsupported pixel format: %s\n",
13506 drm_get_format_name(mode_cmd
->pixel_format
));
13510 case DRM_FORMAT_XBGR8888
:
13511 case DRM_FORMAT_ABGR8888
:
13512 case DRM_FORMAT_XRGB2101010
:
13513 case DRM_FORMAT_ARGB2101010
:
13514 case DRM_FORMAT_XBGR2101010
:
13515 case DRM_FORMAT_ABGR2101010
:
13516 if (INTEL_INFO(dev
)->gen
< 4) {
13517 DRM_DEBUG("unsupported pixel format: %s\n",
13518 drm_get_format_name(mode_cmd
->pixel_format
));
13522 case DRM_FORMAT_YUYV
:
13523 case DRM_FORMAT_UYVY
:
13524 case DRM_FORMAT_YVYU
:
13525 case DRM_FORMAT_VYUY
:
13526 if (INTEL_INFO(dev
)->gen
< 5) {
13527 DRM_DEBUG("unsupported pixel format: %s\n",
13528 drm_get_format_name(mode_cmd
->pixel_format
));
13533 DRM_DEBUG("unsupported pixel format: %s\n",
13534 drm_get_format_name(mode_cmd
->pixel_format
));
13538 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13539 if (mode_cmd
->offsets
[0] != 0)
13542 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
13543 mode_cmd
->pixel_format
,
13544 mode_cmd
->modifier
[0]);
13545 /* FIXME drm helper for size checks (especially planar formats)? */
13546 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
13549 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
13550 intel_fb
->obj
= obj
;
13551 intel_fb
->obj
->framebuffer_references
++;
13553 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
13555 DRM_ERROR("framebuffer init failed %d\n", ret
);
13562 static struct drm_framebuffer
*
13563 intel_user_framebuffer_create(struct drm_device
*dev
,
13564 struct drm_file
*filp
,
13565 struct drm_mode_fb_cmd2
*mode_cmd
)
13567 struct drm_i915_gem_object
*obj
;
13569 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
13570 mode_cmd
->handles
[0]));
13571 if (&obj
->base
== NULL
)
13572 return ERR_PTR(-ENOENT
);
13574 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
13577 #ifndef CONFIG_DRM_I915_FBDEV
13578 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
13583 static const struct drm_mode_config_funcs intel_mode_funcs
= {
13584 .fb_create
= intel_user_framebuffer_create
,
13585 .output_poll_changed
= intel_fbdev_output_poll_changed
,
13586 .atomic_check
= intel_atomic_check
,
13587 .atomic_commit
= intel_atomic_commit
,
13590 /* Set up chip specific display functions */
13591 static void intel_init_display(struct drm_device
*dev
)
13593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13595 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
13596 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
13597 else if (IS_CHERRYVIEW(dev
))
13598 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
13599 else if (IS_VALLEYVIEW(dev
))
13600 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
13601 else if (IS_PINEVIEW(dev
))
13602 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
13604 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
13606 if (INTEL_INFO(dev
)->gen
>= 9) {
13607 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
13608 dev_priv
->display
.get_initial_plane_config
=
13609 skylake_get_initial_plane_config
;
13610 dev_priv
->display
.crtc_compute_clock
=
13611 haswell_crtc_compute_clock
;
13612 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
13613 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
13614 dev_priv
->display
.off
= ironlake_crtc_off
;
13615 dev_priv
->display
.update_primary_plane
=
13616 skylake_update_primary_plane
;
13617 } else if (HAS_DDI(dev
)) {
13618 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
13619 dev_priv
->display
.get_initial_plane_config
=
13620 ironlake_get_initial_plane_config
;
13621 dev_priv
->display
.crtc_compute_clock
=
13622 haswell_crtc_compute_clock
;
13623 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
13624 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
13625 dev_priv
->display
.off
= ironlake_crtc_off
;
13626 dev_priv
->display
.update_primary_plane
=
13627 ironlake_update_primary_plane
;
13628 } else if (HAS_PCH_SPLIT(dev
)) {
13629 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
13630 dev_priv
->display
.get_initial_plane_config
=
13631 ironlake_get_initial_plane_config
;
13632 dev_priv
->display
.crtc_compute_clock
=
13633 ironlake_crtc_compute_clock
;
13634 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
13635 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
13636 dev_priv
->display
.off
= ironlake_crtc_off
;
13637 dev_priv
->display
.update_primary_plane
=
13638 ironlake_update_primary_plane
;
13639 } else if (IS_VALLEYVIEW(dev
)) {
13640 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
13641 dev_priv
->display
.get_initial_plane_config
=
13642 i9xx_get_initial_plane_config
;
13643 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
13644 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
13645 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
13646 dev_priv
->display
.off
= i9xx_crtc_off
;
13647 dev_priv
->display
.update_primary_plane
=
13648 i9xx_update_primary_plane
;
13650 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
13651 dev_priv
->display
.get_initial_plane_config
=
13652 i9xx_get_initial_plane_config
;
13653 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
13654 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
13655 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
13656 dev_priv
->display
.off
= i9xx_crtc_off
;
13657 dev_priv
->display
.update_primary_plane
=
13658 i9xx_update_primary_plane
;
13661 /* Returns the core display clock speed */
13662 if (IS_SKYLAKE(dev
))
13663 dev_priv
->display
.get_display_clock_speed
=
13664 skylake_get_display_clock_speed
;
13665 else if (IS_BROADWELL(dev
))
13666 dev_priv
->display
.get_display_clock_speed
=
13667 broadwell_get_display_clock_speed
;
13668 else if (IS_HASWELL(dev
))
13669 dev_priv
->display
.get_display_clock_speed
=
13670 haswell_get_display_clock_speed
;
13671 else if (IS_VALLEYVIEW(dev
))
13672 dev_priv
->display
.get_display_clock_speed
=
13673 valleyview_get_display_clock_speed
;
13674 else if (IS_GEN5(dev
))
13675 dev_priv
->display
.get_display_clock_speed
=
13676 ilk_get_display_clock_speed
;
13677 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
13678 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
13679 dev_priv
->display
.get_display_clock_speed
=
13680 i945_get_display_clock_speed
;
13681 else if (IS_I915G(dev
))
13682 dev_priv
->display
.get_display_clock_speed
=
13683 i915_get_display_clock_speed
;
13684 else if (IS_I945GM(dev
) || IS_845G(dev
))
13685 dev_priv
->display
.get_display_clock_speed
=
13686 i9xx_misc_get_display_clock_speed
;
13687 else if (IS_PINEVIEW(dev
))
13688 dev_priv
->display
.get_display_clock_speed
=
13689 pnv_get_display_clock_speed
;
13690 else if (IS_I915GM(dev
))
13691 dev_priv
->display
.get_display_clock_speed
=
13692 i915gm_get_display_clock_speed
;
13693 else if (IS_I865G(dev
))
13694 dev_priv
->display
.get_display_clock_speed
=
13695 i865_get_display_clock_speed
;
13696 else if (IS_I85X(dev
))
13697 dev_priv
->display
.get_display_clock_speed
=
13698 i855_get_display_clock_speed
;
13699 else /* 852, 830 */
13700 dev_priv
->display
.get_display_clock_speed
=
13701 i830_get_display_clock_speed
;
13703 if (IS_GEN5(dev
)) {
13704 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
13705 } else if (IS_GEN6(dev
)) {
13706 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
13707 } else if (IS_IVYBRIDGE(dev
)) {
13708 /* FIXME: detect B0+ stepping and use auto training */
13709 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
13710 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
13711 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
13712 } else if (IS_VALLEYVIEW(dev
)) {
13713 dev_priv
->display
.modeset_global_resources
=
13714 valleyview_modeset_global_resources
;
13717 switch (INTEL_INFO(dev
)->gen
) {
13719 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
13723 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
13728 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
13732 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
13735 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13736 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
13739 /* Drop through - unsupported since execlist only. */
13741 /* Default just returns -ENODEV to indicate unsupported */
13742 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
13745 intel_panel_init_backlight_funcs(dev
);
13747 mutex_init(&dev_priv
->pps_mutex
);
13751 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13752 * resume, or other times. This quirk makes sure that's the case for
13753 * affected systems.
13755 static void quirk_pipea_force(struct drm_device
*dev
)
13757 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13759 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
13760 DRM_INFO("applying pipe a force quirk\n");
13763 static void quirk_pipeb_force(struct drm_device
*dev
)
13765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13767 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
13768 DRM_INFO("applying pipe b force quirk\n");
13772 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13774 static void quirk_ssc_force_disable(struct drm_device
*dev
)
13776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13777 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
13778 DRM_INFO("applying lvds SSC disable quirk\n");
13782 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13785 static void quirk_invert_brightness(struct drm_device
*dev
)
13787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13788 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
13789 DRM_INFO("applying inverted panel brightness quirk\n");
13792 /* Some VBT's incorrectly indicate no backlight is present */
13793 static void quirk_backlight_present(struct drm_device
*dev
)
13795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13796 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
13797 DRM_INFO("applying backlight present quirk\n");
13800 struct intel_quirk
{
13802 int subsystem_vendor
;
13803 int subsystem_device
;
13804 void (*hook
)(struct drm_device
*dev
);
13807 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13808 struct intel_dmi_quirk
{
13809 void (*hook
)(struct drm_device
*dev
);
13810 const struct dmi_system_id (*dmi_id_list
)[];
13813 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
13815 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
13819 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
13821 .dmi_id_list
= &(const struct dmi_system_id
[]) {
13823 .callback
= intel_dmi_reverse_brightness
,
13824 .ident
= "NCR Corporation",
13825 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
13826 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
13829 { } /* terminating entry */
13831 .hook
= quirk_invert_brightness
,
13835 static struct intel_quirk intel_quirks
[] = {
13836 /* HP Mini needs pipe A force quirk (LP: #322104) */
13837 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
13839 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13840 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
13842 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13843 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
13845 /* 830 needs to leave pipe A & dpll A up */
13846 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
13848 /* 830 needs to leave pipe B & dpll B up */
13849 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
13851 /* Lenovo U160 cannot use SSC on LVDS */
13852 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
13854 /* Sony Vaio Y cannot use SSC on LVDS */
13855 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
13857 /* Acer Aspire 5734Z must invert backlight brightness */
13858 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
13860 /* Acer/eMachines G725 */
13861 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
13863 /* Acer/eMachines e725 */
13864 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
13866 /* Acer/Packard Bell NCL20 */
13867 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
13869 /* Acer Aspire 4736Z */
13870 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
13872 /* Acer Aspire 5336 */
13873 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
13875 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13876 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
13878 /* Acer C720 Chromebook (Core i3 4005U) */
13879 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
13881 /* Apple Macbook 2,1 (Core 2 T7400) */
13882 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
13884 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13885 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
13887 /* HP Chromebook 14 (Celeron 2955U) */
13888 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
13890 /* Dell Chromebook 11 */
13891 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
13894 static void intel_init_quirks(struct drm_device
*dev
)
13896 struct pci_dev
*d
= dev
->pdev
;
13899 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
13900 struct intel_quirk
*q
= &intel_quirks
[i
];
13902 if (d
->device
== q
->device
&&
13903 (d
->subsystem_vendor
== q
->subsystem_vendor
||
13904 q
->subsystem_vendor
== PCI_ANY_ID
) &&
13905 (d
->subsystem_device
== q
->subsystem_device
||
13906 q
->subsystem_device
== PCI_ANY_ID
))
13909 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
13910 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
13911 intel_dmi_quirks
[i
].hook(dev
);
13915 /* Disable the VGA plane that we never use */
13916 static void i915_disable_vga(struct drm_device
*dev
)
13918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13920 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13922 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13923 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13924 outb(SR01
, VGA_SR_INDEX
);
13925 sr1
= inb(VGA_SR_DATA
);
13926 outb(sr1
| 1<<5, VGA_SR_DATA
);
13927 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13930 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
13931 POSTING_READ(vga_reg
);
13934 void intel_modeset_init_hw(struct drm_device
*dev
)
13936 intel_prepare_ddi(dev
);
13938 if (IS_VALLEYVIEW(dev
))
13939 vlv_update_cdclk(dev
);
13941 intel_init_clock_gating(dev
);
13943 intel_enable_gt_powersave(dev
);
13946 void intel_modeset_init(struct drm_device
*dev
)
13948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13951 struct intel_crtc
*crtc
;
13953 drm_mode_config_init(dev
);
13955 dev
->mode_config
.min_width
= 0;
13956 dev
->mode_config
.min_height
= 0;
13958 dev
->mode_config
.preferred_depth
= 24;
13959 dev
->mode_config
.prefer_shadow
= 1;
13961 dev
->mode_config
.allow_fb_modifiers
= true;
13963 dev
->mode_config
.funcs
= &intel_mode_funcs
;
13965 intel_init_quirks(dev
);
13967 intel_init_pm(dev
);
13969 if (INTEL_INFO(dev
)->num_pipes
== 0)
13972 intel_init_display(dev
);
13973 intel_init_audio(dev
);
13975 if (IS_GEN2(dev
)) {
13976 dev
->mode_config
.max_width
= 2048;
13977 dev
->mode_config
.max_height
= 2048;
13978 } else if (IS_GEN3(dev
)) {
13979 dev
->mode_config
.max_width
= 4096;
13980 dev
->mode_config
.max_height
= 4096;
13982 dev
->mode_config
.max_width
= 8192;
13983 dev
->mode_config
.max_height
= 8192;
13986 if (IS_845G(dev
) || IS_I865G(dev
)) {
13987 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13988 dev
->mode_config
.cursor_height
= 1023;
13989 } else if (IS_GEN2(dev
)) {
13990 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13991 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13993 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13994 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13997 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13999 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14000 INTEL_INFO(dev
)->num_pipes
,
14001 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14003 for_each_pipe(dev_priv
, pipe
) {
14004 intel_crtc_init(dev
, pipe
);
14005 for_each_sprite(dev_priv
, pipe
, sprite
) {
14006 ret
= intel_plane_init(dev
, pipe
, sprite
);
14008 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14009 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14013 intel_init_dpio(dev
);
14015 intel_shared_dpll_init(dev
);
14017 /* Just disable it once at startup */
14018 i915_disable_vga(dev
);
14019 intel_setup_outputs(dev
);
14021 /* Just in case the BIOS is doing something questionable. */
14022 intel_fbc_disable(dev
);
14024 drm_modeset_lock_all(dev
);
14025 intel_modeset_setup_hw_state(dev
, false);
14026 drm_modeset_unlock_all(dev
);
14028 for_each_intel_crtc(dev
, crtc
) {
14033 * Note that reserving the BIOS fb up front prevents us
14034 * from stuffing other stolen allocations like the ring
14035 * on top. This prevents some ugliness at boot time, and
14036 * can even allow for smooth boot transitions if the BIOS
14037 * fb is large enough for the active pipe configuration.
14039 if (dev_priv
->display
.get_initial_plane_config
) {
14040 dev_priv
->display
.get_initial_plane_config(crtc
,
14041 &crtc
->plane_config
);
14043 * If the fb is shared between multiple heads, we'll
14044 * just get the first one.
14046 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
14051 static void intel_enable_pipe_a(struct drm_device
*dev
)
14053 struct intel_connector
*connector
;
14054 struct drm_connector
*crt
= NULL
;
14055 struct intel_load_detect_pipe load_detect_temp
;
14056 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14058 /* We can't just switch on the pipe A, we need to set things up with a
14059 * proper mode and output configuration. As a gross hack, enable pipe A
14060 * by enabling the load detect pipe once. */
14061 for_each_intel_connector(dev
, connector
) {
14062 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14063 crt
= &connector
->base
;
14071 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14072 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14076 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14078 struct drm_device
*dev
= crtc
->base
.dev
;
14079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14082 if (INTEL_INFO(dev
)->num_pipes
== 1)
14085 reg
= DSPCNTR(!crtc
->plane
);
14086 val
= I915_READ(reg
);
14088 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14089 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14095 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14097 struct drm_device
*dev
= crtc
->base
.dev
;
14098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14101 /* Clear any frame start delays used for debugging left by the BIOS */
14102 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14103 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14105 /* restore vblank interrupts to correct state */
14106 drm_crtc_vblank_reset(&crtc
->base
);
14107 if (crtc
->active
) {
14108 update_scanline_offset(crtc
);
14109 drm_crtc_vblank_on(&crtc
->base
);
14112 /* We need to sanitize the plane -> pipe mapping first because this will
14113 * disable the crtc (and hence change the state) if it is wrong. Note
14114 * that gen4+ has a fixed plane -> pipe mapping. */
14115 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14116 struct intel_connector
*connector
;
14119 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14120 crtc
->base
.base
.id
);
14122 /* Pipe has the wrong plane attached and the plane is active.
14123 * Temporarily change the plane mapping and disable everything
14125 plane
= crtc
->plane
;
14126 crtc
->plane
= !plane
;
14127 crtc
->primary_enabled
= true;
14128 dev_priv
->display
.crtc_disable(&crtc
->base
);
14129 crtc
->plane
= plane
;
14131 /* ... and break all links. */
14132 for_each_intel_connector(dev
, connector
) {
14133 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
14136 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14137 connector
->base
.encoder
= NULL
;
14139 /* multiple connectors may have the same encoder:
14140 * handle them and break crtc link separately */
14141 for_each_intel_connector(dev
, connector
)
14142 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
14143 connector
->encoder
->base
.crtc
= NULL
;
14144 connector
->encoder
->connectors_active
= false;
14147 WARN_ON(crtc
->active
);
14148 crtc
->base
.state
->enable
= false;
14149 crtc
->base
.enabled
= false;
14152 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14153 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14154 /* BIOS forgot to enable pipe A, this mostly happens after
14155 * resume. Force-enable the pipe to fix this, the update_dpms
14156 * call below we restore the pipe to the right state, but leave
14157 * the required bits on. */
14158 intel_enable_pipe_a(dev
);
14161 /* Adjust the state of the output pipe according to whether we
14162 * have active connectors/encoders. */
14163 intel_crtc_update_dpms(&crtc
->base
);
14165 if (crtc
->active
!= crtc
->base
.state
->enable
) {
14166 struct intel_encoder
*encoder
;
14168 /* This can happen either due to bugs in the get_hw_state
14169 * functions or because the pipe is force-enabled due to the
14171 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14172 crtc
->base
.base
.id
,
14173 crtc
->base
.state
->enable
? "enabled" : "disabled",
14174 crtc
->active
? "enabled" : "disabled");
14176 crtc
->base
.state
->enable
= crtc
->active
;
14177 crtc
->base
.enabled
= crtc
->active
;
14179 /* Because we only establish the connector -> encoder ->
14180 * crtc links if something is active, this means the
14181 * crtc is now deactivated. Break the links. connector
14182 * -> encoder links are only establish when things are
14183 * actually up, hence no need to break them. */
14184 WARN_ON(crtc
->active
);
14186 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
14187 WARN_ON(encoder
->connectors_active
);
14188 encoder
->base
.crtc
= NULL
;
14192 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
14194 * We start out with underrun reporting disabled to avoid races.
14195 * For correct bookkeeping mark this on active crtcs.
14197 * Also on gmch platforms we dont have any hardware bits to
14198 * disable the underrun reporting. Which means we need to start
14199 * out with underrun reporting disabled also on inactive pipes,
14200 * since otherwise we'll complain about the garbage we read when
14201 * e.g. coming up after runtime pm.
14203 * No protection against concurrent access is required - at
14204 * worst a fifo underrun happens which also sets this to false.
14206 crtc
->cpu_fifo_underrun_disabled
= true;
14207 crtc
->pch_fifo_underrun_disabled
= true;
14211 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14213 struct intel_connector
*connector
;
14214 struct drm_device
*dev
= encoder
->base
.dev
;
14216 /* We need to check both for a crtc link (meaning that the
14217 * encoder is active and trying to read from a pipe) and the
14218 * pipe itself being active. */
14219 bool has_active_crtc
= encoder
->base
.crtc
&&
14220 to_intel_crtc(encoder
->base
.crtc
)->active
;
14222 if (encoder
->connectors_active
&& !has_active_crtc
) {
14223 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14224 encoder
->base
.base
.id
,
14225 encoder
->base
.name
);
14227 /* Connector is active, but has no active pipe. This is
14228 * fallout from our resume register restoring. Disable
14229 * the encoder manually again. */
14230 if (encoder
->base
.crtc
) {
14231 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14232 encoder
->base
.base
.id
,
14233 encoder
->base
.name
);
14234 encoder
->disable(encoder
);
14235 if (encoder
->post_disable
)
14236 encoder
->post_disable(encoder
);
14238 encoder
->base
.crtc
= NULL
;
14239 encoder
->connectors_active
= false;
14241 /* Inconsistent output/port/pipe state happens presumably due to
14242 * a bug in one of the get_hw_state functions. Or someplace else
14243 * in our code, like the register restore mess on resume. Clamp
14244 * things to off as a safer default. */
14245 for_each_intel_connector(dev
, connector
) {
14246 if (connector
->encoder
!= encoder
)
14248 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14249 connector
->base
.encoder
= NULL
;
14252 /* Enabled encoders without active connectors will be fixed in
14253 * the crtc fixup. */
14256 void i915_redisable_vga_power_on(struct drm_device
*dev
)
14258 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14259 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14261 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14262 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14263 i915_disable_vga(dev
);
14267 void i915_redisable_vga(struct drm_device
*dev
)
14269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14271 /* This function can be called both from intel_modeset_setup_hw_state or
14272 * at a very early point in our resume sequence, where the power well
14273 * structures are not yet restored. Since this function is at a very
14274 * paranoid "someone might have enabled VGA while we were not looking"
14275 * level, just check if the power well is enabled instead of trying to
14276 * follow the "don't touch the power well if we don't need it" policy
14277 * the rest of the driver uses. */
14278 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14281 i915_redisable_vga_power_on(dev
);
14284 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
14286 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
14291 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
14294 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
14296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14298 struct intel_crtc
*crtc
;
14299 struct intel_encoder
*encoder
;
14300 struct intel_connector
*connector
;
14303 for_each_intel_crtc(dev
, crtc
) {
14304 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
14306 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
14308 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
14311 crtc
->base
.state
->enable
= crtc
->active
;
14312 crtc
->base
.enabled
= crtc
->active
;
14313 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
14315 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14316 crtc
->base
.base
.id
,
14317 crtc
->active
? "enabled" : "disabled");
14320 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14321 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14323 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
14324 &pll
->config
.hw_state
);
14326 pll
->config
.crtc_mask
= 0;
14327 for_each_intel_crtc(dev
, crtc
) {
14328 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
14330 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
14334 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14335 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
14337 if (pll
->config
.crtc_mask
)
14338 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
14341 for_each_intel_encoder(dev
, encoder
) {
14344 if (encoder
->get_hw_state(encoder
, &pipe
)) {
14345 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
14346 encoder
->base
.crtc
= &crtc
->base
;
14347 encoder
->get_config(encoder
, crtc
->config
);
14349 encoder
->base
.crtc
= NULL
;
14352 encoder
->connectors_active
= false;
14353 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14354 encoder
->base
.base
.id
,
14355 encoder
->base
.name
,
14356 encoder
->base
.crtc
? "enabled" : "disabled",
14360 for_each_intel_connector(dev
, connector
) {
14361 if (connector
->get_hw_state(connector
)) {
14362 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
14363 connector
->encoder
->connectors_active
= true;
14364 connector
->base
.encoder
= &connector
->encoder
->base
;
14366 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14367 connector
->base
.encoder
= NULL
;
14369 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14370 connector
->base
.base
.id
,
14371 connector
->base
.name
,
14372 connector
->base
.encoder
? "enabled" : "disabled");
14376 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14377 * and i915 state tracking structures. */
14378 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
14379 bool force_restore
)
14381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14383 struct intel_crtc
*crtc
;
14384 struct intel_encoder
*encoder
;
14387 intel_modeset_readout_hw_state(dev
);
14390 * Now that we have the config, copy it to each CRTC struct
14391 * Note that this could go away if we move to using crtc_config
14392 * checking everywhere.
14394 for_each_intel_crtc(dev
, crtc
) {
14395 if (crtc
->active
&& i915
.fastboot
) {
14396 intel_mode_from_pipe_config(&crtc
->base
.mode
,
14398 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14399 crtc
->base
.base
.id
);
14400 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
14404 /* HW state is read out, now we need to sanitize this mess. */
14405 for_each_intel_encoder(dev
, encoder
) {
14406 intel_sanitize_encoder(encoder
);
14409 for_each_pipe(dev_priv
, pipe
) {
14410 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
14411 intel_sanitize_crtc(crtc
);
14412 intel_dump_pipe_config(crtc
, crtc
->config
,
14413 "[setup_hw_state]");
14416 intel_modeset_update_connector_atomic_state(dev
);
14418 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14419 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14421 if (!pll
->on
|| pll
->active
)
14424 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
14426 pll
->disable(dev_priv
, pll
);
14431 skl_wm_get_hw_state(dev
);
14432 else if (HAS_PCH_SPLIT(dev
))
14433 ilk_wm_get_hw_state(dev
);
14435 if (force_restore
) {
14436 i915_redisable_vga(dev
);
14439 * We need to use raw interfaces for restoring state to avoid
14440 * checking (bogus) intermediate states.
14442 for_each_pipe(dev_priv
, pipe
) {
14443 struct drm_crtc
*crtc
=
14444 dev_priv
->pipe_to_crtc_mapping
[pipe
];
14446 intel_crtc_restore_mode(crtc
);
14449 intel_modeset_update_staged_output_state(dev
);
14452 intel_modeset_check_state(dev
);
14455 void intel_modeset_gem_init(struct drm_device
*dev
)
14457 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14458 struct drm_crtc
*c
;
14459 struct drm_i915_gem_object
*obj
;
14461 mutex_lock(&dev
->struct_mutex
);
14462 intel_init_gt_powersave(dev
);
14463 mutex_unlock(&dev
->struct_mutex
);
14466 * There may be no VBT; and if the BIOS enabled SSC we can
14467 * just keep using it to avoid unnecessary flicker. Whereas if the
14468 * BIOS isn't using it, don't assume it will work even if the VBT
14469 * indicates as much.
14471 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
14472 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14475 intel_modeset_init_hw(dev
);
14477 intel_setup_overlay(dev
);
14480 * Make sure any fbs we allocated at startup are properly
14481 * pinned & fenced. When we do the allocation it's too early
14484 mutex_lock(&dev
->struct_mutex
);
14485 for_each_crtc(dev
, c
) {
14486 obj
= intel_fb_obj(c
->primary
->fb
);
14490 if (intel_pin_and_fence_fb_obj(c
->primary
,
14494 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14495 to_intel_crtc(c
)->pipe
);
14496 drm_framebuffer_unreference(c
->primary
->fb
);
14497 c
->primary
->fb
= NULL
;
14498 update_state_fb(c
->primary
);
14501 mutex_unlock(&dev
->struct_mutex
);
14503 intel_backlight_register(dev
);
14506 void intel_connector_unregister(struct intel_connector
*intel_connector
)
14508 struct drm_connector
*connector
= &intel_connector
->base
;
14510 intel_panel_destroy_backlight(connector
);
14511 drm_connector_unregister(connector
);
14514 void intel_modeset_cleanup(struct drm_device
*dev
)
14516 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14517 struct drm_connector
*connector
;
14519 intel_disable_gt_powersave(dev
);
14521 intel_backlight_unregister(dev
);
14524 * Interrupts and polling as the first thing to avoid creating havoc.
14525 * Too much stuff here (turning of connectors, ...) would
14526 * experience fancy races otherwise.
14528 intel_irq_uninstall(dev_priv
);
14531 * Due to the hpd irq storm handling the hotplug work can re-arm the
14532 * poll handlers. Hence disable polling after hpd handling is shut down.
14534 drm_kms_helper_poll_fini(dev
);
14536 mutex_lock(&dev
->struct_mutex
);
14538 intel_unregister_dsm_handler();
14540 intel_fbc_disable(dev
);
14542 mutex_unlock(&dev
->struct_mutex
);
14544 /* flush any delayed tasks or pending work */
14545 flush_scheduled_work();
14547 /* destroy the backlight and sysfs files before encoders/connectors */
14548 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
14549 struct intel_connector
*intel_connector
;
14551 intel_connector
= to_intel_connector(connector
);
14552 intel_connector
->unregister(intel_connector
);
14555 drm_mode_config_cleanup(dev
);
14557 intel_cleanup_overlay(dev
);
14559 mutex_lock(&dev
->struct_mutex
);
14560 intel_cleanup_gt_powersave(dev
);
14561 mutex_unlock(&dev
->struct_mutex
);
14565 * Return which encoder is currently attached for connector.
14567 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
14569 return &intel_attached_encoder(connector
)->base
;
14572 void intel_connector_attach_encoder(struct intel_connector
*connector
,
14573 struct intel_encoder
*encoder
)
14575 connector
->encoder
= encoder
;
14576 drm_mode_connector_attach_encoder(&connector
->base
,
14581 * set vga decode state - true == enable VGA decode
14583 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
14585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14586 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
14589 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
14590 DRM_ERROR("failed to read control word\n");
14594 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
14598 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
14600 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
14602 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
14603 DRM_ERROR("failed to write control word\n");
14610 struct intel_display_error_state
{
14612 u32 power_well_driver
;
14614 int num_transcoders
;
14616 struct intel_cursor_error_state
{
14621 } cursor
[I915_MAX_PIPES
];
14623 struct intel_pipe_error_state
{
14624 bool power_domain_on
;
14627 } pipe
[I915_MAX_PIPES
];
14629 struct intel_plane_error_state
{
14637 } plane
[I915_MAX_PIPES
];
14639 struct intel_transcoder_error_state
{
14640 bool power_domain_on
;
14641 enum transcoder cpu_transcoder
;
14654 struct intel_display_error_state
*
14655 intel_display_capture_error_state(struct drm_device
*dev
)
14657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14658 struct intel_display_error_state
*error
;
14659 int transcoders
[] = {
14667 if (INTEL_INFO(dev
)->num_pipes
== 0)
14670 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
14674 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
14675 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
14677 for_each_pipe(dev_priv
, i
) {
14678 error
->pipe
[i
].power_domain_on
=
14679 __intel_display_power_is_enabled(dev_priv
,
14680 POWER_DOMAIN_PIPE(i
));
14681 if (!error
->pipe
[i
].power_domain_on
)
14684 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
14685 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
14686 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
14688 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
14689 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
14690 if (INTEL_INFO(dev
)->gen
<= 3) {
14691 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
14692 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
14694 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
14695 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
14696 if (INTEL_INFO(dev
)->gen
>= 4) {
14697 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
14698 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
14701 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
14703 if (HAS_GMCH_DISPLAY(dev
))
14704 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
14707 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
14708 if (HAS_DDI(dev_priv
->dev
))
14709 error
->num_transcoders
++; /* Account for eDP. */
14711 for (i
= 0; i
< error
->num_transcoders
; i
++) {
14712 enum transcoder cpu_transcoder
= transcoders
[i
];
14714 error
->transcoder
[i
].power_domain_on
=
14715 __intel_display_power_is_enabled(dev_priv
,
14716 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
14717 if (!error
->transcoder
[i
].power_domain_on
)
14720 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
14722 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
14723 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
14724 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
14725 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
14726 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
14727 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
14728 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
14734 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14737 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
14738 struct drm_device
*dev
,
14739 struct intel_display_error_state
*error
)
14741 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14747 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
14748 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
14749 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
14750 error
->power_well_driver
);
14751 for_each_pipe(dev_priv
, i
) {
14752 err_printf(m
, "Pipe [%d]:\n", i
);
14753 err_printf(m
, " Power: %s\n",
14754 error
->pipe
[i
].power_domain_on
? "on" : "off");
14755 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
14756 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
14758 err_printf(m
, "Plane [%d]:\n", i
);
14759 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
14760 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
14761 if (INTEL_INFO(dev
)->gen
<= 3) {
14762 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
14763 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
14765 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
14766 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
14767 if (INTEL_INFO(dev
)->gen
>= 4) {
14768 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
14769 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
14772 err_printf(m
, "Cursor [%d]:\n", i
);
14773 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
14774 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
14775 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
14778 for (i
= 0; i
< error
->num_transcoders
; i
++) {
14779 err_printf(m
, "CPU transcoder: %c\n",
14780 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
14781 err_printf(m
, " Power: %s\n",
14782 error
->transcoder
[i
].power_domain_on
? "on" : "off");
14783 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
14784 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
14785 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
14786 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
14787 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
14788 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
14789 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
14793 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
14795 struct intel_crtc
*crtc
;
14797 for_each_intel_crtc(dev
, crtc
) {
14798 struct intel_unpin_work
*work
;
14800 spin_lock_irq(&dev
->event_lock
);
14802 work
= crtc
->unpin_work
;
14804 if (work
&& work
->event
&&
14805 work
->event
->base
.file_priv
== file
) {
14806 kfree(work
->event
);
14807 work
->event
= NULL
;
14810 spin_unlock_irq(&dev
->event_lock
);