2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
95 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
97 struct intel_link_m_n
*m_n
,
98 struct intel_link_m_n
*m2_n2
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
103 static void chv_prepare_pll(struct intel_crtc
*crtc
);
105 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
107 if (!connector
->mst_port
)
108 return connector
->encoder
;
110 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
119 int p2_slow
, p2_fast
;
122 typedef struct intel_limit intel_limit_t
;
124 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
129 intel_pch_rawclk(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 WARN_ON(!HAS_PCH_SPLIT(dev
));
135 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
138 static inline u32
/* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac
= {
149 .dot
= { .min
= 25000, .max
= 350000 },
150 .vco
= { .min
= 908000, .max
= 1512000 },
151 .n
= { .min
= 2, .max
= 16 },
152 .m
= { .min
= 96, .max
= 140 },
153 .m1
= { .min
= 18, .max
= 26 },
154 .m2
= { .min
= 6, .max
= 16 },
155 .p
= { .min
= 4, .max
= 128 },
156 .p1
= { .min
= 2, .max
= 33 },
157 .p2
= { .dot_limit
= 165000,
158 .p2_slow
= 4, .p2_fast
= 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo
= {
162 .dot
= { .min
= 25000, .max
= 350000 },
163 .vco
= { .min
= 908000, .max
= 1512000 },
164 .n
= { .min
= 2, .max
= 16 },
165 .m
= { .min
= 96, .max
= 140 },
166 .m1
= { .min
= 18, .max
= 26 },
167 .m2
= { .min
= 6, .max
= 16 },
168 .p
= { .min
= 4, .max
= 128 },
169 .p1
= { .min
= 2, .max
= 33 },
170 .p2
= { .dot_limit
= 165000,
171 .p2_slow
= 4, .p2_fast
= 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds
= {
175 .dot
= { .min
= 25000, .max
= 350000 },
176 .vco
= { .min
= 908000, .max
= 1512000 },
177 .n
= { .min
= 2, .max
= 16 },
178 .m
= { .min
= 96, .max
= 140 },
179 .m1
= { .min
= 18, .max
= 26 },
180 .m2
= { .min
= 6, .max
= 16 },
181 .p
= { .min
= 4, .max
= 128 },
182 .p1
= { .min
= 1, .max
= 6 },
183 .p2
= { .dot_limit
= 165000,
184 .p2_slow
= 14, .p2_fast
= 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo
= {
188 .dot
= { .min
= 20000, .max
= 400000 },
189 .vco
= { .min
= 1400000, .max
= 2800000 },
190 .n
= { .min
= 1, .max
= 6 },
191 .m
= { .min
= 70, .max
= 120 },
192 .m1
= { .min
= 8, .max
= 18 },
193 .m2
= { .min
= 3, .max
= 7 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8 },
196 .p2
= { .dot_limit
= 200000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds
= {
201 .dot
= { .min
= 20000, .max
= 400000 },
202 .vco
= { .min
= 1400000, .max
= 2800000 },
203 .n
= { .min
= 1, .max
= 6 },
204 .m
= { .min
= 70, .max
= 120 },
205 .m1
= { .min
= 8, .max
= 18 },
206 .m2
= { .min
= 3, .max
= 7 },
207 .p
= { .min
= 7, .max
= 98 },
208 .p1
= { .min
= 1, .max
= 8 },
209 .p2
= { .dot_limit
= 112000,
210 .p2_slow
= 14, .p2_fast
= 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo
= {
215 .dot
= { .min
= 25000, .max
= 270000 },
216 .vco
= { .min
= 1750000, .max
= 3500000},
217 .n
= { .min
= 1, .max
= 4 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 10, .max
= 30 },
222 .p1
= { .min
= 1, .max
= 3},
223 .p2
= { .dot_limit
= 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi
= {
230 .dot
= { .min
= 22000, .max
= 400000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 4 },
233 .m
= { .min
= 104, .max
= 138 },
234 .m1
= { .min
= 16, .max
= 23 },
235 .m2
= { .min
= 5, .max
= 11 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8},
238 .p2
= { .dot_limit
= 165000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
243 .dot
= { .min
= 20000, .max
= 115000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 14, .p2_fast
= 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
257 .dot
= { .min
= 80000, .max
= 224000 },
258 .vco
= { .min
= 1750000, .max
= 3500000 },
259 .n
= { .min
= 1, .max
= 3 },
260 .m
= { .min
= 104, .max
= 138 },
261 .m1
= { .min
= 17, .max
= 23 },
262 .m2
= { .min
= 5, .max
= 11 },
263 .p
= { .min
= 14, .max
= 42 },
264 .p1
= { .min
= 2, .max
= 6 },
265 .p2
= { .dot_limit
= 0,
266 .p2_slow
= 7, .p2_fast
= 7
270 static const intel_limit_t intel_limits_pineview_sdvo
= {
271 .dot
= { .min
= 20000, .max
= 400000},
272 .vco
= { .min
= 1700000, .max
= 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1
= { .min
= 0, .max
= 0 },
278 .m2
= { .min
= 0, .max
= 254 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 200000,
282 .p2_slow
= 10, .p2_fast
= 5 },
285 static const intel_limit_t intel_limits_pineview_lvds
= {
286 .dot
= { .min
= 20000, .max
= 400000 },
287 .vco
= { .min
= 1700000, .max
= 3500000 },
288 .n
= { .min
= 3, .max
= 6 },
289 .m
= { .min
= 2, .max
= 256 },
290 .m1
= { .min
= 0, .max
= 0 },
291 .m2
= { .min
= 0, .max
= 254 },
292 .p
= { .min
= 7, .max
= 112 },
293 .p1
= { .min
= 1, .max
= 8 },
294 .p2
= { .dot_limit
= 112000,
295 .p2_slow
= 14, .p2_fast
= 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac
= {
304 .dot
= { .min
= 25000, .max
= 350000 },
305 .vco
= { .min
= 1760000, .max
= 3510000 },
306 .n
= { .min
= 1, .max
= 5 },
307 .m
= { .min
= 79, .max
= 127 },
308 .m1
= { .min
= 12, .max
= 22 },
309 .m2
= { .min
= 5, .max
= 9 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 225000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
317 .dot
= { .min
= 25000, .max
= 350000 },
318 .vco
= { .min
= 1760000, .max
= 3510000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 79, .max
= 118 },
321 .m1
= { .min
= 12, .max
= 22 },
322 .m2
= { .min
= 5, .max
= 9 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 225000,
326 .p2_slow
= 14, .p2_fast
= 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 127 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 56 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 79, .max
= 126 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 28, .max
= 112 },
351 .p1
= { .min
= 2, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 14, .p2_fast
= 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 126 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 14, .max
= 42 },
364 .p1
= { .min
= 2, .max
= 6 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 7, .p2_fast
= 7 },
369 static const intel_limit_t intel_limits_vlv
= {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m1
= { .min
= 2, .max
= 3 },
380 .m2
= { .min
= 11, .max
= 156 },
381 .p1
= { .min
= 2, .max
= 3 },
382 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv
= {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
393 .vco
= { .min
= 4860000, .max
= 6700000 },
394 .n
= { .min
= 1, .max
= 1 },
395 .m1
= { .min
= 2, .max
= 2 },
396 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
397 .p1
= { .min
= 2, .max
= 4 },
398 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
401 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
403 clock
->m
= clock
->m1
* clock
->m2
;
404 clock
->p
= clock
->p1
* clock
->p2
;
405 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
407 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
408 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
412 * Returns whether any output on the specified pipe is of the specified type
414 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
416 struct drm_device
*dev
= crtc
->dev
;
417 struct intel_encoder
*encoder
;
419 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
420 if (encoder
->type
== type
)
426 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
429 struct drm_device
*dev
= crtc
->dev
;
430 const intel_limit_t
*limit
;
432 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
433 if (intel_is_dual_link_lvds(dev
)) {
434 if (refclk
== 100000)
435 limit
= &intel_limits_ironlake_dual_lvds_100m
;
437 limit
= &intel_limits_ironlake_dual_lvds
;
439 if (refclk
== 100000)
440 limit
= &intel_limits_ironlake_single_lvds_100m
;
442 limit
= &intel_limits_ironlake_single_lvds
;
445 limit
= &intel_limits_ironlake_dac
;
450 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
452 struct drm_device
*dev
= crtc
->dev
;
453 const intel_limit_t
*limit
;
455 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
456 if (intel_is_dual_link_lvds(dev
))
457 limit
= &intel_limits_g4x_dual_channel_lvds
;
459 limit
= &intel_limits_g4x_single_channel_lvds
;
460 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
461 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
462 limit
= &intel_limits_g4x_hdmi
;
463 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
464 limit
= &intel_limits_g4x_sdvo
;
465 } else /* The option is for other outputs */
466 limit
= &intel_limits_i9xx_sdvo
;
471 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
473 struct drm_device
*dev
= crtc
->dev
;
474 const intel_limit_t
*limit
;
476 if (HAS_PCH_SPLIT(dev
))
477 limit
= intel_ironlake_limit(crtc
, refclk
);
478 else if (IS_G4X(dev
)) {
479 limit
= intel_g4x_limit(crtc
);
480 } else if (IS_PINEVIEW(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
482 limit
= &intel_limits_pineview_lvds
;
484 limit
= &intel_limits_pineview_sdvo
;
485 } else if (IS_CHERRYVIEW(dev
)) {
486 limit
= &intel_limits_chv
;
487 } else if (IS_VALLEYVIEW(dev
)) {
488 limit
= &intel_limits_vlv
;
489 } else if (!IS_GEN2(dev
)) {
490 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
491 limit
= &intel_limits_i9xx_lvds
;
493 limit
= &intel_limits_i9xx_sdvo
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
496 limit
= &intel_limits_i8xx_lvds
;
497 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
498 limit
= &intel_limits_i8xx_dvo
;
500 limit
= &intel_limits_i8xx_dac
;
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
508 clock
->m
= clock
->m2
+ 2;
509 clock
->p
= clock
->p1
* clock
->p2
;
510 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
512 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
513 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
516 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
518 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
521 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= i9xx_dpll_compute_m(clock
);
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static void chv_clock(int refclk
, intel_clock_t
*clock
)
533 clock
->m
= clock
->m1
* clock
->m2
;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
539 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device
*dev
,
549 const intel_limit_t
*limit
,
550 const intel_clock_t
*clock
)
552 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
553 INTELPllInvalid("n out of range\n");
554 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
559 INTELPllInvalid("m1 out of range\n");
561 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
562 if (clock
->m1
<= clock
->m2
)
563 INTELPllInvalid("m1 <= m2\n");
565 if (!IS_VALLEYVIEW(dev
)) {
566 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
567 INTELPllInvalid("p out of range\n");
568 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
569 INTELPllInvalid("m out of range\n");
572 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
577 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
578 INTELPllInvalid("dot out of range\n");
584 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
585 int target
, int refclk
, intel_clock_t
*match_clock
,
586 intel_clock_t
*best_clock
)
588 struct drm_device
*dev
= crtc
->dev
;
592 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
598 if (intel_is_dual_link_lvds(dev
))
599 clock
.p2
= limit
->p2
.p2_fast
;
601 clock
.p2
= limit
->p2
.p2_slow
;
603 if (target
< limit
->p2
.dot_limit
)
604 clock
.p2
= limit
->p2
.p2_slow
;
606 clock
.p2
= limit
->p2
.p2_fast
;
609 memset(best_clock
, 0, sizeof(*best_clock
));
611 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
613 for (clock
.m2
= limit
->m2
.min
;
614 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
615 if (clock
.m2
>= clock
.m1
)
617 for (clock
.n
= limit
->n
.min
;
618 clock
.n
<= limit
->n
.max
; clock
.n
++) {
619 for (clock
.p1
= limit
->p1
.min
;
620 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
623 i9xx_clock(refclk
, &clock
);
624 if (!intel_PLL_is_valid(dev
, limit
,
628 clock
.p
!= match_clock
->p
)
631 this_err
= abs(clock
.dot
- target
);
632 if (this_err
< err
) {
641 return (err
!= target
);
645 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
646 int target
, int refclk
, intel_clock_t
*match_clock
,
647 intel_clock_t
*best_clock
)
649 struct drm_device
*dev
= crtc
->dev
;
653 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev
))
660 clock
.p2
= limit
->p2
.p2_fast
;
662 clock
.p2
= limit
->p2
.p2_slow
;
664 if (target
< limit
->p2
.dot_limit
)
665 clock
.p2
= limit
->p2
.p2_slow
;
667 clock
.p2
= limit
->p2
.p2_fast
;
670 memset(best_clock
, 0, sizeof(*best_clock
));
672 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
674 for (clock
.m2
= limit
->m2
.min
;
675 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
676 for (clock
.n
= limit
->n
.min
;
677 clock
.n
<= limit
->n
.max
; clock
.n
++) {
678 for (clock
.p1
= limit
->p1
.min
;
679 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
682 pineview_clock(refclk
, &clock
);
683 if (!intel_PLL_is_valid(dev
, limit
,
687 clock
.p
!= match_clock
->p
)
690 this_err
= abs(clock
.dot
- target
);
691 if (this_err
< err
) {
700 return (err
!= target
);
704 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 struct drm_device
*dev
= crtc
->dev
;
712 /* approximately equals target * 0.00585 */
713 int err_most
= (target
>> 8) + (target
>> 9);
716 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (intel_is_dual_link_lvds(dev
))
718 clock
.p2
= limit
->p2
.p2_fast
;
720 clock
.p2
= limit
->p2
.p2_slow
;
722 if (target
< limit
->p2
.dot_limit
)
723 clock
.p2
= limit
->p2
.p2_slow
;
725 clock
.p2
= limit
->p2
.p2_fast
;
728 memset(best_clock
, 0, sizeof(*best_clock
));
729 max_n
= limit
->n
.max
;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock
.m1
= limit
->m1
.max
;
734 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
735 for (clock
.m2
= limit
->m2
.max
;
736 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
737 for (clock
.p1
= limit
->p1
.max
;
738 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
741 i9xx_clock(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 this_err
= abs(clock
.dot
- target
);
747 if (this_err
< err_most
) {
761 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
762 int target
, int refclk
, intel_clock_t
*match_clock
,
763 intel_clock_t
*best_clock
)
765 struct drm_device
*dev
= crtc
->dev
;
767 unsigned int bestppm
= 1000000;
768 /* min update 19.2 MHz */
769 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
772 target
*= 5; /* fast clock */
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
778 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
779 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
780 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
781 clock
.p
= clock
.p1
* clock
.p2
;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
784 unsigned int ppm
, diff
;
786 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
789 vlv_clock(refclk
, &clock
);
791 if (!intel_PLL_is_valid(dev
, limit
,
795 diff
= abs(clock
.dot
- target
);
796 ppm
= div_u64(1000000ULL * diff
, target
);
798 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
804 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
818 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
819 int target
, int refclk
, intel_clock_t
*match_clock
,
820 intel_clock_t
*best_clock
)
822 struct drm_device
*dev
= crtc
->dev
;
827 memset(best_clock
, 0, sizeof(*best_clock
));
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
834 clock
.n
= 1, clock
.m1
= 2;
835 target
*= 5; /* fast clock */
837 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
838 for (clock
.p2
= limit
->p2
.p2_fast
;
839 clock
.p2
>= limit
->p2
.p2_slow
;
840 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
842 clock
.p
= clock
.p1
* clock
.p2
;
844 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
845 clock
.n
) << 22, refclk
* clock
.m1
);
847 if (m2
> INT_MAX
/clock
.m1
)
852 chv_clock(refclk
, &clock
);
854 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
857 /* based on hardware requirement, prefer bigger p
859 if (clock
.p
> best_clock
->p
) {
869 bool intel_crtc_active(struct drm_crtc
*crtc
)
871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
882 return intel_crtc
->active
&& crtc
->primary
->fb
&&
883 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
886 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
889 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
892 return intel_crtc
->config
.cpu_transcoder
;
895 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
898 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
900 frame
= I915_READ(frame_reg
);
902 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
908 * intel_wait_for_vblank - wait for vblank on a given pipe
910 * @pipe: pipe to wait for
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
918 int pipestat_reg
= PIPESTAT(pipe
);
920 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
921 g4x_wait_for_vblank(dev
, pipe
);
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
938 I915_WRITE(pipestat_reg
,
939 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg
) &
943 PIPE_VBLANK_INTERRUPT_STATUS
,
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
949 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 u32 reg
= PIPEDSL(pipe
);
957 line_mask
= DSL_LINEMASK_GEN2
;
959 line_mask
= DSL_LINEMASK_GEN3
;
961 line1
= I915_READ(reg
) & line_mask
;
963 line2
= I915_READ(reg
) & line_mask
;
965 return line1
== line2
;
969 * intel_wait_for_pipe_off - wait for pipe to turn off
970 * @crtc: crtc whose pipe to wait for
972 * After disabling a pipe, we can't wait for vblank in the usual way,
973 * spinning on the vblank interrupt status bit, since we won't actually
974 * see an interrupt when the pipe is disabled.
977 * wait for the pipe register state bit to turn off
980 * wait for the display line value to settle (it usually
981 * ends up stopping at the start of the next frame).
984 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
986 struct drm_device
*dev
= crtc
->base
.dev
;
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
989 enum pipe pipe
= crtc
->pipe
;
991 if (INTEL_INFO(dev
)->gen
>= 4) {
992 int reg
= PIPECONF(cpu_transcoder
);
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
997 WARN(1, "pipe_off wait timed out\n");
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1010 * Returns true if @port is connected, false otherwise.
1012 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1013 struct intel_digital_port
*port
)
1017 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1018 switch (port
->port
) {
1020 bit
= SDE_PORTB_HOTPLUG
;
1023 bit
= SDE_PORTC_HOTPLUG
;
1026 bit
= SDE_PORTD_HOTPLUG
;
1032 switch (port
->port
) {
1034 bit
= SDE_PORTB_HOTPLUG_CPT
;
1037 bit
= SDE_PORTC_HOTPLUG_CPT
;
1040 bit
= SDE_PORTD_HOTPLUG_CPT
;
1047 return I915_READ(SDEISR
) & bit
;
1050 static const char *state_string(bool enabled
)
1052 return enabled
? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private
*dev_priv
,
1057 enum pipe pipe
, bool state
)
1064 val
= I915_READ(reg
);
1065 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1066 WARN(cur_state
!= state
,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state
), state_string(cur_state
));
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1077 mutex_lock(&dev_priv
->dpio_lock
);
1078 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1079 mutex_unlock(&dev_priv
->dpio_lock
);
1081 cur_state
= val
& DSI_PLL_VCO_EN
;
1082 WARN(cur_state
!= state
,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state
), state_string(cur_state
));
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1089 struct intel_shared_dpll
*
1090 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1092 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1094 if (crtc
->config
.shared_dpll
< 0)
1097 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1101 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1102 struct intel_shared_dpll
*pll
,
1106 struct intel_dpll_hw_state hw_state
;
1109 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1112 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1113 WARN(cur_state
!= state
,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll
->name
, state_string(state
), state_string(cur_state
));
1118 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1119 enum pipe pipe
, bool state
)
1124 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1127 if (HAS_DDI(dev_priv
->dev
)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1130 val
= I915_READ(reg
);
1131 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1133 reg
= FDI_TX_CTL(pipe
);
1134 val
= I915_READ(reg
);
1135 cur_state
= !!(val
& FDI_TX_ENABLE
);
1137 WARN(cur_state
!= state
,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state
), state_string(cur_state
));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1151 reg
= FDI_RX_CTL(pipe
);
1152 val
= I915_READ(reg
);
1153 cur_state
= !!(val
& FDI_RX_ENABLE
);
1154 WARN(cur_state
!= state
,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state
), state_string(cur_state
));
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv
->dev
))
1175 reg
= FDI_TX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1181 enum pipe pipe
, bool state
)
1187 reg
= FDI_RX_CTL(pipe
);
1188 val
= I915_READ(reg
);
1189 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1190 WARN(cur_state
!= state
,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state
), state_string(cur_state
));
1195 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1198 struct drm_device
*dev
= dev_priv
->dev
;
1201 enum pipe panel_pipe
= PIPE_A
;
1204 if (WARN_ON(HAS_DDI(dev
)))
1207 if (HAS_PCH_SPLIT(dev
)) {
1210 pp_reg
= PCH_PP_CONTROL
;
1211 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1213 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1214 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1215 panel_pipe
= PIPE_B
;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev
)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1222 pp_reg
= PP_CONTROL
;
1223 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1224 panel_pipe
= PIPE_B
;
1227 val
= I915_READ(pp_reg
);
1228 if (!(val
& PANEL_POWER_ON
) ||
1229 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1232 WARN(panel_pipe
== pipe
&& locked
,
1233 "panel assertion failure, pipe %c regs locked\n",
1237 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1238 enum pipe pipe
, bool state
)
1240 struct drm_device
*dev
= dev_priv
->dev
;
1243 if (IS_845G(dev
) || IS_I865G(dev
))
1244 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1246 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1248 WARN(cur_state
!= state
,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1255 void assert_pipe(struct drm_i915_private
*dev_priv
,
1256 enum pipe pipe
, bool state
)
1261 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1264 /* if we need the pipe quirk it must be always on */
1265 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1266 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1269 if (!intel_display_power_enabled(dev_priv
,
1270 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1273 reg
= PIPECONF(cpu_transcoder
);
1274 val
= I915_READ(reg
);
1275 cur_state
= !!(val
& PIPECONF_ENABLE
);
1278 WARN(cur_state
!= state
,
1279 "pipe %c assertion failure (expected %s, current %s)\n",
1280 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1283 static void assert_plane(struct drm_i915_private
*dev_priv
,
1284 enum plane plane
, bool state
)
1290 reg
= DSPCNTR(plane
);
1291 val
= I915_READ(reg
);
1292 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1293 WARN(cur_state
!= state
,
1294 "plane %c assertion failure (expected %s, current %s)\n",
1295 plane_name(plane
), state_string(state
), state_string(cur_state
));
1298 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1299 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1301 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1304 struct drm_device
*dev
= dev_priv
->dev
;
1309 /* Primary planes are fixed to pipes on gen4+ */
1310 if (INTEL_INFO(dev
)->gen
>= 4) {
1311 reg
= DSPCNTR(pipe
);
1312 val
= I915_READ(reg
);
1313 WARN(val
& DISPLAY_PLANE_ENABLE
,
1314 "plane %c assertion failure, should be disabled but not\n",
1319 /* Need to check both planes against the pipe */
1320 for_each_pipe(dev_priv
, i
) {
1322 val
= I915_READ(reg
);
1323 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1324 DISPPLANE_SEL_PIPE_SHIFT
;
1325 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1326 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1327 plane_name(i
), pipe_name(pipe
));
1331 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1334 struct drm_device
*dev
= dev_priv
->dev
;
1338 if (IS_VALLEYVIEW(dev
)) {
1339 for_each_sprite(pipe
, sprite
) {
1340 reg
= SPCNTR(pipe
, sprite
);
1341 val
= I915_READ(reg
);
1342 WARN(val
& SP_ENABLE
,
1343 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1344 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1346 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1348 val
= I915_READ(reg
);
1349 WARN(val
& SPRITE_ENABLE
,
1350 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1351 plane_name(pipe
), pipe_name(pipe
));
1352 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1353 reg
= DVSCNTR(pipe
);
1354 val
= I915_READ(reg
);
1355 WARN(val
& DVS_ENABLE
,
1356 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1357 plane_name(pipe
), pipe_name(pipe
));
1361 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1363 if (WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1364 drm_crtc_vblank_put(crtc
);
1367 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1372 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1374 val
= I915_READ(PCH_DREF_CONTROL
);
1375 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1376 DREF_SUPERSPREAD_SOURCE_MASK
));
1377 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1380 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1387 reg
= PCH_TRANSCONF(pipe
);
1388 val
= I915_READ(reg
);
1389 enabled
= !!(val
& TRANS_ENABLE
);
1391 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1395 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1396 enum pipe pipe
, u32 port_sel
, u32 val
)
1398 if ((val
& DP_PORT_EN
) == 0)
1401 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1402 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1403 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1404 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1406 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1407 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1410 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1416 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1417 enum pipe pipe
, u32 val
)
1419 if ((val
& SDVO_ENABLE
) == 0)
1422 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1423 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1425 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1426 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1429 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1435 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1436 enum pipe pipe
, u32 val
)
1438 if ((val
& LVDS_PORT_EN
) == 0)
1441 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1442 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1445 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1451 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1452 enum pipe pipe
, u32 val
)
1454 if ((val
& ADPA_DAC_ENABLE
) == 0)
1456 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1457 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1460 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1466 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1467 enum pipe pipe
, int reg
, u32 port_sel
)
1469 u32 val
= I915_READ(reg
);
1470 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1471 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1472 reg
, pipe_name(pipe
));
1474 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1475 && (val
& DP_PIPEB_SELECT
),
1476 "IBX PCH dp port still using transcoder B\n");
1479 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1480 enum pipe pipe
, int reg
)
1482 u32 val
= I915_READ(reg
);
1483 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1484 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1485 reg
, pipe_name(pipe
));
1487 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1488 && (val
& SDVO_PIPE_B_SELECT
),
1489 "IBX PCH hdmi port still using transcoder B\n");
1492 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1498 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1499 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1500 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1503 val
= I915_READ(reg
);
1504 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1505 "PCH VGA enabled on transcoder %c, should be disabled\n",
1509 val
= I915_READ(reg
);
1510 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1511 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1514 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1515 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1516 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1519 static void intel_init_dpio(struct drm_device
*dev
)
1521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 if (!IS_VALLEYVIEW(dev
))
1527 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1528 * CHV x1 PHY (DP/HDMI D)
1529 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1531 if (IS_CHERRYVIEW(dev
)) {
1532 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1533 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1535 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1539 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1541 struct drm_device
*dev
= crtc
->base
.dev
;
1542 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1543 int reg
= DPLL(crtc
->pipe
);
1544 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1546 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1548 /* No really, not for ILK+ */
1549 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1551 /* PLL is protected by panel, make sure we can write it */
1552 if (IS_MOBILE(dev_priv
->dev
))
1553 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1555 I915_WRITE(reg
, dpll
);
1559 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1560 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1562 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1563 POSTING_READ(DPLL_MD(crtc
->pipe
));
1565 /* We do this three times for luck */
1566 I915_WRITE(reg
, dpll
);
1568 udelay(150); /* wait for warmup */
1569 I915_WRITE(reg
, dpll
);
1571 udelay(150); /* wait for warmup */
1572 I915_WRITE(reg
, dpll
);
1574 udelay(150); /* wait for warmup */
1577 static void chv_enable_pll(struct intel_crtc
*crtc
)
1579 struct drm_device
*dev
= crtc
->base
.dev
;
1580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1581 int pipe
= crtc
->pipe
;
1582 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1585 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1587 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1589 mutex_lock(&dev_priv
->dpio_lock
);
1591 /* Enable back the 10bit clock to display controller */
1592 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1593 tmp
|= DPIO_DCLKP_EN
;
1594 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1597 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1602 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1604 /* Check PLL is locked */
1605 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1606 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1608 /* not sure when this should be written */
1609 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1610 POSTING_READ(DPLL_MD(pipe
));
1612 mutex_unlock(&dev_priv
->dpio_lock
);
1615 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1617 struct drm_device
*dev
= crtc
->base
.dev
;
1618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1619 int reg
= DPLL(crtc
->pipe
);
1620 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1622 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1624 /* No really, not for ILK+ */
1625 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1627 /* PLL is protected by panel, make sure we can write it */
1628 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1629 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1631 I915_WRITE(reg
, dpll
);
1633 /* Wait for the clocks to stabilize. */
1637 if (INTEL_INFO(dev
)->gen
>= 4) {
1638 I915_WRITE(DPLL_MD(crtc
->pipe
),
1639 crtc
->config
.dpll_hw_state
.dpll_md
);
1641 /* The pixel multiplier can only be updated once the
1642 * DPLL is enabled and the clocks are stable.
1644 * So write it again.
1646 I915_WRITE(reg
, dpll
);
1649 /* We do this three times for luck */
1650 I915_WRITE(reg
, dpll
);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg
, dpll
);
1655 udelay(150); /* wait for warmup */
1656 I915_WRITE(reg
, dpll
);
1658 udelay(150); /* wait for warmup */
1662 * i9xx_disable_pll - disable a PLL
1663 * @dev_priv: i915 private structure
1664 * @pipe: pipe PLL to disable
1666 * Disable the PLL for @pipe, making sure the pipe is off first.
1668 * Note! This is for pre-ILK only.
1670 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1672 /* Don't disable pipe or pipe PLLs if needed */
1673 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1674 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1677 /* Make sure the pipe isn't still relying on us */
1678 assert_pipe_disabled(dev_priv
, pipe
);
1680 I915_WRITE(DPLL(pipe
), 0);
1681 POSTING_READ(DPLL(pipe
));
1684 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1688 /* Make sure the pipe isn't still relying on us */
1689 assert_pipe_disabled(dev_priv
, pipe
);
1692 * Leave integrated clock source and reference clock enabled for pipe B.
1693 * The latter is needed for VGA hotplug / manual detection.
1696 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1697 I915_WRITE(DPLL(pipe
), val
);
1698 POSTING_READ(DPLL(pipe
));
1702 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1704 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1707 /* Make sure the pipe isn't still relying on us */
1708 assert_pipe_disabled(dev_priv
, pipe
);
1710 /* Set PLL en = 0 */
1711 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1713 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1714 I915_WRITE(DPLL(pipe
), val
);
1715 POSTING_READ(DPLL(pipe
));
1717 mutex_lock(&dev_priv
->dpio_lock
);
1719 /* Disable 10bit clock to display controller */
1720 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1721 val
&= ~DPIO_DCLKP_EN
;
1722 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1724 /* disable left/right clock distribution */
1725 if (pipe
!= PIPE_B
) {
1726 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1727 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1728 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1730 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1731 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1732 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1735 mutex_unlock(&dev_priv
->dpio_lock
);
1738 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1739 struct intel_digital_port
*dport
)
1744 switch (dport
->port
) {
1746 port_mask
= DPLL_PORTB_READY_MASK
;
1750 port_mask
= DPLL_PORTC_READY_MASK
;
1754 port_mask
= DPLL_PORTD_READY_MASK
;
1755 dpll_reg
= DPIO_PHY_STATUS
;
1761 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1762 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1763 port_name(dport
->port
), I915_READ(dpll_reg
));
1766 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1768 struct drm_device
*dev
= crtc
->base
.dev
;
1769 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1770 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1772 if (WARN_ON(pll
== NULL
))
1775 WARN_ON(!pll
->refcount
);
1776 if (pll
->active
== 0) {
1777 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1779 assert_shared_dpll_disabled(dev_priv
, pll
);
1781 pll
->mode_set(dev_priv
, pll
);
1786 * intel_enable_shared_dpll - enable PCH PLL
1787 * @dev_priv: i915 private structure
1788 * @pipe: pipe PLL to enable
1790 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1791 * drives the transcoder clock.
1793 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1795 struct drm_device
*dev
= crtc
->base
.dev
;
1796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1797 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1799 if (WARN_ON(pll
== NULL
))
1802 if (WARN_ON(pll
->refcount
== 0))
1805 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1806 pll
->name
, pll
->active
, pll
->on
,
1807 crtc
->base
.base
.id
);
1809 if (pll
->active
++) {
1811 assert_shared_dpll_enabled(dev_priv
, pll
);
1816 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1818 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1819 pll
->enable(dev_priv
, pll
);
1823 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1825 struct drm_device
*dev
= crtc
->base
.dev
;
1826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1827 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1829 /* PCH only available on ILK+ */
1830 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1831 if (WARN_ON(pll
== NULL
))
1834 if (WARN_ON(pll
->refcount
== 0))
1837 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1838 pll
->name
, pll
->active
, pll
->on
,
1839 crtc
->base
.base
.id
);
1841 if (WARN_ON(pll
->active
== 0)) {
1842 assert_shared_dpll_disabled(dev_priv
, pll
);
1846 assert_shared_dpll_enabled(dev_priv
, pll
);
1851 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1852 pll
->disable(dev_priv
, pll
);
1855 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1858 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1861 struct drm_device
*dev
= dev_priv
->dev
;
1862 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1863 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1864 uint32_t reg
, val
, pipeconf_val
;
1866 /* PCH only available on ILK+ */
1867 BUG_ON(!HAS_PCH_SPLIT(dev
));
1869 /* Make sure PCH DPLL is enabled */
1870 assert_shared_dpll_enabled(dev_priv
,
1871 intel_crtc_to_shared_dpll(intel_crtc
));
1873 /* FDI must be feeding us bits for PCH ports */
1874 assert_fdi_tx_enabled(dev_priv
, pipe
);
1875 assert_fdi_rx_enabled(dev_priv
, pipe
);
1877 if (HAS_PCH_CPT(dev
)) {
1878 /* Workaround: Set the timing override bit before enabling the
1879 * pch transcoder. */
1880 reg
= TRANS_CHICKEN2(pipe
);
1881 val
= I915_READ(reg
);
1882 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1883 I915_WRITE(reg
, val
);
1886 reg
= PCH_TRANSCONF(pipe
);
1887 val
= I915_READ(reg
);
1888 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1890 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1892 * make the BPC in transcoder be consistent with
1893 * that in pipeconf reg.
1895 val
&= ~PIPECONF_BPC_MASK
;
1896 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1899 val
&= ~TRANS_INTERLACE_MASK
;
1900 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1901 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1902 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1903 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1905 val
|= TRANS_INTERLACED
;
1907 val
|= TRANS_PROGRESSIVE
;
1909 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1910 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1911 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1914 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1915 enum transcoder cpu_transcoder
)
1917 u32 val
, pipeconf_val
;
1919 /* PCH only available on ILK+ */
1920 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
1922 /* FDI must be feeding us bits for PCH ports */
1923 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1924 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1926 /* Workaround: set timing override bit. */
1927 val
= I915_READ(_TRANSA_CHICKEN2
);
1928 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1929 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1932 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1934 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1935 PIPECONF_INTERLACED_ILK
)
1936 val
|= TRANS_INTERLACED
;
1938 val
|= TRANS_PROGRESSIVE
;
1940 I915_WRITE(LPT_TRANSCONF
, val
);
1941 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1942 DRM_ERROR("Failed to enable PCH transcoder\n");
1945 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1948 struct drm_device
*dev
= dev_priv
->dev
;
1951 /* FDI relies on the transcoder */
1952 assert_fdi_tx_disabled(dev_priv
, pipe
);
1953 assert_fdi_rx_disabled(dev_priv
, pipe
);
1955 /* Ports must be off as well */
1956 assert_pch_ports_disabled(dev_priv
, pipe
);
1958 reg
= PCH_TRANSCONF(pipe
);
1959 val
= I915_READ(reg
);
1960 val
&= ~TRANS_ENABLE
;
1961 I915_WRITE(reg
, val
);
1962 /* wait for PCH transcoder off, transcoder state */
1963 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1964 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1966 if (!HAS_PCH_IBX(dev
)) {
1967 /* Workaround: Clear the timing override chicken bit again. */
1968 reg
= TRANS_CHICKEN2(pipe
);
1969 val
= I915_READ(reg
);
1970 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1971 I915_WRITE(reg
, val
);
1975 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1979 val
= I915_READ(LPT_TRANSCONF
);
1980 val
&= ~TRANS_ENABLE
;
1981 I915_WRITE(LPT_TRANSCONF
, val
);
1982 /* wait for PCH transcoder off, transcoder state */
1983 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1984 DRM_ERROR("Failed to disable PCH transcoder\n");
1986 /* Workaround: clear timing override bit. */
1987 val
= I915_READ(_TRANSA_CHICKEN2
);
1988 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1989 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1993 * intel_enable_pipe - enable a pipe, asserting requirements
1994 * @crtc: crtc responsible for the pipe
1996 * Enable @crtc's pipe, making sure that various hardware specific requirements
1997 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1999 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2001 struct drm_device
*dev
= crtc
->base
.dev
;
2002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2003 enum pipe pipe
= crtc
->pipe
;
2004 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2006 enum pipe pch_transcoder
;
2010 assert_planes_disabled(dev_priv
, pipe
);
2011 assert_cursor_disabled(dev_priv
, pipe
);
2012 assert_sprites_disabled(dev_priv
, pipe
);
2014 if (HAS_PCH_LPT(dev_priv
->dev
))
2015 pch_transcoder
= TRANSCODER_A
;
2017 pch_transcoder
= pipe
;
2020 * A pipe without a PLL won't actually be able to drive bits from
2021 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2024 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2025 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2026 assert_dsi_pll_enabled(dev_priv
);
2028 assert_pll_enabled(dev_priv
, pipe
);
2030 if (crtc
->config
.has_pch_encoder
) {
2031 /* if driving the PCH, we need FDI enabled */
2032 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2033 assert_fdi_tx_pll_enabled(dev_priv
,
2034 (enum pipe
) cpu_transcoder
);
2036 /* FIXME: assert CPU port conditions for SNB+ */
2039 reg
= PIPECONF(cpu_transcoder
);
2040 val
= I915_READ(reg
);
2041 if (val
& PIPECONF_ENABLE
) {
2042 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2043 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2047 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2052 * intel_disable_pipe - disable a pipe, asserting requirements
2053 * @crtc: crtc whose pipes is to be disabled
2055 * Disable the pipe of @crtc, making sure that various hardware
2056 * specific requirements are met, if applicable, e.g. plane
2057 * disabled, panel fitter off, etc.
2059 * Will wait until the pipe has shut down before returning.
2061 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2063 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2064 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
2065 enum pipe pipe
= crtc
->pipe
;
2070 * Make sure planes won't keep trying to pump pixels to us,
2071 * or we might hang the display.
2073 assert_planes_disabled(dev_priv
, pipe
);
2074 assert_cursor_disabled(dev_priv
, pipe
);
2075 assert_sprites_disabled(dev_priv
, pipe
);
2077 reg
= PIPECONF(cpu_transcoder
);
2078 val
= I915_READ(reg
);
2079 if ((val
& PIPECONF_ENABLE
) == 0)
2083 * Double wide has implications for planes
2084 * so best keep it disabled when not needed.
2086 if (crtc
->config
.double_wide
)
2087 val
&= ~PIPECONF_DOUBLE_WIDE
;
2089 /* Don't disable pipe or pipe PLLs if needed */
2090 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2091 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2092 val
&= ~PIPECONF_ENABLE
;
2094 I915_WRITE(reg
, val
);
2095 if ((val
& PIPECONF_ENABLE
) == 0)
2096 intel_wait_for_pipe_off(crtc
);
2100 * Plane regs are double buffered, going from enabled->disabled needs a
2101 * trigger in order to latch. The display address reg provides this.
2103 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2106 struct drm_device
*dev
= dev_priv
->dev
;
2107 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2109 I915_WRITE(reg
, I915_READ(reg
));
2114 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2115 * @plane: plane to be enabled
2116 * @crtc: crtc for the plane
2118 * Enable @plane on @crtc, making sure that the pipe is running first.
2120 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2121 struct drm_crtc
*crtc
)
2123 struct drm_device
*dev
= plane
->dev
;
2124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2125 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2127 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2128 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2130 if (intel_crtc
->primary_enabled
)
2133 intel_crtc
->primary_enabled
= true;
2135 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2139 * BDW signals flip done immediately if the plane
2140 * is disabled, even if the plane enable is already
2141 * armed to occur at the next vblank :(
2143 if (IS_BROADWELL(dev
))
2144 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2148 * intel_disable_primary_hw_plane - disable the primary hardware plane
2149 * @plane: plane to be disabled
2150 * @crtc: crtc for the plane
2152 * Disable @plane on @crtc, making sure that the pipe is running first.
2154 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2155 struct drm_crtc
*crtc
)
2157 struct drm_device
*dev
= plane
->dev
;
2158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2159 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2161 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2163 if (!intel_crtc
->primary_enabled
)
2166 intel_crtc
->primary_enabled
= false;
2168 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2172 static bool need_vtd_wa(struct drm_device
*dev
)
2174 #ifdef CONFIG_INTEL_IOMMU
2175 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2181 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2185 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2186 return ALIGN(height
, tile_height
);
2190 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2191 struct drm_i915_gem_object
*obj
,
2192 struct intel_engine_cs
*pipelined
)
2194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2198 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2200 switch (obj
->tiling_mode
) {
2201 case I915_TILING_NONE
:
2202 if (INTEL_INFO(dev
)->gen
>= 9)
2203 alignment
= 256 * 1024;
2204 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2205 alignment
= 128 * 1024;
2206 else if (INTEL_INFO(dev
)->gen
>= 4)
2207 alignment
= 4 * 1024;
2209 alignment
= 64 * 1024;
2212 if (INTEL_INFO(dev
)->gen
>= 9)
2213 alignment
= 256 * 1024;
2215 /* pin() will align the object as required by fence */
2220 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2226 /* Note that the w/a also requires 64 PTE of padding following the
2227 * bo. We currently fill all unused PTE with the shadow page and so
2228 * we should always have valid PTE following the scanout preventing
2231 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2232 alignment
= 256 * 1024;
2235 * Global gtt pte registers are special registers which actually forward
2236 * writes to a chunk of system memory. Which means that there is no risk
2237 * that the register values disappear as soon as we call
2238 * intel_runtime_pm_put(), so it is correct to wrap only the
2239 * pin/unpin/fence and not more.
2241 intel_runtime_pm_get(dev_priv
);
2243 dev_priv
->mm
.interruptible
= false;
2244 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2246 goto err_interruptible
;
2248 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2249 * fence, whereas 965+ only requires a fence if using
2250 * framebuffer compression. For simplicity, we always install
2251 * a fence as the cost is not that onerous.
2253 ret
= i915_gem_object_get_fence(obj
);
2257 i915_gem_object_pin_fence(obj
);
2259 dev_priv
->mm
.interruptible
= true;
2260 intel_runtime_pm_put(dev_priv
);
2264 i915_gem_object_unpin_from_display_plane(obj
);
2266 dev_priv
->mm
.interruptible
= true;
2267 intel_runtime_pm_put(dev_priv
);
2271 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2273 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2275 i915_gem_object_unpin_fence(obj
);
2276 i915_gem_object_unpin_from_display_plane(obj
);
2279 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2280 * is assumed to be a power-of-two. */
2281 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2282 unsigned int tiling_mode
,
2286 if (tiling_mode
!= I915_TILING_NONE
) {
2287 unsigned int tile_rows
, tiles
;
2292 tiles
= *x
/ (512/cpp
);
2295 return tile_rows
* pitch
* 8 + tiles
* 4096;
2297 unsigned int offset
;
2299 offset
= *y
* pitch
+ *x
* cpp
;
2301 *x
= (offset
& 4095) / cpp
;
2302 return offset
& -4096;
2306 int intel_format_to_fourcc(int format
)
2309 case DISPPLANE_8BPP
:
2310 return DRM_FORMAT_C8
;
2311 case DISPPLANE_BGRX555
:
2312 return DRM_FORMAT_XRGB1555
;
2313 case DISPPLANE_BGRX565
:
2314 return DRM_FORMAT_RGB565
;
2316 case DISPPLANE_BGRX888
:
2317 return DRM_FORMAT_XRGB8888
;
2318 case DISPPLANE_RGBX888
:
2319 return DRM_FORMAT_XBGR8888
;
2320 case DISPPLANE_BGRX101010
:
2321 return DRM_FORMAT_XRGB2101010
;
2322 case DISPPLANE_RGBX101010
:
2323 return DRM_FORMAT_XBGR2101010
;
2327 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2328 struct intel_plane_config
*plane_config
)
2330 struct drm_device
*dev
= crtc
->base
.dev
;
2331 struct drm_i915_gem_object
*obj
= NULL
;
2332 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2333 u32 base
= plane_config
->base
;
2335 if (plane_config
->size
== 0)
2338 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2339 plane_config
->size
);
2343 if (plane_config
->tiled
) {
2344 obj
->tiling_mode
= I915_TILING_X
;
2345 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2348 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2349 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2350 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2351 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2353 mutex_lock(&dev
->struct_mutex
);
2355 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2357 DRM_DEBUG_KMS("intel fb init failed\n");
2361 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2362 mutex_unlock(&dev
->struct_mutex
);
2364 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2368 drm_gem_object_unreference(&obj
->base
);
2369 mutex_unlock(&dev
->struct_mutex
);
2373 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2374 struct intel_plane_config
*plane_config
)
2376 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2378 struct intel_crtc
*i
;
2379 struct drm_i915_gem_object
*obj
;
2381 if (!intel_crtc
->base
.primary
->fb
)
2384 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2387 kfree(intel_crtc
->base
.primary
->fb
);
2388 intel_crtc
->base
.primary
->fb
= NULL
;
2391 * Failed to alloc the obj, check to see if we should share
2392 * an fb with another CRTC instead
2394 for_each_crtc(dev
, c
) {
2395 i
= to_intel_crtc(c
);
2397 if (c
== &intel_crtc
->base
)
2403 obj
= intel_fb_obj(c
->primary
->fb
);
2407 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2408 drm_framebuffer_reference(c
->primary
->fb
);
2409 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2410 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2416 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2417 struct drm_framebuffer
*fb
,
2420 struct drm_device
*dev
= crtc
->dev
;
2421 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2422 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2423 struct drm_i915_gem_object
*obj
;
2424 int plane
= intel_crtc
->plane
;
2425 unsigned long linear_offset
;
2427 u32 reg
= DSPCNTR(plane
);
2430 if (!intel_crtc
->primary_enabled
) {
2432 if (INTEL_INFO(dev
)->gen
>= 4)
2433 I915_WRITE(DSPSURF(plane
), 0);
2435 I915_WRITE(DSPADDR(plane
), 0);
2440 obj
= intel_fb_obj(fb
);
2441 if (WARN_ON(obj
== NULL
))
2444 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2446 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2448 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2450 if (INTEL_INFO(dev
)->gen
< 4) {
2451 if (intel_crtc
->pipe
== PIPE_B
)
2452 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2454 /* pipesrc and dspsize control the size that is scaled from,
2455 * which should always be the user's requested size.
2457 I915_WRITE(DSPSIZE(plane
),
2458 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2459 (intel_crtc
->config
.pipe_src_w
- 1));
2460 I915_WRITE(DSPPOS(plane
), 0);
2463 switch (fb
->pixel_format
) {
2465 dspcntr
|= DISPPLANE_8BPP
;
2467 case DRM_FORMAT_XRGB1555
:
2468 case DRM_FORMAT_ARGB1555
:
2469 dspcntr
|= DISPPLANE_BGRX555
;
2471 case DRM_FORMAT_RGB565
:
2472 dspcntr
|= DISPPLANE_BGRX565
;
2474 case DRM_FORMAT_XRGB8888
:
2475 case DRM_FORMAT_ARGB8888
:
2476 dspcntr
|= DISPPLANE_BGRX888
;
2478 case DRM_FORMAT_XBGR8888
:
2479 case DRM_FORMAT_ABGR8888
:
2480 dspcntr
|= DISPPLANE_RGBX888
;
2482 case DRM_FORMAT_XRGB2101010
:
2483 case DRM_FORMAT_ARGB2101010
:
2484 dspcntr
|= DISPPLANE_BGRX101010
;
2486 case DRM_FORMAT_XBGR2101010
:
2487 case DRM_FORMAT_ABGR2101010
:
2488 dspcntr
|= DISPPLANE_RGBX101010
;
2494 if (INTEL_INFO(dev
)->gen
>= 4 &&
2495 obj
->tiling_mode
!= I915_TILING_NONE
)
2496 dspcntr
|= DISPPLANE_TILED
;
2499 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2501 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2503 if (INTEL_INFO(dev
)->gen
>= 4) {
2504 intel_crtc
->dspaddr_offset
=
2505 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2508 linear_offset
-= intel_crtc
->dspaddr_offset
;
2510 intel_crtc
->dspaddr_offset
= linear_offset
;
2513 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2514 dspcntr
|= DISPPLANE_ROTATE_180
;
2516 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2517 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2519 /* Finding the last pixel of the last line of the display
2520 data and adding to linear_offset*/
2522 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2523 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2526 I915_WRITE(reg
, dspcntr
);
2528 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2529 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2531 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2532 if (INTEL_INFO(dev
)->gen
>= 4) {
2533 I915_WRITE(DSPSURF(plane
),
2534 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2535 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2536 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2538 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2542 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2543 struct drm_framebuffer
*fb
,
2546 struct drm_device
*dev
= crtc
->dev
;
2547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2548 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2549 struct drm_i915_gem_object
*obj
;
2550 int plane
= intel_crtc
->plane
;
2551 unsigned long linear_offset
;
2553 u32 reg
= DSPCNTR(plane
);
2556 if (!intel_crtc
->primary_enabled
) {
2558 I915_WRITE(DSPSURF(plane
), 0);
2563 obj
= intel_fb_obj(fb
);
2564 if (WARN_ON(obj
== NULL
))
2567 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2569 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2571 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2573 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2574 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2576 switch (fb
->pixel_format
) {
2578 dspcntr
|= DISPPLANE_8BPP
;
2580 case DRM_FORMAT_RGB565
:
2581 dspcntr
|= DISPPLANE_BGRX565
;
2583 case DRM_FORMAT_XRGB8888
:
2584 case DRM_FORMAT_ARGB8888
:
2585 dspcntr
|= DISPPLANE_BGRX888
;
2587 case DRM_FORMAT_XBGR8888
:
2588 case DRM_FORMAT_ABGR8888
:
2589 dspcntr
|= DISPPLANE_RGBX888
;
2591 case DRM_FORMAT_XRGB2101010
:
2592 case DRM_FORMAT_ARGB2101010
:
2593 dspcntr
|= DISPPLANE_BGRX101010
;
2595 case DRM_FORMAT_XBGR2101010
:
2596 case DRM_FORMAT_ABGR2101010
:
2597 dspcntr
|= DISPPLANE_RGBX101010
;
2603 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2604 dspcntr
|= DISPPLANE_TILED
;
2606 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2607 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2609 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2610 intel_crtc
->dspaddr_offset
=
2611 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2614 linear_offset
-= intel_crtc
->dspaddr_offset
;
2615 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2616 dspcntr
|= DISPPLANE_ROTATE_180
;
2618 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2619 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2620 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2622 /* Finding the last pixel of the last line of the display
2623 data and adding to linear_offset*/
2625 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2626 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2630 I915_WRITE(reg
, dspcntr
);
2632 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2633 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2635 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2636 I915_WRITE(DSPSURF(plane
),
2637 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2638 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2639 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2641 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2642 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2647 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2649 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2650 int x
, int y
, enum mode_set_atomic state
)
2652 struct drm_device
*dev
= crtc
->dev
;
2653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2655 if (dev_priv
->display
.disable_fbc
)
2656 dev_priv
->display
.disable_fbc(dev
);
2657 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2659 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2664 void intel_display_handle_reset(struct drm_device
*dev
)
2666 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2667 struct drm_crtc
*crtc
;
2670 * Flips in the rings have been nuked by the reset,
2671 * so complete all pending flips so that user space
2672 * will get its events and not get stuck.
2674 * Also update the base address of all primary
2675 * planes to the the last fb to make sure we're
2676 * showing the correct fb after a reset.
2678 * Need to make two loops over the crtcs so that we
2679 * don't try to grab a crtc mutex before the
2680 * pending_flip_queue really got woken up.
2683 for_each_crtc(dev
, crtc
) {
2684 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2685 enum plane plane
= intel_crtc
->plane
;
2687 intel_prepare_page_flip(dev
, plane
);
2688 intel_finish_page_flip_plane(dev
, plane
);
2691 for_each_crtc(dev
, crtc
) {
2692 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2694 drm_modeset_lock(&crtc
->mutex
, NULL
);
2696 * FIXME: Once we have proper support for primary planes (and
2697 * disabling them without disabling the entire crtc) allow again
2698 * a NULL crtc->primary->fb.
2700 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2701 dev_priv
->display
.update_primary_plane(crtc
,
2705 drm_modeset_unlock(&crtc
->mutex
);
2710 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2712 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2713 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2714 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2717 /* Big Hammer, we also need to ensure that any pending
2718 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2719 * current scanout is retired before unpinning the old
2722 * This should only fail upon a hung GPU, in which case we
2723 * can safely continue.
2725 dev_priv
->mm
.interruptible
= false;
2726 ret
= i915_gem_object_finish_gpu(obj
);
2727 dev_priv
->mm
.interruptible
= was_interruptible
;
2732 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2734 struct drm_device
*dev
= crtc
->dev
;
2735 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2736 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2737 unsigned long flags
;
2740 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2741 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2744 spin_lock_irqsave(&dev
->event_lock
, flags
);
2745 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2746 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2752 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2753 struct drm_framebuffer
*fb
)
2755 struct drm_device
*dev
= crtc
->dev
;
2756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2757 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2758 enum pipe pipe
= intel_crtc
->pipe
;
2759 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2760 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2761 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2764 if (intel_crtc_has_pending_flip(crtc
)) {
2765 DRM_ERROR("pipe is still busy with an old pageflip\n");
2771 DRM_ERROR("No FB bound\n");
2775 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2776 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2777 plane_name(intel_crtc
->plane
),
2778 INTEL_INFO(dev
)->num_pipes
);
2782 mutex_lock(&dev
->struct_mutex
);
2783 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2785 i915_gem_track_fb(old_obj
, obj
,
2786 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2787 mutex_unlock(&dev
->struct_mutex
);
2789 DRM_ERROR("pin & fence failed\n");
2794 * Update pipe size and adjust fitter if needed: the reason for this is
2795 * that in compute_mode_changes we check the native mode (not the pfit
2796 * mode) to see if we can flip rather than do a full mode set. In the
2797 * fastboot case, we'll flip, but if we don't update the pipesrc and
2798 * pfit state, we'll end up with a big fb scanned out into the wrong
2801 * To fix this properly, we need to hoist the checks up into
2802 * compute_mode_changes (or above), check the actual pfit state and
2803 * whether the platform allows pfit disable with pipe active, and only
2804 * then update the pipesrc and pfit state, even on the flip path.
2806 if (i915
.fastboot
) {
2807 const struct drm_display_mode
*adjusted_mode
=
2808 &intel_crtc
->config
.adjusted_mode
;
2810 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2811 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2812 (adjusted_mode
->crtc_vdisplay
- 1));
2813 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2814 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2815 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2816 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2817 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2818 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2820 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2821 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2824 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2826 if (intel_crtc
->active
)
2827 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2829 crtc
->primary
->fb
= fb
;
2834 if (intel_crtc
->active
&& old_fb
!= fb
)
2835 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2836 mutex_lock(&dev
->struct_mutex
);
2837 intel_unpin_fb_obj(old_obj
);
2838 mutex_unlock(&dev
->struct_mutex
);
2841 mutex_lock(&dev
->struct_mutex
);
2842 intel_update_fbc(dev
);
2843 mutex_unlock(&dev
->struct_mutex
);
2848 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2850 struct drm_device
*dev
= crtc
->dev
;
2851 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2852 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2853 int pipe
= intel_crtc
->pipe
;
2856 /* enable normal train */
2857 reg
= FDI_TX_CTL(pipe
);
2858 temp
= I915_READ(reg
);
2859 if (IS_IVYBRIDGE(dev
)) {
2860 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2861 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2863 temp
&= ~FDI_LINK_TRAIN_NONE
;
2864 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2866 I915_WRITE(reg
, temp
);
2868 reg
= FDI_RX_CTL(pipe
);
2869 temp
= I915_READ(reg
);
2870 if (HAS_PCH_CPT(dev
)) {
2871 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2872 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2874 temp
&= ~FDI_LINK_TRAIN_NONE
;
2875 temp
|= FDI_LINK_TRAIN_NONE
;
2877 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2879 /* wait one idle pattern time */
2883 /* IVB wants error correction enabled */
2884 if (IS_IVYBRIDGE(dev
))
2885 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2886 FDI_FE_ERRC_ENABLE
);
2889 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2891 return crtc
->base
.enabled
&& crtc
->active
&&
2892 crtc
->config
.has_pch_encoder
;
2895 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2898 struct intel_crtc
*pipe_B_crtc
=
2899 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2900 struct intel_crtc
*pipe_C_crtc
=
2901 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2905 * When everything is off disable fdi C so that we could enable fdi B
2906 * with all lanes. Note that we don't care about enabled pipes without
2907 * an enabled pch encoder.
2909 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2910 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2911 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2912 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2914 temp
= I915_READ(SOUTH_CHICKEN1
);
2915 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2916 DRM_DEBUG_KMS("disabling fdi C rx\n");
2917 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2921 /* The FDI link training functions for ILK/Ibexpeak. */
2922 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2924 struct drm_device
*dev
= crtc
->dev
;
2925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2926 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2927 int pipe
= intel_crtc
->pipe
;
2928 u32 reg
, temp
, tries
;
2930 /* FDI needs bits from pipe first */
2931 assert_pipe_enabled(dev_priv
, pipe
);
2933 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2935 reg
= FDI_RX_IMR(pipe
);
2936 temp
= I915_READ(reg
);
2937 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2938 temp
&= ~FDI_RX_BIT_LOCK
;
2939 I915_WRITE(reg
, temp
);
2943 /* enable CPU FDI TX and PCH FDI RX */
2944 reg
= FDI_TX_CTL(pipe
);
2945 temp
= I915_READ(reg
);
2946 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2947 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2948 temp
&= ~FDI_LINK_TRAIN_NONE
;
2949 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2950 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2952 reg
= FDI_RX_CTL(pipe
);
2953 temp
= I915_READ(reg
);
2954 temp
&= ~FDI_LINK_TRAIN_NONE
;
2955 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2956 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2961 /* Ironlake workaround, enable clock pointer after FDI enable*/
2962 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2963 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2964 FDI_RX_PHASE_SYNC_POINTER_EN
);
2966 reg
= FDI_RX_IIR(pipe
);
2967 for (tries
= 0; tries
< 5; tries
++) {
2968 temp
= I915_READ(reg
);
2969 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2971 if ((temp
& FDI_RX_BIT_LOCK
)) {
2972 DRM_DEBUG_KMS("FDI train 1 done.\n");
2973 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2978 DRM_ERROR("FDI train 1 fail!\n");
2981 reg
= FDI_TX_CTL(pipe
);
2982 temp
= I915_READ(reg
);
2983 temp
&= ~FDI_LINK_TRAIN_NONE
;
2984 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2985 I915_WRITE(reg
, temp
);
2987 reg
= FDI_RX_CTL(pipe
);
2988 temp
= I915_READ(reg
);
2989 temp
&= ~FDI_LINK_TRAIN_NONE
;
2990 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2991 I915_WRITE(reg
, temp
);
2996 reg
= FDI_RX_IIR(pipe
);
2997 for (tries
= 0; tries
< 5; tries
++) {
2998 temp
= I915_READ(reg
);
2999 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3001 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3002 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3003 DRM_DEBUG_KMS("FDI train 2 done.\n");
3008 DRM_ERROR("FDI train 2 fail!\n");
3010 DRM_DEBUG_KMS("FDI train done\n");
3014 static const int snb_b_fdi_train_param
[] = {
3015 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3016 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3017 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3018 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3021 /* The FDI link training functions for SNB/Cougarpoint. */
3022 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3024 struct drm_device
*dev
= crtc
->dev
;
3025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3026 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3027 int pipe
= intel_crtc
->pipe
;
3028 u32 reg
, temp
, i
, retry
;
3030 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3032 reg
= FDI_RX_IMR(pipe
);
3033 temp
= I915_READ(reg
);
3034 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3035 temp
&= ~FDI_RX_BIT_LOCK
;
3036 I915_WRITE(reg
, temp
);
3041 /* enable CPU FDI TX and PCH FDI RX */
3042 reg
= FDI_TX_CTL(pipe
);
3043 temp
= I915_READ(reg
);
3044 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3045 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3046 temp
&= ~FDI_LINK_TRAIN_NONE
;
3047 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3048 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3050 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3051 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3053 I915_WRITE(FDI_RX_MISC(pipe
),
3054 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3056 reg
= FDI_RX_CTL(pipe
);
3057 temp
= I915_READ(reg
);
3058 if (HAS_PCH_CPT(dev
)) {
3059 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3060 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3062 temp
&= ~FDI_LINK_TRAIN_NONE
;
3063 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3065 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3070 for (i
= 0; i
< 4; i
++) {
3071 reg
= FDI_TX_CTL(pipe
);
3072 temp
= I915_READ(reg
);
3073 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3074 temp
|= snb_b_fdi_train_param
[i
];
3075 I915_WRITE(reg
, temp
);
3080 for (retry
= 0; retry
< 5; retry
++) {
3081 reg
= FDI_RX_IIR(pipe
);
3082 temp
= I915_READ(reg
);
3083 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3084 if (temp
& FDI_RX_BIT_LOCK
) {
3085 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3086 DRM_DEBUG_KMS("FDI train 1 done.\n");
3095 DRM_ERROR("FDI train 1 fail!\n");
3098 reg
= FDI_TX_CTL(pipe
);
3099 temp
= I915_READ(reg
);
3100 temp
&= ~FDI_LINK_TRAIN_NONE
;
3101 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3103 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3105 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3107 I915_WRITE(reg
, temp
);
3109 reg
= FDI_RX_CTL(pipe
);
3110 temp
= I915_READ(reg
);
3111 if (HAS_PCH_CPT(dev
)) {
3112 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3113 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3115 temp
&= ~FDI_LINK_TRAIN_NONE
;
3116 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3118 I915_WRITE(reg
, temp
);
3123 for (i
= 0; i
< 4; i
++) {
3124 reg
= FDI_TX_CTL(pipe
);
3125 temp
= I915_READ(reg
);
3126 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3127 temp
|= snb_b_fdi_train_param
[i
];
3128 I915_WRITE(reg
, temp
);
3133 for (retry
= 0; retry
< 5; retry
++) {
3134 reg
= FDI_RX_IIR(pipe
);
3135 temp
= I915_READ(reg
);
3136 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3137 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3138 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3139 DRM_DEBUG_KMS("FDI train 2 done.\n");
3148 DRM_ERROR("FDI train 2 fail!\n");
3150 DRM_DEBUG_KMS("FDI train done.\n");
3153 /* Manual link training for Ivy Bridge A0 parts */
3154 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3156 struct drm_device
*dev
= crtc
->dev
;
3157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3158 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3159 int pipe
= intel_crtc
->pipe
;
3160 u32 reg
, temp
, i
, j
;
3162 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3164 reg
= FDI_RX_IMR(pipe
);
3165 temp
= I915_READ(reg
);
3166 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3167 temp
&= ~FDI_RX_BIT_LOCK
;
3168 I915_WRITE(reg
, temp
);
3173 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3174 I915_READ(FDI_RX_IIR(pipe
)));
3176 /* Try each vswing and preemphasis setting twice before moving on */
3177 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3178 /* disable first in case we need to retry */
3179 reg
= FDI_TX_CTL(pipe
);
3180 temp
= I915_READ(reg
);
3181 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3182 temp
&= ~FDI_TX_ENABLE
;
3183 I915_WRITE(reg
, temp
);
3185 reg
= FDI_RX_CTL(pipe
);
3186 temp
= I915_READ(reg
);
3187 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3188 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3189 temp
&= ~FDI_RX_ENABLE
;
3190 I915_WRITE(reg
, temp
);
3192 /* enable CPU FDI TX and PCH FDI RX */
3193 reg
= FDI_TX_CTL(pipe
);
3194 temp
= I915_READ(reg
);
3195 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3196 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3197 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3198 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3199 temp
|= snb_b_fdi_train_param
[j
/2];
3200 temp
|= FDI_COMPOSITE_SYNC
;
3201 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3203 I915_WRITE(FDI_RX_MISC(pipe
),
3204 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3206 reg
= FDI_RX_CTL(pipe
);
3207 temp
= I915_READ(reg
);
3208 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3209 temp
|= FDI_COMPOSITE_SYNC
;
3210 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3213 udelay(1); /* should be 0.5us */
3215 for (i
= 0; i
< 4; i
++) {
3216 reg
= FDI_RX_IIR(pipe
);
3217 temp
= I915_READ(reg
);
3218 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3220 if (temp
& FDI_RX_BIT_LOCK
||
3221 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3222 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3223 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3227 udelay(1); /* should be 0.5us */
3230 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3235 reg
= FDI_TX_CTL(pipe
);
3236 temp
= I915_READ(reg
);
3237 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3238 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3239 I915_WRITE(reg
, temp
);
3241 reg
= FDI_RX_CTL(pipe
);
3242 temp
= I915_READ(reg
);
3243 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3244 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3245 I915_WRITE(reg
, temp
);
3248 udelay(2); /* should be 1.5us */
3250 for (i
= 0; i
< 4; i
++) {
3251 reg
= FDI_RX_IIR(pipe
);
3252 temp
= I915_READ(reg
);
3253 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3255 if (temp
& FDI_RX_SYMBOL_LOCK
||
3256 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3257 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3258 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3262 udelay(2); /* should be 1.5us */
3265 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3269 DRM_DEBUG_KMS("FDI train done.\n");
3272 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3274 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3276 int pipe
= intel_crtc
->pipe
;
3280 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3281 reg
= FDI_RX_CTL(pipe
);
3282 temp
= I915_READ(reg
);
3283 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3284 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3285 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3286 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3291 /* Switch from Rawclk to PCDclk */
3292 temp
= I915_READ(reg
);
3293 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3298 /* Enable CPU FDI TX PLL, always on for Ironlake */
3299 reg
= FDI_TX_CTL(pipe
);
3300 temp
= I915_READ(reg
);
3301 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3302 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3309 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3311 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3312 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3313 int pipe
= intel_crtc
->pipe
;
3316 /* Switch from PCDclk to Rawclk */
3317 reg
= FDI_RX_CTL(pipe
);
3318 temp
= I915_READ(reg
);
3319 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3321 /* Disable CPU FDI TX PLL */
3322 reg
= FDI_TX_CTL(pipe
);
3323 temp
= I915_READ(reg
);
3324 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3329 reg
= FDI_RX_CTL(pipe
);
3330 temp
= I915_READ(reg
);
3331 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3333 /* Wait for the clocks to turn off. */
3338 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3340 struct drm_device
*dev
= crtc
->dev
;
3341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3342 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3343 int pipe
= intel_crtc
->pipe
;
3346 /* disable CPU FDI tx and PCH FDI rx */
3347 reg
= FDI_TX_CTL(pipe
);
3348 temp
= I915_READ(reg
);
3349 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3352 reg
= FDI_RX_CTL(pipe
);
3353 temp
= I915_READ(reg
);
3354 temp
&= ~(0x7 << 16);
3355 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3356 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3361 /* Ironlake workaround, disable clock pointer after downing FDI */
3362 if (HAS_PCH_IBX(dev
))
3363 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3365 /* still set train pattern 1 */
3366 reg
= FDI_TX_CTL(pipe
);
3367 temp
= I915_READ(reg
);
3368 temp
&= ~FDI_LINK_TRAIN_NONE
;
3369 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3370 I915_WRITE(reg
, temp
);
3372 reg
= FDI_RX_CTL(pipe
);
3373 temp
= I915_READ(reg
);
3374 if (HAS_PCH_CPT(dev
)) {
3375 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3376 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3378 temp
&= ~FDI_LINK_TRAIN_NONE
;
3379 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3381 /* BPC in FDI rx is consistent with that in PIPECONF */
3382 temp
&= ~(0x07 << 16);
3383 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3384 I915_WRITE(reg
, temp
);
3390 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3392 struct intel_crtc
*crtc
;
3394 /* Note that we don't need to be called with mode_config.lock here
3395 * as our list of CRTC objects is static for the lifetime of the
3396 * device and so cannot disappear as we iterate. Similarly, we can
3397 * happily treat the predicates as racy, atomic checks as userspace
3398 * cannot claim and pin a new fb without at least acquring the
3399 * struct_mutex and so serialising with us.
3401 for_each_intel_crtc(dev
, crtc
) {
3402 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3405 if (crtc
->unpin_work
)
3406 intel_wait_for_vblank(dev
, crtc
->pipe
);
3414 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3416 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3417 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3419 /* ensure that the unpin work is consistent wrt ->pending. */
3421 intel_crtc
->unpin_work
= NULL
;
3424 drm_send_vblank_event(intel_crtc
->base
.dev
,
3428 drm_crtc_vblank_put(&intel_crtc
->base
);
3430 wake_up_all(&dev_priv
->pending_flip_queue
);
3431 queue_work(dev_priv
->wq
, &work
->work
);
3433 trace_i915_flip_complete(intel_crtc
->plane
,
3434 work
->pending_flip_obj
);
3437 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3439 struct drm_device
*dev
= crtc
->dev
;
3440 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3442 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3443 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3444 !intel_crtc_has_pending_flip(crtc
),
3446 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3447 unsigned long flags
;
3449 spin_lock_irqsave(&dev
->event_lock
, flags
);
3450 if (intel_crtc
->unpin_work
) {
3451 WARN_ONCE(1, "Removing stuck page flip\n");
3452 page_flip_completed(intel_crtc
);
3454 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
3457 if (crtc
->primary
->fb
) {
3458 mutex_lock(&dev
->struct_mutex
);
3459 intel_finish_fb(crtc
->primary
->fb
);
3460 mutex_unlock(&dev
->struct_mutex
);
3464 /* Program iCLKIP clock to the desired frequency */
3465 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3467 struct drm_device
*dev
= crtc
->dev
;
3468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3469 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3470 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3473 mutex_lock(&dev_priv
->dpio_lock
);
3475 /* It is necessary to ungate the pixclk gate prior to programming
3476 * the divisors, and gate it back when it is done.
3478 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3480 /* Disable SSCCTL */
3481 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3482 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3486 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3487 if (clock
== 20000) {
3492 /* The iCLK virtual clock root frequency is in MHz,
3493 * but the adjusted_mode->crtc_clock in in KHz. To get the
3494 * divisors, it is necessary to divide one by another, so we
3495 * convert the virtual clock precision to KHz here for higher
3498 u32 iclk_virtual_root_freq
= 172800 * 1000;
3499 u32 iclk_pi_range
= 64;
3500 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3502 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3503 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3504 pi_value
= desired_divisor
% iclk_pi_range
;
3507 divsel
= msb_divisor_value
- 2;
3508 phaseinc
= pi_value
;
3511 /* This should not happen with any sane values */
3512 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3513 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3514 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3515 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3517 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3524 /* Program SSCDIVINTPHASE6 */
3525 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3526 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3527 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3528 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3529 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3530 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3531 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3532 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3534 /* Program SSCAUXDIV */
3535 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3536 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3537 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3538 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3540 /* Enable modulator and associated divider */
3541 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3542 temp
&= ~SBI_SSCCTL_DISABLE
;
3543 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3545 /* Wait for initialization time */
3548 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3550 mutex_unlock(&dev_priv
->dpio_lock
);
3553 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3554 enum pipe pch_transcoder
)
3556 struct drm_device
*dev
= crtc
->base
.dev
;
3557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3558 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3560 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3561 I915_READ(HTOTAL(cpu_transcoder
)));
3562 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3563 I915_READ(HBLANK(cpu_transcoder
)));
3564 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3565 I915_READ(HSYNC(cpu_transcoder
)));
3567 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3568 I915_READ(VTOTAL(cpu_transcoder
)));
3569 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3570 I915_READ(VBLANK(cpu_transcoder
)));
3571 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3572 I915_READ(VSYNC(cpu_transcoder
)));
3573 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3574 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3577 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3582 temp
= I915_READ(SOUTH_CHICKEN1
);
3583 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3586 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3587 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3589 temp
|= FDI_BC_BIFURCATION_SELECT
;
3590 DRM_DEBUG_KMS("enabling fdi C rx\n");
3591 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3592 POSTING_READ(SOUTH_CHICKEN1
);
3595 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3597 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3598 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3600 switch (intel_crtc
->pipe
) {
3604 if (intel_crtc
->config
.fdi_lanes
> 2)
3605 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3607 cpt_enable_fdi_bc_bifurcation(dev
);
3611 cpt_enable_fdi_bc_bifurcation(dev
);
3620 * Enable PCH resources required for PCH ports:
3622 * - FDI training & RX/TX
3623 * - update transcoder timings
3624 * - DP transcoding bits
3627 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3629 struct drm_device
*dev
= crtc
->dev
;
3630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3631 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3632 int pipe
= intel_crtc
->pipe
;
3635 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3637 if (IS_IVYBRIDGE(dev
))
3638 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3640 /* Write the TU size bits before fdi link training, so that error
3641 * detection works. */
3642 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3643 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3645 /* For PCH output, training FDI link */
3646 dev_priv
->display
.fdi_link_train(crtc
);
3648 /* We need to program the right clock selection before writing the pixel
3649 * mutliplier into the DPLL. */
3650 if (HAS_PCH_CPT(dev
)) {
3653 temp
= I915_READ(PCH_DPLL_SEL
);
3654 temp
|= TRANS_DPLL_ENABLE(pipe
);
3655 sel
= TRANS_DPLLB_SEL(pipe
);
3656 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3660 I915_WRITE(PCH_DPLL_SEL
, temp
);
3663 /* XXX: pch pll's can be enabled any time before we enable the PCH
3664 * transcoder, and we actually should do this to not upset any PCH
3665 * transcoder that already use the clock when we share it.
3667 * Note that enable_shared_dpll tries to do the right thing, but
3668 * get_shared_dpll unconditionally resets the pll - we need that to have
3669 * the right LVDS enable sequence. */
3670 intel_enable_shared_dpll(intel_crtc
);
3672 /* set transcoder timing, panel must allow it */
3673 assert_panel_unlocked(dev_priv
, pipe
);
3674 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3676 intel_fdi_normal_train(crtc
);
3678 /* For PCH DP, enable TRANS_DP_CTL */
3679 if (HAS_PCH_CPT(dev
) &&
3680 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3681 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3682 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3683 reg
= TRANS_DP_CTL(pipe
);
3684 temp
= I915_READ(reg
);
3685 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3686 TRANS_DP_SYNC_MASK
|
3688 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3689 TRANS_DP_ENH_FRAMING
);
3690 temp
|= bpc
<< 9; /* same format but at 11:9 */
3692 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3693 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3694 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3695 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3697 switch (intel_trans_dp_port_sel(crtc
)) {
3699 temp
|= TRANS_DP_PORT_SEL_B
;
3702 temp
|= TRANS_DP_PORT_SEL_C
;
3705 temp
|= TRANS_DP_PORT_SEL_D
;
3711 I915_WRITE(reg
, temp
);
3714 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3717 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3719 struct drm_device
*dev
= crtc
->dev
;
3720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3721 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3722 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3724 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3726 lpt_program_iclkip(crtc
);
3728 /* Set transcoder timing. */
3729 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3731 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3734 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3736 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3741 if (pll
->refcount
== 0) {
3742 WARN(1, "bad %s refcount\n", pll
->name
);
3746 if (--pll
->refcount
== 0) {
3748 WARN_ON(pll
->active
);
3751 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3754 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3756 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3757 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3758 enum intel_dpll_id i
;
3761 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3762 crtc
->base
.base
.id
, pll
->name
);
3763 intel_put_shared_dpll(crtc
);
3766 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3767 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3768 i
= (enum intel_dpll_id
) crtc
->pipe
;
3769 pll
= &dev_priv
->shared_dplls
[i
];
3771 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3772 crtc
->base
.base
.id
, pll
->name
);
3774 WARN_ON(pll
->refcount
);
3779 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3780 pll
= &dev_priv
->shared_dplls
[i
];
3782 /* Only want to check enabled timings first */
3783 if (pll
->refcount
== 0)
3786 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3787 sizeof(pll
->hw_state
)) == 0) {
3788 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3790 pll
->name
, pll
->refcount
, pll
->active
);
3796 /* Ok no matching timings, maybe there's a free one? */
3797 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3798 pll
= &dev_priv
->shared_dplls
[i
];
3799 if (pll
->refcount
== 0) {
3800 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3801 crtc
->base
.base
.id
, pll
->name
);
3809 if (pll
->refcount
== 0)
3810 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3812 crtc
->config
.shared_dpll
= i
;
3813 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3814 pipe_name(crtc
->pipe
));
3821 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3824 int dslreg
= PIPEDSL(pipe
);
3827 temp
= I915_READ(dslreg
);
3829 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3830 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3831 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3835 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3837 struct drm_device
*dev
= crtc
->base
.dev
;
3838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3839 int pipe
= crtc
->pipe
;
3841 if (crtc
->config
.pch_pfit
.enabled
) {
3842 /* Force use of hard-coded filter coefficients
3843 * as some pre-programmed values are broken,
3846 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3847 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3848 PF_PIPE_SEL_IVB(pipe
));
3850 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3851 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3852 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3856 static void intel_enable_planes(struct drm_crtc
*crtc
)
3858 struct drm_device
*dev
= crtc
->dev
;
3859 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3860 struct drm_plane
*plane
;
3861 struct intel_plane
*intel_plane
;
3863 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3864 intel_plane
= to_intel_plane(plane
);
3865 if (intel_plane
->pipe
== pipe
)
3866 intel_plane_restore(&intel_plane
->base
);
3870 static void intel_disable_planes(struct drm_crtc
*crtc
)
3872 struct drm_device
*dev
= crtc
->dev
;
3873 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3874 struct drm_plane
*plane
;
3875 struct intel_plane
*intel_plane
;
3877 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3878 intel_plane
= to_intel_plane(plane
);
3879 if (intel_plane
->pipe
== pipe
)
3880 intel_plane_disable(&intel_plane
->base
);
3884 void hsw_enable_ips(struct intel_crtc
*crtc
)
3886 struct drm_device
*dev
= crtc
->base
.dev
;
3887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3889 if (!crtc
->config
.ips_enabled
)
3892 /* We can only enable IPS after we enable a plane and wait for a vblank */
3893 intel_wait_for_vblank(dev
, crtc
->pipe
);
3895 assert_plane_enabled(dev_priv
, crtc
->plane
);
3896 if (IS_BROADWELL(dev
)) {
3897 mutex_lock(&dev_priv
->rps
.hw_lock
);
3898 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3899 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3900 /* Quoting Art Runyan: "its not safe to expect any particular
3901 * value in IPS_CTL bit 31 after enabling IPS through the
3902 * mailbox." Moreover, the mailbox may return a bogus state,
3903 * so we need to just enable it and continue on.
3906 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3907 /* The bit only becomes 1 in the next vblank, so this wait here
3908 * is essentially intel_wait_for_vblank. If we don't have this
3909 * and don't wait for vblanks until the end of crtc_enable, then
3910 * the HW state readout code will complain that the expected
3911 * IPS_CTL value is not the one we read. */
3912 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3913 DRM_ERROR("Timed out waiting for IPS enable\n");
3917 void hsw_disable_ips(struct intel_crtc
*crtc
)
3919 struct drm_device
*dev
= crtc
->base
.dev
;
3920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3922 if (!crtc
->config
.ips_enabled
)
3925 assert_plane_enabled(dev_priv
, crtc
->plane
);
3926 if (IS_BROADWELL(dev
)) {
3927 mutex_lock(&dev_priv
->rps
.hw_lock
);
3928 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3929 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3930 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3931 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3932 DRM_ERROR("Timed out waiting for IPS disable\n");
3934 I915_WRITE(IPS_CTL
, 0);
3935 POSTING_READ(IPS_CTL
);
3938 /* We need to wait for a vblank before we can disable the plane. */
3939 intel_wait_for_vblank(dev
, crtc
->pipe
);
3942 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3943 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3945 struct drm_device
*dev
= crtc
->dev
;
3946 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3947 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3948 enum pipe pipe
= intel_crtc
->pipe
;
3949 int palreg
= PALETTE(pipe
);
3951 bool reenable_ips
= false;
3953 /* The clocks have to be on to load the palette. */
3954 if (!crtc
->enabled
|| !intel_crtc
->active
)
3957 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3958 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3959 assert_dsi_pll_enabled(dev_priv
);
3961 assert_pll_enabled(dev_priv
, pipe
);
3964 /* use legacy palette for Ironlake */
3965 if (!HAS_GMCH_DISPLAY(dev
))
3966 palreg
= LGC_PALETTE(pipe
);
3968 /* Workaround : Do not read or write the pipe palette/gamma data while
3969 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3971 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3972 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3973 GAMMA_MODE_MODE_SPLIT
)) {
3974 hsw_disable_ips(intel_crtc
);
3975 reenable_ips
= true;
3978 for (i
= 0; i
< 256; i
++) {
3979 I915_WRITE(palreg
+ 4 * i
,
3980 (intel_crtc
->lut_r
[i
] << 16) |
3981 (intel_crtc
->lut_g
[i
] << 8) |
3982 intel_crtc
->lut_b
[i
]);
3986 hsw_enable_ips(intel_crtc
);
3989 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3991 if (!enable
&& intel_crtc
->overlay
) {
3992 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3995 mutex_lock(&dev
->struct_mutex
);
3996 dev_priv
->mm
.interruptible
= false;
3997 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3998 dev_priv
->mm
.interruptible
= true;
3999 mutex_unlock(&dev
->struct_mutex
);
4002 /* Let userspace switch the overlay on again. In most cases userspace
4003 * has to recompute where to put it anyway.
4007 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4009 struct drm_device
*dev
= crtc
->dev
;
4010 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4011 int pipe
= intel_crtc
->pipe
;
4013 assert_vblank_disabled(crtc
);
4015 drm_vblank_on(dev
, pipe
);
4017 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4018 intel_enable_planes(crtc
);
4019 intel_crtc_update_cursor(crtc
, true);
4020 intel_crtc_dpms_overlay(intel_crtc
, true);
4022 hsw_enable_ips(intel_crtc
);
4024 mutex_lock(&dev
->struct_mutex
);
4025 intel_update_fbc(dev
);
4026 mutex_unlock(&dev
->struct_mutex
);
4029 * FIXME: Once we grow proper nuclear flip support out of this we need
4030 * to compute the mask of flip planes precisely. For the time being
4031 * consider this a flip from a NULL plane.
4033 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4036 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4038 struct drm_device
*dev
= crtc
->dev
;
4039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4040 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4041 int pipe
= intel_crtc
->pipe
;
4042 int plane
= intel_crtc
->plane
;
4044 intel_crtc_wait_for_pending_flips(crtc
);
4046 if (dev_priv
->fbc
.plane
== plane
)
4047 intel_disable_fbc(dev
);
4049 hsw_disable_ips(intel_crtc
);
4051 intel_crtc_dpms_overlay(intel_crtc
, false);
4052 intel_crtc_update_cursor(crtc
, false);
4053 intel_disable_planes(crtc
);
4054 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4057 * FIXME: Once we grow proper nuclear flip support out of this we need
4058 * to compute the mask of flip planes precisely. For the time being
4059 * consider this a flip to a NULL plane.
4061 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4063 drm_vblank_off(dev
, pipe
);
4065 assert_vblank_disabled(crtc
);
4068 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4070 struct drm_device
*dev
= crtc
->dev
;
4071 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4072 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4073 struct intel_encoder
*encoder
;
4074 int pipe
= intel_crtc
->pipe
;
4076 WARN_ON(!crtc
->enabled
);
4078 if (intel_crtc
->active
)
4081 if (intel_crtc
->config
.has_pch_encoder
)
4082 intel_prepare_shared_dpll(intel_crtc
);
4084 if (intel_crtc
->config
.has_dp_encoder
)
4085 intel_dp_set_m_n(intel_crtc
);
4087 intel_set_pipe_timings(intel_crtc
);
4089 if (intel_crtc
->config
.has_pch_encoder
) {
4090 intel_cpu_transcoder_set_m_n(intel_crtc
,
4091 &intel_crtc
->config
.fdi_m_n
, NULL
);
4094 ironlake_set_pipeconf(crtc
);
4096 intel_crtc
->active
= true;
4098 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4099 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4101 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4102 if (encoder
->pre_enable
)
4103 encoder
->pre_enable(encoder
);
4105 if (intel_crtc
->config
.has_pch_encoder
) {
4106 /* Note: FDI PLL enabling _must_ be done before we enable the
4107 * cpu pipes, hence this is separate from all the other fdi/pch
4109 ironlake_fdi_pll_enable(intel_crtc
);
4111 assert_fdi_tx_disabled(dev_priv
, pipe
);
4112 assert_fdi_rx_disabled(dev_priv
, pipe
);
4115 ironlake_pfit_enable(intel_crtc
);
4118 * On ILK+ LUT must be loaded before the pipe is running but with
4121 intel_crtc_load_lut(crtc
);
4123 intel_update_watermarks(crtc
);
4124 intel_enable_pipe(intel_crtc
);
4126 if (intel_crtc
->config
.has_pch_encoder
)
4127 ironlake_pch_enable(crtc
);
4129 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4130 encoder
->enable(encoder
);
4132 if (HAS_PCH_CPT(dev
))
4133 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4135 intel_crtc_enable_planes(crtc
);
4138 /* IPS only exists on ULT machines and is tied to pipe A. */
4139 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4141 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4145 * This implements the workaround described in the "notes" section of the mode
4146 * set sequence documentation. When going from no pipes or single pipe to
4147 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4148 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4150 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4152 struct drm_device
*dev
= crtc
->base
.dev
;
4153 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4155 /* We want to get the other_active_crtc only if there's only 1 other
4157 for_each_intel_crtc(dev
, crtc_it
) {
4158 if (!crtc_it
->active
|| crtc_it
== crtc
)
4161 if (other_active_crtc
)
4164 other_active_crtc
= crtc_it
;
4166 if (!other_active_crtc
)
4169 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4170 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4173 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4175 struct drm_device
*dev
= crtc
->dev
;
4176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4177 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4178 struct intel_encoder
*encoder
;
4179 int pipe
= intel_crtc
->pipe
;
4181 WARN_ON(!crtc
->enabled
);
4183 if (intel_crtc
->active
)
4186 if (intel_crtc_to_shared_dpll(intel_crtc
))
4187 intel_enable_shared_dpll(intel_crtc
);
4189 if (intel_crtc
->config
.has_dp_encoder
)
4190 intel_dp_set_m_n(intel_crtc
);
4192 intel_set_pipe_timings(intel_crtc
);
4194 if (intel_crtc
->config
.has_pch_encoder
) {
4195 intel_cpu_transcoder_set_m_n(intel_crtc
,
4196 &intel_crtc
->config
.fdi_m_n
, NULL
);
4199 haswell_set_pipeconf(crtc
);
4201 intel_set_pipe_csc(crtc
);
4203 intel_crtc
->active
= true;
4205 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4206 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4207 if (encoder
->pre_enable
)
4208 encoder
->pre_enable(encoder
);
4210 if (intel_crtc
->config
.has_pch_encoder
) {
4211 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4212 dev_priv
->display
.fdi_link_train(crtc
);
4215 intel_ddi_enable_pipe_clock(intel_crtc
);
4217 ironlake_pfit_enable(intel_crtc
);
4220 * On ILK+ LUT must be loaded before the pipe is running but with
4223 intel_crtc_load_lut(crtc
);
4225 intel_ddi_set_pipe_settings(crtc
);
4226 intel_ddi_enable_transcoder_func(crtc
);
4228 intel_update_watermarks(crtc
);
4229 intel_enable_pipe(intel_crtc
);
4231 if (intel_crtc
->config
.has_pch_encoder
)
4232 lpt_pch_enable(crtc
);
4234 if (intel_crtc
->config
.dp_encoder_is_mst
)
4235 intel_ddi_set_vc_payload_alloc(crtc
, true);
4237 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4238 encoder
->enable(encoder
);
4239 intel_opregion_notify_encoder(encoder
, true);
4242 /* If we change the relative order between pipe/planes enabling, we need
4243 * to change the workaround. */
4244 haswell_mode_set_planes_workaround(intel_crtc
);
4245 intel_crtc_enable_planes(crtc
);
4248 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4250 struct drm_device
*dev
= crtc
->base
.dev
;
4251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4252 int pipe
= crtc
->pipe
;
4254 /* To avoid upsetting the power well on haswell only disable the pfit if
4255 * it's in use. The hw state code will make sure we get this right. */
4256 if (crtc
->config
.pch_pfit
.enabled
) {
4257 I915_WRITE(PF_CTL(pipe
), 0);
4258 I915_WRITE(PF_WIN_POS(pipe
), 0);
4259 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4263 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4265 struct drm_device
*dev
= crtc
->dev
;
4266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4267 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4268 struct intel_encoder
*encoder
;
4269 int pipe
= intel_crtc
->pipe
;
4272 if (!intel_crtc
->active
)
4275 intel_crtc_disable_planes(crtc
);
4277 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4278 encoder
->disable(encoder
);
4280 if (intel_crtc
->config
.has_pch_encoder
)
4281 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4283 intel_disable_pipe(intel_crtc
);
4285 ironlake_pfit_disable(intel_crtc
);
4287 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4288 if (encoder
->post_disable
)
4289 encoder
->post_disable(encoder
);
4291 if (intel_crtc
->config
.has_pch_encoder
) {
4292 ironlake_fdi_disable(crtc
);
4294 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4295 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4297 if (HAS_PCH_CPT(dev
)) {
4298 /* disable TRANS_DP_CTL */
4299 reg
= TRANS_DP_CTL(pipe
);
4300 temp
= I915_READ(reg
);
4301 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4302 TRANS_DP_PORT_SEL_MASK
);
4303 temp
|= TRANS_DP_PORT_SEL_NONE
;
4304 I915_WRITE(reg
, temp
);
4306 /* disable DPLL_SEL */
4307 temp
= I915_READ(PCH_DPLL_SEL
);
4308 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4309 I915_WRITE(PCH_DPLL_SEL
, temp
);
4312 /* disable PCH DPLL */
4313 intel_disable_shared_dpll(intel_crtc
);
4315 ironlake_fdi_pll_disable(intel_crtc
);
4318 intel_crtc
->active
= false;
4319 intel_update_watermarks(crtc
);
4321 mutex_lock(&dev
->struct_mutex
);
4322 intel_update_fbc(dev
);
4323 mutex_unlock(&dev
->struct_mutex
);
4326 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4328 struct drm_device
*dev
= crtc
->dev
;
4329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4330 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4331 struct intel_encoder
*encoder
;
4332 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4334 if (!intel_crtc
->active
)
4337 intel_crtc_disable_planes(crtc
);
4339 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4340 intel_opregion_notify_encoder(encoder
, false);
4341 encoder
->disable(encoder
);
4344 if (intel_crtc
->config
.has_pch_encoder
)
4345 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4346 intel_disable_pipe(intel_crtc
);
4348 if (intel_crtc
->config
.dp_encoder_is_mst
)
4349 intel_ddi_set_vc_payload_alloc(crtc
, false);
4351 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4353 ironlake_pfit_disable(intel_crtc
);
4355 intel_ddi_disable_pipe_clock(intel_crtc
);
4357 if (intel_crtc
->config
.has_pch_encoder
) {
4358 lpt_disable_pch_transcoder(dev_priv
);
4359 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4360 intel_ddi_fdi_disable(crtc
);
4363 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4364 if (encoder
->post_disable
)
4365 encoder
->post_disable(encoder
);
4367 intel_crtc
->active
= false;
4368 intel_update_watermarks(crtc
);
4370 mutex_lock(&dev
->struct_mutex
);
4371 intel_update_fbc(dev
);
4372 mutex_unlock(&dev
->struct_mutex
);
4374 if (intel_crtc_to_shared_dpll(intel_crtc
))
4375 intel_disable_shared_dpll(intel_crtc
);
4378 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4380 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4381 intel_put_shared_dpll(intel_crtc
);
4385 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4387 struct drm_device
*dev
= crtc
->base
.dev
;
4388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4389 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4391 if (!crtc
->config
.gmch_pfit
.control
)
4395 * The panel fitter should only be adjusted whilst the pipe is disabled,
4396 * according to register description and PRM.
4398 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4399 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4401 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4402 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4404 /* Border color in case we don't scale up to the full screen. Black by
4405 * default, change to something else for debugging. */
4406 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4409 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4413 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4415 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4417 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4419 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4422 return POWER_DOMAIN_PORT_OTHER
;
4426 #define for_each_power_domain(domain, mask) \
4427 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4428 if ((1 << (domain)) & (mask))
4430 enum intel_display_power_domain
4431 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4433 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4434 struct intel_digital_port
*intel_dig_port
;
4436 switch (intel_encoder
->type
) {
4437 case INTEL_OUTPUT_UNKNOWN
:
4438 /* Only DDI platforms should ever use this output type */
4439 WARN_ON_ONCE(!HAS_DDI(dev
));
4440 case INTEL_OUTPUT_DISPLAYPORT
:
4441 case INTEL_OUTPUT_HDMI
:
4442 case INTEL_OUTPUT_EDP
:
4443 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4444 return port_to_power_domain(intel_dig_port
->port
);
4445 case INTEL_OUTPUT_DP_MST
:
4446 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4447 return port_to_power_domain(intel_dig_port
->port
);
4448 case INTEL_OUTPUT_ANALOG
:
4449 return POWER_DOMAIN_PORT_CRT
;
4450 case INTEL_OUTPUT_DSI
:
4451 return POWER_DOMAIN_PORT_DSI
;
4453 return POWER_DOMAIN_PORT_OTHER
;
4457 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4459 struct drm_device
*dev
= crtc
->dev
;
4460 struct intel_encoder
*intel_encoder
;
4461 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4462 enum pipe pipe
= intel_crtc
->pipe
;
4464 enum transcoder transcoder
;
4466 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4468 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4469 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4470 if (intel_crtc
->config
.pch_pfit
.enabled
||
4471 intel_crtc
->config
.pch_pfit
.force_thru
)
4472 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4474 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4475 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4480 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4483 if (dev_priv
->power_domains
.init_power_on
== enable
)
4487 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4489 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4491 dev_priv
->power_domains
.init_power_on
= enable
;
4494 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4497 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4498 struct intel_crtc
*crtc
;
4501 * First get all needed power domains, then put all unneeded, to avoid
4502 * any unnecessary toggling of the power wells.
4504 for_each_intel_crtc(dev
, crtc
) {
4505 enum intel_display_power_domain domain
;
4507 if (!crtc
->base
.enabled
)
4510 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4512 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4513 intel_display_power_get(dev_priv
, domain
);
4516 for_each_intel_crtc(dev
, crtc
) {
4517 enum intel_display_power_domain domain
;
4519 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4520 intel_display_power_put(dev_priv
, domain
);
4522 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4525 intel_display_set_init_power(dev_priv
, false);
4528 /* returns HPLL frequency in kHz */
4529 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4531 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4533 /* Obtain SKU information */
4534 mutex_lock(&dev_priv
->dpio_lock
);
4535 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4536 CCK_FUSE_HPLL_FREQ_MASK
;
4537 mutex_unlock(&dev_priv
->dpio_lock
);
4539 return vco_freq
[hpll_freq
] * 1000;
4542 static void vlv_update_cdclk(struct drm_device
*dev
)
4544 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4546 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4547 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4548 dev_priv
->vlv_cdclk_freq
);
4551 * Program the gmbus_freq based on the cdclk frequency.
4552 * BSpec erroneously claims we should aim for 4MHz, but
4553 * in fact 1MHz is the correct frequency.
4555 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4558 /* Adjust CDclk dividers to allow high res or save power if possible */
4559 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4564 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4566 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4568 else if (cdclk
== 266667)
4573 mutex_lock(&dev_priv
->rps
.hw_lock
);
4574 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4575 val
&= ~DSPFREQGUAR_MASK
;
4576 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4577 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4578 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4579 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4581 DRM_ERROR("timed out waiting for CDclk change\n");
4583 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4585 if (cdclk
== 400000) {
4588 vco
= valleyview_get_vco(dev_priv
);
4589 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4591 mutex_lock(&dev_priv
->dpio_lock
);
4592 /* adjust cdclk divider */
4593 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4594 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4596 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4598 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4599 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4601 DRM_ERROR("timed out waiting for CDclk change\n");
4602 mutex_unlock(&dev_priv
->dpio_lock
);
4605 mutex_lock(&dev_priv
->dpio_lock
);
4606 /* adjust self-refresh exit latency value */
4607 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4611 * For high bandwidth configs, we set a higher latency in the bunit
4612 * so that the core display fetch happens in time to avoid underruns.
4614 if (cdclk
== 400000)
4615 val
|= 4500 / 250; /* 4.5 usec */
4617 val
|= 3000 / 250; /* 3.0 usec */
4618 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4619 mutex_unlock(&dev_priv
->dpio_lock
);
4621 vlv_update_cdclk(dev
);
4624 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4629 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4650 mutex_lock(&dev_priv
->rps
.hw_lock
);
4651 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4652 val
&= ~DSPFREQGUAR_MASK_CHV
;
4653 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4654 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4655 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4656 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4658 DRM_ERROR("timed out waiting for CDclk change\n");
4660 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4662 vlv_update_cdclk(dev
);
4665 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4668 int vco
= valleyview_get_vco(dev_priv
);
4669 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4671 /* FIXME: Punit isn't quite ready yet */
4672 if (IS_CHERRYVIEW(dev_priv
->dev
))
4676 * Really only a few cases to deal with, as only 4 CDclks are supported:
4679 * 320/333MHz (depends on HPLL freq)
4681 * So we check to see whether we're above 90% of the lower bin and
4684 * We seem to get an unstable or solid color picture at 200MHz.
4685 * Not sure what's wrong. For now use 200MHz only when all pipes
4688 if (max_pixclk
> freq_320
*9/10)
4690 else if (max_pixclk
> 266667*9/10)
4692 else if (max_pixclk
> 0)
4698 /* compute the max pixel clock for new configuration */
4699 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4701 struct drm_device
*dev
= dev_priv
->dev
;
4702 struct intel_crtc
*intel_crtc
;
4705 for_each_intel_crtc(dev
, intel_crtc
) {
4706 if (intel_crtc
->new_enabled
)
4707 max_pixclk
= max(max_pixclk
,
4708 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4714 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4715 unsigned *prepare_pipes
)
4717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4718 struct intel_crtc
*intel_crtc
;
4719 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4721 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4722 dev_priv
->vlv_cdclk_freq
)
4725 /* disable/enable all currently active pipes while we change cdclk */
4726 for_each_intel_crtc(dev
, intel_crtc
)
4727 if (intel_crtc
->base
.enabled
)
4728 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4731 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4734 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4735 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4737 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4738 if (IS_CHERRYVIEW(dev
))
4739 cherryview_set_cdclk(dev
, req_cdclk
);
4741 valleyview_set_cdclk(dev
, req_cdclk
);
4744 modeset_update_crtc_power_domains(dev
);
4747 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4749 struct drm_device
*dev
= crtc
->dev
;
4750 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4751 struct intel_encoder
*encoder
;
4752 int pipe
= intel_crtc
->pipe
;
4755 WARN_ON(!crtc
->enabled
);
4757 if (intel_crtc
->active
)
4760 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4763 if (IS_CHERRYVIEW(dev
))
4764 chv_prepare_pll(intel_crtc
);
4766 vlv_prepare_pll(intel_crtc
);
4769 if (intel_crtc
->config
.has_dp_encoder
)
4770 intel_dp_set_m_n(intel_crtc
);
4772 intel_set_pipe_timings(intel_crtc
);
4774 i9xx_set_pipeconf(intel_crtc
);
4776 intel_crtc
->active
= true;
4778 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4780 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4781 if (encoder
->pre_pll_enable
)
4782 encoder
->pre_pll_enable(encoder
);
4785 if (IS_CHERRYVIEW(dev
))
4786 chv_enable_pll(intel_crtc
);
4788 vlv_enable_pll(intel_crtc
);
4791 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4792 if (encoder
->pre_enable
)
4793 encoder
->pre_enable(encoder
);
4795 i9xx_pfit_enable(intel_crtc
);
4797 intel_crtc_load_lut(crtc
);
4799 intel_update_watermarks(crtc
);
4800 intel_enable_pipe(intel_crtc
);
4802 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4803 encoder
->enable(encoder
);
4805 intel_crtc_enable_planes(crtc
);
4807 /* Underruns don't raise interrupts, so check manually. */
4808 i9xx_check_fifo_underruns(dev
);
4811 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4813 struct drm_device
*dev
= crtc
->base
.dev
;
4814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4816 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4817 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4820 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4822 struct drm_device
*dev
= crtc
->dev
;
4823 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4824 struct intel_encoder
*encoder
;
4825 int pipe
= intel_crtc
->pipe
;
4827 WARN_ON(!crtc
->enabled
);
4829 if (intel_crtc
->active
)
4832 i9xx_set_pll_dividers(intel_crtc
);
4834 if (intel_crtc
->config
.has_dp_encoder
)
4835 intel_dp_set_m_n(intel_crtc
);
4837 intel_set_pipe_timings(intel_crtc
);
4839 i9xx_set_pipeconf(intel_crtc
);
4841 intel_crtc
->active
= true;
4844 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4846 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4847 if (encoder
->pre_enable
)
4848 encoder
->pre_enable(encoder
);
4850 i9xx_enable_pll(intel_crtc
);
4852 i9xx_pfit_enable(intel_crtc
);
4854 intel_crtc_load_lut(crtc
);
4856 intel_update_watermarks(crtc
);
4857 intel_enable_pipe(intel_crtc
);
4859 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4860 encoder
->enable(encoder
);
4862 intel_crtc_enable_planes(crtc
);
4865 * Gen2 reports pipe underruns whenever all planes are disabled.
4866 * So don't enable underrun reporting before at least some planes
4868 * FIXME: Need to fix the logic to work when we turn off all planes
4869 * but leave the pipe running.
4872 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4874 /* Underruns don't raise interrupts, so check manually. */
4875 i9xx_check_fifo_underruns(dev
);
4878 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4880 struct drm_device
*dev
= crtc
->base
.dev
;
4881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4883 if (!crtc
->config
.gmch_pfit
.control
)
4886 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4888 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4889 I915_READ(PFIT_CONTROL
));
4890 I915_WRITE(PFIT_CONTROL
, 0);
4893 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4895 struct drm_device
*dev
= crtc
->dev
;
4896 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4897 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4898 struct intel_encoder
*encoder
;
4899 int pipe
= intel_crtc
->pipe
;
4901 if (!intel_crtc
->active
)
4905 * Gen2 reports pipe underruns whenever all planes are disabled.
4906 * So diasble underrun reporting before all the planes get disabled.
4907 * FIXME: Need to fix the logic to work when we turn off all planes
4908 * but leave the pipe running.
4911 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4914 * Vblank time updates from the shadow to live plane control register
4915 * are blocked if the memory self-refresh mode is active at that
4916 * moment. So to make sure the plane gets truly disabled, disable
4917 * first the self-refresh mode. The self-refresh enable bit in turn
4918 * will be checked/applied by the HW only at the next frame start
4919 * event which is after the vblank start event, so we need to have a
4920 * wait-for-vblank between disabling the plane and the pipe.
4922 intel_set_memory_cxsr(dev_priv
, false);
4923 intel_crtc_disable_planes(crtc
);
4925 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4926 encoder
->disable(encoder
);
4929 * On gen2 planes are double buffered but the pipe isn't, so we must
4930 * wait for planes to fully turn off before disabling the pipe.
4931 * We also need to wait on all gmch platforms because of the
4932 * self-refresh mode constraint explained above.
4934 intel_wait_for_vblank(dev
, pipe
);
4936 intel_disable_pipe(intel_crtc
);
4938 i9xx_pfit_disable(intel_crtc
);
4940 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4941 if (encoder
->post_disable
)
4942 encoder
->post_disable(encoder
);
4944 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4945 if (IS_CHERRYVIEW(dev
))
4946 chv_disable_pll(dev_priv
, pipe
);
4947 else if (IS_VALLEYVIEW(dev
))
4948 vlv_disable_pll(dev_priv
, pipe
);
4950 i9xx_disable_pll(dev_priv
, pipe
);
4954 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4956 intel_crtc
->active
= false;
4957 intel_update_watermarks(crtc
);
4959 mutex_lock(&dev
->struct_mutex
);
4960 intel_update_fbc(dev
);
4961 mutex_unlock(&dev
->struct_mutex
);
4964 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4968 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4971 struct drm_device
*dev
= crtc
->dev
;
4972 struct drm_i915_master_private
*master_priv
;
4973 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4974 int pipe
= intel_crtc
->pipe
;
4976 if (!dev
->primary
->master
)
4979 master_priv
= dev
->primary
->master
->driver_priv
;
4980 if (!master_priv
->sarea_priv
)
4985 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4986 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4989 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4990 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4993 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4998 /* Master function to enable/disable CRTC and corresponding power wells */
4999 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5001 struct drm_device
*dev
= crtc
->dev
;
5002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5003 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5004 enum intel_display_power_domain domain
;
5005 unsigned long domains
;
5008 if (!intel_crtc
->active
) {
5009 domains
= get_crtc_power_domains(crtc
);
5010 for_each_power_domain(domain
, domains
)
5011 intel_display_power_get(dev_priv
, domain
);
5012 intel_crtc
->enabled_power_domains
= domains
;
5014 dev_priv
->display
.crtc_enable(crtc
);
5017 if (intel_crtc
->active
) {
5018 dev_priv
->display
.crtc_disable(crtc
);
5020 domains
= intel_crtc
->enabled_power_domains
;
5021 for_each_power_domain(domain
, domains
)
5022 intel_display_power_put(dev_priv
, domain
);
5023 intel_crtc
->enabled_power_domains
= 0;
5029 * Sets the power management mode of the pipe and plane.
5031 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5033 struct drm_device
*dev
= crtc
->dev
;
5034 struct intel_encoder
*intel_encoder
;
5035 bool enable
= false;
5037 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5038 enable
|= intel_encoder
->connectors_active
;
5040 intel_crtc_control(crtc
, enable
);
5042 intel_crtc_update_sarea(crtc
, enable
);
5045 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5047 struct drm_device
*dev
= crtc
->dev
;
5048 struct drm_connector
*connector
;
5049 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5050 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
5051 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
5053 /* crtc should still be enabled when we disable it. */
5054 WARN_ON(!crtc
->enabled
);
5056 dev_priv
->display
.crtc_disable(crtc
);
5057 intel_crtc_update_sarea(crtc
, false);
5058 dev_priv
->display
.off(crtc
);
5060 if (crtc
->primary
->fb
) {
5061 mutex_lock(&dev
->struct_mutex
);
5062 intel_unpin_fb_obj(old_obj
);
5063 i915_gem_track_fb(old_obj
, NULL
,
5064 INTEL_FRONTBUFFER_PRIMARY(pipe
));
5065 mutex_unlock(&dev
->struct_mutex
);
5066 crtc
->primary
->fb
= NULL
;
5069 /* Update computed state. */
5070 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5071 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5074 if (connector
->encoder
->crtc
!= crtc
)
5077 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5078 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5082 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5084 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5086 drm_encoder_cleanup(encoder
);
5087 kfree(intel_encoder
);
5090 /* Simple dpms helper for encoders with just one connector, no cloning and only
5091 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5092 * state of the entire output pipe. */
5093 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5095 if (mode
== DRM_MODE_DPMS_ON
) {
5096 encoder
->connectors_active
= true;
5098 intel_crtc_update_dpms(encoder
->base
.crtc
);
5100 encoder
->connectors_active
= false;
5102 intel_crtc_update_dpms(encoder
->base
.crtc
);
5106 /* Cross check the actual hw state with our own modeset state tracking (and it's
5107 * internal consistency). */
5108 static void intel_connector_check_state(struct intel_connector
*connector
)
5110 if (connector
->get_hw_state(connector
)) {
5111 struct intel_encoder
*encoder
= connector
->encoder
;
5112 struct drm_crtc
*crtc
;
5113 bool encoder_enabled
;
5116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5117 connector
->base
.base
.id
,
5118 connector
->base
.name
);
5120 /* there is no real hw state for MST connectors */
5121 if (connector
->mst_port
)
5124 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5125 "wrong connector dpms state\n");
5126 WARN(connector
->base
.encoder
!= &encoder
->base
,
5127 "active connector not linked to encoder\n");
5130 WARN(!encoder
->connectors_active
,
5131 "encoder->connectors_active not set\n");
5133 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5134 WARN(!encoder_enabled
, "encoder not enabled\n");
5135 if (WARN_ON(!encoder
->base
.crtc
))
5138 crtc
= encoder
->base
.crtc
;
5140 WARN(!crtc
->enabled
, "crtc not enabled\n");
5141 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5142 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5143 "encoder active on the wrong pipe\n");
5148 /* Even simpler default implementation, if there's really no special case to
5150 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5152 /* All the simple cases only support two dpms states. */
5153 if (mode
!= DRM_MODE_DPMS_ON
)
5154 mode
= DRM_MODE_DPMS_OFF
;
5156 if (mode
== connector
->dpms
)
5159 connector
->dpms
= mode
;
5161 /* Only need to change hw state when actually enabled */
5162 if (connector
->encoder
)
5163 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5165 intel_modeset_check_state(connector
->dev
);
5168 /* Simple connector->get_hw_state implementation for encoders that support only
5169 * one connector and no cloning and hence the encoder state determines the state
5170 * of the connector. */
5171 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5174 struct intel_encoder
*encoder
= connector
->encoder
;
5176 return encoder
->get_hw_state(encoder
, &pipe
);
5179 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5180 struct intel_crtc_config
*pipe_config
)
5182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5183 struct intel_crtc
*pipe_B_crtc
=
5184 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5186 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5187 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5188 if (pipe_config
->fdi_lanes
> 4) {
5189 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5190 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5194 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5195 if (pipe_config
->fdi_lanes
> 2) {
5196 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5197 pipe_config
->fdi_lanes
);
5204 if (INTEL_INFO(dev
)->num_pipes
== 2)
5207 /* Ivybridge 3 pipe is really complicated */
5212 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5213 pipe_config
->fdi_lanes
> 2) {
5214 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5215 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5220 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5221 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5222 if (pipe_config
->fdi_lanes
> 2) {
5223 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5224 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5228 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5238 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5239 struct intel_crtc_config
*pipe_config
)
5241 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5242 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5243 int lane
, link_bw
, fdi_dotclock
;
5244 bool setup_ok
, needs_recompute
= false;
5247 /* FDI is a binary signal running at ~2.7GHz, encoding
5248 * each output octet as 10 bits. The actual frequency
5249 * is stored as a divider into a 100MHz clock, and the
5250 * mode pixel clock is stored in units of 1KHz.
5251 * Hence the bw of each lane in terms of the mode signal
5254 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5256 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5258 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5259 pipe_config
->pipe_bpp
);
5261 pipe_config
->fdi_lanes
= lane
;
5263 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5264 link_bw
, &pipe_config
->fdi_m_n
);
5266 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5267 intel_crtc
->pipe
, pipe_config
);
5268 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5269 pipe_config
->pipe_bpp
-= 2*3;
5270 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5271 pipe_config
->pipe_bpp
);
5272 needs_recompute
= true;
5273 pipe_config
->bw_constrained
= true;
5278 if (needs_recompute
)
5281 return setup_ok
? 0 : -EINVAL
;
5284 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5285 struct intel_crtc_config
*pipe_config
)
5287 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5288 hsw_crtc_supports_ips(crtc
) &&
5289 pipe_config
->pipe_bpp
<= 24;
5292 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5293 struct intel_crtc_config
*pipe_config
)
5295 struct drm_device
*dev
= crtc
->base
.dev
;
5296 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5298 /* FIXME should check pixel clock limits on all platforms */
5299 if (INTEL_INFO(dev
)->gen
< 4) {
5300 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5302 dev_priv
->display
.get_display_clock_speed(dev
);
5305 * Enable pixel doubling when the dot clock
5306 * is > 90% of the (display) core speed.
5308 * GDG double wide on either pipe,
5309 * otherwise pipe A only.
5311 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5312 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5314 pipe_config
->double_wide
= true;
5317 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5322 * Pipe horizontal size must be even in:
5324 * - LVDS dual channel mode
5325 * - Double wide pipe
5327 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5328 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5329 pipe_config
->pipe_src_w
&= ~1;
5331 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5332 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5334 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5335 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5338 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5339 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5340 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5341 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5343 pipe_config
->pipe_bpp
= 8*3;
5347 hsw_compute_ips_config(crtc
, pipe_config
);
5350 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5351 * old clock survives for now.
5353 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5354 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5356 if (pipe_config
->has_pch_encoder
)
5357 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5362 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5365 int vco
= valleyview_get_vco(dev_priv
);
5369 /* FIXME: Punit isn't quite ready yet */
5370 if (IS_CHERRYVIEW(dev
))
5373 mutex_lock(&dev_priv
->dpio_lock
);
5374 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5375 mutex_unlock(&dev_priv
->dpio_lock
);
5377 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5379 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5380 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5381 "cdclk change in progress\n");
5383 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5386 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5391 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5396 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5401 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5405 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5407 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5408 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5410 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5412 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5414 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5417 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5418 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5420 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5425 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5429 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5431 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5434 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5435 case GC_DISPLAY_CLOCK_333_MHZ
:
5438 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5444 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5449 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5452 /* Assume that the hardware is in the high speed state. This
5453 * should be the default.
5455 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5456 case GC_CLOCK_133_200
:
5457 case GC_CLOCK_100_200
:
5459 case GC_CLOCK_166_250
:
5461 case GC_CLOCK_100_133
:
5465 /* Shouldn't happen */
5469 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5475 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5477 while (*num
> DATA_LINK_M_N_MASK
||
5478 *den
> DATA_LINK_M_N_MASK
) {
5484 static void compute_m_n(unsigned int m
, unsigned int n
,
5485 uint32_t *ret_m
, uint32_t *ret_n
)
5487 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5488 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5489 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5493 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5494 int pixel_clock
, int link_clock
,
5495 struct intel_link_m_n
*m_n
)
5499 compute_m_n(bits_per_pixel
* pixel_clock
,
5500 link_clock
* nlanes
* 8,
5501 &m_n
->gmch_m
, &m_n
->gmch_n
);
5503 compute_m_n(pixel_clock
, link_clock
,
5504 &m_n
->link_m
, &m_n
->link_n
);
5507 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5509 if (i915
.panel_use_ssc
>= 0)
5510 return i915
.panel_use_ssc
!= 0;
5511 return dev_priv
->vbt
.lvds_use_ssc
5512 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5515 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5517 struct drm_device
*dev
= crtc
->dev
;
5518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5521 if (IS_VALLEYVIEW(dev
)) {
5523 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5524 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5525 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5526 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5527 } else if (!IS_GEN2(dev
)) {
5536 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5538 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5541 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5543 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5546 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5547 intel_clock_t
*reduced_clock
)
5549 struct drm_device
*dev
= crtc
->base
.dev
;
5552 if (IS_PINEVIEW(dev
)) {
5553 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5555 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5557 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5559 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5562 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5564 crtc
->lowfreq_avail
= false;
5565 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5566 reduced_clock
&& i915
.powersave
) {
5567 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5568 crtc
->lowfreq_avail
= true;
5570 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5574 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5580 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5581 * and set it to a reasonable value instead.
5583 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5584 reg_val
&= 0xffffff00;
5585 reg_val
|= 0x00000030;
5586 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5588 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5589 reg_val
&= 0x8cffffff;
5590 reg_val
= 0x8c000000;
5591 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5593 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5594 reg_val
&= 0xffffff00;
5595 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5597 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5598 reg_val
&= 0x00ffffff;
5599 reg_val
|= 0xb0000000;
5600 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5603 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5604 struct intel_link_m_n
*m_n
)
5606 struct drm_device
*dev
= crtc
->base
.dev
;
5607 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5608 int pipe
= crtc
->pipe
;
5610 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5611 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5612 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5613 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5616 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5617 struct intel_link_m_n
*m_n
,
5618 struct intel_link_m_n
*m2_n2
)
5620 struct drm_device
*dev
= crtc
->base
.dev
;
5621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5622 int pipe
= crtc
->pipe
;
5623 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5625 if (INTEL_INFO(dev
)->gen
>= 5) {
5626 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5627 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5628 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5629 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5630 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5631 * for gen < 8) and if DRRS is supported (to make sure the
5632 * registers are not unnecessarily accessed).
5634 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5635 crtc
->config
.has_drrs
) {
5636 I915_WRITE(PIPE_DATA_M2(transcoder
),
5637 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5638 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5639 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5640 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5643 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5644 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5645 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5646 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5650 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5652 if (crtc
->config
.has_pch_encoder
)
5653 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5655 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5656 &crtc
->config
.dp_m2_n2
);
5659 static void vlv_update_pll(struct intel_crtc
*crtc
)
5664 * Enable DPIO clock input. We should never disable the reference
5665 * clock for pipe B, since VGA hotplug / manual detection depends
5668 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5669 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5670 /* We should never disable this, set it here for state tracking */
5671 if (crtc
->pipe
== PIPE_B
)
5672 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5673 dpll
|= DPLL_VCO_ENABLE
;
5674 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5676 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5677 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5678 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5681 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5683 struct drm_device
*dev
= crtc
->base
.dev
;
5684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5685 int pipe
= crtc
->pipe
;
5687 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5688 u32 coreclk
, reg_val
;
5690 mutex_lock(&dev_priv
->dpio_lock
);
5692 bestn
= crtc
->config
.dpll
.n
;
5693 bestm1
= crtc
->config
.dpll
.m1
;
5694 bestm2
= crtc
->config
.dpll
.m2
;
5695 bestp1
= crtc
->config
.dpll
.p1
;
5696 bestp2
= crtc
->config
.dpll
.p2
;
5698 /* See eDP HDMI DPIO driver vbios notes doc */
5700 /* PLL B needs special handling */
5702 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5704 /* Set up Tx target for periodic Rcomp update */
5705 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5707 /* Disable target IRef on PLL */
5708 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5709 reg_val
&= 0x00ffffff;
5710 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5712 /* Disable fast lock */
5713 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5715 /* Set idtafcrecal before PLL is enabled */
5716 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5717 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5718 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5719 mdiv
|= (1 << DPIO_K_SHIFT
);
5722 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5723 * but we don't support that).
5724 * Note: don't use the DAC post divider as it seems unstable.
5726 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5727 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5729 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5730 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5732 /* Set HBR and RBR LPF coefficients */
5733 if (crtc
->config
.port_clock
== 162000 ||
5734 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5735 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5736 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5739 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5742 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5743 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5744 /* Use SSC source */
5746 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5749 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5751 } else { /* HDMI or VGA */
5752 /* Use bend source */
5754 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5757 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5761 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5762 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5763 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5764 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5765 coreclk
|= 0x01000000;
5766 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5768 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5769 mutex_unlock(&dev_priv
->dpio_lock
);
5772 static void chv_update_pll(struct intel_crtc
*crtc
)
5774 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5775 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5777 if (crtc
->pipe
!= PIPE_A
)
5778 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5780 crtc
->config
.dpll_hw_state
.dpll_md
=
5781 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5784 static void chv_prepare_pll(struct intel_crtc
*crtc
)
5786 struct drm_device
*dev
= crtc
->base
.dev
;
5787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5788 int pipe
= crtc
->pipe
;
5789 int dpll_reg
= DPLL(crtc
->pipe
);
5790 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5791 u32 loopfilter
, intcoeff
;
5792 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5795 bestn
= crtc
->config
.dpll
.n
;
5796 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5797 bestm1
= crtc
->config
.dpll
.m1
;
5798 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5799 bestp1
= crtc
->config
.dpll
.p1
;
5800 bestp2
= crtc
->config
.dpll
.p2
;
5803 * Enable Refclk and SSC
5805 I915_WRITE(dpll_reg
,
5806 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5808 mutex_lock(&dev_priv
->dpio_lock
);
5810 /* p1 and p2 divider */
5811 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5812 5 << DPIO_CHV_S1_DIV_SHIFT
|
5813 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5814 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5815 1 << DPIO_CHV_K_DIV_SHIFT
);
5817 /* Feedback post-divider - m2 */
5818 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5820 /* Feedback refclk divider - n and m1 */
5821 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5822 DPIO_CHV_M1_DIV_BY_2
|
5823 1 << DPIO_CHV_N_DIV_SHIFT
);
5825 /* M2 fraction division */
5826 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5828 /* M2 fraction division enable */
5829 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5830 DPIO_CHV_FRAC_DIV_EN
|
5831 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5834 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5835 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5836 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5837 if (refclk
== 100000)
5839 else if (refclk
== 38400)
5843 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5844 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5847 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5848 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5851 mutex_unlock(&dev_priv
->dpio_lock
);
5854 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5855 intel_clock_t
*reduced_clock
,
5858 struct drm_device
*dev
= crtc
->base
.dev
;
5859 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5862 struct dpll
*clock
= &crtc
->config
.dpll
;
5864 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5866 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5867 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5869 dpll
= DPLL_VGA_MODE_DIS
;
5871 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5872 dpll
|= DPLLB_MODE_LVDS
;
5874 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5876 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5877 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5878 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5882 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5884 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5885 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5887 /* compute bitmask from p1 value */
5888 if (IS_PINEVIEW(dev
))
5889 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5891 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5892 if (IS_G4X(dev
) && reduced_clock
)
5893 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5895 switch (clock
->p2
) {
5897 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5900 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5903 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5906 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5909 if (INTEL_INFO(dev
)->gen
>= 4)
5910 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5912 if (crtc
->config
.sdvo_tv_clock
)
5913 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5914 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5915 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5916 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5918 dpll
|= PLL_REF_INPUT_DREFCLK
;
5920 dpll
|= DPLL_VCO_ENABLE
;
5921 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5923 if (INTEL_INFO(dev
)->gen
>= 4) {
5924 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5925 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5926 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5930 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5931 intel_clock_t
*reduced_clock
,
5934 struct drm_device
*dev
= crtc
->base
.dev
;
5935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5937 struct dpll
*clock
= &crtc
->config
.dpll
;
5939 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5941 dpll
= DPLL_VGA_MODE_DIS
;
5943 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5944 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5947 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5949 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5951 dpll
|= PLL_P2_DIVIDE_BY_4
;
5954 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5955 dpll
|= DPLL_DVO_2X_MODE
;
5957 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5958 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5959 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5961 dpll
|= PLL_REF_INPUT_DREFCLK
;
5963 dpll
|= DPLL_VCO_ENABLE
;
5964 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5967 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5969 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5971 enum pipe pipe
= intel_crtc
->pipe
;
5972 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5973 struct drm_display_mode
*adjusted_mode
=
5974 &intel_crtc
->config
.adjusted_mode
;
5975 uint32_t crtc_vtotal
, crtc_vblank_end
;
5978 /* We need to be careful not to changed the adjusted mode, for otherwise
5979 * the hw state checker will get angry at the mismatch. */
5980 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5981 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5983 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5984 /* the chip adds 2 halflines automatically */
5986 crtc_vblank_end
-= 1;
5988 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5989 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
5991 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
5992 adjusted_mode
->crtc_htotal
/ 2;
5994 vsyncshift
+= adjusted_mode
->crtc_htotal
;
5997 if (INTEL_INFO(dev
)->gen
> 3)
5998 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6000 I915_WRITE(HTOTAL(cpu_transcoder
),
6001 (adjusted_mode
->crtc_hdisplay
- 1) |
6002 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6003 I915_WRITE(HBLANK(cpu_transcoder
),
6004 (adjusted_mode
->crtc_hblank_start
- 1) |
6005 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6006 I915_WRITE(HSYNC(cpu_transcoder
),
6007 (adjusted_mode
->crtc_hsync_start
- 1) |
6008 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6010 I915_WRITE(VTOTAL(cpu_transcoder
),
6011 (adjusted_mode
->crtc_vdisplay
- 1) |
6012 ((crtc_vtotal
- 1) << 16));
6013 I915_WRITE(VBLANK(cpu_transcoder
),
6014 (adjusted_mode
->crtc_vblank_start
- 1) |
6015 ((crtc_vblank_end
- 1) << 16));
6016 I915_WRITE(VSYNC(cpu_transcoder
),
6017 (adjusted_mode
->crtc_vsync_start
- 1) |
6018 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6020 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6021 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6022 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6024 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6025 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6026 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6028 /* pipesrc controls the size that is scaled from, which should
6029 * always be the user's requested size.
6031 I915_WRITE(PIPESRC(pipe
),
6032 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
6033 (intel_crtc
->config
.pipe_src_h
- 1));
6036 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6037 struct intel_crtc_config
*pipe_config
)
6039 struct drm_device
*dev
= crtc
->base
.dev
;
6040 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6041 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6044 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6045 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6046 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6047 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6048 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6049 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6050 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6051 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6052 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6054 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6055 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6056 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6057 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6058 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6059 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6060 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6061 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6062 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6064 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6065 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6066 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
6067 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6070 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6071 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6072 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6074 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6075 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6078 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6079 struct intel_crtc_config
*pipe_config
)
6081 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6082 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6083 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6084 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6086 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6087 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6088 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6089 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6091 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6093 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6094 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6097 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6099 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6100 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6105 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6106 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6107 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6109 if (intel_crtc
->config
.double_wide
)
6110 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6112 /* only g4x and later have fancy bpc/dither controls */
6113 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6114 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6115 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6116 pipeconf
|= PIPECONF_DITHER_EN
|
6117 PIPECONF_DITHER_TYPE_SP
;
6119 switch (intel_crtc
->config
.pipe_bpp
) {
6121 pipeconf
|= PIPECONF_6BPC
;
6124 pipeconf
|= PIPECONF_8BPC
;
6127 pipeconf
|= PIPECONF_10BPC
;
6130 /* Case prevented by intel_choose_pipe_bpp_dither. */
6135 if (HAS_PIPE_CXSR(dev
)) {
6136 if (intel_crtc
->lowfreq_avail
) {
6137 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6138 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6140 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6144 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6145 if (INTEL_INFO(dev
)->gen
< 4 ||
6146 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6147 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6149 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6151 pipeconf
|= PIPECONF_PROGRESSIVE
;
6153 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6154 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6156 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6157 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6160 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6162 struct drm_framebuffer
*fb
)
6164 struct drm_device
*dev
= crtc
->dev
;
6165 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6167 int refclk
, num_connectors
= 0;
6168 intel_clock_t clock
, reduced_clock
;
6169 bool ok
, has_reduced_clock
= false;
6170 bool is_lvds
= false, is_dsi
= false;
6171 struct intel_encoder
*encoder
;
6172 const intel_limit_t
*limit
;
6174 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6175 switch (encoder
->type
) {
6176 case INTEL_OUTPUT_LVDS
:
6179 case INTEL_OUTPUT_DSI
:
6190 if (!intel_crtc
->config
.clock_set
) {
6191 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6194 * Returns a set of divisors for the desired target clock with
6195 * the given refclk, or FALSE. The returned values represent
6196 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6199 limit
= intel_limit(crtc
, refclk
);
6200 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6201 intel_crtc
->config
.port_clock
,
6202 refclk
, NULL
, &clock
);
6204 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6208 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6210 * Ensure we match the reduced clock's P to the target
6211 * clock. If the clocks don't match, we can't switch
6212 * the display clock by using the FP0/FP1. In such case
6213 * we will disable the LVDS downclock feature.
6216 dev_priv
->display
.find_dpll(limit
, crtc
,
6217 dev_priv
->lvds_downclock
,
6221 /* Compat-code for transition, will disappear. */
6222 intel_crtc
->config
.dpll
.n
= clock
.n
;
6223 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6224 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6225 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6226 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6230 i8xx_update_pll(intel_crtc
,
6231 has_reduced_clock
? &reduced_clock
: NULL
,
6233 } else if (IS_CHERRYVIEW(dev
)) {
6234 chv_update_pll(intel_crtc
);
6235 } else if (IS_VALLEYVIEW(dev
)) {
6236 vlv_update_pll(intel_crtc
);
6238 i9xx_update_pll(intel_crtc
,
6239 has_reduced_clock
? &reduced_clock
: NULL
,
6246 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6247 struct intel_crtc_config
*pipe_config
)
6249 struct drm_device
*dev
= crtc
->base
.dev
;
6250 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6253 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6256 tmp
= I915_READ(PFIT_CONTROL
);
6257 if (!(tmp
& PFIT_ENABLE
))
6260 /* Check whether the pfit is attached to our pipe. */
6261 if (INTEL_INFO(dev
)->gen
< 4) {
6262 if (crtc
->pipe
!= PIPE_B
)
6265 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6269 pipe_config
->gmch_pfit
.control
= tmp
;
6270 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6271 if (INTEL_INFO(dev
)->gen
< 5)
6272 pipe_config
->gmch_pfit
.lvds_border_bits
=
6273 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6276 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6277 struct intel_crtc_config
*pipe_config
)
6279 struct drm_device
*dev
= crtc
->base
.dev
;
6280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6281 int pipe
= pipe_config
->cpu_transcoder
;
6282 intel_clock_t clock
;
6284 int refclk
= 100000;
6286 /* In case of MIPI DPLL will not even be used */
6287 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6290 mutex_lock(&dev_priv
->dpio_lock
);
6291 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6292 mutex_unlock(&dev_priv
->dpio_lock
);
6294 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6295 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6296 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6297 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6298 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6300 vlv_clock(refclk
, &clock
);
6302 /* clock.dot is the fast clock */
6303 pipe_config
->port_clock
= clock
.dot
/ 5;
6306 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6307 struct intel_plane_config
*plane_config
)
6309 struct drm_device
*dev
= crtc
->base
.dev
;
6310 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6311 u32 val
, base
, offset
;
6312 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6313 int fourcc
, pixel_format
;
6316 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6317 if (!crtc
->base
.primary
->fb
) {
6318 DRM_DEBUG_KMS("failed to alloc fb\n");
6322 val
= I915_READ(DSPCNTR(plane
));
6324 if (INTEL_INFO(dev
)->gen
>= 4)
6325 if (val
& DISPPLANE_TILED
)
6326 plane_config
->tiled
= true;
6328 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6329 fourcc
= intel_format_to_fourcc(pixel_format
);
6330 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6331 crtc
->base
.primary
->fb
->bits_per_pixel
=
6332 drm_format_plane_cpp(fourcc
, 0) * 8;
6334 if (INTEL_INFO(dev
)->gen
>= 4) {
6335 if (plane_config
->tiled
)
6336 offset
= I915_READ(DSPTILEOFF(plane
));
6338 offset
= I915_READ(DSPLINOFF(plane
));
6339 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6341 base
= I915_READ(DSPADDR(plane
));
6343 plane_config
->base
= base
;
6345 val
= I915_READ(PIPESRC(pipe
));
6346 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6347 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6349 val
= I915_READ(DSPSTRIDE(pipe
));
6350 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6352 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6353 plane_config
->tiled
);
6355 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6358 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6359 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6360 crtc
->base
.primary
->fb
->height
,
6361 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6362 crtc
->base
.primary
->fb
->pitches
[0],
6363 plane_config
->size
);
6367 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6368 struct intel_crtc_config
*pipe_config
)
6370 struct drm_device
*dev
= crtc
->base
.dev
;
6371 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6372 int pipe
= pipe_config
->cpu_transcoder
;
6373 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6374 intel_clock_t clock
;
6375 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6376 int refclk
= 100000;
6378 mutex_lock(&dev_priv
->dpio_lock
);
6379 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6380 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6381 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6382 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6383 mutex_unlock(&dev_priv
->dpio_lock
);
6385 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6386 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6387 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6388 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6389 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6391 chv_clock(refclk
, &clock
);
6393 /* clock.dot is the fast clock */
6394 pipe_config
->port_clock
= clock
.dot
/ 5;
6397 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6398 struct intel_crtc_config
*pipe_config
)
6400 struct drm_device
*dev
= crtc
->base
.dev
;
6401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6404 if (!intel_display_power_enabled(dev_priv
,
6405 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6408 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6409 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6411 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6412 if (!(tmp
& PIPECONF_ENABLE
))
6415 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6416 switch (tmp
& PIPECONF_BPC_MASK
) {
6418 pipe_config
->pipe_bpp
= 18;
6421 pipe_config
->pipe_bpp
= 24;
6423 case PIPECONF_10BPC
:
6424 pipe_config
->pipe_bpp
= 30;
6431 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6432 pipe_config
->limited_color_range
= true;
6434 if (INTEL_INFO(dev
)->gen
< 4)
6435 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6437 intel_get_pipe_timings(crtc
, pipe_config
);
6439 i9xx_get_pfit_config(crtc
, pipe_config
);
6441 if (INTEL_INFO(dev
)->gen
>= 4) {
6442 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6443 pipe_config
->pixel_multiplier
=
6444 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6445 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6446 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6447 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6448 tmp
= I915_READ(DPLL(crtc
->pipe
));
6449 pipe_config
->pixel_multiplier
=
6450 ((tmp
& SDVO_MULTIPLIER_MASK
)
6451 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6453 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6454 * port and will be fixed up in the encoder->get_config
6456 pipe_config
->pixel_multiplier
= 1;
6458 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6459 if (!IS_VALLEYVIEW(dev
)) {
6460 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6461 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6463 /* Mask out read-only status bits. */
6464 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6465 DPLL_PORTC_READY_MASK
|
6466 DPLL_PORTB_READY_MASK
);
6469 if (IS_CHERRYVIEW(dev
))
6470 chv_crtc_clock_get(crtc
, pipe_config
);
6471 else if (IS_VALLEYVIEW(dev
))
6472 vlv_crtc_clock_get(crtc
, pipe_config
);
6474 i9xx_crtc_clock_get(crtc
, pipe_config
);
6479 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6481 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6482 struct intel_encoder
*encoder
;
6484 bool has_lvds
= false;
6485 bool has_cpu_edp
= false;
6486 bool has_panel
= false;
6487 bool has_ck505
= false;
6488 bool can_ssc
= false;
6490 /* We need to take the global config into account */
6491 for_each_intel_encoder(dev
, encoder
) {
6492 switch (encoder
->type
) {
6493 case INTEL_OUTPUT_LVDS
:
6497 case INTEL_OUTPUT_EDP
:
6499 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6505 if (HAS_PCH_IBX(dev
)) {
6506 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6507 can_ssc
= has_ck505
;
6513 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6514 has_panel
, has_lvds
, has_ck505
);
6516 /* Ironlake: try to setup display ref clock before DPLL
6517 * enabling. This is only under driver's control after
6518 * PCH B stepping, previous chipset stepping should be
6519 * ignoring this setting.
6521 val
= I915_READ(PCH_DREF_CONTROL
);
6523 /* As we must carefully and slowly disable/enable each source in turn,
6524 * compute the final state we want first and check if we need to
6525 * make any changes at all.
6528 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6530 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6532 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6534 final
&= ~DREF_SSC_SOURCE_MASK
;
6535 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6536 final
&= ~DREF_SSC1_ENABLE
;
6539 final
|= DREF_SSC_SOURCE_ENABLE
;
6541 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6542 final
|= DREF_SSC1_ENABLE
;
6545 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6546 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6548 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6550 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6552 final
|= DREF_SSC_SOURCE_DISABLE
;
6553 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6559 /* Always enable nonspread source */
6560 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6563 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6565 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6568 val
&= ~DREF_SSC_SOURCE_MASK
;
6569 val
|= DREF_SSC_SOURCE_ENABLE
;
6571 /* SSC must be turned on before enabling the CPU output */
6572 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6573 DRM_DEBUG_KMS("Using SSC on panel\n");
6574 val
|= DREF_SSC1_ENABLE
;
6576 val
&= ~DREF_SSC1_ENABLE
;
6578 /* Get SSC going before enabling the outputs */
6579 I915_WRITE(PCH_DREF_CONTROL
, val
);
6580 POSTING_READ(PCH_DREF_CONTROL
);
6583 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6585 /* Enable CPU source on CPU attached eDP */
6587 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6588 DRM_DEBUG_KMS("Using SSC on eDP\n");
6589 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6591 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6593 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6595 I915_WRITE(PCH_DREF_CONTROL
, val
);
6596 POSTING_READ(PCH_DREF_CONTROL
);
6599 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6601 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6603 /* Turn off CPU output */
6604 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6606 I915_WRITE(PCH_DREF_CONTROL
, val
);
6607 POSTING_READ(PCH_DREF_CONTROL
);
6610 /* Turn off the SSC source */
6611 val
&= ~DREF_SSC_SOURCE_MASK
;
6612 val
|= DREF_SSC_SOURCE_DISABLE
;
6615 val
&= ~DREF_SSC1_ENABLE
;
6617 I915_WRITE(PCH_DREF_CONTROL
, val
);
6618 POSTING_READ(PCH_DREF_CONTROL
);
6622 BUG_ON(val
!= final
);
6625 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6629 tmp
= I915_READ(SOUTH_CHICKEN2
);
6630 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6631 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6633 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6634 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6635 DRM_ERROR("FDI mPHY reset assert timeout\n");
6637 tmp
= I915_READ(SOUTH_CHICKEN2
);
6638 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6639 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6641 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6642 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6643 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6646 /* WaMPhyProgramming:hsw */
6647 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6651 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6652 tmp
&= ~(0xFF << 24);
6653 tmp
|= (0x12 << 24);
6654 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6656 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6658 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6660 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6662 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6664 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6665 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6666 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6668 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6669 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6670 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6672 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6675 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6677 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6680 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6682 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6685 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6687 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6690 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6692 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6693 tmp
&= ~(0xFF << 16);
6694 tmp
|= (0x1C << 16);
6695 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6697 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6698 tmp
&= ~(0xFF << 16);
6699 tmp
|= (0x1C << 16);
6700 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6702 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6704 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6706 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6708 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6710 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6711 tmp
&= ~(0xF << 28);
6713 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6715 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6716 tmp
&= ~(0xF << 28);
6718 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6721 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6722 * Programming" based on the parameters passed:
6723 * - Sequence to enable CLKOUT_DP
6724 * - Sequence to enable CLKOUT_DP without spread
6725 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6727 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6733 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6735 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6736 with_fdi
, "LP PCH doesn't have FDI\n"))
6739 mutex_lock(&dev_priv
->dpio_lock
);
6741 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6742 tmp
&= ~SBI_SSCCTL_DISABLE
;
6743 tmp
|= SBI_SSCCTL_PATHALT
;
6744 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6749 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6750 tmp
&= ~SBI_SSCCTL_PATHALT
;
6751 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6754 lpt_reset_fdi_mphy(dev_priv
);
6755 lpt_program_fdi_mphy(dev_priv
);
6759 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6760 SBI_GEN0
: SBI_DBUFF0
;
6761 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6762 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6763 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6765 mutex_unlock(&dev_priv
->dpio_lock
);
6768 /* Sequence to disable CLKOUT_DP */
6769 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6771 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6774 mutex_lock(&dev_priv
->dpio_lock
);
6776 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6777 SBI_GEN0
: SBI_DBUFF0
;
6778 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6779 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6780 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6782 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6783 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6784 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6785 tmp
|= SBI_SSCCTL_PATHALT
;
6786 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6789 tmp
|= SBI_SSCCTL_DISABLE
;
6790 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6793 mutex_unlock(&dev_priv
->dpio_lock
);
6796 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6798 struct intel_encoder
*encoder
;
6799 bool has_vga
= false;
6801 for_each_intel_encoder(dev
, encoder
) {
6802 switch (encoder
->type
) {
6803 case INTEL_OUTPUT_ANALOG
:
6810 lpt_enable_clkout_dp(dev
, true, true);
6812 lpt_disable_clkout_dp(dev
);
6816 * Initialize reference clocks when the driver loads
6818 void intel_init_pch_refclk(struct drm_device
*dev
)
6820 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6821 ironlake_init_pch_refclk(dev
);
6822 else if (HAS_PCH_LPT(dev
))
6823 lpt_init_pch_refclk(dev
);
6826 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6828 struct drm_device
*dev
= crtc
->dev
;
6829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6830 struct intel_encoder
*encoder
;
6831 int num_connectors
= 0;
6832 bool is_lvds
= false;
6834 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6835 switch (encoder
->type
) {
6836 case INTEL_OUTPUT_LVDS
:
6843 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6844 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6845 dev_priv
->vbt
.lvds_ssc_freq
);
6846 return dev_priv
->vbt
.lvds_ssc_freq
;
6852 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6854 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6856 int pipe
= intel_crtc
->pipe
;
6861 switch (intel_crtc
->config
.pipe_bpp
) {
6863 val
|= PIPECONF_6BPC
;
6866 val
|= PIPECONF_8BPC
;
6869 val
|= PIPECONF_10BPC
;
6872 val
|= PIPECONF_12BPC
;
6875 /* Case prevented by intel_choose_pipe_bpp_dither. */
6879 if (intel_crtc
->config
.dither
)
6880 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6882 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6883 val
|= PIPECONF_INTERLACED_ILK
;
6885 val
|= PIPECONF_PROGRESSIVE
;
6887 if (intel_crtc
->config
.limited_color_range
)
6888 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6890 I915_WRITE(PIPECONF(pipe
), val
);
6891 POSTING_READ(PIPECONF(pipe
));
6895 * Set up the pipe CSC unit.
6897 * Currently only full range RGB to limited range RGB conversion
6898 * is supported, but eventually this should handle various
6899 * RGB<->YCbCr scenarios as well.
6901 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6903 struct drm_device
*dev
= crtc
->dev
;
6904 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6905 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6906 int pipe
= intel_crtc
->pipe
;
6907 uint16_t coeff
= 0x7800; /* 1.0 */
6910 * TODO: Check what kind of values actually come out of the pipe
6911 * with these coeff/postoff values and adjust to get the best
6912 * accuracy. Perhaps we even need to take the bpc value into
6916 if (intel_crtc
->config
.limited_color_range
)
6917 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6920 * GY/GU and RY/RU should be the other way around according
6921 * to BSpec, but reality doesn't agree. Just set them up in
6922 * a way that results in the correct picture.
6924 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6925 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6927 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6928 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6930 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6931 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6933 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6934 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6935 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6937 if (INTEL_INFO(dev
)->gen
> 6) {
6938 uint16_t postoff
= 0;
6940 if (intel_crtc
->config
.limited_color_range
)
6941 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6943 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6944 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6945 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6947 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6949 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6951 if (intel_crtc
->config
.limited_color_range
)
6952 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6954 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6958 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6960 struct drm_device
*dev
= crtc
->dev
;
6961 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6962 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6963 enum pipe pipe
= intel_crtc
->pipe
;
6964 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6969 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6970 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6972 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6973 val
|= PIPECONF_INTERLACED_ILK
;
6975 val
|= PIPECONF_PROGRESSIVE
;
6977 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6978 POSTING_READ(PIPECONF(cpu_transcoder
));
6980 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6981 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6983 if (IS_BROADWELL(dev
)) {
6986 switch (intel_crtc
->config
.pipe_bpp
) {
6988 val
|= PIPEMISC_DITHER_6_BPC
;
6991 val
|= PIPEMISC_DITHER_8_BPC
;
6994 val
|= PIPEMISC_DITHER_10_BPC
;
6997 val
|= PIPEMISC_DITHER_12_BPC
;
7000 /* Case prevented by pipe_config_set_bpp. */
7004 if (intel_crtc
->config
.dither
)
7005 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7007 I915_WRITE(PIPEMISC(pipe
), val
);
7011 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7012 intel_clock_t
*clock
,
7013 bool *has_reduced_clock
,
7014 intel_clock_t
*reduced_clock
)
7016 struct drm_device
*dev
= crtc
->dev
;
7017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7018 struct intel_encoder
*intel_encoder
;
7020 const intel_limit_t
*limit
;
7021 bool ret
, is_lvds
= false;
7023 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7024 switch (intel_encoder
->type
) {
7025 case INTEL_OUTPUT_LVDS
:
7031 refclk
= ironlake_get_refclk(crtc
);
7034 * Returns a set of divisors for the desired target clock with the given
7035 * refclk, or FALSE. The returned values represent the clock equation:
7036 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7038 limit
= intel_limit(crtc
, refclk
);
7039 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
7040 to_intel_crtc(crtc
)->config
.port_clock
,
7041 refclk
, NULL
, clock
);
7045 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7047 * Ensure we match the reduced clock's P to the target clock.
7048 * If the clocks don't match, we can't switch the display clock
7049 * by using the FP0/FP1. In such case we will disable the LVDS
7050 * downclock feature.
7052 *has_reduced_clock
=
7053 dev_priv
->display
.find_dpll(limit
, crtc
,
7054 dev_priv
->lvds_downclock
,
7062 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7065 * Account for spread spectrum to avoid
7066 * oversubscribing the link. Max center spread
7067 * is 2.5%; use 5% for safety's sake.
7069 u32 bps
= target_clock
* bpp
* 21 / 20;
7070 return DIV_ROUND_UP(bps
, link_bw
* 8);
7073 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7075 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7078 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7080 intel_clock_t
*reduced_clock
, u32
*fp2
)
7082 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7083 struct drm_device
*dev
= crtc
->dev
;
7084 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7085 struct intel_encoder
*intel_encoder
;
7087 int factor
, num_connectors
= 0;
7088 bool is_lvds
= false, is_sdvo
= false;
7090 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7091 switch (intel_encoder
->type
) {
7092 case INTEL_OUTPUT_LVDS
:
7095 case INTEL_OUTPUT_SDVO
:
7096 case INTEL_OUTPUT_HDMI
:
7104 /* Enable autotuning of the PLL clock (if permissible) */
7107 if ((intel_panel_use_ssc(dev_priv
) &&
7108 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7109 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7111 } else if (intel_crtc
->config
.sdvo_tv_clock
)
7114 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
7117 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7123 dpll
|= DPLLB_MODE_LVDS
;
7125 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7127 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
7128 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7131 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7132 if (intel_crtc
->config
.has_dp_encoder
)
7133 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7135 /* compute bitmask from p1 value */
7136 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7138 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7140 switch (intel_crtc
->config
.dpll
.p2
) {
7142 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7145 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7148 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7151 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7155 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7156 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7158 dpll
|= PLL_REF_INPUT_DREFCLK
;
7160 return dpll
| DPLL_VCO_ENABLE
;
7163 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7165 struct drm_framebuffer
*fb
)
7167 struct drm_device
*dev
= crtc
->dev
;
7168 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7169 int num_connectors
= 0;
7170 intel_clock_t clock
, reduced_clock
;
7171 u32 dpll
= 0, fp
= 0, fp2
= 0;
7172 bool ok
, has_reduced_clock
= false;
7173 bool is_lvds
= false;
7174 struct intel_encoder
*encoder
;
7175 struct intel_shared_dpll
*pll
;
7177 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7178 switch (encoder
->type
) {
7179 case INTEL_OUTPUT_LVDS
:
7187 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7188 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7190 ok
= ironlake_compute_clocks(crtc
, &clock
,
7191 &has_reduced_clock
, &reduced_clock
);
7192 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7193 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7196 /* Compat-code for transition, will disappear. */
7197 if (!intel_crtc
->config
.clock_set
) {
7198 intel_crtc
->config
.dpll
.n
= clock
.n
;
7199 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7200 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7201 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7202 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7205 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7206 if (intel_crtc
->config
.has_pch_encoder
) {
7207 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7208 if (has_reduced_clock
)
7209 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7211 dpll
= ironlake_compute_dpll(intel_crtc
,
7212 &fp
, &reduced_clock
,
7213 has_reduced_clock
? &fp2
: NULL
);
7215 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7216 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7217 if (has_reduced_clock
)
7218 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7220 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7222 pll
= intel_get_shared_dpll(intel_crtc
);
7224 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7225 pipe_name(intel_crtc
->pipe
));
7229 intel_put_shared_dpll(intel_crtc
);
7231 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7232 intel_crtc
->lowfreq_avail
= true;
7234 intel_crtc
->lowfreq_avail
= false;
7239 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7240 struct intel_link_m_n
*m_n
)
7242 struct drm_device
*dev
= crtc
->base
.dev
;
7243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7244 enum pipe pipe
= crtc
->pipe
;
7246 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7247 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7248 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7250 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7251 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7252 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7255 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7256 enum transcoder transcoder
,
7257 struct intel_link_m_n
*m_n
,
7258 struct intel_link_m_n
*m2_n2
)
7260 struct drm_device
*dev
= crtc
->base
.dev
;
7261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7262 enum pipe pipe
= crtc
->pipe
;
7264 if (INTEL_INFO(dev
)->gen
>= 5) {
7265 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7266 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7267 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7269 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7270 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7271 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7272 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7273 * gen < 8) and if DRRS is supported (to make sure the
7274 * registers are not unnecessarily read).
7276 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7277 crtc
->config
.has_drrs
) {
7278 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7279 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7280 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7282 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7283 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7284 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7287 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7288 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7289 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7291 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7292 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7293 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7297 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7298 struct intel_crtc_config
*pipe_config
)
7300 if (crtc
->config
.has_pch_encoder
)
7301 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7303 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7304 &pipe_config
->dp_m_n
,
7305 &pipe_config
->dp_m2_n2
);
7308 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7309 struct intel_crtc_config
*pipe_config
)
7311 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7312 &pipe_config
->fdi_m_n
, NULL
);
7315 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7316 struct intel_crtc_config
*pipe_config
)
7318 struct drm_device
*dev
= crtc
->base
.dev
;
7319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7322 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7324 if (tmp
& PF_ENABLE
) {
7325 pipe_config
->pch_pfit
.enabled
= true;
7326 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7327 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7329 /* We currently do not free assignements of panel fitters on
7330 * ivb/hsw (since we don't use the higher upscaling modes which
7331 * differentiates them) so just WARN about this case for now. */
7333 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7334 PF_PIPE_SEL_IVB(crtc
->pipe
));
7339 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7340 struct intel_plane_config
*plane_config
)
7342 struct drm_device
*dev
= crtc
->base
.dev
;
7343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7344 u32 val
, base
, offset
;
7345 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7346 int fourcc
, pixel_format
;
7349 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7350 if (!crtc
->base
.primary
->fb
) {
7351 DRM_DEBUG_KMS("failed to alloc fb\n");
7355 val
= I915_READ(DSPCNTR(plane
));
7357 if (INTEL_INFO(dev
)->gen
>= 4)
7358 if (val
& DISPPLANE_TILED
)
7359 plane_config
->tiled
= true;
7361 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7362 fourcc
= intel_format_to_fourcc(pixel_format
);
7363 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7364 crtc
->base
.primary
->fb
->bits_per_pixel
=
7365 drm_format_plane_cpp(fourcc
, 0) * 8;
7367 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7368 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7369 offset
= I915_READ(DSPOFFSET(plane
));
7371 if (plane_config
->tiled
)
7372 offset
= I915_READ(DSPTILEOFF(plane
));
7374 offset
= I915_READ(DSPLINOFF(plane
));
7376 plane_config
->base
= base
;
7378 val
= I915_READ(PIPESRC(pipe
));
7379 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7380 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7382 val
= I915_READ(DSPSTRIDE(pipe
));
7383 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7385 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7386 plane_config
->tiled
);
7388 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7391 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7392 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7393 crtc
->base
.primary
->fb
->height
,
7394 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7395 crtc
->base
.primary
->fb
->pitches
[0],
7396 plane_config
->size
);
7399 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7400 struct intel_crtc_config
*pipe_config
)
7402 struct drm_device
*dev
= crtc
->base
.dev
;
7403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7406 if (!intel_display_power_enabled(dev_priv
,
7407 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7410 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7411 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7413 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7414 if (!(tmp
& PIPECONF_ENABLE
))
7417 switch (tmp
& PIPECONF_BPC_MASK
) {
7419 pipe_config
->pipe_bpp
= 18;
7422 pipe_config
->pipe_bpp
= 24;
7424 case PIPECONF_10BPC
:
7425 pipe_config
->pipe_bpp
= 30;
7427 case PIPECONF_12BPC
:
7428 pipe_config
->pipe_bpp
= 36;
7434 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7435 pipe_config
->limited_color_range
= true;
7437 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7438 struct intel_shared_dpll
*pll
;
7440 pipe_config
->has_pch_encoder
= true;
7442 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7443 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7444 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7446 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7448 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7449 pipe_config
->shared_dpll
=
7450 (enum intel_dpll_id
) crtc
->pipe
;
7452 tmp
= I915_READ(PCH_DPLL_SEL
);
7453 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7454 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7456 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7459 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7461 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7462 &pipe_config
->dpll_hw_state
));
7464 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7465 pipe_config
->pixel_multiplier
=
7466 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7467 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7469 ironlake_pch_clock_get(crtc
, pipe_config
);
7471 pipe_config
->pixel_multiplier
= 1;
7474 intel_get_pipe_timings(crtc
, pipe_config
);
7476 ironlake_get_pfit_config(crtc
, pipe_config
);
7481 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7483 struct drm_device
*dev
= dev_priv
->dev
;
7484 struct intel_crtc
*crtc
;
7486 for_each_intel_crtc(dev
, crtc
)
7487 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7488 pipe_name(crtc
->pipe
));
7490 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7491 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7492 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7493 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7494 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7495 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7496 "CPU PWM1 enabled\n");
7497 if (IS_HASWELL(dev
))
7498 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7499 "CPU PWM2 enabled\n");
7500 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7501 "PCH PWM1 enabled\n");
7502 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7503 "Utility pin enabled\n");
7504 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7507 * In theory we can still leave IRQs enabled, as long as only the HPD
7508 * interrupts remain enabled. We used to check for that, but since it's
7509 * gen-specific and since we only disable LCPLL after we fully disable
7510 * the interrupts, the check below should be enough.
7512 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7515 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7517 struct drm_device
*dev
= dev_priv
->dev
;
7519 if (IS_HASWELL(dev
))
7520 return I915_READ(D_COMP_HSW
);
7522 return I915_READ(D_COMP_BDW
);
7525 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7527 struct drm_device
*dev
= dev_priv
->dev
;
7529 if (IS_HASWELL(dev
)) {
7530 mutex_lock(&dev_priv
->rps
.hw_lock
);
7531 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7533 DRM_ERROR("Failed to write to D_COMP\n");
7534 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7536 I915_WRITE(D_COMP_BDW
, val
);
7537 POSTING_READ(D_COMP_BDW
);
7542 * This function implements pieces of two sequences from BSpec:
7543 * - Sequence for display software to disable LCPLL
7544 * - Sequence for display software to allow package C8+
7545 * The steps implemented here are just the steps that actually touch the LCPLL
7546 * register. Callers should take care of disabling all the display engine
7547 * functions, doing the mode unset, fixing interrupts, etc.
7549 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7550 bool switch_to_fclk
, bool allow_power_down
)
7554 assert_can_disable_lcpll(dev_priv
);
7556 val
= I915_READ(LCPLL_CTL
);
7558 if (switch_to_fclk
) {
7559 val
|= LCPLL_CD_SOURCE_FCLK
;
7560 I915_WRITE(LCPLL_CTL
, val
);
7562 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7563 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7564 DRM_ERROR("Switching to FCLK failed\n");
7566 val
= I915_READ(LCPLL_CTL
);
7569 val
|= LCPLL_PLL_DISABLE
;
7570 I915_WRITE(LCPLL_CTL
, val
);
7571 POSTING_READ(LCPLL_CTL
);
7573 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7574 DRM_ERROR("LCPLL still locked\n");
7576 val
= hsw_read_dcomp(dev_priv
);
7577 val
|= D_COMP_COMP_DISABLE
;
7578 hsw_write_dcomp(dev_priv
, val
);
7581 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7583 DRM_ERROR("D_COMP RCOMP still in progress\n");
7585 if (allow_power_down
) {
7586 val
= I915_READ(LCPLL_CTL
);
7587 val
|= LCPLL_POWER_DOWN_ALLOW
;
7588 I915_WRITE(LCPLL_CTL
, val
);
7589 POSTING_READ(LCPLL_CTL
);
7594 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7597 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7600 unsigned long irqflags
;
7602 val
= I915_READ(LCPLL_CTL
);
7604 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7605 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7609 * Make sure we're not on PC8 state before disabling PC8, otherwise
7610 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7612 * The other problem is that hsw_restore_lcpll() is called as part of
7613 * the runtime PM resume sequence, so we can't just call
7614 * gen6_gt_force_wake_get() because that function calls
7615 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7616 * while we are on the resume sequence. So to solve this problem we have
7617 * to call special forcewake code that doesn't touch runtime PM and
7618 * doesn't enable the forcewake delayed work.
7620 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7621 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7622 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7623 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7625 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7626 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7627 I915_WRITE(LCPLL_CTL
, val
);
7628 POSTING_READ(LCPLL_CTL
);
7631 val
= hsw_read_dcomp(dev_priv
);
7632 val
|= D_COMP_COMP_FORCE
;
7633 val
&= ~D_COMP_COMP_DISABLE
;
7634 hsw_write_dcomp(dev_priv
, val
);
7636 val
= I915_READ(LCPLL_CTL
);
7637 val
&= ~LCPLL_PLL_DISABLE
;
7638 I915_WRITE(LCPLL_CTL
, val
);
7640 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7641 DRM_ERROR("LCPLL not locked yet\n");
7643 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7644 val
= I915_READ(LCPLL_CTL
);
7645 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7646 I915_WRITE(LCPLL_CTL
, val
);
7648 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7649 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7650 DRM_ERROR("Switching back to LCPLL failed\n");
7653 /* See the big comment above. */
7654 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7655 if (--dev_priv
->uncore
.forcewake_count
== 0)
7656 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7657 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7661 * Package states C8 and deeper are really deep PC states that can only be
7662 * reached when all the devices on the system allow it, so even if the graphics
7663 * device allows PC8+, it doesn't mean the system will actually get to these
7664 * states. Our driver only allows PC8+ when going into runtime PM.
7666 * The requirements for PC8+ are that all the outputs are disabled, the power
7667 * well is disabled and most interrupts are disabled, and these are also
7668 * requirements for runtime PM. When these conditions are met, we manually do
7669 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7670 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7673 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7674 * the state of some registers, so when we come back from PC8+ we need to
7675 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7676 * need to take care of the registers kept by RC6. Notice that this happens even
7677 * if we don't put the device in PCI D3 state (which is what currently happens
7678 * because of the runtime PM support).
7680 * For more, read "Display Sequences for Package C8" on the hardware
7683 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7685 struct drm_device
*dev
= dev_priv
->dev
;
7688 DRM_DEBUG_KMS("Enabling package C8+\n");
7690 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7691 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7692 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7693 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7696 lpt_disable_clkout_dp(dev
);
7697 hsw_disable_lcpll(dev_priv
, true, true);
7700 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7702 struct drm_device
*dev
= dev_priv
->dev
;
7705 DRM_DEBUG_KMS("Disabling package C8+\n");
7707 hsw_restore_lcpll(dev_priv
);
7708 lpt_init_pch_refclk(dev
);
7710 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7711 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7712 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7713 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7716 intel_prepare_ddi(dev
);
7719 static void snb_modeset_global_resources(struct drm_device
*dev
)
7721 modeset_update_crtc_power_domains(dev
);
7724 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7726 modeset_update_crtc_power_domains(dev
);
7729 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7731 struct drm_framebuffer
*fb
)
7733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7735 if (!intel_ddi_pll_select(intel_crtc
))
7738 intel_crtc
->lowfreq_avail
= false;
7743 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7745 struct intel_crtc_config
*pipe_config
)
7747 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7749 switch (pipe_config
->ddi_pll_sel
) {
7750 case PORT_CLK_SEL_WRPLL1
:
7751 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7753 case PORT_CLK_SEL_WRPLL2
:
7754 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7759 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7760 struct intel_crtc_config
*pipe_config
)
7762 struct drm_device
*dev
= crtc
->base
.dev
;
7763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7764 struct intel_shared_dpll
*pll
;
7768 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7770 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7772 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
7774 if (pipe_config
->shared_dpll
>= 0) {
7775 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7777 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7778 &pipe_config
->dpll_hw_state
));
7782 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7783 * DDI E. So just check whether this pipe is wired to DDI E and whether
7784 * the PCH transcoder is on.
7786 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7787 pipe_config
->has_pch_encoder
= true;
7789 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7790 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7791 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7793 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7797 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7798 struct intel_crtc_config
*pipe_config
)
7800 struct drm_device
*dev
= crtc
->base
.dev
;
7801 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7802 enum intel_display_power_domain pfit_domain
;
7805 if (!intel_display_power_enabled(dev_priv
,
7806 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7809 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7810 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7812 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7813 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7814 enum pipe trans_edp_pipe
;
7815 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7817 WARN(1, "unknown pipe linked to edp transcoder\n");
7818 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7819 case TRANS_DDI_EDP_INPUT_A_ON
:
7820 trans_edp_pipe
= PIPE_A
;
7822 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7823 trans_edp_pipe
= PIPE_B
;
7825 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7826 trans_edp_pipe
= PIPE_C
;
7830 if (trans_edp_pipe
== crtc
->pipe
)
7831 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7834 if (!intel_display_power_enabled(dev_priv
,
7835 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7838 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7839 if (!(tmp
& PIPECONF_ENABLE
))
7842 haswell_get_ddi_port_state(crtc
, pipe_config
);
7844 intel_get_pipe_timings(crtc
, pipe_config
);
7846 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7847 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7848 ironlake_get_pfit_config(crtc
, pipe_config
);
7850 if (IS_HASWELL(dev
))
7851 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7852 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7854 pipe_config
->pixel_multiplier
= 1;
7862 } hdmi_audio_clock
[] = {
7863 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7864 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7865 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7866 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7867 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7868 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7869 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7870 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7871 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7872 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7875 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7876 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7880 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7881 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7885 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7886 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7890 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7891 hdmi_audio_clock
[i
].clock
,
7892 hdmi_audio_clock
[i
].config
);
7894 return hdmi_audio_clock
[i
].config
;
7897 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7898 int reg_eldv
, uint32_t bits_eldv
,
7899 int reg_elda
, uint32_t bits_elda
,
7902 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7903 uint8_t *eld
= connector
->eld
;
7906 i
= I915_READ(reg_eldv
);
7915 i
= I915_READ(reg_elda
);
7917 I915_WRITE(reg_elda
, i
);
7919 for (i
= 0; i
< eld
[2]; i
++)
7920 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7926 static void g4x_write_eld(struct drm_connector
*connector
,
7927 struct drm_crtc
*crtc
,
7928 struct drm_display_mode
*mode
)
7930 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7931 uint8_t *eld
= connector
->eld
;
7936 i
= I915_READ(G4X_AUD_VID_DID
);
7938 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7939 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7941 eldv
= G4X_ELDV_DEVCTG
;
7943 if (intel_eld_uptodate(connector
,
7944 G4X_AUD_CNTL_ST
, eldv
,
7945 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7946 G4X_HDMIW_HDMIEDID
))
7949 i
= I915_READ(G4X_AUD_CNTL_ST
);
7950 i
&= ~(eldv
| G4X_ELD_ADDR
);
7951 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7952 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7957 len
= min_t(uint8_t, eld
[2], len
);
7958 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7959 for (i
= 0; i
< len
; i
++)
7960 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7962 i
= I915_READ(G4X_AUD_CNTL_ST
);
7964 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7967 static void haswell_write_eld(struct drm_connector
*connector
,
7968 struct drm_crtc
*crtc
,
7969 struct drm_display_mode
*mode
)
7971 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7972 uint8_t *eld
= connector
->eld
;
7976 int pipe
= to_intel_crtc(crtc
)->pipe
;
7979 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7980 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7981 int aud_config
= HSW_AUD_CFG(pipe
);
7982 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7984 /* Audio output enable */
7985 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7986 tmp
= I915_READ(aud_cntrl_st2
);
7987 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7988 I915_WRITE(aud_cntrl_st2
, tmp
);
7989 POSTING_READ(aud_cntrl_st2
);
7991 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
7993 /* Set ELD valid state */
7994 tmp
= I915_READ(aud_cntrl_st2
);
7995 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7996 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7997 I915_WRITE(aud_cntrl_st2
, tmp
);
7998 tmp
= I915_READ(aud_cntrl_st2
);
7999 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
8001 /* Enable HDMI mode */
8002 tmp
= I915_READ(aud_config
);
8003 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
8004 /* clear N_programing_enable and N_value_index */
8005 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
8006 I915_WRITE(aud_config
, tmp
);
8008 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8010 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
8012 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8013 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8014 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8015 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8017 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8020 if (intel_eld_uptodate(connector
,
8021 aud_cntrl_st2
, eldv
,
8022 aud_cntl_st
, IBX_ELD_ADDRESS
,
8026 i
= I915_READ(aud_cntrl_st2
);
8028 I915_WRITE(aud_cntrl_st2
, i
);
8033 i
= I915_READ(aud_cntl_st
);
8034 i
&= ~IBX_ELD_ADDRESS
;
8035 I915_WRITE(aud_cntl_st
, i
);
8036 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
8037 DRM_DEBUG_DRIVER("port num:%d\n", i
);
8039 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8040 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8041 for (i
= 0; i
< len
; i
++)
8042 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8044 i
= I915_READ(aud_cntrl_st2
);
8046 I915_WRITE(aud_cntrl_st2
, i
);
8050 static void ironlake_write_eld(struct drm_connector
*connector
,
8051 struct drm_crtc
*crtc
,
8052 struct drm_display_mode
*mode
)
8054 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
8055 uint8_t *eld
= connector
->eld
;
8063 int pipe
= to_intel_crtc(crtc
)->pipe
;
8065 if (HAS_PCH_IBX(connector
->dev
)) {
8066 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
8067 aud_config
= IBX_AUD_CFG(pipe
);
8068 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
8069 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
8070 } else if (IS_VALLEYVIEW(connector
->dev
)) {
8071 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
8072 aud_config
= VLV_AUD_CFG(pipe
);
8073 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
8074 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
8076 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
8077 aud_config
= CPT_AUD_CFG(pipe
);
8078 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
8079 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
8082 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8084 if (IS_VALLEYVIEW(connector
->dev
)) {
8085 struct intel_encoder
*intel_encoder
;
8086 struct intel_digital_port
*intel_dig_port
;
8088 intel_encoder
= intel_attached_encoder(connector
);
8089 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
8090 i
= intel_dig_port
->port
;
8092 i
= I915_READ(aud_cntl_st
);
8093 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
8094 /* DIP_Port_Select, 0x1 = PortB */
8098 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8099 /* operate blindly on all ports */
8100 eldv
= IBX_ELD_VALIDB
;
8101 eldv
|= IBX_ELD_VALIDB
<< 4;
8102 eldv
|= IBX_ELD_VALIDB
<< 8;
8104 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
8105 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
8108 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8109 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8110 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8111 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8113 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8116 if (intel_eld_uptodate(connector
,
8117 aud_cntrl_st2
, eldv
,
8118 aud_cntl_st
, IBX_ELD_ADDRESS
,
8122 i
= I915_READ(aud_cntrl_st2
);
8124 I915_WRITE(aud_cntrl_st2
, i
);
8129 i
= I915_READ(aud_cntl_st
);
8130 i
&= ~IBX_ELD_ADDRESS
;
8131 I915_WRITE(aud_cntl_st
, i
);
8133 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8134 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8135 for (i
= 0; i
< len
; i
++)
8136 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8138 i
= I915_READ(aud_cntrl_st2
);
8140 I915_WRITE(aud_cntrl_st2
, i
);
8143 void intel_write_eld(struct drm_encoder
*encoder
,
8144 struct drm_display_mode
*mode
)
8146 struct drm_crtc
*crtc
= encoder
->crtc
;
8147 struct drm_connector
*connector
;
8148 struct drm_device
*dev
= encoder
->dev
;
8149 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8151 connector
= drm_select_eld(encoder
, mode
);
8155 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8158 connector
->encoder
->base
.id
,
8159 connector
->encoder
->name
);
8161 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
8163 if (dev_priv
->display
.write_eld
)
8164 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
8167 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8169 struct drm_device
*dev
= crtc
->dev
;
8170 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8171 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8172 uint32_t cntl
= 0, size
= 0;
8175 unsigned int width
= intel_crtc
->cursor_width
;
8176 unsigned int height
= intel_crtc
->cursor_height
;
8177 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8181 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8192 cntl
|= CURSOR_ENABLE
|
8193 CURSOR_GAMMA_ENABLE
|
8194 CURSOR_FORMAT_ARGB
|
8195 CURSOR_STRIDE(stride
);
8197 size
= (height
<< 12) | width
;
8200 if (intel_crtc
->cursor_cntl
!= 0 &&
8201 (intel_crtc
->cursor_base
!= base
||
8202 intel_crtc
->cursor_size
!= size
||
8203 intel_crtc
->cursor_cntl
!= cntl
)) {
8204 /* On these chipsets we can only modify the base/size/stride
8205 * whilst the cursor is disabled.
8207 I915_WRITE(_CURACNTR
, 0);
8208 POSTING_READ(_CURACNTR
);
8209 intel_crtc
->cursor_cntl
= 0;
8212 if (intel_crtc
->cursor_base
!= base
)
8213 I915_WRITE(_CURABASE
, base
);
8215 if (intel_crtc
->cursor_size
!= size
) {
8216 I915_WRITE(CURSIZE
, size
);
8217 intel_crtc
->cursor_size
= size
;
8220 if (intel_crtc
->cursor_cntl
!= cntl
) {
8221 I915_WRITE(_CURACNTR
, cntl
);
8222 POSTING_READ(_CURACNTR
);
8223 intel_crtc
->cursor_cntl
= cntl
;
8227 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8229 struct drm_device
*dev
= crtc
->dev
;
8230 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8231 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8232 int pipe
= intel_crtc
->pipe
;
8237 cntl
= MCURSOR_GAMMA_ENABLE
;
8238 switch (intel_crtc
->cursor_width
) {
8240 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8243 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8246 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8252 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8254 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8255 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8257 if (intel_crtc
->cursor_cntl
!= cntl
) {
8258 I915_WRITE(CURCNTR(pipe
), cntl
);
8259 POSTING_READ(CURCNTR(pipe
));
8260 intel_crtc
->cursor_cntl
= cntl
;
8263 /* and commit changes on next vblank */
8264 I915_WRITE(CURBASE(pipe
), base
);
8265 POSTING_READ(CURBASE(pipe
));
8268 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8269 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8272 struct drm_device
*dev
= crtc
->dev
;
8273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8274 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8275 int pipe
= intel_crtc
->pipe
;
8276 int x
= crtc
->cursor_x
;
8277 int y
= crtc
->cursor_y
;
8278 u32 base
= 0, pos
= 0;
8281 base
= intel_crtc
->cursor_addr
;
8283 if (x
>= intel_crtc
->config
.pipe_src_w
)
8286 if (y
>= intel_crtc
->config
.pipe_src_h
)
8290 if (x
+ intel_crtc
->cursor_width
<= 0)
8293 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8296 pos
|= x
<< CURSOR_X_SHIFT
;
8299 if (y
+ intel_crtc
->cursor_height
<= 0)
8302 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8305 pos
|= y
<< CURSOR_Y_SHIFT
;
8307 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8310 I915_WRITE(CURPOS(pipe
), pos
);
8312 if (IS_845G(dev
) || IS_I865G(dev
))
8313 i845_update_cursor(crtc
, base
);
8315 i9xx_update_cursor(crtc
, base
);
8316 intel_crtc
->cursor_base
= base
;
8319 static bool cursor_size_ok(struct drm_device
*dev
,
8320 uint32_t width
, uint32_t height
)
8322 if (width
== 0 || height
== 0)
8326 * 845g/865g are special in that they are only limited by
8327 * the width of their cursors, the height is arbitrary up to
8328 * the precision of the register. Everything else requires
8329 * square cursors, limited to a few power-of-two sizes.
8331 if (IS_845G(dev
) || IS_I865G(dev
)) {
8332 if ((width
& 63) != 0)
8335 if (width
> (IS_845G(dev
) ? 64 : 512))
8341 switch (width
| height
) {
8357 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8359 * Note that the object's reference will be consumed if the update fails. If
8360 * the update succeeds, the reference of the old object (if any) will be
8363 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8364 struct drm_i915_gem_object
*obj
,
8365 uint32_t width
, uint32_t height
)
8367 struct drm_device
*dev
= crtc
->dev
;
8368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8370 enum pipe pipe
= intel_crtc
->pipe
;
8371 unsigned old_width
, stride
;
8375 /* if we want to turn off the cursor ignore width and height */
8377 DRM_DEBUG_KMS("cursor off\n");
8379 mutex_lock(&dev
->struct_mutex
);
8383 /* Check for which cursor types we support */
8384 if (!cursor_size_ok(dev
, width
, height
)) {
8385 DRM_DEBUG("Cursor dimension not supported\n");
8389 stride
= roundup_pow_of_two(width
) * 4;
8390 if (obj
->base
.size
< stride
* height
) {
8391 DRM_DEBUG_KMS("buffer is too small\n");
8396 /* we only need to pin inside GTT if cursor is non-phy */
8397 mutex_lock(&dev
->struct_mutex
);
8398 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8401 if (obj
->tiling_mode
) {
8402 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8408 * Global gtt pte registers are special registers which actually
8409 * forward writes to a chunk of system memory. Which means that
8410 * there is no risk that the register values disappear as soon
8411 * as we call intel_runtime_pm_put(), so it is correct to wrap
8412 * only the pin/unpin/fence and not more.
8414 intel_runtime_pm_get(dev_priv
);
8416 /* Note that the w/a also requires 2 PTE of padding following
8417 * the bo. We currently fill all unused PTE with the shadow
8418 * page and so we should always have valid PTE following the
8419 * cursor preventing the VT-d warning.
8422 if (need_vtd_wa(dev
))
8423 alignment
= 64*1024;
8425 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8427 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8428 intel_runtime_pm_put(dev_priv
);
8432 ret
= i915_gem_object_put_fence(obj
);
8434 DRM_DEBUG_KMS("failed to release fence for cursor");
8435 intel_runtime_pm_put(dev_priv
);
8439 addr
= i915_gem_obj_ggtt_offset(obj
);
8441 intel_runtime_pm_put(dev_priv
);
8443 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8444 ret
= i915_gem_object_attach_phys(obj
, align
);
8446 DRM_DEBUG_KMS("failed to attach phys object\n");
8449 addr
= obj
->phys_handle
->busaddr
;
8453 if (intel_crtc
->cursor_bo
) {
8454 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8455 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8458 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8459 INTEL_FRONTBUFFER_CURSOR(pipe
));
8460 mutex_unlock(&dev
->struct_mutex
);
8462 old_width
= intel_crtc
->cursor_width
;
8464 intel_crtc
->cursor_addr
= addr
;
8465 intel_crtc
->cursor_bo
= obj
;
8466 intel_crtc
->cursor_width
= width
;
8467 intel_crtc
->cursor_height
= height
;
8469 if (intel_crtc
->active
) {
8470 if (old_width
!= width
)
8471 intel_update_watermarks(crtc
);
8472 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8475 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8479 i915_gem_object_unpin_from_display_plane(obj
);
8481 mutex_unlock(&dev
->struct_mutex
);
8483 drm_gem_object_unreference_unlocked(&obj
->base
);
8487 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8488 u16
*blue
, uint32_t start
, uint32_t size
)
8490 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8491 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8493 for (i
= start
; i
< end
; i
++) {
8494 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8495 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8496 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8499 intel_crtc_load_lut(crtc
);
8502 /* VESA 640x480x72Hz mode to set on the pipe */
8503 static struct drm_display_mode load_detect_mode
= {
8504 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8505 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8508 struct drm_framebuffer
*
8509 __intel_framebuffer_create(struct drm_device
*dev
,
8510 struct drm_mode_fb_cmd2
*mode_cmd
,
8511 struct drm_i915_gem_object
*obj
)
8513 struct intel_framebuffer
*intel_fb
;
8516 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8518 drm_gem_object_unreference_unlocked(&obj
->base
);
8519 return ERR_PTR(-ENOMEM
);
8522 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8526 return &intel_fb
->base
;
8528 drm_gem_object_unreference_unlocked(&obj
->base
);
8531 return ERR_PTR(ret
);
8534 static struct drm_framebuffer
*
8535 intel_framebuffer_create(struct drm_device
*dev
,
8536 struct drm_mode_fb_cmd2
*mode_cmd
,
8537 struct drm_i915_gem_object
*obj
)
8539 struct drm_framebuffer
*fb
;
8542 ret
= i915_mutex_lock_interruptible(dev
);
8544 return ERR_PTR(ret
);
8545 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8546 mutex_unlock(&dev
->struct_mutex
);
8552 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8554 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8555 return ALIGN(pitch
, 64);
8559 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8561 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8562 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8565 static struct drm_framebuffer
*
8566 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8567 struct drm_display_mode
*mode
,
8570 struct drm_i915_gem_object
*obj
;
8571 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8573 obj
= i915_gem_alloc_object(dev
,
8574 intel_framebuffer_size_for_mode(mode
, bpp
));
8576 return ERR_PTR(-ENOMEM
);
8578 mode_cmd
.width
= mode
->hdisplay
;
8579 mode_cmd
.height
= mode
->vdisplay
;
8580 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8582 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8584 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8587 static struct drm_framebuffer
*
8588 mode_fits_in_fbdev(struct drm_device
*dev
,
8589 struct drm_display_mode
*mode
)
8591 #ifdef CONFIG_DRM_I915_FBDEV
8592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8593 struct drm_i915_gem_object
*obj
;
8594 struct drm_framebuffer
*fb
;
8596 if (!dev_priv
->fbdev
)
8599 if (!dev_priv
->fbdev
->fb
)
8602 obj
= dev_priv
->fbdev
->fb
->obj
;
8605 fb
= &dev_priv
->fbdev
->fb
->base
;
8606 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8607 fb
->bits_per_pixel
))
8610 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8619 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8620 struct drm_display_mode
*mode
,
8621 struct intel_load_detect_pipe
*old
,
8622 struct drm_modeset_acquire_ctx
*ctx
)
8624 struct intel_crtc
*intel_crtc
;
8625 struct intel_encoder
*intel_encoder
=
8626 intel_attached_encoder(connector
);
8627 struct drm_crtc
*possible_crtc
;
8628 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8629 struct drm_crtc
*crtc
= NULL
;
8630 struct drm_device
*dev
= encoder
->dev
;
8631 struct drm_framebuffer
*fb
;
8632 struct drm_mode_config
*config
= &dev
->mode_config
;
8635 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8636 connector
->base
.id
, connector
->name
,
8637 encoder
->base
.id
, encoder
->name
);
8640 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8645 * Algorithm gets a little messy:
8647 * - if the connector already has an assigned crtc, use it (but make
8648 * sure it's on first)
8650 * - try to find the first unused crtc that can drive this connector,
8651 * and use that if we find one
8654 /* See if we already have a CRTC for this connector */
8655 if (encoder
->crtc
) {
8656 crtc
= encoder
->crtc
;
8658 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8662 old
->dpms_mode
= connector
->dpms
;
8663 old
->load_detect_temp
= false;
8665 /* Make sure the crtc and connector are running */
8666 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8667 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8672 /* Find an unused one (if possible) */
8673 for_each_crtc(dev
, possible_crtc
) {
8675 if (!(encoder
->possible_crtcs
& (1 << i
)))
8677 if (possible_crtc
->enabled
)
8679 /* This can occur when applying the pipe A quirk on resume. */
8680 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8683 crtc
= possible_crtc
;
8688 * If we didn't find an unused CRTC, don't use any.
8691 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8695 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8698 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8699 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8701 intel_crtc
= to_intel_crtc(crtc
);
8702 intel_crtc
->new_enabled
= true;
8703 intel_crtc
->new_config
= &intel_crtc
->config
;
8704 old
->dpms_mode
= connector
->dpms
;
8705 old
->load_detect_temp
= true;
8706 old
->release_fb
= NULL
;
8709 mode
= &load_detect_mode
;
8711 /* We need a framebuffer large enough to accommodate all accesses
8712 * that the plane may generate whilst we perform load detection.
8713 * We can not rely on the fbcon either being present (we get called
8714 * during its initialisation to detect all boot displays, or it may
8715 * not even exist) or that it is large enough to satisfy the
8718 fb
= mode_fits_in_fbdev(dev
, mode
);
8720 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8721 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8722 old
->release_fb
= fb
;
8724 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8726 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8730 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8731 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8732 if (old
->release_fb
)
8733 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8737 /* let the connector get through one full cycle before testing */
8738 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8742 intel_crtc
->new_enabled
= crtc
->enabled
;
8743 if (intel_crtc
->new_enabled
)
8744 intel_crtc
->new_config
= &intel_crtc
->config
;
8746 intel_crtc
->new_config
= NULL
;
8748 if (ret
== -EDEADLK
) {
8749 drm_modeset_backoff(ctx
);
8756 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8757 struct intel_load_detect_pipe
*old
)
8759 struct intel_encoder
*intel_encoder
=
8760 intel_attached_encoder(connector
);
8761 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8762 struct drm_crtc
*crtc
= encoder
->crtc
;
8763 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8765 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8766 connector
->base
.id
, connector
->name
,
8767 encoder
->base
.id
, encoder
->name
);
8769 if (old
->load_detect_temp
) {
8770 to_intel_connector(connector
)->new_encoder
= NULL
;
8771 intel_encoder
->new_crtc
= NULL
;
8772 intel_crtc
->new_enabled
= false;
8773 intel_crtc
->new_config
= NULL
;
8774 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8776 if (old
->release_fb
) {
8777 drm_framebuffer_unregister_private(old
->release_fb
);
8778 drm_framebuffer_unreference(old
->release_fb
);
8784 /* Switch crtc and encoder back off if necessary */
8785 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8786 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8789 static int i9xx_pll_refclk(struct drm_device
*dev
,
8790 const struct intel_crtc_config
*pipe_config
)
8792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8793 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8795 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8796 return dev_priv
->vbt
.lvds_ssc_freq
;
8797 else if (HAS_PCH_SPLIT(dev
))
8799 else if (!IS_GEN2(dev
))
8805 /* Returns the clock of the currently programmed mode of the given pipe. */
8806 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8807 struct intel_crtc_config
*pipe_config
)
8809 struct drm_device
*dev
= crtc
->base
.dev
;
8810 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8811 int pipe
= pipe_config
->cpu_transcoder
;
8812 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8814 intel_clock_t clock
;
8815 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8817 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8818 fp
= pipe_config
->dpll_hw_state
.fp0
;
8820 fp
= pipe_config
->dpll_hw_state
.fp1
;
8822 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8823 if (IS_PINEVIEW(dev
)) {
8824 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8825 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8827 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8828 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8831 if (!IS_GEN2(dev
)) {
8832 if (IS_PINEVIEW(dev
))
8833 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8834 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8836 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8837 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8839 switch (dpll
& DPLL_MODE_MASK
) {
8840 case DPLLB_MODE_DAC_SERIAL
:
8841 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8844 case DPLLB_MODE_LVDS
:
8845 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8849 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8850 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8854 if (IS_PINEVIEW(dev
))
8855 pineview_clock(refclk
, &clock
);
8857 i9xx_clock(refclk
, &clock
);
8859 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8860 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8863 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8864 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8866 if (lvds
& LVDS_CLKB_POWER_UP
)
8871 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8874 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8875 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8877 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8883 i9xx_clock(refclk
, &clock
);
8887 * This value includes pixel_multiplier. We will use
8888 * port_clock to compute adjusted_mode.crtc_clock in the
8889 * encoder's get_config() function.
8891 pipe_config
->port_clock
= clock
.dot
;
8894 int intel_dotclock_calculate(int link_freq
,
8895 const struct intel_link_m_n
*m_n
)
8898 * The calculation for the data clock is:
8899 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8900 * But we want to avoid losing precison if possible, so:
8901 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8903 * and the link clock is simpler:
8904 * link_clock = (m * link_clock) / n
8910 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8913 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8914 struct intel_crtc_config
*pipe_config
)
8916 struct drm_device
*dev
= crtc
->base
.dev
;
8918 /* read out port_clock from the DPLL */
8919 i9xx_crtc_clock_get(crtc
, pipe_config
);
8922 * This value does not include pixel_multiplier.
8923 * We will check that port_clock and adjusted_mode.crtc_clock
8924 * agree once we know their relationship in the encoder's
8925 * get_config() function.
8927 pipe_config
->adjusted_mode
.crtc_clock
=
8928 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8929 &pipe_config
->fdi_m_n
);
8932 /** Returns the currently programmed mode of the given pipe. */
8933 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8934 struct drm_crtc
*crtc
)
8936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8937 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8938 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8939 struct drm_display_mode
*mode
;
8940 struct intel_crtc_config pipe_config
;
8941 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8942 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8943 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8944 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8945 enum pipe pipe
= intel_crtc
->pipe
;
8947 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8952 * Construct a pipe_config sufficient for getting the clock info
8953 * back out of crtc_clock_get.
8955 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8956 * to use a real value here instead.
8958 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8959 pipe_config
.pixel_multiplier
= 1;
8960 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8961 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8962 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8963 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8965 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8966 mode
->hdisplay
= (htot
& 0xffff) + 1;
8967 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8968 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8969 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8970 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8971 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8972 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8973 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8975 drm_mode_set_name(mode
);
8980 static void intel_increase_pllclock(struct drm_device
*dev
,
8983 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8984 int dpll_reg
= DPLL(pipe
);
8987 if (!HAS_GMCH_DISPLAY(dev
))
8990 if (!dev_priv
->lvds_downclock_avail
)
8993 dpll
= I915_READ(dpll_reg
);
8994 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8995 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8997 assert_panel_unlocked(dev_priv
, pipe
);
8999 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
9000 I915_WRITE(dpll_reg
, dpll
);
9001 intel_wait_for_vblank(dev
, pipe
);
9003 dpll
= I915_READ(dpll_reg
);
9004 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
9005 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
9009 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
9011 struct drm_device
*dev
= crtc
->dev
;
9012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9013 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9015 if (!HAS_GMCH_DISPLAY(dev
))
9018 if (!dev_priv
->lvds_downclock_avail
)
9022 * Since this is called by a timer, we should never get here in
9025 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9026 int pipe
= intel_crtc
->pipe
;
9027 int dpll_reg
= DPLL(pipe
);
9030 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9032 assert_panel_unlocked(dev_priv
, pipe
);
9034 dpll
= I915_READ(dpll_reg
);
9035 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9036 I915_WRITE(dpll_reg
, dpll
);
9037 intel_wait_for_vblank(dev
, pipe
);
9038 dpll
= I915_READ(dpll_reg
);
9039 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9040 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9045 void intel_mark_busy(struct drm_device
*dev
)
9047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9049 if (dev_priv
->mm
.busy
)
9052 intel_runtime_pm_get(dev_priv
);
9053 i915_update_gfx_val(dev_priv
);
9054 dev_priv
->mm
.busy
= true;
9057 void intel_mark_idle(struct drm_device
*dev
)
9059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9060 struct drm_crtc
*crtc
;
9062 if (!dev_priv
->mm
.busy
)
9065 dev_priv
->mm
.busy
= false;
9067 if (!i915
.powersave
)
9070 for_each_crtc(dev
, crtc
) {
9071 if (!crtc
->primary
->fb
)
9074 intel_decrease_pllclock(crtc
);
9077 if (INTEL_INFO(dev
)->gen
>= 6)
9078 gen6_rps_idle(dev
->dev_private
);
9081 intel_runtime_pm_put(dev_priv
);
9086 * intel_mark_fb_busy - mark given planes as busy
9088 * @frontbuffer_bits: bits for the affected planes
9089 * @ring: optional ring for asynchronous commands
9091 * This function gets called every time the screen contents change. It can be
9092 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9094 static void intel_mark_fb_busy(struct drm_device
*dev
,
9095 unsigned frontbuffer_bits
,
9096 struct intel_engine_cs
*ring
)
9098 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9101 if (!i915
.powersave
)
9104 for_each_pipe(dev_priv
, pipe
) {
9105 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
9108 intel_increase_pllclock(dev
, pipe
);
9109 if (ring
&& intel_fbc_enabled(dev
))
9110 ring
->fbc_dirty
= true;
9115 * intel_fb_obj_invalidate - invalidate frontbuffer object
9116 * @obj: GEM object to invalidate
9117 * @ring: set for asynchronous rendering
9119 * This function gets called every time rendering on the given object starts and
9120 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9121 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9122 * until the rendering completes or a flip on this frontbuffer plane is
9125 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
9126 struct intel_engine_cs
*ring
)
9128 struct drm_device
*dev
= obj
->base
.dev
;
9129 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9131 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9133 if (!obj
->frontbuffer_bits
)
9137 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9138 dev_priv
->fb_tracking
.busy_bits
9139 |= obj
->frontbuffer_bits
;
9140 dev_priv
->fb_tracking
.flip_bits
9141 &= ~obj
->frontbuffer_bits
;
9142 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9145 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
9147 intel_edp_psr_invalidate(dev
, obj
->frontbuffer_bits
);
9151 * intel_frontbuffer_flush - flush frontbuffer
9153 * @frontbuffer_bits: frontbuffer plane tracking bits
9155 * This function gets called every time rendering on the given planes has
9156 * completed and frontbuffer caching can be started again. Flushes will get
9157 * delayed if they're blocked by some oustanding asynchronous rendering.
9159 * Can be called without any locks held.
9161 void intel_frontbuffer_flush(struct drm_device
*dev
,
9162 unsigned frontbuffer_bits
)
9164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9166 /* Delay flushing when rings are still busy.*/
9167 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9168 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
9169 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9171 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
9173 intel_edp_psr_flush(dev
, frontbuffer_bits
);
9176 * FIXME: Unconditional fbc flushing here is a rather gross hack and
9177 * needs to be reworked into a proper frontbuffer tracking scheme like
9180 if (IS_BROADWELL(dev
))
9181 gen8_fbc_sw_flush(dev
, FBC_REND_CACHE_CLEAN
);
9185 * intel_fb_obj_flush - flush frontbuffer object
9186 * @obj: GEM object to flush
9187 * @retire: set when retiring asynchronous rendering
9189 * This function gets called every time rendering on the given object has
9190 * completed and frontbuffer caching can be started again. If @retire is true
9191 * then any delayed flushes will be unblocked.
9193 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
9196 struct drm_device
*dev
= obj
->base
.dev
;
9197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9198 unsigned frontbuffer_bits
;
9200 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9202 if (!obj
->frontbuffer_bits
)
9205 frontbuffer_bits
= obj
->frontbuffer_bits
;
9208 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9209 /* Filter out new bits since rendering started. */
9210 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9212 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9213 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9216 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9220 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9222 * @frontbuffer_bits: frontbuffer plane tracking bits
9224 * This function gets called after scheduling a flip on @obj. The actual
9225 * frontbuffer flushing will be delayed until completion is signalled with
9226 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9227 * flush will be cancelled.
9229 * Can be called without any locks held.
9231 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9232 unsigned frontbuffer_bits
)
9234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9236 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9237 dev_priv
->fb_tracking
.flip_bits
9238 |= frontbuffer_bits
;
9239 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9243 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9245 * @frontbuffer_bits: frontbuffer plane tracking bits
9247 * This function gets called after the flip has been latched and will complete
9248 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9250 * Can be called without any locks held.
9252 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9253 unsigned frontbuffer_bits
)
9255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9257 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9258 /* Mask any cancelled flips. */
9259 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9260 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9261 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9263 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9266 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9268 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9269 struct drm_device
*dev
= crtc
->dev
;
9270 struct intel_unpin_work
*work
;
9271 unsigned long flags
;
9273 spin_lock_irqsave(&dev
->event_lock
, flags
);
9274 work
= intel_crtc
->unpin_work
;
9275 intel_crtc
->unpin_work
= NULL
;
9276 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9279 cancel_work_sync(&work
->work
);
9283 drm_crtc_cleanup(crtc
);
9288 static void intel_unpin_work_fn(struct work_struct
*__work
)
9290 struct intel_unpin_work
*work
=
9291 container_of(__work
, struct intel_unpin_work
, work
);
9292 struct drm_device
*dev
= work
->crtc
->dev
;
9293 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9295 mutex_lock(&dev
->struct_mutex
);
9296 intel_unpin_fb_obj(work
->old_fb_obj
);
9297 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9298 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9300 intel_update_fbc(dev
);
9301 mutex_unlock(&dev
->struct_mutex
);
9303 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9305 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9306 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9311 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9312 struct drm_crtc
*crtc
)
9314 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9315 struct intel_unpin_work
*work
;
9316 unsigned long flags
;
9318 /* Ignore early vblank irqs */
9319 if (intel_crtc
== NULL
)
9322 spin_lock_irqsave(&dev
->event_lock
, flags
);
9323 work
= intel_crtc
->unpin_work
;
9325 /* Ensure we don't miss a work->pending update ... */
9328 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9329 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9333 page_flip_completed(intel_crtc
);
9335 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9338 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9341 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9343 do_intel_finish_page_flip(dev
, crtc
);
9346 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9349 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9351 do_intel_finish_page_flip(dev
, crtc
);
9354 /* Is 'a' after or equal to 'b'? */
9355 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9357 return !((a
- b
) & 0x80000000);
9360 static bool page_flip_finished(struct intel_crtc
*crtc
)
9362 struct drm_device
*dev
= crtc
->base
.dev
;
9363 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9366 * The relevant registers doen't exist on pre-ctg.
9367 * As the flip done interrupt doesn't trigger for mmio
9368 * flips on gmch platforms, a flip count check isn't
9369 * really needed there. But since ctg has the registers,
9370 * include it in the check anyway.
9372 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9376 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9377 * used the same base address. In that case the mmio flip might
9378 * have completed, but the CS hasn't even executed the flip yet.
9380 * A flip count check isn't enough as the CS might have updated
9381 * the base address just after start of vblank, but before we
9382 * managed to process the interrupt. This means we'd complete the
9385 * Combining both checks should get us a good enough result. It may
9386 * still happen that the CS flip has been executed, but has not
9387 * yet actually completed. But in case the base address is the same
9388 * anyway, we don't really care.
9390 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9391 crtc
->unpin_work
->gtt_offset
&&
9392 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9393 crtc
->unpin_work
->flip_count
);
9396 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9399 struct intel_crtc
*intel_crtc
=
9400 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9401 unsigned long flags
;
9403 /* NB: An MMIO update of the plane base pointer will also
9404 * generate a page-flip completion irq, i.e. every modeset
9405 * is also accompanied by a spurious intel_prepare_page_flip().
9407 spin_lock_irqsave(&dev
->event_lock
, flags
);
9408 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9409 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9410 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9413 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9415 /* Ensure that the work item is consistent when activating it ... */
9417 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9418 /* and that it is marked active as soon as the irq could fire. */
9422 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9423 struct drm_crtc
*crtc
,
9424 struct drm_framebuffer
*fb
,
9425 struct drm_i915_gem_object
*obj
,
9426 struct intel_engine_cs
*ring
,
9429 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9433 ret
= intel_ring_begin(ring
, 6);
9437 /* Can't queue multiple flips, so wait for the previous
9438 * one to finish before executing the next.
9440 if (intel_crtc
->plane
)
9441 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9443 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9444 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9445 intel_ring_emit(ring
, MI_NOOP
);
9446 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9447 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9448 intel_ring_emit(ring
, fb
->pitches
[0]);
9449 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9450 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9452 intel_mark_page_flip_active(intel_crtc
);
9453 __intel_ring_advance(ring
);
9457 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9458 struct drm_crtc
*crtc
,
9459 struct drm_framebuffer
*fb
,
9460 struct drm_i915_gem_object
*obj
,
9461 struct intel_engine_cs
*ring
,
9464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9468 ret
= intel_ring_begin(ring
, 6);
9472 if (intel_crtc
->plane
)
9473 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9475 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9476 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9477 intel_ring_emit(ring
, MI_NOOP
);
9478 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9479 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9480 intel_ring_emit(ring
, fb
->pitches
[0]);
9481 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9482 intel_ring_emit(ring
, MI_NOOP
);
9484 intel_mark_page_flip_active(intel_crtc
);
9485 __intel_ring_advance(ring
);
9489 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9490 struct drm_crtc
*crtc
,
9491 struct drm_framebuffer
*fb
,
9492 struct drm_i915_gem_object
*obj
,
9493 struct intel_engine_cs
*ring
,
9496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9497 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9498 uint32_t pf
, pipesrc
;
9501 ret
= intel_ring_begin(ring
, 4);
9505 /* i965+ uses the linear or tiled offsets from the
9506 * Display Registers (which do not change across a page-flip)
9507 * so we need only reprogram the base address.
9509 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9510 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9511 intel_ring_emit(ring
, fb
->pitches
[0]);
9512 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9515 /* XXX Enabling the panel-fitter across page-flip is so far
9516 * untested on non-native modes, so ignore it for now.
9517 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9520 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9521 intel_ring_emit(ring
, pf
| pipesrc
);
9523 intel_mark_page_flip_active(intel_crtc
);
9524 __intel_ring_advance(ring
);
9528 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9529 struct drm_crtc
*crtc
,
9530 struct drm_framebuffer
*fb
,
9531 struct drm_i915_gem_object
*obj
,
9532 struct intel_engine_cs
*ring
,
9535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9536 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9537 uint32_t pf
, pipesrc
;
9540 ret
= intel_ring_begin(ring
, 4);
9544 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9545 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9546 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9547 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9549 /* Contrary to the suggestions in the documentation,
9550 * "Enable Panel Fitter" does not seem to be required when page
9551 * flipping with a non-native mode, and worse causes a normal
9553 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9556 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9557 intel_ring_emit(ring
, pf
| pipesrc
);
9559 intel_mark_page_flip_active(intel_crtc
);
9560 __intel_ring_advance(ring
);
9564 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9565 struct drm_crtc
*crtc
,
9566 struct drm_framebuffer
*fb
,
9567 struct drm_i915_gem_object
*obj
,
9568 struct intel_engine_cs
*ring
,
9571 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9572 uint32_t plane_bit
= 0;
9575 switch (intel_crtc
->plane
) {
9577 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9580 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9583 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9586 WARN_ONCE(1, "unknown plane in flip command\n");
9591 if (ring
->id
== RCS
) {
9594 * On Gen 8, SRM is now taking an extra dword to accommodate
9595 * 48bits addresses, and we need a NOOP for the batch size to
9603 * BSpec MI_DISPLAY_FLIP for IVB:
9604 * "The full packet must be contained within the same cache line."
9606 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9607 * cacheline, if we ever start emitting more commands before
9608 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9609 * then do the cacheline alignment, and finally emit the
9612 ret
= intel_ring_cacheline_align(ring
);
9616 ret
= intel_ring_begin(ring
, len
);
9620 /* Unmask the flip-done completion message. Note that the bspec says that
9621 * we should do this for both the BCS and RCS, and that we must not unmask
9622 * more than one flip event at any time (or ensure that one flip message
9623 * can be sent by waiting for flip-done prior to queueing new flips).
9624 * Experimentation says that BCS works despite DERRMR masking all
9625 * flip-done completion events and that unmasking all planes at once
9626 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9627 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9629 if (ring
->id
== RCS
) {
9630 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9631 intel_ring_emit(ring
, DERRMR
);
9632 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9633 DERRMR_PIPEB_PRI_FLIP_DONE
|
9634 DERRMR_PIPEC_PRI_FLIP_DONE
));
9636 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9637 MI_SRM_LRM_GLOBAL_GTT
);
9639 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9640 MI_SRM_LRM_GLOBAL_GTT
);
9641 intel_ring_emit(ring
, DERRMR
);
9642 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9644 intel_ring_emit(ring
, 0);
9645 intel_ring_emit(ring
, MI_NOOP
);
9649 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9650 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9651 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9652 intel_ring_emit(ring
, (MI_NOOP
));
9654 intel_mark_page_flip_active(intel_crtc
);
9655 __intel_ring_advance(ring
);
9659 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9660 struct drm_i915_gem_object
*obj
)
9663 * This is not being used for older platforms, because
9664 * non-availability of flip done interrupt forces us to use
9665 * CS flips. Older platforms derive flip done using some clever
9666 * tricks involving the flip_pending status bits and vblank irqs.
9667 * So using MMIO flips there would disrupt this mechanism.
9673 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9676 if (i915
.use_mmio_flip
< 0)
9678 else if (i915
.use_mmio_flip
> 0)
9680 else if (i915
.enable_execlists
)
9683 return ring
!= obj
->ring
;
9686 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9688 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9689 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9690 struct intel_framebuffer
*intel_fb
=
9691 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9692 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9696 intel_mark_page_flip_active(intel_crtc
);
9698 reg
= DSPCNTR(intel_crtc
->plane
);
9699 dspcntr
= I915_READ(reg
);
9701 if (INTEL_INFO(dev
)->gen
>= 4) {
9702 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9703 dspcntr
|= DISPPLANE_TILED
;
9705 dspcntr
&= ~DISPPLANE_TILED
;
9707 I915_WRITE(reg
, dspcntr
);
9709 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9710 intel_crtc
->unpin_work
->gtt_offset
);
9711 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9714 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9716 struct intel_engine_cs
*ring
;
9719 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9721 if (!obj
->last_write_seqno
)
9726 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9727 obj
->last_write_seqno
))
9730 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9734 if (WARN_ON(!ring
->irq_get(ring
)))
9740 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9742 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9743 struct intel_crtc
*intel_crtc
;
9744 unsigned long irq_flags
;
9747 seqno
= ring
->get_seqno(ring
, false);
9749 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9750 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9751 struct intel_mmio_flip
*mmio_flip
;
9753 mmio_flip
= &intel_crtc
->mmio_flip
;
9754 if (mmio_flip
->seqno
== 0)
9757 if (ring
->id
!= mmio_flip
->ring_id
)
9760 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9761 intel_do_mmio_flip(intel_crtc
);
9762 mmio_flip
->seqno
= 0;
9763 ring
->irq_put(ring
);
9766 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9769 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9770 struct drm_crtc
*crtc
,
9771 struct drm_framebuffer
*fb
,
9772 struct drm_i915_gem_object
*obj
,
9773 struct intel_engine_cs
*ring
,
9776 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9777 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9778 unsigned long irq_flags
;
9781 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9784 ret
= intel_postpone_flip(obj
);
9788 intel_do_mmio_flip(intel_crtc
);
9792 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9793 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9794 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9795 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9798 * Double check to catch cases where irq fired before
9799 * mmio flip data was ready
9801 intel_notify_mmio_flip(obj
->ring
);
9805 static int intel_default_queue_flip(struct drm_device
*dev
,
9806 struct drm_crtc
*crtc
,
9807 struct drm_framebuffer
*fb
,
9808 struct drm_i915_gem_object
*obj
,
9809 struct intel_engine_cs
*ring
,
9815 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
9816 struct drm_crtc
*crtc
)
9818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9819 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9820 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
9823 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
9826 if (!work
->enable_stall_check
)
9829 if (work
->flip_ready_vblank
== 0) {
9830 if (work
->flip_queued_ring
&&
9831 !i915_seqno_passed(work
->flip_queued_ring
->get_seqno(work
->flip_queued_ring
, true),
9832 work
->flip_queued_seqno
))
9835 work
->flip_ready_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
9838 if (drm_vblank_count(dev
, intel_crtc
->pipe
) - work
->flip_ready_vblank
< 3)
9841 /* Potential stall - if we see that the flip has happened,
9842 * assume a missed interrupt. */
9843 if (INTEL_INFO(dev
)->gen
>= 4)
9844 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
9846 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
9848 /* There is a potential issue here with a false positive after a flip
9849 * to the same address. We could address this by checking for a
9850 * non-incrementing frame counter.
9852 return addr
== work
->gtt_offset
;
9855 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
9857 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9858 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9860 unsigned long flags
;
9865 spin_lock_irqsave(&dev
->event_lock
, flags
);
9866 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
9867 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9868 intel_crtc
->unpin_work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
9869 page_flip_completed(intel_crtc
);
9871 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9874 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9875 struct drm_framebuffer
*fb
,
9876 struct drm_pending_vblank_event
*event
,
9877 uint32_t page_flip_flags
)
9879 struct drm_device
*dev
= crtc
->dev
;
9880 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9881 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9882 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9883 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9884 enum pipe pipe
= intel_crtc
->pipe
;
9885 struct intel_unpin_work
*work
;
9886 struct intel_engine_cs
*ring
;
9887 unsigned long flags
;
9890 //trigger software GT busyness calculation
9891 gen8_flip_interrupt(dev
);
9894 * drm_mode_page_flip_ioctl() should already catch this, but double
9895 * check to be safe. In the future we may enable pageflipping from
9896 * a disabled primary plane.
9898 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9901 /* Can't change pixel format via MI display flips. */
9902 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9906 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9907 * Note that pitch changes could also affect these register.
9909 if (INTEL_INFO(dev
)->gen
> 3 &&
9910 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9911 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9914 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9917 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9921 work
->event
= event
;
9923 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9924 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9926 ret
= drm_crtc_vblank_get(crtc
);
9930 /* We borrow the event spin lock for protecting unpin_work */
9931 spin_lock_irqsave(&dev
->event_lock
, flags
);
9932 if (intel_crtc
->unpin_work
) {
9933 /* Before declaring the flip queue wedged, check if
9934 * the hardware completed the operation behind our backs.
9936 if (__intel_pageflip_stall_check(dev
, crtc
)) {
9937 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9938 page_flip_completed(intel_crtc
);
9940 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9941 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9943 drm_crtc_vblank_put(crtc
);
9948 intel_crtc
->unpin_work
= work
;
9949 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9951 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9952 flush_workqueue(dev_priv
->wq
);
9954 ret
= i915_mutex_lock_interruptible(dev
);
9958 /* Reference the objects for the scheduled work. */
9959 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9960 drm_gem_object_reference(&obj
->base
);
9962 crtc
->primary
->fb
= fb
;
9964 work
->pending_flip_obj
= obj
;
9966 atomic_inc(&intel_crtc
->unpin_work_count
);
9967 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9969 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9970 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9972 if (IS_VALLEYVIEW(dev
)) {
9973 ring
= &dev_priv
->ring
[BCS
];
9974 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9975 /* vlv: DISPLAY_FLIP fails to change tiling */
9977 } else if (IS_IVYBRIDGE(dev
)) {
9978 ring
= &dev_priv
->ring
[BCS
];
9979 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9981 if (ring
== NULL
|| ring
->id
!= RCS
)
9982 ring
= &dev_priv
->ring
[BCS
];
9984 ring
= &dev_priv
->ring
[RCS
];
9987 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
9989 goto cleanup_pending
;
9992 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9994 if (use_mmio_flip(ring
, obj
)) {
9995 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
10000 work
->flip_queued_seqno
= obj
->last_write_seqno
;
10001 work
->flip_queued_ring
= obj
->ring
;
10003 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
10006 goto cleanup_unpin
;
10008 work
->flip_queued_seqno
= intel_ring_get_seqno(ring
);
10009 work
->flip_queued_ring
= ring
;
10012 work
->flip_queued_vblank
= drm_vblank_count(dev
, intel_crtc
->pipe
);
10013 work
->enable_stall_check
= true;
10015 i915_gem_track_fb(work
->old_fb_obj
, obj
,
10016 INTEL_FRONTBUFFER_PRIMARY(pipe
));
10018 intel_disable_fbc(dev
);
10019 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10020 mutex_unlock(&dev
->struct_mutex
);
10022 trace_i915_flip_request(intel_crtc
->plane
, obj
);
10027 intel_unpin_fb_obj(obj
);
10029 atomic_dec(&intel_crtc
->unpin_work_count
);
10030 crtc
->primary
->fb
= old_fb
;
10031 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
10032 drm_gem_object_unreference(&obj
->base
);
10033 mutex_unlock(&dev
->struct_mutex
);
10036 spin_lock_irqsave(&dev
->event_lock
, flags
);
10037 intel_crtc
->unpin_work
= NULL
;
10038 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10040 drm_crtc_vblank_put(crtc
);
10046 intel_crtc_wait_for_pending_flips(crtc
);
10047 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
10048 if (ret
== 0 && event
)
10049 drm_send_vblank_event(dev
, pipe
, event
);
10054 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
10055 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
10056 .load_lut
= intel_crtc_load_lut
,
10060 * intel_modeset_update_staged_output_state
10062 * Updates the staged output configuration state, e.g. after we've read out the
10063 * current hw state.
10065 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
10067 struct intel_crtc
*crtc
;
10068 struct intel_encoder
*encoder
;
10069 struct intel_connector
*connector
;
10071 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10073 connector
->new_encoder
=
10074 to_intel_encoder(connector
->base
.encoder
);
10077 for_each_intel_encoder(dev
, encoder
) {
10078 encoder
->new_crtc
=
10079 to_intel_crtc(encoder
->base
.crtc
);
10082 for_each_intel_crtc(dev
, crtc
) {
10083 crtc
->new_enabled
= crtc
->base
.enabled
;
10085 if (crtc
->new_enabled
)
10086 crtc
->new_config
= &crtc
->config
;
10088 crtc
->new_config
= NULL
;
10093 * intel_modeset_commit_output_state
10095 * This function copies the stage display pipe configuration to the real one.
10097 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
10099 struct intel_crtc
*crtc
;
10100 struct intel_encoder
*encoder
;
10101 struct intel_connector
*connector
;
10103 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10105 connector
->base
.encoder
= &connector
->new_encoder
->base
;
10108 for_each_intel_encoder(dev
, encoder
) {
10109 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
10112 for_each_intel_crtc(dev
, crtc
) {
10113 crtc
->base
.enabled
= crtc
->new_enabled
;
10118 connected_sink_compute_bpp(struct intel_connector
*connector
,
10119 struct intel_crtc_config
*pipe_config
)
10121 int bpp
= pipe_config
->pipe_bpp
;
10123 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10124 connector
->base
.base
.id
,
10125 connector
->base
.name
);
10127 /* Don't use an invalid EDID bpc value */
10128 if (connector
->base
.display_info
.bpc
&&
10129 connector
->base
.display_info
.bpc
* 3 < bpp
) {
10130 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10131 bpp
, connector
->base
.display_info
.bpc
*3);
10132 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
10135 /* Clamp bpp to 8 on screens without EDID 1.4 */
10136 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
10137 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10139 pipe_config
->pipe_bpp
= 24;
10144 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10145 struct drm_framebuffer
*fb
,
10146 struct intel_crtc_config
*pipe_config
)
10148 struct drm_device
*dev
= crtc
->base
.dev
;
10149 struct intel_connector
*connector
;
10152 switch (fb
->pixel_format
) {
10153 case DRM_FORMAT_C8
:
10154 bpp
= 8*3; /* since we go through a colormap */
10156 case DRM_FORMAT_XRGB1555
:
10157 case DRM_FORMAT_ARGB1555
:
10158 /* checked in intel_framebuffer_init already */
10159 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10161 case DRM_FORMAT_RGB565
:
10162 bpp
= 6*3; /* min is 18bpp */
10164 case DRM_FORMAT_XBGR8888
:
10165 case DRM_FORMAT_ABGR8888
:
10166 /* checked in intel_framebuffer_init already */
10167 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10169 case DRM_FORMAT_XRGB8888
:
10170 case DRM_FORMAT_ARGB8888
:
10173 case DRM_FORMAT_XRGB2101010
:
10174 case DRM_FORMAT_ARGB2101010
:
10175 case DRM_FORMAT_XBGR2101010
:
10176 case DRM_FORMAT_ABGR2101010
:
10177 /* checked in intel_framebuffer_init already */
10178 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10182 /* TODO: gen4+ supports 16 bpc floating point, too. */
10184 DRM_DEBUG_KMS("unsupported depth\n");
10188 pipe_config
->pipe_bpp
= bpp
;
10190 /* Clamp display bpp to EDID value */
10191 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10193 if (!connector
->new_encoder
||
10194 connector
->new_encoder
->new_crtc
!= crtc
)
10197 connected_sink_compute_bpp(connector
, pipe_config
);
10203 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10205 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10206 "type: 0x%x flags: 0x%x\n",
10208 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10209 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10210 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10211 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10214 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10215 struct intel_crtc_config
*pipe_config
,
10216 const char *context
)
10218 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10219 context
, pipe_name(crtc
->pipe
));
10221 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10222 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10223 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10224 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10225 pipe_config
->has_pch_encoder
,
10226 pipe_config
->fdi_lanes
,
10227 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10228 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10229 pipe_config
->fdi_m_n
.tu
);
10230 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10231 pipe_config
->has_dp_encoder
,
10232 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10233 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10234 pipe_config
->dp_m_n
.tu
);
10236 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10237 pipe_config
->has_dp_encoder
,
10238 pipe_config
->dp_m2_n2
.gmch_m
,
10239 pipe_config
->dp_m2_n2
.gmch_n
,
10240 pipe_config
->dp_m2_n2
.link_m
,
10241 pipe_config
->dp_m2_n2
.link_n
,
10242 pipe_config
->dp_m2_n2
.tu
);
10244 DRM_DEBUG_KMS("requested mode:\n");
10245 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10246 DRM_DEBUG_KMS("adjusted mode:\n");
10247 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10248 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10249 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10250 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10251 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10252 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10253 pipe_config
->gmch_pfit
.control
,
10254 pipe_config
->gmch_pfit
.pgm_ratios
,
10255 pipe_config
->gmch_pfit
.lvds_border_bits
);
10256 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10257 pipe_config
->pch_pfit
.pos
,
10258 pipe_config
->pch_pfit
.size
,
10259 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10260 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10261 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10264 static bool encoders_cloneable(const struct intel_encoder
*a
,
10265 const struct intel_encoder
*b
)
10267 /* masks could be asymmetric, so check both ways */
10268 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10269 b
->cloneable
& (1 << a
->type
));
10272 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10273 struct intel_encoder
*encoder
)
10275 struct drm_device
*dev
= crtc
->base
.dev
;
10276 struct intel_encoder
*source_encoder
;
10278 for_each_intel_encoder(dev
, source_encoder
) {
10279 if (source_encoder
->new_crtc
!= crtc
)
10282 if (!encoders_cloneable(encoder
, source_encoder
))
10289 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10291 struct drm_device
*dev
= crtc
->base
.dev
;
10292 struct intel_encoder
*encoder
;
10294 for_each_intel_encoder(dev
, encoder
) {
10295 if (encoder
->new_crtc
!= crtc
)
10298 if (!check_single_encoder_cloning(crtc
, encoder
))
10305 static struct intel_crtc_config
*
10306 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10307 struct drm_framebuffer
*fb
,
10308 struct drm_display_mode
*mode
)
10310 struct drm_device
*dev
= crtc
->dev
;
10311 struct intel_encoder
*encoder
;
10312 struct intel_crtc_config
*pipe_config
;
10313 int plane_bpp
, ret
= -EINVAL
;
10316 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10317 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10318 return ERR_PTR(-EINVAL
);
10321 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10323 return ERR_PTR(-ENOMEM
);
10325 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10326 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10328 pipe_config
->cpu_transcoder
=
10329 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10330 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10333 * Sanitize sync polarity flags based on requested ones. If neither
10334 * positive or negative polarity is requested, treat this as meaning
10335 * negative polarity.
10337 if (!(pipe_config
->adjusted_mode
.flags
&
10338 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10339 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10341 if (!(pipe_config
->adjusted_mode
.flags
&
10342 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10343 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10345 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10346 * plane pixel format and any sink constraints into account. Returns the
10347 * source plane bpp so that dithering can be selected on mismatches
10348 * after encoders and crtc also have had their say. */
10349 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10355 * Determine the real pipe dimensions. Note that stereo modes can
10356 * increase the actual pipe size due to the frame doubling and
10357 * insertion of additional space for blanks between the frame. This
10358 * is stored in the crtc timings. We use the requested mode to do this
10359 * computation to clearly distinguish it from the adjusted mode, which
10360 * can be changed by the connectors in the below retry loop.
10362 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10363 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10364 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10367 /* Ensure the port clock defaults are reset when retrying. */
10368 pipe_config
->port_clock
= 0;
10369 pipe_config
->pixel_multiplier
= 1;
10371 /* Fill in default crtc timings, allow encoders to overwrite them. */
10372 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10374 /* Pass our mode to the connectors and the CRTC to give them a chance to
10375 * adjust it according to limitations or connector properties, and also
10376 * a chance to reject the mode entirely.
10378 for_each_intel_encoder(dev
, encoder
) {
10380 if (&encoder
->new_crtc
->base
!= crtc
)
10383 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10384 DRM_DEBUG_KMS("Encoder config failure\n");
10389 /* Set default port clock if not overwritten by the encoder. Needs to be
10390 * done afterwards in case the encoder adjusts the mode. */
10391 if (!pipe_config
->port_clock
)
10392 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10393 * pipe_config
->pixel_multiplier
;
10395 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10397 DRM_DEBUG_KMS("CRTC fixup failed\n");
10401 if (ret
== RETRY
) {
10402 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10407 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10409 goto encoder_retry
;
10412 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10413 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10414 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10416 return pipe_config
;
10418 kfree(pipe_config
);
10419 return ERR_PTR(ret
);
10422 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10423 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10425 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10426 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10428 struct intel_crtc
*intel_crtc
;
10429 struct drm_device
*dev
= crtc
->dev
;
10430 struct intel_encoder
*encoder
;
10431 struct intel_connector
*connector
;
10432 struct drm_crtc
*tmp_crtc
;
10434 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10436 /* Check which crtcs have changed outputs connected to them, these need
10437 * to be part of the prepare_pipes mask. We don't (yet) support global
10438 * modeset across multiple crtcs, so modeset_pipes will only have one
10439 * bit set at most. */
10440 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10442 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10445 if (connector
->base
.encoder
) {
10446 tmp_crtc
= connector
->base
.encoder
->crtc
;
10448 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10451 if (connector
->new_encoder
)
10453 1 << connector
->new_encoder
->new_crtc
->pipe
;
10456 for_each_intel_encoder(dev
, encoder
) {
10457 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10460 if (encoder
->base
.crtc
) {
10461 tmp_crtc
= encoder
->base
.crtc
;
10463 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10466 if (encoder
->new_crtc
)
10467 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10470 /* Check for pipes that will be enabled/disabled ... */
10471 for_each_intel_crtc(dev
, intel_crtc
) {
10472 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10475 if (!intel_crtc
->new_enabled
)
10476 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10478 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10482 /* set_mode is also used to update properties on life display pipes. */
10483 intel_crtc
= to_intel_crtc(crtc
);
10484 if (intel_crtc
->new_enabled
)
10485 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10488 * For simplicity do a full modeset on any pipe where the output routing
10489 * changed. We could be more clever, but that would require us to be
10490 * more careful with calling the relevant encoder->mode_set functions.
10492 if (*prepare_pipes
)
10493 *modeset_pipes
= *prepare_pipes
;
10495 /* ... and mask these out. */
10496 *modeset_pipes
&= ~(*disable_pipes
);
10497 *prepare_pipes
&= ~(*disable_pipes
);
10500 * HACK: We don't (yet) fully support global modesets. intel_set_config
10501 * obies this rule, but the modeset restore mode of
10502 * intel_modeset_setup_hw_state does not.
10504 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10505 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10507 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10508 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10511 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10513 struct drm_encoder
*encoder
;
10514 struct drm_device
*dev
= crtc
->dev
;
10516 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10517 if (encoder
->crtc
== crtc
)
10524 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10526 struct intel_encoder
*intel_encoder
;
10527 struct intel_crtc
*intel_crtc
;
10528 struct drm_connector
*connector
;
10530 for_each_intel_encoder(dev
, intel_encoder
) {
10531 if (!intel_encoder
->base
.crtc
)
10534 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10536 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10537 intel_encoder
->connectors_active
= false;
10540 intel_modeset_commit_output_state(dev
);
10542 /* Double check state. */
10543 for_each_intel_crtc(dev
, intel_crtc
) {
10544 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10545 WARN_ON(intel_crtc
->new_config
&&
10546 intel_crtc
->new_config
!= &intel_crtc
->config
);
10547 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10550 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10551 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10554 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10556 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10557 struct drm_property
*dpms_property
=
10558 dev
->mode_config
.dpms_property
;
10560 connector
->dpms
= DRM_MODE_DPMS_ON
;
10561 drm_object_property_set_value(&connector
->base
,
10565 intel_encoder
= to_intel_encoder(connector
->encoder
);
10566 intel_encoder
->connectors_active
= true;
10572 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10576 if (clock1
== clock2
)
10579 if (!clock1
|| !clock2
)
10582 diff
= abs(clock1
- clock2
);
10584 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10590 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10591 list_for_each_entry((intel_crtc), \
10592 &(dev)->mode_config.crtc_list, \
10594 if (mask & (1 <<(intel_crtc)->pipe))
10597 intel_pipe_config_compare(struct drm_device
*dev
,
10598 struct intel_crtc_config
*current_config
,
10599 struct intel_crtc_config
*pipe_config
)
10601 #define PIPE_CONF_CHECK_X(name) \
10602 if (current_config->name != pipe_config->name) { \
10603 DRM_ERROR("mismatch in " #name " " \
10604 "(expected 0x%08x, found 0x%08x)\n", \
10605 current_config->name, \
10606 pipe_config->name); \
10610 #define PIPE_CONF_CHECK_I(name) \
10611 if (current_config->name != pipe_config->name) { \
10612 DRM_ERROR("mismatch in " #name " " \
10613 "(expected %i, found %i)\n", \
10614 current_config->name, \
10615 pipe_config->name); \
10619 /* This is required for BDW+ where there is only one set of registers for
10620 * switching between high and low RR.
10621 * This macro can be used whenever a comparison has to be made between one
10622 * hw state and multiple sw state variables.
10624 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10625 if ((current_config->name != pipe_config->name) && \
10626 (current_config->alt_name != pipe_config->name)) { \
10627 DRM_ERROR("mismatch in " #name " " \
10628 "(expected %i or %i, found %i)\n", \
10629 current_config->name, \
10630 current_config->alt_name, \
10631 pipe_config->name); \
10635 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10636 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10637 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10638 "(expected %i, found %i)\n", \
10639 current_config->name & (mask), \
10640 pipe_config->name & (mask)); \
10644 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10645 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10646 DRM_ERROR("mismatch in " #name " " \
10647 "(expected %i, found %i)\n", \
10648 current_config->name, \
10649 pipe_config->name); \
10653 #define PIPE_CONF_QUIRK(quirk) \
10654 ((current_config->quirks | pipe_config->quirks) & (quirk))
10656 PIPE_CONF_CHECK_I(cpu_transcoder
);
10658 PIPE_CONF_CHECK_I(has_pch_encoder
);
10659 PIPE_CONF_CHECK_I(fdi_lanes
);
10660 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10661 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10662 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10663 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10664 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10666 PIPE_CONF_CHECK_I(has_dp_encoder
);
10668 if (INTEL_INFO(dev
)->gen
< 8) {
10669 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10670 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10671 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10672 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10673 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10675 if (current_config
->has_drrs
) {
10676 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10677 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10678 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10679 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10680 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10683 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10684 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10685 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10686 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10687 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10690 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10691 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10692 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10693 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10694 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10695 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10697 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10698 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10699 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10700 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10701 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10702 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10704 PIPE_CONF_CHECK_I(pixel_multiplier
);
10705 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10706 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10707 IS_VALLEYVIEW(dev
))
10708 PIPE_CONF_CHECK_I(limited_color_range
);
10710 PIPE_CONF_CHECK_I(has_audio
);
10712 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10713 DRM_MODE_FLAG_INTERLACE
);
10715 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10716 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10717 DRM_MODE_FLAG_PHSYNC
);
10718 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10719 DRM_MODE_FLAG_NHSYNC
);
10720 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10721 DRM_MODE_FLAG_PVSYNC
);
10722 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10723 DRM_MODE_FLAG_NVSYNC
);
10726 PIPE_CONF_CHECK_I(pipe_src_w
);
10727 PIPE_CONF_CHECK_I(pipe_src_h
);
10730 * FIXME: BIOS likes to set up a cloned config with lvds+external
10731 * screen. Since we don't yet re-compute the pipe config when moving
10732 * just the lvds port away to another pipe the sw tracking won't match.
10734 * Proper atomic modesets with recomputed global state will fix this.
10735 * Until then just don't check gmch state for inherited modes.
10737 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10738 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10739 /* pfit ratios are autocomputed by the hw on gen4+ */
10740 if (INTEL_INFO(dev
)->gen
< 4)
10741 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10742 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10745 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10746 if (current_config
->pch_pfit
.enabled
) {
10747 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10748 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10751 /* BDW+ don't expose a synchronous way to read the state */
10752 if (IS_HASWELL(dev
))
10753 PIPE_CONF_CHECK_I(ips_enabled
);
10755 PIPE_CONF_CHECK_I(double_wide
);
10757 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10759 PIPE_CONF_CHECK_I(shared_dpll
);
10760 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10761 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10762 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10763 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10764 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10766 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10767 PIPE_CONF_CHECK_I(pipe_bpp
);
10769 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10770 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10772 #undef PIPE_CONF_CHECK_X
10773 #undef PIPE_CONF_CHECK_I
10774 #undef PIPE_CONF_CHECK_I_ALT
10775 #undef PIPE_CONF_CHECK_FLAGS
10776 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10777 #undef PIPE_CONF_QUIRK
10783 check_connector_state(struct drm_device
*dev
)
10785 struct intel_connector
*connector
;
10787 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10789 /* This also checks the encoder/connector hw state with the
10790 * ->get_hw_state callbacks. */
10791 intel_connector_check_state(connector
);
10793 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10794 "connector's staged encoder doesn't match current encoder\n");
10799 check_encoder_state(struct drm_device
*dev
)
10801 struct intel_encoder
*encoder
;
10802 struct intel_connector
*connector
;
10804 for_each_intel_encoder(dev
, encoder
) {
10805 bool enabled
= false;
10806 bool active
= false;
10807 enum pipe pipe
, tracked_pipe
;
10809 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10810 encoder
->base
.base
.id
,
10811 encoder
->base
.name
);
10813 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10814 "encoder's stage crtc doesn't match current crtc\n");
10815 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10816 "encoder's active_connectors set, but no crtc\n");
10818 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10820 if (connector
->base
.encoder
!= &encoder
->base
)
10823 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10827 * for MST connectors if we unplug the connector is gone
10828 * away but the encoder is still connected to a crtc
10829 * until a modeset happens in response to the hotplug.
10831 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10834 WARN(!!encoder
->base
.crtc
!= enabled
,
10835 "encoder's enabled state mismatch "
10836 "(expected %i, found %i)\n",
10837 !!encoder
->base
.crtc
, enabled
);
10838 WARN(active
&& !encoder
->base
.crtc
,
10839 "active encoder with no crtc\n");
10841 WARN(encoder
->connectors_active
!= active
,
10842 "encoder's computed active state doesn't match tracked active state "
10843 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10845 active
= encoder
->get_hw_state(encoder
, &pipe
);
10846 WARN(active
!= encoder
->connectors_active
,
10847 "encoder's hw state doesn't match sw tracking "
10848 "(expected %i, found %i)\n",
10849 encoder
->connectors_active
, active
);
10851 if (!encoder
->base
.crtc
)
10854 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10855 WARN(active
&& pipe
!= tracked_pipe
,
10856 "active encoder's pipe doesn't match"
10857 "(expected %i, found %i)\n",
10858 tracked_pipe
, pipe
);
10864 check_crtc_state(struct drm_device
*dev
)
10866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10867 struct intel_crtc
*crtc
;
10868 struct intel_encoder
*encoder
;
10869 struct intel_crtc_config pipe_config
;
10871 for_each_intel_crtc(dev
, crtc
) {
10872 bool enabled
= false;
10873 bool active
= false;
10875 memset(&pipe_config
, 0, sizeof(pipe_config
));
10877 DRM_DEBUG_KMS("[CRTC:%d]\n",
10878 crtc
->base
.base
.id
);
10880 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10881 "active crtc, but not enabled in sw tracking\n");
10883 for_each_intel_encoder(dev
, encoder
) {
10884 if (encoder
->base
.crtc
!= &crtc
->base
)
10887 if (encoder
->connectors_active
)
10891 WARN(active
!= crtc
->active
,
10892 "crtc's computed active state doesn't match tracked active state "
10893 "(expected %i, found %i)\n", active
, crtc
->active
);
10894 WARN(enabled
!= crtc
->base
.enabled
,
10895 "crtc's computed enabled state doesn't match tracked enabled state "
10896 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10898 active
= dev_priv
->display
.get_pipe_config(crtc
,
10901 /* hw state is inconsistent with the pipe quirk */
10902 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
10903 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
10904 active
= crtc
->active
;
10906 for_each_intel_encoder(dev
, encoder
) {
10908 if (encoder
->base
.crtc
!= &crtc
->base
)
10910 if (encoder
->get_hw_state(encoder
, &pipe
))
10911 encoder
->get_config(encoder
, &pipe_config
);
10914 WARN(crtc
->active
!= active
,
10915 "crtc active state doesn't match with hw state "
10916 "(expected %i, found %i)\n", crtc
->active
, active
);
10919 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10920 WARN(1, "pipe state doesn't match!\n");
10921 intel_dump_pipe_config(crtc
, &pipe_config
,
10923 intel_dump_pipe_config(crtc
, &crtc
->config
,
10930 check_shared_dpll_state(struct drm_device
*dev
)
10932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10933 struct intel_crtc
*crtc
;
10934 struct intel_dpll_hw_state dpll_hw_state
;
10937 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10938 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10939 int enabled_crtcs
= 0, active_crtcs
= 0;
10942 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10944 DRM_DEBUG_KMS("%s\n", pll
->name
);
10946 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10948 WARN(pll
->active
> pll
->refcount
,
10949 "more active pll users than references: %i vs %i\n",
10950 pll
->active
, pll
->refcount
);
10951 WARN(pll
->active
&& !pll
->on
,
10952 "pll in active use but not on in sw tracking\n");
10953 WARN(pll
->on
&& !pll
->active
,
10954 "pll in on but not on in use in sw tracking\n");
10955 WARN(pll
->on
!= active
,
10956 "pll on state mismatch (expected %i, found %i)\n",
10959 for_each_intel_crtc(dev
, crtc
) {
10960 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10962 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10965 WARN(pll
->active
!= active_crtcs
,
10966 "pll active crtcs mismatch (expected %i, found %i)\n",
10967 pll
->active
, active_crtcs
);
10968 WARN(pll
->refcount
!= enabled_crtcs
,
10969 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10970 pll
->refcount
, enabled_crtcs
);
10972 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
10973 sizeof(dpll_hw_state
)),
10974 "pll hw state mismatch\n");
10979 intel_modeset_check_state(struct drm_device
*dev
)
10981 check_connector_state(dev
);
10982 check_encoder_state(dev
);
10983 check_crtc_state(dev
);
10984 check_shared_dpll_state(dev
);
10987 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10991 * FDI already provided one idea for the dotclock.
10992 * Yell if the encoder disagrees.
10994 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10995 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10996 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10999 static void update_scanline_offset(struct intel_crtc
*crtc
)
11001 struct drm_device
*dev
= crtc
->base
.dev
;
11004 * The scanline counter increments at the leading edge of hsync.
11006 * On most platforms it starts counting from vtotal-1 on the
11007 * first active line. That means the scanline counter value is
11008 * always one less than what we would expect. Ie. just after
11009 * start of vblank, which also occurs at start of hsync (on the
11010 * last active line), the scanline counter will read vblank_start-1.
11012 * On gen2 the scanline counter starts counting from 1 instead
11013 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11014 * to keep the value positive), instead of adding one.
11016 * On HSW+ the behaviour of the scanline counter depends on the output
11017 * type. For DP ports it behaves like most other platforms, but on HDMI
11018 * there's an extra 1 line difference. So we need to add two instead of
11019 * one to the value.
11021 if (IS_GEN2(dev
)) {
11022 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
11025 vtotal
= mode
->crtc_vtotal
;
11026 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11029 crtc
->scanline_offset
= vtotal
- 1;
11030 } else if (HAS_DDI(dev
) &&
11031 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
11032 crtc
->scanline_offset
= 2;
11034 crtc
->scanline_offset
= 1;
11037 static int __intel_set_mode(struct drm_crtc
*crtc
,
11038 struct drm_display_mode
*mode
,
11039 int x
, int y
, struct drm_framebuffer
*fb
)
11041 struct drm_device
*dev
= crtc
->dev
;
11042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11043 struct drm_display_mode
*saved_mode
;
11044 struct intel_crtc_config
*pipe_config
= NULL
;
11045 struct intel_crtc
*intel_crtc
;
11046 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
11049 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11053 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
11054 &prepare_pipes
, &disable_pipes
);
11056 *saved_mode
= crtc
->mode
;
11058 /* Hack: Because we don't (yet) support global modeset on multiple
11059 * crtcs, we don't keep track of the new mode for more than one crtc.
11060 * Hence simply check whether any bit is set in modeset_pipes in all the
11061 * pieces of code that are not yet converted to deal with mutliple crtcs
11062 * changing their mode at the same time. */
11063 if (modeset_pipes
) {
11064 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
11065 if (IS_ERR(pipe_config
)) {
11066 ret
= PTR_ERR(pipe_config
);
11067 pipe_config
= NULL
;
11071 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11073 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11077 * See if the config requires any additional preparation, e.g.
11078 * to adjust global state with pipes off. We need to do this
11079 * here so we can get the modeset_pipe updated config for the new
11080 * mode set on this crtc. For other crtcs we need to use the
11081 * adjusted_mode bits in the crtc directly.
11083 if (IS_VALLEYVIEW(dev
)) {
11084 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11086 /* may have added more to prepare_pipes than we should */
11087 prepare_pipes
&= ~disable_pipes
;
11090 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11091 intel_crtc_disable(&intel_crtc
->base
);
11093 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11094 if (intel_crtc
->base
.enabled
)
11095 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11098 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11099 * to set it here already despite that we pass it down the callchain.
11101 if (modeset_pipes
) {
11102 crtc
->mode
= *mode
;
11103 /* mode_set/enable/disable functions rely on a correct pipe
11105 to_intel_crtc(crtc
)->config
= *pipe_config
;
11106 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
11109 * Calculate and store various constants which
11110 * are later needed by vblank and swap-completion
11111 * timestamping. They are derived from true hwmode.
11113 drm_calc_timestamping_constants(crtc
,
11114 &pipe_config
->adjusted_mode
);
11117 /* Only after disabling all output pipelines that will be changed can we
11118 * update the the output configuration. */
11119 intel_modeset_update_state(dev
, prepare_pipes
);
11121 if (dev_priv
->display
.modeset_global_resources
)
11122 dev_priv
->display
.modeset_global_resources(dev
);
11124 /* Set up the DPLL and any encoders state that needs to adjust or depend
11127 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11128 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11129 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
11130 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11132 mutex_lock(&dev
->struct_mutex
);
11133 ret
= intel_pin_and_fence_fb_obj(dev
,
11137 DRM_ERROR("pin & fence failed\n");
11138 mutex_unlock(&dev
->struct_mutex
);
11142 intel_unpin_fb_obj(old_obj
);
11143 i915_gem_track_fb(old_obj
, obj
,
11144 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11145 mutex_unlock(&dev
->struct_mutex
);
11147 crtc
->primary
->fb
= fb
;
11151 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
11157 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11158 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11159 update_scanline_offset(intel_crtc
);
11161 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11164 /* FIXME: add subpixel order */
11166 if (ret
&& crtc
->enabled
)
11167 crtc
->mode
= *saved_mode
;
11170 kfree(pipe_config
);
11175 static int intel_set_mode(struct drm_crtc
*crtc
,
11176 struct drm_display_mode
*mode
,
11177 int x
, int y
, struct drm_framebuffer
*fb
)
11181 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
11184 intel_modeset_check_state(crtc
->dev
);
11189 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11191 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11194 #undef for_each_intel_crtc_masked
11196 static void intel_set_config_free(struct intel_set_config
*config
)
11201 kfree(config
->save_connector_encoders
);
11202 kfree(config
->save_encoder_crtcs
);
11203 kfree(config
->save_crtc_enabled
);
11207 static int intel_set_config_save_state(struct drm_device
*dev
,
11208 struct intel_set_config
*config
)
11210 struct drm_crtc
*crtc
;
11211 struct drm_encoder
*encoder
;
11212 struct drm_connector
*connector
;
11215 config
->save_crtc_enabled
=
11216 kcalloc(dev
->mode_config
.num_crtc
,
11217 sizeof(bool), GFP_KERNEL
);
11218 if (!config
->save_crtc_enabled
)
11221 config
->save_encoder_crtcs
=
11222 kcalloc(dev
->mode_config
.num_encoder
,
11223 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11224 if (!config
->save_encoder_crtcs
)
11227 config
->save_connector_encoders
=
11228 kcalloc(dev
->mode_config
.num_connector
,
11229 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11230 if (!config
->save_connector_encoders
)
11233 /* Copy data. Note that driver private data is not affected.
11234 * Should anything bad happen only the expected state is
11235 * restored, not the drivers personal bookkeeping.
11238 for_each_crtc(dev
, crtc
) {
11239 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11243 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11244 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11248 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11249 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11255 static void intel_set_config_restore_state(struct drm_device
*dev
,
11256 struct intel_set_config
*config
)
11258 struct intel_crtc
*crtc
;
11259 struct intel_encoder
*encoder
;
11260 struct intel_connector
*connector
;
11264 for_each_intel_crtc(dev
, crtc
) {
11265 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11267 if (crtc
->new_enabled
)
11268 crtc
->new_config
= &crtc
->config
;
11270 crtc
->new_config
= NULL
;
11274 for_each_intel_encoder(dev
, encoder
) {
11275 encoder
->new_crtc
=
11276 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11280 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11281 connector
->new_encoder
=
11282 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11287 is_crtc_connector_off(struct drm_mode_set
*set
)
11291 if (set
->num_connectors
== 0)
11294 if (WARN_ON(set
->connectors
== NULL
))
11297 for (i
= 0; i
< set
->num_connectors
; i
++)
11298 if (set
->connectors
[i
]->encoder
&&
11299 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11300 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11307 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11308 struct intel_set_config
*config
)
11311 /* We should be able to check here if the fb has the same properties
11312 * and then just flip_or_move it */
11313 if (is_crtc_connector_off(set
)) {
11314 config
->mode_changed
= true;
11315 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11317 * If we have no fb, we can only flip as long as the crtc is
11318 * active, otherwise we need a full mode set. The crtc may
11319 * be active if we've only disabled the primary plane, or
11320 * in fastboot situations.
11322 if (set
->crtc
->primary
->fb
== NULL
) {
11323 struct intel_crtc
*intel_crtc
=
11324 to_intel_crtc(set
->crtc
);
11326 if (intel_crtc
->active
) {
11327 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11328 config
->fb_changed
= true;
11330 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11331 config
->mode_changed
= true;
11333 } else if (set
->fb
== NULL
) {
11334 config
->mode_changed
= true;
11335 } else if (set
->fb
->pixel_format
!=
11336 set
->crtc
->primary
->fb
->pixel_format
) {
11337 config
->mode_changed
= true;
11339 config
->fb_changed
= true;
11343 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11344 config
->fb_changed
= true;
11346 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11347 DRM_DEBUG_KMS("modes are different, full mode set\n");
11348 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11349 drm_mode_debug_printmodeline(set
->mode
);
11350 config
->mode_changed
= true;
11353 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11354 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11358 intel_modeset_stage_output_state(struct drm_device
*dev
,
11359 struct drm_mode_set
*set
,
11360 struct intel_set_config
*config
)
11362 struct intel_connector
*connector
;
11363 struct intel_encoder
*encoder
;
11364 struct intel_crtc
*crtc
;
11367 /* The upper layers ensure that we either disable a crtc or have a list
11368 * of connectors. For paranoia, double-check this. */
11369 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11370 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11372 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11374 /* Otherwise traverse passed in connector list and get encoders
11376 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11377 if (set
->connectors
[ro
] == &connector
->base
) {
11378 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11383 /* If we disable the crtc, disable all its connectors. Also, if
11384 * the connector is on the changing crtc but not on the new
11385 * connector list, disable it. */
11386 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11387 connector
->base
.encoder
&&
11388 connector
->base
.encoder
->crtc
== set
->crtc
) {
11389 connector
->new_encoder
= NULL
;
11391 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11392 connector
->base
.base
.id
,
11393 connector
->base
.name
);
11397 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11398 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11399 config
->mode_changed
= true;
11402 /* connector->new_encoder is now updated for all connectors. */
11404 /* Update crtc of enabled connectors. */
11405 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11407 struct drm_crtc
*new_crtc
;
11409 if (!connector
->new_encoder
)
11412 new_crtc
= connector
->new_encoder
->base
.crtc
;
11414 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11415 if (set
->connectors
[ro
] == &connector
->base
)
11416 new_crtc
= set
->crtc
;
11419 /* Make sure the new CRTC will work with the encoder */
11420 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11424 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11426 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11427 connector
->base
.base
.id
,
11428 connector
->base
.name
,
11429 new_crtc
->base
.id
);
11432 /* Check for any encoders that needs to be disabled. */
11433 for_each_intel_encoder(dev
, encoder
) {
11434 int num_connectors
= 0;
11435 list_for_each_entry(connector
,
11436 &dev
->mode_config
.connector_list
,
11438 if (connector
->new_encoder
== encoder
) {
11439 WARN_ON(!connector
->new_encoder
->new_crtc
);
11444 if (num_connectors
== 0)
11445 encoder
->new_crtc
= NULL
;
11446 else if (num_connectors
> 1)
11449 /* Only now check for crtc changes so we don't miss encoders
11450 * that will be disabled. */
11451 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11452 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11453 config
->mode_changed
= true;
11456 /* Now we've also updated encoder->new_crtc for all encoders. */
11457 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11459 if (connector
->new_encoder
)
11460 if (connector
->new_encoder
!= connector
->encoder
)
11461 connector
->encoder
= connector
->new_encoder
;
11463 for_each_intel_crtc(dev
, crtc
) {
11464 crtc
->new_enabled
= false;
11466 for_each_intel_encoder(dev
, encoder
) {
11467 if (encoder
->new_crtc
== crtc
) {
11468 crtc
->new_enabled
= true;
11473 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11474 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11475 crtc
->new_enabled
? "en" : "dis");
11476 config
->mode_changed
= true;
11479 if (crtc
->new_enabled
)
11480 crtc
->new_config
= &crtc
->config
;
11482 crtc
->new_config
= NULL
;
11488 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11490 struct drm_device
*dev
= crtc
->base
.dev
;
11491 struct intel_encoder
*encoder
;
11492 struct intel_connector
*connector
;
11494 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11495 pipe_name(crtc
->pipe
));
11497 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11498 if (connector
->new_encoder
&&
11499 connector
->new_encoder
->new_crtc
== crtc
)
11500 connector
->new_encoder
= NULL
;
11503 for_each_intel_encoder(dev
, encoder
) {
11504 if (encoder
->new_crtc
== crtc
)
11505 encoder
->new_crtc
= NULL
;
11508 crtc
->new_enabled
= false;
11509 crtc
->new_config
= NULL
;
11512 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11514 struct drm_device
*dev
;
11515 struct drm_mode_set save_set
;
11516 struct intel_set_config
*config
;
11520 BUG_ON(!set
->crtc
);
11521 BUG_ON(!set
->crtc
->helper_private
);
11523 /* Enforce sane interface api - has been abused by the fb helper. */
11524 BUG_ON(!set
->mode
&& set
->fb
);
11525 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11528 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11529 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11530 (int)set
->num_connectors
, set
->x
, set
->y
);
11532 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11535 dev
= set
->crtc
->dev
;
11538 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11542 ret
= intel_set_config_save_state(dev
, config
);
11546 save_set
.crtc
= set
->crtc
;
11547 save_set
.mode
= &set
->crtc
->mode
;
11548 save_set
.x
= set
->crtc
->x
;
11549 save_set
.y
= set
->crtc
->y
;
11550 save_set
.fb
= set
->crtc
->primary
->fb
;
11552 /* Compute whether we need a full modeset, only an fb base update or no
11553 * change at all. In the future we might also check whether only the
11554 * mode changed, e.g. for LVDS where we only change the panel fitter in
11556 intel_set_config_compute_mode_changes(set
, config
);
11558 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11562 if (config
->mode_changed
) {
11563 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11564 set
->x
, set
->y
, set
->fb
);
11565 } else if (config
->fb_changed
) {
11566 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11568 intel_crtc_wait_for_pending_flips(set
->crtc
);
11570 ret
= intel_pipe_set_base(set
->crtc
,
11571 set
->x
, set
->y
, set
->fb
);
11574 * We need to make sure the primary plane is re-enabled if it
11575 * has previously been turned off.
11577 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11578 WARN_ON(!intel_crtc
->active
);
11579 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11583 * In the fastboot case this may be our only check of the
11584 * state after boot. It would be better to only do it on
11585 * the first update, but we don't have a nice way of doing that
11586 * (and really, set_config isn't used much for high freq page
11587 * flipping, so increasing its cost here shouldn't be a big
11590 if (i915
.fastboot
&& ret
== 0)
11591 intel_modeset_check_state(set
->crtc
->dev
);
11595 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11596 set
->crtc
->base
.id
, ret
);
11598 intel_set_config_restore_state(dev
, config
);
11601 * HACK: if the pipe was on, but we didn't have a framebuffer,
11602 * force the pipe off to avoid oopsing in the modeset code
11603 * due to fb==NULL. This should only happen during boot since
11604 * we don't yet reconstruct the FB from the hardware state.
11606 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11607 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11609 /* Try to restore the config */
11610 if (config
->mode_changed
&&
11611 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11612 save_set
.x
, save_set
.y
, save_set
.fb
))
11613 DRM_ERROR("failed to restore config after modeset failure\n");
11617 intel_set_config_free(config
);
11621 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11622 .gamma_set
= intel_crtc_gamma_set
,
11623 .set_config
= intel_crtc_set_config
,
11624 .destroy
= intel_crtc_destroy
,
11625 .page_flip
= intel_crtc_page_flip
,
11628 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11629 struct intel_shared_dpll
*pll
,
11630 struct intel_dpll_hw_state
*hw_state
)
11634 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11637 val
= I915_READ(PCH_DPLL(pll
->id
));
11638 hw_state
->dpll
= val
;
11639 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11640 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11642 return val
& DPLL_VCO_ENABLE
;
11645 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11646 struct intel_shared_dpll
*pll
)
11648 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11649 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11652 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11653 struct intel_shared_dpll
*pll
)
11655 /* PCH refclock must be enabled first */
11656 ibx_assert_pch_refclk_enabled(dev_priv
);
11658 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11660 /* Wait for the clocks to stabilize. */
11661 POSTING_READ(PCH_DPLL(pll
->id
));
11664 /* The pixel multiplier can only be updated once the
11665 * DPLL is enabled and the clocks are stable.
11667 * So write it again.
11669 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11670 POSTING_READ(PCH_DPLL(pll
->id
));
11674 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11675 struct intel_shared_dpll
*pll
)
11677 struct drm_device
*dev
= dev_priv
->dev
;
11678 struct intel_crtc
*crtc
;
11680 /* Make sure no transcoder isn't still depending on us. */
11681 for_each_intel_crtc(dev
, crtc
) {
11682 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11683 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11686 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11687 POSTING_READ(PCH_DPLL(pll
->id
));
11691 static char *ibx_pch_dpll_names
[] = {
11696 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11701 dev_priv
->num_shared_dpll
= 2;
11703 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11704 dev_priv
->shared_dplls
[i
].id
= i
;
11705 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11706 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11707 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11708 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11709 dev_priv
->shared_dplls
[i
].get_hw_state
=
11710 ibx_pch_dpll_get_hw_state
;
11714 static void intel_shared_dpll_init(struct drm_device
*dev
)
11716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11719 intel_ddi_pll_init(dev
);
11720 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11721 ibx_pch_dpll_init(dev
);
11723 dev_priv
->num_shared_dpll
= 0;
11725 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11729 intel_primary_plane_disable(struct drm_plane
*plane
)
11731 struct drm_device
*dev
= plane
->dev
;
11732 struct intel_crtc
*intel_crtc
;
11737 BUG_ON(!plane
->crtc
);
11739 intel_crtc
= to_intel_crtc(plane
->crtc
);
11742 * Even though we checked plane->fb above, it's still possible that
11743 * the primary plane has been implicitly disabled because the crtc
11744 * coordinates given weren't visible, or because we detected
11745 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11746 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11747 * In either case, we need to unpin the FB and let the fb pointer get
11748 * updated, but otherwise we don't need to touch the hardware.
11750 if (!intel_crtc
->primary_enabled
)
11751 goto disable_unpin
;
11753 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11754 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11757 mutex_lock(&dev
->struct_mutex
);
11758 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11759 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11760 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11761 mutex_unlock(&dev
->struct_mutex
);
11768 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11769 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11770 unsigned int crtc_w
, unsigned int crtc_h
,
11771 uint32_t src_x
, uint32_t src_y
,
11772 uint32_t src_w
, uint32_t src_h
)
11774 struct drm_device
*dev
= crtc
->dev
;
11775 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11776 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11777 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11778 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11779 struct drm_rect dest
= {
11780 /* integer pixels */
11783 .x2
= crtc_x
+ crtc_w
,
11784 .y2
= crtc_y
+ crtc_h
,
11786 struct drm_rect src
= {
11787 /* 16.16 fixed point */
11790 .x2
= src_x
+ src_w
,
11791 .y2
= src_y
+ src_h
,
11793 const struct drm_rect clip
= {
11794 /* integer pixels */
11795 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11796 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11799 int crtc_x
, crtc_y
;
11800 unsigned int crtc_w
, crtc_h
;
11801 uint32_t src_x
, src_y
, src_w
, src_h
;
11812 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11816 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11817 &src
, &dest
, &clip
,
11818 DRM_PLANE_HELPER_NO_SCALING
,
11819 DRM_PLANE_HELPER_NO_SCALING
,
11820 false, true, &visible
);
11826 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11827 * updating the fb pointer, and returning without touching the
11828 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11829 * turn on the display with all planes setup as desired.
11831 if (!crtc
->enabled
) {
11832 mutex_lock(&dev
->struct_mutex
);
11835 * If we already called setplane while the crtc was disabled,
11836 * we may have an fb pinned; unpin it.
11839 intel_unpin_fb_obj(old_obj
);
11841 i915_gem_track_fb(old_obj
, obj
,
11842 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11844 /* Pin and return without programming hardware */
11845 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11846 mutex_unlock(&dev
->struct_mutex
);
11851 intel_crtc_wait_for_pending_flips(crtc
);
11854 * If clipping results in a non-visible primary plane, we'll disable
11855 * the primary plane. Note that this is a bit different than what
11856 * happens if userspace explicitly disables the plane by passing fb=0
11857 * because plane->fb still gets set and pinned.
11860 mutex_lock(&dev
->struct_mutex
);
11863 * Try to pin the new fb first so that we can bail out if we
11866 if (plane
->fb
!= fb
) {
11867 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11869 mutex_unlock(&dev
->struct_mutex
);
11874 i915_gem_track_fb(old_obj
, obj
,
11875 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11877 if (intel_crtc
->primary_enabled
)
11878 intel_disable_primary_hw_plane(plane
, crtc
);
11881 if (plane
->fb
!= fb
)
11883 intel_unpin_fb_obj(old_obj
);
11885 mutex_unlock(&dev
->struct_mutex
);
11888 if (intel_crtc
&& intel_crtc
->active
&&
11889 intel_crtc
->primary_enabled
) {
11891 * FBC does not work on some platforms for rotated
11892 * planes, so disable it when rotation is not 0 and
11893 * update it when rotation is set back to 0.
11895 * FIXME: This is redundant with the fbc update done in
11896 * the primary plane enable function except that that
11897 * one is done too late. We eventually need to unify
11900 if (INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11901 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11902 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11903 intel_disable_fbc(dev
);
11906 ret
= intel_pipe_set_base(crtc
, src
.x1
, src
.y1
, fb
);
11910 if (!intel_crtc
->primary_enabled
)
11911 intel_enable_primary_hw_plane(plane
, crtc
);
11914 intel_plane
->crtc_x
= orig
.crtc_x
;
11915 intel_plane
->crtc_y
= orig
.crtc_y
;
11916 intel_plane
->crtc_w
= orig
.crtc_w
;
11917 intel_plane
->crtc_h
= orig
.crtc_h
;
11918 intel_plane
->src_x
= orig
.src_x
;
11919 intel_plane
->src_y
= orig
.src_y
;
11920 intel_plane
->src_w
= orig
.src_w
;
11921 intel_plane
->src_h
= orig
.src_h
;
11922 intel_plane
->obj
= obj
;
11927 /* Common destruction function for both primary and cursor planes */
11928 static void intel_plane_destroy(struct drm_plane
*plane
)
11930 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11931 drm_plane_cleanup(plane
);
11932 kfree(intel_plane
);
11935 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11936 .update_plane
= intel_primary_plane_setplane
,
11937 .disable_plane
= intel_primary_plane_disable
,
11938 .destroy
= intel_plane_destroy
,
11939 .set_property
= intel_plane_set_property
11942 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11945 struct intel_plane
*primary
;
11946 const uint32_t *intel_primary_formats
;
11949 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11950 if (primary
== NULL
)
11953 primary
->can_scale
= false;
11954 primary
->max_downscale
= 1;
11955 primary
->pipe
= pipe
;
11956 primary
->plane
= pipe
;
11957 primary
->rotation
= BIT(DRM_ROTATE_0
);
11958 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11959 primary
->plane
= !pipe
;
11961 if (INTEL_INFO(dev
)->gen
<= 3) {
11962 intel_primary_formats
= intel_primary_formats_gen2
;
11963 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11965 intel_primary_formats
= intel_primary_formats_gen4
;
11966 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11969 drm_universal_plane_init(dev
, &primary
->base
, 0,
11970 &intel_primary_plane_funcs
,
11971 intel_primary_formats
, num_formats
,
11972 DRM_PLANE_TYPE_PRIMARY
);
11974 if (INTEL_INFO(dev
)->gen
>= 4) {
11975 if (!dev
->mode_config
.rotation_property
)
11976 dev
->mode_config
.rotation_property
=
11977 drm_mode_create_rotation_property(dev
,
11978 BIT(DRM_ROTATE_0
) |
11979 BIT(DRM_ROTATE_180
));
11980 if (dev
->mode_config
.rotation_property
)
11981 drm_object_attach_property(&primary
->base
.base
,
11982 dev
->mode_config
.rotation_property
,
11983 primary
->rotation
);
11986 return &primary
->base
;
11990 intel_cursor_plane_disable(struct drm_plane
*plane
)
11995 BUG_ON(!plane
->crtc
);
11997 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
12001 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
12002 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
12003 unsigned int crtc_w
, unsigned int crtc_h
,
12004 uint32_t src_x
, uint32_t src_y
,
12005 uint32_t src_w
, uint32_t src_h
)
12007 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12008 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12009 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12010 struct drm_rect dest
= {
12011 /* integer pixels */
12014 .x2
= crtc_x
+ crtc_w
,
12015 .y2
= crtc_y
+ crtc_h
,
12017 struct drm_rect src
= {
12018 /* 16.16 fixed point */
12021 .x2
= src_x
+ src_w
,
12022 .y2
= src_y
+ src_h
,
12024 const struct drm_rect clip
= {
12025 /* integer pixels */
12026 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
12027 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
12032 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12033 &src
, &dest
, &clip
,
12034 DRM_PLANE_HELPER_NO_SCALING
,
12035 DRM_PLANE_HELPER_NO_SCALING
,
12036 true, true, &visible
);
12040 crtc
->cursor_x
= crtc_x
;
12041 crtc
->cursor_y
= crtc_y
;
12042 if (fb
!= crtc
->cursor
->fb
) {
12043 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
12045 intel_crtc_update_cursor(crtc
, visible
);
12047 intel_frontbuffer_flip(crtc
->dev
,
12048 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
12053 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
12054 .update_plane
= intel_cursor_plane_update
,
12055 .disable_plane
= intel_cursor_plane_disable
,
12056 .destroy
= intel_plane_destroy
,
12059 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12062 struct intel_plane
*cursor
;
12064 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12065 if (cursor
== NULL
)
12068 cursor
->can_scale
= false;
12069 cursor
->max_downscale
= 1;
12070 cursor
->pipe
= pipe
;
12071 cursor
->plane
= pipe
;
12073 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12074 &intel_cursor_plane_funcs
,
12075 intel_cursor_formats
,
12076 ARRAY_SIZE(intel_cursor_formats
),
12077 DRM_PLANE_TYPE_CURSOR
);
12078 return &cursor
->base
;
12081 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12083 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12084 struct intel_crtc
*intel_crtc
;
12085 struct drm_plane
*primary
= NULL
;
12086 struct drm_plane
*cursor
= NULL
;
12089 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12090 if (intel_crtc
== NULL
)
12093 primary
= intel_primary_plane_create(dev
, pipe
);
12097 cursor
= intel_cursor_plane_create(dev
, pipe
);
12101 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12102 cursor
, &intel_crtc_funcs
);
12106 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12107 for (i
= 0; i
< 256; i
++) {
12108 intel_crtc
->lut_r
[i
] = i
;
12109 intel_crtc
->lut_g
[i
] = i
;
12110 intel_crtc
->lut_b
[i
] = i
;
12114 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12115 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12117 intel_crtc
->pipe
= pipe
;
12118 intel_crtc
->plane
= pipe
;
12119 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12120 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12121 intel_crtc
->plane
= !pipe
;
12124 intel_crtc
->cursor_base
= ~0;
12125 intel_crtc
->cursor_cntl
= ~0;
12126 intel_crtc
->cursor_size
= ~0;
12128 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
12129 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
12130 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
12131 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
12133 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
12135 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
12140 drm_plane_cleanup(primary
);
12142 drm_plane_cleanup(cursor
);
12146 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
12148 struct drm_encoder
*encoder
= connector
->base
.encoder
;
12149 struct drm_device
*dev
= connector
->base
.dev
;
12151 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12154 return INVALID_PIPE
;
12156 return to_intel_crtc(encoder
->crtc
)->pipe
;
12159 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12160 struct drm_file
*file
)
12162 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12163 struct drm_crtc
*drmmode_crtc
;
12164 struct intel_crtc
*crtc
;
12166 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12169 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12171 if (!drmmode_crtc
) {
12172 DRM_ERROR("no such CRTC id\n");
12176 crtc
= to_intel_crtc(drmmode_crtc
);
12177 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12182 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12184 struct drm_device
*dev
= encoder
->base
.dev
;
12185 struct intel_encoder
*source_encoder
;
12186 int index_mask
= 0;
12189 for_each_intel_encoder(dev
, source_encoder
) {
12190 if (encoders_cloneable(encoder
, source_encoder
))
12191 index_mask
|= (1 << entry
);
12199 static bool has_edp_a(struct drm_device
*dev
)
12201 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12203 if (!IS_MOBILE(dev
))
12206 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12209 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12215 const char *intel_output_name(int output
)
12217 static const char *names
[] = {
12218 [INTEL_OUTPUT_UNUSED
] = "Unused",
12219 [INTEL_OUTPUT_ANALOG
] = "Analog",
12220 [INTEL_OUTPUT_DVO
] = "DVO",
12221 [INTEL_OUTPUT_SDVO
] = "SDVO",
12222 [INTEL_OUTPUT_LVDS
] = "LVDS",
12223 [INTEL_OUTPUT_TVOUT
] = "TV",
12224 [INTEL_OUTPUT_HDMI
] = "HDMI",
12225 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12226 [INTEL_OUTPUT_EDP
] = "eDP",
12227 [INTEL_OUTPUT_DSI
] = "DSI",
12228 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12231 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12234 return names
[output
];
12237 static bool intel_crt_present(struct drm_device
*dev
)
12239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12244 if (IS_CHERRYVIEW(dev
))
12247 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12253 static void intel_setup_outputs(struct drm_device
*dev
)
12255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12256 struct intel_encoder
*encoder
;
12257 bool dpd_is_edp
= false;
12259 intel_lvds_init(dev
);
12261 if (intel_crt_present(dev
))
12262 intel_crt_init(dev
);
12264 if (HAS_DDI(dev
)) {
12267 /* Haswell uses DDI functions to detect digital outputs */
12268 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12269 /* DDI A only supports eDP */
12271 intel_ddi_init(dev
, PORT_A
);
12273 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12275 found
= I915_READ(SFUSE_STRAP
);
12277 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12278 intel_ddi_init(dev
, PORT_B
);
12279 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12280 intel_ddi_init(dev
, PORT_C
);
12281 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12282 intel_ddi_init(dev
, PORT_D
);
12283 } else if (HAS_PCH_SPLIT(dev
)) {
12285 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12287 if (has_edp_a(dev
))
12288 intel_dp_init(dev
, DP_A
, PORT_A
);
12290 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12291 /* PCH SDVOB multiplex with HDMIB */
12292 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12294 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12295 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12296 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12299 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12300 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12302 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12303 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12305 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12306 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12308 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12309 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12310 } else if (IS_VALLEYVIEW(dev
)) {
12311 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
12312 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12314 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
12315 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12318 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
12319 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12321 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
12322 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12325 if (IS_CHERRYVIEW(dev
)) {
12326 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
12327 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12329 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12330 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12334 intel_dsi_init(dev
);
12335 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12336 bool found
= false;
12338 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12339 DRM_DEBUG_KMS("probing SDVOB\n");
12340 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12341 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12342 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12343 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12346 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12347 intel_dp_init(dev
, DP_B
, PORT_B
);
12350 /* Before G4X SDVOC doesn't have its own detect register */
12352 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12353 DRM_DEBUG_KMS("probing SDVOC\n");
12354 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12357 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12359 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12360 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12361 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12363 if (SUPPORTS_INTEGRATED_DP(dev
))
12364 intel_dp_init(dev
, DP_C
, PORT_C
);
12367 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12368 (I915_READ(DP_D
) & DP_DETECTED
))
12369 intel_dp_init(dev
, DP_D
, PORT_D
);
12370 } else if (IS_GEN2(dev
))
12371 intel_dvo_init(dev
);
12373 if (SUPPORTS_TV(dev
))
12374 intel_tv_init(dev
);
12376 intel_edp_psr_init(dev
);
12378 for_each_intel_encoder(dev
, encoder
) {
12379 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12380 encoder
->base
.possible_clones
=
12381 intel_encoder_clones(encoder
);
12384 intel_init_pch_refclk(dev
);
12386 drm_helper_move_panel_connectors_to_head(dev
);
12389 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12391 struct drm_device
*dev
= fb
->dev
;
12392 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12394 drm_framebuffer_cleanup(fb
);
12395 mutex_lock(&dev
->struct_mutex
);
12396 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12397 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12398 mutex_unlock(&dev
->struct_mutex
);
12402 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12403 struct drm_file
*file
,
12404 unsigned int *handle
)
12406 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12407 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12409 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12412 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12413 .destroy
= intel_user_framebuffer_destroy
,
12414 .create_handle
= intel_user_framebuffer_create_handle
,
12417 static int intel_framebuffer_init(struct drm_device
*dev
,
12418 struct intel_framebuffer
*intel_fb
,
12419 struct drm_mode_fb_cmd2
*mode_cmd
,
12420 struct drm_i915_gem_object
*obj
)
12422 int aligned_height
;
12426 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12428 if (obj
->tiling_mode
== I915_TILING_Y
) {
12429 DRM_DEBUG("hardware does not support tiling Y\n");
12433 if (mode_cmd
->pitches
[0] & 63) {
12434 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12435 mode_cmd
->pitches
[0]);
12439 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12440 pitch_limit
= 32*1024;
12441 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12442 if (obj
->tiling_mode
)
12443 pitch_limit
= 16*1024;
12445 pitch_limit
= 32*1024;
12446 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12447 if (obj
->tiling_mode
)
12448 pitch_limit
= 8*1024;
12450 pitch_limit
= 16*1024;
12452 /* XXX DSPC is limited to 4k tiled */
12453 pitch_limit
= 8*1024;
12455 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12456 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12457 obj
->tiling_mode
? "tiled" : "linear",
12458 mode_cmd
->pitches
[0], pitch_limit
);
12462 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12463 mode_cmd
->pitches
[0] != obj
->stride
) {
12464 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12465 mode_cmd
->pitches
[0], obj
->stride
);
12469 /* Reject formats not supported by any plane early. */
12470 switch (mode_cmd
->pixel_format
) {
12471 case DRM_FORMAT_C8
:
12472 case DRM_FORMAT_RGB565
:
12473 case DRM_FORMAT_XRGB8888
:
12474 case DRM_FORMAT_ARGB8888
:
12476 case DRM_FORMAT_XRGB1555
:
12477 case DRM_FORMAT_ARGB1555
:
12478 if (INTEL_INFO(dev
)->gen
> 3) {
12479 DRM_DEBUG("unsupported pixel format: %s\n",
12480 drm_get_format_name(mode_cmd
->pixel_format
));
12484 case DRM_FORMAT_XBGR8888
:
12485 case DRM_FORMAT_ABGR8888
:
12486 case DRM_FORMAT_XRGB2101010
:
12487 case DRM_FORMAT_ARGB2101010
:
12488 case DRM_FORMAT_XBGR2101010
:
12489 case DRM_FORMAT_ABGR2101010
:
12490 if (INTEL_INFO(dev
)->gen
< 4) {
12491 DRM_DEBUG("unsupported pixel format: %s\n",
12492 drm_get_format_name(mode_cmd
->pixel_format
));
12496 case DRM_FORMAT_YUYV
:
12497 case DRM_FORMAT_UYVY
:
12498 case DRM_FORMAT_YVYU
:
12499 case DRM_FORMAT_VYUY
:
12500 if (INTEL_INFO(dev
)->gen
< 5) {
12501 DRM_DEBUG("unsupported pixel format: %s\n",
12502 drm_get_format_name(mode_cmd
->pixel_format
));
12507 DRM_DEBUG("unsupported pixel format: %s\n",
12508 drm_get_format_name(mode_cmd
->pixel_format
));
12512 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12513 if (mode_cmd
->offsets
[0] != 0)
12516 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12518 /* FIXME drm helper for size checks (especially planar formats)? */
12519 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12522 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12523 intel_fb
->obj
= obj
;
12524 intel_fb
->obj
->framebuffer_references
++;
12526 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12528 DRM_ERROR("framebuffer init failed %d\n", ret
);
12535 static struct drm_framebuffer
*
12536 intel_user_framebuffer_create(struct drm_device
*dev
,
12537 struct drm_file
*filp
,
12538 struct drm_mode_fb_cmd2
*mode_cmd
)
12540 struct drm_i915_gem_object
*obj
;
12542 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12543 mode_cmd
->handles
[0]));
12544 if (&obj
->base
== NULL
)
12545 return ERR_PTR(-ENOENT
);
12547 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12550 #ifndef CONFIG_DRM_I915_FBDEV
12551 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12556 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12557 .fb_create
= intel_user_framebuffer_create
,
12558 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12561 /* Set up chip specific display functions */
12562 static void intel_init_display(struct drm_device
*dev
)
12564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12566 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12567 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12568 else if (IS_CHERRYVIEW(dev
))
12569 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12570 else if (IS_VALLEYVIEW(dev
))
12571 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12572 else if (IS_PINEVIEW(dev
))
12573 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12575 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12577 if (HAS_DDI(dev
)) {
12578 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12579 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12580 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12581 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12582 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12583 dev_priv
->display
.off
= ironlake_crtc_off
;
12584 dev_priv
->display
.update_primary_plane
=
12585 ironlake_update_primary_plane
;
12586 } else if (HAS_PCH_SPLIT(dev
)) {
12587 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12588 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12589 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12590 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12591 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12592 dev_priv
->display
.off
= ironlake_crtc_off
;
12593 dev_priv
->display
.update_primary_plane
=
12594 ironlake_update_primary_plane
;
12595 } else if (IS_VALLEYVIEW(dev
)) {
12596 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12597 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12598 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12599 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12600 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12601 dev_priv
->display
.off
= i9xx_crtc_off
;
12602 dev_priv
->display
.update_primary_plane
=
12603 i9xx_update_primary_plane
;
12605 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12606 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12607 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12608 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12609 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12610 dev_priv
->display
.off
= i9xx_crtc_off
;
12611 dev_priv
->display
.update_primary_plane
=
12612 i9xx_update_primary_plane
;
12615 /* Returns the core display clock speed */
12616 if (IS_VALLEYVIEW(dev
))
12617 dev_priv
->display
.get_display_clock_speed
=
12618 valleyview_get_display_clock_speed
;
12619 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12620 dev_priv
->display
.get_display_clock_speed
=
12621 i945_get_display_clock_speed
;
12622 else if (IS_I915G(dev
))
12623 dev_priv
->display
.get_display_clock_speed
=
12624 i915_get_display_clock_speed
;
12625 else if (IS_I945GM(dev
) || IS_845G(dev
))
12626 dev_priv
->display
.get_display_clock_speed
=
12627 i9xx_misc_get_display_clock_speed
;
12628 else if (IS_PINEVIEW(dev
))
12629 dev_priv
->display
.get_display_clock_speed
=
12630 pnv_get_display_clock_speed
;
12631 else if (IS_I915GM(dev
))
12632 dev_priv
->display
.get_display_clock_speed
=
12633 i915gm_get_display_clock_speed
;
12634 else if (IS_I865G(dev
))
12635 dev_priv
->display
.get_display_clock_speed
=
12636 i865_get_display_clock_speed
;
12637 else if (IS_I85X(dev
))
12638 dev_priv
->display
.get_display_clock_speed
=
12639 i855_get_display_clock_speed
;
12640 else /* 852, 830 */
12641 dev_priv
->display
.get_display_clock_speed
=
12642 i830_get_display_clock_speed
;
12645 dev_priv
->display
.write_eld
= g4x_write_eld
;
12646 } else if (IS_GEN5(dev
)) {
12647 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12648 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12649 } else if (IS_GEN6(dev
)) {
12650 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12651 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12652 dev_priv
->display
.modeset_global_resources
=
12653 snb_modeset_global_resources
;
12654 } else if (IS_IVYBRIDGE(dev
)) {
12655 /* FIXME: detect B0+ stepping and use auto training */
12656 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12657 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12658 dev_priv
->display
.modeset_global_resources
=
12659 ivb_modeset_global_resources
;
12660 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
12661 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12662 dev_priv
->display
.write_eld
= haswell_write_eld
;
12663 dev_priv
->display
.modeset_global_resources
=
12664 haswell_modeset_global_resources
;
12665 } else if (IS_VALLEYVIEW(dev
)) {
12666 dev_priv
->display
.modeset_global_resources
=
12667 valleyview_modeset_global_resources
;
12668 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12671 /* Default just returns -ENODEV to indicate unsupported */
12672 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12674 switch (INTEL_INFO(dev
)->gen
) {
12676 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12680 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12685 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12689 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12692 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12693 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12697 intel_panel_init_backlight_funcs(dev
);
12699 mutex_init(&dev_priv
->pps_mutex
);
12703 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12704 * resume, or other times. This quirk makes sure that's the case for
12705 * affected systems.
12707 static void quirk_pipea_force(struct drm_device
*dev
)
12709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12711 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12712 DRM_INFO("applying pipe a force quirk\n");
12715 static void quirk_pipeb_force(struct drm_device
*dev
)
12717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12719 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
12720 DRM_INFO("applying pipe b force quirk\n");
12724 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12726 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12729 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12730 DRM_INFO("applying lvds SSC disable quirk\n");
12734 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12737 static void quirk_invert_brightness(struct drm_device
*dev
)
12739 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12740 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12741 DRM_INFO("applying inverted panel brightness quirk\n");
12744 /* Some VBT's incorrectly indicate no backlight is present */
12745 static void quirk_backlight_present(struct drm_device
*dev
)
12747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12748 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12749 DRM_INFO("applying backlight present quirk\n");
12752 struct intel_quirk
{
12754 int subsystem_vendor
;
12755 int subsystem_device
;
12756 void (*hook
)(struct drm_device
*dev
);
12759 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12760 struct intel_dmi_quirk
{
12761 void (*hook
)(struct drm_device
*dev
);
12762 const struct dmi_system_id (*dmi_id_list
)[];
12765 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12767 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12771 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12773 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12775 .callback
= intel_dmi_reverse_brightness
,
12776 .ident
= "NCR Corporation",
12777 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12778 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12781 { } /* terminating entry */
12783 .hook
= quirk_invert_brightness
,
12787 static struct intel_quirk intel_quirks
[] = {
12788 /* HP Mini needs pipe A force quirk (LP: #322104) */
12789 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12791 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12792 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12794 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12795 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12797 /* 830 needs to leave pipe A & dpll A up */
12798 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
12800 /* 830 needs to leave pipe B & dpll B up */
12801 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
12803 /* Lenovo U160 cannot use SSC on LVDS */
12804 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12806 /* Sony Vaio Y cannot use SSC on LVDS */
12807 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12809 /* Acer Aspire 5734Z must invert backlight brightness */
12810 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12812 /* Acer/eMachines G725 */
12813 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12815 /* Acer/eMachines e725 */
12816 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12818 /* Acer/Packard Bell NCL20 */
12819 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12821 /* Acer Aspire 4736Z */
12822 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12824 /* Acer Aspire 5336 */
12825 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12827 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12828 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12830 /* Acer C720 Chromebook (Core i3 4005U) */
12831 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
12833 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12834 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12836 /* HP Chromebook 14 (Celeron 2955U) */
12837 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12840 static void intel_init_quirks(struct drm_device
*dev
)
12842 struct pci_dev
*d
= dev
->pdev
;
12845 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12846 struct intel_quirk
*q
= &intel_quirks
[i
];
12848 if (d
->device
== q
->device
&&
12849 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12850 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12851 (d
->subsystem_device
== q
->subsystem_device
||
12852 q
->subsystem_device
== PCI_ANY_ID
))
12855 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12856 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12857 intel_dmi_quirks
[i
].hook(dev
);
12861 /* Disable the VGA plane that we never use */
12862 static void i915_disable_vga(struct drm_device
*dev
)
12864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12866 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12868 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12869 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12870 outb(SR01
, VGA_SR_INDEX
);
12871 sr1
= inb(VGA_SR_DATA
);
12872 outb(sr1
| 1<<5, VGA_SR_DATA
);
12873 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12877 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12878 * from S3 without preserving (some of?) the other bits.
12880 I915_WRITE(vga_reg
, dev_priv
->bios_vgacntr
| VGA_DISP_DISABLE
);
12881 POSTING_READ(vga_reg
);
12884 void intel_modeset_init_hw(struct drm_device
*dev
)
12886 intel_prepare_ddi(dev
);
12888 if (IS_VALLEYVIEW(dev
))
12889 vlv_update_cdclk(dev
);
12891 intel_init_clock_gating(dev
);
12893 intel_enable_gt_powersave(dev
);
12896 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12898 intel_suspend_hw(dev
);
12901 void intel_modeset_init(struct drm_device
*dev
)
12903 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12906 struct intel_crtc
*crtc
;
12908 drm_mode_config_init(dev
);
12910 dev
->mode_config
.min_width
= 0;
12911 dev
->mode_config
.min_height
= 0;
12913 dev
->mode_config
.preferred_depth
= 24;
12914 dev
->mode_config
.prefer_shadow
= 1;
12916 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12918 intel_init_quirks(dev
);
12920 intel_init_pm(dev
);
12922 if (INTEL_INFO(dev
)->num_pipes
== 0)
12925 intel_init_display(dev
);
12927 if (IS_GEN2(dev
)) {
12928 dev
->mode_config
.max_width
= 2048;
12929 dev
->mode_config
.max_height
= 2048;
12930 } else if (IS_GEN3(dev
)) {
12931 dev
->mode_config
.max_width
= 4096;
12932 dev
->mode_config
.max_height
= 4096;
12934 dev
->mode_config
.max_width
= 8192;
12935 dev
->mode_config
.max_height
= 8192;
12938 if (IS_845G(dev
) || IS_I865G(dev
)) {
12939 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
12940 dev
->mode_config
.cursor_height
= 1023;
12941 } else if (IS_GEN2(dev
)) {
12942 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12943 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12945 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12946 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12949 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12951 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12952 INTEL_INFO(dev
)->num_pipes
,
12953 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12955 for_each_pipe(dev_priv
, pipe
) {
12956 intel_crtc_init(dev
, pipe
);
12957 for_each_sprite(pipe
, sprite
) {
12958 ret
= intel_plane_init(dev
, pipe
, sprite
);
12960 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12961 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12965 intel_init_dpio(dev
);
12967 intel_shared_dpll_init(dev
);
12969 /* save the BIOS value before clobbering it */
12970 dev_priv
->bios_vgacntr
= I915_READ(i915_vgacntrl_reg(dev
));
12971 /* Just disable it once at startup */
12972 i915_disable_vga(dev
);
12973 intel_setup_outputs(dev
);
12975 /* Just in case the BIOS is doing something questionable. */
12976 intel_disable_fbc(dev
);
12978 drm_modeset_lock_all(dev
);
12979 intel_modeset_setup_hw_state(dev
, false);
12980 drm_modeset_unlock_all(dev
);
12982 for_each_intel_crtc(dev
, crtc
) {
12987 * Note that reserving the BIOS fb up front prevents us
12988 * from stuffing other stolen allocations like the ring
12989 * on top. This prevents some ugliness at boot time, and
12990 * can even allow for smooth boot transitions if the BIOS
12991 * fb is large enough for the active pipe configuration.
12993 if (dev_priv
->display
.get_plane_config
) {
12994 dev_priv
->display
.get_plane_config(crtc
,
12995 &crtc
->plane_config
);
12997 * If the fb is shared between multiple heads, we'll
12998 * just get the first one.
13000 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
13005 static void intel_enable_pipe_a(struct drm_device
*dev
)
13007 struct intel_connector
*connector
;
13008 struct drm_connector
*crt
= NULL
;
13009 struct intel_load_detect_pipe load_detect_temp
;
13010 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13012 /* We can't just switch on the pipe A, we need to set things up with a
13013 * proper mode and output configuration. As a gross hack, enable pipe A
13014 * by enabling the load detect pipe once. */
13015 list_for_each_entry(connector
,
13016 &dev
->mode_config
.connector_list
,
13018 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13019 crt
= &connector
->base
;
13027 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
13028 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
13032 intel_check_plane_mapping(struct intel_crtc
*crtc
)
13034 struct drm_device
*dev
= crtc
->base
.dev
;
13035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13038 if (INTEL_INFO(dev
)->num_pipes
== 1)
13041 reg
= DSPCNTR(!crtc
->plane
);
13042 val
= I915_READ(reg
);
13044 if ((val
& DISPLAY_PLANE_ENABLE
) &&
13045 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
13051 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
13053 struct drm_device
*dev
= crtc
->base
.dev
;
13054 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13057 /* Clear any frame start delays used for debugging left by the BIOS */
13058 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
13059 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
13061 /* restore vblank interrupts to correct state */
13062 if (crtc
->active
) {
13063 update_scanline_offset(crtc
);
13064 drm_vblank_on(dev
, crtc
->pipe
);
13066 drm_vblank_off(dev
, crtc
->pipe
);
13068 /* We need to sanitize the plane -> pipe mapping first because this will
13069 * disable the crtc (and hence change the state) if it is wrong. Note
13070 * that gen4+ has a fixed plane -> pipe mapping. */
13071 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
13072 struct intel_connector
*connector
;
13075 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13076 crtc
->base
.base
.id
);
13078 /* Pipe has the wrong plane attached and the plane is active.
13079 * Temporarily change the plane mapping and disable everything
13081 plane
= crtc
->plane
;
13082 crtc
->plane
= !plane
;
13083 crtc
->primary_enabled
= true;
13084 dev_priv
->display
.crtc_disable(&crtc
->base
);
13085 crtc
->plane
= plane
;
13087 /* ... and break all links. */
13088 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13090 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
13093 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13094 connector
->base
.encoder
= NULL
;
13096 /* multiple connectors may have the same encoder:
13097 * handle them and break crtc link separately */
13098 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13100 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
13101 connector
->encoder
->base
.crtc
= NULL
;
13102 connector
->encoder
->connectors_active
= false;
13105 WARN_ON(crtc
->active
);
13106 crtc
->base
.enabled
= false;
13109 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
13110 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
13111 /* BIOS forgot to enable pipe A, this mostly happens after
13112 * resume. Force-enable the pipe to fix this, the update_dpms
13113 * call below we restore the pipe to the right state, but leave
13114 * the required bits on. */
13115 intel_enable_pipe_a(dev
);
13118 /* Adjust the state of the output pipe according to whether we
13119 * have active connectors/encoders. */
13120 intel_crtc_update_dpms(&crtc
->base
);
13122 if (crtc
->active
!= crtc
->base
.enabled
) {
13123 struct intel_encoder
*encoder
;
13125 /* This can happen either due to bugs in the get_hw_state
13126 * functions or because the pipe is force-enabled due to the
13128 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13129 crtc
->base
.base
.id
,
13130 crtc
->base
.enabled
? "enabled" : "disabled",
13131 crtc
->active
? "enabled" : "disabled");
13133 crtc
->base
.enabled
= crtc
->active
;
13135 /* Because we only establish the connector -> encoder ->
13136 * crtc links if something is active, this means the
13137 * crtc is now deactivated. Break the links. connector
13138 * -> encoder links are only establish when things are
13139 * actually up, hence no need to break them. */
13140 WARN_ON(crtc
->active
);
13142 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
13143 WARN_ON(encoder
->connectors_active
);
13144 encoder
->base
.crtc
= NULL
;
13148 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
13150 * We start out with underrun reporting disabled to avoid races.
13151 * For correct bookkeeping mark this on active crtcs.
13153 * Also on gmch platforms we dont have any hardware bits to
13154 * disable the underrun reporting. Which means we need to start
13155 * out with underrun reporting disabled also on inactive pipes,
13156 * since otherwise we'll complain about the garbage we read when
13157 * e.g. coming up after runtime pm.
13159 * No protection against concurrent access is required - at
13160 * worst a fifo underrun happens which also sets this to false.
13162 crtc
->cpu_fifo_underrun_disabled
= true;
13163 crtc
->pch_fifo_underrun_disabled
= true;
13167 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
13169 struct intel_connector
*connector
;
13170 struct drm_device
*dev
= encoder
->base
.dev
;
13172 /* We need to check both for a crtc link (meaning that the
13173 * encoder is active and trying to read from a pipe) and the
13174 * pipe itself being active. */
13175 bool has_active_crtc
= encoder
->base
.crtc
&&
13176 to_intel_crtc(encoder
->base
.crtc
)->active
;
13178 if (encoder
->connectors_active
&& !has_active_crtc
) {
13179 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13180 encoder
->base
.base
.id
,
13181 encoder
->base
.name
);
13183 /* Connector is active, but has no active pipe. This is
13184 * fallout from our resume register restoring. Disable
13185 * the encoder manually again. */
13186 if (encoder
->base
.crtc
) {
13187 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13188 encoder
->base
.base
.id
,
13189 encoder
->base
.name
);
13190 encoder
->disable(encoder
);
13191 if (encoder
->post_disable
)
13192 encoder
->post_disable(encoder
);
13194 encoder
->base
.crtc
= NULL
;
13195 encoder
->connectors_active
= false;
13197 /* Inconsistent output/port/pipe state happens presumably due to
13198 * a bug in one of the get_hw_state functions. Or someplace else
13199 * in our code, like the register restore mess on resume. Clamp
13200 * things to off as a safer default. */
13201 list_for_each_entry(connector
,
13202 &dev
->mode_config
.connector_list
,
13204 if (connector
->encoder
!= encoder
)
13206 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13207 connector
->base
.encoder
= NULL
;
13210 /* Enabled encoders without active connectors will be fixed in
13211 * the crtc fixup. */
13214 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13217 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13219 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13220 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13221 i915_disable_vga(dev
);
13225 void i915_redisable_vga(struct drm_device
*dev
)
13227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13229 /* This function can be called both from intel_modeset_setup_hw_state or
13230 * at a very early point in our resume sequence, where the power well
13231 * structures are not yet restored. Since this function is at a very
13232 * paranoid "someone might have enabled VGA while we were not looking"
13233 * level, just check if the power well is enabled instead of trying to
13234 * follow the "don't touch the power well if we don't need it" policy
13235 * the rest of the driver uses. */
13236 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13239 i915_redisable_vga_power_on(dev
);
13242 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13244 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13249 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13252 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13256 struct intel_crtc
*crtc
;
13257 struct intel_encoder
*encoder
;
13258 struct intel_connector
*connector
;
13261 for_each_intel_crtc(dev
, crtc
) {
13262 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13264 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13266 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13269 crtc
->base
.enabled
= crtc
->active
;
13270 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13272 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13273 crtc
->base
.base
.id
,
13274 crtc
->active
? "enabled" : "disabled");
13277 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13278 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13280 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
13282 for_each_intel_crtc(dev
, crtc
) {
13283 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
13286 pll
->refcount
= pll
->active
;
13288 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13289 pll
->name
, pll
->refcount
, pll
->on
);
13292 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13295 for_each_intel_encoder(dev
, encoder
) {
13298 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13299 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13300 encoder
->base
.crtc
= &crtc
->base
;
13301 encoder
->get_config(encoder
, &crtc
->config
);
13303 encoder
->base
.crtc
= NULL
;
13306 encoder
->connectors_active
= false;
13307 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13308 encoder
->base
.base
.id
,
13309 encoder
->base
.name
,
13310 encoder
->base
.crtc
? "enabled" : "disabled",
13314 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13316 if (connector
->get_hw_state(connector
)) {
13317 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13318 connector
->encoder
->connectors_active
= true;
13319 connector
->base
.encoder
= &connector
->encoder
->base
;
13321 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13322 connector
->base
.encoder
= NULL
;
13324 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13325 connector
->base
.base
.id
,
13326 connector
->base
.name
,
13327 connector
->base
.encoder
? "enabled" : "disabled");
13331 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13332 * and i915 state tracking structures. */
13333 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13334 bool force_restore
)
13336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13338 struct intel_crtc
*crtc
;
13339 struct intel_encoder
*encoder
;
13342 intel_modeset_readout_hw_state(dev
);
13345 * Now that we have the config, copy it to each CRTC struct
13346 * Note that this could go away if we move to using crtc_config
13347 * checking everywhere.
13349 for_each_intel_crtc(dev
, crtc
) {
13350 if (crtc
->active
&& i915
.fastboot
) {
13351 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13352 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13353 crtc
->base
.base
.id
);
13354 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13358 /* HW state is read out, now we need to sanitize this mess. */
13359 for_each_intel_encoder(dev
, encoder
) {
13360 intel_sanitize_encoder(encoder
);
13363 for_each_pipe(dev_priv
, pipe
) {
13364 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13365 intel_sanitize_crtc(crtc
);
13366 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13369 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13370 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13372 if (!pll
->on
|| pll
->active
)
13375 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13377 pll
->disable(dev_priv
, pll
);
13381 if (HAS_PCH_SPLIT(dev
))
13382 ilk_wm_get_hw_state(dev
);
13384 if (force_restore
) {
13385 i915_redisable_vga(dev
);
13388 * We need to use raw interfaces for restoring state to avoid
13389 * checking (bogus) intermediate states.
13391 for_each_pipe(dev_priv
, pipe
) {
13392 struct drm_crtc
*crtc
=
13393 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13395 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13396 crtc
->primary
->fb
);
13399 intel_modeset_update_staged_output_state(dev
);
13402 intel_modeset_check_state(dev
);
13405 void intel_modeset_gem_init(struct drm_device
*dev
)
13407 struct drm_crtc
*c
;
13408 struct drm_i915_gem_object
*obj
;
13410 mutex_lock(&dev
->struct_mutex
);
13411 intel_init_gt_powersave(dev
);
13412 mutex_unlock(&dev
->struct_mutex
);
13414 intel_modeset_init_hw(dev
);
13416 intel_setup_overlay(dev
);
13419 * Make sure any fbs we allocated at startup are properly
13420 * pinned & fenced. When we do the allocation it's too early
13423 mutex_lock(&dev
->struct_mutex
);
13424 for_each_crtc(dev
, c
) {
13425 obj
= intel_fb_obj(c
->primary
->fb
);
13429 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13430 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13431 to_intel_crtc(c
)->pipe
);
13432 drm_framebuffer_unreference(c
->primary
->fb
);
13433 c
->primary
->fb
= NULL
;
13436 mutex_unlock(&dev
->struct_mutex
);
13439 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13441 struct drm_connector
*connector
= &intel_connector
->base
;
13443 intel_panel_destroy_backlight(connector
);
13444 drm_connector_unregister(connector
);
13447 void intel_modeset_cleanup(struct drm_device
*dev
)
13449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13450 struct drm_connector
*connector
;
13453 * Interrupts and polling as the first thing to avoid creating havoc.
13454 * Too much stuff here (turning of rps, connectors, ...) would
13455 * experience fancy races otherwise.
13457 drm_irq_uninstall(dev
);
13458 intel_hpd_cancel_work(dev_priv
);
13459 dev_priv
->pm
._irqs_disabled
= true;
13462 * Due to the hpd irq storm handling the hotplug work can re-arm the
13463 * poll handlers. Hence disable polling after hpd handling is shut down.
13465 drm_kms_helper_poll_fini(dev
);
13467 mutex_lock(&dev
->struct_mutex
);
13469 intel_unregister_dsm_handler();
13471 intel_disable_fbc(dev
);
13473 intel_disable_gt_powersave(dev
);
13475 ironlake_teardown_rc6(dev
);
13477 mutex_unlock(&dev
->struct_mutex
);
13479 /* flush any delayed tasks or pending work */
13480 flush_scheduled_work();
13482 /* destroy the backlight and sysfs files before encoders/connectors */
13483 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13484 struct intel_connector
*intel_connector
;
13486 intel_connector
= to_intel_connector(connector
);
13487 intel_connector
->unregister(intel_connector
);
13490 drm_mode_config_cleanup(dev
);
13492 intel_cleanup_overlay(dev
);
13494 mutex_lock(&dev
->struct_mutex
);
13495 intel_cleanup_gt_powersave(dev
);
13496 mutex_unlock(&dev
->struct_mutex
);
13500 * Return which encoder is currently attached for connector.
13502 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13504 return &intel_attached_encoder(connector
)->base
;
13507 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13508 struct intel_encoder
*encoder
)
13510 connector
->encoder
= encoder
;
13511 drm_mode_connector_attach_encoder(&connector
->base
,
13516 * set vga decode state - true == enable VGA decode
13518 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13521 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13524 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13525 DRM_ERROR("failed to read control word\n");
13529 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13533 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13535 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13537 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13538 DRM_ERROR("failed to write control word\n");
13545 struct intel_display_error_state
{
13547 u32 power_well_driver
;
13549 int num_transcoders
;
13551 struct intel_cursor_error_state
{
13556 } cursor
[I915_MAX_PIPES
];
13558 struct intel_pipe_error_state
{
13559 bool power_domain_on
;
13562 } pipe
[I915_MAX_PIPES
];
13564 struct intel_plane_error_state
{
13572 } plane
[I915_MAX_PIPES
];
13574 struct intel_transcoder_error_state
{
13575 bool power_domain_on
;
13576 enum transcoder cpu_transcoder
;
13589 struct intel_display_error_state
*
13590 intel_display_capture_error_state(struct drm_device
*dev
)
13592 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13593 struct intel_display_error_state
*error
;
13594 int transcoders
[] = {
13602 if (INTEL_INFO(dev
)->num_pipes
== 0)
13605 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13609 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13610 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13612 for_each_pipe(dev_priv
, i
) {
13613 error
->pipe
[i
].power_domain_on
=
13614 intel_display_power_enabled_unlocked(dev_priv
,
13615 POWER_DOMAIN_PIPE(i
));
13616 if (!error
->pipe
[i
].power_domain_on
)
13619 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13620 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13621 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13623 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13624 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13625 if (INTEL_INFO(dev
)->gen
<= 3) {
13626 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13627 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13629 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13630 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13631 if (INTEL_INFO(dev
)->gen
>= 4) {
13632 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13633 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13636 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13638 if (HAS_GMCH_DISPLAY(dev
))
13639 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13642 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13643 if (HAS_DDI(dev_priv
->dev
))
13644 error
->num_transcoders
++; /* Account for eDP. */
13646 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13647 enum transcoder cpu_transcoder
= transcoders
[i
];
13649 error
->transcoder
[i
].power_domain_on
=
13650 intel_display_power_enabled_unlocked(dev_priv
,
13651 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13652 if (!error
->transcoder
[i
].power_domain_on
)
13655 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13657 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13658 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13659 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13660 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13661 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13662 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13663 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13669 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13672 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13673 struct drm_device
*dev
,
13674 struct intel_display_error_state
*error
)
13676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13682 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13683 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13684 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13685 error
->power_well_driver
);
13686 for_each_pipe(dev_priv
, i
) {
13687 err_printf(m
, "Pipe [%d]:\n", i
);
13688 err_printf(m
, " Power: %s\n",
13689 error
->pipe
[i
].power_domain_on
? "on" : "off");
13690 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13691 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13693 err_printf(m
, "Plane [%d]:\n", i
);
13694 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13695 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13696 if (INTEL_INFO(dev
)->gen
<= 3) {
13697 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13698 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13700 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13701 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13702 if (INTEL_INFO(dev
)->gen
>= 4) {
13703 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13704 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13707 err_printf(m
, "Cursor [%d]:\n", i
);
13708 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13709 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13710 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13713 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13714 err_printf(m
, "CPU transcoder: %c\n",
13715 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13716 err_printf(m
, " Power: %s\n",
13717 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13718 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13719 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13720 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13721 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13722 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13723 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13724 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13728 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13730 struct intel_crtc
*crtc
;
13732 for_each_intel_crtc(dev
, crtc
) {
13733 struct intel_unpin_work
*work
;
13734 unsigned long irqflags
;
13736 spin_lock_irqsave(&dev
->event_lock
, irqflags
);
13738 work
= crtc
->unpin_work
;
13740 if (work
&& work
->event
&&
13741 work
->event
->base
.file_priv
== file
) {
13742 kfree(work
->event
);
13743 work
->event
= NULL
;
13746 spin_unlock_irqrestore(&dev
->event_lock
, irqflags
);