2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/cpufreq.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_update_watermarks(struct drm_device
*dev
);
48 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
49 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
72 #define INTEL_P2_NUM 2
73 typedef struct intel_limit intel_limit_t
;
75 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
77 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
78 int, int, intel_clock_t
*, intel_clock_t
*);
82 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
85 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
86 int target
, int refclk
, intel_clock_t
*match_clock
,
87 intel_clock_t
*best_clock
);
89 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
90 int target
, int refclk
, intel_clock_t
*match_clock
,
91 intel_clock_t
*best_clock
);
94 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
95 int target
, int refclk
, intel_clock_t
*match_clock
,
96 intel_clock_t
*best_clock
);
98 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
99 int target
, int refclk
, intel_clock_t
*match_clock
,
100 intel_clock_t
*best_clock
);
102 static inline u32
/* units of 100MHz */
103 intel_fdi_link_freq(struct drm_device
*dev
)
106 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
107 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
112 static const intel_limit_t intel_limits_i8xx_dvo
= {
113 .dot
= { .min
= 25000, .max
= 350000 },
114 .vco
= { .min
= 930000, .max
= 1400000 },
115 .n
= { .min
= 3, .max
= 16 },
116 .m
= { .min
= 96, .max
= 140 },
117 .m1
= { .min
= 18, .max
= 26 },
118 .m2
= { .min
= 6, .max
= 16 },
119 .p
= { .min
= 4, .max
= 128 },
120 .p1
= { .min
= 2, .max
= 33 },
121 .p2
= { .dot_limit
= 165000,
122 .p2_slow
= 4, .p2_fast
= 2 },
123 .find_pll
= intel_find_best_PLL
,
126 static const intel_limit_t intel_limits_i8xx_lvds
= {
127 .dot
= { .min
= 25000, .max
= 350000 },
128 .vco
= { .min
= 930000, .max
= 1400000 },
129 .n
= { .min
= 3, .max
= 16 },
130 .m
= { .min
= 96, .max
= 140 },
131 .m1
= { .min
= 18, .max
= 26 },
132 .m2
= { .min
= 6, .max
= 16 },
133 .p
= { .min
= 4, .max
= 128 },
134 .p1
= { .min
= 1, .max
= 6 },
135 .p2
= { .dot_limit
= 165000,
136 .p2_slow
= 14, .p2_fast
= 7 },
137 .find_pll
= intel_find_best_PLL
,
140 static const intel_limit_t intel_limits_i9xx_sdvo
= {
141 .dot
= { .min
= 20000, .max
= 400000 },
142 .vco
= { .min
= 1400000, .max
= 2800000 },
143 .n
= { .min
= 1, .max
= 6 },
144 .m
= { .min
= 70, .max
= 120 },
145 .m1
= { .min
= 10, .max
= 22 },
146 .m2
= { .min
= 5, .max
= 9 },
147 .p
= { .min
= 5, .max
= 80 },
148 .p1
= { .min
= 1, .max
= 8 },
149 .p2
= { .dot_limit
= 200000,
150 .p2_slow
= 10, .p2_fast
= 5 },
151 .find_pll
= intel_find_best_PLL
,
154 static const intel_limit_t intel_limits_i9xx_lvds
= {
155 .dot
= { .min
= 20000, .max
= 400000 },
156 .vco
= { .min
= 1400000, .max
= 2800000 },
157 .n
= { .min
= 1, .max
= 6 },
158 .m
= { .min
= 70, .max
= 120 },
159 .m1
= { .min
= 10, .max
= 22 },
160 .m2
= { .min
= 5, .max
= 9 },
161 .p
= { .min
= 7, .max
= 98 },
162 .p1
= { .min
= 1, .max
= 8 },
163 .p2
= { .dot_limit
= 112000,
164 .p2_slow
= 14, .p2_fast
= 7 },
165 .find_pll
= intel_find_best_PLL
,
169 static const intel_limit_t intel_limits_g4x_sdvo
= {
170 .dot
= { .min
= 25000, .max
= 270000 },
171 .vco
= { .min
= 1750000, .max
= 3500000},
172 .n
= { .min
= 1, .max
= 4 },
173 .m
= { .min
= 104, .max
= 138 },
174 .m1
= { .min
= 17, .max
= 23 },
175 .m2
= { .min
= 5, .max
= 11 },
176 .p
= { .min
= 10, .max
= 30 },
177 .p1
= { .min
= 1, .max
= 3},
178 .p2
= { .dot_limit
= 270000,
182 .find_pll
= intel_g4x_find_best_PLL
,
185 static const intel_limit_t intel_limits_g4x_hdmi
= {
186 .dot
= { .min
= 22000, .max
= 400000 },
187 .vco
= { .min
= 1750000, .max
= 3500000},
188 .n
= { .min
= 1, .max
= 4 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 16, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 5, .max
= 80 },
193 .p1
= { .min
= 1, .max
= 8},
194 .p2
= { .dot_limit
= 165000,
195 .p2_slow
= 10, .p2_fast
= 5 },
196 .find_pll
= intel_g4x_find_best_PLL
,
199 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
200 .dot
= { .min
= 20000, .max
= 115000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 28, .max
= 112 },
207 .p1
= { .min
= 2, .max
= 8 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 14, .p2_fast
= 14
211 .find_pll
= intel_g4x_find_best_PLL
,
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
215 .dot
= { .min
= 80000, .max
= 224000 },
216 .vco
= { .min
= 1750000, .max
= 3500000 },
217 .n
= { .min
= 1, .max
= 3 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 14, .max
= 42 },
222 .p1
= { .min
= 2, .max
= 6 },
223 .p2
= { .dot_limit
= 0,
224 .p2_slow
= 7, .p2_fast
= 7
226 .find_pll
= intel_g4x_find_best_PLL
,
229 static const intel_limit_t intel_limits_g4x_display_port
= {
230 .dot
= { .min
= 161670, .max
= 227000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 2 },
233 .m
= { .min
= 97, .max
= 108 },
234 .m1
= { .min
= 0x10, .max
= 0x12 },
235 .m2
= { .min
= 0x05, .max
= 0x06 },
236 .p
= { .min
= 10, .max
= 20 },
237 .p1
= { .min
= 1, .max
= 2},
238 .p2
= { .dot_limit
= 0,
239 .p2_slow
= 10, .p2_fast
= 10 },
240 .find_pll
= intel_find_pll_g4x_dp
,
243 static const intel_limit_t intel_limits_pineview_sdvo
= {
244 .dot
= { .min
= 20000, .max
= 400000},
245 .vco
= { .min
= 1700000, .max
= 3500000 },
246 /* Pineview's Ncounter is a ring counter */
247 .n
= { .min
= 3, .max
= 6 },
248 .m
= { .min
= 2, .max
= 256 },
249 /* Pineview only has one combined m divider, which we treat as m2. */
250 .m1
= { .min
= 0, .max
= 0 },
251 .m2
= { .min
= 0, .max
= 254 },
252 .p
= { .min
= 5, .max
= 80 },
253 .p1
= { .min
= 1, .max
= 8 },
254 .p2
= { .dot_limit
= 200000,
255 .p2_slow
= 10, .p2_fast
= 5 },
256 .find_pll
= intel_find_best_PLL
,
259 static const intel_limit_t intel_limits_pineview_lvds
= {
260 .dot
= { .min
= 20000, .max
= 400000 },
261 .vco
= { .min
= 1700000, .max
= 3500000 },
262 .n
= { .min
= 3, .max
= 6 },
263 .m
= { .min
= 2, .max
= 256 },
264 .m1
= { .min
= 0, .max
= 0 },
265 .m2
= { .min
= 0, .max
= 254 },
266 .p
= { .min
= 7, .max
= 112 },
267 .p1
= { .min
= 1, .max
= 8 },
268 .p2
= { .dot_limit
= 112000,
269 .p2_slow
= 14, .p2_fast
= 14 },
270 .find_pll
= intel_find_best_PLL
,
273 /* Ironlake / Sandybridge
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
278 static const intel_limit_t intel_limits_ironlake_dac
= {
279 .dot
= { .min
= 25000, .max
= 350000 },
280 .vco
= { .min
= 1760000, .max
= 3510000 },
281 .n
= { .min
= 1, .max
= 5 },
282 .m
= { .min
= 79, .max
= 127 },
283 .m1
= { .min
= 12, .max
= 22 },
284 .m2
= { .min
= 5, .max
= 9 },
285 .p
= { .min
= 5, .max
= 80 },
286 .p1
= { .min
= 1, .max
= 8 },
287 .p2
= { .dot_limit
= 225000,
288 .p2_slow
= 10, .p2_fast
= 5 },
289 .find_pll
= intel_g4x_find_best_PLL
,
292 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
293 .dot
= { .min
= 25000, .max
= 350000 },
294 .vco
= { .min
= 1760000, .max
= 3510000 },
295 .n
= { .min
= 1, .max
= 3 },
296 .m
= { .min
= 79, .max
= 118 },
297 .m1
= { .min
= 12, .max
= 22 },
298 .m2
= { .min
= 5, .max
= 9 },
299 .p
= { .min
= 28, .max
= 112 },
300 .p1
= { .min
= 2, .max
= 8 },
301 .p2
= { .dot_limit
= 225000,
302 .p2_slow
= 14, .p2_fast
= 14 },
303 .find_pll
= intel_g4x_find_best_PLL
,
306 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
307 .dot
= { .min
= 25000, .max
= 350000 },
308 .vco
= { .min
= 1760000, .max
= 3510000 },
309 .n
= { .min
= 1, .max
= 3 },
310 .m
= { .min
= 79, .max
= 127 },
311 .m1
= { .min
= 12, .max
= 22 },
312 .m2
= { .min
= 5, .max
= 9 },
313 .p
= { .min
= 14, .max
= 56 },
314 .p1
= { .min
= 2, .max
= 8 },
315 .p2
= { .dot_limit
= 225000,
316 .p2_slow
= 7, .p2_fast
= 7 },
317 .find_pll
= intel_g4x_find_best_PLL
,
320 /* LVDS 100mhz refclk limits. */
321 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
322 .dot
= { .min
= 25000, .max
= 350000 },
323 .vco
= { .min
= 1760000, .max
= 3510000 },
324 .n
= { .min
= 1, .max
= 2 },
325 .m
= { .min
= 79, .max
= 126 },
326 .m1
= { .min
= 12, .max
= 22 },
327 .m2
= { .min
= 5, .max
= 9 },
328 .p
= { .min
= 28, .max
= 112 },
329 .p1
= { .min
= 2, .max
= 8 },
330 .p2
= { .dot_limit
= 225000,
331 .p2_slow
= 14, .p2_fast
= 14 },
332 .find_pll
= intel_g4x_find_best_PLL
,
335 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
336 .dot
= { .min
= 25000, .max
= 350000 },
337 .vco
= { .min
= 1760000, .max
= 3510000 },
338 .n
= { .min
= 1, .max
= 3 },
339 .m
= { .min
= 79, .max
= 126 },
340 .m1
= { .min
= 12, .max
= 22 },
341 .m2
= { .min
= 5, .max
= 9 },
342 .p
= { .min
= 14, .max
= 42 },
343 .p1
= { .min
= 2, .max
= 6 },
344 .p2
= { .dot_limit
= 225000,
345 .p2_slow
= 7, .p2_fast
= 7 },
346 .find_pll
= intel_g4x_find_best_PLL
,
349 static const intel_limit_t intel_limits_ironlake_display_port
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000},
352 .n
= { .min
= 1, .max
= 2 },
353 .m
= { .min
= 81, .max
= 90 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 10, .max
= 20 },
357 .p1
= { .min
= 1, .max
= 2},
358 .p2
= { .dot_limit
= 0,
359 .p2_slow
= 10, .p2_fast
= 10 },
360 .find_pll
= intel_find_pll_ironlake_dp
,
363 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
366 struct drm_device
*dev
= crtc
->dev
;
367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
368 const intel_limit_t
*limit
;
370 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
371 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
372 LVDS_CLKB_POWER_UP
) {
373 /* LVDS dual channel */
374 if (refclk
== 100000)
375 limit
= &intel_limits_ironlake_dual_lvds_100m
;
377 limit
= &intel_limits_ironlake_dual_lvds
;
379 if (refclk
== 100000)
380 limit
= &intel_limits_ironlake_single_lvds_100m
;
382 limit
= &intel_limits_ironlake_single_lvds
;
384 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
386 limit
= &intel_limits_ironlake_display_port
;
388 limit
= &intel_limits_ironlake_dac
;
393 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
395 struct drm_device
*dev
= crtc
->dev
;
396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
397 const intel_limit_t
*limit
;
399 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
400 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
402 /* LVDS with dual channel */
403 limit
= &intel_limits_g4x_dual_channel_lvds
;
405 /* LVDS with dual channel */
406 limit
= &intel_limits_g4x_single_channel_lvds
;
407 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
408 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
409 limit
= &intel_limits_g4x_hdmi
;
410 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
411 limit
= &intel_limits_g4x_sdvo
;
412 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
413 limit
= &intel_limits_g4x_display_port
;
414 } else /* The option is for other outputs */
415 limit
= &intel_limits_i9xx_sdvo
;
420 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
422 struct drm_device
*dev
= crtc
->dev
;
423 const intel_limit_t
*limit
;
425 if (HAS_PCH_SPLIT(dev
))
426 limit
= intel_ironlake_limit(crtc
, refclk
);
427 else if (IS_G4X(dev
)) {
428 limit
= intel_g4x_limit(crtc
);
429 } else if (IS_PINEVIEW(dev
)) {
430 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
431 limit
= &intel_limits_pineview_lvds
;
433 limit
= &intel_limits_pineview_sdvo
;
434 } else if (!IS_GEN2(dev
)) {
435 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
436 limit
= &intel_limits_i9xx_lvds
;
438 limit
= &intel_limits_i9xx_sdvo
;
440 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
441 limit
= &intel_limits_i8xx_lvds
;
443 limit
= &intel_limits_i8xx_dvo
;
448 /* m1 is reserved as 0 in Pineview, n is a ring counter */
449 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
451 clock
->m
= clock
->m2
+ 2;
452 clock
->p
= clock
->p1
* clock
->p2
;
453 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
454 clock
->dot
= clock
->vco
/ clock
->p
;
457 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
459 if (IS_PINEVIEW(dev
)) {
460 pineview_clock(refclk
, clock
);
463 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
464 clock
->p
= clock
->p1
* clock
->p2
;
465 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
466 clock
->dot
= clock
->vco
/ clock
->p
;
470 * Returns whether any output on the specified pipe is of the specified type
472 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
474 struct drm_device
*dev
= crtc
->dev
;
475 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
476 struct intel_encoder
*encoder
;
478 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
479 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
485 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
491 static bool intel_PLL_is_valid(struct drm_device
*dev
,
492 const intel_limit_t
*limit
,
493 const intel_clock_t
*clock
)
495 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
496 INTELPllInvalid("p1 out of range\n");
497 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
498 INTELPllInvalid("p out of range\n");
499 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
500 INTELPllInvalid("m2 out of range\n");
501 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
502 INTELPllInvalid("m1 out of range\n");
503 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
504 INTELPllInvalid("m1 <= m2\n");
505 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
506 INTELPllInvalid("m out of range\n");
507 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
508 INTELPllInvalid("n out of range\n");
509 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
510 INTELPllInvalid("vco out of range\n");
511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
514 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
515 INTELPllInvalid("dot out of range\n");
521 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
522 int target
, int refclk
, intel_clock_t
*match_clock
,
523 intel_clock_t
*best_clock
)
526 struct drm_device
*dev
= crtc
->dev
;
527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
531 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
532 (I915_READ(LVDS
)) != 0) {
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
539 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
541 clock
.p2
= limit
->p2
.p2_fast
;
543 clock
.p2
= limit
->p2
.p2_slow
;
545 if (target
< limit
->p2
.dot_limit
)
546 clock
.p2
= limit
->p2
.p2_slow
;
548 clock
.p2
= limit
->p2
.p2_fast
;
551 memset(best_clock
, 0, sizeof(*best_clock
));
553 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
555 for (clock
.m2
= limit
->m2
.min
;
556 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
557 /* m1 is always 0 in Pineview */
558 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
560 for (clock
.n
= limit
->n
.min
;
561 clock
.n
<= limit
->n
.max
; clock
.n
++) {
562 for (clock
.p1
= limit
->p1
.min
;
563 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
566 intel_clock(dev
, refclk
, &clock
);
567 if (!intel_PLL_is_valid(dev
, limit
,
571 clock
.p
!= match_clock
->p
)
574 this_err
= abs(clock
.dot
- target
);
575 if (this_err
< err
) {
584 return (err
!= target
);
588 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
589 int target
, int refclk
, intel_clock_t
*match_clock
,
590 intel_clock_t
*best_clock
)
592 struct drm_device
*dev
= crtc
->dev
;
593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
597 /* approximately equals target * 0.00585 */
598 int err_most
= (target
>> 8) + (target
>> 9);
601 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
604 if (HAS_PCH_SPLIT(dev
))
608 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
610 clock
.p2
= limit
->p2
.p2_fast
;
612 clock
.p2
= limit
->p2
.p2_slow
;
614 if (target
< limit
->p2
.dot_limit
)
615 clock
.p2
= limit
->p2
.p2_slow
;
617 clock
.p2
= limit
->p2
.p2_fast
;
620 memset(best_clock
, 0, sizeof(*best_clock
));
621 max_n
= limit
->n
.max
;
622 /* based on hardware requirement, prefer smaller n to precision */
623 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
624 /* based on hardware requirement, prefere larger m1,m2 */
625 for (clock
.m1
= limit
->m1
.max
;
626 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
627 for (clock
.m2
= limit
->m2
.max
;
628 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
629 for (clock
.p1
= limit
->p1
.max
;
630 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
633 intel_clock(dev
, refclk
, &clock
);
634 if (!intel_PLL_is_valid(dev
, limit
,
638 clock
.p
!= match_clock
->p
)
641 this_err
= abs(clock
.dot
- target
);
642 if (this_err
< err_most
) {
656 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
657 int target
, int refclk
, intel_clock_t
*match_clock
,
658 intel_clock_t
*best_clock
)
660 struct drm_device
*dev
= crtc
->dev
;
663 if (target
< 200000) {
676 intel_clock(dev
, refclk
, &clock
);
677 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
681 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
683 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
684 int target
, int refclk
, intel_clock_t
*match_clock
,
685 intel_clock_t
*best_clock
)
688 if (target
< 200000) {
701 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
702 clock
.p
= (clock
.p1
* clock
.p2
);
703 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
705 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
710 * intel_wait_for_vblank - wait for vblank on a given pipe
712 * @pipe: pipe to wait for
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
717 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
720 int pipestat_reg
= PIPESTAT(pipe
);
722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
735 I915_WRITE(pipestat_reg
,
736 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
738 /* Wait for vblank interrupt bit to set */
739 if (wait_for(I915_READ(pipestat_reg
) &
740 PIPE_VBLANK_INTERRUPT_STATUS
,
742 DRM_DEBUG_KMS("vblank wait timed out\n");
746 * intel_wait_for_pipe_off - wait for pipe to turn off
748 * @pipe: pipe to wait for
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
755 * wait for the pipe register state bit to turn off
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
762 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
764 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
766 if (INTEL_INFO(dev
)->gen
>= 4) {
767 int reg
= PIPECONF(pipe
);
769 /* Wait for the Pipe State to go off */
770 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
775 int reg
= PIPEDSL(pipe
);
776 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
778 /* Wait for the display line to settle */
780 last_line
= I915_READ(reg
) & DSL_LINEMASK
;
782 } while (((I915_READ(reg
) & DSL_LINEMASK
) != last_line
) &&
783 time_after(timeout
, jiffies
));
784 if (time_after(jiffies
, timeout
))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
789 static const char *state_string(bool enabled
)
791 return enabled
? "on" : "off";
794 /* Only for pre-ILK configs */
795 static void assert_pll(struct drm_i915_private
*dev_priv
,
796 enum pipe pipe
, bool state
)
803 val
= I915_READ(reg
);
804 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
805 WARN(cur_state
!= state
,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state
), state_string(cur_state
));
809 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
810 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
813 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
814 enum pipe pipe
, bool state
)
820 if (HAS_PCH_CPT(dev_priv
->dev
)) {
823 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll
>> (4 * pipe
)) & 8),
827 "transcoder %d PLL not enabled\n", pipe
);
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe
= (pch_dpll
>> (4 * pipe
)) & 1;
833 reg
= PCH_DPLL(pipe
);
834 val
= I915_READ(reg
);
835 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
836 WARN(cur_state
!= state
,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state
), state_string(cur_state
));
840 #define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841 #define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
843 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
844 enum pipe pipe
, bool state
)
850 reg
= FDI_TX_CTL(pipe
);
851 val
= I915_READ(reg
);
852 cur_state
= !!(val
& FDI_TX_ENABLE
);
853 WARN(cur_state
!= state
,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state
), state_string(cur_state
));
857 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
860 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
861 enum pipe pipe
, bool state
)
867 reg
= FDI_RX_CTL(pipe
);
868 val
= I915_READ(reg
);
869 cur_state
= !!(val
& FDI_RX_ENABLE
);
870 WARN(cur_state
!= state
,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state
), state_string(cur_state
));
874 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
877 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv
->info
->gen
== 5)
887 reg
= FDI_TX_CTL(pipe
);
888 val
= I915_READ(reg
);
889 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
892 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
898 reg
= FDI_RX_CTL(pipe
);
899 val
= I915_READ(reg
);
900 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
903 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
906 int pp_reg
, lvds_reg
;
908 enum pipe panel_pipe
= PIPE_A
;
911 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
912 pp_reg
= PCH_PP_CONTROL
;
919 val
= I915_READ(pp_reg
);
920 if (!(val
& PANEL_POWER_ON
) ||
921 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
924 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
927 WARN(panel_pipe
== pipe
&& locked
,
928 "panel assertion failure, pipe %c regs locked\n",
932 void assert_pipe(struct drm_i915_private
*dev_priv
,
933 enum pipe pipe
, bool state
)
939 /* if we need the pipe A quirk it must be always on */
940 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
943 reg
= PIPECONF(pipe
);
944 val
= I915_READ(reg
);
945 cur_state
= !!(val
& PIPECONF_ENABLE
);
946 WARN(cur_state
!= state
,
947 "pipe %c assertion failure (expected %s, current %s)\n",
948 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
951 static void assert_plane(struct drm_i915_private
*dev_priv
,
952 enum plane plane
, bool state
)
958 reg
= DSPCNTR(plane
);
959 val
= I915_READ(reg
);
960 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
961 WARN(cur_state
!= state
,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane
), state_string(state
), state_string(cur_state
));
966 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
967 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
969 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
976 /* Planes are fixed to pipes on ILK+ */
977 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
979 val
= I915_READ(reg
);
980 WARN((val
& DISPLAY_PLANE_ENABLE
),
981 "plane %c assertion failure, should be disabled but not\n",
986 /* Need to check both planes against the pipe */
987 for (i
= 0; i
< 2; i
++) {
989 val
= I915_READ(reg
);
990 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
991 DISPPLANE_SEL_PIPE_SHIFT
;
992 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i
), pipe_name(pipe
));
998 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1003 val
= I915_READ(PCH_DREF_CONTROL
);
1004 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1005 DREF_SUPERSPREAD_SOURCE_MASK
));
1006 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1009 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1016 reg
= TRANSCONF(pipe
);
1017 val
= I915_READ(reg
);
1018 enabled
= !!(val
& TRANS_ENABLE
);
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1024 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1025 enum pipe pipe
, u32 port_sel
, u32 val
)
1027 if ((val
& DP_PORT_EN
) == 0)
1030 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1031 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1032 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1033 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1036 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1042 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1043 enum pipe pipe
, u32 val
)
1045 if ((val
& PORT_ENABLE
) == 0)
1048 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1049 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1052 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1058 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1059 enum pipe pipe
, u32 val
)
1061 if ((val
& LVDS_PORT_EN
) == 0)
1064 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1065 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1068 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1074 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1075 enum pipe pipe
, u32 val
)
1077 if ((val
& ADPA_DAC_ENABLE
) == 0)
1079 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1080 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1083 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1089 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1090 enum pipe pipe
, int reg
, u32 port_sel
)
1092 u32 val
= I915_READ(reg
);
1093 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1095 reg
, pipe_name(pipe
));
1098 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1099 enum pipe pipe
, int reg
)
1101 u32 val
= I915_READ(reg
);
1102 WARN(hdmi_pipe_enabled(dev_priv
, val
, pipe
),
1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1104 reg
, pipe_name(pipe
));
1107 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1113 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1114 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1115 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1118 val
= I915_READ(reg
);
1119 WARN(adpa_pipe_enabled(dev_priv
, val
, pipe
),
1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
1124 val
= I915_READ(reg
);
1125 WARN(lvds_pipe_enabled(dev_priv
, val
, pipe
),
1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1129 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1130 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1131 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1143 * Note! This is for pre-ILK only.
1145 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv
->info
->gen
>= 5);
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1155 assert_panel_unlocked(dev_priv
, pipe
);
1158 val
= I915_READ(reg
);
1159 val
|= DPLL_VCO_ENABLE
;
1161 /* We do this three times for luck */
1162 I915_WRITE(reg
, val
);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg
, val
);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg
, val
);
1170 udelay(150); /* wait for warmup */
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1180 * Note! This is for pre-ILK only.
1182 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv
, pipe
);
1195 val
= I915_READ(reg
);
1196 val
&= ~DPLL_VCO_ENABLE
;
1197 I915_WRITE(reg
, val
);
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1209 static void intel_enable_pch_pll(struct drm_i915_private
*dev_priv
,
1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv
->info
->gen
< 5);
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv
);
1224 reg
= PCH_DPLL(pipe
);
1225 val
= I915_READ(reg
);
1226 val
|= DPLL_VCO_ENABLE
;
1227 I915_WRITE(reg
, val
);
1232 static void intel_disable_pch_pll(struct drm_i915_private
*dev_priv
,
1236 u32 val
, pll_mask
= TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
,
1237 pll_sel
= TRANSC_DPLL_ENABLE
;
1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv
->info
->gen
< 5);
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv
, pipe
);
1249 pll_sel
|= TRANSC_DPLLA_SEL
;
1251 pll_sel
|= TRANSC_DPLLB_SEL
;
1254 if ((I915_READ(PCH_DPLL_SEL
) & pll_mask
) == pll_sel
)
1257 reg
= PCH_DPLL(pipe
);
1258 val
= I915_READ(reg
);
1259 val
&= ~DPLL_VCO_ENABLE
;
1260 I915_WRITE(reg
, val
);
1265 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1269 u32 val
, pipeconf_val
;
1270 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1272 /* PCH only available on ILK+ */
1273 BUG_ON(dev_priv
->info
->gen
< 5);
1275 /* Make sure PCH DPLL is enabled */
1276 assert_pch_pll_enabled(dev_priv
, pipe
);
1278 /* FDI must be feeding us bits for PCH ports */
1279 assert_fdi_tx_enabled(dev_priv
, pipe
);
1280 assert_fdi_rx_enabled(dev_priv
, pipe
);
1282 reg
= TRANSCONF(pipe
);
1283 val
= I915_READ(reg
);
1284 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1286 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1288 * make the BPC in transcoder be consistent with
1289 * that in pipeconf reg.
1291 val
&= ~PIPE_BPC_MASK
;
1292 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1295 val
&= ~TRANS_INTERLACE_MASK
;
1296 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1297 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1298 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1299 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1301 val
|= TRANS_INTERLACED
;
1303 val
|= TRANS_PROGRESSIVE
;
1305 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1306 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1307 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1310 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1316 /* FDI relies on the transcoder */
1317 assert_fdi_tx_disabled(dev_priv
, pipe
);
1318 assert_fdi_rx_disabled(dev_priv
, pipe
);
1320 /* Ports must be off as well */
1321 assert_pch_ports_disabled(dev_priv
, pipe
);
1323 reg
= TRANSCONF(pipe
);
1324 val
= I915_READ(reg
);
1325 val
&= ~TRANS_ENABLE
;
1326 I915_WRITE(reg
, val
);
1327 /* wait for PCH transcoder off, transcoder state */
1328 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1329 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1333 * intel_enable_pipe - enable a pipe, asserting requirements
1334 * @dev_priv: i915 private structure
1335 * @pipe: pipe to enable
1336 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1338 * Enable @pipe, making sure that various hardware specific requirements
1339 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1341 * @pipe should be %PIPE_A or %PIPE_B.
1343 * Will wait until the pipe is actually running (i.e. first vblank) before
1346 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1353 * A pipe without a PLL won't actually be able to drive bits from
1354 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1357 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1358 assert_pll_enabled(dev_priv
, pipe
);
1361 /* if driving the PCH, we need FDI enabled */
1362 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1363 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1365 /* FIXME: assert CPU port conditions for SNB+ */
1368 reg
= PIPECONF(pipe
);
1369 val
= I915_READ(reg
);
1370 if (val
& PIPECONF_ENABLE
)
1373 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1374 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1378 * intel_disable_pipe - disable a pipe, asserting requirements
1379 * @dev_priv: i915 private structure
1380 * @pipe: pipe to disable
1382 * Disable @pipe, making sure that various hardware specific requirements
1383 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1385 * @pipe should be %PIPE_A or %PIPE_B.
1387 * Will wait until the pipe has shut down before returning.
1389 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1396 * Make sure planes won't keep trying to pump pixels to us,
1397 * or we might hang the display.
1399 assert_planes_disabled(dev_priv
, pipe
);
1401 /* Don't disable pipe A or pipe A PLLs if needed */
1402 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1405 reg
= PIPECONF(pipe
);
1406 val
= I915_READ(reg
);
1407 if ((val
& PIPECONF_ENABLE
) == 0)
1410 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1411 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1415 * Plane regs are double buffered, going from enabled->disabled needs a
1416 * trigger in order to latch. The display address reg provides this.
1418 static void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1421 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1422 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1426 * intel_enable_plane - enable a display plane on a given pipe
1427 * @dev_priv: i915 private structure
1428 * @plane: plane to enable
1429 * @pipe: pipe being fed
1431 * Enable @plane on @pipe, making sure that @pipe is running first.
1433 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1434 enum plane plane
, enum pipe pipe
)
1439 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1440 assert_pipe_enabled(dev_priv
, pipe
);
1442 reg
= DSPCNTR(plane
);
1443 val
= I915_READ(reg
);
1444 if (val
& DISPLAY_PLANE_ENABLE
)
1447 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1448 intel_flush_display_plane(dev_priv
, plane
);
1449 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1453 * intel_disable_plane - disable a display plane
1454 * @dev_priv: i915 private structure
1455 * @plane: plane to disable
1456 * @pipe: pipe consuming the data
1458 * Disable @plane; should be an independent operation.
1460 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1461 enum plane plane
, enum pipe pipe
)
1466 reg
= DSPCNTR(plane
);
1467 val
= I915_READ(reg
);
1468 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1471 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1472 intel_flush_display_plane(dev_priv
, plane
);
1473 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1476 static void disable_pch_dp(struct drm_i915_private
*dev_priv
,
1477 enum pipe pipe
, int reg
, u32 port_sel
)
1479 u32 val
= I915_READ(reg
);
1480 if (dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
)) {
1481 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg
, pipe
);
1482 I915_WRITE(reg
, val
& ~DP_PORT_EN
);
1486 static void disable_pch_hdmi(struct drm_i915_private
*dev_priv
,
1487 enum pipe pipe
, int reg
)
1489 u32 val
= I915_READ(reg
);
1490 if (hdmi_pipe_enabled(dev_priv
, val
, pipe
)) {
1491 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1493 I915_WRITE(reg
, val
& ~PORT_ENABLE
);
1497 /* Disable any ports connected to this transcoder */
1498 static void intel_disable_pch_ports(struct drm_i915_private
*dev_priv
,
1503 val
= I915_READ(PCH_PP_CONTROL
);
1504 I915_WRITE(PCH_PP_CONTROL
, val
| PANEL_UNLOCK_REGS
);
1506 disable_pch_dp(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1507 disable_pch_dp(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1508 disable_pch_dp(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1511 val
= I915_READ(reg
);
1512 if (adpa_pipe_enabled(dev_priv
, val
, pipe
))
1513 I915_WRITE(reg
, val
& ~ADPA_DAC_ENABLE
);
1516 val
= I915_READ(reg
);
1517 if (lvds_pipe_enabled(dev_priv
, val
, pipe
)) {
1518 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe
, val
);
1519 I915_WRITE(reg
, val
& ~LVDS_PORT_EN
);
1524 disable_pch_hdmi(dev_priv
, pipe
, HDMIB
);
1525 disable_pch_hdmi(dev_priv
, pipe
, HDMIC
);
1526 disable_pch_hdmi(dev_priv
, pipe
, HDMID
);
1529 static void i8xx_disable_fbc(struct drm_device
*dev
)
1531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1534 /* Disable compression */
1535 fbc_ctl
= I915_READ(FBC_CONTROL
);
1536 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
1539 fbc_ctl
&= ~FBC_CTL_EN
;
1540 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1542 /* Wait for compressing bit to clear */
1543 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
1544 DRM_DEBUG_KMS("FBC idle timed out\n");
1548 DRM_DEBUG_KMS("disabled FBC\n");
1551 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1553 struct drm_device
*dev
= crtc
->dev
;
1554 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1555 struct drm_framebuffer
*fb
= crtc
->fb
;
1556 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1557 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1558 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1561 u32 fbc_ctl
, fbc_ctl2
;
1563 cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1564 if (fb
->pitches
[0] < cfb_pitch
)
1565 cfb_pitch
= fb
->pitches
[0];
1567 /* FBC_CTL wants 64B units */
1568 cfb_pitch
= (cfb_pitch
/ 64) - 1;
1569 plane
= intel_crtc
->plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1571 /* Clear old tags */
1572 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1573 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1576 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
1578 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1579 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1582 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1584 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1585 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1586 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1587 fbc_ctl
|= obj
->fence_reg
;
1588 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1590 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1591 cfb_pitch
, crtc
->y
, intel_crtc
->plane
);
1594 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1596 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1598 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1601 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1603 struct drm_device
*dev
= crtc
->dev
;
1604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1605 struct drm_framebuffer
*fb
= crtc
->fb
;
1606 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1607 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1608 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1609 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1610 unsigned long stall_watermark
= 200;
1613 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1614 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
1615 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1617 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1618 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1619 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1620 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1623 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1625 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1628 static void g4x_disable_fbc(struct drm_device
*dev
)
1630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1633 /* Disable compression */
1634 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1635 if (dpfc_ctl
& DPFC_CTL_EN
) {
1636 dpfc_ctl
&= ~DPFC_CTL_EN
;
1637 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1639 DRM_DEBUG_KMS("disabled FBC\n");
1643 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1647 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1650 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
1652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1655 /* Make sure blitter notifies FBC of writes */
1656 gen6_gt_force_wake_get(dev_priv
);
1657 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
1658 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
1659 GEN6_BLITTER_LOCK_SHIFT
;
1660 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1661 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
1662 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1663 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
1664 GEN6_BLITTER_LOCK_SHIFT
);
1665 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
1666 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
1667 gen6_gt_force_wake_put(dev_priv
);
1670 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1672 struct drm_device
*dev
= crtc
->dev
;
1673 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1674 struct drm_framebuffer
*fb
= crtc
->fb
;
1675 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1676 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
1677 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1678 int plane
= intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
: DPFC_CTL_PLANEB
;
1679 unsigned long stall_watermark
= 200;
1682 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1683 dpfc_ctl
&= DPFC_RESERVED
;
1684 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1685 /* Set persistent mode for front-buffer rendering, ala X. */
1686 dpfc_ctl
|= DPFC_CTL_PERSISTENT_MODE
;
1687 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| obj
->fence_reg
);
1688 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1690 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1691 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1692 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1693 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1694 I915_WRITE(ILK_FBC_RT_BASE
, obj
->gtt_offset
| ILK_FBC_RT_VALID
);
1696 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
1699 I915_WRITE(SNB_DPFC_CTL_SA
,
1700 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
1701 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
1702 sandybridge_blit_fbc_update(dev
);
1705 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1708 static void ironlake_disable_fbc(struct drm_device
*dev
)
1710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1713 /* Disable compression */
1714 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1715 if (dpfc_ctl
& DPFC_CTL_EN
) {
1716 dpfc_ctl
&= ~DPFC_CTL_EN
;
1717 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1719 DRM_DEBUG_KMS("disabled FBC\n");
1723 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1727 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1730 bool intel_fbc_enabled(struct drm_device
*dev
)
1732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1734 if (!dev_priv
->display
.fbc_enabled
)
1737 return dev_priv
->display
.fbc_enabled(dev
);
1740 static void intel_fbc_work_fn(struct work_struct
*__work
)
1742 struct intel_fbc_work
*work
=
1743 container_of(to_delayed_work(__work
),
1744 struct intel_fbc_work
, work
);
1745 struct drm_device
*dev
= work
->crtc
->dev
;
1746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1748 mutex_lock(&dev
->struct_mutex
);
1749 if (work
== dev_priv
->fbc_work
) {
1750 /* Double check that we haven't switched fb without cancelling
1753 if (work
->crtc
->fb
== work
->fb
) {
1754 dev_priv
->display
.enable_fbc(work
->crtc
,
1757 dev_priv
->cfb_plane
= to_intel_crtc(work
->crtc
)->plane
;
1758 dev_priv
->cfb_fb
= work
->crtc
->fb
->base
.id
;
1759 dev_priv
->cfb_y
= work
->crtc
->y
;
1762 dev_priv
->fbc_work
= NULL
;
1764 mutex_unlock(&dev
->struct_mutex
);
1769 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
1771 if (dev_priv
->fbc_work
== NULL
)
1774 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1776 /* Synchronisation is provided by struct_mutex and checking of
1777 * dev_priv->fbc_work, so we can perform the cancellation
1778 * entirely asynchronously.
1780 if (cancel_delayed_work(&dev_priv
->fbc_work
->work
))
1781 /* tasklet was killed before being run, clean up */
1782 kfree(dev_priv
->fbc_work
);
1784 /* Mark the work as no longer wanted so that if it does
1785 * wake-up (because the work was already running and waiting
1786 * for our mutex), it will discover that is no longer
1789 dev_priv
->fbc_work
= NULL
;
1792 static void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1794 struct intel_fbc_work
*work
;
1795 struct drm_device
*dev
= crtc
->dev
;
1796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1798 if (!dev_priv
->display
.enable_fbc
)
1801 intel_cancel_fbc_work(dev_priv
);
1803 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
1805 dev_priv
->display
.enable_fbc(crtc
, interval
);
1810 work
->fb
= crtc
->fb
;
1811 work
->interval
= interval
;
1812 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
1814 dev_priv
->fbc_work
= work
;
1816 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1818 /* Delay the actual enabling to let pageflipping cease and the
1819 * display to settle before starting the compression. Note that
1820 * this delay also serves a second purpose: it allows for a
1821 * vblank to pass after disabling the FBC before we attempt
1822 * to modify the control registers.
1824 * A more complicated solution would involve tracking vblanks
1825 * following the termination of the page-flipping sequence
1826 * and indeed performing the enable as a co-routine and not
1827 * waiting synchronously upon the vblank.
1829 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
1832 void intel_disable_fbc(struct drm_device
*dev
)
1834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1836 intel_cancel_fbc_work(dev_priv
);
1838 if (!dev_priv
->display
.disable_fbc
)
1841 dev_priv
->display
.disable_fbc(dev
);
1842 dev_priv
->cfb_plane
= -1;
1846 * intel_update_fbc - enable/disable FBC as needed
1847 * @dev: the drm_device
1849 * Set up the framebuffer compression hardware at mode set time. We
1850 * enable it if possible:
1851 * - plane A only (on pre-965)
1852 * - no pixel mulitply/line duplication
1853 * - no alpha buffer discard
1855 * - framebuffer <= 2048 in width, 1536 in height
1857 * We can't assume that any compression will take place (worst case),
1858 * so the compressed buffer has to be the same size as the uncompressed
1859 * one. It also must reside (along with the line length buffer) in
1862 * We need to enable/disable FBC on a global basis.
1864 static void intel_update_fbc(struct drm_device
*dev
)
1866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1867 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
1868 struct intel_crtc
*intel_crtc
;
1869 struct drm_framebuffer
*fb
;
1870 struct intel_framebuffer
*intel_fb
;
1871 struct drm_i915_gem_object
*obj
;
1874 DRM_DEBUG_KMS("\n");
1876 if (!i915_powersave
)
1879 if (!I915_HAS_FBC(dev
))
1883 * If FBC is already on, we just have to verify that we can
1884 * keep it that way...
1885 * Need to disable if:
1886 * - more than one pipe is active
1887 * - changing FBC params (stride, fence, mode)
1888 * - new fb is too large to fit in compressed buffer
1889 * - going to an unsupported config (interlace, pixel multiply, etc.)
1891 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1892 if (tmp_crtc
->enabled
&& tmp_crtc
->fb
) {
1894 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1895 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
1902 if (!crtc
|| crtc
->fb
== NULL
) {
1903 DRM_DEBUG_KMS("no output, disabling\n");
1904 dev_priv
->no_fbc_reason
= FBC_NO_OUTPUT
;
1908 intel_crtc
= to_intel_crtc(crtc
);
1910 intel_fb
= to_intel_framebuffer(fb
);
1911 obj
= intel_fb
->obj
;
1913 enable_fbc
= i915_enable_fbc
;
1914 if (enable_fbc
< 0) {
1915 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1917 if (INTEL_INFO(dev
)->gen
<= 6)
1921 DRM_DEBUG_KMS("fbc disabled per module param\n");
1922 dev_priv
->no_fbc_reason
= FBC_MODULE_PARAM
;
1925 if (intel_fb
->obj
->base
.size
> dev_priv
->cfb_size
) {
1926 DRM_DEBUG_KMS("framebuffer too large, disabling "
1928 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1931 if ((crtc
->mode
.flags
& DRM_MODE_FLAG_INTERLACE
) ||
1932 (crtc
->mode
.flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1933 DRM_DEBUG_KMS("mode incompatible with compression, "
1935 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1938 if ((crtc
->mode
.hdisplay
> 2048) ||
1939 (crtc
->mode
.vdisplay
> 1536)) {
1940 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1941 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1944 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && intel_crtc
->plane
!= 0) {
1945 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1946 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1950 /* The use of a CPU fence is mandatory in order to detect writes
1951 * by the CPU to the scanout and trigger updates to the FBC.
1953 if (obj
->tiling_mode
!= I915_TILING_X
||
1954 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
1955 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
1956 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1960 /* If the kernel debugger is active, always disable compression */
1961 if (in_dbg_master())
1964 /* If the scanout has not changed, don't modify the FBC settings.
1965 * Note that we make the fundamental assumption that the fb->obj
1966 * cannot be unpinned (and have its GTT offset and fence revoked)
1967 * without first being decoupled from the scanout and FBC disabled.
1969 if (dev_priv
->cfb_plane
== intel_crtc
->plane
&&
1970 dev_priv
->cfb_fb
== fb
->base
.id
&&
1971 dev_priv
->cfb_y
== crtc
->y
)
1974 if (intel_fbc_enabled(dev
)) {
1975 /* We update FBC along two paths, after changing fb/crtc
1976 * configuration (modeswitching) and after page-flipping
1977 * finishes. For the latter, we know that not only did
1978 * we disable the FBC at the start of the page-flip
1979 * sequence, but also more than one vblank has passed.
1981 * For the former case of modeswitching, it is possible
1982 * to switch between two FBC valid configurations
1983 * instantaneously so we do need to disable the FBC
1984 * before we can modify its control registers. We also
1985 * have to wait for the next vblank for that to take
1986 * effect. However, since we delay enabling FBC we can
1987 * assume that a vblank has passed since disabling and
1988 * that we can safely alter the registers in the deferred
1991 * In the scenario that we go from a valid to invalid
1992 * and then back to valid FBC configuration we have
1993 * no strict enforcement that a vblank occurred since
1994 * disabling the FBC. However, along all current pipe
1995 * disabling paths we do need to wait for a vblank at
1996 * some point. And we wait before enabling FBC anyway.
1998 DRM_DEBUG_KMS("disabling active FBC for update\n");
1999 intel_disable_fbc(dev
);
2002 intel_enable_fbc(crtc
, 500);
2006 /* Multiple disables should be harmless */
2007 if (intel_fbc_enabled(dev
)) {
2008 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
2009 intel_disable_fbc(dev
);
2014 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2015 struct drm_i915_gem_object
*obj
,
2016 struct intel_ring_buffer
*pipelined
)
2018 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2022 switch (obj
->tiling_mode
) {
2023 case I915_TILING_NONE
:
2024 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2025 alignment
= 128 * 1024;
2026 else if (INTEL_INFO(dev
)->gen
>= 4)
2027 alignment
= 4 * 1024;
2029 alignment
= 64 * 1024;
2032 /* pin() will align the object as required by fence */
2036 /* FIXME: Is this true? */
2037 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2043 dev_priv
->mm
.interruptible
= false;
2044 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2046 goto err_interruptible
;
2048 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2049 * fence, whereas 965+ only requires a fence if using
2050 * framebuffer compression. For simplicity, we always install
2051 * a fence as the cost is not that onerous.
2053 if (obj
->tiling_mode
!= I915_TILING_NONE
) {
2054 ret
= i915_gem_object_get_fence(obj
, pipelined
);
2058 i915_gem_object_pin_fence(obj
);
2061 dev_priv
->mm
.interruptible
= true;
2065 i915_gem_object_unpin(obj
);
2067 dev_priv
->mm
.interruptible
= true;
2071 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2073 i915_gem_object_unpin_fence(obj
);
2074 i915_gem_object_unpin(obj
);
2077 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2080 struct drm_device
*dev
= crtc
->dev
;
2081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2082 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2083 struct intel_framebuffer
*intel_fb
;
2084 struct drm_i915_gem_object
*obj
;
2085 int plane
= intel_crtc
->plane
;
2086 unsigned long Start
, Offset
;
2095 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2099 intel_fb
= to_intel_framebuffer(fb
);
2100 obj
= intel_fb
->obj
;
2102 reg
= DSPCNTR(plane
);
2103 dspcntr
= I915_READ(reg
);
2104 /* Mask out pixel format bits in case we change it */
2105 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2106 switch (fb
->bits_per_pixel
) {
2108 dspcntr
|= DISPPLANE_8BPP
;
2111 if (fb
->depth
== 15)
2112 dspcntr
|= DISPPLANE_15_16BPP
;
2114 dspcntr
|= DISPPLANE_16BPP
;
2118 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2121 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2124 if (INTEL_INFO(dev
)->gen
>= 4) {
2125 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2126 dspcntr
|= DISPPLANE_TILED
;
2128 dspcntr
&= ~DISPPLANE_TILED
;
2131 I915_WRITE(reg
, dspcntr
);
2133 Start
= obj
->gtt_offset
;
2134 Offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 Start
, Offset
, x
, y
, fb
->pitches
[0]);
2138 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2139 if (INTEL_INFO(dev
)->gen
>= 4) {
2140 I915_WRITE(DSPSURF(plane
), Start
);
2141 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2142 I915_WRITE(DSPADDR(plane
), Offset
);
2144 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
2150 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2151 struct drm_framebuffer
*fb
, int x
, int y
)
2153 struct drm_device
*dev
= crtc
->dev
;
2154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2156 struct intel_framebuffer
*intel_fb
;
2157 struct drm_i915_gem_object
*obj
;
2158 int plane
= intel_crtc
->plane
;
2159 unsigned long Start
, Offset
;
2169 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2173 intel_fb
= to_intel_framebuffer(fb
);
2174 obj
= intel_fb
->obj
;
2176 reg
= DSPCNTR(plane
);
2177 dspcntr
= I915_READ(reg
);
2178 /* Mask out pixel format bits in case we change it */
2179 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2180 switch (fb
->bits_per_pixel
) {
2182 dspcntr
|= DISPPLANE_8BPP
;
2185 if (fb
->depth
!= 16)
2188 dspcntr
|= DISPPLANE_16BPP
;
2192 if (fb
->depth
== 24)
2193 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2194 else if (fb
->depth
== 30)
2195 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2200 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2204 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2205 dspcntr
|= DISPPLANE_TILED
;
2207 dspcntr
&= ~DISPPLANE_TILED
;
2210 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2212 I915_WRITE(reg
, dspcntr
);
2214 Start
= obj
->gtt_offset
;
2215 Offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2217 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2218 Start
, Offset
, x
, y
, fb
->pitches
[0]);
2219 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2220 I915_WRITE(DSPSURF(plane
), Start
);
2221 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2222 I915_WRITE(DSPADDR(plane
), Offset
);
2228 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2230 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2231 int x
, int y
, enum mode_set_atomic state
)
2233 struct drm_device
*dev
= crtc
->dev
;
2234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2237 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2241 intel_update_fbc(dev
);
2242 intel_increase_pllclock(crtc
);
2248 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2249 struct drm_framebuffer
*old_fb
)
2251 struct drm_device
*dev
= crtc
->dev
;
2252 struct drm_i915_master_private
*master_priv
;
2253 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2258 DRM_ERROR("No FB bound\n");
2262 switch (intel_crtc
->plane
) {
2267 if (IS_IVYBRIDGE(dev
))
2269 /* fall through otherwise */
2271 DRM_ERROR("no plane for crtc\n");
2275 mutex_lock(&dev
->struct_mutex
);
2276 ret
= intel_pin_and_fence_fb_obj(dev
,
2277 to_intel_framebuffer(crtc
->fb
)->obj
,
2280 mutex_unlock(&dev
->struct_mutex
);
2281 DRM_ERROR("pin & fence failed\n");
2286 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2287 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2289 wait_event(dev_priv
->pending_flip_queue
,
2290 atomic_read(&dev_priv
->mm
.wedged
) ||
2291 atomic_read(&obj
->pending_flip
) == 0);
2293 /* Big Hammer, we also need to ensure that any pending
2294 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2295 * current scanout is retired before unpinning the old
2298 * This should only fail upon a hung GPU, in which case we
2299 * can safely continue.
2301 ret
= i915_gem_object_finish_gpu(obj
);
2305 ret
= intel_pipe_set_base_atomic(crtc
, crtc
->fb
, x
, y
,
2306 LEAVE_ATOMIC_MODE_SET
);
2308 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
2309 mutex_unlock(&dev
->struct_mutex
);
2310 DRM_ERROR("failed to update base address\n");
2315 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2316 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2319 mutex_unlock(&dev
->struct_mutex
);
2321 if (!dev
->primary
->master
)
2324 master_priv
= dev
->primary
->master
->driver_priv
;
2325 if (!master_priv
->sarea_priv
)
2328 if (intel_crtc
->pipe
) {
2329 master_priv
->sarea_priv
->pipeB_x
= x
;
2330 master_priv
->sarea_priv
->pipeB_y
= y
;
2332 master_priv
->sarea_priv
->pipeA_x
= x
;
2333 master_priv
->sarea_priv
->pipeA_y
= y
;
2339 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2341 struct drm_device
*dev
= crtc
->dev
;
2342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2345 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2346 dpa_ctl
= I915_READ(DP_A
);
2347 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2349 if (clock
< 200000) {
2351 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2352 /* workaround for 160Mhz:
2353 1) program 0x4600c bits 15:0 = 0x8124
2354 2) program 0x46010 bit 0 = 1
2355 3) program 0x46034 bit 24 = 1
2356 4) program 0x64000 bit 14 = 1
2358 temp
= I915_READ(0x4600c);
2360 I915_WRITE(0x4600c, temp
| 0x8124);
2362 temp
= I915_READ(0x46010);
2363 I915_WRITE(0x46010, temp
| 1);
2365 temp
= I915_READ(0x46034);
2366 I915_WRITE(0x46034, temp
| (1 << 24));
2368 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2370 I915_WRITE(DP_A
, dpa_ctl
);
2376 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2378 struct drm_device
*dev
= crtc
->dev
;
2379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2380 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2381 int pipe
= intel_crtc
->pipe
;
2384 /* enable normal train */
2385 reg
= FDI_TX_CTL(pipe
);
2386 temp
= I915_READ(reg
);
2387 if (IS_IVYBRIDGE(dev
)) {
2388 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2389 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2391 temp
&= ~FDI_LINK_TRAIN_NONE
;
2392 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2394 I915_WRITE(reg
, temp
);
2396 reg
= FDI_RX_CTL(pipe
);
2397 temp
= I915_READ(reg
);
2398 if (HAS_PCH_CPT(dev
)) {
2399 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2400 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2402 temp
&= ~FDI_LINK_TRAIN_NONE
;
2403 temp
|= FDI_LINK_TRAIN_NONE
;
2405 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2407 /* wait one idle pattern time */
2411 /* IVB wants error correction enabled */
2412 if (IS_IVYBRIDGE(dev
))
2413 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2414 FDI_FE_ERRC_ENABLE
);
2417 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2420 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2422 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2423 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2424 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2425 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2426 POSTING_READ(SOUTH_CHICKEN1
);
2429 /* The FDI link training functions for ILK/Ibexpeak. */
2430 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2432 struct drm_device
*dev
= crtc
->dev
;
2433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2434 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2435 int pipe
= intel_crtc
->pipe
;
2436 int plane
= intel_crtc
->plane
;
2437 u32 reg
, temp
, tries
;
2439 /* FDI needs bits from pipe & plane first */
2440 assert_pipe_enabled(dev_priv
, pipe
);
2441 assert_plane_enabled(dev_priv
, plane
);
2443 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2445 reg
= FDI_RX_IMR(pipe
);
2446 temp
= I915_READ(reg
);
2447 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2448 temp
&= ~FDI_RX_BIT_LOCK
;
2449 I915_WRITE(reg
, temp
);
2453 /* enable CPU FDI TX and PCH FDI RX */
2454 reg
= FDI_TX_CTL(pipe
);
2455 temp
= I915_READ(reg
);
2457 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2458 temp
&= ~FDI_LINK_TRAIN_NONE
;
2459 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2460 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2462 reg
= FDI_RX_CTL(pipe
);
2463 temp
= I915_READ(reg
);
2464 temp
&= ~FDI_LINK_TRAIN_NONE
;
2465 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2466 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2471 /* Ironlake workaround, enable clock pointer after FDI enable*/
2472 if (HAS_PCH_IBX(dev
)) {
2473 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2474 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2475 FDI_RX_PHASE_SYNC_POINTER_EN
);
2478 reg
= FDI_RX_IIR(pipe
);
2479 for (tries
= 0; tries
< 5; tries
++) {
2480 temp
= I915_READ(reg
);
2481 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2483 if ((temp
& FDI_RX_BIT_LOCK
)) {
2484 DRM_DEBUG_KMS("FDI train 1 done.\n");
2485 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2490 DRM_ERROR("FDI train 1 fail!\n");
2493 reg
= FDI_TX_CTL(pipe
);
2494 temp
= I915_READ(reg
);
2495 temp
&= ~FDI_LINK_TRAIN_NONE
;
2496 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2497 I915_WRITE(reg
, temp
);
2499 reg
= FDI_RX_CTL(pipe
);
2500 temp
= I915_READ(reg
);
2501 temp
&= ~FDI_LINK_TRAIN_NONE
;
2502 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2503 I915_WRITE(reg
, temp
);
2508 reg
= FDI_RX_IIR(pipe
);
2509 for (tries
= 0; tries
< 5; tries
++) {
2510 temp
= I915_READ(reg
);
2511 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2513 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2514 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2515 DRM_DEBUG_KMS("FDI train 2 done.\n");
2520 DRM_ERROR("FDI train 2 fail!\n");
2522 DRM_DEBUG_KMS("FDI train done\n");
2526 static const int snb_b_fdi_train_param
[] = {
2527 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2528 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2529 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2530 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2533 /* The FDI link training functions for SNB/Cougarpoint. */
2534 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2536 struct drm_device
*dev
= crtc
->dev
;
2537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2538 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2539 int pipe
= intel_crtc
->pipe
;
2542 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2544 reg
= FDI_RX_IMR(pipe
);
2545 temp
= I915_READ(reg
);
2546 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2547 temp
&= ~FDI_RX_BIT_LOCK
;
2548 I915_WRITE(reg
, temp
);
2553 /* enable CPU FDI TX and PCH FDI RX */
2554 reg
= FDI_TX_CTL(pipe
);
2555 temp
= I915_READ(reg
);
2557 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2558 temp
&= ~FDI_LINK_TRAIN_NONE
;
2559 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2560 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2562 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2563 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2565 reg
= FDI_RX_CTL(pipe
);
2566 temp
= I915_READ(reg
);
2567 if (HAS_PCH_CPT(dev
)) {
2568 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2569 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2571 temp
&= ~FDI_LINK_TRAIN_NONE
;
2572 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2574 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2579 if (HAS_PCH_CPT(dev
))
2580 cpt_phase_pointer_enable(dev
, pipe
);
2582 for (i
= 0; i
< 4; i
++) {
2583 reg
= FDI_TX_CTL(pipe
);
2584 temp
= I915_READ(reg
);
2585 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2586 temp
|= snb_b_fdi_train_param
[i
];
2587 I915_WRITE(reg
, temp
);
2592 reg
= FDI_RX_IIR(pipe
);
2593 temp
= I915_READ(reg
);
2594 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2596 if (temp
& FDI_RX_BIT_LOCK
) {
2597 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2598 DRM_DEBUG_KMS("FDI train 1 done.\n");
2603 DRM_ERROR("FDI train 1 fail!\n");
2606 reg
= FDI_TX_CTL(pipe
);
2607 temp
= I915_READ(reg
);
2608 temp
&= ~FDI_LINK_TRAIN_NONE
;
2609 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2611 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2613 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2615 I915_WRITE(reg
, temp
);
2617 reg
= FDI_RX_CTL(pipe
);
2618 temp
= I915_READ(reg
);
2619 if (HAS_PCH_CPT(dev
)) {
2620 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2621 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2623 temp
&= ~FDI_LINK_TRAIN_NONE
;
2624 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2626 I915_WRITE(reg
, temp
);
2631 for (i
= 0; i
< 4; i
++) {
2632 reg
= FDI_TX_CTL(pipe
);
2633 temp
= I915_READ(reg
);
2634 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2635 temp
|= snb_b_fdi_train_param
[i
];
2636 I915_WRITE(reg
, temp
);
2641 reg
= FDI_RX_IIR(pipe
);
2642 temp
= I915_READ(reg
);
2643 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2645 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2646 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2647 DRM_DEBUG_KMS("FDI train 2 done.\n");
2652 DRM_ERROR("FDI train 2 fail!\n");
2654 DRM_DEBUG_KMS("FDI train done.\n");
2657 /* Manual link training for Ivy Bridge A0 parts */
2658 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2660 struct drm_device
*dev
= crtc
->dev
;
2661 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2662 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2663 int pipe
= intel_crtc
->pipe
;
2666 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2668 reg
= FDI_RX_IMR(pipe
);
2669 temp
= I915_READ(reg
);
2670 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2671 temp
&= ~FDI_RX_BIT_LOCK
;
2672 I915_WRITE(reg
, temp
);
2677 /* enable CPU FDI TX and PCH FDI RX */
2678 reg
= FDI_TX_CTL(pipe
);
2679 temp
= I915_READ(reg
);
2681 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2682 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2683 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2684 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2685 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2686 temp
|= FDI_COMPOSITE_SYNC
;
2687 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2689 reg
= FDI_RX_CTL(pipe
);
2690 temp
= I915_READ(reg
);
2691 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2692 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2693 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2694 temp
|= FDI_COMPOSITE_SYNC
;
2695 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2700 if (HAS_PCH_CPT(dev
))
2701 cpt_phase_pointer_enable(dev
, pipe
);
2703 for (i
= 0; i
< 4; i
++) {
2704 reg
= FDI_TX_CTL(pipe
);
2705 temp
= I915_READ(reg
);
2706 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2707 temp
|= snb_b_fdi_train_param
[i
];
2708 I915_WRITE(reg
, temp
);
2713 reg
= FDI_RX_IIR(pipe
);
2714 temp
= I915_READ(reg
);
2715 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2717 if (temp
& FDI_RX_BIT_LOCK
||
2718 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2719 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2720 DRM_DEBUG_KMS("FDI train 1 done.\n");
2725 DRM_ERROR("FDI train 1 fail!\n");
2728 reg
= FDI_TX_CTL(pipe
);
2729 temp
= I915_READ(reg
);
2730 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2731 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2732 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2733 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2734 I915_WRITE(reg
, temp
);
2736 reg
= FDI_RX_CTL(pipe
);
2737 temp
= I915_READ(reg
);
2738 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2739 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2740 I915_WRITE(reg
, temp
);
2745 for (i
= 0; i
< 4; i
++) {
2746 reg
= FDI_TX_CTL(pipe
);
2747 temp
= I915_READ(reg
);
2748 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2749 temp
|= snb_b_fdi_train_param
[i
];
2750 I915_WRITE(reg
, temp
);
2755 reg
= FDI_RX_IIR(pipe
);
2756 temp
= I915_READ(reg
);
2757 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2759 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2760 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2761 DRM_DEBUG_KMS("FDI train 2 done.\n");
2766 DRM_ERROR("FDI train 2 fail!\n");
2768 DRM_DEBUG_KMS("FDI train done.\n");
2771 static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc
)
2773 struct drm_device
*dev
= crtc
->dev
;
2774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2775 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2776 int pipe
= intel_crtc
->pipe
;
2779 /* Write the TU size bits so error detection works */
2780 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2781 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2783 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2784 reg
= FDI_RX_CTL(pipe
);
2785 temp
= I915_READ(reg
);
2786 temp
&= ~((0x7 << 19) | (0x7 << 16));
2787 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2788 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2789 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2794 /* Switch from Rawclk to PCDclk */
2795 temp
= I915_READ(reg
);
2796 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2801 /* Enable CPU FDI TX PLL, always on for Ironlake */
2802 reg
= FDI_TX_CTL(pipe
);
2803 temp
= I915_READ(reg
);
2804 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2805 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2812 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2814 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2815 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2817 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2818 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2819 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2820 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2821 POSTING_READ(SOUTH_CHICKEN1
);
2823 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2825 struct drm_device
*dev
= crtc
->dev
;
2826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2827 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2828 int pipe
= intel_crtc
->pipe
;
2831 /* disable CPU FDI tx and PCH FDI rx */
2832 reg
= FDI_TX_CTL(pipe
);
2833 temp
= I915_READ(reg
);
2834 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2837 reg
= FDI_RX_CTL(pipe
);
2838 temp
= I915_READ(reg
);
2839 temp
&= ~(0x7 << 16);
2840 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2841 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2846 /* Ironlake workaround, disable clock pointer after downing FDI */
2847 if (HAS_PCH_IBX(dev
)) {
2848 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2849 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2850 I915_READ(FDI_RX_CHICKEN(pipe
) &
2851 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2852 } else if (HAS_PCH_CPT(dev
)) {
2853 cpt_phase_pointer_disable(dev
, pipe
);
2856 /* still set train pattern 1 */
2857 reg
= FDI_TX_CTL(pipe
);
2858 temp
= I915_READ(reg
);
2859 temp
&= ~FDI_LINK_TRAIN_NONE
;
2860 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2861 I915_WRITE(reg
, temp
);
2863 reg
= FDI_RX_CTL(pipe
);
2864 temp
= I915_READ(reg
);
2865 if (HAS_PCH_CPT(dev
)) {
2866 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2867 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2869 temp
&= ~FDI_LINK_TRAIN_NONE
;
2870 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2872 /* BPC in FDI rx is consistent with that in PIPECONF */
2873 temp
&= ~(0x07 << 16);
2874 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2875 I915_WRITE(reg
, temp
);
2882 * When we disable a pipe, we need to clear any pending scanline wait events
2883 * to avoid hanging the ring, which we assume we are waiting on.
2885 static void intel_clear_scanline_wait(struct drm_device
*dev
)
2887 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2888 struct intel_ring_buffer
*ring
;
2892 /* Can't break the hang on i8xx */
2895 ring
= LP_RING(dev_priv
);
2896 tmp
= I915_READ_CTL(ring
);
2897 if (tmp
& RING_WAIT
)
2898 I915_WRITE_CTL(ring
, tmp
);
2901 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2903 struct drm_i915_gem_object
*obj
;
2904 struct drm_i915_private
*dev_priv
;
2906 if (crtc
->fb
== NULL
)
2909 obj
= to_intel_framebuffer(crtc
->fb
)->obj
;
2910 dev_priv
= crtc
->dev
->dev_private
;
2911 wait_event(dev_priv
->pending_flip_queue
,
2912 atomic_read(&obj
->pending_flip
) == 0);
2915 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2917 struct drm_device
*dev
= crtc
->dev
;
2918 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2919 struct intel_encoder
*encoder
;
2922 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2923 * must be driven by its own crtc; no sharing is possible.
2925 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
2926 if (encoder
->base
.crtc
!= crtc
)
2929 switch (encoder
->type
) {
2930 case INTEL_OUTPUT_EDP
:
2931 if (!intel_encoder_is_pch_edp(&encoder
->base
))
2941 * Enable PCH resources required for PCH ports:
2943 * - FDI training & RX/TX
2944 * - update transcoder timings
2945 * - DP transcoding bits
2948 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2950 struct drm_device
*dev
= crtc
->dev
;
2951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2952 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2953 int pipe
= intel_crtc
->pipe
;
2954 u32 reg
, temp
, transc_sel
;
2956 /* For PCH output, training FDI link */
2957 dev_priv
->display
.fdi_link_train(crtc
);
2959 intel_enable_pch_pll(dev_priv
, pipe
);
2961 if (HAS_PCH_CPT(dev
)) {
2962 transc_sel
= intel_crtc
->use_pll_a
? TRANSC_DPLLA_SEL
:
2965 /* Be sure PCH DPLL SEL is set */
2966 temp
= I915_READ(PCH_DPLL_SEL
);
2968 temp
&= ~(TRANSA_DPLLB_SEL
);
2969 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2970 } else if (pipe
== 1) {
2971 temp
&= ~(TRANSB_DPLLB_SEL
);
2972 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2973 } else if (pipe
== 2) {
2974 temp
&= ~(TRANSC_DPLLB_SEL
);
2975 temp
|= (TRANSC_DPLL_ENABLE
| transc_sel
);
2977 I915_WRITE(PCH_DPLL_SEL
, temp
);
2980 /* set transcoder timing, panel must allow it */
2981 assert_panel_unlocked(dev_priv
, pipe
);
2982 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
2983 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
2984 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
2986 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
2987 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
2988 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
2989 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
2991 intel_fdi_normal_train(crtc
);
2993 /* For PCH DP, enable TRANS_DP_CTL */
2994 if (HAS_PCH_CPT(dev
) &&
2995 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
2996 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2997 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
2998 reg
= TRANS_DP_CTL(pipe
);
2999 temp
= I915_READ(reg
);
3000 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3001 TRANS_DP_SYNC_MASK
|
3003 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3004 TRANS_DP_ENH_FRAMING
);
3005 temp
|= bpc
<< 9; /* same format but at 11:9 */
3007 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3008 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3009 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3010 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3012 switch (intel_trans_dp_port_sel(crtc
)) {
3014 temp
|= TRANS_DP_PORT_SEL_B
;
3017 temp
|= TRANS_DP_PORT_SEL_C
;
3020 temp
|= TRANS_DP_PORT_SEL_D
;
3023 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3024 temp
|= TRANS_DP_PORT_SEL_B
;
3028 I915_WRITE(reg
, temp
);
3031 intel_enable_transcoder(dev_priv
, pipe
);
3034 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3037 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3040 temp
= I915_READ(dslreg
);
3042 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3043 /* Without this, mode sets may fail silently on FDI */
3044 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3046 I915_WRITE(tc2reg
, 0);
3047 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3048 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3052 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3054 struct drm_device
*dev
= crtc
->dev
;
3055 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3056 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3057 int pipe
= intel_crtc
->pipe
;
3058 int plane
= intel_crtc
->plane
;
3062 if (intel_crtc
->active
)
3065 intel_crtc
->active
= true;
3066 intel_update_watermarks(dev
);
3068 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3069 temp
= I915_READ(PCH_LVDS
);
3070 if ((temp
& LVDS_PORT_EN
) == 0)
3071 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3074 is_pch_port
= intel_crtc_driving_pch(crtc
);
3077 ironlake_fdi_pll_enable(crtc
);
3079 ironlake_fdi_disable(crtc
);
3081 /* Enable panel fitting for LVDS */
3082 if (dev_priv
->pch_pf_size
&&
3083 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3084 /* Force use of hard-coded filter coefficients
3085 * as some pre-programmed values are broken,
3088 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3089 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3090 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3094 * On ILK+ LUT must be loaded before the pipe is running but with
3097 intel_crtc_load_lut(crtc
);
3099 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3100 intel_enable_plane(dev_priv
, plane
, pipe
);
3103 ironlake_pch_enable(crtc
);
3105 mutex_lock(&dev
->struct_mutex
);
3106 intel_update_fbc(dev
);
3107 mutex_unlock(&dev
->struct_mutex
);
3109 intel_crtc_update_cursor(crtc
, true);
3112 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3114 struct drm_device
*dev
= crtc
->dev
;
3115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3116 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3117 int pipe
= intel_crtc
->pipe
;
3118 int plane
= intel_crtc
->plane
;
3121 if (!intel_crtc
->active
)
3124 intel_crtc_wait_for_pending_flips(crtc
);
3125 drm_vblank_off(dev
, pipe
);
3126 intel_crtc_update_cursor(crtc
, false);
3128 intel_disable_plane(dev_priv
, plane
, pipe
);
3130 if (dev_priv
->cfb_plane
== plane
)
3131 intel_disable_fbc(dev
);
3133 intel_disable_pipe(dev_priv
, pipe
);
3136 I915_WRITE(PF_CTL(pipe
), 0);
3137 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3139 ironlake_fdi_disable(crtc
);
3141 /* This is a horrible layering violation; we should be doing this in
3142 * the connector/encoder ->prepare instead, but we don't always have
3143 * enough information there about the config to know whether it will
3144 * actually be necessary or just cause undesired flicker.
3146 intel_disable_pch_ports(dev_priv
, pipe
);
3148 intel_disable_transcoder(dev_priv
, pipe
);
3150 if (HAS_PCH_CPT(dev
)) {
3151 /* disable TRANS_DP_CTL */
3152 reg
= TRANS_DP_CTL(pipe
);
3153 temp
= I915_READ(reg
);
3154 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3155 temp
|= TRANS_DP_PORT_SEL_NONE
;
3156 I915_WRITE(reg
, temp
);
3158 /* disable DPLL_SEL */
3159 temp
= I915_READ(PCH_DPLL_SEL
);
3162 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3165 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3168 /* C shares PLL A or B */
3169 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3174 I915_WRITE(PCH_DPLL_SEL
, temp
);
3177 /* disable PCH DPLL */
3178 if (!intel_crtc
->no_pll
)
3179 intel_disable_pch_pll(dev_priv
, pipe
);
3181 /* Switch from PCDclk to Rawclk */
3182 reg
= FDI_RX_CTL(pipe
);
3183 temp
= I915_READ(reg
);
3184 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3186 /* Disable CPU FDI TX PLL */
3187 reg
= FDI_TX_CTL(pipe
);
3188 temp
= I915_READ(reg
);
3189 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3194 reg
= FDI_RX_CTL(pipe
);
3195 temp
= I915_READ(reg
);
3196 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3198 /* Wait for the clocks to turn off. */
3202 intel_crtc
->active
= false;
3203 intel_update_watermarks(dev
);
3205 mutex_lock(&dev
->struct_mutex
);
3206 intel_update_fbc(dev
);
3207 intel_clear_scanline_wait(dev
);
3208 mutex_unlock(&dev
->struct_mutex
);
3211 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3213 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3214 int pipe
= intel_crtc
->pipe
;
3215 int plane
= intel_crtc
->plane
;
3217 /* XXX: When our outputs are all unaware of DPMS modes other than off
3218 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3221 case DRM_MODE_DPMS_ON
:
3222 case DRM_MODE_DPMS_STANDBY
:
3223 case DRM_MODE_DPMS_SUSPEND
:
3224 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
3225 ironlake_crtc_enable(crtc
);
3228 case DRM_MODE_DPMS_OFF
:
3229 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
3230 ironlake_crtc_disable(crtc
);
3235 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3237 if (!enable
&& intel_crtc
->overlay
) {
3238 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3241 mutex_lock(&dev
->struct_mutex
);
3242 dev_priv
->mm
.interruptible
= false;
3243 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3244 dev_priv
->mm
.interruptible
= true;
3245 mutex_unlock(&dev
->struct_mutex
);
3248 /* Let userspace switch the overlay on again. In most cases userspace
3249 * has to recompute where to put it anyway.
3253 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3255 struct drm_device
*dev
= crtc
->dev
;
3256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3257 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3258 int pipe
= intel_crtc
->pipe
;
3259 int plane
= intel_crtc
->plane
;
3261 if (intel_crtc
->active
)
3264 intel_crtc
->active
= true;
3265 intel_update_watermarks(dev
);
3267 intel_enable_pll(dev_priv
, pipe
);
3268 intel_enable_pipe(dev_priv
, pipe
, false);
3269 intel_enable_plane(dev_priv
, plane
, pipe
);
3271 intel_crtc_load_lut(crtc
);
3272 intel_update_fbc(dev
);
3274 /* Give the overlay scaler a chance to enable if it's on this pipe */
3275 intel_crtc_dpms_overlay(intel_crtc
, true);
3276 intel_crtc_update_cursor(crtc
, true);
3279 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3281 struct drm_device
*dev
= crtc
->dev
;
3282 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3283 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3284 int pipe
= intel_crtc
->pipe
;
3285 int plane
= intel_crtc
->plane
;
3287 if (!intel_crtc
->active
)
3290 /* Give the overlay scaler a chance to disable if it's on this pipe */
3291 intel_crtc_wait_for_pending_flips(crtc
);
3292 drm_vblank_off(dev
, pipe
);
3293 intel_crtc_dpms_overlay(intel_crtc
, false);
3294 intel_crtc_update_cursor(crtc
, false);
3296 if (dev_priv
->cfb_plane
== plane
)
3297 intel_disable_fbc(dev
);
3299 intel_disable_plane(dev_priv
, plane
, pipe
);
3300 intel_disable_pipe(dev_priv
, pipe
);
3301 intel_disable_pll(dev_priv
, pipe
);
3303 intel_crtc
->active
= false;
3304 intel_update_fbc(dev
);
3305 intel_update_watermarks(dev
);
3306 intel_clear_scanline_wait(dev
);
3309 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3311 /* XXX: When our outputs are all unaware of DPMS modes other than off
3312 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3315 case DRM_MODE_DPMS_ON
:
3316 case DRM_MODE_DPMS_STANDBY
:
3317 case DRM_MODE_DPMS_SUSPEND
:
3318 i9xx_crtc_enable(crtc
);
3320 case DRM_MODE_DPMS_OFF
:
3321 i9xx_crtc_disable(crtc
);
3327 * Sets the power management mode of the pipe and plane.
3329 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3331 struct drm_device
*dev
= crtc
->dev
;
3332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3333 struct drm_i915_master_private
*master_priv
;
3334 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3335 int pipe
= intel_crtc
->pipe
;
3338 if (intel_crtc
->dpms_mode
== mode
)
3341 intel_crtc
->dpms_mode
= mode
;
3343 dev_priv
->display
.dpms(crtc
, mode
);
3345 if (!dev
->primary
->master
)
3348 master_priv
= dev
->primary
->master
->driver_priv
;
3349 if (!master_priv
->sarea_priv
)
3352 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
3356 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3357 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3360 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3361 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3364 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3369 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3371 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3372 struct drm_device
*dev
= crtc
->dev
;
3374 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
3375 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3376 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3379 mutex_lock(&dev
->struct_mutex
);
3380 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3381 mutex_unlock(&dev
->struct_mutex
);
3385 /* Prepare for a mode set.
3387 * Note we could be a lot smarter here. We need to figure out which outputs
3388 * will be enabled, which disabled (in short, how the config will changes)
3389 * and perform the minimum necessary steps to accomplish that, e.g. updating
3390 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3391 * panel fitting is in the proper state, etc.
3393 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
3395 i9xx_crtc_disable(crtc
);
3398 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3400 i9xx_crtc_enable(crtc
);
3403 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3405 ironlake_crtc_disable(crtc
);
3408 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3410 ironlake_crtc_enable(crtc
);
3413 void intel_encoder_prepare(struct drm_encoder
*encoder
)
3415 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3416 /* lvds has its own version of prepare see intel_lvds_prepare */
3417 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3420 void intel_encoder_commit(struct drm_encoder
*encoder
)
3422 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3423 struct drm_device
*dev
= encoder
->dev
;
3424 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3425 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
3427 /* lvds has its own version of commit see intel_lvds_commit */
3428 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3430 if (HAS_PCH_CPT(dev
))
3431 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3434 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3436 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3438 drm_encoder_cleanup(encoder
);
3439 kfree(intel_encoder
);
3442 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3443 struct drm_display_mode
*mode
,
3444 struct drm_display_mode
*adjusted_mode
)
3446 struct drm_device
*dev
= crtc
->dev
;
3448 if (HAS_PCH_SPLIT(dev
)) {
3449 /* FDI link clock is fixed at 2.7G */
3450 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3454 /* All interlaced capable intel hw wants timings in frames. */
3455 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3460 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3465 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3470 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3475 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3479 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3481 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3484 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3485 case GC_DISPLAY_CLOCK_333_MHZ
:
3488 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3494 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3499 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3502 /* Assume that the hardware is in the high speed state. This
3503 * should be the default.
3505 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3506 case GC_CLOCK_133_200
:
3507 case GC_CLOCK_100_200
:
3509 case GC_CLOCK_166_250
:
3511 case GC_CLOCK_100_133
:
3515 /* Shouldn't happen */
3519 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3533 fdi_reduce_ratio(u32
*num
, u32
*den
)
3535 while (*num
> 0xffffff || *den
> 0xffffff) {
3542 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3543 int link_clock
, struct fdi_m_n
*m_n
)
3545 m_n
->tu
= 64; /* default size */
3547 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3548 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3549 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3550 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3552 m_n
->link_m
= pixel_clock
;
3553 m_n
->link_n
= link_clock
;
3554 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3558 struct intel_watermark_params
{
3559 unsigned long fifo_size
;
3560 unsigned long max_wm
;
3561 unsigned long default_wm
;
3562 unsigned long guard_size
;
3563 unsigned long cacheline_size
;
3566 /* Pineview has different values for various configs */
3567 static const struct intel_watermark_params pineview_display_wm
= {
3568 PINEVIEW_DISPLAY_FIFO
,
3572 PINEVIEW_FIFO_LINE_SIZE
3574 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
3575 PINEVIEW_DISPLAY_FIFO
,
3577 PINEVIEW_DFT_HPLLOFF_WM
,
3579 PINEVIEW_FIFO_LINE_SIZE
3581 static const struct intel_watermark_params pineview_cursor_wm
= {
3582 PINEVIEW_CURSOR_FIFO
,
3583 PINEVIEW_CURSOR_MAX_WM
,
3584 PINEVIEW_CURSOR_DFT_WM
,
3585 PINEVIEW_CURSOR_GUARD_WM
,
3586 PINEVIEW_FIFO_LINE_SIZE
,
3588 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
3589 PINEVIEW_CURSOR_FIFO
,
3590 PINEVIEW_CURSOR_MAX_WM
,
3591 PINEVIEW_CURSOR_DFT_WM
,
3592 PINEVIEW_CURSOR_GUARD_WM
,
3593 PINEVIEW_FIFO_LINE_SIZE
3595 static const struct intel_watermark_params g4x_wm_info
= {
3602 static const struct intel_watermark_params g4x_cursor_wm_info
= {
3609 static const struct intel_watermark_params i965_cursor_wm_info
= {
3614 I915_FIFO_LINE_SIZE
,
3616 static const struct intel_watermark_params i945_wm_info
= {
3623 static const struct intel_watermark_params i915_wm_info
= {
3630 static const struct intel_watermark_params i855_wm_info
= {
3637 static const struct intel_watermark_params i830_wm_info
= {
3645 static const struct intel_watermark_params ironlake_display_wm_info
= {
3652 static const struct intel_watermark_params ironlake_cursor_wm_info
= {
3659 static const struct intel_watermark_params ironlake_display_srwm_info
= {
3660 ILK_DISPLAY_SR_FIFO
,
3661 ILK_DISPLAY_MAX_SRWM
,
3662 ILK_DISPLAY_DFT_SRWM
,
3666 static const struct intel_watermark_params ironlake_cursor_srwm_info
= {
3668 ILK_CURSOR_MAX_SRWM
,
3669 ILK_CURSOR_DFT_SRWM
,
3674 static const struct intel_watermark_params sandybridge_display_wm_info
= {
3681 static const struct intel_watermark_params sandybridge_cursor_wm_info
= {
3688 static const struct intel_watermark_params sandybridge_display_srwm_info
= {
3689 SNB_DISPLAY_SR_FIFO
,
3690 SNB_DISPLAY_MAX_SRWM
,
3691 SNB_DISPLAY_DFT_SRWM
,
3695 static const struct intel_watermark_params sandybridge_cursor_srwm_info
= {
3697 SNB_CURSOR_MAX_SRWM
,
3698 SNB_CURSOR_DFT_SRWM
,
3705 * intel_calculate_wm - calculate watermark level
3706 * @clock_in_khz: pixel clock
3707 * @wm: chip FIFO params
3708 * @pixel_size: display pixel size
3709 * @latency_ns: memory latency for the platform
3711 * Calculate the watermark level (the level at which the display plane will
3712 * start fetching from memory again). Each chip has a different display
3713 * FIFO size and allocation, so the caller needs to figure that out and pass
3714 * in the correct intel_watermark_params structure.
3716 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3717 * on the pixel size. When it reaches the watermark level, it'll start
3718 * fetching FIFO line sized based chunks from memory until the FIFO fills
3719 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3720 * will occur, and a display engine hang could result.
3722 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
3723 const struct intel_watermark_params
*wm
,
3726 unsigned long latency_ns
)
3728 long entries_required
, wm_size
;
3731 * Note: we need to make sure we don't overflow for various clock &
3733 * clocks go from a few thousand to several hundred thousand.
3734 * latency is usually a few thousand
3736 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
3738 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
3740 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
3742 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
3744 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
3746 /* Don't promote wm_size to unsigned... */
3747 if (wm_size
> (long)wm
->max_wm
)
3748 wm_size
= wm
->max_wm
;
3750 wm_size
= wm
->default_wm
;
3754 struct cxsr_latency
{
3757 unsigned long fsb_freq
;
3758 unsigned long mem_freq
;
3759 unsigned long display_sr
;
3760 unsigned long display_hpll_disable
;
3761 unsigned long cursor_sr
;
3762 unsigned long cursor_hpll_disable
;
3765 static const struct cxsr_latency cxsr_latency_table
[] = {
3766 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3767 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3768 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3769 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3770 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3772 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3773 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3774 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3775 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3776 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3778 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3779 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3780 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3781 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3782 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3784 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3785 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3786 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3787 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3788 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3790 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3791 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3792 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3793 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3794 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3796 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3797 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3798 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3799 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3800 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
3803 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
3808 const struct cxsr_latency
*latency
;
3811 if (fsb
== 0 || mem
== 0)
3814 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
3815 latency
= &cxsr_latency_table
[i
];
3816 if (is_desktop
== latency
->is_desktop
&&
3817 is_ddr3
== latency
->is_ddr3
&&
3818 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
3822 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3827 static void pineview_disable_cxsr(struct drm_device
*dev
)
3829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3831 /* deactivate cxsr */
3832 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
3836 * Latency for FIFO fetches is dependent on several factors:
3837 * - memory configuration (speed, channels)
3839 * - current MCH state
3840 * It can be fairly high in some situations, so here we assume a fairly
3841 * pessimal value. It's a tradeoff between extra memory fetches (if we
3842 * set this value too high, the FIFO will fetch frequently to stay full)
3843 * and power consumption (set it too low to save power and we might see
3844 * FIFO underruns and display "flicker").
3846 * A value of 5us seems to be a good balance; safe for very low end
3847 * platforms but not overly aggressive on lower latency configs.
3849 static const int latency_ns
= 5000;
3851 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
3853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3854 uint32_t dsparb
= I915_READ(DSPARB
);
3857 size
= dsparb
& 0x7f;
3859 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
3861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3862 plane
? "B" : "A", size
);
3867 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
3869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3870 uint32_t dsparb
= I915_READ(DSPARB
);
3873 size
= dsparb
& 0x1ff;
3875 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
3876 size
>>= 1; /* Convert to cachelines */
3878 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3879 plane
? "B" : "A", size
);
3884 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
3886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3887 uint32_t dsparb
= I915_READ(DSPARB
);
3890 size
= dsparb
& 0x7f;
3891 size
>>= 2; /* Convert to cachelines */
3893 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3900 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
3902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3903 uint32_t dsparb
= I915_READ(DSPARB
);
3906 size
= dsparb
& 0x7f;
3907 size
>>= 1; /* Convert to cachelines */
3909 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3910 plane
? "B" : "A", size
);
3915 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
3917 struct drm_crtc
*crtc
, *enabled
= NULL
;
3919 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3920 if (crtc
->enabled
&& crtc
->fb
) {
3930 static void pineview_update_wm(struct drm_device
*dev
)
3932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3933 struct drm_crtc
*crtc
;
3934 const struct cxsr_latency
*latency
;
3938 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
3939 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3941 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3942 pineview_disable_cxsr(dev
);
3946 crtc
= single_enabled_crtc(dev
);
3948 int clock
= crtc
->mode
.clock
;
3949 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3952 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
3953 pineview_display_wm
.fifo_size
,
3954 pixel_size
, latency
->display_sr
);
3955 reg
= I915_READ(DSPFW1
);
3956 reg
&= ~DSPFW_SR_MASK
;
3957 reg
|= wm
<< DSPFW_SR_SHIFT
;
3958 I915_WRITE(DSPFW1
, reg
);
3959 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
3962 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
3963 pineview_display_wm
.fifo_size
,
3964 pixel_size
, latency
->cursor_sr
);
3965 reg
= I915_READ(DSPFW3
);
3966 reg
&= ~DSPFW_CURSOR_SR_MASK
;
3967 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
3968 I915_WRITE(DSPFW3
, reg
);
3970 /* Display HPLL off SR */
3971 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
3972 pineview_display_hplloff_wm
.fifo_size
,
3973 pixel_size
, latency
->display_hpll_disable
);
3974 reg
= I915_READ(DSPFW3
);
3975 reg
&= ~DSPFW_HPLL_SR_MASK
;
3976 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
3977 I915_WRITE(DSPFW3
, reg
);
3979 /* cursor HPLL off SR */
3980 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
3981 pineview_display_hplloff_wm
.fifo_size
,
3982 pixel_size
, latency
->cursor_hpll_disable
);
3983 reg
= I915_READ(DSPFW3
);
3984 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
3985 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
3986 I915_WRITE(DSPFW3
, reg
);
3987 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
3991 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
3992 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3994 pineview_disable_cxsr(dev
);
3995 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3999 static bool g4x_compute_wm0(struct drm_device
*dev
,
4001 const struct intel_watermark_params
*display
,
4002 int display_latency_ns
,
4003 const struct intel_watermark_params
*cursor
,
4004 int cursor_latency_ns
,
4008 struct drm_crtc
*crtc
;
4009 int htotal
, hdisplay
, clock
, pixel_size
;
4010 int line_time_us
, line_count
;
4011 int entries
, tlb_miss
;
4013 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4014 if (crtc
->fb
== NULL
|| !crtc
->enabled
) {
4015 *cursor_wm
= cursor
->guard_size
;
4016 *plane_wm
= display
->guard_size
;
4020 htotal
= crtc
->mode
.htotal
;
4021 hdisplay
= crtc
->mode
.hdisplay
;
4022 clock
= crtc
->mode
.clock
;
4023 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4025 /* Use the small buffer method to calculate plane watermark */
4026 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
4027 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
4029 entries
+= tlb_miss
;
4030 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
4031 *plane_wm
= entries
+ display
->guard_size
;
4032 if (*plane_wm
> (int)display
->max_wm
)
4033 *plane_wm
= display
->max_wm
;
4035 /* Use the large buffer method to calculate cursor watermark */
4036 line_time_us
= ((htotal
* 1000) / clock
);
4037 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
4038 entries
= line_count
* 64 * pixel_size
;
4039 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
4041 entries
+= tlb_miss
;
4042 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4043 *cursor_wm
= entries
+ cursor
->guard_size
;
4044 if (*cursor_wm
> (int)cursor
->max_wm
)
4045 *cursor_wm
= (int)cursor
->max_wm
;
4051 * Check the wm result.
4053 * If any calculated watermark values is larger than the maximum value that
4054 * can be programmed into the associated watermark register, that watermark
4057 static bool g4x_check_srwm(struct drm_device
*dev
,
4058 int display_wm
, int cursor_wm
,
4059 const struct intel_watermark_params
*display
,
4060 const struct intel_watermark_params
*cursor
)
4062 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4063 display_wm
, cursor_wm
);
4065 if (display_wm
> display
->max_wm
) {
4066 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
4067 display_wm
, display
->max_wm
);
4071 if (cursor_wm
> cursor
->max_wm
) {
4072 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
4073 cursor_wm
, cursor
->max_wm
);
4077 if (!(display_wm
|| cursor_wm
)) {
4078 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4085 static bool g4x_compute_srwm(struct drm_device
*dev
,
4088 const struct intel_watermark_params
*display
,
4089 const struct intel_watermark_params
*cursor
,
4090 int *display_wm
, int *cursor_wm
)
4092 struct drm_crtc
*crtc
;
4093 int hdisplay
, htotal
, pixel_size
, clock
;
4094 unsigned long line_time_us
;
4095 int line_count
, line_size
;
4100 *display_wm
= *cursor_wm
= 0;
4104 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4105 hdisplay
= crtc
->mode
.hdisplay
;
4106 htotal
= crtc
->mode
.htotal
;
4107 clock
= crtc
->mode
.clock
;
4108 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4110 line_time_us
= (htotal
* 1000) / clock
;
4111 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
4112 line_size
= hdisplay
* pixel_size
;
4114 /* Use the minimum of the small and large buffer method for primary */
4115 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
4116 large
= line_count
* line_size
;
4118 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
4119 *display_wm
= entries
+ display
->guard_size
;
4121 /* calculate the self-refresh watermark for display cursor */
4122 entries
= line_count
* pixel_size
* 64;
4123 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4124 *cursor_wm
= entries
+ cursor
->guard_size
;
4126 return g4x_check_srwm(dev
,
4127 *display_wm
, *cursor_wm
,
4131 #define single_plane_enabled(mask) is_power_of_2(mask)
4133 static void g4x_update_wm(struct drm_device
*dev
)
4135 static const int sr_latency_ns
= 12000;
4136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4137 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
4138 int plane_sr
, cursor_sr
;
4139 unsigned int enabled
= 0;
4141 if (g4x_compute_wm0(dev
, 0,
4142 &g4x_wm_info
, latency_ns
,
4143 &g4x_cursor_wm_info
, latency_ns
,
4144 &planea_wm
, &cursora_wm
))
4147 if (g4x_compute_wm0(dev
, 1,
4148 &g4x_wm_info
, latency_ns
,
4149 &g4x_cursor_wm_info
, latency_ns
,
4150 &planeb_wm
, &cursorb_wm
))
4153 plane_sr
= cursor_sr
= 0;
4154 if (single_plane_enabled(enabled
) &&
4155 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
4158 &g4x_cursor_wm_info
,
4159 &plane_sr
, &cursor_sr
))
4160 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
4162 I915_WRITE(FW_BLC_SELF
,
4163 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
4165 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4166 planea_wm
, cursora_wm
,
4167 planeb_wm
, cursorb_wm
,
4168 plane_sr
, cursor_sr
);
4171 (plane_sr
<< DSPFW_SR_SHIFT
) |
4172 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
4173 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
4176 (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
4177 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
4178 /* HPLL off in SR has some issues on G4x... disable it */
4180 (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
4181 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
4184 static void i965_update_wm(struct drm_device
*dev
)
4186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4187 struct drm_crtc
*crtc
;
4191 /* Calc sr entries for one plane configs */
4192 crtc
= single_enabled_crtc(dev
);
4194 /* self-refresh has much higher latency */
4195 static const int sr_latency_ns
= 12000;
4196 int clock
= crtc
->mode
.clock
;
4197 int htotal
= crtc
->mode
.htotal
;
4198 int hdisplay
= crtc
->mode
.hdisplay
;
4199 int pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4200 unsigned long line_time_us
;
4203 line_time_us
= ((htotal
* 1000) / clock
);
4205 /* Use ns/us then divide to preserve precision */
4206 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
4207 pixel_size
* hdisplay
;
4208 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
4209 srwm
= I965_FIFO_SIZE
- entries
;
4213 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4216 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
4218 entries
= DIV_ROUND_UP(entries
,
4219 i965_cursor_wm_info
.cacheline_size
);
4220 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
4221 (entries
+ i965_cursor_wm_info
.guard_size
);
4223 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
4224 cursor_sr
= i965_cursor_wm_info
.max_wm
;
4226 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4227 "cursor %d\n", srwm
, cursor_sr
);
4229 if (IS_CRESTLINE(dev
))
4230 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
4232 /* Turn off self refresh if both pipes are enabled */
4233 if (IS_CRESTLINE(dev
))
4234 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
4238 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4241 /* 965 has limitations... */
4242 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
4243 (8 << 16) | (8 << 8) | (8 << 0));
4244 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
4245 /* update cursor SR watermark */
4246 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
4249 static void i9xx_update_wm(struct drm_device
*dev
)
4251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4252 const struct intel_watermark_params
*wm_info
;
4257 int planea_wm
, planeb_wm
;
4258 struct drm_crtc
*crtc
, *enabled
= NULL
;
4261 wm_info
= &i945_wm_info
;
4262 else if (!IS_GEN2(dev
))
4263 wm_info
= &i915_wm_info
;
4265 wm_info
= &i855_wm_info
;
4267 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
4268 crtc
= intel_get_crtc_for_plane(dev
, 0);
4269 if (crtc
->enabled
&& crtc
->fb
) {
4270 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
,
4272 crtc
->fb
->bits_per_pixel
/ 8,
4276 planea_wm
= fifo_size
- wm_info
->guard_size
;
4278 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
4279 crtc
= intel_get_crtc_for_plane(dev
, 1);
4280 if (crtc
->enabled
&& crtc
->fb
) {
4281 planeb_wm
= intel_calculate_wm(crtc
->mode
.clock
,
4283 crtc
->fb
->bits_per_pixel
/ 8,
4285 if (enabled
== NULL
)
4290 planeb_wm
= fifo_size
- wm_info
->guard_size
;
4292 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
4295 * Overlay gets an aggressive default since video jitter is bad.
4299 /* Play safe and disable self-refresh before adjusting watermarks. */
4300 if (IS_I945G(dev
) || IS_I945GM(dev
))
4301 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
4302 else if (IS_I915GM(dev
))
4303 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
4305 /* Calc sr entries for one plane configs */
4306 if (HAS_FW_BLC(dev
) && enabled
) {
4307 /* self-refresh has much higher latency */
4308 static const int sr_latency_ns
= 6000;
4309 int clock
= enabled
->mode
.clock
;
4310 int htotal
= enabled
->mode
.htotal
;
4311 int hdisplay
= enabled
->mode
.hdisplay
;
4312 int pixel_size
= enabled
->fb
->bits_per_pixel
/ 8;
4313 unsigned long line_time_us
;
4316 line_time_us
= (htotal
* 1000) / clock
;
4318 /* Use ns/us then divide to preserve precision */
4319 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
4320 pixel_size
* hdisplay
;
4321 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
4322 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
4323 srwm
= wm_info
->fifo_size
- entries
;
4327 if (IS_I945G(dev
) || IS_I945GM(dev
))
4328 I915_WRITE(FW_BLC_SELF
,
4329 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
4330 else if (IS_I915GM(dev
))
4331 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
4334 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
4335 planea_wm
, planeb_wm
, cwm
, srwm
);
4337 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
4338 fwater_hi
= (cwm
& 0x1f);
4340 /* Set request length to 8 cachelines per fetch */
4341 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
4342 fwater_hi
= fwater_hi
| (1 << 8);
4344 I915_WRITE(FW_BLC
, fwater_lo
);
4345 I915_WRITE(FW_BLC2
, fwater_hi
);
4347 if (HAS_FW_BLC(dev
)) {
4349 if (IS_I945G(dev
) || IS_I945GM(dev
))
4350 I915_WRITE(FW_BLC_SELF
,
4351 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4352 else if (IS_I915GM(dev
))
4353 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
4354 DRM_DEBUG_KMS("memory self refresh enabled\n");
4356 DRM_DEBUG_KMS("memory self refresh disabled\n");
4360 static void i830_update_wm(struct drm_device
*dev
)
4362 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4363 struct drm_crtc
*crtc
;
4367 crtc
= single_enabled_crtc(dev
);
4371 planea_wm
= intel_calculate_wm(crtc
->mode
.clock
, &i830_wm_info
,
4372 dev_priv
->display
.get_fifo_size(dev
, 0),
4373 crtc
->fb
->bits_per_pixel
/ 8,
4375 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
4376 fwater_lo
|= (3<<8) | planea_wm
;
4378 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
4380 I915_WRITE(FW_BLC
, fwater_lo
);
4383 #define ILK_LP0_PLANE_LATENCY 700
4384 #define ILK_LP0_CURSOR_LATENCY 1300
4387 * Check the wm result.
4389 * If any calculated watermark values is larger than the maximum value that
4390 * can be programmed into the associated watermark register, that watermark
4393 static bool ironlake_check_srwm(struct drm_device
*dev
, int level
,
4394 int fbc_wm
, int display_wm
, int cursor_wm
,
4395 const struct intel_watermark_params
*display
,
4396 const struct intel_watermark_params
*cursor
)
4398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4400 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4401 " cursor %d\n", level
, display_wm
, fbc_wm
, cursor_wm
);
4403 if (fbc_wm
> SNB_FBC_MAX_SRWM
) {
4404 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
4405 fbc_wm
, SNB_FBC_MAX_SRWM
, level
);
4407 /* fbc has it's own way to disable FBC WM */
4408 I915_WRITE(DISP_ARB_CTL
,
4409 I915_READ(DISP_ARB_CTL
) | DISP_FBC_WM_DIS
);
4413 if (display_wm
> display
->max_wm
) {
4414 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
4415 display_wm
, SNB_DISPLAY_MAX_SRWM
, level
);
4419 if (cursor_wm
> cursor
->max_wm
) {
4420 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
4421 cursor_wm
, SNB_CURSOR_MAX_SRWM
, level
);
4425 if (!(fbc_wm
|| display_wm
|| cursor_wm
)) {
4426 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level
, level
);
4434 * Compute watermark values of WM[1-3],
4436 static bool ironlake_compute_srwm(struct drm_device
*dev
, int level
, int plane
,
4438 const struct intel_watermark_params
*display
,
4439 const struct intel_watermark_params
*cursor
,
4440 int *fbc_wm
, int *display_wm
, int *cursor_wm
)
4442 struct drm_crtc
*crtc
;
4443 unsigned long line_time_us
;
4444 int hdisplay
, htotal
, pixel_size
, clock
;
4445 int line_count
, line_size
;
4450 *fbc_wm
= *display_wm
= *cursor_wm
= 0;
4454 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4455 hdisplay
= crtc
->mode
.hdisplay
;
4456 htotal
= crtc
->mode
.htotal
;
4457 clock
= crtc
->mode
.clock
;
4458 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
4460 line_time_us
= (htotal
* 1000) / clock
;
4461 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
4462 line_size
= hdisplay
* pixel_size
;
4464 /* Use the minimum of the small and large buffer method for primary */
4465 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
4466 large
= line_count
* line_size
;
4468 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
4469 *display_wm
= entries
+ display
->guard_size
;
4473 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4475 *fbc_wm
= DIV_ROUND_UP(*display_wm
* 64, line_size
) + 2;
4477 /* calculate the self-refresh watermark for display cursor */
4478 entries
= line_count
* pixel_size
* 64;
4479 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
4480 *cursor_wm
= entries
+ cursor
->guard_size
;
4482 return ironlake_check_srwm(dev
, level
,
4483 *fbc_wm
, *display_wm
, *cursor_wm
,
4487 static void ironlake_update_wm(struct drm_device
*dev
)
4489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4490 int fbc_wm
, plane_wm
, cursor_wm
;
4491 unsigned int enabled
;
4494 if (g4x_compute_wm0(dev
, 0,
4495 &ironlake_display_wm_info
,
4496 ILK_LP0_PLANE_LATENCY
,
4497 &ironlake_cursor_wm_info
,
4498 ILK_LP0_CURSOR_LATENCY
,
4499 &plane_wm
, &cursor_wm
)) {
4500 I915_WRITE(WM0_PIPEA_ILK
,
4501 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4502 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4503 " plane %d, " "cursor: %d\n",
4504 plane_wm
, cursor_wm
);
4508 if (g4x_compute_wm0(dev
, 1,
4509 &ironlake_display_wm_info
,
4510 ILK_LP0_PLANE_LATENCY
,
4511 &ironlake_cursor_wm_info
,
4512 ILK_LP0_CURSOR_LATENCY
,
4513 &plane_wm
, &cursor_wm
)) {
4514 I915_WRITE(WM0_PIPEB_ILK
,
4515 (plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
);
4516 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4517 " plane %d, cursor: %d\n",
4518 plane_wm
, cursor_wm
);
4523 * Calculate and update the self-refresh watermark only when one
4524 * display plane is used.
4526 I915_WRITE(WM3_LP_ILK
, 0);
4527 I915_WRITE(WM2_LP_ILK
, 0);
4528 I915_WRITE(WM1_LP_ILK
, 0);
4530 if (!single_plane_enabled(enabled
))
4532 enabled
= ffs(enabled
) - 1;
4535 if (!ironlake_compute_srwm(dev
, 1, enabled
,
4536 ILK_READ_WM1_LATENCY() * 500,
4537 &ironlake_display_srwm_info
,
4538 &ironlake_cursor_srwm_info
,
4539 &fbc_wm
, &plane_wm
, &cursor_wm
))
4542 I915_WRITE(WM1_LP_ILK
,
4544 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4545 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4546 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4550 if (!ironlake_compute_srwm(dev
, 2, enabled
,
4551 ILK_READ_WM2_LATENCY() * 500,
4552 &ironlake_display_srwm_info
,
4553 &ironlake_cursor_srwm_info
,
4554 &fbc_wm
, &plane_wm
, &cursor_wm
))
4557 I915_WRITE(WM2_LP_ILK
,
4559 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4560 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4561 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4565 * WM3 is unsupported on ILK, probably because we don't have latency
4566 * data for that power state
4570 void sandybridge_update_wm(struct drm_device
*dev
)
4572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4573 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4575 int fbc_wm
, plane_wm
, cursor_wm
;
4576 unsigned int enabled
;
4579 if (g4x_compute_wm0(dev
, 0,
4580 &sandybridge_display_wm_info
, latency
,
4581 &sandybridge_cursor_wm_info
, latency
,
4582 &plane_wm
, &cursor_wm
)) {
4583 val
= I915_READ(WM0_PIPEA_ILK
);
4584 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
4585 I915_WRITE(WM0_PIPEA_ILK
, val
|
4586 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
4587 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4588 " plane %d, " "cursor: %d\n",
4589 plane_wm
, cursor_wm
);
4593 if (g4x_compute_wm0(dev
, 1,
4594 &sandybridge_display_wm_info
, latency
,
4595 &sandybridge_cursor_wm_info
, latency
,
4596 &plane_wm
, &cursor_wm
)) {
4597 val
= I915_READ(WM0_PIPEB_ILK
);
4598 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
4599 I915_WRITE(WM0_PIPEB_ILK
, val
|
4600 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
4601 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4602 " plane %d, cursor: %d\n",
4603 plane_wm
, cursor_wm
);
4607 /* IVB has 3 pipes */
4608 if (IS_IVYBRIDGE(dev
) &&
4609 g4x_compute_wm0(dev
, 2,
4610 &sandybridge_display_wm_info
, latency
,
4611 &sandybridge_cursor_wm_info
, latency
,
4612 &plane_wm
, &cursor_wm
)) {
4613 val
= I915_READ(WM0_PIPEC_IVB
);
4614 val
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
4615 I915_WRITE(WM0_PIPEC_IVB
, val
|
4616 ((plane_wm
<< WM0_PIPE_PLANE_SHIFT
) | cursor_wm
));
4617 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4618 " plane %d, cursor: %d\n",
4619 plane_wm
, cursor_wm
);
4624 * Calculate and update the self-refresh watermark only when one
4625 * display plane is used.
4627 * SNB support 3 levels of watermark.
4629 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4630 * and disabled in the descending order
4633 I915_WRITE(WM3_LP_ILK
, 0);
4634 I915_WRITE(WM2_LP_ILK
, 0);
4635 I915_WRITE(WM1_LP_ILK
, 0);
4637 if (!single_plane_enabled(enabled
) ||
4638 dev_priv
->sprite_scaling_enabled
)
4640 enabled
= ffs(enabled
) - 1;
4643 if (!ironlake_compute_srwm(dev
, 1, enabled
,
4644 SNB_READ_WM1_LATENCY() * 500,
4645 &sandybridge_display_srwm_info
,
4646 &sandybridge_cursor_srwm_info
,
4647 &fbc_wm
, &plane_wm
, &cursor_wm
))
4650 I915_WRITE(WM1_LP_ILK
,
4652 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4653 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4654 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4658 if (!ironlake_compute_srwm(dev
, 2, enabled
,
4659 SNB_READ_WM2_LATENCY() * 500,
4660 &sandybridge_display_srwm_info
,
4661 &sandybridge_cursor_srwm_info
,
4662 &fbc_wm
, &plane_wm
, &cursor_wm
))
4665 I915_WRITE(WM2_LP_ILK
,
4667 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4668 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4669 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4673 if (!ironlake_compute_srwm(dev
, 3, enabled
,
4674 SNB_READ_WM3_LATENCY() * 500,
4675 &sandybridge_display_srwm_info
,
4676 &sandybridge_cursor_srwm_info
,
4677 &fbc_wm
, &plane_wm
, &cursor_wm
))
4680 I915_WRITE(WM3_LP_ILK
,
4682 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT
) |
4683 (fbc_wm
<< WM1_LP_FBC_SHIFT
) |
4684 (plane_wm
<< WM1_LP_SR_SHIFT
) |
4689 sandybridge_compute_sprite_wm(struct drm_device
*dev
, int plane
,
4690 uint32_t sprite_width
, int pixel_size
,
4691 const struct intel_watermark_params
*display
,
4692 int display_latency_ns
, int *sprite_wm
)
4694 struct drm_crtc
*crtc
;
4696 int entries
, tlb_miss
;
4698 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4699 if (crtc
->fb
== NULL
|| !crtc
->enabled
) {
4700 *sprite_wm
= display
->guard_size
;
4704 clock
= crtc
->mode
.clock
;
4706 /* Use the small buffer method to calculate the sprite watermark */
4707 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
4708 tlb_miss
= display
->fifo_size
*display
->cacheline_size
-
4711 entries
+= tlb_miss
;
4712 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
4713 *sprite_wm
= entries
+ display
->guard_size
;
4714 if (*sprite_wm
> (int)display
->max_wm
)
4715 *sprite_wm
= display
->max_wm
;
4721 sandybridge_compute_sprite_srwm(struct drm_device
*dev
, int plane
,
4722 uint32_t sprite_width
, int pixel_size
,
4723 const struct intel_watermark_params
*display
,
4724 int latency_ns
, int *sprite_wm
)
4726 struct drm_crtc
*crtc
;
4727 unsigned long line_time_us
;
4729 int line_count
, line_size
;
4738 crtc
= intel_get_crtc_for_plane(dev
, plane
);
4739 clock
= crtc
->mode
.clock
;
4745 line_time_us
= (sprite_width
* 1000) / clock
;
4746 if (!line_time_us
) {
4751 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
4752 line_size
= sprite_width
* pixel_size
;
4754 /* Use the minimum of the small and large buffer method for primary */
4755 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
4756 large
= line_count
* line_size
;
4758 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
4759 *sprite_wm
= entries
+ display
->guard_size
;
4761 return *sprite_wm
> 0x3ff ? false : true;
4764 static void sandybridge_update_sprite_wm(struct drm_device
*dev
, int pipe
,
4765 uint32_t sprite_width
, int pixel_size
)
4767 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4768 int latency
= SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4775 reg
= WM0_PIPEA_ILK
;
4778 reg
= WM0_PIPEB_ILK
;
4781 reg
= WM0_PIPEC_IVB
;
4784 return; /* bad pipe */
4787 ret
= sandybridge_compute_sprite_wm(dev
, pipe
, sprite_width
, pixel_size
,
4788 &sandybridge_display_wm_info
,
4789 latency
, &sprite_wm
);
4791 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4796 val
= I915_READ(reg
);
4797 val
&= ~WM0_PIPE_SPRITE_MASK
;
4798 I915_WRITE(reg
, val
| (sprite_wm
<< WM0_PIPE_SPRITE_SHIFT
));
4799 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe
, sprite_wm
);
4802 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
4804 &sandybridge_display_srwm_info
,
4805 SNB_READ_WM1_LATENCY() * 500,
4808 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4812 I915_WRITE(WM1S_LP_ILK
, sprite_wm
);
4814 /* Only IVB has two more LP watermarks for sprite */
4815 if (!IS_IVYBRIDGE(dev
))
4818 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
4820 &sandybridge_display_srwm_info
,
4821 SNB_READ_WM2_LATENCY() * 500,
4824 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4828 I915_WRITE(WM2S_LP_IVB
, sprite_wm
);
4830 ret
= sandybridge_compute_sprite_srwm(dev
, pipe
, sprite_width
,
4832 &sandybridge_display_srwm_info
,
4833 SNB_READ_WM3_LATENCY() * 500,
4836 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4840 I915_WRITE(WM3S_LP_IVB
, sprite_wm
);
4844 * intel_update_watermarks - update FIFO watermark values based on current modes
4846 * Calculate watermark values for the various WM regs based on current mode
4847 * and plane configuration.
4849 * There are several cases to deal with here:
4850 * - normal (i.e. non-self-refresh)
4851 * - self-refresh (SR) mode
4852 * - lines are large relative to FIFO size (buffer can hold up to 2)
4853 * - lines are small relative to FIFO size (buffer can hold more than 2
4854 * lines), so need to account for TLB latency
4856 * The normal calculation is:
4857 * watermark = dotclock * bytes per pixel * latency
4858 * where latency is platform & configuration dependent (we assume pessimal
4861 * The SR calculation is:
4862 * watermark = (trunc(latency/line time)+1) * surface width *
4865 * line time = htotal / dotclock
4866 * surface width = hdisplay for normal plane and 64 for cursor
4867 * and latency is assumed to be high, as above.
4869 * The final value programmed to the register should always be rounded up,
4870 * and include an extra 2 entries to account for clock crossings.
4872 * We don't use the sprite, so we can ignore that. And on Crestline we have
4873 * to set the non-SR watermarks to 8.
4875 static void intel_update_watermarks(struct drm_device
*dev
)
4877 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4879 if (dev_priv
->display
.update_wm
)
4880 dev_priv
->display
.update_wm(dev
);
4883 void intel_update_sprite_watermarks(struct drm_device
*dev
, int pipe
,
4884 uint32_t sprite_width
, int pixel_size
)
4886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4888 if (dev_priv
->display
.update_sprite_wm
)
4889 dev_priv
->display
.update_sprite_wm(dev
, pipe
, sprite_width
,
4893 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4895 if (i915_panel_use_ssc
>= 0)
4896 return i915_panel_use_ssc
!= 0;
4897 return dev_priv
->lvds_use_ssc
4898 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4902 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4903 * @crtc: CRTC structure
4904 * @mode: requested mode
4906 * A pipe may be connected to one or more outputs. Based on the depth of the
4907 * attached framebuffer, choose a good color depth to use on the pipe.
4909 * If possible, match the pipe depth to the fb depth. In some cases, this
4910 * isn't ideal, because the connected output supports a lesser or restricted
4911 * set of depths. Resolve that here:
4912 * LVDS typically supports only 6bpc, so clamp down in that case
4913 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4914 * Displays may support a restricted set as well, check EDID and clamp as
4916 * DP may want to dither down to 6bpc to fit larger modes
4919 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4920 * true if they don't match).
4922 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
4923 unsigned int *pipe_bpp
,
4924 struct drm_display_mode
*mode
)
4926 struct drm_device
*dev
= crtc
->dev
;
4927 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4928 struct drm_encoder
*encoder
;
4929 struct drm_connector
*connector
;
4930 unsigned int display_bpc
= UINT_MAX
, bpc
;
4932 /* Walk the encoders & connectors on this crtc, get min bpc */
4933 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
4934 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
4936 if (encoder
->crtc
!= crtc
)
4939 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
4940 unsigned int lvds_bpc
;
4942 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
4948 if (lvds_bpc
< display_bpc
) {
4949 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
4950 display_bpc
= lvds_bpc
;
4955 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
4956 /* Use VBT settings if we have an eDP panel */
4957 unsigned int edp_bpc
= dev_priv
->edp
.bpp
/ 3;
4959 if (edp_bpc
< display_bpc
) {
4960 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc
, edp_bpc
);
4961 display_bpc
= edp_bpc
;
4966 /* Not one of the known troublemakers, check the EDID */
4967 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
4969 if (connector
->encoder
!= encoder
)
4972 /* Don't use an invalid EDID bpc value */
4973 if (connector
->display_info
.bpc
&&
4974 connector
->display_info
.bpc
< display_bpc
) {
4975 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
4976 display_bpc
= connector
->display_info
.bpc
;
4981 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4982 * through, clamp it down. (Note: >12bpc will be caught below.)
4984 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
4985 if (display_bpc
> 8 && display_bpc
< 12) {
4986 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4989 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4995 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4996 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
5001 * We could just drive the pipe at the highest bpc all the time and
5002 * enable dithering as needed, but that costs bandwidth. So choose
5003 * the minimum value that expresses the full color range of the fb but
5004 * also stays within the max display bpc discovered above.
5007 switch (crtc
->fb
->depth
) {
5009 bpc
= 8; /* since we go through a colormap */
5013 bpc
= 6; /* min is 18bpp */
5025 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5026 bpc
= min((unsigned int)8, display_bpc
);
5030 display_bpc
= min(display_bpc
, bpc
);
5032 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5035 *pipe_bpp
= display_bpc
* 3;
5037 return display_bpc
!= bpc
;
5040 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5042 struct drm_device
*dev
= crtc
->dev
;
5043 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5046 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5047 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5048 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
5049 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5051 } else if (!IS_GEN2(dev
)) {
5060 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
5061 intel_clock_t
*clock
)
5063 /* SDVO TV has fixed PLL values depend on its clock range,
5064 this mirrors vbios setting. */
5065 if (adjusted_mode
->clock
>= 100000
5066 && adjusted_mode
->clock
< 140500) {
5072 } else if (adjusted_mode
->clock
>= 140500
5073 && adjusted_mode
->clock
<= 200000) {
5082 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
5083 intel_clock_t
*clock
,
5084 intel_clock_t
*reduced_clock
)
5086 struct drm_device
*dev
= crtc
->dev
;
5087 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5088 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5089 int pipe
= intel_crtc
->pipe
;
5092 if (IS_PINEVIEW(dev
)) {
5093 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
5095 fp2
= (1 << reduced_clock
->n
) << 16 |
5096 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
5098 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
5100 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
5104 I915_WRITE(FP0(pipe
), fp
);
5106 intel_crtc
->lowfreq_avail
= false;
5107 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5108 reduced_clock
&& i915_powersave
) {
5109 I915_WRITE(FP1(pipe
), fp2
);
5110 intel_crtc
->lowfreq_avail
= true;
5112 I915_WRITE(FP1(pipe
), fp
);
5116 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
5117 struct drm_display_mode
*mode
,
5118 struct drm_display_mode
*adjusted_mode
,
5120 struct drm_framebuffer
*old_fb
)
5122 struct drm_device
*dev
= crtc
->dev
;
5123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5124 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5125 int pipe
= intel_crtc
->pipe
;
5126 int plane
= intel_crtc
->plane
;
5127 int refclk
, num_connectors
= 0;
5128 intel_clock_t clock
, reduced_clock
;
5129 u32 dpll
, dspcntr
, pipeconf
, vsyncshift
;
5130 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
5131 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
5132 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5133 struct intel_encoder
*encoder
;
5134 const intel_limit_t
*limit
;
5139 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5140 if (encoder
->base
.crtc
!= crtc
)
5143 switch (encoder
->type
) {
5144 case INTEL_OUTPUT_LVDS
:
5147 case INTEL_OUTPUT_SDVO
:
5148 case INTEL_OUTPUT_HDMI
:
5150 if (encoder
->needs_tv_clock
)
5153 case INTEL_OUTPUT_DVO
:
5156 case INTEL_OUTPUT_TVOUT
:
5159 case INTEL_OUTPUT_ANALOG
:
5162 case INTEL_OUTPUT_DISPLAYPORT
:
5170 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
5173 * Returns a set of divisors for the desired target clock with the given
5174 * refclk, or FALSE. The returned values represent the clock equation:
5175 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5177 limit
= intel_limit(crtc
, refclk
);
5178 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5181 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5185 /* Ensure that the cursor is valid for the new mode before changing... */
5186 intel_crtc_update_cursor(crtc
, true);
5188 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5190 * Ensure we match the reduced clock's P to the target clock.
5191 * If the clocks don't match, we can't switch the display clock
5192 * by using the FP0/FP1. In such case we will disable the LVDS
5193 * downclock feature.
5195 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5196 dev_priv
->lvds_downclock
,
5202 if (is_sdvo
&& is_tv
)
5203 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
5205 i9xx_update_pll_dividers(crtc
, &clock
, has_reduced_clock
?
5206 &reduced_clock
: NULL
);
5208 dpll
= DPLL_VGA_MODE_DIS
;
5210 if (!IS_GEN2(dev
)) {
5212 dpll
|= DPLLB_MODE_LVDS
;
5214 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5216 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5217 if (pixel_multiplier
> 1) {
5218 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
5219 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
5221 dpll
|= DPLL_DVO_HIGH_SPEED
;
5224 dpll
|= DPLL_DVO_HIGH_SPEED
;
5226 /* compute bitmask from p1 value */
5227 if (IS_PINEVIEW(dev
))
5228 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5230 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5231 if (IS_G4X(dev
) && has_reduced_clock
)
5232 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5236 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5239 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5242 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5245 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5248 if (INTEL_INFO(dev
)->gen
>= 4)
5249 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5252 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5255 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5257 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5259 dpll
|= PLL_P2_DIVIDE_BY_4
;
5263 if (is_sdvo
&& is_tv
)
5264 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5266 /* XXX: just matching BIOS for now */
5267 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5269 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5270 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5272 dpll
|= PLL_REF_INPUT_DREFCLK
;
5274 /* setup pipeconf */
5275 pipeconf
= I915_READ(PIPECONF(pipe
));
5277 /* Set up the display plane register */
5278 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5281 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5283 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5285 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
5286 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5289 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5293 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
5294 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
5296 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
5299 /* default to 8bpc */
5300 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
5302 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
5303 pipeconf
|= PIPECONF_BPP_6
|
5304 PIPECONF_DITHER_EN
|
5305 PIPECONF_DITHER_TYPE_SP
;
5309 dpll
|= DPLL_VCO_ENABLE
;
5311 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
5312 drm_mode_debug_printmodeline(mode
);
5314 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
5316 POSTING_READ(DPLL(pipe
));
5319 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5320 * This is an exception to the general rule that mode_set doesn't turn
5324 temp
= I915_READ(LVDS
);
5325 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5327 temp
|= LVDS_PIPEB_SELECT
;
5329 temp
&= ~LVDS_PIPEB_SELECT
;
5331 /* set the corresponsding LVDS_BORDER bit */
5332 temp
|= dev_priv
->lvds_border_bits
;
5333 /* Set the B0-B3 data pairs corresponding to whether we're going to
5334 * set the DPLLs for dual-channel mode or not.
5337 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5339 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
5341 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5342 * appropriately here, but we need to look more thoroughly into how
5343 * panels behave in the two modes.
5345 /* set the dithering flag on LVDS as needed */
5346 if (INTEL_INFO(dev
)->gen
>= 4) {
5347 if (dev_priv
->lvds_dither
)
5348 temp
|= LVDS_ENABLE_DITHER
;
5350 temp
&= ~LVDS_ENABLE_DITHER
;
5352 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5353 lvds_sync
|= LVDS_HSYNC_POLARITY
;
5354 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5355 lvds_sync
|= LVDS_VSYNC_POLARITY
;
5356 if ((temp
& (LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
))
5358 char flags
[2] = "-+";
5359 DRM_INFO("Changing LVDS panel from "
5360 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5361 flags
[!(temp
& LVDS_HSYNC_POLARITY
)],
5362 flags
[!(temp
& LVDS_VSYNC_POLARITY
)],
5363 flags
[!(lvds_sync
& LVDS_HSYNC_POLARITY
)],
5364 flags
[!(lvds_sync
& LVDS_VSYNC_POLARITY
)]);
5365 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5368 I915_WRITE(LVDS
, temp
);
5372 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5375 I915_WRITE(DPLL(pipe
), dpll
);
5377 /* Wait for the clocks to stabilize. */
5378 POSTING_READ(DPLL(pipe
));
5381 if (INTEL_INFO(dev
)->gen
>= 4) {
5384 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5386 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5390 I915_WRITE(DPLL_MD(pipe
), temp
);
5392 /* The pixel multiplier can only be updated once the
5393 * DPLL is enabled and the clocks are stable.
5395 * So write it again.
5397 I915_WRITE(DPLL(pipe
), dpll
);
5400 if (HAS_PIPE_CXSR(dev
)) {
5401 if (intel_crtc
->lowfreq_avail
) {
5402 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5403 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5405 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5406 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
5410 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
5411 if (!IS_GEN2(dev
) &&
5412 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5413 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
5414 /* the chip adds 2 halflines automatically */
5415 adjusted_mode
->crtc_vtotal
-= 1;
5416 adjusted_mode
->crtc_vblank_end
-= 1;
5417 vsyncshift
= adjusted_mode
->crtc_hsync_start
5418 - adjusted_mode
->crtc_htotal
/2;
5420 pipeconf
|= PIPECONF_PROGRESSIVE
;
5425 I915_WRITE(VSYNCSHIFT(pipe
), vsyncshift
);
5427 I915_WRITE(HTOTAL(pipe
),
5428 (adjusted_mode
->crtc_hdisplay
- 1) |
5429 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5430 I915_WRITE(HBLANK(pipe
),
5431 (adjusted_mode
->crtc_hblank_start
- 1) |
5432 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5433 I915_WRITE(HSYNC(pipe
),
5434 (adjusted_mode
->crtc_hsync_start
- 1) |
5435 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5437 I915_WRITE(VTOTAL(pipe
),
5438 (adjusted_mode
->crtc_vdisplay
- 1) |
5439 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
5440 I915_WRITE(VBLANK(pipe
),
5441 (adjusted_mode
->crtc_vblank_start
- 1) |
5442 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
5443 I915_WRITE(VSYNC(pipe
),
5444 (adjusted_mode
->crtc_vsync_start
- 1) |
5445 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5447 /* pipesrc and dspsize control the size that is scaled from,
5448 * which should always be the user's requested size.
5450 I915_WRITE(DSPSIZE(plane
),
5451 ((mode
->vdisplay
- 1) << 16) |
5452 (mode
->hdisplay
- 1));
5453 I915_WRITE(DSPPOS(plane
), 0);
5454 I915_WRITE(PIPESRC(pipe
),
5455 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
5457 I915_WRITE(PIPECONF(pipe
), pipeconf
);
5458 POSTING_READ(PIPECONF(pipe
));
5459 intel_enable_pipe(dev_priv
, pipe
, false);
5461 intel_wait_for_vblank(dev
, pipe
);
5463 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5464 POSTING_READ(DSPCNTR(plane
));
5465 intel_enable_plane(dev_priv
, plane
, pipe
);
5467 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
5469 intel_update_watermarks(dev
);
5475 * Initialize reference clocks when the driver loads
5477 void ironlake_init_pch_refclk(struct drm_device
*dev
)
5479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5480 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5481 struct intel_encoder
*encoder
;
5483 bool has_lvds
= false;
5484 bool has_cpu_edp
= false;
5485 bool has_pch_edp
= false;
5486 bool has_panel
= false;
5487 bool has_ck505
= false;
5488 bool can_ssc
= false;
5490 /* We need to take the global config into account */
5491 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5493 switch (encoder
->type
) {
5494 case INTEL_OUTPUT_LVDS
:
5498 case INTEL_OUTPUT_EDP
:
5500 if (intel_encoder_is_pch_edp(&encoder
->base
))
5508 if (HAS_PCH_IBX(dev
)) {
5509 has_ck505
= dev_priv
->display_clock_mode
;
5510 can_ssc
= has_ck505
;
5516 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5517 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
5520 /* Ironlake: try to setup display ref clock before DPLL
5521 * enabling. This is only under driver's control after
5522 * PCH B stepping, previous chipset stepping should be
5523 * ignoring this setting.
5525 temp
= I915_READ(PCH_DREF_CONTROL
);
5526 /* Always enable nonspread source */
5527 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5530 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
5532 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5535 temp
&= ~DREF_SSC_SOURCE_MASK
;
5536 temp
|= DREF_SSC_SOURCE_ENABLE
;
5538 /* SSC must be turned on before enabling the CPU output */
5539 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5540 DRM_DEBUG_KMS("Using SSC on panel\n");
5541 temp
|= DREF_SSC1_ENABLE
;
5544 /* Get SSC going before enabling the outputs */
5545 I915_WRITE(PCH_DREF_CONTROL
, temp
);
5546 POSTING_READ(PCH_DREF_CONTROL
);
5549 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5551 /* Enable CPU source on CPU attached eDP */
5553 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5554 DRM_DEBUG_KMS("Using SSC on eDP\n");
5555 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5558 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5560 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5562 I915_WRITE(PCH_DREF_CONTROL
, temp
);
5563 POSTING_READ(PCH_DREF_CONTROL
);
5566 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5568 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5570 /* Turn off CPU output */
5571 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5573 I915_WRITE(PCH_DREF_CONTROL
, temp
);
5574 POSTING_READ(PCH_DREF_CONTROL
);
5577 /* Turn off the SSC source */
5578 temp
&= ~DREF_SSC_SOURCE_MASK
;
5579 temp
|= DREF_SSC_SOURCE_DISABLE
;
5582 temp
&= ~ DREF_SSC1_ENABLE
;
5584 I915_WRITE(PCH_DREF_CONTROL
, temp
);
5585 POSTING_READ(PCH_DREF_CONTROL
);
5590 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5592 struct drm_device
*dev
= crtc
->dev
;
5593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5594 struct intel_encoder
*encoder
;
5595 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5596 struct intel_encoder
*edp_encoder
= NULL
;
5597 int num_connectors
= 0;
5598 bool is_lvds
= false;
5600 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5601 if (encoder
->base
.crtc
!= crtc
)
5604 switch (encoder
->type
) {
5605 case INTEL_OUTPUT_LVDS
:
5608 case INTEL_OUTPUT_EDP
:
5609 edp_encoder
= encoder
;
5615 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5616 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5617 dev_priv
->lvds_ssc_freq
);
5618 return dev_priv
->lvds_ssc_freq
* 1000;
5624 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5625 struct drm_display_mode
*mode
,
5626 struct drm_display_mode
*adjusted_mode
,
5628 struct drm_framebuffer
*old_fb
)
5630 struct drm_device
*dev
= crtc
->dev
;
5631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5632 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5633 int pipe
= intel_crtc
->pipe
;
5634 int plane
= intel_crtc
->plane
;
5635 int refclk
, num_connectors
= 0;
5636 intel_clock_t clock
, reduced_clock
;
5637 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
5638 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
5639 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
5640 struct intel_encoder
*has_edp_encoder
= NULL
;
5641 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5642 struct intel_encoder
*encoder
;
5643 const intel_limit_t
*limit
;
5645 struct fdi_m_n m_n
= {0};
5648 int target_clock
, pixel_multiplier
, lane
, link_bw
, factor
;
5649 unsigned int pipe_bpp
;
5652 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5653 if (encoder
->base
.crtc
!= crtc
)
5656 switch (encoder
->type
) {
5657 case INTEL_OUTPUT_LVDS
:
5660 case INTEL_OUTPUT_SDVO
:
5661 case INTEL_OUTPUT_HDMI
:
5663 if (encoder
->needs_tv_clock
)
5666 case INTEL_OUTPUT_TVOUT
:
5669 case INTEL_OUTPUT_ANALOG
:
5672 case INTEL_OUTPUT_DISPLAYPORT
:
5675 case INTEL_OUTPUT_EDP
:
5676 has_edp_encoder
= encoder
;
5683 refclk
= ironlake_get_refclk(crtc
);
5686 * Returns a set of divisors for the desired target clock with the given
5687 * refclk, or FALSE. The returned values represent the clock equation:
5688 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5690 limit
= intel_limit(crtc
, refclk
);
5691 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5694 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5698 /* Ensure that the cursor is valid for the new mode before changing... */
5699 intel_crtc_update_cursor(crtc
, true);
5701 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5703 * Ensure we match the reduced clock's P to the target clock.
5704 * If the clocks don't match, we can't switch the display clock
5705 * by using the FP0/FP1. In such case we will disable the LVDS
5706 * downclock feature.
5708 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5709 dev_priv
->lvds_downclock
,
5714 /* SDVO TV has fixed PLL values depend on its clock range,
5715 this mirrors vbios setting. */
5716 if (is_sdvo
&& is_tv
) {
5717 if (adjusted_mode
->clock
>= 100000
5718 && adjusted_mode
->clock
< 140500) {
5724 } else if (adjusted_mode
->clock
>= 140500
5725 && adjusted_mode
->clock
<= 200000) {
5735 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5737 /* CPU eDP doesn't require FDI link, so just set DP M/N
5738 according to current link config */
5739 if (has_edp_encoder
&&
5740 !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5741 target_clock
= mode
->clock
;
5742 intel_edp_link_config(has_edp_encoder
,
5745 /* [e]DP over FDI requires target mode clock
5746 instead of link clock */
5747 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
5748 target_clock
= mode
->clock
;
5750 target_clock
= adjusted_mode
->clock
;
5752 /* FDI is a binary signal running at ~2.7GHz, encoding
5753 * each output octet as 10 bits. The actual frequency
5754 * is stored as a divider into a 100MHz clock, and the
5755 * mode pixel clock is stored in units of 1KHz.
5756 * Hence the bw of each lane in terms of the mode signal
5759 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5762 /* determine panel color depth */
5763 temp
= I915_READ(PIPECONF(pipe
));
5764 temp
&= ~PIPE_BPC_MASK
;
5765 dither
= intel_choose_pipe_bpp_dither(crtc
, &pipe_bpp
, mode
);
5780 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5787 intel_crtc
->bpp
= pipe_bpp
;
5788 I915_WRITE(PIPECONF(pipe
), temp
);
5792 * Account for spread spectrum to avoid
5793 * oversubscribing the link. Max center spread
5794 * is 2.5%; use 5% for safety's sake.
5796 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
5797 lane
= bps
/ (link_bw
* 8) + 1;
5800 intel_crtc
->fdi_lanes
= lane
;
5802 if (pixel_multiplier
> 1)
5803 link_bw
*= pixel_multiplier
;
5804 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
5807 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5808 if (has_reduced_clock
)
5809 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5812 /* Enable autotuning of the PLL clock (if permissible) */
5815 if ((intel_panel_use_ssc(dev_priv
) &&
5816 dev_priv
->lvds_ssc_freq
== 100) ||
5817 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
5819 } else if (is_sdvo
&& is_tv
)
5822 if (clock
.m
< factor
* clock
.n
)
5828 dpll
|= DPLLB_MODE_LVDS
;
5830 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5832 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5833 if (pixel_multiplier
> 1) {
5834 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5836 dpll
|= DPLL_DVO_HIGH_SPEED
;
5838 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
))
5839 dpll
|= DPLL_DVO_HIGH_SPEED
;
5841 /* compute bitmask from p1 value */
5842 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5844 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5848 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5851 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5854 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5857 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5861 if (is_sdvo
&& is_tv
)
5862 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5864 /* XXX: just matching BIOS for now */
5865 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5867 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5868 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5870 dpll
|= PLL_REF_INPUT_DREFCLK
;
5872 /* setup pipeconf */
5873 pipeconf
= I915_READ(PIPECONF(pipe
));
5875 /* Set up the display plane register */
5876 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5878 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5879 drm_mode_debug_printmodeline(mode
);
5881 /* PCH eDP needs FDI, but CPU eDP does not */
5882 if (!intel_crtc
->no_pll
) {
5883 if (!has_edp_encoder
||
5884 intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5885 I915_WRITE(PCH_FP0(pipe
), fp
);
5886 I915_WRITE(PCH_DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
5888 POSTING_READ(PCH_DPLL(pipe
));
5892 if (dpll
== (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5893 fp
== I915_READ(PCH_FP0(0))) {
5894 intel_crtc
->use_pll_a
= true;
5895 DRM_DEBUG_KMS("using pipe a dpll\n");
5896 } else if (dpll
== (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5897 fp
== I915_READ(PCH_FP0(1))) {
5898 intel_crtc
->use_pll_a
= false;
5899 DRM_DEBUG_KMS("using pipe b dpll\n");
5901 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5906 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5907 * This is an exception to the general rule that mode_set doesn't turn
5911 temp
= I915_READ(PCH_LVDS
);
5912 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5913 if (HAS_PCH_CPT(dev
)) {
5914 temp
&= ~PORT_TRANS_SEL_MASK
;
5915 temp
|= PORT_TRANS_SEL_CPT(pipe
);
5918 temp
|= LVDS_PIPEB_SELECT
;
5920 temp
&= ~LVDS_PIPEB_SELECT
;
5923 /* set the corresponsding LVDS_BORDER bit */
5924 temp
|= dev_priv
->lvds_border_bits
;
5925 /* Set the B0-B3 data pairs corresponding to whether we're going to
5926 * set the DPLLs for dual-channel mode or not.
5929 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5931 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
5933 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5934 * appropriately here, but we need to look more thoroughly into how
5935 * panels behave in the two modes.
5937 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5938 lvds_sync
|= LVDS_HSYNC_POLARITY
;
5939 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5940 lvds_sync
|= LVDS_VSYNC_POLARITY
;
5941 if ((temp
& (LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
))
5943 char flags
[2] = "-+";
5944 DRM_INFO("Changing LVDS panel from "
5945 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5946 flags
[!(temp
& LVDS_HSYNC_POLARITY
)],
5947 flags
[!(temp
& LVDS_VSYNC_POLARITY
)],
5948 flags
[!(lvds_sync
& LVDS_HSYNC_POLARITY
)],
5949 flags
[!(lvds_sync
& LVDS_VSYNC_POLARITY
)]);
5950 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5953 I915_WRITE(PCH_LVDS
, temp
);
5956 pipeconf
&= ~PIPECONF_DITHER_EN
;
5957 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
5958 if ((is_lvds
&& dev_priv
->lvds_dither
) || dither
) {
5959 pipeconf
|= PIPECONF_DITHER_EN
;
5960 pipeconf
|= PIPECONF_DITHER_TYPE_SP
;
5962 if (is_dp
|| intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
5963 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5965 /* For non-DP output, clear any trans DP clock recovery setting.*/
5966 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5967 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5968 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5969 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5972 if (!intel_crtc
->no_pll
&&
5973 (!has_edp_encoder
||
5974 intel_encoder_is_pch_edp(&has_edp_encoder
->base
))) {
5975 I915_WRITE(PCH_DPLL(pipe
), dpll
);
5977 /* Wait for the clocks to stabilize. */
5978 POSTING_READ(PCH_DPLL(pipe
));
5981 /* The pixel multiplier can only be updated once the
5982 * DPLL is enabled and the clocks are stable.
5984 * So write it again.
5986 I915_WRITE(PCH_DPLL(pipe
), dpll
);
5989 intel_crtc
->lowfreq_avail
= false;
5990 if (!intel_crtc
->no_pll
) {
5991 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5992 I915_WRITE(PCH_FP1(pipe
), fp2
);
5993 intel_crtc
->lowfreq_avail
= true;
5994 if (HAS_PIPE_CXSR(dev
)) {
5995 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5996 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
5999 I915_WRITE(PCH_FP1(pipe
), fp
);
6000 if (HAS_PIPE_CXSR(dev
)) {
6001 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6002 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
6007 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
6008 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6009 pipeconf
|= PIPECONF_INTERLACED_ILK
;
6010 /* the chip adds 2 halflines automatically */
6011 adjusted_mode
->crtc_vtotal
-= 1;
6012 adjusted_mode
->crtc_vblank_end
-= 1;
6013 I915_WRITE(VSYNCSHIFT(pipe
),
6014 adjusted_mode
->crtc_hsync_start
6015 - adjusted_mode
->crtc_htotal
/2);
6017 pipeconf
|= PIPECONF_PROGRESSIVE
;
6018 I915_WRITE(VSYNCSHIFT(pipe
), 0);
6021 I915_WRITE(HTOTAL(pipe
),
6022 (adjusted_mode
->crtc_hdisplay
- 1) |
6023 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6024 I915_WRITE(HBLANK(pipe
),
6025 (adjusted_mode
->crtc_hblank_start
- 1) |
6026 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6027 I915_WRITE(HSYNC(pipe
),
6028 (adjusted_mode
->crtc_hsync_start
- 1) |
6029 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6031 I915_WRITE(VTOTAL(pipe
),
6032 (adjusted_mode
->crtc_vdisplay
- 1) |
6033 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
6034 I915_WRITE(VBLANK(pipe
),
6035 (adjusted_mode
->crtc_vblank_start
- 1) |
6036 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
6037 I915_WRITE(VSYNC(pipe
),
6038 (adjusted_mode
->crtc_vsync_start
- 1) |
6039 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6041 /* pipesrc controls the size that is scaled from, which should
6042 * always be the user's requested size.
6044 I915_WRITE(PIPESRC(pipe
),
6045 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
6047 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
6048 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
6049 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
6050 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
6052 if (has_edp_encoder
&&
6053 !intel_encoder_is_pch_edp(&has_edp_encoder
->base
)) {
6054 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
6057 I915_WRITE(PIPECONF(pipe
), pipeconf
);
6058 POSTING_READ(PIPECONF(pipe
));
6060 intel_wait_for_vblank(dev
, pipe
);
6062 I915_WRITE(DSPCNTR(plane
), dspcntr
);
6063 POSTING_READ(DSPCNTR(plane
));
6065 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
6067 intel_update_watermarks(dev
);
6072 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6073 struct drm_display_mode
*mode
,
6074 struct drm_display_mode
*adjusted_mode
,
6076 struct drm_framebuffer
*old_fb
)
6078 struct drm_device
*dev
= crtc
->dev
;
6079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6080 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6081 int pipe
= intel_crtc
->pipe
;
6084 drm_vblank_pre_modeset(dev
, pipe
);
6086 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
6088 drm_vblank_post_modeset(dev
, pipe
);
6091 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
6093 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_ON
;
6098 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6099 int reg_eldv
, uint32_t bits_eldv
,
6100 int reg_elda
, uint32_t bits_elda
,
6103 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6104 uint8_t *eld
= connector
->eld
;
6107 i
= I915_READ(reg_eldv
);
6116 i
= I915_READ(reg_elda
);
6118 I915_WRITE(reg_elda
, i
);
6120 for (i
= 0; i
< eld
[2]; i
++)
6121 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6127 static void g4x_write_eld(struct drm_connector
*connector
,
6128 struct drm_crtc
*crtc
)
6130 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6131 uint8_t *eld
= connector
->eld
;
6136 i
= I915_READ(G4X_AUD_VID_DID
);
6138 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6139 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6141 eldv
= G4X_ELDV_DEVCTG
;
6143 if (intel_eld_uptodate(connector
,
6144 G4X_AUD_CNTL_ST
, eldv
,
6145 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6146 G4X_HDMIW_HDMIEDID
))
6149 i
= I915_READ(G4X_AUD_CNTL_ST
);
6150 i
&= ~(eldv
| G4X_ELD_ADDR
);
6151 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6152 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6157 len
= min_t(uint8_t, eld
[2], len
);
6158 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6159 for (i
= 0; i
< len
; i
++)
6160 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6162 i
= I915_READ(G4X_AUD_CNTL_ST
);
6164 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6167 static void ironlake_write_eld(struct drm_connector
*connector
,
6168 struct drm_crtc
*crtc
)
6170 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6171 uint8_t *eld
= connector
->eld
;
6180 if (HAS_PCH_IBX(connector
->dev
)) {
6181 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID_A
;
6182 aud_config
= IBX_AUD_CONFIG_A
;
6183 aud_cntl_st
= IBX_AUD_CNTL_ST_A
;
6184 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6186 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID_A
;
6187 aud_config
= CPT_AUD_CONFIG_A
;
6188 aud_cntl_st
= CPT_AUD_CNTL_ST_A
;
6189 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6192 i
= to_intel_crtc(crtc
)->pipe
;
6193 hdmiw_hdmiedid
+= i
* 0x100;
6194 aud_cntl_st
+= i
* 0x100;
6195 aud_config
+= i
* 0x100;
6197 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i
));
6199 i
= I915_READ(aud_cntl_st
);
6200 i
= (i
>> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6202 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6203 /* operate blindly on all ports */
6204 eldv
= IBX_ELD_VALIDB
;
6205 eldv
|= IBX_ELD_VALIDB
<< 4;
6206 eldv
|= IBX_ELD_VALIDB
<< 8;
6208 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
6209 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6212 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6213 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6214 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6215 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6217 I915_WRITE(aud_config
, 0);
6219 if (intel_eld_uptodate(connector
,
6220 aud_cntrl_st2
, eldv
,
6221 aud_cntl_st
, IBX_ELD_ADDRESS
,
6225 i
= I915_READ(aud_cntrl_st2
);
6227 I915_WRITE(aud_cntrl_st2
, i
);
6232 i
= I915_READ(aud_cntl_st
);
6233 i
&= ~IBX_ELD_ADDRESS
;
6234 I915_WRITE(aud_cntl_st
, i
);
6236 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6237 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6238 for (i
= 0; i
< len
; i
++)
6239 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6241 i
= I915_READ(aud_cntrl_st2
);
6243 I915_WRITE(aud_cntrl_st2
, i
);
6246 void intel_write_eld(struct drm_encoder
*encoder
,
6247 struct drm_display_mode
*mode
)
6249 struct drm_crtc
*crtc
= encoder
->crtc
;
6250 struct drm_connector
*connector
;
6251 struct drm_device
*dev
= encoder
->dev
;
6252 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6254 connector
= drm_select_eld(encoder
, mode
);
6258 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6260 drm_get_connector_name(connector
),
6261 connector
->encoder
->base
.id
,
6262 drm_get_encoder_name(connector
->encoder
));
6264 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6266 if (dev_priv
->display
.write_eld
)
6267 dev_priv
->display
.write_eld(connector
, crtc
);
6270 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6271 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
6273 struct drm_device
*dev
= crtc
->dev
;
6274 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6275 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6276 int palreg
= PALETTE(intel_crtc
->pipe
);
6279 /* The clocks have to be on to load the palette. */
6280 if (!crtc
->enabled
|| !intel_crtc
->active
)
6283 /* use legacy palette for Ironlake */
6284 if (HAS_PCH_SPLIT(dev
))
6285 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
6287 for (i
= 0; i
< 256; i
++) {
6288 I915_WRITE(palreg
+ 4 * i
,
6289 (intel_crtc
->lut_r
[i
] << 16) |
6290 (intel_crtc
->lut_g
[i
] << 8) |
6291 intel_crtc
->lut_b
[i
]);
6295 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6297 struct drm_device
*dev
= crtc
->dev
;
6298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6299 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6300 bool visible
= base
!= 0;
6303 if (intel_crtc
->cursor_visible
== visible
)
6306 cntl
= I915_READ(_CURACNTR
);
6308 /* On these chipsets we can only modify the base whilst
6309 * the cursor is disabled.
6311 I915_WRITE(_CURABASE
, base
);
6313 cntl
&= ~(CURSOR_FORMAT_MASK
);
6314 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6315 cntl
|= CURSOR_ENABLE
|
6316 CURSOR_GAMMA_ENABLE
|
6319 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6320 I915_WRITE(_CURACNTR
, cntl
);
6322 intel_crtc
->cursor_visible
= visible
;
6325 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6327 struct drm_device
*dev
= crtc
->dev
;
6328 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6329 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6330 int pipe
= intel_crtc
->pipe
;
6331 bool visible
= base
!= 0;
6333 if (intel_crtc
->cursor_visible
!= visible
) {
6334 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6336 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6337 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6338 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6340 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6341 cntl
|= CURSOR_MODE_DISABLE
;
6343 I915_WRITE(CURCNTR(pipe
), cntl
);
6345 intel_crtc
->cursor_visible
= visible
;
6347 /* and commit changes on next vblank */
6348 I915_WRITE(CURBASE(pipe
), base
);
6351 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6353 struct drm_device
*dev
= crtc
->dev
;
6354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6355 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6356 int pipe
= intel_crtc
->pipe
;
6357 bool visible
= base
!= 0;
6359 if (intel_crtc
->cursor_visible
!= visible
) {
6360 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6362 cntl
&= ~CURSOR_MODE
;
6363 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6365 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6366 cntl
|= CURSOR_MODE_DISABLE
;
6368 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6370 intel_crtc
->cursor_visible
= visible
;
6372 /* and commit changes on next vblank */
6373 I915_WRITE(CURBASE_IVB(pipe
), base
);
6376 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6377 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6380 struct drm_device
*dev
= crtc
->dev
;
6381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6382 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6383 int pipe
= intel_crtc
->pipe
;
6384 int x
= intel_crtc
->cursor_x
;
6385 int y
= intel_crtc
->cursor_y
;
6391 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6392 base
= intel_crtc
->cursor_addr
;
6393 if (x
> (int) crtc
->fb
->width
)
6396 if (y
> (int) crtc
->fb
->height
)
6402 if (x
+ intel_crtc
->cursor_width
< 0)
6405 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6408 pos
|= x
<< CURSOR_X_SHIFT
;
6411 if (y
+ intel_crtc
->cursor_height
< 0)
6414 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6417 pos
|= y
<< CURSOR_Y_SHIFT
;
6419 visible
= base
!= 0;
6420 if (!visible
&& !intel_crtc
->cursor_visible
)
6423 if (IS_IVYBRIDGE(dev
)) {
6424 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6425 ivb_update_cursor(crtc
, base
);
6427 I915_WRITE(CURPOS(pipe
), pos
);
6428 if (IS_845G(dev
) || IS_I865G(dev
))
6429 i845_update_cursor(crtc
, base
);
6431 i9xx_update_cursor(crtc
, base
);
6435 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
6438 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6439 struct drm_file
*file
,
6441 uint32_t width
, uint32_t height
)
6443 struct drm_device
*dev
= crtc
->dev
;
6444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6445 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6446 struct drm_i915_gem_object
*obj
;
6450 DRM_DEBUG_KMS("\n");
6452 /* if we want to turn off the cursor ignore width and height */
6454 DRM_DEBUG_KMS("cursor off\n");
6457 mutex_lock(&dev
->struct_mutex
);
6461 /* Currently we only support 64x64 cursors */
6462 if (width
!= 64 || height
!= 64) {
6463 DRM_ERROR("we currently only support 64x64 cursors\n");
6467 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6468 if (&obj
->base
== NULL
)
6471 if (obj
->base
.size
< width
* height
* 4) {
6472 DRM_ERROR("buffer is to small\n");
6477 /* we only need to pin inside GTT if cursor is non-phy */
6478 mutex_lock(&dev
->struct_mutex
);
6479 if (!dev_priv
->info
->cursor_needs_physical
) {
6480 if (obj
->tiling_mode
) {
6481 DRM_ERROR("cursor cannot be tiled\n");
6486 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
6488 DRM_ERROR("failed to move cursor bo into the GTT\n");
6492 ret
= i915_gem_object_put_fence(obj
);
6494 DRM_ERROR("failed to release fence for cursor");
6498 addr
= obj
->gtt_offset
;
6500 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6501 ret
= i915_gem_attach_phys_object(dev
, obj
,
6502 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6505 DRM_ERROR("failed to attach phys object\n");
6508 addr
= obj
->phys_obj
->handle
->busaddr
;
6512 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6515 if (intel_crtc
->cursor_bo
) {
6516 if (dev_priv
->info
->cursor_needs_physical
) {
6517 if (intel_crtc
->cursor_bo
!= obj
)
6518 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6520 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6521 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6524 mutex_unlock(&dev
->struct_mutex
);
6526 intel_crtc
->cursor_addr
= addr
;
6527 intel_crtc
->cursor_bo
= obj
;
6528 intel_crtc
->cursor_width
= width
;
6529 intel_crtc
->cursor_height
= height
;
6531 intel_crtc_update_cursor(crtc
, true);
6535 i915_gem_object_unpin(obj
);
6537 mutex_unlock(&dev
->struct_mutex
);
6539 drm_gem_object_unreference_unlocked(&obj
->base
);
6543 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6545 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6547 intel_crtc
->cursor_x
= x
;
6548 intel_crtc
->cursor_y
= y
;
6550 intel_crtc_update_cursor(crtc
, true);
6555 /** Sets the color ramps on behalf of RandR */
6556 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6557 u16 blue
, int regno
)
6559 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6561 intel_crtc
->lut_r
[regno
] = red
>> 8;
6562 intel_crtc
->lut_g
[regno
] = green
>> 8;
6563 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6566 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6567 u16
*blue
, int regno
)
6569 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6571 *red
= intel_crtc
->lut_r
[regno
] << 8;
6572 *green
= intel_crtc
->lut_g
[regno
] << 8;
6573 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6576 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6577 u16
*blue
, uint32_t start
, uint32_t size
)
6579 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6580 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6582 for (i
= start
; i
< end
; i
++) {
6583 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6584 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6585 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6588 intel_crtc_load_lut(crtc
);
6592 * Get a pipe with a simple mode set on it for doing load-based monitor
6595 * It will be up to the load-detect code to adjust the pipe as appropriate for
6596 * its requirements. The pipe will be connected to no other encoders.
6598 * Currently this code will only succeed if there is a pipe with no encoders
6599 * configured for it. In the future, it could choose to temporarily disable
6600 * some outputs to free up a pipe for its use.
6602 * \return crtc, or NULL if no pipes are available.
6605 /* VESA 640x480x72Hz mode to set on the pipe */
6606 static struct drm_display_mode load_detect_mode
= {
6607 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6608 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6611 static struct drm_framebuffer
*
6612 intel_framebuffer_create(struct drm_device
*dev
,
6613 struct drm_mode_fb_cmd2
*mode_cmd
,
6614 struct drm_i915_gem_object
*obj
)
6616 struct intel_framebuffer
*intel_fb
;
6619 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6621 drm_gem_object_unreference_unlocked(&obj
->base
);
6622 return ERR_PTR(-ENOMEM
);
6625 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6627 drm_gem_object_unreference_unlocked(&obj
->base
);
6629 return ERR_PTR(ret
);
6632 return &intel_fb
->base
;
6636 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6638 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6639 return ALIGN(pitch
, 64);
6643 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6645 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6646 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6649 static struct drm_framebuffer
*
6650 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6651 struct drm_display_mode
*mode
,
6654 struct drm_i915_gem_object
*obj
;
6655 struct drm_mode_fb_cmd2 mode_cmd
;
6657 obj
= i915_gem_alloc_object(dev
,
6658 intel_framebuffer_size_for_mode(mode
, bpp
));
6660 return ERR_PTR(-ENOMEM
);
6662 mode_cmd
.width
= mode
->hdisplay
;
6663 mode_cmd
.height
= mode
->vdisplay
;
6664 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6666 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6668 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6671 static struct drm_framebuffer
*
6672 mode_fits_in_fbdev(struct drm_device
*dev
,
6673 struct drm_display_mode
*mode
)
6675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6676 struct drm_i915_gem_object
*obj
;
6677 struct drm_framebuffer
*fb
;
6679 if (dev_priv
->fbdev
== NULL
)
6682 obj
= dev_priv
->fbdev
->ifb
.obj
;
6686 fb
= &dev_priv
->fbdev
->ifb
.base
;
6687 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6688 fb
->bits_per_pixel
))
6691 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6697 bool intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
6698 struct drm_connector
*connector
,
6699 struct drm_display_mode
*mode
,
6700 struct intel_load_detect_pipe
*old
)
6702 struct intel_crtc
*intel_crtc
;
6703 struct drm_crtc
*possible_crtc
;
6704 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6705 struct drm_crtc
*crtc
= NULL
;
6706 struct drm_device
*dev
= encoder
->dev
;
6707 struct drm_framebuffer
*old_fb
;
6710 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6711 connector
->base
.id
, drm_get_connector_name(connector
),
6712 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6715 * Algorithm gets a little messy:
6717 * - if the connector already has an assigned crtc, use it (but make
6718 * sure it's on first)
6720 * - try to find the first unused crtc that can drive this connector,
6721 * and use that if we find one
6724 /* See if we already have a CRTC for this connector */
6725 if (encoder
->crtc
) {
6726 crtc
= encoder
->crtc
;
6728 intel_crtc
= to_intel_crtc(crtc
);
6729 old
->dpms_mode
= intel_crtc
->dpms_mode
;
6730 old
->load_detect_temp
= false;
6732 /* Make sure the crtc and connector are running */
6733 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
6734 struct drm_encoder_helper_funcs
*encoder_funcs
;
6735 struct drm_crtc_helper_funcs
*crtc_funcs
;
6737 crtc_funcs
= crtc
->helper_private
;
6738 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
6740 encoder_funcs
= encoder
->helper_private
;
6741 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
6747 /* Find an unused one (if possible) */
6748 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6750 if (!(encoder
->possible_crtcs
& (1 << i
)))
6752 if (!possible_crtc
->enabled
) {
6753 crtc
= possible_crtc
;
6759 * If we didn't find an unused CRTC, don't use any.
6762 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6766 encoder
->crtc
= crtc
;
6767 connector
->encoder
= encoder
;
6769 intel_crtc
= to_intel_crtc(crtc
);
6770 old
->dpms_mode
= intel_crtc
->dpms_mode
;
6771 old
->load_detect_temp
= true;
6772 old
->release_fb
= NULL
;
6775 mode
= &load_detect_mode
;
6779 /* We need a framebuffer large enough to accommodate all accesses
6780 * that the plane may generate whilst we perform load detection.
6781 * We can not rely on the fbcon either being present (we get called
6782 * during its initialisation to detect all boot displays, or it may
6783 * not even exist) or that it is large enough to satisfy the
6786 crtc
->fb
= mode_fits_in_fbdev(dev
, mode
);
6787 if (crtc
->fb
== NULL
) {
6788 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6789 crtc
->fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6790 old
->release_fb
= crtc
->fb
;
6792 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6793 if (IS_ERR(crtc
->fb
)) {
6794 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6799 if (!drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, old_fb
)) {
6800 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6801 if (old
->release_fb
)
6802 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6807 /* let the connector get through one full cycle before testing */
6808 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6813 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
6814 struct drm_connector
*connector
,
6815 struct intel_load_detect_pipe
*old
)
6817 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6818 struct drm_device
*dev
= encoder
->dev
;
6819 struct drm_crtc
*crtc
= encoder
->crtc
;
6820 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
6821 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
6823 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6824 connector
->base
.id
, drm_get_connector_name(connector
),
6825 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6827 if (old
->load_detect_temp
) {
6828 connector
->encoder
= NULL
;
6829 drm_helper_disable_unused_functions(dev
);
6831 if (old
->release_fb
)
6832 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6837 /* Switch crtc and encoder back off if necessary */
6838 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
6839 encoder_funcs
->dpms(encoder
, old
->dpms_mode
);
6840 crtc_funcs
->dpms(crtc
, old
->dpms_mode
);
6844 /* Returns the clock of the currently programmed mode of the given pipe. */
6845 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6849 int pipe
= intel_crtc
->pipe
;
6850 u32 dpll
= I915_READ(DPLL(pipe
));
6852 intel_clock_t clock
;
6854 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6855 fp
= I915_READ(FP0(pipe
));
6857 fp
= I915_READ(FP1(pipe
));
6859 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6860 if (IS_PINEVIEW(dev
)) {
6861 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6862 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6864 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6865 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6868 if (!IS_GEN2(dev
)) {
6869 if (IS_PINEVIEW(dev
))
6870 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6871 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6873 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6874 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6876 switch (dpll
& DPLL_MODE_MASK
) {
6877 case DPLLB_MODE_DAC_SERIAL
:
6878 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6881 case DPLLB_MODE_LVDS
:
6882 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6886 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6887 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6891 /* XXX: Handle the 100Mhz refclk */
6892 intel_clock(dev
, 96000, &clock
);
6894 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6897 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6898 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6901 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6902 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6903 /* XXX: might not be 66MHz */
6904 intel_clock(dev
, 66000, &clock
);
6906 intel_clock(dev
, 48000, &clock
);
6908 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6911 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6912 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6914 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6919 intel_clock(dev
, 48000, &clock
);
6923 /* XXX: It would be nice to validate the clocks, but we can't reuse
6924 * i830PllIsValid() because it relies on the xf86_config connector
6925 * configuration being accurate, which it isn't necessarily.
6931 /** Returns the currently programmed mode of the given pipe. */
6932 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6933 struct drm_crtc
*crtc
)
6935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6936 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6937 int pipe
= intel_crtc
->pipe
;
6938 struct drm_display_mode
*mode
;
6939 int htot
= I915_READ(HTOTAL(pipe
));
6940 int hsync
= I915_READ(HSYNC(pipe
));
6941 int vtot
= I915_READ(VTOTAL(pipe
));
6942 int vsync
= I915_READ(VSYNC(pipe
));
6944 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6948 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6949 mode
->hdisplay
= (htot
& 0xffff) + 1;
6950 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6951 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6952 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6953 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6954 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6955 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6956 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6958 drm_mode_set_name(mode
);
6959 drm_mode_set_crtcinfo(mode
, 0);
6964 #define GPU_IDLE_TIMEOUT 500 /* ms */
6966 /* When this timer fires, we've been idle for awhile */
6967 static void intel_gpu_idle_timer(unsigned long arg
)
6969 struct drm_device
*dev
= (struct drm_device
*)arg
;
6970 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6972 if (!list_empty(&dev_priv
->mm
.active_list
)) {
6973 /* Still processing requests, so just re-arm the timer. */
6974 mod_timer(&dev_priv
->idle_timer
, jiffies
+
6975 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
6979 dev_priv
->busy
= false;
6980 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
6983 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
6985 static void intel_crtc_idle_timer(unsigned long arg
)
6987 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
6988 struct drm_crtc
*crtc
= &intel_crtc
->base
;
6989 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
6990 struct intel_framebuffer
*intel_fb
;
6992 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6993 if (intel_fb
&& intel_fb
->obj
->active
) {
6994 /* The framebuffer is still being accessed by the GPU. */
6995 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
6996 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
7000 intel_crtc
->busy
= false;
7001 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
7004 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7006 struct drm_device
*dev
= crtc
->dev
;
7007 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7008 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7009 int pipe
= intel_crtc
->pipe
;
7010 int dpll_reg
= DPLL(pipe
);
7013 if (HAS_PCH_SPLIT(dev
))
7016 if (!dev_priv
->lvds_downclock_avail
)
7019 dpll
= I915_READ(dpll_reg
);
7020 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7021 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7023 assert_panel_unlocked(dev_priv
, pipe
);
7025 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7026 I915_WRITE(dpll_reg
, dpll
);
7027 intel_wait_for_vblank(dev
, pipe
);
7029 dpll
= I915_READ(dpll_reg
);
7030 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7031 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7034 /* Schedule downclock */
7035 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
7036 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
7039 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7041 struct drm_device
*dev
= crtc
->dev
;
7042 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7043 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7044 int pipe
= intel_crtc
->pipe
;
7045 int dpll_reg
= DPLL(pipe
);
7046 int dpll
= I915_READ(dpll_reg
);
7048 if (HAS_PCH_SPLIT(dev
))
7051 if (!dev_priv
->lvds_downclock_avail
)
7055 * Since this is called by a timer, we should never get here in
7058 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7059 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7061 assert_panel_unlocked(dev_priv
, pipe
);
7063 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7064 I915_WRITE(dpll_reg
, dpll
);
7065 intel_wait_for_vblank(dev
, pipe
);
7066 dpll
= I915_READ(dpll_reg
);
7067 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7068 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7074 * intel_idle_update - adjust clocks for idleness
7075 * @work: work struct
7077 * Either the GPU or display (or both) went idle. Check the busy status
7078 * here and adjust the CRTC and GPU clocks as necessary.
7080 static void intel_idle_update(struct work_struct
*work
)
7082 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
7084 struct drm_device
*dev
= dev_priv
->dev
;
7085 struct drm_crtc
*crtc
;
7086 struct intel_crtc
*intel_crtc
;
7088 if (!i915_powersave
)
7091 mutex_lock(&dev
->struct_mutex
);
7093 i915_update_gfx_val(dev_priv
);
7095 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7096 /* Skip inactive CRTCs */
7100 intel_crtc
= to_intel_crtc(crtc
);
7101 if (!intel_crtc
->busy
)
7102 intel_decrease_pllclock(crtc
);
7106 mutex_unlock(&dev
->struct_mutex
);
7110 * intel_mark_busy - mark the GPU and possibly the display busy
7112 * @obj: object we're operating on
7114 * Callers can use this function to indicate that the GPU is busy processing
7115 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7116 * buffer), we'll also mark the display as busy, so we know to increase its
7119 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
7121 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7122 struct drm_crtc
*crtc
= NULL
;
7123 struct intel_framebuffer
*intel_fb
;
7124 struct intel_crtc
*intel_crtc
;
7126 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
7129 if (!dev_priv
->busy
)
7130 dev_priv
->busy
= true;
7132 mod_timer(&dev_priv
->idle_timer
, jiffies
+
7133 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
7135 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7139 intel_crtc
= to_intel_crtc(crtc
);
7140 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7141 if (intel_fb
->obj
== obj
) {
7142 if (!intel_crtc
->busy
) {
7143 /* Non-busy -> busy, upclock */
7144 intel_increase_pllclock(crtc
);
7145 intel_crtc
->busy
= true;
7147 /* Busy -> busy, put off timer */
7148 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
7149 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
7155 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7157 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7158 struct drm_device
*dev
= crtc
->dev
;
7159 struct intel_unpin_work
*work
;
7160 unsigned long flags
;
7162 spin_lock_irqsave(&dev
->event_lock
, flags
);
7163 work
= intel_crtc
->unpin_work
;
7164 intel_crtc
->unpin_work
= NULL
;
7165 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7168 cancel_work_sync(&work
->work
);
7172 drm_crtc_cleanup(crtc
);
7177 static void intel_unpin_work_fn(struct work_struct
*__work
)
7179 struct intel_unpin_work
*work
=
7180 container_of(__work
, struct intel_unpin_work
, work
);
7182 mutex_lock(&work
->dev
->struct_mutex
);
7183 intel_unpin_fb_obj(work
->old_fb_obj
);
7184 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7185 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7187 intel_update_fbc(work
->dev
);
7188 mutex_unlock(&work
->dev
->struct_mutex
);
7192 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7193 struct drm_crtc
*crtc
)
7195 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7197 struct intel_unpin_work
*work
;
7198 struct drm_i915_gem_object
*obj
;
7199 struct drm_pending_vblank_event
*e
;
7200 struct timeval tnow
, tvbl
;
7201 unsigned long flags
;
7203 /* Ignore early vblank irqs */
7204 if (intel_crtc
== NULL
)
7207 do_gettimeofday(&tnow
);
7209 spin_lock_irqsave(&dev
->event_lock
, flags
);
7210 work
= intel_crtc
->unpin_work
;
7211 if (work
== NULL
|| !work
->pending
) {
7212 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7216 intel_crtc
->unpin_work
= NULL
;
7220 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
7222 /* Called before vblank count and timestamps have
7223 * been updated for the vblank interval of flip
7224 * completion? Need to increment vblank count and
7225 * add one videorefresh duration to returned timestamp
7226 * to account for this. We assume this happened if we
7227 * get called over 0.9 frame durations after the last
7228 * timestamped vblank.
7230 * This calculation can not be used with vrefresh rates
7231 * below 5Hz (10Hz to be on the safe side) without
7232 * promoting to 64 integers.
7234 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
7235 9 * crtc
->framedur_ns
) {
7236 e
->event
.sequence
++;
7237 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
7241 e
->event
.tv_sec
= tvbl
.tv_sec
;
7242 e
->event
.tv_usec
= tvbl
.tv_usec
;
7244 list_add_tail(&e
->base
.link
,
7245 &e
->base
.file_priv
->event_list
);
7246 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
7249 drm_vblank_put(dev
, intel_crtc
->pipe
);
7251 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7253 obj
= work
->old_fb_obj
;
7255 atomic_clear_mask(1 << intel_crtc
->plane
,
7256 &obj
->pending_flip
.counter
);
7257 if (atomic_read(&obj
->pending_flip
) == 0)
7258 wake_up(&dev_priv
->pending_flip_queue
);
7260 schedule_work(&work
->work
);
7262 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7265 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7267 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7268 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7270 do_intel_finish_page_flip(dev
, crtc
);
7273 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7275 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7276 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7278 do_intel_finish_page_flip(dev
, crtc
);
7281 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7283 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7284 struct intel_crtc
*intel_crtc
=
7285 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7286 unsigned long flags
;
7288 spin_lock_irqsave(&dev
->event_lock
, flags
);
7289 if (intel_crtc
->unpin_work
) {
7290 if ((++intel_crtc
->unpin_work
->pending
) > 1)
7291 DRM_ERROR("Prepared flip multiple times\n");
7293 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7295 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7298 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7299 struct drm_crtc
*crtc
,
7300 struct drm_framebuffer
*fb
,
7301 struct drm_i915_gem_object
*obj
)
7303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7304 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7305 unsigned long offset
;
7309 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
7313 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7314 offset
= crtc
->y
* fb
->pitches
[0] + crtc
->x
* fb
->bits_per_pixel
/8;
7316 ret
= BEGIN_LP_RING(6);
7320 /* Can't queue multiple flips, so wait for the previous
7321 * one to finish before executing the next.
7323 if (intel_crtc
->plane
)
7324 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7326 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7327 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
7329 OUT_RING(MI_DISPLAY_FLIP
|
7330 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7331 OUT_RING(fb
->pitches
[0]);
7332 OUT_RING(obj
->gtt_offset
+ offset
);
7333 OUT_RING(0); /* aux display base address, unused */
7339 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7340 struct drm_crtc
*crtc
,
7341 struct drm_framebuffer
*fb
,
7342 struct drm_i915_gem_object
*obj
)
7344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7345 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7346 unsigned long offset
;
7350 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
7354 /* Offset into the new buffer for cases of shared fbs between CRTCs */
7355 offset
= crtc
->y
* fb
->pitches
[0] + crtc
->x
* fb
->bits_per_pixel
/8;
7357 ret
= BEGIN_LP_RING(6);
7361 if (intel_crtc
->plane
)
7362 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7364 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7365 OUT_RING(MI_WAIT_FOR_EVENT
| flip_mask
);
7367 OUT_RING(MI_DISPLAY_FLIP_I915
|
7368 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7369 OUT_RING(fb
->pitches
[0]);
7370 OUT_RING(obj
->gtt_offset
+ offset
);
7378 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7379 struct drm_crtc
*crtc
,
7380 struct drm_framebuffer
*fb
,
7381 struct drm_i915_gem_object
*obj
)
7383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7384 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7385 uint32_t pf
, pipesrc
;
7388 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
7392 ret
= BEGIN_LP_RING(4);
7396 /* i965+ uses the linear or tiled offsets from the
7397 * Display Registers (which do not change across a page-flip)
7398 * so we need only reprogram the base address.
7400 OUT_RING(MI_DISPLAY_FLIP
|
7401 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7402 OUT_RING(fb
->pitches
[0]);
7403 OUT_RING(obj
->gtt_offset
| obj
->tiling_mode
);
7405 /* XXX Enabling the panel-fitter across page-flip is so far
7406 * untested on non-native modes, so ignore it for now.
7407 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7410 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7411 OUT_RING(pf
| pipesrc
);
7417 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7418 struct drm_crtc
*crtc
,
7419 struct drm_framebuffer
*fb
,
7420 struct drm_i915_gem_object
*obj
)
7422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7423 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7424 uint32_t pf
, pipesrc
;
7427 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, LP_RING(dev_priv
));
7431 ret
= BEGIN_LP_RING(4);
7435 OUT_RING(MI_DISPLAY_FLIP
|
7436 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7437 OUT_RING(fb
->pitches
[0] | obj
->tiling_mode
);
7438 OUT_RING(obj
->gtt_offset
);
7440 pf
= I915_READ(PF_CTL(intel_crtc
->pipe
)) & PF_ENABLE
;
7441 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7442 OUT_RING(pf
| pipesrc
);
7449 * On gen7 we currently use the blit ring because (in early silicon at least)
7450 * the render ring doesn't give us interrpts for page flip completion, which
7451 * means clients will hang after the first flip is queued. Fortunately the
7452 * blit ring generates interrupts properly, so use it instead.
7454 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7455 struct drm_crtc
*crtc
,
7456 struct drm_framebuffer
*fb
,
7457 struct drm_i915_gem_object
*obj
)
7459 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7460 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7461 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7464 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7468 ret
= intel_ring_begin(ring
, 4);
7472 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| (intel_crtc
->plane
<< 19));
7473 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7474 intel_ring_emit(ring
, (obj
->gtt_offset
));
7475 intel_ring_emit(ring
, (MI_NOOP
));
7476 intel_ring_advance(ring
);
7481 static int intel_default_queue_flip(struct drm_device
*dev
,
7482 struct drm_crtc
*crtc
,
7483 struct drm_framebuffer
*fb
,
7484 struct drm_i915_gem_object
*obj
)
7489 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7490 struct drm_framebuffer
*fb
,
7491 struct drm_pending_vblank_event
*event
)
7493 struct drm_device
*dev
= crtc
->dev
;
7494 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7495 struct intel_framebuffer
*intel_fb
;
7496 struct drm_i915_gem_object
*obj
;
7497 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7498 struct intel_unpin_work
*work
;
7499 unsigned long flags
;
7502 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7506 work
->event
= event
;
7507 work
->dev
= crtc
->dev
;
7508 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7509 work
->old_fb_obj
= intel_fb
->obj
;
7510 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7512 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7516 /* We borrow the event spin lock for protecting unpin_work */
7517 spin_lock_irqsave(&dev
->event_lock
, flags
);
7518 if (intel_crtc
->unpin_work
) {
7519 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7521 drm_vblank_put(dev
, intel_crtc
->pipe
);
7523 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7526 intel_crtc
->unpin_work
= work
;
7527 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7529 intel_fb
= to_intel_framebuffer(fb
);
7530 obj
= intel_fb
->obj
;
7532 mutex_lock(&dev
->struct_mutex
);
7534 /* Reference the objects for the scheduled work. */
7535 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7536 drm_gem_object_reference(&obj
->base
);
7540 work
->pending_flip_obj
= obj
;
7542 work
->enable_stall_check
= true;
7544 /* Block clients from rendering to the new back buffer until
7545 * the flip occurs and the object is no longer visible.
7547 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7549 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7551 goto cleanup_pending
;
7553 intel_disable_fbc(dev
);
7554 mutex_unlock(&dev
->struct_mutex
);
7556 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7561 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7562 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7563 drm_gem_object_unreference(&obj
->base
);
7564 mutex_unlock(&dev
->struct_mutex
);
7566 spin_lock_irqsave(&dev
->event_lock
, flags
);
7567 intel_crtc
->unpin_work
= NULL
;
7568 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7570 drm_vblank_put(dev
, intel_crtc
->pipe
);
7577 static void intel_sanitize_modesetting(struct drm_device
*dev
,
7578 int pipe
, int plane
)
7580 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7583 /* Clear any frame start delays used for debugging left by the BIOS */
7584 for_each_pipe(pipe
) {
7585 reg
= PIPECONF(pipe
);
7586 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
7589 if (HAS_PCH_SPLIT(dev
))
7592 /* Who knows what state these registers were left in by the BIOS or
7595 * If we leave the registers in a conflicting state (e.g. with the
7596 * display plane reading from the other pipe than the one we intend
7597 * to use) then when we attempt to teardown the active mode, we will
7598 * not disable the pipes and planes in the correct order -- leaving
7599 * a plane reading from a disabled pipe and possibly leading to
7600 * undefined behaviour.
7603 reg
= DSPCNTR(plane
);
7604 val
= I915_READ(reg
);
7606 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
7608 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
7611 /* This display plane is active and attached to the other CPU pipe. */
7614 /* Disable the plane and wait for it to stop reading from the pipe. */
7615 intel_disable_plane(dev_priv
, plane
, pipe
);
7616 intel_disable_pipe(dev_priv
, pipe
);
7619 static void intel_crtc_reset(struct drm_crtc
*crtc
)
7621 struct drm_device
*dev
= crtc
->dev
;
7622 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7624 /* Reset flags back to the 'unknown' status so that they
7625 * will be correctly set on the initial modeset.
7627 intel_crtc
->dpms_mode
= -1;
7629 /* We need to fix up any BIOS configuration that conflicts with
7632 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
7635 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7636 .dpms
= intel_crtc_dpms
,
7637 .mode_fixup
= intel_crtc_mode_fixup
,
7638 .mode_set
= intel_crtc_mode_set
,
7639 .mode_set_base
= intel_pipe_set_base
,
7640 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7641 .load_lut
= intel_crtc_load_lut
,
7642 .disable
= intel_crtc_disable
,
7645 static const struct drm_crtc_funcs intel_crtc_funcs
= {
7646 .reset
= intel_crtc_reset
,
7647 .cursor_set
= intel_crtc_cursor_set
,
7648 .cursor_move
= intel_crtc_cursor_move
,
7649 .gamma_set
= intel_crtc_gamma_set
,
7650 .set_config
= drm_crtc_helper_set_config
,
7651 .destroy
= intel_crtc_destroy
,
7652 .page_flip
= intel_crtc_page_flip
,
7655 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
7657 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7658 struct intel_crtc
*intel_crtc
;
7661 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
7662 if (intel_crtc
== NULL
)
7665 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
7667 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
7668 for (i
= 0; i
< 256; i
++) {
7669 intel_crtc
->lut_r
[i
] = i
;
7670 intel_crtc
->lut_g
[i
] = i
;
7671 intel_crtc
->lut_b
[i
] = i
;
7674 /* Swap pipes & planes for FBC on pre-965 */
7675 intel_crtc
->pipe
= pipe
;
7676 intel_crtc
->plane
= pipe
;
7677 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
7678 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
7679 intel_crtc
->plane
= !pipe
;
7682 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
7683 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
7684 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
7685 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
7687 intel_crtc_reset(&intel_crtc
->base
);
7688 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
7689 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
7691 if (HAS_PCH_SPLIT(dev
)) {
7692 if (pipe
== 2 && IS_IVYBRIDGE(dev
))
7693 intel_crtc
->no_pll
= true;
7694 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
7695 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
7697 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
7698 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
7701 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
7703 intel_crtc
->busy
= false;
7705 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
7706 (unsigned long)intel_crtc
);
7709 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
7710 struct drm_file
*file
)
7712 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7713 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
7714 struct drm_mode_object
*drmmode_obj
;
7715 struct intel_crtc
*crtc
;
7718 DRM_ERROR("called with no initialization\n");
7722 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
7723 DRM_MODE_OBJECT_CRTC
);
7726 DRM_ERROR("no such CRTC id\n");
7730 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
7731 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
7736 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
7738 struct intel_encoder
*encoder
;
7742 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7743 if (type_mask
& encoder
->clone_mask
)
7744 index_mask
|= (1 << entry
);
7751 static bool has_edp_a(struct drm_device
*dev
)
7753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7755 if (!IS_MOBILE(dev
))
7758 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
7762 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
7768 static void intel_setup_outputs(struct drm_device
*dev
)
7770 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7771 struct intel_encoder
*encoder
;
7772 bool dpd_is_edp
= false;
7775 has_lvds
= intel_lvds_init(dev
);
7776 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
7777 /* disable the panel fitter on everything but LVDS */
7778 I915_WRITE(PFIT_CONTROL
, 0);
7781 if (HAS_PCH_SPLIT(dev
)) {
7782 dpd_is_edp
= intel_dpd_is_edp(dev
);
7785 intel_dp_init(dev
, DP_A
);
7787 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
7788 intel_dp_init(dev
, PCH_DP_D
);
7791 intel_crt_init(dev
);
7793 if (HAS_PCH_SPLIT(dev
)) {
7796 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
7797 /* PCH SDVOB multiplex with HDMIB */
7798 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
7800 intel_hdmi_init(dev
, HDMIB
);
7801 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
7802 intel_dp_init(dev
, PCH_DP_B
);
7805 if (I915_READ(HDMIC
) & PORT_DETECTED
)
7806 intel_hdmi_init(dev
, HDMIC
);
7808 if (I915_READ(HDMID
) & PORT_DETECTED
)
7809 intel_hdmi_init(dev
, HDMID
);
7811 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
7812 intel_dp_init(dev
, PCH_DP_C
);
7814 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
7815 intel_dp_init(dev
, PCH_DP_D
);
7817 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
7820 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
7821 DRM_DEBUG_KMS("probing SDVOB\n");
7822 found
= intel_sdvo_init(dev
, SDVOB
);
7823 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
7824 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
7825 intel_hdmi_init(dev
, SDVOB
);
7828 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
7829 DRM_DEBUG_KMS("probing DP_B\n");
7830 intel_dp_init(dev
, DP_B
);
7834 /* Before G4X SDVOC doesn't have its own detect register */
7836 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
7837 DRM_DEBUG_KMS("probing SDVOC\n");
7838 found
= intel_sdvo_init(dev
, SDVOC
);
7841 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
7843 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
7844 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
7845 intel_hdmi_init(dev
, SDVOC
);
7847 if (SUPPORTS_INTEGRATED_DP(dev
)) {
7848 DRM_DEBUG_KMS("probing DP_C\n");
7849 intel_dp_init(dev
, DP_C
);
7853 if (SUPPORTS_INTEGRATED_DP(dev
) &&
7854 (I915_READ(DP_D
) & DP_DETECTED
)) {
7855 DRM_DEBUG_KMS("probing DP_D\n");
7856 intel_dp_init(dev
, DP_D
);
7858 } else if (IS_GEN2(dev
))
7859 intel_dvo_init(dev
);
7861 if (SUPPORTS_TV(dev
))
7864 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7865 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
7866 encoder
->base
.possible_clones
=
7867 intel_encoder_clones(dev
, encoder
->clone_mask
);
7870 /* disable all the possible outputs/crtcs before entering KMS mode */
7871 drm_helper_disable_unused_functions(dev
);
7873 if (HAS_PCH_SPLIT(dev
))
7874 ironlake_init_pch_refclk(dev
);
7877 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
7879 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
7881 drm_framebuffer_cleanup(fb
);
7882 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
7887 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
7888 struct drm_file
*file
,
7889 unsigned int *handle
)
7891 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
7892 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
7894 return drm_gem_handle_create(file
, &obj
->base
, handle
);
7897 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
7898 .destroy
= intel_user_framebuffer_destroy
,
7899 .create_handle
= intel_user_framebuffer_create_handle
,
7902 int intel_framebuffer_init(struct drm_device
*dev
,
7903 struct intel_framebuffer
*intel_fb
,
7904 struct drm_mode_fb_cmd2
*mode_cmd
,
7905 struct drm_i915_gem_object
*obj
)
7909 if (obj
->tiling_mode
== I915_TILING_Y
)
7912 if (mode_cmd
->pitches
[0] & 63)
7915 switch (mode_cmd
->pixel_format
) {
7916 case DRM_FORMAT_RGB332
:
7917 case DRM_FORMAT_RGB565
:
7918 case DRM_FORMAT_XRGB8888
:
7919 case DRM_FORMAT_XBGR8888
:
7920 case DRM_FORMAT_ARGB8888
:
7921 case DRM_FORMAT_XRGB2101010
:
7922 case DRM_FORMAT_ARGB2101010
:
7923 /* RGB formats are common across chipsets */
7925 case DRM_FORMAT_YUYV
:
7926 case DRM_FORMAT_UYVY
:
7927 case DRM_FORMAT_YVYU
:
7928 case DRM_FORMAT_VYUY
:
7931 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7932 mode_cmd
->pixel_format
);
7936 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
7938 DRM_ERROR("framebuffer init failed %d\n", ret
);
7942 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
7943 intel_fb
->obj
= obj
;
7947 static struct drm_framebuffer
*
7948 intel_user_framebuffer_create(struct drm_device
*dev
,
7949 struct drm_file
*filp
,
7950 struct drm_mode_fb_cmd2
*mode_cmd
)
7952 struct drm_i915_gem_object
*obj
;
7954 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
7955 mode_cmd
->handles
[0]));
7956 if (&obj
->base
== NULL
)
7957 return ERR_PTR(-ENOENT
);
7959 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
7962 static const struct drm_mode_config_funcs intel_mode_funcs
= {
7963 .fb_create
= intel_user_framebuffer_create
,
7964 .output_poll_changed
= intel_fb_output_poll_changed
,
7967 static struct drm_i915_gem_object
*
7968 intel_alloc_context_page(struct drm_device
*dev
)
7970 struct drm_i915_gem_object
*ctx
;
7973 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
7975 ctx
= i915_gem_alloc_object(dev
, 4096);
7977 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7981 ret
= i915_gem_object_pin(ctx
, 4096, true);
7983 DRM_ERROR("failed to pin power context: %d\n", ret
);
7987 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
7989 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
7996 i915_gem_object_unpin(ctx
);
7998 drm_gem_object_unreference(&ctx
->base
);
7999 mutex_unlock(&dev
->struct_mutex
);
8003 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
8005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8008 rgvswctl
= I915_READ16(MEMSWCTL
);
8009 if (rgvswctl
& MEMCTL_CMD_STS
) {
8010 DRM_DEBUG("gpu busy, RCS change rejected\n");
8011 return false; /* still busy with another command */
8014 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
8015 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
8016 I915_WRITE16(MEMSWCTL
, rgvswctl
);
8017 POSTING_READ16(MEMSWCTL
);
8019 rgvswctl
|= MEMCTL_CMD_STS
;
8020 I915_WRITE16(MEMSWCTL
, rgvswctl
);
8025 void ironlake_enable_drps(struct drm_device
*dev
)
8027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8028 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
8029 u8 fmax
, fmin
, fstart
, vstart
;
8031 /* Enable temp reporting */
8032 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
8033 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
8035 /* 100ms RC evaluation intervals */
8036 I915_WRITE(RCUPEI
, 100000);
8037 I915_WRITE(RCDNEI
, 100000);
8039 /* Set max/min thresholds to 90ms and 80ms respectively */
8040 I915_WRITE(RCBMAXAVG
, 90000);
8041 I915_WRITE(RCBMINAVG
, 80000);
8043 I915_WRITE(MEMIHYST
, 1);
8045 /* Set up min, max, and cur for interrupt handling */
8046 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
8047 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
8048 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
8049 MEMMODE_FSTART_SHIFT
;
8051 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
8054 dev_priv
->fmax
= fmax
; /* IPS callback will increase this */
8055 dev_priv
->fstart
= fstart
;
8057 dev_priv
->max_delay
= fstart
;
8058 dev_priv
->min_delay
= fmin
;
8059 dev_priv
->cur_delay
= fstart
;
8061 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8062 fmax
, fmin
, fstart
);
8064 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
8067 * Interrupts will be enabled in ironlake_irq_postinstall
8070 I915_WRITE(VIDSTART
, vstart
);
8071 POSTING_READ(VIDSTART
);
8073 rgvmodectl
|= MEMMODE_SWMODE_EN
;
8074 I915_WRITE(MEMMODECTL
, rgvmodectl
);
8076 if (wait_for((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
8077 DRM_ERROR("stuck trying to change perf mode\n");
8080 ironlake_set_drps(dev
, fstart
);
8082 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
8084 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
8085 dev_priv
->last_count2
= I915_READ(0x112f4);
8086 getrawmonotonic(&dev_priv
->last_time2
);
8089 void ironlake_disable_drps(struct drm_device
*dev
)
8091 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8092 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
8094 /* Ack interrupts, disable EFC interrupt */
8095 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
8096 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
8097 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
8098 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
8099 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
8101 /* Go back to the starting frequency */
8102 ironlake_set_drps(dev
, dev_priv
->fstart
);
8104 rgvswctl
|= MEMCTL_CMD_STS
;
8105 I915_WRITE(MEMSWCTL
, rgvswctl
);
8110 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
8112 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8115 swreq
= (val
& 0x3ff) << 25;
8116 I915_WRITE(GEN6_RPNSWREQ
, swreq
);
8119 void gen6_disable_rps(struct drm_device
*dev
)
8121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8123 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
8124 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
8125 I915_WRITE(GEN6_PMIER
, 0);
8126 /* Complete PM interrupt masking here doesn't race with the rps work
8127 * item again unmasking PM interrupts because that is using a different
8128 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8129 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
8131 spin_lock_irq(&dev_priv
->rps_lock
);
8132 dev_priv
->pm_iir
= 0;
8133 spin_unlock_irq(&dev_priv
->rps_lock
);
8135 I915_WRITE(GEN6_PMIIR
, I915_READ(GEN6_PMIIR
));
8138 static unsigned long intel_pxfreq(u32 vidfreq
)
8141 int div
= (vidfreq
& 0x3f0000) >> 16;
8142 int post
= (vidfreq
& 0x3000) >> 12;
8143 int pre
= (vidfreq
& 0x7);
8148 freq
= ((div
* 133333) / ((1<<post
) * pre
));
8153 void intel_init_emon(struct drm_device
*dev
)
8155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8160 /* Disable to program */
8164 /* Program energy weights for various events */
8165 I915_WRITE(SDEW
, 0x15040d00);
8166 I915_WRITE(CSIEW0
, 0x007f0000);
8167 I915_WRITE(CSIEW1
, 0x1e220004);
8168 I915_WRITE(CSIEW2
, 0x04000004);
8170 for (i
= 0; i
< 5; i
++)
8171 I915_WRITE(PEW
+ (i
* 4), 0);
8172 for (i
= 0; i
< 3; i
++)
8173 I915_WRITE(DEW
+ (i
* 4), 0);
8175 /* Program P-state weights to account for frequency power adjustment */
8176 for (i
= 0; i
< 16; i
++) {
8177 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
8178 unsigned long freq
= intel_pxfreq(pxvidfreq
);
8179 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
8184 val
*= (freq
/ 1000);
8186 val
/= (127*127*900);
8188 DRM_ERROR("bad pxval: %ld\n", val
);
8191 /* Render standby states get 0 weight */
8195 for (i
= 0; i
< 4; i
++) {
8196 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
8197 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
8198 I915_WRITE(PXW
+ (i
* 4), val
);
8201 /* Adjust magic regs to magic values (more experimental results) */
8202 I915_WRITE(OGW0
, 0);
8203 I915_WRITE(OGW1
, 0);
8204 I915_WRITE(EG0
, 0x00007f00);
8205 I915_WRITE(EG1
, 0x0000000e);
8206 I915_WRITE(EG2
, 0x000e0000);
8207 I915_WRITE(EG3
, 0x68000300);
8208 I915_WRITE(EG4
, 0x42000000);
8209 I915_WRITE(EG5
, 0x00140031);
8213 for (i
= 0; i
< 8; i
++)
8214 I915_WRITE(PXWL
+ (i
* 4), 0);
8216 /* Enable PMON + select events */
8217 I915_WRITE(ECR
, 0x80000019);
8219 lcfuse
= I915_READ(LCFUSE02
);
8221 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
8224 static int intel_enable_rc6(struct drm_device
*dev
)
8227 * Respect the kernel parameter if it is set
8229 if (i915_enable_rc6
>= 0)
8230 return i915_enable_rc6
;
8233 * Disable RC6 on Ironlake
8235 if (INTEL_INFO(dev
)->gen
== 5)
8239 * Disable rc6 on Sandybridge
8241 if (INTEL_INFO(dev
)->gen
== 6) {
8242 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
8243 return INTEL_RC6_ENABLE
;
8245 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
8246 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
8249 void gen6_enable_rps(struct drm_i915_private
*dev_priv
)
8251 u32 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
8252 u32 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
8253 u32 pcu_mbox
, rc6_mask
= 0;
8255 int cur_freq
, min_freq
, max_freq
;
8259 /* Here begins a magic sequence of register writes to enable
8260 * auto-downclocking.
8262 * Perhaps there might be some value in exposing these to
8265 I915_WRITE(GEN6_RC_STATE
, 0);
8266 mutex_lock(&dev_priv
->dev
->struct_mutex
);
8268 /* Clear the DBG now so we don't confuse earlier errors */
8269 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
8270 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
8271 I915_WRITE(GTFIFODBG
, gtfifodbg
);
8274 gen6_gt_force_wake_get(dev_priv
);
8276 /* disable the counters and set deterministic thresholds */
8277 I915_WRITE(GEN6_RC_CONTROL
, 0);
8279 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
8280 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
8281 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
8282 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
8283 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
8285 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
8286 I915_WRITE(RING_MAX_IDLE(dev_priv
->ring
[i
].mmio_base
), 10);
8288 I915_WRITE(GEN6_RC_SLEEP
, 0);
8289 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
8290 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
8291 I915_WRITE(GEN6_RC6p_THRESHOLD
, 100000);
8292 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
8294 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
8295 if (rc6_mode
& INTEL_RC6_ENABLE
)
8296 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
8298 if (rc6_mode
& INTEL_RC6p_ENABLE
)
8299 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
8301 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
8302 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
8304 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
8305 (rc6_mode
& INTEL_RC6_ENABLE
) ? "on" : "off",
8306 (rc6_mode
& INTEL_RC6p_ENABLE
) ? "on" : "off",
8307 (rc6_mode
& INTEL_RC6pp_ENABLE
) ? "on" : "off");
8309 I915_WRITE(GEN6_RC_CONTROL
,
8311 GEN6_RC_CTL_EI_MODE(1) |
8312 GEN6_RC_CTL_HW_ENABLE
);
8314 I915_WRITE(GEN6_RPNSWREQ
,
8315 GEN6_FREQUENCY(10) |
8317 GEN6_AGGRESSIVE_TURBO
);
8318 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
8319 GEN6_FREQUENCY(12));
8321 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 1000000);
8322 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
8325 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 10000);
8326 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 1000000);
8327 I915_WRITE(GEN6_RP_UP_EI
, 100000);
8328 I915_WRITE(GEN6_RP_DOWN_EI
, 5000000);
8329 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
8330 I915_WRITE(GEN6_RP_CONTROL
,
8331 GEN6_RP_MEDIA_TURBO
|
8332 GEN6_RP_MEDIA_HW_MODE
|
8333 GEN6_RP_MEDIA_IS_GFX
|
8335 GEN6_RP_UP_BUSY_AVG
|
8336 GEN6_RP_DOWN_IDLE_CONT
);
8338 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
8340 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8342 I915_WRITE(GEN6_PCODE_DATA
, 0);
8343 I915_WRITE(GEN6_PCODE_MAILBOX
,
8345 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
8346 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
8348 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8350 min_freq
= (rp_state_cap
& 0xff0000) >> 16;
8351 max_freq
= rp_state_cap
& 0xff;
8352 cur_freq
= (gt_perf_status
& 0xff00) >> 8;
8354 /* Check for overclock support */
8355 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
8357 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8358 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_READ_OC_PARAMS
);
8359 pcu_mbox
= I915_READ(GEN6_PCODE_DATA
);
8360 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
8362 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8363 if (pcu_mbox
& (1<<31)) { /* OC supported */
8364 max_freq
= pcu_mbox
& 0xff;
8365 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox
* 50);
8368 /* In units of 100MHz */
8369 dev_priv
->max_delay
= max_freq
;
8370 dev_priv
->min_delay
= min_freq
;
8371 dev_priv
->cur_delay
= cur_freq
;
8373 /* requires MSI enabled */
8374 I915_WRITE(GEN6_PMIER
,
8375 GEN6_PM_MBOX_EVENT
|
8376 GEN6_PM_THERMAL_EVENT
|
8377 GEN6_PM_RP_DOWN_TIMEOUT
|
8378 GEN6_PM_RP_UP_THRESHOLD
|
8379 GEN6_PM_RP_DOWN_THRESHOLD
|
8380 GEN6_PM_RP_UP_EI_EXPIRED
|
8381 GEN6_PM_RP_DOWN_EI_EXPIRED
);
8382 spin_lock_irq(&dev_priv
->rps_lock
);
8383 WARN_ON(dev_priv
->pm_iir
!= 0);
8384 I915_WRITE(GEN6_PMIMR
, 0);
8385 spin_unlock_irq(&dev_priv
->rps_lock
);
8386 /* enable all PM interrupts */
8387 I915_WRITE(GEN6_PMINTRMSK
, 0);
8389 gen6_gt_force_wake_put(dev_priv
);
8390 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
8393 void gen6_update_ring_freq(struct drm_i915_private
*dev_priv
)
8396 int gpu_freq
, ia_freq
, max_ia_freq
;
8397 int scaling_factor
= 180;
8399 max_ia_freq
= cpufreq_quick_get_max(0);
8401 * Default to measured freq if none found, PCU will ensure we don't go
8405 max_ia_freq
= tsc_khz
;
8407 /* Convert from kHz to MHz */
8408 max_ia_freq
/= 1000;
8410 mutex_lock(&dev_priv
->dev
->struct_mutex
);
8413 * For each potential GPU frequency, load a ring frequency we'd like
8414 * to use for memory access. We do this by specifying the IA frequency
8415 * the PCU should use as a reference to determine the ring frequency.
8417 for (gpu_freq
= dev_priv
->max_delay
; gpu_freq
>= dev_priv
->min_delay
;
8419 int diff
= dev_priv
->max_delay
- gpu_freq
;
8422 * For GPU frequencies less than 750MHz, just use the lowest
8425 if (gpu_freq
< min_freq
)
8428 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
8429 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
8431 I915_WRITE(GEN6_PCODE_DATA
,
8432 (ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
) |
8434 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
|
8435 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
);
8436 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) &
8437 GEN6_PCODE_READY
) == 0, 10)) {
8438 DRM_ERROR("pcode write of freq table timed out\n");
8443 mutex_unlock(&dev_priv
->dev
->struct_mutex
);
8446 static void ironlake_init_clock_gating(struct drm_device
*dev
)
8448 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8449 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
8451 /* Required for FBC */
8452 dspclk_gate
|= DPFCUNIT_CLOCK_GATE_DISABLE
|
8453 DPFCRUNIT_CLOCK_GATE_DISABLE
|
8454 DPFDUNIT_CLOCK_GATE_DISABLE
;
8455 /* Required for CxSR */
8456 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
8458 I915_WRITE(PCH_3DCGDIS0
,
8459 MARIUNIT_CLOCK_GATE_DISABLE
|
8460 SVSMUNIT_CLOCK_GATE_DISABLE
);
8461 I915_WRITE(PCH_3DCGDIS1
,
8462 VFMUNIT_CLOCK_GATE_DISABLE
);
8464 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
8467 * According to the spec the following bits should be set in
8468 * order to enable memory self-refresh
8469 * The bit 22/21 of 0x42004
8470 * The bit 5 of 0x42020
8471 * The bit 15 of 0x45000
8473 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8474 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
8475 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
8476 I915_WRITE(ILK_DSPCLK_GATE
,
8477 (I915_READ(ILK_DSPCLK_GATE
) |
8478 ILK_DPARB_CLK_GATE
));
8479 I915_WRITE(DISP_ARB_CTL
,
8480 (I915_READ(DISP_ARB_CTL
) |
8482 I915_WRITE(WM3_LP_ILK
, 0);
8483 I915_WRITE(WM2_LP_ILK
, 0);
8484 I915_WRITE(WM1_LP_ILK
, 0);
8487 * Based on the document from hardware guys the following bits
8488 * should be set unconditionally in order to enable FBC.
8489 * The bit 22 of 0x42000
8490 * The bit 22 of 0x42004
8491 * The bit 7,8,9 of 0x42020.
8493 if (IS_IRONLAKE_M(dev
)) {
8494 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8495 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8497 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8498 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8500 I915_WRITE(ILK_DSPCLK_GATE
,
8501 I915_READ(ILK_DSPCLK_GATE
) |
8507 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8508 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8509 ILK_ELPIN_409_SELECT
);
8510 I915_WRITE(_3D_CHICKEN2
,
8511 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
8512 _3D_CHICKEN2_WM_READ_PIPELINED
);
8515 static void gen6_init_clock_gating(struct drm_device
*dev
)
8517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8519 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
8521 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
8523 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8524 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8525 ILK_ELPIN_409_SELECT
);
8527 I915_WRITE(WM3_LP_ILK
, 0);
8528 I915_WRITE(WM2_LP_ILK
, 0);
8529 I915_WRITE(WM1_LP_ILK
, 0);
8531 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8532 * gating disable must be set. Failure to set it results in
8533 * flickering pixels due to Z write ordering failures after
8534 * some amount of runtime in the Mesa "fire" demo, and Unigine
8535 * Sanctuary and Tropics, and apparently anything else with
8536 * alpha test or pixel discard.
8538 * According to the spec, bit 11 (RCCUNIT) must also be set,
8539 * but we didn't debug actual testcases to find it out.
8541 I915_WRITE(GEN6_UCGCTL2
,
8542 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
8543 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
8546 * According to the spec the following bits should be
8547 * set in order to enable memory self-refresh and fbc:
8548 * The bit21 and bit22 of 0x42000
8549 * The bit21 and bit22 of 0x42004
8550 * The bit5 and bit7 of 0x42020
8551 * The bit14 of 0x70180
8552 * The bit14 of 0x71180
8554 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
8555 I915_READ(ILK_DISPLAY_CHICKEN1
) |
8556 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
8557 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
8558 I915_READ(ILK_DISPLAY_CHICKEN2
) |
8559 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
8560 I915_WRITE(ILK_DSPCLK_GATE
,
8561 I915_READ(ILK_DSPCLK_GATE
) |
8562 ILK_DPARB_CLK_GATE
|
8565 for_each_pipe(pipe
) {
8566 I915_WRITE(DSPCNTR(pipe
),
8567 I915_READ(DSPCNTR(pipe
)) |
8568 DISPPLANE_TRICKLE_FEED_DISABLE
);
8569 intel_flush_display_plane(dev_priv
, pipe
);
8573 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
8575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8577 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
8579 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
8581 I915_WRITE(WM3_LP_ILK
, 0);
8582 I915_WRITE(WM2_LP_ILK
, 0);
8583 I915_WRITE(WM1_LP_ILK
, 0);
8585 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
8586 * This implements the WaDisableRCZUnitClockGating workaround.
8588 I915_WRITE(GEN6_UCGCTL2
, GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
8590 I915_WRITE(ILK_DSPCLK_GATE
, IVB_VRHUNIT_CLK_GATE
);
8592 I915_WRITE(IVB_CHICKEN3
,
8593 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
8594 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
8596 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
8597 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
8598 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
8600 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
8601 I915_WRITE(GEN7_L3CNTLREG1
,
8602 GEN7_WA_FOR_GEN7_L3_CONTROL
);
8603 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
8604 GEN7_WA_L3_CHICKEN_MODE
);
8606 /* This is required by WaCatErrorRejectionIssue */
8607 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
8608 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
8609 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
8611 for_each_pipe(pipe
) {
8612 I915_WRITE(DSPCNTR(pipe
),
8613 I915_READ(DSPCNTR(pipe
)) |
8614 DISPPLANE_TRICKLE_FEED_DISABLE
);
8615 intel_flush_display_plane(dev_priv
, pipe
);
8619 static void g4x_init_clock_gating(struct drm_device
*dev
)
8621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8622 uint32_t dspclk_gate
;
8624 I915_WRITE(RENCLK_GATE_D1
, 0);
8625 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
8626 GS_UNIT_CLOCK_GATE_DISABLE
|
8627 CL_UNIT_CLOCK_GATE_DISABLE
);
8628 I915_WRITE(RAMCLK_GATE_D
, 0);
8629 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
8630 OVRUNIT_CLOCK_GATE_DISABLE
|
8631 OVCUNIT_CLOCK_GATE_DISABLE
;
8633 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
8634 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
8637 static void crestline_init_clock_gating(struct drm_device
*dev
)
8639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8641 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
8642 I915_WRITE(RENCLK_GATE_D2
, 0);
8643 I915_WRITE(DSPCLK_GATE_D
, 0);
8644 I915_WRITE(RAMCLK_GATE_D
, 0);
8645 I915_WRITE16(DEUC
, 0);
8648 static void broadwater_init_clock_gating(struct drm_device
*dev
)
8650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8652 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
8653 I965_RCC_CLOCK_GATE_DISABLE
|
8654 I965_RCPB_CLOCK_GATE_DISABLE
|
8655 I965_ISC_CLOCK_GATE_DISABLE
|
8656 I965_FBC_CLOCK_GATE_DISABLE
);
8657 I915_WRITE(RENCLK_GATE_D2
, 0);
8660 static void gen3_init_clock_gating(struct drm_device
*dev
)
8662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8663 u32 dstate
= I915_READ(D_STATE
);
8665 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
8666 DSTATE_DOT_CLOCK_GATING
;
8667 I915_WRITE(D_STATE
, dstate
);
8670 static void i85x_init_clock_gating(struct drm_device
*dev
)
8672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8674 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
8677 static void i830_init_clock_gating(struct drm_device
*dev
)
8679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8681 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
8684 static void ibx_init_clock_gating(struct drm_device
*dev
)
8686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8689 * On Ibex Peak and Cougar Point, we need to disable clock
8690 * gating for the panel power sequencer or it will fail to
8691 * start up when no ports are active.
8693 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
8696 static void cpt_init_clock_gating(struct drm_device
*dev
)
8698 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8702 * On Ibex Peak and Cougar Point, we need to disable clock
8703 * gating for the panel power sequencer or it will fail to
8704 * start up when no ports are active.
8706 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
8707 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
8708 DPLS_EDP_PPS_FIX_DIS
);
8709 /* Without this, mode sets may fail silently on FDI */
8711 I915_WRITE(TRANS_CHICKEN2(pipe
), TRANS_AUTOTRAIN_GEN_STALL_DIS
);
8714 static void ironlake_teardown_rc6(struct drm_device
*dev
)
8716 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8718 if (dev_priv
->renderctx
) {
8719 i915_gem_object_unpin(dev_priv
->renderctx
);
8720 drm_gem_object_unreference(&dev_priv
->renderctx
->base
);
8721 dev_priv
->renderctx
= NULL
;
8724 if (dev_priv
->pwrctx
) {
8725 i915_gem_object_unpin(dev_priv
->pwrctx
);
8726 drm_gem_object_unreference(&dev_priv
->pwrctx
->base
);
8727 dev_priv
->pwrctx
= NULL
;
8731 static void ironlake_disable_rc6(struct drm_device
*dev
)
8733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8735 if (I915_READ(PWRCTXA
)) {
8736 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8737 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
8738 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
8741 I915_WRITE(PWRCTXA
, 0);
8742 POSTING_READ(PWRCTXA
);
8744 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
8745 POSTING_READ(RSTDBYCTL
);
8748 ironlake_teardown_rc6(dev
);
8751 static int ironlake_setup_rc6(struct drm_device
*dev
)
8753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8755 if (dev_priv
->renderctx
== NULL
)
8756 dev_priv
->renderctx
= intel_alloc_context_page(dev
);
8757 if (!dev_priv
->renderctx
)
8760 if (dev_priv
->pwrctx
== NULL
)
8761 dev_priv
->pwrctx
= intel_alloc_context_page(dev
);
8762 if (!dev_priv
->pwrctx
) {
8763 ironlake_teardown_rc6(dev
);
8770 void ironlake_enable_rc6(struct drm_device
*dev
)
8772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8775 /* rc6 disabled by default due to repeated reports of hanging during
8778 if (!intel_enable_rc6(dev
))
8781 mutex_lock(&dev
->struct_mutex
);
8782 ret
= ironlake_setup_rc6(dev
);
8784 mutex_unlock(&dev
->struct_mutex
);
8789 * GPU can automatically power down the render unit if given a page
8792 ret
= BEGIN_LP_RING(6);
8794 ironlake_teardown_rc6(dev
);
8795 mutex_unlock(&dev
->struct_mutex
);
8799 OUT_RING(MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
8800 OUT_RING(MI_SET_CONTEXT
);
8801 OUT_RING(dev_priv
->renderctx
->gtt_offset
|
8803 MI_SAVE_EXT_STATE_EN
|
8804 MI_RESTORE_EXT_STATE_EN
|
8805 MI_RESTORE_INHIBIT
);
8806 OUT_RING(MI_SUSPEND_FLUSH
);
8812 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8813 * does an implicit flush, combined with MI_FLUSH above, it should be
8814 * safe to assume that renderctx is valid
8816 ret
= intel_wait_ring_idle(LP_RING(dev_priv
));
8818 DRM_ERROR("failed to enable ironlake power power savings\n");
8819 ironlake_teardown_rc6(dev
);
8820 mutex_unlock(&dev
->struct_mutex
);
8824 I915_WRITE(PWRCTXA
, dev_priv
->pwrctx
->gtt_offset
| PWRCTX_EN
);
8825 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
8826 mutex_unlock(&dev
->struct_mutex
);
8829 void intel_init_clock_gating(struct drm_device
*dev
)
8831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8833 dev_priv
->display
.init_clock_gating(dev
);
8835 if (dev_priv
->display
.init_pch_clock_gating
)
8836 dev_priv
->display
.init_pch_clock_gating(dev
);
8839 /* Set up chip specific display functions */
8840 static void intel_init_display(struct drm_device
*dev
)
8842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8844 /* We always want a DPMS function */
8845 if (HAS_PCH_SPLIT(dev
)) {
8846 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
8847 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8848 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8850 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
8851 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8852 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8855 if (I915_HAS_FBC(dev
)) {
8856 if (HAS_PCH_SPLIT(dev
)) {
8857 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
8858 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
8859 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
8860 } else if (IS_GM45(dev
)) {
8861 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
8862 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
8863 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
8864 } else if (IS_CRESTLINE(dev
)) {
8865 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
8866 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
8867 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
8869 /* 855GM needs testing */
8872 /* Returns the core display clock speed */
8873 if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8874 dev_priv
->display
.get_display_clock_speed
=
8875 i945_get_display_clock_speed
;
8876 else if (IS_I915G(dev
))
8877 dev_priv
->display
.get_display_clock_speed
=
8878 i915_get_display_clock_speed
;
8879 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8880 dev_priv
->display
.get_display_clock_speed
=
8881 i9xx_misc_get_display_clock_speed
;
8882 else if (IS_I915GM(dev
))
8883 dev_priv
->display
.get_display_clock_speed
=
8884 i915gm_get_display_clock_speed
;
8885 else if (IS_I865G(dev
))
8886 dev_priv
->display
.get_display_clock_speed
=
8887 i865_get_display_clock_speed
;
8888 else if (IS_I85X(dev
))
8889 dev_priv
->display
.get_display_clock_speed
=
8890 i855_get_display_clock_speed
;
8892 dev_priv
->display
.get_display_clock_speed
=
8893 i830_get_display_clock_speed
;
8895 /* For FIFO watermark updates */
8896 if (HAS_PCH_SPLIT(dev
)) {
8897 dev_priv
->display
.force_wake_get
= __gen6_gt_force_wake_get
;
8898 dev_priv
->display
.force_wake_put
= __gen6_gt_force_wake_put
;
8900 /* IVB configs may use multi-threaded forcewake */
8901 if (IS_IVYBRIDGE(dev
)) {
8904 /* A small trick here - if the bios hasn't configured MT forcewake,
8905 * and if the device is in RC6, then force_wake_mt_get will not wake
8906 * the device and the ECOBUS read will return zero. Which will be
8907 * (correctly) interpreted by the test below as MT forcewake being
8910 mutex_lock(&dev
->struct_mutex
);
8911 __gen6_gt_force_wake_mt_get(dev_priv
);
8912 ecobus
= I915_READ_NOTRACE(ECOBUS
);
8913 __gen6_gt_force_wake_mt_put(dev_priv
);
8914 mutex_unlock(&dev
->struct_mutex
);
8916 if (ecobus
& FORCEWAKE_MT_ENABLE
) {
8917 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8918 dev_priv
->display
.force_wake_get
=
8919 __gen6_gt_force_wake_mt_get
;
8920 dev_priv
->display
.force_wake_put
=
8921 __gen6_gt_force_wake_mt_put
;
8925 if (HAS_PCH_IBX(dev
))
8926 dev_priv
->display
.init_pch_clock_gating
= ibx_init_clock_gating
;
8927 else if (HAS_PCH_CPT(dev
))
8928 dev_priv
->display
.init_pch_clock_gating
= cpt_init_clock_gating
;
8931 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
8932 dev_priv
->display
.update_wm
= ironlake_update_wm
;
8934 DRM_DEBUG_KMS("Failed to get proper latency. "
8936 dev_priv
->display
.update_wm
= NULL
;
8938 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8939 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
8940 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8941 } else if (IS_GEN6(dev
)) {
8942 if (SNB_READ_WM0_LATENCY()) {
8943 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
8944 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
8946 DRM_DEBUG_KMS("Failed to read display plane latency. "
8948 dev_priv
->display
.update_wm
= NULL
;
8950 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8951 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
8952 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8953 } else if (IS_IVYBRIDGE(dev
)) {
8954 /* FIXME: detect B0+ stepping and use auto training */
8955 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8956 if (SNB_READ_WM0_LATENCY()) {
8957 dev_priv
->display
.update_wm
= sandybridge_update_wm
;
8958 dev_priv
->display
.update_sprite_wm
= sandybridge_update_sprite_wm
;
8960 DRM_DEBUG_KMS("Failed to read display plane latency. "
8962 dev_priv
->display
.update_wm
= NULL
;
8964 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
8965 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8967 dev_priv
->display
.update_wm
= NULL
;
8968 } else if (IS_PINEVIEW(dev
)) {
8969 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
8972 dev_priv
->mem_freq
)) {
8973 DRM_INFO("failed to find known CxSR latency "
8974 "(found ddr%s fsb freq %d, mem freq %d), "
8976 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
8977 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
8978 /* Disable CxSR and never update its watermark again */
8979 pineview_disable_cxsr(dev
);
8980 dev_priv
->display
.update_wm
= NULL
;
8982 dev_priv
->display
.update_wm
= pineview_update_wm
;
8983 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
8984 } else if (IS_G4X(dev
)) {
8985 dev_priv
->display
.write_eld
= g4x_write_eld
;
8986 dev_priv
->display
.update_wm
= g4x_update_wm
;
8987 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
8988 } else if (IS_GEN4(dev
)) {
8989 dev_priv
->display
.update_wm
= i965_update_wm
;
8990 if (IS_CRESTLINE(dev
))
8991 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
8992 else if (IS_BROADWATER(dev
))
8993 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
8994 } else if (IS_GEN3(dev
)) {
8995 dev_priv
->display
.update_wm
= i9xx_update_wm
;
8996 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
8997 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
8998 } else if (IS_I865G(dev
)) {
8999 dev_priv
->display
.update_wm
= i830_update_wm
;
9000 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
9001 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
9002 } else if (IS_I85X(dev
)) {
9003 dev_priv
->display
.update_wm
= i9xx_update_wm
;
9004 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
9005 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
9007 dev_priv
->display
.update_wm
= i830_update_wm
;
9008 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
9010 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
9012 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
9015 /* Default just returns -ENODEV to indicate unsupported */
9016 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
9018 switch (INTEL_INFO(dev
)->gen
) {
9020 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
9024 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
9029 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
9033 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
9036 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
9042 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9043 * resume, or other times. This quirk makes sure that's the case for
9046 static void quirk_pipea_force(struct drm_device
*dev
)
9048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9050 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
9051 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
9055 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9057 static void quirk_ssc_force_disable(struct drm_device
*dev
)
9059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9060 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
9063 struct intel_quirk
{
9065 int subsystem_vendor
;
9066 int subsystem_device
;
9067 void (*hook
)(struct drm_device
*dev
);
9070 struct intel_quirk intel_quirks
[] = {
9071 /* HP Mini needs pipe A force quirk (LP: #322104) */
9072 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
9074 /* Thinkpad R31 needs pipe A force quirk */
9075 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
9076 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9077 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
9079 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9080 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
9081 /* ThinkPad X40 needs pipe A force quirk */
9083 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9084 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
9086 /* 855 & before need to leave pipe A & dpll A up */
9087 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9088 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
9090 /* Lenovo U160 cannot use SSC on LVDS */
9091 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
9093 /* Sony Vaio Y cannot use SSC on LVDS */
9094 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
9097 static void intel_init_quirks(struct drm_device
*dev
)
9099 struct pci_dev
*d
= dev
->pdev
;
9102 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
9103 struct intel_quirk
*q
= &intel_quirks
[i
];
9105 if (d
->device
== q
->device
&&
9106 (d
->subsystem_vendor
== q
->subsystem_vendor
||
9107 q
->subsystem_vendor
== PCI_ANY_ID
) &&
9108 (d
->subsystem_device
== q
->subsystem_device
||
9109 q
->subsystem_device
== PCI_ANY_ID
))
9114 /* Disable the VGA plane that we never use */
9115 static void i915_disable_vga(struct drm_device
*dev
)
9117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9121 if (HAS_PCH_SPLIT(dev
))
9122 vga_reg
= CPU_VGACNTRL
;
9126 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9127 outb(1, VGA_SR_INDEX
);
9128 sr1
= inb(VGA_SR_DATA
);
9129 outb(sr1
| 1<<5, VGA_SR_DATA
);
9130 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
9133 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
9134 POSTING_READ(vga_reg
);
9137 void intel_modeset_init(struct drm_device
*dev
)
9139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9142 drm_mode_config_init(dev
);
9144 dev
->mode_config
.min_width
= 0;
9145 dev
->mode_config
.min_height
= 0;
9147 dev
->mode_config
.preferred_depth
= 24;
9148 dev
->mode_config
.prefer_shadow
= 1;
9150 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
9152 intel_init_quirks(dev
);
9154 intel_init_display(dev
);
9157 dev
->mode_config
.max_width
= 2048;
9158 dev
->mode_config
.max_height
= 2048;
9159 } else if (IS_GEN3(dev
)) {
9160 dev
->mode_config
.max_width
= 4096;
9161 dev
->mode_config
.max_height
= 4096;
9163 dev
->mode_config
.max_width
= 8192;
9164 dev
->mode_config
.max_height
= 8192;
9166 dev
->mode_config
.fb_base
= dev
->agp
->base
;
9168 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9169 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
9171 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
9172 intel_crtc_init(dev
, i
);
9173 ret
= intel_plane_init(dev
, i
);
9175 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
9178 /* Just disable it once at startup */
9179 i915_disable_vga(dev
);
9180 intel_setup_outputs(dev
);
9182 intel_init_clock_gating(dev
);
9184 if (IS_IRONLAKE_M(dev
)) {
9185 ironlake_enable_drps(dev
);
9186 intel_init_emon(dev
);
9189 if (IS_GEN6(dev
) || IS_GEN7(dev
)) {
9190 gen6_enable_rps(dev_priv
);
9191 gen6_update_ring_freq(dev_priv
);
9194 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
9195 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
9196 (unsigned long)dev
);
9199 void intel_modeset_gem_init(struct drm_device
*dev
)
9201 if (IS_IRONLAKE_M(dev
))
9202 ironlake_enable_rc6(dev
);
9204 intel_setup_overlay(dev
);
9207 void intel_modeset_cleanup(struct drm_device
*dev
)
9209 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9210 struct drm_crtc
*crtc
;
9211 struct intel_crtc
*intel_crtc
;
9213 drm_kms_helper_poll_fini(dev
);
9214 mutex_lock(&dev
->struct_mutex
);
9216 intel_unregister_dsm_handler();
9219 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9220 /* Skip inactive CRTCs */
9224 intel_crtc
= to_intel_crtc(crtc
);
9225 intel_increase_pllclock(crtc
);
9228 intel_disable_fbc(dev
);
9230 if (IS_IRONLAKE_M(dev
))
9231 ironlake_disable_drps(dev
);
9232 if (IS_GEN6(dev
) || IS_GEN7(dev
))
9233 gen6_disable_rps(dev
);
9235 if (IS_IRONLAKE_M(dev
))
9236 ironlake_disable_rc6(dev
);
9238 mutex_unlock(&dev
->struct_mutex
);
9240 /* Disable the irq before mode object teardown, for the irq might
9241 * enqueue unpin/hotplug work. */
9242 drm_irq_uninstall(dev
);
9243 cancel_work_sync(&dev_priv
->hotplug_work
);
9244 cancel_work_sync(&dev_priv
->rps_work
);
9246 /* flush any delayed tasks or pending work */
9247 flush_scheduled_work();
9249 /* Shut off idle work before the crtcs get freed. */
9250 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
9251 intel_crtc
= to_intel_crtc(crtc
);
9252 del_timer_sync(&intel_crtc
->idle_timer
);
9254 del_timer_sync(&dev_priv
->idle_timer
);
9255 cancel_work_sync(&dev_priv
->idle_work
);
9257 drm_mode_config_cleanup(dev
);
9261 * Return which encoder is currently attached for connector.
9263 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9265 return &intel_attached_encoder(connector
)->base
;
9268 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9269 struct intel_encoder
*encoder
)
9271 connector
->encoder
= encoder
;
9272 drm_mode_connector_attach_encoder(&connector
->base
,
9277 * set vga decode state - true == enable VGA decode
9279 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9281 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9284 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9286 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9288 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9289 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9293 #ifdef CONFIG_DEBUG_FS
9294 #include <linux/seq_file.h>
9296 struct intel_display_error_state
{
9297 struct intel_cursor_error_state
{
9304 struct intel_pipe_error_state
{
9316 struct intel_plane_error_state
{
9327 struct intel_display_error_state
*
9328 intel_display_capture_error_state(struct drm_device
*dev
)
9330 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9331 struct intel_display_error_state
*error
;
9334 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9338 for (i
= 0; i
< 2; i
++) {
9339 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9340 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9341 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9343 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9344 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9345 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9346 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9347 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9348 if (INTEL_INFO(dev
)->gen
>= 4) {
9349 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9350 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9353 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
9354 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9355 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
9356 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
9357 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
9358 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
9359 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
9360 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
9367 intel_display_print_error_state(struct seq_file
*m
,
9368 struct drm_device
*dev
,
9369 struct intel_display_error_state
*error
)
9373 for (i
= 0; i
< 2; i
++) {
9374 seq_printf(m
, "Pipe [%d]:\n", i
);
9375 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9376 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9377 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9378 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9379 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9380 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9381 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9382 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9384 seq_printf(m
, "Plane [%d]:\n", i
);
9385 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9386 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9387 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9388 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9389 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9390 if (INTEL_INFO(dev
)->gen
>= 4) {
9391 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9392 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9395 seq_printf(m
, "Cursor [%d]:\n", i
);
9396 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9397 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9398 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);