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efd3cf50cb0f6a647d670a0f2a7b886b4e1d0b8a
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
45 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
46
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
53 struct intel_crtc_config *pipe_config);
54
55 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
56 int x, int y, struct drm_framebuffer *old_fb);
57 static int intel_framebuffer_init(struct drm_device *dev,
58 struct intel_framebuffer *ifb,
59 struct drm_mode_fb_cmd2 *mode_cmd,
60 struct drm_i915_gem_object *obj);
61 static void intel_dp_set_m_n(struct intel_crtc *crtc);
62 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
63 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
64 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
65 struct intel_link_m_n *m_n);
66 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
67 static void haswell_set_pipeconf(struct drm_crtc *crtc);
68 static void intel_set_pipe_csc(struct drm_crtc *crtc);
69 static void vlv_prepare_pll(struct intel_crtc *crtc);
70
71 typedef struct {
72 int min, max;
73 } intel_range_t;
74
75 typedef struct {
76 int dot_limit;
77 int p2_slow, p2_fast;
78 } intel_p2_t;
79
80 typedef struct intel_limit intel_limit_t;
81 struct intel_limit {
82 intel_range_t dot, vco, n, m, m1, m2, p, p1;
83 intel_p2_t p2;
84 };
85
86 int
87 intel_pch_rawclk(struct drm_device *dev)
88 {
89 struct drm_i915_private *dev_priv = dev->dev_private;
90
91 WARN_ON(!HAS_PCH_SPLIT(dev));
92
93 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
94 }
95
96 static inline u32 /* units of 100MHz */
97 intel_fdi_link_freq(struct drm_device *dev)
98 {
99 if (IS_GEN5(dev)) {
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
102 } else
103 return 27;
104 }
105
106 static const intel_limit_t intel_limits_i8xx_dac = {
107 .dot = { .min = 25000, .max = 350000 },
108 .vco = { .min = 908000, .max = 1512000 },
109 .n = { .min = 2, .max = 16 },
110 .m = { .min = 96, .max = 140 },
111 .m1 = { .min = 18, .max = 26 },
112 .m2 = { .min = 6, .max = 16 },
113 .p = { .min = 4, .max = 128 },
114 .p1 = { .min = 2, .max = 33 },
115 .p2 = { .dot_limit = 165000,
116 .p2_slow = 4, .p2_fast = 2 },
117 };
118
119 static const intel_limit_t intel_limits_i8xx_dvo = {
120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 908000, .max = 1512000 },
122 .n = { .min = 2, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 4 },
130 };
131
132 static const intel_limit_t intel_limits_i8xx_lvds = {
133 .dot = { .min = 25000, .max = 350000 },
134 .vco = { .min = 908000, .max = 1512000 },
135 .n = { .min = 2, .max = 16 },
136 .m = { .min = 96, .max = 140 },
137 .m1 = { .min = 18, .max = 26 },
138 .m2 = { .min = 6, .max = 16 },
139 .p = { .min = 4, .max = 128 },
140 .p1 = { .min = 1, .max = 6 },
141 .p2 = { .dot_limit = 165000,
142 .p2_slow = 14, .p2_fast = 7 },
143 };
144
145 static const intel_limit_t intel_limits_i9xx_sdvo = {
146 .dot = { .min = 20000, .max = 400000 },
147 .vco = { .min = 1400000, .max = 2800000 },
148 .n = { .min = 1, .max = 6 },
149 .m = { .min = 70, .max = 120 },
150 .m1 = { .min = 8, .max = 18 },
151 .m2 = { .min = 3, .max = 7 },
152 .p = { .min = 5, .max = 80 },
153 .p1 = { .min = 1, .max = 8 },
154 .p2 = { .dot_limit = 200000,
155 .p2_slow = 10, .p2_fast = 5 },
156 };
157
158 static const intel_limit_t intel_limits_i9xx_lvds = {
159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 8, .max = 18 },
164 .m2 = { .min = 3, .max = 7 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
169 };
170
171
172 static const intel_limit_t intel_limits_g4x_sdvo = {
173 .dot = { .min = 25000, .max = 270000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 17, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 10, .max = 30 },
180 .p1 = { .min = 1, .max = 3},
181 .p2 = { .dot_limit = 270000,
182 .p2_slow = 10,
183 .p2_fast = 10
184 },
185 };
186
187 static const intel_limit_t intel_limits_g4x_hdmi = {
188 .dot = { .min = 22000, .max = 400000 },
189 .vco = { .min = 1750000, .max = 3500000},
190 .n = { .min = 1, .max = 4 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 16, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8},
196 .p2 = { .dot_limit = 165000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
201 .dot = { .min = 20000, .max = 115000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 28, .max = 112 },
208 .p1 = { .min = 2, .max = 8 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 14, .p2_fast = 14
211 },
212 };
213
214 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
225 },
226 };
227
228 static const intel_limit_t intel_limits_pineview_sdvo = {
229 .dot = { .min = 20000, .max = 400000},
230 .vco = { .min = 1700000, .max = 3500000 },
231 /* Pineview's Ncounter is a ring counter */
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 /* Pineview only has one combined m divider, which we treat as m2. */
235 .m1 = { .min = 0, .max = 0 },
236 .m2 = { .min = 0, .max = 254 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8 },
239 .p2 = { .dot_limit = 200000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_pineview_lvds = {
244 .dot = { .min = 20000, .max = 400000 },
245 .vco = { .min = 1700000, .max = 3500000 },
246 .n = { .min = 3, .max = 6 },
247 .m = { .min = 2, .max = 256 },
248 .m1 = { .min = 0, .max = 0 },
249 .m2 = { .min = 0, .max = 254 },
250 .p = { .min = 7, .max = 112 },
251 .p1 = { .min = 1, .max = 8 },
252 .p2 = { .dot_limit = 112000,
253 .p2_slow = 14, .p2_fast = 14 },
254 };
255
256 /* Ironlake / Sandybridge
257 *
258 * We calculate clock using (register_value + 2) for N/M1/M2, so here
259 * the range value for them is (actual_value - 2).
260 */
261 static const intel_limit_t intel_limits_ironlake_dac = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 1760000, .max = 3510000 },
264 .n = { .min = 1, .max = 5 },
265 .m = { .min = 79, .max = 127 },
266 .m1 = { .min = 12, .max = 22 },
267 .m2 = { .min = 5, .max = 9 },
268 .p = { .min = 5, .max = 80 },
269 .p1 = { .min = 1, .max = 8 },
270 .p2 = { .dot_limit = 225000,
271 .p2_slow = 10, .p2_fast = 5 },
272 };
273
274 static const intel_limit_t intel_limits_ironlake_single_lvds = {
275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 3 },
278 .m = { .min = 79, .max = 118 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
282 .p1 = { .min = 2, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
285 };
286
287 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 127 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 56 },
295 .p1 = { .min = 2, .max = 8 },
296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
298 };
299
300 /* LVDS 100mhz refclk limits. */
301 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
302 .dot = { .min = 25000, .max = 350000 },
303 .vco = { .min = 1760000, .max = 3510000 },
304 .n = { .min = 1, .max = 2 },
305 .m = { .min = 79, .max = 126 },
306 .m1 = { .min = 12, .max = 22 },
307 .m2 = { .min = 5, .max = 9 },
308 .p = { .min = 28, .max = 112 },
309 .p1 = { .min = 2, .max = 8 },
310 .p2 = { .dot_limit = 225000,
311 .p2_slow = 14, .p2_fast = 14 },
312 };
313
314 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 3 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 14, .max = 42 },
322 .p1 = { .min = 2, .max = 6 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 7, .p2_fast = 7 },
325 };
326
327 static const intel_limit_t intel_limits_vlv = {
328 /*
329 * These are the data rate limits (measured in fast clocks)
330 * since those are the strictest limits we have. The fast
331 * clock and actual rate limits are more relaxed, so checking
332 * them would make no difference.
333 */
334 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
335 .vco = { .min = 4000000, .max = 6000000 },
336 .n = { .min = 1, .max = 7 },
337 .m1 = { .min = 2, .max = 3 },
338 .m2 = { .min = 11, .max = 156 },
339 .p1 = { .min = 2, .max = 3 },
340 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
341 };
342
343 static const intel_limit_t intel_limits_chv = {
344 /*
345 * These are the data rate limits (measured in fast clocks)
346 * since those are the strictest limits we have. The fast
347 * clock and actual rate limits are more relaxed, so checking
348 * them would make no difference.
349 */
350 .dot = { .min = 25000 * 5, .max = 540000 * 5},
351 .vco = { .min = 4860000, .max = 6700000 },
352 .n = { .min = 1, .max = 1 },
353 .m1 = { .min = 2, .max = 2 },
354 .m2 = { .min = 24 << 22, .max = 175 << 22 },
355 .p1 = { .min = 2, .max = 4 },
356 .p2 = { .p2_slow = 1, .p2_fast = 14 },
357 };
358
359 static void vlv_clock(int refclk, intel_clock_t *clock)
360 {
361 clock->m = clock->m1 * clock->m2;
362 clock->p = clock->p1 * clock->p2;
363 if (WARN_ON(clock->n == 0 || clock->p == 0))
364 return;
365 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
366 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
367 }
368
369 /**
370 * Returns whether any output on the specified pipe is of the specified type
371 */
372 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
373 {
374 struct drm_device *dev = crtc->dev;
375 struct intel_encoder *encoder;
376
377 for_each_encoder_on_crtc(dev, crtc, encoder)
378 if (encoder->type == type)
379 return true;
380
381 return false;
382 }
383
384 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
386 {
387 struct drm_device *dev = crtc->dev;
388 const intel_limit_t *limit;
389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
391 if (intel_is_dual_link_lvds(dev)) {
392 if (refclk == 100000)
393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
397 if (refclk == 100000)
398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
402 } else
403 limit = &intel_limits_ironlake_dac;
404
405 return limit;
406 }
407
408 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409 {
410 struct drm_device *dev = crtc->dev;
411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
414 if (intel_is_dual_link_lvds(dev))
415 limit = &intel_limits_g4x_dual_channel_lvds;
416 else
417 limit = &intel_limits_g4x_single_channel_lvds;
418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
420 limit = &intel_limits_g4x_hdmi;
421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
422 limit = &intel_limits_g4x_sdvo;
423 } else /* The option is for other outputs */
424 limit = &intel_limits_i9xx_sdvo;
425
426 return limit;
427 }
428
429 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
430 {
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
434 if (HAS_PCH_SPLIT(dev))
435 limit = intel_ironlake_limit(crtc, refclk);
436 else if (IS_G4X(dev)) {
437 limit = intel_g4x_limit(crtc);
438 } else if (IS_PINEVIEW(dev)) {
439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
440 limit = &intel_limits_pineview_lvds;
441 else
442 limit = &intel_limits_pineview_sdvo;
443 } else if (IS_CHERRYVIEW(dev)) {
444 limit = &intel_limits_chv;
445 } else if (IS_VALLEYVIEW(dev)) {
446 limit = &intel_limits_vlv;
447 } else if (!IS_GEN2(dev)) {
448 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
449 limit = &intel_limits_i9xx_lvds;
450 else
451 limit = &intel_limits_i9xx_sdvo;
452 } else {
453 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
454 limit = &intel_limits_i8xx_lvds;
455 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
456 limit = &intel_limits_i8xx_dvo;
457 else
458 limit = &intel_limits_i8xx_dac;
459 }
460 return limit;
461 }
462
463 /* m1 is reserved as 0 in Pineview, n is a ring counter */
464 static void pineview_clock(int refclk, intel_clock_t *clock)
465 {
466 clock->m = clock->m2 + 2;
467 clock->p = clock->p1 * clock->p2;
468 if (WARN_ON(clock->n == 0 || clock->p == 0))
469 return;
470 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
471 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
472 }
473
474 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
475 {
476 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
477 }
478
479 static void i9xx_clock(int refclk, intel_clock_t *clock)
480 {
481 clock->m = i9xx_dpll_compute_m(clock);
482 clock->p = clock->p1 * clock->p2;
483 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
484 return;
485 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
486 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
487 }
488
489 static void chv_clock(int refclk, intel_clock_t *clock)
490 {
491 clock->m = clock->m1 * clock->m2;
492 clock->p = clock->p1 * clock->p2;
493 if (WARN_ON(clock->n == 0 || clock->p == 0))
494 return;
495 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
496 clock->n << 22);
497 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
498 }
499
500 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
501 /**
502 * Returns whether the given set of divisors are valid for a given refclk with
503 * the given connectors.
504 */
505
506 static bool intel_PLL_is_valid(struct drm_device *dev,
507 const intel_limit_t *limit,
508 const intel_clock_t *clock)
509 {
510 if (clock->n < limit->n.min || limit->n.max < clock->n)
511 INTELPllInvalid("n out of range\n");
512 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
513 INTELPllInvalid("p1 out of range\n");
514 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
515 INTELPllInvalid("m2 out of range\n");
516 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
517 INTELPllInvalid("m1 out of range\n");
518
519 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
520 if (clock->m1 <= clock->m2)
521 INTELPllInvalid("m1 <= m2\n");
522
523 if (!IS_VALLEYVIEW(dev)) {
524 if (clock->p < limit->p.min || limit->p.max < clock->p)
525 INTELPllInvalid("p out of range\n");
526 if (clock->m < limit->m.min || limit->m.max < clock->m)
527 INTELPllInvalid("m out of range\n");
528 }
529
530 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
531 INTELPllInvalid("vco out of range\n");
532 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
533 * connector, etc., rather than just a single range.
534 */
535 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
536 INTELPllInvalid("dot out of range\n");
537
538 return true;
539 }
540
541 static bool
542 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
543 int target, int refclk, intel_clock_t *match_clock,
544 intel_clock_t *best_clock)
545 {
546 struct drm_device *dev = crtc->dev;
547 intel_clock_t clock;
548 int err = target;
549
550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
551 /*
552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
555 */
556 if (intel_is_dual_link_lvds(dev))
557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
567 memset(best_clock, 0, sizeof(*best_clock));
568
569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
573 if (clock.m2 >= clock.m1)
574 break;
575 for (clock.n = limit->n.min;
576 clock.n <= limit->n.max; clock.n++) {
577 for (clock.p1 = limit->p1.min;
578 clock.p1 <= limit->p1.max; clock.p1++) {
579 int this_err;
580
581 i9xx_clock(refclk, &clock);
582 if (!intel_PLL_is_valid(dev, limit,
583 &clock))
584 continue;
585 if (match_clock &&
586 clock.p != match_clock->p)
587 continue;
588
589 this_err = abs(clock.dot - target);
590 if (this_err < err) {
591 *best_clock = clock;
592 err = this_err;
593 }
594 }
595 }
596 }
597 }
598
599 return (err != target);
600 }
601
602 static bool
603 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 for (clock.n = limit->n.min;
635 clock.n <= limit->n.max; clock.n++) {
636 for (clock.p1 = limit->p1.min;
637 clock.p1 <= limit->p1.max; clock.p1++) {
638 int this_err;
639
640 pineview_clock(refclk, &clock);
641 if (!intel_PLL_is_valid(dev, limit,
642 &clock))
643 continue;
644 if (match_clock &&
645 clock.p != match_clock->p)
646 continue;
647
648 this_err = abs(clock.dot - target);
649 if (this_err < err) {
650 *best_clock = clock;
651 err = this_err;
652 }
653 }
654 }
655 }
656 }
657
658 return (err != target);
659 }
660
661 static bool
662 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
663 int target, int refclk, intel_clock_t *match_clock,
664 intel_clock_t *best_clock)
665 {
666 struct drm_device *dev = crtc->dev;
667 intel_clock_t clock;
668 int max_n;
669 bool found;
670 /* approximately equals target * 0.00585 */
671 int err_most = (target >> 8) + (target >> 9);
672 found = false;
673
674 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
675 if (intel_is_dual_link_lvds(dev))
676 clock.p2 = limit->p2.p2_fast;
677 else
678 clock.p2 = limit->p2.p2_slow;
679 } else {
680 if (target < limit->p2.dot_limit)
681 clock.p2 = limit->p2.p2_slow;
682 else
683 clock.p2 = limit->p2.p2_fast;
684 }
685
686 memset(best_clock, 0, sizeof(*best_clock));
687 max_n = limit->n.max;
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
690 /* based on hardware requirement, prefere larger m1,m2 */
691 for (clock.m1 = limit->m1.max;
692 clock.m1 >= limit->m1.min; clock.m1--) {
693 for (clock.m2 = limit->m2.max;
694 clock.m2 >= limit->m2.min; clock.m2--) {
695 for (clock.p1 = limit->p1.max;
696 clock.p1 >= limit->p1.min; clock.p1--) {
697 int this_err;
698
699 i9xx_clock(refclk, &clock);
700 if (!intel_PLL_is_valid(dev, limit,
701 &clock))
702 continue;
703
704 this_err = abs(clock.dot - target);
705 if (this_err < err_most) {
706 *best_clock = clock;
707 err_most = this_err;
708 max_n = clock.n;
709 found = true;
710 }
711 }
712 }
713 }
714 }
715 return found;
716 }
717
718 static bool
719 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722 {
723 struct drm_device *dev = crtc->dev;
724 intel_clock_t clock;
725 unsigned int bestppm = 1000000;
726 /* min update 19.2 MHz */
727 int max_n = min(limit->n.max, refclk / 19200);
728 bool found = false;
729
730 target *= 5; /* fast clock */
731
732 memset(best_clock, 0, sizeof(*best_clock));
733
734 /* based on hardware requirement, prefer smaller n to precision */
735 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
736 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
737 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
738 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
739 clock.p = clock.p1 * clock.p2;
740 /* based on hardware requirement, prefer bigger m1,m2 values */
741 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
742 unsigned int ppm, diff;
743
744 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
745 refclk * clock.m1);
746
747 vlv_clock(refclk, &clock);
748
749 if (!intel_PLL_is_valid(dev, limit,
750 &clock))
751 continue;
752
753 diff = abs(clock.dot - target);
754 ppm = div_u64(1000000ULL * diff, target);
755
756 if (ppm < 100 && clock.p > best_clock->p) {
757 bestppm = 0;
758 *best_clock = clock;
759 found = true;
760 }
761
762 if (bestppm >= 10 && ppm < bestppm - 10) {
763 bestppm = ppm;
764 *best_clock = clock;
765 found = true;
766 }
767 }
768 }
769 }
770 }
771
772 return found;
773 }
774
775 static bool
776 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779 {
780 struct drm_device *dev = crtc->dev;
781 intel_clock_t clock;
782 uint64_t m2;
783 int found = false;
784
785 memset(best_clock, 0, sizeof(*best_clock));
786
787 /*
788 * Based on hardware doc, the n always set to 1, and m1 always
789 * set to 2. If requires to support 200Mhz refclk, we need to
790 * revisit this because n may not 1 anymore.
791 */
792 clock.n = 1, clock.m1 = 2;
793 target *= 5; /* fast clock */
794
795 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
796 for (clock.p2 = limit->p2.p2_fast;
797 clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799
800 clock.p = clock.p1 * clock.p2;
801
802 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
803 clock.n) << 22, refclk * clock.m1);
804
805 if (m2 > INT_MAX/clock.m1)
806 continue;
807
808 clock.m2 = m2;
809
810 chv_clock(refclk, &clock);
811
812 if (!intel_PLL_is_valid(dev, limit, &clock))
813 continue;
814
815 /* based on hardware requirement, prefer bigger p
816 */
817 if (clock.p > best_clock->p) {
818 *best_clock = clock;
819 found = true;
820 }
821 }
822 }
823
824 return found;
825 }
826
827 bool intel_crtc_active(struct drm_crtc *crtc)
828 {
829 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
830
831 /* Be paranoid as we can arrive here with only partial
832 * state retrieved from the hardware during setup.
833 *
834 * We can ditch the adjusted_mode.crtc_clock check as soon
835 * as Haswell has gained clock readout/fastboot support.
836 *
837 * We can ditch the crtc->primary->fb check as soon as we can
838 * properly reconstruct framebuffers.
839 */
840 return intel_crtc->active && crtc->primary->fb &&
841 intel_crtc->config.adjusted_mode.crtc_clock;
842 }
843
844 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
845 enum pipe pipe)
846 {
847 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
849
850 return intel_crtc->config.cpu_transcoder;
851 }
852
853 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
854 {
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
857
858 frame = I915_READ(frame_reg);
859
860 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
861 WARN(1, "vblank wait timed out\n");
862 }
863
864 /**
865 * intel_wait_for_vblank - wait for vblank on a given pipe
866 * @dev: drm device
867 * @pipe: pipe to wait for
868 *
869 * Wait for vblank to occur on a given pipe. Needed for various bits of
870 * mode setting code.
871 */
872 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
873 {
874 struct drm_i915_private *dev_priv = dev->dev_private;
875 int pipestat_reg = PIPESTAT(pipe);
876
877 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
878 g4x_wait_for_vblank(dev, pipe);
879 return;
880 }
881
882 /* Clear existing vblank status. Note this will clear any other
883 * sticky status fields as well.
884 *
885 * This races with i915_driver_irq_handler() with the result
886 * that either function could miss a vblank event. Here it is not
887 * fatal, as we will either wait upon the next vblank interrupt or
888 * timeout. Generally speaking intel_wait_for_vblank() is only
889 * called during modeset at which time the GPU should be idle and
890 * should *not* be performing page flips and thus not waiting on
891 * vblanks...
892 * Currently, the result of us stealing a vblank from the irq
893 * handler is that a single frame will be skipped during swapbuffers.
894 */
895 I915_WRITE(pipestat_reg,
896 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
897
898 /* Wait for vblank interrupt bit to set */
899 if (wait_for(I915_READ(pipestat_reg) &
900 PIPE_VBLANK_INTERRUPT_STATUS,
901 50))
902 DRM_DEBUG_KMS("vblank wait timed out\n");
903 }
904
905 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
906 {
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 u32 reg = PIPEDSL(pipe);
909 u32 line1, line2;
910 u32 line_mask;
911
912 if (IS_GEN2(dev))
913 line_mask = DSL_LINEMASK_GEN2;
914 else
915 line_mask = DSL_LINEMASK_GEN3;
916
917 line1 = I915_READ(reg) & line_mask;
918 mdelay(5);
919 line2 = I915_READ(reg) & line_mask;
920
921 return line1 == line2;
922 }
923
924 /*
925 * intel_wait_for_pipe_off - wait for pipe to turn off
926 * @dev: drm device
927 * @pipe: pipe to wait for
928 *
929 * After disabling a pipe, we can't wait for vblank in the usual way,
930 * spinning on the vblank interrupt status bit, since we won't actually
931 * see an interrupt when the pipe is disabled.
932 *
933 * On Gen4 and above:
934 * wait for the pipe register state bit to turn off
935 *
936 * Otherwise:
937 * wait for the display line value to settle (it usually
938 * ends up stopping at the start of the next frame).
939 *
940 */
941 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
942 {
943 struct drm_i915_private *dev_priv = dev->dev_private;
944 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
945 pipe);
946
947 if (INTEL_INFO(dev)->gen >= 4) {
948 int reg = PIPECONF(cpu_transcoder);
949
950 /* Wait for the Pipe State to go off */
951 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
952 100))
953 WARN(1, "pipe_off wait timed out\n");
954 } else {
955 /* Wait for the display line to settle */
956 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
957 WARN(1, "pipe_off wait timed out\n");
958 }
959 }
960
961 /*
962 * ibx_digital_port_connected - is the specified port connected?
963 * @dev_priv: i915 private structure
964 * @port: the port to test
965 *
966 * Returns true if @port is connected, false otherwise.
967 */
968 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
969 struct intel_digital_port *port)
970 {
971 u32 bit;
972
973 if (HAS_PCH_IBX(dev_priv->dev)) {
974 switch (port->port) {
975 case PORT_B:
976 bit = SDE_PORTB_HOTPLUG;
977 break;
978 case PORT_C:
979 bit = SDE_PORTC_HOTPLUG;
980 break;
981 case PORT_D:
982 bit = SDE_PORTD_HOTPLUG;
983 break;
984 default:
985 return true;
986 }
987 } else {
988 switch (port->port) {
989 case PORT_B:
990 bit = SDE_PORTB_HOTPLUG_CPT;
991 break;
992 case PORT_C:
993 bit = SDE_PORTC_HOTPLUG_CPT;
994 break;
995 case PORT_D:
996 bit = SDE_PORTD_HOTPLUG_CPT;
997 break;
998 default:
999 return true;
1000 }
1001 }
1002
1003 return I915_READ(SDEISR) & bit;
1004 }
1005
1006 static const char *state_string(bool enabled)
1007 {
1008 return enabled ? "on" : "off";
1009 }
1010
1011 /* Only for pre-ILK configs */
1012 void assert_pll(struct drm_i915_private *dev_priv,
1013 enum pipe pipe, bool state)
1014 {
1015 int reg;
1016 u32 val;
1017 bool cur_state;
1018
1019 reg = DPLL(pipe);
1020 val = I915_READ(reg);
1021 cur_state = !!(val & DPLL_VCO_ENABLE);
1022 WARN(cur_state != state,
1023 "PLL state assertion failure (expected %s, current %s)\n",
1024 state_string(state), state_string(cur_state));
1025 }
1026
1027 /* XXX: the dsi pll is shared between MIPI DSI ports */
1028 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1029 {
1030 u32 val;
1031 bool cur_state;
1032
1033 mutex_lock(&dev_priv->dpio_lock);
1034 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1035 mutex_unlock(&dev_priv->dpio_lock);
1036
1037 cur_state = val & DSI_PLL_VCO_EN;
1038 WARN(cur_state != state,
1039 "DSI PLL state assertion failure (expected %s, current %s)\n",
1040 state_string(state), state_string(cur_state));
1041 }
1042 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1043 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1044
1045 struct intel_shared_dpll *
1046 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1047 {
1048 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1049
1050 if (crtc->config.shared_dpll < 0)
1051 return NULL;
1052
1053 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1054 }
1055
1056 /* For ILK+ */
1057 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1058 struct intel_shared_dpll *pll,
1059 bool state)
1060 {
1061 bool cur_state;
1062 struct intel_dpll_hw_state hw_state;
1063
1064 if (HAS_PCH_LPT(dev_priv->dev)) {
1065 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1066 return;
1067 }
1068
1069 if (WARN (!pll,
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1071 return;
1072
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081 {
1082 int reg;
1083 u32 val;
1084 bool cur_state;
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
1087
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124 {
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130 return;
1131
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1134 return;
1135
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155
1156 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158 {
1159 int pp_reg, lvds_reg;
1160 u32 val;
1161 enum pipe panel_pipe = PIPE_A;
1162 bool locked = true;
1163
1164 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1165 pp_reg = PCH_PP_CONTROL;
1166 lvds_reg = PCH_LVDS;
1167 } else {
1168 pp_reg = PP_CONTROL;
1169 lvds_reg = LVDS;
1170 }
1171
1172 val = I915_READ(pp_reg);
1173 if (!(val & PANEL_POWER_ON) ||
1174 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1175 locked = false;
1176
1177 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1178 panel_pipe = PIPE_B;
1179
1180 WARN(panel_pipe == pipe && locked,
1181 "panel assertion failure, pipe %c regs locked\n",
1182 pipe_name(pipe));
1183 }
1184
1185 static void assert_cursor(struct drm_i915_private *dev_priv,
1186 enum pipe pipe, bool state)
1187 {
1188 struct drm_device *dev = dev_priv->dev;
1189 bool cur_state;
1190
1191 if (IS_845G(dev) || IS_I865G(dev))
1192 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1193 else
1194 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1195
1196 WARN(cur_state != state,
1197 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1198 pipe_name(pipe), state_string(state), state_string(cur_state));
1199 }
1200 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1201 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1202
1203 void assert_pipe(struct drm_i915_private *dev_priv,
1204 enum pipe pipe, bool state)
1205 {
1206 int reg;
1207 u32 val;
1208 bool cur_state;
1209 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1210 pipe);
1211
1212 /* if we need the pipe A quirk it must be always on */
1213 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1214 state = true;
1215
1216 if (!intel_display_power_enabled(dev_priv,
1217 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1218 cur_state = false;
1219 } else {
1220 reg = PIPECONF(cpu_transcoder);
1221 val = I915_READ(reg);
1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 }
1224
1225 WARN(cur_state != state,
1226 "pipe %c assertion failure (expected %s, current %s)\n",
1227 pipe_name(pipe), state_string(state), state_string(cur_state));
1228 }
1229
1230 static void assert_plane(struct drm_i915_private *dev_priv,
1231 enum plane plane, bool state)
1232 {
1233 int reg;
1234 u32 val;
1235 bool cur_state;
1236
1237 reg = DSPCNTR(plane);
1238 val = I915_READ(reg);
1239 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1240 WARN(cur_state != state,
1241 "plane %c assertion failure (expected %s, current %s)\n",
1242 plane_name(plane), state_string(state), state_string(cur_state));
1243 }
1244
1245 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1246 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1247
1248 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1249 enum pipe pipe)
1250 {
1251 struct drm_device *dev = dev_priv->dev;
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
1256 /* Primary planes are fixed to pipes on gen4+ */
1257 if (INTEL_INFO(dev)->gen >= 4) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN(val & DISPLAY_PLANE_ENABLE,
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
1263 return;
1264 }
1265
1266 /* Need to check both planes against the pipe */
1267 for_each_pipe(i) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
1275 }
1276 }
1277
1278 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1279 enum pipe pipe)
1280 {
1281 struct drm_device *dev = dev_priv->dev;
1282 int reg, sprite;
1283 u32 val;
1284
1285 if (IS_VALLEYVIEW(dev)) {
1286 for_each_sprite(pipe, sprite) {
1287 reg = SPCNTR(pipe, sprite);
1288 val = I915_READ(reg);
1289 WARN(val & SP_ENABLE,
1290 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1291 sprite_name(pipe, sprite), pipe_name(pipe));
1292 }
1293 } else if (INTEL_INFO(dev)->gen >= 7) {
1294 reg = SPRCTL(pipe);
1295 val = I915_READ(reg);
1296 WARN(val & SPRITE_ENABLE,
1297 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1298 plane_name(pipe), pipe_name(pipe));
1299 } else if (INTEL_INFO(dev)->gen >= 5) {
1300 reg = DVSCNTR(pipe);
1301 val = I915_READ(reg);
1302 WARN(val & DVS_ENABLE,
1303 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1304 plane_name(pipe), pipe_name(pipe));
1305 }
1306 }
1307
1308 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1309 {
1310 u32 val;
1311 bool enabled;
1312
1313 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1314
1315 val = I915_READ(PCH_DREF_CONTROL);
1316 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1317 DREF_SUPERSPREAD_SOURCE_MASK));
1318 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1319 }
1320
1321 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1322 enum pipe pipe)
1323 {
1324 int reg;
1325 u32 val;
1326 bool enabled;
1327
1328 reg = PCH_TRANSCONF(pipe);
1329 val = I915_READ(reg);
1330 enabled = !!(val & TRANS_ENABLE);
1331 WARN(enabled,
1332 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1333 pipe_name(pipe));
1334 }
1335
1336 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe, u32 port_sel, u32 val)
1338 {
1339 if ((val & DP_PORT_EN) == 0)
1340 return false;
1341
1342 if (HAS_PCH_CPT(dev_priv->dev)) {
1343 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1344 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1345 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1346 return false;
1347 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1348 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1349 return false;
1350 } else {
1351 if ((val & DP_PIPE_MASK) != (pipe << 30))
1352 return false;
1353 }
1354 return true;
1355 }
1356
1357 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1358 enum pipe pipe, u32 val)
1359 {
1360 if ((val & SDVO_ENABLE) == 0)
1361 return false;
1362
1363 if (HAS_PCH_CPT(dev_priv->dev)) {
1364 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1365 return false;
1366 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1367 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1368 return false;
1369 } else {
1370 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1371 return false;
1372 }
1373 return true;
1374 }
1375
1376 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1377 enum pipe pipe, u32 val)
1378 {
1379 if ((val & LVDS_PORT_EN) == 0)
1380 return false;
1381
1382 if (HAS_PCH_CPT(dev_priv->dev)) {
1383 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1384 return false;
1385 } else {
1386 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1387 return false;
1388 }
1389 return true;
1390 }
1391
1392 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1393 enum pipe pipe, u32 val)
1394 {
1395 if ((val & ADPA_DAC_ENABLE) == 0)
1396 return false;
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1399 return false;
1400 } else {
1401 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1402 return false;
1403 }
1404 return true;
1405 }
1406
1407 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg, u32 port_sel)
1409 {
1410 u32 val = I915_READ(reg);
1411 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1412 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1413 reg, pipe_name(pipe));
1414
1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1416 && (val & DP_PIPEB_SELECT),
1417 "IBX PCH dp port still using transcoder B\n");
1418 }
1419
1420 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1421 enum pipe pipe, int reg)
1422 {
1423 u32 val = I915_READ(reg);
1424 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1425 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1426 reg, pipe_name(pipe));
1427
1428 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1429 && (val & SDVO_PIPE_B_SELECT),
1430 "IBX PCH hdmi port still using transcoder B\n");
1431 }
1432
1433 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1434 enum pipe pipe)
1435 {
1436 int reg;
1437 u32 val;
1438
1439 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1440 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1441 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1442
1443 reg = PCH_ADPA;
1444 val = I915_READ(reg);
1445 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1446 "PCH VGA enabled on transcoder %c, should be disabled\n",
1447 pipe_name(pipe));
1448
1449 reg = PCH_LVDS;
1450 val = I915_READ(reg);
1451 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1452 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1453 pipe_name(pipe));
1454
1455 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1456 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1457 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1458 }
1459
1460 static void intel_init_dpio(struct drm_device *dev)
1461 {
1462 struct drm_i915_private *dev_priv = dev->dev_private;
1463
1464 if (!IS_VALLEYVIEW(dev))
1465 return;
1466
1467 /*
1468 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1469 * CHV x1 PHY (DP/HDMI D)
1470 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1471 */
1472 if (IS_CHERRYVIEW(dev)) {
1473 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1474 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1475 } else {
1476 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1477 }
1478 }
1479
1480 static void intel_reset_dpio(struct drm_device *dev)
1481 {
1482 struct drm_i915_private *dev_priv = dev->dev_private;
1483
1484 if (!IS_VALLEYVIEW(dev))
1485 return;
1486
1487 if (IS_CHERRYVIEW(dev)) {
1488 enum dpio_phy phy;
1489 u32 val;
1490
1491 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1492 /* Poll for phypwrgood signal */
1493 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1494 PHY_POWERGOOD(phy), 1))
1495 DRM_ERROR("Display PHY %d is not power up\n", phy);
1496
1497 /*
1498 * Deassert common lane reset for PHY.
1499 *
1500 * This should only be done on init and resume from S3
1501 * with both PLLs disabled, or we risk losing DPIO and
1502 * PLL synchronization.
1503 */
1504 val = I915_READ(DISPLAY_PHY_CONTROL);
1505 I915_WRITE(DISPLAY_PHY_CONTROL,
1506 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1507 }
1508
1509 } else {
1510 /*
1511 * If DPIO has already been reset, e.g. by BIOS, just skip all
1512 * this.
1513 */
1514 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1515 return;
1516
1517 /*
1518 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1519 * Need to assert and de-assert PHY SB reset by gating the
1520 * common lane power, then un-gating it.
1521 * Simply ungating isn't enough to reset the PHY enough to get
1522 * ports and lanes running.
1523 */
1524 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1525 false);
1526 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1527 true);
1528 }
1529 }
1530
1531 static void vlv_enable_pll(struct intel_crtc *crtc)
1532 {
1533 struct drm_device *dev = crtc->base.dev;
1534 struct drm_i915_private *dev_priv = dev->dev_private;
1535 int reg = DPLL(crtc->pipe);
1536 u32 dpll = crtc->config.dpll_hw_state.dpll;
1537
1538 assert_pipe_disabled(dev_priv, crtc->pipe);
1539
1540 /* No really, not for ILK+ */
1541 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1542
1543 /* PLL is protected by panel, make sure we can write it */
1544 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1545 assert_panel_unlocked(dev_priv, crtc->pipe);
1546
1547 I915_WRITE(reg, dpll);
1548 POSTING_READ(reg);
1549 udelay(150);
1550
1551 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1552 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1553
1554 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1555 POSTING_READ(DPLL_MD(crtc->pipe));
1556
1557 /* We do this three times for luck */
1558 I915_WRITE(reg, dpll);
1559 POSTING_READ(reg);
1560 udelay(150); /* wait for warmup */
1561 I915_WRITE(reg, dpll);
1562 POSTING_READ(reg);
1563 udelay(150); /* wait for warmup */
1564 I915_WRITE(reg, dpll);
1565 POSTING_READ(reg);
1566 udelay(150); /* wait for warmup */
1567 }
1568
1569 static void chv_enable_pll(struct intel_crtc *crtc)
1570 {
1571 struct drm_device *dev = crtc->base.dev;
1572 struct drm_i915_private *dev_priv = dev->dev_private;
1573 int pipe = crtc->pipe;
1574 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1575 u32 tmp;
1576
1577 assert_pipe_disabled(dev_priv, crtc->pipe);
1578
1579 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1580
1581 mutex_lock(&dev_priv->dpio_lock);
1582
1583 /* Enable back the 10bit clock to display controller */
1584 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1585 tmp |= DPIO_DCLKP_EN;
1586 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1587
1588 /*
1589 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1590 */
1591 udelay(1);
1592
1593 /* Enable PLL */
1594 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1595
1596 /* Check PLL is locked */
1597 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1598 DRM_ERROR("PLL %d failed to lock\n", pipe);
1599
1600 /* not sure when this should be written */
1601 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1602 POSTING_READ(DPLL_MD(pipe));
1603
1604 mutex_unlock(&dev_priv->dpio_lock);
1605 }
1606
1607 static void i9xx_enable_pll(struct intel_crtc *crtc)
1608 {
1609 struct drm_device *dev = crtc->base.dev;
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 int reg = DPLL(crtc->pipe);
1612 u32 dpll = crtc->config.dpll_hw_state.dpll;
1613
1614 assert_pipe_disabled(dev_priv, crtc->pipe);
1615
1616 /* No really, not for ILK+ */
1617 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1618
1619 /* PLL is protected by panel, make sure we can write it */
1620 if (IS_MOBILE(dev) && !IS_I830(dev))
1621 assert_panel_unlocked(dev_priv, crtc->pipe);
1622
1623 I915_WRITE(reg, dpll);
1624
1625 /* Wait for the clocks to stabilize. */
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (INTEL_INFO(dev)->gen >= 4) {
1630 I915_WRITE(DPLL_MD(crtc->pipe),
1631 crtc->config.dpll_hw_state.dpll_md);
1632 } else {
1633 /* The pixel multiplier can only be updated once the
1634 * DPLL is enabled and the clocks are stable.
1635 *
1636 * So write it again.
1637 */
1638 I915_WRITE(reg, dpll);
1639 }
1640
1641 /* We do this three times for luck */
1642 I915_WRITE(reg, dpll);
1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645 I915_WRITE(reg, dpll);
1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
1648 I915_WRITE(reg, dpll);
1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651 }
1652
1653 /**
1654 * i9xx_disable_pll - disable a PLL
1655 * @dev_priv: i915 private structure
1656 * @pipe: pipe PLL to disable
1657 *
1658 * Disable the PLL for @pipe, making sure the pipe is off first.
1659 *
1660 * Note! This is for pre-ILK only.
1661 */
1662 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1663 {
1664 /* Don't disable pipe A or pipe A PLLs if needed */
1665 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1666 return;
1667
1668 /* Make sure the pipe isn't still relying on us */
1669 assert_pipe_disabled(dev_priv, pipe);
1670
1671 I915_WRITE(DPLL(pipe), 0);
1672 POSTING_READ(DPLL(pipe));
1673 }
1674
1675 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1676 {
1677 u32 val = 0;
1678
1679 /* Make sure the pipe isn't still relying on us */
1680 assert_pipe_disabled(dev_priv, pipe);
1681
1682 /*
1683 * Leave integrated clock source and reference clock enabled for pipe B.
1684 * The latter is needed for VGA hotplug / manual detection.
1685 */
1686 if (pipe == PIPE_B)
1687 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1688 I915_WRITE(DPLL(pipe), val);
1689 POSTING_READ(DPLL(pipe));
1690
1691 }
1692
1693 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1694 {
1695 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1696 u32 val;
1697
1698 /* Make sure the pipe isn't still relying on us */
1699 assert_pipe_disabled(dev_priv, pipe);
1700
1701 /* Set PLL en = 0 */
1702 val = DPLL_SSC_REF_CLOCK_CHV;
1703 if (pipe != PIPE_A)
1704 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1705 I915_WRITE(DPLL(pipe), val);
1706 POSTING_READ(DPLL(pipe));
1707
1708 mutex_lock(&dev_priv->dpio_lock);
1709
1710 /* Disable 10bit clock to display controller */
1711 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1712 val &= ~DPIO_DCLKP_EN;
1713 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1714
1715 mutex_unlock(&dev_priv->dpio_lock);
1716 }
1717
1718 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1719 struct intel_digital_port *dport)
1720 {
1721 u32 port_mask;
1722 int dpll_reg;
1723
1724 switch (dport->port) {
1725 case PORT_B:
1726 port_mask = DPLL_PORTB_READY_MASK;
1727 dpll_reg = DPLL(0);
1728 break;
1729 case PORT_C:
1730 port_mask = DPLL_PORTC_READY_MASK;
1731 dpll_reg = DPLL(0);
1732 break;
1733 case PORT_D:
1734 port_mask = DPLL_PORTD_READY_MASK;
1735 dpll_reg = DPIO_PHY_STATUS;
1736 break;
1737 default:
1738 BUG();
1739 }
1740
1741 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1742 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1743 port_name(dport->port), I915_READ(dpll_reg));
1744 }
1745
1746 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1747 {
1748 struct drm_device *dev = crtc->base.dev;
1749 struct drm_i915_private *dev_priv = dev->dev_private;
1750 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1751
1752 WARN_ON(!pll->refcount);
1753 if (pll->active == 0) {
1754 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1755 WARN_ON(pll->on);
1756 assert_shared_dpll_disabled(dev_priv, pll);
1757
1758 pll->mode_set(dev_priv, pll);
1759 }
1760 }
1761
1762 /**
1763 * intel_enable_shared_dpll - enable PCH PLL
1764 * @dev_priv: i915 private structure
1765 * @pipe: pipe PLL to enable
1766 *
1767 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1768 * drives the transcoder clock.
1769 */
1770 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1771 {
1772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1775
1776 if (WARN_ON(pll == NULL))
1777 return;
1778
1779 if (WARN_ON(pll->refcount == 0))
1780 return;
1781
1782 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1783 pll->name, pll->active, pll->on,
1784 crtc->base.base.id);
1785
1786 if (pll->active++) {
1787 WARN_ON(!pll->on);
1788 assert_shared_dpll_enabled(dev_priv, pll);
1789 return;
1790 }
1791 WARN_ON(pll->on);
1792
1793 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1794 pll->enable(dev_priv, pll);
1795 pll->on = true;
1796 }
1797
1798 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1799 {
1800 struct drm_device *dev = crtc->base.dev;
1801 struct drm_i915_private *dev_priv = dev->dev_private;
1802 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1803
1804 /* PCH only available on ILK+ */
1805 BUG_ON(INTEL_INFO(dev)->gen < 5);
1806 if (WARN_ON(pll == NULL))
1807 return;
1808
1809 if (WARN_ON(pll->refcount == 0))
1810 return;
1811
1812 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1815
1816 if (WARN_ON(pll->active == 0)) {
1817 assert_shared_dpll_disabled(dev_priv, pll);
1818 return;
1819 }
1820
1821 assert_shared_dpll_enabled(dev_priv, pll);
1822 WARN_ON(!pll->on);
1823 if (--pll->active)
1824 return;
1825
1826 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1827 pll->disable(dev_priv, pll);
1828 pll->on = false;
1829 }
1830
1831 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1832 enum pipe pipe)
1833 {
1834 struct drm_device *dev = dev_priv->dev;
1835 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1837 uint32_t reg, val, pipeconf_val;
1838
1839 /* PCH only available on ILK+ */
1840 BUG_ON(INTEL_INFO(dev)->gen < 5);
1841
1842 /* Make sure PCH DPLL is enabled */
1843 assert_shared_dpll_enabled(dev_priv,
1844 intel_crtc_to_shared_dpll(intel_crtc));
1845
1846 /* FDI must be feeding us bits for PCH ports */
1847 assert_fdi_tx_enabled(dev_priv, pipe);
1848 assert_fdi_rx_enabled(dev_priv, pipe);
1849
1850 if (HAS_PCH_CPT(dev)) {
1851 /* Workaround: Set the timing override bit before enabling the
1852 * pch transcoder. */
1853 reg = TRANS_CHICKEN2(pipe);
1854 val = I915_READ(reg);
1855 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1856 I915_WRITE(reg, val);
1857 }
1858
1859 reg = PCH_TRANSCONF(pipe);
1860 val = I915_READ(reg);
1861 pipeconf_val = I915_READ(PIPECONF(pipe));
1862
1863 if (HAS_PCH_IBX(dev_priv->dev)) {
1864 /*
1865 * make the BPC in transcoder be consistent with
1866 * that in pipeconf reg.
1867 */
1868 val &= ~PIPECONF_BPC_MASK;
1869 val |= pipeconf_val & PIPECONF_BPC_MASK;
1870 }
1871
1872 val &= ~TRANS_INTERLACE_MASK;
1873 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1874 if (HAS_PCH_IBX(dev_priv->dev) &&
1875 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1876 val |= TRANS_LEGACY_INTERLACED_ILK;
1877 else
1878 val |= TRANS_INTERLACED;
1879 else
1880 val |= TRANS_PROGRESSIVE;
1881
1882 I915_WRITE(reg, val | TRANS_ENABLE);
1883 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1884 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1885 }
1886
1887 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1888 enum transcoder cpu_transcoder)
1889 {
1890 u32 val, pipeconf_val;
1891
1892 /* PCH only available on ILK+ */
1893 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1894
1895 /* FDI must be feeding us bits for PCH ports */
1896 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1897 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1898
1899 /* Workaround: set timing override bit. */
1900 val = I915_READ(_TRANSA_CHICKEN2);
1901 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1902 I915_WRITE(_TRANSA_CHICKEN2, val);
1903
1904 val = TRANS_ENABLE;
1905 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1906
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1908 PIPECONF_INTERLACED_ILK)
1909 val |= TRANS_INTERLACED;
1910 else
1911 val |= TRANS_PROGRESSIVE;
1912
1913 I915_WRITE(LPT_TRANSCONF, val);
1914 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1915 DRM_ERROR("Failed to enable PCH transcoder\n");
1916 }
1917
1918 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1919 enum pipe pipe)
1920 {
1921 struct drm_device *dev = dev_priv->dev;
1922 uint32_t reg, val;
1923
1924 /* FDI relies on the transcoder */
1925 assert_fdi_tx_disabled(dev_priv, pipe);
1926 assert_fdi_rx_disabled(dev_priv, pipe);
1927
1928 /* Ports must be off as well */
1929 assert_pch_ports_disabled(dev_priv, pipe);
1930
1931 reg = PCH_TRANSCONF(pipe);
1932 val = I915_READ(reg);
1933 val &= ~TRANS_ENABLE;
1934 I915_WRITE(reg, val);
1935 /* wait for PCH transcoder off, transcoder state */
1936 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1937 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1938
1939 if (!HAS_PCH_IBX(dev)) {
1940 /* Workaround: Clear the timing override chicken bit again. */
1941 reg = TRANS_CHICKEN2(pipe);
1942 val = I915_READ(reg);
1943 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1944 I915_WRITE(reg, val);
1945 }
1946 }
1947
1948 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1949 {
1950 u32 val;
1951
1952 val = I915_READ(LPT_TRANSCONF);
1953 val &= ~TRANS_ENABLE;
1954 I915_WRITE(LPT_TRANSCONF, val);
1955 /* wait for PCH transcoder off, transcoder state */
1956 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1957 DRM_ERROR("Failed to disable PCH transcoder\n");
1958
1959 /* Workaround: clear timing override bit. */
1960 val = I915_READ(_TRANSA_CHICKEN2);
1961 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1962 I915_WRITE(_TRANSA_CHICKEN2, val);
1963 }
1964
1965 /**
1966 * intel_enable_pipe - enable a pipe, asserting requirements
1967 * @crtc: crtc responsible for the pipe
1968 *
1969 * Enable @crtc's pipe, making sure that various hardware specific requirements
1970 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1971 */
1972 static void intel_enable_pipe(struct intel_crtc *crtc)
1973 {
1974 struct drm_device *dev = crtc->base.dev;
1975 struct drm_i915_private *dev_priv = dev->dev_private;
1976 enum pipe pipe = crtc->pipe;
1977 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1978 pipe);
1979 enum pipe pch_transcoder;
1980 int reg;
1981 u32 val;
1982
1983 assert_planes_disabled(dev_priv, pipe);
1984 assert_cursor_disabled(dev_priv, pipe);
1985 assert_sprites_disabled(dev_priv, pipe);
1986
1987 if (HAS_PCH_LPT(dev_priv->dev))
1988 pch_transcoder = TRANSCODER_A;
1989 else
1990 pch_transcoder = pipe;
1991
1992 /*
1993 * A pipe without a PLL won't actually be able to drive bits from
1994 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1995 * need the check.
1996 */
1997 if (!HAS_PCH_SPLIT(dev_priv->dev))
1998 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
1999 assert_dsi_pll_enabled(dev_priv);
2000 else
2001 assert_pll_enabled(dev_priv, pipe);
2002 else {
2003 if (crtc->config.has_pch_encoder) {
2004 /* if driving the PCH, we need FDI enabled */
2005 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2006 assert_fdi_tx_pll_enabled(dev_priv,
2007 (enum pipe) cpu_transcoder);
2008 }
2009 /* FIXME: assert CPU port conditions for SNB+ */
2010 }
2011
2012 reg = PIPECONF(cpu_transcoder);
2013 val = I915_READ(reg);
2014 if (val & PIPECONF_ENABLE) {
2015 WARN_ON(!(pipe == PIPE_A &&
2016 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2017 return;
2018 }
2019
2020 I915_WRITE(reg, val | PIPECONF_ENABLE);
2021 POSTING_READ(reg);
2022 }
2023
2024 /**
2025 * intel_disable_pipe - disable a pipe, asserting requirements
2026 * @dev_priv: i915 private structure
2027 * @pipe: pipe to disable
2028 *
2029 * Disable @pipe, making sure that various hardware specific requirements
2030 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2031 *
2032 * @pipe should be %PIPE_A or %PIPE_B.
2033 *
2034 * Will wait until the pipe has shut down before returning.
2035 */
2036 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2037 enum pipe pipe)
2038 {
2039 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2040 pipe);
2041 int reg;
2042 u32 val;
2043
2044 /*
2045 * Make sure planes won't keep trying to pump pixels to us,
2046 * or we might hang the display.
2047 */
2048 assert_planes_disabled(dev_priv, pipe);
2049 assert_cursor_disabled(dev_priv, pipe);
2050 assert_sprites_disabled(dev_priv, pipe);
2051
2052 /* Don't disable pipe A or pipe A PLLs if needed */
2053 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2054 return;
2055
2056 reg = PIPECONF(cpu_transcoder);
2057 val = I915_READ(reg);
2058 if ((val & PIPECONF_ENABLE) == 0)
2059 return;
2060
2061 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2062 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2063 }
2064
2065 /*
2066 * Plane regs are double buffered, going from enabled->disabled needs a
2067 * trigger in order to latch. The display address reg provides this.
2068 */
2069 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2070 enum plane plane)
2071 {
2072 struct drm_device *dev = dev_priv->dev;
2073 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2074
2075 I915_WRITE(reg, I915_READ(reg));
2076 POSTING_READ(reg);
2077 }
2078
2079 /**
2080 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2081 * @dev_priv: i915 private structure
2082 * @plane: plane to enable
2083 * @pipe: pipe being fed
2084 *
2085 * Enable @plane on @pipe, making sure that @pipe is running first.
2086 */
2087 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2088 enum plane plane, enum pipe pipe)
2089 {
2090 struct intel_crtc *intel_crtc =
2091 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2092 int reg;
2093 u32 val;
2094
2095 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2096 assert_pipe_enabled(dev_priv, pipe);
2097
2098 if (intel_crtc->primary_enabled)
2099 return;
2100
2101 intel_crtc->primary_enabled = true;
2102
2103 reg = DSPCNTR(plane);
2104 val = I915_READ(reg);
2105 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2106
2107 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2108 intel_flush_primary_plane(dev_priv, plane);
2109 }
2110
2111 /**
2112 * intel_disable_primary_hw_plane - disable the primary hardware plane
2113 * @dev_priv: i915 private structure
2114 * @plane: plane to disable
2115 * @pipe: pipe consuming the data
2116 *
2117 * Disable @plane; should be an independent operation.
2118 */
2119 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2120 enum plane plane, enum pipe pipe)
2121 {
2122 struct intel_crtc *intel_crtc =
2123 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2124 int reg;
2125 u32 val;
2126
2127 if (!intel_crtc->primary_enabled)
2128 return;
2129
2130 intel_crtc->primary_enabled = false;
2131
2132 reg = DSPCNTR(plane);
2133 val = I915_READ(reg);
2134 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2135
2136 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2137 intel_flush_primary_plane(dev_priv, plane);
2138 }
2139
2140 static bool need_vtd_wa(struct drm_device *dev)
2141 {
2142 #ifdef CONFIG_INTEL_IOMMU
2143 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2144 return true;
2145 #endif
2146 return false;
2147 }
2148
2149 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2150 {
2151 int tile_height;
2152
2153 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2154 return ALIGN(height, tile_height);
2155 }
2156
2157 int
2158 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2159 struct drm_i915_gem_object *obj,
2160 struct intel_engine_cs *pipelined)
2161 {
2162 struct drm_i915_private *dev_priv = dev->dev_private;
2163 u32 alignment;
2164 int ret;
2165
2166 switch (obj->tiling_mode) {
2167 case I915_TILING_NONE:
2168 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2169 alignment = 128 * 1024;
2170 else if (INTEL_INFO(dev)->gen >= 4)
2171 alignment = 4 * 1024;
2172 else
2173 alignment = 64 * 1024;
2174 break;
2175 case I915_TILING_X:
2176 /* pin() will align the object as required by fence */
2177 alignment = 0;
2178 break;
2179 case I915_TILING_Y:
2180 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2181 return -EINVAL;
2182 default:
2183 BUG();
2184 }
2185
2186 /* Note that the w/a also requires 64 PTE of padding following the
2187 * bo. We currently fill all unused PTE with the shadow page and so
2188 * we should always have valid PTE following the scanout preventing
2189 * the VT-d warning.
2190 */
2191 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2192 alignment = 256 * 1024;
2193
2194 dev_priv->mm.interruptible = false;
2195 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2196 if (ret)
2197 goto err_interruptible;
2198
2199 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2200 * fence, whereas 965+ only requires a fence if using
2201 * framebuffer compression. For simplicity, we always install
2202 * a fence as the cost is not that onerous.
2203 */
2204 ret = i915_gem_object_get_fence(obj);
2205 if (ret)
2206 goto err_unpin;
2207
2208 i915_gem_object_pin_fence(obj);
2209
2210 dev_priv->mm.interruptible = true;
2211 return 0;
2212
2213 err_unpin:
2214 i915_gem_object_unpin_from_display_plane(obj);
2215 err_interruptible:
2216 dev_priv->mm.interruptible = true;
2217 return ret;
2218 }
2219
2220 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2221 {
2222 i915_gem_object_unpin_fence(obj);
2223 i915_gem_object_unpin_from_display_plane(obj);
2224 }
2225
2226 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2227 * is assumed to be a power-of-two. */
2228 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2229 unsigned int tiling_mode,
2230 unsigned int cpp,
2231 unsigned int pitch)
2232 {
2233 if (tiling_mode != I915_TILING_NONE) {
2234 unsigned int tile_rows, tiles;
2235
2236 tile_rows = *y / 8;
2237 *y %= 8;
2238
2239 tiles = *x / (512/cpp);
2240 *x %= 512/cpp;
2241
2242 return tile_rows * pitch * 8 + tiles * 4096;
2243 } else {
2244 unsigned int offset;
2245
2246 offset = *y * pitch + *x * cpp;
2247 *y = 0;
2248 *x = (offset & 4095) / cpp;
2249 return offset & -4096;
2250 }
2251 }
2252
2253 int intel_format_to_fourcc(int format)
2254 {
2255 switch (format) {
2256 case DISPPLANE_8BPP:
2257 return DRM_FORMAT_C8;
2258 case DISPPLANE_BGRX555:
2259 return DRM_FORMAT_XRGB1555;
2260 case DISPPLANE_BGRX565:
2261 return DRM_FORMAT_RGB565;
2262 default:
2263 case DISPPLANE_BGRX888:
2264 return DRM_FORMAT_XRGB8888;
2265 case DISPPLANE_RGBX888:
2266 return DRM_FORMAT_XBGR8888;
2267 case DISPPLANE_BGRX101010:
2268 return DRM_FORMAT_XRGB2101010;
2269 case DISPPLANE_RGBX101010:
2270 return DRM_FORMAT_XBGR2101010;
2271 }
2272 }
2273
2274 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2275 struct intel_plane_config *plane_config)
2276 {
2277 struct drm_device *dev = crtc->base.dev;
2278 struct drm_i915_gem_object *obj = NULL;
2279 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2280 u32 base = plane_config->base;
2281
2282 if (plane_config->size == 0)
2283 return false;
2284
2285 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2286 plane_config->size);
2287 if (!obj)
2288 return false;
2289
2290 if (plane_config->tiled) {
2291 obj->tiling_mode = I915_TILING_X;
2292 obj->stride = crtc->base.primary->fb->pitches[0];
2293 }
2294
2295 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2296 mode_cmd.width = crtc->base.primary->fb->width;
2297 mode_cmd.height = crtc->base.primary->fb->height;
2298 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2299
2300 mutex_lock(&dev->struct_mutex);
2301
2302 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2303 &mode_cmd, obj)) {
2304 DRM_DEBUG_KMS("intel fb init failed\n");
2305 goto out_unref_obj;
2306 }
2307
2308 mutex_unlock(&dev->struct_mutex);
2309
2310 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2311 return true;
2312
2313 out_unref_obj:
2314 drm_gem_object_unreference(&obj->base);
2315 mutex_unlock(&dev->struct_mutex);
2316 return false;
2317 }
2318
2319 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2320 struct intel_plane_config *plane_config)
2321 {
2322 struct drm_device *dev = intel_crtc->base.dev;
2323 struct drm_crtc *c;
2324 struct intel_crtc *i;
2325 struct intel_framebuffer *fb;
2326
2327 if (!intel_crtc->base.primary->fb)
2328 return;
2329
2330 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2331 return;
2332
2333 kfree(intel_crtc->base.primary->fb);
2334 intel_crtc->base.primary->fb = NULL;
2335
2336 /*
2337 * Failed to alloc the obj, check to see if we should share
2338 * an fb with another CRTC instead
2339 */
2340 for_each_crtc(dev, c) {
2341 i = to_intel_crtc(c);
2342
2343 if (c == &intel_crtc->base)
2344 continue;
2345
2346 if (!i->active || !c->primary->fb)
2347 continue;
2348
2349 fb = to_intel_framebuffer(c->primary->fb);
2350 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2351 drm_framebuffer_reference(c->primary->fb);
2352 intel_crtc->base.primary->fb = c->primary->fb;
2353 break;
2354 }
2355 }
2356 }
2357
2358 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2359 struct drm_framebuffer *fb,
2360 int x, int y)
2361 {
2362 struct drm_device *dev = crtc->dev;
2363 struct drm_i915_private *dev_priv = dev->dev_private;
2364 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2365 struct intel_framebuffer *intel_fb;
2366 struct drm_i915_gem_object *obj;
2367 int plane = intel_crtc->plane;
2368 unsigned long linear_offset;
2369 u32 dspcntr;
2370 u32 reg;
2371
2372 intel_fb = to_intel_framebuffer(fb);
2373 obj = intel_fb->obj;
2374
2375 reg = DSPCNTR(plane);
2376 dspcntr = I915_READ(reg);
2377 /* Mask out pixel format bits in case we change it */
2378 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2379 switch (fb->pixel_format) {
2380 case DRM_FORMAT_C8:
2381 dspcntr |= DISPPLANE_8BPP;
2382 break;
2383 case DRM_FORMAT_XRGB1555:
2384 case DRM_FORMAT_ARGB1555:
2385 dspcntr |= DISPPLANE_BGRX555;
2386 break;
2387 case DRM_FORMAT_RGB565:
2388 dspcntr |= DISPPLANE_BGRX565;
2389 break;
2390 case DRM_FORMAT_XRGB8888:
2391 case DRM_FORMAT_ARGB8888:
2392 dspcntr |= DISPPLANE_BGRX888;
2393 break;
2394 case DRM_FORMAT_XBGR8888:
2395 case DRM_FORMAT_ABGR8888:
2396 dspcntr |= DISPPLANE_RGBX888;
2397 break;
2398 case DRM_FORMAT_XRGB2101010:
2399 case DRM_FORMAT_ARGB2101010:
2400 dspcntr |= DISPPLANE_BGRX101010;
2401 break;
2402 case DRM_FORMAT_XBGR2101010:
2403 case DRM_FORMAT_ABGR2101010:
2404 dspcntr |= DISPPLANE_RGBX101010;
2405 break;
2406 default:
2407 BUG();
2408 }
2409
2410 if (INTEL_INFO(dev)->gen >= 4) {
2411 if (obj->tiling_mode != I915_TILING_NONE)
2412 dspcntr |= DISPPLANE_TILED;
2413 else
2414 dspcntr &= ~DISPPLANE_TILED;
2415 }
2416
2417 if (IS_G4X(dev))
2418 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2419
2420 I915_WRITE(reg, dspcntr);
2421
2422 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2423
2424 if (INTEL_INFO(dev)->gen >= 4) {
2425 intel_crtc->dspaddr_offset =
2426 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2427 fb->bits_per_pixel / 8,
2428 fb->pitches[0]);
2429 linear_offset -= intel_crtc->dspaddr_offset;
2430 } else {
2431 intel_crtc->dspaddr_offset = linear_offset;
2432 }
2433
2434 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2435 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2436 fb->pitches[0]);
2437 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2438 if (INTEL_INFO(dev)->gen >= 4) {
2439 I915_WRITE(DSPSURF(plane),
2440 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2441 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2442 I915_WRITE(DSPLINOFF(plane), linear_offset);
2443 } else
2444 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2445 POSTING_READ(reg);
2446 }
2447
2448 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2449 struct drm_framebuffer *fb,
2450 int x, int y)
2451 {
2452 struct drm_device *dev = crtc->dev;
2453 struct drm_i915_private *dev_priv = dev->dev_private;
2454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2455 struct intel_framebuffer *intel_fb;
2456 struct drm_i915_gem_object *obj;
2457 int plane = intel_crtc->plane;
2458 unsigned long linear_offset;
2459 u32 dspcntr;
2460 u32 reg;
2461
2462 intel_fb = to_intel_framebuffer(fb);
2463 obj = intel_fb->obj;
2464
2465 reg = DSPCNTR(plane);
2466 dspcntr = I915_READ(reg);
2467 /* Mask out pixel format bits in case we change it */
2468 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2469 switch (fb->pixel_format) {
2470 case DRM_FORMAT_C8:
2471 dspcntr |= DISPPLANE_8BPP;
2472 break;
2473 case DRM_FORMAT_RGB565:
2474 dspcntr |= DISPPLANE_BGRX565;
2475 break;
2476 case DRM_FORMAT_XRGB8888:
2477 case DRM_FORMAT_ARGB8888:
2478 dspcntr |= DISPPLANE_BGRX888;
2479 break;
2480 case DRM_FORMAT_XBGR8888:
2481 case DRM_FORMAT_ABGR8888:
2482 dspcntr |= DISPPLANE_RGBX888;
2483 break;
2484 case DRM_FORMAT_XRGB2101010:
2485 case DRM_FORMAT_ARGB2101010:
2486 dspcntr |= DISPPLANE_BGRX101010;
2487 break;
2488 case DRM_FORMAT_XBGR2101010:
2489 case DRM_FORMAT_ABGR2101010:
2490 dspcntr |= DISPPLANE_RGBX101010;
2491 break;
2492 default:
2493 BUG();
2494 }
2495
2496 if (obj->tiling_mode != I915_TILING_NONE)
2497 dspcntr |= DISPPLANE_TILED;
2498 else
2499 dspcntr &= ~DISPPLANE_TILED;
2500
2501 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2502 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2503 else
2504 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2505
2506 I915_WRITE(reg, dspcntr);
2507
2508 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2509 intel_crtc->dspaddr_offset =
2510 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2511 fb->bits_per_pixel / 8,
2512 fb->pitches[0]);
2513 linear_offset -= intel_crtc->dspaddr_offset;
2514
2515 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2516 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2517 fb->pitches[0]);
2518 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2519 I915_WRITE(DSPSURF(plane),
2520 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2521 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2522 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2523 } else {
2524 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2525 I915_WRITE(DSPLINOFF(plane), linear_offset);
2526 }
2527 POSTING_READ(reg);
2528 }
2529
2530 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2531 static int
2532 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2533 int x, int y, enum mode_set_atomic state)
2534 {
2535 struct drm_device *dev = crtc->dev;
2536 struct drm_i915_private *dev_priv = dev->dev_private;
2537
2538 if (dev_priv->display.disable_fbc)
2539 dev_priv->display.disable_fbc(dev);
2540 intel_increase_pllclock(crtc);
2541
2542 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2543
2544 return 0;
2545 }
2546
2547 void intel_display_handle_reset(struct drm_device *dev)
2548 {
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550 struct drm_crtc *crtc;
2551
2552 /*
2553 * Flips in the rings have been nuked by the reset,
2554 * so complete all pending flips so that user space
2555 * will get its events and not get stuck.
2556 *
2557 * Also update the base address of all primary
2558 * planes to the the last fb to make sure we're
2559 * showing the correct fb after a reset.
2560 *
2561 * Need to make two loops over the crtcs so that we
2562 * don't try to grab a crtc mutex before the
2563 * pending_flip_queue really got woken up.
2564 */
2565
2566 for_each_crtc(dev, crtc) {
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 enum plane plane = intel_crtc->plane;
2569
2570 intel_prepare_page_flip(dev, plane);
2571 intel_finish_page_flip_plane(dev, plane);
2572 }
2573
2574 for_each_crtc(dev, crtc) {
2575 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2576
2577 drm_modeset_lock(&crtc->mutex, NULL);
2578 /*
2579 * FIXME: Once we have proper support for primary planes (and
2580 * disabling them without disabling the entire crtc) allow again
2581 * a NULL crtc->primary->fb.
2582 */
2583 if (intel_crtc->active && crtc->primary->fb)
2584 dev_priv->display.update_primary_plane(crtc,
2585 crtc->primary->fb,
2586 crtc->x,
2587 crtc->y);
2588 drm_modeset_unlock(&crtc->mutex);
2589 }
2590 }
2591
2592 static int
2593 intel_finish_fb(struct drm_framebuffer *old_fb)
2594 {
2595 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2596 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2597 bool was_interruptible = dev_priv->mm.interruptible;
2598 int ret;
2599
2600 /* Big Hammer, we also need to ensure that any pending
2601 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2602 * current scanout is retired before unpinning the old
2603 * framebuffer.
2604 *
2605 * This should only fail upon a hung GPU, in which case we
2606 * can safely continue.
2607 */
2608 dev_priv->mm.interruptible = false;
2609 ret = i915_gem_object_finish_gpu(obj);
2610 dev_priv->mm.interruptible = was_interruptible;
2611
2612 return ret;
2613 }
2614
2615 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2616 {
2617 struct drm_device *dev = crtc->dev;
2618 struct drm_i915_private *dev_priv = dev->dev_private;
2619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2620 unsigned long flags;
2621 bool pending;
2622
2623 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2624 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2625 return false;
2626
2627 spin_lock_irqsave(&dev->event_lock, flags);
2628 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2629 spin_unlock_irqrestore(&dev->event_lock, flags);
2630
2631 return pending;
2632 }
2633
2634 static int
2635 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2636 struct drm_framebuffer *fb)
2637 {
2638 struct drm_device *dev = crtc->dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2641 struct drm_framebuffer *old_fb;
2642 int ret;
2643
2644 if (intel_crtc_has_pending_flip(crtc)) {
2645 DRM_ERROR("pipe is still busy with an old pageflip\n");
2646 return -EBUSY;
2647 }
2648
2649 /* no fb bound */
2650 if (!fb) {
2651 DRM_ERROR("No FB bound\n");
2652 return 0;
2653 }
2654
2655 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2656 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2657 plane_name(intel_crtc->plane),
2658 INTEL_INFO(dev)->num_pipes);
2659 return -EINVAL;
2660 }
2661
2662 mutex_lock(&dev->struct_mutex);
2663 ret = intel_pin_and_fence_fb_obj(dev,
2664 to_intel_framebuffer(fb)->obj,
2665 NULL);
2666 mutex_unlock(&dev->struct_mutex);
2667 if (ret != 0) {
2668 DRM_ERROR("pin & fence failed\n");
2669 return ret;
2670 }
2671
2672 /*
2673 * Update pipe size and adjust fitter if needed: the reason for this is
2674 * that in compute_mode_changes we check the native mode (not the pfit
2675 * mode) to see if we can flip rather than do a full mode set. In the
2676 * fastboot case, we'll flip, but if we don't update the pipesrc and
2677 * pfit state, we'll end up with a big fb scanned out into the wrong
2678 * sized surface.
2679 *
2680 * To fix this properly, we need to hoist the checks up into
2681 * compute_mode_changes (or above), check the actual pfit state and
2682 * whether the platform allows pfit disable with pipe active, and only
2683 * then update the pipesrc and pfit state, even on the flip path.
2684 */
2685 if (i915.fastboot) {
2686 const struct drm_display_mode *adjusted_mode =
2687 &intel_crtc->config.adjusted_mode;
2688
2689 I915_WRITE(PIPESRC(intel_crtc->pipe),
2690 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2691 (adjusted_mode->crtc_vdisplay - 1));
2692 if (!intel_crtc->config.pch_pfit.enabled &&
2693 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2694 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2695 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2696 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2697 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2698 }
2699 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2700 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2701 }
2702
2703 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2704
2705 old_fb = crtc->primary->fb;
2706 crtc->primary->fb = fb;
2707 crtc->x = x;
2708 crtc->y = y;
2709
2710 if (old_fb) {
2711 if (intel_crtc->active && old_fb != fb)
2712 intel_wait_for_vblank(dev, intel_crtc->pipe);
2713 mutex_lock(&dev->struct_mutex);
2714 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2715 mutex_unlock(&dev->struct_mutex);
2716 }
2717
2718 mutex_lock(&dev->struct_mutex);
2719 intel_update_fbc(dev);
2720 intel_edp_psr_update(dev);
2721 mutex_unlock(&dev->struct_mutex);
2722
2723 return 0;
2724 }
2725
2726 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2727 {
2728 struct drm_device *dev = crtc->dev;
2729 struct drm_i915_private *dev_priv = dev->dev_private;
2730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2731 int pipe = intel_crtc->pipe;
2732 u32 reg, temp;
2733
2734 /* enable normal train */
2735 reg = FDI_TX_CTL(pipe);
2736 temp = I915_READ(reg);
2737 if (IS_IVYBRIDGE(dev)) {
2738 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2739 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2740 } else {
2741 temp &= ~FDI_LINK_TRAIN_NONE;
2742 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2743 }
2744 I915_WRITE(reg, temp);
2745
2746 reg = FDI_RX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 if (HAS_PCH_CPT(dev)) {
2749 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2750 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2751 } else {
2752 temp &= ~FDI_LINK_TRAIN_NONE;
2753 temp |= FDI_LINK_TRAIN_NONE;
2754 }
2755 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2756
2757 /* wait one idle pattern time */
2758 POSTING_READ(reg);
2759 udelay(1000);
2760
2761 /* IVB wants error correction enabled */
2762 if (IS_IVYBRIDGE(dev))
2763 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2764 FDI_FE_ERRC_ENABLE);
2765 }
2766
2767 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2768 {
2769 return crtc->base.enabled && crtc->active &&
2770 crtc->config.has_pch_encoder;
2771 }
2772
2773 static void ivb_modeset_global_resources(struct drm_device *dev)
2774 {
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *pipe_B_crtc =
2777 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2778 struct intel_crtc *pipe_C_crtc =
2779 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2780 uint32_t temp;
2781
2782 /*
2783 * When everything is off disable fdi C so that we could enable fdi B
2784 * with all lanes. Note that we don't care about enabled pipes without
2785 * an enabled pch encoder.
2786 */
2787 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2788 !pipe_has_enabled_pch(pipe_C_crtc)) {
2789 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2790 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2791
2792 temp = I915_READ(SOUTH_CHICKEN1);
2793 temp &= ~FDI_BC_BIFURCATION_SELECT;
2794 DRM_DEBUG_KMS("disabling fdi C rx\n");
2795 I915_WRITE(SOUTH_CHICKEN1, temp);
2796 }
2797 }
2798
2799 /* The FDI link training functions for ILK/Ibexpeak. */
2800 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2801 {
2802 struct drm_device *dev = crtc->dev;
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805 int pipe = intel_crtc->pipe;
2806 u32 reg, temp, tries;
2807
2808 /* FDI needs bits from pipe first */
2809 assert_pipe_enabled(dev_priv, pipe);
2810
2811 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2812 for train result */
2813 reg = FDI_RX_IMR(pipe);
2814 temp = I915_READ(reg);
2815 temp &= ~FDI_RX_SYMBOL_LOCK;
2816 temp &= ~FDI_RX_BIT_LOCK;
2817 I915_WRITE(reg, temp);
2818 I915_READ(reg);
2819 udelay(150);
2820
2821 /* enable CPU FDI TX and PCH FDI RX */
2822 reg = FDI_TX_CTL(pipe);
2823 temp = I915_READ(reg);
2824 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2825 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2826 temp &= ~FDI_LINK_TRAIN_NONE;
2827 temp |= FDI_LINK_TRAIN_PATTERN_1;
2828 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2829
2830 reg = FDI_RX_CTL(pipe);
2831 temp = I915_READ(reg);
2832 temp &= ~FDI_LINK_TRAIN_NONE;
2833 temp |= FDI_LINK_TRAIN_PATTERN_1;
2834 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2835
2836 POSTING_READ(reg);
2837 udelay(150);
2838
2839 /* Ironlake workaround, enable clock pointer after FDI enable*/
2840 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2841 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2842 FDI_RX_PHASE_SYNC_POINTER_EN);
2843
2844 reg = FDI_RX_IIR(pipe);
2845 for (tries = 0; tries < 5; tries++) {
2846 temp = I915_READ(reg);
2847 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2848
2849 if ((temp & FDI_RX_BIT_LOCK)) {
2850 DRM_DEBUG_KMS("FDI train 1 done.\n");
2851 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2852 break;
2853 }
2854 }
2855 if (tries == 5)
2856 DRM_ERROR("FDI train 1 fail!\n");
2857
2858 /* Train 2 */
2859 reg = FDI_TX_CTL(pipe);
2860 temp = I915_READ(reg);
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_2;
2863 I915_WRITE(reg, temp);
2864
2865 reg = FDI_RX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 temp &= ~FDI_LINK_TRAIN_NONE;
2868 temp |= FDI_LINK_TRAIN_PATTERN_2;
2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(150);
2873
2874 reg = FDI_RX_IIR(pipe);
2875 for (tries = 0; tries < 5; tries++) {
2876 temp = I915_READ(reg);
2877 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2878
2879 if (temp & FDI_RX_SYMBOL_LOCK) {
2880 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2881 DRM_DEBUG_KMS("FDI train 2 done.\n");
2882 break;
2883 }
2884 }
2885 if (tries == 5)
2886 DRM_ERROR("FDI train 2 fail!\n");
2887
2888 DRM_DEBUG_KMS("FDI train done\n");
2889
2890 }
2891
2892 static const int snb_b_fdi_train_param[] = {
2893 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2894 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2895 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2896 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2897 };
2898
2899 /* The FDI link training functions for SNB/Cougarpoint. */
2900 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2901 {
2902 struct drm_device *dev = crtc->dev;
2903 struct drm_i915_private *dev_priv = dev->dev_private;
2904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2905 int pipe = intel_crtc->pipe;
2906 u32 reg, temp, i, retry;
2907
2908 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2909 for train result */
2910 reg = FDI_RX_IMR(pipe);
2911 temp = I915_READ(reg);
2912 temp &= ~FDI_RX_SYMBOL_LOCK;
2913 temp &= ~FDI_RX_BIT_LOCK;
2914 I915_WRITE(reg, temp);
2915
2916 POSTING_READ(reg);
2917 udelay(150);
2918
2919 /* enable CPU FDI TX and PCH FDI RX */
2920 reg = FDI_TX_CTL(pipe);
2921 temp = I915_READ(reg);
2922 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2923 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2924 temp &= ~FDI_LINK_TRAIN_NONE;
2925 temp |= FDI_LINK_TRAIN_PATTERN_1;
2926 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2927 /* SNB-B */
2928 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2929 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2930
2931 I915_WRITE(FDI_RX_MISC(pipe),
2932 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2933
2934 reg = FDI_RX_CTL(pipe);
2935 temp = I915_READ(reg);
2936 if (HAS_PCH_CPT(dev)) {
2937 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2938 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2939 } else {
2940 temp &= ~FDI_LINK_TRAIN_NONE;
2941 temp |= FDI_LINK_TRAIN_PATTERN_1;
2942 }
2943 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2944
2945 POSTING_READ(reg);
2946 udelay(150);
2947
2948 for (i = 0; i < 4; i++) {
2949 reg = FDI_TX_CTL(pipe);
2950 temp = I915_READ(reg);
2951 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2952 temp |= snb_b_fdi_train_param[i];
2953 I915_WRITE(reg, temp);
2954
2955 POSTING_READ(reg);
2956 udelay(500);
2957
2958 for (retry = 0; retry < 5; retry++) {
2959 reg = FDI_RX_IIR(pipe);
2960 temp = I915_READ(reg);
2961 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2962 if (temp & FDI_RX_BIT_LOCK) {
2963 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2964 DRM_DEBUG_KMS("FDI train 1 done.\n");
2965 break;
2966 }
2967 udelay(50);
2968 }
2969 if (retry < 5)
2970 break;
2971 }
2972 if (i == 4)
2973 DRM_ERROR("FDI train 1 fail!\n");
2974
2975 /* Train 2 */
2976 reg = FDI_TX_CTL(pipe);
2977 temp = I915_READ(reg);
2978 temp &= ~FDI_LINK_TRAIN_NONE;
2979 temp |= FDI_LINK_TRAIN_PATTERN_2;
2980 if (IS_GEN6(dev)) {
2981 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2982 /* SNB-B */
2983 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2984 }
2985 I915_WRITE(reg, temp);
2986
2987 reg = FDI_RX_CTL(pipe);
2988 temp = I915_READ(reg);
2989 if (HAS_PCH_CPT(dev)) {
2990 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2991 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2992 } else {
2993 temp &= ~FDI_LINK_TRAIN_NONE;
2994 temp |= FDI_LINK_TRAIN_PATTERN_2;
2995 }
2996 I915_WRITE(reg, temp);
2997
2998 POSTING_READ(reg);
2999 udelay(150);
3000
3001 for (i = 0; i < 4; i++) {
3002 reg = FDI_TX_CTL(pipe);
3003 temp = I915_READ(reg);
3004 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3005 temp |= snb_b_fdi_train_param[i];
3006 I915_WRITE(reg, temp);
3007
3008 POSTING_READ(reg);
3009 udelay(500);
3010
3011 for (retry = 0; retry < 5; retry++) {
3012 reg = FDI_RX_IIR(pipe);
3013 temp = I915_READ(reg);
3014 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3015 if (temp & FDI_RX_SYMBOL_LOCK) {
3016 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3017 DRM_DEBUG_KMS("FDI train 2 done.\n");
3018 break;
3019 }
3020 udelay(50);
3021 }
3022 if (retry < 5)
3023 break;
3024 }
3025 if (i == 4)
3026 DRM_ERROR("FDI train 2 fail!\n");
3027
3028 DRM_DEBUG_KMS("FDI train done.\n");
3029 }
3030
3031 /* Manual link training for Ivy Bridge A0 parts */
3032 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3033 {
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3037 int pipe = intel_crtc->pipe;
3038 u32 reg, temp, i, j;
3039
3040 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3041 for train result */
3042 reg = FDI_RX_IMR(pipe);
3043 temp = I915_READ(reg);
3044 temp &= ~FDI_RX_SYMBOL_LOCK;
3045 temp &= ~FDI_RX_BIT_LOCK;
3046 I915_WRITE(reg, temp);
3047
3048 POSTING_READ(reg);
3049 udelay(150);
3050
3051 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3052 I915_READ(FDI_RX_IIR(pipe)));
3053
3054 /* Try each vswing and preemphasis setting twice before moving on */
3055 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3056 /* disable first in case we need to retry */
3057 reg = FDI_TX_CTL(pipe);
3058 temp = I915_READ(reg);
3059 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3060 temp &= ~FDI_TX_ENABLE;
3061 I915_WRITE(reg, temp);
3062
3063 reg = FDI_RX_CTL(pipe);
3064 temp = I915_READ(reg);
3065 temp &= ~FDI_LINK_TRAIN_AUTO;
3066 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3067 temp &= ~FDI_RX_ENABLE;
3068 I915_WRITE(reg, temp);
3069
3070 /* enable CPU FDI TX and PCH FDI RX */
3071 reg = FDI_TX_CTL(pipe);
3072 temp = I915_READ(reg);
3073 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3074 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3075 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3076 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3077 temp |= snb_b_fdi_train_param[j/2];
3078 temp |= FDI_COMPOSITE_SYNC;
3079 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3080
3081 I915_WRITE(FDI_RX_MISC(pipe),
3082 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3083
3084 reg = FDI_RX_CTL(pipe);
3085 temp = I915_READ(reg);
3086 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3087 temp |= FDI_COMPOSITE_SYNC;
3088 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3089
3090 POSTING_READ(reg);
3091 udelay(1); /* should be 0.5us */
3092
3093 for (i = 0; i < 4; i++) {
3094 reg = FDI_RX_IIR(pipe);
3095 temp = I915_READ(reg);
3096 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3097
3098 if (temp & FDI_RX_BIT_LOCK ||
3099 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3100 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3101 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3102 i);
3103 break;
3104 }
3105 udelay(1); /* should be 0.5us */
3106 }
3107 if (i == 4) {
3108 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3109 continue;
3110 }
3111
3112 /* Train 2 */
3113 reg = FDI_TX_CTL(pipe);
3114 temp = I915_READ(reg);
3115 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3116 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3117 I915_WRITE(reg, temp);
3118
3119 reg = FDI_RX_CTL(pipe);
3120 temp = I915_READ(reg);
3121 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3122 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3123 I915_WRITE(reg, temp);
3124
3125 POSTING_READ(reg);
3126 udelay(2); /* should be 1.5us */
3127
3128 for (i = 0; i < 4; i++) {
3129 reg = FDI_RX_IIR(pipe);
3130 temp = I915_READ(reg);
3131 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3132
3133 if (temp & FDI_RX_SYMBOL_LOCK ||
3134 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3135 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3136 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3137 i);
3138 goto train_done;
3139 }
3140 udelay(2); /* should be 1.5us */
3141 }
3142 if (i == 4)
3143 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3144 }
3145
3146 train_done:
3147 DRM_DEBUG_KMS("FDI train done.\n");
3148 }
3149
3150 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3151 {
3152 struct drm_device *dev = intel_crtc->base.dev;
3153 struct drm_i915_private *dev_priv = dev->dev_private;
3154 int pipe = intel_crtc->pipe;
3155 u32 reg, temp;
3156
3157
3158 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3159 reg = FDI_RX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3162 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3163 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3164 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3165
3166 POSTING_READ(reg);
3167 udelay(200);
3168
3169 /* Switch from Rawclk to PCDclk */
3170 temp = I915_READ(reg);
3171 I915_WRITE(reg, temp | FDI_PCDCLK);
3172
3173 POSTING_READ(reg);
3174 udelay(200);
3175
3176 /* Enable CPU FDI TX PLL, always on for Ironlake */
3177 reg = FDI_TX_CTL(pipe);
3178 temp = I915_READ(reg);
3179 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3180 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3181
3182 POSTING_READ(reg);
3183 udelay(100);
3184 }
3185 }
3186
3187 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3188 {
3189 struct drm_device *dev = intel_crtc->base.dev;
3190 struct drm_i915_private *dev_priv = dev->dev_private;
3191 int pipe = intel_crtc->pipe;
3192 u32 reg, temp;
3193
3194 /* Switch from PCDclk to Rawclk */
3195 reg = FDI_RX_CTL(pipe);
3196 temp = I915_READ(reg);
3197 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3198
3199 /* Disable CPU FDI TX PLL */
3200 reg = FDI_TX_CTL(pipe);
3201 temp = I915_READ(reg);
3202 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3203
3204 POSTING_READ(reg);
3205 udelay(100);
3206
3207 reg = FDI_RX_CTL(pipe);
3208 temp = I915_READ(reg);
3209 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3210
3211 /* Wait for the clocks to turn off. */
3212 POSTING_READ(reg);
3213 udelay(100);
3214 }
3215
3216 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3217 {
3218 struct drm_device *dev = crtc->dev;
3219 struct drm_i915_private *dev_priv = dev->dev_private;
3220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3221 int pipe = intel_crtc->pipe;
3222 u32 reg, temp;
3223
3224 /* disable CPU FDI tx and PCH FDI rx */
3225 reg = FDI_TX_CTL(pipe);
3226 temp = I915_READ(reg);
3227 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3228 POSTING_READ(reg);
3229
3230 reg = FDI_RX_CTL(pipe);
3231 temp = I915_READ(reg);
3232 temp &= ~(0x7 << 16);
3233 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3234 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3235
3236 POSTING_READ(reg);
3237 udelay(100);
3238
3239 /* Ironlake workaround, disable clock pointer after downing FDI */
3240 if (HAS_PCH_IBX(dev))
3241 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3242
3243 /* still set train pattern 1 */
3244 reg = FDI_TX_CTL(pipe);
3245 temp = I915_READ(reg);
3246 temp &= ~FDI_LINK_TRAIN_NONE;
3247 temp |= FDI_LINK_TRAIN_PATTERN_1;
3248 I915_WRITE(reg, temp);
3249
3250 reg = FDI_RX_CTL(pipe);
3251 temp = I915_READ(reg);
3252 if (HAS_PCH_CPT(dev)) {
3253 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3254 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3255 } else {
3256 temp &= ~FDI_LINK_TRAIN_NONE;
3257 temp |= FDI_LINK_TRAIN_PATTERN_1;
3258 }
3259 /* BPC in FDI rx is consistent with that in PIPECONF */
3260 temp &= ~(0x07 << 16);
3261 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3262 I915_WRITE(reg, temp);
3263
3264 POSTING_READ(reg);
3265 udelay(100);
3266 }
3267
3268 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3269 {
3270 struct intel_crtc *crtc;
3271
3272 /* Note that we don't need to be called with mode_config.lock here
3273 * as our list of CRTC objects is static for the lifetime of the
3274 * device and so cannot disappear as we iterate. Similarly, we can
3275 * happily treat the predicates as racy, atomic checks as userspace
3276 * cannot claim and pin a new fb without at least acquring the
3277 * struct_mutex and so serialising with us.
3278 */
3279 for_each_intel_crtc(dev, crtc) {
3280 if (atomic_read(&crtc->unpin_work_count) == 0)
3281 continue;
3282
3283 if (crtc->unpin_work)
3284 intel_wait_for_vblank(dev, crtc->pipe);
3285
3286 return true;
3287 }
3288
3289 return false;
3290 }
3291
3292 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3293 {
3294 struct drm_device *dev = crtc->dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296
3297 if (crtc->primary->fb == NULL)
3298 return;
3299
3300 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3301
3302 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3303 !intel_crtc_has_pending_flip(crtc),
3304 60*HZ) == 0);
3305
3306 mutex_lock(&dev->struct_mutex);
3307 intel_finish_fb(crtc->primary->fb);
3308 mutex_unlock(&dev->struct_mutex);
3309 }
3310
3311 /* Program iCLKIP clock to the desired frequency */
3312 static void lpt_program_iclkip(struct drm_crtc *crtc)
3313 {
3314 struct drm_device *dev = crtc->dev;
3315 struct drm_i915_private *dev_priv = dev->dev_private;
3316 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3317 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3318 u32 temp;
3319
3320 mutex_lock(&dev_priv->dpio_lock);
3321
3322 /* It is necessary to ungate the pixclk gate prior to programming
3323 * the divisors, and gate it back when it is done.
3324 */
3325 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3326
3327 /* Disable SSCCTL */
3328 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3329 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3330 SBI_SSCCTL_DISABLE,
3331 SBI_ICLK);
3332
3333 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3334 if (clock == 20000) {
3335 auxdiv = 1;
3336 divsel = 0x41;
3337 phaseinc = 0x20;
3338 } else {
3339 /* The iCLK virtual clock root frequency is in MHz,
3340 * but the adjusted_mode->crtc_clock in in KHz. To get the
3341 * divisors, it is necessary to divide one by another, so we
3342 * convert the virtual clock precision to KHz here for higher
3343 * precision.
3344 */
3345 u32 iclk_virtual_root_freq = 172800 * 1000;
3346 u32 iclk_pi_range = 64;
3347 u32 desired_divisor, msb_divisor_value, pi_value;
3348
3349 desired_divisor = (iclk_virtual_root_freq / clock);
3350 msb_divisor_value = desired_divisor / iclk_pi_range;
3351 pi_value = desired_divisor % iclk_pi_range;
3352
3353 auxdiv = 0;
3354 divsel = msb_divisor_value - 2;
3355 phaseinc = pi_value;
3356 }
3357
3358 /* This should not happen with any sane values */
3359 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3360 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3361 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3362 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3363
3364 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3365 clock,
3366 auxdiv,
3367 divsel,
3368 phasedir,
3369 phaseinc);
3370
3371 /* Program SSCDIVINTPHASE6 */
3372 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3373 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3374 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3375 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3376 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3377 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3378 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3379 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3380
3381 /* Program SSCAUXDIV */
3382 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3383 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3384 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3385 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3386
3387 /* Enable modulator and associated divider */
3388 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3389 temp &= ~SBI_SSCCTL_DISABLE;
3390 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3391
3392 /* Wait for initialization time */
3393 udelay(24);
3394
3395 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3396
3397 mutex_unlock(&dev_priv->dpio_lock);
3398 }
3399
3400 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3401 enum pipe pch_transcoder)
3402 {
3403 struct drm_device *dev = crtc->base.dev;
3404 struct drm_i915_private *dev_priv = dev->dev_private;
3405 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3406
3407 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3408 I915_READ(HTOTAL(cpu_transcoder)));
3409 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3410 I915_READ(HBLANK(cpu_transcoder)));
3411 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3412 I915_READ(HSYNC(cpu_transcoder)));
3413
3414 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3415 I915_READ(VTOTAL(cpu_transcoder)));
3416 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3417 I915_READ(VBLANK(cpu_transcoder)));
3418 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3419 I915_READ(VSYNC(cpu_transcoder)));
3420 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3421 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3422 }
3423
3424 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3425 {
3426 struct drm_i915_private *dev_priv = dev->dev_private;
3427 uint32_t temp;
3428
3429 temp = I915_READ(SOUTH_CHICKEN1);
3430 if (temp & FDI_BC_BIFURCATION_SELECT)
3431 return;
3432
3433 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3434 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3435
3436 temp |= FDI_BC_BIFURCATION_SELECT;
3437 DRM_DEBUG_KMS("enabling fdi C rx\n");
3438 I915_WRITE(SOUTH_CHICKEN1, temp);
3439 POSTING_READ(SOUTH_CHICKEN1);
3440 }
3441
3442 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3443 {
3444 struct drm_device *dev = intel_crtc->base.dev;
3445 struct drm_i915_private *dev_priv = dev->dev_private;
3446
3447 switch (intel_crtc->pipe) {
3448 case PIPE_A:
3449 break;
3450 case PIPE_B:
3451 if (intel_crtc->config.fdi_lanes > 2)
3452 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3453 else
3454 cpt_enable_fdi_bc_bifurcation(dev);
3455
3456 break;
3457 case PIPE_C:
3458 cpt_enable_fdi_bc_bifurcation(dev);
3459
3460 break;
3461 default:
3462 BUG();
3463 }
3464 }
3465
3466 /*
3467 * Enable PCH resources required for PCH ports:
3468 * - PCH PLLs
3469 * - FDI training & RX/TX
3470 * - update transcoder timings
3471 * - DP transcoding bits
3472 * - transcoder
3473 */
3474 static void ironlake_pch_enable(struct drm_crtc *crtc)
3475 {
3476 struct drm_device *dev = crtc->dev;
3477 struct drm_i915_private *dev_priv = dev->dev_private;
3478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3479 int pipe = intel_crtc->pipe;
3480 u32 reg, temp;
3481
3482 assert_pch_transcoder_disabled(dev_priv, pipe);
3483
3484 if (IS_IVYBRIDGE(dev))
3485 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3486
3487 /* Write the TU size bits before fdi link training, so that error
3488 * detection works. */
3489 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3490 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3491
3492 /* For PCH output, training FDI link */
3493 dev_priv->display.fdi_link_train(crtc);
3494
3495 /* We need to program the right clock selection before writing the pixel
3496 * mutliplier into the DPLL. */
3497 if (HAS_PCH_CPT(dev)) {
3498 u32 sel;
3499
3500 temp = I915_READ(PCH_DPLL_SEL);
3501 temp |= TRANS_DPLL_ENABLE(pipe);
3502 sel = TRANS_DPLLB_SEL(pipe);
3503 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3504 temp |= sel;
3505 else
3506 temp &= ~sel;
3507 I915_WRITE(PCH_DPLL_SEL, temp);
3508 }
3509
3510 /* XXX: pch pll's can be enabled any time before we enable the PCH
3511 * transcoder, and we actually should do this to not upset any PCH
3512 * transcoder that already use the clock when we share it.
3513 *
3514 * Note that enable_shared_dpll tries to do the right thing, but
3515 * get_shared_dpll unconditionally resets the pll - we need that to have
3516 * the right LVDS enable sequence. */
3517 intel_enable_shared_dpll(intel_crtc);
3518
3519 /* set transcoder timing, panel must allow it */
3520 assert_panel_unlocked(dev_priv, pipe);
3521 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3522
3523 intel_fdi_normal_train(crtc);
3524
3525 /* For PCH DP, enable TRANS_DP_CTL */
3526 if (HAS_PCH_CPT(dev) &&
3527 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3528 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3529 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3530 reg = TRANS_DP_CTL(pipe);
3531 temp = I915_READ(reg);
3532 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3533 TRANS_DP_SYNC_MASK |
3534 TRANS_DP_BPC_MASK);
3535 temp |= (TRANS_DP_OUTPUT_ENABLE |
3536 TRANS_DP_ENH_FRAMING);
3537 temp |= bpc << 9; /* same format but at 11:9 */
3538
3539 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3540 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3541 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3542 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3543
3544 switch (intel_trans_dp_port_sel(crtc)) {
3545 case PCH_DP_B:
3546 temp |= TRANS_DP_PORT_SEL_B;
3547 break;
3548 case PCH_DP_C:
3549 temp |= TRANS_DP_PORT_SEL_C;
3550 break;
3551 case PCH_DP_D:
3552 temp |= TRANS_DP_PORT_SEL_D;
3553 break;
3554 default:
3555 BUG();
3556 }
3557
3558 I915_WRITE(reg, temp);
3559 }
3560
3561 ironlake_enable_pch_transcoder(dev_priv, pipe);
3562 }
3563
3564 static void lpt_pch_enable(struct drm_crtc *crtc)
3565 {
3566 struct drm_device *dev = crtc->dev;
3567 struct drm_i915_private *dev_priv = dev->dev_private;
3568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3569 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3570
3571 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3572
3573 lpt_program_iclkip(crtc);
3574
3575 /* Set transcoder timing. */
3576 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3577
3578 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3579 }
3580
3581 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3582 {
3583 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3584
3585 if (pll == NULL)
3586 return;
3587
3588 if (pll->refcount == 0) {
3589 WARN(1, "bad %s refcount\n", pll->name);
3590 return;
3591 }
3592
3593 if (--pll->refcount == 0) {
3594 WARN_ON(pll->on);
3595 WARN_ON(pll->active);
3596 }
3597
3598 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3599 }
3600
3601 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3602 {
3603 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3604 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3605 enum intel_dpll_id i;
3606
3607 if (pll) {
3608 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3609 crtc->base.base.id, pll->name);
3610 intel_put_shared_dpll(crtc);
3611 }
3612
3613 if (HAS_PCH_IBX(dev_priv->dev)) {
3614 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3615 i = (enum intel_dpll_id) crtc->pipe;
3616 pll = &dev_priv->shared_dplls[i];
3617
3618 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3619 crtc->base.base.id, pll->name);
3620
3621 WARN_ON(pll->refcount);
3622
3623 goto found;
3624 }
3625
3626 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3627 pll = &dev_priv->shared_dplls[i];
3628
3629 /* Only want to check enabled timings first */
3630 if (pll->refcount == 0)
3631 continue;
3632
3633 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3634 sizeof(pll->hw_state)) == 0) {
3635 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3636 crtc->base.base.id,
3637 pll->name, pll->refcount, pll->active);
3638
3639 goto found;
3640 }
3641 }
3642
3643 /* Ok no matching timings, maybe there's a free one? */
3644 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3645 pll = &dev_priv->shared_dplls[i];
3646 if (pll->refcount == 0) {
3647 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3648 crtc->base.base.id, pll->name);
3649 goto found;
3650 }
3651 }
3652
3653 return NULL;
3654
3655 found:
3656 if (pll->refcount == 0)
3657 pll->hw_state = crtc->config.dpll_hw_state;
3658
3659 crtc->config.shared_dpll = i;
3660 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3661 pipe_name(crtc->pipe));
3662
3663 pll->refcount++;
3664
3665 return pll;
3666 }
3667
3668 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3669 {
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 int dslreg = PIPEDSL(pipe);
3672 u32 temp;
3673
3674 temp = I915_READ(dslreg);
3675 udelay(500);
3676 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3677 if (wait_for(I915_READ(dslreg) != temp, 5))
3678 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3679 }
3680 }
3681
3682 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3683 {
3684 struct drm_device *dev = crtc->base.dev;
3685 struct drm_i915_private *dev_priv = dev->dev_private;
3686 int pipe = crtc->pipe;
3687
3688 if (crtc->config.pch_pfit.enabled) {
3689 /* Force use of hard-coded filter coefficients
3690 * as some pre-programmed values are broken,
3691 * e.g. x201.
3692 */
3693 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3694 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3695 PF_PIPE_SEL_IVB(pipe));
3696 else
3697 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3698 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3699 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3700 }
3701 }
3702
3703 static void intel_enable_planes(struct drm_crtc *crtc)
3704 {
3705 struct drm_device *dev = crtc->dev;
3706 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3707 struct drm_plane *plane;
3708 struct intel_plane *intel_plane;
3709
3710 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3711 intel_plane = to_intel_plane(plane);
3712 if (intel_plane->pipe == pipe)
3713 intel_plane_restore(&intel_plane->base);
3714 }
3715 }
3716
3717 static void intel_disable_planes(struct drm_crtc *crtc)
3718 {
3719 struct drm_device *dev = crtc->dev;
3720 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3721 struct drm_plane *plane;
3722 struct intel_plane *intel_plane;
3723
3724 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3725 intel_plane = to_intel_plane(plane);
3726 if (intel_plane->pipe == pipe)
3727 intel_plane_disable(&intel_plane->base);
3728 }
3729 }
3730
3731 void hsw_enable_ips(struct intel_crtc *crtc)
3732 {
3733 struct drm_device *dev = crtc->base.dev;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
3735
3736 if (!crtc->config.ips_enabled)
3737 return;
3738
3739 /* We can only enable IPS after we enable a plane and wait for a vblank */
3740 intel_wait_for_vblank(dev, crtc->pipe);
3741
3742 assert_plane_enabled(dev_priv, crtc->plane);
3743 if (IS_BROADWELL(dev)) {
3744 mutex_lock(&dev_priv->rps.hw_lock);
3745 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3746 mutex_unlock(&dev_priv->rps.hw_lock);
3747 /* Quoting Art Runyan: "its not safe to expect any particular
3748 * value in IPS_CTL bit 31 after enabling IPS through the
3749 * mailbox." Moreover, the mailbox may return a bogus state,
3750 * so we need to just enable it and continue on.
3751 */
3752 } else {
3753 I915_WRITE(IPS_CTL, IPS_ENABLE);
3754 /* The bit only becomes 1 in the next vblank, so this wait here
3755 * is essentially intel_wait_for_vblank. If we don't have this
3756 * and don't wait for vblanks until the end of crtc_enable, then
3757 * the HW state readout code will complain that the expected
3758 * IPS_CTL value is not the one we read. */
3759 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3760 DRM_ERROR("Timed out waiting for IPS enable\n");
3761 }
3762 }
3763
3764 void hsw_disable_ips(struct intel_crtc *crtc)
3765 {
3766 struct drm_device *dev = crtc->base.dev;
3767 struct drm_i915_private *dev_priv = dev->dev_private;
3768
3769 if (!crtc->config.ips_enabled)
3770 return;
3771
3772 assert_plane_enabled(dev_priv, crtc->plane);
3773 if (IS_BROADWELL(dev)) {
3774 mutex_lock(&dev_priv->rps.hw_lock);
3775 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3776 mutex_unlock(&dev_priv->rps.hw_lock);
3777 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3778 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3779 DRM_ERROR("Timed out waiting for IPS disable\n");
3780 } else {
3781 I915_WRITE(IPS_CTL, 0);
3782 POSTING_READ(IPS_CTL);
3783 }
3784
3785 /* We need to wait for a vblank before we can disable the plane. */
3786 intel_wait_for_vblank(dev, crtc->pipe);
3787 }
3788
3789 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3790 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3791 {
3792 struct drm_device *dev = crtc->dev;
3793 struct drm_i915_private *dev_priv = dev->dev_private;
3794 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3795 enum pipe pipe = intel_crtc->pipe;
3796 int palreg = PALETTE(pipe);
3797 int i;
3798 bool reenable_ips = false;
3799
3800 /* The clocks have to be on to load the palette. */
3801 if (!crtc->enabled || !intel_crtc->active)
3802 return;
3803
3804 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3805 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3806 assert_dsi_pll_enabled(dev_priv);
3807 else
3808 assert_pll_enabled(dev_priv, pipe);
3809 }
3810
3811 /* use legacy palette for Ironlake */
3812 if (HAS_PCH_SPLIT(dev))
3813 palreg = LGC_PALETTE(pipe);
3814
3815 /* Workaround : Do not read or write the pipe palette/gamma data while
3816 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3817 */
3818 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3819 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3820 GAMMA_MODE_MODE_SPLIT)) {
3821 hsw_disable_ips(intel_crtc);
3822 reenable_ips = true;
3823 }
3824
3825 for (i = 0; i < 256; i++) {
3826 I915_WRITE(palreg + 4 * i,
3827 (intel_crtc->lut_r[i] << 16) |
3828 (intel_crtc->lut_g[i] << 8) |
3829 intel_crtc->lut_b[i]);
3830 }
3831
3832 if (reenable_ips)
3833 hsw_enable_ips(intel_crtc);
3834 }
3835
3836 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3837 {
3838 if (!enable && intel_crtc->overlay) {
3839 struct drm_device *dev = intel_crtc->base.dev;
3840 struct drm_i915_private *dev_priv = dev->dev_private;
3841
3842 mutex_lock(&dev->struct_mutex);
3843 dev_priv->mm.interruptible = false;
3844 (void) intel_overlay_switch_off(intel_crtc->overlay);
3845 dev_priv->mm.interruptible = true;
3846 mutex_unlock(&dev->struct_mutex);
3847 }
3848
3849 /* Let userspace switch the overlay on again. In most cases userspace
3850 * has to recompute where to put it anyway.
3851 */
3852 }
3853
3854 /**
3855 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3856 * cursor plane briefly if not already running after enabling the display
3857 * plane.
3858 * This workaround avoids occasional blank screens when self refresh is
3859 * enabled.
3860 */
3861 static void
3862 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3863 {
3864 u32 cntl = I915_READ(CURCNTR(pipe));
3865
3866 if ((cntl & CURSOR_MODE) == 0) {
3867 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3868
3869 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3870 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3871 intel_wait_for_vblank(dev_priv->dev, pipe);
3872 I915_WRITE(CURCNTR(pipe), cntl);
3873 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3874 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3875 }
3876 }
3877
3878 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3879 {
3880 struct drm_device *dev = crtc->dev;
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3883 int pipe = intel_crtc->pipe;
3884 int plane = intel_crtc->plane;
3885
3886 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3887 intel_enable_planes(crtc);
3888 /* The fixup needs to happen before cursor is enabled */
3889 if (IS_G4X(dev))
3890 g4x_fixup_plane(dev_priv, pipe);
3891 intel_crtc_update_cursor(crtc, true);
3892 intel_crtc_dpms_overlay(intel_crtc, true);
3893
3894 hsw_enable_ips(intel_crtc);
3895
3896 mutex_lock(&dev->struct_mutex);
3897 intel_update_fbc(dev);
3898 intel_edp_psr_update(dev);
3899 mutex_unlock(&dev->struct_mutex);
3900 }
3901
3902 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3903 {
3904 struct drm_device *dev = crtc->dev;
3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3907 int pipe = intel_crtc->pipe;
3908 int plane = intel_crtc->plane;
3909
3910 intel_crtc_wait_for_pending_flips(crtc);
3911 drm_crtc_vblank_off(crtc);
3912
3913 if (dev_priv->fbc.plane == plane)
3914 intel_disable_fbc(dev);
3915
3916 hsw_disable_ips(intel_crtc);
3917
3918 intel_crtc_dpms_overlay(intel_crtc, false);
3919 intel_crtc_update_cursor(crtc, false);
3920 intel_disable_planes(crtc);
3921 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3922 }
3923
3924 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3925 {
3926 struct drm_device *dev = crtc->dev;
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929 struct intel_encoder *encoder;
3930 int pipe = intel_crtc->pipe;
3931 enum plane plane = intel_crtc->plane;
3932
3933 WARN_ON(!crtc->enabled);
3934
3935 if (intel_crtc->active)
3936 return;
3937
3938 if (intel_crtc->config.has_pch_encoder)
3939 intel_prepare_shared_dpll(intel_crtc);
3940
3941 if (intel_crtc->config.has_dp_encoder)
3942 intel_dp_set_m_n(intel_crtc);
3943
3944 intel_set_pipe_timings(intel_crtc);
3945
3946 if (intel_crtc->config.has_pch_encoder) {
3947 intel_cpu_transcoder_set_m_n(intel_crtc,
3948 &intel_crtc->config.fdi_m_n);
3949 }
3950
3951 ironlake_set_pipeconf(crtc);
3952
3953 /* Set up the display plane register */
3954 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
3955 POSTING_READ(DSPCNTR(plane));
3956
3957 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
3958 crtc->x, crtc->y);
3959
3960 intel_crtc->active = true;
3961
3962 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3963 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3964
3965 for_each_encoder_on_crtc(dev, crtc, encoder)
3966 if (encoder->pre_enable)
3967 encoder->pre_enable(encoder);
3968
3969 if (intel_crtc->config.has_pch_encoder) {
3970 /* Note: FDI PLL enabling _must_ be done before we enable the
3971 * cpu pipes, hence this is separate from all the other fdi/pch
3972 * enabling. */
3973 ironlake_fdi_pll_enable(intel_crtc);
3974 } else {
3975 assert_fdi_tx_disabled(dev_priv, pipe);
3976 assert_fdi_rx_disabled(dev_priv, pipe);
3977 }
3978
3979 ironlake_pfit_enable(intel_crtc);
3980
3981 /*
3982 * On ILK+ LUT must be loaded before the pipe is running but with
3983 * clocks enabled
3984 */
3985 intel_crtc_load_lut(crtc);
3986
3987 intel_update_watermarks(crtc);
3988 intel_enable_pipe(intel_crtc);
3989
3990 if (intel_crtc->config.has_pch_encoder)
3991 ironlake_pch_enable(crtc);
3992
3993 for_each_encoder_on_crtc(dev, crtc, encoder)
3994 encoder->enable(encoder);
3995
3996 if (HAS_PCH_CPT(dev))
3997 cpt_verify_modeset(dev, intel_crtc->pipe);
3998
3999 intel_crtc_enable_planes(crtc);
4000
4001 drm_crtc_vblank_on(crtc);
4002 }
4003
4004 /* IPS only exists on ULT machines and is tied to pipe A. */
4005 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4006 {
4007 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4008 }
4009
4010 /*
4011 * This implements the workaround described in the "notes" section of the mode
4012 * set sequence documentation. When going from no pipes or single pipe to
4013 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4014 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4015 */
4016 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4017 {
4018 struct drm_device *dev = crtc->base.dev;
4019 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4020
4021 /* We want to get the other_active_crtc only if there's only 1 other
4022 * active crtc. */
4023 for_each_intel_crtc(dev, crtc_it) {
4024 if (!crtc_it->active || crtc_it == crtc)
4025 continue;
4026
4027 if (other_active_crtc)
4028 return;
4029
4030 other_active_crtc = crtc_it;
4031 }
4032 if (!other_active_crtc)
4033 return;
4034
4035 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4036 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4037 }
4038
4039 static void haswell_crtc_enable(struct drm_crtc *crtc)
4040 {
4041 struct drm_device *dev = crtc->dev;
4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4044 struct intel_encoder *encoder;
4045 int pipe = intel_crtc->pipe;
4046 enum plane plane = intel_crtc->plane;
4047
4048 WARN_ON(!crtc->enabled);
4049
4050 if (intel_crtc->active)
4051 return;
4052
4053 if (intel_crtc->config.has_dp_encoder)
4054 intel_dp_set_m_n(intel_crtc);
4055
4056 intel_set_pipe_timings(intel_crtc);
4057
4058 if (intel_crtc->config.has_pch_encoder) {
4059 intel_cpu_transcoder_set_m_n(intel_crtc,
4060 &intel_crtc->config.fdi_m_n);
4061 }
4062
4063 haswell_set_pipeconf(crtc);
4064
4065 intel_set_pipe_csc(crtc);
4066
4067 /* Set up the display plane register */
4068 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4069 POSTING_READ(DSPCNTR(plane));
4070
4071 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4072 crtc->x, crtc->y);
4073
4074 intel_crtc->active = true;
4075
4076 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4077 if (intel_crtc->config.has_pch_encoder)
4078 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4079
4080 if (intel_crtc->config.has_pch_encoder)
4081 dev_priv->display.fdi_link_train(crtc);
4082
4083 for_each_encoder_on_crtc(dev, crtc, encoder)
4084 if (encoder->pre_enable)
4085 encoder->pre_enable(encoder);
4086
4087 intel_ddi_enable_pipe_clock(intel_crtc);
4088
4089 ironlake_pfit_enable(intel_crtc);
4090
4091 /*
4092 * On ILK+ LUT must be loaded before the pipe is running but with
4093 * clocks enabled
4094 */
4095 intel_crtc_load_lut(crtc);
4096
4097 intel_ddi_set_pipe_settings(crtc);
4098 intel_ddi_enable_transcoder_func(crtc);
4099
4100 intel_update_watermarks(crtc);
4101 intel_enable_pipe(intel_crtc);
4102
4103 if (intel_crtc->config.has_pch_encoder)
4104 lpt_pch_enable(crtc);
4105
4106 for_each_encoder_on_crtc(dev, crtc, encoder) {
4107 encoder->enable(encoder);
4108 intel_opregion_notify_encoder(encoder, true);
4109 }
4110
4111 /* If we change the relative order between pipe/planes enabling, we need
4112 * to change the workaround. */
4113 haswell_mode_set_planes_workaround(intel_crtc);
4114 intel_crtc_enable_planes(crtc);
4115
4116 drm_crtc_vblank_on(crtc);
4117 }
4118
4119 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4120 {
4121 struct drm_device *dev = crtc->base.dev;
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 int pipe = crtc->pipe;
4124
4125 /* To avoid upsetting the power well on haswell only disable the pfit if
4126 * it's in use. The hw state code will make sure we get this right. */
4127 if (crtc->config.pch_pfit.enabled) {
4128 I915_WRITE(PF_CTL(pipe), 0);
4129 I915_WRITE(PF_WIN_POS(pipe), 0);
4130 I915_WRITE(PF_WIN_SZ(pipe), 0);
4131 }
4132 }
4133
4134 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4135 {
4136 struct drm_device *dev = crtc->dev;
4137 struct drm_i915_private *dev_priv = dev->dev_private;
4138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4139 struct intel_encoder *encoder;
4140 int pipe = intel_crtc->pipe;
4141 u32 reg, temp;
4142
4143 if (!intel_crtc->active)
4144 return;
4145
4146 intel_crtc_disable_planes(crtc);
4147
4148 for_each_encoder_on_crtc(dev, crtc, encoder)
4149 encoder->disable(encoder);
4150
4151 if (intel_crtc->config.has_pch_encoder)
4152 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4153
4154 intel_disable_pipe(dev_priv, pipe);
4155
4156 ironlake_pfit_disable(intel_crtc);
4157
4158 for_each_encoder_on_crtc(dev, crtc, encoder)
4159 if (encoder->post_disable)
4160 encoder->post_disable(encoder);
4161
4162 if (intel_crtc->config.has_pch_encoder) {
4163 ironlake_fdi_disable(crtc);
4164
4165 ironlake_disable_pch_transcoder(dev_priv, pipe);
4166 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4167
4168 if (HAS_PCH_CPT(dev)) {
4169 /* disable TRANS_DP_CTL */
4170 reg = TRANS_DP_CTL(pipe);
4171 temp = I915_READ(reg);
4172 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4173 TRANS_DP_PORT_SEL_MASK);
4174 temp |= TRANS_DP_PORT_SEL_NONE;
4175 I915_WRITE(reg, temp);
4176
4177 /* disable DPLL_SEL */
4178 temp = I915_READ(PCH_DPLL_SEL);
4179 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4180 I915_WRITE(PCH_DPLL_SEL, temp);
4181 }
4182
4183 /* disable PCH DPLL */
4184 intel_disable_shared_dpll(intel_crtc);
4185
4186 ironlake_fdi_pll_disable(intel_crtc);
4187 }
4188
4189 intel_crtc->active = false;
4190 intel_update_watermarks(crtc);
4191
4192 mutex_lock(&dev->struct_mutex);
4193 intel_update_fbc(dev);
4194 intel_edp_psr_update(dev);
4195 mutex_unlock(&dev->struct_mutex);
4196 }
4197
4198 static void haswell_crtc_disable(struct drm_crtc *crtc)
4199 {
4200 struct drm_device *dev = crtc->dev;
4201 struct drm_i915_private *dev_priv = dev->dev_private;
4202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4203 struct intel_encoder *encoder;
4204 int pipe = intel_crtc->pipe;
4205 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4206
4207 if (!intel_crtc->active)
4208 return;
4209
4210 intel_crtc_disable_planes(crtc);
4211
4212 for_each_encoder_on_crtc(dev, crtc, encoder) {
4213 intel_opregion_notify_encoder(encoder, false);
4214 encoder->disable(encoder);
4215 }
4216
4217 if (intel_crtc->config.has_pch_encoder)
4218 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4219 intel_disable_pipe(dev_priv, pipe);
4220
4221 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4222
4223 ironlake_pfit_disable(intel_crtc);
4224
4225 intel_ddi_disable_pipe_clock(intel_crtc);
4226
4227 for_each_encoder_on_crtc(dev, crtc, encoder)
4228 if (encoder->post_disable)
4229 encoder->post_disable(encoder);
4230
4231 if (intel_crtc->config.has_pch_encoder) {
4232 lpt_disable_pch_transcoder(dev_priv);
4233 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4234 intel_ddi_fdi_disable(crtc);
4235 }
4236
4237 intel_crtc->active = false;
4238 intel_update_watermarks(crtc);
4239
4240 mutex_lock(&dev->struct_mutex);
4241 intel_update_fbc(dev);
4242 intel_edp_psr_update(dev);
4243 mutex_unlock(&dev->struct_mutex);
4244 }
4245
4246 static void ironlake_crtc_off(struct drm_crtc *crtc)
4247 {
4248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4249 intel_put_shared_dpll(intel_crtc);
4250 }
4251
4252 static void haswell_crtc_off(struct drm_crtc *crtc)
4253 {
4254 intel_ddi_put_crtc_pll(crtc);
4255 }
4256
4257 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4258 {
4259 struct drm_device *dev = crtc->base.dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 struct intel_crtc_config *pipe_config = &crtc->config;
4262
4263 if (!crtc->config.gmch_pfit.control)
4264 return;
4265
4266 /*
4267 * The panel fitter should only be adjusted whilst the pipe is disabled,
4268 * according to register description and PRM.
4269 */
4270 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4271 assert_pipe_disabled(dev_priv, crtc->pipe);
4272
4273 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4274 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4275
4276 /* Border color in case we don't scale up to the full screen. Black by
4277 * default, change to something else for debugging. */
4278 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4279 }
4280
4281 #define for_each_power_domain(domain, mask) \
4282 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4283 if ((1 << (domain)) & (mask))
4284
4285 enum intel_display_power_domain
4286 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4287 {
4288 struct drm_device *dev = intel_encoder->base.dev;
4289 struct intel_digital_port *intel_dig_port;
4290
4291 switch (intel_encoder->type) {
4292 case INTEL_OUTPUT_UNKNOWN:
4293 /* Only DDI platforms should ever use this output type */
4294 WARN_ON_ONCE(!HAS_DDI(dev));
4295 case INTEL_OUTPUT_DISPLAYPORT:
4296 case INTEL_OUTPUT_HDMI:
4297 case INTEL_OUTPUT_EDP:
4298 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4299 switch (intel_dig_port->port) {
4300 case PORT_A:
4301 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4302 case PORT_B:
4303 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4304 case PORT_C:
4305 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4306 case PORT_D:
4307 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4308 default:
4309 WARN_ON_ONCE(1);
4310 return POWER_DOMAIN_PORT_OTHER;
4311 }
4312 case INTEL_OUTPUT_ANALOG:
4313 return POWER_DOMAIN_PORT_CRT;
4314 case INTEL_OUTPUT_DSI:
4315 return POWER_DOMAIN_PORT_DSI;
4316 default:
4317 return POWER_DOMAIN_PORT_OTHER;
4318 }
4319 }
4320
4321 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4322 {
4323 struct drm_device *dev = crtc->dev;
4324 struct intel_encoder *intel_encoder;
4325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4326 enum pipe pipe = intel_crtc->pipe;
4327 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4328 unsigned long mask;
4329 enum transcoder transcoder;
4330
4331 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4332
4333 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4334 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4335 if (pfit_enabled)
4336 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4337
4338 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4339 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4340
4341 return mask;
4342 }
4343
4344 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4345 bool enable)
4346 {
4347 if (dev_priv->power_domains.init_power_on == enable)
4348 return;
4349
4350 if (enable)
4351 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4352 else
4353 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4354
4355 dev_priv->power_domains.init_power_on = enable;
4356 }
4357
4358 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4359 {
4360 struct drm_i915_private *dev_priv = dev->dev_private;
4361 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4362 struct intel_crtc *crtc;
4363
4364 /*
4365 * First get all needed power domains, then put all unneeded, to avoid
4366 * any unnecessary toggling of the power wells.
4367 */
4368 for_each_intel_crtc(dev, crtc) {
4369 enum intel_display_power_domain domain;
4370
4371 if (!crtc->base.enabled)
4372 continue;
4373
4374 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4375
4376 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4377 intel_display_power_get(dev_priv, domain);
4378 }
4379
4380 for_each_intel_crtc(dev, crtc) {
4381 enum intel_display_power_domain domain;
4382
4383 for_each_power_domain(domain, crtc->enabled_power_domains)
4384 intel_display_power_put(dev_priv, domain);
4385
4386 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4387 }
4388
4389 intel_display_set_init_power(dev_priv, false);
4390 }
4391
4392 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4393 {
4394 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4395
4396 /* Obtain SKU information */
4397 mutex_lock(&dev_priv->dpio_lock);
4398 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4399 CCK_FUSE_HPLL_FREQ_MASK;
4400 mutex_unlock(&dev_priv->dpio_lock);
4401
4402 return vco_freq[hpll_freq];
4403 }
4404
4405 /* Adjust CDclk dividers to allow high res or save power if possible */
4406 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4407 {
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4409 u32 val, cmd;
4410
4411 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4412 dev_priv->vlv_cdclk_freq = cdclk;
4413
4414 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4415 cmd = 2;
4416 else if (cdclk == 266)
4417 cmd = 1;
4418 else
4419 cmd = 0;
4420
4421 mutex_lock(&dev_priv->rps.hw_lock);
4422 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4423 val &= ~DSPFREQGUAR_MASK;
4424 val |= (cmd << DSPFREQGUAR_SHIFT);
4425 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4426 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4427 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4428 50)) {
4429 DRM_ERROR("timed out waiting for CDclk change\n");
4430 }
4431 mutex_unlock(&dev_priv->rps.hw_lock);
4432
4433 if (cdclk == 400) {
4434 u32 divider, vco;
4435
4436 vco = valleyview_get_vco(dev_priv);
4437 divider = ((vco << 1) / cdclk) - 1;
4438
4439 mutex_lock(&dev_priv->dpio_lock);
4440 /* adjust cdclk divider */
4441 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4442 val &= ~0xf;
4443 val |= divider;
4444 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4445 mutex_unlock(&dev_priv->dpio_lock);
4446 }
4447
4448 mutex_lock(&dev_priv->dpio_lock);
4449 /* adjust self-refresh exit latency value */
4450 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4451 val &= ~0x7f;
4452
4453 /*
4454 * For high bandwidth configs, we set a higher latency in the bunit
4455 * so that the core display fetch happens in time to avoid underruns.
4456 */
4457 if (cdclk == 400)
4458 val |= 4500 / 250; /* 4.5 usec */
4459 else
4460 val |= 3000 / 250; /* 3.0 usec */
4461 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4462 mutex_unlock(&dev_priv->dpio_lock);
4463
4464 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4465 intel_i2c_reset(dev);
4466 }
4467
4468 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4469 {
4470 int cur_cdclk, vco;
4471 int divider;
4472
4473 vco = valleyview_get_vco(dev_priv);
4474
4475 mutex_lock(&dev_priv->dpio_lock);
4476 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4477 mutex_unlock(&dev_priv->dpio_lock);
4478
4479 divider &= 0xf;
4480
4481 cur_cdclk = (vco << 1) / (divider + 1);
4482
4483 return cur_cdclk;
4484 }
4485
4486 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4487 int max_pixclk)
4488 {
4489 /*
4490 * Really only a few cases to deal with, as only 4 CDclks are supported:
4491 * 200MHz
4492 * 267MHz
4493 * 320MHz
4494 * 400MHz
4495 * So we check to see whether we're above 90% of the lower bin and
4496 * adjust if needed.
4497 */
4498 if (max_pixclk > 288000) {
4499 return 400;
4500 } else if (max_pixclk > 240000) {
4501 return 320;
4502 } else
4503 return 266;
4504 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4505 }
4506
4507 /* compute the max pixel clock for new configuration */
4508 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4509 {
4510 struct drm_device *dev = dev_priv->dev;
4511 struct intel_crtc *intel_crtc;
4512 int max_pixclk = 0;
4513
4514 for_each_intel_crtc(dev, intel_crtc) {
4515 if (intel_crtc->new_enabled)
4516 max_pixclk = max(max_pixclk,
4517 intel_crtc->new_config->adjusted_mode.crtc_clock);
4518 }
4519
4520 return max_pixclk;
4521 }
4522
4523 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4524 unsigned *prepare_pipes)
4525 {
4526 struct drm_i915_private *dev_priv = dev->dev_private;
4527 struct intel_crtc *intel_crtc;
4528 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4529
4530 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4531 dev_priv->vlv_cdclk_freq)
4532 return;
4533
4534 /* disable/enable all currently active pipes while we change cdclk */
4535 for_each_intel_crtc(dev, intel_crtc)
4536 if (intel_crtc->base.enabled)
4537 *prepare_pipes |= (1 << intel_crtc->pipe);
4538 }
4539
4540 static void valleyview_modeset_global_resources(struct drm_device *dev)
4541 {
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4544 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4545
4546 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4547 valleyview_set_cdclk(dev, req_cdclk);
4548 modeset_update_crtc_power_domains(dev);
4549 }
4550
4551 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4552 {
4553 struct drm_device *dev = crtc->dev;
4554 struct drm_i915_private *dev_priv = dev->dev_private;
4555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4556 struct intel_encoder *encoder;
4557 int pipe = intel_crtc->pipe;
4558 int plane = intel_crtc->plane;
4559 bool is_dsi;
4560 u32 dspcntr;
4561
4562 WARN_ON(!crtc->enabled);
4563
4564 if (intel_crtc->active)
4565 return;
4566
4567 vlv_prepare_pll(intel_crtc);
4568
4569 /* Set up the display plane register */
4570 dspcntr = DISPPLANE_GAMMA_ENABLE;
4571
4572 if (intel_crtc->config.has_dp_encoder)
4573 intel_dp_set_m_n(intel_crtc);
4574
4575 intel_set_pipe_timings(intel_crtc);
4576
4577 /* pipesrc and dspsize control the size that is scaled from,
4578 * which should always be the user's requested size.
4579 */
4580 I915_WRITE(DSPSIZE(plane),
4581 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4582 (intel_crtc->config.pipe_src_w - 1));
4583 I915_WRITE(DSPPOS(plane), 0);
4584
4585 i9xx_set_pipeconf(intel_crtc);
4586
4587 I915_WRITE(DSPCNTR(plane), dspcntr);
4588 POSTING_READ(DSPCNTR(plane));
4589
4590 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4591 crtc->x, crtc->y);
4592
4593 intel_crtc->active = true;
4594
4595 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4596
4597 for_each_encoder_on_crtc(dev, crtc, encoder)
4598 if (encoder->pre_pll_enable)
4599 encoder->pre_pll_enable(encoder);
4600
4601 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4602
4603 if (!is_dsi) {
4604 if (IS_CHERRYVIEW(dev))
4605 chv_enable_pll(intel_crtc);
4606 else
4607 vlv_enable_pll(intel_crtc);
4608 }
4609
4610 for_each_encoder_on_crtc(dev, crtc, encoder)
4611 if (encoder->pre_enable)
4612 encoder->pre_enable(encoder);
4613
4614 i9xx_pfit_enable(intel_crtc);
4615
4616 intel_crtc_load_lut(crtc);
4617
4618 intel_update_watermarks(crtc);
4619 intel_enable_pipe(intel_crtc);
4620
4621 for_each_encoder_on_crtc(dev, crtc, encoder)
4622 encoder->enable(encoder);
4623
4624 intel_crtc_enable_planes(crtc);
4625
4626 drm_crtc_vblank_on(crtc);
4627
4628 /* Underruns don't raise interrupts, so check manually. */
4629 i9xx_check_fifo_underruns(dev);
4630 }
4631
4632 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4633 {
4634 struct drm_device *dev = crtc->base.dev;
4635 struct drm_i915_private *dev_priv = dev->dev_private;
4636
4637 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4638 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4639 }
4640
4641 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4642 {
4643 struct drm_device *dev = crtc->dev;
4644 struct drm_i915_private *dev_priv = dev->dev_private;
4645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4646 struct intel_encoder *encoder;
4647 int pipe = intel_crtc->pipe;
4648 int plane = intel_crtc->plane;
4649 u32 dspcntr;
4650
4651 WARN_ON(!crtc->enabled);
4652
4653 if (intel_crtc->active)
4654 return;
4655
4656 i9xx_set_pll_dividers(intel_crtc);
4657
4658 /* Set up the display plane register */
4659 dspcntr = DISPPLANE_GAMMA_ENABLE;
4660
4661 if (pipe == 0)
4662 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4663 else
4664 dspcntr |= DISPPLANE_SEL_PIPE_B;
4665
4666 if (intel_crtc->config.has_dp_encoder)
4667 intel_dp_set_m_n(intel_crtc);
4668
4669 intel_set_pipe_timings(intel_crtc);
4670
4671 /* pipesrc and dspsize control the size that is scaled from,
4672 * which should always be the user's requested size.
4673 */
4674 I915_WRITE(DSPSIZE(plane),
4675 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4676 (intel_crtc->config.pipe_src_w - 1));
4677 I915_WRITE(DSPPOS(plane), 0);
4678
4679 i9xx_set_pipeconf(intel_crtc);
4680
4681 I915_WRITE(DSPCNTR(plane), dspcntr);
4682 POSTING_READ(DSPCNTR(plane));
4683
4684 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4685 crtc->x, crtc->y);
4686
4687 intel_crtc->active = true;
4688
4689 if (!IS_GEN2(dev))
4690 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4691
4692 for_each_encoder_on_crtc(dev, crtc, encoder)
4693 if (encoder->pre_enable)
4694 encoder->pre_enable(encoder);
4695
4696 i9xx_enable_pll(intel_crtc);
4697
4698 i9xx_pfit_enable(intel_crtc);
4699
4700 intel_crtc_load_lut(crtc);
4701
4702 intel_update_watermarks(crtc);
4703 intel_enable_pipe(intel_crtc);
4704
4705 for_each_encoder_on_crtc(dev, crtc, encoder)
4706 encoder->enable(encoder);
4707
4708 intel_crtc_enable_planes(crtc);
4709
4710 /*
4711 * Gen2 reports pipe underruns whenever all planes are disabled.
4712 * So don't enable underrun reporting before at least some planes
4713 * are enabled.
4714 * FIXME: Need to fix the logic to work when we turn off all planes
4715 * but leave the pipe running.
4716 */
4717 if (IS_GEN2(dev))
4718 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4719
4720 drm_crtc_vblank_on(crtc);
4721
4722 /* Underruns don't raise interrupts, so check manually. */
4723 i9xx_check_fifo_underruns(dev);
4724 }
4725
4726 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4727 {
4728 struct drm_device *dev = crtc->base.dev;
4729 struct drm_i915_private *dev_priv = dev->dev_private;
4730
4731 if (!crtc->config.gmch_pfit.control)
4732 return;
4733
4734 assert_pipe_disabled(dev_priv, crtc->pipe);
4735
4736 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4737 I915_READ(PFIT_CONTROL));
4738 I915_WRITE(PFIT_CONTROL, 0);
4739 }
4740
4741 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4742 {
4743 struct drm_device *dev = crtc->dev;
4744 struct drm_i915_private *dev_priv = dev->dev_private;
4745 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4746 struct intel_encoder *encoder;
4747 int pipe = intel_crtc->pipe;
4748
4749 if (!intel_crtc->active)
4750 return;
4751
4752 /*
4753 * Gen2 reports pipe underruns whenever all planes are disabled.
4754 * So diasble underrun reporting before all the planes get disabled.
4755 * FIXME: Need to fix the logic to work when we turn off all planes
4756 * but leave the pipe running.
4757 */
4758 if (IS_GEN2(dev))
4759 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4760
4761 intel_crtc_disable_planes(crtc);
4762
4763 for_each_encoder_on_crtc(dev, crtc, encoder)
4764 encoder->disable(encoder);
4765
4766 /*
4767 * On gen2 planes are double buffered but the pipe isn't, so we must
4768 * wait for planes to fully turn off before disabling the pipe.
4769 */
4770 if (IS_GEN2(dev))
4771 intel_wait_for_vblank(dev, pipe);
4772
4773 intel_disable_pipe(dev_priv, pipe);
4774
4775 i9xx_pfit_disable(intel_crtc);
4776
4777 for_each_encoder_on_crtc(dev, crtc, encoder)
4778 if (encoder->post_disable)
4779 encoder->post_disable(encoder);
4780
4781 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4782 if (IS_CHERRYVIEW(dev))
4783 chv_disable_pll(dev_priv, pipe);
4784 else if (IS_VALLEYVIEW(dev))
4785 vlv_disable_pll(dev_priv, pipe);
4786 else
4787 i9xx_disable_pll(dev_priv, pipe);
4788 }
4789
4790 if (!IS_GEN2(dev))
4791 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4792
4793 intel_crtc->active = false;
4794 intel_update_watermarks(crtc);
4795
4796 mutex_lock(&dev->struct_mutex);
4797 intel_update_fbc(dev);
4798 intel_edp_psr_update(dev);
4799 mutex_unlock(&dev->struct_mutex);
4800 }
4801
4802 static void i9xx_crtc_off(struct drm_crtc *crtc)
4803 {
4804 }
4805
4806 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4807 bool enabled)
4808 {
4809 struct drm_device *dev = crtc->dev;
4810 struct drm_i915_master_private *master_priv;
4811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4812 int pipe = intel_crtc->pipe;
4813
4814 if (!dev->primary->master)
4815 return;
4816
4817 master_priv = dev->primary->master->driver_priv;
4818 if (!master_priv->sarea_priv)
4819 return;
4820
4821 switch (pipe) {
4822 case 0:
4823 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4824 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4825 break;
4826 case 1:
4827 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4828 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4829 break;
4830 default:
4831 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4832 break;
4833 }
4834 }
4835
4836 /**
4837 * Sets the power management mode of the pipe and plane.
4838 */
4839 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4840 {
4841 struct drm_device *dev = crtc->dev;
4842 struct drm_i915_private *dev_priv = dev->dev_private;
4843 struct intel_encoder *intel_encoder;
4844 bool enable = false;
4845
4846 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4847 enable |= intel_encoder->connectors_active;
4848
4849 if (enable)
4850 dev_priv->display.crtc_enable(crtc);
4851 else
4852 dev_priv->display.crtc_disable(crtc);
4853
4854 intel_crtc_update_sarea(crtc, enable);
4855 }
4856
4857 static void intel_crtc_disable(struct drm_crtc *crtc)
4858 {
4859 struct drm_device *dev = crtc->dev;
4860 struct drm_connector *connector;
4861 struct drm_i915_private *dev_priv = dev->dev_private;
4862
4863 /* crtc should still be enabled when we disable it. */
4864 WARN_ON(!crtc->enabled);
4865
4866 dev_priv->display.crtc_disable(crtc);
4867 intel_crtc_update_sarea(crtc, false);
4868 dev_priv->display.off(crtc);
4869
4870 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4871 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4872 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4873
4874 if (crtc->primary->fb) {
4875 mutex_lock(&dev->struct_mutex);
4876 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4877 mutex_unlock(&dev->struct_mutex);
4878 crtc->primary->fb = NULL;
4879 }
4880
4881 /* Update computed state. */
4882 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4883 if (!connector->encoder || !connector->encoder->crtc)
4884 continue;
4885
4886 if (connector->encoder->crtc != crtc)
4887 continue;
4888
4889 connector->dpms = DRM_MODE_DPMS_OFF;
4890 to_intel_encoder(connector->encoder)->connectors_active = false;
4891 }
4892 }
4893
4894 void intel_encoder_destroy(struct drm_encoder *encoder)
4895 {
4896 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4897
4898 drm_encoder_cleanup(encoder);
4899 kfree(intel_encoder);
4900 }
4901
4902 /* Simple dpms helper for encoders with just one connector, no cloning and only
4903 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4904 * state of the entire output pipe. */
4905 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4906 {
4907 if (mode == DRM_MODE_DPMS_ON) {
4908 encoder->connectors_active = true;
4909
4910 intel_crtc_update_dpms(encoder->base.crtc);
4911 } else {
4912 encoder->connectors_active = false;
4913
4914 intel_crtc_update_dpms(encoder->base.crtc);
4915 }
4916 }
4917
4918 /* Cross check the actual hw state with our own modeset state tracking (and it's
4919 * internal consistency). */
4920 static void intel_connector_check_state(struct intel_connector *connector)
4921 {
4922 if (connector->get_hw_state(connector)) {
4923 struct intel_encoder *encoder = connector->encoder;
4924 struct drm_crtc *crtc;
4925 bool encoder_enabled;
4926 enum pipe pipe;
4927
4928 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4929 connector->base.base.id,
4930 connector->base.name);
4931
4932 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4933 "wrong connector dpms state\n");
4934 WARN(connector->base.encoder != &encoder->base,
4935 "active connector not linked to encoder\n");
4936 WARN(!encoder->connectors_active,
4937 "encoder->connectors_active not set\n");
4938
4939 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4940 WARN(!encoder_enabled, "encoder not enabled\n");
4941 if (WARN_ON(!encoder->base.crtc))
4942 return;
4943
4944 crtc = encoder->base.crtc;
4945
4946 WARN(!crtc->enabled, "crtc not enabled\n");
4947 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4948 WARN(pipe != to_intel_crtc(crtc)->pipe,
4949 "encoder active on the wrong pipe\n");
4950 }
4951 }
4952
4953 /* Even simpler default implementation, if there's really no special case to
4954 * consider. */
4955 void intel_connector_dpms(struct drm_connector *connector, int mode)
4956 {
4957 /* All the simple cases only support two dpms states. */
4958 if (mode != DRM_MODE_DPMS_ON)
4959 mode = DRM_MODE_DPMS_OFF;
4960
4961 if (mode == connector->dpms)
4962 return;
4963
4964 connector->dpms = mode;
4965
4966 /* Only need to change hw state when actually enabled */
4967 if (connector->encoder)
4968 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4969
4970 intel_modeset_check_state(connector->dev);
4971 }
4972
4973 /* Simple connector->get_hw_state implementation for encoders that support only
4974 * one connector and no cloning and hence the encoder state determines the state
4975 * of the connector. */
4976 bool intel_connector_get_hw_state(struct intel_connector *connector)
4977 {
4978 enum pipe pipe = 0;
4979 struct intel_encoder *encoder = connector->encoder;
4980
4981 return encoder->get_hw_state(encoder, &pipe);
4982 }
4983
4984 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4985 struct intel_crtc_config *pipe_config)
4986 {
4987 struct drm_i915_private *dev_priv = dev->dev_private;
4988 struct intel_crtc *pipe_B_crtc =
4989 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4990
4991 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4992 pipe_name(pipe), pipe_config->fdi_lanes);
4993 if (pipe_config->fdi_lanes > 4) {
4994 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4995 pipe_name(pipe), pipe_config->fdi_lanes);
4996 return false;
4997 }
4998
4999 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5000 if (pipe_config->fdi_lanes > 2) {
5001 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5002 pipe_config->fdi_lanes);
5003 return false;
5004 } else {
5005 return true;
5006 }
5007 }
5008
5009 if (INTEL_INFO(dev)->num_pipes == 2)
5010 return true;
5011
5012 /* Ivybridge 3 pipe is really complicated */
5013 switch (pipe) {
5014 case PIPE_A:
5015 return true;
5016 case PIPE_B:
5017 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5018 pipe_config->fdi_lanes > 2) {
5019 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5020 pipe_name(pipe), pipe_config->fdi_lanes);
5021 return false;
5022 }
5023 return true;
5024 case PIPE_C:
5025 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5026 pipe_B_crtc->config.fdi_lanes <= 2) {
5027 if (pipe_config->fdi_lanes > 2) {
5028 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5029 pipe_name(pipe), pipe_config->fdi_lanes);
5030 return false;
5031 }
5032 } else {
5033 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5034 return false;
5035 }
5036 return true;
5037 default:
5038 BUG();
5039 }
5040 }
5041
5042 #define RETRY 1
5043 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5044 struct intel_crtc_config *pipe_config)
5045 {
5046 struct drm_device *dev = intel_crtc->base.dev;
5047 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5048 int lane, link_bw, fdi_dotclock;
5049 bool setup_ok, needs_recompute = false;
5050
5051 retry:
5052 /* FDI is a binary signal running at ~2.7GHz, encoding
5053 * each output octet as 10 bits. The actual frequency
5054 * is stored as a divider into a 100MHz clock, and the
5055 * mode pixel clock is stored in units of 1KHz.
5056 * Hence the bw of each lane in terms of the mode signal
5057 * is:
5058 */
5059 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5060
5061 fdi_dotclock = adjusted_mode->crtc_clock;
5062
5063 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5064 pipe_config->pipe_bpp);
5065
5066 pipe_config->fdi_lanes = lane;
5067
5068 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5069 link_bw, &pipe_config->fdi_m_n);
5070
5071 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5072 intel_crtc->pipe, pipe_config);
5073 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5074 pipe_config->pipe_bpp -= 2*3;
5075 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5076 pipe_config->pipe_bpp);
5077 needs_recompute = true;
5078 pipe_config->bw_constrained = true;
5079
5080 goto retry;
5081 }
5082
5083 if (needs_recompute)
5084 return RETRY;
5085
5086 return setup_ok ? 0 : -EINVAL;
5087 }
5088
5089 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5090 struct intel_crtc_config *pipe_config)
5091 {
5092 pipe_config->ips_enabled = i915.enable_ips &&
5093 hsw_crtc_supports_ips(crtc) &&
5094 pipe_config->pipe_bpp <= 24;
5095 }
5096
5097 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5098 struct intel_crtc_config *pipe_config)
5099 {
5100 struct drm_device *dev = crtc->base.dev;
5101 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5102
5103 /* FIXME should check pixel clock limits on all platforms */
5104 if (INTEL_INFO(dev)->gen < 4) {
5105 struct drm_i915_private *dev_priv = dev->dev_private;
5106 int clock_limit =
5107 dev_priv->display.get_display_clock_speed(dev);
5108
5109 /*
5110 * Enable pixel doubling when the dot clock
5111 * is > 90% of the (display) core speed.
5112 *
5113 * GDG double wide on either pipe,
5114 * otherwise pipe A only.
5115 */
5116 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5117 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5118 clock_limit *= 2;
5119 pipe_config->double_wide = true;
5120 }
5121
5122 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5123 return -EINVAL;
5124 }
5125
5126 /*
5127 * Pipe horizontal size must be even in:
5128 * - DVO ganged mode
5129 * - LVDS dual channel mode
5130 * - Double wide pipe
5131 */
5132 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5133 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5134 pipe_config->pipe_src_w &= ~1;
5135
5136 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5137 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5138 */
5139 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5140 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5141 return -EINVAL;
5142
5143 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5144 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5145 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5146 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5147 * for lvds. */
5148 pipe_config->pipe_bpp = 8*3;
5149 }
5150
5151 if (HAS_IPS(dev))
5152 hsw_compute_ips_config(crtc, pipe_config);
5153
5154 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5155 * clock survives for now. */
5156 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5157 pipe_config->shared_dpll = crtc->config.shared_dpll;
5158
5159 if (pipe_config->has_pch_encoder)
5160 return ironlake_fdi_compute_config(crtc, pipe_config);
5161
5162 return 0;
5163 }
5164
5165 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5166 {
5167 return 400000; /* FIXME */
5168 }
5169
5170 static int i945_get_display_clock_speed(struct drm_device *dev)
5171 {
5172 return 400000;
5173 }
5174
5175 static int i915_get_display_clock_speed(struct drm_device *dev)
5176 {
5177 return 333000;
5178 }
5179
5180 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5181 {
5182 return 200000;
5183 }
5184
5185 static int pnv_get_display_clock_speed(struct drm_device *dev)
5186 {
5187 u16 gcfgc = 0;
5188
5189 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5190
5191 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5192 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5193 return 267000;
5194 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5195 return 333000;
5196 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5197 return 444000;
5198 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5199 return 200000;
5200 default:
5201 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5202 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5203 return 133000;
5204 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5205 return 167000;
5206 }
5207 }
5208
5209 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5210 {
5211 u16 gcfgc = 0;
5212
5213 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5214
5215 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5216 return 133000;
5217 else {
5218 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5219 case GC_DISPLAY_CLOCK_333_MHZ:
5220 return 333000;
5221 default:
5222 case GC_DISPLAY_CLOCK_190_200_MHZ:
5223 return 190000;
5224 }
5225 }
5226 }
5227
5228 static int i865_get_display_clock_speed(struct drm_device *dev)
5229 {
5230 return 266000;
5231 }
5232
5233 static int i855_get_display_clock_speed(struct drm_device *dev)
5234 {
5235 u16 hpllcc = 0;
5236 /* Assume that the hardware is in the high speed state. This
5237 * should be the default.
5238 */
5239 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5240 case GC_CLOCK_133_200:
5241 case GC_CLOCK_100_200:
5242 return 200000;
5243 case GC_CLOCK_166_250:
5244 return 250000;
5245 case GC_CLOCK_100_133:
5246 return 133000;
5247 }
5248
5249 /* Shouldn't happen */
5250 return 0;
5251 }
5252
5253 static int i830_get_display_clock_speed(struct drm_device *dev)
5254 {
5255 return 133000;
5256 }
5257
5258 static void
5259 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5260 {
5261 while (*num > DATA_LINK_M_N_MASK ||
5262 *den > DATA_LINK_M_N_MASK) {
5263 *num >>= 1;
5264 *den >>= 1;
5265 }
5266 }
5267
5268 static void compute_m_n(unsigned int m, unsigned int n,
5269 uint32_t *ret_m, uint32_t *ret_n)
5270 {
5271 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5272 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5273 intel_reduce_m_n_ratio(ret_m, ret_n);
5274 }
5275
5276 void
5277 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5278 int pixel_clock, int link_clock,
5279 struct intel_link_m_n *m_n)
5280 {
5281 m_n->tu = 64;
5282
5283 compute_m_n(bits_per_pixel * pixel_clock,
5284 link_clock * nlanes * 8,
5285 &m_n->gmch_m, &m_n->gmch_n);
5286
5287 compute_m_n(pixel_clock, link_clock,
5288 &m_n->link_m, &m_n->link_n);
5289 }
5290
5291 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5292 {
5293 if (i915.panel_use_ssc >= 0)
5294 return i915.panel_use_ssc != 0;
5295 return dev_priv->vbt.lvds_use_ssc
5296 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5297 }
5298
5299 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5300 {
5301 struct drm_device *dev = crtc->dev;
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 int refclk;
5304
5305 if (IS_VALLEYVIEW(dev)) {
5306 refclk = 100000;
5307 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5308 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5309 refclk = dev_priv->vbt.lvds_ssc_freq;
5310 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5311 } else if (!IS_GEN2(dev)) {
5312 refclk = 96000;
5313 } else {
5314 refclk = 48000;
5315 }
5316
5317 return refclk;
5318 }
5319
5320 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5321 {
5322 return (1 << dpll->n) << 16 | dpll->m2;
5323 }
5324
5325 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5326 {
5327 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5328 }
5329
5330 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5331 intel_clock_t *reduced_clock)
5332 {
5333 struct drm_device *dev = crtc->base.dev;
5334 u32 fp, fp2 = 0;
5335
5336 if (IS_PINEVIEW(dev)) {
5337 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5338 if (reduced_clock)
5339 fp2 = pnv_dpll_compute_fp(reduced_clock);
5340 } else {
5341 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5342 if (reduced_clock)
5343 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5344 }
5345
5346 crtc->config.dpll_hw_state.fp0 = fp;
5347
5348 crtc->lowfreq_avail = false;
5349 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5350 reduced_clock && i915.powersave) {
5351 crtc->config.dpll_hw_state.fp1 = fp2;
5352 crtc->lowfreq_avail = true;
5353 } else {
5354 crtc->config.dpll_hw_state.fp1 = fp;
5355 }
5356 }
5357
5358 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5359 pipe)
5360 {
5361 u32 reg_val;
5362
5363 /*
5364 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5365 * and set it to a reasonable value instead.
5366 */
5367 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5368 reg_val &= 0xffffff00;
5369 reg_val |= 0x00000030;
5370 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5371
5372 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5373 reg_val &= 0x8cffffff;
5374 reg_val = 0x8c000000;
5375 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5376
5377 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5378 reg_val &= 0xffffff00;
5379 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5380
5381 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5382 reg_val &= 0x00ffffff;
5383 reg_val |= 0xb0000000;
5384 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5385 }
5386
5387 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5388 struct intel_link_m_n *m_n)
5389 {
5390 struct drm_device *dev = crtc->base.dev;
5391 struct drm_i915_private *dev_priv = dev->dev_private;
5392 int pipe = crtc->pipe;
5393
5394 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5395 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5396 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5397 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5398 }
5399
5400 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5401 struct intel_link_m_n *m_n)
5402 {
5403 struct drm_device *dev = crtc->base.dev;
5404 struct drm_i915_private *dev_priv = dev->dev_private;
5405 int pipe = crtc->pipe;
5406 enum transcoder transcoder = crtc->config.cpu_transcoder;
5407
5408 if (INTEL_INFO(dev)->gen >= 5) {
5409 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5410 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5411 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5412 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5413 } else {
5414 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5415 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5416 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5417 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5418 }
5419 }
5420
5421 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5422 {
5423 if (crtc->config.has_pch_encoder)
5424 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5425 else
5426 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5427 }
5428
5429 static void vlv_update_pll(struct intel_crtc *crtc)
5430 {
5431 u32 dpll, dpll_md;
5432
5433 /*
5434 * Enable DPIO clock input. We should never disable the reference
5435 * clock for pipe B, since VGA hotplug / manual detection depends
5436 * on it.
5437 */
5438 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5439 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5440 /* We should never disable this, set it here for state tracking */
5441 if (crtc->pipe == PIPE_B)
5442 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5443 dpll |= DPLL_VCO_ENABLE;
5444 crtc->config.dpll_hw_state.dpll = dpll;
5445
5446 dpll_md = (crtc->config.pixel_multiplier - 1)
5447 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5448 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5449 }
5450
5451 static void vlv_prepare_pll(struct intel_crtc *crtc)
5452 {
5453 struct drm_device *dev = crtc->base.dev;
5454 struct drm_i915_private *dev_priv = dev->dev_private;
5455 int pipe = crtc->pipe;
5456 u32 mdiv;
5457 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5458 u32 coreclk, reg_val;
5459
5460 mutex_lock(&dev_priv->dpio_lock);
5461
5462 bestn = crtc->config.dpll.n;
5463 bestm1 = crtc->config.dpll.m1;
5464 bestm2 = crtc->config.dpll.m2;
5465 bestp1 = crtc->config.dpll.p1;
5466 bestp2 = crtc->config.dpll.p2;
5467
5468 /* See eDP HDMI DPIO driver vbios notes doc */
5469
5470 /* PLL B needs special handling */
5471 if (pipe == PIPE_B)
5472 vlv_pllb_recal_opamp(dev_priv, pipe);
5473
5474 /* Set up Tx target for periodic Rcomp update */
5475 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5476
5477 /* Disable target IRef on PLL */
5478 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5479 reg_val &= 0x00ffffff;
5480 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5481
5482 /* Disable fast lock */
5483 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5484
5485 /* Set idtafcrecal before PLL is enabled */
5486 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5487 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5488 mdiv |= ((bestn << DPIO_N_SHIFT));
5489 mdiv |= (1 << DPIO_K_SHIFT);
5490
5491 /*
5492 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5493 * but we don't support that).
5494 * Note: don't use the DAC post divider as it seems unstable.
5495 */
5496 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5497 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5498
5499 mdiv |= DPIO_ENABLE_CALIBRATION;
5500 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5501
5502 /* Set HBR and RBR LPF coefficients */
5503 if (crtc->config.port_clock == 162000 ||
5504 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5505 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5506 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5507 0x009f0003);
5508 else
5509 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5510 0x00d0000f);
5511
5512 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5513 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5514 /* Use SSC source */
5515 if (pipe == PIPE_A)
5516 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5517 0x0df40000);
5518 else
5519 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5520 0x0df70000);
5521 } else { /* HDMI or VGA */
5522 /* Use bend source */
5523 if (pipe == PIPE_A)
5524 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5525 0x0df70000);
5526 else
5527 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5528 0x0df40000);
5529 }
5530
5531 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5532 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5533 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5534 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5535 coreclk |= 0x01000000;
5536 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5537
5538 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5539 mutex_unlock(&dev_priv->dpio_lock);
5540 }
5541
5542 static void chv_update_pll(struct intel_crtc *crtc)
5543 {
5544 struct drm_device *dev = crtc->base.dev;
5545 struct drm_i915_private *dev_priv = dev->dev_private;
5546 int pipe = crtc->pipe;
5547 int dpll_reg = DPLL(crtc->pipe);
5548 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5549 u32 loopfilter, intcoeff;
5550 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5551 int refclk;
5552
5553 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5554 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5555 DPLL_VCO_ENABLE;
5556 if (pipe != PIPE_A)
5557 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5558
5559 crtc->config.dpll_hw_state.dpll_md =
5560 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5561
5562 bestn = crtc->config.dpll.n;
5563 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5564 bestm1 = crtc->config.dpll.m1;
5565 bestm2 = crtc->config.dpll.m2 >> 22;
5566 bestp1 = crtc->config.dpll.p1;
5567 bestp2 = crtc->config.dpll.p2;
5568
5569 /*
5570 * Enable Refclk and SSC
5571 */
5572 I915_WRITE(dpll_reg,
5573 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5574
5575 mutex_lock(&dev_priv->dpio_lock);
5576
5577 /* p1 and p2 divider */
5578 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5579 5 << DPIO_CHV_S1_DIV_SHIFT |
5580 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5581 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5582 1 << DPIO_CHV_K_DIV_SHIFT);
5583
5584 /* Feedback post-divider - m2 */
5585 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5586
5587 /* Feedback refclk divider - n and m1 */
5588 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5589 DPIO_CHV_M1_DIV_BY_2 |
5590 1 << DPIO_CHV_N_DIV_SHIFT);
5591
5592 /* M2 fraction division */
5593 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5594
5595 /* M2 fraction division enable */
5596 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5597 DPIO_CHV_FRAC_DIV_EN |
5598 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5599
5600 /* Loop filter */
5601 refclk = i9xx_get_refclk(&crtc->base, 0);
5602 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5603 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5604 if (refclk == 100000)
5605 intcoeff = 11;
5606 else if (refclk == 38400)
5607 intcoeff = 10;
5608 else
5609 intcoeff = 9;
5610 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5611 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5612
5613 /* AFC Recal */
5614 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5615 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5616 DPIO_AFC_RECAL);
5617
5618 mutex_unlock(&dev_priv->dpio_lock);
5619 }
5620
5621 static void i9xx_update_pll(struct intel_crtc *crtc,
5622 intel_clock_t *reduced_clock,
5623 int num_connectors)
5624 {
5625 struct drm_device *dev = crtc->base.dev;
5626 struct drm_i915_private *dev_priv = dev->dev_private;
5627 u32 dpll;
5628 bool is_sdvo;
5629 struct dpll *clock = &crtc->config.dpll;
5630
5631 i9xx_update_pll_dividers(crtc, reduced_clock);
5632
5633 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5634 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5635
5636 dpll = DPLL_VGA_MODE_DIS;
5637
5638 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5639 dpll |= DPLLB_MODE_LVDS;
5640 else
5641 dpll |= DPLLB_MODE_DAC_SERIAL;
5642
5643 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5644 dpll |= (crtc->config.pixel_multiplier - 1)
5645 << SDVO_MULTIPLIER_SHIFT_HIRES;
5646 }
5647
5648 if (is_sdvo)
5649 dpll |= DPLL_SDVO_HIGH_SPEED;
5650
5651 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5652 dpll |= DPLL_SDVO_HIGH_SPEED;
5653
5654 /* compute bitmask from p1 value */
5655 if (IS_PINEVIEW(dev))
5656 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5657 else {
5658 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5659 if (IS_G4X(dev) && reduced_clock)
5660 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5661 }
5662 switch (clock->p2) {
5663 case 5:
5664 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5665 break;
5666 case 7:
5667 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5668 break;
5669 case 10:
5670 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5671 break;
5672 case 14:
5673 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5674 break;
5675 }
5676 if (INTEL_INFO(dev)->gen >= 4)
5677 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5678
5679 if (crtc->config.sdvo_tv_clock)
5680 dpll |= PLL_REF_INPUT_TVCLKINBC;
5681 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5682 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5683 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5684 else
5685 dpll |= PLL_REF_INPUT_DREFCLK;
5686
5687 dpll |= DPLL_VCO_ENABLE;
5688 crtc->config.dpll_hw_state.dpll = dpll;
5689
5690 if (INTEL_INFO(dev)->gen >= 4) {
5691 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5692 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5693 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5694 }
5695 }
5696
5697 static void i8xx_update_pll(struct intel_crtc *crtc,
5698 intel_clock_t *reduced_clock,
5699 int num_connectors)
5700 {
5701 struct drm_device *dev = crtc->base.dev;
5702 struct drm_i915_private *dev_priv = dev->dev_private;
5703 u32 dpll;
5704 struct dpll *clock = &crtc->config.dpll;
5705
5706 i9xx_update_pll_dividers(crtc, reduced_clock);
5707
5708 dpll = DPLL_VGA_MODE_DIS;
5709
5710 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5711 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5712 } else {
5713 if (clock->p1 == 2)
5714 dpll |= PLL_P1_DIVIDE_BY_TWO;
5715 else
5716 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5717 if (clock->p2 == 4)
5718 dpll |= PLL_P2_DIVIDE_BY_4;
5719 }
5720
5721 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5722 dpll |= DPLL_DVO_2X_MODE;
5723
5724 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5725 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5726 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5727 else
5728 dpll |= PLL_REF_INPUT_DREFCLK;
5729
5730 dpll |= DPLL_VCO_ENABLE;
5731 crtc->config.dpll_hw_state.dpll = dpll;
5732 }
5733
5734 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5735 {
5736 struct drm_device *dev = intel_crtc->base.dev;
5737 struct drm_i915_private *dev_priv = dev->dev_private;
5738 enum pipe pipe = intel_crtc->pipe;
5739 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5740 struct drm_display_mode *adjusted_mode =
5741 &intel_crtc->config.adjusted_mode;
5742 uint32_t crtc_vtotal, crtc_vblank_end;
5743 int vsyncshift = 0;
5744
5745 /* We need to be careful not to changed the adjusted mode, for otherwise
5746 * the hw state checker will get angry at the mismatch. */
5747 crtc_vtotal = adjusted_mode->crtc_vtotal;
5748 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5749
5750 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5751 /* the chip adds 2 halflines automatically */
5752 crtc_vtotal -= 1;
5753 crtc_vblank_end -= 1;
5754
5755 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5756 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5757 else
5758 vsyncshift = adjusted_mode->crtc_hsync_start -
5759 adjusted_mode->crtc_htotal / 2;
5760 if (vsyncshift < 0)
5761 vsyncshift += adjusted_mode->crtc_htotal;
5762 }
5763
5764 if (INTEL_INFO(dev)->gen > 3)
5765 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5766
5767 I915_WRITE(HTOTAL(cpu_transcoder),
5768 (adjusted_mode->crtc_hdisplay - 1) |
5769 ((adjusted_mode->crtc_htotal - 1) << 16));
5770 I915_WRITE(HBLANK(cpu_transcoder),
5771 (adjusted_mode->crtc_hblank_start - 1) |
5772 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5773 I915_WRITE(HSYNC(cpu_transcoder),
5774 (adjusted_mode->crtc_hsync_start - 1) |
5775 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5776
5777 I915_WRITE(VTOTAL(cpu_transcoder),
5778 (adjusted_mode->crtc_vdisplay - 1) |
5779 ((crtc_vtotal - 1) << 16));
5780 I915_WRITE(VBLANK(cpu_transcoder),
5781 (adjusted_mode->crtc_vblank_start - 1) |
5782 ((crtc_vblank_end - 1) << 16));
5783 I915_WRITE(VSYNC(cpu_transcoder),
5784 (adjusted_mode->crtc_vsync_start - 1) |
5785 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5786
5787 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5788 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5789 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5790 * bits. */
5791 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5792 (pipe == PIPE_B || pipe == PIPE_C))
5793 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5794
5795 /* pipesrc controls the size that is scaled from, which should
5796 * always be the user's requested size.
5797 */
5798 I915_WRITE(PIPESRC(pipe),
5799 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5800 (intel_crtc->config.pipe_src_h - 1));
5801 }
5802
5803 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5804 struct intel_crtc_config *pipe_config)
5805 {
5806 struct drm_device *dev = crtc->base.dev;
5807 struct drm_i915_private *dev_priv = dev->dev_private;
5808 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5809 uint32_t tmp;
5810
5811 tmp = I915_READ(HTOTAL(cpu_transcoder));
5812 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5813 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5814 tmp = I915_READ(HBLANK(cpu_transcoder));
5815 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5816 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5817 tmp = I915_READ(HSYNC(cpu_transcoder));
5818 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5819 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5820
5821 tmp = I915_READ(VTOTAL(cpu_transcoder));
5822 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5823 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5824 tmp = I915_READ(VBLANK(cpu_transcoder));
5825 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5826 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5827 tmp = I915_READ(VSYNC(cpu_transcoder));
5828 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5829 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5830
5831 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5832 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5833 pipe_config->adjusted_mode.crtc_vtotal += 1;
5834 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5835 }
5836
5837 tmp = I915_READ(PIPESRC(crtc->pipe));
5838 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5839 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5840
5841 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5842 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5843 }
5844
5845 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5846 struct intel_crtc_config *pipe_config)
5847 {
5848 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5849 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5850 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5851 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5852
5853 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5854 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5855 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5856 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5857
5858 mode->flags = pipe_config->adjusted_mode.flags;
5859
5860 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5861 mode->flags |= pipe_config->adjusted_mode.flags;
5862 }
5863
5864 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5865 {
5866 struct drm_device *dev = intel_crtc->base.dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 uint32_t pipeconf;
5869
5870 pipeconf = 0;
5871
5872 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5873 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5874 pipeconf |= PIPECONF_ENABLE;
5875
5876 if (intel_crtc->config.double_wide)
5877 pipeconf |= PIPECONF_DOUBLE_WIDE;
5878
5879 /* only g4x and later have fancy bpc/dither controls */
5880 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5881 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5882 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5883 pipeconf |= PIPECONF_DITHER_EN |
5884 PIPECONF_DITHER_TYPE_SP;
5885
5886 switch (intel_crtc->config.pipe_bpp) {
5887 case 18:
5888 pipeconf |= PIPECONF_6BPC;
5889 break;
5890 case 24:
5891 pipeconf |= PIPECONF_8BPC;
5892 break;
5893 case 30:
5894 pipeconf |= PIPECONF_10BPC;
5895 break;
5896 default:
5897 /* Case prevented by intel_choose_pipe_bpp_dither. */
5898 BUG();
5899 }
5900 }
5901
5902 if (HAS_PIPE_CXSR(dev)) {
5903 if (intel_crtc->lowfreq_avail) {
5904 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5905 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5906 } else {
5907 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5908 }
5909 }
5910
5911 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5912 if (INTEL_INFO(dev)->gen < 4 ||
5913 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5914 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5915 else
5916 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5917 } else
5918 pipeconf |= PIPECONF_PROGRESSIVE;
5919
5920 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5921 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5922
5923 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5924 POSTING_READ(PIPECONF(intel_crtc->pipe));
5925 }
5926
5927 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5928 int x, int y,
5929 struct drm_framebuffer *fb)
5930 {
5931 struct drm_device *dev = crtc->dev;
5932 struct drm_i915_private *dev_priv = dev->dev_private;
5933 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5934 int refclk, num_connectors = 0;
5935 intel_clock_t clock, reduced_clock;
5936 bool ok, has_reduced_clock = false;
5937 bool is_lvds = false, is_dsi = false;
5938 struct intel_encoder *encoder;
5939 const intel_limit_t *limit;
5940
5941 for_each_encoder_on_crtc(dev, crtc, encoder) {
5942 switch (encoder->type) {
5943 case INTEL_OUTPUT_LVDS:
5944 is_lvds = true;
5945 break;
5946 case INTEL_OUTPUT_DSI:
5947 is_dsi = true;
5948 break;
5949 }
5950
5951 num_connectors++;
5952 }
5953
5954 if (is_dsi)
5955 return 0;
5956
5957 if (!intel_crtc->config.clock_set) {
5958 refclk = i9xx_get_refclk(crtc, num_connectors);
5959
5960 /*
5961 * Returns a set of divisors for the desired target clock with
5962 * the given refclk, or FALSE. The returned values represent
5963 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5964 * 2) / p1 / p2.
5965 */
5966 limit = intel_limit(crtc, refclk);
5967 ok = dev_priv->display.find_dpll(limit, crtc,
5968 intel_crtc->config.port_clock,
5969 refclk, NULL, &clock);
5970 if (!ok) {
5971 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5972 return -EINVAL;
5973 }
5974
5975 if (is_lvds && dev_priv->lvds_downclock_avail) {
5976 /*
5977 * Ensure we match the reduced clock's P to the target
5978 * clock. If the clocks don't match, we can't switch
5979 * the display clock by using the FP0/FP1. In such case
5980 * we will disable the LVDS downclock feature.
5981 */
5982 has_reduced_clock =
5983 dev_priv->display.find_dpll(limit, crtc,
5984 dev_priv->lvds_downclock,
5985 refclk, &clock,
5986 &reduced_clock);
5987 }
5988 /* Compat-code for transition, will disappear. */
5989 intel_crtc->config.dpll.n = clock.n;
5990 intel_crtc->config.dpll.m1 = clock.m1;
5991 intel_crtc->config.dpll.m2 = clock.m2;
5992 intel_crtc->config.dpll.p1 = clock.p1;
5993 intel_crtc->config.dpll.p2 = clock.p2;
5994 }
5995
5996 if (IS_GEN2(dev)) {
5997 i8xx_update_pll(intel_crtc,
5998 has_reduced_clock ? &reduced_clock : NULL,
5999 num_connectors);
6000 } else if (IS_CHERRYVIEW(dev)) {
6001 chv_update_pll(intel_crtc);
6002 } else if (IS_VALLEYVIEW(dev)) {
6003 vlv_update_pll(intel_crtc);
6004 } else {
6005 i9xx_update_pll(intel_crtc,
6006 has_reduced_clock ? &reduced_clock : NULL,
6007 num_connectors);
6008 }
6009
6010 return 0;
6011 }
6012
6013 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6014 struct intel_crtc_config *pipe_config)
6015 {
6016 struct drm_device *dev = crtc->base.dev;
6017 struct drm_i915_private *dev_priv = dev->dev_private;
6018 uint32_t tmp;
6019
6020 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6021 return;
6022
6023 tmp = I915_READ(PFIT_CONTROL);
6024 if (!(tmp & PFIT_ENABLE))
6025 return;
6026
6027 /* Check whether the pfit is attached to our pipe. */
6028 if (INTEL_INFO(dev)->gen < 4) {
6029 if (crtc->pipe != PIPE_B)
6030 return;
6031 } else {
6032 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6033 return;
6034 }
6035
6036 pipe_config->gmch_pfit.control = tmp;
6037 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6038 if (INTEL_INFO(dev)->gen < 5)
6039 pipe_config->gmch_pfit.lvds_border_bits =
6040 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6041 }
6042
6043 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6044 struct intel_crtc_config *pipe_config)
6045 {
6046 struct drm_device *dev = crtc->base.dev;
6047 struct drm_i915_private *dev_priv = dev->dev_private;
6048 int pipe = pipe_config->cpu_transcoder;
6049 intel_clock_t clock;
6050 u32 mdiv;
6051 int refclk = 100000;
6052
6053 mutex_lock(&dev_priv->dpio_lock);
6054 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6055 mutex_unlock(&dev_priv->dpio_lock);
6056
6057 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6058 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6059 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6060 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6061 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6062
6063 vlv_clock(refclk, &clock);
6064
6065 /* clock.dot is the fast clock */
6066 pipe_config->port_clock = clock.dot / 5;
6067 }
6068
6069 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6070 struct intel_plane_config *plane_config)
6071 {
6072 struct drm_device *dev = crtc->base.dev;
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074 u32 val, base, offset;
6075 int pipe = crtc->pipe, plane = crtc->plane;
6076 int fourcc, pixel_format;
6077 int aligned_height;
6078
6079 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6080 if (!crtc->base.primary->fb) {
6081 DRM_DEBUG_KMS("failed to alloc fb\n");
6082 return;
6083 }
6084
6085 val = I915_READ(DSPCNTR(plane));
6086
6087 if (INTEL_INFO(dev)->gen >= 4)
6088 if (val & DISPPLANE_TILED)
6089 plane_config->tiled = true;
6090
6091 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6092 fourcc = intel_format_to_fourcc(pixel_format);
6093 crtc->base.primary->fb->pixel_format = fourcc;
6094 crtc->base.primary->fb->bits_per_pixel =
6095 drm_format_plane_cpp(fourcc, 0) * 8;
6096
6097 if (INTEL_INFO(dev)->gen >= 4) {
6098 if (plane_config->tiled)
6099 offset = I915_READ(DSPTILEOFF(plane));
6100 else
6101 offset = I915_READ(DSPLINOFF(plane));
6102 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6103 } else {
6104 base = I915_READ(DSPADDR(plane));
6105 }
6106 plane_config->base = base;
6107
6108 val = I915_READ(PIPESRC(pipe));
6109 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6110 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6111
6112 val = I915_READ(DSPSTRIDE(pipe));
6113 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6114
6115 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6116 plane_config->tiled);
6117
6118 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6119 aligned_height, PAGE_SIZE);
6120
6121 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6122 pipe, plane, crtc->base.primary->fb->width,
6123 crtc->base.primary->fb->height,
6124 crtc->base.primary->fb->bits_per_pixel, base,
6125 crtc->base.primary->fb->pitches[0],
6126 plane_config->size);
6127
6128 }
6129
6130 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6131 struct intel_crtc_config *pipe_config)
6132 {
6133 struct drm_device *dev = crtc->base.dev;
6134 struct drm_i915_private *dev_priv = dev->dev_private;
6135 int pipe = pipe_config->cpu_transcoder;
6136 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6137 intel_clock_t clock;
6138 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6139 int refclk = 100000;
6140
6141 mutex_lock(&dev_priv->dpio_lock);
6142 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6143 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6144 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6145 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6146 mutex_unlock(&dev_priv->dpio_lock);
6147
6148 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6149 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6150 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6151 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6152 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6153
6154 chv_clock(refclk, &clock);
6155
6156 /* clock.dot is the fast clock */
6157 pipe_config->port_clock = clock.dot / 5;
6158 }
6159
6160 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6161 struct intel_crtc_config *pipe_config)
6162 {
6163 struct drm_device *dev = crtc->base.dev;
6164 struct drm_i915_private *dev_priv = dev->dev_private;
6165 uint32_t tmp;
6166
6167 if (!intel_display_power_enabled(dev_priv,
6168 POWER_DOMAIN_PIPE(crtc->pipe)))
6169 return false;
6170
6171 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6172 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6173
6174 tmp = I915_READ(PIPECONF(crtc->pipe));
6175 if (!(tmp & PIPECONF_ENABLE))
6176 return false;
6177
6178 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6179 switch (tmp & PIPECONF_BPC_MASK) {
6180 case PIPECONF_6BPC:
6181 pipe_config->pipe_bpp = 18;
6182 break;
6183 case PIPECONF_8BPC:
6184 pipe_config->pipe_bpp = 24;
6185 break;
6186 case PIPECONF_10BPC:
6187 pipe_config->pipe_bpp = 30;
6188 break;
6189 default:
6190 break;
6191 }
6192 }
6193
6194 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6195 pipe_config->limited_color_range = true;
6196
6197 if (INTEL_INFO(dev)->gen < 4)
6198 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6199
6200 intel_get_pipe_timings(crtc, pipe_config);
6201
6202 i9xx_get_pfit_config(crtc, pipe_config);
6203
6204 if (INTEL_INFO(dev)->gen >= 4) {
6205 tmp = I915_READ(DPLL_MD(crtc->pipe));
6206 pipe_config->pixel_multiplier =
6207 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6208 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6209 pipe_config->dpll_hw_state.dpll_md = tmp;
6210 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6211 tmp = I915_READ(DPLL(crtc->pipe));
6212 pipe_config->pixel_multiplier =
6213 ((tmp & SDVO_MULTIPLIER_MASK)
6214 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6215 } else {
6216 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6217 * port and will be fixed up in the encoder->get_config
6218 * function. */
6219 pipe_config->pixel_multiplier = 1;
6220 }
6221 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6222 if (!IS_VALLEYVIEW(dev)) {
6223 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6224 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6225 } else {
6226 /* Mask out read-only status bits. */
6227 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6228 DPLL_PORTC_READY_MASK |
6229 DPLL_PORTB_READY_MASK);
6230 }
6231
6232 if (IS_CHERRYVIEW(dev))
6233 chv_crtc_clock_get(crtc, pipe_config);
6234 else if (IS_VALLEYVIEW(dev))
6235 vlv_crtc_clock_get(crtc, pipe_config);
6236 else
6237 i9xx_crtc_clock_get(crtc, pipe_config);
6238
6239 return true;
6240 }
6241
6242 static void ironlake_init_pch_refclk(struct drm_device *dev)
6243 {
6244 struct drm_i915_private *dev_priv = dev->dev_private;
6245 struct drm_mode_config *mode_config = &dev->mode_config;
6246 struct intel_encoder *encoder;
6247 u32 val, final;
6248 bool has_lvds = false;
6249 bool has_cpu_edp = false;
6250 bool has_panel = false;
6251 bool has_ck505 = false;
6252 bool can_ssc = false;
6253
6254 /* We need to take the global config into account */
6255 list_for_each_entry(encoder, &mode_config->encoder_list,
6256 base.head) {
6257 switch (encoder->type) {
6258 case INTEL_OUTPUT_LVDS:
6259 has_panel = true;
6260 has_lvds = true;
6261 break;
6262 case INTEL_OUTPUT_EDP:
6263 has_panel = true;
6264 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6265 has_cpu_edp = true;
6266 break;
6267 }
6268 }
6269
6270 if (HAS_PCH_IBX(dev)) {
6271 has_ck505 = dev_priv->vbt.display_clock_mode;
6272 can_ssc = has_ck505;
6273 } else {
6274 has_ck505 = false;
6275 can_ssc = true;
6276 }
6277
6278 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6279 has_panel, has_lvds, has_ck505);
6280
6281 /* Ironlake: try to setup display ref clock before DPLL
6282 * enabling. This is only under driver's control after
6283 * PCH B stepping, previous chipset stepping should be
6284 * ignoring this setting.
6285 */
6286 val = I915_READ(PCH_DREF_CONTROL);
6287
6288 /* As we must carefully and slowly disable/enable each source in turn,
6289 * compute the final state we want first and check if we need to
6290 * make any changes at all.
6291 */
6292 final = val;
6293 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6294 if (has_ck505)
6295 final |= DREF_NONSPREAD_CK505_ENABLE;
6296 else
6297 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6298
6299 final &= ~DREF_SSC_SOURCE_MASK;
6300 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6301 final &= ~DREF_SSC1_ENABLE;
6302
6303 if (has_panel) {
6304 final |= DREF_SSC_SOURCE_ENABLE;
6305
6306 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6307 final |= DREF_SSC1_ENABLE;
6308
6309 if (has_cpu_edp) {
6310 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6311 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6312 else
6313 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6314 } else
6315 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6316 } else {
6317 final |= DREF_SSC_SOURCE_DISABLE;
6318 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6319 }
6320
6321 if (final == val)
6322 return;
6323
6324 /* Always enable nonspread source */
6325 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6326
6327 if (has_ck505)
6328 val |= DREF_NONSPREAD_CK505_ENABLE;
6329 else
6330 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6331
6332 if (has_panel) {
6333 val &= ~DREF_SSC_SOURCE_MASK;
6334 val |= DREF_SSC_SOURCE_ENABLE;
6335
6336 /* SSC must be turned on before enabling the CPU output */
6337 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6338 DRM_DEBUG_KMS("Using SSC on panel\n");
6339 val |= DREF_SSC1_ENABLE;
6340 } else
6341 val &= ~DREF_SSC1_ENABLE;
6342
6343 /* Get SSC going before enabling the outputs */
6344 I915_WRITE(PCH_DREF_CONTROL, val);
6345 POSTING_READ(PCH_DREF_CONTROL);
6346 udelay(200);
6347
6348 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6349
6350 /* Enable CPU source on CPU attached eDP */
6351 if (has_cpu_edp) {
6352 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6353 DRM_DEBUG_KMS("Using SSC on eDP\n");
6354 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6355 } else
6356 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6357 } else
6358 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6359
6360 I915_WRITE(PCH_DREF_CONTROL, val);
6361 POSTING_READ(PCH_DREF_CONTROL);
6362 udelay(200);
6363 } else {
6364 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6365
6366 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6367
6368 /* Turn off CPU output */
6369 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6370
6371 I915_WRITE(PCH_DREF_CONTROL, val);
6372 POSTING_READ(PCH_DREF_CONTROL);
6373 udelay(200);
6374
6375 /* Turn off the SSC source */
6376 val &= ~DREF_SSC_SOURCE_MASK;
6377 val |= DREF_SSC_SOURCE_DISABLE;
6378
6379 /* Turn off SSC1 */
6380 val &= ~DREF_SSC1_ENABLE;
6381
6382 I915_WRITE(PCH_DREF_CONTROL, val);
6383 POSTING_READ(PCH_DREF_CONTROL);
6384 udelay(200);
6385 }
6386
6387 BUG_ON(val != final);
6388 }
6389
6390 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6391 {
6392 uint32_t tmp;
6393
6394 tmp = I915_READ(SOUTH_CHICKEN2);
6395 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6396 I915_WRITE(SOUTH_CHICKEN2, tmp);
6397
6398 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6399 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6400 DRM_ERROR("FDI mPHY reset assert timeout\n");
6401
6402 tmp = I915_READ(SOUTH_CHICKEN2);
6403 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6404 I915_WRITE(SOUTH_CHICKEN2, tmp);
6405
6406 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6407 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6408 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6409 }
6410
6411 /* WaMPhyProgramming:hsw */
6412 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6413 {
6414 uint32_t tmp;
6415
6416 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6417 tmp &= ~(0xFF << 24);
6418 tmp |= (0x12 << 24);
6419 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6420
6421 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6422 tmp |= (1 << 11);
6423 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6424
6425 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6426 tmp |= (1 << 11);
6427 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6428
6429 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6430 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6431 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6432
6433 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6434 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6435 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6436
6437 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6438 tmp &= ~(7 << 13);
6439 tmp |= (5 << 13);
6440 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6441
6442 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6443 tmp &= ~(7 << 13);
6444 tmp |= (5 << 13);
6445 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6446
6447 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6448 tmp &= ~0xFF;
6449 tmp |= 0x1C;
6450 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6451
6452 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6453 tmp &= ~0xFF;
6454 tmp |= 0x1C;
6455 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6456
6457 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6458 tmp &= ~(0xFF << 16);
6459 tmp |= (0x1C << 16);
6460 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6461
6462 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6463 tmp &= ~(0xFF << 16);
6464 tmp |= (0x1C << 16);
6465 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6466
6467 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6468 tmp |= (1 << 27);
6469 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6470
6471 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6472 tmp |= (1 << 27);
6473 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6474
6475 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6476 tmp &= ~(0xF << 28);
6477 tmp |= (4 << 28);
6478 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6479
6480 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6481 tmp &= ~(0xF << 28);
6482 tmp |= (4 << 28);
6483 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6484 }
6485
6486 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6487 * Programming" based on the parameters passed:
6488 * - Sequence to enable CLKOUT_DP
6489 * - Sequence to enable CLKOUT_DP without spread
6490 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6491 */
6492 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6493 bool with_fdi)
6494 {
6495 struct drm_i915_private *dev_priv = dev->dev_private;
6496 uint32_t reg, tmp;
6497
6498 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6499 with_spread = true;
6500 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6501 with_fdi, "LP PCH doesn't have FDI\n"))
6502 with_fdi = false;
6503
6504 mutex_lock(&dev_priv->dpio_lock);
6505
6506 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6507 tmp &= ~SBI_SSCCTL_DISABLE;
6508 tmp |= SBI_SSCCTL_PATHALT;
6509 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6510
6511 udelay(24);
6512
6513 if (with_spread) {
6514 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6515 tmp &= ~SBI_SSCCTL_PATHALT;
6516 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6517
6518 if (with_fdi) {
6519 lpt_reset_fdi_mphy(dev_priv);
6520 lpt_program_fdi_mphy(dev_priv);
6521 }
6522 }
6523
6524 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6525 SBI_GEN0 : SBI_DBUFF0;
6526 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6527 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6528 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6529
6530 mutex_unlock(&dev_priv->dpio_lock);
6531 }
6532
6533 /* Sequence to disable CLKOUT_DP */
6534 static void lpt_disable_clkout_dp(struct drm_device *dev)
6535 {
6536 struct drm_i915_private *dev_priv = dev->dev_private;
6537 uint32_t reg, tmp;
6538
6539 mutex_lock(&dev_priv->dpio_lock);
6540
6541 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6542 SBI_GEN0 : SBI_DBUFF0;
6543 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6544 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6545 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6546
6547 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6548 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6549 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6550 tmp |= SBI_SSCCTL_PATHALT;
6551 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6552 udelay(32);
6553 }
6554 tmp |= SBI_SSCCTL_DISABLE;
6555 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6556 }
6557
6558 mutex_unlock(&dev_priv->dpio_lock);
6559 }
6560
6561 static void lpt_init_pch_refclk(struct drm_device *dev)
6562 {
6563 struct drm_mode_config *mode_config = &dev->mode_config;
6564 struct intel_encoder *encoder;
6565 bool has_vga = false;
6566
6567 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6568 switch (encoder->type) {
6569 case INTEL_OUTPUT_ANALOG:
6570 has_vga = true;
6571 break;
6572 }
6573 }
6574
6575 if (has_vga)
6576 lpt_enable_clkout_dp(dev, true, true);
6577 else
6578 lpt_disable_clkout_dp(dev);
6579 }
6580
6581 /*
6582 * Initialize reference clocks when the driver loads
6583 */
6584 void intel_init_pch_refclk(struct drm_device *dev)
6585 {
6586 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6587 ironlake_init_pch_refclk(dev);
6588 else if (HAS_PCH_LPT(dev))
6589 lpt_init_pch_refclk(dev);
6590 }
6591
6592 static int ironlake_get_refclk(struct drm_crtc *crtc)
6593 {
6594 struct drm_device *dev = crtc->dev;
6595 struct drm_i915_private *dev_priv = dev->dev_private;
6596 struct intel_encoder *encoder;
6597 int num_connectors = 0;
6598 bool is_lvds = false;
6599
6600 for_each_encoder_on_crtc(dev, crtc, encoder) {
6601 switch (encoder->type) {
6602 case INTEL_OUTPUT_LVDS:
6603 is_lvds = true;
6604 break;
6605 }
6606 num_connectors++;
6607 }
6608
6609 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6610 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6611 dev_priv->vbt.lvds_ssc_freq);
6612 return dev_priv->vbt.lvds_ssc_freq;
6613 }
6614
6615 return 120000;
6616 }
6617
6618 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6619 {
6620 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6622 int pipe = intel_crtc->pipe;
6623 uint32_t val;
6624
6625 val = 0;
6626
6627 switch (intel_crtc->config.pipe_bpp) {
6628 case 18:
6629 val |= PIPECONF_6BPC;
6630 break;
6631 case 24:
6632 val |= PIPECONF_8BPC;
6633 break;
6634 case 30:
6635 val |= PIPECONF_10BPC;
6636 break;
6637 case 36:
6638 val |= PIPECONF_12BPC;
6639 break;
6640 default:
6641 /* Case prevented by intel_choose_pipe_bpp_dither. */
6642 BUG();
6643 }
6644
6645 if (intel_crtc->config.dither)
6646 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6647
6648 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6649 val |= PIPECONF_INTERLACED_ILK;
6650 else
6651 val |= PIPECONF_PROGRESSIVE;
6652
6653 if (intel_crtc->config.limited_color_range)
6654 val |= PIPECONF_COLOR_RANGE_SELECT;
6655
6656 I915_WRITE(PIPECONF(pipe), val);
6657 POSTING_READ(PIPECONF(pipe));
6658 }
6659
6660 /*
6661 * Set up the pipe CSC unit.
6662 *
6663 * Currently only full range RGB to limited range RGB conversion
6664 * is supported, but eventually this should handle various
6665 * RGB<->YCbCr scenarios as well.
6666 */
6667 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6668 {
6669 struct drm_device *dev = crtc->dev;
6670 struct drm_i915_private *dev_priv = dev->dev_private;
6671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6672 int pipe = intel_crtc->pipe;
6673 uint16_t coeff = 0x7800; /* 1.0 */
6674
6675 /*
6676 * TODO: Check what kind of values actually come out of the pipe
6677 * with these coeff/postoff values and adjust to get the best
6678 * accuracy. Perhaps we even need to take the bpc value into
6679 * consideration.
6680 */
6681
6682 if (intel_crtc->config.limited_color_range)
6683 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6684
6685 /*
6686 * GY/GU and RY/RU should be the other way around according
6687 * to BSpec, but reality doesn't agree. Just set them up in
6688 * a way that results in the correct picture.
6689 */
6690 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6691 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6692
6693 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6694 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6695
6696 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6697 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6698
6699 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6700 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6701 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6702
6703 if (INTEL_INFO(dev)->gen > 6) {
6704 uint16_t postoff = 0;
6705
6706 if (intel_crtc->config.limited_color_range)
6707 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6708
6709 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6710 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6711 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6712
6713 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6714 } else {
6715 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6716
6717 if (intel_crtc->config.limited_color_range)
6718 mode |= CSC_BLACK_SCREEN_OFFSET;
6719
6720 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6721 }
6722 }
6723
6724 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6725 {
6726 struct drm_device *dev = crtc->dev;
6727 struct drm_i915_private *dev_priv = dev->dev_private;
6728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6729 enum pipe pipe = intel_crtc->pipe;
6730 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6731 uint32_t val;
6732
6733 val = 0;
6734
6735 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6736 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6737
6738 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6739 val |= PIPECONF_INTERLACED_ILK;
6740 else
6741 val |= PIPECONF_PROGRESSIVE;
6742
6743 I915_WRITE(PIPECONF(cpu_transcoder), val);
6744 POSTING_READ(PIPECONF(cpu_transcoder));
6745
6746 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6747 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6748
6749 if (IS_BROADWELL(dev)) {
6750 val = 0;
6751
6752 switch (intel_crtc->config.pipe_bpp) {
6753 case 18:
6754 val |= PIPEMISC_DITHER_6_BPC;
6755 break;
6756 case 24:
6757 val |= PIPEMISC_DITHER_8_BPC;
6758 break;
6759 case 30:
6760 val |= PIPEMISC_DITHER_10_BPC;
6761 break;
6762 case 36:
6763 val |= PIPEMISC_DITHER_12_BPC;
6764 break;
6765 default:
6766 /* Case prevented by pipe_config_set_bpp. */
6767 BUG();
6768 }
6769
6770 if (intel_crtc->config.dither)
6771 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6772
6773 I915_WRITE(PIPEMISC(pipe), val);
6774 }
6775 }
6776
6777 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6778 intel_clock_t *clock,
6779 bool *has_reduced_clock,
6780 intel_clock_t *reduced_clock)
6781 {
6782 struct drm_device *dev = crtc->dev;
6783 struct drm_i915_private *dev_priv = dev->dev_private;
6784 struct intel_encoder *intel_encoder;
6785 int refclk;
6786 const intel_limit_t *limit;
6787 bool ret, is_lvds = false;
6788
6789 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6790 switch (intel_encoder->type) {
6791 case INTEL_OUTPUT_LVDS:
6792 is_lvds = true;
6793 break;
6794 }
6795 }
6796
6797 refclk = ironlake_get_refclk(crtc);
6798
6799 /*
6800 * Returns a set of divisors for the desired target clock with the given
6801 * refclk, or FALSE. The returned values represent the clock equation:
6802 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6803 */
6804 limit = intel_limit(crtc, refclk);
6805 ret = dev_priv->display.find_dpll(limit, crtc,
6806 to_intel_crtc(crtc)->config.port_clock,
6807 refclk, NULL, clock);
6808 if (!ret)
6809 return false;
6810
6811 if (is_lvds && dev_priv->lvds_downclock_avail) {
6812 /*
6813 * Ensure we match the reduced clock's P to the target clock.
6814 * If the clocks don't match, we can't switch the display clock
6815 * by using the FP0/FP1. In such case we will disable the LVDS
6816 * downclock feature.
6817 */
6818 *has_reduced_clock =
6819 dev_priv->display.find_dpll(limit, crtc,
6820 dev_priv->lvds_downclock,
6821 refclk, clock,
6822 reduced_clock);
6823 }
6824
6825 return true;
6826 }
6827
6828 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6829 {
6830 /*
6831 * Account for spread spectrum to avoid
6832 * oversubscribing the link. Max center spread
6833 * is 2.5%; use 5% for safety's sake.
6834 */
6835 u32 bps = target_clock * bpp * 21 / 20;
6836 return DIV_ROUND_UP(bps, link_bw * 8);
6837 }
6838
6839 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6840 {
6841 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6842 }
6843
6844 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6845 u32 *fp,
6846 intel_clock_t *reduced_clock, u32 *fp2)
6847 {
6848 struct drm_crtc *crtc = &intel_crtc->base;
6849 struct drm_device *dev = crtc->dev;
6850 struct drm_i915_private *dev_priv = dev->dev_private;
6851 struct intel_encoder *intel_encoder;
6852 uint32_t dpll;
6853 int factor, num_connectors = 0;
6854 bool is_lvds = false, is_sdvo = false;
6855
6856 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6857 switch (intel_encoder->type) {
6858 case INTEL_OUTPUT_LVDS:
6859 is_lvds = true;
6860 break;
6861 case INTEL_OUTPUT_SDVO:
6862 case INTEL_OUTPUT_HDMI:
6863 is_sdvo = true;
6864 break;
6865 }
6866
6867 num_connectors++;
6868 }
6869
6870 /* Enable autotuning of the PLL clock (if permissible) */
6871 factor = 21;
6872 if (is_lvds) {
6873 if ((intel_panel_use_ssc(dev_priv) &&
6874 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6875 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6876 factor = 25;
6877 } else if (intel_crtc->config.sdvo_tv_clock)
6878 factor = 20;
6879
6880 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6881 *fp |= FP_CB_TUNE;
6882
6883 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6884 *fp2 |= FP_CB_TUNE;
6885
6886 dpll = 0;
6887
6888 if (is_lvds)
6889 dpll |= DPLLB_MODE_LVDS;
6890 else
6891 dpll |= DPLLB_MODE_DAC_SERIAL;
6892
6893 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6894 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6895
6896 if (is_sdvo)
6897 dpll |= DPLL_SDVO_HIGH_SPEED;
6898 if (intel_crtc->config.has_dp_encoder)
6899 dpll |= DPLL_SDVO_HIGH_SPEED;
6900
6901 /* compute bitmask from p1 value */
6902 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6903 /* also FPA1 */
6904 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6905
6906 switch (intel_crtc->config.dpll.p2) {
6907 case 5:
6908 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6909 break;
6910 case 7:
6911 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6912 break;
6913 case 10:
6914 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6915 break;
6916 case 14:
6917 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6918 break;
6919 }
6920
6921 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6922 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6923 else
6924 dpll |= PLL_REF_INPUT_DREFCLK;
6925
6926 return dpll | DPLL_VCO_ENABLE;
6927 }
6928
6929 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6930 int x, int y,
6931 struct drm_framebuffer *fb)
6932 {
6933 struct drm_device *dev = crtc->dev;
6934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6935 int num_connectors = 0;
6936 intel_clock_t clock, reduced_clock;
6937 u32 dpll = 0, fp = 0, fp2 = 0;
6938 bool ok, has_reduced_clock = false;
6939 bool is_lvds = false;
6940 struct intel_encoder *encoder;
6941 struct intel_shared_dpll *pll;
6942
6943 for_each_encoder_on_crtc(dev, crtc, encoder) {
6944 switch (encoder->type) {
6945 case INTEL_OUTPUT_LVDS:
6946 is_lvds = true;
6947 break;
6948 }
6949
6950 num_connectors++;
6951 }
6952
6953 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6954 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6955
6956 ok = ironlake_compute_clocks(crtc, &clock,
6957 &has_reduced_clock, &reduced_clock);
6958 if (!ok && !intel_crtc->config.clock_set) {
6959 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6960 return -EINVAL;
6961 }
6962 /* Compat-code for transition, will disappear. */
6963 if (!intel_crtc->config.clock_set) {
6964 intel_crtc->config.dpll.n = clock.n;
6965 intel_crtc->config.dpll.m1 = clock.m1;
6966 intel_crtc->config.dpll.m2 = clock.m2;
6967 intel_crtc->config.dpll.p1 = clock.p1;
6968 intel_crtc->config.dpll.p2 = clock.p2;
6969 }
6970
6971 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6972 if (intel_crtc->config.has_pch_encoder) {
6973 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6974 if (has_reduced_clock)
6975 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6976
6977 dpll = ironlake_compute_dpll(intel_crtc,
6978 &fp, &reduced_clock,
6979 has_reduced_clock ? &fp2 : NULL);
6980
6981 intel_crtc->config.dpll_hw_state.dpll = dpll;
6982 intel_crtc->config.dpll_hw_state.fp0 = fp;
6983 if (has_reduced_clock)
6984 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6985 else
6986 intel_crtc->config.dpll_hw_state.fp1 = fp;
6987
6988 pll = intel_get_shared_dpll(intel_crtc);
6989 if (pll == NULL) {
6990 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6991 pipe_name(intel_crtc->pipe));
6992 return -EINVAL;
6993 }
6994 } else
6995 intel_put_shared_dpll(intel_crtc);
6996
6997 if (is_lvds && has_reduced_clock && i915.powersave)
6998 intel_crtc->lowfreq_avail = true;
6999 else
7000 intel_crtc->lowfreq_avail = false;
7001
7002 return 0;
7003 }
7004
7005 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7006 struct intel_link_m_n *m_n)
7007 {
7008 struct drm_device *dev = crtc->base.dev;
7009 struct drm_i915_private *dev_priv = dev->dev_private;
7010 enum pipe pipe = crtc->pipe;
7011
7012 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7013 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7014 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7015 & ~TU_SIZE_MASK;
7016 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7017 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7018 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7019 }
7020
7021 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7022 enum transcoder transcoder,
7023 struct intel_link_m_n *m_n)
7024 {
7025 struct drm_device *dev = crtc->base.dev;
7026 struct drm_i915_private *dev_priv = dev->dev_private;
7027 enum pipe pipe = crtc->pipe;
7028
7029 if (INTEL_INFO(dev)->gen >= 5) {
7030 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7031 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7032 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7033 & ~TU_SIZE_MASK;
7034 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7035 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7036 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7037 } else {
7038 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7039 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7040 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7041 & ~TU_SIZE_MASK;
7042 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7043 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7044 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7045 }
7046 }
7047
7048 void intel_dp_get_m_n(struct intel_crtc *crtc,
7049 struct intel_crtc_config *pipe_config)
7050 {
7051 if (crtc->config.has_pch_encoder)
7052 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7053 else
7054 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7055 &pipe_config->dp_m_n);
7056 }
7057
7058 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7059 struct intel_crtc_config *pipe_config)
7060 {
7061 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7062 &pipe_config->fdi_m_n);
7063 }
7064
7065 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7066 struct intel_crtc_config *pipe_config)
7067 {
7068 struct drm_device *dev = crtc->base.dev;
7069 struct drm_i915_private *dev_priv = dev->dev_private;
7070 uint32_t tmp;
7071
7072 tmp = I915_READ(PF_CTL(crtc->pipe));
7073
7074 if (tmp & PF_ENABLE) {
7075 pipe_config->pch_pfit.enabled = true;
7076 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7077 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7078
7079 /* We currently do not free assignements of panel fitters on
7080 * ivb/hsw (since we don't use the higher upscaling modes which
7081 * differentiates them) so just WARN about this case for now. */
7082 if (IS_GEN7(dev)) {
7083 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7084 PF_PIPE_SEL_IVB(crtc->pipe));
7085 }
7086 }
7087 }
7088
7089 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7090 struct intel_plane_config *plane_config)
7091 {
7092 struct drm_device *dev = crtc->base.dev;
7093 struct drm_i915_private *dev_priv = dev->dev_private;
7094 u32 val, base, offset;
7095 int pipe = crtc->pipe, plane = crtc->plane;
7096 int fourcc, pixel_format;
7097 int aligned_height;
7098
7099 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7100 if (!crtc->base.primary->fb) {
7101 DRM_DEBUG_KMS("failed to alloc fb\n");
7102 return;
7103 }
7104
7105 val = I915_READ(DSPCNTR(plane));
7106
7107 if (INTEL_INFO(dev)->gen >= 4)
7108 if (val & DISPPLANE_TILED)
7109 plane_config->tiled = true;
7110
7111 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7112 fourcc = intel_format_to_fourcc(pixel_format);
7113 crtc->base.primary->fb->pixel_format = fourcc;
7114 crtc->base.primary->fb->bits_per_pixel =
7115 drm_format_plane_cpp(fourcc, 0) * 8;
7116
7117 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7118 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7119 offset = I915_READ(DSPOFFSET(plane));
7120 } else {
7121 if (plane_config->tiled)
7122 offset = I915_READ(DSPTILEOFF(plane));
7123 else
7124 offset = I915_READ(DSPLINOFF(plane));
7125 }
7126 plane_config->base = base;
7127
7128 val = I915_READ(PIPESRC(pipe));
7129 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7130 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7131
7132 val = I915_READ(DSPSTRIDE(pipe));
7133 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7134
7135 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7136 plane_config->tiled);
7137
7138 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7139 aligned_height, PAGE_SIZE);
7140
7141 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7142 pipe, plane, crtc->base.primary->fb->width,
7143 crtc->base.primary->fb->height,
7144 crtc->base.primary->fb->bits_per_pixel, base,
7145 crtc->base.primary->fb->pitches[0],
7146 plane_config->size);
7147 }
7148
7149 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7150 struct intel_crtc_config *pipe_config)
7151 {
7152 struct drm_device *dev = crtc->base.dev;
7153 struct drm_i915_private *dev_priv = dev->dev_private;
7154 uint32_t tmp;
7155
7156 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7157 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7158
7159 tmp = I915_READ(PIPECONF(crtc->pipe));
7160 if (!(tmp & PIPECONF_ENABLE))
7161 return false;
7162
7163 switch (tmp & PIPECONF_BPC_MASK) {
7164 case PIPECONF_6BPC:
7165 pipe_config->pipe_bpp = 18;
7166 break;
7167 case PIPECONF_8BPC:
7168 pipe_config->pipe_bpp = 24;
7169 break;
7170 case PIPECONF_10BPC:
7171 pipe_config->pipe_bpp = 30;
7172 break;
7173 case PIPECONF_12BPC:
7174 pipe_config->pipe_bpp = 36;
7175 break;
7176 default:
7177 break;
7178 }
7179
7180 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7181 pipe_config->limited_color_range = true;
7182
7183 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7184 struct intel_shared_dpll *pll;
7185
7186 pipe_config->has_pch_encoder = true;
7187
7188 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7189 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7190 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7191
7192 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7193
7194 if (HAS_PCH_IBX(dev_priv->dev)) {
7195 pipe_config->shared_dpll =
7196 (enum intel_dpll_id) crtc->pipe;
7197 } else {
7198 tmp = I915_READ(PCH_DPLL_SEL);
7199 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7200 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7201 else
7202 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7203 }
7204
7205 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7206
7207 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7208 &pipe_config->dpll_hw_state));
7209
7210 tmp = pipe_config->dpll_hw_state.dpll;
7211 pipe_config->pixel_multiplier =
7212 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7213 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7214
7215 ironlake_pch_clock_get(crtc, pipe_config);
7216 } else {
7217 pipe_config->pixel_multiplier = 1;
7218 }
7219
7220 intel_get_pipe_timings(crtc, pipe_config);
7221
7222 ironlake_get_pfit_config(crtc, pipe_config);
7223
7224 return true;
7225 }
7226
7227 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7228 {
7229 struct drm_device *dev = dev_priv->dev;
7230 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7231 struct intel_crtc *crtc;
7232
7233 for_each_intel_crtc(dev, crtc)
7234 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7235 pipe_name(crtc->pipe));
7236
7237 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7238 WARN(plls->spll_refcount, "SPLL enabled\n");
7239 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7240 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7241 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7242 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7243 "CPU PWM1 enabled\n");
7244 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7245 "CPU PWM2 enabled\n");
7246 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7247 "PCH PWM1 enabled\n");
7248 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7249 "Utility pin enabled\n");
7250 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7251
7252 /*
7253 * In theory we can still leave IRQs enabled, as long as only the HPD
7254 * interrupts remain enabled. We used to check for that, but since it's
7255 * gen-specific and since we only disable LCPLL after we fully disable
7256 * the interrupts, the check below should be enough.
7257 */
7258 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7259 }
7260
7261 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7262 {
7263 struct drm_device *dev = dev_priv->dev;
7264
7265 if (IS_HASWELL(dev)) {
7266 mutex_lock(&dev_priv->rps.hw_lock);
7267 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7268 val))
7269 DRM_ERROR("Failed to disable D_COMP\n");
7270 mutex_unlock(&dev_priv->rps.hw_lock);
7271 } else {
7272 I915_WRITE(D_COMP, val);
7273 }
7274 POSTING_READ(D_COMP);
7275 }
7276
7277 /*
7278 * This function implements pieces of two sequences from BSpec:
7279 * - Sequence for display software to disable LCPLL
7280 * - Sequence for display software to allow package C8+
7281 * The steps implemented here are just the steps that actually touch the LCPLL
7282 * register. Callers should take care of disabling all the display engine
7283 * functions, doing the mode unset, fixing interrupts, etc.
7284 */
7285 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7286 bool switch_to_fclk, bool allow_power_down)
7287 {
7288 uint32_t val;
7289
7290 assert_can_disable_lcpll(dev_priv);
7291
7292 val = I915_READ(LCPLL_CTL);
7293
7294 if (switch_to_fclk) {
7295 val |= LCPLL_CD_SOURCE_FCLK;
7296 I915_WRITE(LCPLL_CTL, val);
7297
7298 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7299 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7300 DRM_ERROR("Switching to FCLK failed\n");
7301
7302 val = I915_READ(LCPLL_CTL);
7303 }
7304
7305 val |= LCPLL_PLL_DISABLE;
7306 I915_WRITE(LCPLL_CTL, val);
7307 POSTING_READ(LCPLL_CTL);
7308
7309 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7310 DRM_ERROR("LCPLL still locked\n");
7311
7312 val = I915_READ(D_COMP);
7313 val |= D_COMP_COMP_DISABLE;
7314 hsw_write_dcomp(dev_priv, val);
7315 ndelay(100);
7316
7317 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7318 DRM_ERROR("D_COMP RCOMP still in progress\n");
7319
7320 if (allow_power_down) {
7321 val = I915_READ(LCPLL_CTL);
7322 val |= LCPLL_POWER_DOWN_ALLOW;
7323 I915_WRITE(LCPLL_CTL, val);
7324 POSTING_READ(LCPLL_CTL);
7325 }
7326 }
7327
7328 /*
7329 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7330 * source.
7331 */
7332 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7333 {
7334 uint32_t val;
7335 unsigned long irqflags;
7336
7337 val = I915_READ(LCPLL_CTL);
7338
7339 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7340 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7341 return;
7342
7343 /*
7344 * Make sure we're not on PC8 state before disabling PC8, otherwise
7345 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7346 *
7347 * The other problem is that hsw_restore_lcpll() is called as part of
7348 * the runtime PM resume sequence, so we can't just call
7349 * gen6_gt_force_wake_get() because that function calls
7350 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7351 * while we are on the resume sequence. So to solve this problem we have
7352 * to call special forcewake code that doesn't touch runtime PM and
7353 * doesn't enable the forcewake delayed work.
7354 */
7355 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7356 if (dev_priv->uncore.forcewake_count++ == 0)
7357 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7358 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7359
7360 if (val & LCPLL_POWER_DOWN_ALLOW) {
7361 val &= ~LCPLL_POWER_DOWN_ALLOW;
7362 I915_WRITE(LCPLL_CTL, val);
7363 POSTING_READ(LCPLL_CTL);
7364 }
7365
7366 val = I915_READ(D_COMP);
7367 val |= D_COMP_COMP_FORCE;
7368 val &= ~D_COMP_COMP_DISABLE;
7369 hsw_write_dcomp(dev_priv, val);
7370
7371 val = I915_READ(LCPLL_CTL);
7372 val &= ~LCPLL_PLL_DISABLE;
7373 I915_WRITE(LCPLL_CTL, val);
7374
7375 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7376 DRM_ERROR("LCPLL not locked yet\n");
7377
7378 if (val & LCPLL_CD_SOURCE_FCLK) {
7379 val = I915_READ(LCPLL_CTL);
7380 val &= ~LCPLL_CD_SOURCE_FCLK;
7381 I915_WRITE(LCPLL_CTL, val);
7382
7383 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7384 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7385 DRM_ERROR("Switching back to LCPLL failed\n");
7386 }
7387
7388 /* See the big comment above. */
7389 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7390 if (--dev_priv->uncore.forcewake_count == 0)
7391 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7392 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7393 }
7394
7395 /*
7396 * Package states C8 and deeper are really deep PC states that can only be
7397 * reached when all the devices on the system allow it, so even if the graphics
7398 * device allows PC8+, it doesn't mean the system will actually get to these
7399 * states. Our driver only allows PC8+ when going into runtime PM.
7400 *
7401 * The requirements for PC8+ are that all the outputs are disabled, the power
7402 * well is disabled and most interrupts are disabled, and these are also
7403 * requirements for runtime PM. When these conditions are met, we manually do
7404 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7405 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7406 * hang the machine.
7407 *
7408 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7409 * the state of some registers, so when we come back from PC8+ we need to
7410 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7411 * need to take care of the registers kept by RC6. Notice that this happens even
7412 * if we don't put the device in PCI D3 state (which is what currently happens
7413 * because of the runtime PM support).
7414 *
7415 * For more, read "Display Sequences for Package C8" on the hardware
7416 * documentation.
7417 */
7418 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7419 {
7420 struct drm_device *dev = dev_priv->dev;
7421 uint32_t val;
7422
7423 DRM_DEBUG_KMS("Enabling package C8+\n");
7424
7425 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7426 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7427 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7428 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7429 }
7430
7431 lpt_disable_clkout_dp(dev);
7432 hsw_disable_lcpll(dev_priv, true, true);
7433 }
7434
7435 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7436 {
7437 struct drm_device *dev = dev_priv->dev;
7438 uint32_t val;
7439
7440 DRM_DEBUG_KMS("Disabling package C8+\n");
7441
7442 hsw_restore_lcpll(dev_priv);
7443 lpt_init_pch_refclk(dev);
7444
7445 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7446 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7447 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7448 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7449 }
7450
7451 intel_prepare_ddi(dev);
7452 }
7453
7454 static void snb_modeset_global_resources(struct drm_device *dev)
7455 {
7456 modeset_update_crtc_power_domains(dev);
7457 }
7458
7459 static void haswell_modeset_global_resources(struct drm_device *dev)
7460 {
7461 modeset_update_crtc_power_domains(dev);
7462 }
7463
7464 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7465 int x, int y,
7466 struct drm_framebuffer *fb)
7467 {
7468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7469
7470 if (!intel_ddi_pll_select(intel_crtc))
7471 return -EINVAL;
7472 intel_ddi_pll_enable(intel_crtc);
7473
7474 intel_crtc->lowfreq_avail = false;
7475
7476 return 0;
7477 }
7478
7479 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7480 struct intel_crtc_config *pipe_config)
7481 {
7482 struct drm_device *dev = crtc->base.dev;
7483 struct drm_i915_private *dev_priv = dev->dev_private;
7484 enum intel_display_power_domain pfit_domain;
7485 uint32_t tmp;
7486
7487 if (!intel_display_power_enabled(dev_priv,
7488 POWER_DOMAIN_PIPE(crtc->pipe)))
7489 return false;
7490
7491 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7492 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7493
7494 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7495 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7496 enum pipe trans_edp_pipe;
7497 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7498 default:
7499 WARN(1, "unknown pipe linked to edp transcoder\n");
7500 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7501 case TRANS_DDI_EDP_INPUT_A_ON:
7502 trans_edp_pipe = PIPE_A;
7503 break;
7504 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7505 trans_edp_pipe = PIPE_B;
7506 break;
7507 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7508 trans_edp_pipe = PIPE_C;
7509 break;
7510 }
7511
7512 if (trans_edp_pipe == crtc->pipe)
7513 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7514 }
7515
7516 if (!intel_display_power_enabled(dev_priv,
7517 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7518 return false;
7519
7520 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7521 if (!(tmp & PIPECONF_ENABLE))
7522 return false;
7523
7524 /*
7525 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7526 * DDI E. So just check whether this pipe is wired to DDI E and whether
7527 * the PCH transcoder is on.
7528 */
7529 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7530 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7531 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7532 pipe_config->has_pch_encoder = true;
7533
7534 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7535 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7536 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7537
7538 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7539 }
7540
7541 intel_get_pipe_timings(crtc, pipe_config);
7542
7543 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7544 if (intel_display_power_enabled(dev_priv, pfit_domain))
7545 ironlake_get_pfit_config(crtc, pipe_config);
7546
7547 if (IS_HASWELL(dev))
7548 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7549 (I915_READ(IPS_CTL) & IPS_ENABLE);
7550
7551 pipe_config->pixel_multiplier = 1;
7552
7553 return true;
7554 }
7555
7556 static struct {
7557 int clock;
7558 u32 config;
7559 } hdmi_audio_clock[] = {
7560 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7561 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7562 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7563 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7564 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7565 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7566 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7567 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7568 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7569 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7570 };
7571
7572 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7573 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7574 {
7575 int i;
7576
7577 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7578 if (mode->clock == hdmi_audio_clock[i].clock)
7579 break;
7580 }
7581
7582 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7583 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7584 i = 1;
7585 }
7586
7587 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7588 hdmi_audio_clock[i].clock,
7589 hdmi_audio_clock[i].config);
7590
7591 return hdmi_audio_clock[i].config;
7592 }
7593
7594 static bool intel_eld_uptodate(struct drm_connector *connector,
7595 int reg_eldv, uint32_t bits_eldv,
7596 int reg_elda, uint32_t bits_elda,
7597 int reg_edid)
7598 {
7599 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7600 uint8_t *eld = connector->eld;
7601 uint32_t i;
7602
7603 i = I915_READ(reg_eldv);
7604 i &= bits_eldv;
7605
7606 if (!eld[0])
7607 return !i;
7608
7609 if (!i)
7610 return false;
7611
7612 i = I915_READ(reg_elda);
7613 i &= ~bits_elda;
7614 I915_WRITE(reg_elda, i);
7615
7616 for (i = 0; i < eld[2]; i++)
7617 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7618 return false;
7619
7620 return true;
7621 }
7622
7623 static void g4x_write_eld(struct drm_connector *connector,
7624 struct drm_crtc *crtc,
7625 struct drm_display_mode *mode)
7626 {
7627 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7628 uint8_t *eld = connector->eld;
7629 uint32_t eldv;
7630 uint32_t len;
7631 uint32_t i;
7632
7633 i = I915_READ(G4X_AUD_VID_DID);
7634
7635 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7636 eldv = G4X_ELDV_DEVCL_DEVBLC;
7637 else
7638 eldv = G4X_ELDV_DEVCTG;
7639
7640 if (intel_eld_uptodate(connector,
7641 G4X_AUD_CNTL_ST, eldv,
7642 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7643 G4X_HDMIW_HDMIEDID))
7644 return;
7645
7646 i = I915_READ(G4X_AUD_CNTL_ST);
7647 i &= ~(eldv | G4X_ELD_ADDR);
7648 len = (i >> 9) & 0x1f; /* ELD buffer size */
7649 I915_WRITE(G4X_AUD_CNTL_ST, i);
7650
7651 if (!eld[0])
7652 return;
7653
7654 len = min_t(uint8_t, eld[2], len);
7655 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7656 for (i = 0; i < len; i++)
7657 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7658
7659 i = I915_READ(G4X_AUD_CNTL_ST);
7660 i |= eldv;
7661 I915_WRITE(G4X_AUD_CNTL_ST, i);
7662 }
7663
7664 static void haswell_write_eld(struct drm_connector *connector,
7665 struct drm_crtc *crtc,
7666 struct drm_display_mode *mode)
7667 {
7668 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7669 uint8_t *eld = connector->eld;
7670 uint32_t eldv;
7671 uint32_t i;
7672 int len;
7673 int pipe = to_intel_crtc(crtc)->pipe;
7674 int tmp;
7675
7676 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7677 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7678 int aud_config = HSW_AUD_CFG(pipe);
7679 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7680
7681 /* Audio output enable */
7682 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7683 tmp = I915_READ(aud_cntrl_st2);
7684 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7685 I915_WRITE(aud_cntrl_st2, tmp);
7686 POSTING_READ(aud_cntrl_st2);
7687
7688 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7689
7690 /* Set ELD valid state */
7691 tmp = I915_READ(aud_cntrl_st2);
7692 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7693 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7694 I915_WRITE(aud_cntrl_st2, tmp);
7695 tmp = I915_READ(aud_cntrl_st2);
7696 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7697
7698 /* Enable HDMI mode */
7699 tmp = I915_READ(aud_config);
7700 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7701 /* clear N_programing_enable and N_value_index */
7702 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7703 I915_WRITE(aud_config, tmp);
7704
7705 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7706
7707 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7708
7709 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7710 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7711 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7712 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7713 } else {
7714 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7715 }
7716
7717 if (intel_eld_uptodate(connector,
7718 aud_cntrl_st2, eldv,
7719 aud_cntl_st, IBX_ELD_ADDRESS,
7720 hdmiw_hdmiedid))
7721 return;
7722
7723 i = I915_READ(aud_cntrl_st2);
7724 i &= ~eldv;
7725 I915_WRITE(aud_cntrl_st2, i);
7726
7727 if (!eld[0])
7728 return;
7729
7730 i = I915_READ(aud_cntl_st);
7731 i &= ~IBX_ELD_ADDRESS;
7732 I915_WRITE(aud_cntl_st, i);
7733 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7734 DRM_DEBUG_DRIVER("port num:%d\n", i);
7735
7736 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7737 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7738 for (i = 0; i < len; i++)
7739 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7740
7741 i = I915_READ(aud_cntrl_st2);
7742 i |= eldv;
7743 I915_WRITE(aud_cntrl_st2, i);
7744
7745 }
7746
7747 static void ironlake_write_eld(struct drm_connector *connector,
7748 struct drm_crtc *crtc,
7749 struct drm_display_mode *mode)
7750 {
7751 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7752 uint8_t *eld = connector->eld;
7753 uint32_t eldv;
7754 uint32_t i;
7755 int len;
7756 int hdmiw_hdmiedid;
7757 int aud_config;
7758 int aud_cntl_st;
7759 int aud_cntrl_st2;
7760 int pipe = to_intel_crtc(crtc)->pipe;
7761
7762 if (HAS_PCH_IBX(connector->dev)) {
7763 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7764 aud_config = IBX_AUD_CFG(pipe);
7765 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7766 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7767 } else if (IS_VALLEYVIEW(connector->dev)) {
7768 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7769 aud_config = VLV_AUD_CFG(pipe);
7770 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7771 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7772 } else {
7773 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7774 aud_config = CPT_AUD_CFG(pipe);
7775 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7776 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7777 }
7778
7779 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7780
7781 if (IS_VALLEYVIEW(connector->dev)) {
7782 struct intel_encoder *intel_encoder;
7783 struct intel_digital_port *intel_dig_port;
7784
7785 intel_encoder = intel_attached_encoder(connector);
7786 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7787 i = intel_dig_port->port;
7788 } else {
7789 i = I915_READ(aud_cntl_st);
7790 i = (i >> 29) & DIP_PORT_SEL_MASK;
7791 /* DIP_Port_Select, 0x1 = PortB */
7792 }
7793
7794 if (!i) {
7795 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7796 /* operate blindly on all ports */
7797 eldv = IBX_ELD_VALIDB;
7798 eldv |= IBX_ELD_VALIDB << 4;
7799 eldv |= IBX_ELD_VALIDB << 8;
7800 } else {
7801 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7802 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7803 }
7804
7805 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7806 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7807 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7808 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7809 } else {
7810 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7811 }
7812
7813 if (intel_eld_uptodate(connector,
7814 aud_cntrl_st2, eldv,
7815 aud_cntl_st, IBX_ELD_ADDRESS,
7816 hdmiw_hdmiedid))
7817 return;
7818
7819 i = I915_READ(aud_cntrl_st2);
7820 i &= ~eldv;
7821 I915_WRITE(aud_cntrl_st2, i);
7822
7823 if (!eld[0])
7824 return;
7825
7826 i = I915_READ(aud_cntl_st);
7827 i &= ~IBX_ELD_ADDRESS;
7828 I915_WRITE(aud_cntl_st, i);
7829
7830 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7831 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7832 for (i = 0; i < len; i++)
7833 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7834
7835 i = I915_READ(aud_cntrl_st2);
7836 i |= eldv;
7837 I915_WRITE(aud_cntrl_st2, i);
7838 }
7839
7840 void intel_write_eld(struct drm_encoder *encoder,
7841 struct drm_display_mode *mode)
7842 {
7843 struct drm_crtc *crtc = encoder->crtc;
7844 struct drm_connector *connector;
7845 struct drm_device *dev = encoder->dev;
7846 struct drm_i915_private *dev_priv = dev->dev_private;
7847
7848 connector = drm_select_eld(encoder, mode);
7849 if (!connector)
7850 return;
7851
7852 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7853 connector->base.id,
7854 connector->name,
7855 connector->encoder->base.id,
7856 connector->encoder->name);
7857
7858 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7859
7860 if (dev_priv->display.write_eld)
7861 dev_priv->display.write_eld(connector, crtc, mode);
7862 }
7863
7864 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7865 {
7866 struct drm_device *dev = crtc->dev;
7867 struct drm_i915_private *dev_priv = dev->dev_private;
7868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7869 uint32_t cntl;
7870
7871 if (base != intel_crtc->cursor_base) {
7872 /* On these chipsets we can only modify the base whilst
7873 * the cursor is disabled.
7874 */
7875 if (intel_crtc->cursor_cntl) {
7876 I915_WRITE(_CURACNTR, 0);
7877 POSTING_READ(_CURACNTR);
7878 intel_crtc->cursor_cntl = 0;
7879 }
7880
7881 I915_WRITE(_CURABASE, base);
7882 POSTING_READ(_CURABASE);
7883 }
7884
7885 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7886 cntl = 0;
7887 if (base)
7888 cntl = (CURSOR_ENABLE |
7889 CURSOR_GAMMA_ENABLE |
7890 CURSOR_FORMAT_ARGB);
7891 if (intel_crtc->cursor_cntl != cntl) {
7892 I915_WRITE(_CURACNTR, cntl);
7893 POSTING_READ(_CURACNTR);
7894 intel_crtc->cursor_cntl = cntl;
7895 }
7896 }
7897
7898 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7899 {
7900 struct drm_device *dev = crtc->dev;
7901 struct drm_i915_private *dev_priv = dev->dev_private;
7902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7903 int pipe = intel_crtc->pipe;
7904 uint32_t cntl;
7905
7906 cntl = 0;
7907 if (base) {
7908 cntl = MCURSOR_GAMMA_ENABLE;
7909 switch (intel_crtc->cursor_width) {
7910 case 64:
7911 cntl |= CURSOR_MODE_64_ARGB_AX;
7912 break;
7913 case 128:
7914 cntl |= CURSOR_MODE_128_ARGB_AX;
7915 break;
7916 case 256:
7917 cntl |= CURSOR_MODE_256_ARGB_AX;
7918 break;
7919 default:
7920 WARN_ON(1);
7921 return;
7922 }
7923 cntl |= pipe << 28; /* Connect to correct pipe */
7924 }
7925 if (intel_crtc->cursor_cntl != cntl) {
7926 I915_WRITE(CURCNTR(pipe), cntl);
7927 POSTING_READ(CURCNTR(pipe));
7928 intel_crtc->cursor_cntl = cntl;
7929 }
7930
7931 /* and commit changes on next vblank */
7932 I915_WRITE(CURBASE(pipe), base);
7933 POSTING_READ(CURBASE(pipe));
7934 }
7935
7936 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7937 {
7938 struct drm_device *dev = crtc->dev;
7939 struct drm_i915_private *dev_priv = dev->dev_private;
7940 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7941 int pipe = intel_crtc->pipe;
7942 uint32_t cntl;
7943
7944 cntl = 0;
7945 if (base) {
7946 cntl = MCURSOR_GAMMA_ENABLE;
7947 switch (intel_crtc->cursor_width) {
7948 case 64:
7949 cntl |= CURSOR_MODE_64_ARGB_AX;
7950 break;
7951 case 128:
7952 cntl |= CURSOR_MODE_128_ARGB_AX;
7953 break;
7954 case 256:
7955 cntl |= CURSOR_MODE_256_ARGB_AX;
7956 break;
7957 default:
7958 WARN_ON(1);
7959 return;
7960 }
7961 }
7962 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
7963 cntl |= CURSOR_PIPE_CSC_ENABLE;
7964
7965 if (intel_crtc->cursor_cntl != cntl) {
7966 I915_WRITE(CURCNTR(pipe), cntl);
7967 POSTING_READ(CURCNTR(pipe));
7968 intel_crtc->cursor_cntl = cntl;
7969 }
7970
7971 /* and commit changes on next vblank */
7972 I915_WRITE(CURBASE(pipe), base);
7973 POSTING_READ(CURBASE(pipe));
7974 }
7975
7976 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7977 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7978 bool on)
7979 {
7980 struct drm_device *dev = crtc->dev;
7981 struct drm_i915_private *dev_priv = dev->dev_private;
7982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7983 int pipe = intel_crtc->pipe;
7984 int x = intel_crtc->cursor_x;
7985 int y = intel_crtc->cursor_y;
7986 u32 base = 0, pos = 0;
7987
7988 if (on)
7989 base = intel_crtc->cursor_addr;
7990
7991 if (x >= intel_crtc->config.pipe_src_w)
7992 base = 0;
7993
7994 if (y >= intel_crtc->config.pipe_src_h)
7995 base = 0;
7996
7997 if (x < 0) {
7998 if (x + intel_crtc->cursor_width <= 0)
7999 base = 0;
8000
8001 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8002 x = -x;
8003 }
8004 pos |= x << CURSOR_X_SHIFT;
8005
8006 if (y < 0) {
8007 if (y + intel_crtc->cursor_height <= 0)
8008 base = 0;
8009
8010 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8011 y = -y;
8012 }
8013 pos |= y << CURSOR_Y_SHIFT;
8014
8015 if (base == 0 && intel_crtc->cursor_base == 0)
8016 return;
8017
8018 I915_WRITE(CURPOS(pipe), pos);
8019
8020 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8021 ivb_update_cursor(crtc, base);
8022 else if (IS_845G(dev) || IS_I865G(dev))
8023 i845_update_cursor(crtc, base);
8024 else
8025 i9xx_update_cursor(crtc, base);
8026 intel_crtc->cursor_base = base;
8027 }
8028
8029 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
8030 struct drm_file *file,
8031 uint32_t handle,
8032 uint32_t width, uint32_t height)
8033 {
8034 struct drm_device *dev = crtc->dev;
8035 struct drm_i915_private *dev_priv = dev->dev_private;
8036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8037 struct drm_i915_gem_object *obj;
8038 unsigned old_width;
8039 uint32_t addr;
8040 int ret;
8041
8042 /* if we want to turn off the cursor ignore width and height */
8043 if (!handle) {
8044 DRM_DEBUG_KMS("cursor off\n");
8045 addr = 0;
8046 obj = NULL;
8047 mutex_lock(&dev->struct_mutex);
8048 goto finish;
8049 }
8050
8051 /* Check for which cursor types we support */
8052 if (!((width == 64 && height == 64) ||
8053 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8054 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8055 DRM_DEBUG("Cursor dimension not supported\n");
8056 return -EINVAL;
8057 }
8058
8059 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
8060 if (&obj->base == NULL)
8061 return -ENOENT;
8062
8063 if (obj->base.size < width * height * 4) {
8064 DRM_DEBUG_KMS("buffer is to small\n");
8065 ret = -ENOMEM;
8066 goto fail;
8067 }
8068
8069 /* we only need to pin inside GTT if cursor is non-phy */
8070 mutex_lock(&dev->struct_mutex);
8071 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8072 unsigned alignment;
8073
8074 if (obj->tiling_mode) {
8075 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8076 ret = -EINVAL;
8077 goto fail_locked;
8078 }
8079
8080 /* Note that the w/a also requires 2 PTE of padding following
8081 * the bo. We currently fill all unused PTE with the shadow
8082 * page and so we should always have valid PTE following the
8083 * cursor preventing the VT-d warning.
8084 */
8085 alignment = 0;
8086 if (need_vtd_wa(dev))
8087 alignment = 64*1024;
8088
8089 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8090 if (ret) {
8091 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8092 goto fail_locked;
8093 }
8094
8095 ret = i915_gem_object_put_fence(obj);
8096 if (ret) {
8097 DRM_DEBUG_KMS("failed to release fence for cursor");
8098 goto fail_unpin;
8099 }
8100
8101 addr = i915_gem_obj_ggtt_offset(obj);
8102 } else {
8103 int align = IS_I830(dev) ? 16 * 1024 : 256;
8104 ret = i915_gem_object_attach_phys(obj, align);
8105 if (ret) {
8106 DRM_DEBUG_KMS("failed to attach phys object\n");
8107 goto fail_locked;
8108 }
8109 addr = obj->phys_handle->busaddr;
8110 }
8111
8112 if (IS_GEN2(dev))
8113 I915_WRITE(CURSIZE, (height << 12) | width);
8114
8115 finish:
8116 if (intel_crtc->cursor_bo) {
8117 if (!INTEL_INFO(dev)->cursor_needs_physical)
8118 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8119 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
8120 }
8121
8122 mutex_unlock(&dev->struct_mutex);
8123
8124 old_width = intel_crtc->cursor_width;
8125
8126 intel_crtc->cursor_addr = addr;
8127 intel_crtc->cursor_bo = obj;
8128 intel_crtc->cursor_width = width;
8129 intel_crtc->cursor_height = height;
8130
8131 if (intel_crtc->active) {
8132 if (old_width != width)
8133 intel_update_watermarks(crtc);
8134 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8135 }
8136
8137 return 0;
8138 fail_unpin:
8139 i915_gem_object_unpin_from_display_plane(obj);
8140 fail_locked:
8141 mutex_unlock(&dev->struct_mutex);
8142 fail:
8143 drm_gem_object_unreference_unlocked(&obj->base);
8144 return ret;
8145 }
8146
8147 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
8148 {
8149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8150
8151 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
8152 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
8153
8154 if (intel_crtc->active)
8155 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8156
8157 return 0;
8158 }
8159
8160 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8161 u16 *blue, uint32_t start, uint32_t size)
8162 {
8163 int end = (start + size > 256) ? 256 : start + size, i;
8164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8165
8166 for (i = start; i < end; i++) {
8167 intel_crtc->lut_r[i] = red[i] >> 8;
8168 intel_crtc->lut_g[i] = green[i] >> 8;
8169 intel_crtc->lut_b[i] = blue[i] >> 8;
8170 }
8171
8172 intel_crtc_load_lut(crtc);
8173 }
8174
8175 /* VESA 640x480x72Hz mode to set on the pipe */
8176 static struct drm_display_mode load_detect_mode = {
8177 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8178 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8179 };
8180
8181 struct drm_framebuffer *
8182 __intel_framebuffer_create(struct drm_device *dev,
8183 struct drm_mode_fb_cmd2 *mode_cmd,
8184 struct drm_i915_gem_object *obj)
8185 {
8186 struct intel_framebuffer *intel_fb;
8187 int ret;
8188
8189 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8190 if (!intel_fb) {
8191 drm_gem_object_unreference_unlocked(&obj->base);
8192 return ERR_PTR(-ENOMEM);
8193 }
8194
8195 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8196 if (ret)
8197 goto err;
8198
8199 return &intel_fb->base;
8200 err:
8201 drm_gem_object_unreference_unlocked(&obj->base);
8202 kfree(intel_fb);
8203
8204 return ERR_PTR(ret);
8205 }
8206
8207 static struct drm_framebuffer *
8208 intel_framebuffer_create(struct drm_device *dev,
8209 struct drm_mode_fb_cmd2 *mode_cmd,
8210 struct drm_i915_gem_object *obj)
8211 {
8212 struct drm_framebuffer *fb;
8213 int ret;
8214
8215 ret = i915_mutex_lock_interruptible(dev);
8216 if (ret)
8217 return ERR_PTR(ret);
8218 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8219 mutex_unlock(&dev->struct_mutex);
8220
8221 return fb;
8222 }
8223
8224 static u32
8225 intel_framebuffer_pitch_for_width(int width, int bpp)
8226 {
8227 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8228 return ALIGN(pitch, 64);
8229 }
8230
8231 static u32
8232 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8233 {
8234 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8235 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8236 }
8237
8238 static struct drm_framebuffer *
8239 intel_framebuffer_create_for_mode(struct drm_device *dev,
8240 struct drm_display_mode *mode,
8241 int depth, int bpp)
8242 {
8243 struct drm_i915_gem_object *obj;
8244 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8245
8246 obj = i915_gem_alloc_object(dev,
8247 intel_framebuffer_size_for_mode(mode, bpp));
8248 if (obj == NULL)
8249 return ERR_PTR(-ENOMEM);
8250
8251 mode_cmd.width = mode->hdisplay;
8252 mode_cmd.height = mode->vdisplay;
8253 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8254 bpp);
8255 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8256
8257 return intel_framebuffer_create(dev, &mode_cmd, obj);
8258 }
8259
8260 static struct drm_framebuffer *
8261 mode_fits_in_fbdev(struct drm_device *dev,
8262 struct drm_display_mode *mode)
8263 {
8264 #ifdef CONFIG_DRM_I915_FBDEV
8265 struct drm_i915_private *dev_priv = dev->dev_private;
8266 struct drm_i915_gem_object *obj;
8267 struct drm_framebuffer *fb;
8268
8269 if (!dev_priv->fbdev)
8270 return NULL;
8271
8272 if (!dev_priv->fbdev->fb)
8273 return NULL;
8274
8275 obj = dev_priv->fbdev->fb->obj;
8276 BUG_ON(!obj);
8277
8278 fb = &dev_priv->fbdev->fb->base;
8279 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8280 fb->bits_per_pixel))
8281 return NULL;
8282
8283 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8284 return NULL;
8285
8286 return fb;
8287 #else
8288 return NULL;
8289 #endif
8290 }
8291
8292 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8293 struct drm_display_mode *mode,
8294 struct intel_load_detect_pipe *old,
8295 struct drm_modeset_acquire_ctx *ctx)
8296 {
8297 struct intel_crtc *intel_crtc;
8298 struct intel_encoder *intel_encoder =
8299 intel_attached_encoder(connector);
8300 struct drm_crtc *possible_crtc;
8301 struct drm_encoder *encoder = &intel_encoder->base;
8302 struct drm_crtc *crtc = NULL;
8303 struct drm_device *dev = encoder->dev;
8304 struct drm_framebuffer *fb;
8305 struct drm_mode_config *config = &dev->mode_config;
8306 int ret, i = -1;
8307
8308 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8309 connector->base.id, connector->name,
8310 encoder->base.id, encoder->name);
8311
8312 drm_modeset_acquire_init(ctx, 0);
8313
8314 retry:
8315 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8316 if (ret)
8317 goto fail_unlock;
8318
8319 /*
8320 * Algorithm gets a little messy:
8321 *
8322 * - if the connector already has an assigned crtc, use it (but make
8323 * sure it's on first)
8324 *
8325 * - try to find the first unused crtc that can drive this connector,
8326 * and use that if we find one
8327 */
8328
8329 /* See if we already have a CRTC for this connector */
8330 if (encoder->crtc) {
8331 crtc = encoder->crtc;
8332
8333 ret = drm_modeset_lock(&crtc->mutex, ctx);
8334 if (ret)
8335 goto fail_unlock;
8336
8337 old->dpms_mode = connector->dpms;
8338 old->load_detect_temp = false;
8339
8340 /* Make sure the crtc and connector are running */
8341 if (connector->dpms != DRM_MODE_DPMS_ON)
8342 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8343
8344 return true;
8345 }
8346
8347 /* Find an unused one (if possible) */
8348 for_each_crtc(dev, possible_crtc) {
8349 i++;
8350 if (!(encoder->possible_crtcs & (1 << i)))
8351 continue;
8352 if (!possible_crtc->enabled) {
8353 crtc = possible_crtc;
8354 break;
8355 }
8356 }
8357
8358 /*
8359 * If we didn't find an unused CRTC, don't use any.
8360 */
8361 if (!crtc) {
8362 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8363 goto fail_unlock;
8364 }
8365
8366 ret = drm_modeset_lock(&crtc->mutex, ctx);
8367 if (ret)
8368 goto fail_unlock;
8369 intel_encoder->new_crtc = to_intel_crtc(crtc);
8370 to_intel_connector(connector)->new_encoder = intel_encoder;
8371
8372 intel_crtc = to_intel_crtc(crtc);
8373 intel_crtc->new_enabled = true;
8374 intel_crtc->new_config = &intel_crtc->config;
8375 old->dpms_mode = connector->dpms;
8376 old->load_detect_temp = true;
8377 old->release_fb = NULL;
8378
8379 if (!mode)
8380 mode = &load_detect_mode;
8381
8382 /* We need a framebuffer large enough to accommodate all accesses
8383 * that the plane may generate whilst we perform load detection.
8384 * We can not rely on the fbcon either being present (we get called
8385 * during its initialisation to detect all boot displays, or it may
8386 * not even exist) or that it is large enough to satisfy the
8387 * requested mode.
8388 */
8389 fb = mode_fits_in_fbdev(dev, mode);
8390 if (fb == NULL) {
8391 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8392 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8393 old->release_fb = fb;
8394 } else
8395 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8396 if (IS_ERR(fb)) {
8397 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8398 goto fail;
8399 }
8400
8401 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8402 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8403 if (old->release_fb)
8404 old->release_fb->funcs->destroy(old->release_fb);
8405 goto fail;
8406 }
8407
8408 /* let the connector get through one full cycle before testing */
8409 intel_wait_for_vblank(dev, intel_crtc->pipe);
8410 return true;
8411
8412 fail:
8413 intel_crtc->new_enabled = crtc->enabled;
8414 if (intel_crtc->new_enabled)
8415 intel_crtc->new_config = &intel_crtc->config;
8416 else
8417 intel_crtc->new_config = NULL;
8418 fail_unlock:
8419 if (ret == -EDEADLK) {
8420 drm_modeset_backoff(ctx);
8421 goto retry;
8422 }
8423
8424 drm_modeset_drop_locks(ctx);
8425 drm_modeset_acquire_fini(ctx);
8426
8427 return false;
8428 }
8429
8430 void intel_release_load_detect_pipe(struct drm_connector *connector,
8431 struct intel_load_detect_pipe *old,
8432 struct drm_modeset_acquire_ctx *ctx)
8433 {
8434 struct intel_encoder *intel_encoder =
8435 intel_attached_encoder(connector);
8436 struct drm_encoder *encoder = &intel_encoder->base;
8437 struct drm_crtc *crtc = encoder->crtc;
8438 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8439
8440 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8441 connector->base.id, connector->name,
8442 encoder->base.id, encoder->name);
8443
8444 if (old->load_detect_temp) {
8445 to_intel_connector(connector)->new_encoder = NULL;
8446 intel_encoder->new_crtc = NULL;
8447 intel_crtc->new_enabled = false;
8448 intel_crtc->new_config = NULL;
8449 intel_set_mode(crtc, NULL, 0, 0, NULL);
8450
8451 if (old->release_fb) {
8452 drm_framebuffer_unregister_private(old->release_fb);
8453 drm_framebuffer_unreference(old->release_fb);
8454 }
8455
8456 goto unlock;
8457 return;
8458 }
8459
8460 /* Switch crtc and encoder back off if necessary */
8461 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8462 connector->funcs->dpms(connector, old->dpms_mode);
8463
8464 unlock:
8465 drm_modeset_drop_locks(ctx);
8466 drm_modeset_acquire_fini(ctx);
8467 }
8468
8469 static int i9xx_pll_refclk(struct drm_device *dev,
8470 const struct intel_crtc_config *pipe_config)
8471 {
8472 struct drm_i915_private *dev_priv = dev->dev_private;
8473 u32 dpll = pipe_config->dpll_hw_state.dpll;
8474
8475 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8476 return dev_priv->vbt.lvds_ssc_freq;
8477 else if (HAS_PCH_SPLIT(dev))
8478 return 120000;
8479 else if (!IS_GEN2(dev))
8480 return 96000;
8481 else
8482 return 48000;
8483 }
8484
8485 /* Returns the clock of the currently programmed mode of the given pipe. */
8486 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8487 struct intel_crtc_config *pipe_config)
8488 {
8489 struct drm_device *dev = crtc->base.dev;
8490 struct drm_i915_private *dev_priv = dev->dev_private;
8491 int pipe = pipe_config->cpu_transcoder;
8492 u32 dpll = pipe_config->dpll_hw_state.dpll;
8493 u32 fp;
8494 intel_clock_t clock;
8495 int refclk = i9xx_pll_refclk(dev, pipe_config);
8496
8497 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8498 fp = pipe_config->dpll_hw_state.fp0;
8499 else
8500 fp = pipe_config->dpll_hw_state.fp1;
8501
8502 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8503 if (IS_PINEVIEW(dev)) {
8504 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8505 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8506 } else {
8507 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8508 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8509 }
8510
8511 if (!IS_GEN2(dev)) {
8512 if (IS_PINEVIEW(dev))
8513 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8514 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8515 else
8516 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8517 DPLL_FPA01_P1_POST_DIV_SHIFT);
8518
8519 switch (dpll & DPLL_MODE_MASK) {
8520 case DPLLB_MODE_DAC_SERIAL:
8521 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8522 5 : 10;
8523 break;
8524 case DPLLB_MODE_LVDS:
8525 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8526 7 : 14;
8527 break;
8528 default:
8529 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8530 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8531 return;
8532 }
8533
8534 if (IS_PINEVIEW(dev))
8535 pineview_clock(refclk, &clock);
8536 else
8537 i9xx_clock(refclk, &clock);
8538 } else {
8539 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8540 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8541
8542 if (is_lvds) {
8543 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8544 DPLL_FPA01_P1_POST_DIV_SHIFT);
8545
8546 if (lvds & LVDS_CLKB_POWER_UP)
8547 clock.p2 = 7;
8548 else
8549 clock.p2 = 14;
8550 } else {
8551 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8552 clock.p1 = 2;
8553 else {
8554 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8555 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8556 }
8557 if (dpll & PLL_P2_DIVIDE_BY_4)
8558 clock.p2 = 4;
8559 else
8560 clock.p2 = 2;
8561 }
8562
8563 i9xx_clock(refclk, &clock);
8564 }
8565
8566 /*
8567 * This value includes pixel_multiplier. We will use
8568 * port_clock to compute adjusted_mode.crtc_clock in the
8569 * encoder's get_config() function.
8570 */
8571 pipe_config->port_clock = clock.dot;
8572 }
8573
8574 int intel_dotclock_calculate(int link_freq,
8575 const struct intel_link_m_n *m_n)
8576 {
8577 /*
8578 * The calculation for the data clock is:
8579 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8580 * But we want to avoid losing precison if possible, so:
8581 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8582 *
8583 * and the link clock is simpler:
8584 * link_clock = (m * link_clock) / n
8585 */
8586
8587 if (!m_n->link_n)
8588 return 0;
8589
8590 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8591 }
8592
8593 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8594 struct intel_crtc_config *pipe_config)
8595 {
8596 struct drm_device *dev = crtc->base.dev;
8597
8598 /* read out port_clock from the DPLL */
8599 i9xx_crtc_clock_get(crtc, pipe_config);
8600
8601 /*
8602 * This value does not include pixel_multiplier.
8603 * We will check that port_clock and adjusted_mode.crtc_clock
8604 * agree once we know their relationship in the encoder's
8605 * get_config() function.
8606 */
8607 pipe_config->adjusted_mode.crtc_clock =
8608 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8609 &pipe_config->fdi_m_n);
8610 }
8611
8612 /** Returns the currently programmed mode of the given pipe. */
8613 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8614 struct drm_crtc *crtc)
8615 {
8616 struct drm_i915_private *dev_priv = dev->dev_private;
8617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8618 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8619 struct drm_display_mode *mode;
8620 struct intel_crtc_config pipe_config;
8621 int htot = I915_READ(HTOTAL(cpu_transcoder));
8622 int hsync = I915_READ(HSYNC(cpu_transcoder));
8623 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8624 int vsync = I915_READ(VSYNC(cpu_transcoder));
8625 enum pipe pipe = intel_crtc->pipe;
8626
8627 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8628 if (!mode)
8629 return NULL;
8630
8631 /*
8632 * Construct a pipe_config sufficient for getting the clock info
8633 * back out of crtc_clock_get.
8634 *
8635 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8636 * to use a real value here instead.
8637 */
8638 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8639 pipe_config.pixel_multiplier = 1;
8640 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8641 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8642 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8643 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8644
8645 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8646 mode->hdisplay = (htot & 0xffff) + 1;
8647 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8648 mode->hsync_start = (hsync & 0xffff) + 1;
8649 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8650 mode->vdisplay = (vtot & 0xffff) + 1;
8651 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8652 mode->vsync_start = (vsync & 0xffff) + 1;
8653 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8654
8655 drm_mode_set_name(mode);
8656
8657 return mode;
8658 }
8659
8660 static void intel_increase_pllclock(struct drm_crtc *crtc)
8661 {
8662 struct drm_device *dev = crtc->dev;
8663 struct drm_i915_private *dev_priv = dev->dev_private;
8664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8665 int pipe = intel_crtc->pipe;
8666 int dpll_reg = DPLL(pipe);
8667 int dpll;
8668
8669 if (HAS_PCH_SPLIT(dev))
8670 return;
8671
8672 if (!dev_priv->lvds_downclock_avail)
8673 return;
8674
8675 dpll = I915_READ(dpll_reg);
8676 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8677 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8678
8679 assert_panel_unlocked(dev_priv, pipe);
8680
8681 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8682 I915_WRITE(dpll_reg, dpll);
8683 intel_wait_for_vblank(dev, pipe);
8684
8685 dpll = I915_READ(dpll_reg);
8686 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8687 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8688 }
8689 }
8690
8691 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8692 {
8693 struct drm_device *dev = crtc->dev;
8694 struct drm_i915_private *dev_priv = dev->dev_private;
8695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8696
8697 if (HAS_PCH_SPLIT(dev))
8698 return;
8699
8700 if (!dev_priv->lvds_downclock_avail)
8701 return;
8702
8703 /*
8704 * Since this is called by a timer, we should never get here in
8705 * the manual case.
8706 */
8707 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8708 int pipe = intel_crtc->pipe;
8709 int dpll_reg = DPLL(pipe);
8710 int dpll;
8711
8712 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8713
8714 assert_panel_unlocked(dev_priv, pipe);
8715
8716 dpll = I915_READ(dpll_reg);
8717 dpll |= DISPLAY_RATE_SELECT_FPA1;
8718 I915_WRITE(dpll_reg, dpll);
8719 intel_wait_for_vblank(dev, pipe);
8720 dpll = I915_READ(dpll_reg);
8721 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8722 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8723 }
8724
8725 }
8726
8727 void intel_mark_busy(struct drm_device *dev)
8728 {
8729 struct drm_i915_private *dev_priv = dev->dev_private;
8730
8731 if (dev_priv->mm.busy)
8732 return;
8733
8734 intel_runtime_pm_get(dev_priv);
8735 i915_update_gfx_val(dev_priv);
8736 dev_priv->mm.busy = true;
8737 }
8738
8739 void intel_mark_idle(struct drm_device *dev)
8740 {
8741 struct drm_i915_private *dev_priv = dev->dev_private;
8742 struct drm_crtc *crtc;
8743
8744 if (!dev_priv->mm.busy)
8745 return;
8746
8747 dev_priv->mm.busy = false;
8748
8749 if (!i915.powersave)
8750 goto out;
8751
8752 for_each_crtc(dev, crtc) {
8753 if (!crtc->primary->fb)
8754 continue;
8755
8756 intel_decrease_pllclock(crtc);
8757 }
8758
8759 if (INTEL_INFO(dev)->gen >= 6)
8760 gen6_rps_idle(dev->dev_private);
8761
8762 out:
8763 intel_runtime_pm_put(dev_priv);
8764 }
8765
8766 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8767 struct intel_engine_cs *ring)
8768 {
8769 struct drm_device *dev = obj->base.dev;
8770 struct drm_crtc *crtc;
8771
8772 if (!i915.powersave)
8773 return;
8774
8775 for_each_crtc(dev, crtc) {
8776 if (!crtc->primary->fb)
8777 continue;
8778
8779 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8780 continue;
8781
8782 intel_increase_pllclock(crtc);
8783 if (ring && intel_fbc_enabled(dev))
8784 ring->fbc_dirty = true;
8785 }
8786 }
8787
8788 static void intel_crtc_destroy(struct drm_crtc *crtc)
8789 {
8790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8791 struct drm_device *dev = crtc->dev;
8792 struct intel_unpin_work *work;
8793 unsigned long flags;
8794
8795 spin_lock_irqsave(&dev->event_lock, flags);
8796 work = intel_crtc->unpin_work;
8797 intel_crtc->unpin_work = NULL;
8798 spin_unlock_irqrestore(&dev->event_lock, flags);
8799
8800 if (work) {
8801 cancel_work_sync(&work->work);
8802 kfree(work);
8803 }
8804
8805 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8806
8807 drm_crtc_cleanup(crtc);
8808
8809 kfree(intel_crtc);
8810 }
8811
8812 static void intel_unpin_work_fn(struct work_struct *__work)
8813 {
8814 struct intel_unpin_work *work =
8815 container_of(__work, struct intel_unpin_work, work);
8816 struct drm_device *dev = work->crtc->dev;
8817
8818 mutex_lock(&dev->struct_mutex);
8819 intel_unpin_fb_obj(work->old_fb_obj);
8820 drm_gem_object_unreference(&work->pending_flip_obj->base);
8821 drm_gem_object_unreference(&work->old_fb_obj->base);
8822
8823 intel_update_fbc(dev);
8824 mutex_unlock(&dev->struct_mutex);
8825
8826 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8827 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8828
8829 kfree(work);
8830 }
8831
8832 static void do_intel_finish_page_flip(struct drm_device *dev,
8833 struct drm_crtc *crtc)
8834 {
8835 struct drm_i915_private *dev_priv = dev->dev_private;
8836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8837 struct intel_unpin_work *work;
8838 unsigned long flags;
8839
8840 /* Ignore early vblank irqs */
8841 if (intel_crtc == NULL)
8842 return;
8843
8844 spin_lock_irqsave(&dev->event_lock, flags);
8845 work = intel_crtc->unpin_work;
8846
8847 /* Ensure we don't miss a work->pending update ... */
8848 smp_rmb();
8849
8850 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8851 spin_unlock_irqrestore(&dev->event_lock, flags);
8852 return;
8853 }
8854
8855 /* and that the unpin work is consistent wrt ->pending. */
8856 smp_rmb();
8857
8858 intel_crtc->unpin_work = NULL;
8859
8860 if (work->event)
8861 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8862
8863 drm_crtc_vblank_put(crtc);
8864
8865 spin_unlock_irqrestore(&dev->event_lock, flags);
8866
8867 wake_up_all(&dev_priv->pending_flip_queue);
8868
8869 queue_work(dev_priv->wq, &work->work);
8870
8871 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8872 }
8873
8874 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8875 {
8876 struct drm_i915_private *dev_priv = dev->dev_private;
8877 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8878
8879 do_intel_finish_page_flip(dev, crtc);
8880 }
8881
8882 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8883 {
8884 struct drm_i915_private *dev_priv = dev->dev_private;
8885 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8886
8887 do_intel_finish_page_flip(dev, crtc);
8888 }
8889
8890 /* Is 'a' after or equal to 'b'? */
8891 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8892 {
8893 return !((a - b) & 0x80000000);
8894 }
8895
8896 static bool page_flip_finished(struct intel_crtc *crtc)
8897 {
8898 struct drm_device *dev = crtc->base.dev;
8899 struct drm_i915_private *dev_priv = dev->dev_private;
8900
8901 /*
8902 * The relevant registers doen't exist on pre-ctg.
8903 * As the flip done interrupt doesn't trigger for mmio
8904 * flips on gmch platforms, a flip count check isn't
8905 * really needed there. But since ctg has the registers,
8906 * include it in the check anyway.
8907 */
8908 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8909 return true;
8910
8911 /*
8912 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8913 * used the same base address. In that case the mmio flip might
8914 * have completed, but the CS hasn't even executed the flip yet.
8915 *
8916 * A flip count check isn't enough as the CS might have updated
8917 * the base address just after start of vblank, but before we
8918 * managed to process the interrupt. This means we'd complete the
8919 * CS flip too soon.
8920 *
8921 * Combining both checks should get us a good enough result. It may
8922 * still happen that the CS flip has been executed, but has not
8923 * yet actually completed. But in case the base address is the same
8924 * anyway, we don't really care.
8925 */
8926 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8927 crtc->unpin_work->gtt_offset &&
8928 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8929 crtc->unpin_work->flip_count);
8930 }
8931
8932 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8933 {
8934 struct drm_i915_private *dev_priv = dev->dev_private;
8935 struct intel_crtc *intel_crtc =
8936 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8937 unsigned long flags;
8938
8939 /* NB: An MMIO update of the plane base pointer will also
8940 * generate a page-flip completion irq, i.e. every modeset
8941 * is also accompanied by a spurious intel_prepare_page_flip().
8942 */
8943 spin_lock_irqsave(&dev->event_lock, flags);
8944 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
8945 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8946 spin_unlock_irqrestore(&dev->event_lock, flags);
8947 }
8948
8949 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8950 {
8951 /* Ensure that the work item is consistent when activating it ... */
8952 smp_wmb();
8953 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8954 /* and that it is marked active as soon as the irq could fire. */
8955 smp_wmb();
8956 }
8957
8958 static int intel_gen2_queue_flip(struct drm_device *dev,
8959 struct drm_crtc *crtc,
8960 struct drm_framebuffer *fb,
8961 struct drm_i915_gem_object *obj,
8962 struct intel_engine_cs *ring,
8963 uint32_t flags)
8964 {
8965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8966 u32 flip_mask;
8967 int ret;
8968
8969 ret = intel_ring_begin(ring, 6);
8970 if (ret)
8971 return ret;
8972
8973 /* Can't queue multiple flips, so wait for the previous
8974 * one to finish before executing the next.
8975 */
8976 if (intel_crtc->plane)
8977 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8978 else
8979 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8980 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8981 intel_ring_emit(ring, MI_NOOP);
8982 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8983 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8984 intel_ring_emit(ring, fb->pitches[0]);
8985 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8986 intel_ring_emit(ring, 0); /* aux display base address, unused */
8987
8988 intel_mark_page_flip_active(intel_crtc);
8989 __intel_ring_advance(ring);
8990 return 0;
8991 }
8992
8993 static int intel_gen3_queue_flip(struct drm_device *dev,
8994 struct drm_crtc *crtc,
8995 struct drm_framebuffer *fb,
8996 struct drm_i915_gem_object *obj,
8997 struct intel_engine_cs *ring,
8998 uint32_t flags)
8999 {
9000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9001 u32 flip_mask;
9002 int ret;
9003
9004 ret = intel_ring_begin(ring, 6);
9005 if (ret)
9006 return ret;
9007
9008 if (intel_crtc->plane)
9009 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9010 else
9011 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9012 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9013 intel_ring_emit(ring, MI_NOOP);
9014 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9015 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9016 intel_ring_emit(ring, fb->pitches[0]);
9017 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9018 intel_ring_emit(ring, MI_NOOP);
9019
9020 intel_mark_page_flip_active(intel_crtc);
9021 __intel_ring_advance(ring);
9022 return 0;
9023 }
9024
9025 static int intel_gen4_queue_flip(struct drm_device *dev,
9026 struct drm_crtc *crtc,
9027 struct drm_framebuffer *fb,
9028 struct drm_i915_gem_object *obj,
9029 struct intel_engine_cs *ring,
9030 uint32_t flags)
9031 {
9032 struct drm_i915_private *dev_priv = dev->dev_private;
9033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9034 uint32_t pf, pipesrc;
9035 int ret;
9036
9037 ret = intel_ring_begin(ring, 4);
9038 if (ret)
9039 return ret;
9040
9041 /* i965+ uses the linear or tiled offsets from the
9042 * Display Registers (which do not change across a page-flip)
9043 * so we need only reprogram the base address.
9044 */
9045 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9046 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9047 intel_ring_emit(ring, fb->pitches[0]);
9048 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9049 obj->tiling_mode);
9050
9051 /* XXX Enabling the panel-fitter across page-flip is so far
9052 * untested on non-native modes, so ignore it for now.
9053 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9054 */
9055 pf = 0;
9056 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9057 intel_ring_emit(ring, pf | pipesrc);
9058
9059 intel_mark_page_flip_active(intel_crtc);
9060 __intel_ring_advance(ring);
9061 return 0;
9062 }
9063
9064 static int intel_gen6_queue_flip(struct drm_device *dev,
9065 struct drm_crtc *crtc,
9066 struct drm_framebuffer *fb,
9067 struct drm_i915_gem_object *obj,
9068 struct intel_engine_cs *ring,
9069 uint32_t flags)
9070 {
9071 struct drm_i915_private *dev_priv = dev->dev_private;
9072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9073 uint32_t pf, pipesrc;
9074 int ret;
9075
9076 ret = intel_ring_begin(ring, 4);
9077 if (ret)
9078 return ret;
9079
9080 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9081 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9082 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9083 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9084
9085 /* Contrary to the suggestions in the documentation,
9086 * "Enable Panel Fitter" does not seem to be required when page
9087 * flipping with a non-native mode, and worse causes a normal
9088 * modeset to fail.
9089 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9090 */
9091 pf = 0;
9092 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9093 intel_ring_emit(ring, pf | pipesrc);
9094
9095 intel_mark_page_flip_active(intel_crtc);
9096 __intel_ring_advance(ring);
9097 return 0;
9098 }
9099
9100 static int intel_gen7_queue_flip(struct drm_device *dev,
9101 struct drm_crtc *crtc,
9102 struct drm_framebuffer *fb,
9103 struct drm_i915_gem_object *obj,
9104 struct intel_engine_cs *ring,
9105 uint32_t flags)
9106 {
9107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9108 uint32_t plane_bit = 0;
9109 int len, ret;
9110
9111 switch (intel_crtc->plane) {
9112 case PLANE_A:
9113 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9114 break;
9115 case PLANE_B:
9116 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9117 break;
9118 case PLANE_C:
9119 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9120 break;
9121 default:
9122 WARN_ONCE(1, "unknown plane in flip command\n");
9123 return -ENODEV;
9124 }
9125
9126 len = 4;
9127 if (ring->id == RCS) {
9128 len += 6;
9129 /*
9130 * On Gen 8, SRM is now taking an extra dword to accommodate
9131 * 48bits addresses, and we need a NOOP for the batch size to
9132 * stay even.
9133 */
9134 if (IS_GEN8(dev))
9135 len += 2;
9136 }
9137
9138 /*
9139 * BSpec MI_DISPLAY_FLIP for IVB:
9140 * "The full packet must be contained within the same cache line."
9141 *
9142 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9143 * cacheline, if we ever start emitting more commands before
9144 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9145 * then do the cacheline alignment, and finally emit the
9146 * MI_DISPLAY_FLIP.
9147 */
9148 ret = intel_ring_cacheline_align(ring);
9149 if (ret)
9150 return ret;
9151
9152 ret = intel_ring_begin(ring, len);
9153 if (ret)
9154 return ret;
9155
9156 /* Unmask the flip-done completion message. Note that the bspec says that
9157 * we should do this for both the BCS and RCS, and that we must not unmask
9158 * more than one flip event at any time (or ensure that one flip message
9159 * can be sent by waiting for flip-done prior to queueing new flips).
9160 * Experimentation says that BCS works despite DERRMR masking all
9161 * flip-done completion events and that unmasking all planes at once
9162 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9163 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9164 */
9165 if (ring->id == RCS) {
9166 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9167 intel_ring_emit(ring, DERRMR);
9168 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9169 DERRMR_PIPEB_PRI_FLIP_DONE |
9170 DERRMR_PIPEC_PRI_FLIP_DONE));
9171 if (IS_GEN8(dev))
9172 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9173 MI_SRM_LRM_GLOBAL_GTT);
9174 else
9175 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9176 MI_SRM_LRM_GLOBAL_GTT);
9177 intel_ring_emit(ring, DERRMR);
9178 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9179 if (IS_GEN8(dev)) {
9180 intel_ring_emit(ring, 0);
9181 intel_ring_emit(ring, MI_NOOP);
9182 }
9183 }
9184
9185 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9186 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9187 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9188 intel_ring_emit(ring, (MI_NOOP));
9189
9190 intel_mark_page_flip_active(intel_crtc);
9191 __intel_ring_advance(ring);
9192 return 0;
9193 }
9194
9195 static int intel_default_queue_flip(struct drm_device *dev,
9196 struct drm_crtc *crtc,
9197 struct drm_framebuffer *fb,
9198 struct drm_i915_gem_object *obj,
9199 struct intel_engine_cs *ring,
9200 uint32_t flags)
9201 {
9202 return -ENODEV;
9203 }
9204
9205 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9206 struct drm_framebuffer *fb,
9207 struct drm_pending_vblank_event *event,
9208 uint32_t page_flip_flags)
9209 {
9210 struct drm_device *dev = crtc->dev;
9211 struct drm_i915_private *dev_priv = dev->dev_private;
9212 struct drm_framebuffer *old_fb = crtc->primary->fb;
9213 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9215 struct intel_unpin_work *work;
9216 struct intel_engine_cs *ring;
9217 unsigned long flags;
9218 int ret;
9219
9220 /* Can't change pixel format via MI display flips. */
9221 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9222 return -EINVAL;
9223
9224 /*
9225 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9226 * Note that pitch changes could also affect these register.
9227 */
9228 if (INTEL_INFO(dev)->gen > 3 &&
9229 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9230 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9231 return -EINVAL;
9232
9233 if (i915_terminally_wedged(&dev_priv->gpu_error))
9234 goto out_hang;
9235
9236 work = kzalloc(sizeof(*work), GFP_KERNEL);
9237 if (work == NULL)
9238 return -ENOMEM;
9239
9240 work->event = event;
9241 work->crtc = crtc;
9242 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9243 INIT_WORK(&work->work, intel_unpin_work_fn);
9244
9245 ret = drm_crtc_vblank_get(crtc);
9246 if (ret)
9247 goto free_work;
9248
9249 /* We borrow the event spin lock for protecting unpin_work */
9250 spin_lock_irqsave(&dev->event_lock, flags);
9251 if (intel_crtc->unpin_work) {
9252 spin_unlock_irqrestore(&dev->event_lock, flags);
9253 kfree(work);
9254 drm_crtc_vblank_put(crtc);
9255
9256 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9257 return -EBUSY;
9258 }
9259 intel_crtc->unpin_work = work;
9260 spin_unlock_irqrestore(&dev->event_lock, flags);
9261
9262 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9263 flush_workqueue(dev_priv->wq);
9264
9265 ret = i915_mutex_lock_interruptible(dev);
9266 if (ret)
9267 goto cleanup;
9268
9269 /* Reference the objects for the scheduled work. */
9270 drm_gem_object_reference(&work->old_fb_obj->base);
9271 drm_gem_object_reference(&obj->base);
9272
9273 crtc->primary->fb = fb;
9274
9275 work->pending_flip_obj = obj;
9276
9277 work->enable_stall_check = true;
9278
9279 atomic_inc(&intel_crtc->unpin_work_count);
9280 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9281
9282 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9283 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9284
9285 if (IS_VALLEYVIEW(dev)) {
9286 ring = &dev_priv->ring[BCS];
9287 } else if (INTEL_INFO(dev)->gen >= 7) {
9288 ring = obj->ring;
9289 if (ring == NULL || ring->id != RCS)
9290 ring = &dev_priv->ring[BCS];
9291 } else {
9292 ring = &dev_priv->ring[RCS];
9293 }
9294
9295 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9296 if (ret)
9297 goto cleanup_pending;
9298
9299 work->gtt_offset =
9300 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9301
9302 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags);
9303 if (ret)
9304 goto cleanup_unpin;
9305
9306 intel_disable_fbc(dev);
9307 intel_mark_fb_busy(obj, NULL);
9308 mutex_unlock(&dev->struct_mutex);
9309
9310 trace_i915_flip_request(intel_crtc->plane, obj);
9311
9312 return 0;
9313
9314 cleanup_unpin:
9315 intel_unpin_fb_obj(obj);
9316 cleanup_pending:
9317 atomic_dec(&intel_crtc->unpin_work_count);
9318 crtc->primary->fb = old_fb;
9319 drm_gem_object_unreference(&work->old_fb_obj->base);
9320 drm_gem_object_unreference(&obj->base);
9321 mutex_unlock(&dev->struct_mutex);
9322
9323 cleanup:
9324 spin_lock_irqsave(&dev->event_lock, flags);
9325 intel_crtc->unpin_work = NULL;
9326 spin_unlock_irqrestore(&dev->event_lock, flags);
9327
9328 drm_crtc_vblank_put(crtc);
9329 free_work:
9330 kfree(work);
9331
9332 if (ret == -EIO) {
9333 out_hang:
9334 intel_crtc_wait_for_pending_flips(crtc);
9335 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9336 if (ret == 0 && event)
9337 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9338 }
9339 return ret;
9340 }
9341
9342 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9343 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9344 .load_lut = intel_crtc_load_lut,
9345 };
9346
9347 /**
9348 * intel_modeset_update_staged_output_state
9349 *
9350 * Updates the staged output configuration state, e.g. after we've read out the
9351 * current hw state.
9352 */
9353 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9354 {
9355 struct intel_crtc *crtc;
9356 struct intel_encoder *encoder;
9357 struct intel_connector *connector;
9358
9359 list_for_each_entry(connector, &dev->mode_config.connector_list,
9360 base.head) {
9361 connector->new_encoder =
9362 to_intel_encoder(connector->base.encoder);
9363 }
9364
9365 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9366 base.head) {
9367 encoder->new_crtc =
9368 to_intel_crtc(encoder->base.crtc);
9369 }
9370
9371 for_each_intel_crtc(dev, crtc) {
9372 crtc->new_enabled = crtc->base.enabled;
9373
9374 if (crtc->new_enabled)
9375 crtc->new_config = &crtc->config;
9376 else
9377 crtc->new_config = NULL;
9378 }
9379 }
9380
9381 /**
9382 * intel_modeset_commit_output_state
9383 *
9384 * This function copies the stage display pipe configuration to the real one.
9385 */
9386 static void intel_modeset_commit_output_state(struct drm_device *dev)
9387 {
9388 struct intel_crtc *crtc;
9389 struct intel_encoder *encoder;
9390 struct intel_connector *connector;
9391
9392 list_for_each_entry(connector, &dev->mode_config.connector_list,
9393 base.head) {
9394 connector->base.encoder = &connector->new_encoder->base;
9395 }
9396
9397 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9398 base.head) {
9399 encoder->base.crtc = &encoder->new_crtc->base;
9400 }
9401
9402 for_each_intel_crtc(dev, crtc) {
9403 crtc->base.enabled = crtc->new_enabled;
9404 }
9405 }
9406
9407 static void
9408 connected_sink_compute_bpp(struct intel_connector *connector,
9409 struct intel_crtc_config *pipe_config)
9410 {
9411 int bpp = pipe_config->pipe_bpp;
9412
9413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9414 connector->base.base.id,
9415 connector->base.name);
9416
9417 /* Don't use an invalid EDID bpc value */
9418 if (connector->base.display_info.bpc &&
9419 connector->base.display_info.bpc * 3 < bpp) {
9420 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9421 bpp, connector->base.display_info.bpc*3);
9422 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9423 }
9424
9425 /* Clamp bpp to 8 on screens without EDID 1.4 */
9426 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9427 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9428 bpp);
9429 pipe_config->pipe_bpp = 24;
9430 }
9431 }
9432
9433 static int
9434 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9435 struct drm_framebuffer *fb,
9436 struct intel_crtc_config *pipe_config)
9437 {
9438 struct drm_device *dev = crtc->base.dev;
9439 struct intel_connector *connector;
9440 int bpp;
9441
9442 switch (fb->pixel_format) {
9443 case DRM_FORMAT_C8:
9444 bpp = 8*3; /* since we go through a colormap */
9445 break;
9446 case DRM_FORMAT_XRGB1555:
9447 case DRM_FORMAT_ARGB1555:
9448 /* checked in intel_framebuffer_init already */
9449 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9450 return -EINVAL;
9451 case DRM_FORMAT_RGB565:
9452 bpp = 6*3; /* min is 18bpp */
9453 break;
9454 case DRM_FORMAT_XBGR8888:
9455 case DRM_FORMAT_ABGR8888:
9456 /* checked in intel_framebuffer_init already */
9457 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9458 return -EINVAL;
9459 case DRM_FORMAT_XRGB8888:
9460 case DRM_FORMAT_ARGB8888:
9461 bpp = 8*3;
9462 break;
9463 case DRM_FORMAT_XRGB2101010:
9464 case DRM_FORMAT_ARGB2101010:
9465 case DRM_FORMAT_XBGR2101010:
9466 case DRM_FORMAT_ABGR2101010:
9467 /* checked in intel_framebuffer_init already */
9468 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9469 return -EINVAL;
9470 bpp = 10*3;
9471 break;
9472 /* TODO: gen4+ supports 16 bpc floating point, too. */
9473 default:
9474 DRM_DEBUG_KMS("unsupported depth\n");
9475 return -EINVAL;
9476 }
9477
9478 pipe_config->pipe_bpp = bpp;
9479
9480 /* Clamp display bpp to EDID value */
9481 list_for_each_entry(connector, &dev->mode_config.connector_list,
9482 base.head) {
9483 if (!connector->new_encoder ||
9484 connector->new_encoder->new_crtc != crtc)
9485 continue;
9486
9487 connected_sink_compute_bpp(connector, pipe_config);
9488 }
9489
9490 return bpp;
9491 }
9492
9493 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9494 {
9495 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9496 "type: 0x%x flags: 0x%x\n",
9497 mode->crtc_clock,
9498 mode->crtc_hdisplay, mode->crtc_hsync_start,
9499 mode->crtc_hsync_end, mode->crtc_htotal,
9500 mode->crtc_vdisplay, mode->crtc_vsync_start,
9501 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9502 }
9503
9504 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9505 struct intel_crtc_config *pipe_config,
9506 const char *context)
9507 {
9508 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9509 context, pipe_name(crtc->pipe));
9510
9511 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9512 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9513 pipe_config->pipe_bpp, pipe_config->dither);
9514 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9515 pipe_config->has_pch_encoder,
9516 pipe_config->fdi_lanes,
9517 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9518 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9519 pipe_config->fdi_m_n.tu);
9520 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9521 pipe_config->has_dp_encoder,
9522 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9523 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9524 pipe_config->dp_m_n.tu);
9525 DRM_DEBUG_KMS("requested mode:\n");
9526 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9527 DRM_DEBUG_KMS("adjusted mode:\n");
9528 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9529 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9530 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9531 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9532 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9533 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9534 pipe_config->gmch_pfit.control,
9535 pipe_config->gmch_pfit.pgm_ratios,
9536 pipe_config->gmch_pfit.lvds_border_bits);
9537 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9538 pipe_config->pch_pfit.pos,
9539 pipe_config->pch_pfit.size,
9540 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9541 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9542 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9543 }
9544
9545 static bool encoders_cloneable(const struct intel_encoder *a,
9546 const struct intel_encoder *b)
9547 {
9548 /* masks could be asymmetric, so check both ways */
9549 return a == b || (a->cloneable & (1 << b->type) &&
9550 b->cloneable & (1 << a->type));
9551 }
9552
9553 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9554 struct intel_encoder *encoder)
9555 {
9556 struct drm_device *dev = crtc->base.dev;
9557 struct intel_encoder *source_encoder;
9558
9559 list_for_each_entry(source_encoder,
9560 &dev->mode_config.encoder_list, base.head) {
9561 if (source_encoder->new_crtc != crtc)
9562 continue;
9563
9564 if (!encoders_cloneable(encoder, source_encoder))
9565 return false;
9566 }
9567
9568 return true;
9569 }
9570
9571 static bool check_encoder_cloning(struct intel_crtc *crtc)
9572 {
9573 struct drm_device *dev = crtc->base.dev;
9574 struct intel_encoder *encoder;
9575
9576 list_for_each_entry(encoder,
9577 &dev->mode_config.encoder_list, base.head) {
9578 if (encoder->new_crtc != crtc)
9579 continue;
9580
9581 if (!check_single_encoder_cloning(crtc, encoder))
9582 return false;
9583 }
9584
9585 return true;
9586 }
9587
9588 static struct intel_crtc_config *
9589 intel_modeset_pipe_config(struct drm_crtc *crtc,
9590 struct drm_framebuffer *fb,
9591 struct drm_display_mode *mode)
9592 {
9593 struct drm_device *dev = crtc->dev;
9594 struct intel_encoder *encoder;
9595 struct intel_crtc_config *pipe_config;
9596 int plane_bpp, ret = -EINVAL;
9597 bool retry = true;
9598
9599 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9600 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9601 return ERR_PTR(-EINVAL);
9602 }
9603
9604 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9605 if (!pipe_config)
9606 return ERR_PTR(-ENOMEM);
9607
9608 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9609 drm_mode_copy(&pipe_config->requested_mode, mode);
9610
9611 pipe_config->cpu_transcoder =
9612 (enum transcoder) to_intel_crtc(crtc)->pipe;
9613 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9614
9615 /*
9616 * Sanitize sync polarity flags based on requested ones. If neither
9617 * positive or negative polarity is requested, treat this as meaning
9618 * negative polarity.
9619 */
9620 if (!(pipe_config->adjusted_mode.flags &
9621 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9622 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9623
9624 if (!(pipe_config->adjusted_mode.flags &
9625 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9626 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9627
9628 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9629 * plane pixel format and any sink constraints into account. Returns the
9630 * source plane bpp so that dithering can be selected on mismatches
9631 * after encoders and crtc also have had their say. */
9632 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9633 fb, pipe_config);
9634 if (plane_bpp < 0)
9635 goto fail;
9636
9637 /*
9638 * Determine the real pipe dimensions. Note that stereo modes can
9639 * increase the actual pipe size due to the frame doubling and
9640 * insertion of additional space for blanks between the frame. This
9641 * is stored in the crtc timings. We use the requested mode to do this
9642 * computation to clearly distinguish it from the adjusted mode, which
9643 * can be changed by the connectors in the below retry loop.
9644 */
9645 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9646 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9647 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9648
9649 encoder_retry:
9650 /* Ensure the port clock defaults are reset when retrying. */
9651 pipe_config->port_clock = 0;
9652 pipe_config->pixel_multiplier = 1;
9653
9654 /* Fill in default crtc timings, allow encoders to overwrite them. */
9655 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9656
9657 /* Pass our mode to the connectors and the CRTC to give them a chance to
9658 * adjust it according to limitations or connector properties, and also
9659 * a chance to reject the mode entirely.
9660 */
9661 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9662 base.head) {
9663
9664 if (&encoder->new_crtc->base != crtc)
9665 continue;
9666
9667 if (!(encoder->compute_config(encoder, pipe_config))) {
9668 DRM_DEBUG_KMS("Encoder config failure\n");
9669 goto fail;
9670 }
9671 }
9672
9673 /* Set default port clock if not overwritten by the encoder. Needs to be
9674 * done afterwards in case the encoder adjusts the mode. */
9675 if (!pipe_config->port_clock)
9676 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9677 * pipe_config->pixel_multiplier;
9678
9679 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9680 if (ret < 0) {
9681 DRM_DEBUG_KMS("CRTC fixup failed\n");
9682 goto fail;
9683 }
9684
9685 if (ret == RETRY) {
9686 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9687 ret = -EINVAL;
9688 goto fail;
9689 }
9690
9691 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9692 retry = false;
9693 goto encoder_retry;
9694 }
9695
9696 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9697 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9698 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9699
9700 return pipe_config;
9701 fail:
9702 kfree(pipe_config);
9703 return ERR_PTR(ret);
9704 }
9705
9706 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9707 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9708 static void
9709 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9710 unsigned *prepare_pipes, unsigned *disable_pipes)
9711 {
9712 struct intel_crtc *intel_crtc;
9713 struct drm_device *dev = crtc->dev;
9714 struct intel_encoder *encoder;
9715 struct intel_connector *connector;
9716 struct drm_crtc *tmp_crtc;
9717
9718 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9719
9720 /* Check which crtcs have changed outputs connected to them, these need
9721 * to be part of the prepare_pipes mask. We don't (yet) support global
9722 * modeset across multiple crtcs, so modeset_pipes will only have one
9723 * bit set at most. */
9724 list_for_each_entry(connector, &dev->mode_config.connector_list,
9725 base.head) {
9726 if (connector->base.encoder == &connector->new_encoder->base)
9727 continue;
9728
9729 if (connector->base.encoder) {
9730 tmp_crtc = connector->base.encoder->crtc;
9731
9732 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9733 }
9734
9735 if (connector->new_encoder)
9736 *prepare_pipes |=
9737 1 << connector->new_encoder->new_crtc->pipe;
9738 }
9739
9740 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9741 base.head) {
9742 if (encoder->base.crtc == &encoder->new_crtc->base)
9743 continue;
9744
9745 if (encoder->base.crtc) {
9746 tmp_crtc = encoder->base.crtc;
9747
9748 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9749 }
9750
9751 if (encoder->new_crtc)
9752 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9753 }
9754
9755 /* Check for pipes that will be enabled/disabled ... */
9756 for_each_intel_crtc(dev, intel_crtc) {
9757 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9758 continue;
9759
9760 if (!intel_crtc->new_enabled)
9761 *disable_pipes |= 1 << intel_crtc->pipe;
9762 else
9763 *prepare_pipes |= 1 << intel_crtc->pipe;
9764 }
9765
9766
9767 /* set_mode is also used to update properties on life display pipes. */
9768 intel_crtc = to_intel_crtc(crtc);
9769 if (intel_crtc->new_enabled)
9770 *prepare_pipes |= 1 << intel_crtc->pipe;
9771
9772 /*
9773 * For simplicity do a full modeset on any pipe where the output routing
9774 * changed. We could be more clever, but that would require us to be
9775 * more careful with calling the relevant encoder->mode_set functions.
9776 */
9777 if (*prepare_pipes)
9778 *modeset_pipes = *prepare_pipes;
9779
9780 /* ... and mask these out. */
9781 *modeset_pipes &= ~(*disable_pipes);
9782 *prepare_pipes &= ~(*disable_pipes);
9783
9784 /*
9785 * HACK: We don't (yet) fully support global modesets. intel_set_config
9786 * obies this rule, but the modeset restore mode of
9787 * intel_modeset_setup_hw_state does not.
9788 */
9789 *modeset_pipes &= 1 << intel_crtc->pipe;
9790 *prepare_pipes &= 1 << intel_crtc->pipe;
9791
9792 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9793 *modeset_pipes, *prepare_pipes, *disable_pipes);
9794 }
9795
9796 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9797 {
9798 struct drm_encoder *encoder;
9799 struct drm_device *dev = crtc->dev;
9800
9801 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9802 if (encoder->crtc == crtc)
9803 return true;
9804
9805 return false;
9806 }
9807
9808 static void
9809 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9810 {
9811 struct intel_encoder *intel_encoder;
9812 struct intel_crtc *intel_crtc;
9813 struct drm_connector *connector;
9814
9815 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9816 base.head) {
9817 if (!intel_encoder->base.crtc)
9818 continue;
9819
9820 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9821
9822 if (prepare_pipes & (1 << intel_crtc->pipe))
9823 intel_encoder->connectors_active = false;
9824 }
9825
9826 intel_modeset_commit_output_state(dev);
9827
9828 /* Double check state. */
9829 for_each_intel_crtc(dev, intel_crtc) {
9830 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9831 WARN_ON(intel_crtc->new_config &&
9832 intel_crtc->new_config != &intel_crtc->config);
9833 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9834 }
9835
9836 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9837 if (!connector->encoder || !connector->encoder->crtc)
9838 continue;
9839
9840 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9841
9842 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9843 struct drm_property *dpms_property =
9844 dev->mode_config.dpms_property;
9845
9846 connector->dpms = DRM_MODE_DPMS_ON;
9847 drm_object_property_set_value(&connector->base,
9848 dpms_property,
9849 DRM_MODE_DPMS_ON);
9850
9851 intel_encoder = to_intel_encoder(connector->encoder);
9852 intel_encoder->connectors_active = true;
9853 }
9854 }
9855
9856 }
9857
9858 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9859 {
9860 int diff;
9861
9862 if (clock1 == clock2)
9863 return true;
9864
9865 if (!clock1 || !clock2)
9866 return false;
9867
9868 diff = abs(clock1 - clock2);
9869
9870 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9871 return true;
9872
9873 return false;
9874 }
9875
9876 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9877 list_for_each_entry((intel_crtc), \
9878 &(dev)->mode_config.crtc_list, \
9879 base.head) \
9880 if (mask & (1 <<(intel_crtc)->pipe))
9881
9882 static bool
9883 intel_pipe_config_compare(struct drm_device *dev,
9884 struct intel_crtc_config *current_config,
9885 struct intel_crtc_config *pipe_config)
9886 {
9887 #define PIPE_CONF_CHECK_X(name) \
9888 if (current_config->name != pipe_config->name) { \
9889 DRM_ERROR("mismatch in " #name " " \
9890 "(expected 0x%08x, found 0x%08x)\n", \
9891 current_config->name, \
9892 pipe_config->name); \
9893 return false; \
9894 }
9895
9896 #define PIPE_CONF_CHECK_I(name) \
9897 if (current_config->name != pipe_config->name) { \
9898 DRM_ERROR("mismatch in " #name " " \
9899 "(expected %i, found %i)\n", \
9900 current_config->name, \
9901 pipe_config->name); \
9902 return false; \
9903 }
9904
9905 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9906 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9907 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9908 "(expected %i, found %i)\n", \
9909 current_config->name & (mask), \
9910 pipe_config->name & (mask)); \
9911 return false; \
9912 }
9913
9914 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9915 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9916 DRM_ERROR("mismatch in " #name " " \
9917 "(expected %i, found %i)\n", \
9918 current_config->name, \
9919 pipe_config->name); \
9920 return false; \
9921 }
9922
9923 #define PIPE_CONF_QUIRK(quirk) \
9924 ((current_config->quirks | pipe_config->quirks) & (quirk))
9925
9926 PIPE_CONF_CHECK_I(cpu_transcoder);
9927
9928 PIPE_CONF_CHECK_I(has_pch_encoder);
9929 PIPE_CONF_CHECK_I(fdi_lanes);
9930 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9931 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9932 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9933 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9934 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9935
9936 PIPE_CONF_CHECK_I(has_dp_encoder);
9937 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9938 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9939 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9940 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9941 PIPE_CONF_CHECK_I(dp_m_n.tu);
9942
9943 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9944 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9945 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9946 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9947 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9948 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9949
9950 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9951 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9952 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9953 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9954 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9955 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9956
9957 PIPE_CONF_CHECK_I(pixel_multiplier);
9958 PIPE_CONF_CHECK_I(has_hdmi_sink);
9959 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
9960 IS_VALLEYVIEW(dev))
9961 PIPE_CONF_CHECK_I(limited_color_range);
9962
9963 PIPE_CONF_CHECK_I(has_audio);
9964
9965 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9966 DRM_MODE_FLAG_INTERLACE);
9967
9968 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9969 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9970 DRM_MODE_FLAG_PHSYNC);
9971 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9972 DRM_MODE_FLAG_NHSYNC);
9973 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9974 DRM_MODE_FLAG_PVSYNC);
9975 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9976 DRM_MODE_FLAG_NVSYNC);
9977 }
9978
9979 PIPE_CONF_CHECK_I(pipe_src_w);
9980 PIPE_CONF_CHECK_I(pipe_src_h);
9981
9982 /*
9983 * FIXME: BIOS likes to set up a cloned config with lvds+external
9984 * screen. Since we don't yet re-compute the pipe config when moving
9985 * just the lvds port away to another pipe the sw tracking won't match.
9986 *
9987 * Proper atomic modesets with recomputed global state will fix this.
9988 * Until then just don't check gmch state for inherited modes.
9989 */
9990 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
9991 PIPE_CONF_CHECK_I(gmch_pfit.control);
9992 /* pfit ratios are autocomputed by the hw on gen4+ */
9993 if (INTEL_INFO(dev)->gen < 4)
9994 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9995 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9996 }
9997
9998 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9999 if (current_config->pch_pfit.enabled) {
10000 PIPE_CONF_CHECK_I(pch_pfit.pos);
10001 PIPE_CONF_CHECK_I(pch_pfit.size);
10002 }
10003
10004 /* BDW+ don't expose a synchronous way to read the state */
10005 if (IS_HASWELL(dev))
10006 PIPE_CONF_CHECK_I(ips_enabled);
10007
10008 PIPE_CONF_CHECK_I(double_wide);
10009
10010 PIPE_CONF_CHECK_I(shared_dpll);
10011 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10012 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10013 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10014 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10015
10016 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10017 PIPE_CONF_CHECK_I(pipe_bpp);
10018
10019 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10020 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10021
10022 #undef PIPE_CONF_CHECK_X
10023 #undef PIPE_CONF_CHECK_I
10024 #undef PIPE_CONF_CHECK_FLAGS
10025 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10026 #undef PIPE_CONF_QUIRK
10027
10028 return true;
10029 }
10030
10031 static void
10032 check_connector_state(struct drm_device *dev)
10033 {
10034 struct intel_connector *connector;
10035
10036 list_for_each_entry(connector, &dev->mode_config.connector_list,
10037 base.head) {
10038 /* This also checks the encoder/connector hw state with the
10039 * ->get_hw_state callbacks. */
10040 intel_connector_check_state(connector);
10041
10042 WARN(&connector->new_encoder->base != connector->base.encoder,
10043 "connector's staged encoder doesn't match current encoder\n");
10044 }
10045 }
10046
10047 static void
10048 check_encoder_state(struct drm_device *dev)
10049 {
10050 struct intel_encoder *encoder;
10051 struct intel_connector *connector;
10052
10053 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10054 base.head) {
10055 bool enabled = false;
10056 bool active = false;
10057 enum pipe pipe, tracked_pipe;
10058
10059 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10060 encoder->base.base.id,
10061 encoder->base.name);
10062
10063 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10064 "encoder's stage crtc doesn't match current crtc\n");
10065 WARN(encoder->connectors_active && !encoder->base.crtc,
10066 "encoder's active_connectors set, but no crtc\n");
10067
10068 list_for_each_entry(connector, &dev->mode_config.connector_list,
10069 base.head) {
10070 if (connector->base.encoder != &encoder->base)
10071 continue;
10072 enabled = true;
10073 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10074 active = true;
10075 }
10076 WARN(!!encoder->base.crtc != enabled,
10077 "encoder's enabled state mismatch "
10078 "(expected %i, found %i)\n",
10079 !!encoder->base.crtc, enabled);
10080 WARN(active && !encoder->base.crtc,
10081 "active encoder with no crtc\n");
10082
10083 WARN(encoder->connectors_active != active,
10084 "encoder's computed active state doesn't match tracked active state "
10085 "(expected %i, found %i)\n", active, encoder->connectors_active);
10086
10087 active = encoder->get_hw_state(encoder, &pipe);
10088 WARN(active != encoder->connectors_active,
10089 "encoder's hw state doesn't match sw tracking "
10090 "(expected %i, found %i)\n",
10091 encoder->connectors_active, active);
10092
10093 if (!encoder->base.crtc)
10094 continue;
10095
10096 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10097 WARN(active && pipe != tracked_pipe,
10098 "active encoder's pipe doesn't match"
10099 "(expected %i, found %i)\n",
10100 tracked_pipe, pipe);
10101
10102 }
10103 }
10104
10105 static void
10106 check_crtc_state(struct drm_device *dev)
10107 {
10108 struct drm_i915_private *dev_priv = dev->dev_private;
10109 struct intel_crtc *crtc;
10110 struct intel_encoder *encoder;
10111 struct intel_crtc_config pipe_config;
10112
10113 for_each_intel_crtc(dev, crtc) {
10114 bool enabled = false;
10115 bool active = false;
10116
10117 memset(&pipe_config, 0, sizeof(pipe_config));
10118
10119 DRM_DEBUG_KMS("[CRTC:%d]\n",
10120 crtc->base.base.id);
10121
10122 WARN(crtc->active && !crtc->base.enabled,
10123 "active crtc, but not enabled in sw tracking\n");
10124
10125 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10126 base.head) {
10127 if (encoder->base.crtc != &crtc->base)
10128 continue;
10129 enabled = true;
10130 if (encoder->connectors_active)
10131 active = true;
10132 }
10133
10134 WARN(active != crtc->active,
10135 "crtc's computed active state doesn't match tracked active state "
10136 "(expected %i, found %i)\n", active, crtc->active);
10137 WARN(enabled != crtc->base.enabled,
10138 "crtc's computed enabled state doesn't match tracked enabled state "
10139 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10140
10141 active = dev_priv->display.get_pipe_config(crtc,
10142 &pipe_config);
10143
10144 /* hw state is inconsistent with the pipe A quirk */
10145 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10146 active = crtc->active;
10147
10148 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10149 base.head) {
10150 enum pipe pipe;
10151 if (encoder->base.crtc != &crtc->base)
10152 continue;
10153 if (encoder->get_hw_state(encoder, &pipe))
10154 encoder->get_config(encoder, &pipe_config);
10155 }
10156
10157 WARN(crtc->active != active,
10158 "crtc active state doesn't match with hw state "
10159 "(expected %i, found %i)\n", crtc->active, active);
10160
10161 if (active &&
10162 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10163 WARN(1, "pipe state doesn't match!\n");
10164 intel_dump_pipe_config(crtc, &pipe_config,
10165 "[hw state]");
10166 intel_dump_pipe_config(crtc, &crtc->config,
10167 "[sw state]");
10168 }
10169 }
10170 }
10171
10172 static void
10173 check_shared_dpll_state(struct drm_device *dev)
10174 {
10175 struct drm_i915_private *dev_priv = dev->dev_private;
10176 struct intel_crtc *crtc;
10177 struct intel_dpll_hw_state dpll_hw_state;
10178 int i;
10179
10180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10181 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10182 int enabled_crtcs = 0, active_crtcs = 0;
10183 bool active;
10184
10185 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10186
10187 DRM_DEBUG_KMS("%s\n", pll->name);
10188
10189 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10190
10191 WARN(pll->active > pll->refcount,
10192 "more active pll users than references: %i vs %i\n",
10193 pll->active, pll->refcount);
10194 WARN(pll->active && !pll->on,
10195 "pll in active use but not on in sw tracking\n");
10196 WARN(pll->on && !pll->active,
10197 "pll in on but not on in use in sw tracking\n");
10198 WARN(pll->on != active,
10199 "pll on state mismatch (expected %i, found %i)\n",
10200 pll->on, active);
10201
10202 for_each_intel_crtc(dev, crtc) {
10203 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10204 enabled_crtcs++;
10205 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10206 active_crtcs++;
10207 }
10208 WARN(pll->active != active_crtcs,
10209 "pll active crtcs mismatch (expected %i, found %i)\n",
10210 pll->active, active_crtcs);
10211 WARN(pll->refcount != enabled_crtcs,
10212 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10213 pll->refcount, enabled_crtcs);
10214
10215 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10216 sizeof(dpll_hw_state)),
10217 "pll hw state mismatch\n");
10218 }
10219 }
10220
10221 void
10222 intel_modeset_check_state(struct drm_device *dev)
10223 {
10224 check_connector_state(dev);
10225 check_encoder_state(dev);
10226 check_crtc_state(dev);
10227 check_shared_dpll_state(dev);
10228 }
10229
10230 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10231 int dotclock)
10232 {
10233 /*
10234 * FDI already provided one idea for the dotclock.
10235 * Yell if the encoder disagrees.
10236 */
10237 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10238 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10239 pipe_config->adjusted_mode.crtc_clock, dotclock);
10240 }
10241
10242 static void update_scanline_offset(struct intel_crtc *crtc)
10243 {
10244 struct drm_device *dev = crtc->base.dev;
10245
10246 /*
10247 * The scanline counter increments at the leading edge of hsync.
10248 *
10249 * On most platforms it starts counting from vtotal-1 on the
10250 * first active line. That means the scanline counter value is
10251 * always one less than what we would expect. Ie. just after
10252 * start of vblank, which also occurs at start of hsync (on the
10253 * last active line), the scanline counter will read vblank_start-1.
10254 *
10255 * On gen2 the scanline counter starts counting from 1 instead
10256 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10257 * to keep the value positive), instead of adding one.
10258 *
10259 * On HSW+ the behaviour of the scanline counter depends on the output
10260 * type. For DP ports it behaves like most other platforms, but on HDMI
10261 * there's an extra 1 line difference. So we need to add two instead of
10262 * one to the value.
10263 */
10264 if (IS_GEN2(dev)) {
10265 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10266 int vtotal;
10267
10268 vtotal = mode->crtc_vtotal;
10269 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10270 vtotal /= 2;
10271
10272 crtc->scanline_offset = vtotal - 1;
10273 } else if (HAS_DDI(dev) &&
10274 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10275 crtc->scanline_offset = 2;
10276 } else
10277 crtc->scanline_offset = 1;
10278 }
10279
10280 static int __intel_set_mode(struct drm_crtc *crtc,
10281 struct drm_display_mode *mode,
10282 int x, int y, struct drm_framebuffer *fb)
10283 {
10284 struct drm_device *dev = crtc->dev;
10285 struct drm_i915_private *dev_priv = dev->dev_private;
10286 struct drm_display_mode *saved_mode;
10287 struct intel_crtc_config *pipe_config = NULL;
10288 struct intel_crtc *intel_crtc;
10289 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10290 int ret = 0;
10291
10292 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10293 if (!saved_mode)
10294 return -ENOMEM;
10295
10296 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10297 &prepare_pipes, &disable_pipes);
10298
10299 *saved_mode = crtc->mode;
10300
10301 /* Hack: Because we don't (yet) support global modeset on multiple
10302 * crtcs, we don't keep track of the new mode for more than one crtc.
10303 * Hence simply check whether any bit is set in modeset_pipes in all the
10304 * pieces of code that are not yet converted to deal with mutliple crtcs
10305 * changing their mode at the same time. */
10306 if (modeset_pipes) {
10307 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10308 if (IS_ERR(pipe_config)) {
10309 ret = PTR_ERR(pipe_config);
10310 pipe_config = NULL;
10311
10312 goto out;
10313 }
10314 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10315 "[modeset]");
10316 to_intel_crtc(crtc)->new_config = pipe_config;
10317 }
10318
10319 /*
10320 * See if the config requires any additional preparation, e.g.
10321 * to adjust global state with pipes off. We need to do this
10322 * here so we can get the modeset_pipe updated config for the new
10323 * mode set on this crtc. For other crtcs we need to use the
10324 * adjusted_mode bits in the crtc directly.
10325 */
10326 if (IS_VALLEYVIEW(dev)) {
10327 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10328
10329 /* may have added more to prepare_pipes than we should */
10330 prepare_pipes &= ~disable_pipes;
10331 }
10332
10333 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10334 intel_crtc_disable(&intel_crtc->base);
10335
10336 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10337 if (intel_crtc->base.enabled)
10338 dev_priv->display.crtc_disable(&intel_crtc->base);
10339 }
10340
10341 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10342 * to set it here already despite that we pass it down the callchain.
10343 */
10344 if (modeset_pipes) {
10345 crtc->mode = *mode;
10346 /* mode_set/enable/disable functions rely on a correct pipe
10347 * config. */
10348 to_intel_crtc(crtc)->config = *pipe_config;
10349 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10350
10351 /*
10352 * Calculate and store various constants which
10353 * are later needed by vblank and swap-completion
10354 * timestamping. They are derived from true hwmode.
10355 */
10356 drm_calc_timestamping_constants(crtc,
10357 &pipe_config->adjusted_mode);
10358 }
10359
10360 /* Only after disabling all output pipelines that will be changed can we
10361 * update the the output configuration. */
10362 intel_modeset_update_state(dev, prepare_pipes);
10363
10364 if (dev_priv->display.modeset_global_resources)
10365 dev_priv->display.modeset_global_resources(dev);
10366
10367 /* Set up the DPLL and any encoders state that needs to adjust or depend
10368 * on the DPLL.
10369 */
10370 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10371 struct drm_framebuffer *old_fb;
10372
10373 mutex_lock(&dev->struct_mutex);
10374 ret = intel_pin_and_fence_fb_obj(dev,
10375 to_intel_framebuffer(fb)->obj,
10376 NULL);
10377 if (ret != 0) {
10378 DRM_ERROR("pin & fence failed\n");
10379 mutex_unlock(&dev->struct_mutex);
10380 goto done;
10381 }
10382 old_fb = crtc->primary->fb;
10383 if (old_fb)
10384 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10385 mutex_unlock(&dev->struct_mutex);
10386
10387 crtc->primary->fb = fb;
10388 crtc->x = x;
10389 crtc->y = y;
10390
10391 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10392 x, y, fb);
10393 if (ret)
10394 goto done;
10395 }
10396
10397 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10398 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10399 update_scanline_offset(intel_crtc);
10400
10401 dev_priv->display.crtc_enable(&intel_crtc->base);
10402 }
10403
10404 /* FIXME: add subpixel order */
10405 done:
10406 if (ret && crtc->enabled)
10407 crtc->mode = *saved_mode;
10408
10409 out:
10410 kfree(pipe_config);
10411 kfree(saved_mode);
10412 return ret;
10413 }
10414
10415 static int intel_set_mode(struct drm_crtc *crtc,
10416 struct drm_display_mode *mode,
10417 int x, int y, struct drm_framebuffer *fb)
10418 {
10419 int ret;
10420
10421 ret = __intel_set_mode(crtc, mode, x, y, fb);
10422
10423 if (ret == 0)
10424 intel_modeset_check_state(crtc->dev);
10425
10426 return ret;
10427 }
10428
10429 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10430 {
10431 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10432 }
10433
10434 #undef for_each_intel_crtc_masked
10435
10436 static void intel_set_config_free(struct intel_set_config *config)
10437 {
10438 if (!config)
10439 return;
10440
10441 kfree(config->save_connector_encoders);
10442 kfree(config->save_encoder_crtcs);
10443 kfree(config->save_crtc_enabled);
10444 kfree(config);
10445 }
10446
10447 static int intel_set_config_save_state(struct drm_device *dev,
10448 struct intel_set_config *config)
10449 {
10450 struct drm_crtc *crtc;
10451 struct drm_encoder *encoder;
10452 struct drm_connector *connector;
10453 int count;
10454
10455 config->save_crtc_enabled =
10456 kcalloc(dev->mode_config.num_crtc,
10457 sizeof(bool), GFP_KERNEL);
10458 if (!config->save_crtc_enabled)
10459 return -ENOMEM;
10460
10461 config->save_encoder_crtcs =
10462 kcalloc(dev->mode_config.num_encoder,
10463 sizeof(struct drm_crtc *), GFP_KERNEL);
10464 if (!config->save_encoder_crtcs)
10465 return -ENOMEM;
10466
10467 config->save_connector_encoders =
10468 kcalloc(dev->mode_config.num_connector,
10469 sizeof(struct drm_encoder *), GFP_KERNEL);
10470 if (!config->save_connector_encoders)
10471 return -ENOMEM;
10472
10473 /* Copy data. Note that driver private data is not affected.
10474 * Should anything bad happen only the expected state is
10475 * restored, not the drivers personal bookkeeping.
10476 */
10477 count = 0;
10478 for_each_crtc(dev, crtc) {
10479 config->save_crtc_enabled[count++] = crtc->enabled;
10480 }
10481
10482 count = 0;
10483 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10484 config->save_encoder_crtcs[count++] = encoder->crtc;
10485 }
10486
10487 count = 0;
10488 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10489 config->save_connector_encoders[count++] = connector->encoder;
10490 }
10491
10492 return 0;
10493 }
10494
10495 static void intel_set_config_restore_state(struct drm_device *dev,
10496 struct intel_set_config *config)
10497 {
10498 struct intel_crtc *crtc;
10499 struct intel_encoder *encoder;
10500 struct intel_connector *connector;
10501 int count;
10502
10503 count = 0;
10504 for_each_intel_crtc(dev, crtc) {
10505 crtc->new_enabled = config->save_crtc_enabled[count++];
10506
10507 if (crtc->new_enabled)
10508 crtc->new_config = &crtc->config;
10509 else
10510 crtc->new_config = NULL;
10511 }
10512
10513 count = 0;
10514 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10515 encoder->new_crtc =
10516 to_intel_crtc(config->save_encoder_crtcs[count++]);
10517 }
10518
10519 count = 0;
10520 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10521 connector->new_encoder =
10522 to_intel_encoder(config->save_connector_encoders[count++]);
10523 }
10524 }
10525
10526 static bool
10527 is_crtc_connector_off(struct drm_mode_set *set)
10528 {
10529 int i;
10530
10531 if (set->num_connectors == 0)
10532 return false;
10533
10534 if (WARN_ON(set->connectors == NULL))
10535 return false;
10536
10537 for (i = 0; i < set->num_connectors; i++)
10538 if (set->connectors[i]->encoder &&
10539 set->connectors[i]->encoder->crtc == set->crtc &&
10540 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10541 return true;
10542
10543 return false;
10544 }
10545
10546 static void
10547 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10548 struct intel_set_config *config)
10549 {
10550
10551 /* We should be able to check here if the fb has the same properties
10552 * and then just flip_or_move it */
10553 if (is_crtc_connector_off(set)) {
10554 config->mode_changed = true;
10555 } else if (set->crtc->primary->fb != set->fb) {
10556 /* If we have no fb then treat it as a full mode set */
10557 if (set->crtc->primary->fb == NULL) {
10558 struct intel_crtc *intel_crtc =
10559 to_intel_crtc(set->crtc);
10560
10561 if (intel_crtc->active && i915.fastboot) {
10562 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10563 config->fb_changed = true;
10564 } else {
10565 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10566 config->mode_changed = true;
10567 }
10568 } else if (set->fb == NULL) {
10569 config->mode_changed = true;
10570 } else if (set->fb->pixel_format !=
10571 set->crtc->primary->fb->pixel_format) {
10572 config->mode_changed = true;
10573 } else {
10574 config->fb_changed = true;
10575 }
10576 }
10577
10578 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10579 config->fb_changed = true;
10580
10581 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10582 DRM_DEBUG_KMS("modes are different, full mode set\n");
10583 drm_mode_debug_printmodeline(&set->crtc->mode);
10584 drm_mode_debug_printmodeline(set->mode);
10585 config->mode_changed = true;
10586 }
10587
10588 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10589 set->crtc->base.id, config->mode_changed, config->fb_changed);
10590 }
10591
10592 static int
10593 intel_modeset_stage_output_state(struct drm_device *dev,
10594 struct drm_mode_set *set,
10595 struct intel_set_config *config)
10596 {
10597 struct intel_connector *connector;
10598 struct intel_encoder *encoder;
10599 struct intel_crtc *crtc;
10600 int ro;
10601
10602 /* The upper layers ensure that we either disable a crtc or have a list
10603 * of connectors. For paranoia, double-check this. */
10604 WARN_ON(!set->fb && (set->num_connectors != 0));
10605 WARN_ON(set->fb && (set->num_connectors == 0));
10606
10607 list_for_each_entry(connector, &dev->mode_config.connector_list,
10608 base.head) {
10609 /* Otherwise traverse passed in connector list and get encoders
10610 * for them. */
10611 for (ro = 0; ro < set->num_connectors; ro++) {
10612 if (set->connectors[ro] == &connector->base) {
10613 connector->new_encoder = connector->encoder;
10614 break;
10615 }
10616 }
10617
10618 /* If we disable the crtc, disable all its connectors. Also, if
10619 * the connector is on the changing crtc but not on the new
10620 * connector list, disable it. */
10621 if ((!set->fb || ro == set->num_connectors) &&
10622 connector->base.encoder &&
10623 connector->base.encoder->crtc == set->crtc) {
10624 connector->new_encoder = NULL;
10625
10626 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10627 connector->base.base.id,
10628 connector->base.name);
10629 }
10630
10631
10632 if (&connector->new_encoder->base != connector->base.encoder) {
10633 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10634 config->mode_changed = true;
10635 }
10636 }
10637 /* connector->new_encoder is now updated for all connectors. */
10638
10639 /* Update crtc of enabled connectors. */
10640 list_for_each_entry(connector, &dev->mode_config.connector_list,
10641 base.head) {
10642 struct drm_crtc *new_crtc;
10643
10644 if (!connector->new_encoder)
10645 continue;
10646
10647 new_crtc = connector->new_encoder->base.crtc;
10648
10649 for (ro = 0; ro < set->num_connectors; ro++) {
10650 if (set->connectors[ro] == &connector->base)
10651 new_crtc = set->crtc;
10652 }
10653
10654 /* Make sure the new CRTC will work with the encoder */
10655 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10656 new_crtc)) {
10657 return -EINVAL;
10658 }
10659 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10660
10661 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10662 connector->base.base.id,
10663 connector->base.name,
10664 new_crtc->base.id);
10665 }
10666
10667 /* Check for any encoders that needs to be disabled. */
10668 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10669 base.head) {
10670 int num_connectors = 0;
10671 list_for_each_entry(connector,
10672 &dev->mode_config.connector_list,
10673 base.head) {
10674 if (connector->new_encoder == encoder) {
10675 WARN_ON(!connector->new_encoder->new_crtc);
10676 num_connectors++;
10677 }
10678 }
10679
10680 if (num_connectors == 0)
10681 encoder->new_crtc = NULL;
10682 else if (num_connectors > 1)
10683 return -EINVAL;
10684
10685 /* Only now check for crtc changes so we don't miss encoders
10686 * that will be disabled. */
10687 if (&encoder->new_crtc->base != encoder->base.crtc) {
10688 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10689 config->mode_changed = true;
10690 }
10691 }
10692 /* Now we've also updated encoder->new_crtc for all encoders. */
10693
10694 for_each_intel_crtc(dev, crtc) {
10695 crtc->new_enabled = false;
10696
10697 list_for_each_entry(encoder,
10698 &dev->mode_config.encoder_list,
10699 base.head) {
10700 if (encoder->new_crtc == crtc) {
10701 crtc->new_enabled = true;
10702 break;
10703 }
10704 }
10705
10706 if (crtc->new_enabled != crtc->base.enabled) {
10707 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10708 crtc->new_enabled ? "en" : "dis");
10709 config->mode_changed = true;
10710 }
10711
10712 if (crtc->new_enabled)
10713 crtc->new_config = &crtc->config;
10714 else
10715 crtc->new_config = NULL;
10716 }
10717
10718 return 0;
10719 }
10720
10721 static void disable_crtc_nofb(struct intel_crtc *crtc)
10722 {
10723 struct drm_device *dev = crtc->base.dev;
10724 struct intel_encoder *encoder;
10725 struct intel_connector *connector;
10726
10727 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10728 pipe_name(crtc->pipe));
10729
10730 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10731 if (connector->new_encoder &&
10732 connector->new_encoder->new_crtc == crtc)
10733 connector->new_encoder = NULL;
10734 }
10735
10736 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10737 if (encoder->new_crtc == crtc)
10738 encoder->new_crtc = NULL;
10739 }
10740
10741 crtc->new_enabled = false;
10742 crtc->new_config = NULL;
10743 }
10744
10745 static int intel_crtc_set_config(struct drm_mode_set *set)
10746 {
10747 struct drm_device *dev;
10748 struct drm_mode_set save_set;
10749 struct intel_set_config *config;
10750 int ret;
10751
10752 BUG_ON(!set);
10753 BUG_ON(!set->crtc);
10754 BUG_ON(!set->crtc->helper_private);
10755
10756 /* Enforce sane interface api - has been abused by the fb helper. */
10757 BUG_ON(!set->mode && set->fb);
10758 BUG_ON(set->fb && set->num_connectors == 0);
10759
10760 if (set->fb) {
10761 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10762 set->crtc->base.id, set->fb->base.id,
10763 (int)set->num_connectors, set->x, set->y);
10764 } else {
10765 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10766 }
10767
10768 dev = set->crtc->dev;
10769
10770 ret = -ENOMEM;
10771 config = kzalloc(sizeof(*config), GFP_KERNEL);
10772 if (!config)
10773 goto out_config;
10774
10775 ret = intel_set_config_save_state(dev, config);
10776 if (ret)
10777 goto out_config;
10778
10779 save_set.crtc = set->crtc;
10780 save_set.mode = &set->crtc->mode;
10781 save_set.x = set->crtc->x;
10782 save_set.y = set->crtc->y;
10783 save_set.fb = set->crtc->primary->fb;
10784
10785 /* Compute whether we need a full modeset, only an fb base update or no
10786 * change at all. In the future we might also check whether only the
10787 * mode changed, e.g. for LVDS where we only change the panel fitter in
10788 * such cases. */
10789 intel_set_config_compute_mode_changes(set, config);
10790
10791 ret = intel_modeset_stage_output_state(dev, set, config);
10792 if (ret)
10793 goto fail;
10794
10795 if (config->mode_changed) {
10796 ret = intel_set_mode(set->crtc, set->mode,
10797 set->x, set->y, set->fb);
10798 } else if (config->fb_changed) {
10799 intel_crtc_wait_for_pending_flips(set->crtc);
10800
10801 ret = intel_pipe_set_base(set->crtc,
10802 set->x, set->y, set->fb);
10803 /*
10804 * In the fastboot case this may be our only check of the
10805 * state after boot. It would be better to only do it on
10806 * the first update, but we don't have a nice way of doing that
10807 * (and really, set_config isn't used much for high freq page
10808 * flipping, so increasing its cost here shouldn't be a big
10809 * deal).
10810 */
10811 if (i915.fastboot && ret == 0)
10812 intel_modeset_check_state(set->crtc->dev);
10813 }
10814
10815 if (ret) {
10816 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10817 set->crtc->base.id, ret);
10818 fail:
10819 intel_set_config_restore_state(dev, config);
10820
10821 /*
10822 * HACK: if the pipe was on, but we didn't have a framebuffer,
10823 * force the pipe off to avoid oopsing in the modeset code
10824 * due to fb==NULL. This should only happen during boot since
10825 * we don't yet reconstruct the FB from the hardware state.
10826 */
10827 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10828 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10829
10830 /* Try to restore the config */
10831 if (config->mode_changed &&
10832 intel_set_mode(save_set.crtc, save_set.mode,
10833 save_set.x, save_set.y, save_set.fb))
10834 DRM_ERROR("failed to restore config after modeset failure\n");
10835 }
10836
10837 out_config:
10838 intel_set_config_free(config);
10839 return ret;
10840 }
10841
10842 static const struct drm_crtc_funcs intel_crtc_funcs = {
10843 .cursor_set = intel_crtc_cursor_set,
10844 .cursor_move = intel_crtc_cursor_move,
10845 .gamma_set = intel_crtc_gamma_set,
10846 .set_config = intel_crtc_set_config,
10847 .destroy = intel_crtc_destroy,
10848 .page_flip = intel_crtc_page_flip,
10849 };
10850
10851 static void intel_cpu_pll_init(struct drm_device *dev)
10852 {
10853 if (HAS_DDI(dev))
10854 intel_ddi_pll_init(dev);
10855 }
10856
10857 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10858 struct intel_shared_dpll *pll,
10859 struct intel_dpll_hw_state *hw_state)
10860 {
10861 uint32_t val;
10862
10863 val = I915_READ(PCH_DPLL(pll->id));
10864 hw_state->dpll = val;
10865 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10866 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10867
10868 return val & DPLL_VCO_ENABLE;
10869 }
10870
10871 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10872 struct intel_shared_dpll *pll)
10873 {
10874 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10875 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10876 }
10877
10878 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10879 struct intel_shared_dpll *pll)
10880 {
10881 /* PCH refclock must be enabled first */
10882 ibx_assert_pch_refclk_enabled(dev_priv);
10883
10884 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10885
10886 /* Wait for the clocks to stabilize. */
10887 POSTING_READ(PCH_DPLL(pll->id));
10888 udelay(150);
10889
10890 /* The pixel multiplier can only be updated once the
10891 * DPLL is enabled and the clocks are stable.
10892 *
10893 * So write it again.
10894 */
10895 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10896 POSTING_READ(PCH_DPLL(pll->id));
10897 udelay(200);
10898 }
10899
10900 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10901 struct intel_shared_dpll *pll)
10902 {
10903 struct drm_device *dev = dev_priv->dev;
10904 struct intel_crtc *crtc;
10905
10906 /* Make sure no transcoder isn't still depending on us. */
10907 for_each_intel_crtc(dev, crtc) {
10908 if (intel_crtc_to_shared_dpll(crtc) == pll)
10909 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10910 }
10911
10912 I915_WRITE(PCH_DPLL(pll->id), 0);
10913 POSTING_READ(PCH_DPLL(pll->id));
10914 udelay(200);
10915 }
10916
10917 static char *ibx_pch_dpll_names[] = {
10918 "PCH DPLL A",
10919 "PCH DPLL B",
10920 };
10921
10922 static void ibx_pch_dpll_init(struct drm_device *dev)
10923 {
10924 struct drm_i915_private *dev_priv = dev->dev_private;
10925 int i;
10926
10927 dev_priv->num_shared_dpll = 2;
10928
10929 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10930 dev_priv->shared_dplls[i].id = i;
10931 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10932 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10933 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10934 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10935 dev_priv->shared_dplls[i].get_hw_state =
10936 ibx_pch_dpll_get_hw_state;
10937 }
10938 }
10939
10940 static void intel_shared_dpll_init(struct drm_device *dev)
10941 {
10942 struct drm_i915_private *dev_priv = dev->dev_private;
10943
10944 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10945 ibx_pch_dpll_init(dev);
10946 else
10947 dev_priv->num_shared_dpll = 0;
10948
10949 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10950 }
10951
10952 static void intel_crtc_init(struct drm_device *dev, int pipe)
10953 {
10954 struct drm_i915_private *dev_priv = dev->dev_private;
10955 struct intel_crtc *intel_crtc;
10956 int i;
10957
10958 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10959 if (intel_crtc == NULL)
10960 return;
10961
10962 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10963
10964 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10965 for (i = 0; i < 256; i++) {
10966 intel_crtc->lut_r[i] = i;
10967 intel_crtc->lut_g[i] = i;
10968 intel_crtc->lut_b[i] = i;
10969 }
10970
10971 /*
10972 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10973 * is hooked to plane B. Hence we want plane A feeding pipe B.
10974 */
10975 intel_crtc->pipe = pipe;
10976 intel_crtc->plane = pipe;
10977 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
10978 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10979 intel_crtc->plane = !pipe;
10980 }
10981
10982 intel_crtc->cursor_base = ~0;
10983 intel_crtc->cursor_cntl = ~0;
10984
10985 init_waitqueue_head(&intel_crtc->vbl_wait);
10986
10987 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10988 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10989 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10990 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10991
10992 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10993
10994 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
10995 }
10996
10997 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10998 {
10999 struct drm_encoder *encoder = connector->base.encoder;
11000 struct drm_device *dev = connector->base.dev;
11001
11002 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11003
11004 if (!encoder)
11005 return INVALID_PIPE;
11006
11007 return to_intel_crtc(encoder->crtc)->pipe;
11008 }
11009
11010 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11011 struct drm_file *file)
11012 {
11013 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11014 struct drm_mode_object *drmmode_obj;
11015 struct intel_crtc *crtc;
11016
11017 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11018 return -ENODEV;
11019
11020 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11021 DRM_MODE_OBJECT_CRTC);
11022
11023 if (!drmmode_obj) {
11024 DRM_ERROR("no such CRTC id\n");
11025 return -ENOENT;
11026 }
11027
11028 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11029 pipe_from_crtc_id->pipe = crtc->pipe;
11030
11031 return 0;
11032 }
11033
11034 static int intel_encoder_clones(struct intel_encoder *encoder)
11035 {
11036 struct drm_device *dev = encoder->base.dev;
11037 struct intel_encoder *source_encoder;
11038 int index_mask = 0;
11039 int entry = 0;
11040
11041 list_for_each_entry(source_encoder,
11042 &dev->mode_config.encoder_list, base.head) {
11043 if (encoders_cloneable(encoder, source_encoder))
11044 index_mask |= (1 << entry);
11045
11046 entry++;
11047 }
11048
11049 return index_mask;
11050 }
11051
11052 static bool has_edp_a(struct drm_device *dev)
11053 {
11054 struct drm_i915_private *dev_priv = dev->dev_private;
11055
11056 if (!IS_MOBILE(dev))
11057 return false;
11058
11059 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11060 return false;
11061
11062 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11063 return false;
11064
11065 return true;
11066 }
11067
11068 const char *intel_output_name(int output)
11069 {
11070 static const char *names[] = {
11071 [INTEL_OUTPUT_UNUSED] = "Unused",
11072 [INTEL_OUTPUT_ANALOG] = "Analog",
11073 [INTEL_OUTPUT_DVO] = "DVO",
11074 [INTEL_OUTPUT_SDVO] = "SDVO",
11075 [INTEL_OUTPUT_LVDS] = "LVDS",
11076 [INTEL_OUTPUT_TVOUT] = "TV",
11077 [INTEL_OUTPUT_HDMI] = "HDMI",
11078 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11079 [INTEL_OUTPUT_EDP] = "eDP",
11080 [INTEL_OUTPUT_DSI] = "DSI",
11081 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11082 };
11083
11084 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11085 return "Invalid";
11086
11087 return names[output];
11088 }
11089
11090 static void intel_setup_outputs(struct drm_device *dev)
11091 {
11092 struct drm_i915_private *dev_priv = dev->dev_private;
11093 struct intel_encoder *encoder;
11094 bool dpd_is_edp = false;
11095
11096 intel_lvds_init(dev);
11097
11098 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
11099 intel_crt_init(dev);
11100
11101 if (HAS_DDI(dev)) {
11102 int found;
11103
11104 /* Haswell uses DDI functions to detect digital outputs */
11105 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11106 /* DDI A only supports eDP */
11107 if (found)
11108 intel_ddi_init(dev, PORT_A);
11109
11110 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11111 * register */
11112 found = I915_READ(SFUSE_STRAP);
11113
11114 if (found & SFUSE_STRAP_DDIB_DETECTED)
11115 intel_ddi_init(dev, PORT_B);
11116 if (found & SFUSE_STRAP_DDIC_DETECTED)
11117 intel_ddi_init(dev, PORT_C);
11118 if (found & SFUSE_STRAP_DDID_DETECTED)
11119 intel_ddi_init(dev, PORT_D);
11120 } else if (HAS_PCH_SPLIT(dev)) {
11121 int found;
11122 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11123
11124 if (has_edp_a(dev))
11125 intel_dp_init(dev, DP_A, PORT_A);
11126
11127 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11128 /* PCH SDVOB multiplex with HDMIB */
11129 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11130 if (!found)
11131 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11132 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11133 intel_dp_init(dev, PCH_DP_B, PORT_B);
11134 }
11135
11136 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11137 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11138
11139 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11140 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11141
11142 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11143 intel_dp_init(dev, PCH_DP_C, PORT_C);
11144
11145 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11146 intel_dp_init(dev, PCH_DP_D, PORT_D);
11147 } else if (IS_VALLEYVIEW(dev)) {
11148 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11149 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11150 PORT_B);
11151 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11152 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11153 }
11154
11155 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11156 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11157 PORT_C);
11158 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11159 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11160 }
11161
11162 if (IS_CHERRYVIEW(dev)) {
11163 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11164 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11165 PORT_D);
11166 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11167 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11168 }
11169 }
11170
11171 intel_dsi_init(dev);
11172 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11173 bool found = false;
11174
11175 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11176 DRM_DEBUG_KMS("probing SDVOB\n");
11177 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11178 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11179 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11180 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11181 }
11182
11183 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11184 intel_dp_init(dev, DP_B, PORT_B);
11185 }
11186
11187 /* Before G4X SDVOC doesn't have its own detect register */
11188
11189 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11190 DRM_DEBUG_KMS("probing SDVOC\n");
11191 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11192 }
11193
11194 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11195
11196 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11197 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11198 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11199 }
11200 if (SUPPORTS_INTEGRATED_DP(dev))
11201 intel_dp_init(dev, DP_C, PORT_C);
11202 }
11203
11204 if (SUPPORTS_INTEGRATED_DP(dev) &&
11205 (I915_READ(DP_D) & DP_DETECTED))
11206 intel_dp_init(dev, DP_D, PORT_D);
11207 } else if (IS_GEN2(dev))
11208 intel_dvo_init(dev);
11209
11210 if (SUPPORTS_TV(dev))
11211 intel_tv_init(dev);
11212
11213 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11214 encoder->base.possible_crtcs = encoder->crtc_mask;
11215 encoder->base.possible_clones =
11216 intel_encoder_clones(encoder);
11217 }
11218
11219 intel_init_pch_refclk(dev);
11220
11221 drm_helper_move_panel_connectors_to_head(dev);
11222 }
11223
11224 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11225 {
11226 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11227
11228 drm_framebuffer_cleanup(fb);
11229 WARN_ON(!intel_fb->obj->framebuffer_references--);
11230 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
11231 kfree(intel_fb);
11232 }
11233
11234 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11235 struct drm_file *file,
11236 unsigned int *handle)
11237 {
11238 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11239 struct drm_i915_gem_object *obj = intel_fb->obj;
11240
11241 return drm_gem_handle_create(file, &obj->base, handle);
11242 }
11243
11244 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11245 .destroy = intel_user_framebuffer_destroy,
11246 .create_handle = intel_user_framebuffer_create_handle,
11247 };
11248
11249 static int intel_framebuffer_init(struct drm_device *dev,
11250 struct intel_framebuffer *intel_fb,
11251 struct drm_mode_fb_cmd2 *mode_cmd,
11252 struct drm_i915_gem_object *obj)
11253 {
11254 int aligned_height;
11255 int pitch_limit;
11256 int ret;
11257
11258 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11259
11260 if (obj->tiling_mode == I915_TILING_Y) {
11261 DRM_DEBUG("hardware does not support tiling Y\n");
11262 return -EINVAL;
11263 }
11264
11265 if (mode_cmd->pitches[0] & 63) {
11266 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11267 mode_cmd->pitches[0]);
11268 return -EINVAL;
11269 }
11270
11271 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11272 pitch_limit = 32*1024;
11273 } else if (INTEL_INFO(dev)->gen >= 4) {
11274 if (obj->tiling_mode)
11275 pitch_limit = 16*1024;
11276 else
11277 pitch_limit = 32*1024;
11278 } else if (INTEL_INFO(dev)->gen >= 3) {
11279 if (obj->tiling_mode)
11280 pitch_limit = 8*1024;
11281 else
11282 pitch_limit = 16*1024;
11283 } else
11284 /* XXX DSPC is limited to 4k tiled */
11285 pitch_limit = 8*1024;
11286
11287 if (mode_cmd->pitches[0] > pitch_limit) {
11288 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11289 obj->tiling_mode ? "tiled" : "linear",
11290 mode_cmd->pitches[0], pitch_limit);
11291 return -EINVAL;
11292 }
11293
11294 if (obj->tiling_mode != I915_TILING_NONE &&
11295 mode_cmd->pitches[0] != obj->stride) {
11296 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11297 mode_cmd->pitches[0], obj->stride);
11298 return -EINVAL;
11299 }
11300
11301 /* Reject formats not supported by any plane early. */
11302 switch (mode_cmd->pixel_format) {
11303 case DRM_FORMAT_C8:
11304 case DRM_FORMAT_RGB565:
11305 case DRM_FORMAT_XRGB8888:
11306 case DRM_FORMAT_ARGB8888:
11307 break;
11308 case DRM_FORMAT_XRGB1555:
11309 case DRM_FORMAT_ARGB1555:
11310 if (INTEL_INFO(dev)->gen > 3) {
11311 DRM_DEBUG("unsupported pixel format: %s\n",
11312 drm_get_format_name(mode_cmd->pixel_format));
11313 return -EINVAL;
11314 }
11315 break;
11316 case DRM_FORMAT_XBGR8888:
11317 case DRM_FORMAT_ABGR8888:
11318 case DRM_FORMAT_XRGB2101010:
11319 case DRM_FORMAT_ARGB2101010:
11320 case DRM_FORMAT_XBGR2101010:
11321 case DRM_FORMAT_ABGR2101010:
11322 if (INTEL_INFO(dev)->gen < 4) {
11323 DRM_DEBUG("unsupported pixel format: %s\n",
11324 drm_get_format_name(mode_cmd->pixel_format));
11325 return -EINVAL;
11326 }
11327 break;
11328 case DRM_FORMAT_YUYV:
11329 case DRM_FORMAT_UYVY:
11330 case DRM_FORMAT_YVYU:
11331 case DRM_FORMAT_VYUY:
11332 if (INTEL_INFO(dev)->gen < 5) {
11333 DRM_DEBUG("unsupported pixel format: %s\n",
11334 drm_get_format_name(mode_cmd->pixel_format));
11335 return -EINVAL;
11336 }
11337 break;
11338 default:
11339 DRM_DEBUG("unsupported pixel format: %s\n",
11340 drm_get_format_name(mode_cmd->pixel_format));
11341 return -EINVAL;
11342 }
11343
11344 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11345 if (mode_cmd->offsets[0] != 0)
11346 return -EINVAL;
11347
11348 aligned_height = intel_align_height(dev, mode_cmd->height,
11349 obj->tiling_mode);
11350 /* FIXME drm helper for size checks (especially planar formats)? */
11351 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11352 return -EINVAL;
11353
11354 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11355 intel_fb->obj = obj;
11356 intel_fb->obj->framebuffer_references++;
11357
11358 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11359 if (ret) {
11360 DRM_ERROR("framebuffer init failed %d\n", ret);
11361 return ret;
11362 }
11363
11364 return 0;
11365 }
11366
11367 static struct drm_framebuffer *
11368 intel_user_framebuffer_create(struct drm_device *dev,
11369 struct drm_file *filp,
11370 struct drm_mode_fb_cmd2 *mode_cmd)
11371 {
11372 struct drm_i915_gem_object *obj;
11373
11374 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11375 mode_cmd->handles[0]));
11376 if (&obj->base == NULL)
11377 return ERR_PTR(-ENOENT);
11378
11379 return intel_framebuffer_create(dev, mode_cmd, obj);
11380 }
11381
11382 #ifndef CONFIG_DRM_I915_FBDEV
11383 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11384 {
11385 }
11386 #endif
11387
11388 static const struct drm_mode_config_funcs intel_mode_funcs = {
11389 .fb_create = intel_user_framebuffer_create,
11390 .output_poll_changed = intel_fbdev_output_poll_changed,
11391 };
11392
11393 /* Set up chip specific display functions */
11394 static void intel_init_display(struct drm_device *dev)
11395 {
11396 struct drm_i915_private *dev_priv = dev->dev_private;
11397
11398 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11399 dev_priv->display.find_dpll = g4x_find_best_dpll;
11400 else if (IS_CHERRYVIEW(dev))
11401 dev_priv->display.find_dpll = chv_find_best_dpll;
11402 else if (IS_VALLEYVIEW(dev))
11403 dev_priv->display.find_dpll = vlv_find_best_dpll;
11404 else if (IS_PINEVIEW(dev))
11405 dev_priv->display.find_dpll = pnv_find_best_dpll;
11406 else
11407 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11408
11409 if (HAS_DDI(dev)) {
11410 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11411 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11412 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11413 dev_priv->display.crtc_enable = haswell_crtc_enable;
11414 dev_priv->display.crtc_disable = haswell_crtc_disable;
11415 dev_priv->display.off = haswell_crtc_off;
11416 dev_priv->display.update_primary_plane =
11417 ironlake_update_primary_plane;
11418 } else if (HAS_PCH_SPLIT(dev)) {
11419 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11420 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11421 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11422 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11423 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11424 dev_priv->display.off = ironlake_crtc_off;
11425 dev_priv->display.update_primary_plane =
11426 ironlake_update_primary_plane;
11427 } else if (IS_VALLEYVIEW(dev)) {
11428 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11429 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11430 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11431 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11432 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11433 dev_priv->display.off = i9xx_crtc_off;
11434 dev_priv->display.update_primary_plane =
11435 i9xx_update_primary_plane;
11436 } else {
11437 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11438 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11439 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11440 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11441 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11442 dev_priv->display.off = i9xx_crtc_off;
11443 dev_priv->display.update_primary_plane =
11444 i9xx_update_primary_plane;
11445 }
11446
11447 /* Returns the core display clock speed */
11448 if (IS_VALLEYVIEW(dev))
11449 dev_priv->display.get_display_clock_speed =
11450 valleyview_get_display_clock_speed;
11451 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11452 dev_priv->display.get_display_clock_speed =
11453 i945_get_display_clock_speed;
11454 else if (IS_I915G(dev))
11455 dev_priv->display.get_display_clock_speed =
11456 i915_get_display_clock_speed;
11457 else if (IS_I945GM(dev) || IS_845G(dev))
11458 dev_priv->display.get_display_clock_speed =
11459 i9xx_misc_get_display_clock_speed;
11460 else if (IS_PINEVIEW(dev))
11461 dev_priv->display.get_display_clock_speed =
11462 pnv_get_display_clock_speed;
11463 else if (IS_I915GM(dev))
11464 dev_priv->display.get_display_clock_speed =
11465 i915gm_get_display_clock_speed;
11466 else if (IS_I865G(dev))
11467 dev_priv->display.get_display_clock_speed =
11468 i865_get_display_clock_speed;
11469 else if (IS_I85X(dev))
11470 dev_priv->display.get_display_clock_speed =
11471 i855_get_display_clock_speed;
11472 else /* 852, 830 */
11473 dev_priv->display.get_display_clock_speed =
11474 i830_get_display_clock_speed;
11475
11476 if (HAS_PCH_SPLIT(dev)) {
11477 if (IS_GEN5(dev)) {
11478 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11479 dev_priv->display.write_eld = ironlake_write_eld;
11480 } else if (IS_GEN6(dev)) {
11481 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11482 dev_priv->display.write_eld = ironlake_write_eld;
11483 dev_priv->display.modeset_global_resources =
11484 snb_modeset_global_resources;
11485 } else if (IS_IVYBRIDGE(dev)) {
11486 /* FIXME: detect B0+ stepping and use auto training */
11487 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11488 dev_priv->display.write_eld = ironlake_write_eld;
11489 dev_priv->display.modeset_global_resources =
11490 ivb_modeset_global_resources;
11491 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11492 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11493 dev_priv->display.write_eld = haswell_write_eld;
11494 dev_priv->display.modeset_global_resources =
11495 haswell_modeset_global_resources;
11496 }
11497 } else if (IS_G4X(dev)) {
11498 dev_priv->display.write_eld = g4x_write_eld;
11499 } else if (IS_VALLEYVIEW(dev)) {
11500 dev_priv->display.modeset_global_resources =
11501 valleyview_modeset_global_resources;
11502 dev_priv->display.write_eld = ironlake_write_eld;
11503 }
11504
11505 /* Default just returns -ENODEV to indicate unsupported */
11506 dev_priv->display.queue_flip = intel_default_queue_flip;
11507
11508 switch (INTEL_INFO(dev)->gen) {
11509 case 2:
11510 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11511 break;
11512
11513 case 3:
11514 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11515 break;
11516
11517 case 4:
11518 case 5:
11519 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11520 break;
11521
11522 case 6:
11523 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11524 break;
11525 case 7:
11526 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11527 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11528 break;
11529 }
11530
11531 intel_panel_init_backlight_funcs(dev);
11532 }
11533
11534 /*
11535 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11536 * resume, or other times. This quirk makes sure that's the case for
11537 * affected systems.
11538 */
11539 static void quirk_pipea_force(struct drm_device *dev)
11540 {
11541 struct drm_i915_private *dev_priv = dev->dev_private;
11542
11543 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11544 DRM_INFO("applying pipe a force quirk\n");
11545 }
11546
11547 /*
11548 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11549 */
11550 static void quirk_ssc_force_disable(struct drm_device *dev)
11551 {
11552 struct drm_i915_private *dev_priv = dev->dev_private;
11553 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11554 DRM_INFO("applying lvds SSC disable quirk\n");
11555 }
11556
11557 /*
11558 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11559 * brightness value
11560 */
11561 static void quirk_invert_brightness(struct drm_device *dev)
11562 {
11563 struct drm_i915_private *dev_priv = dev->dev_private;
11564 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11565 DRM_INFO("applying inverted panel brightness quirk\n");
11566 }
11567
11568 struct intel_quirk {
11569 int device;
11570 int subsystem_vendor;
11571 int subsystem_device;
11572 void (*hook)(struct drm_device *dev);
11573 };
11574
11575 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11576 struct intel_dmi_quirk {
11577 void (*hook)(struct drm_device *dev);
11578 const struct dmi_system_id (*dmi_id_list)[];
11579 };
11580
11581 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11582 {
11583 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11584 return 1;
11585 }
11586
11587 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11588 {
11589 .dmi_id_list = &(const struct dmi_system_id[]) {
11590 {
11591 .callback = intel_dmi_reverse_brightness,
11592 .ident = "NCR Corporation",
11593 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11594 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11595 },
11596 },
11597 { } /* terminating entry */
11598 },
11599 .hook = quirk_invert_brightness,
11600 },
11601 };
11602
11603 static struct intel_quirk intel_quirks[] = {
11604 /* HP Mini needs pipe A force quirk (LP: #322104) */
11605 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11606
11607 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11608 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11609
11610 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11611 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11612
11613 /* Lenovo U160 cannot use SSC on LVDS */
11614 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11615
11616 /* Sony Vaio Y cannot use SSC on LVDS */
11617 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
11618
11619 /* Acer Aspire 5734Z must invert backlight brightness */
11620 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
11621
11622 /* Acer/eMachines G725 */
11623 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
11624
11625 /* Acer/eMachines e725 */
11626 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
11627
11628 /* Acer/Packard Bell NCL20 */
11629 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
11630
11631 /* Acer Aspire 4736Z */
11632 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
11633
11634 /* Acer Aspire 5336 */
11635 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
11636 };
11637
11638 static void intel_init_quirks(struct drm_device *dev)
11639 {
11640 struct pci_dev *d = dev->pdev;
11641 int i;
11642
11643 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
11644 struct intel_quirk *q = &intel_quirks[i];
11645
11646 if (d->device == q->device &&
11647 (d->subsystem_vendor == q->subsystem_vendor ||
11648 q->subsystem_vendor == PCI_ANY_ID) &&
11649 (d->subsystem_device == q->subsystem_device ||
11650 q->subsystem_device == PCI_ANY_ID))
11651 q->hook(dev);
11652 }
11653 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
11654 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
11655 intel_dmi_quirks[i].hook(dev);
11656 }
11657 }
11658
11659 /* Disable the VGA plane that we never use */
11660 static void i915_disable_vga(struct drm_device *dev)
11661 {
11662 struct drm_i915_private *dev_priv = dev->dev_private;
11663 u8 sr1;
11664 u32 vga_reg = i915_vgacntrl_reg(dev);
11665
11666 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
11667 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
11668 outb(SR01, VGA_SR_INDEX);
11669 sr1 = inb(VGA_SR_DATA);
11670 outb(sr1 | 1<<5, VGA_SR_DATA);
11671 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
11672 udelay(300);
11673
11674 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
11675 POSTING_READ(vga_reg);
11676 }
11677
11678 void intel_modeset_init_hw(struct drm_device *dev)
11679 {
11680 intel_prepare_ddi(dev);
11681
11682 intel_init_clock_gating(dev);
11683
11684 intel_reset_dpio(dev);
11685
11686 intel_enable_gt_powersave(dev);
11687 }
11688
11689 void intel_modeset_suspend_hw(struct drm_device *dev)
11690 {
11691 intel_suspend_hw(dev);
11692 }
11693
11694 void intel_modeset_init(struct drm_device *dev)
11695 {
11696 struct drm_i915_private *dev_priv = dev->dev_private;
11697 int sprite, ret;
11698 enum pipe pipe;
11699 struct intel_crtc *crtc;
11700
11701 drm_mode_config_init(dev);
11702
11703 dev->mode_config.min_width = 0;
11704 dev->mode_config.min_height = 0;
11705
11706 dev->mode_config.preferred_depth = 24;
11707 dev->mode_config.prefer_shadow = 1;
11708
11709 dev->mode_config.funcs = &intel_mode_funcs;
11710
11711 intel_init_quirks(dev);
11712
11713 intel_init_pm(dev);
11714
11715 if (INTEL_INFO(dev)->num_pipes == 0)
11716 return;
11717
11718 intel_init_display(dev);
11719
11720 if (IS_GEN2(dev)) {
11721 dev->mode_config.max_width = 2048;
11722 dev->mode_config.max_height = 2048;
11723 } else if (IS_GEN3(dev)) {
11724 dev->mode_config.max_width = 4096;
11725 dev->mode_config.max_height = 4096;
11726 } else {
11727 dev->mode_config.max_width = 8192;
11728 dev->mode_config.max_height = 8192;
11729 }
11730
11731 if (IS_GEN2(dev)) {
11732 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
11733 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
11734 } else {
11735 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
11736 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
11737 }
11738
11739 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
11740
11741 DRM_DEBUG_KMS("%d display pipe%s available.\n",
11742 INTEL_INFO(dev)->num_pipes,
11743 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
11744
11745 for_each_pipe(pipe) {
11746 intel_crtc_init(dev, pipe);
11747 for_each_sprite(pipe, sprite) {
11748 ret = intel_plane_init(dev, pipe, sprite);
11749 if (ret)
11750 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
11751 pipe_name(pipe), sprite_name(pipe, sprite), ret);
11752 }
11753 }
11754
11755 intel_init_dpio(dev);
11756 intel_reset_dpio(dev);
11757
11758 intel_cpu_pll_init(dev);
11759 intel_shared_dpll_init(dev);
11760
11761 /* Just disable it once at startup */
11762 i915_disable_vga(dev);
11763 intel_setup_outputs(dev);
11764
11765 /* Just in case the BIOS is doing something questionable. */
11766 intel_disable_fbc(dev);
11767
11768 drm_modeset_lock_all(dev);
11769 intel_modeset_setup_hw_state(dev, false);
11770 drm_modeset_unlock_all(dev);
11771
11772 for_each_intel_crtc(dev, crtc) {
11773 if (!crtc->active)
11774 continue;
11775
11776 /*
11777 * Note that reserving the BIOS fb up front prevents us
11778 * from stuffing other stolen allocations like the ring
11779 * on top. This prevents some ugliness at boot time, and
11780 * can even allow for smooth boot transitions if the BIOS
11781 * fb is large enough for the active pipe configuration.
11782 */
11783 if (dev_priv->display.get_plane_config) {
11784 dev_priv->display.get_plane_config(crtc,
11785 &crtc->plane_config);
11786 /*
11787 * If the fb is shared between multiple heads, we'll
11788 * just get the first one.
11789 */
11790 intel_find_plane_obj(crtc, &crtc->plane_config);
11791 }
11792 }
11793 }
11794
11795 static void intel_enable_pipe_a(struct drm_device *dev)
11796 {
11797 struct intel_connector *connector;
11798 struct drm_connector *crt = NULL;
11799 struct intel_load_detect_pipe load_detect_temp;
11800 struct drm_modeset_acquire_ctx ctx;
11801
11802 /* We can't just switch on the pipe A, we need to set things up with a
11803 * proper mode and output configuration. As a gross hack, enable pipe A
11804 * by enabling the load detect pipe once. */
11805 list_for_each_entry(connector,
11806 &dev->mode_config.connector_list,
11807 base.head) {
11808 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
11809 crt = &connector->base;
11810 break;
11811 }
11812 }
11813
11814 if (!crt)
11815 return;
11816
11817 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
11818 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
11819
11820
11821 }
11822
11823 static bool
11824 intel_check_plane_mapping(struct intel_crtc *crtc)
11825 {
11826 struct drm_device *dev = crtc->base.dev;
11827 struct drm_i915_private *dev_priv = dev->dev_private;
11828 u32 reg, val;
11829
11830 if (INTEL_INFO(dev)->num_pipes == 1)
11831 return true;
11832
11833 reg = DSPCNTR(!crtc->plane);
11834 val = I915_READ(reg);
11835
11836 if ((val & DISPLAY_PLANE_ENABLE) &&
11837 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
11838 return false;
11839
11840 return true;
11841 }
11842
11843 static void intel_sanitize_crtc(struct intel_crtc *crtc)
11844 {
11845 struct drm_device *dev = crtc->base.dev;
11846 struct drm_i915_private *dev_priv = dev->dev_private;
11847 u32 reg;
11848
11849 /* Clear any frame start delays used for debugging left by the BIOS */
11850 reg = PIPECONF(crtc->config.cpu_transcoder);
11851 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
11852
11853 /* restore vblank interrupts to correct state */
11854 if (crtc->active)
11855 drm_vblank_on(dev, crtc->pipe);
11856 else
11857 drm_vblank_off(dev, crtc->pipe);
11858
11859 /* We need to sanitize the plane -> pipe mapping first because this will
11860 * disable the crtc (and hence change the state) if it is wrong. Note
11861 * that gen4+ has a fixed plane -> pipe mapping. */
11862 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
11863 struct intel_connector *connector;
11864 bool plane;
11865
11866 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
11867 crtc->base.base.id);
11868
11869 /* Pipe has the wrong plane attached and the plane is active.
11870 * Temporarily change the plane mapping and disable everything
11871 * ... */
11872 plane = crtc->plane;
11873 crtc->plane = !plane;
11874 dev_priv->display.crtc_disable(&crtc->base);
11875 crtc->plane = plane;
11876
11877 /* ... and break all links. */
11878 list_for_each_entry(connector, &dev->mode_config.connector_list,
11879 base.head) {
11880 if (connector->encoder->base.crtc != &crtc->base)
11881 continue;
11882
11883 connector->base.dpms = DRM_MODE_DPMS_OFF;
11884 connector->base.encoder = NULL;
11885 }
11886 /* multiple connectors may have the same encoder:
11887 * handle them and break crtc link separately */
11888 list_for_each_entry(connector, &dev->mode_config.connector_list,
11889 base.head)
11890 if (connector->encoder->base.crtc == &crtc->base) {
11891 connector->encoder->base.crtc = NULL;
11892 connector->encoder->connectors_active = false;
11893 }
11894
11895 WARN_ON(crtc->active);
11896 crtc->base.enabled = false;
11897 }
11898
11899 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
11900 crtc->pipe == PIPE_A && !crtc->active) {
11901 /* BIOS forgot to enable pipe A, this mostly happens after
11902 * resume. Force-enable the pipe to fix this, the update_dpms
11903 * call below we restore the pipe to the right state, but leave
11904 * the required bits on. */
11905 intel_enable_pipe_a(dev);
11906 }
11907
11908 /* Adjust the state of the output pipe according to whether we
11909 * have active connectors/encoders. */
11910 intel_crtc_update_dpms(&crtc->base);
11911
11912 if (crtc->active != crtc->base.enabled) {
11913 struct intel_encoder *encoder;
11914
11915 /* This can happen either due to bugs in the get_hw_state
11916 * functions or because the pipe is force-enabled due to the
11917 * pipe A quirk. */
11918 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11919 crtc->base.base.id,
11920 crtc->base.enabled ? "enabled" : "disabled",
11921 crtc->active ? "enabled" : "disabled");
11922
11923 crtc->base.enabled = crtc->active;
11924
11925 /* Because we only establish the connector -> encoder ->
11926 * crtc links if something is active, this means the
11927 * crtc is now deactivated. Break the links. connector
11928 * -> encoder links are only establish when things are
11929 * actually up, hence no need to break them. */
11930 WARN_ON(crtc->active);
11931
11932 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11933 WARN_ON(encoder->connectors_active);
11934 encoder->base.crtc = NULL;
11935 }
11936 }
11937
11938 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
11939 /*
11940 * We start out with underrun reporting disabled to avoid races.
11941 * For correct bookkeeping mark this on active crtcs.
11942 *
11943 * Also on gmch platforms we dont have any hardware bits to
11944 * disable the underrun reporting. Which means we need to start
11945 * out with underrun reporting disabled also on inactive pipes,
11946 * since otherwise we'll complain about the garbage we read when
11947 * e.g. coming up after runtime pm.
11948 *
11949 * No protection against concurrent access is required - at
11950 * worst a fifo underrun happens which also sets this to false.
11951 */
11952 crtc->cpu_fifo_underrun_disabled = true;
11953 crtc->pch_fifo_underrun_disabled = true;
11954
11955 update_scanline_offset(crtc);
11956 }
11957 }
11958
11959 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11960 {
11961 struct intel_connector *connector;
11962 struct drm_device *dev = encoder->base.dev;
11963
11964 /* We need to check both for a crtc link (meaning that the
11965 * encoder is active and trying to read from a pipe) and the
11966 * pipe itself being active. */
11967 bool has_active_crtc = encoder->base.crtc &&
11968 to_intel_crtc(encoder->base.crtc)->active;
11969
11970 if (encoder->connectors_active && !has_active_crtc) {
11971 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11972 encoder->base.base.id,
11973 encoder->base.name);
11974
11975 /* Connector is active, but has no active pipe. This is
11976 * fallout from our resume register restoring. Disable
11977 * the encoder manually again. */
11978 if (encoder->base.crtc) {
11979 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11980 encoder->base.base.id,
11981 encoder->base.name);
11982 encoder->disable(encoder);
11983 }
11984 encoder->base.crtc = NULL;
11985 encoder->connectors_active = false;
11986
11987 /* Inconsistent output/port/pipe state happens presumably due to
11988 * a bug in one of the get_hw_state functions. Or someplace else
11989 * in our code, like the register restore mess on resume. Clamp
11990 * things to off as a safer default. */
11991 list_for_each_entry(connector,
11992 &dev->mode_config.connector_list,
11993 base.head) {
11994 if (connector->encoder != encoder)
11995 continue;
11996 connector->base.dpms = DRM_MODE_DPMS_OFF;
11997 connector->base.encoder = NULL;
11998 }
11999 }
12000 /* Enabled encoders without active connectors will be fixed in
12001 * the crtc fixup. */
12002 }
12003
12004 void i915_redisable_vga_power_on(struct drm_device *dev)
12005 {
12006 struct drm_i915_private *dev_priv = dev->dev_private;
12007 u32 vga_reg = i915_vgacntrl_reg(dev);
12008
12009 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12010 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12011 i915_disable_vga(dev);
12012 }
12013 }
12014
12015 void i915_redisable_vga(struct drm_device *dev)
12016 {
12017 struct drm_i915_private *dev_priv = dev->dev_private;
12018
12019 /* This function can be called both from intel_modeset_setup_hw_state or
12020 * at a very early point in our resume sequence, where the power well
12021 * structures are not yet restored. Since this function is at a very
12022 * paranoid "someone might have enabled VGA while we were not looking"
12023 * level, just check if the power well is enabled instead of trying to
12024 * follow the "don't touch the power well if we don't need it" policy
12025 * the rest of the driver uses. */
12026 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12027 return;
12028
12029 i915_redisable_vga_power_on(dev);
12030 }
12031
12032 static bool primary_get_hw_state(struct intel_crtc *crtc)
12033 {
12034 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12035
12036 if (!crtc->active)
12037 return false;
12038
12039 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12040 }
12041
12042 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12043 {
12044 struct drm_i915_private *dev_priv = dev->dev_private;
12045 enum pipe pipe;
12046 struct intel_crtc *crtc;
12047 struct intel_encoder *encoder;
12048 struct intel_connector *connector;
12049 int i;
12050
12051 for_each_intel_crtc(dev, crtc) {
12052 memset(&crtc->config, 0, sizeof(crtc->config));
12053
12054 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12055
12056 crtc->active = dev_priv->display.get_pipe_config(crtc,
12057 &crtc->config);
12058
12059 crtc->base.enabled = crtc->active;
12060 crtc->primary_enabled = primary_get_hw_state(crtc);
12061
12062 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12063 crtc->base.base.id,
12064 crtc->active ? "enabled" : "disabled");
12065 }
12066
12067 /* FIXME: Smash this into the new shared dpll infrastructure. */
12068 if (HAS_DDI(dev))
12069 intel_ddi_setup_hw_pll_state(dev);
12070
12071 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12072 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12073
12074 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12075 pll->active = 0;
12076 for_each_intel_crtc(dev, crtc) {
12077 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12078 pll->active++;
12079 }
12080 pll->refcount = pll->active;
12081
12082 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12083 pll->name, pll->refcount, pll->on);
12084 }
12085
12086 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12087 base.head) {
12088 pipe = 0;
12089
12090 if (encoder->get_hw_state(encoder, &pipe)) {
12091 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12092 encoder->base.crtc = &crtc->base;
12093 encoder->get_config(encoder, &crtc->config);
12094 } else {
12095 encoder->base.crtc = NULL;
12096 }
12097
12098 encoder->connectors_active = false;
12099 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12100 encoder->base.base.id,
12101 encoder->base.name,
12102 encoder->base.crtc ? "enabled" : "disabled",
12103 pipe_name(pipe));
12104 }
12105
12106 list_for_each_entry(connector, &dev->mode_config.connector_list,
12107 base.head) {
12108 if (connector->get_hw_state(connector)) {
12109 connector->base.dpms = DRM_MODE_DPMS_ON;
12110 connector->encoder->connectors_active = true;
12111 connector->base.encoder = &connector->encoder->base;
12112 } else {
12113 connector->base.dpms = DRM_MODE_DPMS_OFF;
12114 connector->base.encoder = NULL;
12115 }
12116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12117 connector->base.base.id,
12118 connector->base.name,
12119 connector->base.encoder ? "enabled" : "disabled");
12120 }
12121 }
12122
12123 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12124 * and i915 state tracking structures. */
12125 void intel_modeset_setup_hw_state(struct drm_device *dev,
12126 bool force_restore)
12127 {
12128 struct drm_i915_private *dev_priv = dev->dev_private;
12129 enum pipe pipe;
12130 struct intel_crtc *crtc;
12131 struct intel_encoder *encoder;
12132 int i;
12133
12134 intel_modeset_readout_hw_state(dev);
12135
12136 /*
12137 * Now that we have the config, copy it to each CRTC struct
12138 * Note that this could go away if we move to using crtc_config
12139 * checking everywhere.
12140 */
12141 for_each_intel_crtc(dev, crtc) {
12142 if (crtc->active && i915.fastboot) {
12143 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12144 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12145 crtc->base.base.id);
12146 drm_mode_debug_printmodeline(&crtc->base.mode);
12147 }
12148 }
12149
12150 /* HW state is read out, now we need to sanitize this mess. */
12151 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12152 base.head) {
12153 intel_sanitize_encoder(encoder);
12154 }
12155
12156 for_each_pipe(pipe) {
12157 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12158 intel_sanitize_crtc(crtc);
12159 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12160 }
12161
12162 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12163 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12164
12165 if (!pll->on || pll->active)
12166 continue;
12167
12168 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12169
12170 pll->disable(dev_priv, pll);
12171 pll->on = false;
12172 }
12173
12174 if (HAS_PCH_SPLIT(dev))
12175 ilk_wm_get_hw_state(dev);
12176
12177 if (force_restore) {
12178 i915_redisable_vga(dev);
12179
12180 /*
12181 * We need to use raw interfaces for restoring state to avoid
12182 * checking (bogus) intermediate states.
12183 */
12184 for_each_pipe(pipe) {
12185 struct drm_crtc *crtc =
12186 dev_priv->pipe_to_crtc_mapping[pipe];
12187
12188 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12189 crtc->primary->fb);
12190 }
12191 } else {
12192 intel_modeset_update_staged_output_state(dev);
12193 }
12194
12195 intel_modeset_check_state(dev);
12196 }
12197
12198 void intel_modeset_gem_init(struct drm_device *dev)
12199 {
12200 struct drm_crtc *c;
12201 struct intel_framebuffer *fb;
12202
12203 mutex_lock(&dev->struct_mutex);
12204 intel_init_gt_powersave(dev);
12205 mutex_unlock(&dev->struct_mutex);
12206
12207 intel_modeset_init_hw(dev);
12208
12209 intel_setup_overlay(dev);
12210
12211 /*
12212 * Make sure any fbs we allocated at startup are properly
12213 * pinned & fenced. When we do the allocation it's too early
12214 * for this.
12215 */
12216 mutex_lock(&dev->struct_mutex);
12217 for_each_crtc(dev, c) {
12218 if (!c->primary->fb)
12219 continue;
12220
12221 fb = to_intel_framebuffer(c->primary->fb);
12222 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12223 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12224 to_intel_crtc(c)->pipe);
12225 drm_framebuffer_unreference(c->primary->fb);
12226 c->primary->fb = NULL;
12227 }
12228 }
12229 mutex_unlock(&dev->struct_mutex);
12230 }
12231
12232 void intel_connector_unregister(struct intel_connector *intel_connector)
12233 {
12234 struct drm_connector *connector = &intel_connector->base;
12235
12236 intel_panel_destroy_backlight(connector);
12237 drm_sysfs_connector_remove(connector);
12238 }
12239
12240 void intel_modeset_cleanup(struct drm_device *dev)
12241 {
12242 struct drm_i915_private *dev_priv = dev->dev_private;
12243 struct drm_crtc *crtc;
12244 struct drm_connector *connector;
12245
12246 /*
12247 * Interrupts and polling as the first thing to avoid creating havoc.
12248 * Too much stuff here (turning of rps, connectors, ...) would
12249 * experience fancy races otherwise.
12250 */
12251 drm_irq_uninstall(dev);
12252 cancel_work_sync(&dev_priv->hotplug_work);
12253 /*
12254 * Due to the hpd irq storm handling the hotplug work can re-arm the
12255 * poll handlers. Hence disable polling after hpd handling is shut down.
12256 */
12257 drm_kms_helper_poll_fini(dev);
12258
12259 mutex_lock(&dev->struct_mutex);
12260
12261 intel_unregister_dsm_handler();
12262
12263 for_each_crtc(dev, crtc) {
12264 /* Skip inactive CRTCs */
12265 if (!crtc->primary->fb)
12266 continue;
12267
12268 intel_increase_pllclock(crtc);
12269 }
12270
12271 intel_disable_fbc(dev);
12272
12273 intel_disable_gt_powersave(dev);
12274
12275 ironlake_teardown_rc6(dev);
12276
12277 mutex_unlock(&dev->struct_mutex);
12278
12279 /* flush any delayed tasks or pending work */
12280 flush_scheduled_work();
12281
12282 /* destroy the backlight and sysfs files before encoders/connectors */
12283 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12284 struct intel_connector *intel_connector;
12285
12286 intel_connector = to_intel_connector(connector);
12287 intel_connector->unregister(intel_connector);
12288 }
12289
12290 drm_mode_config_cleanup(dev);
12291
12292 intel_cleanup_overlay(dev);
12293
12294 mutex_lock(&dev->struct_mutex);
12295 intel_cleanup_gt_powersave(dev);
12296 mutex_unlock(&dev->struct_mutex);
12297 }
12298
12299 /*
12300 * Return which encoder is currently attached for connector.
12301 */
12302 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12303 {
12304 return &intel_attached_encoder(connector)->base;
12305 }
12306
12307 void intel_connector_attach_encoder(struct intel_connector *connector,
12308 struct intel_encoder *encoder)
12309 {
12310 connector->encoder = encoder;
12311 drm_mode_connector_attach_encoder(&connector->base,
12312 &encoder->base);
12313 }
12314
12315 /*
12316 * set vga decode state - true == enable VGA decode
12317 */
12318 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12319 {
12320 struct drm_i915_private *dev_priv = dev->dev_private;
12321 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12322 u16 gmch_ctrl;
12323
12324 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12325 DRM_ERROR("failed to read control word\n");
12326 return -EIO;
12327 }
12328
12329 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12330 return 0;
12331
12332 if (state)
12333 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12334 else
12335 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12336
12337 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12338 DRM_ERROR("failed to write control word\n");
12339 return -EIO;
12340 }
12341
12342 return 0;
12343 }
12344
12345 struct intel_display_error_state {
12346
12347 u32 power_well_driver;
12348
12349 int num_transcoders;
12350
12351 struct intel_cursor_error_state {
12352 u32 control;
12353 u32 position;
12354 u32 base;
12355 u32 size;
12356 } cursor[I915_MAX_PIPES];
12357
12358 struct intel_pipe_error_state {
12359 bool power_domain_on;
12360 u32 source;
12361 u32 stat;
12362 } pipe[I915_MAX_PIPES];
12363
12364 struct intel_plane_error_state {
12365 u32 control;
12366 u32 stride;
12367 u32 size;
12368 u32 pos;
12369 u32 addr;
12370 u32 surface;
12371 u32 tile_offset;
12372 } plane[I915_MAX_PIPES];
12373
12374 struct intel_transcoder_error_state {
12375 bool power_domain_on;
12376 enum transcoder cpu_transcoder;
12377
12378 u32 conf;
12379
12380 u32 htotal;
12381 u32 hblank;
12382 u32 hsync;
12383 u32 vtotal;
12384 u32 vblank;
12385 u32 vsync;
12386 } transcoder[4];
12387 };
12388
12389 struct intel_display_error_state *
12390 intel_display_capture_error_state(struct drm_device *dev)
12391 {
12392 struct drm_i915_private *dev_priv = dev->dev_private;
12393 struct intel_display_error_state *error;
12394 int transcoders[] = {
12395 TRANSCODER_A,
12396 TRANSCODER_B,
12397 TRANSCODER_C,
12398 TRANSCODER_EDP,
12399 };
12400 int i;
12401
12402 if (INTEL_INFO(dev)->num_pipes == 0)
12403 return NULL;
12404
12405 error = kzalloc(sizeof(*error), GFP_ATOMIC);
12406 if (error == NULL)
12407 return NULL;
12408
12409 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12410 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12411
12412 for_each_pipe(i) {
12413 error->pipe[i].power_domain_on =
12414 intel_display_power_enabled_sw(dev_priv,
12415 POWER_DOMAIN_PIPE(i));
12416 if (!error->pipe[i].power_domain_on)
12417 continue;
12418
12419 error->cursor[i].control = I915_READ(CURCNTR(i));
12420 error->cursor[i].position = I915_READ(CURPOS(i));
12421 error->cursor[i].base = I915_READ(CURBASE(i));
12422
12423 error->plane[i].control = I915_READ(DSPCNTR(i));
12424 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12425 if (INTEL_INFO(dev)->gen <= 3) {
12426 error->plane[i].size = I915_READ(DSPSIZE(i));
12427 error->plane[i].pos = I915_READ(DSPPOS(i));
12428 }
12429 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12430 error->plane[i].addr = I915_READ(DSPADDR(i));
12431 if (INTEL_INFO(dev)->gen >= 4) {
12432 error->plane[i].surface = I915_READ(DSPSURF(i));
12433 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12434 }
12435
12436 error->pipe[i].source = I915_READ(PIPESRC(i));
12437
12438 if (!HAS_PCH_SPLIT(dev))
12439 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12440 }
12441
12442 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12443 if (HAS_DDI(dev_priv->dev))
12444 error->num_transcoders++; /* Account for eDP. */
12445
12446 for (i = 0; i < error->num_transcoders; i++) {
12447 enum transcoder cpu_transcoder = transcoders[i];
12448
12449 error->transcoder[i].power_domain_on =
12450 intel_display_power_enabled_sw(dev_priv,
12451 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12452 if (!error->transcoder[i].power_domain_on)
12453 continue;
12454
12455 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12456
12457 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12458 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12459 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12460 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12461 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12462 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12463 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12464 }
12465
12466 return error;
12467 }
12468
12469 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12470
12471 void
12472 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12473 struct drm_device *dev,
12474 struct intel_display_error_state *error)
12475 {
12476 int i;
12477
12478 if (!error)
12479 return;
12480
12481 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12482 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12483 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12484 error->power_well_driver);
12485 for_each_pipe(i) {
12486 err_printf(m, "Pipe [%d]:\n", i);
12487 err_printf(m, " Power: %s\n",
12488 error->pipe[i].power_domain_on ? "on" : "off");
12489 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12490 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12491
12492 err_printf(m, "Plane [%d]:\n", i);
12493 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12494 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12495 if (INTEL_INFO(dev)->gen <= 3) {
12496 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12497 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12498 }
12499 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12500 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12501 if (INTEL_INFO(dev)->gen >= 4) {
12502 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12503 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12504 }
12505
12506 err_printf(m, "Cursor [%d]:\n", i);
12507 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12508 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12509 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12510 }
12511
12512 for (i = 0; i < error->num_transcoders; i++) {
12513 err_printf(m, "CPU transcoder: %c\n",
12514 transcoder_name(error->transcoder[i].cpu_transcoder));
12515 err_printf(m, " Power: %s\n",
12516 error->transcoder[i].power_domain_on ? "on" : "off");
12517 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12518 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12519 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12520 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12521 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12522 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12523 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12524 }
12525 }
Linux kernel - Deliverables
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