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drm: Pass 'name' to drm_universal_plane_init()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats[] = {
50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
52 DRM_FORMAT_XRGB1555,
53 DRM_FORMAT_XRGB8888,
54 };
55
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats[] = {
58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64 };
65
66 static const uint32_t skl_primary_formats[] = {
67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
70 DRM_FORMAT_XBGR8888,
71 DRM_FORMAT_ARGB8888,
72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
74 DRM_FORMAT_XBGR2101010,
75 DRM_FORMAT_YUYV,
76 DRM_FORMAT_YVYU,
77 DRM_FORMAT_UYVY,
78 DRM_FORMAT_VYUY,
79 };
80
81 /* Cursor formats */
82 static const uint32_t intel_cursor_formats[] = {
83 DRM_FORMAT_ARGB8888,
84 };
85
86 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
137 {
138 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
139
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv->sb_lock);
142 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
143 CCK_FUSE_HPLL_FREQ_MASK;
144 mutex_unlock(&dev_priv->sb_lock);
145
146 return vco_freq[hpll_freq] * 1000;
147 }
148
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
150 const char *name, u32 reg)
151 {
152 u32 val;
153 int divider;
154
155 if (dev_priv->hpll_freq == 0)
156 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
157
158 mutex_lock(&dev_priv->sb_lock);
159 val = vlv_cck_read(dev_priv, reg);
160 mutex_unlock(&dev_priv->sb_lock);
161
162 divider = val & CCK_FREQUENCY_VALUES;
163
164 WARN((val & CCK_FREQUENCY_STATUS) !=
165 (divider << CCK_FREQUENCY_STATUS_SHIFT),
166 "%s change in progress\n", name);
167
168 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
169 }
170
171 int
172 intel_pch_rawclk(struct drm_device *dev)
173 {
174 struct drm_i915_private *dev_priv = dev->dev_private;
175
176 WARN_ON(!HAS_PCH_SPLIT(dev));
177
178 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
179 }
180
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device *dev)
183 {
184 struct drm_i915_private *dev_priv = dev->dev_private;
185 uint32_t clkcfg;
186
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev))
189 return 200;
190
191 clkcfg = I915_READ(CLKCFG);
192 switch (clkcfg & CLKCFG_FSB_MASK) {
193 case CLKCFG_FSB_400:
194 return 100;
195 case CLKCFG_FSB_533:
196 return 133;
197 case CLKCFG_FSB_667:
198 return 166;
199 case CLKCFG_FSB_800:
200 return 200;
201 case CLKCFG_FSB_1067:
202 return 266;
203 case CLKCFG_FSB_1333:
204 return 333;
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600:
207 case CLKCFG_FSB_1600_ALT:
208 return 400;
209 default:
210 return 133;
211 }
212 }
213
214 static void intel_update_czclk(struct drm_i915_private *dev_priv)
215 {
216 if (!IS_VALLEYVIEW(dev_priv))
217 return;
218
219 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
220 CCK_CZ_CLOCK_CONTROL);
221
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
223 }
224
225 static inline u32 /* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device *dev)
227 {
228 if (IS_GEN5(dev)) {
229 struct drm_i915_private *dev_priv = dev->dev_private;
230 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
231 } else
232 return 27;
233 }
234
235 static const intel_limit_t intel_limits_i8xx_dac = {
236 .dot = { .min = 25000, .max = 350000 },
237 .vco = { .min = 908000, .max = 1512000 },
238 .n = { .min = 2, .max = 16 },
239 .m = { .min = 96, .max = 140 },
240 .m1 = { .min = 18, .max = 26 },
241 .m2 = { .min = 6, .max = 16 },
242 .p = { .min = 4, .max = 128 },
243 .p1 = { .min = 2, .max = 33 },
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 4, .p2_fast = 2 },
246 };
247
248 static const intel_limit_t intel_limits_i8xx_dvo = {
249 .dot = { .min = 25000, .max = 350000 },
250 .vco = { .min = 908000, .max = 1512000 },
251 .n = { .min = 2, .max = 16 },
252 .m = { .min = 96, .max = 140 },
253 .m1 = { .min = 18, .max = 26 },
254 .m2 = { .min = 6, .max = 16 },
255 .p = { .min = 4, .max = 128 },
256 .p1 = { .min = 2, .max = 33 },
257 .p2 = { .dot_limit = 165000,
258 .p2_slow = 4, .p2_fast = 4 },
259 };
260
261 static const intel_limit_t intel_limits_i8xx_lvds = {
262 .dot = { .min = 25000, .max = 350000 },
263 .vco = { .min = 908000, .max = 1512000 },
264 .n = { .min = 2, .max = 16 },
265 .m = { .min = 96, .max = 140 },
266 .m1 = { .min = 18, .max = 26 },
267 .m2 = { .min = 6, .max = 16 },
268 .p = { .min = 4, .max = 128 },
269 .p1 = { .min = 1, .max = 6 },
270 .p2 = { .dot_limit = 165000,
271 .p2_slow = 14, .p2_fast = 7 },
272 };
273
274 static const intel_limit_t intel_limits_i9xx_sdvo = {
275 .dot = { .min = 20000, .max = 400000 },
276 .vco = { .min = 1400000, .max = 2800000 },
277 .n = { .min = 1, .max = 6 },
278 .m = { .min = 70, .max = 120 },
279 .m1 = { .min = 8, .max = 18 },
280 .m2 = { .min = 3, .max = 7 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 200000,
284 .p2_slow = 10, .p2_fast = 5 },
285 };
286
287 static const intel_limit_t intel_limits_i9xx_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1400000, .max = 2800000 },
290 .n = { .min = 1, .max = 6 },
291 .m = { .min = 70, .max = 120 },
292 .m1 = { .min = 8, .max = 18 },
293 .m2 = { .min = 3, .max = 7 },
294 .p = { .min = 7, .max = 98 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 7 },
298 };
299
300
301 static const intel_limit_t intel_limits_g4x_sdvo = {
302 .dot = { .min = 25000, .max = 270000 },
303 .vco = { .min = 1750000, .max = 3500000},
304 .n = { .min = 1, .max = 4 },
305 .m = { .min = 104, .max = 138 },
306 .m1 = { .min = 17, .max = 23 },
307 .m2 = { .min = 5, .max = 11 },
308 .p = { .min = 10, .max = 30 },
309 .p1 = { .min = 1, .max = 3},
310 .p2 = { .dot_limit = 270000,
311 .p2_slow = 10,
312 .p2_fast = 10
313 },
314 };
315
316 static const intel_limit_t intel_limits_g4x_hdmi = {
317 .dot = { .min = 22000, .max = 400000 },
318 .vco = { .min = 1750000, .max = 3500000},
319 .n = { .min = 1, .max = 4 },
320 .m = { .min = 104, .max = 138 },
321 .m1 = { .min = 16, .max = 23 },
322 .m2 = { .min = 5, .max = 11 },
323 .p = { .min = 5, .max = 80 },
324 .p1 = { .min = 1, .max = 8},
325 .p2 = { .dot_limit = 165000,
326 .p2_slow = 10, .p2_fast = 5 },
327 };
328
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
330 .dot = { .min = 20000, .max = 115000 },
331 .vco = { .min = 1750000, .max = 3500000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 104, .max = 138 },
334 .m1 = { .min = 17, .max = 23 },
335 .m2 = { .min = 5, .max = 11 },
336 .p = { .min = 28, .max = 112 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 0,
339 .p2_slow = 14, .p2_fast = 14
340 },
341 };
342
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
344 .dot = { .min = 80000, .max = 224000 },
345 .vco = { .min = 1750000, .max = 3500000 },
346 .n = { .min = 1, .max = 3 },
347 .m = { .min = 104, .max = 138 },
348 .m1 = { .min = 17, .max = 23 },
349 .m2 = { .min = 5, .max = 11 },
350 .p = { .min = 14, .max = 42 },
351 .p1 = { .min = 2, .max = 6 },
352 .p2 = { .dot_limit = 0,
353 .p2_slow = 7, .p2_fast = 7
354 },
355 };
356
357 static const intel_limit_t intel_limits_pineview_sdvo = {
358 .dot = { .min = 20000, .max = 400000},
359 .vco = { .min = 1700000, .max = 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n = { .min = 3, .max = 6 },
362 .m = { .min = 2, .max = 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1 = { .min = 0, .max = 0 },
365 .m2 = { .min = 0, .max = 254 },
366 .p = { .min = 5, .max = 80 },
367 .p1 = { .min = 1, .max = 8 },
368 .p2 = { .dot_limit = 200000,
369 .p2_slow = 10, .p2_fast = 5 },
370 };
371
372 static const intel_limit_t intel_limits_pineview_lvds = {
373 .dot = { .min = 20000, .max = 400000 },
374 .vco = { .min = 1700000, .max = 3500000 },
375 .n = { .min = 3, .max = 6 },
376 .m = { .min = 2, .max = 256 },
377 .m1 = { .min = 0, .max = 0 },
378 .m2 = { .min = 0, .max = 254 },
379 .p = { .min = 7, .max = 112 },
380 .p1 = { .min = 1, .max = 8 },
381 .p2 = { .dot_limit = 112000,
382 .p2_slow = 14, .p2_fast = 14 },
383 };
384
385 /* Ironlake / Sandybridge
386 *
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
389 */
390 static const intel_limit_t intel_limits_ironlake_dac = {
391 .dot = { .min = 25000, .max = 350000 },
392 .vco = { .min = 1760000, .max = 3510000 },
393 .n = { .min = 1, .max = 5 },
394 .m = { .min = 79, .max = 127 },
395 .m1 = { .min = 12, .max = 22 },
396 .m2 = { .min = 5, .max = 9 },
397 .p = { .min = 5, .max = 80 },
398 .p1 = { .min = 1, .max = 8 },
399 .p2 = { .dot_limit = 225000,
400 .p2_slow = 10, .p2_fast = 5 },
401 };
402
403 static const intel_limit_t intel_limits_ironlake_single_lvds = {
404 .dot = { .min = 25000, .max = 350000 },
405 .vco = { .min = 1760000, .max = 3510000 },
406 .n = { .min = 1, .max = 3 },
407 .m = { .min = 79, .max = 118 },
408 .m1 = { .min = 12, .max = 22 },
409 .m2 = { .min = 5, .max = 9 },
410 .p = { .min = 28, .max = 112 },
411 .p1 = { .min = 2, .max = 8 },
412 .p2 = { .dot_limit = 225000,
413 .p2_slow = 14, .p2_fast = 14 },
414 };
415
416 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
417 .dot = { .min = 25000, .max = 350000 },
418 .vco = { .min = 1760000, .max = 3510000 },
419 .n = { .min = 1, .max = 3 },
420 .m = { .min = 79, .max = 127 },
421 .m1 = { .min = 12, .max = 22 },
422 .m2 = { .min = 5, .max = 9 },
423 .p = { .min = 14, .max = 56 },
424 .p1 = { .min = 2, .max = 8 },
425 .p2 = { .dot_limit = 225000,
426 .p2_slow = 7, .p2_fast = 7 },
427 };
428
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
431 .dot = { .min = 25000, .max = 350000 },
432 .vco = { .min = 1760000, .max = 3510000 },
433 .n = { .min = 1, .max = 2 },
434 .m = { .min = 79, .max = 126 },
435 .m1 = { .min = 12, .max = 22 },
436 .m2 = { .min = 5, .max = 9 },
437 .p = { .min = 28, .max = 112 },
438 .p1 = { .min = 2, .max = 8 },
439 .p2 = { .dot_limit = 225000,
440 .p2_slow = 14, .p2_fast = 14 },
441 };
442
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
444 .dot = { .min = 25000, .max = 350000 },
445 .vco = { .min = 1760000, .max = 3510000 },
446 .n = { .min = 1, .max = 3 },
447 .m = { .min = 79, .max = 126 },
448 .m1 = { .min = 12, .max = 22 },
449 .m2 = { .min = 5, .max = 9 },
450 .p = { .min = 14, .max = 42 },
451 .p1 = { .min = 2, .max = 6 },
452 .p2 = { .dot_limit = 225000,
453 .p2_slow = 7, .p2_fast = 7 },
454 };
455
456 static const intel_limit_t intel_limits_vlv = {
457 /*
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
462 */
463 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
464 .vco = { .min = 4000000, .max = 6000000 },
465 .n = { .min = 1, .max = 7 },
466 .m1 = { .min = 2, .max = 3 },
467 .m2 = { .min = 11, .max = 156 },
468 .p1 = { .min = 2, .max = 3 },
469 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
470 };
471
472 static const intel_limit_t intel_limits_chv = {
473 /*
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
478 */
479 .dot = { .min = 25000 * 5, .max = 540000 * 5},
480 .vco = { .min = 4800000, .max = 6480000 },
481 .n = { .min = 1, .max = 1 },
482 .m1 = { .min = 2, .max = 2 },
483 .m2 = { .min = 24 << 22, .max = 175 << 22 },
484 .p1 = { .min = 2, .max = 4 },
485 .p2 = { .p2_slow = 1, .p2_fast = 14 },
486 };
487
488 static const intel_limit_t intel_limits_bxt = {
489 /* FIXME: find real dot limits */
490 .dot = { .min = 0, .max = INT_MAX },
491 .vco = { .min = 4800000, .max = 6700000 },
492 .n = { .min = 1, .max = 1 },
493 .m1 = { .min = 2, .max = 2 },
494 /* FIXME: find real m2 limits */
495 .m2 = { .min = 2 << 22, .max = 255 << 22 },
496 .p1 = { .min = 2, .max = 4 },
497 .p2 = { .p2_slow = 1, .p2_fast = 20 },
498 };
499
500 static bool
501 needs_modeset(struct drm_crtc_state *state)
502 {
503 return drm_atomic_crtc_needs_modeset(state);
504 }
505
506 /**
507 * Returns whether any output on the specified pipe is of the specified type
508 */
509 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
510 {
511 struct drm_device *dev = crtc->base.dev;
512 struct intel_encoder *encoder;
513
514 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
515 if (encoder->type == type)
516 return true;
517
518 return false;
519 }
520
521 /**
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
525 * encoder->crtc.
526 */
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
528 int type)
529 {
530 struct drm_atomic_state *state = crtc_state->base.state;
531 struct drm_connector *connector;
532 struct drm_connector_state *connector_state;
533 struct intel_encoder *encoder;
534 int i, num_connectors = 0;
535
536 for_each_connector_in_state(state, connector, connector_state, i) {
537 if (connector_state->crtc != crtc_state->base.crtc)
538 continue;
539
540 num_connectors++;
541
542 encoder = to_intel_encoder(connector_state->best_encoder);
543 if (encoder->type == type)
544 return true;
545 }
546
547 WARN_ON(num_connectors == 0);
548
549 return false;
550 }
551
552 static const intel_limit_t *
553 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
554 {
555 struct drm_device *dev = crtc_state->base.crtc->dev;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
559 if (intel_is_dual_link_lvds(dev)) {
560 if (refclk == 100000)
561 limit = &intel_limits_ironlake_dual_lvds_100m;
562 else
563 limit = &intel_limits_ironlake_dual_lvds;
564 } else {
565 if (refclk == 100000)
566 limit = &intel_limits_ironlake_single_lvds_100m;
567 else
568 limit = &intel_limits_ironlake_single_lvds;
569 }
570 } else
571 limit = &intel_limits_ironlake_dac;
572
573 return limit;
574 }
575
576 static const intel_limit_t *
577 intel_g4x_limit(struct intel_crtc_state *crtc_state)
578 {
579 struct drm_device *dev = crtc_state->base.crtc->dev;
580 const intel_limit_t *limit;
581
582 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
583 if (intel_is_dual_link_lvds(dev))
584 limit = &intel_limits_g4x_dual_channel_lvds;
585 else
586 limit = &intel_limits_g4x_single_channel_lvds;
587 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
588 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
589 limit = &intel_limits_g4x_hdmi;
590 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
591 limit = &intel_limits_g4x_sdvo;
592 } else /* The option is for other outputs */
593 limit = &intel_limits_i9xx_sdvo;
594
595 return limit;
596 }
597
598 static const intel_limit_t *
599 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
600 {
601 struct drm_device *dev = crtc_state->base.crtc->dev;
602 const intel_limit_t *limit;
603
604 if (IS_BROXTON(dev))
605 limit = &intel_limits_bxt;
606 else if (HAS_PCH_SPLIT(dev))
607 limit = intel_ironlake_limit(crtc_state, refclk);
608 else if (IS_G4X(dev)) {
609 limit = intel_g4x_limit(crtc_state);
610 } else if (IS_PINEVIEW(dev)) {
611 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
612 limit = &intel_limits_pineview_lvds;
613 else
614 limit = &intel_limits_pineview_sdvo;
615 } else if (IS_CHERRYVIEW(dev)) {
616 limit = &intel_limits_chv;
617 } else if (IS_VALLEYVIEW(dev)) {
618 limit = &intel_limits_vlv;
619 } else if (!IS_GEN2(dev)) {
620 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
621 limit = &intel_limits_i9xx_lvds;
622 else
623 limit = &intel_limits_i9xx_sdvo;
624 } else {
625 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
626 limit = &intel_limits_i8xx_lvds;
627 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
628 limit = &intel_limits_i8xx_dvo;
629 else
630 limit = &intel_limits_i8xx_dac;
631 }
632 return limit;
633 }
634
635 /*
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
642 */
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
645 {
646 clock->m = clock->m2 + 2;
647 clock->p = clock->p1 * clock->p2;
648 if (WARN_ON(clock->n == 0 || clock->p == 0))
649 return 0;
650 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
651 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
652
653 return clock->dot;
654 }
655
656 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
657 {
658 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
659 }
660
661 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
662 {
663 clock->m = i9xx_dpll_compute_m(clock);
664 clock->p = clock->p1 * clock->p2;
665 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
666 return 0;
667 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
668 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
669
670 return clock->dot;
671 }
672
673 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
674 {
675 clock->m = clock->m1 * clock->m2;
676 clock->p = clock->p1 * clock->p2;
677 if (WARN_ON(clock->n == 0 || clock->p == 0))
678 return 0;
679 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
680 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
681
682 return clock->dot / 5;
683 }
684
685 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
686 {
687 clock->m = clock->m1 * clock->m2;
688 clock->p = clock->p1 * clock->p2;
689 if (WARN_ON(clock->n == 0 || clock->p == 0))
690 return 0;
691 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
692 clock->n << 22);
693 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
694
695 return clock->dot / 5;
696 }
697
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
699 /**
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
702 */
703
704 static bool intel_PLL_is_valid(struct drm_device *dev,
705 const intel_limit_t *limit,
706 const intel_clock_t *clock)
707 {
708 if (clock->n < limit->n.min || limit->n.max < clock->n)
709 INTELPllInvalid("n out of range\n");
710 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
715 INTELPllInvalid("m1 out of range\n");
716
717 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
718 if (clock->m1 <= clock->m2)
719 INTELPllInvalid("m1 <= m2\n");
720
721 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
722 if (clock->p < limit->p.min || limit->p.max < clock->p)
723 INTELPllInvalid("p out of range\n");
724 if (clock->m < limit->m.min || limit->m.max < clock->m)
725 INTELPllInvalid("m out of range\n");
726 }
727
728 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
732 */
733 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
734 INTELPllInvalid("dot out of range\n");
735
736 return true;
737 }
738
739 static int
740 i9xx_select_p2_div(const intel_limit_t *limit,
741 const struct intel_crtc_state *crtc_state,
742 int target)
743 {
744 struct drm_device *dev = crtc_state->base.crtc->dev;
745
746 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
747 /*
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
751 */
752 if (intel_is_dual_link_lvds(dev))
753 return limit->p2.p2_fast;
754 else
755 return limit->p2.p2_slow;
756 } else {
757 if (target < limit->p2.dot_limit)
758 return limit->p2.p2_slow;
759 else
760 return limit->p2.p2_fast;
761 }
762 }
763
764 static bool
765 i9xx_find_best_dpll(const intel_limit_t *limit,
766 struct intel_crtc_state *crtc_state,
767 int target, int refclk, intel_clock_t *match_clock,
768 intel_clock_t *best_clock)
769 {
770 struct drm_device *dev = crtc_state->base.crtc->dev;
771 intel_clock_t clock;
772 int err = target;
773
774 memset(best_clock, 0, sizeof(*best_clock));
775
776 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
777
778 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
779 clock.m1++) {
780 for (clock.m2 = limit->m2.min;
781 clock.m2 <= limit->m2.max; clock.m2++) {
782 if (clock.m2 >= clock.m1)
783 break;
784 for (clock.n = limit->n.min;
785 clock.n <= limit->n.max; clock.n++) {
786 for (clock.p1 = limit->p1.min;
787 clock.p1 <= limit->p1.max; clock.p1++) {
788 int this_err;
789
790 i9xx_calc_dpll_params(refclk, &clock);
791 if (!intel_PLL_is_valid(dev, limit,
792 &clock))
793 continue;
794 if (match_clock &&
795 clock.p != match_clock->p)
796 continue;
797
798 this_err = abs(clock.dot - target);
799 if (this_err < err) {
800 *best_clock = clock;
801 err = this_err;
802 }
803 }
804 }
805 }
806 }
807
808 return (err != target);
809 }
810
811 static bool
812 pnv_find_best_dpll(const intel_limit_t *limit,
813 struct intel_crtc_state *crtc_state,
814 int target, int refclk, intel_clock_t *match_clock,
815 intel_clock_t *best_clock)
816 {
817 struct drm_device *dev = crtc_state->base.crtc->dev;
818 intel_clock_t clock;
819 int err = target;
820
821 memset(best_clock, 0, sizeof(*best_clock));
822
823 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
824
825 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
826 clock.m1++) {
827 for (clock.m2 = limit->m2.min;
828 clock.m2 <= limit->m2.max; clock.m2++) {
829 for (clock.n = limit->n.min;
830 clock.n <= limit->n.max; clock.n++) {
831 for (clock.p1 = limit->p1.min;
832 clock.p1 <= limit->p1.max; clock.p1++) {
833 int this_err;
834
835 pnv_calc_dpll_params(refclk, &clock);
836 if (!intel_PLL_is_valid(dev, limit,
837 &clock))
838 continue;
839 if (match_clock &&
840 clock.p != match_clock->p)
841 continue;
842
843 this_err = abs(clock.dot - target);
844 if (this_err < err) {
845 *best_clock = clock;
846 err = this_err;
847 }
848 }
849 }
850 }
851 }
852
853 return (err != target);
854 }
855
856 static bool
857 g4x_find_best_dpll(const intel_limit_t *limit,
858 struct intel_crtc_state *crtc_state,
859 int target, int refclk, intel_clock_t *match_clock,
860 intel_clock_t *best_clock)
861 {
862 struct drm_device *dev = crtc_state->base.crtc->dev;
863 intel_clock_t clock;
864 int max_n;
865 bool found = false;
866 /* approximately equals target * 0.00585 */
867 int err_most = (target >> 8) + (target >> 9);
868
869 memset(best_clock, 0, sizeof(*best_clock));
870
871 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
872
873 max_n = limit->n.max;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock.m1 = limit->m1.max;
878 clock.m1 >= limit->m1.min; clock.m1--) {
879 for (clock.m2 = limit->m2.max;
880 clock.m2 >= limit->m2.min; clock.m2--) {
881 for (clock.p1 = limit->p1.max;
882 clock.p1 >= limit->p1.min; clock.p1--) {
883 int this_err;
884
885 i9xx_calc_dpll_params(refclk, &clock);
886 if (!intel_PLL_is_valid(dev, limit,
887 &clock))
888 continue;
889
890 this_err = abs(clock.dot - target);
891 if (this_err < err_most) {
892 *best_clock = clock;
893 err_most = this_err;
894 max_n = clock.n;
895 found = true;
896 }
897 }
898 }
899 }
900 }
901 return found;
902 }
903
904 /*
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
907 */
908 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
909 const intel_clock_t *calculated_clock,
910 const intel_clock_t *best_clock,
911 unsigned int best_error_ppm,
912 unsigned int *error_ppm)
913 {
914 /*
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
917 */
918 if (IS_CHERRYVIEW(dev)) {
919 *error_ppm = 0;
920
921 return calculated_clock->p > best_clock->p;
922 }
923
924 if (WARN_ON_ONCE(!target_freq))
925 return false;
926
927 *error_ppm = div_u64(1000000ULL *
928 abs(target_freq - calculated_clock->dot),
929 target_freq);
930 /*
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
934 */
935 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
936 *error_ppm = 0;
937
938 return true;
939 }
940
941 return *error_ppm + 10 < best_error_ppm;
942 }
943
944 static bool
945 vlv_find_best_dpll(const intel_limit_t *limit,
946 struct intel_crtc_state *crtc_state,
947 int target, int refclk, intel_clock_t *match_clock,
948 intel_clock_t *best_clock)
949 {
950 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
951 struct drm_device *dev = crtc->base.dev;
952 intel_clock_t clock;
953 unsigned int bestppm = 1000000;
954 /* min update 19.2 MHz */
955 int max_n = min(limit->n.max, refclk / 19200);
956 bool found = false;
957
958 target *= 5; /* fast clock */
959
960 memset(best_clock, 0, sizeof(*best_clock));
961
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
964 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
965 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
966 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
967 clock.p = clock.p1 * clock.p2;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
970 unsigned int ppm;
971
972 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
973 refclk * clock.m1);
974
975 vlv_calc_dpll_params(refclk, &clock);
976
977 if (!intel_PLL_is_valid(dev, limit,
978 &clock))
979 continue;
980
981 if (!vlv_PLL_is_optimal(dev, target,
982 &clock,
983 best_clock,
984 bestppm, &ppm))
985 continue;
986
987 *best_clock = clock;
988 bestppm = ppm;
989 found = true;
990 }
991 }
992 }
993 }
994
995 return found;
996 }
997
998 static bool
999 chv_find_best_dpll(const intel_limit_t *limit,
1000 struct intel_crtc_state *crtc_state,
1001 int target, int refclk, intel_clock_t *match_clock,
1002 intel_clock_t *best_clock)
1003 {
1004 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1005 struct drm_device *dev = crtc->base.dev;
1006 unsigned int best_error_ppm;
1007 intel_clock_t clock;
1008 uint64_t m2;
1009 int found = false;
1010
1011 memset(best_clock, 0, sizeof(*best_clock));
1012 best_error_ppm = 1000000;
1013
1014 /*
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1018 */
1019 clock.n = 1, clock.m1 = 2;
1020 target *= 5; /* fast clock */
1021
1022 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1023 for (clock.p2 = limit->p2.p2_fast;
1024 clock.p2 >= limit->p2.p2_slow;
1025 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1026 unsigned int error_ppm;
1027
1028 clock.p = clock.p1 * clock.p2;
1029
1030 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1031 clock.n) << 22, refclk * clock.m1);
1032
1033 if (m2 > INT_MAX/clock.m1)
1034 continue;
1035
1036 clock.m2 = m2;
1037
1038 chv_calc_dpll_params(refclk, &clock);
1039
1040 if (!intel_PLL_is_valid(dev, limit, &clock))
1041 continue;
1042
1043 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1044 best_error_ppm, &error_ppm))
1045 continue;
1046
1047 *best_clock = clock;
1048 best_error_ppm = error_ppm;
1049 found = true;
1050 }
1051 }
1052
1053 return found;
1054 }
1055
1056 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1057 intel_clock_t *best_clock)
1058 {
1059 int refclk = i9xx_get_refclk(crtc_state, 0);
1060
1061 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1062 target_clock, refclk, NULL, best_clock);
1063 }
1064
1065 bool intel_crtc_active(struct drm_crtc *crtc)
1066 {
1067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1068
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1071 *
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1074 *
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1077 *
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1080 * for atomic.
1081 */
1082 return intel_crtc->active && crtc->primary->state->fb &&
1083 intel_crtc->config->base.adjusted_mode.crtc_clock;
1084 }
1085
1086 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1087 enum pipe pipe)
1088 {
1089 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1091
1092 return intel_crtc->config->cpu_transcoder;
1093 }
1094
1095 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1096 {
1097 struct drm_i915_private *dev_priv = dev->dev_private;
1098 i915_reg_t reg = PIPEDSL(pipe);
1099 u32 line1, line2;
1100 u32 line_mask;
1101
1102 if (IS_GEN2(dev))
1103 line_mask = DSL_LINEMASK_GEN2;
1104 else
1105 line_mask = DSL_LINEMASK_GEN3;
1106
1107 line1 = I915_READ(reg) & line_mask;
1108 msleep(5);
1109 line2 = I915_READ(reg) & line_mask;
1110
1111 return line1 == line2;
1112 }
1113
1114 /*
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1117 *
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1121 *
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1124 *
1125 * Otherwise:
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1128 *
1129 */
1130 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1131 {
1132 struct drm_device *dev = crtc->base.dev;
1133 struct drm_i915_private *dev_priv = dev->dev_private;
1134 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1135 enum pipe pipe = crtc->pipe;
1136
1137 if (INTEL_INFO(dev)->gen >= 4) {
1138 i915_reg_t reg = PIPECONF(cpu_transcoder);
1139
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1142 100))
1143 WARN(1, "pipe_off wait timed out\n");
1144 } else {
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1148 }
1149 }
1150
1151 static const char *state_string(bool enabled)
1152 {
1153 return enabled ? "on" : "off";
1154 }
1155
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private *dev_priv,
1158 enum pipe pipe, bool state)
1159 {
1160 u32 val;
1161 bool cur_state;
1162
1163 val = I915_READ(DPLL(pipe));
1164 cur_state = !!(val & DPLL_VCO_ENABLE);
1165 I915_STATE_WARN(cur_state != state,
1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state), state_string(cur_state));
1168 }
1169
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1172 {
1173 u32 val;
1174 bool cur_state;
1175
1176 mutex_lock(&dev_priv->sb_lock);
1177 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1178 mutex_unlock(&dev_priv->sb_lock);
1179
1180 cur_state = val & DSI_PLL_VCO_EN;
1181 I915_STATE_WARN(cur_state != state,
1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state), state_string(cur_state));
1184 }
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1187
1188 struct intel_shared_dpll *
1189 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1190 {
1191 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1192
1193 if (crtc->config->shared_dpll < 0)
1194 return NULL;
1195
1196 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1197 }
1198
1199 /* For ILK+ */
1200 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1201 struct intel_shared_dpll *pll,
1202 bool state)
1203 {
1204 bool cur_state;
1205 struct intel_dpll_hw_state hw_state;
1206
1207 if (WARN (!pll,
1208 "asserting DPLL %s with no DPLL\n", state_string(state)))
1209 return;
1210
1211 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1212 I915_STATE_WARN(cur_state != state,
1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll->name, state_string(state), state_string(cur_state));
1215 }
1216
1217 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 bool cur_state;
1221 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1222 pipe);
1223
1224 if (HAS_DDI(dev_priv->dev)) {
1225 /* DDI does not have a specific FDI_TX register */
1226 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1227 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1228 } else {
1229 u32 val = I915_READ(FDI_TX_CTL(pipe));
1230 cur_state = !!(val & FDI_TX_ENABLE);
1231 }
1232 I915_STATE_WARN(cur_state != state,
1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state), state_string(cur_state));
1235 }
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1238
1239 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, bool state)
1241 {
1242 u32 val;
1243 bool cur_state;
1244
1245 val = I915_READ(FDI_RX_CTL(pipe));
1246 cur_state = !!(val & FDI_RX_ENABLE);
1247 I915_STATE_WARN(cur_state != state,
1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state), state_string(cur_state));
1250 }
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1253
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1255 enum pipe pipe)
1256 {
1257 u32 val;
1258
1259 /* ILK FDI PLL is always enabled */
1260 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1261 return;
1262
1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264 if (HAS_DDI(dev_priv->dev))
1265 return;
1266
1267 val = I915_READ(FDI_TX_CTL(pipe));
1268 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1269 }
1270
1271 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1272 enum pipe pipe, bool state)
1273 {
1274 u32 val;
1275 bool cur_state;
1276
1277 val = I915_READ(FDI_RX_CTL(pipe));
1278 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1279 I915_STATE_WARN(cur_state != state,
1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state), state_string(cur_state));
1282 }
1283
1284 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1285 enum pipe pipe)
1286 {
1287 struct drm_device *dev = dev_priv->dev;
1288 i915_reg_t pp_reg;
1289 u32 val;
1290 enum pipe panel_pipe = PIPE_A;
1291 bool locked = true;
1292
1293 if (WARN_ON(HAS_DDI(dev)))
1294 return;
1295
1296 if (HAS_PCH_SPLIT(dev)) {
1297 u32 port_sel;
1298
1299 pp_reg = PCH_PP_CONTROL;
1300 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1301
1302 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1303 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1304 panel_pipe = PIPE_B;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1309 panel_pipe = pipe;
1310 } else {
1311 pp_reg = PP_CONTROL;
1312 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1313 panel_pipe = PIPE_B;
1314 }
1315
1316 val = I915_READ(pp_reg);
1317 if (!(val & PANEL_POWER_ON) ||
1318 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1319 locked = false;
1320
1321 I915_STATE_WARN(panel_pipe == pipe && locked,
1322 "panel assertion failure, pipe %c regs locked\n",
1323 pipe_name(pipe));
1324 }
1325
1326 static void assert_cursor(struct drm_i915_private *dev_priv,
1327 enum pipe pipe, bool state)
1328 {
1329 struct drm_device *dev = dev_priv->dev;
1330 bool cur_state;
1331
1332 if (IS_845G(dev) || IS_I865G(dev))
1333 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1334 else
1335 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1336
1337 I915_STATE_WARN(cur_state != state,
1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe), state_string(state), state_string(cur_state));
1340 }
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1343
1344 void assert_pipe(struct drm_i915_private *dev_priv,
1345 enum pipe pipe, bool state)
1346 {
1347 bool cur_state;
1348 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1349 pipe);
1350
1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1353 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1354 state = true;
1355
1356 if (!intel_display_power_is_enabled(dev_priv,
1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1358 cur_state = false;
1359 } else {
1360 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1361 cur_state = !!(val & PIPECONF_ENABLE);
1362 }
1363
1364 I915_STATE_WARN(cur_state != state,
1365 "pipe %c assertion failure (expected %s, current %s)\n",
1366 pipe_name(pipe), state_string(state), state_string(cur_state));
1367 }
1368
1369 static void assert_plane(struct drm_i915_private *dev_priv,
1370 enum plane plane, bool state)
1371 {
1372 u32 val;
1373 bool cur_state;
1374
1375 val = I915_READ(DSPCNTR(plane));
1376 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1377 I915_STATE_WARN(cur_state != state,
1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane), state_string(state), state_string(cur_state));
1380 }
1381
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1384
1385 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1386 enum pipe pipe)
1387 {
1388 struct drm_device *dev = dev_priv->dev;
1389 int i;
1390
1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev)->gen >= 4) {
1393 u32 val = I915_READ(DSPCNTR(pipe));
1394 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1395 "plane %c assertion failure, should be disabled but not\n",
1396 plane_name(pipe));
1397 return;
1398 }
1399
1400 /* Need to check both planes against the pipe */
1401 for_each_pipe(dev_priv, i) {
1402 u32 val = I915_READ(DSPCNTR(i));
1403 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1404 DISPPLANE_SEL_PIPE_SHIFT;
1405 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i), pipe_name(pipe));
1408 }
1409 }
1410
1411 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1412 enum pipe pipe)
1413 {
1414 struct drm_device *dev = dev_priv->dev;
1415 int sprite;
1416
1417 if (INTEL_INFO(dev)->gen >= 9) {
1418 for_each_sprite(dev_priv, pipe, sprite) {
1419 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1420 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite, pipe_name(pipe));
1423 }
1424 } else if (IS_VALLEYVIEW(dev)) {
1425 for_each_sprite(dev_priv, pipe, sprite) {
1426 u32 val = I915_READ(SPCNTR(pipe, sprite));
1427 I915_STATE_WARN(val & SP_ENABLE,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 sprite_name(pipe, sprite), pipe_name(pipe));
1430 }
1431 } else if (INTEL_INFO(dev)->gen >= 7) {
1432 u32 val = I915_READ(SPRCTL(pipe));
1433 I915_STATE_WARN(val & SPRITE_ENABLE,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe), pipe_name(pipe));
1436 } else if (INTEL_INFO(dev)->gen >= 5) {
1437 u32 val = I915_READ(DVSCNTR(pipe));
1438 I915_STATE_WARN(val & DVS_ENABLE,
1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440 plane_name(pipe), pipe_name(pipe));
1441 }
1442 }
1443
1444 static void assert_vblank_disabled(struct drm_crtc *crtc)
1445 {
1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1447 drm_crtc_vblank_put(crtc);
1448 }
1449
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1451 {
1452 u32 val;
1453 bool enabled;
1454
1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1456
1457 val = I915_READ(PCH_DREF_CONTROL);
1458 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1459 DREF_SUPERSPREAD_SOURCE_MASK));
1460 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1461 }
1462
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1464 enum pipe pipe)
1465 {
1466 u32 val;
1467 bool enabled;
1468
1469 val = I915_READ(PCH_TRANSCONF(pipe));
1470 enabled = !!(val & TRANS_ENABLE);
1471 I915_STATE_WARN(enabled,
1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1473 pipe_name(pipe));
1474 }
1475
1476 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1477 enum pipe pipe, u32 port_sel, u32 val)
1478 {
1479 if ((val & DP_PORT_EN) == 0)
1480 return false;
1481
1482 if (HAS_PCH_CPT(dev_priv->dev)) {
1483 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1484 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1485 return false;
1486 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1487 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1488 return false;
1489 } else {
1490 if ((val & DP_PIPE_MASK) != (pipe << 30))
1491 return false;
1492 }
1493 return true;
1494 }
1495
1496 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1497 enum pipe pipe, u32 val)
1498 {
1499 if ((val & SDVO_ENABLE) == 0)
1500 return false;
1501
1502 if (HAS_PCH_CPT(dev_priv->dev)) {
1503 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1504 return false;
1505 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1506 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1507 return false;
1508 } else {
1509 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1510 return false;
1511 }
1512 return true;
1513 }
1514
1515 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1516 enum pipe pipe, u32 val)
1517 {
1518 if ((val & LVDS_PORT_EN) == 0)
1519 return false;
1520
1521 if (HAS_PCH_CPT(dev_priv->dev)) {
1522 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1523 return false;
1524 } else {
1525 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1526 return false;
1527 }
1528 return true;
1529 }
1530
1531 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1532 enum pipe pipe, u32 val)
1533 {
1534 if ((val & ADPA_DAC_ENABLE) == 0)
1535 return false;
1536 if (HAS_PCH_CPT(dev_priv->dev)) {
1537 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1538 return false;
1539 } else {
1540 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1541 return false;
1542 }
1543 return true;
1544 }
1545
1546 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1547 enum pipe pipe, i915_reg_t reg,
1548 u32 port_sel)
1549 {
1550 u32 val = I915_READ(reg);
1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 i915_mmio_reg_offset(reg), pipe_name(pipe));
1554
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1556 && (val & DP_PIPEB_SELECT),
1557 "IBX PCH dp port still using transcoder B\n");
1558 }
1559
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1561 enum pipe pipe, i915_reg_t reg)
1562 {
1563 u32 val = I915_READ(reg);
1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 i915_mmio_reg_offset(reg), pipe_name(pipe));
1567
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1569 && (val & SDVO_PIPE_B_SELECT),
1570 "IBX PCH hdmi port still using transcoder B\n");
1571 }
1572
1573 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1574 enum pipe pipe)
1575 {
1576 u32 val;
1577
1578 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1579 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1581
1582 val = I915_READ(PCH_ADPA);
1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
1585 pipe_name(pipe));
1586
1587 val = I915_READ(PCH_LVDS);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1590 pipe_name(pipe));
1591
1592 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1593 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1595 }
1596
1597 static void vlv_enable_pll(struct intel_crtc *crtc,
1598 const struct intel_crtc_state *pipe_config)
1599 {
1600 struct drm_device *dev = crtc->base.dev;
1601 struct drm_i915_private *dev_priv = dev->dev_private;
1602 i915_reg_t reg = DPLL(crtc->pipe);
1603 u32 dpll = pipe_config->dpll_hw_state.dpll;
1604
1605 assert_pipe_disabled(dev_priv, crtc->pipe);
1606
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1609
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv->dev))
1612 assert_panel_unlocked(dev_priv, crtc->pipe);
1613
1614 I915_WRITE(reg, dpll);
1615 POSTING_READ(reg);
1616 udelay(150);
1617
1618 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1620
1621 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1622 POSTING_READ(DPLL_MD(crtc->pipe));
1623
1624 /* We do this three times for luck */
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg, dpll);
1629 POSTING_READ(reg);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150); /* wait for warmup */
1634 }
1635
1636 static void chv_enable_pll(struct intel_crtc *crtc,
1637 const struct intel_crtc_state *pipe_config)
1638 {
1639 struct drm_device *dev = crtc->base.dev;
1640 struct drm_i915_private *dev_priv = dev->dev_private;
1641 int pipe = crtc->pipe;
1642 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1643 u32 tmp;
1644
1645 assert_pipe_disabled(dev_priv, crtc->pipe);
1646
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1648
1649 mutex_lock(&dev_priv->sb_lock);
1650
1651 /* Enable back the 10bit clock to display controller */
1652 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1653 tmp |= DPIO_DCLKP_EN;
1654 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1655
1656 mutex_unlock(&dev_priv->sb_lock);
1657
1658 /*
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1660 */
1661 udelay(1);
1662
1663 /* Enable PLL */
1664 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1665
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe);
1669
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1672 POSTING_READ(DPLL_MD(pipe));
1673 }
1674
1675 static int intel_num_dvo_pipes(struct drm_device *dev)
1676 {
1677 struct intel_crtc *crtc;
1678 int count = 0;
1679
1680 for_each_intel_crtc(dev, crtc)
1681 count += crtc->base.state->active &&
1682 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1683
1684 return count;
1685 }
1686
1687 static void i9xx_enable_pll(struct intel_crtc *crtc)
1688 {
1689 struct drm_device *dev = crtc->base.dev;
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691 i915_reg_t reg = DPLL(crtc->pipe);
1692 u32 dpll = crtc->config->dpll_hw_state.dpll;
1693
1694 assert_pipe_disabled(dev_priv, crtc->pipe);
1695
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1698
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev) && !IS_I830(dev))
1701 assert_panel_unlocked(dev_priv, crtc->pipe);
1702
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1705 /*
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1710 */
1711 dpll |= DPLL_DVO_2X_MODE;
1712 I915_WRITE(DPLL(!crtc->pipe),
1713 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1714 }
1715
1716 /*
1717 * Apparently we need to have VGA mode enabled prior to changing
1718 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719 * dividers, even though the register value does change.
1720 */
1721 I915_WRITE(reg, 0);
1722
1723 I915_WRITE(reg, dpll);
1724
1725 /* Wait for the clocks to stabilize. */
1726 POSTING_READ(reg);
1727 udelay(150);
1728
1729 if (INTEL_INFO(dev)->gen >= 4) {
1730 I915_WRITE(DPLL_MD(crtc->pipe),
1731 crtc->config->dpll_hw_state.dpll_md);
1732 } else {
1733 /* The pixel multiplier can only be updated once the
1734 * DPLL is enabled and the clocks are stable.
1735 *
1736 * So write it again.
1737 */
1738 I915_WRITE(reg, dpll);
1739 }
1740
1741 /* We do this three times for luck */
1742 I915_WRITE(reg, dpll);
1743 POSTING_READ(reg);
1744 udelay(150); /* wait for warmup */
1745 I915_WRITE(reg, dpll);
1746 POSTING_READ(reg);
1747 udelay(150); /* wait for warmup */
1748 I915_WRITE(reg, dpll);
1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
1751 }
1752
1753 /**
1754 * i9xx_disable_pll - disable a PLL
1755 * @dev_priv: i915 private structure
1756 * @pipe: pipe PLL to disable
1757 *
1758 * Disable the PLL for @pipe, making sure the pipe is off first.
1759 *
1760 * Note! This is for pre-ILK only.
1761 */
1762 static void i9xx_disable_pll(struct intel_crtc *crtc)
1763 {
1764 struct drm_device *dev = crtc->base.dev;
1765 struct drm_i915_private *dev_priv = dev->dev_private;
1766 enum pipe pipe = crtc->pipe;
1767
1768 /* Disable DVO 2x clock on both PLLs if necessary */
1769 if (IS_I830(dev) &&
1770 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1771 !intel_num_dvo_pipes(dev)) {
1772 I915_WRITE(DPLL(PIPE_B),
1773 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1774 I915_WRITE(DPLL(PIPE_A),
1775 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1776 }
1777
1778 /* Don't disable pipe or pipe PLLs if needed */
1779 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1780 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1781 return;
1782
1783 /* Make sure the pipe isn't still relying on us */
1784 assert_pipe_disabled(dev_priv, pipe);
1785
1786 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1787 POSTING_READ(DPLL(pipe));
1788 }
1789
1790 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1791 {
1792 u32 val;
1793
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv, pipe);
1796
1797 /*
1798 * Leave integrated clock source and reference clock enabled for pipe B.
1799 * The latter is needed for VGA hotplug / manual detection.
1800 */
1801 val = DPLL_VGA_MODE_DIS;
1802 if (pipe == PIPE_B)
1803 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1804 I915_WRITE(DPLL(pipe), val);
1805 POSTING_READ(DPLL(pipe));
1806
1807 }
1808
1809 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1810 {
1811 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1812 u32 val;
1813
1814 /* Make sure the pipe isn't still relying on us */
1815 assert_pipe_disabled(dev_priv, pipe);
1816
1817 /* Set PLL en = 0 */
1818 val = DPLL_SSC_REF_CLK_CHV |
1819 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->sb_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 mutex_unlock(&dev_priv->sb_lock);
1833 }
1834
1835 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1836 struct intel_digital_port *dport,
1837 unsigned int expected_mask)
1838 {
1839 u32 port_mask;
1840 i915_reg_t dpll_reg;
1841
1842 switch (dport->port) {
1843 case PORT_B:
1844 port_mask = DPLL_PORTB_READY_MASK;
1845 dpll_reg = DPLL(0);
1846 break;
1847 case PORT_C:
1848 port_mask = DPLL_PORTC_READY_MASK;
1849 dpll_reg = DPLL(0);
1850 expected_mask <<= 4;
1851 break;
1852 case PORT_D:
1853 port_mask = DPLL_PORTD_READY_MASK;
1854 dpll_reg = DPIO_PHY_STATUS;
1855 break;
1856 default:
1857 BUG();
1858 }
1859
1860 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1863 }
1864
1865 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1866 {
1867 struct drm_device *dev = crtc->base.dev;
1868 struct drm_i915_private *dev_priv = dev->dev_private;
1869 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1870
1871 if (WARN_ON(pll == NULL))
1872 return;
1873
1874 WARN_ON(!pll->config.crtc_mask);
1875 if (pll->active == 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1877 WARN_ON(pll->on);
1878 assert_shared_dpll_disabled(dev_priv, pll);
1879
1880 pll->mode_set(dev_priv, pll);
1881 }
1882 }
1883
1884 /**
1885 * intel_enable_shared_dpll - enable PCH PLL
1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1888 *
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1891 */
1892 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1893 {
1894 struct drm_device *dev = crtc->base.dev;
1895 struct drm_i915_private *dev_priv = dev->dev_private;
1896 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1897
1898 if (WARN_ON(pll == NULL))
1899 return;
1900
1901 if (WARN_ON(pll->config.crtc_mask == 0))
1902 return;
1903
1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905 pll->name, pll->active, pll->on,
1906 crtc->base.base.id);
1907
1908 if (pll->active++) {
1909 WARN_ON(!pll->on);
1910 assert_shared_dpll_enabled(dev_priv, pll);
1911 return;
1912 }
1913 WARN_ON(pll->on);
1914
1915 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1916
1917 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1918 pll->enable(dev_priv, pll);
1919 pll->on = true;
1920 }
1921
1922 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1923 {
1924 struct drm_device *dev = crtc->base.dev;
1925 struct drm_i915_private *dev_priv = dev->dev_private;
1926 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1927
1928 /* PCH only available on ILK+ */
1929 if (INTEL_INFO(dev)->gen < 5)
1930 return;
1931
1932 if (pll == NULL)
1933 return;
1934
1935 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1936 return;
1937
1938 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939 pll->name, pll->active, pll->on,
1940 crtc->base.base.id);
1941
1942 if (WARN_ON(pll->active == 0)) {
1943 assert_shared_dpll_disabled(dev_priv, pll);
1944 return;
1945 }
1946
1947 assert_shared_dpll_enabled(dev_priv, pll);
1948 WARN_ON(!pll->on);
1949 if (--pll->active)
1950 return;
1951
1952 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1953 pll->disable(dev_priv, pll);
1954 pll->on = false;
1955
1956 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1957 }
1958
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1960 enum pipe pipe)
1961 {
1962 struct drm_device *dev = dev_priv->dev;
1963 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1965 i915_reg_t reg;
1966 uint32_t val, pipeconf_val;
1967
1968 /* PCH only available on ILK+ */
1969 BUG_ON(!HAS_PCH_SPLIT(dev));
1970
1971 /* Make sure PCH DPLL is enabled */
1972 assert_shared_dpll_enabled(dev_priv,
1973 intel_crtc_to_shared_dpll(intel_crtc));
1974
1975 /* FDI must be feeding us bits for PCH ports */
1976 assert_fdi_tx_enabled(dev_priv, pipe);
1977 assert_fdi_rx_enabled(dev_priv, pipe);
1978
1979 if (HAS_PCH_CPT(dev)) {
1980 /* Workaround: Set the timing override bit before enabling the
1981 * pch transcoder. */
1982 reg = TRANS_CHICKEN2(pipe);
1983 val = I915_READ(reg);
1984 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1985 I915_WRITE(reg, val);
1986 }
1987
1988 reg = PCH_TRANSCONF(pipe);
1989 val = I915_READ(reg);
1990 pipeconf_val = I915_READ(PIPECONF(pipe));
1991
1992 if (HAS_PCH_IBX(dev_priv->dev)) {
1993 /*
1994 * Make the BPC in transcoder be consistent with
1995 * that in pipeconf reg. For HDMI we must use 8bpc
1996 * here for both 8bpc and 12bpc.
1997 */
1998 val &= ~PIPECONF_BPC_MASK;
1999 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2000 val |= PIPECONF_8BPC;
2001 else
2002 val |= pipeconf_val & PIPECONF_BPC_MASK;
2003 }
2004
2005 val &= ~TRANS_INTERLACE_MASK;
2006 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2007 if (HAS_PCH_IBX(dev_priv->dev) &&
2008 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2009 val |= TRANS_LEGACY_INTERLACED_ILK;
2010 else
2011 val |= TRANS_INTERLACED;
2012 else
2013 val |= TRANS_PROGRESSIVE;
2014
2015 I915_WRITE(reg, val | TRANS_ENABLE);
2016 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2017 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2018 }
2019
2020 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2021 enum transcoder cpu_transcoder)
2022 {
2023 u32 val, pipeconf_val;
2024
2025 /* PCH only available on ILK+ */
2026 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2027
2028 /* FDI must be feeding us bits for PCH ports */
2029 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2030 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2031
2032 /* Workaround: set timing override bit. */
2033 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2034 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2035 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2036
2037 val = TRANS_ENABLE;
2038 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2039
2040 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2041 PIPECONF_INTERLACED_ILK)
2042 val |= TRANS_INTERLACED;
2043 else
2044 val |= TRANS_PROGRESSIVE;
2045
2046 I915_WRITE(LPT_TRANSCONF, val);
2047 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2048 DRM_ERROR("Failed to enable PCH transcoder\n");
2049 }
2050
2051 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2052 enum pipe pipe)
2053 {
2054 struct drm_device *dev = dev_priv->dev;
2055 i915_reg_t reg;
2056 uint32_t val;
2057
2058 /* FDI relies on the transcoder */
2059 assert_fdi_tx_disabled(dev_priv, pipe);
2060 assert_fdi_rx_disabled(dev_priv, pipe);
2061
2062 /* Ports must be off as well */
2063 assert_pch_ports_disabled(dev_priv, pipe);
2064
2065 reg = PCH_TRANSCONF(pipe);
2066 val = I915_READ(reg);
2067 val &= ~TRANS_ENABLE;
2068 I915_WRITE(reg, val);
2069 /* wait for PCH transcoder off, transcoder state */
2070 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2071 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2072
2073 if (HAS_PCH_CPT(dev)) {
2074 /* Workaround: Clear the timing override chicken bit again. */
2075 reg = TRANS_CHICKEN2(pipe);
2076 val = I915_READ(reg);
2077 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2078 I915_WRITE(reg, val);
2079 }
2080 }
2081
2082 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2083 {
2084 u32 val;
2085
2086 val = I915_READ(LPT_TRANSCONF);
2087 val &= ~TRANS_ENABLE;
2088 I915_WRITE(LPT_TRANSCONF, val);
2089 /* wait for PCH transcoder off, transcoder state */
2090 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2091 DRM_ERROR("Failed to disable PCH transcoder\n");
2092
2093 /* Workaround: clear timing override bit. */
2094 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2095 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2096 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2097 }
2098
2099 /**
2100 * intel_enable_pipe - enable a pipe, asserting requirements
2101 * @crtc: crtc responsible for the pipe
2102 *
2103 * Enable @crtc's pipe, making sure that various hardware specific requirements
2104 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2105 */
2106 static void intel_enable_pipe(struct intel_crtc *crtc)
2107 {
2108 struct drm_device *dev = crtc->base.dev;
2109 struct drm_i915_private *dev_priv = dev->dev_private;
2110 enum pipe pipe = crtc->pipe;
2111 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2112 enum pipe pch_transcoder;
2113 i915_reg_t reg;
2114 u32 val;
2115
2116 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2117
2118 assert_planes_disabled(dev_priv, pipe);
2119 assert_cursor_disabled(dev_priv, pipe);
2120 assert_sprites_disabled(dev_priv, pipe);
2121
2122 if (HAS_PCH_LPT(dev_priv->dev))
2123 pch_transcoder = TRANSCODER_A;
2124 else
2125 pch_transcoder = pipe;
2126
2127 /*
2128 * A pipe without a PLL won't actually be able to drive bits from
2129 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2130 * need the check.
2131 */
2132 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2134 assert_dsi_pll_enabled(dev_priv);
2135 else
2136 assert_pll_enabled(dev_priv, pipe);
2137 else {
2138 if (crtc->config->has_pch_encoder) {
2139 /* if driving the PCH, we need FDI enabled */
2140 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2141 assert_fdi_tx_pll_enabled(dev_priv,
2142 (enum pipe) cpu_transcoder);
2143 }
2144 /* FIXME: assert CPU port conditions for SNB+ */
2145 }
2146
2147 reg = PIPECONF(cpu_transcoder);
2148 val = I915_READ(reg);
2149 if (val & PIPECONF_ENABLE) {
2150 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2151 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2152 return;
2153 }
2154
2155 I915_WRITE(reg, val | PIPECONF_ENABLE);
2156 POSTING_READ(reg);
2157 }
2158
2159 /**
2160 * intel_disable_pipe - disable a pipe, asserting requirements
2161 * @crtc: crtc whose pipes is to be disabled
2162 *
2163 * Disable the pipe of @crtc, making sure that various hardware
2164 * specific requirements are met, if applicable, e.g. plane
2165 * disabled, panel fitter off, etc.
2166 *
2167 * Will wait until the pipe has shut down before returning.
2168 */
2169 static void intel_disable_pipe(struct intel_crtc *crtc)
2170 {
2171 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2172 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2173 enum pipe pipe = crtc->pipe;
2174 i915_reg_t reg;
2175 u32 val;
2176
2177 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
2184 assert_cursor_disabled(dev_priv, pipe);
2185 assert_sprites_disabled(dev_priv, pipe);
2186
2187 reg = PIPECONF(cpu_transcoder);
2188 val = I915_READ(reg);
2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
2196 if (crtc->config->double_wide)
2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
2207 }
2208
2209 static bool need_vtd_wa(struct drm_device *dev)
2210 {
2211 #ifdef CONFIG_INTEL_IOMMU
2212 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2213 return true;
2214 #endif
2215 return false;
2216 }
2217
2218 unsigned int
2219 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2220 uint64_t fb_format_modifier, unsigned int plane)
2221 {
2222 unsigned int tile_height;
2223 uint32_t pixel_bytes;
2224
2225 switch (fb_format_modifier) {
2226 case DRM_FORMAT_MOD_NONE:
2227 tile_height = 1;
2228 break;
2229 case I915_FORMAT_MOD_X_TILED:
2230 tile_height = IS_GEN2(dev) ? 16 : 8;
2231 break;
2232 case I915_FORMAT_MOD_Y_TILED:
2233 tile_height = 32;
2234 break;
2235 case I915_FORMAT_MOD_Yf_TILED:
2236 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2237 switch (pixel_bytes) {
2238 default:
2239 case 1:
2240 tile_height = 64;
2241 break;
2242 case 2:
2243 case 4:
2244 tile_height = 32;
2245 break;
2246 case 8:
2247 tile_height = 16;
2248 break;
2249 case 16:
2250 WARN_ONCE(1,
2251 "128-bit pixels are not supported for display!");
2252 tile_height = 16;
2253 break;
2254 }
2255 break;
2256 default:
2257 MISSING_CASE(fb_format_modifier);
2258 tile_height = 1;
2259 break;
2260 }
2261
2262 return tile_height;
2263 }
2264
2265 unsigned int
2266 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2267 uint32_t pixel_format, uint64_t fb_format_modifier)
2268 {
2269 return ALIGN(height, intel_tile_height(dev, pixel_format,
2270 fb_format_modifier, 0));
2271 }
2272
2273 static void
2274 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2275 const struct drm_plane_state *plane_state)
2276 {
2277 struct intel_rotation_info *info = &view->params.rotation_info;
2278 unsigned int tile_height, tile_pitch;
2279
2280 *view = i915_ggtt_view_normal;
2281
2282 if (!plane_state)
2283 return;
2284
2285 if (!intel_rotation_90_or_270(plane_state->rotation))
2286 return;
2287
2288 *view = i915_ggtt_view_rotated;
2289
2290 info->height = fb->height;
2291 info->pixel_format = fb->pixel_format;
2292 info->pitch = fb->pitches[0];
2293 info->uv_offset = fb->offsets[1];
2294 info->fb_modifier = fb->modifier[0];
2295
2296 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2297 fb->modifier[0], 0);
2298 tile_pitch = PAGE_SIZE / tile_height;
2299 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2300 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2301 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2302
2303 if (info->pixel_format == DRM_FORMAT_NV12) {
2304 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2305 fb->modifier[0], 1);
2306 tile_pitch = PAGE_SIZE / tile_height;
2307 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2308 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2309 tile_height);
2310 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2311 PAGE_SIZE;
2312 }
2313 }
2314
2315 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2316 {
2317 if (INTEL_INFO(dev_priv)->gen >= 9)
2318 return 256 * 1024;
2319 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2320 IS_VALLEYVIEW(dev_priv))
2321 return 128 * 1024;
2322 else if (INTEL_INFO(dev_priv)->gen >= 4)
2323 return 4 * 1024;
2324 else
2325 return 0;
2326 }
2327
2328 int
2329 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2330 struct drm_framebuffer *fb,
2331 const struct drm_plane_state *plane_state)
2332 {
2333 struct drm_device *dev = fb->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2336 struct i915_ggtt_view view;
2337 u32 alignment;
2338 int ret;
2339
2340 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2341
2342 switch (fb->modifier[0]) {
2343 case DRM_FORMAT_MOD_NONE:
2344 alignment = intel_linear_alignment(dev_priv);
2345 break;
2346 case I915_FORMAT_MOD_X_TILED:
2347 if (INTEL_INFO(dev)->gen >= 9)
2348 alignment = 256 * 1024;
2349 else {
2350 /* pin() will align the object as required by fence */
2351 alignment = 0;
2352 }
2353 break;
2354 case I915_FORMAT_MOD_Y_TILED:
2355 case I915_FORMAT_MOD_Yf_TILED:
2356 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2357 "Y tiling bo slipped through, driver bug!\n"))
2358 return -EINVAL;
2359 alignment = 1 * 1024 * 1024;
2360 break;
2361 default:
2362 MISSING_CASE(fb->modifier[0]);
2363 return -EINVAL;
2364 }
2365
2366 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2367
2368 /* Note that the w/a also requires 64 PTE of padding following the
2369 * bo. We currently fill all unused PTE with the shadow page and so
2370 * we should always have valid PTE following the scanout preventing
2371 * the VT-d warning.
2372 */
2373 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2374 alignment = 256 * 1024;
2375
2376 /*
2377 * Global gtt pte registers are special registers which actually forward
2378 * writes to a chunk of system memory. Which means that there is no risk
2379 * that the register values disappear as soon as we call
2380 * intel_runtime_pm_put(), so it is correct to wrap only the
2381 * pin/unpin/fence and not more.
2382 */
2383 intel_runtime_pm_get(dev_priv);
2384
2385 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2386 &view);
2387 if (ret)
2388 goto err_pm;
2389
2390 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2391 * fence, whereas 965+ only requires a fence if using
2392 * framebuffer compression. For simplicity, we always install
2393 * a fence as the cost is not that onerous.
2394 */
2395 if (view.type == I915_GGTT_VIEW_NORMAL) {
2396 ret = i915_gem_object_get_fence(obj);
2397 if (ret == -EDEADLK) {
2398 /*
2399 * -EDEADLK means there are no free fences
2400 * no pending flips.
2401 *
2402 * This is propagated to atomic, but it uses
2403 * -EDEADLK to force a locking recovery, so
2404 * change the returned error to -EBUSY.
2405 */
2406 ret = -EBUSY;
2407 goto err_unpin;
2408 } else if (ret)
2409 goto err_unpin;
2410
2411 i915_gem_object_pin_fence(obj);
2412 }
2413
2414 intel_runtime_pm_put(dev_priv);
2415 return 0;
2416
2417 err_unpin:
2418 i915_gem_object_unpin_from_display_plane(obj, &view);
2419 err_pm:
2420 intel_runtime_pm_put(dev_priv);
2421 return ret;
2422 }
2423
2424 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425 const struct drm_plane_state *plane_state)
2426 {
2427 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2428 struct i915_ggtt_view view;
2429
2430 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2431
2432 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2433
2434 if (view.type == I915_GGTT_VIEW_NORMAL)
2435 i915_gem_object_unpin_fence(obj);
2436
2437 i915_gem_object_unpin_from_display_plane(obj, &view);
2438 }
2439
2440 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441 * is assumed to be a power-of-two. */
2442 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2443 int *x, int *y,
2444 unsigned int tiling_mode,
2445 unsigned int cpp,
2446 unsigned int pitch)
2447 {
2448 if (tiling_mode != I915_TILING_NONE) {
2449 unsigned int tile_rows, tiles;
2450
2451 tile_rows = *y / 8;
2452 *y %= 8;
2453
2454 tiles = *x / (512/cpp);
2455 *x %= 512/cpp;
2456
2457 return tile_rows * pitch * 8 + tiles * 4096;
2458 } else {
2459 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2460 unsigned int offset;
2461
2462 offset = *y * pitch + *x * cpp;
2463 *y = (offset & alignment) / pitch;
2464 *x = ((offset & alignment) - *y * pitch) / cpp;
2465 return offset & ~alignment;
2466 }
2467 }
2468
2469 static int i9xx_format_to_fourcc(int format)
2470 {
2471 switch (format) {
2472 case DISPPLANE_8BPP:
2473 return DRM_FORMAT_C8;
2474 case DISPPLANE_BGRX555:
2475 return DRM_FORMAT_XRGB1555;
2476 case DISPPLANE_BGRX565:
2477 return DRM_FORMAT_RGB565;
2478 default:
2479 case DISPPLANE_BGRX888:
2480 return DRM_FORMAT_XRGB8888;
2481 case DISPPLANE_RGBX888:
2482 return DRM_FORMAT_XBGR8888;
2483 case DISPPLANE_BGRX101010:
2484 return DRM_FORMAT_XRGB2101010;
2485 case DISPPLANE_RGBX101010:
2486 return DRM_FORMAT_XBGR2101010;
2487 }
2488 }
2489
2490 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2491 {
2492 switch (format) {
2493 case PLANE_CTL_FORMAT_RGB_565:
2494 return DRM_FORMAT_RGB565;
2495 default:
2496 case PLANE_CTL_FORMAT_XRGB_8888:
2497 if (rgb_order) {
2498 if (alpha)
2499 return DRM_FORMAT_ABGR8888;
2500 else
2501 return DRM_FORMAT_XBGR8888;
2502 } else {
2503 if (alpha)
2504 return DRM_FORMAT_ARGB8888;
2505 else
2506 return DRM_FORMAT_XRGB8888;
2507 }
2508 case PLANE_CTL_FORMAT_XRGB_2101010:
2509 if (rgb_order)
2510 return DRM_FORMAT_XBGR2101010;
2511 else
2512 return DRM_FORMAT_XRGB2101010;
2513 }
2514 }
2515
2516 static bool
2517 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2518 struct intel_initial_plane_config *plane_config)
2519 {
2520 struct drm_device *dev = crtc->base.dev;
2521 struct drm_i915_private *dev_priv = to_i915(dev);
2522 struct drm_i915_gem_object *obj = NULL;
2523 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2524 struct drm_framebuffer *fb = &plane_config->fb->base;
2525 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2526 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2527 PAGE_SIZE);
2528
2529 size_aligned -= base_aligned;
2530
2531 if (plane_config->size == 0)
2532 return false;
2533
2534 /* If the FB is too big, just don't use it since fbdev is not very
2535 * important and we should probably use that space with FBC or other
2536 * features. */
2537 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2538 return false;
2539
2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541 base_aligned,
2542 base_aligned,
2543 size_aligned);
2544 if (!obj)
2545 return false;
2546
2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
2549 obj->stride = fb->pitches[0];
2550
2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2557
2558 mutex_lock(&dev->struct_mutex);
2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2560 &mode_cmd, obj)) {
2561 DRM_DEBUG_KMS("intel fb init failed\n");
2562 goto out_unref_obj;
2563 }
2564 mutex_unlock(&dev->struct_mutex);
2565
2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2567 return true;
2568
2569 out_unref_obj:
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
2572 return false;
2573 }
2574
2575 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2576 static void
2577 update_state_fb(struct drm_plane *plane)
2578 {
2579 if (plane->fb == plane->state->fb)
2580 return;
2581
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2587 }
2588
2589 static void
2590 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
2592 {
2593 struct drm_device *dev = intel_crtc->base.dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct drm_crtc *c;
2596 struct intel_crtc *i;
2597 struct drm_i915_gem_object *obj;
2598 struct drm_plane *primary = intel_crtc->base.primary;
2599 struct drm_plane_state *plane_state = primary->state;
2600 struct drm_framebuffer *fb;
2601
2602 if (!plane_config->fb)
2603 return;
2604
2605 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2606 fb = &plane_config->fb->base;
2607 goto valid_fb;
2608 }
2609
2610 kfree(plane_config->fb);
2611
2612 /*
2613 * Failed to alloc the obj, check to see if we should share
2614 * an fb with another CRTC instead
2615 */
2616 for_each_crtc(dev, c) {
2617 i = to_intel_crtc(c);
2618
2619 if (c == &intel_crtc->base)
2620 continue;
2621
2622 if (!i->active)
2623 continue;
2624
2625 fb = c->primary->fb;
2626 if (!fb)
2627 continue;
2628
2629 obj = intel_fb_obj(fb);
2630 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2631 drm_framebuffer_reference(fb);
2632 goto valid_fb;
2633 }
2634 }
2635
2636 return;
2637
2638 valid_fb:
2639 plane_state->src_x = 0;
2640 plane_state->src_y = 0;
2641 plane_state->src_w = fb->width << 16;
2642 plane_state->src_h = fb->height << 16;
2643
2644 plane_state->crtc_x = 0;
2645 plane_state->crtc_y = 0;
2646 plane_state->crtc_w = fb->width;
2647 plane_state->crtc_h = fb->height;
2648
2649 obj = intel_fb_obj(fb);
2650 if (obj->tiling_mode != I915_TILING_NONE)
2651 dev_priv->preserve_bios_swizzle = true;
2652
2653 drm_framebuffer_reference(fb);
2654 primary->fb = primary->state->fb = fb;
2655 primary->crtc = primary->state->crtc = &intel_crtc->base;
2656 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2657 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2658 }
2659
2660 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2661 struct drm_framebuffer *fb,
2662 int x, int y)
2663 {
2664 struct drm_device *dev = crtc->dev;
2665 struct drm_i915_private *dev_priv = dev->dev_private;
2666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2667 struct drm_plane *primary = crtc->primary;
2668 bool visible = to_intel_plane_state(primary->state)->visible;
2669 struct drm_i915_gem_object *obj;
2670 int plane = intel_crtc->plane;
2671 unsigned long linear_offset;
2672 u32 dspcntr;
2673 i915_reg_t reg = DSPCNTR(plane);
2674 int pixel_size;
2675
2676 if (!visible || !fb) {
2677 I915_WRITE(reg, 0);
2678 if (INTEL_INFO(dev)->gen >= 4)
2679 I915_WRITE(DSPSURF(plane), 0);
2680 else
2681 I915_WRITE(DSPADDR(plane), 0);
2682 POSTING_READ(reg);
2683 return;
2684 }
2685
2686 obj = intel_fb_obj(fb);
2687 if (WARN_ON(obj == NULL))
2688 return;
2689
2690 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2691
2692 dspcntr = DISPPLANE_GAMMA_ENABLE;
2693
2694 dspcntr |= DISPLAY_PLANE_ENABLE;
2695
2696 if (INTEL_INFO(dev)->gen < 4) {
2697 if (intel_crtc->pipe == PIPE_B)
2698 dspcntr |= DISPPLANE_SEL_PIPE_B;
2699
2700 /* pipesrc and dspsize control the size that is scaled from,
2701 * which should always be the user's requested size.
2702 */
2703 I915_WRITE(DSPSIZE(plane),
2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
2706 I915_WRITE(DSPPOS(plane), 0);
2707 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2708 I915_WRITE(PRIMSIZE(plane),
2709 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2710 (intel_crtc->config->pipe_src_w - 1));
2711 I915_WRITE(PRIMPOS(plane), 0);
2712 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2713 }
2714
2715 switch (fb->pixel_format) {
2716 case DRM_FORMAT_C8:
2717 dspcntr |= DISPPLANE_8BPP;
2718 break;
2719 case DRM_FORMAT_XRGB1555:
2720 dspcntr |= DISPPLANE_BGRX555;
2721 break;
2722 case DRM_FORMAT_RGB565:
2723 dspcntr |= DISPPLANE_BGRX565;
2724 break;
2725 case DRM_FORMAT_XRGB8888:
2726 dspcntr |= DISPPLANE_BGRX888;
2727 break;
2728 case DRM_FORMAT_XBGR8888:
2729 dspcntr |= DISPPLANE_RGBX888;
2730 break;
2731 case DRM_FORMAT_XRGB2101010:
2732 dspcntr |= DISPPLANE_BGRX101010;
2733 break;
2734 case DRM_FORMAT_XBGR2101010:
2735 dspcntr |= DISPPLANE_RGBX101010;
2736 break;
2737 default:
2738 BUG();
2739 }
2740
2741 if (INTEL_INFO(dev)->gen >= 4 &&
2742 obj->tiling_mode != I915_TILING_NONE)
2743 dspcntr |= DISPPLANE_TILED;
2744
2745 if (IS_G4X(dev))
2746 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2747
2748 linear_offset = y * fb->pitches[0] + x * pixel_size;
2749
2750 if (INTEL_INFO(dev)->gen >= 4) {
2751 intel_crtc->dspaddr_offset =
2752 intel_gen4_compute_page_offset(dev_priv,
2753 &x, &y, obj->tiling_mode,
2754 pixel_size,
2755 fb->pitches[0]);
2756 linear_offset -= intel_crtc->dspaddr_offset;
2757 } else {
2758 intel_crtc->dspaddr_offset = linear_offset;
2759 }
2760
2761 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2762 dspcntr |= DISPPLANE_ROTATE_180;
2763
2764 x += (intel_crtc->config->pipe_src_w - 1);
2765 y += (intel_crtc->config->pipe_src_h - 1);
2766
2767 /* Finding the last pixel of the last line of the display
2768 data and adding to linear_offset*/
2769 linear_offset +=
2770 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2771 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2772 }
2773
2774 intel_crtc->adjusted_x = x;
2775 intel_crtc->adjusted_y = y;
2776
2777 I915_WRITE(reg, dspcntr);
2778
2779 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2780 if (INTEL_INFO(dev)->gen >= 4) {
2781 I915_WRITE(DSPSURF(plane),
2782 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2783 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2784 I915_WRITE(DSPLINOFF(plane), linear_offset);
2785 } else
2786 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2787 POSTING_READ(reg);
2788 }
2789
2790 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2791 struct drm_framebuffer *fb,
2792 int x, int y)
2793 {
2794 struct drm_device *dev = crtc->dev;
2795 struct drm_i915_private *dev_priv = dev->dev_private;
2796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797 struct drm_plane *primary = crtc->primary;
2798 bool visible = to_intel_plane_state(primary->state)->visible;
2799 struct drm_i915_gem_object *obj;
2800 int plane = intel_crtc->plane;
2801 unsigned long linear_offset;
2802 u32 dspcntr;
2803 i915_reg_t reg = DSPCNTR(plane);
2804 int pixel_size;
2805
2806 if (!visible || !fb) {
2807 I915_WRITE(reg, 0);
2808 I915_WRITE(DSPSURF(plane), 0);
2809 POSTING_READ(reg);
2810 return;
2811 }
2812
2813 obj = intel_fb_obj(fb);
2814 if (WARN_ON(obj == NULL))
2815 return;
2816
2817 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2818
2819 dspcntr = DISPPLANE_GAMMA_ENABLE;
2820
2821 dspcntr |= DISPLAY_PLANE_ENABLE;
2822
2823 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2824 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2825
2826 switch (fb->pixel_format) {
2827 case DRM_FORMAT_C8:
2828 dspcntr |= DISPPLANE_8BPP;
2829 break;
2830 case DRM_FORMAT_RGB565:
2831 dspcntr |= DISPPLANE_BGRX565;
2832 break;
2833 case DRM_FORMAT_XRGB8888:
2834 dspcntr |= DISPPLANE_BGRX888;
2835 break;
2836 case DRM_FORMAT_XBGR8888:
2837 dspcntr |= DISPPLANE_RGBX888;
2838 break;
2839 case DRM_FORMAT_XRGB2101010:
2840 dspcntr |= DISPPLANE_BGRX101010;
2841 break;
2842 case DRM_FORMAT_XBGR2101010:
2843 dspcntr |= DISPPLANE_RGBX101010;
2844 break;
2845 default:
2846 BUG();
2847 }
2848
2849 if (obj->tiling_mode != I915_TILING_NONE)
2850 dspcntr |= DISPPLANE_TILED;
2851
2852 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2853 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2854
2855 linear_offset = y * fb->pitches[0] + x * pixel_size;
2856 intel_crtc->dspaddr_offset =
2857 intel_gen4_compute_page_offset(dev_priv,
2858 &x, &y, obj->tiling_mode,
2859 pixel_size,
2860 fb->pitches[0]);
2861 linear_offset -= intel_crtc->dspaddr_offset;
2862 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2863 dspcntr |= DISPPLANE_ROTATE_180;
2864
2865 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2866 x += (intel_crtc->config->pipe_src_w - 1);
2867 y += (intel_crtc->config->pipe_src_h - 1);
2868
2869 /* Finding the last pixel of the last line of the display
2870 data and adding to linear_offset*/
2871 linear_offset +=
2872 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2873 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2874 }
2875 }
2876
2877 intel_crtc->adjusted_x = x;
2878 intel_crtc->adjusted_y = y;
2879
2880 I915_WRITE(reg, dspcntr);
2881
2882 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2883 I915_WRITE(DSPSURF(plane),
2884 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2885 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2886 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2887 } else {
2888 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2889 I915_WRITE(DSPLINOFF(plane), linear_offset);
2890 }
2891 POSTING_READ(reg);
2892 }
2893
2894 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2895 uint32_t pixel_format)
2896 {
2897 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2898
2899 /*
2900 * The stride is either expressed as a multiple of 64 bytes
2901 * chunks for linear buffers or in number of tiles for tiled
2902 * buffers.
2903 */
2904 switch (fb_modifier) {
2905 case DRM_FORMAT_MOD_NONE:
2906 return 64;
2907 case I915_FORMAT_MOD_X_TILED:
2908 if (INTEL_INFO(dev)->gen == 2)
2909 return 128;
2910 return 512;
2911 case I915_FORMAT_MOD_Y_TILED:
2912 /* No need to check for old gens and Y tiling since this is
2913 * about the display engine and those will be blocked before
2914 * we get here.
2915 */
2916 return 128;
2917 case I915_FORMAT_MOD_Yf_TILED:
2918 if (bits_per_pixel == 8)
2919 return 64;
2920 else
2921 return 128;
2922 default:
2923 MISSING_CASE(fb_modifier);
2924 return 64;
2925 }
2926 }
2927
2928 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2929 struct drm_i915_gem_object *obj,
2930 unsigned int plane)
2931 {
2932 struct i915_ggtt_view view;
2933 struct i915_vma *vma;
2934 u64 offset;
2935
2936 intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2937 intel_plane->base.state);
2938
2939 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2940 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2941 view.type))
2942 return -1;
2943
2944 offset = vma->node.start;
2945
2946 if (plane == 1) {
2947 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2948 PAGE_SIZE;
2949 }
2950
2951 WARN_ON(upper_32_bits(offset));
2952
2953 return lower_32_bits(offset);
2954 }
2955
2956 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2957 {
2958 struct drm_device *dev = intel_crtc->base.dev;
2959 struct drm_i915_private *dev_priv = dev->dev_private;
2960
2961 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2962 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2963 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2964 }
2965
2966 /*
2967 * This function detaches (aka. unbinds) unused scalers in hardware
2968 */
2969 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
2970 {
2971 struct intel_crtc_scaler_state *scaler_state;
2972 int i;
2973
2974 scaler_state = &intel_crtc->config->scaler_state;
2975
2976 /* loop through and disable scalers that aren't in use */
2977 for (i = 0; i < intel_crtc->num_scalers; i++) {
2978 if (!scaler_state->scalers[i].in_use)
2979 skl_detach_scaler(intel_crtc, i);
2980 }
2981 }
2982
2983 u32 skl_plane_ctl_format(uint32_t pixel_format)
2984 {
2985 switch (pixel_format) {
2986 case DRM_FORMAT_C8:
2987 return PLANE_CTL_FORMAT_INDEXED;
2988 case DRM_FORMAT_RGB565:
2989 return PLANE_CTL_FORMAT_RGB_565;
2990 case DRM_FORMAT_XBGR8888:
2991 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2992 case DRM_FORMAT_XRGB8888:
2993 return PLANE_CTL_FORMAT_XRGB_8888;
2994 /*
2995 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2996 * to be already pre-multiplied. We need to add a knob (or a different
2997 * DRM_FORMAT) for user-space to configure that.
2998 */
2999 case DRM_FORMAT_ABGR8888:
3000 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3001 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3002 case DRM_FORMAT_ARGB8888:
3003 return PLANE_CTL_FORMAT_XRGB_8888 |
3004 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3005 case DRM_FORMAT_XRGB2101010:
3006 return PLANE_CTL_FORMAT_XRGB_2101010;
3007 case DRM_FORMAT_XBGR2101010:
3008 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3009 case DRM_FORMAT_YUYV:
3010 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3011 case DRM_FORMAT_YVYU:
3012 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3013 case DRM_FORMAT_UYVY:
3014 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3015 case DRM_FORMAT_VYUY:
3016 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3017 default:
3018 MISSING_CASE(pixel_format);
3019 }
3020
3021 return 0;
3022 }
3023
3024 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3025 {
3026 switch (fb_modifier) {
3027 case DRM_FORMAT_MOD_NONE:
3028 break;
3029 case I915_FORMAT_MOD_X_TILED:
3030 return PLANE_CTL_TILED_X;
3031 case I915_FORMAT_MOD_Y_TILED:
3032 return PLANE_CTL_TILED_Y;
3033 case I915_FORMAT_MOD_Yf_TILED:
3034 return PLANE_CTL_TILED_YF;
3035 default:
3036 MISSING_CASE(fb_modifier);
3037 }
3038
3039 return 0;
3040 }
3041
3042 u32 skl_plane_ctl_rotation(unsigned int rotation)
3043 {
3044 switch (rotation) {
3045 case BIT(DRM_ROTATE_0):
3046 break;
3047 /*
3048 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3049 * while i915 HW rotation is clockwise, thats why this swapping.
3050 */
3051 case BIT(DRM_ROTATE_90):
3052 return PLANE_CTL_ROTATE_270;
3053 case BIT(DRM_ROTATE_180):
3054 return PLANE_CTL_ROTATE_180;
3055 case BIT(DRM_ROTATE_270):
3056 return PLANE_CTL_ROTATE_90;
3057 default:
3058 MISSING_CASE(rotation);
3059 }
3060
3061 return 0;
3062 }
3063
3064 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3065 struct drm_framebuffer *fb,
3066 int x, int y)
3067 {
3068 struct drm_device *dev = crtc->dev;
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3071 struct drm_plane *plane = crtc->primary;
3072 bool visible = to_intel_plane_state(plane->state)->visible;
3073 struct drm_i915_gem_object *obj;
3074 int pipe = intel_crtc->pipe;
3075 u32 plane_ctl, stride_div, stride;
3076 u32 tile_height, plane_offset, plane_size;
3077 unsigned int rotation;
3078 int x_offset, y_offset;
3079 u32 surf_addr;
3080 struct intel_crtc_state *crtc_state = intel_crtc->config;
3081 struct intel_plane_state *plane_state;
3082 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3083 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3084 int scaler_id = -1;
3085
3086 plane_state = to_intel_plane_state(plane->state);
3087
3088 if (!visible || !fb) {
3089 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3090 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3091 POSTING_READ(PLANE_CTL(pipe, 0));
3092 return;
3093 }
3094
3095 plane_ctl = PLANE_CTL_ENABLE |
3096 PLANE_CTL_PIPE_GAMMA_ENABLE |
3097 PLANE_CTL_PIPE_CSC_ENABLE;
3098
3099 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3100 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3101 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3102
3103 rotation = plane->state->rotation;
3104 plane_ctl |= skl_plane_ctl_rotation(rotation);
3105
3106 obj = intel_fb_obj(fb);
3107 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3108 fb->pixel_format);
3109 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3110
3111 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3112
3113 scaler_id = plane_state->scaler_id;
3114 src_x = plane_state->src.x1 >> 16;
3115 src_y = plane_state->src.y1 >> 16;
3116 src_w = drm_rect_width(&plane_state->src) >> 16;
3117 src_h = drm_rect_height(&plane_state->src) >> 16;
3118 dst_x = plane_state->dst.x1;
3119 dst_y = plane_state->dst.y1;
3120 dst_w = drm_rect_width(&plane_state->dst);
3121 dst_h = drm_rect_height(&plane_state->dst);
3122
3123 WARN_ON(x != src_x || y != src_y);
3124
3125 if (intel_rotation_90_or_270(rotation)) {
3126 /* stride = Surface height in tiles */
3127 tile_height = intel_tile_height(dev, fb->pixel_format,
3128 fb->modifier[0], 0);
3129 stride = DIV_ROUND_UP(fb->height, tile_height);
3130 x_offset = stride * tile_height - y - src_h;
3131 y_offset = x;
3132 plane_size = (src_w - 1) << 16 | (src_h - 1);
3133 } else {
3134 stride = fb->pitches[0] / stride_div;
3135 x_offset = x;
3136 y_offset = y;
3137 plane_size = (src_h - 1) << 16 | (src_w - 1);
3138 }
3139 plane_offset = y_offset << 16 | x_offset;
3140
3141 intel_crtc->adjusted_x = x_offset;
3142 intel_crtc->adjusted_y = y_offset;
3143
3144 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3145 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3146 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3147 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3148
3149 if (scaler_id >= 0) {
3150 uint32_t ps_ctrl = 0;
3151
3152 WARN_ON(!dst_w || !dst_h);
3153 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3154 crtc_state->scaler_state.scalers[scaler_id].mode;
3155 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3156 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3157 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3158 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3159 I915_WRITE(PLANE_POS(pipe, 0), 0);
3160 } else {
3161 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3162 }
3163
3164 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3165
3166 POSTING_READ(PLANE_SURF(pipe, 0));
3167 }
3168
3169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3170 static int
3171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3172 int x, int y, enum mode_set_atomic state)
3173 {
3174 struct drm_device *dev = crtc->dev;
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176
3177 if (dev_priv->fbc.disable_fbc)
3178 dev_priv->fbc.disable_fbc(dev_priv);
3179
3180 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3181
3182 return 0;
3183 }
3184
3185 static void intel_complete_page_flips(struct drm_device *dev)
3186 {
3187 struct drm_crtc *crtc;
3188
3189 for_each_crtc(dev, crtc) {
3190 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3191 enum plane plane = intel_crtc->plane;
3192
3193 intel_prepare_page_flip(dev, plane);
3194 intel_finish_page_flip_plane(dev, plane);
3195 }
3196 }
3197
3198 static void intel_update_primary_planes(struct drm_device *dev)
3199 {
3200 struct drm_crtc *crtc;
3201
3202 for_each_crtc(dev, crtc) {
3203 struct intel_plane *plane = to_intel_plane(crtc->primary);
3204 struct intel_plane_state *plane_state;
3205
3206 drm_modeset_lock_crtc(crtc, &plane->base);
3207 plane_state = to_intel_plane_state(plane->base.state);
3208
3209 if (crtc->state->active && plane_state->base.fb)
3210 plane->commit_plane(&plane->base, plane_state);
3211
3212 drm_modeset_unlock_crtc(crtc);
3213 }
3214 }
3215
3216 void intel_prepare_reset(struct drm_device *dev)
3217 {
3218 /* no reset support for gen2 */
3219 if (IS_GEN2(dev))
3220 return;
3221
3222 /* reset doesn't touch the display */
3223 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3224 return;
3225
3226 drm_modeset_lock_all(dev);
3227 /*
3228 * Disabling the crtcs gracefully seems nicer. Also the
3229 * g33 docs say we should at least disable all the planes.
3230 */
3231 intel_display_suspend(dev);
3232 }
3233
3234 void intel_finish_reset(struct drm_device *dev)
3235 {
3236 struct drm_i915_private *dev_priv = to_i915(dev);
3237
3238 /*
3239 * Flips in the rings will be nuked by the reset,
3240 * so complete all pending flips so that user space
3241 * will get its events and not get stuck.
3242 */
3243 intel_complete_page_flips(dev);
3244
3245 /* no reset support for gen2 */
3246 if (IS_GEN2(dev))
3247 return;
3248
3249 /* reset doesn't touch the display */
3250 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3251 /*
3252 * Flips in the rings have been nuked by the reset,
3253 * so update the base address of all primary
3254 * planes to the the last fb to make sure we're
3255 * showing the correct fb after a reset.
3256 *
3257 * FIXME: Atomic will make this obsolete since we won't schedule
3258 * CS-based flips (which might get lost in gpu resets) any more.
3259 */
3260 intel_update_primary_planes(dev);
3261 return;
3262 }
3263
3264 /*
3265 * The display has been reset as well,
3266 * so need a full re-initialization.
3267 */
3268 intel_runtime_pm_disable_interrupts(dev_priv);
3269 intel_runtime_pm_enable_interrupts(dev_priv);
3270
3271 intel_modeset_init_hw(dev);
3272
3273 spin_lock_irq(&dev_priv->irq_lock);
3274 if (dev_priv->display.hpd_irq_setup)
3275 dev_priv->display.hpd_irq_setup(dev);
3276 spin_unlock_irq(&dev_priv->irq_lock);
3277
3278 intel_display_resume(dev);
3279
3280 intel_hpd_init(dev_priv);
3281
3282 drm_modeset_unlock_all(dev);
3283 }
3284
3285 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3286 {
3287 struct drm_device *dev = crtc->dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290 bool pending;
3291
3292 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3293 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3294 return false;
3295
3296 spin_lock_irq(&dev->event_lock);
3297 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3298 spin_unlock_irq(&dev->event_lock);
3299
3300 return pending;
3301 }
3302
3303 static void intel_update_pipe_config(struct intel_crtc *crtc,
3304 struct intel_crtc_state *old_crtc_state)
3305 {
3306 struct drm_device *dev = crtc->base.dev;
3307 struct drm_i915_private *dev_priv = dev->dev_private;
3308 struct intel_crtc_state *pipe_config =
3309 to_intel_crtc_state(crtc->base.state);
3310
3311 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3312 crtc->base.mode = crtc->base.state->mode;
3313
3314 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3315 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3316 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3317
3318 if (HAS_DDI(dev))
3319 intel_set_pipe_csc(&crtc->base);
3320
3321 /*
3322 * Update pipe size and adjust fitter if needed: the reason for this is
3323 * that in compute_mode_changes we check the native mode (not the pfit
3324 * mode) to see if we can flip rather than do a full mode set. In the
3325 * fastboot case, we'll flip, but if we don't update the pipesrc and
3326 * pfit state, we'll end up with a big fb scanned out into the wrong
3327 * sized surface.
3328 */
3329
3330 I915_WRITE(PIPESRC(crtc->pipe),
3331 ((pipe_config->pipe_src_w - 1) << 16) |
3332 (pipe_config->pipe_src_h - 1));
3333
3334 /* on skylake this is done by detaching scalers */
3335 if (INTEL_INFO(dev)->gen >= 9) {
3336 skl_detach_scalers(crtc);
3337
3338 if (pipe_config->pch_pfit.enabled)
3339 skylake_pfit_enable(crtc);
3340 } else if (HAS_PCH_SPLIT(dev)) {
3341 if (pipe_config->pch_pfit.enabled)
3342 ironlake_pfit_enable(crtc);
3343 else if (old_crtc_state->pch_pfit.enabled)
3344 ironlake_pfit_disable(crtc, true);
3345 }
3346 }
3347
3348 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3349 {
3350 struct drm_device *dev = crtc->dev;
3351 struct drm_i915_private *dev_priv = dev->dev_private;
3352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3353 int pipe = intel_crtc->pipe;
3354 i915_reg_t reg;
3355 u32 temp;
3356
3357 /* enable normal train */
3358 reg = FDI_TX_CTL(pipe);
3359 temp = I915_READ(reg);
3360 if (IS_IVYBRIDGE(dev)) {
3361 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3362 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3363 } else {
3364 temp &= ~FDI_LINK_TRAIN_NONE;
3365 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3366 }
3367 I915_WRITE(reg, temp);
3368
3369 reg = FDI_RX_CTL(pipe);
3370 temp = I915_READ(reg);
3371 if (HAS_PCH_CPT(dev)) {
3372 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3373 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3374 } else {
3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_NONE;
3377 }
3378 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3379
3380 /* wait one idle pattern time */
3381 POSTING_READ(reg);
3382 udelay(1000);
3383
3384 /* IVB wants error correction enabled */
3385 if (IS_IVYBRIDGE(dev))
3386 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3387 FDI_FE_ERRC_ENABLE);
3388 }
3389
3390 /* The FDI link training functions for ILK/Ibexpeak. */
3391 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3392 {
3393 struct drm_device *dev = crtc->dev;
3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3396 int pipe = intel_crtc->pipe;
3397 i915_reg_t reg;
3398 u32 temp, tries;
3399
3400 /* FDI needs bits from pipe first */
3401 assert_pipe_enabled(dev_priv, pipe);
3402
3403 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3404 for train result */
3405 reg = FDI_RX_IMR(pipe);
3406 temp = I915_READ(reg);
3407 temp &= ~FDI_RX_SYMBOL_LOCK;
3408 temp &= ~FDI_RX_BIT_LOCK;
3409 I915_WRITE(reg, temp);
3410 I915_READ(reg);
3411 udelay(150);
3412
3413 /* enable CPU FDI TX and PCH FDI RX */
3414 reg = FDI_TX_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3417 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3418 temp &= ~FDI_LINK_TRAIN_NONE;
3419 temp |= FDI_LINK_TRAIN_PATTERN_1;
3420 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3421
3422 reg = FDI_RX_CTL(pipe);
3423 temp = I915_READ(reg);
3424 temp &= ~FDI_LINK_TRAIN_NONE;
3425 temp |= FDI_LINK_TRAIN_PATTERN_1;
3426 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3427
3428 POSTING_READ(reg);
3429 udelay(150);
3430
3431 /* Ironlake workaround, enable clock pointer after FDI enable*/
3432 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3433 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3434 FDI_RX_PHASE_SYNC_POINTER_EN);
3435
3436 reg = FDI_RX_IIR(pipe);
3437 for (tries = 0; tries < 5; tries++) {
3438 temp = I915_READ(reg);
3439 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3440
3441 if ((temp & FDI_RX_BIT_LOCK)) {
3442 DRM_DEBUG_KMS("FDI train 1 done.\n");
3443 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3444 break;
3445 }
3446 }
3447 if (tries == 5)
3448 DRM_ERROR("FDI train 1 fail!\n");
3449
3450 /* Train 2 */
3451 reg = FDI_TX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_2;
3455 I915_WRITE(reg, temp);
3456
3457 reg = FDI_RX_CTL(pipe);
3458 temp = I915_READ(reg);
3459 temp &= ~FDI_LINK_TRAIN_NONE;
3460 temp |= FDI_LINK_TRAIN_PATTERN_2;
3461 I915_WRITE(reg, temp);
3462
3463 POSTING_READ(reg);
3464 udelay(150);
3465
3466 reg = FDI_RX_IIR(pipe);
3467 for (tries = 0; tries < 5; tries++) {
3468 temp = I915_READ(reg);
3469 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3470
3471 if (temp & FDI_RX_SYMBOL_LOCK) {
3472 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3473 DRM_DEBUG_KMS("FDI train 2 done.\n");
3474 break;
3475 }
3476 }
3477 if (tries == 5)
3478 DRM_ERROR("FDI train 2 fail!\n");
3479
3480 DRM_DEBUG_KMS("FDI train done\n");
3481
3482 }
3483
3484 static const int snb_b_fdi_train_param[] = {
3485 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3486 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3487 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3488 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3489 };
3490
3491 /* The FDI link training functions for SNB/Cougarpoint. */
3492 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3493 {
3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3497 int pipe = intel_crtc->pipe;
3498 i915_reg_t reg;
3499 u32 temp, i, retry;
3500
3501 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3502 for train result */
3503 reg = FDI_RX_IMR(pipe);
3504 temp = I915_READ(reg);
3505 temp &= ~FDI_RX_SYMBOL_LOCK;
3506 temp &= ~FDI_RX_BIT_LOCK;
3507 I915_WRITE(reg, temp);
3508
3509 POSTING_READ(reg);
3510 udelay(150);
3511
3512 /* enable CPU FDI TX and PCH FDI RX */
3513 reg = FDI_TX_CTL(pipe);
3514 temp = I915_READ(reg);
3515 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3516 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3517 temp &= ~FDI_LINK_TRAIN_NONE;
3518 temp |= FDI_LINK_TRAIN_PATTERN_1;
3519 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3520 /* SNB-B */
3521 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3522 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3523
3524 I915_WRITE(FDI_RX_MISC(pipe),
3525 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3526
3527 reg = FDI_RX_CTL(pipe);
3528 temp = I915_READ(reg);
3529 if (HAS_PCH_CPT(dev)) {
3530 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3532 } else {
3533 temp &= ~FDI_LINK_TRAIN_NONE;
3534 temp |= FDI_LINK_TRAIN_PATTERN_1;
3535 }
3536 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3537
3538 POSTING_READ(reg);
3539 udelay(150);
3540
3541 for (i = 0; i < 4; i++) {
3542 reg = FDI_TX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3545 temp |= snb_b_fdi_train_param[i];
3546 I915_WRITE(reg, temp);
3547
3548 POSTING_READ(reg);
3549 udelay(500);
3550
3551 for (retry = 0; retry < 5; retry++) {
3552 reg = FDI_RX_IIR(pipe);
3553 temp = I915_READ(reg);
3554 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3555 if (temp & FDI_RX_BIT_LOCK) {
3556 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3557 DRM_DEBUG_KMS("FDI train 1 done.\n");
3558 break;
3559 }
3560 udelay(50);
3561 }
3562 if (retry < 5)
3563 break;
3564 }
3565 if (i == 4)
3566 DRM_ERROR("FDI train 1 fail!\n");
3567
3568 /* Train 2 */
3569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~FDI_LINK_TRAIN_NONE;
3572 temp |= FDI_LINK_TRAIN_PATTERN_2;
3573 if (IS_GEN6(dev)) {
3574 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3575 /* SNB-B */
3576 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3577 }
3578 I915_WRITE(reg, temp);
3579
3580 reg = FDI_RX_CTL(pipe);
3581 temp = I915_READ(reg);
3582 if (HAS_PCH_CPT(dev)) {
3583 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3584 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3585 } else {
3586 temp &= ~FDI_LINK_TRAIN_NONE;
3587 temp |= FDI_LINK_TRAIN_PATTERN_2;
3588 }
3589 I915_WRITE(reg, temp);
3590
3591 POSTING_READ(reg);
3592 udelay(150);
3593
3594 for (i = 0; i < 4; i++) {
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3598 temp |= snb_b_fdi_train_param[i];
3599 I915_WRITE(reg, temp);
3600
3601 POSTING_READ(reg);
3602 udelay(500);
3603
3604 for (retry = 0; retry < 5; retry++) {
3605 reg = FDI_RX_IIR(pipe);
3606 temp = I915_READ(reg);
3607 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3608 if (temp & FDI_RX_SYMBOL_LOCK) {
3609 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3610 DRM_DEBUG_KMS("FDI train 2 done.\n");
3611 break;
3612 }
3613 udelay(50);
3614 }
3615 if (retry < 5)
3616 break;
3617 }
3618 if (i == 4)
3619 DRM_ERROR("FDI train 2 fail!\n");
3620
3621 DRM_DEBUG_KMS("FDI train done.\n");
3622 }
3623
3624 /* Manual link training for Ivy Bridge A0 parts */
3625 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3626 {
3627 struct drm_device *dev = crtc->dev;
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3630 int pipe = intel_crtc->pipe;
3631 i915_reg_t reg;
3632 u32 temp, i, j;
3633
3634 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3635 for train result */
3636 reg = FDI_RX_IMR(pipe);
3637 temp = I915_READ(reg);
3638 temp &= ~FDI_RX_SYMBOL_LOCK;
3639 temp &= ~FDI_RX_BIT_LOCK;
3640 I915_WRITE(reg, temp);
3641
3642 POSTING_READ(reg);
3643 udelay(150);
3644
3645 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3646 I915_READ(FDI_RX_IIR(pipe)));
3647
3648 /* Try each vswing and preemphasis setting twice before moving on */
3649 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3650 /* disable first in case we need to retry */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3654 temp &= ~FDI_TX_ENABLE;
3655 I915_WRITE(reg, temp);
3656
3657 reg = FDI_RX_CTL(pipe);
3658 temp = I915_READ(reg);
3659 temp &= ~FDI_LINK_TRAIN_AUTO;
3660 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3661 temp &= ~FDI_RX_ENABLE;
3662 I915_WRITE(reg, temp);
3663
3664 /* enable CPU FDI TX and PCH FDI RX */
3665 reg = FDI_TX_CTL(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3668 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3669 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3670 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3671 temp |= snb_b_fdi_train_param[j/2];
3672 temp |= FDI_COMPOSITE_SYNC;
3673 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3674
3675 I915_WRITE(FDI_RX_MISC(pipe),
3676 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3677
3678 reg = FDI_RX_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3681 temp |= FDI_COMPOSITE_SYNC;
3682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3683
3684 POSTING_READ(reg);
3685 udelay(1); /* should be 0.5us */
3686
3687 for (i = 0; i < 4; i++) {
3688 reg = FDI_RX_IIR(pipe);
3689 temp = I915_READ(reg);
3690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3691
3692 if (temp & FDI_RX_BIT_LOCK ||
3693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3696 i);
3697 break;
3698 }
3699 udelay(1); /* should be 0.5us */
3700 }
3701 if (i == 4) {
3702 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3703 continue;
3704 }
3705
3706 /* Train 2 */
3707 reg = FDI_TX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3710 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3711 I915_WRITE(reg, temp);
3712
3713 reg = FDI_RX_CTL(pipe);
3714 temp = I915_READ(reg);
3715 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3716 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3717 I915_WRITE(reg, temp);
3718
3719 POSTING_READ(reg);
3720 udelay(2); /* should be 1.5us */
3721
3722 for (i = 0; i < 4; i++) {
3723 reg = FDI_RX_IIR(pipe);
3724 temp = I915_READ(reg);
3725 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3726
3727 if (temp & FDI_RX_SYMBOL_LOCK ||
3728 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3729 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3730 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3731 i);
3732 goto train_done;
3733 }
3734 udelay(2); /* should be 1.5us */
3735 }
3736 if (i == 4)
3737 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3738 }
3739
3740 train_done:
3741 DRM_DEBUG_KMS("FDI train done.\n");
3742 }
3743
3744 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3745 {
3746 struct drm_device *dev = intel_crtc->base.dev;
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 int pipe = intel_crtc->pipe;
3749 i915_reg_t reg;
3750 u32 temp;
3751
3752 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3753 reg = FDI_RX_CTL(pipe);
3754 temp = I915_READ(reg);
3755 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3756 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3758 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3759
3760 POSTING_READ(reg);
3761 udelay(200);
3762
3763 /* Switch from Rawclk to PCDclk */
3764 temp = I915_READ(reg);
3765 I915_WRITE(reg, temp | FDI_PCDCLK);
3766
3767 POSTING_READ(reg);
3768 udelay(200);
3769
3770 /* Enable CPU FDI TX PLL, always on for Ironlake */
3771 reg = FDI_TX_CTL(pipe);
3772 temp = I915_READ(reg);
3773 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3774 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3775
3776 POSTING_READ(reg);
3777 udelay(100);
3778 }
3779 }
3780
3781 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3782 {
3783 struct drm_device *dev = intel_crtc->base.dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 int pipe = intel_crtc->pipe;
3786 i915_reg_t reg;
3787 u32 temp;
3788
3789 /* Switch from PCDclk to Rawclk */
3790 reg = FDI_RX_CTL(pipe);
3791 temp = I915_READ(reg);
3792 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3793
3794 /* Disable CPU FDI TX PLL */
3795 reg = FDI_TX_CTL(pipe);
3796 temp = I915_READ(reg);
3797 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3798
3799 POSTING_READ(reg);
3800 udelay(100);
3801
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3805
3806 /* Wait for the clocks to turn off. */
3807 POSTING_READ(reg);
3808 udelay(100);
3809 }
3810
3811 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3812 {
3813 struct drm_device *dev = crtc->dev;
3814 struct drm_i915_private *dev_priv = dev->dev_private;
3815 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3816 int pipe = intel_crtc->pipe;
3817 i915_reg_t reg;
3818 u32 temp;
3819
3820 /* disable CPU FDI tx and PCH FDI rx */
3821 reg = FDI_TX_CTL(pipe);
3822 temp = I915_READ(reg);
3823 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3824 POSTING_READ(reg);
3825
3826 reg = FDI_RX_CTL(pipe);
3827 temp = I915_READ(reg);
3828 temp &= ~(0x7 << 16);
3829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3830 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3831
3832 POSTING_READ(reg);
3833 udelay(100);
3834
3835 /* Ironlake workaround, disable clock pointer after downing FDI */
3836 if (HAS_PCH_IBX(dev))
3837 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3838
3839 /* still set train pattern 1 */
3840 reg = FDI_TX_CTL(pipe);
3841 temp = I915_READ(reg);
3842 temp &= ~FDI_LINK_TRAIN_NONE;
3843 temp |= FDI_LINK_TRAIN_PATTERN_1;
3844 I915_WRITE(reg, temp);
3845
3846 reg = FDI_RX_CTL(pipe);
3847 temp = I915_READ(reg);
3848 if (HAS_PCH_CPT(dev)) {
3849 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3850 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3851 } else {
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 }
3855 /* BPC in FDI rx is consistent with that in PIPECONF */
3856 temp &= ~(0x07 << 16);
3857 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3858 I915_WRITE(reg, temp);
3859
3860 POSTING_READ(reg);
3861 udelay(100);
3862 }
3863
3864 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3865 {
3866 struct intel_crtc *crtc;
3867
3868 /* Note that we don't need to be called with mode_config.lock here
3869 * as our list of CRTC objects is static for the lifetime of the
3870 * device and so cannot disappear as we iterate. Similarly, we can
3871 * happily treat the predicates as racy, atomic checks as userspace
3872 * cannot claim and pin a new fb without at least acquring the
3873 * struct_mutex and so serialising with us.
3874 */
3875 for_each_intel_crtc(dev, crtc) {
3876 if (atomic_read(&crtc->unpin_work_count) == 0)
3877 continue;
3878
3879 if (crtc->unpin_work)
3880 intel_wait_for_vblank(dev, crtc->pipe);
3881
3882 return true;
3883 }
3884
3885 return false;
3886 }
3887
3888 static void page_flip_completed(struct intel_crtc *intel_crtc)
3889 {
3890 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3891 struct intel_unpin_work *work = intel_crtc->unpin_work;
3892
3893 /* ensure that the unpin work is consistent wrt ->pending. */
3894 smp_rmb();
3895 intel_crtc->unpin_work = NULL;
3896
3897 if (work->event)
3898 drm_send_vblank_event(intel_crtc->base.dev,
3899 intel_crtc->pipe,
3900 work->event);
3901
3902 drm_crtc_vblank_put(&intel_crtc->base);
3903
3904 wake_up_all(&dev_priv->pending_flip_queue);
3905 queue_work(dev_priv->wq, &work->work);
3906
3907 trace_i915_flip_complete(intel_crtc->plane,
3908 work->pending_flip_obj);
3909 }
3910
3911 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3912 {
3913 struct drm_device *dev = crtc->dev;
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 long ret;
3916
3917 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3918
3919 ret = wait_event_interruptible_timeout(
3920 dev_priv->pending_flip_queue,
3921 !intel_crtc_has_pending_flip(crtc),
3922 60*HZ);
3923
3924 if (ret < 0)
3925 return ret;
3926
3927 if (ret == 0) {
3928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929
3930 spin_lock_irq(&dev->event_lock);
3931 if (intel_crtc->unpin_work) {
3932 WARN_ONCE(1, "Removing stuck page flip\n");
3933 page_flip_completed(intel_crtc);
3934 }
3935 spin_unlock_irq(&dev->event_lock);
3936 }
3937
3938 return 0;
3939 }
3940
3941 /* Program iCLKIP clock to the desired frequency */
3942 static void lpt_program_iclkip(struct drm_crtc *crtc)
3943 {
3944 struct drm_device *dev = crtc->dev;
3945 struct drm_i915_private *dev_priv = dev->dev_private;
3946 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3947 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3948 u32 temp;
3949
3950 mutex_lock(&dev_priv->sb_lock);
3951
3952 /* It is necessary to ungate the pixclk gate prior to programming
3953 * the divisors, and gate it back when it is done.
3954 */
3955 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3956
3957 /* Disable SSCCTL */
3958 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3959 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3960 SBI_SSCCTL_DISABLE,
3961 SBI_ICLK);
3962
3963 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3964 if (clock == 20000) {
3965 auxdiv = 1;
3966 divsel = 0x41;
3967 phaseinc = 0x20;
3968 } else {
3969 /* The iCLK virtual clock root frequency is in MHz,
3970 * but the adjusted_mode->crtc_clock in in KHz. To get the
3971 * divisors, it is necessary to divide one by another, so we
3972 * convert the virtual clock precision to KHz here for higher
3973 * precision.
3974 */
3975 u32 iclk_virtual_root_freq = 172800 * 1000;
3976 u32 iclk_pi_range = 64;
3977 u32 desired_divisor, msb_divisor_value, pi_value;
3978
3979 desired_divisor = (iclk_virtual_root_freq / clock);
3980 msb_divisor_value = desired_divisor / iclk_pi_range;
3981 pi_value = desired_divisor % iclk_pi_range;
3982
3983 auxdiv = 0;
3984 divsel = msb_divisor_value - 2;
3985 phaseinc = pi_value;
3986 }
3987
3988 /* This should not happen with any sane values */
3989 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3990 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3991 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3992 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3993
3994 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3995 clock,
3996 auxdiv,
3997 divsel,
3998 phasedir,
3999 phaseinc);
4000
4001 /* Program SSCDIVINTPHASE6 */
4002 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4003 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4004 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4005 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4006 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4007 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4008 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4009 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4010
4011 /* Program SSCAUXDIV */
4012 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4013 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4014 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4015 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4016
4017 /* Enable modulator and associated divider */
4018 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4019 temp &= ~SBI_SSCCTL_DISABLE;
4020 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4021
4022 /* Wait for initialization time */
4023 udelay(24);
4024
4025 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4026
4027 mutex_unlock(&dev_priv->sb_lock);
4028 }
4029
4030 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4031 enum pipe pch_transcoder)
4032 {
4033 struct drm_device *dev = crtc->base.dev;
4034 struct drm_i915_private *dev_priv = dev->dev_private;
4035 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4036
4037 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4038 I915_READ(HTOTAL(cpu_transcoder)));
4039 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4040 I915_READ(HBLANK(cpu_transcoder)));
4041 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4042 I915_READ(HSYNC(cpu_transcoder)));
4043
4044 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4045 I915_READ(VTOTAL(cpu_transcoder)));
4046 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4047 I915_READ(VBLANK(cpu_transcoder)));
4048 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4049 I915_READ(VSYNC(cpu_transcoder)));
4050 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4051 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4052 }
4053
4054 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4055 {
4056 struct drm_i915_private *dev_priv = dev->dev_private;
4057 uint32_t temp;
4058
4059 temp = I915_READ(SOUTH_CHICKEN1);
4060 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4061 return;
4062
4063 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4064 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4065
4066 temp &= ~FDI_BC_BIFURCATION_SELECT;
4067 if (enable)
4068 temp |= FDI_BC_BIFURCATION_SELECT;
4069
4070 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4071 I915_WRITE(SOUTH_CHICKEN1, temp);
4072 POSTING_READ(SOUTH_CHICKEN1);
4073 }
4074
4075 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4076 {
4077 struct drm_device *dev = intel_crtc->base.dev;
4078
4079 switch (intel_crtc->pipe) {
4080 case PIPE_A:
4081 break;
4082 case PIPE_B:
4083 if (intel_crtc->config->fdi_lanes > 2)
4084 cpt_set_fdi_bc_bifurcation(dev, false);
4085 else
4086 cpt_set_fdi_bc_bifurcation(dev, true);
4087
4088 break;
4089 case PIPE_C:
4090 cpt_set_fdi_bc_bifurcation(dev, true);
4091
4092 break;
4093 default:
4094 BUG();
4095 }
4096 }
4097
4098 /* Return which DP Port should be selected for Transcoder DP control */
4099 static enum port
4100 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4101 {
4102 struct drm_device *dev = crtc->dev;
4103 struct intel_encoder *encoder;
4104
4105 for_each_encoder_on_crtc(dev, crtc, encoder) {
4106 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4107 encoder->type == INTEL_OUTPUT_EDP)
4108 return enc_to_dig_port(&encoder->base)->port;
4109 }
4110
4111 return -1;
4112 }
4113
4114 /*
4115 * Enable PCH resources required for PCH ports:
4116 * - PCH PLLs
4117 * - FDI training & RX/TX
4118 * - update transcoder timings
4119 * - DP transcoding bits
4120 * - transcoder
4121 */
4122 static void ironlake_pch_enable(struct drm_crtc *crtc)
4123 {
4124 struct drm_device *dev = crtc->dev;
4125 struct drm_i915_private *dev_priv = dev->dev_private;
4126 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4127 int pipe = intel_crtc->pipe;
4128 u32 temp;
4129
4130 assert_pch_transcoder_disabled(dev_priv, pipe);
4131
4132 if (IS_IVYBRIDGE(dev))
4133 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4134
4135 /* Write the TU size bits before fdi link training, so that error
4136 * detection works. */
4137 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4138 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4139
4140 /* For PCH output, training FDI link */
4141 dev_priv->display.fdi_link_train(crtc);
4142
4143 /* We need to program the right clock selection before writing the pixel
4144 * mutliplier into the DPLL. */
4145 if (HAS_PCH_CPT(dev)) {
4146 u32 sel;
4147
4148 temp = I915_READ(PCH_DPLL_SEL);
4149 temp |= TRANS_DPLL_ENABLE(pipe);
4150 sel = TRANS_DPLLB_SEL(pipe);
4151 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4152 temp |= sel;
4153 else
4154 temp &= ~sel;
4155 I915_WRITE(PCH_DPLL_SEL, temp);
4156 }
4157
4158 /* XXX: pch pll's can be enabled any time before we enable the PCH
4159 * transcoder, and we actually should do this to not upset any PCH
4160 * transcoder that already use the clock when we share it.
4161 *
4162 * Note that enable_shared_dpll tries to do the right thing, but
4163 * get_shared_dpll unconditionally resets the pll - we need that to have
4164 * the right LVDS enable sequence. */
4165 intel_enable_shared_dpll(intel_crtc);
4166
4167 /* set transcoder timing, panel must allow it */
4168 assert_panel_unlocked(dev_priv, pipe);
4169 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4170
4171 intel_fdi_normal_train(crtc);
4172
4173 /* For PCH DP, enable TRANS_DP_CTL */
4174 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4175 const struct drm_display_mode *adjusted_mode =
4176 &intel_crtc->config->base.adjusted_mode;
4177 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4178 i915_reg_t reg = TRANS_DP_CTL(pipe);
4179 temp = I915_READ(reg);
4180 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4181 TRANS_DP_SYNC_MASK |
4182 TRANS_DP_BPC_MASK);
4183 temp |= TRANS_DP_OUTPUT_ENABLE;
4184 temp |= bpc << 9; /* same format but at 11:9 */
4185
4186 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4187 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4188 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4189 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4190
4191 switch (intel_trans_dp_port_sel(crtc)) {
4192 case PORT_B:
4193 temp |= TRANS_DP_PORT_SEL_B;
4194 break;
4195 case PORT_C:
4196 temp |= TRANS_DP_PORT_SEL_C;
4197 break;
4198 case PORT_D:
4199 temp |= TRANS_DP_PORT_SEL_D;
4200 break;
4201 default:
4202 BUG();
4203 }
4204
4205 I915_WRITE(reg, temp);
4206 }
4207
4208 ironlake_enable_pch_transcoder(dev_priv, pipe);
4209 }
4210
4211 static void lpt_pch_enable(struct drm_crtc *crtc)
4212 {
4213 struct drm_device *dev = crtc->dev;
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4216 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4217
4218 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4219
4220 lpt_program_iclkip(crtc);
4221
4222 /* Set transcoder timing. */
4223 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4224
4225 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4226 }
4227
4228 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4229 struct intel_crtc_state *crtc_state)
4230 {
4231 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4232 struct intel_shared_dpll *pll;
4233 struct intel_shared_dpll_config *shared_dpll;
4234 enum intel_dpll_id i;
4235 int max = dev_priv->num_shared_dpll;
4236
4237 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4238
4239 if (HAS_PCH_IBX(dev_priv->dev)) {
4240 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4241 i = (enum intel_dpll_id) crtc->pipe;
4242 pll = &dev_priv->shared_dplls[i];
4243
4244 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4245 crtc->base.base.id, pll->name);
4246
4247 WARN_ON(shared_dpll[i].crtc_mask);
4248
4249 goto found;
4250 }
4251
4252 if (IS_BROXTON(dev_priv->dev)) {
4253 /* PLL is attached to port in bxt */
4254 struct intel_encoder *encoder;
4255 struct intel_digital_port *intel_dig_port;
4256
4257 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4258 if (WARN_ON(!encoder))
4259 return NULL;
4260
4261 intel_dig_port = enc_to_dig_port(&encoder->base);
4262 /* 1:1 mapping between ports and PLLs */
4263 i = (enum intel_dpll_id)intel_dig_port->port;
4264 pll = &dev_priv->shared_dplls[i];
4265 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4266 crtc->base.base.id, pll->name);
4267 WARN_ON(shared_dpll[i].crtc_mask);
4268
4269 goto found;
4270 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4271 /* Do not consider SPLL */
4272 max = 2;
4273
4274 for (i = 0; i < max; i++) {
4275 pll = &dev_priv->shared_dplls[i];
4276
4277 /* Only want to check enabled timings first */
4278 if (shared_dpll[i].crtc_mask == 0)
4279 continue;
4280
4281 if (memcmp(&crtc_state->dpll_hw_state,
4282 &shared_dpll[i].hw_state,
4283 sizeof(crtc_state->dpll_hw_state)) == 0) {
4284 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4285 crtc->base.base.id, pll->name,
4286 shared_dpll[i].crtc_mask,
4287 pll->active);
4288 goto found;
4289 }
4290 }
4291
4292 /* Ok no matching timings, maybe there's a free one? */
4293 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4294 pll = &dev_priv->shared_dplls[i];
4295 if (shared_dpll[i].crtc_mask == 0) {
4296 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4297 crtc->base.base.id, pll->name);
4298 goto found;
4299 }
4300 }
4301
4302 return NULL;
4303
4304 found:
4305 if (shared_dpll[i].crtc_mask == 0)
4306 shared_dpll[i].hw_state =
4307 crtc_state->dpll_hw_state;
4308
4309 crtc_state->shared_dpll = i;
4310 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4311 pipe_name(crtc->pipe));
4312
4313 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4314
4315 return pll;
4316 }
4317
4318 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4319 {
4320 struct drm_i915_private *dev_priv = to_i915(state->dev);
4321 struct intel_shared_dpll_config *shared_dpll;
4322 struct intel_shared_dpll *pll;
4323 enum intel_dpll_id i;
4324
4325 if (!to_intel_atomic_state(state)->dpll_set)
4326 return;
4327
4328 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4329 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4330 pll = &dev_priv->shared_dplls[i];
4331 pll->config = shared_dpll[i];
4332 }
4333 }
4334
4335 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4336 {
4337 struct drm_i915_private *dev_priv = dev->dev_private;
4338 i915_reg_t dslreg = PIPEDSL(pipe);
4339 u32 temp;
4340
4341 temp = I915_READ(dslreg);
4342 udelay(500);
4343 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4344 if (wait_for(I915_READ(dslreg) != temp, 5))
4345 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4346 }
4347 }
4348
4349 static int
4350 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4351 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4352 int src_w, int src_h, int dst_w, int dst_h)
4353 {
4354 struct intel_crtc_scaler_state *scaler_state =
4355 &crtc_state->scaler_state;
4356 struct intel_crtc *intel_crtc =
4357 to_intel_crtc(crtc_state->base.crtc);
4358 int need_scaling;
4359
4360 need_scaling = intel_rotation_90_or_270(rotation) ?
4361 (src_h != dst_w || src_w != dst_h):
4362 (src_w != dst_w || src_h != dst_h);
4363
4364 /*
4365 * if plane is being disabled or scaler is no more required or force detach
4366 * - free scaler binded to this plane/crtc
4367 * - in order to do this, update crtc->scaler_usage
4368 *
4369 * Here scaler state in crtc_state is set free so that
4370 * scaler can be assigned to other user. Actual register
4371 * update to free the scaler is done in plane/panel-fit programming.
4372 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4373 */
4374 if (force_detach || !need_scaling) {
4375 if (*scaler_id >= 0) {
4376 scaler_state->scaler_users &= ~(1 << scaler_user);
4377 scaler_state->scalers[*scaler_id].in_use = 0;
4378
4379 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4380 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4381 intel_crtc->pipe, scaler_user, *scaler_id,
4382 scaler_state->scaler_users);
4383 *scaler_id = -1;
4384 }
4385 return 0;
4386 }
4387
4388 /* range checks */
4389 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4390 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4391
4392 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4393 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4394 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4395 "size is out of scaler range\n",
4396 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4397 return -EINVAL;
4398 }
4399
4400 /* mark this plane as a scaler user in crtc_state */
4401 scaler_state->scaler_users |= (1 << scaler_user);
4402 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4403 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4404 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4405 scaler_state->scaler_users);
4406
4407 return 0;
4408 }
4409
4410 /**
4411 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4412 *
4413 * @state: crtc's scaler state
4414 *
4415 * Return
4416 * 0 - scaler_usage updated successfully
4417 * error - requested scaling cannot be supported or other error condition
4418 */
4419 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4420 {
4421 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4422 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4423
4424 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4425 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4426
4427 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4428 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4429 state->pipe_src_w, state->pipe_src_h,
4430 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4431 }
4432
4433 /**
4434 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4435 *
4436 * @state: crtc's scaler state
4437 * @plane_state: atomic plane state to update
4438 *
4439 * Return
4440 * 0 - scaler_usage updated successfully
4441 * error - requested scaling cannot be supported or other error condition
4442 */
4443 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4444 struct intel_plane_state *plane_state)
4445 {
4446
4447 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4448 struct intel_plane *intel_plane =
4449 to_intel_plane(plane_state->base.plane);
4450 struct drm_framebuffer *fb = plane_state->base.fb;
4451 int ret;
4452
4453 bool force_detach = !fb || !plane_state->visible;
4454
4455 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4456 intel_plane->base.base.id, intel_crtc->pipe,
4457 drm_plane_index(&intel_plane->base));
4458
4459 ret = skl_update_scaler(crtc_state, force_detach,
4460 drm_plane_index(&intel_plane->base),
4461 &plane_state->scaler_id,
4462 plane_state->base.rotation,
4463 drm_rect_width(&plane_state->src) >> 16,
4464 drm_rect_height(&plane_state->src) >> 16,
4465 drm_rect_width(&plane_state->dst),
4466 drm_rect_height(&plane_state->dst));
4467
4468 if (ret || plane_state->scaler_id < 0)
4469 return ret;
4470
4471 /* check colorkey */
4472 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4473 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4474 intel_plane->base.base.id);
4475 return -EINVAL;
4476 }
4477
4478 /* Check src format */
4479 switch (fb->pixel_format) {
4480 case DRM_FORMAT_RGB565:
4481 case DRM_FORMAT_XBGR8888:
4482 case DRM_FORMAT_XRGB8888:
4483 case DRM_FORMAT_ABGR8888:
4484 case DRM_FORMAT_ARGB8888:
4485 case DRM_FORMAT_XRGB2101010:
4486 case DRM_FORMAT_XBGR2101010:
4487 case DRM_FORMAT_YUYV:
4488 case DRM_FORMAT_YVYU:
4489 case DRM_FORMAT_UYVY:
4490 case DRM_FORMAT_VYUY:
4491 break;
4492 default:
4493 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4494 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4495 return -EINVAL;
4496 }
4497
4498 return 0;
4499 }
4500
4501 static void skylake_scaler_disable(struct intel_crtc *crtc)
4502 {
4503 int i;
4504
4505 for (i = 0; i < crtc->num_scalers; i++)
4506 skl_detach_scaler(crtc, i);
4507 }
4508
4509 static void skylake_pfit_enable(struct intel_crtc *crtc)
4510 {
4511 struct drm_device *dev = crtc->base.dev;
4512 struct drm_i915_private *dev_priv = dev->dev_private;
4513 int pipe = crtc->pipe;
4514 struct intel_crtc_scaler_state *scaler_state =
4515 &crtc->config->scaler_state;
4516
4517 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4518
4519 if (crtc->config->pch_pfit.enabled) {
4520 int id;
4521
4522 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4523 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4524 return;
4525 }
4526
4527 id = scaler_state->scaler_id;
4528 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4529 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4530 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4531 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4532
4533 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4534 }
4535 }
4536
4537 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4538 {
4539 struct drm_device *dev = crtc->base.dev;
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 int pipe = crtc->pipe;
4542
4543 if (crtc->config->pch_pfit.enabled) {
4544 /* Force use of hard-coded filter coefficients
4545 * as some pre-programmed values are broken,
4546 * e.g. x201.
4547 */
4548 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4549 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4550 PF_PIPE_SEL_IVB(pipe));
4551 else
4552 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4553 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4554 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4555 }
4556 }
4557
4558 void hsw_enable_ips(struct intel_crtc *crtc)
4559 {
4560 struct drm_device *dev = crtc->base.dev;
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562
4563 if (!crtc->config->ips_enabled)
4564 return;
4565
4566 /* We can only enable IPS after we enable a plane and wait for a vblank */
4567 intel_wait_for_vblank(dev, crtc->pipe);
4568
4569 assert_plane_enabled(dev_priv, crtc->plane);
4570 if (IS_BROADWELL(dev)) {
4571 mutex_lock(&dev_priv->rps.hw_lock);
4572 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4573 mutex_unlock(&dev_priv->rps.hw_lock);
4574 /* Quoting Art Runyan: "its not safe to expect any particular
4575 * value in IPS_CTL bit 31 after enabling IPS through the
4576 * mailbox." Moreover, the mailbox may return a bogus state,
4577 * so we need to just enable it and continue on.
4578 */
4579 } else {
4580 I915_WRITE(IPS_CTL, IPS_ENABLE);
4581 /* The bit only becomes 1 in the next vblank, so this wait here
4582 * is essentially intel_wait_for_vblank. If we don't have this
4583 * and don't wait for vblanks until the end of crtc_enable, then
4584 * the HW state readout code will complain that the expected
4585 * IPS_CTL value is not the one we read. */
4586 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4587 DRM_ERROR("Timed out waiting for IPS enable\n");
4588 }
4589 }
4590
4591 void hsw_disable_ips(struct intel_crtc *crtc)
4592 {
4593 struct drm_device *dev = crtc->base.dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595
4596 if (!crtc->config->ips_enabled)
4597 return;
4598
4599 assert_plane_enabled(dev_priv, crtc->plane);
4600 if (IS_BROADWELL(dev)) {
4601 mutex_lock(&dev_priv->rps.hw_lock);
4602 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4603 mutex_unlock(&dev_priv->rps.hw_lock);
4604 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4605 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4606 DRM_ERROR("Timed out waiting for IPS disable\n");
4607 } else {
4608 I915_WRITE(IPS_CTL, 0);
4609 POSTING_READ(IPS_CTL);
4610 }
4611
4612 /* We need to wait for a vblank before we can disable the plane. */
4613 intel_wait_for_vblank(dev, crtc->pipe);
4614 }
4615
4616 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4617 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4618 {
4619 struct drm_device *dev = crtc->dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4622 enum pipe pipe = intel_crtc->pipe;
4623 int i;
4624 bool reenable_ips = false;
4625
4626 /* The clocks have to be on to load the palette. */
4627 if (!crtc->state->active)
4628 return;
4629
4630 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4631 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4632 assert_dsi_pll_enabled(dev_priv);
4633 else
4634 assert_pll_enabled(dev_priv, pipe);
4635 }
4636
4637 /* Workaround : Do not read or write the pipe palette/gamma data while
4638 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4639 */
4640 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4641 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4642 GAMMA_MODE_MODE_SPLIT)) {
4643 hsw_disable_ips(intel_crtc);
4644 reenable_ips = true;
4645 }
4646
4647 for (i = 0; i < 256; i++) {
4648 i915_reg_t palreg;
4649
4650 if (HAS_GMCH_DISPLAY(dev))
4651 palreg = PALETTE(pipe, i);
4652 else
4653 palreg = LGC_PALETTE(pipe, i);
4654
4655 I915_WRITE(palreg,
4656 (intel_crtc->lut_r[i] << 16) |
4657 (intel_crtc->lut_g[i] << 8) |
4658 intel_crtc->lut_b[i]);
4659 }
4660
4661 if (reenable_ips)
4662 hsw_enable_ips(intel_crtc);
4663 }
4664
4665 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4666 {
4667 if (intel_crtc->overlay) {
4668 struct drm_device *dev = intel_crtc->base.dev;
4669 struct drm_i915_private *dev_priv = dev->dev_private;
4670
4671 mutex_lock(&dev->struct_mutex);
4672 dev_priv->mm.interruptible = false;
4673 (void) intel_overlay_switch_off(intel_crtc->overlay);
4674 dev_priv->mm.interruptible = true;
4675 mutex_unlock(&dev->struct_mutex);
4676 }
4677
4678 /* Let userspace switch the overlay on again. In most cases userspace
4679 * has to recompute where to put it anyway.
4680 */
4681 }
4682
4683 /**
4684 * intel_post_enable_primary - Perform operations after enabling primary plane
4685 * @crtc: the CRTC whose primary plane was just enabled
4686 *
4687 * Performs potentially sleeping operations that must be done after the primary
4688 * plane is enabled, such as updating FBC and IPS. Note that this may be
4689 * called due to an explicit primary plane update, or due to an implicit
4690 * re-enable that is caused when a sprite plane is updated to no longer
4691 * completely hide the primary plane.
4692 */
4693 static void
4694 intel_post_enable_primary(struct drm_crtc *crtc)
4695 {
4696 struct drm_device *dev = crtc->dev;
4697 struct drm_i915_private *dev_priv = dev->dev_private;
4698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4699 int pipe = intel_crtc->pipe;
4700
4701 /*
4702 * BDW signals flip done immediately if the plane
4703 * is disabled, even if the plane enable is already
4704 * armed to occur at the next vblank :(
4705 */
4706 if (IS_BROADWELL(dev))
4707 intel_wait_for_vblank(dev, pipe);
4708
4709 /*
4710 * FIXME IPS should be fine as long as one plane is
4711 * enabled, but in practice it seems to have problems
4712 * when going from primary only to sprite only and vice
4713 * versa.
4714 */
4715 hsw_enable_ips(intel_crtc);
4716
4717 /*
4718 * Gen2 reports pipe underruns whenever all planes are disabled.
4719 * So don't enable underrun reporting before at least some planes
4720 * are enabled.
4721 * FIXME: Need to fix the logic to work when we turn off all planes
4722 * but leave the pipe running.
4723 */
4724 if (IS_GEN2(dev))
4725 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4726
4727 /* Underruns don't always raise interrupts, so check manually. */
4728 intel_check_cpu_fifo_underruns(dev_priv);
4729 intel_check_pch_fifo_underruns(dev_priv);
4730 }
4731
4732 /**
4733 * intel_pre_disable_primary - Perform operations before disabling primary plane
4734 * @crtc: the CRTC whose primary plane is to be disabled
4735 *
4736 * Performs potentially sleeping operations that must be done before the
4737 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4738 * be called due to an explicit primary plane update, or due to an implicit
4739 * disable that is caused when a sprite plane completely hides the primary
4740 * plane.
4741 */
4742 static void
4743 intel_pre_disable_primary(struct drm_crtc *crtc)
4744 {
4745 struct drm_device *dev = crtc->dev;
4746 struct drm_i915_private *dev_priv = dev->dev_private;
4747 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4748 int pipe = intel_crtc->pipe;
4749
4750 /*
4751 * Gen2 reports pipe underruns whenever all planes are disabled.
4752 * So diasble underrun reporting before all the planes get disabled.
4753 * FIXME: Need to fix the logic to work when we turn off all planes
4754 * but leave the pipe running.
4755 */
4756 if (IS_GEN2(dev))
4757 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4758
4759 /*
4760 * Vblank time updates from the shadow to live plane control register
4761 * are blocked if the memory self-refresh mode is active at that
4762 * moment. So to make sure the plane gets truly disabled, disable
4763 * first the self-refresh mode. The self-refresh enable bit in turn
4764 * will be checked/applied by the HW only at the next frame start
4765 * event which is after the vblank start event, so we need to have a
4766 * wait-for-vblank between disabling the plane and the pipe.
4767 */
4768 if (HAS_GMCH_DISPLAY(dev)) {
4769 intel_set_memory_cxsr(dev_priv, false);
4770 dev_priv->wm.vlv.cxsr = false;
4771 intel_wait_for_vblank(dev, pipe);
4772 }
4773
4774 /*
4775 * FIXME IPS should be fine as long as one plane is
4776 * enabled, but in practice it seems to have problems
4777 * when going from primary only to sprite only and vice
4778 * versa.
4779 */
4780 hsw_disable_ips(intel_crtc);
4781 }
4782
4783 static void intel_post_plane_update(struct intel_crtc *crtc)
4784 {
4785 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4786 struct drm_device *dev = crtc->base.dev;
4787 struct drm_i915_private *dev_priv = dev->dev_private;
4788
4789 if (atomic->wait_vblank)
4790 intel_wait_for_vblank(dev, crtc->pipe);
4791
4792 intel_frontbuffer_flip(dev, atomic->fb_bits);
4793
4794 if (atomic->disable_cxsr)
4795 crtc->wm.cxsr_allowed = true;
4796
4797 if (crtc->atomic.update_wm_post)
4798 intel_update_watermarks(&crtc->base);
4799
4800 if (atomic->update_fbc)
4801 intel_fbc_update(dev_priv);
4802
4803 if (atomic->post_enable_primary)
4804 intel_post_enable_primary(&crtc->base);
4805
4806 memset(atomic, 0, sizeof(*atomic));
4807 }
4808
4809 static void intel_pre_plane_update(struct intel_crtc *crtc)
4810 {
4811 struct drm_device *dev = crtc->base.dev;
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4813 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4814
4815 if (atomic->disable_fbc)
4816 intel_fbc_disable_crtc(crtc);
4817
4818 if (crtc->atomic.disable_ips)
4819 hsw_disable_ips(crtc);
4820
4821 if (atomic->pre_disable_primary)
4822 intel_pre_disable_primary(&crtc->base);
4823
4824 if (atomic->disable_cxsr) {
4825 crtc->wm.cxsr_allowed = false;
4826 intel_set_memory_cxsr(dev_priv, false);
4827 }
4828 }
4829
4830 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4831 {
4832 struct drm_device *dev = crtc->dev;
4833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834 struct drm_plane *p;
4835 int pipe = intel_crtc->pipe;
4836
4837 intel_crtc_dpms_overlay_disable(intel_crtc);
4838
4839 drm_for_each_plane_mask(p, dev, plane_mask)
4840 to_intel_plane(p)->disable_plane(p, crtc);
4841
4842 /*
4843 * FIXME: Once we grow proper nuclear flip support out of this we need
4844 * to compute the mask of flip planes precisely. For the time being
4845 * consider this a flip to a NULL plane.
4846 */
4847 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4848 }
4849
4850 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4851 {
4852 struct drm_device *dev = crtc->dev;
4853 struct drm_i915_private *dev_priv = dev->dev_private;
4854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4855 struct intel_encoder *encoder;
4856 int pipe = intel_crtc->pipe;
4857
4858 if (WARN_ON(intel_crtc->active))
4859 return;
4860
4861 if (intel_crtc->config->has_pch_encoder)
4862 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4863
4864 if (intel_crtc->config->has_pch_encoder)
4865 intel_prepare_shared_dpll(intel_crtc);
4866
4867 if (intel_crtc->config->has_dp_encoder)
4868 intel_dp_set_m_n(intel_crtc, M1_N1);
4869
4870 intel_set_pipe_timings(intel_crtc);
4871
4872 if (intel_crtc->config->has_pch_encoder) {
4873 intel_cpu_transcoder_set_m_n(intel_crtc,
4874 &intel_crtc->config->fdi_m_n, NULL);
4875 }
4876
4877 ironlake_set_pipeconf(crtc);
4878
4879 intel_crtc->active = true;
4880
4881 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4882
4883 for_each_encoder_on_crtc(dev, crtc, encoder)
4884 if (encoder->pre_enable)
4885 encoder->pre_enable(encoder);
4886
4887 if (intel_crtc->config->has_pch_encoder) {
4888 /* Note: FDI PLL enabling _must_ be done before we enable the
4889 * cpu pipes, hence this is separate from all the other fdi/pch
4890 * enabling. */
4891 ironlake_fdi_pll_enable(intel_crtc);
4892 } else {
4893 assert_fdi_tx_disabled(dev_priv, pipe);
4894 assert_fdi_rx_disabled(dev_priv, pipe);
4895 }
4896
4897 ironlake_pfit_enable(intel_crtc);
4898
4899 /*
4900 * On ILK+ LUT must be loaded before the pipe is running but with
4901 * clocks enabled
4902 */
4903 intel_crtc_load_lut(crtc);
4904
4905 intel_update_watermarks(crtc);
4906 intel_enable_pipe(intel_crtc);
4907
4908 if (intel_crtc->config->has_pch_encoder)
4909 ironlake_pch_enable(crtc);
4910
4911 assert_vblank_disabled(crtc);
4912 drm_crtc_vblank_on(crtc);
4913
4914 for_each_encoder_on_crtc(dev, crtc, encoder)
4915 encoder->enable(encoder);
4916
4917 if (HAS_PCH_CPT(dev))
4918 cpt_verify_modeset(dev, intel_crtc->pipe);
4919
4920 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4921 if (intel_crtc->config->has_pch_encoder)
4922 intel_wait_for_vblank(dev, pipe);
4923 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4924 }
4925
4926 /* IPS only exists on ULT machines and is tied to pipe A. */
4927 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4928 {
4929 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4930 }
4931
4932 static void haswell_crtc_enable(struct drm_crtc *crtc)
4933 {
4934 struct drm_device *dev = crtc->dev;
4935 struct drm_i915_private *dev_priv = dev->dev_private;
4936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4937 struct intel_encoder *encoder;
4938 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4939 struct intel_crtc_state *pipe_config =
4940 to_intel_crtc_state(crtc->state);
4941 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4942
4943 if (WARN_ON(intel_crtc->active))
4944 return;
4945
4946 if (intel_crtc->config->has_pch_encoder)
4947 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4948 false);
4949
4950 if (intel_crtc_to_shared_dpll(intel_crtc))
4951 intel_enable_shared_dpll(intel_crtc);
4952
4953 if (intel_crtc->config->has_dp_encoder)
4954 intel_dp_set_m_n(intel_crtc, M1_N1);
4955
4956 intel_set_pipe_timings(intel_crtc);
4957
4958 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4959 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4960 intel_crtc->config->pixel_multiplier - 1);
4961 }
4962
4963 if (intel_crtc->config->has_pch_encoder) {
4964 intel_cpu_transcoder_set_m_n(intel_crtc,
4965 &intel_crtc->config->fdi_m_n, NULL);
4966 }
4967
4968 haswell_set_pipeconf(crtc);
4969
4970 intel_set_pipe_csc(crtc);
4971
4972 intel_crtc->active = true;
4973
4974 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4975 for_each_encoder_on_crtc(dev, crtc, encoder) {
4976 if (encoder->pre_pll_enable)
4977 encoder->pre_pll_enable(encoder);
4978 if (encoder->pre_enable)
4979 encoder->pre_enable(encoder);
4980 }
4981
4982 if (intel_crtc->config->has_pch_encoder)
4983 dev_priv->display.fdi_link_train(crtc);
4984
4985 if (!is_dsi)
4986 intel_ddi_enable_pipe_clock(intel_crtc);
4987
4988 if (INTEL_INFO(dev)->gen >= 9)
4989 skylake_pfit_enable(intel_crtc);
4990 else
4991 ironlake_pfit_enable(intel_crtc);
4992
4993 /*
4994 * On ILK+ LUT must be loaded before the pipe is running but with
4995 * clocks enabled
4996 */
4997 intel_crtc_load_lut(crtc);
4998
4999 intel_ddi_set_pipe_settings(crtc);
5000 if (!is_dsi)
5001 intel_ddi_enable_transcoder_func(crtc);
5002
5003 intel_update_watermarks(crtc);
5004 intel_enable_pipe(intel_crtc);
5005
5006 if (intel_crtc->config->has_pch_encoder)
5007 lpt_pch_enable(crtc);
5008
5009 if (intel_crtc->config->dp_encoder_is_mst && !is_dsi)
5010 intel_ddi_set_vc_payload_alloc(crtc, true);
5011
5012 assert_vblank_disabled(crtc);
5013 drm_crtc_vblank_on(crtc);
5014
5015 for_each_encoder_on_crtc(dev, crtc, encoder) {
5016 encoder->enable(encoder);
5017 intel_opregion_notify_encoder(encoder, true);
5018 }
5019
5020 if (intel_crtc->config->has_pch_encoder)
5021 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5022 true);
5023
5024 /* If we change the relative order between pipe/planes enabling, we need
5025 * to change the workaround. */
5026 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5027 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5028 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5029 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5030 }
5031 }
5032
5033 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5034 {
5035 struct drm_device *dev = crtc->base.dev;
5036 struct drm_i915_private *dev_priv = dev->dev_private;
5037 int pipe = crtc->pipe;
5038
5039 /* To avoid upsetting the power well on haswell only disable the pfit if
5040 * it's in use. The hw state code will make sure we get this right. */
5041 if (force || crtc->config->pch_pfit.enabled) {
5042 I915_WRITE(PF_CTL(pipe), 0);
5043 I915_WRITE(PF_WIN_POS(pipe), 0);
5044 I915_WRITE(PF_WIN_SZ(pipe), 0);
5045 }
5046 }
5047
5048 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5049 {
5050 struct drm_device *dev = crtc->dev;
5051 struct drm_i915_private *dev_priv = dev->dev_private;
5052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5053 struct intel_encoder *encoder;
5054 int pipe = intel_crtc->pipe;
5055
5056 if (intel_crtc->config->has_pch_encoder)
5057 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5058
5059 for_each_encoder_on_crtc(dev, crtc, encoder)
5060 encoder->disable(encoder);
5061
5062 drm_crtc_vblank_off(crtc);
5063 assert_vblank_disabled(crtc);
5064
5065 intel_disable_pipe(intel_crtc);
5066
5067 ironlake_pfit_disable(intel_crtc, false);
5068
5069 if (intel_crtc->config->has_pch_encoder)
5070 ironlake_fdi_disable(crtc);
5071
5072 for_each_encoder_on_crtc(dev, crtc, encoder)
5073 if (encoder->post_disable)
5074 encoder->post_disable(encoder);
5075
5076 if (intel_crtc->config->has_pch_encoder) {
5077 ironlake_disable_pch_transcoder(dev_priv, pipe);
5078
5079 if (HAS_PCH_CPT(dev)) {
5080 i915_reg_t reg;
5081 u32 temp;
5082
5083 /* disable TRANS_DP_CTL */
5084 reg = TRANS_DP_CTL(pipe);
5085 temp = I915_READ(reg);
5086 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5087 TRANS_DP_PORT_SEL_MASK);
5088 temp |= TRANS_DP_PORT_SEL_NONE;
5089 I915_WRITE(reg, temp);
5090
5091 /* disable DPLL_SEL */
5092 temp = I915_READ(PCH_DPLL_SEL);
5093 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5094 I915_WRITE(PCH_DPLL_SEL, temp);
5095 }
5096
5097 ironlake_fdi_pll_disable(intel_crtc);
5098 }
5099
5100 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5101 }
5102
5103 static void haswell_crtc_disable(struct drm_crtc *crtc)
5104 {
5105 struct drm_device *dev = crtc->dev;
5106 struct drm_i915_private *dev_priv = dev->dev_private;
5107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5108 struct intel_encoder *encoder;
5109 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5110 bool is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5111
5112 if (intel_crtc->config->has_pch_encoder)
5113 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5114 false);
5115
5116 for_each_encoder_on_crtc(dev, crtc, encoder) {
5117 intel_opregion_notify_encoder(encoder, false);
5118 encoder->disable(encoder);
5119 }
5120
5121 drm_crtc_vblank_off(crtc);
5122 assert_vblank_disabled(crtc);
5123
5124 intel_disable_pipe(intel_crtc);
5125
5126 if (intel_crtc->config->dp_encoder_is_mst)
5127 intel_ddi_set_vc_payload_alloc(crtc, false);
5128
5129 if (!is_dsi)
5130 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5131
5132 if (INTEL_INFO(dev)->gen >= 9)
5133 skylake_scaler_disable(intel_crtc);
5134 else
5135 ironlake_pfit_disable(intel_crtc, false);
5136
5137 if (!is_dsi)
5138 intel_ddi_disable_pipe_clock(intel_crtc);
5139
5140 if (intel_crtc->config->has_pch_encoder) {
5141 lpt_disable_pch_transcoder(dev_priv);
5142 intel_ddi_fdi_disable(crtc);
5143 }
5144
5145 for_each_encoder_on_crtc(dev, crtc, encoder)
5146 if (encoder->post_disable)
5147 encoder->post_disable(encoder);
5148
5149 if (intel_crtc->config->has_pch_encoder)
5150 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5151 true);
5152 }
5153
5154 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5155 {
5156 struct drm_device *dev = crtc->base.dev;
5157 struct drm_i915_private *dev_priv = dev->dev_private;
5158 struct intel_crtc_state *pipe_config = crtc->config;
5159
5160 if (!pipe_config->gmch_pfit.control)
5161 return;
5162
5163 /*
5164 * The panel fitter should only be adjusted whilst the pipe is disabled,
5165 * according to register description and PRM.
5166 */
5167 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5168 assert_pipe_disabled(dev_priv, crtc->pipe);
5169
5170 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5171 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5172
5173 /* Border color in case we don't scale up to the full screen. Black by
5174 * default, change to something else for debugging. */
5175 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5176 }
5177
5178 static enum intel_display_power_domain port_to_power_domain(enum port port)
5179 {
5180 switch (port) {
5181 case PORT_A:
5182 return POWER_DOMAIN_PORT_DDI_A_LANES;
5183 case PORT_B:
5184 return POWER_DOMAIN_PORT_DDI_B_LANES;
5185 case PORT_C:
5186 return POWER_DOMAIN_PORT_DDI_C_LANES;
5187 case PORT_D:
5188 return POWER_DOMAIN_PORT_DDI_D_LANES;
5189 case PORT_E:
5190 return POWER_DOMAIN_PORT_DDI_E_LANES;
5191 default:
5192 MISSING_CASE(port);
5193 return POWER_DOMAIN_PORT_OTHER;
5194 }
5195 }
5196
5197 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5198 {
5199 switch (port) {
5200 case PORT_A:
5201 return POWER_DOMAIN_AUX_A;
5202 case PORT_B:
5203 return POWER_DOMAIN_AUX_B;
5204 case PORT_C:
5205 return POWER_DOMAIN_AUX_C;
5206 case PORT_D:
5207 return POWER_DOMAIN_AUX_D;
5208 case PORT_E:
5209 /* FIXME: Check VBT for actual wiring of PORT E */
5210 return POWER_DOMAIN_AUX_D;
5211 default:
5212 MISSING_CASE(port);
5213 return POWER_DOMAIN_AUX_A;
5214 }
5215 }
5216
5217 #define for_each_power_domain(domain, mask) \
5218 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5219 if ((1 << (domain)) & (mask))
5220
5221 enum intel_display_power_domain
5222 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5223 {
5224 struct drm_device *dev = intel_encoder->base.dev;
5225 struct intel_digital_port *intel_dig_port;
5226
5227 switch (intel_encoder->type) {
5228 case INTEL_OUTPUT_UNKNOWN:
5229 /* Only DDI platforms should ever use this output type */
5230 WARN_ON_ONCE(!HAS_DDI(dev));
5231 case INTEL_OUTPUT_DISPLAYPORT:
5232 case INTEL_OUTPUT_HDMI:
5233 case INTEL_OUTPUT_EDP:
5234 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5235 return port_to_power_domain(intel_dig_port->port);
5236 case INTEL_OUTPUT_DP_MST:
5237 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5238 return port_to_power_domain(intel_dig_port->port);
5239 case INTEL_OUTPUT_ANALOG:
5240 return POWER_DOMAIN_PORT_CRT;
5241 case INTEL_OUTPUT_DSI:
5242 return POWER_DOMAIN_PORT_DSI;
5243 default:
5244 return POWER_DOMAIN_PORT_OTHER;
5245 }
5246 }
5247
5248 enum intel_display_power_domain
5249 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5250 {
5251 struct drm_device *dev = intel_encoder->base.dev;
5252 struct intel_digital_port *intel_dig_port;
5253
5254 switch (intel_encoder->type) {
5255 case INTEL_OUTPUT_UNKNOWN:
5256 case INTEL_OUTPUT_HDMI:
5257 /*
5258 * Only DDI platforms should ever use these output types.
5259 * We can get here after the HDMI detect code has already set
5260 * the type of the shared encoder. Since we can't be sure
5261 * what's the status of the given connectors, play safe and
5262 * run the DP detection too.
5263 */
5264 WARN_ON_ONCE(!HAS_DDI(dev));
5265 case INTEL_OUTPUT_DISPLAYPORT:
5266 case INTEL_OUTPUT_EDP:
5267 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5268 return port_to_aux_power_domain(intel_dig_port->port);
5269 case INTEL_OUTPUT_DP_MST:
5270 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5271 return port_to_aux_power_domain(intel_dig_port->port);
5272 default:
5273 MISSING_CASE(intel_encoder->type);
5274 return POWER_DOMAIN_AUX_A;
5275 }
5276 }
5277
5278 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5279 {
5280 struct drm_device *dev = crtc->dev;
5281 struct intel_encoder *intel_encoder;
5282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5283 enum pipe pipe = intel_crtc->pipe;
5284 unsigned long mask;
5285 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5286
5287 if (!crtc->state->active)
5288 return 0;
5289
5290 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5291 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5292 if (intel_crtc->config->pch_pfit.enabled ||
5293 intel_crtc->config->pch_pfit.force_thru)
5294 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5295
5296 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5297 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5298
5299 return mask;
5300 }
5301
5302 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5303 {
5304 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5306 enum intel_display_power_domain domain;
5307 unsigned long domains, new_domains, old_domains;
5308
5309 old_domains = intel_crtc->enabled_power_domains;
5310 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5311
5312 domains = new_domains & ~old_domains;
5313
5314 for_each_power_domain(domain, domains)
5315 intel_display_power_get(dev_priv, domain);
5316
5317 return old_domains & ~new_domains;
5318 }
5319
5320 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5321 unsigned long domains)
5322 {
5323 enum intel_display_power_domain domain;
5324
5325 for_each_power_domain(domain, domains)
5326 intel_display_power_put(dev_priv, domain);
5327 }
5328
5329 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5330 {
5331 struct drm_device *dev = state->dev;
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 unsigned long put_domains[I915_MAX_PIPES] = {};
5334 struct drm_crtc_state *crtc_state;
5335 struct drm_crtc *crtc;
5336 int i;
5337
5338 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5339 if (needs_modeset(crtc->state))
5340 put_domains[to_intel_crtc(crtc)->pipe] =
5341 modeset_get_crtc_power_domains(crtc);
5342 }
5343
5344 if (dev_priv->display.modeset_commit_cdclk) {
5345 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5346
5347 if (cdclk != dev_priv->cdclk_freq &&
5348 !WARN_ON(!state->allow_modeset))
5349 dev_priv->display.modeset_commit_cdclk(state);
5350 }
5351
5352 for (i = 0; i < I915_MAX_PIPES; i++)
5353 if (put_domains[i])
5354 modeset_put_power_domains(dev_priv, put_domains[i]);
5355 }
5356
5357 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5358 {
5359 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5360
5361 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5362 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5363 return max_cdclk_freq;
5364 else if (IS_CHERRYVIEW(dev_priv))
5365 return max_cdclk_freq*95/100;
5366 else if (INTEL_INFO(dev_priv)->gen < 4)
5367 return 2*max_cdclk_freq*90/100;
5368 else
5369 return max_cdclk_freq*90/100;
5370 }
5371
5372 static void intel_update_max_cdclk(struct drm_device *dev)
5373 {
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375
5376 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5377 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5378
5379 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5380 dev_priv->max_cdclk_freq = 675000;
5381 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5382 dev_priv->max_cdclk_freq = 540000;
5383 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5384 dev_priv->max_cdclk_freq = 450000;
5385 else
5386 dev_priv->max_cdclk_freq = 337500;
5387 } else if (IS_BROADWELL(dev)) {
5388 /*
5389 * FIXME with extra cooling we can allow
5390 * 540 MHz for ULX and 675 Mhz for ULT.
5391 * How can we know if extra cooling is
5392 * available? PCI ID, VTB, something else?
5393 */
5394 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5395 dev_priv->max_cdclk_freq = 450000;
5396 else if (IS_BDW_ULX(dev))
5397 dev_priv->max_cdclk_freq = 450000;
5398 else if (IS_BDW_ULT(dev))
5399 dev_priv->max_cdclk_freq = 540000;
5400 else
5401 dev_priv->max_cdclk_freq = 675000;
5402 } else if (IS_CHERRYVIEW(dev)) {
5403 dev_priv->max_cdclk_freq = 320000;
5404 } else if (IS_VALLEYVIEW(dev)) {
5405 dev_priv->max_cdclk_freq = 400000;
5406 } else {
5407 /* otherwise assume cdclk is fixed */
5408 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5409 }
5410
5411 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5412
5413 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5414 dev_priv->max_cdclk_freq);
5415
5416 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5417 dev_priv->max_dotclk_freq);
5418 }
5419
5420 static void intel_update_cdclk(struct drm_device *dev)
5421 {
5422 struct drm_i915_private *dev_priv = dev->dev_private;
5423
5424 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5425 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5426 dev_priv->cdclk_freq);
5427
5428 /*
5429 * Program the gmbus_freq based on the cdclk frequency.
5430 * BSpec erroneously claims we should aim for 4MHz, but
5431 * in fact 1MHz is the correct frequency.
5432 */
5433 if (IS_VALLEYVIEW(dev)) {
5434 /*
5435 * Program the gmbus_freq based on the cdclk frequency.
5436 * BSpec erroneously claims we should aim for 4MHz, but
5437 * in fact 1MHz is the correct frequency.
5438 */
5439 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5440 }
5441
5442 if (dev_priv->max_cdclk_freq == 0)
5443 intel_update_max_cdclk(dev);
5444 }
5445
5446 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5447 {
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 uint32_t divider;
5450 uint32_t ratio;
5451 uint32_t current_freq;
5452 int ret;
5453
5454 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5455 switch (frequency) {
5456 case 144000:
5457 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5458 ratio = BXT_DE_PLL_RATIO(60);
5459 break;
5460 case 288000:
5461 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5462 ratio = BXT_DE_PLL_RATIO(60);
5463 break;
5464 case 384000:
5465 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5466 ratio = BXT_DE_PLL_RATIO(60);
5467 break;
5468 case 576000:
5469 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5470 ratio = BXT_DE_PLL_RATIO(60);
5471 break;
5472 case 624000:
5473 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5474 ratio = BXT_DE_PLL_RATIO(65);
5475 break;
5476 case 19200:
5477 /*
5478 * Bypass frequency with DE PLL disabled. Init ratio, divider
5479 * to suppress GCC warning.
5480 */
5481 ratio = 0;
5482 divider = 0;
5483 break;
5484 default:
5485 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5486
5487 return;
5488 }
5489
5490 mutex_lock(&dev_priv->rps.hw_lock);
5491 /* Inform power controller of upcoming frequency change */
5492 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5493 0x80000000);
5494 mutex_unlock(&dev_priv->rps.hw_lock);
5495
5496 if (ret) {
5497 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5498 ret, frequency);
5499 return;
5500 }
5501
5502 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5503 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5504 current_freq = current_freq * 500 + 1000;
5505
5506 /*
5507 * DE PLL has to be disabled when
5508 * - setting to 19.2MHz (bypass, PLL isn't used)
5509 * - before setting to 624MHz (PLL needs toggling)
5510 * - before setting to any frequency from 624MHz (PLL needs toggling)
5511 */
5512 if (frequency == 19200 || frequency == 624000 ||
5513 current_freq == 624000) {
5514 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5515 /* Timeout 200us */
5516 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5517 1))
5518 DRM_ERROR("timout waiting for DE PLL unlock\n");
5519 }
5520
5521 if (frequency != 19200) {
5522 uint32_t val;
5523
5524 val = I915_READ(BXT_DE_PLL_CTL);
5525 val &= ~BXT_DE_PLL_RATIO_MASK;
5526 val |= ratio;
5527 I915_WRITE(BXT_DE_PLL_CTL, val);
5528
5529 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5530 /* Timeout 200us */
5531 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5532 DRM_ERROR("timeout waiting for DE PLL lock\n");
5533
5534 val = I915_READ(CDCLK_CTL);
5535 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5536 val |= divider;
5537 /*
5538 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5539 * enable otherwise.
5540 */
5541 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5542 if (frequency >= 500000)
5543 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5544
5545 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5546 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5547 val |= (frequency - 1000) / 500;
5548 I915_WRITE(CDCLK_CTL, val);
5549 }
5550
5551 mutex_lock(&dev_priv->rps.hw_lock);
5552 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5553 DIV_ROUND_UP(frequency, 25000));
5554 mutex_unlock(&dev_priv->rps.hw_lock);
5555
5556 if (ret) {
5557 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5558 ret, frequency);
5559 return;
5560 }
5561
5562 intel_update_cdclk(dev);
5563 }
5564
5565 void broxton_init_cdclk(struct drm_device *dev)
5566 {
5567 struct drm_i915_private *dev_priv = dev->dev_private;
5568 uint32_t val;
5569
5570 /*
5571 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5572 * or else the reset will hang because there is no PCH to respond.
5573 * Move the handshake programming to initialization sequence.
5574 * Previously was left up to BIOS.
5575 */
5576 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5577 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5578 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5579
5580 /* Enable PG1 for cdclk */
5581 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5582
5583 /* check if cd clock is enabled */
5584 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5585 DRM_DEBUG_KMS("Display already initialized\n");
5586 return;
5587 }
5588
5589 /*
5590 * FIXME:
5591 * - The initial CDCLK needs to be read from VBT.
5592 * Need to make this change after VBT has changes for BXT.
5593 * - check if setting the max (or any) cdclk freq is really necessary
5594 * here, it belongs to modeset time
5595 */
5596 broxton_set_cdclk(dev, 624000);
5597
5598 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5599 POSTING_READ(DBUF_CTL);
5600
5601 udelay(10);
5602
5603 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5604 DRM_ERROR("DBuf power enable timeout!\n");
5605 }
5606
5607 void broxton_uninit_cdclk(struct drm_device *dev)
5608 {
5609 struct drm_i915_private *dev_priv = dev->dev_private;
5610
5611 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5612 POSTING_READ(DBUF_CTL);
5613
5614 udelay(10);
5615
5616 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5617 DRM_ERROR("DBuf power disable timeout!\n");
5618
5619 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5620 broxton_set_cdclk(dev, 19200);
5621
5622 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5623 }
5624
5625 static const struct skl_cdclk_entry {
5626 unsigned int freq;
5627 unsigned int vco;
5628 } skl_cdclk_frequencies[] = {
5629 { .freq = 308570, .vco = 8640 },
5630 { .freq = 337500, .vco = 8100 },
5631 { .freq = 432000, .vco = 8640 },
5632 { .freq = 450000, .vco = 8100 },
5633 { .freq = 540000, .vco = 8100 },
5634 { .freq = 617140, .vco = 8640 },
5635 { .freq = 675000, .vco = 8100 },
5636 };
5637
5638 static unsigned int skl_cdclk_decimal(unsigned int freq)
5639 {
5640 return (freq - 1000) / 500;
5641 }
5642
5643 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5644 {
5645 unsigned int i;
5646
5647 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5648 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5649
5650 if (e->freq == freq)
5651 return e->vco;
5652 }
5653
5654 return 8100;
5655 }
5656
5657 static void
5658 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5659 {
5660 unsigned int min_freq;
5661 u32 val;
5662
5663 /* select the minimum CDCLK before enabling DPLL 0 */
5664 val = I915_READ(CDCLK_CTL);
5665 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5666 val |= CDCLK_FREQ_337_308;
5667
5668 if (required_vco == 8640)
5669 min_freq = 308570;
5670 else
5671 min_freq = 337500;
5672
5673 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5674
5675 I915_WRITE(CDCLK_CTL, val);
5676 POSTING_READ(CDCLK_CTL);
5677
5678 /*
5679 * We always enable DPLL0 with the lowest link rate possible, but still
5680 * taking into account the VCO required to operate the eDP panel at the
5681 * desired frequency. The usual DP link rates operate with a VCO of
5682 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5683 * The modeset code is responsible for the selection of the exact link
5684 * rate later on, with the constraint of choosing a frequency that
5685 * works with required_vco.
5686 */
5687 val = I915_READ(DPLL_CTRL1);
5688
5689 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5690 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5691 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5692 if (required_vco == 8640)
5693 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5694 SKL_DPLL0);
5695 else
5696 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5697 SKL_DPLL0);
5698
5699 I915_WRITE(DPLL_CTRL1, val);
5700 POSTING_READ(DPLL_CTRL1);
5701
5702 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5703
5704 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5705 DRM_ERROR("DPLL0 not locked\n");
5706 }
5707
5708 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5709 {
5710 int ret;
5711 u32 val;
5712
5713 /* inform PCU we want to change CDCLK */
5714 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5715 mutex_lock(&dev_priv->rps.hw_lock);
5716 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5717 mutex_unlock(&dev_priv->rps.hw_lock);
5718
5719 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5720 }
5721
5722 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5723 {
5724 unsigned int i;
5725
5726 for (i = 0; i < 15; i++) {
5727 if (skl_cdclk_pcu_ready(dev_priv))
5728 return true;
5729 udelay(10);
5730 }
5731
5732 return false;
5733 }
5734
5735 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5736 {
5737 struct drm_device *dev = dev_priv->dev;
5738 u32 freq_select, pcu_ack;
5739
5740 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5741
5742 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5743 DRM_ERROR("failed to inform PCU about cdclk change\n");
5744 return;
5745 }
5746
5747 /* set CDCLK_CTL */
5748 switch(freq) {
5749 case 450000:
5750 case 432000:
5751 freq_select = CDCLK_FREQ_450_432;
5752 pcu_ack = 1;
5753 break;
5754 case 540000:
5755 freq_select = CDCLK_FREQ_540;
5756 pcu_ack = 2;
5757 break;
5758 case 308570:
5759 case 337500:
5760 default:
5761 freq_select = CDCLK_FREQ_337_308;
5762 pcu_ack = 0;
5763 break;
5764 case 617140:
5765 case 675000:
5766 freq_select = CDCLK_FREQ_675_617;
5767 pcu_ack = 3;
5768 break;
5769 }
5770
5771 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5772 POSTING_READ(CDCLK_CTL);
5773
5774 /* inform PCU of the change */
5775 mutex_lock(&dev_priv->rps.hw_lock);
5776 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5777 mutex_unlock(&dev_priv->rps.hw_lock);
5778
5779 intel_update_cdclk(dev);
5780 }
5781
5782 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5783 {
5784 /* disable DBUF power */
5785 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5786 POSTING_READ(DBUF_CTL);
5787
5788 udelay(10);
5789
5790 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5791 DRM_ERROR("DBuf power disable timeout\n");
5792
5793 /* disable DPLL0 */
5794 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5795 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5796 DRM_ERROR("Couldn't disable DPLL0\n");
5797 }
5798
5799 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5800 {
5801 unsigned int required_vco;
5802
5803 /* DPLL0 not enabled (happens on early BIOS versions) */
5804 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5805 /* enable DPLL0 */
5806 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5807 skl_dpll0_enable(dev_priv, required_vco);
5808 }
5809
5810 /* set CDCLK to the frequency the BIOS chose */
5811 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5812
5813 /* enable DBUF power */
5814 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5815 POSTING_READ(DBUF_CTL);
5816
5817 udelay(10);
5818
5819 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5820 DRM_ERROR("DBuf power enable timeout\n");
5821 }
5822
5823 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5824 {
5825 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5826 uint32_t cdctl = I915_READ(CDCLK_CTL);
5827 int freq = dev_priv->skl_boot_cdclk;
5828
5829 /*
5830 * check if the pre-os intialized the display
5831 * There is SWF18 scratchpad register defined which is set by the
5832 * pre-os which can be used by the OS drivers to check the status
5833 */
5834 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5835 goto sanitize;
5836
5837 /* Is PLL enabled and locked ? */
5838 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5839 goto sanitize;
5840
5841 /* DPLL okay; verify the cdclock
5842 *
5843 * Noticed in some instances that the freq selection is correct but
5844 * decimal part is programmed wrong from BIOS where pre-os does not
5845 * enable display. Verify the same as well.
5846 */
5847 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5848 /* All well; nothing to sanitize */
5849 return false;
5850 sanitize:
5851 /*
5852 * As of now initialize with max cdclk till
5853 * we get dynamic cdclk support
5854 * */
5855 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5856 skl_init_cdclk(dev_priv);
5857
5858 /* we did have to sanitize */
5859 return true;
5860 }
5861
5862 /* Adjust CDclk dividers to allow high res or save power if possible */
5863 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5864 {
5865 struct drm_i915_private *dev_priv = dev->dev_private;
5866 u32 val, cmd;
5867
5868 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5869 != dev_priv->cdclk_freq);
5870
5871 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5872 cmd = 2;
5873 else if (cdclk == 266667)
5874 cmd = 1;
5875 else
5876 cmd = 0;
5877
5878 mutex_lock(&dev_priv->rps.hw_lock);
5879 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5880 val &= ~DSPFREQGUAR_MASK;
5881 val |= (cmd << DSPFREQGUAR_SHIFT);
5882 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5883 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5884 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5885 50)) {
5886 DRM_ERROR("timed out waiting for CDclk change\n");
5887 }
5888 mutex_unlock(&dev_priv->rps.hw_lock);
5889
5890 mutex_lock(&dev_priv->sb_lock);
5891
5892 if (cdclk == 400000) {
5893 u32 divider;
5894
5895 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5896
5897 /* adjust cdclk divider */
5898 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5899 val &= ~CCK_FREQUENCY_VALUES;
5900 val |= divider;
5901 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5902
5903 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5904 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5905 50))
5906 DRM_ERROR("timed out waiting for CDclk change\n");
5907 }
5908
5909 /* adjust self-refresh exit latency value */
5910 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5911 val &= ~0x7f;
5912
5913 /*
5914 * For high bandwidth configs, we set a higher latency in the bunit
5915 * so that the core display fetch happens in time to avoid underruns.
5916 */
5917 if (cdclk == 400000)
5918 val |= 4500 / 250; /* 4.5 usec */
5919 else
5920 val |= 3000 / 250; /* 3.0 usec */
5921 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5922
5923 mutex_unlock(&dev_priv->sb_lock);
5924
5925 intel_update_cdclk(dev);
5926 }
5927
5928 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5929 {
5930 struct drm_i915_private *dev_priv = dev->dev_private;
5931 u32 val, cmd;
5932
5933 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5934 != dev_priv->cdclk_freq);
5935
5936 switch (cdclk) {
5937 case 333333:
5938 case 320000:
5939 case 266667:
5940 case 200000:
5941 break;
5942 default:
5943 MISSING_CASE(cdclk);
5944 return;
5945 }
5946
5947 /*
5948 * Specs are full of misinformation, but testing on actual
5949 * hardware has shown that we just need to write the desired
5950 * CCK divider into the Punit register.
5951 */
5952 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5953
5954 mutex_lock(&dev_priv->rps.hw_lock);
5955 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5956 val &= ~DSPFREQGUAR_MASK_CHV;
5957 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5958 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5959 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5960 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5961 50)) {
5962 DRM_ERROR("timed out waiting for CDclk change\n");
5963 }
5964 mutex_unlock(&dev_priv->rps.hw_lock);
5965
5966 intel_update_cdclk(dev);
5967 }
5968
5969 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5970 int max_pixclk)
5971 {
5972 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5973 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5974
5975 /*
5976 * Really only a few cases to deal with, as only 4 CDclks are supported:
5977 * 200MHz
5978 * 267MHz
5979 * 320/333MHz (depends on HPLL freq)
5980 * 400MHz (VLV only)
5981 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5982 * of the lower bin and adjust if needed.
5983 *
5984 * We seem to get an unstable or solid color picture at 200MHz.
5985 * Not sure what's wrong. For now use 200MHz only when all pipes
5986 * are off.
5987 */
5988 if (!IS_CHERRYVIEW(dev_priv) &&
5989 max_pixclk > freq_320*limit/100)
5990 return 400000;
5991 else if (max_pixclk > 266667*limit/100)
5992 return freq_320;
5993 else if (max_pixclk > 0)
5994 return 266667;
5995 else
5996 return 200000;
5997 }
5998
5999 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6000 int max_pixclk)
6001 {
6002 /*
6003 * FIXME:
6004 * - remove the guardband, it's not needed on BXT
6005 * - set 19.2MHz bypass frequency if there are no active pipes
6006 */
6007 if (max_pixclk > 576000*9/10)
6008 return 624000;
6009 else if (max_pixclk > 384000*9/10)
6010 return 576000;
6011 else if (max_pixclk > 288000*9/10)
6012 return 384000;
6013 else if (max_pixclk > 144000*9/10)
6014 return 288000;
6015 else
6016 return 144000;
6017 }
6018
6019 /* Compute the max pixel clock for new configuration. Uses atomic state if
6020 * that's non-NULL, look at current state otherwise. */
6021 static int intel_mode_max_pixclk(struct drm_device *dev,
6022 struct drm_atomic_state *state)
6023 {
6024 struct intel_crtc *intel_crtc;
6025 struct intel_crtc_state *crtc_state;
6026 int max_pixclk = 0;
6027
6028 for_each_intel_crtc(dev, intel_crtc) {
6029 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
6030 if (IS_ERR(crtc_state))
6031 return PTR_ERR(crtc_state);
6032
6033 if (!crtc_state->base.enable)
6034 continue;
6035
6036 max_pixclk = max(max_pixclk,
6037 crtc_state->base.adjusted_mode.crtc_clock);
6038 }
6039
6040 return max_pixclk;
6041 }
6042
6043 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6044 {
6045 struct drm_device *dev = state->dev;
6046 struct drm_i915_private *dev_priv = dev->dev_private;
6047 int max_pixclk = intel_mode_max_pixclk(dev, state);
6048
6049 if (max_pixclk < 0)
6050 return max_pixclk;
6051
6052 to_intel_atomic_state(state)->cdclk =
6053 valleyview_calc_cdclk(dev_priv, max_pixclk);
6054
6055 return 0;
6056 }
6057
6058 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6059 {
6060 struct drm_device *dev = state->dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
6062 int max_pixclk = intel_mode_max_pixclk(dev, state);
6063
6064 if (max_pixclk < 0)
6065 return max_pixclk;
6066
6067 to_intel_atomic_state(state)->cdclk =
6068 broxton_calc_cdclk(dev_priv, max_pixclk);
6069
6070 return 0;
6071 }
6072
6073 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6074 {
6075 unsigned int credits, default_credits;
6076
6077 if (IS_CHERRYVIEW(dev_priv))
6078 default_credits = PFI_CREDIT(12);
6079 else
6080 default_credits = PFI_CREDIT(8);
6081
6082 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6083 /* CHV suggested value is 31 or 63 */
6084 if (IS_CHERRYVIEW(dev_priv))
6085 credits = PFI_CREDIT_63;
6086 else
6087 credits = PFI_CREDIT(15);
6088 } else {
6089 credits = default_credits;
6090 }
6091
6092 /*
6093 * WA - write default credits before re-programming
6094 * FIXME: should we also set the resend bit here?
6095 */
6096 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6097 default_credits);
6098
6099 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6100 credits | PFI_CREDIT_RESEND);
6101
6102 /*
6103 * FIXME is this guaranteed to clear
6104 * immediately or should we poll for it?
6105 */
6106 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6107 }
6108
6109 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6110 {
6111 struct drm_device *dev = old_state->dev;
6112 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
6113 struct drm_i915_private *dev_priv = dev->dev_private;
6114
6115 /*
6116 * FIXME: We can end up here with all power domains off, yet
6117 * with a CDCLK frequency other than the minimum. To account
6118 * for this take the PIPE-A power domain, which covers the HW
6119 * blocks needed for the following programming. This can be
6120 * removed once it's guaranteed that we get here either with
6121 * the minimum CDCLK set, or the required power domains
6122 * enabled.
6123 */
6124 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6125
6126 if (IS_CHERRYVIEW(dev))
6127 cherryview_set_cdclk(dev, req_cdclk);
6128 else
6129 valleyview_set_cdclk(dev, req_cdclk);
6130
6131 vlv_program_pfi_credits(dev_priv);
6132
6133 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6134 }
6135
6136 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6137 {
6138 struct drm_device *dev = crtc->dev;
6139 struct drm_i915_private *dev_priv = to_i915(dev);
6140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6141 struct intel_encoder *encoder;
6142 int pipe = intel_crtc->pipe;
6143 bool is_dsi;
6144
6145 if (WARN_ON(intel_crtc->active))
6146 return;
6147
6148 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
6149
6150 if (intel_crtc->config->has_dp_encoder)
6151 intel_dp_set_m_n(intel_crtc, M1_N1);
6152
6153 intel_set_pipe_timings(intel_crtc);
6154
6155 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6156 struct drm_i915_private *dev_priv = dev->dev_private;
6157
6158 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6159 I915_WRITE(CHV_CANVAS(pipe), 0);
6160 }
6161
6162 i9xx_set_pipeconf(intel_crtc);
6163
6164 intel_crtc->active = true;
6165
6166 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6167
6168 for_each_encoder_on_crtc(dev, crtc, encoder)
6169 if (encoder->pre_pll_enable)
6170 encoder->pre_pll_enable(encoder);
6171
6172 if (!is_dsi) {
6173 if (IS_CHERRYVIEW(dev)) {
6174 chv_prepare_pll(intel_crtc, intel_crtc->config);
6175 chv_enable_pll(intel_crtc, intel_crtc->config);
6176 } else {
6177 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6178 vlv_enable_pll(intel_crtc, intel_crtc->config);
6179 }
6180 }
6181
6182 for_each_encoder_on_crtc(dev, crtc, encoder)
6183 if (encoder->pre_enable)
6184 encoder->pre_enable(encoder);
6185
6186 i9xx_pfit_enable(intel_crtc);
6187
6188 intel_crtc_load_lut(crtc);
6189
6190 intel_enable_pipe(intel_crtc);
6191
6192 assert_vblank_disabled(crtc);
6193 drm_crtc_vblank_on(crtc);
6194
6195 for_each_encoder_on_crtc(dev, crtc, encoder)
6196 encoder->enable(encoder);
6197 }
6198
6199 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6200 {
6201 struct drm_device *dev = crtc->base.dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203
6204 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6205 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6206 }
6207
6208 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6209 {
6210 struct drm_device *dev = crtc->dev;
6211 struct drm_i915_private *dev_priv = to_i915(dev);
6212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6213 struct intel_encoder *encoder;
6214 int pipe = intel_crtc->pipe;
6215
6216 if (WARN_ON(intel_crtc->active))
6217 return;
6218
6219 i9xx_set_pll_dividers(intel_crtc);
6220
6221 if (intel_crtc->config->has_dp_encoder)
6222 intel_dp_set_m_n(intel_crtc, M1_N1);
6223
6224 intel_set_pipe_timings(intel_crtc);
6225
6226 i9xx_set_pipeconf(intel_crtc);
6227
6228 intel_crtc->active = true;
6229
6230 if (!IS_GEN2(dev))
6231 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6232
6233 for_each_encoder_on_crtc(dev, crtc, encoder)
6234 if (encoder->pre_enable)
6235 encoder->pre_enable(encoder);
6236
6237 i9xx_enable_pll(intel_crtc);
6238
6239 i9xx_pfit_enable(intel_crtc);
6240
6241 intel_crtc_load_lut(crtc);
6242
6243 intel_update_watermarks(crtc);
6244 intel_enable_pipe(intel_crtc);
6245
6246 assert_vblank_disabled(crtc);
6247 drm_crtc_vblank_on(crtc);
6248
6249 for_each_encoder_on_crtc(dev, crtc, encoder)
6250 encoder->enable(encoder);
6251 }
6252
6253 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6254 {
6255 struct drm_device *dev = crtc->base.dev;
6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257
6258 if (!crtc->config->gmch_pfit.control)
6259 return;
6260
6261 assert_pipe_disabled(dev_priv, crtc->pipe);
6262
6263 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6264 I915_READ(PFIT_CONTROL));
6265 I915_WRITE(PFIT_CONTROL, 0);
6266 }
6267
6268 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6269 {
6270 struct drm_device *dev = crtc->dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6273 struct intel_encoder *encoder;
6274 int pipe = intel_crtc->pipe;
6275
6276 /*
6277 * On gen2 planes are double buffered but the pipe isn't, so we must
6278 * wait for planes to fully turn off before disabling the pipe.
6279 * We also need to wait on all gmch platforms because of the
6280 * self-refresh mode constraint explained above.
6281 */
6282 intel_wait_for_vblank(dev, pipe);
6283
6284 for_each_encoder_on_crtc(dev, crtc, encoder)
6285 encoder->disable(encoder);
6286
6287 drm_crtc_vblank_off(crtc);
6288 assert_vblank_disabled(crtc);
6289
6290 intel_disable_pipe(intel_crtc);
6291
6292 i9xx_pfit_disable(intel_crtc);
6293
6294 for_each_encoder_on_crtc(dev, crtc, encoder)
6295 if (encoder->post_disable)
6296 encoder->post_disable(encoder);
6297
6298 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6299 if (IS_CHERRYVIEW(dev))
6300 chv_disable_pll(dev_priv, pipe);
6301 else if (IS_VALLEYVIEW(dev))
6302 vlv_disable_pll(dev_priv, pipe);
6303 else
6304 i9xx_disable_pll(intel_crtc);
6305 }
6306
6307 for_each_encoder_on_crtc(dev, crtc, encoder)
6308 if (encoder->post_pll_disable)
6309 encoder->post_pll_disable(encoder);
6310
6311 if (!IS_GEN2(dev))
6312 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6313 }
6314
6315 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6316 {
6317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6318 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6319 enum intel_display_power_domain domain;
6320 unsigned long domains;
6321
6322 if (!intel_crtc->active)
6323 return;
6324
6325 if (to_intel_plane_state(crtc->primary->state)->visible) {
6326 WARN_ON(intel_crtc->unpin_work);
6327
6328 intel_pre_disable_primary(crtc);
6329 }
6330
6331 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
6332 dev_priv->display.crtc_disable(crtc);
6333 intel_crtc->active = false;
6334 intel_update_watermarks(crtc);
6335 intel_disable_shared_dpll(intel_crtc);
6336
6337 domains = intel_crtc->enabled_power_domains;
6338 for_each_power_domain(domain, domains)
6339 intel_display_power_put(dev_priv, domain);
6340 intel_crtc->enabled_power_domains = 0;
6341 }
6342
6343 /*
6344 * turn all crtc's off, but do not adjust state
6345 * This has to be paired with a call to intel_modeset_setup_hw_state.
6346 */
6347 int intel_display_suspend(struct drm_device *dev)
6348 {
6349 struct drm_mode_config *config = &dev->mode_config;
6350 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6351 struct drm_atomic_state *state;
6352 struct drm_crtc *crtc;
6353 unsigned crtc_mask = 0;
6354 int ret = 0;
6355
6356 if (WARN_ON(!ctx))
6357 return 0;
6358
6359 lockdep_assert_held(&ctx->ww_ctx);
6360 state = drm_atomic_state_alloc(dev);
6361 if (WARN_ON(!state))
6362 return -ENOMEM;
6363
6364 state->acquire_ctx = ctx;
6365 state->allow_modeset = true;
6366
6367 for_each_crtc(dev, crtc) {
6368 struct drm_crtc_state *crtc_state =
6369 drm_atomic_get_crtc_state(state, crtc);
6370
6371 ret = PTR_ERR_OR_ZERO(crtc_state);
6372 if (ret)
6373 goto free;
6374
6375 if (!crtc_state->active)
6376 continue;
6377
6378 crtc_state->active = false;
6379 crtc_mask |= 1 << drm_crtc_index(crtc);
6380 }
6381
6382 if (crtc_mask) {
6383 ret = drm_atomic_commit(state);
6384
6385 if (!ret) {
6386 for_each_crtc(dev, crtc)
6387 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6388 crtc->state->active = true;
6389
6390 return ret;
6391 }
6392 }
6393
6394 free:
6395 if (ret)
6396 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6397 drm_atomic_state_free(state);
6398 return ret;
6399 }
6400
6401 void intel_encoder_destroy(struct drm_encoder *encoder)
6402 {
6403 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6404
6405 drm_encoder_cleanup(encoder);
6406 kfree(intel_encoder);
6407 }
6408
6409 /* Cross check the actual hw state with our own modeset state tracking (and it's
6410 * internal consistency). */
6411 static void intel_connector_check_state(struct intel_connector *connector)
6412 {
6413 struct drm_crtc *crtc = connector->base.state->crtc;
6414
6415 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6416 connector->base.base.id,
6417 connector->base.name);
6418
6419 if (connector->get_hw_state(connector)) {
6420 struct intel_encoder *encoder = connector->encoder;
6421 struct drm_connector_state *conn_state = connector->base.state;
6422
6423 I915_STATE_WARN(!crtc,
6424 "connector enabled without attached crtc\n");
6425
6426 if (!crtc)
6427 return;
6428
6429 I915_STATE_WARN(!crtc->state->active,
6430 "connector is active, but attached crtc isn't\n");
6431
6432 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6433 return;
6434
6435 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6436 "atomic encoder doesn't match attached encoder\n");
6437
6438 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6439 "attached encoder crtc differs from connector crtc\n");
6440 } else {
6441 I915_STATE_WARN(crtc && crtc->state->active,
6442 "attached crtc is active, but connector isn't\n");
6443 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6444 "best encoder set without crtc!\n");
6445 }
6446 }
6447
6448 int intel_connector_init(struct intel_connector *connector)
6449 {
6450 struct drm_connector_state *connector_state;
6451
6452 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6453 if (!connector_state)
6454 return -ENOMEM;
6455
6456 connector->base.state = connector_state;
6457 return 0;
6458 }
6459
6460 struct intel_connector *intel_connector_alloc(void)
6461 {
6462 struct intel_connector *connector;
6463
6464 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6465 if (!connector)
6466 return NULL;
6467
6468 if (intel_connector_init(connector) < 0) {
6469 kfree(connector);
6470 return NULL;
6471 }
6472
6473 return connector;
6474 }
6475
6476 /* Simple connector->get_hw_state implementation for encoders that support only
6477 * one connector and no cloning and hence the encoder state determines the state
6478 * of the connector. */
6479 bool intel_connector_get_hw_state(struct intel_connector *connector)
6480 {
6481 enum pipe pipe = 0;
6482 struct intel_encoder *encoder = connector->encoder;
6483
6484 return encoder->get_hw_state(encoder, &pipe);
6485 }
6486
6487 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6488 {
6489 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6490 return crtc_state->fdi_lanes;
6491
6492 return 0;
6493 }
6494
6495 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6496 struct intel_crtc_state *pipe_config)
6497 {
6498 struct drm_atomic_state *state = pipe_config->base.state;
6499 struct intel_crtc *other_crtc;
6500 struct intel_crtc_state *other_crtc_state;
6501
6502 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6503 pipe_name(pipe), pipe_config->fdi_lanes);
6504 if (pipe_config->fdi_lanes > 4) {
6505 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6506 pipe_name(pipe), pipe_config->fdi_lanes);
6507 return -EINVAL;
6508 }
6509
6510 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6511 if (pipe_config->fdi_lanes > 2) {
6512 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6513 pipe_config->fdi_lanes);
6514 return -EINVAL;
6515 } else {
6516 return 0;
6517 }
6518 }
6519
6520 if (INTEL_INFO(dev)->num_pipes == 2)
6521 return 0;
6522
6523 /* Ivybridge 3 pipe is really complicated */
6524 switch (pipe) {
6525 case PIPE_A:
6526 return 0;
6527 case PIPE_B:
6528 if (pipe_config->fdi_lanes <= 2)
6529 return 0;
6530
6531 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6532 other_crtc_state =
6533 intel_atomic_get_crtc_state(state, other_crtc);
6534 if (IS_ERR(other_crtc_state))
6535 return PTR_ERR(other_crtc_state);
6536
6537 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6538 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6539 pipe_name(pipe), pipe_config->fdi_lanes);
6540 return -EINVAL;
6541 }
6542 return 0;
6543 case PIPE_C:
6544 if (pipe_config->fdi_lanes > 2) {
6545 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6546 pipe_name(pipe), pipe_config->fdi_lanes);
6547 return -EINVAL;
6548 }
6549
6550 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6551 other_crtc_state =
6552 intel_atomic_get_crtc_state(state, other_crtc);
6553 if (IS_ERR(other_crtc_state))
6554 return PTR_ERR(other_crtc_state);
6555
6556 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6557 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6558 return -EINVAL;
6559 }
6560 return 0;
6561 default:
6562 BUG();
6563 }
6564 }
6565
6566 #define RETRY 1
6567 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6568 struct intel_crtc_state *pipe_config)
6569 {
6570 struct drm_device *dev = intel_crtc->base.dev;
6571 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6572 int lane, link_bw, fdi_dotclock, ret;
6573 bool needs_recompute = false;
6574
6575 retry:
6576 /* FDI is a binary signal running at ~2.7GHz, encoding
6577 * each output octet as 10 bits. The actual frequency
6578 * is stored as a divider into a 100MHz clock, and the
6579 * mode pixel clock is stored in units of 1KHz.
6580 * Hence the bw of each lane in terms of the mode signal
6581 * is:
6582 */
6583 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6584
6585 fdi_dotclock = adjusted_mode->crtc_clock;
6586
6587 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6588 pipe_config->pipe_bpp);
6589
6590 pipe_config->fdi_lanes = lane;
6591
6592 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6593 link_bw, &pipe_config->fdi_m_n);
6594
6595 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6596 intel_crtc->pipe, pipe_config);
6597 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6598 pipe_config->pipe_bpp -= 2*3;
6599 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6600 pipe_config->pipe_bpp);
6601 needs_recompute = true;
6602 pipe_config->bw_constrained = true;
6603
6604 goto retry;
6605 }
6606
6607 if (needs_recompute)
6608 return RETRY;
6609
6610 return ret;
6611 }
6612
6613 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6614 struct intel_crtc_state *pipe_config)
6615 {
6616 if (pipe_config->pipe_bpp > 24)
6617 return false;
6618
6619 /* HSW can handle pixel rate up to cdclk? */
6620 if (IS_HASWELL(dev_priv->dev))
6621 return true;
6622
6623 /*
6624 * We compare against max which means we must take
6625 * the increased cdclk requirement into account when
6626 * calculating the new cdclk.
6627 *
6628 * Should measure whether using a lower cdclk w/o IPS
6629 */
6630 return ilk_pipe_pixel_rate(pipe_config) <=
6631 dev_priv->max_cdclk_freq * 95 / 100;
6632 }
6633
6634 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6635 struct intel_crtc_state *pipe_config)
6636 {
6637 struct drm_device *dev = crtc->base.dev;
6638 struct drm_i915_private *dev_priv = dev->dev_private;
6639
6640 pipe_config->ips_enabled = i915.enable_ips &&
6641 hsw_crtc_supports_ips(crtc) &&
6642 pipe_config_supports_ips(dev_priv, pipe_config);
6643 }
6644
6645 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6646 {
6647 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6648
6649 /* GDG double wide on either pipe, otherwise pipe A only */
6650 return INTEL_INFO(dev_priv)->gen < 4 &&
6651 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6652 }
6653
6654 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6655 struct intel_crtc_state *pipe_config)
6656 {
6657 struct drm_device *dev = crtc->base.dev;
6658 struct drm_i915_private *dev_priv = dev->dev_private;
6659 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6660
6661 /* FIXME should check pixel clock limits on all platforms */
6662 if (INTEL_INFO(dev)->gen < 4) {
6663 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6664
6665 /*
6666 * Enable double wide mode when the dot clock
6667 * is > 90% of the (display) core speed.
6668 */
6669 if (intel_crtc_supports_double_wide(crtc) &&
6670 adjusted_mode->crtc_clock > clock_limit) {
6671 clock_limit *= 2;
6672 pipe_config->double_wide = true;
6673 }
6674
6675 if (adjusted_mode->crtc_clock > clock_limit) {
6676 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6677 adjusted_mode->crtc_clock, clock_limit,
6678 yesno(pipe_config->double_wide));
6679 return -EINVAL;
6680 }
6681 }
6682
6683 /*
6684 * Pipe horizontal size must be even in:
6685 * - DVO ganged mode
6686 * - LVDS dual channel mode
6687 * - Double wide pipe
6688 */
6689 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6690 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6691 pipe_config->pipe_src_w &= ~1;
6692
6693 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6694 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6695 */
6696 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6697 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6698 return -EINVAL;
6699
6700 if (HAS_IPS(dev))
6701 hsw_compute_ips_config(crtc, pipe_config);
6702
6703 if (pipe_config->has_pch_encoder)
6704 return ironlake_fdi_compute_config(crtc, pipe_config);
6705
6706 return 0;
6707 }
6708
6709 static int skylake_get_display_clock_speed(struct drm_device *dev)
6710 {
6711 struct drm_i915_private *dev_priv = to_i915(dev);
6712 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6713 uint32_t cdctl = I915_READ(CDCLK_CTL);
6714 uint32_t linkrate;
6715
6716 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6717 return 24000; /* 24MHz is the cd freq with NSSC ref */
6718
6719 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6720 return 540000;
6721
6722 linkrate = (I915_READ(DPLL_CTRL1) &
6723 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6724
6725 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6726 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6727 /* vco 8640 */
6728 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6729 case CDCLK_FREQ_450_432:
6730 return 432000;
6731 case CDCLK_FREQ_337_308:
6732 return 308570;
6733 case CDCLK_FREQ_675_617:
6734 return 617140;
6735 default:
6736 WARN(1, "Unknown cd freq selection\n");
6737 }
6738 } else {
6739 /* vco 8100 */
6740 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6741 case CDCLK_FREQ_450_432:
6742 return 450000;
6743 case CDCLK_FREQ_337_308:
6744 return 337500;
6745 case CDCLK_FREQ_675_617:
6746 return 675000;
6747 default:
6748 WARN(1, "Unknown cd freq selection\n");
6749 }
6750 }
6751
6752 /* error case, do as if DPLL0 isn't enabled */
6753 return 24000;
6754 }
6755
6756 static int broxton_get_display_clock_speed(struct drm_device *dev)
6757 {
6758 struct drm_i915_private *dev_priv = to_i915(dev);
6759 uint32_t cdctl = I915_READ(CDCLK_CTL);
6760 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6761 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6762 int cdclk;
6763
6764 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6765 return 19200;
6766
6767 cdclk = 19200 * pll_ratio / 2;
6768
6769 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6770 case BXT_CDCLK_CD2X_DIV_SEL_1:
6771 return cdclk; /* 576MHz or 624MHz */
6772 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6773 return cdclk * 2 / 3; /* 384MHz */
6774 case BXT_CDCLK_CD2X_DIV_SEL_2:
6775 return cdclk / 2; /* 288MHz */
6776 case BXT_CDCLK_CD2X_DIV_SEL_4:
6777 return cdclk / 4; /* 144MHz */
6778 }
6779
6780 /* error case, do as if DE PLL isn't enabled */
6781 return 19200;
6782 }
6783
6784 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6785 {
6786 struct drm_i915_private *dev_priv = dev->dev_private;
6787 uint32_t lcpll = I915_READ(LCPLL_CTL);
6788 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6789
6790 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6791 return 800000;
6792 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6793 return 450000;
6794 else if (freq == LCPLL_CLK_FREQ_450)
6795 return 450000;
6796 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6797 return 540000;
6798 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6799 return 337500;
6800 else
6801 return 675000;
6802 }
6803
6804 static int haswell_get_display_clock_speed(struct drm_device *dev)
6805 {
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 uint32_t lcpll = I915_READ(LCPLL_CTL);
6808 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6809
6810 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6811 return 800000;
6812 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6813 return 450000;
6814 else if (freq == LCPLL_CLK_FREQ_450)
6815 return 450000;
6816 else if (IS_HSW_ULT(dev))
6817 return 337500;
6818 else
6819 return 540000;
6820 }
6821
6822 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6823 {
6824 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6825 CCK_DISPLAY_CLOCK_CONTROL);
6826 }
6827
6828 static int ilk_get_display_clock_speed(struct drm_device *dev)
6829 {
6830 return 450000;
6831 }
6832
6833 static int i945_get_display_clock_speed(struct drm_device *dev)
6834 {
6835 return 400000;
6836 }
6837
6838 static int i915_get_display_clock_speed(struct drm_device *dev)
6839 {
6840 return 333333;
6841 }
6842
6843 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6844 {
6845 return 200000;
6846 }
6847
6848 static int pnv_get_display_clock_speed(struct drm_device *dev)
6849 {
6850 u16 gcfgc = 0;
6851
6852 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6853
6854 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6855 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6856 return 266667;
6857 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6858 return 333333;
6859 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6860 return 444444;
6861 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6862 return 200000;
6863 default:
6864 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6865 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6866 return 133333;
6867 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6868 return 166667;
6869 }
6870 }
6871
6872 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6873 {
6874 u16 gcfgc = 0;
6875
6876 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6877
6878 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6879 return 133333;
6880 else {
6881 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6882 case GC_DISPLAY_CLOCK_333_MHZ:
6883 return 333333;
6884 default:
6885 case GC_DISPLAY_CLOCK_190_200_MHZ:
6886 return 190000;
6887 }
6888 }
6889 }
6890
6891 static int i865_get_display_clock_speed(struct drm_device *dev)
6892 {
6893 return 266667;
6894 }
6895
6896 static int i85x_get_display_clock_speed(struct drm_device *dev)
6897 {
6898 u16 hpllcc = 0;
6899
6900 /*
6901 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6902 * encoding is different :(
6903 * FIXME is this the right way to detect 852GM/852GMV?
6904 */
6905 if (dev->pdev->revision == 0x1)
6906 return 133333;
6907
6908 pci_bus_read_config_word(dev->pdev->bus,
6909 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6910
6911 /* Assume that the hardware is in the high speed state. This
6912 * should be the default.
6913 */
6914 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6915 case GC_CLOCK_133_200:
6916 case GC_CLOCK_133_200_2:
6917 case GC_CLOCK_100_200:
6918 return 200000;
6919 case GC_CLOCK_166_250:
6920 return 250000;
6921 case GC_CLOCK_100_133:
6922 return 133333;
6923 case GC_CLOCK_133_266:
6924 case GC_CLOCK_133_266_2:
6925 case GC_CLOCK_166_266:
6926 return 266667;
6927 }
6928
6929 /* Shouldn't happen */
6930 return 0;
6931 }
6932
6933 static int i830_get_display_clock_speed(struct drm_device *dev)
6934 {
6935 return 133333;
6936 }
6937
6938 static unsigned int intel_hpll_vco(struct drm_device *dev)
6939 {
6940 struct drm_i915_private *dev_priv = dev->dev_private;
6941 static const unsigned int blb_vco[8] = {
6942 [0] = 3200000,
6943 [1] = 4000000,
6944 [2] = 5333333,
6945 [3] = 4800000,
6946 [4] = 6400000,
6947 };
6948 static const unsigned int pnv_vco[8] = {
6949 [0] = 3200000,
6950 [1] = 4000000,
6951 [2] = 5333333,
6952 [3] = 4800000,
6953 [4] = 2666667,
6954 };
6955 static const unsigned int cl_vco[8] = {
6956 [0] = 3200000,
6957 [1] = 4000000,
6958 [2] = 5333333,
6959 [3] = 6400000,
6960 [4] = 3333333,
6961 [5] = 3566667,
6962 [6] = 4266667,
6963 };
6964 static const unsigned int elk_vco[8] = {
6965 [0] = 3200000,
6966 [1] = 4000000,
6967 [2] = 5333333,
6968 [3] = 4800000,
6969 };
6970 static const unsigned int ctg_vco[8] = {
6971 [0] = 3200000,
6972 [1] = 4000000,
6973 [2] = 5333333,
6974 [3] = 6400000,
6975 [4] = 2666667,
6976 [5] = 4266667,
6977 };
6978 const unsigned int *vco_table;
6979 unsigned int vco;
6980 uint8_t tmp = 0;
6981
6982 /* FIXME other chipsets? */
6983 if (IS_GM45(dev))
6984 vco_table = ctg_vco;
6985 else if (IS_G4X(dev))
6986 vco_table = elk_vco;
6987 else if (IS_CRESTLINE(dev))
6988 vco_table = cl_vco;
6989 else if (IS_PINEVIEW(dev))
6990 vco_table = pnv_vco;
6991 else if (IS_G33(dev))
6992 vco_table = blb_vco;
6993 else
6994 return 0;
6995
6996 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6997
6998 vco = vco_table[tmp & 0x7];
6999 if (vco == 0)
7000 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7001 else
7002 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7003
7004 return vco;
7005 }
7006
7007 static int gm45_get_display_clock_speed(struct drm_device *dev)
7008 {
7009 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7010 uint16_t tmp = 0;
7011
7012 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7013
7014 cdclk_sel = (tmp >> 12) & 0x1;
7015
7016 switch (vco) {
7017 case 2666667:
7018 case 4000000:
7019 case 5333333:
7020 return cdclk_sel ? 333333 : 222222;
7021 case 3200000:
7022 return cdclk_sel ? 320000 : 228571;
7023 default:
7024 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7025 return 222222;
7026 }
7027 }
7028
7029 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7030 {
7031 static const uint8_t div_3200[] = { 16, 10, 8 };
7032 static const uint8_t div_4000[] = { 20, 12, 10 };
7033 static const uint8_t div_5333[] = { 24, 16, 14 };
7034 const uint8_t *div_table;
7035 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7036 uint16_t tmp = 0;
7037
7038 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7039
7040 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7041
7042 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7043 goto fail;
7044
7045 switch (vco) {
7046 case 3200000:
7047 div_table = div_3200;
7048 break;
7049 case 4000000:
7050 div_table = div_4000;
7051 break;
7052 case 5333333:
7053 div_table = div_5333;
7054 break;
7055 default:
7056 goto fail;
7057 }
7058
7059 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7060
7061 fail:
7062 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7063 return 200000;
7064 }
7065
7066 static int g33_get_display_clock_speed(struct drm_device *dev)
7067 {
7068 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7069 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7070 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7071 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7072 const uint8_t *div_table;
7073 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7074 uint16_t tmp = 0;
7075
7076 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7077
7078 cdclk_sel = (tmp >> 4) & 0x7;
7079
7080 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7081 goto fail;
7082
7083 switch (vco) {
7084 case 3200000:
7085 div_table = div_3200;
7086 break;
7087 case 4000000:
7088 div_table = div_4000;
7089 break;
7090 case 4800000:
7091 div_table = div_4800;
7092 break;
7093 case 5333333:
7094 div_table = div_5333;
7095 break;
7096 default:
7097 goto fail;
7098 }
7099
7100 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7101
7102 fail:
7103 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7104 return 190476;
7105 }
7106
7107 static void
7108 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7109 {
7110 while (*num > DATA_LINK_M_N_MASK ||
7111 *den > DATA_LINK_M_N_MASK) {
7112 *num >>= 1;
7113 *den >>= 1;
7114 }
7115 }
7116
7117 static void compute_m_n(unsigned int m, unsigned int n,
7118 uint32_t *ret_m, uint32_t *ret_n)
7119 {
7120 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7121 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7122 intel_reduce_m_n_ratio(ret_m, ret_n);
7123 }
7124
7125 void
7126 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7127 int pixel_clock, int link_clock,
7128 struct intel_link_m_n *m_n)
7129 {
7130 m_n->tu = 64;
7131
7132 compute_m_n(bits_per_pixel * pixel_clock,
7133 link_clock * nlanes * 8,
7134 &m_n->gmch_m, &m_n->gmch_n);
7135
7136 compute_m_n(pixel_clock, link_clock,
7137 &m_n->link_m, &m_n->link_n);
7138 }
7139
7140 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7141 {
7142 if (i915.panel_use_ssc >= 0)
7143 return i915.panel_use_ssc != 0;
7144 return dev_priv->vbt.lvds_use_ssc
7145 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7146 }
7147
7148 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7149 int num_connectors)
7150 {
7151 struct drm_device *dev = crtc_state->base.crtc->dev;
7152 struct drm_i915_private *dev_priv = dev->dev_private;
7153 int refclk;
7154
7155 WARN_ON(!crtc_state->base.state);
7156
7157 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
7158 refclk = 100000;
7159 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7160 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7161 refclk = dev_priv->vbt.lvds_ssc_freq;
7162 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7163 } else if (!IS_GEN2(dev)) {
7164 refclk = 96000;
7165 } else {
7166 refclk = 48000;
7167 }
7168
7169 return refclk;
7170 }
7171
7172 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7173 {
7174 return (1 << dpll->n) << 16 | dpll->m2;
7175 }
7176
7177 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7178 {
7179 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7180 }
7181
7182 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7183 struct intel_crtc_state *crtc_state,
7184 intel_clock_t *reduced_clock)
7185 {
7186 struct drm_device *dev = crtc->base.dev;
7187 u32 fp, fp2 = 0;
7188
7189 if (IS_PINEVIEW(dev)) {
7190 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7191 if (reduced_clock)
7192 fp2 = pnv_dpll_compute_fp(reduced_clock);
7193 } else {
7194 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7195 if (reduced_clock)
7196 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7197 }
7198
7199 crtc_state->dpll_hw_state.fp0 = fp;
7200
7201 crtc->lowfreq_avail = false;
7202 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7203 reduced_clock) {
7204 crtc_state->dpll_hw_state.fp1 = fp2;
7205 crtc->lowfreq_avail = true;
7206 } else {
7207 crtc_state->dpll_hw_state.fp1 = fp;
7208 }
7209 }
7210
7211 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7212 pipe)
7213 {
7214 u32 reg_val;
7215
7216 /*
7217 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7218 * and set it to a reasonable value instead.
7219 */
7220 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7221 reg_val &= 0xffffff00;
7222 reg_val |= 0x00000030;
7223 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7224
7225 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7226 reg_val &= 0x8cffffff;
7227 reg_val = 0x8c000000;
7228 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7229
7230 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7231 reg_val &= 0xffffff00;
7232 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7233
7234 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7235 reg_val &= 0x00ffffff;
7236 reg_val |= 0xb0000000;
7237 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7238 }
7239
7240 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7241 struct intel_link_m_n *m_n)
7242 {
7243 struct drm_device *dev = crtc->base.dev;
7244 struct drm_i915_private *dev_priv = dev->dev_private;
7245 int pipe = crtc->pipe;
7246
7247 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7248 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7249 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7250 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7251 }
7252
7253 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7254 struct intel_link_m_n *m_n,
7255 struct intel_link_m_n *m2_n2)
7256 {
7257 struct drm_device *dev = crtc->base.dev;
7258 struct drm_i915_private *dev_priv = dev->dev_private;
7259 int pipe = crtc->pipe;
7260 enum transcoder transcoder = crtc->config->cpu_transcoder;
7261
7262 if (INTEL_INFO(dev)->gen >= 5) {
7263 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7264 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7265 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7266 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7267 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7268 * for gen < 8) and if DRRS is supported (to make sure the
7269 * registers are not unnecessarily accessed).
7270 */
7271 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7272 crtc->config->has_drrs) {
7273 I915_WRITE(PIPE_DATA_M2(transcoder),
7274 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7275 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7276 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7277 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7278 }
7279 } else {
7280 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7281 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7282 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7283 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7284 }
7285 }
7286
7287 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7288 {
7289 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7290
7291 if (m_n == M1_N1) {
7292 dp_m_n = &crtc->config->dp_m_n;
7293 dp_m2_n2 = &crtc->config->dp_m2_n2;
7294 } else if (m_n == M2_N2) {
7295
7296 /*
7297 * M2_N2 registers are not supported. Hence m2_n2 divider value
7298 * needs to be programmed into M1_N1.
7299 */
7300 dp_m_n = &crtc->config->dp_m2_n2;
7301 } else {
7302 DRM_ERROR("Unsupported divider value\n");
7303 return;
7304 }
7305
7306 if (crtc->config->has_pch_encoder)
7307 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7308 else
7309 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7310 }
7311
7312 static void vlv_compute_dpll(struct intel_crtc *crtc,
7313 struct intel_crtc_state *pipe_config)
7314 {
7315 u32 dpll, dpll_md;
7316
7317 /*
7318 * Enable DPIO clock input. We should never disable the reference
7319 * clock for pipe B, since VGA hotplug / manual detection depends
7320 * on it.
7321 */
7322 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7323 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7324 /* We should never disable this, set it here for state tracking */
7325 if (crtc->pipe == PIPE_B)
7326 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7327 dpll |= DPLL_VCO_ENABLE;
7328 pipe_config->dpll_hw_state.dpll = dpll;
7329
7330 dpll_md = (pipe_config->pixel_multiplier - 1)
7331 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7332 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7333 }
7334
7335 static void vlv_prepare_pll(struct intel_crtc *crtc,
7336 const struct intel_crtc_state *pipe_config)
7337 {
7338 struct drm_device *dev = crtc->base.dev;
7339 struct drm_i915_private *dev_priv = dev->dev_private;
7340 int pipe = crtc->pipe;
7341 u32 mdiv;
7342 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7343 u32 coreclk, reg_val;
7344
7345 mutex_lock(&dev_priv->sb_lock);
7346
7347 bestn = pipe_config->dpll.n;
7348 bestm1 = pipe_config->dpll.m1;
7349 bestm2 = pipe_config->dpll.m2;
7350 bestp1 = pipe_config->dpll.p1;
7351 bestp2 = pipe_config->dpll.p2;
7352
7353 /* See eDP HDMI DPIO driver vbios notes doc */
7354
7355 /* PLL B needs special handling */
7356 if (pipe == PIPE_B)
7357 vlv_pllb_recal_opamp(dev_priv, pipe);
7358
7359 /* Set up Tx target for periodic Rcomp update */
7360 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7361
7362 /* Disable target IRef on PLL */
7363 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7364 reg_val &= 0x00ffffff;
7365 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7366
7367 /* Disable fast lock */
7368 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7369
7370 /* Set idtafcrecal before PLL is enabled */
7371 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7372 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7373 mdiv |= ((bestn << DPIO_N_SHIFT));
7374 mdiv |= (1 << DPIO_K_SHIFT);
7375
7376 /*
7377 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7378 * but we don't support that).
7379 * Note: don't use the DAC post divider as it seems unstable.
7380 */
7381 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7382 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7383
7384 mdiv |= DPIO_ENABLE_CALIBRATION;
7385 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7386
7387 /* Set HBR and RBR LPF coefficients */
7388 if (pipe_config->port_clock == 162000 ||
7389 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7390 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7391 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7392 0x009f0003);
7393 else
7394 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7395 0x00d0000f);
7396
7397 if (pipe_config->has_dp_encoder) {
7398 /* Use SSC source */
7399 if (pipe == PIPE_A)
7400 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7401 0x0df40000);
7402 else
7403 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7404 0x0df70000);
7405 } else { /* HDMI or VGA */
7406 /* Use bend source */
7407 if (pipe == PIPE_A)
7408 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7409 0x0df70000);
7410 else
7411 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7412 0x0df40000);
7413 }
7414
7415 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7416 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7417 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7418 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7419 coreclk |= 0x01000000;
7420 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7421
7422 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7423 mutex_unlock(&dev_priv->sb_lock);
7424 }
7425
7426 static void chv_compute_dpll(struct intel_crtc *crtc,
7427 struct intel_crtc_state *pipe_config)
7428 {
7429 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7430 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7431 DPLL_VCO_ENABLE;
7432 if (crtc->pipe != PIPE_A)
7433 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7434
7435 pipe_config->dpll_hw_state.dpll_md =
7436 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7437 }
7438
7439 static void chv_prepare_pll(struct intel_crtc *crtc,
7440 const struct intel_crtc_state *pipe_config)
7441 {
7442 struct drm_device *dev = crtc->base.dev;
7443 struct drm_i915_private *dev_priv = dev->dev_private;
7444 int pipe = crtc->pipe;
7445 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7446 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7447 u32 loopfilter, tribuf_calcntr;
7448 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7449 u32 dpio_val;
7450 int vco;
7451
7452 bestn = pipe_config->dpll.n;
7453 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7454 bestm1 = pipe_config->dpll.m1;
7455 bestm2 = pipe_config->dpll.m2 >> 22;
7456 bestp1 = pipe_config->dpll.p1;
7457 bestp2 = pipe_config->dpll.p2;
7458 vco = pipe_config->dpll.vco;
7459 dpio_val = 0;
7460 loopfilter = 0;
7461
7462 /*
7463 * Enable Refclk and SSC
7464 */
7465 I915_WRITE(dpll_reg,
7466 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7467
7468 mutex_lock(&dev_priv->sb_lock);
7469
7470 /* p1 and p2 divider */
7471 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7472 5 << DPIO_CHV_S1_DIV_SHIFT |
7473 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7474 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7475 1 << DPIO_CHV_K_DIV_SHIFT);
7476
7477 /* Feedback post-divider - m2 */
7478 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7479
7480 /* Feedback refclk divider - n and m1 */
7481 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7482 DPIO_CHV_M1_DIV_BY_2 |
7483 1 << DPIO_CHV_N_DIV_SHIFT);
7484
7485 /* M2 fraction division */
7486 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7487
7488 /* M2 fraction division enable */
7489 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7490 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7491 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7492 if (bestm2_frac)
7493 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7494 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7495
7496 /* Program digital lock detect threshold */
7497 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7498 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7499 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7500 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7501 if (!bestm2_frac)
7502 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7503 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7504
7505 /* Loop filter */
7506 if (vco == 5400000) {
7507 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7508 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7509 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7510 tribuf_calcntr = 0x9;
7511 } else if (vco <= 6200000) {
7512 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7513 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7514 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7515 tribuf_calcntr = 0x9;
7516 } else if (vco <= 6480000) {
7517 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7518 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7519 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7520 tribuf_calcntr = 0x8;
7521 } else {
7522 /* Not supported. Apply the same limits as in the max case */
7523 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7524 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7525 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7526 tribuf_calcntr = 0;
7527 }
7528 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7529
7530 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7531 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7532 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7533 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7534
7535 /* AFC Recal */
7536 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7537 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7538 DPIO_AFC_RECAL);
7539
7540 mutex_unlock(&dev_priv->sb_lock);
7541 }
7542
7543 /**
7544 * vlv_force_pll_on - forcibly enable just the PLL
7545 * @dev_priv: i915 private structure
7546 * @pipe: pipe PLL to enable
7547 * @dpll: PLL configuration
7548 *
7549 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7550 * in cases where we need the PLL enabled even when @pipe is not going to
7551 * be enabled.
7552 */
7553 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7554 const struct dpll *dpll)
7555 {
7556 struct intel_crtc *crtc =
7557 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7558 struct intel_crtc_state pipe_config = {
7559 .base.crtc = &crtc->base,
7560 .pixel_multiplier = 1,
7561 .dpll = *dpll,
7562 };
7563
7564 if (IS_CHERRYVIEW(dev)) {
7565 chv_compute_dpll(crtc, &pipe_config);
7566 chv_prepare_pll(crtc, &pipe_config);
7567 chv_enable_pll(crtc, &pipe_config);
7568 } else {
7569 vlv_compute_dpll(crtc, &pipe_config);
7570 vlv_prepare_pll(crtc, &pipe_config);
7571 vlv_enable_pll(crtc, &pipe_config);
7572 }
7573 }
7574
7575 /**
7576 * vlv_force_pll_off - forcibly disable just the PLL
7577 * @dev_priv: i915 private structure
7578 * @pipe: pipe PLL to disable
7579 *
7580 * Disable the PLL for @pipe. To be used in cases where we need
7581 * the PLL enabled even when @pipe is not going to be enabled.
7582 */
7583 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7584 {
7585 if (IS_CHERRYVIEW(dev))
7586 chv_disable_pll(to_i915(dev), pipe);
7587 else
7588 vlv_disable_pll(to_i915(dev), pipe);
7589 }
7590
7591 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7592 struct intel_crtc_state *crtc_state,
7593 intel_clock_t *reduced_clock,
7594 int num_connectors)
7595 {
7596 struct drm_device *dev = crtc->base.dev;
7597 struct drm_i915_private *dev_priv = dev->dev_private;
7598 u32 dpll;
7599 bool is_sdvo;
7600 struct dpll *clock = &crtc_state->dpll;
7601
7602 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7603
7604 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7605 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7606
7607 dpll = DPLL_VGA_MODE_DIS;
7608
7609 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7610 dpll |= DPLLB_MODE_LVDS;
7611 else
7612 dpll |= DPLLB_MODE_DAC_SERIAL;
7613
7614 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7615 dpll |= (crtc_state->pixel_multiplier - 1)
7616 << SDVO_MULTIPLIER_SHIFT_HIRES;
7617 }
7618
7619 if (is_sdvo)
7620 dpll |= DPLL_SDVO_HIGH_SPEED;
7621
7622 if (crtc_state->has_dp_encoder)
7623 dpll |= DPLL_SDVO_HIGH_SPEED;
7624
7625 /* compute bitmask from p1 value */
7626 if (IS_PINEVIEW(dev))
7627 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7628 else {
7629 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7630 if (IS_G4X(dev) && reduced_clock)
7631 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7632 }
7633 switch (clock->p2) {
7634 case 5:
7635 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7636 break;
7637 case 7:
7638 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7639 break;
7640 case 10:
7641 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7642 break;
7643 case 14:
7644 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7645 break;
7646 }
7647 if (INTEL_INFO(dev)->gen >= 4)
7648 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7649
7650 if (crtc_state->sdvo_tv_clock)
7651 dpll |= PLL_REF_INPUT_TVCLKINBC;
7652 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7653 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7654 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7655 else
7656 dpll |= PLL_REF_INPUT_DREFCLK;
7657
7658 dpll |= DPLL_VCO_ENABLE;
7659 crtc_state->dpll_hw_state.dpll = dpll;
7660
7661 if (INTEL_INFO(dev)->gen >= 4) {
7662 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7663 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7664 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7665 }
7666 }
7667
7668 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7669 struct intel_crtc_state *crtc_state,
7670 intel_clock_t *reduced_clock,
7671 int num_connectors)
7672 {
7673 struct drm_device *dev = crtc->base.dev;
7674 struct drm_i915_private *dev_priv = dev->dev_private;
7675 u32 dpll;
7676 struct dpll *clock = &crtc_state->dpll;
7677
7678 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7679
7680 dpll = DPLL_VGA_MODE_DIS;
7681
7682 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7683 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7684 } else {
7685 if (clock->p1 == 2)
7686 dpll |= PLL_P1_DIVIDE_BY_TWO;
7687 else
7688 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7689 if (clock->p2 == 4)
7690 dpll |= PLL_P2_DIVIDE_BY_4;
7691 }
7692
7693 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7694 dpll |= DPLL_DVO_2X_MODE;
7695
7696 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7697 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7698 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7699 else
7700 dpll |= PLL_REF_INPUT_DREFCLK;
7701
7702 dpll |= DPLL_VCO_ENABLE;
7703 crtc_state->dpll_hw_state.dpll = dpll;
7704 }
7705
7706 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7707 {
7708 struct drm_device *dev = intel_crtc->base.dev;
7709 struct drm_i915_private *dev_priv = dev->dev_private;
7710 enum pipe pipe = intel_crtc->pipe;
7711 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7712 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7713 uint32_t crtc_vtotal, crtc_vblank_end;
7714 int vsyncshift = 0;
7715
7716 /* We need to be careful not to changed the adjusted mode, for otherwise
7717 * the hw state checker will get angry at the mismatch. */
7718 crtc_vtotal = adjusted_mode->crtc_vtotal;
7719 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7720
7721 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7722 /* the chip adds 2 halflines automatically */
7723 crtc_vtotal -= 1;
7724 crtc_vblank_end -= 1;
7725
7726 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7727 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7728 else
7729 vsyncshift = adjusted_mode->crtc_hsync_start -
7730 adjusted_mode->crtc_htotal / 2;
7731 if (vsyncshift < 0)
7732 vsyncshift += adjusted_mode->crtc_htotal;
7733 }
7734
7735 if (INTEL_INFO(dev)->gen > 3)
7736 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7737
7738 I915_WRITE(HTOTAL(cpu_transcoder),
7739 (adjusted_mode->crtc_hdisplay - 1) |
7740 ((adjusted_mode->crtc_htotal - 1) << 16));
7741 I915_WRITE(HBLANK(cpu_transcoder),
7742 (adjusted_mode->crtc_hblank_start - 1) |
7743 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7744 I915_WRITE(HSYNC(cpu_transcoder),
7745 (adjusted_mode->crtc_hsync_start - 1) |
7746 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7747
7748 I915_WRITE(VTOTAL(cpu_transcoder),
7749 (adjusted_mode->crtc_vdisplay - 1) |
7750 ((crtc_vtotal - 1) << 16));
7751 I915_WRITE(VBLANK(cpu_transcoder),
7752 (adjusted_mode->crtc_vblank_start - 1) |
7753 ((crtc_vblank_end - 1) << 16));
7754 I915_WRITE(VSYNC(cpu_transcoder),
7755 (adjusted_mode->crtc_vsync_start - 1) |
7756 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7757
7758 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7759 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7760 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7761 * bits. */
7762 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7763 (pipe == PIPE_B || pipe == PIPE_C))
7764 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7765
7766 /* pipesrc controls the size that is scaled from, which should
7767 * always be the user's requested size.
7768 */
7769 I915_WRITE(PIPESRC(pipe),
7770 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7771 (intel_crtc->config->pipe_src_h - 1));
7772 }
7773
7774 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7775 struct intel_crtc_state *pipe_config)
7776 {
7777 struct drm_device *dev = crtc->base.dev;
7778 struct drm_i915_private *dev_priv = dev->dev_private;
7779 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7780 uint32_t tmp;
7781
7782 tmp = I915_READ(HTOTAL(cpu_transcoder));
7783 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7784 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7785 tmp = I915_READ(HBLANK(cpu_transcoder));
7786 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7787 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7788 tmp = I915_READ(HSYNC(cpu_transcoder));
7789 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7790 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7791
7792 tmp = I915_READ(VTOTAL(cpu_transcoder));
7793 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7794 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7795 tmp = I915_READ(VBLANK(cpu_transcoder));
7796 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7797 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7798 tmp = I915_READ(VSYNC(cpu_transcoder));
7799 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7800 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7801
7802 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7803 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7804 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7805 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7806 }
7807
7808 tmp = I915_READ(PIPESRC(crtc->pipe));
7809 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7810 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7811
7812 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7813 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7814 }
7815
7816 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7817 struct intel_crtc_state *pipe_config)
7818 {
7819 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7820 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7821 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7822 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7823
7824 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7825 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7826 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7827 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7828
7829 mode->flags = pipe_config->base.adjusted_mode.flags;
7830 mode->type = DRM_MODE_TYPE_DRIVER;
7831
7832 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7833 mode->flags |= pipe_config->base.adjusted_mode.flags;
7834
7835 mode->hsync = drm_mode_hsync(mode);
7836 mode->vrefresh = drm_mode_vrefresh(mode);
7837 drm_mode_set_name(mode);
7838 }
7839
7840 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7841 {
7842 struct drm_device *dev = intel_crtc->base.dev;
7843 struct drm_i915_private *dev_priv = dev->dev_private;
7844 uint32_t pipeconf;
7845
7846 pipeconf = 0;
7847
7848 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7849 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7850 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7851
7852 if (intel_crtc->config->double_wide)
7853 pipeconf |= PIPECONF_DOUBLE_WIDE;
7854
7855 /* only g4x and later have fancy bpc/dither controls */
7856 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7857 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7858 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7859 pipeconf |= PIPECONF_DITHER_EN |
7860 PIPECONF_DITHER_TYPE_SP;
7861
7862 switch (intel_crtc->config->pipe_bpp) {
7863 case 18:
7864 pipeconf |= PIPECONF_6BPC;
7865 break;
7866 case 24:
7867 pipeconf |= PIPECONF_8BPC;
7868 break;
7869 case 30:
7870 pipeconf |= PIPECONF_10BPC;
7871 break;
7872 default:
7873 /* Case prevented by intel_choose_pipe_bpp_dither. */
7874 BUG();
7875 }
7876 }
7877
7878 if (HAS_PIPE_CXSR(dev)) {
7879 if (intel_crtc->lowfreq_avail) {
7880 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7881 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7882 } else {
7883 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7884 }
7885 }
7886
7887 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7888 if (INTEL_INFO(dev)->gen < 4 ||
7889 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7890 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7891 else
7892 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7893 } else
7894 pipeconf |= PIPECONF_PROGRESSIVE;
7895
7896 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7897 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7898
7899 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7900 POSTING_READ(PIPECONF(intel_crtc->pipe));
7901 }
7902
7903 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7904 struct intel_crtc_state *crtc_state)
7905 {
7906 struct drm_device *dev = crtc->base.dev;
7907 struct drm_i915_private *dev_priv = dev->dev_private;
7908 int refclk, num_connectors = 0;
7909 intel_clock_t clock;
7910 bool ok;
7911 bool is_dsi = false;
7912 struct intel_encoder *encoder;
7913 const intel_limit_t *limit;
7914 struct drm_atomic_state *state = crtc_state->base.state;
7915 struct drm_connector *connector;
7916 struct drm_connector_state *connector_state;
7917 int i;
7918
7919 memset(&crtc_state->dpll_hw_state, 0,
7920 sizeof(crtc_state->dpll_hw_state));
7921
7922 for_each_connector_in_state(state, connector, connector_state, i) {
7923 if (connector_state->crtc != &crtc->base)
7924 continue;
7925
7926 encoder = to_intel_encoder(connector_state->best_encoder);
7927
7928 switch (encoder->type) {
7929 case INTEL_OUTPUT_DSI:
7930 is_dsi = true;
7931 break;
7932 default:
7933 break;
7934 }
7935
7936 num_connectors++;
7937 }
7938
7939 if (is_dsi)
7940 return 0;
7941
7942 if (!crtc_state->clock_set) {
7943 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7944
7945 /*
7946 * Returns a set of divisors for the desired target clock with
7947 * the given refclk, or FALSE. The returned values represent
7948 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7949 * 2) / p1 / p2.
7950 */
7951 limit = intel_limit(crtc_state, refclk);
7952 ok = dev_priv->display.find_dpll(limit, crtc_state,
7953 crtc_state->port_clock,
7954 refclk, NULL, &clock);
7955 if (!ok) {
7956 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7957 return -EINVAL;
7958 }
7959
7960 /* Compat-code for transition, will disappear. */
7961 crtc_state->dpll.n = clock.n;
7962 crtc_state->dpll.m1 = clock.m1;
7963 crtc_state->dpll.m2 = clock.m2;
7964 crtc_state->dpll.p1 = clock.p1;
7965 crtc_state->dpll.p2 = clock.p2;
7966 }
7967
7968 if (IS_GEN2(dev)) {
7969 i8xx_compute_dpll(crtc, crtc_state, NULL,
7970 num_connectors);
7971 } else if (IS_CHERRYVIEW(dev)) {
7972 chv_compute_dpll(crtc, crtc_state);
7973 } else if (IS_VALLEYVIEW(dev)) {
7974 vlv_compute_dpll(crtc, crtc_state);
7975 } else {
7976 i9xx_compute_dpll(crtc, crtc_state, NULL,
7977 num_connectors);
7978 }
7979
7980 return 0;
7981 }
7982
7983 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7984 struct intel_crtc_state *pipe_config)
7985 {
7986 struct drm_device *dev = crtc->base.dev;
7987 struct drm_i915_private *dev_priv = dev->dev_private;
7988 uint32_t tmp;
7989
7990 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7991 return;
7992
7993 tmp = I915_READ(PFIT_CONTROL);
7994 if (!(tmp & PFIT_ENABLE))
7995 return;
7996
7997 /* Check whether the pfit is attached to our pipe. */
7998 if (INTEL_INFO(dev)->gen < 4) {
7999 if (crtc->pipe != PIPE_B)
8000 return;
8001 } else {
8002 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8003 return;
8004 }
8005
8006 pipe_config->gmch_pfit.control = tmp;
8007 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8008 if (INTEL_INFO(dev)->gen < 5)
8009 pipe_config->gmch_pfit.lvds_border_bits =
8010 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8011 }
8012
8013 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8014 struct intel_crtc_state *pipe_config)
8015 {
8016 struct drm_device *dev = crtc->base.dev;
8017 struct drm_i915_private *dev_priv = dev->dev_private;
8018 int pipe = pipe_config->cpu_transcoder;
8019 intel_clock_t clock;
8020 u32 mdiv;
8021 int refclk = 100000;
8022
8023 /* In case of MIPI DPLL will not even be used */
8024 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8025 return;
8026
8027 mutex_lock(&dev_priv->sb_lock);
8028 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8029 mutex_unlock(&dev_priv->sb_lock);
8030
8031 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8032 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8033 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8034 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8035 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8036
8037 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8038 }
8039
8040 static void
8041 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8042 struct intel_initial_plane_config *plane_config)
8043 {
8044 struct drm_device *dev = crtc->base.dev;
8045 struct drm_i915_private *dev_priv = dev->dev_private;
8046 u32 val, base, offset;
8047 int pipe = crtc->pipe, plane = crtc->plane;
8048 int fourcc, pixel_format;
8049 unsigned int aligned_height;
8050 struct drm_framebuffer *fb;
8051 struct intel_framebuffer *intel_fb;
8052
8053 val = I915_READ(DSPCNTR(plane));
8054 if (!(val & DISPLAY_PLANE_ENABLE))
8055 return;
8056
8057 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8058 if (!intel_fb) {
8059 DRM_DEBUG_KMS("failed to alloc fb\n");
8060 return;
8061 }
8062
8063 fb = &intel_fb->base;
8064
8065 if (INTEL_INFO(dev)->gen >= 4) {
8066 if (val & DISPPLANE_TILED) {
8067 plane_config->tiling = I915_TILING_X;
8068 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8069 }
8070 }
8071
8072 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8073 fourcc = i9xx_format_to_fourcc(pixel_format);
8074 fb->pixel_format = fourcc;
8075 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8076
8077 if (INTEL_INFO(dev)->gen >= 4) {
8078 if (plane_config->tiling)
8079 offset = I915_READ(DSPTILEOFF(plane));
8080 else
8081 offset = I915_READ(DSPLINOFF(plane));
8082 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8083 } else {
8084 base = I915_READ(DSPADDR(plane));
8085 }
8086 plane_config->base = base;
8087
8088 val = I915_READ(PIPESRC(pipe));
8089 fb->width = ((val >> 16) & 0xfff) + 1;
8090 fb->height = ((val >> 0) & 0xfff) + 1;
8091
8092 val = I915_READ(DSPSTRIDE(pipe));
8093 fb->pitches[0] = val & 0xffffffc0;
8094
8095 aligned_height = intel_fb_align_height(dev, fb->height,
8096 fb->pixel_format,
8097 fb->modifier[0]);
8098
8099 plane_config->size = fb->pitches[0] * aligned_height;
8100
8101 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8102 pipe_name(pipe), plane, fb->width, fb->height,
8103 fb->bits_per_pixel, base, fb->pitches[0],
8104 plane_config->size);
8105
8106 plane_config->fb = intel_fb;
8107 }
8108
8109 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8110 struct intel_crtc_state *pipe_config)
8111 {
8112 struct drm_device *dev = crtc->base.dev;
8113 struct drm_i915_private *dev_priv = dev->dev_private;
8114 int pipe = pipe_config->cpu_transcoder;
8115 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8116 intel_clock_t clock;
8117 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8118 int refclk = 100000;
8119
8120 mutex_lock(&dev_priv->sb_lock);
8121 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8122 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8123 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8124 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8125 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8126 mutex_unlock(&dev_priv->sb_lock);
8127
8128 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8129 clock.m2 = (pll_dw0 & 0xff) << 22;
8130 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8131 clock.m2 |= pll_dw2 & 0x3fffff;
8132 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8133 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8134 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8135
8136 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8137 }
8138
8139 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8140 struct intel_crtc_state *pipe_config)
8141 {
8142 struct drm_device *dev = crtc->base.dev;
8143 struct drm_i915_private *dev_priv = dev->dev_private;
8144 uint32_t tmp;
8145
8146 if (!intel_display_power_is_enabled(dev_priv,
8147 POWER_DOMAIN_PIPE(crtc->pipe)))
8148 return false;
8149
8150 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8151 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8152
8153 tmp = I915_READ(PIPECONF(crtc->pipe));
8154 if (!(tmp & PIPECONF_ENABLE))
8155 return false;
8156
8157 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8158 switch (tmp & PIPECONF_BPC_MASK) {
8159 case PIPECONF_6BPC:
8160 pipe_config->pipe_bpp = 18;
8161 break;
8162 case PIPECONF_8BPC:
8163 pipe_config->pipe_bpp = 24;
8164 break;
8165 case PIPECONF_10BPC:
8166 pipe_config->pipe_bpp = 30;
8167 break;
8168 default:
8169 break;
8170 }
8171 }
8172
8173 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8174 pipe_config->limited_color_range = true;
8175
8176 if (INTEL_INFO(dev)->gen < 4)
8177 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8178
8179 intel_get_pipe_timings(crtc, pipe_config);
8180
8181 i9xx_get_pfit_config(crtc, pipe_config);
8182
8183 if (INTEL_INFO(dev)->gen >= 4) {
8184 tmp = I915_READ(DPLL_MD(crtc->pipe));
8185 pipe_config->pixel_multiplier =
8186 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8187 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8188 pipe_config->dpll_hw_state.dpll_md = tmp;
8189 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8190 tmp = I915_READ(DPLL(crtc->pipe));
8191 pipe_config->pixel_multiplier =
8192 ((tmp & SDVO_MULTIPLIER_MASK)
8193 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8194 } else {
8195 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8196 * port and will be fixed up in the encoder->get_config
8197 * function. */
8198 pipe_config->pixel_multiplier = 1;
8199 }
8200 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8201 if (!IS_VALLEYVIEW(dev)) {
8202 /*
8203 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8204 * on 830. Filter it out here so that we don't
8205 * report errors due to that.
8206 */
8207 if (IS_I830(dev))
8208 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8209
8210 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8211 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8212 } else {
8213 /* Mask out read-only status bits. */
8214 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8215 DPLL_PORTC_READY_MASK |
8216 DPLL_PORTB_READY_MASK);
8217 }
8218
8219 if (IS_CHERRYVIEW(dev))
8220 chv_crtc_clock_get(crtc, pipe_config);
8221 else if (IS_VALLEYVIEW(dev))
8222 vlv_crtc_clock_get(crtc, pipe_config);
8223 else
8224 i9xx_crtc_clock_get(crtc, pipe_config);
8225
8226 /*
8227 * Normally the dotclock is filled in by the encoder .get_config()
8228 * but in case the pipe is enabled w/o any ports we need a sane
8229 * default.
8230 */
8231 pipe_config->base.adjusted_mode.crtc_clock =
8232 pipe_config->port_clock / pipe_config->pixel_multiplier;
8233
8234 return true;
8235 }
8236
8237 static void ironlake_init_pch_refclk(struct drm_device *dev)
8238 {
8239 struct drm_i915_private *dev_priv = dev->dev_private;
8240 struct intel_encoder *encoder;
8241 u32 val, final;
8242 bool has_lvds = false;
8243 bool has_cpu_edp = false;
8244 bool has_panel = false;
8245 bool has_ck505 = false;
8246 bool can_ssc = false;
8247
8248 /* We need to take the global config into account */
8249 for_each_intel_encoder(dev, encoder) {
8250 switch (encoder->type) {
8251 case INTEL_OUTPUT_LVDS:
8252 has_panel = true;
8253 has_lvds = true;
8254 break;
8255 case INTEL_OUTPUT_EDP:
8256 has_panel = true;
8257 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8258 has_cpu_edp = true;
8259 break;
8260 default:
8261 break;
8262 }
8263 }
8264
8265 if (HAS_PCH_IBX(dev)) {
8266 has_ck505 = dev_priv->vbt.display_clock_mode;
8267 can_ssc = has_ck505;
8268 } else {
8269 has_ck505 = false;
8270 can_ssc = true;
8271 }
8272
8273 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8274 has_panel, has_lvds, has_ck505);
8275
8276 /* Ironlake: try to setup display ref clock before DPLL
8277 * enabling. This is only under driver's control after
8278 * PCH B stepping, previous chipset stepping should be
8279 * ignoring this setting.
8280 */
8281 val = I915_READ(PCH_DREF_CONTROL);
8282
8283 /* As we must carefully and slowly disable/enable each source in turn,
8284 * compute the final state we want first and check if we need to
8285 * make any changes at all.
8286 */
8287 final = val;
8288 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8289 if (has_ck505)
8290 final |= DREF_NONSPREAD_CK505_ENABLE;
8291 else
8292 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8293
8294 final &= ~DREF_SSC_SOURCE_MASK;
8295 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8296 final &= ~DREF_SSC1_ENABLE;
8297
8298 if (has_panel) {
8299 final |= DREF_SSC_SOURCE_ENABLE;
8300
8301 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8302 final |= DREF_SSC1_ENABLE;
8303
8304 if (has_cpu_edp) {
8305 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8306 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8307 else
8308 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8309 } else
8310 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8311 } else {
8312 final |= DREF_SSC_SOURCE_DISABLE;
8313 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8314 }
8315
8316 if (final == val)
8317 return;
8318
8319 /* Always enable nonspread source */
8320 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8321
8322 if (has_ck505)
8323 val |= DREF_NONSPREAD_CK505_ENABLE;
8324 else
8325 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8326
8327 if (has_panel) {
8328 val &= ~DREF_SSC_SOURCE_MASK;
8329 val |= DREF_SSC_SOURCE_ENABLE;
8330
8331 /* SSC must be turned on before enabling the CPU output */
8332 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8333 DRM_DEBUG_KMS("Using SSC on panel\n");
8334 val |= DREF_SSC1_ENABLE;
8335 } else
8336 val &= ~DREF_SSC1_ENABLE;
8337
8338 /* Get SSC going before enabling the outputs */
8339 I915_WRITE(PCH_DREF_CONTROL, val);
8340 POSTING_READ(PCH_DREF_CONTROL);
8341 udelay(200);
8342
8343 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8344
8345 /* Enable CPU source on CPU attached eDP */
8346 if (has_cpu_edp) {
8347 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8348 DRM_DEBUG_KMS("Using SSC on eDP\n");
8349 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8350 } else
8351 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8352 } else
8353 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8354
8355 I915_WRITE(PCH_DREF_CONTROL, val);
8356 POSTING_READ(PCH_DREF_CONTROL);
8357 udelay(200);
8358 } else {
8359 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8360
8361 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8362
8363 /* Turn off CPU output */
8364 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8365
8366 I915_WRITE(PCH_DREF_CONTROL, val);
8367 POSTING_READ(PCH_DREF_CONTROL);
8368 udelay(200);
8369
8370 /* Turn off the SSC source */
8371 val &= ~DREF_SSC_SOURCE_MASK;
8372 val |= DREF_SSC_SOURCE_DISABLE;
8373
8374 /* Turn off SSC1 */
8375 val &= ~DREF_SSC1_ENABLE;
8376
8377 I915_WRITE(PCH_DREF_CONTROL, val);
8378 POSTING_READ(PCH_DREF_CONTROL);
8379 udelay(200);
8380 }
8381
8382 BUG_ON(val != final);
8383 }
8384
8385 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8386 {
8387 uint32_t tmp;
8388
8389 tmp = I915_READ(SOUTH_CHICKEN2);
8390 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8391 I915_WRITE(SOUTH_CHICKEN2, tmp);
8392
8393 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8394 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8395 DRM_ERROR("FDI mPHY reset assert timeout\n");
8396
8397 tmp = I915_READ(SOUTH_CHICKEN2);
8398 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8399 I915_WRITE(SOUTH_CHICKEN2, tmp);
8400
8401 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8402 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8403 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8404 }
8405
8406 /* WaMPhyProgramming:hsw */
8407 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8408 {
8409 uint32_t tmp;
8410
8411 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8412 tmp &= ~(0xFF << 24);
8413 tmp |= (0x12 << 24);
8414 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8415
8416 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8417 tmp |= (1 << 11);
8418 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8419
8420 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8421 tmp |= (1 << 11);
8422 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8423
8424 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8425 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8426 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8427
8428 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8429 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8430 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8431
8432 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8433 tmp &= ~(7 << 13);
8434 tmp |= (5 << 13);
8435 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8436
8437 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8438 tmp &= ~(7 << 13);
8439 tmp |= (5 << 13);
8440 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8441
8442 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8443 tmp &= ~0xFF;
8444 tmp |= 0x1C;
8445 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8446
8447 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8448 tmp &= ~0xFF;
8449 tmp |= 0x1C;
8450 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8451
8452 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8453 tmp &= ~(0xFF << 16);
8454 tmp |= (0x1C << 16);
8455 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8456
8457 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8458 tmp &= ~(0xFF << 16);
8459 tmp |= (0x1C << 16);
8460 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8461
8462 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8463 tmp |= (1 << 27);
8464 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8465
8466 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8467 tmp |= (1 << 27);
8468 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8469
8470 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8471 tmp &= ~(0xF << 28);
8472 tmp |= (4 << 28);
8473 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8474
8475 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8476 tmp &= ~(0xF << 28);
8477 tmp |= (4 << 28);
8478 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8479 }
8480
8481 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8482 * Programming" based on the parameters passed:
8483 * - Sequence to enable CLKOUT_DP
8484 * - Sequence to enable CLKOUT_DP without spread
8485 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8486 */
8487 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8488 bool with_fdi)
8489 {
8490 struct drm_i915_private *dev_priv = dev->dev_private;
8491 uint32_t reg, tmp;
8492
8493 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8494 with_spread = true;
8495 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8496 with_fdi = false;
8497
8498 mutex_lock(&dev_priv->sb_lock);
8499
8500 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8501 tmp &= ~SBI_SSCCTL_DISABLE;
8502 tmp |= SBI_SSCCTL_PATHALT;
8503 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8504
8505 udelay(24);
8506
8507 if (with_spread) {
8508 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8509 tmp &= ~SBI_SSCCTL_PATHALT;
8510 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8511
8512 if (with_fdi) {
8513 lpt_reset_fdi_mphy(dev_priv);
8514 lpt_program_fdi_mphy(dev_priv);
8515 }
8516 }
8517
8518 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8519 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8520 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8521 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8522
8523 mutex_unlock(&dev_priv->sb_lock);
8524 }
8525
8526 /* Sequence to disable CLKOUT_DP */
8527 static void lpt_disable_clkout_dp(struct drm_device *dev)
8528 {
8529 struct drm_i915_private *dev_priv = dev->dev_private;
8530 uint32_t reg, tmp;
8531
8532 mutex_lock(&dev_priv->sb_lock);
8533
8534 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8535 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8536 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8537 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8538
8539 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8540 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8541 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8542 tmp |= SBI_SSCCTL_PATHALT;
8543 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8544 udelay(32);
8545 }
8546 tmp |= SBI_SSCCTL_DISABLE;
8547 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8548 }
8549
8550 mutex_unlock(&dev_priv->sb_lock);
8551 }
8552
8553 static void lpt_init_pch_refclk(struct drm_device *dev)
8554 {
8555 struct intel_encoder *encoder;
8556 bool has_vga = false;
8557
8558 for_each_intel_encoder(dev, encoder) {
8559 switch (encoder->type) {
8560 case INTEL_OUTPUT_ANALOG:
8561 has_vga = true;
8562 break;
8563 default:
8564 break;
8565 }
8566 }
8567
8568 if (has_vga)
8569 lpt_enable_clkout_dp(dev, true, true);
8570 else
8571 lpt_disable_clkout_dp(dev);
8572 }
8573
8574 /*
8575 * Initialize reference clocks when the driver loads
8576 */
8577 void intel_init_pch_refclk(struct drm_device *dev)
8578 {
8579 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8580 ironlake_init_pch_refclk(dev);
8581 else if (HAS_PCH_LPT(dev))
8582 lpt_init_pch_refclk(dev);
8583 }
8584
8585 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8586 {
8587 struct drm_device *dev = crtc_state->base.crtc->dev;
8588 struct drm_i915_private *dev_priv = dev->dev_private;
8589 struct drm_atomic_state *state = crtc_state->base.state;
8590 struct drm_connector *connector;
8591 struct drm_connector_state *connector_state;
8592 struct intel_encoder *encoder;
8593 int num_connectors = 0, i;
8594 bool is_lvds = false;
8595
8596 for_each_connector_in_state(state, connector, connector_state, i) {
8597 if (connector_state->crtc != crtc_state->base.crtc)
8598 continue;
8599
8600 encoder = to_intel_encoder(connector_state->best_encoder);
8601
8602 switch (encoder->type) {
8603 case INTEL_OUTPUT_LVDS:
8604 is_lvds = true;
8605 break;
8606 default:
8607 break;
8608 }
8609 num_connectors++;
8610 }
8611
8612 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8613 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8614 dev_priv->vbt.lvds_ssc_freq);
8615 return dev_priv->vbt.lvds_ssc_freq;
8616 }
8617
8618 return 120000;
8619 }
8620
8621 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8622 {
8623 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8624 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8625 int pipe = intel_crtc->pipe;
8626 uint32_t val;
8627
8628 val = 0;
8629
8630 switch (intel_crtc->config->pipe_bpp) {
8631 case 18:
8632 val |= PIPECONF_6BPC;
8633 break;
8634 case 24:
8635 val |= PIPECONF_8BPC;
8636 break;
8637 case 30:
8638 val |= PIPECONF_10BPC;
8639 break;
8640 case 36:
8641 val |= PIPECONF_12BPC;
8642 break;
8643 default:
8644 /* Case prevented by intel_choose_pipe_bpp_dither. */
8645 BUG();
8646 }
8647
8648 if (intel_crtc->config->dither)
8649 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8650
8651 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8652 val |= PIPECONF_INTERLACED_ILK;
8653 else
8654 val |= PIPECONF_PROGRESSIVE;
8655
8656 if (intel_crtc->config->limited_color_range)
8657 val |= PIPECONF_COLOR_RANGE_SELECT;
8658
8659 I915_WRITE(PIPECONF(pipe), val);
8660 POSTING_READ(PIPECONF(pipe));
8661 }
8662
8663 /*
8664 * Set up the pipe CSC unit.
8665 *
8666 * Currently only full range RGB to limited range RGB conversion
8667 * is supported, but eventually this should handle various
8668 * RGB<->YCbCr scenarios as well.
8669 */
8670 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8671 {
8672 struct drm_device *dev = crtc->dev;
8673 struct drm_i915_private *dev_priv = dev->dev_private;
8674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8675 int pipe = intel_crtc->pipe;
8676 uint16_t coeff = 0x7800; /* 1.0 */
8677
8678 /*
8679 * TODO: Check what kind of values actually come out of the pipe
8680 * with these coeff/postoff values and adjust to get the best
8681 * accuracy. Perhaps we even need to take the bpc value into
8682 * consideration.
8683 */
8684
8685 if (intel_crtc->config->limited_color_range)
8686 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8687
8688 /*
8689 * GY/GU and RY/RU should be the other way around according
8690 * to BSpec, but reality doesn't agree. Just set them up in
8691 * a way that results in the correct picture.
8692 */
8693 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8694 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8695
8696 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8697 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8698
8699 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8700 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8701
8702 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8703 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8704 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8705
8706 if (INTEL_INFO(dev)->gen > 6) {
8707 uint16_t postoff = 0;
8708
8709 if (intel_crtc->config->limited_color_range)
8710 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8711
8712 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8713 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8714 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8715
8716 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8717 } else {
8718 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8719
8720 if (intel_crtc->config->limited_color_range)
8721 mode |= CSC_BLACK_SCREEN_OFFSET;
8722
8723 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8724 }
8725 }
8726
8727 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8728 {
8729 struct drm_device *dev = crtc->dev;
8730 struct drm_i915_private *dev_priv = dev->dev_private;
8731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8732 enum pipe pipe = intel_crtc->pipe;
8733 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8734 uint32_t val;
8735
8736 val = 0;
8737
8738 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8739 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8740
8741 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8742 val |= PIPECONF_INTERLACED_ILK;
8743 else
8744 val |= PIPECONF_PROGRESSIVE;
8745
8746 I915_WRITE(PIPECONF(cpu_transcoder), val);
8747 POSTING_READ(PIPECONF(cpu_transcoder));
8748
8749 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8750 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8751
8752 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8753 val = 0;
8754
8755 switch (intel_crtc->config->pipe_bpp) {
8756 case 18:
8757 val |= PIPEMISC_DITHER_6_BPC;
8758 break;
8759 case 24:
8760 val |= PIPEMISC_DITHER_8_BPC;
8761 break;
8762 case 30:
8763 val |= PIPEMISC_DITHER_10_BPC;
8764 break;
8765 case 36:
8766 val |= PIPEMISC_DITHER_12_BPC;
8767 break;
8768 default:
8769 /* Case prevented by pipe_config_set_bpp. */
8770 BUG();
8771 }
8772
8773 if (intel_crtc->config->dither)
8774 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8775
8776 I915_WRITE(PIPEMISC(pipe), val);
8777 }
8778 }
8779
8780 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8781 struct intel_crtc_state *crtc_state,
8782 intel_clock_t *clock,
8783 bool *has_reduced_clock,
8784 intel_clock_t *reduced_clock)
8785 {
8786 struct drm_device *dev = crtc->dev;
8787 struct drm_i915_private *dev_priv = dev->dev_private;
8788 int refclk;
8789 const intel_limit_t *limit;
8790 bool ret;
8791
8792 refclk = ironlake_get_refclk(crtc_state);
8793
8794 /*
8795 * Returns a set of divisors for the desired target clock with the given
8796 * refclk, or FALSE. The returned values represent the clock equation:
8797 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8798 */
8799 limit = intel_limit(crtc_state, refclk);
8800 ret = dev_priv->display.find_dpll(limit, crtc_state,
8801 crtc_state->port_clock,
8802 refclk, NULL, clock);
8803 if (!ret)
8804 return false;
8805
8806 return true;
8807 }
8808
8809 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8810 {
8811 /*
8812 * Account for spread spectrum to avoid
8813 * oversubscribing the link. Max center spread
8814 * is 2.5%; use 5% for safety's sake.
8815 */
8816 u32 bps = target_clock * bpp * 21 / 20;
8817 return DIV_ROUND_UP(bps, link_bw * 8);
8818 }
8819
8820 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8821 {
8822 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8823 }
8824
8825 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8826 struct intel_crtc_state *crtc_state,
8827 u32 *fp,
8828 intel_clock_t *reduced_clock, u32 *fp2)
8829 {
8830 struct drm_crtc *crtc = &intel_crtc->base;
8831 struct drm_device *dev = crtc->dev;
8832 struct drm_i915_private *dev_priv = dev->dev_private;
8833 struct drm_atomic_state *state = crtc_state->base.state;
8834 struct drm_connector *connector;
8835 struct drm_connector_state *connector_state;
8836 struct intel_encoder *encoder;
8837 uint32_t dpll;
8838 int factor, num_connectors = 0, i;
8839 bool is_lvds = false, is_sdvo = false;
8840
8841 for_each_connector_in_state(state, connector, connector_state, i) {
8842 if (connector_state->crtc != crtc_state->base.crtc)
8843 continue;
8844
8845 encoder = to_intel_encoder(connector_state->best_encoder);
8846
8847 switch (encoder->type) {
8848 case INTEL_OUTPUT_LVDS:
8849 is_lvds = true;
8850 break;
8851 case INTEL_OUTPUT_SDVO:
8852 case INTEL_OUTPUT_HDMI:
8853 is_sdvo = true;
8854 break;
8855 default:
8856 break;
8857 }
8858
8859 num_connectors++;
8860 }
8861
8862 /* Enable autotuning of the PLL clock (if permissible) */
8863 factor = 21;
8864 if (is_lvds) {
8865 if ((intel_panel_use_ssc(dev_priv) &&
8866 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8867 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8868 factor = 25;
8869 } else if (crtc_state->sdvo_tv_clock)
8870 factor = 20;
8871
8872 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8873 *fp |= FP_CB_TUNE;
8874
8875 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8876 *fp2 |= FP_CB_TUNE;
8877
8878 dpll = 0;
8879
8880 if (is_lvds)
8881 dpll |= DPLLB_MODE_LVDS;
8882 else
8883 dpll |= DPLLB_MODE_DAC_SERIAL;
8884
8885 dpll |= (crtc_state->pixel_multiplier - 1)
8886 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8887
8888 if (is_sdvo)
8889 dpll |= DPLL_SDVO_HIGH_SPEED;
8890 if (crtc_state->has_dp_encoder)
8891 dpll |= DPLL_SDVO_HIGH_SPEED;
8892
8893 /* compute bitmask from p1 value */
8894 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8895 /* also FPA1 */
8896 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8897
8898 switch (crtc_state->dpll.p2) {
8899 case 5:
8900 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8901 break;
8902 case 7:
8903 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8904 break;
8905 case 10:
8906 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8907 break;
8908 case 14:
8909 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8910 break;
8911 }
8912
8913 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8914 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8915 else
8916 dpll |= PLL_REF_INPUT_DREFCLK;
8917
8918 return dpll | DPLL_VCO_ENABLE;
8919 }
8920
8921 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8922 struct intel_crtc_state *crtc_state)
8923 {
8924 struct drm_device *dev = crtc->base.dev;
8925 intel_clock_t clock, reduced_clock;
8926 u32 dpll = 0, fp = 0, fp2 = 0;
8927 bool ok, has_reduced_clock = false;
8928 bool is_lvds = false;
8929 struct intel_shared_dpll *pll;
8930
8931 memset(&crtc_state->dpll_hw_state, 0,
8932 sizeof(crtc_state->dpll_hw_state));
8933
8934 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8935
8936 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8937 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8938
8939 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8940 &has_reduced_clock, &reduced_clock);
8941 if (!ok && !crtc_state->clock_set) {
8942 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8943 return -EINVAL;
8944 }
8945 /* Compat-code for transition, will disappear. */
8946 if (!crtc_state->clock_set) {
8947 crtc_state->dpll.n = clock.n;
8948 crtc_state->dpll.m1 = clock.m1;
8949 crtc_state->dpll.m2 = clock.m2;
8950 crtc_state->dpll.p1 = clock.p1;
8951 crtc_state->dpll.p2 = clock.p2;
8952 }
8953
8954 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8955 if (crtc_state->has_pch_encoder) {
8956 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8957 if (has_reduced_clock)
8958 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8959
8960 dpll = ironlake_compute_dpll(crtc, crtc_state,
8961 &fp, &reduced_clock,
8962 has_reduced_clock ? &fp2 : NULL);
8963
8964 crtc_state->dpll_hw_state.dpll = dpll;
8965 crtc_state->dpll_hw_state.fp0 = fp;
8966 if (has_reduced_clock)
8967 crtc_state->dpll_hw_state.fp1 = fp2;
8968 else
8969 crtc_state->dpll_hw_state.fp1 = fp;
8970
8971 pll = intel_get_shared_dpll(crtc, crtc_state);
8972 if (pll == NULL) {
8973 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8974 pipe_name(crtc->pipe));
8975 return -EINVAL;
8976 }
8977 }
8978
8979 if (is_lvds && has_reduced_clock)
8980 crtc->lowfreq_avail = true;
8981 else
8982 crtc->lowfreq_avail = false;
8983
8984 return 0;
8985 }
8986
8987 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8988 struct intel_link_m_n *m_n)
8989 {
8990 struct drm_device *dev = crtc->base.dev;
8991 struct drm_i915_private *dev_priv = dev->dev_private;
8992 enum pipe pipe = crtc->pipe;
8993
8994 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8995 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8996 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8997 & ~TU_SIZE_MASK;
8998 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8999 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9000 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9001 }
9002
9003 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9004 enum transcoder transcoder,
9005 struct intel_link_m_n *m_n,
9006 struct intel_link_m_n *m2_n2)
9007 {
9008 struct drm_device *dev = crtc->base.dev;
9009 struct drm_i915_private *dev_priv = dev->dev_private;
9010 enum pipe pipe = crtc->pipe;
9011
9012 if (INTEL_INFO(dev)->gen >= 5) {
9013 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9014 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9015 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9016 & ~TU_SIZE_MASK;
9017 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9018 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9019 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9020 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9021 * gen < 8) and if DRRS is supported (to make sure the
9022 * registers are not unnecessarily read).
9023 */
9024 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9025 crtc->config->has_drrs) {
9026 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9027 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9028 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9029 & ~TU_SIZE_MASK;
9030 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9031 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9032 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9033 }
9034 } else {
9035 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9036 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9037 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9038 & ~TU_SIZE_MASK;
9039 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9040 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9041 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9042 }
9043 }
9044
9045 void intel_dp_get_m_n(struct intel_crtc *crtc,
9046 struct intel_crtc_state *pipe_config)
9047 {
9048 if (pipe_config->has_pch_encoder)
9049 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9050 else
9051 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9052 &pipe_config->dp_m_n,
9053 &pipe_config->dp_m2_n2);
9054 }
9055
9056 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9057 struct intel_crtc_state *pipe_config)
9058 {
9059 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9060 &pipe_config->fdi_m_n, NULL);
9061 }
9062
9063 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9064 struct intel_crtc_state *pipe_config)
9065 {
9066 struct drm_device *dev = crtc->base.dev;
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9069 uint32_t ps_ctrl = 0;
9070 int id = -1;
9071 int i;
9072
9073 /* find scaler attached to this pipe */
9074 for (i = 0; i < crtc->num_scalers; i++) {
9075 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9076 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9077 id = i;
9078 pipe_config->pch_pfit.enabled = true;
9079 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9080 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9081 break;
9082 }
9083 }
9084
9085 scaler_state->scaler_id = id;
9086 if (id >= 0) {
9087 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9088 } else {
9089 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9090 }
9091 }
9092
9093 static void
9094 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9095 struct intel_initial_plane_config *plane_config)
9096 {
9097 struct drm_device *dev = crtc->base.dev;
9098 struct drm_i915_private *dev_priv = dev->dev_private;
9099 u32 val, base, offset, stride_mult, tiling;
9100 int pipe = crtc->pipe;
9101 int fourcc, pixel_format;
9102 unsigned int aligned_height;
9103 struct drm_framebuffer *fb;
9104 struct intel_framebuffer *intel_fb;
9105
9106 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9107 if (!intel_fb) {
9108 DRM_DEBUG_KMS("failed to alloc fb\n");
9109 return;
9110 }
9111
9112 fb = &intel_fb->base;
9113
9114 val = I915_READ(PLANE_CTL(pipe, 0));
9115 if (!(val & PLANE_CTL_ENABLE))
9116 goto error;
9117
9118 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9119 fourcc = skl_format_to_fourcc(pixel_format,
9120 val & PLANE_CTL_ORDER_RGBX,
9121 val & PLANE_CTL_ALPHA_MASK);
9122 fb->pixel_format = fourcc;
9123 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9124
9125 tiling = val & PLANE_CTL_TILED_MASK;
9126 switch (tiling) {
9127 case PLANE_CTL_TILED_LINEAR:
9128 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9129 break;
9130 case PLANE_CTL_TILED_X:
9131 plane_config->tiling = I915_TILING_X;
9132 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9133 break;
9134 case PLANE_CTL_TILED_Y:
9135 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9136 break;
9137 case PLANE_CTL_TILED_YF:
9138 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9139 break;
9140 default:
9141 MISSING_CASE(tiling);
9142 goto error;
9143 }
9144
9145 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9146 plane_config->base = base;
9147
9148 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9149
9150 val = I915_READ(PLANE_SIZE(pipe, 0));
9151 fb->height = ((val >> 16) & 0xfff) + 1;
9152 fb->width = ((val >> 0) & 0x1fff) + 1;
9153
9154 val = I915_READ(PLANE_STRIDE(pipe, 0));
9155 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9156 fb->pixel_format);
9157 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9158
9159 aligned_height = intel_fb_align_height(dev, fb->height,
9160 fb->pixel_format,
9161 fb->modifier[0]);
9162
9163 plane_config->size = fb->pitches[0] * aligned_height;
9164
9165 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9166 pipe_name(pipe), fb->width, fb->height,
9167 fb->bits_per_pixel, base, fb->pitches[0],
9168 plane_config->size);
9169
9170 plane_config->fb = intel_fb;
9171 return;
9172
9173 error:
9174 kfree(fb);
9175 }
9176
9177 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9178 struct intel_crtc_state *pipe_config)
9179 {
9180 struct drm_device *dev = crtc->base.dev;
9181 struct drm_i915_private *dev_priv = dev->dev_private;
9182 uint32_t tmp;
9183
9184 tmp = I915_READ(PF_CTL(crtc->pipe));
9185
9186 if (tmp & PF_ENABLE) {
9187 pipe_config->pch_pfit.enabled = true;
9188 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9189 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9190
9191 /* We currently do not free assignements of panel fitters on
9192 * ivb/hsw (since we don't use the higher upscaling modes which
9193 * differentiates them) so just WARN about this case for now. */
9194 if (IS_GEN7(dev)) {
9195 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9196 PF_PIPE_SEL_IVB(crtc->pipe));
9197 }
9198 }
9199 }
9200
9201 static void
9202 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9203 struct intel_initial_plane_config *plane_config)
9204 {
9205 struct drm_device *dev = crtc->base.dev;
9206 struct drm_i915_private *dev_priv = dev->dev_private;
9207 u32 val, base, offset;
9208 int pipe = crtc->pipe;
9209 int fourcc, pixel_format;
9210 unsigned int aligned_height;
9211 struct drm_framebuffer *fb;
9212 struct intel_framebuffer *intel_fb;
9213
9214 val = I915_READ(DSPCNTR(pipe));
9215 if (!(val & DISPLAY_PLANE_ENABLE))
9216 return;
9217
9218 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9219 if (!intel_fb) {
9220 DRM_DEBUG_KMS("failed to alloc fb\n");
9221 return;
9222 }
9223
9224 fb = &intel_fb->base;
9225
9226 if (INTEL_INFO(dev)->gen >= 4) {
9227 if (val & DISPPLANE_TILED) {
9228 plane_config->tiling = I915_TILING_X;
9229 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9230 }
9231 }
9232
9233 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9234 fourcc = i9xx_format_to_fourcc(pixel_format);
9235 fb->pixel_format = fourcc;
9236 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9237
9238 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9239 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9240 offset = I915_READ(DSPOFFSET(pipe));
9241 } else {
9242 if (plane_config->tiling)
9243 offset = I915_READ(DSPTILEOFF(pipe));
9244 else
9245 offset = I915_READ(DSPLINOFF(pipe));
9246 }
9247 plane_config->base = base;
9248
9249 val = I915_READ(PIPESRC(pipe));
9250 fb->width = ((val >> 16) & 0xfff) + 1;
9251 fb->height = ((val >> 0) & 0xfff) + 1;
9252
9253 val = I915_READ(DSPSTRIDE(pipe));
9254 fb->pitches[0] = val & 0xffffffc0;
9255
9256 aligned_height = intel_fb_align_height(dev, fb->height,
9257 fb->pixel_format,
9258 fb->modifier[0]);
9259
9260 plane_config->size = fb->pitches[0] * aligned_height;
9261
9262 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9263 pipe_name(pipe), fb->width, fb->height,
9264 fb->bits_per_pixel, base, fb->pitches[0],
9265 plane_config->size);
9266
9267 plane_config->fb = intel_fb;
9268 }
9269
9270 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9271 struct intel_crtc_state *pipe_config)
9272 {
9273 struct drm_device *dev = crtc->base.dev;
9274 struct drm_i915_private *dev_priv = dev->dev_private;
9275 uint32_t tmp;
9276
9277 if (!intel_display_power_is_enabled(dev_priv,
9278 POWER_DOMAIN_PIPE(crtc->pipe)))
9279 return false;
9280
9281 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9282 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9283
9284 tmp = I915_READ(PIPECONF(crtc->pipe));
9285 if (!(tmp & PIPECONF_ENABLE))
9286 return false;
9287
9288 switch (tmp & PIPECONF_BPC_MASK) {
9289 case PIPECONF_6BPC:
9290 pipe_config->pipe_bpp = 18;
9291 break;
9292 case PIPECONF_8BPC:
9293 pipe_config->pipe_bpp = 24;
9294 break;
9295 case PIPECONF_10BPC:
9296 pipe_config->pipe_bpp = 30;
9297 break;
9298 case PIPECONF_12BPC:
9299 pipe_config->pipe_bpp = 36;
9300 break;
9301 default:
9302 break;
9303 }
9304
9305 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9306 pipe_config->limited_color_range = true;
9307
9308 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9309 struct intel_shared_dpll *pll;
9310
9311 pipe_config->has_pch_encoder = true;
9312
9313 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9314 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9315 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9316
9317 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9318
9319 if (HAS_PCH_IBX(dev_priv->dev)) {
9320 pipe_config->shared_dpll =
9321 (enum intel_dpll_id) crtc->pipe;
9322 } else {
9323 tmp = I915_READ(PCH_DPLL_SEL);
9324 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9325 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9326 else
9327 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9328 }
9329
9330 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9331
9332 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9333 &pipe_config->dpll_hw_state));
9334
9335 tmp = pipe_config->dpll_hw_state.dpll;
9336 pipe_config->pixel_multiplier =
9337 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9338 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9339
9340 ironlake_pch_clock_get(crtc, pipe_config);
9341 } else {
9342 pipe_config->pixel_multiplier = 1;
9343 }
9344
9345 intel_get_pipe_timings(crtc, pipe_config);
9346
9347 ironlake_get_pfit_config(crtc, pipe_config);
9348
9349 return true;
9350 }
9351
9352 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9353 {
9354 struct drm_device *dev = dev_priv->dev;
9355 struct intel_crtc *crtc;
9356
9357 for_each_intel_crtc(dev, crtc)
9358 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9359 pipe_name(crtc->pipe));
9360
9361 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9362 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9363 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9364 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9365 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9366 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9367 "CPU PWM1 enabled\n");
9368 if (IS_HASWELL(dev))
9369 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9370 "CPU PWM2 enabled\n");
9371 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9372 "PCH PWM1 enabled\n");
9373 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9374 "Utility pin enabled\n");
9375 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9376
9377 /*
9378 * In theory we can still leave IRQs enabled, as long as only the HPD
9379 * interrupts remain enabled. We used to check for that, but since it's
9380 * gen-specific and since we only disable LCPLL after we fully disable
9381 * the interrupts, the check below should be enough.
9382 */
9383 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9384 }
9385
9386 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9387 {
9388 struct drm_device *dev = dev_priv->dev;
9389
9390 if (IS_HASWELL(dev))
9391 return I915_READ(D_COMP_HSW);
9392 else
9393 return I915_READ(D_COMP_BDW);
9394 }
9395
9396 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9397 {
9398 struct drm_device *dev = dev_priv->dev;
9399
9400 if (IS_HASWELL(dev)) {
9401 mutex_lock(&dev_priv->rps.hw_lock);
9402 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9403 val))
9404 DRM_ERROR("Failed to write to D_COMP\n");
9405 mutex_unlock(&dev_priv->rps.hw_lock);
9406 } else {
9407 I915_WRITE(D_COMP_BDW, val);
9408 POSTING_READ(D_COMP_BDW);
9409 }
9410 }
9411
9412 /*
9413 * This function implements pieces of two sequences from BSpec:
9414 * - Sequence for display software to disable LCPLL
9415 * - Sequence for display software to allow package C8+
9416 * The steps implemented here are just the steps that actually touch the LCPLL
9417 * register. Callers should take care of disabling all the display engine
9418 * functions, doing the mode unset, fixing interrupts, etc.
9419 */
9420 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9421 bool switch_to_fclk, bool allow_power_down)
9422 {
9423 uint32_t val;
9424
9425 assert_can_disable_lcpll(dev_priv);
9426
9427 val = I915_READ(LCPLL_CTL);
9428
9429 if (switch_to_fclk) {
9430 val |= LCPLL_CD_SOURCE_FCLK;
9431 I915_WRITE(LCPLL_CTL, val);
9432
9433 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9434 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9435 DRM_ERROR("Switching to FCLK failed\n");
9436
9437 val = I915_READ(LCPLL_CTL);
9438 }
9439
9440 val |= LCPLL_PLL_DISABLE;
9441 I915_WRITE(LCPLL_CTL, val);
9442 POSTING_READ(LCPLL_CTL);
9443
9444 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9445 DRM_ERROR("LCPLL still locked\n");
9446
9447 val = hsw_read_dcomp(dev_priv);
9448 val |= D_COMP_COMP_DISABLE;
9449 hsw_write_dcomp(dev_priv, val);
9450 ndelay(100);
9451
9452 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9453 1))
9454 DRM_ERROR("D_COMP RCOMP still in progress\n");
9455
9456 if (allow_power_down) {
9457 val = I915_READ(LCPLL_CTL);
9458 val |= LCPLL_POWER_DOWN_ALLOW;
9459 I915_WRITE(LCPLL_CTL, val);
9460 POSTING_READ(LCPLL_CTL);
9461 }
9462 }
9463
9464 /*
9465 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9466 * source.
9467 */
9468 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9469 {
9470 uint32_t val;
9471
9472 val = I915_READ(LCPLL_CTL);
9473
9474 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9475 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9476 return;
9477
9478 /*
9479 * Make sure we're not on PC8 state before disabling PC8, otherwise
9480 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9481 */
9482 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9483
9484 if (val & LCPLL_POWER_DOWN_ALLOW) {
9485 val &= ~LCPLL_POWER_DOWN_ALLOW;
9486 I915_WRITE(LCPLL_CTL, val);
9487 POSTING_READ(LCPLL_CTL);
9488 }
9489
9490 val = hsw_read_dcomp(dev_priv);
9491 val |= D_COMP_COMP_FORCE;
9492 val &= ~D_COMP_COMP_DISABLE;
9493 hsw_write_dcomp(dev_priv, val);
9494
9495 val = I915_READ(LCPLL_CTL);
9496 val &= ~LCPLL_PLL_DISABLE;
9497 I915_WRITE(LCPLL_CTL, val);
9498
9499 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9500 DRM_ERROR("LCPLL not locked yet\n");
9501
9502 if (val & LCPLL_CD_SOURCE_FCLK) {
9503 val = I915_READ(LCPLL_CTL);
9504 val &= ~LCPLL_CD_SOURCE_FCLK;
9505 I915_WRITE(LCPLL_CTL, val);
9506
9507 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9508 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9509 DRM_ERROR("Switching back to LCPLL failed\n");
9510 }
9511
9512 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9513 intel_update_cdclk(dev_priv->dev);
9514 }
9515
9516 /*
9517 * Package states C8 and deeper are really deep PC states that can only be
9518 * reached when all the devices on the system allow it, so even if the graphics
9519 * device allows PC8+, it doesn't mean the system will actually get to these
9520 * states. Our driver only allows PC8+ when going into runtime PM.
9521 *
9522 * The requirements for PC8+ are that all the outputs are disabled, the power
9523 * well is disabled and most interrupts are disabled, and these are also
9524 * requirements for runtime PM. When these conditions are met, we manually do
9525 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9526 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9527 * hang the machine.
9528 *
9529 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9530 * the state of some registers, so when we come back from PC8+ we need to
9531 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9532 * need to take care of the registers kept by RC6. Notice that this happens even
9533 * if we don't put the device in PCI D3 state (which is what currently happens
9534 * because of the runtime PM support).
9535 *
9536 * For more, read "Display Sequences for Package C8" on the hardware
9537 * documentation.
9538 */
9539 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9540 {
9541 struct drm_device *dev = dev_priv->dev;
9542 uint32_t val;
9543
9544 DRM_DEBUG_KMS("Enabling package C8+\n");
9545
9546 if (HAS_PCH_LPT_LP(dev)) {
9547 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9548 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9549 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9550 }
9551
9552 lpt_disable_clkout_dp(dev);
9553 hsw_disable_lcpll(dev_priv, true, true);
9554 }
9555
9556 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9557 {
9558 struct drm_device *dev = dev_priv->dev;
9559 uint32_t val;
9560
9561 DRM_DEBUG_KMS("Disabling package C8+\n");
9562
9563 hsw_restore_lcpll(dev_priv);
9564 lpt_init_pch_refclk(dev);
9565
9566 if (HAS_PCH_LPT_LP(dev)) {
9567 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9568 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9569 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9570 }
9571
9572 intel_prepare_ddi(dev);
9573 }
9574
9575 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9576 {
9577 struct drm_device *dev = old_state->dev;
9578 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9579
9580 broxton_set_cdclk(dev, req_cdclk);
9581 }
9582
9583 /* compute the max rate for new configuration */
9584 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9585 {
9586 struct intel_crtc *intel_crtc;
9587 struct intel_crtc_state *crtc_state;
9588 int max_pixel_rate = 0;
9589
9590 for_each_intel_crtc(state->dev, intel_crtc) {
9591 int pixel_rate;
9592
9593 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9594 if (IS_ERR(crtc_state))
9595 return PTR_ERR(crtc_state);
9596
9597 if (!crtc_state->base.enable)
9598 continue;
9599
9600 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9601
9602 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9603 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
9604 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9605
9606 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9607 }
9608
9609 return max_pixel_rate;
9610 }
9611
9612 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9613 {
9614 struct drm_i915_private *dev_priv = dev->dev_private;
9615 uint32_t val, data;
9616 int ret;
9617
9618 if (WARN((I915_READ(LCPLL_CTL) &
9619 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9620 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9621 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9622 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9623 "trying to change cdclk frequency with cdclk not enabled\n"))
9624 return;
9625
9626 mutex_lock(&dev_priv->rps.hw_lock);
9627 ret = sandybridge_pcode_write(dev_priv,
9628 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9629 mutex_unlock(&dev_priv->rps.hw_lock);
9630 if (ret) {
9631 DRM_ERROR("failed to inform pcode about cdclk change\n");
9632 return;
9633 }
9634
9635 val = I915_READ(LCPLL_CTL);
9636 val |= LCPLL_CD_SOURCE_FCLK;
9637 I915_WRITE(LCPLL_CTL, val);
9638
9639 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9640 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9641 DRM_ERROR("Switching to FCLK failed\n");
9642
9643 val = I915_READ(LCPLL_CTL);
9644 val &= ~LCPLL_CLK_FREQ_MASK;
9645
9646 switch (cdclk) {
9647 case 450000:
9648 val |= LCPLL_CLK_FREQ_450;
9649 data = 0;
9650 break;
9651 case 540000:
9652 val |= LCPLL_CLK_FREQ_54O_BDW;
9653 data = 1;
9654 break;
9655 case 337500:
9656 val |= LCPLL_CLK_FREQ_337_5_BDW;
9657 data = 2;
9658 break;
9659 case 675000:
9660 val |= LCPLL_CLK_FREQ_675_BDW;
9661 data = 3;
9662 break;
9663 default:
9664 WARN(1, "invalid cdclk frequency\n");
9665 return;
9666 }
9667
9668 I915_WRITE(LCPLL_CTL, val);
9669
9670 val = I915_READ(LCPLL_CTL);
9671 val &= ~LCPLL_CD_SOURCE_FCLK;
9672 I915_WRITE(LCPLL_CTL, val);
9673
9674 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9675 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9676 DRM_ERROR("Switching back to LCPLL failed\n");
9677
9678 mutex_lock(&dev_priv->rps.hw_lock);
9679 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9680 mutex_unlock(&dev_priv->rps.hw_lock);
9681
9682 intel_update_cdclk(dev);
9683
9684 WARN(cdclk != dev_priv->cdclk_freq,
9685 "cdclk requested %d kHz but got %d kHz\n",
9686 cdclk, dev_priv->cdclk_freq);
9687 }
9688
9689 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9690 {
9691 struct drm_i915_private *dev_priv = to_i915(state->dev);
9692 int max_pixclk = ilk_max_pixel_rate(state);
9693 int cdclk;
9694
9695 /*
9696 * FIXME should also account for plane ratio
9697 * once 64bpp pixel formats are supported.
9698 */
9699 if (max_pixclk > 540000)
9700 cdclk = 675000;
9701 else if (max_pixclk > 450000)
9702 cdclk = 540000;
9703 else if (max_pixclk > 337500)
9704 cdclk = 450000;
9705 else
9706 cdclk = 337500;
9707
9708 /*
9709 * FIXME move the cdclk caclulation to
9710 * compute_config() so we can fail gracegully.
9711 */
9712 if (cdclk > dev_priv->max_cdclk_freq) {
9713 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9714 cdclk, dev_priv->max_cdclk_freq);
9715 cdclk = dev_priv->max_cdclk_freq;
9716 }
9717
9718 to_intel_atomic_state(state)->cdclk = cdclk;
9719
9720 return 0;
9721 }
9722
9723 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9724 {
9725 struct drm_device *dev = old_state->dev;
9726 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
9727
9728 broadwell_set_cdclk(dev, req_cdclk);
9729 }
9730
9731 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9732 struct intel_crtc_state *crtc_state)
9733 {
9734 if (!intel_ddi_pll_select(crtc, crtc_state))
9735 return -EINVAL;
9736
9737 crtc->lowfreq_avail = false;
9738
9739 return 0;
9740 }
9741
9742 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9743 enum port port,
9744 struct intel_crtc_state *pipe_config)
9745 {
9746 switch (port) {
9747 case PORT_A:
9748 pipe_config->ddi_pll_sel = SKL_DPLL0;
9749 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9750 break;
9751 case PORT_B:
9752 pipe_config->ddi_pll_sel = SKL_DPLL1;
9753 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9754 break;
9755 case PORT_C:
9756 pipe_config->ddi_pll_sel = SKL_DPLL2;
9757 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9758 break;
9759 default:
9760 DRM_ERROR("Incorrect port type\n");
9761 }
9762 }
9763
9764 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9765 enum port port,
9766 struct intel_crtc_state *pipe_config)
9767 {
9768 u32 temp, dpll_ctl1;
9769
9770 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9771 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9772
9773 switch (pipe_config->ddi_pll_sel) {
9774 case SKL_DPLL0:
9775 /*
9776 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9777 * of the shared DPLL framework and thus needs to be read out
9778 * separately
9779 */
9780 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9781 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9782 break;
9783 case SKL_DPLL1:
9784 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9785 break;
9786 case SKL_DPLL2:
9787 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9788 break;
9789 case SKL_DPLL3:
9790 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9791 break;
9792 }
9793 }
9794
9795 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9796 enum port port,
9797 struct intel_crtc_state *pipe_config)
9798 {
9799 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9800
9801 switch (pipe_config->ddi_pll_sel) {
9802 case PORT_CLK_SEL_WRPLL1:
9803 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9804 break;
9805 case PORT_CLK_SEL_WRPLL2:
9806 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9807 break;
9808 case PORT_CLK_SEL_SPLL:
9809 pipe_config->shared_dpll = DPLL_ID_SPLL;
9810 }
9811 }
9812
9813 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9814 struct intel_crtc_state *pipe_config)
9815 {
9816 struct drm_device *dev = crtc->base.dev;
9817 struct drm_i915_private *dev_priv = dev->dev_private;
9818 struct intel_shared_dpll *pll;
9819 enum port port;
9820 uint32_t tmp;
9821
9822 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9823
9824 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9825
9826 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
9827 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9828 else if (IS_BROXTON(dev))
9829 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9830 else
9831 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9832
9833 if (pipe_config->shared_dpll >= 0) {
9834 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9835
9836 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9837 &pipe_config->dpll_hw_state));
9838 }
9839
9840 /*
9841 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9842 * DDI E. So just check whether this pipe is wired to DDI E and whether
9843 * the PCH transcoder is on.
9844 */
9845 if (INTEL_INFO(dev)->gen < 9 &&
9846 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9847 pipe_config->has_pch_encoder = true;
9848
9849 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9850 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9851 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9852
9853 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9854 }
9855 }
9856
9857 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9858 struct intel_crtc_state *pipe_config)
9859 {
9860 struct drm_device *dev = crtc->base.dev;
9861 struct drm_i915_private *dev_priv = dev->dev_private;
9862 enum intel_display_power_domain pfit_domain;
9863 uint32_t tmp;
9864
9865 if (!intel_display_power_is_enabled(dev_priv,
9866 POWER_DOMAIN_PIPE(crtc->pipe)))
9867 return false;
9868
9869 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9870 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9871
9872 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9873 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9874 enum pipe trans_edp_pipe;
9875 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9876 default:
9877 WARN(1, "unknown pipe linked to edp transcoder\n");
9878 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9879 case TRANS_DDI_EDP_INPUT_A_ON:
9880 trans_edp_pipe = PIPE_A;
9881 break;
9882 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9883 trans_edp_pipe = PIPE_B;
9884 break;
9885 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9886 trans_edp_pipe = PIPE_C;
9887 break;
9888 }
9889
9890 if (trans_edp_pipe == crtc->pipe)
9891 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9892 }
9893
9894 if (!intel_display_power_is_enabled(dev_priv,
9895 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9896 return false;
9897
9898 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9899 if (!(tmp & PIPECONF_ENABLE))
9900 return false;
9901
9902 haswell_get_ddi_port_state(crtc, pipe_config);
9903
9904 intel_get_pipe_timings(crtc, pipe_config);
9905
9906 if (INTEL_INFO(dev)->gen >= 9) {
9907 skl_init_scalers(dev, crtc, pipe_config);
9908 }
9909
9910 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9911
9912 if (INTEL_INFO(dev)->gen >= 9) {
9913 pipe_config->scaler_state.scaler_id = -1;
9914 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9915 }
9916
9917 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9918 if (INTEL_INFO(dev)->gen >= 9)
9919 skylake_get_pfit_config(crtc, pipe_config);
9920 else
9921 ironlake_get_pfit_config(crtc, pipe_config);
9922 }
9923
9924 if (IS_HASWELL(dev))
9925 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9926 (I915_READ(IPS_CTL) & IPS_ENABLE);
9927
9928 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9929 pipe_config->pixel_multiplier =
9930 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9931 } else {
9932 pipe_config->pixel_multiplier = 1;
9933 }
9934
9935 return true;
9936 }
9937
9938 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9939 {
9940 struct drm_device *dev = crtc->dev;
9941 struct drm_i915_private *dev_priv = dev->dev_private;
9942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9943 uint32_t cntl = 0, size = 0;
9944
9945 if (base) {
9946 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9947 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9948 unsigned int stride = roundup_pow_of_two(width) * 4;
9949
9950 switch (stride) {
9951 default:
9952 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9953 width, stride);
9954 stride = 256;
9955 /* fallthrough */
9956 case 256:
9957 case 512:
9958 case 1024:
9959 case 2048:
9960 break;
9961 }
9962
9963 cntl |= CURSOR_ENABLE |
9964 CURSOR_GAMMA_ENABLE |
9965 CURSOR_FORMAT_ARGB |
9966 CURSOR_STRIDE(stride);
9967
9968 size = (height << 12) | width;
9969 }
9970
9971 if (intel_crtc->cursor_cntl != 0 &&
9972 (intel_crtc->cursor_base != base ||
9973 intel_crtc->cursor_size != size ||
9974 intel_crtc->cursor_cntl != cntl)) {
9975 /* On these chipsets we can only modify the base/size/stride
9976 * whilst the cursor is disabled.
9977 */
9978 I915_WRITE(CURCNTR(PIPE_A), 0);
9979 POSTING_READ(CURCNTR(PIPE_A));
9980 intel_crtc->cursor_cntl = 0;
9981 }
9982
9983 if (intel_crtc->cursor_base != base) {
9984 I915_WRITE(CURBASE(PIPE_A), base);
9985 intel_crtc->cursor_base = base;
9986 }
9987
9988 if (intel_crtc->cursor_size != size) {
9989 I915_WRITE(CURSIZE, size);
9990 intel_crtc->cursor_size = size;
9991 }
9992
9993 if (intel_crtc->cursor_cntl != cntl) {
9994 I915_WRITE(CURCNTR(PIPE_A), cntl);
9995 POSTING_READ(CURCNTR(PIPE_A));
9996 intel_crtc->cursor_cntl = cntl;
9997 }
9998 }
9999
10000 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
10001 {
10002 struct drm_device *dev = crtc->dev;
10003 struct drm_i915_private *dev_priv = dev->dev_private;
10004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10005 int pipe = intel_crtc->pipe;
10006 uint32_t cntl;
10007
10008 cntl = 0;
10009 if (base) {
10010 cntl = MCURSOR_GAMMA_ENABLE;
10011 switch (intel_crtc->base.cursor->state->crtc_w) {
10012 case 64:
10013 cntl |= CURSOR_MODE_64_ARGB_AX;
10014 break;
10015 case 128:
10016 cntl |= CURSOR_MODE_128_ARGB_AX;
10017 break;
10018 case 256:
10019 cntl |= CURSOR_MODE_256_ARGB_AX;
10020 break;
10021 default:
10022 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
10023 return;
10024 }
10025 cntl |= pipe << 28; /* Connect to correct pipe */
10026
10027 if (HAS_DDI(dev))
10028 cntl |= CURSOR_PIPE_CSC_ENABLE;
10029 }
10030
10031 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
10032 cntl |= CURSOR_ROTATE_180;
10033
10034 if (intel_crtc->cursor_cntl != cntl) {
10035 I915_WRITE(CURCNTR(pipe), cntl);
10036 POSTING_READ(CURCNTR(pipe));
10037 intel_crtc->cursor_cntl = cntl;
10038 }
10039
10040 /* and commit changes on next vblank */
10041 I915_WRITE(CURBASE(pipe), base);
10042 POSTING_READ(CURBASE(pipe));
10043
10044 intel_crtc->cursor_base = base;
10045 }
10046
10047 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10048 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10049 bool on)
10050 {
10051 struct drm_device *dev = crtc->dev;
10052 struct drm_i915_private *dev_priv = dev->dev_private;
10053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10054 int pipe = intel_crtc->pipe;
10055 struct drm_plane_state *cursor_state = crtc->cursor->state;
10056 int x = cursor_state->crtc_x;
10057 int y = cursor_state->crtc_y;
10058 u32 base = 0, pos = 0;
10059
10060 if (on)
10061 base = intel_crtc->cursor_addr;
10062
10063 if (x >= intel_crtc->config->pipe_src_w)
10064 base = 0;
10065
10066 if (y >= intel_crtc->config->pipe_src_h)
10067 base = 0;
10068
10069 if (x < 0) {
10070 if (x + cursor_state->crtc_w <= 0)
10071 base = 0;
10072
10073 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10074 x = -x;
10075 }
10076 pos |= x << CURSOR_X_SHIFT;
10077
10078 if (y < 0) {
10079 if (y + cursor_state->crtc_h <= 0)
10080 base = 0;
10081
10082 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10083 y = -y;
10084 }
10085 pos |= y << CURSOR_Y_SHIFT;
10086
10087 if (base == 0 && intel_crtc->cursor_base == 0)
10088 return;
10089
10090 I915_WRITE(CURPOS(pipe), pos);
10091
10092 /* ILK+ do this automagically */
10093 if (HAS_GMCH_DISPLAY(dev) &&
10094 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
10095 base += (cursor_state->crtc_h *
10096 cursor_state->crtc_w - 1) * 4;
10097 }
10098
10099 if (IS_845G(dev) || IS_I865G(dev))
10100 i845_update_cursor(crtc, base);
10101 else
10102 i9xx_update_cursor(crtc, base);
10103 }
10104
10105 static bool cursor_size_ok(struct drm_device *dev,
10106 uint32_t width, uint32_t height)
10107 {
10108 if (width == 0 || height == 0)
10109 return false;
10110
10111 /*
10112 * 845g/865g are special in that they are only limited by
10113 * the width of their cursors, the height is arbitrary up to
10114 * the precision of the register. Everything else requires
10115 * square cursors, limited to a few power-of-two sizes.
10116 */
10117 if (IS_845G(dev) || IS_I865G(dev)) {
10118 if ((width & 63) != 0)
10119 return false;
10120
10121 if (width > (IS_845G(dev) ? 64 : 512))
10122 return false;
10123
10124 if (height > 1023)
10125 return false;
10126 } else {
10127 switch (width | height) {
10128 case 256:
10129 case 128:
10130 if (IS_GEN2(dev))
10131 return false;
10132 case 64:
10133 break;
10134 default:
10135 return false;
10136 }
10137 }
10138
10139 return true;
10140 }
10141
10142 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10143 u16 *blue, uint32_t start, uint32_t size)
10144 {
10145 int end = (start + size > 256) ? 256 : start + size, i;
10146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10147
10148 for (i = start; i < end; i++) {
10149 intel_crtc->lut_r[i] = red[i] >> 8;
10150 intel_crtc->lut_g[i] = green[i] >> 8;
10151 intel_crtc->lut_b[i] = blue[i] >> 8;
10152 }
10153
10154 intel_crtc_load_lut(crtc);
10155 }
10156
10157 /* VESA 640x480x72Hz mode to set on the pipe */
10158 static struct drm_display_mode load_detect_mode = {
10159 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10160 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10161 };
10162
10163 struct drm_framebuffer *
10164 __intel_framebuffer_create(struct drm_device *dev,
10165 struct drm_mode_fb_cmd2 *mode_cmd,
10166 struct drm_i915_gem_object *obj)
10167 {
10168 struct intel_framebuffer *intel_fb;
10169 int ret;
10170
10171 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10172 if (!intel_fb)
10173 return ERR_PTR(-ENOMEM);
10174
10175 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10176 if (ret)
10177 goto err;
10178
10179 return &intel_fb->base;
10180
10181 err:
10182 kfree(intel_fb);
10183 return ERR_PTR(ret);
10184 }
10185
10186 static struct drm_framebuffer *
10187 intel_framebuffer_create(struct drm_device *dev,
10188 struct drm_mode_fb_cmd2 *mode_cmd,
10189 struct drm_i915_gem_object *obj)
10190 {
10191 struct drm_framebuffer *fb;
10192 int ret;
10193
10194 ret = i915_mutex_lock_interruptible(dev);
10195 if (ret)
10196 return ERR_PTR(ret);
10197 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10198 mutex_unlock(&dev->struct_mutex);
10199
10200 return fb;
10201 }
10202
10203 static u32
10204 intel_framebuffer_pitch_for_width(int width, int bpp)
10205 {
10206 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10207 return ALIGN(pitch, 64);
10208 }
10209
10210 static u32
10211 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10212 {
10213 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10214 return PAGE_ALIGN(pitch * mode->vdisplay);
10215 }
10216
10217 static struct drm_framebuffer *
10218 intel_framebuffer_create_for_mode(struct drm_device *dev,
10219 struct drm_display_mode *mode,
10220 int depth, int bpp)
10221 {
10222 struct drm_framebuffer *fb;
10223 struct drm_i915_gem_object *obj;
10224 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10225
10226 obj = i915_gem_alloc_object(dev,
10227 intel_framebuffer_size_for_mode(mode, bpp));
10228 if (obj == NULL)
10229 return ERR_PTR(-ENOMEM);
10230
10231 mode_cmd.width = mode->hdisplay;
10232 mode_cmd.height = mode->vdisplay;
10233 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10234 bpp);
10235 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10236
10237 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10238 if (IS_ERR(fb))
10239 drm_gem_object_unreference_unlocked(&obj->base);
10240
10241 return fb;
10242 }
10243
10244 static struct drm_framebuffer *
10245 mode_fits_in_fbdev(struct drm_device *dev,
10246 struct drm_display_mode *mode)
10247 {
10248 #ifdef CONFIG_DRM_FBDEV_EMULATION
10249 struct drm_i915_private *dev_priv = dev->dev_private;
10250 struct drm_i915_gem_object *obj;
10251 struct drm_framebuffer *fb;
10252
10253 if (!dev_priv->fbdev)
10254 return NULL;
10255
10256 if (!dev_priv->fbdev->fb)
10257 return NULL;
10258
10259 obj = dev_priv->fbdev->fb->obj;
10260 BUG_ON(!obj);
10261
10262 fb = &dev_priv->fbdev->fb->base;
10263 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10264 fb->bits_per_pixel))
10265 return NULL;
10266
10267 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10268 return NULL;
10269
10270 return fb;
10271 #else
10272 return NULL;
10273 #endif
10274 }
10275
10276 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10277 struct drm_crtc *crtc,
10278 struct drm_display_mode *mode,
10279 struct drm_framebuffer *fb,
10280 int x, int y)
10281 {
10282 struct drm_plane_state *plane_state;
10283 int hdisplay, vdisplay;
10284 int ret;
10285
10286 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10287 if (IS_ERR(plane_state))
10288 return PTR_ERR(plane_state);
10289
10290 if (mode)
10291 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10292 else
10293 hdisplay = vdisplay = 0;
10294
10295 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10296 if (ret)
10297 return ret;
10298 drm_atomic_set_fb_for_plane(plane_state, fb);
10299 plane_state->crtc_x = 0;
10300 plane_state->crtc_y = 0;
10301 plane_state->crtc_w = hdisplay;
10302 plane_state->crtc_h = vdisplay;
10303 plane_state->src_x = x << 16;
10304 plane_state->src_y = y << 16;
10305 plane_state->src_w = hdisplay << 16;
10306 plane_state->src_h = vdisplay << 16;
10307
10308 return 0;
10309 }
10310
10311 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10312 struct drm_display_mode *mode,
10313 struct intel_load_detect_pipe *old,
10314 struct drm_modeset_acquire_ctx *ctx)
10315 {
10316 struct intel_crtc *intel_crtc;
10317 struct intel_encoder *intel_encoder =
10318 intel_attached_encoder(connector);
10319 struct drm_crtc *possible_crtc;
10320 struct drm_encoder *encoder = &intel_encoder->base;
10321 struct drm_crtc *crtc = NULL;
10322 struct drm_device *dev = encoder->dev;
10323 struct drm_framebuffer *fb;
10324 struct drm_mode_config *config = &dev->mode_config;
10325 struct drm_atomic_state *state = NULL;
10326 struct drm_connector_state *connector_state;
10327 struct intel_crtc_state *crtc_state;
10328 int ret, i = -1;
10329
10330 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10331 connector->base.id, connector->name,
10332 encoder->base.id, encoder->name);
10333
10334 retry:
10335 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10336 if (ret)
10337 goto fail;
10338
10339 /*
10340 * Algorithm gets a little messy:
10341 *
10342 * - if the connector already has an assigned crtc, use it (but make
10343 * sure it's on first)
10344 *
10345 * - try to find the first unused crtc that can drive this connector,
10346 * and use that if we find one
10347 */
10348
10349 /* See if we already have a CRTC for this connector */
10350 if (encoder->crtc) {
10351 crtc = encoder->crtc;
10352
10353 ret = drm_modeset_lock(&crtc->mutex, ctx);
10354 if (ret)
10355 goto fail;
10356 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10357 if (ret)
10358 goto fail;
10359
10360 old->dpms_mode = connector->dpms;
10361 old->load_detect_temp = false;
10362
10363 /* Make sure the crtc and connector are running */
10364 if (connector->dpms != DRM_MODE_DPMS_ON)
10365 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10366
10367 return true;
10368 }
10369
10370 /* Find an unused one (if possible) */
10371 for_each_crtc(dev, possible_crtc) {
10372 i++;
10373 if (!(encoder->possible_crtcs & (1 << i)))
10374 continue;
10375 if (possible_crtc->state->enable)
10376 continue;
10377
10378 crtc = possible_crtc;
10379 break;
10380 }
10381
10382 /*
10383 * If we didn't find an unused CRTC, don't use any.
10384 */
10385 if (!crtc) {
10386 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10387 goto fail;
10388 }
10389
10390 ret = drm_modeset_lock(&crtc->mutex, ctx);
10391 if (ret)
10392 goto fail;
10393 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10394 if (ret)
10395 goto fail;
10396
10397 intel_crtc = to_intel_crtc(crtc);
10398 old->dpms_mode = connector->dpms;
10399 old->load_detect_temp = true;
10400 old->release_fb = NULL;
10401
10402 state = drm_atomic_state_alloc(dev);
10403 if (!state)
10404 return false;
10405
10406 state->acquire_ctx = ctx;
10407
10408 connector_state = drm_atomic_get_connector_state(state, connector);
10409 if (IS_ERR(connector_state)) {
10410 ret = PTR_ERR(connector_state);
10411 goto fail;
10412 }
10413
10414 connector_state->crtc = crtc;
10415 connector_state->best_encoder = &intel_encoder->base;
10416
10417 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10418 if (IS_ERR(crtc_state)) {
10419 ret = PTR_ERR(crtc_state);
10420 goto fail;
10421 }
10422
10423 crtc_state->base.active = crtc_state->base.enable = true;
10424
10425 if (!mode)
10426 mode = &load_detect_mode;
10427
10428 /* We need a framebuffer large enough to accommodate all accesses
10429 * that the plane may generate whilst we perform load detection.
10430 * We can not rely on the fbcon either being present (we get called
10431 * during its initialisation to detect all boot displays, or it may
10432 * not even exist) or that it is large enough to satisfy the
10433 * requested mode.
10434 */
10435 fb = mode_fits_in_fbdev(dev, mode);
10436 if (fb == NULL) {
10437 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10438 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10439 old->release_fb = fb;
10440 } else
10441 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10442 if (IS_ERR(fb)) {
10443 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10444 goto fail;
10445 }
10446
10447 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10448 if (ret)
10449 goto fail;
10450
10451 drm_mode_copy(&crtc_state->base.mode, mode);
10452
10453 if (drm_atomic_commit(state)) {
10454 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10455 if (old->release_fb)
10456 old->release_fb->funcs->destroy(old->release_fb);
10457 goto fail;
10458 }
10459 crtc->primary->crtc = crtc;
10460
10461 /* let the connector get through one full cycle before testing */
10462 intel_wait_for_vblank(dev, intel_crtc->pipe);
10463 return true;
10464
10465 fail:
10466 drm_atomic_state_free(state);
10467 state = NULL;
10468
10469 if (ret == -EDEADLK) {
10470 drm_modeset_backoff(ctx);
10471 goto retry;
10472 }
10473
10474 return false;
10475 }
10476
10477 void intel_release_load_detect_pipe(struct drm_connector *connector,
10478 struct intel_load_detect_pipe *old,
10479 struct drm_modeset_acquire_ctx *ctx)
10480 {
10481 struct drm_device *dev = connector->dev;
10482 struct intel_encoder *intel_encoder =
10483 intel_attached_encoder(connector);
10484 struct drm_encoder *encoder = &intel_encoder->base;
10485 struct drm_crtc *crtc = encoder->crtc;
10486 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10487 struct drm_atomic_state *state;
10488 struct drm_connector_state *connector_state;
10489 struct intel_crtc_state *crtc_state;
10490 int ret;
10491
10492 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10493 connector->base.id, connector->name,
10494 encoder->base.id, encoder->name);
10495
10496 if (old->load_detect_temp) {
10497 state = drm_atomic_state_alloc(dev);
10498 if (!state)
10499 goto fail;
10500
10501 state->acquire_ctx = ctx;
10502
10503 connector_state = drm_atomic_get_connector_state(state, connector);
10504 if (IS_ERR(connector_state))
10505 goto fail;
10506
10507 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10508 if (IS_ERR(crtc_state))
10509 goto fail;
10510
10511 connector_state->best_encoder = NULL;
10512 connector_state->crtc = NULL;
10513
10514 crtc_state->base.enable = crtc_state->base.active = false;
10515
10516 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10517 0, 0);
10518 if (ret)
10519 goto fail;
10520
10521 ret = drm_atomic_commit(state);
10522 if (ret)
10523 goto fail;
10524
10525 if (old->release_fb) {
10526 drm_framebuffer_unregister_private(old->release_fb);
10527 drm_framebuffer_unreference(old->release_fb);
10528 }
10529
10530 return;
10531 }
10532
10533 /* Switch crtc and encoder back off if necessary */
10534 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10535 connector->funcs->dpms(connector, old->dpms_mode);
10536
10537 return;
10538 fail:
10539 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10540 drm_atomic_state_free(state);
10541 }
10542
10543 static int i9xx_pll_refclk(struct drm_device *dev,
10544 const struct intel_crtc_state *pipe_config)
10545 {
10546 struct drm_i915_private *dev_priv = dev->dev_private;
10547 u32 dpll = pipe_config->dpll_hw_state.dpll;
10548
10549 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10550 return dev_priv->vbt.lvds_ssc_freq;
10551 else if (HAS_PCH_SPLIT(dev))
10552 return 120000;
10553 else if (!IS_GEN2(dev))
10554 return 96000;
10555 else
10556 return 48000;
10557 }
10558
10559 /* Returns the clock of the currently programmed mode of the given pipe. */
10560 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10561 struct intel_crtc_state *pipe_config)
10562 {
10563 struct drm_device *dev = crtc->base.dev;
10564 struct drm_i915_private *dev_priv = dev->dev_private;
10565 int pipe = pipe_config->cpu_transcoder;
10566 u32 dpll = pipe_config->dpll_hw_state.dpll;
10567 u32 fp;
10568 intel_clock_t clock;
10569 int port_clock;
10570 int refclk = i9xx_pll_refclk(dev, pipe_config);
10571
10572 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10573 fp = pipe_config->dpll_hw_state.fp0;
10574 else
10575 fp = pipe_config->dpll_hw_state.fp1;
10576
10577 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10578 if (IS_PINEVIEW(dev)) {
10579 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10580 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10581 } else {
10582 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10583 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10584 }
10585
10586 if (!IS_GEN2(dev)) {
10587 if (IS_PINEVIEW(dev))
10588 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10589 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10590 else
10591 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10592 DPLL_FPA01_P1_POST_DIV_SHIFT);
10593
10594 switch (dpll & DPLL_MODE_MASK) {
10595 case DPLLB_MODE_DAC_SERIAL:
10596 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10597 5 : 10;
10598 break;
10599 case DPLLB_MODE_LVDS:
10600 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10601 7 : 14;
10602 break;
10603 default:
10604 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10605 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10606 return;
10607 }
10608
10609 if (IS_PINEVIEW(dev))
10610 port_clock = pnv_calc_dpll_params(refclk, &clock);
10611 else
10612 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10613 } else {
10614 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10615 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10616
10617 if (is_lvds) {
10618 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10619 DPLL_FPA01_P1_POST_DIV_SHIFT);
10620
10621 if (lvds & LVDS_CLKB_POWER_UP)
10622 clock.p2 = 7;
10623 else
10624 clock.p2 = 14;
10625 } else {
10626 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10627 clock.p1 = 2;
10628 else {
10629 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10630 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10631 }
10632 if (dpll & PLL_P2_DIVIDE_BY_4)
10633 clock.p2 = 4;
10634 else
10635 clock.p2 = 2;
10636 }
10637
10638 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10639 }
10640
10641 /*
10642 * This value includes pixel_multiplier. We will use
10643 * port_clock to compute adjusted_mode.crtc_clock in the
10644 * encoder's get_config() function.
10645 */
10646 pipe_config->port_clock = port_clock;
10647 }
10648
10649 int intel_dotclock_calculate(int link_freq,
10650 const struct intel_link_m_n *m_n)
10651 {
10652 /*
10653 * The calculation for the data clock is:
10654 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10655 * But we want to avoid losing precison if possible, so:
10656 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10657 *
10658 * and the link clock is simpler:
10659 * link_clock = (m * link_clock) / n
10660 */
10661
10662 if (!m_n->link_n)
10663 return 0;
10664
10665 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10666 }
10667
10668 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10669 struct intel_crtc_state *pipe_config)
10670 {
10671 struct drm_device *dev = crtc->base.dev;
10672
10673 /* read out port_clock from the DPLL */
10674 i9xx_crtc_clock_get(crtc, pipe_config);
10675
10676 /*
10677 * This value does not include pixel_multiplier.
10678 * We will check that port_clock and adjusted_mode.crtc_clock
10679 * agree once we know their relationship in the encoder's
10680 * get_config() function.
10681 */
10682 pipe_config->base.adjusted_mode.crtc_clock =
10683 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10684 &pipe_config->fdi_m_n);
10685 }
10686
10687 /** Returns the currently programmed mode of the given pipe. */
10688 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10689 struct drm_crtc *crtc)
10690 {
10691 struct drm_i915_private *dev_priv = dev->dev_private;
10692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10693 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10694 struct drm_display_mode *mode;
10695 struct intel_crtc_state pipe_config;
10696 int htot = I915_READ(HTOTAL(cpu_transcoder));
10697 int hsync = I915_READ(HSYNC(cpu_transcoder));
10698 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10699 int vsync = I915_READ(VSYNC(cpu_transcoder));
10700 enum pipe pipe = intel_crtc->pipe;
10701
10702 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10703 if (!mode)
10704 return NULL;
10705
10706 /*
10707 * Construct a pipe_config sufficient for getting the clock info
10708 * back out of crtc_clock_get.
10709 *
10710 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10711 * to use a real value here instead.
10712 */
10713 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10714 pipe_config.pixel_multiplier = 1;
10715 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10716 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10717 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10718 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10719
10720 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10721 mode->hdisplay = (htot & 0xffff) + 1;
10722 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10723 mode->hsync_start = (hsync & 0xffff) + 1;
10724 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10725 mode->vdisplay = (vtot & 0xffff) + 1;
10726 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10727 mode->vsync_start = (vsync & 0xffff) + 1;
10728 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10729
10730 drm_mode_set_name(mode);
10731
10732 return mode;
10733 }
10734
10735 void intel_mark_busy(struct drm_device *dev)
10736 {
10737 struct drm_i915_private *dev_priv = dev->dev_private;
10738
10739 if (dev_priv->mm.busy)
10740 return;
10741
10742 intel_runtime_pm_get(dev_priv);
10743 i915_update_gfx_val(dev_priv);
10744 if (INTEL_INFO(dev)->gen >= 6)
10745 gen6_rps_busy(dev_priv);
10746 dev_priv->mm.busy = true;
10747 }
10748
10749 void intel_mark_idle(struct drm_device *dev)
10750 {
10751 struct drm_i915_private *dev_priv = dev->dev_private;
10752
10753 if (!dev_priv->mm.busy)
10754 return;
10755
10756 dev_priv->mm.busy = false;
10757
10758 if (INTEL_INFO(dev)->gen >= 6)
10759 gen6_rps_idle(dev->dev_private);
10760
10761 intel_runtime_pm_put(dev_priv);
10762 }
10763
10764 static void intel_crtc_destroy(struct drm_crtc *crtc)
10765 {
10766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10767 struct drm_device *dev = crtc->dev;
10768 struct intel_unpin_work *work;
10769
10770 spin_lock_irq(&dev->event_lock);
10771 work = intel_crtc->unpin_work;
10772 intel_crtc->unpin_work = NULL;
10773 spin_unlock_irq(&dev->event_lock);
10774
10775 if (work) {
10776 cancel_work_sync(&work->work);
10777 kfree(work);
10778 }
10779
10780 drm_crtc_cleanup(crtc);
10781
10782 kfree(intel_crtc);
10783 }
10784
10785 static void intel_unpin_work_fn(struct work_struct *__work)
10786 {
10787 struct intel_unpin_work *work =
10788 container_of(__work, struct intel_unpin_work, work);
10789 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10790 struct drm_device *dev = crtc->base.dev;
10791 struct drm_plane *primary = crtc->base.primary;
10792
10793 mutex_lock(&dev->struct_mutex);
10794 intel_unpin_fb_obj(work->old_fb, primary->state);
10795 drm_gem_object_unreference(&work->pending_flip_obj->base);
10796
10797 if (work->flip_queued_req)
10798 i915_gem_request_assign(&work->flip_queued_req, NULL);
10799 mutex_unlock(&dev->struct_mutex);
10800
10801 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10802 drm_framebuffer_unreference(work->old_fb);
10803
10804 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10805 atomic_dec(&crtc->unpin_work_count);
10806
10807 kfree(work);
10808 }
10809
10810 static void do_intel_finish_page_flip(struct drm_device *dev,
10811 struct drm_crtc *crtc)
10812 {
10813 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10814 struct intel_unpin_work *work;
10815 unsigned long flags;
10816
10817 /* Ignore early vblank irqs */
10818 if (intel_crtc == NULL)
10819 return;
10820
10821 /*
10822 * This is called both by irq handlers and the reset code (to complete
10823 * lost pageflips) so needs the full irqsave spinlocks.
10824 */
10825 spin_lock_irqsave(&dev->event_lock, flags);
10826 work = intel_crtc->unpin_work;
10827
10828 /* Ensure we don't miss a work->pending update ... */
10829 smp_rmb();
10830
10831 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10832 spin_unlock_irqrestore(&dev->event_lock, flags);
10833 return;
10834 }
10835
10836 page_flip_completed(intel_crtc);
10837
10838 spin_unlock_irqrestore(&dev->event_lock, flags);
10839 }
10840
10841 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10842 {
10843 struct drm_i915_private *dev_priv = dev->dev_private;
10844 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10845
10846 do_intel_finish_page_flip(dev, crtc);
10847 }
10848
10849 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10850 {
10851 struct drm_i915_private *dev_priv = dev->dev_private;
10852 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10853
10854 do_intel_finish_page_flip(dev, crtc);
10855 }
10856
10857 /* Is 'a' after or equal to 'b'? */
10858 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10859 {
10860 return !((a - b) & 0x80000000);
10861 }
10862
10863 static bool page_flip_finished(struct intel_crtc *crtc)
10864 {
10865 struct drm_device *dev = crtc->base.dev;
10866 struct drm_i915_private *dev_priv = dev->dev_private;
10867
10868 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10869 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10870 return true;
10871
10872 /*
10873 * The relevant registers doen't exist on pre-ctg.
10874 * As the flip done interrupt doesn't trigger for mmio
10875 * flips on gmch platforms, a flip count check isn't
10876 * really needed there. But since ctg has the registers,
10877 * include it in the check anyway.
10878 */
10879 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10880 return true;
10881
10882 /*
10883 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10884 * used the same base address. In that case the mmio flip might
10885 * have completed, but the CS hasn't even executed the flip yet.
10886 *
10887 * A flip count check isn't enough as the CS might have updated
10888 * the base address just after start of vblank, but before we
10889 * managed to process the interrupt. This means we'd complete the
10890 * CS flip too soon.
10891 *
10892 * Combining both checks should get us a good enough result. It may
10893 * still happen that the CS flip has been executed, but has not
10894 * yet actually completed. But in case the base address is the same
10895 * anyway, we don't really care.
10896 */
10897 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10898 crtc->unpin_work->gtt_offset &&
10899 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
10900 crtc->unpin_work->flip_count);
10901 }
10902
10903 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10904 {
10905 struct drm_i915_private *dev_priv = dev->dev_private;
10906 struct intel_crtc *intel_crtc =
10907 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10908 unsigned long flags;
10909
10910
10911 /*
10912 * This is called both by irq handlers and the reset code (to complete
10913 * lost pageflips) so needs the full irqsave spinlocks.
10914 *
10915 * NB: An MMIO update of the plane base pointer will also
10916 * generate a page-flip completion irq, i.e. every modeset
10917 * is also accompanied by a spurious intel_prepare_page_flip().
10918 */
10919 spin_lock_irqsave(&dev->event_lock, flags);
10920 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10921 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10922 spin_unlock_irqrestore(&dev->event_lock, flags);
10923 }
10924
10925 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
10926 {
10927 /* Ensure that the work item is consistent when activating it ... */
10928 smp_wmb();
10929 atomic_set(&work->pending, INTEL_FLIP_PENDING);
10930 /* and that it is marked active as soon as the irq could fire. */
10931 smp_wmb();
10932 }
10933
10934 static int intel_gen2_queue_flip(struct drm_device *dev,
10935 struct drm_crtc *crtc,
10936 struct drm_framebuffer *fb,
10937 struct drm_i915_gem_object *obj,
10938 struct drm_i915_gem_request *req,
10939 uint32_t flags)
10940 {
10941 struct intel_engine_cs *ring = req->ring;
10942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10943 u32 flip_mask;
10944 int ret;
10945
10946 ret = intel_ring_begin(req, 6);
10947 if (ret)
10948 return ret;
10949
10950 /* Can't queue multiple flips, so wait for the previous
10951 * one to finish before executing the next.
10952 */
10953 if (intel_crtc->plane)
10954 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10955 else
10956 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10957 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10958 intel_ring_emit(ring, MI_NOOP);
10959 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10960 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10961 intel_ring_emit(ring, fb->pitches[0]);
10962 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10963 intel_ring_emit(ring, 0); /* aux display base address, unused */
10964
10965 intel_mark_page_flip_active(intel_crtc->unpin_work);
10966 return 0;
10967 }
10968
10969 static int intel_gen3_queue_flip(struct drm_device *dev,
10970 struct drm_crtc *crtc,
10971 struct drm_framebuffer *fb,
10972 struct drm_i915_gem_object *obj,
10973 struct drm_i915_gem_request *req,
10974 uint32_t flags)
10975 {
10976 struct intel_engine_cs *ring = req->ring;
10977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10978 u32 flip_mask;
10979 int ret;
10980
10981 ret = intel_ring_begin(req, 6);
10982 if (ret)
10983 return ret;
10984
10985 if (intel_crtc->plane)
10986 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10987 else
10988 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10989 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10990 intel_ring_emit(ring, MI_NOOP);
10991 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10992 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10993 intel_ring_emit(ring, fb->pitches[0]);
10994 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10995 intel_ring_emit(ring, MI_NOOP);
10996
10997 intel_mark_page_flip_active(intel_crtc->unpin_work);
10998 return 0;
10999 }
11000
11001 static int intel_gen4_queue_flip(struct drm_device *dev,
11002 struct drm_crtc *crtc,
11003 struct drm_framebuffer *fb,
11004 struct drm_i915_gem_object *obj,
11005 struct drm_i915_gem_request *req,
11006 uint32_t flags)
11007 {
11008 struct intel_engine_cs *ring = req->ring;
11009 struct drm_i915_private *dev_priv = dev->dev_private;
11010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11011 uint32_t pf, pipesrc;
11012 int ret;
11013
11014 ret = intel_ring_begin(req, 4);
11015 if (ret)
11016 return ret;
11017
11018 /* i965+ uses the linear or tiled offsets from the
11019 * Display Registers (which do not change across a page-flip)
11020 * so we need only reprogram the base address.
11021 */
11022 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11023 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11024 intel_ring_emit(ring, fb->pitches[0]);
11025 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11026 obj->tiling_mode);
11027
11028 /* XXX Enabling the panel-fitter across page-flip is so far
11029 * untested on non-native modes, so ignore it for now.
11030 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11031 */
11032 pf = 0;
11033 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11034 intel_ring_emit(ring, pf | pipesrc);
11035
11036 intel_mark_page_flip_active(intel_crtc->unpin_work);
11037 return 0;
11038 }
11039
11040 static int intel_gen6_queue_flip(struct drm_device *dev,
11041 struct drm_crtc *crtc,
11042 struct drm_framebuffer *fb,
11043 struct drm_i915_gem_object *obj,
11044 struct drm_i915_gem_request *req,
11045 uint32_t flags)
11046 {
11047 struct intel_engine_cs *ring = req->ring;
11048 struct drm_i915_private *dev_priv = dev->dev_private;
11049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11050 uint32_t pf, pipesrc;
11051 int ret;
11052
11053 ret = intel_ring_begin(req, 4);
11054 if (ret)
11055 return ret;
11056
11057 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11058 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11059 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11060 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11061
11062 /* Contrary to the suggestions in the documentation,
11063 * "Enable Panel Fitter" does not seem to be required when page
11064 * flipping with a non-native mode, and worse causes a normal
11065 * modeset to fail.
11066 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11067 */
11068 pf = 0;
11069 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11070 intel_ring_emit(ring, pf | pipesrc);
11071
11072 intel_mark_page_flip_active(intel_crtc->unpin_work);
11073 return 0;
11074 }
11075
11076 static int intel_gen7_queue_flip(struct drm_device *dev,
11077 struct drm_crtc *crtc,
11078 struct drm_framebuffer *fb,
11079 struct drm_i915_gem_object *obj,
11080 struct drm_i915_gem_request *req,
11081 uint32_t flags)
11082 {
11083 struct intel_engine_cs *ring = req->ring;
11084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11085 uint32_t plane_bit = 0;
11086 int len, ret;
11087
11088 switch (intel_crtc->plane) {
11089 case PLANE_A:
11090 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11091 break;
11092 case PLANE_B:
11093 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11094 break;
11095 case PLANE_C:
11096 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11097 break;
11098 default:
11099 WARN_ONCE(1, "unknown plane in flip command\n");
11100 return -ENODEV;
11101 }
11102
11103 len = 4;
11104 if (ring->id == RCS) {
11105 len += 6;
11106 /*
11107 * On Gen 8, SRM is now taking an extra dword to accommodate
11108 * 48bits addresses, and we need a NOOP for the batch size to
11109 * stay even.
11110 */
11111 if (IS_GEN8(dev))
11112 len += 2;
11113 }
11114
11115 /*
11116 * BSpec MI_DISPLAY_FLIP for IVB:
11117 * "The full packet must be contained within the same cache line."
11118 *
11119 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11120 * cacheline, if we ever start emitting more commands before
11121 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11122 * then do the cacheline alignment, and finally emit the
11123 * MI_DISPLAY_FLIP.
11124 */
11125 ret = intel_ring_cacheline_align(req);
11126 if (ret)
11127 return ret;
11128
11129 ret = intel_ring_begin(req, len);
11130 if (ret)
11131 return ret;
11132
11133 /* Unmask the flip-done completion message. Note that the bspec says that
11134 * we should do this for both the BCS and RCS, and that we must not unmask
11135 * more than one flip event at any time (or ensure that one flip message
11136 * can be sent by waiting for flip-done prior to queueing new flips).
11137 * Experimentation says that BCS works despite DERRMR masking all
11138 * flip-done completion events and that unmasking all planes at once
11139 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11140 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11141 */
11142 if (ring->id == RCS) {
11143 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11144 intel_ring_emit_reg(ring, DERRMR);
11145 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11146 DERRMR_PIPEB_PRI_FLIP_DONE |
11147 DERRMR_PIPEC_PRI_FLIP_DONE));
11148 if (IS_GEN8(dev))
11149 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11150 MI_SRM_LRM_GLOBAL_GTT);
11151 else
11152 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11153 MI_SRM_LRM_GLOBAL_GTT);
11154 intel_ring_emit_reg(ring, DERRMR);
11155 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11156 if (IS_GEN8(dev)) {
11157 intel_ring_emit(ring, 0);
11158 intel_ring_emit(ring, MI_NOOP);
11159 }
11160 }
11161
11162 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11163 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11164 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11165 intel_ring_emit(ring, (MI_NOOP));
11166
11167 intel_mark_page_flip_active(intel_crtc->unpin_work);
11168 return 0;
11169 }
11170
11171 static bool use_mmio_flip(struct intel_engine_cs *ring,
11172 struct drm_i915_gem_object *obj)
11173 {
11174 /*
11175 * This is not being used for older platforms, because
11176 * non-availability of flip done interrupt forces us to use
11177 * CS flips. Older platforms derive flip done using some clever
11178 * tricks involving the flip_pending status bits and vblank irqs.
11179 * So using MMIO flips there would disrupt this mechanism.
11180 */
11181
11182 if (ring == NULL)
11183 return true;
11184
11185 if (INTEL_INFO(ring->dev)->gen < 5)
11186 return false;
11187
11188 if (i915.use_mmio_flip < 0)
11189 return false;
11190 else if (i915.use_mmio_flip > 0)
11191 return true;
11192 else if (i915.enable_execlists)
11193 return true;
11194 else
11195 return ring != i915_gem_request_get_ring(obj->last_write_req);
11196 }
11197
11198 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11199 unsigned int rotation,
11200 struct intel_unpin_work *work)
11201 {
11202 struct drm_device *dev = intel_crtc->base.dev;
11203 struct drm_i915_private *dev_priv = dev->dev_private;
11204 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11205 const enum pipe pipe = intel_crtc->pipe;
11206 u32 ctl, stride, tile_height;
11207
11208 ctl = I915_READ(PLANE_CTL(pipe, 0));
11209 ctl &= ~PLANE_CTL_TILED_MASK;
11210 switch (fb->modifier[0]) {
11211 case DRM_FORMAT_MOD_NONE:
11212 break;
11213 case I915_FORMAT_MOD_X_TILED:
11214 ctl |= PLANE_CTL_TILED_X;
11215 break;
11216 case I915_FORMAT_MOD_Y_TILED:
11217 ctl |= PLANE_CTL_TILED_Y;
11218 break;
11219 case I915_FORMAT_MOD_Yf_TILED:
11220 ctl |= PLANE_CTL_TILED_YF;
11221 break;
11222 default:
11223 MISSING_CASE(fb->modifier[0]);
11224 }
11225
11226 /*
11227 * The stride is either expressed as a multiple of 64 bytes chunks for
11228 * linear buffers or in number of tiles for tiled buffers.
11229 */
11230 if (intel_rotation_90_or_270(rotation)) {
11231 /* stride = Surface height in tiles */
11232 tile_height = intel_tile_height(dev, fb->pixel_format,
11233 fb->modifier[0], 0);
11234 stride = DIV_ROUND_UP(fb->height, tile_height);
11235 } else {
11236 stride = fb->pitches[0] /
11237 intel_fb_stride_alignment(dev, fb->modifier[0],
11238 fb->pixel_format);
11239 }
11240
11241 /*
11242 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11243 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11244 */
11245 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11246 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11247
11248 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11249 POSTING_READ(PLANE_SURF(pipe, 0));
11250 }
11251
11252 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11253 struct intel_unpin_work *work)
11254 {
11255 struct drm_device *dev = intel_crtc->base.dev;
11256 struct drm_i915_private *dev_priv = dev->dev_private;
11257 struct intel_framebuffer *intel_fb =
11258 to_intel_framebuffer(intel_crtc->base.primary->fb);
11259 struct drm_i915_gem_object *obj = intel_fb->obj;
11260 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11261 u32 dspcntr;
11262
11263 dspcntr = I915_READ(reg);
11264
11265 if (obj->tiling_mode != I915_TILING_NONE)
11266 dspcntr |= DISPPLANE_TILED;
11267 else
11268 dspcntr &= ~DISPPLANE_TILED;
11269
11270 I915_WRITE(reg, dspcntr);
11271
11272 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11273 POSTING_READ(DSPSURF(intel_crtc->plane));
11274 }
11275
11276 /*
11277 * XXX: This is the temporary way to update the plane registers until we get
11278 * around to using the usual plane update functions for MMIO flips
11279 */
11280 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11281 {
11282 struct intel_crtc *crtc = mmio_flip->crtc;
11283 struct intel_unpin_work *work;
11284
11285 spin_lock_irq(&crtc->base.dev->event_lock);
11286 work = crtc->unpin_work;
11287 spin_unlock_irq(&crtc->base.dev->event_lock);
11288 if (work == NULL)
11289 return;
11290
11291 intel_mark_page_flip_active(work);
11292
11293 intel_pipe_update_start(crtc);
11294
11295 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11296 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11297 else
11298 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11299 ilk_do_mmio_flip(crtc, work);
11300
11301 intel_pipe_update_end(crtc);
11302 }
11303
11304 static void intel_mmio_flip_work_func(struct work_struct *work)
11305 {
11306 struct intel_mmio_flip *mmio_flip =
11307 container_of(work, struct intel_mmio_flip, work);
11308
11309 if (mmio_flip->req) {
11310 WARN_ON(__i915_wait_request(mmio_flip->req,
11311 mmio_flip->crtc->reset_counter,
11312 false, NULL,
11313 &mmio_flip->i915->rps.mmioflips));
11314 i915_gem_request_unreference__unlocked(mmio_flip->req);
11315 }
11316
11317 intel_do_mmio_flip(mmio_flip);
11318 kfree(mmio_flip);
11319 }
11320
11321 static int intel_queue_mmio_flip(struct drm_device *dev,
11322 struct drm_crtc *crtc,
11323 struct drm_i915_gem_object *obj)
11324 {
11325 struct intel_mmio_flip *mmio_flip;
11326
11327 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11328 if (mmio_flip == NULL)
11329 return -ENOMEM;
11330
11331 mmio_flip->i915 = to_i915(dev);
11332 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11333 mmio_flip->crtc = to_intel_crtc(crtc);
11334 mmio_flip->rotation = crtc->primary->state->rotation;
11335
11336 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11337 schedule_work(&mmio_flip->work);
11338
11339 return 0;
11340 }
11341
11342 static int intel_default_queue_flip(struct drm_device *dev,
11343 struct drm_crtc *crtc,
11344 struct drm_framebuffer *fb,
11345 struct drm_i915_gem_object *obj,
11346 struct drm_i915_gem_request *req,
11347 uint32_t flags)
11348 {
11349 return -ENODEV;
11350 }
11351
11352 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11353 struct drm_crtc *crtc)
11354 {
11355 struct drm_i915_private *dev_priv = dev->dev_private;
11356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11357 struct intel_unpin_work *work = intel_crtc->unpin_work;
11358 u32 addr;
11359
11360 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11361 return true;
11362
11363 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11364 return false;
11365
11366 if (!work->enable_stall_check)
11367 return false;
11368
11369 if (work->flip_ready_vblank == 0) {
11370 if (work->flip_queued_req &&
11371 !i915_gem_request_completed(work->flip_queued_req, true))
11372 return false;
11373
11374 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11375 }
11376
11377 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11378 return false;
11379
11380 /* Potential stall - if we see that the flip has happened,
11381 * assume a missed interrupt. */
11382 if (INTEL_INFO(dev)->gen >= 4)
11383 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11384 else
11385 addr = I915_READ(DSPADDR(intel_crtc->plane));
11386
11387 /* There is a potential issue here with a false positive after a flip
11388 * to the same address. We could address this by checking for a
11389 * non-incrementing frame counter.
11390 */
11391 return addr == work->gtt_offset;
11392 }
11393
11394 void intel_check_page_flip(struct drm_device *dev, int pipe)
11395 {
11396 struct drm_i915_private *dev_priv = dev->dev_private;
11397 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11399 struct intel_unpin_work *work;
11400
11401 WARN_ON(!in_interrupt());
11402
11403 if (crtc == NULL)
11404 return;
11405
11406 spin_lock(&dev->event_lock);
11407 work = intel_crtc->unpin_work;
11408 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11409 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11410 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11411 page_flip_completed(intel_crtc);
11412 work = NULL;
11413 }
11414 if (work != NULL &&
11415 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11416 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11417 spin_unlock(&dev->event_lock);
11418 }
11419
11420 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11421 struct drm_framebuffer *fb,
11422 struct drm_pending_vblank_event *event,
11423 uint32_t page_flip_flags)
11424 {
11425 struct drm_device *dev = crtc->dev;
11426 struct drm_i915_private *dev_priv = dev->dev_private;
11427 struct drm_framebuffer *old_fb = crtc->primary->fb;
11428 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11430 struct drm_plane *primary = crtc->primary;
11431 enum pipe pipe = intel_crtc->pipe;
11432 struct intel_unpin_work *work;
11433 struct intel_engine_cs *ring;
11434 bool mmio_flip;
11435 struct drm_i915_gem_request *request = NULL;
11436 int ret;
11437
11438 /*
11439 * drm_mode_page_flip_ioctl() should already catch this, but double
11440 * check to be safe. In the future we may enable pageflipping from
11441 * a disabled primary plane.
11442 */
11443 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11444 return -EBUSY;
11445
11446 /* Can't change pixel format via MI display flips. */
11447 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11448 return -EINVAL;
11449
11450 /*
11451 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11452 * Note that pitch changes could also affect these register.
11453 */
11454 if (INTEL_INFO(dev)->gen > 3 &&
11455 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11456 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11457 return -EINVAL;
11458
11459 if (i915_terminally_wedged(&dev_priv->gpu_error))
11460 goto out_hang;
11461
11462 work = kzalloc(sizeof(*work), GFP_KERNEL);
11463 if (work == NULL)
11464 return -ENOMEM;
11465
11466 work->event = event;
11467 work->crtc = crtc;
11468 work->old_fb = old_fb;
11469 INIT_WORK(&work->work, intel_unpin_work_fn);
11470
11471 ret = drm_crtc_vblank_get(crtc);
11472 if (ret)
11473 goto free_work;
11474
11475 /* We borrow the event spin lock for protecting unpin_work */
11476 spin_lock_irq(&dev->event_lock);
11477 if (intel_crtc->unpin_work) {
11478 /* Before declaring the flip queue wedged, check if
11479 * the hardware completed the operation behind our backs.
11480 */
11481 if (__intel_pageflip_stall_check(dev, crtc)) {
11482 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11483 page_flip_completed(intel_crtc);
11484 } else {
11485 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11486 spin_unlock_irq(&dev->event_lock);
11487
11488 drm_crtc_vblank_put(crtc);
11489 kfree(work);
11490 return -EBUSY;
11491 }
11492 }
11493 intel_crtc->unpin_work = work;
11494 spin_unlock_irq(&dev->event_lock);
11495
11496 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11497 flush_workqueue(dev_priv->wq);
11498
11499 /* Reference the objects for the scheduled work. */
11500 drm_framebuffer_reference(work->old_fb);
11501 drm_gem_object_reference(&obj->base);
11502
11503 crtc->primary->fb = fb;
11504 update_state_fb(crtc->primary);
11505
11506 work->pending_flip_obj = obj;
11507
11508 ret = i915_mutex_lock_interruptible(dev);
11509 if (ret)
11510 goto cleanup;
11511
11512 atomic_inc(&intel_crtc->unpin_work_count);
11513 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11514
11515 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11516 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11517
11518 if (IS_VALLEYVIEW(dev)) {
11519 ring = &dev_priv->ring[BCS];
11520 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11521 /* vlv: DISPLAY_FLIP fails to change tiling */
11522 ring = NULL;
11523 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11524 ring = &dev_priv->ring[BCS];
11525 } else if (INTEL_INFO(dev)->gen >= 7) {
11526 ring = i915_gem_request_get_ring(obj->last_write_req);
11527 if (ring == NULL || ring->id != RCS)
11528 ring = &dev_priv->ring[BCS];
11529 } else {
11530 ring = &dev_priv->ring[RCS];
11531 }
11532
11533 mmio_flip = use_mmio_flip(ring, obj);
11534
11535 /* When using CS flips, we want to emit semaphores between rings.
11536 * However, when using mmio flips we will create a task to do the
11537 * synchronisation, so all we want here is to pin the framebuffer
11538 * into the display plane and skip any waits.
11539 */
11540 if (!mmio_flip) {
11541 ret = i915_gem_object_sync(obj, ring, &request);
11542 if (ret)
11543 goto cleanup_pending;
11544 }
11545
11546 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11547 crtc->primary->state);
11548 if (ret)
11549 goto cleanup_pending;
11550
11551 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11552 obj, 0);
11553 work->gtt_offset += intel_crtc->dspaddr_offset;
11554
11555 if (mmio_flip) {
11556 ret = intel_queue_mmio_flip(dev, crtc, obj);
11557 if (ret)
11558 goto cleanup_unpin;
11559
11560 i915_gem_request_assign(&work->flip_queued_req,
11561 obj->last_write_req);
11562 } else {
11563 if (!request) {
11564 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11565 if (ret)
11566 goto cleanup_unpin;
11567 }
11568
11569 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11570 page_flip_flags);
11571 if (ret)
11572 goto cleanup_unpin;
11573
11574 i915_gem_request_assign(&work->flip_queued_req, request);
11575 }
11576
11577 if (request)
11578 i915_add_request_no_flush(request);
11579
11580 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11581 work->enable_stall_check = true;
11582
11583 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11584 to_intel_plane(primary)->frontbuffer_bit);
11585 mutex_unlock(&dev->struct_mutex);
11586
11587 intel_fbc_disable_crtc(intel_crtc);
11588 intel_frontbuffer_flip_prepare(dev,
11589 to_intel_plane(primary)->frontbuffer_bit);
11590
11591 trace_i915_flip_request(intel_crtc->plane, obj);
11592
11593 return 0;
11594
11595 cleanup_unpin:
11596 intel_unpin_fb_obj(fb, crtc->primary->state);
11597 cleanup_pending:
11598 if (request)
11599 i915_gem_request_cancel(request);
11600 atomic_dec(&intel_crtc->unpin_work_count);
11601 mutex_unlock(&dev->struct_mutex);
11602 cleanup:
11603 crtc->primary->fb = old_fb;
11604 update_state_fb(crtc->primary);
11605
11606 drm_gem_object_unreference_unlocked(&obj->base);
11607 drm_framebuffer_unreference(work->old_fb);
11608
11609 spin_lock_irq(&dev->event_lock);
11610 intel_crtc->unpin_work = NULL;
11611 spin_unlock_irq(&dev->event_lock);
11612
11613 drm_crtc_vblank_put(crtc);
11614 free_work:
11615 kfree(work);
11616
11617 if (ret == -EIO) {
11618 struct drm_atomic_state *state;
11619 struct drm_plane_state *plane_state;
11620
11621 out_hang:
11622 state = drm_atomic_state_alloc(dev);
11623 if (!state)
11624 return -ENOMEM;
11625 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11626
11627 retry:
11628 plane_state = drm_atomic_get_plane_state(state, primary);
11629 ret = PTR_ERR_OR_ZERO(plane_state);
11630 if (!ret) {
11631 drm_atomic_set_fb_for_plane(plane_state, fb);
11632
11633 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11634 if (!ret)
11635 ret = drm_atomic_commit(state);
11636 }
11637
11638 if (ret == -EDEADLK) {
11639 drm_modeset_backoff(state->acquire_ctx);
11640 drm_atomic_state_clear(state);
11641 goto retry;
11642 }
11643
11644 if (ret)
11645 drm_atomic_state_free(state);
11646
11647 if (ret == 0 && event) {
11648 spin_lock_irq(&dev->event_lock);
11649 drm_send_vblank_event(dev, pipe, event);
11650 spin_unlock_irq(&dev->event_lock);
11651 }
11652 }
11653 return ret;
11654 }
11655
11656
11657 /**
11658 * intel_wm_need_update - Check whether watermarks need updating
11659 * @plane: drm plane
11660 * @state: new plane state
11661 *
11662 * Check current plane state versus the new one to determine whether
11663 * watermarks need to be recalculated.
11664 *
11665 * Returns true or false.
11666 */
11667 static bool intel_wm_need_update(struct drm_plane *plane,
11668 struct drm_plane_state *state)
11669 {
11670 struct intel_plane_state *new = to_intel_plane_state(state);
11671 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11672
11673 /* Update watermarks on tiling or size changes. */
11674 if (!plane->state->fb || !state->fb ||
11675 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11676 plane->state->rotation != state->rotation ||
11677 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11678 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11679 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11680 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11681 return true;
11682
11683 return false;
11684 }
11685
11686 static bool needs_scaling(struct intel_plane_state *state)
11687 {
11688 int src_w = drm_rect_width(&state->src) >> 16;
11689 int src_h = drm_rect_height(&state->src) >> 16;
11690 int dst_w = drm_rect_width(&state->dst);
11691 int dst_h = drm_rect_height(&state->dst);
11692
11693 return (src_w != dst_w || src_h != dst_h);
11694 }
11695
11696 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11697 struct drm_plane_state *plane_state)
11698 {
11699 struct drm_crtc *crtc = crtc_state->crtc;
11700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11701 struct drm_plane *plane = plane_state->plane;
11702 struct drm_device *dev = crtc->dev;
11703 struct drm_i915_private *dev_priv = dev->dev_private;
11704 struct intel_plane_state *old_plane_state =
11705 to_intel_plane_state(plane->state);
11706 int idx = intel_crtc->base.base.id, ret;
11707 int i = drm_plane_index(plane);
11708 bool mode_changed = needs_modeset(crtc_state);
11709 bool was_crtc_enabled = crtc->state->active;
11710 bool is_crtc_enabled = crtc_state->active;
11711 bool turn_off, turn_on, visible, was_visible;
11712 struct drm_framebuffer *fb = plane_state->fb;
11713
11714 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11715 plane->type != DRM_PLANE_TYPE_CURSOR) {
11716 ret = skl_update_scaler_plane(
11717 to_intel_crtc_state(crtc_state),
11718 to_intel_plane_state(plane_state));
11719 if (ret)
11720 return ret;
11721 }
11722
11723 was_visible = old_plane_state->visible;
11724 visible = to_intel_plane_state(plane_state)->visible;
11725
11726 if (!was_crtc_enabled && WARN_ON(was_visible))
11727 was_visible = false;
11728
11729 if (!is_crtc_enabled && WARN_ON(visible))
11730 visible = false;
11731
11732 if (!was_visible && !visible)
11733 return 0;
11734
11735 turn_off = was_visible && (!visible || mode_changed);
11736 turn_on = visible && (!was_visible || mode_changed);
11737
11738 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11739 plane->base.id, fb ? fb->base.id : -1);
11740
11741 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11742 plane->base.id, was_visible, visible,
11743 turn_off, turn_on, mode_changed);
11744
11745 if (turn_on) {
11746 intel_crtc->atomic.update_wm_pre = true;
11747 /* must disable cxsr around plane enable/disable */
11748 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11749 intel_crtc->atomic.disable_cxsr = true;
11750 /* to potentially re-enable cxsr */
11751 intel_crtc->atomic.wait_vblank = true;
11752 intel_crtc->atomic.update_wm_post = true;
11753 }
11754 } else if (turn_off) {
11755 intel_crtc->atomic.update_wm_post = true;
11756 /* must disable cxsr around plane enable/disable */
11757 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11758 if (is_crtc_enabled)
11759 intel_crtc->atomic.wait_vblank = true;
11760 intel_crtc->atomic.disable_cxsr = true;
11761 }
11762 } else if (intel_wm_need_update(plane, plane_state)) {
11763 intel_crtc->atomic.update_wm_pre = true;
11764 }
11765
11766 if (visible || was_visible)
11767 intel_crtc->atomic.fb_bits |=
11768 to_intel_plane(plane)->frontbuffer_bit;
11769
11770 switch (plane->type) {
11771 case DRM_PLANE_TYPE_PRIMARY:
11772 intel_crtc->atomic.pre_disable_primary = turn_off;
11773 intel_crtc->atomic.post_enable_primary = turn_on;
11774
11775 if (turn_off) {
11776 /*
11777 * FIXME: Actually if we will still have any other
11778 * plane enabled on the pipe we could let IPS enabled
11779 * still, but for now lets consider that when we make
11780 * primary invisible by setting DSPCNTR to 0 on
11781 * update_primary_plane function IPS needs to be
11782 * disable.
11783 */
11784 intel_crtc->atomic.disable_ips = true;
11785
11786 intel_crtc->atomic.disable_fbc = true;
11787 }
11788
11789 /*
11790 * FBC does not work on some platforms for rotated
11791 * planes, so disable it when rotation is not 0 and
11792 * update it when rotation is set back to 0.
11793 *
11794 * FIXME: This is redundant with the fbc update done in
11795 * the primary plane enable function except that that
11796 * one is done too late. We eventually need to unify
11797 * this.
11798 */
11799
11800 if (visible &&
11801 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11802 dev_priv->fbc.crtc == intel_crtc &&
11803 plane_state->rotation != BIT(DRM_ROTATE_0))
11804 intel_crtc->atomic.disable_fbc = true;
11805
11806 /*
11807 * BDW signals flip done immediately if the plane
11808 * is disabled, even if the plane enable is already
11809 * armed to occur at the next vblank :(
11810 */
11811 if (turn_on && IS_BROADWELL(dev))
11812 intel_crtc->atomic.wait_vblank = true;
11813
11814 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11815 break;
11816 case DRM_PLANE_TYPE_CURSOR:
11817 break;
11818 case DRM_PLANE_TYPE_OVERLAY:
11819 /*
11820 * WaCxSRDisabledForSpriteScaling:ivb
11821 *
11822 * cstate->update_wm was already set above, so this flag will
11823 * take effect when we commit and program watermarks.
11824 */
11825 if (IS_IVYBRIDGE(dev) &&
11826 needs_scaling(to_intel_plane_state(plane_state)) &&
11827 !needs_scaling(old_plane_state)) {
11828 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
11829 } else if (turn_off && !mode_changed) {
11830 intel_crtc->atomic.wait_vblank = true;
11831 intel_crtc->atomic.update_sprite_watermarks |=
11832 1 << i;
11833 }
11834
11835 break;
11836 }
11837 return 0;
11838 }
11839
11840 static bool encoders_cloneable(const struct intel_encoder *a,
11841 const struct intel_encoder *b)
11842 {
11843 /* masks could be asymmetric, so check both ways */
11844 return a == b || (a->cloneable & (1 << b->type) &&
11845 b->cloneable & (1 << a->type));
11846 }
11847
11848 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11849 struct intel_crtc *crtc,
11850 struct intel_encoder *encoder)
11851 {
11852 struct intel_encoder *source_encoder;
11853 struct drm_connector *connector;
11854 struct drm_connector_state *connector_state;
11855 int i;
11856
11857 for_each_connector_in_state(state, connector, connector_state, i) {
11858 if (connector_state->crtc != &crtc->base)
11859 continue;
11860
11861 source_encoder =
11862 to_intel_encoder(connector_state->best_encoder);
11863 if (!encoders_cloneable(encoder, source_encoder))
11864 return false;
11865 }
11866
11867 return true;
11868 }
11869
11870 static bool check_encoder_cloning(struct drm_atomic_state *state,
11871 struct intel_crtc *crtc)
11872 {
11873 struct intel_encoder *encoder;
11874 struct drm_connector *connector;
11875 struct drm_connector_state *connector_state;
11876 int i;
11877
11878 for_each_connector_in_state(state, connector, connector_state, i) {
11879 if (connector_state->crtc != &crtc->base)
11880 continue;
11881
11882 encoder = to_intel_encoder(connector_state->best_encoder);
11883 if (!check_single_encoder_cloning(state, crtc, encoder))
11884 return false;
11885 }
11886
11887 return true;
11888 }
11889
11890 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11891 struct drm_crtc_state *crtc_state)
11892 {
11893 struct drm_device *dev = crtc->dev;
11894 struct drm_i915_private *dev_priv = dev->dev_private;
11895 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11896 struct intel_crtc_state *pipe_config =
11897 to_intel_crtc_state(crtc_state);
11898 struct drm_atomic_state *state = crtc_state->state;
11899 int ret;
11900 bool mode_changed = needs_modeset(crtc_state);
11901
11902 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11903 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11904 return -EINVAL;
11905 }
11906
11907 if (mode_changed && !crtc_state->active)
11908 intel_crtc->atomic.update_wm_post = true;
11909
11910 if (mode_changed && crtc_state->enable &&
11911 dev_priv->display.crtc_compute_clock &&
11912 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11913 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11914 pipe_config);
11915 if (ret)
11916 return ret;
11917 }
11918
11919 ret = 0;
11920 if (dev_priv->display.compute_pipe_wm) {
11921 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
11922 if (ret)
11923 return ret;
11924 }
11925
11926 if (INTEL_INFO(dev)->gen >= 9) {
11927 if (mode_changed)
11928 ret = skl_update_scaler_crtc(pipe_config);
11929
11930 if (!ret)
11931 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11932 pipe_config);
11933 }
11934
11935 return ret;
11936 }
11937
11938 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11939 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11940 .load_lut = intel_crtc_load_lut,
11941 .atomic_begin = intel_begin_crtc_commit,
11942 .atomic_flush = intel_finish_crtc_commit,
11943 .atomic_check = intel_crtc_atomic_check,
11944 };
11945
11946 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11947 {
11948 struct intel_connector *connector;
11949
11950 for_each_intel_connector(dev, connector) {
11951 if (connector->base.encoder) {
11952 connector->base.state->best_encoder =
11953 connector->base.encoder;
11954 connector->base.state->crtc =
11955 connector->base.encoder->crtc;
11956 } else {
11957 connector->base.state->best_encoder = NULL;
11958 connector->base.state->crtc = NULL;
11959 }
11960 }
11961 }
11962
11963 static void
11964 connected_sink_compute_bpp(struct intel_connector *connector,
11965 struct intel_crtc_state *pipe_config)
11966 {
11967 int bpp = pipe_config->pipe_bpp;
11968
11969 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11970 connector->base.base.id,
11971 connector->base.name);
11972
11973 /* Don't use an invalid EDID bpc value */
11974 if (connector->base.display_info.bpc &&
11975 connector->base.display_info.bpc * 3 < bpp) {
11976 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11977 bpp, connector->base.display_info.bpc*3);
11978 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11979 }
11980
11981 /* Clamp bpp to 8 on screens without EDID 1.4 */
11982 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11983 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11984 bpp);
11985 pipe_config->pipe_bpp = 24;
11986 }
11987 }
11988
11989 static int
11990 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11991 struct intel_crtc_state *pipe_config)
11992 {
11993 struct drm_device *dev = crtc->base.dev;
11994 struct drm_atomic_state *state;
11995 struct drm_connector *connector;
11996 struct drm_connector_state *connector_state;
11997 int bpp, i;
11998
11999 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
12000 bpp = 10*3;
12001 else if (INTEL_INFO(dev)->gen >= 5)
12002 bpp = 12*3;
12003 else
12004 bpp = 8*3;
12005
12006
12007 pipe_config->pipe_bpp = bpp;
12008
12009 state = pipe_config->base.state;
12010
12011 /* Clamp display bpp to EDID value */
12012 for_each_connector_in_state(state, connector, connector_state, i) {
12013 if (connector_state->crtc != &crtc->base)
12014 continue;
12015
12016 connected_sink_compute_bpp(to_intel_connector(connector),
12017 pipe_config);
12018 }
12019
12020 return bpp;
12021 }
12022
12023 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12024 {
12025 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12026 "type: 0x%x flags: 0x%x\n",
12027 mode->crtc_clock,
12028 mode->crtc_hdisplay, mode->crtc_hsync_start,
12029 mode->crtc_hsync_end, mode->crtc_htotal,
12030 mode->crtc_vdisplay, mode->crtc_vsync_start,
12031 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12032 }
12033
12034 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12035 struct intel_crtc_state *pipe_config,
12036 const char *context)
12037 {
12038 struct drm_device *dev = crtc->base.dev;
12039 struct drm_plane *plane;
12040 struct intel_plane *intel_plane;
12041 struct intel_plane_state *state;
12042 struct drm_framebuffer *fb;
12043
12044 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12045 context, pipe_config, pipe_name(crtc->pipe));
12046
12047 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12048 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12049 pipe_config->pipe_bpp, pipe_config->dither);
12050 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12051 pipe_config->has_pch_encoder,
12052 pipe_config->fdi_lanes,
12053 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12054 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12055 pipe_config->fdi_m_n.tu);
12056 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12057 pipe_config->has_dp_encoder,
12058 pipe_config->lane_count,
12059 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12060 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12061 pipe_config->dp_m_n.tu);
12062
12063 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12064 pipe_config->has_dp_encoder,
12065 pipe_config->lane_count,
12066 pipe_config->dp_m2_n2.gmch_m,
12067 pipe_config->dp_m2_n2.gmch_n,
12068 pipe_config->dp_m2_n2.link_m,
12069 pipe_config->dp_m2_n2.link_n,
12070 pipe_config->dp_m2_n2.tu);
12071
12072 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12073 pipe_config->has_audio,
12074 pipe_config->has_infoframe);
12075
12076 DRM_DEBUG_KMS("requested mode:\n");
12077 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12078 DRM_DEBUG_KMS("adjusted mode:\n");
12079 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12080 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12081 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12082 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12083 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12084 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12085 crtc->num_scalers,
12086 pipe_config->scaler_state.scaler_users,
12087 pipe_config->scaler_state.scaler_id);
12088 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12089 pipe_config->gmch_pfit.control,
12090 pipe_config->gmch_pfit.pgm_ratios,
12091 pipe_config->gmch_pfit.lvds_border_bits);
12092 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12093 pipe_config->pch_pfit.pos,
12094 pipe_config->pch_pfit.size,
12095 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12096 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12097 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12098
12099 if (IS_BROXTON(dev)) {
12100 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12101 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12102 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12103 pipe_config->ddi_pll_sel,
12104 pipe_config->dpll_hw_state.ebb0,
12105 pipe_config->dpll_hw_state.ebb4,
12106 pipe_config->dpll_hw_state.pll0,
12107 pipe_config->dpll_hw_state.pll1,
12108 pipe_config->dpll_hw_state.pll2,
12109 pipe_config->dpll_hw_state.pll3,
12110 pipe_config->dpll_hw_state.pll6,
12111 pipe_config->dpll_hw_state.pll8,
12112 pipe_config->dpll_hw_state.pll9,
12113 pipe_config->dpll_hw_state.pll10,
12114 pipe_config->dpll_hw_state.pcsdw12);
12115 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12116 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12117 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12118 pipe_config->ddi_pll_sel,
12119 pipe_config->dpll_hw_state.ctrl1,
12120 pipe_config->dpll_hw_state.cfgcr1,
12121 pipe_config->dpll_hw_state.cfgcr2);
12122 } else if (HAS_DDI(dev)) {
12123 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12124 pipe_config->ddi_pll_sel,
12125 pipe_config->dpll_hw_state.wrpll,
12126 pipe_config->dpll_hw_state.spll);
12127 } else {
12128 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12129 "fp0: 0x%x, fp1: 0x%x\n",
12130 pipe_config->dpll_hw_state.dpll,
12131 pipe_config->dpll_hw_state.dpll_md,
12132 pipe_config->dpll_hw_state.fp0,
12133 pipe_config->dpll_hw_state.fp1);
12134 }
12135
12136 DRM_DEBUG_KMS("planes on this crtc\n");
12137 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12138 intel_plane = to_intel_plane(plane);
12139 if (intel_plane->pipe != crtc->pipe)
12140 continue;
12141
12142 state = to_intel_plane_state(plane->state);
12143 fb = state->base.fb;
12144 if (!fb) {
12145 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12146 "disabled, scaler_id = %d\n",
12147 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12148 plane->base.id, intel_plane->pipe,
12149 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12150 drm_plane_index(plane), state->scaler_id);
12151 continue;
12152 }
12153
12154 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12155 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12156 plane->base.id, intel_plane->pipe,
12157 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12158 drm_plane_index(plane));
12159 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12160 fb->base.id, fb->width, fb->height, fb->pixel_format);
12161 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12162 state->scaler_id,
12163 state->src.x1 >> 16, state->src.y1 >> 16,
12164 drm_rect_width(&state->src) >> 16,
12165 drm_rect_height(&state->src) >> 16,
12166 state->dst.x1, state->dst.y1,
12167 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12168 }
12169 }
12170
12171 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12172 {
12173 struct drm_device *dev = state->dev;
12174 struct intel_encoder *encoder;
12175 struct drm_connector *connector;
12176 struct drm_connector_state *connector_state;
12177 unsigned int used_ports = 0;
12178 int i;
12179
12180 /*
12181 * Walk the connector list instead of the encoder
12182 * list to detect the problem on ddi platforms
12183 * where there's just one encoder per digital port.
12184 */
12185 for_each_connector_in_state(state, connector, connector_state, i) {
12186 if (!connector_state->best_encoder)
12187 continue;
12188
12189 encoder = to_intel_encoder(connector_state->best_encoder);
12190
12191 WARN_ON(!connector_state->crtc);
12192
12193 switch (encoder->type) {
12194 unsigned int port_mask;
12195 case INTEL_OUTPUT_UNKNOWN:
12196 if (WARN_ON(!HAS_DDI(dev)))
12197 break;
12198 case INTEL_OUTPUT_DISPLAYPORT:
12199 case INTEL_OUTPUT_HDMI:
12200 case INTEL_OUTPUT_EDP:
12201 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12202
12203 /* the same port mustn't appear more than once */
12204 if (used_ports & port_mask)
12205 return false;
12206
12207 used_ports |= port_mask;
12208 default:
12209 break;
12210 }
12211 }
12212
12213 return true;
12214 }
12215
12216 static void
12217 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12218 {
12219 struct drm_crtc_state tmp_state;
12220 struct intel_crtc_scaler_state scaler_state;
12221 struct intel_dpll_hw_state dpll_hw_state;
12222 enum intel_dpll_id shared_dpll;
12223 uint32_t ddi_pll_sel;
12224 bool force_thru;
12225
12226 /* FIXME: before the switch to atomic started, a new pipe_config was
12227 * kzalloc'd. Code that depends on any field being zero should be
12228 * fixed, so that the crtc_state can be safely duplicated. For now,
12229 * only fields that are know to not cause problems are preserved. */
12230
12231 tmp_state = crtc_state->base;
12232 scaler_state = crtc_state->scaler_state;
12233 shared_dpll = crtc_state->shared_dpll;
12234 dpll_hw_state = crtc_state->dpll_hw_state;
12235 ddi_pll_sel = crtc_state->ddi_pll_sel;
12236 force_thru = crtc_state->pch_pfit.force_thru;
12237
12238 memset(crtc_state, 0, sizeof *crtc_state);
12239
12240 crtc_state->base = tmp_state;
12241 crtc_state->scaler_state = scaler_state;
12242 crtc_state->shared_dpll = shared_dpll;
12243 crtc_state->dpll_hw_state = dpll_hw_state;
12244 crtc_state->ddi_pll_sel = ddi_pll_sel;
12245 crtc_state->pch_pfit.force_thru = force_thru;
12246 }
12247
12248 static int
12249 intel_modeset_pipe_config(struct drm_crtc *crtc,
12250 struct intel_crtc_state *pipe_config)
12251 {
12252 struct drm_atomic_state *state = pipe_config->base.state;
12253 struct intel_encoder *encoder;
12254 struct drm_connector *connector;
12255 struct drm_connector_state *connector_state;
12256 int base_bpp, ret = -EINVAL;
12257 int i;
12258 bool retry = true;
12259
12260 clear_intel_crtc_state(pipe_config);
12261
12262 pipe_config->cpu_transcoder =
12263 (enum transcoder) to_intel_crtc(crtc)->pipe;
12264
12265 /*
12266 * Sanitize sync polarity flags based on requested ones. If neither
12267 * positive or negative polarity is requested, treat this as meaning
12268 * negative polarity.
12269 */
12270 if (!(pipe_config->base.adjusted_mode.flags &
12271 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12272 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12273
12274 if (!(pipe_config->base.adjusted_mode.flags &
12275 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12276 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12277
12278 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12279 pipe_config);
12280 if (base_bpp < 0)
12281 goto fail;
12282
12283 /*
12284 * Determine the real pipe dimensions. Note that stereo modes can
12285 * increase the actual pipe size due to the frame doubling and
12286 * insertion of additional space for blanks between the frame. This
12287 * is stored in the crtc timings. We use the requested mode to do this
12288 * computation to clearly distinguish it from the adjusted mode, which
12289 * can be changed by the connectors in the below retry loop.
12290 */
12291 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12292 &pipe_config->pipe_src_w,
12293 &pipe_config->pipe_src_h);
12294
12295 encoder_retry:
12296 /* Ensure the port clock defaults are reset when retrying. */
12297 pipe_config->port_clock = 0;
12298 pipe_config->pixel_multiplier = 1;
12299
12300 /* Fill in default crtc timings, allow encoders to overwrite them. */
12301 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12302 CRTC_STEREO_DOUBLE);
12303
12304 /* Pass our mode to the connectors and the CRTC to give them a chance to
12305 * adjust it according to limitations or connector properties, and also
12306 * a chance to reject the mode entirely.
12307 */
12308 for_each_connector_in_state(state, connector, connector_state, i) {
12309 if (connector_state->crtc != crtc)
12310 continue;
12311
12312 encoder = to_intel_encoder(connector_state->best_encoder);
12313
12314 if (!(encoder->compute_config(encoder, pipe_config))) {
12315 DRM_DEBUG_KMS("Encoder config failure\n");
12316 goto fail;
12317 }
12318 }
12319
12320 /* Set default port clock if not overwritten by the encoder. Needs to be
12321 * done afterwards in case the encoder adjusts the mode. */
12322 if (!pipe_config->port_clock)
12323 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12324 * pipe_config->pixel_multiplier;
12325
12326 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12327 if (ret < 0) {
12328 DRM_DEBUG_KMS("CRTC fixup failed\n");
12329 goto fail;
12330 }
12331
12332 if (ret == RETRY) {
12333 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12334 ret = -EINVAL;
12335 goto fail;
12336 }
12337
12338 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12339 retry = false;
12340 goto encoder_retry;
12341 }
12342
12343 /* Dithering seems to not pass-through bits correctly when it should, so
12344 * only enable it on 6bpc panels. */
12345 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12346 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12347 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12348
12349 fail:
12350 return ret;
12351 }
12352
12353 static void
12354 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12355 {
12356 struct drm_crtc *crtc;
12357 struct drm_crtc_state *crtc_state;
12358 int i;
12359
12360 /* Double check state. */
12361 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12362 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12363
12364 /* Update hwmode for vblank functions */
12365 if (crtc->state->active)
12366 crtc->hwmode = crtc->state->adjusted_mode;
12367 else
12368 crtc->hwmode.crtc_clock = 0;
12369
12370 /*
12371 * Update legacy state to satisfy fbc code. This can
12372 * be removed when fbc uses the atomic state.
12373 */
12374 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12375 struct drm_plane_state *plane_state = crtc->primary->state;
12376
12377 crtc->primary->fb = plane_state->fb;
12378 crtc->x = plane_state->src_x >> 16;
12379 crtc->y = plane_state->src_y >> 16;
12380 }
12381 }
12382 }
12383
12384 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12385 {
12386 int diff;
12387
12388 if (clock1 == clock2)
12389 return true;
12390
12391 if (!clock1 || !clock2)
12392 return false;
12393
12394 diff = abs(clock1 - clock2);
12395
12396 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12397 return true;
12398
12399 return false;
12400 }
12401
12402 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12403 list_for_each_entry((intel_crtc), \
12404 &(dev)->mode_config.crtc_list, \
12405 base.head) \
12406 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12407
12408 static bool
12409 intel_compare_m_n(unsigned int m, unsigned int n,
12410 unsigned int m2, unsigned int n2,
12411 bool exact)
12412 {
12413 if (m == m2 && n == n2)
12414 return true;
12415
12416 if (exact || !m || !n || !m2 || !n2)
12417 return false;
12418
12419 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12420
12421 if (m > m2) {
12422 while (m > m2) {
12423 m2 <<= 1;
12424 n2 <<= 1;
12425 }
12426 } else if (m < m2) {
12427 while (m < m2) {
12428 m <<= 1;
12429 n <<= 1;
12430 }
12431 }
12432
12433 return m == m2 && n == n2;
12434 }
12435
12436 static bool
12437 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12438 struct intel_link_m_n *m2_n2,
12439 bool adjust)
12440 {
12441 if (m_n->tu == m2_n2->tu &&
12442 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12443 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12444 intel_compare_m_n(m_n->link_m, m_n->link_n,
12445 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12446 if (adjust)
12447 *m2_n2 = *m_n;
12448
12449 return true;
12450 }
12451
12452 return false;
12453 }
12454
12455 static bool
12456 intel_pipe_config_compare(struct drm_device *dev,
12457 struct intel_crtc_state *current_config,
12458 struct intel_crtc_state *pipe_config,
12459 bool adjust)
12460 {
12461 bool ret = true;
12462
12463 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12464 do { \
12465 if (!adjust) \
12466 DRM_ERROR(fmt, ##__VA_ARGS__); \
12467 else \
12468 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12469 } while (0)
12470
12471 #define PIPE_CONF_CHECK_X(name) \
12472 if (current_config->name != pipe_config->name) { \
12473 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12474 "(expected 0x%08x, found 0x%08x)\n", \
12475 current_config->name, \
12476 pipe_config->name); \
12477 ret = false; \
12478 }
12479
12480 #define PIPE_CONF_CHECK_I(name) \
12481 if (current_config->name != pipe_config->name) { \
12482 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12483 "(expected %i, found %i)\n", \
12484 current_config->name, \
12485 pipe_config->name); \
12486 ret = false; \
12487 }
12488
12489 #define PIPE_CONF_CHECK_M_N(name) \
12490 if (!intel_compare_link_m_n(&current_config->name, \
12491 &pipe_config->name,\
12492 adjust)) { \
12493 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12494 "(expected tu %i gmch %i/%i link %i/%i, " \
12495 "found tu %i, gmch %i/%i link %i/%i)\n", \
12496 current_config->name.tu, \
12497 current_config->name.gmch_m, \
12498 current_config->name.gmch_n, \
12499 current_config->name.link_m, \
12500 current_config->name.link_n, \
12501 pipe_config->name.tu, \
12502 pipe_config->name.gmch_m, \
12503 pipe_config->name.gmch_n, \
12504 pipe_config->name.link_m, \
12505 pipe_config->name.link_n); \
12506 ret = false; \
12507 }
12508
12509 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12510 if (!intel_compare_link_m_n(&current_config->name, \
12511 &pipe_config->name, adjust) && \
12512 !intel_compare_link_m_n(&current_config->alt_name, \
12513 &pipe_config->name, adjust)) { \
12514 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12515 "(expected tu %i gmch %i/%i link %i/%i, " \
12516 "or tu %i gmch %i/%i link %i/%i, " \
12517 "found tu %i, gmch %i/%i link %i/%i)\n", \
12518 current_config->name.tu, \
12519 current_config->name.gmch_m, \
12520 current_config->name.gmch_n, \
12521 current_config->name.link_m, \
12522 current_config->name.link_n, \
12523 current_config->alt_name.tu, \
12524 current_config->alt_name.gmch_m, \
12525 current_config->alt_name.gmch_n, \
12526 current_config->alt_name.link_m, \
12527 current_config->alt_name.link_n, \
12528 pipe_config->name.tu, \
12529 pipe_config->name.gmch_m, \
12530 pipe_config->name.gmch_n, \
12531 pipe_config->name.link_m, \
12532 pipe_config->name.link_n); \
12533 ret = false; \
12534 }
12535
12536 /* This is required for BDW+ where there is only one set of registers for
12537 * switching between high and low RR.
12538 * This macro can be used whenever a comparison has to be made between one
12539 * hw state and multiple sw state variables.
12540 */
12541 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12542 if ((current_config->name != pipe_config->name) && \
12543 (current_config->alt_name != pipe_config->name)) { \
12544 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12545 "(expected %i or %i, found %i)\n", \
12546 current_config->name, \
12547 current_config->alt_name, \
12548 pipe_config->name); \
12549 ret = false; \
12550 }
12551
12552 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12553 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12554 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12555 "(expected %i, found %i)\n", \
12556 current_config->name & (mask), \
12557 pipe_config->name & (mask)); \
12558 ret = false; \
12559 }
12560
12561 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12562 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12563 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12564 "(expected %i, found %i)\n", \
12565 current_config->name, \
12566 pipe_config->name); \
12567 ret = false; \
12568 }
12569
12570 #define PIPE_CONF_QUIRK(quirk) \
12571 ((current_config->quirks | pipe_config->quirks) & (quirk))
12572
12573 PIPE_CONF_CHECK_I(cpu_transcoder);
12574
12575 PIPE_CONF_CHECK_I(has_pch_encoder);
12576 PIPE_CONF_CHECK_I(fdi_lanes);
12577 PIPE_CONF_CHECK_M_N(fdi_m_n);
12578
12579 PIPE_CONF_CHECK_I(has_dp_encoder);
12580 PIPE_CONF_CHECK_I(lane_count);
12581
12582 if (INTEL_INFO(dev)->gen < 8) {
12583 PIPE_CONF_CHECK_M_N(dp_m_n);
12584
12585 if (current_config->has_drrs)
12586 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12587 } else
12588 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12589
12590 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12591 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12592 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12593 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12594 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12595 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12596
12597 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12598 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12599 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12600 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12601 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12602 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12603
12604 PIPE_CONF_CHECK_I(pixel_multiplier);
12605 PIPE_CONF_CHECK_I(has_hdmi_sink);
12606 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12607 IS_VALLEYVIEW(dev))
12608 PIPE_CONF_CHECK_I(limited_color_range);
12609 PIPE_CONF_CHECK_I(has_infoframe);
12610
12611 PIPE_CONF_CHECK_I(has_audio);
12612
12613 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12614 DRM_MODE_FLAG_INTERLACE);
12615
12616 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12617 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12618 DRM_MODE_FLAG_PHSYNC);
12619 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12620 DRM_MODE_FLAG_NHSYNC);
12621 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12622 DRM_MODE_FLAG_PVSYNC);
12623 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12624 DRM_MODE_FLAG_NVSYNC);
12625 }
12626
12627 PIPE_CONF_CHECK_X(gmch_pfit.control);
12628 /* pfit ratios are autocomputed by the hw on gen4+ */
12629 if (INTEL_INFO(dev)->gen < 4)
12630 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12631 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12632
12633 if (!adjust) {
12634 PIPE_CONF_CHECK_I(pipe_src_w);
12635 PIPE_CONF_CHECK_I(pipe_src_h);
12636
12637 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12638 if (current_config->pch_pfit.enabled) {
12639 PIPE_CONF_CHECK_X(pch_pfit.pos);
12640 PIPE_CONF_CHECK_X(pch_pfit.size);
12641 }
12642
12643 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12644 }
12645
12646 /* BDW+ don't expose a synchronous way to read the state */
12647 if (IS_HASWELL(dev))
12648 PIPE_CONF_CHECK_I(ips_enabled);
12649
12650 PIPE_CONF_CHECK_I(double_wide);
12651
12652 PIPE_CONF_CHECK_X(ddi_pll_sel);
12653
12654 PIPE_CONF_CHECK_I(shared_dpll);
12655 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12656 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12657 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12658 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12659 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12660 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12661 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12662 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12663 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12664
12665 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12666 PIPE_CONF_CHECK_I(pipe_bpp);
12667
12668 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12669 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12670
12671 #undef PIPE_CONF_CHECK_X
12672 #undef PIPE_CONF_CHECK_I
12673 #undef PIPE_CONF_CHECK_I_ALT
12674 #undef PIPE_CONF_CHECK_FLAGS
12675 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12676 #undef PIPE_CONF_QUIRK
12677 #undef INTEL_ERR_OR_DBG_KMS
12678
12679 return ret;
12680 }
12681
12682 static void check_wm_state(struct drm_device *dev)
12683 {
12684 struct drm_i915_private *dev_priv = dev->dev_private;
12685 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12686 struct intel_crtc *intel_crtc;
12687 int plane;
12688
12689 if (INTEL_INFO(dev)->gen < 9)
12690 return;
12691
12692 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12693 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12694
12695 for_each_intel_crtc(dev, intel_crtc) {
12696 struct skl_ddb_entry *hw_entry, *sw_entry;
12697 const enum pipe pipe = intel_crtc->pipe;
12698
12699 if (!intel_crtc->active)
12700 continue;
12701
12702 /* planes */
12703 for_each_plane(dev_priv, pipe, plane) {
12704 hw_entry = &hw_ddb.plane[pipe][plane];
12705 sw_entry = &sw_ddb->plane[pipe][plane];
12706
12707 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12708 continue;
12709
12710 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12711 "(expected (%u,%u), found (%u,%u))\n",
12712 pipe_name(pipe), plane + 1,
12713 sw_entry->start, sw_entry->end,
12714 hw_entry->start, hw_entry->end);
12715 }
12716
12717 /* cursor */
12718 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12719 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12720
12721 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12722 continue;
12723
12724 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12725 "(expected (%u,%u), found (%u,%u))\n",
12726 pipe_name(pipe),
12727 sw_entry->start, sw_entry->end,
12728 hw_entry->start, hw_entry->end);
12729 }
12730 }
12731
12732 static void
12733 check_connector_state(struct drm_device *dev,
12734 struct drm_atomic_state *old_state)
12735 {
12736 struct drm_connector_state *old_conn_state;
12737 struct drm_connector *connector;
12738 int i;
12739
12740 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12741 struct drm_encoder *encoder = connector->encoder;
12742 struct drm_connector_state *state = connector->state;
12743
12744 /* This also checks the encoder/connector hw state with the
12745 * ->get_hw_state callbacks. */
12746 intel_connector_check_state(to_intel_connector(connector));
12747
12748 I915_STATE_WARN(state->best_encoder != encoder,
12749 "connector's atomic encoder doesn't match legacy encoder\n");
12750 }
12751 }
12752
12753 static void
12754 check_encoder_state(struct drm_device *dev)
12755 {
12756 struct intel_encoder *encoder;
12757 struct intel_connector *connector;
12758
12759 for_each_intel_encoder(dev, encoder) {
12760 bool enabled = false;
12761 enum pipe pipe;
12762
12763 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12764 encoder->base.base.id,
12765 encoder->base.name);
12766
12767 for_each_intel_connector(dev, connector) {
12768 if (connector->base.state->best_encoder != &encoder->base)
12769 continue;
12770 enabled = true;
12771
12772 I915_STATE_WARN(connector->base.state->crtc !=
12773 encoder->base.crtc,
12774 "connector's crtc doesn't match encoder crtc\n");
12775 }
12776
12777 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12778 "encoder's enabled state mismatch "
12779 "(expected %i, found %i)\n",
12780 !!encoder->base.crtc, enabled);
12781
12782 if (!encoder->base.crtc) {
12783 bool active;
12784
12785 active = encoder->get_hw_state(encoder, &pipe);
12786 I915_STATE_WARN(active,
12787 "encoder detached but still enabled on pipe %c.\n",
12788 pipe_name(pipe));
12789 }
12790 }
12791 }
12792
12793 static void
12794 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
12795 {
12796 struct drm_i915_private *dev_priv = dev->dev_private;
12797 struct intel_encoder *encoder;
12798 struct drm_crtc_state *old_crtc_state;
12799 struct drm_crtc *crtc;
12800 int i;
12801
12802 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
12803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12804 struct intel_crtc_state *pipe_config, *sw_config;
12805 bool active;
12806
12807 if (!needs_modeset(crtc->state) &&
12808 !to_intel_crtc_state(crtc->state)->update_pipe)
12809 continue;
12810
12811 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
12812 pipe_config = to_intel_crtc_state(old_crtc_state);
12813 memset(pipe_config, 0, sizeof(*pipe_config));
12814 pipe_config->base.crtc = crtc;
12815 pipe_config->base.state = old_state;
12816
12817 DRM_DEBUG_KMS("[CRTC:%d]\n",
12818 crtc->base.id);
12819
12820 active = dev_priv->display.get_pipe_config(intel_crtc,
12821 pipe_config);
12822
12823 /* hw state is inconsistent with the pipe quirk */
12824 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12825 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12826 active = crtc->state->active;
12827
12828 I915_STATE_WARN(crtc->state->active != active,
12829 "crtc active state doesn't match with hw state "
12830 "(expected %i, found %i)\n", crtc->state->active, active);
12831
12832 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
12833 "transitional active state does not match atomic hw state "
12834 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
12835
12836 for_each_encoder_on_crtc(dev, crtc, encoder) {
12837 enum pipe pipe;
12838
12839 active = encoder->get_hw_state(encoder, &pipe);
12840 I915_STATE_WARN(active != crtc->state->active,
12841 "[ENCODER:%i] active %i with crtc active %i\n",
12842 encoder->base.base.id, active, crtc->state->active);
12843
12844 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
12845 "Encoder connected to wrong pipe %c\n",
12846 pipe_name(pipe));
12847
12848 if (active)
12849 encoder->get_config(encoder, pipe_config);
12850 }
12851
12852 if (!crtc->state->active)
12853 continue;
12854
12855 sw_config = to_intel_crtc_state(crtc->state);
12856 if (!intel_pipe_config_compare(dev, sw_config,
12857 pipe_config, false)) {
12858 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12859 intel_dump_pipe_config(intel_crtc, pipe_config,
12860 "[hw state]");
12861 intel_dump_pipe_config(intel_crtc, sw_config,
12862 "[sw state]");
12863 }
12864 }
12865 }
12866
12867 static void
12868 check_shared_dpll_state(struct drm_device *dev)
12869 {
12870 struct drm_i915_private *dev_priv = dev->dev_private;
12871 struct intel_crtc *crtc;
12872 struct intel_dpll_hw_state dpll_hw_state;
12873 int i;
12874
12875 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12876 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12877 int enabled_crtcs = 0, active_crtcs = 0;
12878 bool active;
12879
12880 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12881
12882 DRM_DEBUG_KMS("%s\n", pll->name);
12883
12884 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12885
12886 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12887 "more active pll users than references: %i vs %i\n",
12888 pll->active, hweight32(pll->config.crtc_mask));
12889 I915_STATE_WARN(pll->active && !pll->on,
12890 "pll in active use but not on in sw tracking\n");
12891 I915_STATE_WARN(pll->on && !pll->active,
12892 "pll in on but not on in use in sw tracking\n");
12893 I915_STATE_WARN(pll->on != active,
12894 "pll on state mismatch (expected %i, found %i)\n",
12895 pll->on, active);
12896
12897 for_each_intel_crtc(dev, crtc) {
12898 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12899 enabled_crtcs++;
12900 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12901 active_crtcs++;
12902 }
12903 I915_STATE_WARN(pll->active != active_crtcs,
12904 "pll active crtcs mismatch (expected %i, found %i)\n",
12905 pll->active, active_crtcs);
12906 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12907 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12908 hweight32(pll->config.crtc_mask), enabled_crtcs);
12909
12910 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12911 sizeof(dpll_hw_state)),
12912 "pll hw state mismatch\n");
12913 }
12914 }
12915
12916 static void
12917 intel_modeset_check_state(struct drm_device *dev,
12918 struct drm_atomic_state *old_state)
12919 {
12920 check_wm_state(dev);
12921 check_connector_state(dev, old_state);
12922 check_encoder_state(dev);
12923 check_crtc_state(dev, old_state);
12924 check_shared_dpll_state(dev);
12925 }
12926
12927 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12928 int dotclock)
12929 {
12930 /*
12931 * FDI already provided one idea for the dotclock.
12932 * Yell if the encoder disagrees.
12933 */
12934 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12935 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12936 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12937 }
12938
12939 static void update_scanline_offset(struct intel_crtc *crtc)
12940 {
12941 struct drm_device *dev = crtc->base.dev;
12942
12943 /*
12944 * The scanline counter increments at the leading edge of hsync.
12945 *
12946 * On most platforms it starts counting from vtotal-1 on the
12947 * first active line. That means the scanline counter value is
12948 * always one less than what we would expect. Ie. just after
12949 * start of vblank, which also occurs at start of hsync (on the
12950 * last active line), the scanline counter will read vblank_start-1.
12951 *
12952 * On gen2 the scanline counter starts counting from 1 instead
12953 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12954 * to keep the value positive), instead of adding one.
12955 *
12956 * On HSW+ the behaviour of the scanline counter depends on the output
12957 * type. For DP ports it behaves like most other platforms, but on HDMI
12958 * there's an extra 1 line difference. So we need to add two instead of
12959 * one to the value.
12960 */
12961 if (IS_GEN2(dev)) {
12962 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
12963 int vtotal;
12964
12965 vtotal = adjusted_mode->crtc_vtotal;
12966 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
12967 vtotal /= 2;
12968
12969 crtc->scanline_offset = vtotal - 1;
12970 } else if (HAS_DDI(dev) &&
12971 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12972 crtc->scanline_offset = 2;
12973 } else
12974 crtc->scanline_offset = 1;
12975 }
12976
12977 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
12978 {
12979 struct drm_device *dev = state->dev;
12980 struct drm_i915_private *dev_priv = to_i915(dev);
12981 struct intel_shared_dpll_config *shared_dpll = NULL;
12982 struct intel_crtc *intel_crtc;
12983 struct intel_crtc_state *intel_crtc_state;
12984 struct drm_crtc *crtc;
12985 struct drm_crtc_state *crtc_state;
12986 int i;
12987
12988 if (!dev_priv->display.crtc_compute_clock)
12989 return;
12990
12991 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12992 int dpll;
12993
12994 intel_crtc = to_intel_crtc(crtc);
12995 intel_crtc_state = to_intel_crtc_state(crtc_state);
12996 dpll = intel_crtc_state->shared_dpll;
12997
12998 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
12999 continue;
13000
13001 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13002
13003 if (!shared_dpll)
13004 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13005
13006 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13007 }
13008 }
13009
13010 /*
13011 * This implements the workaround described in the "notes" section of the mode
13012 * set sequence documentation. When going from no pipes or single pipe to
13013 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13014 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13015 */
13016 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13017 {
13018 struct drm_crtc_state *crtc_state;
13019 struct intel_crtc *intel_crtc;
13020 struct drm_crtc *crtc;
13021 struct intel_crtc_state *first_crtc_state = NULL;
13022 struct intel_crtc_state *other_crtc_state = NULL;
13023 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13024 int i;
13025
13026 /* look at all crtc's that are going to be enabled in during modeset */
13027 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13028 intel_crtc = to_intel_crtc(crtc);
13029
13030 if (!crtc_state->active || !needs_modeset(crtc_state))
13031 continue;
13032
13033 if (first_crtc_state) {
13034 other_crtc_state = to_intel_crtc_state(crtc_state);
13035 break;
13036 } else {
13037 first_crtc_state = to_intel_crtc_state(crtc_state);
13038 first_pipe = intel_crtc->pipe;
13039 }
13040 }
13041
13042 /* No workaround needed? */
13043 if (!first_crtc_state)
13044 return 0;
13045
13046 /* w/a possibly needed, check how many crtc's are already enabled. */
13047 for_each_intel_crtc(state->dev, intel_crtc) {
13048 struct intel_crtc_state *pipe_config;
13049
13050 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13051 if (IS_ERR(pipe_config))
13052 return PTR_ERR(pipe_config);
13053
13054 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13055
13056 if (!pipe_config->base.active ||
13057 needs_modeset(&pipe_config->base))
13058 continue;
13059
13060 /* 2 or more enabled crtcs means no need for w/a */
13061 if (enabled_pipe != INVALID_PIPE)
13062 return 0;
13063
13064 enabled_pipe = intel_crtc->pipe;
13065 }
13066
13067 if (enabled_pipe != INVALID_PIPE)
13068 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13069 else if (other_crtc_state)
13070 other_crtc_state->hsw_workaround_pipe = first_pipe;
13071
13072 return 0;
13073 }
13074
13075 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13076 {
13077 struct drm_crtc *crtc;
13078 struct drm_crtc_state *crtc_state;
13079 int ret = 0;
13080
13081 /* add all active pipes to the state */
13082 for_each_crtc(state->dev, crtc) {
13083 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13084 if (IS_ERR(crtc_state))
13085 return PTR_ERR(crtc_state);
13086
13087 if (!crtc_state->active || needs_modeset(crtc_state))
13088 continue;
13089
13090 crtc_state->mode_changed = true;
13091
13092 ret = drm_atomic_add_affected_connectors(state, crtc);
13093 if (ret)
13094 break;
13095
13096 ret = drm_atomic_add_affected_planes(state, crtc);
13097 if (ret)
13098 break;
13099 }
13100
13101 return ret;
13102 }
13103
13104 static int intel_modeset_checks(struct drm_atomic_state *state)
13105 {
13106 struct drm_device *dev = state->dev;
13107 struct drm_i915_private *dev_priv = dev->dev_private;
13108 int ret;
13109
13110 if (!check_digital_port_conflicts(state)) {
13111 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13112 return -EINVAL;
13113 }
13114
13115 /*
13116 * See if the config requires any additional preparation, e.g.
13117 * to adjust global state with pipes off. We need to do this
13118 * here so we can get the modeset_pipe updated config for the new
13119 * mode set on this crtc. For other crtcs we need to use the
13120 * adjusted_mode bits in the crtc directly.
13121 */
13122 if (dev_priv->display.modeset_calc_cdclk) {
13123 unsigned int cdclk;
13124
13125 ret = dev_priv->display.modeset_calc_cdclk(state);
13126
13127 cdclk = to_intel_atomic_state(state)->cdclk;
13128 if (!ret && cdclk != dev_priv->cdclk_freq)
13129 ret = intel_modeset_all_pipes(state);
13130
13131 if (ret < 0)
13132 return ret;
13133 } else
13134 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
13135
13136 intel_modeset_clear_plls(state);
13137
13138 if (IS_HASWELL(dev))
13139 return haswell_mode_set_planes_workaround(state);
13140
13141 return 0;
13142 }
13143
13144 /*
13145 * Handle calculation of various watermark data at the end of the atomic check
13146 * phase. The code here should be run after the per-crtc and per-plane 'check'
13147 * handlers to ensure that all derived state has been updated.
13148 */
13149 static void calc_watermark_data(struct drm_atomic_state *state)
13150 {
13151 struct drm_device *dev = state->dev;
13152 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13153 struct drm_crtc *crtc;
13154 struct drm_crtc_state *cstate;
13155 struct drm_plane *plane;
13156 struct drm_plane_state *pstate;
13157
13158 /*
13159 * Calculate watermark configuration details now that derived
13160 * plane/crtc state is all properly updated.
13161 */
13162 drm_for_each_crtc(crtc, dev) {
13163 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13164 crtc->state;
13165
13166 if (cstate->active)
13167 intel_state->wm_config.num_pipes_active++;
13168 }
13169 drm_for_each_legacy_plane(plane, dev) {
13170 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13171 plane->state;
13172
13173 if (!to_intel_plane_state(pstate)->visible)
13174 continue;
13175
13176 intel_state->wm_config.sprites_enabled = true;
13177 if (pstate->crtc_w != pstate->src_w >> 16 ||
13178 pstate->crtc_h != pstate->src_h >> 16)
13179 intel_state->wm_config.sprites_scaled = true;
13180 }
13181 }
13182
13183 /**
13184 * intel_atomic_check - validate state object
13185 * @dev: drm device
13186 * @state: state to validate
13187 */
13188 static int intel_atomic_check(struct drm_device *dev,
13189 struct drm_atomic_state *state)
13190 {
13191 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13192 struct drm_crtc *crtc;
13193 struct drm_crtc_state *crtc_state;
13194 int ret, i;
13195 bool any_ms = false;
13196
13197 ret = drm_atomic_helper_check_modeset(dev, state);
13198 if (ret)
13199 return ret;
13200
13201 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13202 struct intel_crtc_state *pipe_config =
13203 to_intel_crtc_state(crtc_state);
13204
13205 memset(&to_intel_crtc(crtc)->atomic, 0,
13206 sizeof(struct intel_crtc_atomic_commit));
13207
13208 /* Catch I915_MODE_FLAG_INHERITED */
13209 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13210 crtc_state->mode_changed = true;
13211
13212 if (!crtc_state->enable) {
13213 if (needs_modeset(crtc_state))
13214 any_ms = true;
13215 continue;
13216 }
13217
13218 if (!needs_modeset(crtc_state))
13219 continue;
13220
13221 /* FIXME: For only active_changed we shouldn't need to do any
13222 * state recomputation at all. */
13223
13224 ret = drm_atomic_add_affected_connectors(state, crtc);
13225 if (ret)
13226 return ret;
13227
13228 ret = intel_modeset_pipe_config(crtc, pipe_config);
13229 if (ret)
13230 return ret;
13231
13232 if (i915.fastboot &&
13233 intel_pipe_config_compare(state->dev,
13234 to_intel_crtc_state(crtc->state),
13235 pipe_config, true)) {
13236 crtc_state->mode_changed = false;
13237 to_intel_crtc_state(crtc_state)->update_pipe = true;
13238 }
13239
13240 if (needs_modeset(crtc_state)) {
13241 any_ms = true;
13242
13243 ret = drm_atomic_add_affected_planes(state, crtc);
13244 if (ret)
13245 return ret;
13246 }
13247
13248 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13249 needs_modeset(crtc_state) ?
13250 "[modeset]" : "[fastset]");
13251 }
13252
13253 if (any_ms) {
13254 ret = intel_modeset_checks(state);
13255
13256 if (ret)
13257 return ret;
13258 } else
13259 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13260
13261 ret = drm_atomic_helper_check_planes(state->dev, state);
13262 if (ret)
13263 return ret;
13264
13265 calc_watermark_data(state);
13266
13267 return 0;
13268 }
13269
13270 static int intel_atomic_prepare_commit(struct drm_device *dev,
13271 struct drm_atomic_state *state,
13272 bool async)
13273 {
13274 struct drm_i915_private *dev_priv = dev->dev_private;
13275 struct drm_plane_state *plane_state;
13276 struct drm_crtc_state *crtc_state;
13277 struct drm_plane *plane;
13278 struct drm_crtc *crtc;
13279 int i, ret;
13280
13281 if (async) {
13282 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13283 return -EINVAL;
13284 }
13285
13286 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13287 ret = intel_crtc_wait_for_pending_flips(crtc);
13288 if (ret)
13289 return ret;
13290
13291 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13292 flush_workqueue(dev_priv->wq);
13293 }
13294
13295 ret = mutex_lock_interruptible(&dev->struct_mutex);
13296 if (ret)
13297 return ret;
13298
13299 ret = drm_atomic_helper_prepare_planes(dev, state);
13300 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13301 u32 reset_counter;
13302
13303 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13304 mutex_unlock(&dev->struct_mutex);
13305
13306 for_each_plane_in_state(state, plane, plane_state, i) {
13307 struct intel_plane_state *intel_plane_state =
13308 to_intel_plane_state(plane_state);
13309
13310 if (!intel_plane_state->wait_req)
13311 continue;
13312
13313 ret = __i915_wait_request(intel_plane_state->wait_req,
13314 reset_counter, true,
13315 NULL, NULL);
13316
13317 /* Swallow -EIO errors to allow updates during hw lockup. */
13318 if (ret == -EIO)
13319 ret = 0;
13320
13321 if (ret)
13322 break;
13323 }
13324
13325 if (!ret)
13326 return 0;
13327
13328 mutex_lock(&dev->struct_mutex);
13329 drm_atomic_helper_cleanup_planes(dev, state);
13330 }
13331
13332 mutex_unlock(&dev->struct_mutex);
13333 return ret;
13334 }
13335
13336 /**
13337 * intel_atomic_commit - commit validated state object
13338 * @dev: DRM device
13339 * @state: the top-level driver state object
13340 * @async: asynchronous commit
13341 *
13342 * This function commits a top-level state object that has been validated
13343 * with drm_atomic_helper_check().
13344 *
13345 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13346 * we can only handle plane-related operations and do not yet support
13347 * asynchronous commit.
13348 *
13349 * RETURNS
13350 * Zero for success or -errno.
13351 */
13352 static int intel_atomic_commit(struct drm_device *dev,
13353 struct drm_atomic_state *state,
13354 bool async)
13355 {
13356 struct drm_i915_private *dev_priv = dev->dev_private;
13357 struct drm_crtc_state *crtc_state;
13358 struct drm_crtc *crtc;
13359 int ret = 0;
13360 int i;
13361 bool any_ms = false;
13362
13363 ret = intel_atomic_prepare_commit(dev, state, async);
13364 if (ret) {
13365 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13366 return ret;
13367 }
13368
13369 drm_atomic_helper_swap_state(dev, state);
13370 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13371
13372 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13374
13375 if (!needs_modeset(crtc->state))
13376 continue;
13377
13378 any_ms = true;
13379 intel_pre_plane_update(intel_crtc);
13380
13381 if (crtc_state->active) {
13382 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13383 dev_priv->display.crtc_disable(crtc);
13384 intel_crtc->active = false;
13385 intel_disable_shared_dpll(intel_crtc);
13386 }
13387 }
13388
13389 /* Only after disabling all output pipelines that will be changed can we
13390 * update the the output configuration. */
13391 intel_modeset_update_crtc_state(state);
13392
13393 if (any_ms) {
13394 intel_shared_dpll_commit(state);
13395
13396 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13397 modeset_update_crtc_power_domains(state);
13398 }
13399
13400 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13401 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13403 bool modeset = needs_modeset(crtc->state);
13404 bool update_pipe = !modeset &&
13405 to_intel_crtc_state(crtc->state)->update_pipe;
13406 unsigned long put_domains = 0;
13407
13408 if (modeset)
13409 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13410
13411 if (modeset && crtc->state->active) {
13412 update_scanline_offset(to_intel_crtc(crtc));
13413 dev_priv->display.crtc_enable(crtc);
13414 }
13415
13416 if (update_pipe) {
13417 put_domains = modeset_get_crtc_power_domains(crtc);
13418
13419 /* make sure intel_modeset_check_state runs */
13420 any_ms = true;
13421 }
13422
13423 if (!modeset)
13424 intel_pre_plane_update(intel_crtc);
13425
13426 if (crtc->state->active &&
13427 (crtc->state->planes_changed || update_pipe))
13428 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13429
13430 if (put_domains)
13431 modeset_put_power_domains(dev_priv, put_domains);
13432
13433 intel_post_plane_update(intel_crtc);
13434
13435 if (modeset)
13436 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13437 }
13438
13439 /* FIXME: add subpixel order */
13440
13441 drm_atomic_helper_wait_for_vblanks(dev, state);
13442
13443 mutex_lock(&dev->struct_mutex);
13444 drm_atomic_helper_cleanup_planes(dev, state);
13445 mutex_unlock(&dev->struct_mutex);
13446
13447 if (any_ms)
13448 intel_modeset_check_state(dev, state);
13449
13450 drm_atomic_state_free(state);
13451
13452 return 0;
13453 }
13454
13455 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13456 {
13457 struct drm_device *dev = crtc->dev;
13458 struct drm_atomic_state *state;
13459 struct drm_crtc_state *crtc_state;
13460 int ret;
13461
13462 state = drm_atomic_state_alloc(dev);
13463 if (!state) {
13464 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13465 crtc->base.id);
13466 return;
13467 }
13468
13469 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13470
13471 retry:
13472 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13473 ret = PTR_ERR_OR_ZERO(crtc_state);
13474 if (!ret) {
13475 if (!crtc_state->active)
13476 goto out;
13477
13478 crtc_state->mode_changed = true;
13479 ret = drm_atomic_commit(state);
13480 }
13481
13482 if (ret == -EDEADLK) {
13483 drm_atomic_state_clear(state);
13484 drm_modeset_backoff(state->acquire_ctx);
13485 goto retry;
13486 }
13487
13488 if (ret)
13489 out:
13490 drm_atomic_state_free(state);
13491 }
13492
13493 #undef for_each_intel_crtc_masked
13494
13495 static const struct drm_crtc_funcs intel_crtc_funcs = {
13496 .gamma_set = intel_crtc_gamma_set,
13497 .set_config = drm_atomic_helper_set_config,
13498 .destroy = intel_crtc_destroy,
13499 .page_flip = intel_crtc_page_flip,
13500 .atomic_duplicate_state = intel_crtc_duplicate_state,
13501 .atomic_destroy_state = intel_crtc_destroy_state,
13502 };
13503
13504 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13505 struct intel_shared_dpll *pll,
13506 struct intel_dpll_hw_state *hw_state)
13507 {
13508 uint32_t val;
13509
13510 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13511 return false;
13512
13513 val = I915_READ(PCH_DPLL(pll->id));
13514 hw_state->dpll = val;
13515 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13516 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13517
13518 return val & DPLL_VCO_ENABLE;
13519 }
13520
13521 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13522 struct intel_shared_dpll *pll)
13523 {
13524 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13525 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13526 }
13527
13528 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13529 struct intel_shared_dpll *pll)
13530 {
13531 /* PCH refclock must be enabled first */
13532 ibx_assert_pch_refclk_enabled(dev_priv);
13533
13534 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13535
13536 /* Wait for the clocks to stabilize. */
13537 POSTING_READ(PCH_DPLL(pll->id));
13538 udelay(150);
13539
13540 /* The pixel multiplier can only be updated once the
13541 * DPLL is enabled and the clocks are stable.
13542 *
13543 * So write it again.
13544 */
13545 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13546 POSTING_READ(PCH_DPLL(pll->id));
13547 udelay(200);
13548 }
13549
13550 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13551 struct intel_shared_dpll *pll)
13552 {
13553 struct drm_device *dev = dev_priv->dev;
13554 struct intel_crtc *crtc;
13555
13556 /* Make sure no transcoder isn't still depending on us. */
13557 for_each_intel_crtc(dev, crtc) {
13558 if (intel_crtc_to_shared_dpll(crtc) == pll)
13559 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13560 }
13561
13562 I915_WRITE(PCH_DPLL(pll->id), 0);
13563 POSTING_READ(PCH_DPLL(pll->id));
13564 udelay(200);
13565 }
13566
13567 static char *ibx_pch_dpll_names[] = {
13568 "PCH DPLL A",
13569 "PCH DPLL B",
13570 };
13571
13572 static void ibx_pch_dpll_init(struct drm_device *dev)
13573 {
13574 struct drm_i915_private *dev_priv = dev->dev_private;
13575 int i;
13576
13577 dev_priv->num_shared_dpll = 2;
13578
13579 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13580 dev_priv->shared_dplls[i].id = i;
13581 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13582 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13583 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13584 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13585 dev_priv->shared_dplls[i].get_hw_state =
13586 ibx_pch_dpll_get_hw_state;
13587 }
13588 }
13589
13590 static void intel_shared_dpll_init(struct drm_device *dev)
13591 {
13592 struct drm_i915_private *dev_priv = dev->dev_private;
13593
13594 if (HAS_DDI(dev))
13595 intel_ddi_pll_init(dev);
13596 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13597 ibx_pch_dpll_init(dev);
13598 else
13599 dev_priv->num_shared_dpll = 0;
13600
13601 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13602 }
13603
13604 /**
13605 * intel_prepare_plane_fb - Prepare fb for usage on plane
13606 * @plane: drm plane to prepare for
13607 * @fb: framebuffer to prepare for presentation
13608 *
13609 * Prepares a framebuffer for usage on a display plane. Generally this
13610 * involves pinning the underlying object and updating the frontbuffer tracking
13611 * bits. Some older platforms need special physical address handling for
13612 * cursor planes.
13613 *
13614 * Must be called with struct_mutex held.
13615 *
13616 * Returns 0 on success, negative error code on failure.
13617 */
13618 int
13619 intel_prepare_plane_fb(struct drm_plane *plane,
13620 const struct drm_plane_state *new_state)
13621 {
13622 struct drm_device *dev = plane->dev;
13623 struct drm_framebuffer *fb = new_state->fb;
13624 struct intel_plane *intel_plane = to_intel_plane(plane);
13625 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13626 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13627 int ret = 0;
13628
13629 if (!obj && !old_obj)
13630 return 0;
13631
13632 if (old_obj) {
13633 struct drm_crtc_state *crtc_state =
13634 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13635
13636 /* Big Hammer, we also need to ensure that any pending
13637 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13638 * current scanout is retired before unpinning the old
13639 * framebuffer. Note that we rely on userspace rendering
13640 * into the buffer attached to the pipe they are waiting
13641 * on. If not, userspace generates a GPU hang with IPEHR
13642 * point to the MI_WAIT_FOR_EVENT.
13643 *
13644 * This should only fail upon a hung GPU, in which case we
13645 * can safely continue.
13646 */
13647 if (needs_modeset(crtc_state))
13648 ret = i915_gem_object_wait_rendering(old_obj, true);
13649
13650 /* Swallow -EIO errors to allow updates during hw lockup. */
13651 if (ret && ret != -EIO)
13652 return ret;
13653 }
13654
13655 if (!obj) {
13656 ret = 0;
13657 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13658 INTEL_INFO(dev)->cursor_needs_physical) {
13659 int align = IS_I830(dev) ? 16 * 1024 : 256;
13660 ret = i915_gem_object_attach_phys(obj, align);
13661 if (ret)
13662 DRM_DEBUG_KMS("failed to attach phys object\n");
13663 } else {
13664 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13665 }
13666
13667 if (ret == 0) {
13668 if (obj) {
13669 struct intel_plane_state *plane_state =
13670 to_intel_plane_state(new_state);
13671
13672 i915_gem_request_assign(&plane_state->wait_req,
13673 obj->last_write_req);
13674 }
13675
13676 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13677 }
13678
13679 return ret;
13680 }
13681
13682 /**
13683 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13684 * @plane: drm plane to clean up for
13685 * @fb: old framebuffer that was on plane
13686 *
13687 * Cleans up a framebuffer that has just been removed from a plane.
13688 *
13689 * Must be called with struct_mutex held.
13690 */
13691 void
13692 intel_cleanup_plane_fb(struct drm_plane *plane,
13693 const struct drm_plane_state *old_state)
13694 {
13695 struct drm_device *dev = plane->dev;
13696 struct intel_plane *intel_plane = to_intel_plane(plane);
13697 struct intel_plane_state *old_intel_state;
13698 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13699 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13700
13701 old_intel_state = to_intel_plane_state(old_state);
13702
13703 if (!obj && !old_obj)
13704 return;
13705
13706 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13707 !INTEL_INFO(dev)->cursor_needs_physical))
13708 intel_unpin_fb_obj(old_state->fb, old_state);
13709
13710 /* prepare_fb aborted? */
13711 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13712 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13713 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13714
13715 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
13716
13717 }
13718
13719 int
13720 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13721 {
13722 int max_scale;
13723 struct drm_device *dev;
13724 struct drm_i915_private *dev_priv;
13725 int crtc_clock, cdclk;
13726
13727 if (!intel_crtc || !crtc_state)
13728 return DRM_PLANE_HELPER_NO_SCALING;
13729
13730 dev = intel_crtc->base.dev;
13731 dev_priv = dev->dev_private;
13732 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13733 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
13734
13735 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
13736 return DRM_PLANE_HELPER_NO_SCALING;
13737
13738 /*
13739 * skl max scale is lower of:
13740 * close to 3 but not 3, -1 is for that purpose
13741 * or
13742 * cdclk/crtc_clock
13743 */
13744 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13745
13746 return max_scale;
13747 }
13748
13749 static int
13750 intel_check_primary_plane(struct drm_plane *plane,
13751 struct intel_crtc_state *crtc_state,
13752 struct intel_plane_state *state)
13753 {
13754 struct drm_crtc *crtc = state->base.crtc;
13755 struct drm_framebuffer *fb = state->base.fb;
13756 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13757 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13758 bool can_position = false;
13759
13760 /* use scaler when colorkey is not required */
13761 if (INTEL_INFO(plane->dev)->gen >= 9 &&
13762 state->ckey.flags == I915_SET_COLORKEY_NONE) {
13763 min_scale = 1;
13764 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
13765 can_position = true;
13766 }
13767
13768 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13769 &state->dst, &state->clip,
13770 min_scale, max_scale,
13771 can_position, true,
13772 &state->visible);
13773 }
13774
13775 static void
13776 intel_commit_primary_plane(struct drm_plane *plane,
13777 struct intel_plane_state *state)
13778 {
13779 struct drm_crtc *crtc = state->base.crtc;
13780 struct drm_framebuffer *fb = state->base.fb;
13781 struct drm_device *dev = plane->dev;
13782 struct drm_i915_private *dev_priv = dev->dev_private;
13783
13784 crtc = crtc ? crtc : plane->crtc;
13785
13786 dev_priv->display.update_primary_plane(crtc, fb,
13787 state->src.x1 >> 16,
13788 state->src.y1 >> 16);
13789 }
13790
13791 static void
13792 intel_disable_primary_plane(struct drm_plane *plane,
13793 struct drm_crtc *crtc)
13794 {
13795 struct drm_device *dev = plane->dev;
13796 struct drm_i915_private *dev_priv = dev->dev_private;
13797
13798 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13799 }
13800
13801 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
13802 struct drm_crtc_state *old_crtc_state)
13803 {
13804 struct drm_device *dev = crtc->dev;
13805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13806 struct intel_crtc_state *old_intel_state =
13807 to_intel_crtc_state(old_crtc_state);
13808 bool modeset = needs_modeset(crtc->state);
13809
13810 if (intel_crtc->atomic.update_wm_pre)
13811 intel_update_watermarks(crtc);
13812
13813 /* Perform vblank evasion around commit operation */
13814 intel_pipe_update_start(intel_crtc);
13815
13816 if (modeset)
13817 return;
13818
13819 if (to_intel_crtc_state(crtc->state)->update_pipe)
13820 intel_update_pipe_config(intel_crtc, old_intel_state);
13821 else if (INTEL_INFO(dev)->gen >= 9)
13822 skl_detach_scalers(intel_crtc);
13823 }
13824
13825 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
13826 struct drm_crtc_state *old_crtc_state)
13827 {
13828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13829
13830 intel_pipe_update_end(intel_crtc);
13831 }
13832
13833 /**
13834 * intel_plane_destroy - destroy a plane
13835 * @plane: plane to destroy
13836 *
13837 * Common destruction function for all types of planes (primary, cursor,
13838 * sprite).
13839 */
13840 void intel_plane_destroy(struct drm_plane *plane)
13841 {
13842 struct intel_plane *intel_plane = to_intel_plane(plane);
13843 drm_plane_cleanup(plane);
13844 kfree(intel_plane);
13845 }
13846
13847 const struct drm_plane_funcs intel_plane_funcs = {
13848 .update_plane = drm_atomic_helper_update_plane,
13849 .disable_plane = drm_atomic_helper_disable_plane,
13850 .destroy = intel_plane_destroy,
13851 .set_property = drm_atomic_helper_plane_set_property,
13852 .atomic_get_property = intel_plane_atomic_get_property,
13853 .atomic_set_property = intel_plane_atomic_set_property,
13854 .atomic_duplicate_state = intel_plane_duplicate_state,
13855 .atomic_destroy_state = intel_plane_destroy_state,
13856
13857 };
13858
13859 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13860 int pipe)
13861 {
13862 struct intel_plane *primary;
13863 struct intel_plane_state *state;
13864 const uint32_t *intel_primary_formats;
13865 unsigned int num_formats;
13866
13867 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13868 if (primary == NULL)
13869 return NULL;
13870
13871 state = intel_create_plane_state(&primary->base);
13872 if (!state) {
13873 kfree(primary);
13874 return NULL;
13875 }
13876 primary->base.state = &state->base;
13877
13878 primary->can_scale = false;
13879 primary->max_downscale = 1;
13880 if (INTEL_INFO(dev)->gen >= 9) {
13881 primary->can_scale = true;
13882 state->scaler_id = -1;
13883 }
13884 primary->pipe = pipe;
13885 primary->plane = pipe;
13886 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
13887 primary->check_plane = intel_check_primary_plane;
13888 primary->commit_plane = intel_commit_primary_plane;
13889 primary->disable_plane = intel_disable_primary_plane;
13890 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13891 primary->plane = !pipe;
13892
13893 if (INTEL_INFO(dev)->gen >= 9) {
13894 intel_primary_formats = skl_primary_formats;
13895 num_formats = ARRAY_SIZE(skl_primary_formats);
13896 } else if (INTEL_INFO(dev)->gen >= 4) {
13897 intel_primary_formats = i965_primary_formats;
13898 num_formats = ARRAY_SIZE(i965_primary_formats);
13899 } else {
13900 intel_primary_formats = i8xx_primary_formats;
13901 num_formats = ARRAY_SIZE(i8xx_primary_formats);
13902 }
13903
13904 drm_universal_plane_init(dev, &primary->base, 0,
13905 &intel_plane_funcs,
13906 intel_primary_formats, num_formats,
13907 DRM_PLANE_TYPE_PRIMARY, NULL);
13908
13909 if (INTEL_INFO(dev)->gen >= 4)
13910 intel_create_rotation_property(dev, primary);
13911
13912 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13913
13914 return &primary->base;
13915 }
13916
13917 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13918 {
13919 if (!dev->mode_config.rotation_property) {
13920 unsigned long flags = BIT(DRM_ROTATE_0) |
13921 BIT(DRM_ROTATE_180);
13922
13923 if (INTEL_INFO(dev)->gen >= 9)
13924 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13925
13926 dev->mode_config.rotation_property =
13927 drm_mode_create_rotation_property(dev, flags);
13928 }
13929 if (dev->mode_config.rotation_property)
13930 drm_object_attach_property(&plane->base.base,
13931 dev->mode_config.rotation_property,
13932 plane->base.state->rotation);
13933 }
13934
13935 static int
13936 intel_check_cursor_plane(struct drm_plane *plane,
13937 struct intel_crtc_state *crtc_state,
13938 struct intel_plane_state *state)
13939 {
13940 struct drm_crtc *crtc = crtc_state->base.crtc;
13941 struct drm_framebuffer *fb = state->base.fb;
13942 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13943 unsigned stride;
13944 int ret;
13945
13946 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13947 &state->dst, &state->clip,
13948 DRM_PLANE_HELPER_NO_SCALING,
13949 DRM_PLANE_HELPER_NO_SCALING,
13950 true, true, &state->visible);
13951 if (ret)
13952 return ret;
13953
13954 /* if we want to turn off the cursor ignore width and height */
13955 if (!obj)
13956 return 0;
13957
13958 /* Check for which cursor types we support */
13959 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
13960 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13961 state->base.crtc_w, state->base.crtc_h);
13962 return -EINVAL;
13963 }
13964
13965 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13966 if (obj->base.size < stride * state->base.crtc_h) {
13967 DRM_DEBUG_KMS("buffer is too small\n");
13968 return -ENOMEM;
13969 }
13970
13971 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13972 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13973 return -EINVAL;
13974 }
13975
13976 return 0;
13977 }
13978
13979 static void
13980 intel_disable_cursor_plane(struct drm_plane *plane,
13981 struct drm_crtc *crtc)
13982 {
13983 intel_crtc_update_cursor(crtc, false);
13984 }
13985
13986 static void
13987 intel_commit_cursor_plane(struct drm_plane *plane,
13988 struct intel_plane_state *state)
13989 {
13990 struct drm_crtc *crtc = state->base.crtc;
13991 struct drm_device *dev = plane->dev;
13992 struct intel_crtc *intel_crtc;
13993 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13994 uint32_t addr;
13995
13996 crtc = crtc ? crtc : plane->crtc;
13997 intel_crtc = to_intel_crtc(crtc);
13998
13999 if (intel_crtc->cursor_bo == obj)
14000 goto update;
14001
14002 if (!obj)
14003 addr = 0;
14004 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14005 addr = i915_gem_obj_ggtt_offset(obj);
14006 else
14007 addr = obj->phys_handle->busaddr;
14008
14009 intel_crtc->cursor_addr = addr;
14010 intel_crtc->cursor_bo = obj;
14011
14012 update:
14013 intel_crtc_update_cursor(crtc, state->visible);
14014 }
14015
14016 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14017 int pipe)
14018 {
14019 struct intel_plane *cursor;
14020 struct intel_plane_state *state;
14021
14022 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14023 if (cursor == NULL)
14024 return NULL;
14025
14026 state = intel_create_plane_state(&cursor->base);
14027 if (!state) {
14028 kfree(cursor);
14029 return NULL;
14030 }
14031 cursor->base.state = &state->base;
14032
14033 cursor->can_scale = false;
14034 cursor->max_downscale = 1;
14035 cursor->pipe = pipe;
14036 cursor->plane = pipe;
14037 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14038 cursor->check_plane = intel_check_cursor_plane;
14039 cursor->commit_plane = intel_commit_cursor_plane;
14040 cursor->disable_plane = intel_disable_cursor_plane;
14041
14042 drm_universal_plane_init(dev, &cursor->base, 0,
14043 &intel_plane_funcs,
14044 intel_cursor_formats,
14045 ARRAY_SIZE(intel_cursor_formats),
14046 DRM_PLANE_TYPE_CURSOR, NULL);
14047
14048 if (INTEL_INFO(dev)->gen >= 4) {
14049 if (!dev->mode_config.rotation_property)
14050 dev->mode_config.rotation_property =
14051 drm_mode_create_rotation_property(dev,
14052 BIT(DRM_ROTATE_0) |
14053 BIT(DRM_ROTATE_180));
14054 if (dev->mode_config.rotation_property)
14055 drm_object_attach_property(&cursor->base.base,
14056 dev->mode_config.rotation_property,
14057 state->base.rotation);
14058 }
14059
14060 if (INTEL_INFO(dev)->gen >=9)
14061 state->scaler_id = -1;
14062
14063 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14064
14065 return &cursor->base;
14066 }
14067
14068 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14069 struct intel_crtc_state *crtc_state)
14070 {
14071 int i;
14072 struct intel_scaler *intel_scaler;
14073 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14074
14075 for (i = 0; i < intel_crtc->num_scalers; i++) {
14076 intel_scaler = &scaler_state->scalers[i];
14077 intel_scaler->in_use = 0;
14078 intel_scaler->mode = PS_SCALER_MODE_DYN;
14079 }
14080
14081 scaler_state->scaler_id = -1;
14082 }
14083
14084 static void intel_crtc_init(struct drm_device *dev, int pipe)
14085 {
14086 struct drm_i915_private *dev_priv = dev->dev_private;
14087 struct intel_crtc *intel_crtc;
14088 struct intel_crtc_state *crtc_state = NULL;
14089 struct drm_plane *primary = NULL;
14090 struct drm_plane *cursor = NULL;
14091 int i, ret;
14092
14093 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14094 if (intel_crtc == NULL)
14095 return;
14096
14097 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14098 if (!crtc_state)
14099 goto fail;
14100 intel_crtc->config = crtc_state;
14101 intel_crtc->base.state = &crtc_state->base;
14102 crtc_state->base.crtc = &intel_crtc->base;
14103
14104 /* initialize shared scalers */
14105 if (INTEL_INFO(dev)->gen >= 9) {
14106 if (pipe == PIPE_C)
14107 intel_crtc->num_scalers = 1;
14108 else
14109 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14110
14111 skl_init_scalers(dev, intel_crtc, crtc_state);
14112 }
14113
14114 primary = intel_primary_plane_create(dev, pipe);
14115 if (!primary)
14116 goto fail;
14117
14118 cursor = intel_cursor_plane_create(dev, pipe);
14119 if (!cursor)
14120 goto fail;
14121
14122 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14123 cursor, &intel_crtc_funcs, NULL);
14124 if (ret)
14125 goto fail;
14126
14127 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14128 for (i = 0; i < 256; i++) {
14129 intel_crtc->lut_r[i] = i;
14130 intel_crtc->lut_g[i] = i;
14131 intel_crtc->lut_b[i] = i;
14132 }
14133
14134 /*
14135 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14136 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14137 */
14138 intel_crtc->pipe = pipe;
14139 intel_crtc->plane = pipe;
14140 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14141 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14142 intel_crtc->plane = !pipe;
14143 }
14144
14145 intel_crtc->cursor_base = ~0;
14146 intel_crtc->cursor_cntl = ~0;
14147 intel_crtc->cursor_size = ~0;
14148
14149 intel_crtc->wm.cxsr_allowed = true;
14150
14151 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14152 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14153 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14154 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14155
14156 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14157
14158 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14159 return;
14160
14161 fail:
14162 if (primary)
14163 drm_plane_cleanup(primary);
14164 if (cursor)
14165 drm_plane_cleanup(cursor);
14166 kfree(crtc_state);
14167 kfree(intel_crtc);
14168 }
14169
14170 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14171 {
14172 struct drm_encoder *encoder = connector->base.encoder;
14173 struct drm_device *dev = connector->base.dev;
14174
14175 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14176
14177 if (!encoder || WARN_ON(!encoder->crtc))
14178 return INVALID_PIPE;
14179
14180 return to_intel_crtc(encoder->crtc)->pipe;
14181 }
14182
14183 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14184 struct drm_file *file)
14185 {
14186 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14187 struct drm_crtc *drmmode_crtc;
14188 struct intel_crtc *crtc;
14189
14190 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14191
14192 if (!drmmode_crtc) {
14193 DRM_ERROR("no such CRTC id\n");
14194 return -ENOENT;
14195 }
14196
14197 crtc = to_intel_crtc(drmmode_crtc);
14198 pipe_from_crtc_id->pipe = crtc->pipe;
14199
14200 return 0;
14201 }
14202
14203 static int intel_encoder_clones(struct intel_encoder *encoder)
14204 {
14205 struct drm_device *dev = encoder->base.dev;
14206 struct intel_encoder *source_encoder;
14207 int index_mask = 0;
14208 int entry = 0;
14209
14210 for_each_intel_encoder(dev, source_encoder) {
14211 if (encoders_cloneable(encoder, source_encoder))
14212 index_mask |= (1 << entry);
14213
14214 entry++;
14215 }
14216
14217 return index_mask;
14218 }
14219
14220 static bool has_edp_a(struct drm_device *dev)
14221 {
14222 struct drm_i915_private *dev_priv = dev->dev_private;
14223
14224 if (!IS_MOBILE(dev))
14225 return false;
14226
14227 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14228 return false;
14229
14230 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14231 return false;
14232
14233 return true;
14234 }
14235
14236 static bool intel_crt_present(struct drm_device *dev)
14237 {
14238 struct drm_i915_private *dev_priv = dev->dev_private;
14239
14240 if (INTEL_INFO(dev)->gen >= 9)
14241 return false;
14242
14243 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14244 return false;
14245
14246 if (IS_CHERRYVIEW(dev))
14247 return false;
14248
14249 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14250 return false;
14251
14252 return true;
14253 }
14254
14255 static void intel_setup_outputs(struct drm_device *dev)
14256 {
14257 struct drm_i915_private *dev_priv = dev->dev_private;
14258 struct intel_encoder *encoder;
14259 bool dpd_is_edp = false;
14260
14261 intel_lvds_init(dev);
14262
14263 if (intel_crt_present(dev))
14264 intel_crt_init(dev);
14265
14266 if (IS_BROXTON(dev)) {
14267 /*
14268 * FIXME: Broxton doesn't support port detection via the
14269 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14270 * detect the ports.
14271 */
14272 intel_ddi_init(dev, PORT_A);
14273 intel_ddi_init(dev, PORT_B);
14274 intel_ddi_init(dev, PORT_C);
14275 } else if (HAS_DDI(dev)) {
14276 int found;
14277
14278 /*
14279 * Haswell uses DDI functions to detect digital outputs.
14280 * On SKL pre-D0 the strap isn't connected, so we assume
14281 * it's there.
14282 */
14283 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14284 /* WaIgnoreDDIAStrap: skl */
14285 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14286 intel_ddi_init(dev, PORT_A);
14287
14288 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14289 * register */
14290 found = I915_READ(SFUSE_STRAP);
14291
14292 if (found & SFUSE_STRAP_DDIB_DETECTED)
14293 intel_ddi_init(dev, PORT_B);
14294 if (found & SFUSE_STRAP_DDIC_DETECTED)
14295 intel_ddi_init(dev, PORT_C);
14296 if (found & SFUSE_STRAP_DDID_DETECTED)
14297 intel_ddi_init(dev, PORT_D);
14298 /*
14299 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14300 */
14301 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14302 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14303 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14304 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14305 intel_ddi_init(dev, PORT_E);
14306
14307 } else if (HAS_PCH_SPLIT(dev)) {
14308 int found;
14309 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14310
14311 if (has_edp_a(dev))
14312 intel_dp_init(dev, DP_A, PORT_A);
14313
14314 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14315 /* PCH SDVOB multiplex with HDMIB */
14316 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14317 if (!found)
14318 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14319 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14320 intel_dp_init(dev, PCH_DP_B, PORT_B);
14321 }
14322
14323 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14324 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14325
14326 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14327 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14328
14329 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14330 intel_dp_init(dev, PCH_DP_C, PORT_C);
14331
14332 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14333 intel_dp_init(dev, PCH_DP_D, PORT_D);
14334 } else if (IS_VALLEYVIEW(dev)) {
14335 /*
14336 * The DP_DETECTED bit is the latched state of the DDC
14337 * SDA pin at boot. However since eDP doesn't require DDC
14338 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14339 * eDP ports may have been muxed to an alternate function.
14340 * Thus we can't rely on the DP_DETECTED bit alone to detect
14341 * eDP ports. Consult the VBT as well as DP_DETECTED to
14342 * detect eDP ports.
14343 */
14344 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14345 !intel_dp_is_edp(dev, PORT_B))
14346 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14347 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14348 intel_dp_is_edp(dev, PORT_B))
14349 intel_dp_init(dev, VLV_DP_B, PORT_B);
14350
14351 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14352 !intel_dp_is_edp(dev, PORT_C))
14353 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14354 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14355 intel_dp_is_edp(dev, PORT_C))
14356 intel_dp_init(dev, VLV_DP_C, PORT_C);
14357
14358 if (IS_CHERRYVIEW(dev)) {
14359 /* eDP not supported on port D, so don't check VBT */
14360 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14361 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14362 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14363 intel_dp_init(dev, CHV_DP_D, PORT_D);
14364 }
14365
14366 intel_dsi_init(dev);
14367 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14368 bool found = false;
14369
14370 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14371 DRM_DEBUG_KMS("probing SDVOB\n");
14372 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14373 if (!found && IS_G4X(dev)) {
14374 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14375 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14376 }
14377
14378 if (!found && IS_G4X(dev))
14379 intel_dp_init(dev, DP_B, PORT_B);
14380 }
14381
14382 /* Before G4X SDVOC doesn't have its own detect register */
14383
14384 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14385 DRM_DEBUG_KMS("probing SDVOC\n");
14386 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14387 }
14388
14389 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14390
14391 if (IS_G4X(dev)) {
14392 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14393 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14394 }
14395 if (IS_G4X(dev))
14396 intel_dp_init(dev, DP_C, PORT_C);
14397 }
14398
14399 if (IS_G4X(dev) &&
14400 (I915_READ(DP_D) & DP_DETECTED))
14401 intel_dp_init(dev, DP_D, PORT_D);
14402 } else if (IS_GEN2(dev))
14403 intel_dvo_init(dev);
14404
14405 if (SUPPORTS_TV(dev))
14406 intel_tv_init(dev);
14407
14408 intel_psr_init(dev);
14409
14410 for_each_intel_encoder(dev, encoder) {
14411 encoder->base.possible_crtcs = encoder->crtc_mask;
14412 encoder->base.possible_clones =
14413 intel_encoder_clones(encoder);
14414 }
14415
14416 intel_init_pch_refclk(dev);
14417
14418 drm_helper_move_panel_connectors_to_head(dev);
14419 }
14420
14421 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14422 {
14423 struct drm_device *dev = fb->dev;
14424 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14425
14426 drm_framebuffer_cleanup(fb);
14427 mutex_lock(&dev->struct_mutex);
14428 WARN_ON(!intel_fb->obj->framebuffer_references--);
14429 drm_gem_object_unreference(&intel_fb->obj->base);
14430 mutex_unlock(&dev->struct_mutex);
14431 kfree(intel_fb);
14432 }
14433
14434 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14435 struct drm_file *file,
14436 unsigned int *handle)
14437 {
14438 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14439 struct drm_i915_gem_object *obj = intel_fb->obj;
14440
14441 if (obj->userptr.mm) {
14442 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14443 return -EINVAL;
14444 }
14445
14446 return drm_gem_handle_create(file, &obj->base, handle);
14447 }
14448
14449 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14450 struct drm_file *file,
14451 unsigned flags, unsigned color,
14452 struct drm_clip_rect *clips,
14453 unsigned num_clips)
14454 {
14455 struct drm_device *dev = fb->dev;
14456 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14457 struct drm_i915_gem_object *obj = intel_fb->obj;
14458
14459 mutex_lock(&dev->struct_mutex);
14460 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14461 mutex_unlock(&dev->struct_mutex);
14462
14463 return 0;
14464 }
14465
14466 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14467 .destroy = intel_user_framebuffer_destroy,
14468 .create_handle = intel_user_framebuffer_create_handle,
14469 .dirty = intel_user_framebuffer_dirty,
14470 };
14471
14472 static
14473 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14474 uint32_t pixel_format)
14475 {
14476 u32 gen = INTEL_INFO(dev)->gen;
14477
14478 if (gen >= 9) {
14479 /* "The stride in bytes must not exceed the of the size of 8K
14480 * pixels and 32K bytes."
14481 */
14482 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14483 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14484 return 32*1024;
14485 } else if (gen >= 4) {
14486 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14487 return 16*1024;
14488 else
14489 return 32*1024;
14490 } else if (gen >= 3) {
14491 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14492 return 8*1024;
14493 else
14494 return 16*1024;
14495 } else {
14496 /* XXX DSPC is limited to 4k tiled */
14497 return 8*1024;
14498 }
14499 }
14500
14501 static int intel_framebuffer_init(struct drm_device *dev,
14502 struct intel_framebuffer *intel_fb,
14503 struct drm_mode_fb_cmd2 *mode_cmd,
14504 struct drm_i915_gem_object *obj)
14505 {
14506 unsigned int aligned_height;
14507 int ret;
14508 u32 pitch_limit, stride_alignment;
14509
14510 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14511
14512 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14513 /* Enforce that fb modifier and tiling mode match, but only for
14514 * X-tiled. This is needed for FBC. */
14515 if (!!(obj->tiling_mode == I915_TILING_X) !=
14516 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14517 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14518 return -EINVAL;
14519 }
14520 } else {
14521 if (obj->tiling_mode == I915_TILING_X)
14522 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14523 else if (obj->tiling_mode == I915_TILING_Y) {
14524 DRM_DEBUG("No Y tiling for legacy addfb\n");
14525 return -EINVAL;
14526 }
14527 }
14528
14529 /* Passed in modifier sanity checking. */
14530 switch (mode_cmd->modifier[0]) {
14531 case I915_FORMAT_MOD_Y_TILED:
14532 case I915_FORMAT_MOD_Yf_TILED:
14533 if (INTEL_INFO(dev)->gen < 9) {
14534 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14535 mode_cmd->modifier[0]);
14536 return -EINVAL;
14537 }
14538 case DRM_FORMAT_MOD_NONE:
14539 case I915_FORMAT_MOD_X_TILED:
14540 break;
14541 default:
14542 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14543 mode_cmd->modifier[0]);
14544 return -EINVAL;
14545 }
14546
14547 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14548 mode_cmd->pixel_format);
14549 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14550 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14551 mode_cmd->pitches[0], stride_alignment);
14552 return -EINVAL;
14553 }
14554
14555 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14556 mode_cmd->pixel_format);
14557 if (mode_cmd->pitches[0] > pitch_limit) {
14558 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14559 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14560 "tiled" : "linear",
14561 mode_cmd->pitches[0], pitch_limit);
14562 return -EINVAL;
14563 }
14564
14565 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14566 mode_cmd->pitches[0] != obj->stride) {
14567 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14568 mode_cmd->pitches[0], obj->stride);
14569 return -EINVAL;
14570 }
14571
14572 /* Reject formats not supported by any plane early. */
14573 switch (mode_cmd->pixel_format) {
14574 case DRM_FORMAT_C8:
14575 case DRM_FORMAT_RGB565:
14576 case DRM_FORMAT_XRGB8888:
14577 case DRM_FORMAT_ARGB8888:
14578 break;
14579 case DRM_FORMAT_XRGB1555:
14580 if (INTEL_INFO(dev)->gen > 3) {
14581 DRM_DEBUG("unsupported pixel format: %s\n",
14582 drm_get_format_name(mode_cmd->pixel_format));
14583 return -EINVAL;
14584 }
14585 break;
14586 case DRM_FORMAT_ABGR8888:
14587 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14588 DRM_DEBUG("unsupported pixel format: %s\n",
14589 drm_get_format_name(mode_cmd->pixel_format));
14590 return -EINVAL;
14591 }
14592 break;
14593 case DRM_FORMAT_XBGR8888:
14594 case DRM_FORMAT_XRGB2101010:
14595 case DRM_FORMAT_XBGR2101010:
14596 if (INTEL_INFO(dev)->gen < 4) {
14597 DRM_DEBUG("unsupported pixel format: %s\n",
14598 drm_get_format_name(mode_cmd->pixel_format));
14599 return -EINVAL;
14600 }
14601 break;
14602 case DRM_FORMAT_ABGR2101010:
14603 if (!IS_VALLEYVIEW(dev)) {
14604 DRM_DEBUG("unsupported pixel format: %s\n",
14605 drm_get_format_name(mode_cmd->pixel_format));
14606 return -EINVAL;
14607 }
14608 break;
14609 case DRM_FORMAT_YUYV:
14610 case DRM_FORMAT_UYVY:
14611 case DRM_FORMAT_YVYU:
14612 case DRM_FORMAT_VYUY:
14613 if (INTEL_INFO(dev)->gen < 5) {
14614 DRM_DEBUG("unsupported pixel format: %s\n",
14615 drm_get_format_name(mode_cmd->pixel_format));
14616 return -EINVAL;
14617 }
14618 break;
14619 default:
14620 DRM_DEBUG("unsupported pixel format: %s\n",
14621 drm_get_format_name(mode_cmd->pixel_format));
14622 return -EINVAL;
14623 }
14624
14625 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14626 if (mode_cmd->offsets[0] != 0)
14627 return -EINVAL;
14628
14629 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14630 mode_cmd->pixel_format,
14631 mode_cmd->modifier[0]);
14632 /* FIXME drm helper for size checks (especially planar formats)? */
14633 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14634 return -EINVAL;
14635
14636 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14637 intel_fb->obj = obj;
14638 intel_fb->obj->framebuffer_references++;
14639
14640 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14641 if (ret) {
14642 DRM_ERROR("framebuffer init failed %d\n", ret);
14643 return ret;
14644 }
14645
14646 return 0;
14647 }
14648
14649 static struct drm_framebuffer *
14650 intel_user_framebuffer_create(struct drm_device *dev,
14651 struct drm_file *filp,
14652 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14653 {
14654 struct drm_framebuffer *fb;
14655 struct drm_i915_gem_object *obj;
14656 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14657
14658 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14659 mode_cmd.handles[0]));
14660 if (&obj->base == NULL)
14661 return ERR_PTR(-ENOENT);
14662
14663 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14664 if (IS_ERR(fb))
14665 drm_gem_object_unreference_unlocked(&obj->base);
14666
14667 return fb;
14668 }
14669
14670 #ifndef CONFIG_DRM_FBDEV_EMULATION
14671 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14672 {
14673 }
14674 #endif
14675
14676 static const struct drm_mode_config_funcs intel_mode_funcs = {
14677 .fb_create = intel_user_framebuffer_create,
14678 .output_poll_changed = intel_fbdev_output_poll_changed,
14679 .atomic_check = intel_atomic_check,
14680 .atomic_commit = intel_atomic_commit,
14681 .atomic_state_alloc = intel_atomic_state_alloc,
14682 .atomic_state_clear = intel_atomic_state_clear,
14683 };
14684
14685 /* Set up chip specific display functions */
14686 static void intel_init_display(struct drm_device *dev)
14687 {
14688 struct drm_i915_private *dev_priv = dev->dev_private;
14689
14690 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14691 dev_priv->display.find_dpll = g4x_find_best_dpll;
14692 else if (IS_CHERRYVIEW(dev))
14693 dev_priv->display.find_dpll = chv_find_best_dpll;
14694 else if (IS_VALLEYVIEW(dev))
14695 dev_priv->display.find_dpll = vlv_find_best_dpll;
14696 else if (IS_PINEVIEW(dev))
14697 dev_priv->display.find_dpll = pnv_find_best_dpll;
14698 else
14699 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14700
14701 if (INTEL_INFO(dev)->gen >= 9) {
14702 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14703 dev_priv->display.get_initial_plane_config =
14704 skylake_get_initial_plane_config;
14705 dev_priv->display.crtc_compute_clock =
14706 haswell_crtc_compute_clock;
14707 dev_priv->display.crtc_enable = haswell_crtc_enable;
14708 dev_priv->display.crtc_disable = haswell_crtc_disable;
14709 dev_priv->display.update_primary_plane =
14710 skylake_update_primary_plane;
14711 } else if (HAS_DDI(dev)) {
14712 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14713 dev_priv->display.get_initial_plane_config =
14714 ironlake_get_initial_plane_config;
14715 dev_priv->display.crtc_compute_clock =
14716 haswell_crtc_compute_clock;
14717 dev_priv->display.crtc_enable = haswell_crtc_enable;
14718 dev_priv->display.crtc_disable = haswell_crtc_disable;
14719 dev_priv->display.update_primary_plane =
14720 ironlake_update_primary_plane;
14721 } else if (HAS_PCH_SPLIT(dev)) {
14722 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14723 dev_priv->display.get_initial_plane_config =
14724 ironlake_get_initial_plane_config;
14725 dev_priv->display.crtc_compute_clock =
14726 ironlake_crtc_compute_clock;
14727 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14728 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14729 dev_priv->display.update_primary_plane =
14730 ironlake_update_primary_plane;
14731 } else if (IS_VALLEYVIEW(dev)) {
14732 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14733 dev_priv->display.get_initial_plane_config =
14734 i9xx_get_initial_plane_config;
14735 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14736 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14737 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14738 dev_priv->display.update_primary_plane =
14739 i9xx_update_primary_plane;
14740 } else {
14741 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14742 dev_priv->display.get_initial_plane_config =
14743 i9xx_get_initial_plane_config;
14744 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14745 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14746 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14747 dev_priv->display.update_primary_plane =
14748 i9xx_update_primary_plane;
14749 }
14750
14751 /* Returns the core display clock speed */
14752 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14753 dev_priv->display.get_display_clock_speed =
14754 skylake_get_display_clock_speed;
14755 else if (IS_BROXTON(dev))
14756 dev_priv->display.get_display_clock_speed =
14757 broxton_get_display_clock_speed;
14758 else if (IS_BROADWELL(dev))
14759 dev_priv->display.get_display_clock_speed =
14760 broadwell_get_display_clock_speed;
14761 else if (IS_HASWELL(dev))
14762 dev_priv->display.get_display_clock_speed =
14763 haswell_get_display_clock_speed;
14764 else if (IS_VALLEYVIEW(dev))
14765 dev_priv->display.get_display_clock_speed =
14766 valleyview_get_display_clock_speed;
14767 else if (IS_GEN5(dev))
14768 dev_priv->display.get_display_clock_speed =
14769 ilk_get_display_clock_speed;
14770 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14771 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
14772 dev_priv->display.get_display_clock_speed =
14773 i945_get_display_clock_speed;
14774 else if (IS_GM45(dev))
14775 dev_priv->display.get_display_clock_speed =
14776 gm45_get_display_clock_speed;
14777 else if (IS_CRESTLINE(dev))
14778 dev_priv->display.get_display_clock_speed =
14779 i965gm_get_display_clock_speed;
14780 else if (IS_PINEVIEW(dev))
14781 dev_priv->display.get_display_clock_speed =
14782 pnv_get_display_clock_speed;
14783 else if (IS_G33(dev) || IS_G4X(dev))
14784 dev_priv->display.get_display_clock_speed =
14785 g33_get_display_clock_speed;
14786 else if (IS_I915G(dev))
14787 dev_priv->display.get_display_clock_speed =
14788 i915_get_display_clock_speed;
14789 else if (IS_I945GM(dev) || IS_845G(dev))
14790 dev_priv->display.get_display_clock_speed =
14791 i9xx_misc_get_display_clock_speed;
14792 else if (IS_PINEVIEW(dev))
14793 dev_priv->display.get_display_clock_speed =
14794 pnv_get_display_clock_speed;
14795 else if (IS_I915GM(dev))
14796 dev_priv->display.get_display_clock_speed =
14797 i915gm_get_display_clock_speed;
14798 else if (IS_I865G(dev))
14799 dev_priv->display.get_display_clock_speed =
14800 i865_get_display_clock_speed;
14801 else if (IS_I85X(dev))
14802 dev_priv->display.get_display_clock_speed =
14803 i85x_get_display_clock_speed;
14804 else { /* 830 */
14805 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
14806 dev_priv->display.get_display_clock_speed =
14807 i830_get_display_clock_speed;
14808 }
14809
14810 if (IS_GEN5(dev)) {
14811 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14812 } else if (IS_GEN6(dev)) {
14813 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14814 } else if (IS_IVYBRIDGE(dev)) {
14815 /* FIXME: detect B0+ stepping and use auto training */
14816 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14817 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14818 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14819 if (IS_BROADWELL(dev)) {
14820 dev_priv->display.modeset_commit_cdclk =
14821 broadwell_modeset_commit_cdclk;
14822 dev_priv->display.modeset_calc_cdclk =
14823 broadwell_modeset_calc_cdclk;
14824 }
14825 } else if (IS_VALLEYVIEW(dev)) {
14826 dev_priv->display.modeset_commit_cdclk =
14827 valleyview_modeset_commit_cdclk;
14828 dev_priv->display.modeset_calc_cdclk =
14829 valleyview_modeset_calc_cdclk;
14830 } else if (IS_BROXTON(dev)) {
14831 dev_priv->display.modeset_commit_cdclk =
14832 broxton_modeset_commit_cdclk;
14833 dev_priv->display.modeset_calc_cdclk =
14834 broxton_modeset_calc_cdclk;
14835 }
14836
14837 switch (INTEL_INFO(dev)->gen) {
14838 case 2:
14839 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14840 break;
14841
14842 case 3:
14843 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14844 break;
14845
14846 case 4:
14847 case 5:
14848 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14849 break;
14850
14851 case 6:
14852 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14853 break;
14854 case 7:
14855 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14856 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14857 break;
14858 case 9:
14859 /* Drop through - unsupported since execlist only. */
14860 default:
14861 /* Default just returns -ENODEV to indicate unsupported */
14862 dev_priv->display.queue_flip = intel_default_queue_flip;
14863 }
14864
14865 mutex_init(&dev_priv->pps_mutex);
14866 }
14867
14868 /*
14869 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14870 * resume, or other times. This quirk makes sure that's the case for
14871 * affected systems.
14872 */
14873 static void quirk_pipea_force(struct drm_device *dev)
14874 {
14875 struct drm_i915_private *dev_priv = dev->dev_private;
14876
14877 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14878 DRM_INFO("applying pipe a force quirk\n");
14879 }
14880
14881 static void quirk_pipeb_force(struct drm_device *dev)
14882 {
14883 struct drm_i915_private *dev_priv = dev->dev_private;
14884
14885 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14886 DRM_INFO("applying pipe b force quirk\n");
14887 }
14888
14889 /*
14890 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14891 */
14892 static void quirk_ssc_force_disable(struct drm_device *dev)
14893 {
14894 struct drm_i915_private *dev_priv = dev->dev_private;
14895 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14896 DRM_INFO("applying lvds SSC disable quirk\n");
14897 }
14898
14899 /*
14900 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14901 * brightness value
14902 */
14903 static void quirk_invert_brightness(struct drm_device *dev)
14904 {
14905 struct drm_i915_private *dev_priv = dev->dev_private;
14906 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14907 DRM_INFO("applying inverted panel brightness quirk\n");
14908 }
14909
14910 /* Some VBT's incorrectly indicate no backlight is present */
14911 static void quirk_backlight_present(struct drm_device *dev)
14912 {
14913 struct drm_i915_private *dev_priv = dev->dev_private;
14914 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14915 DRM_INFO("applying backlight present quirk\n");
14916 }
14917
14918 struct intel_quirk {
14919 int device;
14920 int subsystem_vendor;
14921 int subsystem_device;
14922 void (*hook)(struct drm_device *dev);
14923 };
14924
14925 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14926 struct intel_dmi_quirk {
14927 void (*hook)(struct drm_device *dev);
14928 const struct dmi_system_id (*dmi_id_list)[];
14929 };
14930
14931 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14932 {
14933 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14934 return 1;
14935 }
14936
14937 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14938 {
14939 .dmi_id_list = &(const struct dmi_system_id[]) {
14940 {
14941 .callback = intel_dmi_reverse_brightness,
14942 .ident = "NCR Corporation",
14943 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14944 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14945 },
14946 },
14947 { } /* terminating entry */
14948 },
14949 .hook = quirk_invert_brightness,
14950 },
14951 };
14952
14953 static struct intel_quirk intel_quirks[] = {
14954 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14955 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14956
14957 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14958 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14959
14960 /* 830 needs to leave pipe A & dpll A up */
14961 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14962
14963 /* 830 needs to leave pipe B & dpll B up */
14964 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14965
14966 /* Lenovo U160 cannot use SSC on LVDS */
14967 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14968
14969 /* Sony Vaio Y cannot use SSC on LVDS */
14970 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14971
14972 /* Acer Aspire 5734Z must invert backlight brightness */
14973 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14974
14975 /* Acer/eMachines G725 */
14976 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14977
14978 /* Acer/eMachines e725 */
14979 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14980
14981 /* Acer/Packard Bell NCL20 */
14982 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14983
14984 /* Acer Aspire 4736Z */
14985 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14986
14987 /* Acer Aspire 5336 */
14988 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14989
14990 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14991 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14992
14993 /* Acer C720 Chromebook (Core i3 4005U) */
14994 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14995
14996 /* Apple Macbook 2,1 (Core 2 T7400) */
14997 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14998
14999 /* Apple Macbook 4,1 */
15000 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15001
15002 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15003 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15004
15005 /* HP Chromebook 14 (Celeron 2955U) */
15006 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15007
15008 /* Dell Chromebook 11 */
15009 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15010
15011 /* Dell Chromebook 11 (2015 version) */
15012 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15013 };
15014
15015 static void intel_init_quirks(struct drm_device *dev)
15016 {
15017 struct pci_dev *d = dev->pdev;
15018 int i;
15019
15020 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15021 struct intel_quirk *q = &intel_quirks[i];
15022
15023 if (d->device == q->device &&
15024 (d->subsystem_vendor == q->subsystem_vendor ||
15025 q->subsystem_vendor == PCI_ANY_ID) &&
15026 (d->subsystem_device == q->subsystem_device ||
15027 q->subsystem_device == PCI_ANY_ID))
15028 q->hook(dev);
15029 }
15030 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15031 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15032 intel_dmi_quirks[i].hook(dev);
15033 }
15034 }
15035
15036 /* Disable the VGA plane that we never use */
15037 static void i915_disable_vga(struct drm_device *dev)
15038 {
15039 struct drm_i915_private *dev_priv = dev->dev_private;
15040 u8 sr1;
15041 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15042
15043 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15044 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15045 outb(SR01, VGA_SR_INDEX);
15046 sr1 = inb(VGA_SR_DATA);
15047 outb(sr1 | 1<<5, VGA_SR_DATA);
15048 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15049 udelay(300);
15050
15051 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15052 POSTING_READ(vga_reg);
15053 }
15054
15055 void intel_modeset_init_hw(struct drm_device *dev)
15056 {
15057 intel_update_cdclk(dev);
15058 intel_prepare_ddi(dev);
15059 intel_init_clock_gating(dev);
15060 intel_enable_gt_powersave(dev);
15061 }
15062
15063 void intel_modeset_init(struct drm_device *dev)
15064 {
15065 struct drm_i915_private *dev_priv = dev->dev_private;
15066 int sprite, ret;
15067 enum pipe pipe;
15068 struct intel_crtc *crtc;
15069
15070 drm_mode_config_init(dev);
15071
15072 dev->mode_config.min_width = 0;
15073 dev->mode_config.min_height = 0;
15074
15075 dev->mode_config.preferred_depth = 24;
15076 dev->mode_config.prefer_shadow = 1;
15077
15078 dev->mode_config.allow_fb_modifiers = true;
15079
15080 dev->mode_config.funcs = &intel_mode_funcs;
15081
15082 intel_init_quirks(dev);
15083
15084 intel_init_pm(dev);
15085
15086 if (INTEL_INFO(dev)->num_pipes == 0)
15087 return;
15088
15089 /*
15090 * There may be no VBT; and if the BIOS enabled SSC we can
15091 * just keep using it to avoid unnecessary flicker. Whereas if the
15092 * BIOS isn't using it, don't assume it will work even if the VBT
15093 * indicates as much.
15094 */
15095 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15096 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15097 DREF_SSC1_ENABLE);
15098
15099 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15100 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15101 bios_lvds_use_ssc ? "en" : "dis",
15102 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15103 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15104 }
15105 }
15106
15107 intel_init_display(dev);
15108 intel_init_audio(dev);
15109
15110 if (IS_GEN2(dev)) {
15111 dev->mode_config.max_width = 2048;
15112 dev->mode_config.max_height = 2048;
15113 } else if (IS_GEN3(dev)) {
15114 dev->mode_config.max_width = 4096;
15115 dev->mode_config.max_height = 4096;
15116 } else {
15117 dev->mode_config.max_width = 8192;
15118 dev->mode_config.max_height = 8192;
15119 }
15120
15121 if (IS_845G(dev) || IS_I865G(dev)) {
15122 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15123 dev->mode_config.cursor_height = 1023;
15124 } else if (IS_GEN2(dev)) {
15125 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15126 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15127 } else {
15128 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15129 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15130 }
15131
15132 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15133
15134 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15135 INTEL_INFO(dev)->num_pipes,
15136 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15137
15138 for_each_pipe(dev_priv, pipe) {
15139 intel_crtc_init(dev, pipe);
15140 for_each_sprite(dev_priv, pipe, sprite) {
15141 ret = intel_plane_init(dev, pipe, sprite);
15142 if (ret)
15143 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15144 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15145 }
15146 }
15147
15148 intel_update_czclk(dev_priv);
15149 intel_update_cdclk(dev);
15150
15151 intel_shared_dpll_init(dev);
15152
15153 /* Just disable it once at startup */
15154 i915_disable_vga(dev);
15155 intel_setup_outputs(dev);
15156
15157 drm_modeset_lock_all(dev);
15158 intel_modeset_setup_hw_state(dev);
15159 drm_modeset_unlock_all(dev);
15160
15161 for_each_intel_crtc(dev, crtc) {
15162 struct intel_initial_plane_config plane_config = {};
15163
15164 if (!crtc->active)
15165 continue;
15166
15167 /*
15168 * Note that reserving the BIOS fb up front prevents us
15169 * from stuffing other stolen allocations like the ring
15170 * on top. This prevents some ugliness at boot time, and
15171 * can even allow for smooth boot transitions if the BIOS
15172 * fb is large enough for the active pipe configuration.
15173 */
15174 dev_priv->display.get_initial_plane_config(crtc,
15175 &plane_config);
15176
15177 /*
15178 * If the fb is shared between multiple heads, we'll
15179 * just get the first one.
15180 */
15181 intel_find_initial_plane_obj(crtc, &plane_config);
15182 }
15183 }
15184
15185 static void intel_enable_pipe_a(struct drm_device *dev)
15186 {
15187 struct intel_connector *connector;
15188 struct drm_connector *crt = NULL;
15189 struct intel_load_detect_pipe load_detect_temp;
15190 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15191
15192 /* We can't just switch on the pipe A, we need to set things up with a
15193 * proper mode and output configuration. As a gross hack, enable pipe A
15194 * by enabling the load detect pipe once. */
15195 for_each_intel_connector(dev, connector) {
15196 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15197 crt = &connector->base;
15198 break;
15199 }
15200 }
15201
15202 if (!crt)
15203 return;
15204
15205 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15206 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15207 }
15208
15209 static bool
15210 intel_check_plane_mapping(struct intel_crtc *crtc)
15211 {
15212 struct drm_device *dev = crtc->base.dev;
15213 struct drm_i915_private *dev_priv = dev->dev_private;
15214 u32 val;
15215
15216 if (INTEL_INFO(dev)->num_pipes == 1)
15217 return true;
15218
15219 val = I915_READ(DSPCNTR(!crtc->plane));
15220
15221 if ((val & DISPLAY_PLANE_ENABLE) &&
15222 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15223 return false;
15224
15225 return true;
15226 }
15227
15228 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15229 {
15230 struct drm_device *dev = crtc->base.dev;
15231 struct intel_encoder *encoder;
15232
15233 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15234 return true;
15235
15236 return false;
15237 }
15238
15239 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15240 {
15241 struct drm_device *dev = crtc->base.dev;
15242 struct drm_i915_private *dev_priv = dev->dev_private;
15243 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15244
15245 /* Clear any frame start delays used for debugging left by the BIOS */
15246 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15247
15248 /* restore vblank interrupts to correct state */
15249 drm_crtc_vblank_reset(&crtc->base);
15250 if (crtc->active) {
15251 struct intel_plane *plane;
15252
15253 drm_crtc_vblank_on(&crtc->base);
15254
15255 /* Disable everything but the primary plane */
15256 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15257 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15258 continue;
15259
15260 plane->disable_plane(&plane->base, &crtc->base);
15261 }
15262 }
15263
15264 /* We need to sanitize the plane -> pipe mapping first because this will
15265 * disable the crtc (and hence change the state) if it is wrong. Note
15266 * that gen4+ has a fixed plane -> pipe mapping. */
15267 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15268 bool plane;
15269
15270 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15271 crtc->base.base.id);
15272
15273 /* Pipe has the wrong plane attached and the plane is active.
15274 * Temporarily change the plane mapping and disable everything
15275 * ... */
15276 plane = crtc->plane;
15277 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15278 crtc->plane = !plane;
15279 intel_crtc_disable_noatomic(&crtc->base);
15280 crtc->plane = plane;
15281 }
15282
15283 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15284 crtc->pipe == PIPE_A && !crtc->active) {
15285 /* BIOS forgot to enable pipe A, this mostly happens after
15286 * resume. Force-enable the pipe to fix this, the update_dpms
15287 * call below we restore the pipe to the right state, but leave
15288 * the required bits on. */
15289 intel_enable_pipe_a(dev);
15290 }
15291
15292 /* Adjust the state of the output pipe according to whether we
15293 * have active connectors/encoders. */
15294 if (!intel_crtc_has_encoders(crtc))
15295 intel_crtc_disable_noatomic(&crtc->base);
15296
15297 if (crtc->active != crtc->base.state->active) {
15298 struct intel_encoder *encoder;
15299
15300 /* This can happen either due to bugs in the get_hw_state
15301 * functions or because of calls to intel_crtc_disable_noatomic,
15302 * or because the pipe is force-enabled due to the
15303 * pipe A quirk. */
15304 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15305 crtc->base.base.id,
15306 crtc->base.state->enable ? "enabled" : "disabled",
15307 crtc->active ? "enabled" : "disabled");
15308
15309 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15310 crtc->base.state->active = crtc->active;
15311 crtc->base.enabled = crtc->active;
15312
15313 /* Because we only establish the connector -> encoder ->
15314 * crtc links if something is active, this means the
15315 * crtc is now deactivated. Break the links. connector
15316 * -> encoder links are only establish when things are
15317 * actually up, hence no need to break them. */
15318 WARN_ON(crtc->active);
15319
15320 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15321 encoder->base.crtc = NULL;
15322 }
15323
15324 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15325 /*
15326 * We start out with underrun reporting disabled to avoid races.
15327 * For correct bookkeeping mark this on active crtcs.
15328 *
15329 * Also on gmch platforms we dont have any hardware bits to
15330 * disable the underrun reporting. Which means we need to start
15331 * out with underrun reporting disabled also on inactive pipes,
15332 * since otherwise we'll complain about the garbage we read when
15333 * e.g. coming up after runtime pm.
15334 *
15335 * No protection against concurrent access is required - at
15336 * worst a fifo underrun happens which also sets this to false.
15337 */
15338 crtc->cpu_fifo_underrun_disabled = true;
15339 crtc->pch_fifo_underrun_disabled = true;
15340 }
15341 }
15342
15343 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15344 {
15345 struct intel_connector *connector;
15346 struct drm_device *dev = encoder->base.dev;
15347 bool active = false;
15348
15349 /* We need to check both for a crtc link (meaning that the
15350 * encoder is active and trying to read from a pipe) and the
15351 * pipe itself being active. */
15352 bool has_active_crtc = encoder->base.crtc &&
15353 to_intel_crtc(encoder->base.crtc)->active;
15354
15355 for_each_intel_connector(dev, connector) {
15356 if (connector->base.encoder != &encoder->base)
15357 continue;
15358
15359 active = true;
15360 break;
15361 }
15362
15363 if (active && !has_active_crtc) {
15364 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15365 encoder->base.base.id,
15366 encoder->base.name);
15367
15368 /* Connector is active, but has no active pipe. This is
15369 * fallout from our resume register restoring. Disable
15370 * the encoder manually again. */
15371 if (encoder->base.crtc) {
15372 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15373 encoder->base.base.id,
15374 encoder->base.name);
15375 encoder->disable(encoder);
15376 if (encoder->post_disable)
15377 encoder->post_disable(encoder);
15378 }
15379 encoder->base.crtc = NULL;
15380
15381 /* Inconsistent output/port/pipe state happens presumably due to
15382 * a bug in one of the get_hw_state functions. Or someplace else
15383 * in our code, like the register restore mess on resume. Clamp
15384 * things to off as a safer default. */
15385 for_each_intel_connector(dev, connector) {
15386 if (connector->encoder != encoder)
15387 continue;
15388 connector->base.dpms = DRM_MODE_DPMS_OFF;
15389 connector->base.encoder = NULL;
15390 }
15391 }
15392 /* Enabled encoders without active connectors will be fixed in
15393 * the crtc fixup. */
15394 }
15395
15396 void i915_redisable_vga_power_on(struct drm_device *dev)
15397 {
15398 struct drm_i915_private *dev_priv = dev->dev_private;
15399 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15400
15401 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15402 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15403 i915_disable_vga(dev);
15404 }
15405 }
15406
15407 void i915_redisable_vga(struct drm_device *dev)
15408 {
15409 struct drm_i915_private *dev_priv = dev->dev_private;
15410
15411 /* This function can be called both from intel_modeset_setup_hw_state or
15412 * at a very early point in our resume sequence, where the power well
15413 * structures are not yet restored. Since this function is at a very
15414 * paranoid "someone might have enabled VGA while we were not looking"
15415 * level, just check if the power well is enabled instead of trying to
15416 * follow the "don't touch the power well if we don't need it" policy
15417 * the rest of the driver uses. */
15418 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15419 return;
15420
15421 i915_redisable_vga_power_on(dev);
15422 }
15423
15424 static bool primary_get_hw_state(struct intel_plane *plane)
15425 {
15426 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15427
15428 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15429 }
15430
15431 /* FIXME read out full plane state for all planes */
15432 static void readout_plane_state(struct intel_crtc *crtc)
15433 {
15434 struct drm_plane *primary = crtc->base.primary;
15435 struct intel_plane_state *plane_state =
15436 to_intel_plane_state(primary->state);
15437
15438 plane_state->visible = crtc->active &&
15439 primary_get_hw_state(to_intel_plane(primary));
15440
15441 if (plane_state->visible)
15442 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15443 }
15444
15445 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15446 {
15447 struct drm_i915_private *dev_priv = dev->dev_private;
15448 enum pipe pipe;
15449 struct intel_crtc *crtc;
15450 struct intel_encoder *encoder;
15451 struct intel_connector *connector;
15452 int i;
15453
15454 for_each_intel_crtc(dev, crtc) {
15455 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
15456 memset(crtc->config, 0, sizeof(*crtc->config));
15457 crtc->config->base.crtc = &crtc->base;
15458
15459 crtc->active = dev_priv->display.get_pipe_config(crtc,
15460 crtc->config);
15461
15462 crtc->base.state->active = crtc->active;
15463 crtc->base.enabled = crtc->active;
15464
15465 readout_plane_state(crtc);
15466
15467 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15468 crtc->base.base.id,
15469 crtc->active ? "enabled" : "disabled");
15470 }
15471
15472 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15473 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15474
15475 pll->on = pll->get_hw_state(dev_priv, pll,
15476 &pll->config.hw_state);
15477 pll->active = 0;
15478 pll->config.crtc_mask = 0;
15479 for_each_intel_crtc(dev, crtc) {
15480 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15481 pll->active++;
15482 pll->config.crtc_mask |= 1 << crtc->pipe;
15483 }
15484 }
15485
15486 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15487 pll->name, pll->config.crtc_mask, pll->on);
15488
15489 if (pll->config.crtc_mask)
15490 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15491 }
15492
15493 for_each_intel_encoder(dev, encoder) {
15494 pipe = 0;
15495
15496 if (encoder->get_hw_state(encoder, &pipe)) {
15497 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15498 encoder->base.crtc = &crtc->base;
15499 encoder->get_config(encoder, crtc->config);
15500 } else {
15501 encoder->base.crtc = NULL;
15502 }
15503
15504 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15505 encoder->base.base.id,
15506 encoder->base.name,
15507 encoder->base.crtc ? "enabled" : "disabled",
15508 pipe_name(pipe));
15509 }
15510
15511 for_each_intel_connector(dev, connector) {
15512 if (connector->get_hw_state(connector)) {
15513 connector->base.dpms = DRM_MODE_DPMS_ON;
15514 connector->base.encoder = &connector->encoder->base;
15515 } else {
15516 connector->base.dpms = DRM_MODE_DPMS_OFF;
15517 connector->base.encoder = NULL;
15518 }
15519 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15520 connector->base.base.id,
15521 connector->base.name,
15522 connector->base.encoder ? "enabled" : "disabled");
15523 }
15524
15525 for_each_intel_crtc(dev, crtc) {
15526 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15527
15528 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15529 if (crtc->base.state->active) {
15530 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15531 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15532 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15533
15534 /*
15535 * The initial mode needs to be set in order to keep
15536 * the atomic core happy. It wants a valid mode if the
15537 * crtc's enabled, so we do the above call.
15538 *
15539 * At this point some state updated by the connectors
15540 * in their ->detect() callback has not run yet, so
15541 * no recalculation can be done yet.
15542 *
15543 * Even if we could do a recalculation and modeset
15544 * right now it would cause a double modeset if
15545 * fbdev or userspace chooses a different initial mode.
15546 *
15547 * If that happens, someone indicated they wanted a
15548 * mode change, which means it's safe to do a full
15549 * recalculation.
15550 */
15551 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15552
15553 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15554 update_scanline_offset(crtc);
15555 }
15556 }
15557 }
15558
15559 /* Scan out the current hw modeset state,
15560 * and sanitizes it to the current state
15561 */
15562 static void
15563 intel_modeset_setup_hw_state(struct drm_device *dev)
15564 {
15565 struct drm_i915_private *dev_priv = dev->dev_private;
15566 enum pipe pipe;
15567 struct intel_crtc *crtc;
15568 struct intel_encoder *encoder;
15569 int i;
15570
15571 intel_modeset_readout_hw_state(dev);
15572
15573 /* HW state is read out, now we need to sanitize this mess. */
15574 for_each_intel_encoder(dev, encoder) {
15575 intel_sanitize_encoder(encoder);
15576 }
15577
15578 for_each_pipe(dev_priv, pipe) {
15579 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15580 intel_sanitize_crtc(crtc);
15581 intel_dump_pipe_config(crtc, crtc->config,
15582 "[setup_hw_state]");
15583 }
15584
15585 intel_modeset_update_connector_atomic_state(dev);
15586
15587 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15588 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15589
15590 if (!pll->on || pll->active)
15591 continue;
15592
15593 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15594
15595 pll->disable(dev_priv, pll);
15596 pll->on = false;
15597 }
15598
15599 if (IS_VALLEYVIEW(dev))
15600 vlv_wm_get_hw_state(dev);
15601 else if (IS_GEN9(dev))
15602 skl_wm_get_hw_state(dev);
15603 else if (HAS_PCH_SPLIT(dev))
15604 ilk_wm_get_hw_state(dev);
15605
15606 for_each_intel_crtc(dev, crtc) {
15607 unsigned long put_domains;
15608
15609 put_domains = modeset_get_crtc_power_domains(&crtc->base);
15610 if (WARN_ON(put_domains))
15611 modeset_put_power_domains(dev_priv, put_domains);
15612 }
15613 intel_display_set_init_power(dev_priv, false);
15614 }
15615
15616 void intel_display_resume(struct drm_device *dev)
15617 {
15618 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15619 struct intel_connector *conn;
15620 struct intel_plane *plane;
15621 struct drm_crtc *crtc;
15622 int ret;
15623
15624 if (!state)
15625 return;
15626
15627 state->acquire_ctx = dev->mode_config.acquire_ctx;
15628
15629 /* preserve complete old state, including dpll */
15630 intel_atomic_get_shared_dpll_state(state);
15631
15632 for_each_crtc(dev, crtc) {
15633 struct drm_crtc_state *crtc_state =
15634 drm_atomic_get_crtc_state(state, crtc);
15635
15636 ret = PTR_ERR_OR_ZERO(crtc_state);
15637 if (ret)
15638 goto err;
15639
15640 /* force a restore */
15641 crtc_state->mode_changed = true;
15642 }
15643
15644 for_each_intel_plane(dev, plane) {
15645 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15646 if (ret)
15647 goto err;
15648 }
15649
15650 for_each_intel_connector(dev, conn) {
15651 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15652 if (ret)
15653 goto err;
15654 }
15655
15656 intel_modeset_setup_hw_state(dev);
15657
15658 i915_redisable_vga(dev);
15659 ret = drm_atomic_commit(state);
15660 if (!ret)
15661 return;
15662
15663 err:
15664 DRM_ERROR("Restoring old state failed with %i\n", ret);
15665 drm_atomic_state_free(state);
15666 }
15667
15668 void intel_modeset_gem_init(struct drm_device *dev)
15669 {
15670 struct drm_crtc *c;
15671 struct drm_i915_gem_object *obj;
15672 int ret;
15673
15674 mutex_lock(&dev->struct_mutex);
15675 intel_init_gt_powersave(dev);
15676 mutex_unlock(&dev->struct_mutex);
15677
15678 intel_modeset_init_hw(dev);
15679
15680 intel_setup_overlay(dev);
15681
15682 /*
15683 * Make sure any fbs we allocated at startup are properly
15684 * pinned & fenced. When we do the allocation it's too early
15685 * for this.
15686 */
15687 for_each_crtc(dev, c) {
15688 obj = intel_fb_obj(c->primary->fb);
15689 if (obj == NULL)
15690 continue;
15691
15692 mutex_lock(&dev->struct_mutex);
15693 ret = intel_pin_and_fence_fb_obj(c->primary,
15694 c->primary->fb,
15695 c->primary->state);
15696 mutex_unlock(&dev->struct_mutex);
15697 if (ret) {
15698 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15699 to_intel_crtc(c)->pipe);
15700 drm_framebuffer_unreference(c->primary->fb);
15701 c->primary->fb = NULL;
15702 c->primary->crtc = c->primary->state->crtc = NULL;
15703 update_state_fb(c->primary);
15704 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
15705 }
15706 }
15707
15708 intel_backlight_register(dev);
15709 }
15710
15711 void intel_connector_unregister(struct intel_connector *intel_connector)
15712 {
15713 struct drm_connector *connector = &intel_connector->base;
15714
15715 intel_panel_destroy_backlight(connector);
15716 drm_connector_unregister(connector);
15717 }
15718
15719 void intel_modeset_cleanup(struct drm_device *dev)
15720 {
15721 struct drm_i915_private *dev_priv = dev->dev_private;
15722 struct drm_connector *connector;
15723
15724 intel_disable_gt_powersave(dev);
15725
15726 intel_backlight_unregister(dev);
15727
15728 /*
15729 * Interrupts and polling as the first thing to avoid creating havoc.
15730 * Too much stuff here (turning of connectors, ...) would
15731 * experience fancy races otherwise.
15732 */
15733 intel_irq_uninstall(dev_priv);
15734
15735 /*
15736 * Due to the hpd irq storm handling the hotplug work can re-arm the
15737 * poll handlers. Hence disable polling after hpd handling is shut down.
15738 */
15739 drm_kms_helper_poll_fini(dev);
15740
15741 intel_unregister_dsm_handler();
15742
15743 intel_fbc_disable(dev_priv);
15744
15745 /* flush any delayed tasks or pending work */
15746 flush_scheduled_work();
15747
15748 /* destroy the backlight and sysfs files before encoders/connectors */
15749 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15750 struct intel_connector *intel_connector;
15751
15752 intel_connector = to_intel_connector(connector);
15753 intel_connector->unregister(intel_connector);
15754 }
15755
15756 drm_mode_config_cleanup(dev);
15757
15758 intel_cleanup_overlay(dev);
15759
15760 mutex_lock(&dev->struct_mutex);
15761 intel_cleanup_gt_powersave(dev);
15762 mutex_unlock(&dev->struct_mutex);
15763 }
15764
15765 /*
15766 * Return which encoder is currently attached for connector.
15767 */
15768 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15769 {
15770 return &intel_attached_encoder(connector)->base;
15771 }
15772
15773 void intel_connector_attach_encoder(struct intel_connector *connector,
15774 struct intel_encoder *encoder)
15775 {
15776 connector->encoder = encoder;
15777 drm_mode_connector_attach_encoder(&connector->base,
15778 &encoder->base);
15779 }
15780
15781 /*
15782 * set vga decode state - true == enable VGA decode
15783 */
15784 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15785 {
15786 struct drm_i915_private *dev_priv = dev->dev_private;
15787 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15788 u16 gmch_ctrl;
15789
15790 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15791 DRM_ERROR("failed to read control word\n");
15792 return -EIO;
15793 }
15794
15795 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15796 return 0;
15797
15798 if (state)
15799 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15800 else
15801 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15802
15803 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15804 DRM_ERROR("failed to write control word\n");
15805 return -EIO;
15806 }
15807
15808 return 0;
15809 }
15810
15811 struct intel_display_error_state {
15812
15813 u32 power_well_driver;
15814
15815 int num_transcoders;
15816
15817 struct intel_cursor_error_state {
15818 u32 control;
15819 u32 position;
15820 u32 base;
15821 u32 size;
15822 } cursor[I915_MAX_PIPES];
15823
15824 struct intel_pipe_error_state {
15825 bool power_domain_on;
15826 u32 source;
15827 u32 stat;
15828 } pipe[I915_MAX_PIPES];
15829
15830 struct intel_plane_error_state {
15831 u32 control;
15832 u32 stride;
15833 u32 size;
15834 u32 pos;
15835 u32 addr;
15836 u32 surface;
15837 u32 tile_offset;
15838 } plane[I915_MAX_PIPES];
15839
15840 struct intel_transcoder_error_state {
15841 bool power_domain_on;
15842 enum transcoder cpu_transcoder;
15843
15844 u32 conf;
15845
15846 u32 htotal;
15847 u32 hblank;
15848 u32 hsync;
15849 u32 vtotal;
15850 u32 vblank;
15851 u32 vsync;
15852 } transcoder[4];
15853 };
15854
15855 struct intel_display_error_state *
15856 intel_display_capture_error_state(struct drm_device *dev)
15857 {
15858 struct drm_i915_private *dev_priv = dev->dev_private;
15859 struct intel_display_error_state *error;
15860 int transcoders[] = {
15861 TRANSCODER_A,
15862 TRANSCODER_B,
15863 TRANSCODER_C,
15864 TRANSCODER_EDP,
15865 };
15866 int i;
15867
15868 if (INTEL_INFO(dev)->num_pipes == 0)
15869 return NULL;
15870
15871 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15872 if (error == NULL)
15873 return NULL;
15874
15875 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15876 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15877
15878 for_each_pipe(dev_priv, i) {
15879 error->pipe[i].power_domain_on =
15880 __intel_display_power_is_enabled(dev_priv,
15881 POWER_DOMAIN_PIPE(i));
15882 if (!error->pipe[i].power_domain_on)
15883 continue;
15884
15885 error->cursor[i].control = I915_READ(CURCNTR(i));
15886 error->cursor[i].position = I915_READ(CURPOS(i));
15887 error->cursor[i].base = I915_READ(CURBASE(i));
15888
15889 error->plane[i].control = I915_READ(DSPCNTR(i));
15890 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15891 if (INTEL_INFO(dev)->gen <= 3) {
15892 error->plane[i].size = I915_READ(DSPSIZE(i));
15893 error->plane[i].pos = I915_READ(DSPPOS(i));
15894 }
15895 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15896 error->plane[i].addr = I915_READ(DSPADDR(i));
15897 if (INTEL_INFO(dev)->gen >= 4) {
15898 error->plane[i].surface = I915_READ(DSPSURF(i));
15899 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15900 }
15901
15902 error->pipe[i].source = I915_READ(PIPESRC(i));
15903
15904 if (HAS_GMCH_DISPLAY(dev))
15905 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15906 }
15907
15908 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15909 if (HAS_DDI(dev_priv->dev))
15910 error->num_transcoders++; /* Account for eDP. */
15911
15912 for (i = 0; i < error->num_transcoders; i++) {
15913 enum transcoder cpu_transcoder = transcoders[i];
15914
15915 error->transcoder[i].power_domain_on =
15916 __intel_display_power_is_enabled(dev_priv,
15917 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15918 if (!error->transcoder[i].power_domain_on)
15919 continue;
15920
15921 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15922
15923 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15924 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15925 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15926 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15927 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15928 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15929 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15930 }
15931
15932 return error;
15933 }
15934
15935 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15936
15937 void
15938 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15939 struct drm_device *dev,
15940 struct intel_display_error_state *error)
15941 {
15942 struct drm_i915_private *dev_priv = dev->dev_private;
15943 int i;
15944
15945 if (!error)
15946 return;
15947
15948 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15949 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15950 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15951 error->power_well_driver);
15952 for_each_pipe(dev_priv, i) {
15953 err_printf(m, "Pipe [%d]:\n", i);
15954 err_printf(m, " Power: %s\n",
15955 error->pipe[i].power_domain_on ? "on" : "off");
15956 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15957 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15958
15959 err_printf(m, "Plane [%d]:\n", i);
15960 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15961 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15962 if (INTEL_INFO(dev)->gen <= 3) {
15963 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15964 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15965 }
15966 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15967 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15968 if (INTEL_INFO(dev)->gen >= 4) {
15969 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15970 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15971 }
15972
15973 err_printf(m, "Cursor [%d]:\n", i);
15974 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15975 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15976 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15977 }
15978
15979 for (i = 0; i < error->num_transcoders; i++) {
15980 err_printf(m, "CPU transcoder: %c\n",
15981 transcoder_name(error->transcoder[i].cpu_transcoder));
15982 err_printf(m, " Power: %s\n",
15983 error->transcoder[i].power_domain_on ? "on" : "off");
15984 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15985 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15986 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15987 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15988 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15989 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15990 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15991 }
15992 }
15993
15994 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15995 {
15996 struct intel_crtc *crtc;
15997
15998 for_each_intel_crtc(dev, crtc) {
15999 struct intel_unpin_work *work;
16000
16001 spin_lock_irq(&dev->event_lock);
16002
16003 work = crtc->unpin_work;
16004
16005 if (work && work->event &&
16006 work->event->base.file_priv == file) {
16007 kfree(work->event);
16008 work->event = NULL;
16009 }
16010
16011 spin_unlock_irq(&dev->event_lock);
16012 }
16013 }
Linux kernel - Deliverables
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