2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
45 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
47 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
48 struct intel_crtc_config
*pipe_config
);
49 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
50 struct intel_crtc_config
*pipe_config
);
52 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
53 int x
, int y
, struct drm_framebuffer
*old_fb
);
65 typedef struct intel_limit intel_limit_t
;
67 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
72 intel_pch_rawclk(struct drm_device
*dev
)
74 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
76 WARN_ON(!HAS_PCH_SPLIT(dev
));
78 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
81 static inline u32
/* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device
*dev
)
85 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
86 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
91 static const intel_limit_t intel_limits_i8xx_dac
= {
92 .dot
= { .min
= 25000, .max
= 350000 },
93 .vco
= { .min
= 930000, .max
= 1400000 },
94 .n
= { .min
= 3, .max
= 16 },
95 .m
= { .min
= 96, .max
= 140 },
96 .m1
= { .min
= 18, .max
= 26 },
97 .m2
= { .min
= 6, .max
= 16 },
98 .p
= { .min
= 4, .max
= 128 },
99 .p1
= { .min
= 2, .max
= 33 },
100 .p2
= { .dot_limit
= 165000,
101 .p2_slow
= 4, .p2_fast
= 2 },
104 static const intel_limit_t intel_limits_i8xx_dvo
= {
105 .dot
= { .min
= 25000, .max
= 350000 },
106 .vco
= { .min
= 930000, .max
= 1400000 },
107 .n
= { .min
= 3, .max
= 16 },
108 .m
= { .min
= 96, .max
= 140 },
109 .m1
= { .min
= 18, .max
= 26 },
110 .m2
= { .min
= 6, .max
= 16 },
111 .p
= { .min
= 4, .max
= 128 },
112 .p1
= { .min
= 2, .max
= 33 },
113 .p2
= { .dot_limit
= 165000,
114 .p2_slow
= 4, .p2_fast
= 4 },
117 static const intel_limit_t intel_limits_i8xx_lvds
= {
118 .dot
= { .min
= 25000, .max
= 350000 },
119 .vco
= { .min
= 930000, .max
= 1400000 },
120 .n
= { .min
= 3, .max
= 16 },
121 .m
= { .min
= 96, .max
= 140 },
122 .m1
= { .min
= 18, .max
= 26 },
123 .m2
= { .min
= 6, .max
= 16 },
124 .p
= { .min
= 4, .max
= 128 },
125 .p1
= { .min
= 1, .max
= 6 },
126 .p2
= { .dot_limit
= 165000,
127 .p2_slow
= 14, .p2_fast
= 7 },
130 static const intel_limit_t intel_limits_i9xx_sdvo
= {
131 .dot
= { .min
= 20000, .max
= 400000 },
132 .vco
= { .min
= 1400000, .max
= 2800000 },
133 .n
= { .min
= 1, .max
= 6 },
134 .m
= { .min
= 70, .max
= 120 },
135 .m1
= { .min
= 8, .max
= 18 },
136 .m2
= { .min
= 3, .max
= 7 },
137 .p
= { .min
= 5, .max
= 80 },
138 .p1
= { .min
= 1, .max
= 8 },
139 .p2
= { .dot_limit
= 200000,
140 .p2_slow
= 10, .p2_fast
= 5 },
143 static const intel_limit_t intel_limits_i9xx_lvds
= {
144 .dot
= { .min
= 20000, .max
= 400000 },
145 .vco
= { .min
= 1400000, .max
= 2800000 },
146 .n
= { .min
= 1, .max
= 6 },
147 .m
= { .min
= 70, .max
= 120 },
148 .m1
= { .min
= 8, .max
= 18 },
149 .m2
= { .min
= 3, .max
= 7 },
150 .p
= { .min
= 7, .max
= 98 },
151 .p1
= { .min
= 1, .max
= 8 },
152 .p2
= { .dot_limit
= 112000,
153 .p2_slow
= 14, .p2_fast
= 7 },
157 static const intel_limit_t intel_limits_g4x_sdvo
= {
158 .dot
= { .min
= 25000, .max
= 270000 },
159 .vco
= { .min
= 1750000, .max
= 3500000},
160 .n
= { .min
= 1, .max
= 4 },
161 .m
= { .min
= 104, .max
= 138 },
162 .m1
= { .min
= 17, .max
= 23 },
163 .m2
= { .min
= 5, .max
= 11 },
164 .p
= { .min
= 10, .max
= 30 },
165 .p1
= { .min
= 1, .max
= 3},
166 .p2
= { .dot_limit
= 270000,
172 static const intel_limit_t intel_limits_g4x_hdmi
= {
173 .dot
= { .min
= 22000, .max
= 400000 },
174 .vco
= { .min
= 1750000, .max
= 3500000},
175 .n
= { .min
= 1, .max
= 4 },
176 .m
= { .min
= 104, .max
= 138 },
177 .m1
= { .min
= 16, .max
= 23 },
178 .m2
= { .min
= 5, .max
= 11 },
179 .p
= { .min
= 5, .max
= 80 },
180 .p1
= { .min
= 1, .max
= 8},
181 .p2
= { .dot_limit
= 165000,
182 .p2_slow
= 10, .p2_fast
= 5 },
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
186 .dot
= { .min
= 20000, .max
= 115000 },
187 .vco
= { .min
= 1750000, .max
= 3500000 },
188 .n
= { .min
= 1, .max
= 3 },
189 .m
= { .min
= 104, .max
= 138 },
190 .m1
= { .min
= 17, .max
= 23 },
191 .m2
= { .min
= 5, .max
= 11 },
192 .p
= { .min
= 28, .max
= 112 },
193 .p1
= { .min
= 2, .max
= 8 },
194 .p2
= { .dot_limit
= 0,
195 .p2_slow
= 14, .p2_fast
= 14
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
200 .dot
= { .min
= 80000, .max
= 224000 },
201 .vco
= { .min
= 1750000, .max
= 3500000 },
202 .n
= { .min
= 1, .max
= 3 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 17, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 14, .max
= 42 },
207 .p1
= { .min
= 2, .max
= 6 },
208 .p2
= { .dot_limit
= 0,
209 .p2_slow
= 7, .p2_fast
= 7
213 static const intel_limit_t intel_limits_pineview_sdvo
= {
214 .dot
= { .min
= 20000, .max
= 400000},
215 .vco
= { .min
= 1700000, .max
= 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n
= { .min
= 3, .max
= 6 },
218 .m
= { .min
= 2, .max
= 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1
= { .min
= 0, .max
= 0 },
221 .m2
= { .min
= 0, .max
= 254 },
222 .p
= { .min
= 5, .max
= 80 },
223 .p1
= { .min
= 1, .max
= 8 },
224 .p2
= { .dot_limit
= 200000,
225 .p2_slow
= 10, .p2_fast
= 5 },
228 static const intel_limit_t intel_limits_pineview_lvds
= {
229 .dot
= { .min
= 20000, .max
= 400000 },
230 .vco
= { .min
= 1700000, .max
= 3500000 },
231 .n
= { .min
= 3, .max
= 6 },
232 .m
= { .min
= 2, .max
= 256 },
233 .m1
= { .min
= 0, .max
= 0 },
234 .m2
= { .min
= 0, .max
= 254 },
235 .p
= { .min
= 7, .max
= 112 },
236 .p1
= { .min
= 1, .max
= 8 },
237 .p2
= { .dot_limit
= 112000,
238 .p2_slow
= 14, .p2_fast
= 14 },
241 /* Ironlake / Sandybridge
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
246 static const intel_limit_t intel_limits_ironlake_dac
= {
247 .dot
= { .min
= 25000, .max
= 350000 },
248 .vco
= { .min
= 1760000, .max
= 3510000 },
249 .n
= { .min
= 1, .max
= 5 },
250 .m
= { .min
= 79, .max
= 127 },
251 .m1
= { .min
= 12, .max
= 22 },
252 .m2
= { .min
= 5, .max
= 9 },
253 .p
= { .min
= 5, .max
= 80 },
254 .p1
= { .min
= 1, .max
= 8 },
255 .p2
= { .dot_limit
= 225000,
256 .p2_slow
= 10, .p2_fast
= 5 },
259 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
260 .dot
= { .min
= 25000, .max
= 350000 },
261 .vco
= { .min
= 1760000, .max
= 3510000 },
262 .n
= { .min
= 1, .max
= 3 },
263 .m
= { .min
= 79, .max
= 118 },
264 .m1
= { .min
= 12, .max
= 22 },
265 .m2
= { .min
= 5, .max
= 9 },
266 .p
= { .min
= 28, .max
= 112 },
267 .p1
= { .min
= 2, .max
= 8 },
268 .p2
= { .dot_limit
= 225000,
269 .p2_slow
= 14, .p2_fast
= 14 },
272 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
273 .dot
= { .min
= 25000, .max
= 350000 },
274 .vco
= { .min
= 1760000, .max
= 3510000 },
275 .n
= { .min
= 1, .max
= 3 },
276 .m
= { .min
= 79, .max
= 127 },
277 .m1
= { .min
= 12, .max
= 22 },
278 .m2
= { .min
= 5, .max
= 9 },
279 .p
= { .min
= 14, .max
= 56 },
280 .p1
= { .min
= 2, .max
= 8 },
281 .p2
= { .dot_limit
= 225000,
282 .p2_slow
= 7, .p2_fast
= 7 },
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
287 .dot
= { .min
= 25000, .max
= 350000 },
288 .vco
= { .min
= 1760000, .max
= 3510000 },
289 .n
= { .min
= 1, .max
= 2 },
290 .m
= { .min
= 79, .max
= 126 },
291 .m1
= { .min
= 12, .max
= 22 },
292 .m2
= { .min
= 5, .max
= 9 },
293 .p
= { .min
= 28, .max
= 112 },
294 .p1
= { .min
= 2, .max
= 8 },
295 .p2
= { .dot_limit
= 225000,
296 .p2_slow
= 14, .p2_fast
= 14 },
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
300 .dot
= { .min
= 25000, .max
= 350000 },
301 .vco
= { .min
= 1760000, .max
= 3510000 },
302 .n
= { .min
= 1, .max
= 3 },
303 .m
= { .min
= 79, .max
= 126 },
304 .m1
= { .min
= 12, .max
= 22 },
305 .m2
= { .min
= 5, .max
= 9 },
306 .p
= { .min
= 14, .max
= 42 },
307 .p1
= { .min
= 2, .max
= 6 },
308 .p2
= { .dot_limit
= 225000,
309 .p2_slow
= 7, .p2_fast
= 7 },
312 static const intel_limit_t intel_limits_vlv_dac
= {
313 .dot
= { .min
= 25000, .max
= 270000 },
314 .vco
= { .min
= 4000000, .max
= 6000000 },
315 .n
= { .min
= 1, .max
= 7 },
316 .m
= { .min
= 22, .max
= 450 }, /* guess */
317 .m1
= { .min
= 2, .max
= 3 },
318 .m2
= { .min
= 11, .max
= 156 },
319 .p
= { .min
= 10, .max
= 30 },
320 .p1
= { .min
= 1, .max
= 3 },
321 .p2
= { .dot_limit
= 270000,
322 .p2_slow
= 2, .p2_fast
= 20 },
325 static const intel_limit_t intel_limits_vlv_hdmi
= {
326 .dot
= { .min
= 25000, .max
= 270000 },
327 .vco
= { .min
= 4000000, .max
= 6000000 },
328 .n
= { .min
= 1, .max
= 7 },
329 .m
= { .min
= 60, .max
= 300 }, /* guess */
330 .m1
= { .min
= 2, .max
= 3 },
331 .m2
= { .min
= 11, .max
= 156 },
332 .p
= { .min
= 10, .max
= 30 },
333 .p1
= { .min
= 2, .max
= 3 },
334 .p2
= { .dot_limit
= 270000,
335 .p2_slow
= 2, .p2_fast
= 20 },
339 * Returns whether any output on the specified pipe is of the specified type
341 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
343 struct drm_device
*dev
= crtc
->dev
;
344 struct intel_encoder
*encoder
;
346 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
347 if (encoder
->type
== type
)
353 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
356 struct drm_device
*dev
= crtc
->dev
;
357 const intel_limit_t
*limit
;
359 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
360 if (intel_is_dual_link_lvds(dev
)) {
361 if (refclk
== 100000)
362 limit
= &intel_limits_ironlake_dual_lvds_100m
;
364 limit
= &intel_limits_ironlake_dual_lvds
;
366 if (refclk
== 100000)
367 limit
= &intel_limits_ironlake_single_lvds_100m
;
369 limit
= &intel_limits_ironlake_single_lvds
;
372 limit
= &intel_limits_ironlake_dac
;
377 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
379 struct drm_device
*dev
= crtc
->dev
;
380 const intel_limit_t
*limit
;
382 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
383 if (intel_is_dual_link_lvds(dev
))
384 limit
= &intel_limits_g4x_dual_channel_lvds
;
386 limit
= &intel_limits_g4x_single_channel_lvds
;
387 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
388 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
389 limit
= &intel_limits_g4x_hdmi
;
390 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
391 limit
= &intel_limits_g4x_sdvo
;
392 } else /* The option is for other outputs */
393 limit
= &intel_limits_i9xx_sdvo
;
398 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
400 struct drm_device
*dev
= crtc
->dev
;
401 const intel_limit_t
*limit
;
403 if (HAS_PCH_SPLIT(dev
))
404 limit
= intel_ironlake_limit(crtc
, refclk
);
405 else if (IS_G4X(dev
)) {
406 limit
= intel_g4x_limit(crtc
);
407 } else if (IS_PINEVIEW(dev
)) {
408 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
409 limit
= &intel_limits_pineview_lvds
;
411 limit
= &intel_limits_pineview_sdvo
;
412 } else if (IS_VALLEYVIEW(dev
)) {
413 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
414 limit
= &intel_limits_vlv_dac
;
416 limit
= &intel_limits_vlv_hdmi
;
417 } else if (!IS_GEN2(dev
)) {
418 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
419 limit
= &intel_limits_i9xx_lvds
;
421 limit
= &intel_limits_i9xx_sdvo
;
423 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
424 limit
= &intel_limits_i8xx_lvds
;
425 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
426 limit
= &intel_limits_i8xx_dvo
;
428 limit
= &intel_limits_i8xx_dac
;
433 /* m1 is reserved as 0 in Pineview, n is a ring counter */
434 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
436 clock
->m
= clock
->m2
+ 2;
437 clock
->p
= clock
->p1
* clock
->p2
;
438 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
439 clock
->dot
= clock
->vco
/ clock
->p
;
442 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
444 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
447 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
449 clock
->m
= i9xx_dpll_compute_m(clock
);
450 clock
->p
= clock
->p1
* clock
->p2
;
451 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
452 clock
->dot
= clock
->vco
/ clock
->p
;
455 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
461 static bool intel_PLL_is_valid(struct drm_device
*dev
,
462 const intel_limit_t
*limit
,
463 const intel_clock_t
*clock
)
465 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
466 INTELPllInvalid("p1 out of range\n");
467 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
468 INTELPllInvalid("p out of range\n");
469 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
470 INTELPllInvalid("m2 out of range\n");
471 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
472 INTELPllInvalid("m1 out of range\n");
473 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
474 INTELPllInvalid("m1 <= m2\n");
475 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
476 INTELPllInvalid("m out of range\n");
477 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
478 INTELPllInvalid("n out of range\n");
479 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
480 INTELPllInvalid("vco out of range\n");
481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
484 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
485 INTELPllInvalid("dot out of range\n");
491 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
492 int target
, int refclk
, intel_clock_t
*match_clock
,
493 intel_clock_t
*best_clock
)
495 struct drm_device
*dev
= crtc
->dev
;
499 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
505 if (intel_is_dual_link_lvds(dev
))
506 clock
.p2
= limit
->p2
.p2_fast
;
508 clock
.p2
= limit
->p2
.p2_slow
;
510 if (target
< limit
->p2
.dot_limit
)
511 clock
.p2
= limit
->p2
.p2_slow
;
513 clock
.p2
= limit
->p2
.p2_fast
;
516 memset(best_clock
, 0, sizeof(*best_clock
));
518 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
520 for (clock
.m2
= limit
->m2
.min
;
521 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
522 if (clock
.m2
>= clock
.m1
)
524 for (clock
.n
= limit
->n
.min
;
525 clock
.n
<= limit
->n
.max
; clock
.n
++) {
526 for (clock
.p1
= limit
->p1
.min
;
527 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
530 i9xx_clock(refclk
, &clock
);
531 if (!intel_PLL_is_valid(dev
, limit
,
535 clock
.p
!= match_clock
->p
)
538 this_err
= abs(clock
.dot
- target
);
539 if (this_err
< err
) {
548 return (err
!= target
);
552 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
553 int target
, int refclk
, intel_clock_t
*match_clock
,
554 intel_clock_t
*best_clock
)
556 struct drm_device
*dev
= crtc
->dev
;
560 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
566 if (intel_is_dual_link_lvds(dev
))
567 clock
.p2
= limit
->p2
.p2_fast
;
569 clock
.p2
= limit
->p2
.p2_slow
;
571 if (target
< limit
->p2
.dot_limit
)
572 clock
.p2
= limit
->p2
.p2_slow
;
574 clock
.p2
= limit
->p2
.p2_fast
;
577 memset(best_clock
, 0, sizeof(*best_clock
));
579 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
581 for (clock
.m2
= limit
->m2
.min
;
582 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
583 for (clock
.n
= limit
->n
.min
;
584 clock
.n
<= limit
->n
.max
; clock
.n
++) {
585 for (clock
.p1
= limit
->p1
.min
;
586 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
589 pineview_clock(refclk
, &clock
);
590 if (!intel_PLL_is_valid(dev
, limit
,
594 clock
.p
!= match_clock
->p
)
597 this_err
= abs(clock
.dot
- target
);
598 if (this_err
< err
) {
607 return (err
!= target
);
611 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
612 int target
, int refclk
, intel_clock_t
*match_clock
,
613 intel_clock_t
*best_clock
)
615 struct drm_device
*dev
= crtc
->dev
;
619 /* approximately equals target * 0.00585 */
620 int err_most
= (target
>> 8) + (target
>> 9);
623 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
624 if (intel_is_dual_link_lvds(dev
))
625 clock
.p2
= limit
->p2
.p2_fast
;
627 clock
.p2
= limit
->p2
.p2_slow
;
629 if (target
< limit
->p2
.dot_limit
)
630 clock
.p2
= limit
->p2
.p2_slow
;
632 clock
.p2
= limit
->p2
.p2_fast
;
635 memset(best_clock
, 0, sizeof(*best_clock
));
636 max_n
= limit
->n
.max
;
637 /* based on hardware requirement, prefer smaller n to precision */
638 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
639 /* based on hardware requirement, prefere larger m1,m2 */
640 for (clock
.m1
= limit
->m1
.max
;
641 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
642 for (clock
.m2
= limit
->m2
.max
;
643 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
644 for (clock
.p1
= limit
->p1
.max
;
645 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
648 i9xx_clock(refclk
, &clock
);
649 if (!intel_PLL_is_valid(dev
, limit
,
653 this_err
= abs(clock
.dot
- target
);
654 if (this_err
< err_most
) {
668 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
669 int target
, int refclk
, intel_clock_t
*match_clock
,
670 intel_clock_t
*best_clock
)
672 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
674 u32 updrate
, minupdate
, p
;
675 unsigned long bestppm
, ppm
, absppm
;
679 dotclk
= target
* 1000;
682 fastclk
= dotclk
/ (2*100);
685 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
686 bestm1
= bestm2
= bestp1
= bestp2
= 0;
688 /* based on hardware requirement, prefer smaller n to precision */
689 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
690 updrate
= refclk
/ n
;
691 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
692 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
698 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
699 refclk
) / (2*refclk
));
703 if (vco
< limit
->vco
.min
|| vco
>= limit
->vco
.max
)
706 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
707 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
708 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
712 if (absppm
< bestppm
- 10) {
728 best_clock
->n
= bestn
;
729 best_clock
->m1
= bestm1
;
730 best_clock
->m2
= bestm2
;
731 best_clock
->p1
= bestp1
;
732 best_clock
->p2
= bestp2
;
737 bool intel_crtc_active(struct drm_crtc
*crtc
)
739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
741 /* Be paranoid as we can arrive here with only partial
742 * state retrieved from the hardware during setup.
744 * We can ditch the adjusted_mode.crtc_clock check as soon
745 * as Haswell has gained clock readout/fastboot support.
747 * We can ditch the crtc->fb check as soon as we can
748 * properly reconstruct framebuffers.
750 return intel_crtc
->active
&& crtc
->fb
&&
751 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
754 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
757 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
758 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
760 return intel_crtc
->config
.cpu_transcoder
;
763 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
766 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
768 frame
= I915_READ(frame_reg
);
770 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
771 DRM_DEBUG_KMS("vblank wait timed out\n");
775 * intel_wait_for_vblank - wait for vblank on a given pipe
777 * @pipe: pipe to wait for
779 * Wait for vblank to occur on a given pipe. Needed for various bits of
782 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
784 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
785 int pipestat_reg
= PIPESTAT(pipe
);
787 if (INTEL_INFO(dev
)->gen
>= 5) {
788 ironlake_wait_for_vblank(dev
, pipe
);
792 /* Clear existing vblank status. Note this will clear any other
793 * sticky status fields as well.
795 * This races with i915_driver_irq_handler() with the result
796 * that either function could miss a vblank event. Here it is not
797 * fatal, as we will either wait upon the next vblank interrupt or
798 * timeout. Generally speaking intel_wait_for_vblank() is only
799 * called during modeset at which time the GPU should be idle and
800 * should *not* be performing page flips and thus not waiting on
802 * Currently, the result of us stealing a vblank from the irq
803 * handler is that a single frame will be skipped during swapbuffers.
805 I915_WRITE(pipestat_reg
,
806 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
808 /* Wait for vblank interrupt bit to set */
809 if (wait_for(I915_READ(pipestat_reg
) &
810 PIPE_VBLANK_INTERRUPT_STATUS
,
812 DRM_DEBUG_KMS("vblank wait timed out\n");
816 * intel_wait_for_pipe_off - wait for pipe to turn off
818 * @pipe: pipe to wait for
820 * After disabling a pipe, we can't wait for vblank in the usual way,
821 * spinning on the vblank interrupt status bit, since we won't actually
822 * see an interrupt when the pipe is disabled.
825 * wait for the pipe register state bit to turn off
828 * wait for the display line value to settle (it usually
829 * ends up stopping at the start of the next frame).
832 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
834 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
835 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
838 if (INTEL_INFO(dev
)->gen
>= 4) {
839 int reg
= PIPECONF(cpu_transcoder
);
841 /* Wait for the Pipe State to go off */
842 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
844 WARN(1, "pipe_off wait timed out\n");
846 u32 last_line
, line_mask
;
847 int reg
= PIPEDSL(pipe
);
848 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
851 line_mask
= DSL_LINEMASK_GEN2
;
853 line_mask
= DSL_LINEMASK_GEN3
;
855 /* Wait for the display line to settle */
857 last_line
= I915_READ(reg
) & line_mask
;
859 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
860 time_after(timeout
, jiffies
));
861 if (time_after(jiffies
, timeout
))
862 WARN(1, "pipe_off wait timed out\n");
867 * ibx_digital_port_connected - is the specified port connected?
868 * @dev_priv: i915 private structure
869 * @port: the port to test
871 * Returns true if @port is connected, false otherwise.
873 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
874 struct intel_digital_port
*port
)
878 if (HAS_PCH_IBX(dev_priv
->dev
)) {
881 bit
= SDE_PORTB_HOTPLUG
;
884 bit
= SDE_PORTC_HOTPLUG
;
887 bit
= SDE_PORTD_HOTPLUG
;
895 bit
= SDE_PORTB_HOTPLUG_CPT
;
898 bit
= SDE_PORTC_HOTPLUG_CPT
;
901 bit
= SDE_PORTD_HOTPLUG_CPT
;
908 return I915_READ(SDEISR
) & bit
;
911 static const char *state_string(bool enabled
)
913 return enabled
? "on" : "off";
916 /* Only for pre-ILK configs */
917 void assert_pll(struct drm_i915_private
*dev_priv
,
918 enum pipe pipe
, bool state
)
925 val
= I915_READ(reg
);
926 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
927 WARN(cur_state
!= state
,
928 "PLL state assertion failure (expected %s, current %s)\n",
929 state_string(state
), state_string(cur_state
));
932 /* XXX: the dsi pll is shared between MIPI DSI ports */
933 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
938 mutex_lock(&dev_priv
->dpio_lock
);
939 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
940 mutex_unlock(&dev_priv
->dpio_lock
);
942 cur_state
= val
& DSI_PLL_VCO_EN
;
943 WARN(cur_state
!= state
,
944 "DSI PLL state assertion failure (expected %s, current %s)\n",
945 state_string(state
), state_string(cur_state
));
947 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
948 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
950 struct intel_shared_dpll
*
951 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
953 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
955 if (crtc
->config
.shared_dpll
< 0)
958 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
962 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
963 struct intel_shared_dpll
*pll
,
967 struct intel_dpll_hw_state hw_state
;
969 if (HAS_PCH_LPT(dev_priv
->dev
)) {
970 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
975 "asserting DPLL %s with no DPLL\n", state_string(state
)))
978 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
979 WARN(cur_state
!= state
,
980 "%s assertion failure (expected %s, current %s)\n",
981 pll
->name
, state_string(state
), state_string(cur_state
));
984 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
985 enum pipe pipe
, bool state
)
990 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
993 if (HAS_DDI(dev_priv
->dev
)) {
994 /* DDI does not have a specific FDI_TX register */
995 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
996 val
= I915_READ(reg
);
997 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
999 reg
= FDI_TX_CTL(pipe
);
1000 val
= I915_READ(reg
);
1001 cur_state
= !!(val
& FDI_TX_ENABLE
);
1003 WARN(cur_state
!= state
,
1004 "FDI TX state assertion failure (expected %s, current %s)\n",
1005 state_string(state
), state_string(cur_state
));
1007 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1008 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1010 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1011 enum pipe pipe
, bool state
)
1017 reg
= FDI_RX_CTL(pipe
);
1018 val
= I915_READ(reg
);
1019 cur_state
= !!(val
& FDI_RX_ENABLE
);
1020 WARN(cur_state
!= state
,
1021 "FDI RX state assertion failure (expected %s, current %s)\n",
1022 state_string(state
), state_string(cur_state
));
1024 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1025 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1027 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1033 /* ILK FDI PLL is always enabled */
1034 if (dev_priv
->info
->gen
== 5)
1037 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1038 if (HAS_DDI(dev_priv
->dev
))
1041 reg
= FDI_TX_CTL(pipe
);
1042 val
= I915_READ(reg
);
1043 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1046 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1047 enum pipe pipe
, bool state
)
1053 reg
= FDI_RX_CTL(pipe
);
1054 val
= I915_READ(reg
);
1055 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1056 WARN(cur_state
!= state
,
1057 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1058 state_string(state
), state_string(cur_state
));
1061 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1064 int pp_reg
, lvds_reg
;
1066 enum pipe panel_pipe
= PIPE_A
;
1069 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1070 pp_reg
= PCH_PP_CONTROL
;
1071 lvds_reg
= PCH_LVDS
;
1073 pp_reg
= PP_CONTROL
;
1077 val
= I915_READ(pp_reg
);
1078 if (!(val
& PANEL_POWER_ON
) ||
1079 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1082 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1083 panel_pipe
= PIPE_B
;
1085 WARN(panel_pipe
== pipe
&& locked
,
1086 "panel assertion failure, pipe %c regs locked\n",
1090 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1091 enum pipe pipe
, bool state
)
1093 struct drm_device
*dev
= dev_priv
->dev
;
1096 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
1097 cur_state
= I915_READ(CURCNTR_IVB(pipe
)) & CURSOR_MODE
;
1098 else if (IS_845G(dev
) || IS_I865G(dev
))
1099 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1101 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1103 WARN(cur_state
!= state
,
1104 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1105 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1107 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1108 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1110 void assert_pipe(struct drm_i915_private
*dev_priv
,
1111 enum pipe pipe
, bool state
)
1116 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1119 /* if we need the pipe A quirk it must be always on */
1120 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1123 if (!intel_display_power_enabled(dev_priv
->dev
,
1124 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1127 reg
= PIPECONF(cpu_transcoder
);
1128 val
= I915_READ(reg
);
1129 cur_state
= !!(val
& PIPECONF_ENABLE
);
1132 WARN(cur_state
!= state
,
1133 "pipe %c assertion failure (expected %s, current %s)\n",
1134 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1137 static void assert_plane(struct drm_i915_private
*dev_priv
,
1138 enum plane plane
, bool state
)
1144 reg
= DSPCNTR(plane
);
1145 val
= I915_READ(reg
);
1146 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1147 WARN(cur_state
!= state
,
1148 "plane %c assertion failure (expected %s, current %s)\n",
1149 plane_name(plane
), state_string(state
), state_string(cur_state
));
1152 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1153 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1155 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1158 struct drm_device
*dev
= dev_priv
->dev
;
1163 /* Primary planes are fixed to pipes on gen4+ */
1164 if (INTEL_INFO(dev
)->gen
>= 4) {
1165 reg
= DSPCNTR(pipe
);
1166 val
= I915_READ(reg
);
1167 WARN((val
& DISPLAY_PLANE_ENABLE
),
1168 "plane %c assertion failure, should be disabled but not\n",
1173 /* Need to check both planes against the pipe */
1176 val
= I915_READ(reg
);
1177 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1178 DISPPLANE_SEL_PIPE_SHIFT
;
1179 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1180 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1181 plane_name(i
), pipe_name(pipe
));
1185 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1188 struct drm_device
*dev
= dev_priv
->dev
;
1192 if (IS_VALLEYVIEW(dev
)) {
1193 for (i
= 0; i
< dev_priv
->num_plane
; i
++) {
1194 reg
= SPCNTR(pipe
, i
);
1195 val
= I915_READ(reg
);
1196 WARN((val
& SP_ENABLE
),
1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1198 sprite_name(pipe
, i
), pipe_name(pipe
));
1200 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1202 val
= I915_READ(reg
);
1203 WARN((val
& SPRITE_ENABLE
),
1204 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1205 plane_name(pipe
), pipe_name(pipe
));
1206 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1207 reg
= DVSCNTR(pipe
);
1208 val
= I915_READ(reg
);
1209 WARN((val
& DVS_ENABLE
),
1210 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1211 plane_name(pipe
), pipe_name(pipe
));
1215 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1220 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1221 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1225 val
= I915_READ(PCH_DREF_CONTROL
);
1226 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1227 DREF_SUPERSPREAD_SOURCE_MASK
));
1228 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1231 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1238 reg
= PCH_TRANSCONF(pipe
);
1239 val
= I915_READ(reg
);
1240 enabled
= !!(val
& TRANS_ENABLE
);
1242 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1246 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1247 enum pipe pipe
, u32 port_sel
, u32 val
)
1249 if ((val
& DP_PORT_EN
) == 0)
1252 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1253 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1254 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1255 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1258 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1264 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1265 enum pipe pipe
, u32 val
)
1267 if ((val
& SDVO_ENABLE
) == 0)
1270 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1271 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1274 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1280 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1281 enum pipe pipe
, u32 val
)
1283 if ((val
& LVDS_PORT_EN
) == 0)
1286 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1287 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1290 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1296 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1297 enum pipe pipe
, u32 val
)
1299 if ((val
& ADPA_DAC_ENABLE
) == 0)
1301 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1302 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1305 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1311 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1312 enum pipe pipe
, int reg
, u32 port_sel
)
1314 u32 val
= I915_READ(reg
);
1315 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1316 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1317 reg
, pipe_name(pipe
));
1319 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1320 && (val
& DP_PIPEB_SELECT
),
1321 "IBX PCH dp port still using transcoder B\n");
1324 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1325 enum pipe pipe
, int reg
)
1327 u32 val
= I915_READ(reg
);
1328 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1329 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1330 reg
, pipe_name(pipe
));
1332 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1333 && (val
& SDVO_PIPE_B_SELECT
),
1334 "IBX PCH hdmi port still using transcoder B\n");
1337 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1343 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1344 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1345 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1348 val
= I915_READ(reg
);
1349 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1350 "PCH VGA enabled on transcoder %c, should be disabled\n",
1354 val
= I915_READ(reg
);
1355 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1356 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1359 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1360 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1361 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1364 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1366 struct drm_device
*dev
= crtc
->base
.dev
;
1367 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1368 int reg
= DPLL(crtc
->pipe
);
1369 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1371 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1373 /* No really, not for ILK+ */
1374 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1376 /* PLL is protected by panel, make sure we can write it */
1377 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1378 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1380 I915_WRITE(reg
, dpll
);
1384 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1385 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1387 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1388 POSTING_READ(DPLL_MD(crtc
->pipe
));
1390 /* We do this three times for luck */
1391 I915_WRITE(reg
, dpll
);
1393 udelay(150); /* wait for warmup */
1394 I915_WRITE(reg
, dpll
);
1396 udelay(150); /* wait for warmup */
1397 I915_WRITE(reg
, dpll
);
1399 udelay(150); /* wait for warmup */
1402 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1404 struct drm_device
*dev
= crtc
->base
.dev
;
1405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1406 int reg
= DPLL(crtc
->pipe
);
1407 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1409 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1411 /* No really, not for ILK+ */
1412 BUG_ON(dev_priv
->info
->gen
>= 5);
1414 /* PLL is protected by panel, make sure we can write it */
1415 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1416 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1418 I915_WRITE(reg
, dpll
);
1420 /* Wait for the clocks to stabilize. */
1424 if (INTEL_INFO(dev
)->gen
>= 4) {
1425 I915_WRITE(DPLL_MD(crtc
->pipe
),
1426 crtc
->config
.dpll_hw_state
.dpll_md
);
1428 /* The pixel multiplier can only be updated once the
1429 * DPLL is enabled and the clocks are stable.
1431 * So write it again.
1433 I915_WRITE(reg
, dpll
);
1436 /* We do this three times for luck */
1437 I915_WRITE(reg
, dpll
);
1439 udelay(150); /* wait for warmup */
1440 I915_WRITE(reg
, dpll
);
1442 udelay(150); /* wait for warmup */
1443 I915_WRITE(reg
, dpll
);
1445 udelay(150); /* wait for warmup */
1449 * i9xx_disable_pll - disable a PLL
1450 * @dev_priv: i915 private structure
1451 * @pipe: pipe PLL to disable
1453 * Disable the PLL for @pipe, making sure the pipe is off first.
1455 * Note! This is for pre-ILK only.
1457 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1459 /* Don't disable pipe A or pipe A PLLs if needed */
1460 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1463 /* Make sure the pipe isn't still relying on us */
1464 assert_pipe_disabled(dev_priv
, pipe
);
1466 I915_WRITE(DPLL(pipe
), 0);
1467 POSTING_READ(DPLL(pipe
));
1470 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
, int port
)
1475 port_mask
= DPLL_PORTB_READY_MASK
;
1477 port_mask
= DPLL_PORTC_READY_MASK
;
1479 if (wait_for((I915_READ(DPLL(0)) & port_mask
) == 0, 1000))
1480 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1481 'B' + port
, I915_READ(DPLL(0)));
1485 * ironlake_enable_shared_dpll - enable PCH PLL
1486 * @dev_priv: i915 private structure
1487 * @pipe: pipe PLL to enable
1489 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1490 * drives the transcoder clock.
1492 static void ironlake_enable_shared_dpll(struct intel_crtc
*crtc
)
1494 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1495 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1497 /* PCH PLLs only available on ILK, SNB and IVB */
1498 BUG_ON(dev_priv
->info
->gen
< 5);
1499 if (WARN_ON(pll
== NULL
))
1502 if (WARN_ON(pll
->refcount
== 0))
1505 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1506 pll
->name
, pll
->active
, pll
->on
,
1507 crtc
->base
.base
.id
);
1509 if (pll
->active
++) {
1511 assert_shared_dpll_enabled(dev_priv
, pll
);
1516 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1517 pll
->enable(dev_priv
, pll
);
1521 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1523 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1524 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1526 /* PCH only available on ILK+ */
1527 BUG_ON(dev_priv
->info
->gen
< 5);
1528 if (WARN_ON(pll
== NULL
))
1531 if (WARN_ON(pll
->refcount
== 0))
1534 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1535 pll
->name
, pll
->active
, pll
->on
,
1536 crtc
->base
.base
.id
);
1538 if (WARN_ON(pll
->active
== 0)) {
1539 assert_shared_dpll_disabled(dev_priv
, pll
);
1543 assert_shared_dpll_enabled(dev_priv
, pll
);
1548 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1549 pll
->disable(dev_priv
, pll
);
1553 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1556 struct drm_device
*dev
= dev_priv
->dev
;
1557 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1558 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1559 uint32_t reg
, val
, pipeconf_val
;
1561 /* PCH only available on ILK+ */
1562 BUG_ON(dev_priv
->info
->gen
< 5);
1564 /* Make sure PCH DPLL is enabled */
1565 assert_shared_dpll_enabled(dev_priv
,
1566 intel_crtc_to_shared_dpll(intel_crtc
));
1568 /* FDI must be feeding us bits for PCH ports */
1569 assert_fdi_tx_enabled(dev_priv
, pipe
);
1570 assert_fdi_rx_enabled(dev_priv
, pipe
);
1572 if (HAS_PCH_CPT(dev
)) {
1573 /* Workaround: Set the timing override bit before enabling the
1574 * pch transcoder. */
1575 reg
= TRANS_CHICKEN2(pipe
);
1576 val
= I915_READ(reg
);
1577 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1578 I915_WRITE(reg
, val
);
1581 reg
= PCH_TRANSCONF(pipe
);
1582 val
= I915_READ(reg
);
1583 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1585 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1587 * make the BPC in transcoder be consistent with
1588 * that in pipeconf reg.
1590 val
&= ~PIPECONF_BPC_MASK
;
1591 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1594 val
&= ~TRANS_INTERLACE_MASK
;
1595 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1596 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1597 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1598 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1600 val
|= TRANS_INTERLACED
;
1602 val
|= TRANS_PROGRESSIVE
;
1604 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1605 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1606 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1609 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1610 enum transcoder cpu_transcoder
)
1612 u32 val
, pipeconf_val
;
1614 /* PCH only available on ILK+ */
1615 BUG_ON(dev_priv
->info
->gen
< 5);
1617 /* FDI must be feeding us bits for PCH ports */
1618 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1619 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1621 /* Workaround: set timing override bit. */
1622 val
= I915_READ(_TRANSA_CHICKEN2
);
1623 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1624 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1627 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1629 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1630 PIPECONF_INTERLACED_ILK
)
1631 val
|= TRANS_INTERLACED
;
1633 val
|= TRANS_PROGRESSIVE
;
1635 I915_WRITE(LPT_TRANSCONF
, val
);
1636 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1637 DRM_ERROR("Failed to enable PCH transcoder\n");
1640 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1643 struct drm_device
*dev
= dev_priv
->dev
;
1646 /* FDI relies on the transcoder */
1647 assert_fdi_tx_disabled(dev_priv
, pipe
);
1648 assert_fdi_rx_disabled(dev_priv
, pipe
);
1650 /* Ports must be off as well */
1651 assert_pch_ports_disabled(dev_priv
, pipe
);
1653 reg
= PCH_TRANSCONF(pipe
);
1654 val
= I915_READ(reg
);
1655 val
&= ~TRANS_ENABLE
;
1656 I915_WRITE(reg
, val
);
1657 /* wait for PCH transcoder off, transcoder state */
1658 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1659 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1661 if (!HAS_PCH_IBX(dev
)) {
1662 /* Workaround: Clear the timing override chicken bit again. */
1663 reg
= TRANS_CHICKEN2(pipe
);
1664 val
= I915_READ(reg
);
1665 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1666 I915_WRITE(reg
, val
);
1670 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1674 val
= I915_READ(LPT_TRANSCONF
);
1675 val
&= ~TRANS_ENABLE
;
1676 I915_WRITE(LPT_TRANSCONF
, val
);
1677 /* wait for PCH transcoder off, transcoder state */
1678 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1679 DRM_ERROR("Failed to disable PCH transcoder\n");
1681 /* Workaround: clear timing override bit. */
1682 val
= I915_READ(_TRANSA_CHICKEN2
);
1683 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1684 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1688 * intel_enable_pipe - enable a pipe, asserting requirements
1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to enable
1691 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1693 * Enable @pipe, making sure that various hardware specific requirements
1694 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1696 * @pipe should be %PIPE_A or %PIPE_B.
1698 * Will wait until the pipe is actually running (i.e. first vblank) before
1701 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1702 bool pch_port
, bool dsi
)
1704 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1706 enum pipe pch_transcoder
;
1710 assert_planes_disabled(dev_priv
, pipe
);
1711 assert_cursor_disabled(dev_priv
, pipe
);
1712 assert_sprites_disabled(dev_priv
, pipe
);
1714 if (HAS_PCH_LPT(dev_priv
->dev
))
1715 pch_transcoder
= TRANSCODER_A
;
1717 pch_transcoder
= pipe
;
1720 * A pipe without a PLL won't actually be able to drive bits from
1721 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1724 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1726 assert_dsi_pll_enabled(dev_priv
);
1728 assert_pll_enabled(dev_priv
, pipe
);
1731 /* if driving the PCH, we need FDI enabled */
1732 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
1733 assert_fdi_tx_pll_enabled(dev_priv
,
1734 (enum pipe
) cpu_transcoder
);
1736 /* FIXME: assert CPU port conditions for SNB+ */
1739 reg
= PIPECONF(cpu_transcoder
);
1740 val
= I915_READ(reg
);
1741 if (val
& PIPECONF_ENABLE
)
1744 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1745 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1749 * intel_disable_pipe - disable a pipe, asserting requirements
1750 * @dev_priv: i915 private structure
1751 * @pipe: pipe to disable
1753 * Disable @pipe, making sure that various hardware specific requirements
1754 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1756 * @pipe should be %PIPE_A or %PIPE_B.
1758 * Will wait until the pipe has shut down before returning.
1760 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1763 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1769 * Make sure planes won't keep trying to pump pixels to us,
1770 * or we might hang the display.
1772 assert_planes_disabled(dev_priv
, pipe
);
1773 assert_cursor_disabled(dev_priv
, pipe
);
1774 assert_sprites_disabled(dev_priv
, pipe
);
1776 /* Don't disable pipe A or pipe A PLLs if needed */
1777 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1780 reg
= PIPECONF(cpu_transcoder
);
1781 val
= I915_READ(reg
);
1782 if ((val
& PIPECONF_ENABLE
) == 0)
1785 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1786 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1790 * Plane regs are double buffered, going from enabled->disabled needs a
1791 * trigger in order to latch. The display address reg provides this.
1793 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1796 if (dev_priv
->info
->gen
>= 4)
1797 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1799 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1803 * intel_enable_plane - enable a display plane on a given pipe
1804 * @dev_priv: i915 private structure
1805 * @plane: plane to enable
1806 * @pipe: pipe being fed
1808 * Enable @plane on @pipe, making sure that @pipe is running first.
1810 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1811 enum plane plane
, enum pipe pipe
)
1816 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1817 assert_pipe_enabled(dev_priv
, pipe
);
1819 reg
= DSPCNTR(plane
);
1820 val
= I915_READ(reg
);
1821 if (val
& DISPLAY_PLANE_ENABLE
)
1824 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1825 intel_flush_display_plane(dev_priv
, plane
);
1826 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1830 * intel_disable_plane - disable a display plane
1831 * @dev_priv: i915 private structure
1832 * @plane: plane to disable
1833 * @pipe: pipe consuming the data
1835 * Disable @plane; should be an independent operation.
1837 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1838 enum plane plane
, enum pipe pipe
)
1843 reg
= DSPCNTR(plane
);
1844 val
= I915_READ(reg
);
1845 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1848 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1849 intel_flush_display_plane(dev_priv
, plane
);
1850 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1853 static bool need_vtd_wa(struct drm_device
*dev
)
1855 #ifdef CONFIG_INTEL_IOMMU
1856 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
1863 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1864 struct drm_i915_gem_object
*obj
,
1865 struct intel_ring_buffer
*pipelined
)
1867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1871 switch (obj
->tiling_mode
) {
1872 case I915_TILING_NONE
:
1873 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1874 alignment
= 128 * 1024;
1875 else if (INTEL_INFO(dev
)->gen
>= 4)
1876 alignment
= 4 * 1024;
1878 alignment
= 64 * 1024;
1881 /* pin() will align the object as required by fence */
1885 /* Despite that we check this in framebuffer_init userspace can
1886 * screw us over and change the tiling after the fact. Only
1887 * pinned buffers can't change their tiling. */
1888 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1894 /* Note that the w/a also requires 64 PTE of padding following the
1895 * bo. We currently fill all unused PTE with the shadow page and so
1896 * we should always have valid PTE following the scanout preventing
1899 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
1900 alignment
= 256 * 1024;
1902 dev_priv
->mm
.interruptible
= false;
1903 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1905 goto err_interruptible
;
1907 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1908 * fence, whereas 965+ only requires a fence if using
1909 * framebuffer compression. For simplicity, we always install
1910 * a fence as the cost is not that onerous.
1912 ret
= i915_gem_object_get_fence(obj
);
1916 i915_gem_object_pin_fence(obj
);
1918 dev_priv
->mm
.interruptible
= true;
1922 i915_gem_object_unpin_from_display_plane(obj
);
1924 dev_priv
->mm
.interruptible
= true;
1928 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1930 i915_gem_object_unpin_fence(obj
);
1931 i915_gem_object_unpin_from_display_plane(obj
);
1934 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1935 * is assumed to be a power-of-two. */
1936 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
1937 unsigned int tiling_mode
,
1941 if (tiling_mode
!= I915_TILING_NONE
) {
1942 unsigned int tile_rows
, tiles
;
1947 tiles
= *x
/ (512/cpp
);
1950 return tile_rows
* pitch
* 8 + tiles
* 4096;
1952 unsigned int offset
;
1954 offset
= *y
* pitch
+ *x
* cpp
;
1956 *x
= (offset
& 4095) / cpp
;
1957 return offset
& -4096;
1961 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1964 struct drm_device
*dev
= crtc
->dev
;
1965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1966 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1967 struct intel_framebuffer
*intel_fb
;
1968 struct drm_i915_gem_object
*obj
;
1969 int plane
= intel_crtc
->plane
;
1970 unsigned long linear_offset
;
1979 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
1983 intel_fb
= to_intel_framebuffer(fb
);
1984 obj
= intel_fb
->obj
;
1986 reg
= DSPCNTR(plane
);
1987 dspcntr
= I915_READ(reg
);
1988 /* Mask out pixel format bits in case we change it */
1989 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1990 switch (fb
->pixel_format
) {
1992 dspcntr
|= DISPPLANE_8BPP
;
1994 case DRM_FORMAT_XRGB1555
:
1995 case DRM_FORMAT_ARGB1555
:
1996 dspcntr
|= DISPPLANE_BGRX555
;
1998 case DRM_FORMAT_RGB565
:
1999 dspcntr
|= DISPPLANE_BGRX565
;
2001 case DRM_FORMAT_XRGB8888
:
2002 case DRM_FORMAT_ARGB8888
:
2003 dspcntr
|= DISPPLANE_BGRX888
;
2005 case DRM_FORMAT_XBGR8888
:
2006 case DRM_FORMAT_ABGR8888
:
2007 dspcntr
|= DISPPLANE_RGBX888
;
2009 case DRM_FORMAT_XRGB2101010
:
2010 case DRM_FORMAT_ARGB2101010
:
2011 dspcntr
|= DISPPLANE_BGRX101010
;
2013 case DRM_FORMAT_XBGR2101010
:
2014 case DRM_FORMAT_ABGR2101010
:
2015 dspcntr
|= DISPPLANE_RGBX101010
;
2021 if (INTEL_INFO(dev
)->gen
>= 4) {
2022 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2023 dspcntr
|= DISPPLANE_TILED
;
2025 dspcntr
&= ~DISPPLANE_TILED
;
2029 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2031 I915_WRITE(reg
, dspcntr
);
2033 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2035 if (INTEL_INFO(dev
)->gen
>= 4) {
2036 intel_crtc
->dspaddr_offset
=
2037 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2038 fb
->bits_per_pixel
/ 8,
2040 linear_offset
-= intel_crtc
->dspaddr_offset
;
2042 intel_crtc
->dspaddr_offset
= linear_offset
;
2045 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2046 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2048 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2049 if (INTEL_INFO(dev
)->gen
>= 4) {
2050 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2051 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2052 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2053 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2055 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2061 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2062 struct drm_framebuffer
*fb
, int x
, int y
)
2064 struct drm_device
*dev
= crtc
->dev
;
2065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2066 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2067 struct intel_framebuffer
*intel_fb
;
2068 struct drm_i915_gem_object
*obj
;
2069 int plane
= intel_crtc
->plane
;
2070 unsigned long linear_offset
;
2080 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane
));
2084 intel_fb
= to_intel_framebuffer(fb
);
2085 obj
= intel_fb
->obj
;
2087 reg
= DSPCNTR(plane
);
2088 dspcntr
= I915_READ(reg
);
2089 /* Mask out pixel format bits in case we change it */
2090 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2091 switch (fb
->pixel_format
) {
2093 dspcntr
|= DISPPLANE_8BPP
;
2095 case DRM_FORMAT_RGB565
:
2096 dspcntr
|= DISPPLANE_BGRX565
;
2098 case DRM_FORMAT_XRGB8888
:
2099 case DRM_FORMAT_ARGB8888
:
2100 dspcntr
|= DISPPLANE_BGRX888
;
2102 case DRM_FORMAT_XBGR8888
:
2103 case DRM_FORMAT_ABGR8888
:
2104 dspcntr
|= DISPPLANE_RGBX888
;
2106 case DRM_FORMAT_XRGB2101010
:
2107 case DRM_FORMAT_ARGB2101010
:
2108 dspcntr
|= DISPPLANE_BGRX101010
;
2110 case DRM_FORMAT_XBGR2101010
:
2111 case DRM_FORMAT_ABGR2101010
:
2112 dspcntr
|= DISPPLANE_RGBX101010
;
2118 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2119 dspcntr
|= DISPPLANE_TILED
;
2121 dspcntr
&= ~DISPPLANE_TILED
;
2123 if (IS_HASWELL(dev
))
2124 dspcntr
&= ~DISPPLANE_TRICKLE_FEED_DISABLE
;
2126 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2128 I915_WRITE(reg
, dspcntr
);
2130 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2131 intel_crtc
->dspaddr_offset
=
2132 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2133 fb
->bits_per_pixel
/ 8,
2135 linear_offset
-= intel_crtc
->dspaddr_offset
;
2137 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2138 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2140 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2141 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2142 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2143 if (IS_HASWELL(dev
)) {
2144 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2146 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2147 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2154 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2156 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2157 int x
, int y
, enum mode_set_atomic state
)
2159 struct drm_device
*dev
= crtc
->dev
;
2160 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2162 if (dev_priv
->display
.disable_fbc
)
2163 dev_priv
->display
.disable_fbc(dev
);
2164 intel_increase_pllclock(crtc
);
2166 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2169 void intel_display_handle_reset(struct drm_device
*dev
)
2171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2172 struct drm_crtc
*crtc
;
2175 * Flips in the rings have been nuked by the reset,
2176 * so complete all pending flips so that user space
2177 * will get its events and not get stuck.
2179 * Also update the base address of all primary
2180 * planes to the the last fb to make sure we're
2181 * showing the correct fb after a reset.
2183 * Need to make two loops over the crtcs so that we
2184 * don't try to grab a crtc mutex before the
2185 * pending_flip_queue really got woken up.
2188 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2190 enum plane plane
= intel_crtc
->plane
;
2192 intel_prepare_page_flip(dev
, plane
);
2193 intel_finish_page_flip_plane(dev
, plane
);
2196 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
2197 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2199 mutex_lock(&crtc
->mutex
);
2200 if (intel_crtc
->active
)
2201 dev_priv
->display
.update_plane(crtc
, crtc
->fb
,
2203 mutex_unlock(&crtc
->mutex
);
2208 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2210 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2211 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2212 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2215 /* Big Hammer, we also need to ensure that any pending
2216 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2217 * current scanout is retired before unpinning the old
2220 * This should only fail upon a hung GPU, in which case we
2221 * can safely continue.
2223 dev_priv
->mm
.interruptible
= false;
2224 ret
= i915_gem_object_finish_gpu(obj
);
2225 dev_priv
->mm
.interruptible
= was_interruptible
;
2230 static void intel_crtc_update_sarea_pos(struct drm_crtc
*crtc
, int x
, int y
)
2232 struct drm_device
*dev
= crtc
->dev
;
2233 struct drm_i915_master_private
*master_priv
;
2234 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2236 if (!dev
->primary
->master
)
2239 master_priv
= dev
->primary
->master
->driver_priv
;
2240 if (!master_priv
->sarea_priv
)
2243 switch (intel_crtc
->pipe
) {
2245 master_priv
->sarea_priv
->pipeA_x
= x
;
2246 master_priv
->sarea_priv
->pipeA_y
= y
;
2249 master_priv
->sarea_priv
->pipeB_x
= x
;
2250 master_priv
->sarea_priv
->pipeB_y
= y
;
2258 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2259 struct drm_framebuffer
*fb
)
2261 struct drm_device
*dev
= crtc
->dev
;
2262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2263 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2264 struct drm_framebuffer
*old_fb
;
2269 DRM_ERROR("No FB bound\n");
2273 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2274 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2275 plane_name(intel_crtc
->plane
),
2276 INTEL_INFO(dev
)->num_pipes
);
2280 mutex_lock(&dev
->struct_mutex
);
2281 ret
= intel_pin_and_fence_fb_obj(dev
,
2282 to_intel_framebuffer(fb
)->obj
,
2285 mutex_unlock(&dev
->struct_mutex
);
2286 DRM_ERROR("pin & fence failed\n");
2290 /* Update pipe size and adjust fitter if needed */
2291 if (i915_fastboot
) {
2292 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2293 ((crtc
->mode
.hdisplay
- 1) << 16) |
2294 (crtc
->mode
.vdisplay
- 1));
2295 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2296 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2297 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2298 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2299 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2300 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2304 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2306 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2307 mutex_unlock(&dev
->struct_mutex
);
2308 DRM_ERROR("failed to update base address\n");
2318 if (intel_crtc
->active
&& old_fb
!= fb
)
2319 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2323 intel_update_fbc(dev
);
2324 intel_edp_psr_update(dev
);
2325 mutex_unlock(&dev
->struct_mutex
);
2327 intel_crtc_update_sarea_pos(crtc
, x
, y
);
2332 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2334 struct drm_device
*dev
= crtc
->dev
;
2335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2336 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2337 int pipe
= intel_crtc
->pipe
;
2340 /* enable normal train */
2341 reg
= FDI_TX_CTL(pipe
);
2342 temp
= I915_READ(reg
);
2343 if (IS_IVYBRIDGE(dev
)) {
2344 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2345 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2347 temp
&= ~FDI_LINK_TRAIN_NONE
;
2348 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2350 I915_WRITE(reg
, temp
);
2352 reg
= FDI_RX_CTL(pipe
);
2353 temp
= I915_READ(reg
);
2354 if (HAS_PCH_CPT(dev
)) {
2355 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2356 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2358 temp
&= ~FDI_LINK_TRAIN_NONE
;
2359 temp
|= FDI_LINK_TRAIN_NONE
;
2361 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2363 /* wait one idle pattern time */
2367 /* IVB wants error correction enabled */
2368 if (IS_IVYBRIDGE(dev
))
2369 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2370 FDI_FE_ERRC_ENABLE
);
2373 static bool pipe_has_enabled_pch(struct intel_crtc
*intel_crtc
)
2375 return intel_crtc
->base
.enabled
&& intel_crtc
->config
.has_pch_encoder
;
2378 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2381 struct intel_crtc
*pipe_B_crtc
=
2382 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2383 struct intel_crtc
*pipe_C_crtc
=
2384 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2388 * When everything is off disable fdi C so that we could enable fdi B
2389 * with all lanes. Note that we don't care about enabled pipes without
2390 * an enabled pch encoder.
2392 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2393 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2395 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2397 temp
= I915_READ(SOUTH_CHICKEN1
);
2398 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2399 DRM_DEBUG_KMS("disabling fdi C rx\n");
2400 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2404 /* The FDI link training functions for ILK/Ibexpeak. */
2405 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2407 struct drm_device
*dev
= crtc
->dev
;
2408 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2409 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2410 int pipe
= intel_crtc
->pipe
;
2411 int plane
= intel_crtc
->plane
;
2412 u32 reg
, temp
, tries
;
2414 /* FDI needs bits from pipe & plane first */
2415 assert_pipe_enabled(dev_priv
, pipe
);
2416 assert_plane_enabled(dev_priv
, plane
);
2418 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2420 reg
= FDI_RX_IMR(pipe
);
2421 temp
= I915_READ(reg
);
2422 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2423 temp
&= ~FDI_RX_BIT_LOCK
;
2424 I915_WRITE(reg
, temp
);
2428 /* enable CPU FDI TX and PCH FDI RX */
2429 reg
= FDI_TX_CTL(pipe
);
2430 temp
= I915_READ(reg
);
2431 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2432 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2433 temp
&= ~FDI_LINK_TRAIN_NONE
;
2434 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2435 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2437 reg
= FDI_RX_CTL(pipe
);
2438 temp
= I915_READ(reg
);
2439 temp
&= ~FDI_LINK_TRAIN_NONE
;
2440 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2441 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2446 /* Ironlake workaround, enable clock pointer after FDI enable*/
2447 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2448 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2449 FDI_RX_PHASE_SYNC_POINTER_EN
);
2451 reg
= FDI_RX_IIR(pipe
);
2452 for (tries
= 0; tries
< 5; tries
++) {
2453 temp
= I915_READ(reg
);
2454 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2456 if ((temp
& FDI_RX_BIT_LOCK
)) {
2457 DRM_DEBUG_KMS("FDI train 1 done.\n");
2458 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2463 DRM_ERROR("FDI train 1 fail!\n");
2466 reg
= FDI_TX_CTL(pipe
);
2467 temp
= I915_READ(reg
);
2468 temp
&= ~FDI_LINK_TRAIN_NONE
;
2469 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2470 I915_WRITE(reg
, temp
);
2472 reg
= FDI_RX_CTL(pipe
);
2473 temp
= I915_READ(reg
);
2474 temp
&= ~FDI_LINK_TRAIN_NONE
;
2475 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2476 I915_WRITE(reg
, temp
);
2481 reg
= FDI_RX_IIR(pipe
);
2482 for (tries
= 0; tries
< 5; tries
++) {
2483 temp
= I915_READ(reg
);
2484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2486 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2487 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2488 DRM_DEBUG_KMS("FDI train 2 done.\n");
2493 DRM_ERROR("FDI train 2 fail!\n");
2495 DRM_DEBUG_KMS("FDI train done\n");
2499 static const int snb_b_fdi_train_param
[] = {
2500 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2501 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2502 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2503 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2506 /* The FDI link training functions for SNB/Cougarpoint. */
2507 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2509 struct drm_device
*dev
= crtc
->dev
;
2510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2511 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2512 int pipe
= intel_crtc
->pipe
;
2513 u32 reg
, temp
, i
, retry
;
2515 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2517 reg
= FDI_RX_IMR(pipe
);
2518 temp
= I915_READ(reg
);
2519 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2520 temp
&= ~FDI_RX_BIT_LOCK
;
2521 I915_WRITE(reg
, temp
);
2526 /* enable CPU FDI TX and PCH FDI RX */
2527 reg
= FDI_TX_CTL(pipe
);
2528 temp
= I915_READ(reg
);
2529 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2530 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2531 temp
&= ~FDI_LINK_TRAIN_NONE
;
2532 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2533 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2535 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2536 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2538 I915_WRITE(FDI_RX_MISC(pipe
),
2539 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2541 reg
= FDI_RX_CTL(pipe
);
2542 temp
= I915_READ(reg
);
2543 if (HAS_PCH_CPT(dev
)) {
2544 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2545 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2547 temp
&= ~FDI_LINK_TRAIN_NONE
;
2548 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2550 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2555 for (i
= 0; i
< 4; i
++) {
2556 reg
= FDI_TX_CTL(pipe
);
2557 temp
= I915_READ(reg
);
2558 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2559 temp
|= snb_b_fdi_train_param
[i
];
2560 I915_WRITE(reg
, temp
);
2565 for (retry
= 0; retry
< 5; retry
++) {
2566 reg
= FDI_RX_IIR(pipe
);
2567 temp
= I915_READ(reg
);
2568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2569 if (temp
& FDI_RX_BIT_LOCK
) {
2570 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2571 DRM_DEBUG_KMS("FDI train 1 done.\n");
2580 DRM_ERROR("FDI train 1 fail!\n");
2583 reg
= FDI_TX_CTL(pipe
);
2584 temp
= I915_READ(reg
);
2585 temp
&= ~FDI_LINK_TRAIN_NONE
;
2586 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2588 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2590 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2592 I915_WRITE(reg
, temp
);
2594 reg
= FDI_RX_CTL(pipe
);
2595 temp
= I915_READ(reg
);
2596 if (HAS_PCH_CPT(dev
)) {
2597 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2598 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2600 temp
&= ~FDI_LINK_TRAIN_NONE
;
2601 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2603 I915_WRITE(reg
, temp
);
2608 for (i
= 0; i
< 4; i
++) {
2609 reg
= FDI_TX_CTL(pipe
);
2610 temp
= I915_READ(reg
);
2611 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2612 temp
|= snb_b_fdi_train_param
[i
];
2613 I915_WRITE(reg
, temp
);
2618 for (retry
= 0; retry
< 5; retry
++) {
2619 reg
= FDI_RX_IIR(pipe
);
2620 temp
= I915_READ(reg
);
2621 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2622 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2623 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2624 DRM_DEBUG_KMS("FDI train 2 done.\n");
2633 DRM_ERROR("FDI train 2 fail!\n");
2635 DRM_DEBUG_KMS("FDI train done.\n");
2638 /* Manual link training for Ivy Bridge A0 parts */
2639 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2641 struct drm_device
*dev
= crtc
->dev
;
2642 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2643 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2644 int pipe
= intel_crtc
->pipe
;
2645 u32 reg
, temp
, i
, j
;
2647 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2649 reg
= FDI_RX_IMR(pipe
);
2650 temp
= I915_READ(reg
);
2651 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2652 temp
&= ~FDI_RX_BIT_LOCK
;
2653 I915_WRITE(reg
, temp
);
2658 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2659 I915_READ(FDI_RX_IIR(pipe
)));
2661 /* Try each vswing and preemphasis setting twice before moving on */
2662 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
2663 /* disable first in case we need to retry */
2664 reg
= FDI_TX_CTL(pipe
);
2665 temp
= I915_READ(reg
);
2666 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2667 temp
&= ~FDI_TX_ENABLE
;
2668 I915_WRITE(reg
, temp
);
2670 reg
= FDI_RX_CTL(pipe
);
2671 temp
= I915_READ(reg
);
2672 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2673 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2674 temp
&= ~FDI_RX_ENABLE
;
2675 I915_WRITE(reg
, temp
);
2677 /* enable CPU FDI TX and PCH FDI RX */
2678 reg
= FDI_TX_CTL(pipe
);
2679 temp
= I915_READ(reg
);
2680 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2681 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2682 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2683 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2684 temp
|= snb_b_fdi_train_param
[j
/2];
2685 temp
|= FDI_COMPOSITE_SYNC
;
2686 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2688 I915_WRITE(FDI_RX_MISC(pipe
),
2689 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2691 reg
= FDI_RX_CTL(pipe
);
2692 temp
= I915_READ(reg
);
2693 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2694 temp
|= FDI_COMPOSITE_SYNC
;
2695 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2698 udelay(1); /* should be 0.5us */
2700 for (i
= 0; i
< 4; i
++) {
2701 reg
= FDI_RX_IIR(pipe
);
2702 temp
= I915_READ(reg
);
2703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2705 if (temp
& FDI_RX_BIT_LOCK
||
2706 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2707 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2708 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2712 udelay(1); /* should be 0.5us */
2715 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
2720 reg
= FDI_TX_CTL(pipe
);
2721 temp
= I915_READ(reg
);
2722 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2723 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2724 I915_WRITE(reg
, temp
);
2726 reg
= FDI_RX_CTL(pipe
);
2727 temp
= I915_READ(reg
);
2728 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2729 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2730 I915_WRITE(reg
, temp
);
2733 udelay(2); /* should be 1.5us */
2735 for (i
= 0; i
< 4; i
++) {
2736 reg
= FDI_RX_IIR(pipe
);
2737 temp
= I915_READ(reg
);
2738 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2740 if (temp
& FDI_RX_SYMBOL_LOCK
||
2741 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
2742 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2743 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2747 udelay(2); /* should be 1.5us */
2750 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
2754 DRM_DEBUG_KMS("FDI train done.\n");
2757 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2759 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2760 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2761 int pipe
= intel_crtc
->pipe
;
2765 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2766 reg
= FDI_RX_CTL(pipe
);
2767 temp
= I915_READ(reg
);
2768 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
2769 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2770 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2771 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2776 /* Switch from Rawclk to PCDclk */
2777 temp
= I915_READ(reg
);
2778 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2783 /* Enable CPU FDI TX PLL, always on for Ironlake */
2784 reg
= FDI_TX_CTL(pipe
);
2785 temp
= I915_READ(reg
);
2786 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2787 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2794 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2796 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2798 int pipe
= intel_crtc
->pipe
;
2801 /* Switch from PCDclk to Rawclk */
2802 reg
= FDI_RX_CTL(pipe
);
2803 temp
= I915_READ(reg
);
2804 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2806 /* Disable CPU FDI TX PLL */
2807 reg
= FDI_TX_CTL(pipe
);
2808 temp
= I915_READ(reg
);
2809 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2814 reg
= FDI_RX_CTL(pipe
);
2815 temp
= I915_READ(reg
);
2816 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2818 /* Wait for the clocks to turn off. */
2823 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2825 struct drm_device
*dev
= crtc
->dev
;
2826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2827 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2828 int pipe
= intel_crtc
->pipe
;
2831 /* disable CPU FDI tx and PCH FDI rx */
2832 reg
= FDI_TX_CTL(pipe
);
2833 temp
= I915_READ(reg
);
2834 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2837 reg
= FDI_RX_CTL(pipe
);
2838 temp
= I915_READ(reg
);
2839 temp
&= ~(0x7 << 16);
2840 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2841 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2846 /* Ironlake workaround, disable clock pointer after downing FDI */
2847 if (HAS_PCH_IBX(dev
)) {
2848 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2851 /* still set train pattern 1 */
2852 reg
= FDI_TX_CTL(pipe
);
2853 temp
= I915_READ(reg
);
2854 temp
&= ~FDI_LINK_TRAIN_NONE
;
2855 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2856 I915_WRITE(reg
, temp
);
2858 reg
= FDI_RX_CTL(pipe
);
2859 temp
= I915_READ(reg
);
2860 if (HAS_PCH_CPT(dev
)) {
2861 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2862 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2864 temp
&= ~FDI_LINK_TRAIN_NONE
;
2865 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2867 /* BPC in FDI rx is consistent with that in PIPECONF */
2868 temp
&= ~(0x07 << 16);
2869 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
2870 I915_WRITE(reg
, temp
);
2876 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2878 struct drm_device
*dev
= crtc
->dev
;
2879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2880 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2881 unsigned long flags
;
2884 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2885 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2888 spin_lock_irqsave(&dev
->event_lock
, flags
);
2889 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2890 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2895 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2897 struct drm_device
*dev
= crtc
->dev
;
2898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2900 if (crtc
->fb
== NULL
)
2903 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
2905 wait_event(dev_priv
->pending_flip_queue
,
2906 !intel_crtc_has_pending_flip(crtc
));
2908 mutex_lock(&dev
->struct_mutex
);
2909 intel_finish_fb(crtc
->fb
);
2910 mutex_unlock(&dev
->struct_mutex
);
2913 /* Program iCLKIP clock to the desired frequency */
2914 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2916 struct drm_device
*dev
= crtc
->dev
;
2917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2918 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
2919 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2922 mutex_lock(&dev_priv
->dpio_lock
);
2924 /* It is necessary to ungate the pixclk gate prior to programming
2925 * the divisors, and gate it back when it is done.
2927 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2929 /* Disable SSCCTL */
2930 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2931 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
2935 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2936 if (clock
== 20000) {
2941 /* The iCLK virtual clock root frequency is in MHz,
2942 * but the adjusted_mode->crtc_clock in in KHz. To get the
2943 * divisors, it is necessary to divide one by another, so we
2944 * convert the virtual clock precision to KHz here for higher
2947 u32 iclk_virtual_root_freq
= 172800 * 1000;
2948 u32 iclk_pi_range
= 64;
2949 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2951 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
2952 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2953 pi_value
= desired_divisor
% iclk_pi_range
;
2956 divsel
= msb_divisor_value
- 2;
2957 phaseinc
= pi_value
;
2960 /* This should not happen with any sane values */
2961 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2962 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2963 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2964 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2966 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2973 /* Program SSCDIVINTPHASE6 */
2974 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
2975 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2976 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2977 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2978 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2979 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2980 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2981 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
2983 /* Program SSCAUXDIV */
2984 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
2985 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2986 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2987 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
2989 /* Enable modulator and associated divider */
2990 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
2991 temp
&= ~SBI_SSCCTL_DISABLE
;
2992 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
2994 /* Wait for initialization time */
2997 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2999 mutex_unlock(&dev_priv
->dpio_lock
);
3002 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3003 enum pipe pch_transcoder
)
3005 struct drm_device
*dev
= crtc
->base
.dev
;
3006 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3007 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3009 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3010 I915_READ(HTOTAL(cpu_transcoder
)));
3011 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3012 I915_READ(HBLANK(cpu_transcoder
)));
3013 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3014 I915_READ(HSYNC(cpu_transcoder
)));
3016 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3017 I915_READ(VTOTAL(cpu_transcoder
)));
3018 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3019 I915_READ(VBLANK(cpu_transcoder
)));
3020 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3021 I915_READ(VSYNC(cpu_transcoder
)));
3022 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3023 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3027 * Enable PCH resources required for PCH ports:
3029 * - FDI training & RX/TX
3030 * - update transcoder timings
3031 * - DP transcoding bits
3034 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3036 struct drm_device
*dev
= crtc
->dev
;
3037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3039 int pipe
= intel_crtc
->pipe
;
3042 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3044 /* Write the TU size bits before fdi link training, so that error
3045 * detection works. */
3046 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3047 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3049 /* For PCH output, training FDI link */
3050 dev_priv
->display
.fdi_link_train(crtc
);
3052 /* We need to program the right clock selection before writing the pixel
3053 * mutliplier into the DPLL. */
3054 if (HAS_PCH_CPT(dev
)) {
3057 temp
= I915_READ(PCH_DPLL_SEL
);
3058 temp
|= TRANS_DPLL_ENABLE(pipe
);
3059 sel
= TRANS_DPLLB_SEL(pipe
);
3060 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3064 I915_WRITE(PCH_DPLL_SEL
, temp
);
3067 /* XXX: pch pll's can be enabled any time before we enable the PCH
3068 * transcoder, and we actually should do this to not upset any PCH
3069 * transcoder that already use the clock when we share it.
3071 * Note that enable_shared_dpll tries to do the right thing, but
3072 * get_shared_dpll unconditionally resets the pll - we need that to have
3073 * the right LVDS enable sequence. */
3074 ironlake_enable_shared_dpll(intel_crtc
);
3076 /* set transcoder timing, panel must allow it */
3077 assert_panel_unlocked(dev_priv
, pipe
);
3078 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3080 intel_fdi_normal_train(crtc
);
3082 /* For PCH DP, enable TRANS_DP_CTL */
3083 if (HAS_PCH_CPT(dev
) &&
3084 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3085 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3086 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3087 reg
= TRANS_DP_CTL(pipe
);
3088 temp
= I915_READ(reg
);
3089 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3090 TRANS_DP_SYNC_MASK
|
3092 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3093 TRANS_DP_ENH_FRAMING
);
3094 temp
|= bpc
<< 9; /* same format but at 11:9 */
3096 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3097 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3098 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3099 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3101 switch (intel_trans_dp_port_sel(crtc
)) {
3103 temp
|= TRANS_DP_PORT_SEL_B
;
3106 temp
|= TRANS_DP_PORT_SEL_C
;
3109 temp
|= TRANS_DP_PORT_SEL_D
;
3115 I915_WRITE(reg
, temp
);
3118 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3121 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3123 struct drm_device
*dev
= crtc
->dev
;
3124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3125 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3126 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3128 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3130 lpt_program_iclkip(crtc
);
3132 /* Set transcoder timing. */
3133 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3135 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3138 static void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3140 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3145 if (pll
->refcount
== 0) {
3146 WARN(1, "bad %s refcount\n", pll
->name
);
3150 if (--pll
->refcount
== 0) {
3152 WARN_ON(pll
->active
);
3155 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3158 static struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3160 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3161 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3162 enum intel_dpll_id i
;
3165 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3166 crtc
->base
.base
.id
, pll
->name
);
3167 intel_put_shared_dpll(crtc
);
3170 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3171 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3172 i
= (enum intel_dpll_id
) crtc
->pipe
;
3173 pll
= &dev_priv
->shared_dplls
[i
];
3175 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3176 crtc
->base
.base
.id
, pll
->name
);
3181 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3182 pll
= &dev_priv
->shared_dplls
[i
];
3184 /* Only want to check enabled timings first */
3185 if (pll
->refcount
== 0)
3188 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3189 sizeof(pll
->hw_state
)) == 0) {
3190 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3192 pll
->name
, pll
->refcount
, pll
->active
);
3198 /* Ok no matching timings, maybe there's a free one? */
3199 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3200 pll
= &dev_priv
->shared_dplls
[i
];
3201 if (pll
->refcount
== 0) {
3202 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3203 crtc
->base
.base
.id
, pll
->name
);
3211 crtc
->config
.shared_dpll
= i
;
3212 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3213 pipe_name(crtc
->pipe
));
3215 if (pll
->active
== 0) {
3216 memcpy(&pll
->hw_state
, &crtc
->config
.dpll_hw_state
,
3217 sizeof(pll
->hw_state
));
3219 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
3221 assert_shared_dpll_disabled(dev_priv
, pll
);
3223 pll
->mode_set(dev_priv
, pll
);
3230 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3233 int dslreg
= PIPEDSL(pipe
);
3236 temp
= I915_READ(dslreg
);
3238 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3239 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3240 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3244 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3246 struct drm_device
*dev
= crtc
->base
.dev
;
3247 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3248 int pipe
= crtc
->pipe
;
3250 if (crtc
->config
.pch_pfit
.enabled
) {
3251 /* Force use of hard-coded filter coefficients
3252 * as some pre-programmed values are broken,
3255 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3256 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3257 PF_PIPE_SEL_IVB(pipe
));
3259 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3260 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3261 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3265 static void intel_enable_planes(struct drm_crtc
*crtc
)
3267 struct drm_device
*dev
= crtc
->dev
;
3268 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3269 struct intel_plane
*intel_plane
;
3271 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3272 if (intel_plane
->pipe
== pipe
)
3273 intel_plane_restore(&intel_plane
->base
);
3276 static void intel_disable_planes(struct drm_crtc
*crtc
)
3278 struct drm_device
*dev
= crtc
->dev
;
3279 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3280 struct intel_plane
*intel_plane
;
3282 list_for_each_entry(intel_plane
, &dev
->mode_config
.plane_list
, base
.head
)
3283 if (intel_plane
->pipe
== pipe
)
3284 intel_plane_disable(&intel_plane
->base
);
3287 static void hsw_enable_ips(struct intel_crtc
*crtc
)
3289 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3291 if (!crtc
->config
.ips_enabled
)
3294 /* We can only enable IPS after we enable a plane and wait for a vblank.
3295 * We guarantee that the plane is enabled by calling intel_enable_ips
3296 * only after intel_enable_plane. And intel_enable_plane already waits
3297 * for a vblank, so all we need to do here is to enable the IPS bit. */
3298 assert_plane_enabled(dev_priv
, crtc
->plane
);
3299 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3302 static void hsw_disable_ips(struct intel_crtc
*crtc
)
3304 struct drm_device
*dev
= crtc
->base
.dev
;
3305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3307 if (!crtc
->config
.ips_enabled
)
3310 assert_plane_enabled(dev_priv
, crtc
->plane
);
3311 I915_WRITE(IPS_CTL
, 0);
3312 POSTING_READ(IPS_CTL
);
3314 /* We need to wait for a vblank before we can disable the plane. */
3315 intel_wait_for_vblank(dev
, crtc
->pipe
);
3318 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3319 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3321 struct drm_device
*dev
= crtc
->dev
;
3322 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3323 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3324 enum pipe pipe
= intel_crtc
->pipe
;
3325 int palreg
= PALETTE(pipe
);
3327 bool reenable_ips
= false;
3329 /* The clocks have to be on to load the palette. */
3330 if (!crtc
->enabled
|| !intel_crtc
->active
)
3333 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3334 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3335 assert_dsi_pll_enabled(dev_priv
);
3337 assert_pll_enabled(dev_priv
, pipe
);
3340 /* use legacy palette for Ironlake */
3341 if (HAS_PCH_SPLIT(dev
))
3342 palreg
= LGC_PALETTE(pipe
);
3344 /* Workaround : Do not read or write the pipe palette/gamma data while
3345 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3347 if (intel_crtc
->config
.ips_enabled
&&
3348 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3349 GAMMA_MODE_MODE_SPLIT
)) {
3350 hsw_disable_ips(intel_crtc
);
3351 reenable_ips
= true;
3354 for (i
= 0; i
< 256; i
++) {
3355 I915_WRITE(palreg
+ 4 * i
,
3356 (intel_crtc
->lut_r
[i
] << 16) |
3357 (intel_crtc
->lut_g
[i
] << 8) |
3358 intel_crtc
->lut_b
[i
]);
3362 hsw_enable_ips(intel_crtc
);
3365 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3367 struct drm_device
*dev
= crtc
->dev
;
3368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3369 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3370 struct intel_encoder
*encoder
;
3371 int pipe
= intel_crtc
->pipe
;
3372 int plane
= intel_crtc
->plane
;
3374 WARN_ON(!crtc
->enabled
);
3376 if (intel_crtc
->active
)
3379 intel_crtc
->active
= true;
3381 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3382 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3384 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3385 if (encoder
->pre_enable
)
3386 encoder
->pre_enable(encoder
);
3388 if (intel_crtc
->config
.has_pch_encoder
) {
3389 /* Note: FDI PLL enabling _must_ be done before we enable the
3390 * cpu pipes, hence this is separate from all the other fdi/pch
3392 ironlake_fdi_pll_enable(intel_crtc
);
3394 assert_fdi_tx_disabled(dev_priv
, pipe
);
3395 assert_fdi_rx_disabled(dev_priv
, pipe
);
3398 ironlake_pfit_enable(intel_crtc
);
3401 * On ILK+ LUT must be loaded before the pipe is running but with
3404 intel_crtc_load_lut(crtc
);
3406 intel_update_watermarks(crtc
);
3407 intel_enable_pipe(dev_priv
, pipe
,
3408 intel_crtc
->config
.has_pch_encoder
, false);
3409 intel_enable_plane(dev_priv
, plane
, pipe
);
3410 intel_enable_planes(crtc
);
3411 intel_crtc_update_cursor(crtc
, true);
3413 if (intel_crtc
->config
.has_pch_encoder
)
3414 ironlake_pch_enable(crtc
);
3416 mutex_lock(&dev
->struct_mutex
);
3417 intel_update_fbc(dev
);
3418 mutex_unlock(&dev
->struct_mutex
);
3420 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3421 encoder
->enable(encoder
);
3423 if (HAS_PCH_CPT(dev
))
3424 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3427 * There seems to be a race in PCH platform hw (at least on some
3428 * outputs) where an enabled pipe still completes any pageflip right
3429 * away (as if the pipe is off) instead of waiting for vblank. As soon
3430 * as the first vblank happend, everything works as expected. Hence just
3431 * wait for one vblank before returning to avoid strange things
3434 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3437 /* IPS only exists on ULT machines and is tied to pipe A. */
3438 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
3440 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
3443 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3445 struct drm_device
*dev
= crtc
->dev
;
3446 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3447 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3448 struct intel_encoder
*encoder
;
3449 int pipe
= intel_crtc
->pipe
;
3450 int plane
= intel_crtc
->plane
;
3452 WARN_ON(!crtc
->enabled
);
3454 if (intel_crtc
->active
)
3457 intel_crtc
->active
= true;
3459 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
3460 if (intel_crtc
->config
.has_pch_encoder
)
3461 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3463 if (intel_crtc
->config
.has_pch_encoder
)
3464 dev_priv
->display
.fdi_link_train(crtc
);
3466 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3467 if (encoder
->pre_enable
)
3468 encoder
->pre_enable(encoder
);
3470 intel_ddi_enable_pipe_clock(intel_crtc
);
3472 ironlake_pfit_enable(intel_crtc
);
3475 * On ILK+ LUT must be loaded before the pipe is running but with
3478 intel_crtc_load_lut(crtc
);
3480 intel_ddi_set_pipe_settings(crtc
);
3481 intel_ddi_enable_transcoder_func(crtc
);
3483 intel_update_watermarks(crtc
);
3484 intel_enable_pipe(dev_priv
, pipe
,
3485 intel_crtc
->config
.has_pch_encoder
, false);
3486 intel_enable_plane(dev_priv
, plane
, pipe
);
3487 intel_enable_planes(crtc
);
3488 intel_crtc_update_cursor(crtc
, true);
3490 hsw_enable_ips(intel_crtc
);
3492 if (intel_crtc
->config
.has_pch_encoder
)
3493 lpt_pch_enable(crtc
);
3495 mutex_lock(&dev
->struct_mutex
);
3496 intel_update_fbc(dev
);
3497 mutex_unlock(&dev
->struct_mutex
);
3499 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3500 encoder
->enable(encoder
);
3501 intel_opregion_notify_encoder(encoder
, true);
3505 * There seems to be a race in PCH platform hw (at least on some
3506 * outputs) where an enabled pipe still completes any pageflip right
3507 * away (as if the pipe is off) instead of waiting for vblank. As soon
3508 * as the first vblank happend, everything works as expected. Hence just
3509 * wait for one vblank before returning to avoid strange things
3512 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3515 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
3517 struct drm_device
*dev
= crtc
->base
.dev
;
3518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3519 int pipe
= crtc
->pipe
;
3521 /* To avoid upsetting the power well on haswell only disable the pfit if
3522 * it's in use. The hw state code will make sure we get this right. */
3523 if (crtc
->config
.pch_pfit
.enabled
) {
3524 I915_WRITE(PF_CTL(pipe
), 0);
3525 I915_WRITE(PF_WIN_POS(pipe
), 0);
3526 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3530 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3532 struct drm_device
*dev
= crtc
->dev
;
3533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3534 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3535 struct intel_encoder
*encoder
;
3536 int pipe
= intel_crtc
->pipe
;
3537 int plane
= intel_crtc
->plane
;
3541 if (!intel_crtc
->active
)
3544 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3545 encoder
->disable(encoder
);
3547 intel_crtc_wait_for_pending_flips(crtc
);
3548 drm_vblank_off(dev
, pipe
);
3550 if (dev_priv
->fbc
.plane
== plane
)
3551 intel_disable_fbc(dev
);
3553 intel_crtc_update_cursor(crtc
, false);
3554 intel_disable_planes(crtc
);
3555 intel_disable_plane(dev_priv
, plane
, pipe
);
3557 if (intel_crtc
->config
.has_pch_encoder
)
3558 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
3560 intel_disable_pipe(dev_priv
, pipe
);
3562 ironlake_pfit_disable(intel_crtc
);
3564 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3565 if (encoder
->post_disable
)
3566 encoder
->post_disable(encoder
);
3568 if (intel_crtc
->config
.has_pch_encoder
) {
3569 ironlake_fdi_disable(crtc
);
3571 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
3572 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
3574 if (HAS_PCH_CPT(dev
)) {
3575 /* disable TRANS_DP_CTL */
3576 reg
= TRANS_DP_CTL(pipe
);
3577 temp
= I915_READ(reg
);
3578 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
3579 TRANS_DP_PORT_SEL_MASK
);
3580 temp
|= TRANS_DP_PORT_SEL_NONE
;
3581 I915_WRITE(reg
, temp
);
3583 /* disable DPLL_SEL */
3584 temp
= I915_READ(PCH_DPLL_SEL
);
3585 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
3586 I915_WRITE(PCH_DPLL_SEL
, temp
);
3589 /* disable PCH DPLL */
3590 intel_disable_shared_dpll(intel_crtc
);
3592 ironlake_fdi_pll_disable(intel_crtc
);
3595 intel_crtc
->active
= false;
3596 intel_update_watermarks(crtc
);
3598 mutex_lock(&dev
->struct_mutex
);
3599 intel_update_fbc(dev
);
3600 mutex_unlock(&dev
->struct_mutex
);
3603 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3605 struct drm_device
*dev
= crtc
->dev
;
3606 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3607 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3608 struct intel_encoder
*encoder
;
3609 int pipe
= intel_crtc
->pipe
;
3610 int plane
= intel_crtc
->plane
;
3611 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3613 if (!intel_crtc
->active
)
3616 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
3617 intel_opregion_notify_encoder(encoder
, false);
3618 encoder
->disable(encoder
);
3621 intel_crtc_wait_for_pending_flips(crtc
);
3622 drm_vblank_off(dev
, pipe
);
3624 /* FBC must be disabled before disabling the plane on HSW. */
3625 if (dev_priv
->fbc
.plane
== plane
)
3626 intel_disable_fbc(dev
);
3628 hsw_disable_ips(intel_crtc
);
3630 intel_crtc_update_cursor(crtc
, false);
3631 intel_disable_planes(crtc
);
3632 intel_disable_plane(dev_priv
, plane
, pipe
);
3634 if (intel_crtc
->config
.has_pch_encoder
)
3635 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
3636 intel_disable_pipe(dev_priv
, pipe
);
3638 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3640 ironlake_pfit_disable(intel_crtc
);
3642 intel_ddi_disable_pipe_clock(intel_crtc
);
3644 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3645 if (encoder
->post_disable
)
3646 encoder
->post_disable(encoder
);
3648 if (intel_crtc
->config
.has_pch_encoder
) {
3649 lpt_disable_pch_transcoder(dev_priv
);
3650 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
3651 intel_ddi_fdi_disable(crtc
);
3654 intel_crtc
->active
= false;
3655 intel_update_watermarks(crtc
);
3657 mutex_lock(&dev
->struct_mutex
);
3658 intel_update_fbc(dev
);
3659 mutex_unlock(&dev
->struct_mutex
);
3662 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3664 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3665 intel_put_shared_dpll(intel_crtc
);
3668 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3670 intel_ddi_put_crtc_pll(crtc
);
3673 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3675 if (!enable
&& intel_crtc
->overlay
) {
3676 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3677 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3679 mutex_lock(&dev
->struct_mutex
);
3680 dev_priv
->mm
.interruptible
= false;
3681 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3682 dev_priv
->mm
.interruptible
= true;
3683 mutex_unlock(&dev
->struct_mutex
);
3686 /* Let userspace switch the overlay on again. In most cases userspace
3687 * has to recompute where to put it anyway.
3692 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3693 * cursor plane briefly if not already running after enabling the display
3695 * This workaround avoids occasional blank screens when self refresh is
3699 g4x_fixup_plane(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
3701 u32 cntl
= I915_READ(CURCNTR(pipe
));
3703 if ((cntl
& CURSOR_MODE
) == 0) {
3704 u32 fw_bcl_self
= I915_READ(FW_BLC_SELF
);
3706 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
& ~FW_BLC_SELF_EN
);
3707 I915_WRITE(CURCNTR(pipe
), CURSOR_MODE_64_ARGB_AX
);
3708 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
3709 I915_WRITE(CURCNTR(pipe
), cntl
);
3710 I915_WRITE(CURBASE(pipe
), I915_READ(CURBASE(pipe
)));
3711 I915_WRITE(FW_BLC_SELF
, fw_bcl_self
);
3715 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
3717 struct drm_device
*dev
= crtc
->base
.dev
;
3718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3719 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
3721 if (!crtc
->config
.gmch_pfit
.control
)
3725 * The panel fitter should only be adjusted whilst the pipe is disabled,
3726 * according to register description and PRM.
3728 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
3729 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3731 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
3732 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
3734 /* Border color in case we don't scale up to the full screen. Black by
3735 * default, change to something else for debugging. */
3736 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
3739 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
3741 struct drm_device
*dev
= crtc
->dev
;
3742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3743 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3744 struct intel_encoder
*encoder
;
3745 int pipe
= intel_crtc
->pipe
;
3746 int plane
= intel_crtc
->plane
;
3749 WARN_ON(!crtc
->enabled
);
3751 if (intel_crtc
->active
)
3754 intel_crtc
->active
= true;
3756 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3757 if (encoder
->pre_pll_enable
)
3758 encoder
->pre_pll_enable(encoder
);
3760 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
3763 vlv_enable_pll(intel_crtc
);
3765 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3766 if (encoder
->pre_enable
)
3767 encoder
->pre_enable(encoder
);
3769 i9xx_pfit_enable(intel_crtc
);
3771 intel_crtc_load_lut(crtc
);
3773 intel_update_watermarks(crtc
);
3774 intel_enable_pipe(dev_priv
, pipe
, false, is_dsi
);
3775 intel_enable_plane(dev_priv
, plane
, pipe
);
3776 intel_enable_planes(crtc
);
3777 intel_crtc_update_cursor(crtc
, true);
3779 intel_update_fbc(dev
);
3781 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3782 encoder
->enable(encoder
);
3785 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3787 struct drm_device
*dev
= crtc
->dev
;
3788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3789 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3790 struct intel_encoder
*encoder
;
3791 int pipe
= intel_crtc
->pipe
;
3792 int plane
= intel_crtc
->plane
;
3794 WARN_ON(!crtc
->enabled
);
3796 if (intel_crtc
->active
)
3799 intel_crtc
->active
= true;
3801 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3802 if (encoder
->pre_enable
)
3803 encoder
->pre_enable(encoder
);
3805 i9xx_enable_pll(intel_crtc
);
3807 i9xx_pfit_enable(intel_crtc
);
3809 intel_crtc_load_lut(crtc
);
3811 intel_update_watermarks(crtc
);
3812 intel_enable_pipe(dev_priv
, pipe
, false, false);
3813 intel_enable_plane(dev_priv
, plane
, pipe
);
3814 intel_enable_planes(crtc
);
3815 /* The fixup needs to happen before cursor is enabled */
3817 g4x_fixup_plane(dev_priv
, pipe
);
3818 intel_crtc_update_cursor(crtc
, true);
3820 /* Give the overlay scaler a chance to enable if it's on this pipe */
3821 intel_crtc_dpms_overlay(intel_crtc
, true);
3823 intel_update_fbc(dev
);
3825 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3826 encoder
->enable(encoder
);
3829 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
3831 struct drm_device
*dev
= crtc
->base
.dev
;
3832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3834 if (!crtc
->config
.gmch_pfit
.control
)
3837 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
3839 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3840 I915_READ(PFIT_CONTROL
));
3841 I915_WRITE(PFIT_CONTROL
, 0);
3844 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3846 struct drm_device
*dev
= crtc
->dev
;
3847 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3848 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3849 struct intel_encoder
*encoder
;
3850 int pipe
= intel_crtc
->pipe
;
3851 int plane
= intel_crtc
->plane
;
3853 if (!intel_crtc
->active
)
3856 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3857 encoder
->disable(encoder
);
3859 /* Give the overlay scaler a chance to disable if it's on this pipe */
3860 intel_crtc_wait_for_pending_flips(crtc
);
3861 drm_vblank_off(dev
, pipe
);
3863 if (dev_priv
->fbc
.plane
== plane
)
3864 intel_disable_fbc(dev
);
3866 intel_crtc_dpms_overlay(intel_crtc
, false);
3867 intel_crtc_update_cursor(crtc
, false);
3868 intel_disable_planes(crtc
);
3869 intel_disable_plane(dev_priv
, plane
, pipe
);
3871 intel_disable_pipe(dev_priv
, pipe
);
3873 i9xx_pfit_disable(intel_crtc
);
3875 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3876 if (encoder
->post_disable
)
3877 encoder
->post_disable(encoder
);
3879 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3880 i9xx_disable_pll(dev_priv
, pipe
);
3882 intel_crtc
->active
= false;
3883 intel_update_watermarks(crtc
);
3885 intel_update_fbc(dev
);
3888 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3892 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3895 struct drm_device
*dev
= crtc
->dev
;
3896 struct drm_i915_master_private
*master_priv
;
3897 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3898 int pipe
= intel_crtc
->pipe
;
3900 if (!dev
->primary
->master
)
3903 master_priv
= dev
->primary
->master
->driver_priv
;
3904 if (!master_priv
->sarea_priv
)
3909 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3910 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3913 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3914 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3917 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3923 * Sets the power management mode of the pipe and plane.
3925 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3927 struct drm_device
*dev
= crtc
->dev
;
3928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3929 struct intel_encoder
*intel_encoder
;
3930 bool enable
= false;
3932 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3933 enable
|= intel_encoder
->connectors_active
;
3936 dev_priv
->display
.crtc_enable(crtc
);
3938 dev_priv
->display
.crtc_disable(crtc
);
3940 intel_crtc_update_sarea(crtc
, enable
);
3943 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3945 struct drm_device
*dev
= crtc
->dev
;
3946 struct drm_connector
*connector
;
3947 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3948 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3950 /* crtc should still be enabled when we disable it. */
3951 WARN_ON(!crtc
->enabled
);
3953 dev_priv
->display
.crtc_disable(crtc
);
3954 intel_crtc
->eld_vld
= false;
3955 intel_crtc_update_sarea(crtc
, false);
3956 dev_priv
->display
.off(crtc
);
3958 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3959 assert_cursor_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
3960 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3963 mutex_lock(&dev
->struct_mutex
);
3964 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3965 mutex_unlock(&dev
->struct_mutex
);
3969 /* Update computed state. */
3970 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3971 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3974 if (connector
->encoder
->crtc
!= crtc
)
3977 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3978 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3982 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3984 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3986 drm_encoder_cleanup(encoder
);
3987 kfree(intel_encoder
);
3990 /* Simple dpms helper for encoders with just one connector, no cloning and only
3991 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3992 * state of the entire output pipe. */
3993 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3995 if (mode
== DRM_MODE_DPMS_ON
) {
3996 encoder
->connectors_active
= true;
3998 intel_crtc_update_dpms(encoder
->base
.crtc
);
4000 encoder
->connectors_active
= false;
4002 intel_crtc_update_dpms(encoder
->base
.crtc
);
4006 /* Cross check the actual hw state with our own modeset state tracking (and it's
4007 * internal consistency). */
4008 static void intel_connector_check_state(struct intel_connector
*connector
)
4010 if (connector
->get_hw_state(connector
)) {
4011 struct intel_encoder
*encoder
= connector
->encoder
;
4012 struct drm_crtc
*crtc
;
4013 bool encoder_enabled
;
4016 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4017 connector
->base
.base
.id
,
4018 drm_get_connector_name(&connector
->base
));
4020 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
4021 "wrong connector dpms state\n");
4022 WARN(connector
->base
.encoder
!= &encoder
->base
,
4023 "active connector not linked to encoder\n");
4024 WARN(!encoder
->connectors_active
,
4025 "encoder->connectors_active not set\n");
4027 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
4028 WARN(!encoder_enabled
, "encoder not enabled\n");
4029 if (WARN_ON(!encoder
->base
.crtc
))
4032 crtc
= encoder
->base
.crtc
;
4034 WARN(!crtc
->enabled
, "crtc not enabled\n");
4035 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
4036 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
4037 "encoder active on the wrong pipe\n");
4041 /* Even simpler default implementation, if there's really no special case to
4043 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
4045 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
4047 /* All the simple cases only support two dpms states. */
4048 if (mode
!= DRM_MODE_DPMS_ON
)
4049 mode
= DRM_MODE_DPMS_OFF
;
4051 if (mode
== connector
->dpms
)
4054 connector
->dpms
= mode
;
4056 /* Only need to change hw state when actually enabled */
4057 if (encoder
->base
.crtc
)
4058 intel_encoder_dpms(encoder
, mode
);
4060 WARN_ON(encoder
->connectors_active
!= false);
4062 intel_modeset_check_state(connector
->dev
);
4065 /* Simple connector->get_hw_state implementation for encoders that support only
4066 * one connector and no cloning and hence the encoder state determines the state
4067 * of the connector. */
4068 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
4071 struct intel_encoder
*encoder
= connector
->encoder
;
4073 return encoder
->get_hw_state(encoder
, &pipe
);
4076 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
4077 struct intel_crtc_config
*pipe_config
)
4079 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4080 struct intel_crtc
*pipe_B_crtc
=
4081 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
4083 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4084 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4085 if (pipe_config
->fdi_lanes
> 4) {
4086 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4087 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4091 if (IS_HASWELL(dev
)) {
4092 if (pipe_config
->fdi_lanes
> 2) {
4093 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4094 pipe_config
->fdi_lanes
);
4101 if (INTEL_INFO(dev
)->num_pipes
== 2)
4104 /* Ivybridge 3 pipe is really complicated */
4109 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
4110 pipe_config
->fdi_lanes
> 2) {
4111 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4112 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4117 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
4118 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
4119 if (pipe_config
->fdi_lanes
> 2) {
4120 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4121 pipe_name(pipe
), pipe_config
->fdi_lanes
);
4125 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4135 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
4136 struct intel_crtc_config
*pipe_config
)
4138 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4139 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4140 int lane
, link_bw
, fdi_dotclock
;
4141 bool setup_ok
, needs_recompute
= false;
4144 /* FDI is a binary signal running at ~2.7GHz, encoding
4145 * each output octet as 10 bits. The actual frequency
4146 * is stored as a divider into a 100MHz clock, and the
4147 * mode pixel clock is stored in units of 1KHz.
4148 * Hence the bw of each lane in terms of the mode signal
4151 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4153 fdi_dotclock
= adjusted_mode
->crtc_clock
;
4155 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
4156 pipe_config
->pipe_bpp
);
4158 pipe_config
->fdi_lanes
= lane
;
4160 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
4161 link_bw
, &pipe_config
->fdi_m_n
);
4163 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
4164 intel_crtc
->pipe
, pipe_config
);
4165 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
4166 pipe_config
->pipe_bpp
-= 2*3;
4167 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4168 pipe_config
->pipe_bpp
);
4169 needs_recompute
= true;
4170 pipe_config
->bw_constrained
= true;
4175 if (needs_recompute
)
4178 return setup_ok
? 0 : -EINVAL
;
4181 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
4182 struct intel_crtc_config
*pipe_config
)
4184 pipe_config
->ips_enabled
= i915_enable_ips
&&
4185 hsw_crtc_supports_ips(crtc
) &&
4186 pipe_config
->pipe_bpp
<= 24;
4189 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
4190 struct intel_crtc_config
*pipe_config
)
4192 struct drm_device
*dev
= crtc
->base
.dev
;
4193 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
4195 /* FIXME should check pixel clock limits on all platforms */
4196 if (INTEL_INFO(dev
)->gen
< 4) {
4197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4199 dev_priv
->display
.get_display_clock_speed(dev
);
4202 * Enable pixel doubling when the dot clock
4203 * is > 90% of the (display) core speed.
4205 * GDG double wide on either pipe,
4206 * otherwise pipe A only.
4208 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
4209 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
4211 pipe_config
->double_wide
= true;
4214 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
4219 * Pipe horizontal size must be even in:
4221 * - LVDS dual channel mode
4222 * - Double wide pipe
4224 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4225 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
4226 pipe_config
->pipe_src_w
&= ~1;
4228 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4229 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4231 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
4232 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
4235 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
4236 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
4237 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
4238 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4240 pipe_config
->pipe_bpp
= 8*3;
4244 hsw_compute_ips_config(crtc
, pipe_config
);
4246 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4247 * clock survives for now. */
4248 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
4249 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
4251 if (pipe_config
->has_pch_encoder
)
4252 return ironlake_fdi_compute_config(crtc
, pipe_config
);
4257 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
4259 return 400000; /* FIXME */
4262 static int i945_get_display_clock_speed(struct drm_device
*dev
)
4267 static int i915_get_display_clock_speed(struct drm_device
*dev
)
4272 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
4277 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
4281 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4283 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4284 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
4286 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
4288 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
4290 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
4293 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
4294 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
4296 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
4301 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
4305 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
4307 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
4310 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
4311 case GC_DISPLAY_CLOCK_333_MHZ
:
4314 case GC_DISPLAY_CLOCK_190_200_MHZ
:
4320 static int i865_get_display_clock_speed(struct drm_device
*dev
)
4325 static int i855_get_display_clock_speed(struct drm_device
*dev
)
4328 /* Assume that the hardware is in the high speed state. This
4329 * should be the default.
4331 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
4332 case GC_CLOCK_133_200
:
4333 case GC_CLOCK_100_200
:
4335 case GC_CLOCK_166_250
:
4337 case GC_CLOCK_100_133
:
4341 /* Shouldn't happen */
4345 static int i830_get_display_clock_speed(struct drm_device
*dev
)
4351 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
4353 while (*num
> DATA_LINK_M_N_MASK
||
4354 *den
> DATA_LINK_M_N_MASK
) {
4360 static void compute_m_n(unsigned int m
, unsigned int n
,
4361 uint32_t *ret_m
, uint32_t *ret_n
)
4363 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
4364 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
4365 intel_reduce_m_n_ratio(ret_m
, ret_n
);
4369 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
4370 int pixel_clock
, int link_clock
,
4371 struct intel_link_m_n
*m_n
)
4375 compute_m_n(bits_per_pixel
* pixel_clock
,
4376 link_clock
* nlanes
* 8,
4377 &m_n
->gmch_m
, &m_n
->gmch_n
);
4379 compute_m_n(pixel_clock
, link_clock
,
4380 &m_n
->link_m
, &m_n
->link_n
);
4383 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
4385 if (i915_panel_use_ssc
>= 0)
4386 return i915_panel_use_ssc
!= 0;
4387 return dev_priv
->vbt
.lvds_use_ssc
4388 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
4391 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4393 struct drm_device
*dev
= crtc
->dev
;
4394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4397 if (IS_VALLEYVIEW(dev
)) {
4399 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4400 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4401 refclk
= dev_priv
->vbt
.lvds_ssc_freq
* 1000;
4402 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4404 } else if (!IS_GEN2(dev
)) {
4413 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
4415 return (1 << dpll
->n
) << 16 | dpll
->m2
;
4418 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
4420 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
4423 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
4424 intel_clock_t
*reduced_clock
)
4426 struct drm_device
*dev
= crtc
->base
.dev
;
4427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4428 int pipe
= crtc
->pipe
;
4431 if (IS_PINEVIEW(dev
)) {
4432 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
4434 fp2
= pnv_dpll_compute_fp(reduced_clock
);
4436 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
4438 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
4441 I915_WRITE(FP0(pipe
), fp
);
4442 crtc
->config
.dpll_hw_state
.fp0
= fp
;
4444 crtc
->lowfreq_avail
= false;
4445 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4446 reduced_clock
&& i915_powersave
) {
4447 I915_WRITE(FP1(pipe
), fp2
);
4448 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
4449 crtc
->lowfreq_avail
= true;
4451 I915_WRITE(FP1(pipe
), fp
);
4452 crtc
->config
.dpll_hw_state
.fp1
= fp
;
4456 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
4462 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4463 * and set it to a reasonable value instead.
4465 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4466 reg_val
&= 0xffffff00;
4467 reg_val
|= 0x00000030;
4468 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4470 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4471 reg_val
&= 0x8cffffff;
4472 reg_val
= 0x8c000000;
4473 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4475 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF(1));
4476 reg_val
&= 0xffffff00;
4477 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF(1), reg_val
);
4479 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CALIBRATION
);
4480 reg_val
&= 0x00ffffff;
4481 reg_val
|= 0xb0000000;
4482 vlv_dpio_write(dev_priv
, pipe
, DPIO_CALIBRATION
, reg_val
);
4485 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
4486 struct intel_link_m_n
*m_n
)
4488 struct drm_device
*dev
= crtc
->base
.dev
;
4489 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4490 int pipe
= crtc
->pipe
;
4492 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4493 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
4494 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
4495 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
4498 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
4499 struct intel_link_m_n
*m_n
)
4501 struct drm_device
*dev
= crtc
->base
.dev
;
4502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4503 int pipe
= crtc
->pipe
;
4504 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
4506 if (INTEL_INFO(dev
)->gen
>= 5) {
4507 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4508 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
4509 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
4510 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
4512 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
4513 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
4514 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
4515 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
4519 static void intel_dp_set_m_n(struct intel_crtc
*crtc
)
4521 if (crtc
->config
.has_pch_encoder
)
4522 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4524 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
4527 static void vlv_update_pll(struct intel_crtc
*crtc
)
4529 struct drm_device
*dev
= crtc
->base
.dev
;
4530 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4531 int pipe
= crtc
->pipe
;
4533 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4534 u32 coreclk
, reg_val
, dpll_md
;
4536 mutex_lock(&dev_priv
->dpio_lock
);
4538 bestn
= crtc
->config
.dpll
.n
;
4539 bestm1
= crtc
->config
.dpll
.m1
;
4540 bestm2
= crtc
->config
.dpll
.m2
;
4541 bestp1
= crtc
->config
.dpll
.p1
;
4542 bestp2
= crtc
->config
.dpll
.p2
;
4544 /* See eDP HDMI DPIO driver vbios notes doc */
4546 /* PLL B needs special handling */
4548 vlv_pllb_recal_opamp(dev_priv
, pipe
);
4550 /* Set up Tx target for periodic Rcomp update */
4551 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_BCAST
, 0x0100000f);
4553 /* Disable target IRef on PLL */
4554 reg_val
= vlv_dpio_read(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
));
4555 reg_val
&= 0x00ffffff;
4556 vlv_dpio_write(dev_priv
, pipe
, DPIO_IREF_CTL(pipe
), reg_val
);
4558 /* Disable fast lock */
4559 vlv_dpio_write(dev_priv
, pipe
, DPIO_FASTCLK_DISABLE
, 0x610);
4561 /* Set idtafcrecal before PLL is enabled */
4562 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4563 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4564 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4565 mdiv
|= (1 << DPIO_K_SHIFT
);
4568 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4569 * but we don't support that).
4570 * Note: don't use the DAC post divider as it seems unstable.
4572 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
4573 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4575 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4576 vlv_dpio_write(dev_priv
, pipe
, DPIO_DIV(pipe
), mdiv
);
4578 /* Set HBR and RBR LPF coefficients */
4579 if (crtc
->config
.port_clock
== 162000 ||
4580 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
4581 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
4582 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4585 vlv_dpio_write(dev_priv
, pipe
, DPIO_LPF_COEFF(pipe
),
4588 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
4589 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
4590 /* Use SSC source */
4592 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4595 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4597 } else { /* HDMI or VGA */
4598 /* Use bend source */
4600 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4603 vlv_dpio_write(dev_priv
, pipe
, DPIO_REFSFR(pipe
),
4607 coreclk
= vlv_dpio_read(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
));
4608 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
4609 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
4610 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
4611 coreclk
|= 0x01000000;
4612 vlv_dpio_write(dev_priv
, pipe
, DPIO_CORE_CLK(pipe
), coreclk
);
4614 vlv_dpio_write(dev_priv
, pipe
, DPIO_PLL_CML(pipe
), 0x87871000);
4616 /* Enable DPIO clock input */
4617 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
4618 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
4620 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
4622 dpll
|= DPLL_VCO_ENABLE
;
4623 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4625 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4626 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4627 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4629 if (crtc
->config
.has_dp_encoder
)
4630 intel_dp_set_m_n(crtc
);
4632 mutex_unlock(&dev_priv
->dpio_lock
);
4635 static void i9xx_update_pll(struct intel_crtc
*crtc
,
4636 intel_clock_t
*reduced_clock
,
4639 struct drm_device
*dev
= crtc
->base
.dev
;
4640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4643 struct dpll
*clock
= &crtc
->config
.dpll
;
4645 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4647 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
4648 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
4650 dpll
= DPLL_VGA_MODE_DIS
;
4652 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
4653 dpll
|= DPLLB_MODE_LVDS
;
4655 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4657 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
4658 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
4659 << SDVO_MULTIPLIER_SHIFT_HIRES
;
4663 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4665 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
4666 dpll
|= DPLL_SDVO_HIGH_SPEED
;
4668 /* compute bitmask from p1 value */
4669 if (IS_PINEVIEW(dev
))
4670 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4672 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4673 if (IS_G4X(dev
) && reduced_clock
)
4674 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4676 switch (clock
->p2
) {
4678 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4681 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4684 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4687 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4690 if (INTEL_INFO(dev
)->gen
>= 4)
4691 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4693 if (crtc
->config
.sdvo_tv_clock
)
4694 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4695 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4696 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4697 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4699 dpll
|= PLL_REF_INPUT_DREFCLK
;
4701 dpll
|= DPLL_VCO_ENABLE
;
4702 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4704 if (INTEL_INFO(dev
)->gen
>= 4) {
4705 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
4706 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4707 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
4710 if (crtc
->config
.has_dp_encoder
)
4711 intel_dp_set_m_n(crtc
);
4714 static void i8xx_update_pll(struct intel_crtc
*crtc
,
4715 intel_clock_t
*reduced_clock
,
4718 struct drm_device
*dev
= crtc
->base
.dev
;
4719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4721 struct dpll
*clock
= &crtc
->config
.dpll
;
4723 i9xx_update_pll_dividers(crtc
, reduced_clock
);
4725 dpll
= DPLL_VGA_MODE_DIS
;
4727 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
4728 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4731 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4733 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4735 dpll
|= PLL_P2_DIVIDE_BY_4
;
4738 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
4739 dpll
|= DPLL_DVO_2X_MODE
;
4741 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
4742 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4743 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4745 dpll
|= PLL_REF_INPUT_DREFCLK
;
4747 dpll
|= DPLL_VCO_ENABLE
;
4748 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
4751 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
4753 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4754 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4755 enum pipe pipe
= intel_crtc
->pipe
;
4756 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4757 struct drm_display_mode
*adjusted_mode
=
4758 &intel_crtc
->config
.adjusted_mode
;
4759 uint32_t vsyncshift
, crtc_vtotal
, crtc_vblank_end
;
4761 /* We need to be careful not to changed the adjusted mode, for otherwise
4762 * the hw state checker will get angry at the mismatch. */
4763 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
4764 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
4766 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4767 /* the chip adds 2 halflines automatically */
4769 crtc_vblank_end
-= 1;
4770 vsyncshift
= adjusted_mode
->crtc_hsync_start
4771 - adjusted_mode
->crtc_htotal
/ 2;
4776 if (INTEL_INFO(dev
)->gen
> 3)
4777 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4779 I915_WRITE(HTOTAL(cpu_transcoder
),
4780 (adjusted_mode
->crtc_hdisplay
- 1) |
4781 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4782 I915_WRITE(HBLANK(cpu_transcoder
),
4783 (adjusted_mode
->crtc_hblank_start
- 1) |
4784 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4785 I915_WRITE(HSYNC(cpu_transcoder
),
4786 (adjusted_mode
->crtc_hsync_start
- 1) |
4787 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4789 I915_WRITE(VTOTAL(cpu_transcoder
),
4790 (adjusted_mode
->crtc_vdisplay
- 1) |
4791 ((crtc_vtotal
- 1) << 16));
4792 I915_WRITE(VBLANK(cpu_transcoder
),
4793 (adjusted_mode
->crtc_vblank_start
- 1) |
4794 ((crtc_vblank_end
- 1) << 16));
4795 I915_WRITE(VSYNC(cpu_transcoder
),
4796 (adjusted_mode
->crtc_vsync_start
- 1) |
4797 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4799 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4800 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4801 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4803 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4804 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4805 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4807 /* pipesrc controls the size that is scaled from, which should
4808 * always be the user's requested size.
4810 I915_WRITE(PIPESRC(pipe
),
4811 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
4812 (intel_crtc
->config
.pipe_src_h
- 1));
4815 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
4816 struct intel_crtc_config
*pipe_config
)
4818 struct drm_device
*dev
= crtc
->base
.dev
;
4819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4820 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
4823 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
4824 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
4825 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
4826 tmp
= I915_READ(HBLANK(cpu_transcoder
));
4827 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
4828 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4829 tmp
= I915_READ(HSYNC(cpu_transcoder
));
4830 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
4831 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4833 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
4834 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
4835 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
4836 tmp
= I915_READ(VBLANK(cpu_transcoder
));
4837 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
4838 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
4839 tmp
= I915_READ(VSYNC(cpu_transcoder
));
4840 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
4841 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
4843 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
4844 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
4845 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
4846 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
4849 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
4850 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
4851 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
4853 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
4854 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
4857 static void intel_crtc_mode_from_pipe_config(struct intel_crtc
*intel_crtc
,
4858 struct intel_crtc_config
*pipe_config
)
4860 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4862 crtc
->mode
.hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
4863 crtc
->mode
.htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
4864 crtc
->mode
.hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
4865 crtc
->mode
.hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
4867 crtc
->mode
.vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
4868 crtc
->mode
.vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
4869 crtc
->mode
.vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
4870 crtc
->mode
.vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
4872 crtc
->mode
.flags
= pipe_config
->adjusted_mode
.flags
;
4874 crtc
->mode
.clock
= pipe_config
->adjusted_mode
.crtc_clock
;
4875 crtc
->mode
.flags
|= pipe_config
->adjusted_mode
.flags
;
4878 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
4880 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4886 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
4887 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
4888 pipeconf
|= PIPECONF_ENABLE
;
4890 if (intel_crtc
->config
.double_wide
)
4891 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4893 /* only g4x and later have fancy bpc/dither controls */
4894 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
4895 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4896 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
4897 pipeconf
|= PIPECONF_DITHER_EN
|
4898 PIPECONF_DITHER_TYPE_SP
;
4900 switch (intel_crtc
->config
.pipe_bpp
) {
4902 pipeconf
|= PIPECONF_6BPC
;
4905 pipeconf
|= PIPECONF_8BPC
;
4908 pipeconf
|= PIPECONF_10BPC
;
4911 /* Case prevented by intel_choose_pipe_bpp_dither. */
4916 if (HAS_PIPE_CXSR(dev
)) {
4917 if (intel_crtc
->lowfreq_avail
) {
4918 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4919 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4921 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4925 if (!IS_GEN2(dev
) &&
4926 intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
4927 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4929 pipeconf
|= PIPECONF_PROGRESSIVE
;
4931 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
4932 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
4934 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
4935 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
4938 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4940 struct drm_framebuffer
*fb
)
4942 struct drm_device
*dev
= crtc
->dev
;
4943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4944 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4945 int pipe
= intel_crtc
->pipe
;
4946 int plane
= intel_crtc
->plane
;
4947 int refclk
, num_connectors
= 0;
4948 intel_clock_t clock
, reduced_clock
;
4950 bool ok
, has_reduced_clock
= false;
4951 bool is_lvds
= false, is_dsi
= false;
4952 struct intel_encoder
*encoder
;
4953 const intel_limit_t
*limit
;
4956 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4957 switch (encoder
->type
) {
4958 case INTEL_OUTPUT_LVDS
:
4961 case INTEL_OUTPUT_DSI
:
4972 if (!intel_crtc
->config
.clock_set
) {
4973 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4976 * Returns a set of divisors for the desired target clock with
4977 * the given refclk, or FALSE. The returned values represent
4978 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4981 limit
= intel_limit(crtc
, refclk
);
4982 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
4983 intel_crtc
->config
.port_clock
,
4984 refclk
, NULL
, &clock
);
4986 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4990 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4992 * Ensure we match the reduced clock's P to the target
4993 * clock. If the clocks don't match, we can't switch
4994 * the display clock by using the FP0/FP1. In such case
4995 * we will disable the LVDS downclock feature.
4998 dev_priv
->display
.find_dpll(limit
, crtc
,
4999 dev_priv
->lvds_downclock
,
5003 /* Compat-code for transition, will disappear. */
5004 intel_crtc
->config
.dpll
.n
= clock
.n
;
5005 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5006 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5007 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5008 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5012 i8xx_update_pll(intel_crtc
,
5013 has_reduced_clock
? &reduced_clock
: NULL
,
5015 } else if (IS_VALLEYVIEW(dev
)) {
5016 vlv_update_pll(intel_crtc
);
5018 i9xx_update_pll(intel_crtc
,
5019 has_reduced_clock
? &reduced_clock
: NULL
,
5024 /* Set up the display plane register */
5025 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
5027 if (!IS_VALLEYVIEW(dev
)) {
5029 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
5031 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
5034 intel_set_pipe_timings(intel_crtc
);
5036 /* pipesrc and dspsize control the size that is scaled from,
5037 * which should always be the user's requested size.
5039 I915_WRITE(DSPSIZE(plane
),
5040 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
5041 (intel_crtc
->config
.pipe_src_w
- 1));
5042 I915_WRITE(DSPPOS(plane
), 0);
5044 i9xx_set_pipeconf(intel_crtc
);
5046 I915_WRITE(DSPCNTR(plane
), dspcntr
);
5047 POSTING_READ(DSPCNTR(plane
));
5049 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5054 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
5055 struct intel_crtc_config
*pipe_config
)
5057 struct drm_device
*dev
= crtc
->base
.dev
;
5058 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5061 tmp
= I915_READ(PFIT_CONTROL
);
5062 if (!(tmp
& PFIT_ENABLE
))
5065 /* Check whether the pfit is attached to our pipe. */
5066 if (INTEL_INFO(dev
)->gen
< 4) {
5067 if (crtc
->pipe
!= PIPE_B
)
5070 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
5074 pipe_config
->gmch_pfit
.control
= tmp
;
5075 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
5076 if (INTEL_INFO(dev
)->gen
< 5)
5077 pipe_config
->gmch_pfit
.lvds_border_bits
=
5078 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
5081 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
5082 struct intel_crtc_config
*pipe_config
)
5084 struct drm_device
*dev
= crtc
->base
.dev
;
5085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5086 int pipe
= pipe_config
->cpu_transcoder
;
5087 intel_clock_t clock
;
5089 int refclk
= 100000;
5091 mutex_lock(&dev_priv
->dpio_lock
);
5092 mdiv
= vlv_dpio_read(dev_priv
, pipe
, DPIO_DIV(pipe
));
5093 mutex_unlock(&dev_priv
->dpio_lock
);
5095 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
5096 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
5097 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
5098 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
5099 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
5101 clock
.vco
= refclk
* clock
.m1
* clock
.m2
/ clock
.n
;
5102 clock
.dot
= 2 * clock
.vco
/ (clock
.p1
* clock
.p2
);
5104 pipe_config
->port_clock
= clock
.dot
/ 10;
5107 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
5108 struct intel_crtc_config
*pipe_config
)
5110 struct drm_device
*dev
= crtc
->base
.dev
;
5111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5114 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
5115 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
5117 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
5118 if (!(tmp
& PIPECONF_ENABLE
))
5121 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
5122 switch (tmp
& PIPECONF_BPC_MASK
) {
5124 pipe_config
->pipe_bpp
= 18;
5127 pipe_config
->pipe_bpp
= 24;
5129 case PIPECONF_10BPC
:
5130 pipe_config
->pipe_bpp
= 30;
5137 if (INTEL_INFO(dev
)->gen
< 4)
5138 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
5140 intel_get_pipe_timings(crtc
, pipe_config
);
5142 i9xx_get_pfit_config(crtc
, pipe_config
);
5144 if (INTEL_INFO(dev
)->gen
>= 4) {
5145 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
5146 pipe_config
->pixel_multiplier
=
5147 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
5148 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
5149 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
5150 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5151 tmp
= I915_READ(DPLL(crtc
->pipe
));
5152 pipe_config
->pixel_multiplier
=
5153 ((tmp
& SDVO_MULTIPLIER_MASK
)
5154 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
5156 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5157 * port and will be fixed up in the encoder->get_config
5159 pipe_config
->pixel_multiplier
= 1;
5161 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
5162 if (!IS_VALLEYVIEW(dev
)) {
5163 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
5164 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
5166 /* Mask out read-only status bits. */
5167 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
5168 DPLL_PORTC_READY_MASK
|
5169 DPLL_PORTB_READY_MASK
);
5172 if (IS_VALLEYVIEW(dev
))
5173 vlv_crtc_clock_get(crtc
, pipe_config
);
5175 i9xx_crtc_clock_get(crtc
, pipe_config
);
5180 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
5182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5183 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5184 struct intel_encoder
*encoder
;
5186 bool has_lvds
= false;
5187 bool has_cpu_edp
= false;
5188 bool has_panel
= false;
5189 bool has_ck505
= false;
5190 bool can_ssc
= false;
5192 /* We need to take the global config into account */
5193 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
5195 switch (encoder
->type
) {
5196 case INTEL_OUTPUT_LVDS
:
5200 case INTEL_OUTPUT_EDP
:
5202 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
5208 if (HAS_PCH_IBX(dev
)) {
5209 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
5210 can_ssc
= has_ck505
;
5216 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5217 has_panel
, has_lvds
, has_ck505
);
5219 /* Ironlake: try to setup display ref clock before DPLL
5220 * enabling. This is only under driver's control after
5221 * PCH B stepping, previous chipset stepping should be
5222 * ignoring this setting.
5224 val
= I915_READ(PCH_DREF_CONTROL
);
5226 /* As we must carefully and slowly disable/enable each source in turn,
5227 * compute the final state we want first and check if we need to
5228 * make any changes at all.
5231 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5233 final
|= DREF_NONSPREAD_CK505_ENABLE
;
5235 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5237 final
&= ~DREF_SSC_SOURCE_MASK
;
5238 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5239 final
&= ~DREF_SSC1_ENABLE
;
5242 final
|= DREF_SSC_SOURCE_ENABLE
;
5244 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5245 final
|= DREF_SSC1_ENABLE
;
5248 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
5249 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5251 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5253 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5255 final
|= DREF_SSC_SOURCE_DISABLE
;
5256 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5262 /* Always enable nonspread source */
5263 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
5266 val
|= DREF_NONSPREAD_CK505_ENABLE
;
5268 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
5271 val
&= ~DREF_SSC_SOURCE_MASK
;
5272 val
|= DREF_SSC_SOURCE_ENABLE
;
5274 /* SSC must be turned on before enabling the CPU output */
5275 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5276 DRM_DEBUG_KMS("Using SSC on panel\n");
5277 val
|= DREF_SSC1_ENABLE
;
5279 val
&= ~DREF_SSC1_ENABLE
;
5281 /* Get SSC going before enabling the outputs */
5282 I915_WRITE(PCH_DREF_CONTROL
, val
);
5283 POSTING_READ(PCH_DREF_CONTROL
);
5286 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5288 /* Enable CPU source on CPU attached eDP */
5290 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
5291 DRM_DEBUG_KMS("Using SSC on eDP\n");
5292 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
5295 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
5297 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5299 I915_WRITE(PCH_DREF_CONTROL
, val
);
5300 POSTING_READ(PCH_DREF_CONTROL
);
5303 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5305 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
5307 /* Turn off CPU output */
5308 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
5310 I915_WRITE(PCH_DREF_CONTROL
, val
);
5311 POSTING_READ(PCH_DREF_CONTROL
);
5314 /* Turn off the SSC source */
5315 val
&= ~DREF_SSC_SOURCE_MASK
;
5316 val
|= DREF_SSC_SOURCE_DISABLE
;
5319 val
&= ~DREF_SSC1_ENABLE
;
5321 I915_WRITE(PCH_DREF_CONTROL
, val
);
5322 POSTING_READ(PCH_DREF_CONTROL
);
5326 BUG_ON(val
!= final
);
5329 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
5333 tmp
= I915_READ(SOUTH_CHICKEN2
);
5334 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
5335 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5337 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
5338 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
5339 DRM_ERROR("FDI mPHY reset assert timeout\n");
5341 tmp
= I915_READ(SOUTH_CHICKEN2
);
5342 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
5343 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
5345 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
5346 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
5347 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5350 /* WaMPhyProgramming:hsw */
5351 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
5355 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
5356 tmp
&= ~(0xFF << 24);
5357 tmp
|= (0x12 << 24);
5358 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
5360 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
5362 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
5364 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
5366 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
5368 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
5369 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5370 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
5372 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
5373 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
5374 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
5376 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
5379 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
5381 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
5384 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
5386 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
5389 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
5391 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
5394 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
5396 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
5397 tmp
&= ~(0xFF << 16);
5398 tmp
|= (0x1C << 16);
5399 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
5401 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
5402 tmp
&= ~(0xFF << 16);
5403 tmp
|= (0x1C << 16);
5404 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
5406 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
5408 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
5410 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
5412 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
5414 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
5415 tmp
&= ~(0xF << 28);
5417 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
5419 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
5420 tmp
&= ~(0xF << 28);
5422 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
5425 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5426 * Programming" based on the parameters passed:
5427 * - Sequence to enable CLKOUT_DP
5428 * - Sequence to enable CLKOUT_DP without spread
5429 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5431 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
5434 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5437 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
5439 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
5440 with_fdi
, "LP PCH doesn't have FDI\n"))
5443 mutex_lock(&dev_priv
->dpio_lock
);
5445 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5446 tmp
&= ~SBI_SSCCTL_DISABLE
;
5447 tmp
|= SBI_SSCCTL_PATHALT
;
5448 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5453 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5454 tmp
&= ~SBI_SSCCTL_PATHALT
;
5455 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5458 lpt_reset_fdi_mphy(dev_priv
);
5459 lpt_program_fdi_mphy(dev_priv
);
5463 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5464 SBI_GEN0
: SBI_DBUFF0
;
5465 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5466 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5467 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5469 mutex_unlock(&dev_priv
->dpio_lock
);
5472 /* Sequence to disable CLKOUT_DP */
5473 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
5475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5478 mutex_lock(&dev_priv
->dpio_lock
);
5480 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
5481 SBI_GEN0
: SBI_DBUFF0
;
5482 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
5483 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
5484 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
5486 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
5487 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
5488 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
5489 tmp
|= SBI_SSCCTL_PATHALT
;
5490 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5493 tmp
|= SBI_SSCCTL_DISABLE
;
5494 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
5497 mutex_unlock(&dev_priv
->dpio_lock
);
5500 static void lpt_init_pch_refclk(struct drm_device
*dev
)
5502 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
5503 struct intel_encoder
*encoder
;
5504 bool has_vga
= false;
5506 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
5507 switch (encoder
->type
) {
5508 case INTEL_OUTPUT_ANALOG
:
5515 lpt_enable_clkout_dp(dev
, true, true);
5517 lpt_disable_clkout_dp(dev
);
5521 * Initialize reference clocks when the driver loads
5523 void intel_init_pch_refclk(struct drm_device
*dev
)
5525 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5526 ironlake_init_pch_refclk(dev
);
5527 else if (HAS_PCH_LPT(dev
))
5528 lpt_init_pch_refclk(dev
);
5531 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
5533 struct drm_device
*dev
= crtc
->dev
;
5534 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5535 struct intel_encoder
*encoder
;
5536 int num_connectors
= 0;
5537 bool is_lvds
= false;
5539 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5540 switch (encoder
->type
) {
5541 case INTEL_OUTPUT_LVDS
:
5548 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5549 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5550 dev_priv
->vbt
.lvds_ssc_freq
);
5551 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
5557 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
5559 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5560 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5561 int pipe
= intel_crtc
->pipe
;
5566 switch (intel_crtc
->config
.pipe_bpp
) {
5568 val
|= PIPECONF_6BPC
;
5571 val
|= PIPECONF_8BPC
;
5574 val
|= PIPECONF_10BPC
;
5577 val
|= PIPECONF_12BPC
;
5580 /* Case prevented by intel_choose_pipe_bpp_dither. */
5584 if (intel_crtc
->config
.dither
)
5585 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5587 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5588 val
|= PIPECONF_INTERLACED_ILK
;
5590 val
|= PIPECONF_PROGRESSIVE
;
5592 if (intel_crtc
->config
.limited_color_range
)
5593 val
|= PIPECONF_COLOR_RANGE_SELECT
;
5595 I915_WRITE(PIPECONF(pipe
), val
);
5596 POSTING_READ(PIPECONF(pipe
));
5600 * Set up the pipe CSC unit.
5602 * Currently only full range RGB to limited range RGB conversion
5603 * is supported, but eventually this should handle various
5604 * RGB<->YCbCr scenarios as well.
5606 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
5608 struct drm_device
*dev
= crtc
->dev
;
5609 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5610 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5611 int pipe
= intel_crtc
->pipe
;
5612 uint16_t coeff
= 0x7800; /* 1.0 */
5615 * TODO: Check what kind of values actually come out of the pipe
5616 * with these coeff/postoff values and adjust to get the best
5617 * accuracy. Perhaps we even need to take the bpc value into
5621 if (intel_crtc
->config
.limited_color_range
)
5622 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5625 * GY/GU and RY/RU should be the other way around according
5626 * to BSpec, but reality doesn't agree. Just set them up in
5627 * a way that results in the correct picture.
5629 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
5630 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
5632 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
5633 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
5635 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
5636 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
5638 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
5639 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
5640 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
5642 if (INTEL_INFO(dev
)->gen
> 6) {
5643 uint16_t postoff
= 0;
5645 if (intel_crtc
->config
.limited_color_range
)
5646 postoff
= (16 * (1 << 13) / 255) & 0x1fff;
5648 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
5649 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
5650 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
5652 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
5654 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
5656 if (intel_crtc
->config
.limited_color_range
)
5657 mode
|= CSC_BLACK_SCREEN_OFFSET
;
5659 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
5663 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
5665 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5666 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5667 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5672 if (intel_crtc
->config
.dither
)
5673 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
5675 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
5676 val
|= PIPECONF_INTERLACED_ILK
;
5678 val
|= PIPECONF_PROGRESSIVE
;
5680 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
5681 POSTING_READ(PIPECONF(cpu_transcoder
));
5683 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
5684 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
5687 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
5688 intel_clock_t
*clock
,
5689 bool *has_reduced_clock
,
5690 intel_clock_t
*reduced_clock
)
5692 struct drm_device
*dev
= crtc
->dev
;
5693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5694 struct intel_encoder
*intel_encoder
;
5696 const intel_limit_t
*limit
;
5697 bool ret
, is_lvds
= false;
5699 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5700 switch (intel_encoder
->type
) {
5701 case INTEL_OUTPUT_LVDS
:
5707 refclk
= ironlake_get_refclk(crtc
);
5710 * Returns a set of divisors for the desired target clock with the given
5711 * refclk, or FALSE. The returned values represent the clock equation:
5712 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5714 limit
= intel_limit(crtc
, refclk
);
5715 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
5716 to_intel_crtc(crtc
)->config
.port_clock
,
5717 refclk
, NULL
, clock
);
5721 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5723 * Ensure we match the reduced clock's P to the target clock.
5724 * If the clocks don't match, we can't switch the display clock
5725 * by using the FP0/FP1. In such case we will disable the LVDS
5726 * downclock feature.
5728 *has_reduced_clock
=
5729 dev_priv
->display
.find_dpll(limit
, crtc
,
5730 dev_priv
->lvds_downclock
,
5738 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5743 temp
= I915_READ(SOUTH_CHICKEN1
);
5744 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5747 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5748 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5750 temp
|= FDI_BC_BIFURCATION_SELECT
;
5751 DRM_DEBUG_KMS("enabling fdi C rx\n");
5752 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5753 POSTING_READ(SOUTH_CHICKEN1
);
5756 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
5758 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5761 switch (intel_crtc
->pipe
) {
5765 if (intel_crtc
->config
.fdi_lanes
> 2)
5766 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5768 cpt_enable_fdi_bc_bifurcation(dev
);
5772 cpt_enable_fdi_bc_bifurcation(dev
);
5780 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
5783 * Account for spread spectrum to avoid
5784 * oversubscribing the link. Max center spread
5785 * is 2.5%; use 5% for safety's sake.
5787 u32 bps
= target_clock
* bpp
* 21 / 20;
5788 return bps
/ (link_bw
* 8) + 1;
5791 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
5793 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
5796 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5798 intel_clock_t
*reduced_clock
, u32
*fp2
)
5800 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5801 struct drm_device
*dev
= crtc
->dev
;
5802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5803 struct intel_encoder
*intel_encoder
;
5805 int factor
, num_connectors
= 0;
5806 bool is_lvds
= false, is_sdvo
= false;
5808 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5809 switch (intel_encoder
->type
) {
5810 case INTEL_OUTPUT_LVDS
:
5813 case INTEL_OUTPUT_SDVO
:
5814 case INTEL_OUTPUT_HDMI
:
5822 /* Enable autotuning of the PLL clock (if permissible) */
5825 if ((intel_panel_use_ssc(dev_priv
) &&
5826 dev_priv
->vbt
.lvds_ssc_freq
== 100) ||
5827 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
5829 } else if (intel_crtc
->config
.sdvo_tv_clock
)
5832 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
5835 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
5841 dpll
|= DPLLB_MODE_LVDS
;
5843 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5845 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
5846 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5849 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5850 if (intel_crtc
->config
.has_dp_encoder
)
5851 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5853 /* compute bitmask from p1 value */
5854 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5856 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5858 switch (intel_crtc
->config
.dpll
.p2
) {
5860 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5863 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5866 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5869 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5873 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5874 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5876 dpll
|= PLL_REF_INPUT_DREFCLK
;
5878 return dpll
| DPLL_VCO_ENABLE
;
5881 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5883 struct drm_framebuffer
*fb
)
5885 struct drm_device
*dev
= crtc
->dev
;
5886 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5887 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5888 int pipe
= intel_crtc
->pipe
;
5889 int plane
= intel_crtc
->plane
;
5890 int num_connectors
= 0;
5891 intel_clock_t clock
, reduced_clock
;
5892 u32 dpll
= 0, fp
= 0, fp2
= 0;
5893 bool ok
, has_reduced_clock
= false;
5894 bool is_lvds
= false;
5895 struct intel_encoder
*encoder
;
5896 struct intel_shared_dpll
*pll
;
5899 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5900 switch (encoder
->type
) {
5901 case INTEL_OUTPUT_LVDS
:
5909 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5910 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5912 ok
= ironlake_compute_clocks(crtc
, &clock
,
5913 &has_reduced_clock
, &reduced_clock
);
5914 if (!ok
&& !intel_crtc
->config
.clock_set
) {
5915 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5918 /* Compat-code for transition, will disappear. */
5919 if (!intel_crtc
->config
.clock_set
) {
5920 intel_crtc
->config
.dpll
.n
= clock
.n
;
5921 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
5922 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
5923 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
5924 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
5927 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5928 if (intel_crtc
->config
.has_pch_encoder
) {
5929 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
5930 if (has_reduced_clock
)
5931 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
5933 dpll
= ironlake_compute_dpll(intel_crtc
,
5934 &fp
, &reduced_clock
,
5935 has_reduced_clock
? &fp2
: NULL
);
5937 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5938 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
5939 if (has_reduced_clock
)
5940 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5942 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
5944 pll
= intel_get_shared_dpll(intel_crtc
);
5946 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5951 intel_put_shared_dpll(intel_crtc
);
5953 if (intel_crtc
->config
.has_dp_encoder
)
5954 intel_dp_set_m_n(intel_crtc
);
5956 if (is_lvds
&& has_reduced_clock
&& i915_powersave
)
5957 intel_crtc
->lowfreq_avail
= true;
5959 intel_crtc
->lowfreq_avail
= false;
5961 if (intel_crtc
->config
.has_pch_encoder
) {
5962 pll
= intel_crtc_to_shared_dpll(intel_crtc
);
5966 intel_set_pipe_timings(intel_crtc
);
5968 if (intel_crtc
->config
.has_pch_encoder
) {
5969 intel_cpu_transcoder_set_m_n(intel_crtc
,
5970 &intel_crtc
->config
.fdi_m_n
);
5973 if (IS_IVYBRIDGE(dev
))
5974 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
5976 ironlake_set_pipeconf(crtc
);
5978 /* Set up the display plane register */
5979 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5980 POSTING_READ(DSPCNTR(plane
));
5982 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5987 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
5988 struct intel_link_m_n
*m_n
)
5990 struct drm_device
*dev
= crtc
->base
.dev
;
5991 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5992 enum pipe pipe
= crtc
->pipe
;
5994 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
5995 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
5996 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
5998 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
5999 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
6000 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6003 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
6004 enum transcoder transcoder
,
6005 struct intel_link_m_n
*m_n
)
6007 struct drm_device
*dev
= crtc
->base
.dev
;
6008 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6009 enum pipe pipe
= crtc
->pipe
;
6011 if (INTEL_INFO(dev
)->gen
>= 5) {
6012 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
6013 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
6014 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
6016 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
6017 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
6018 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6020 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
6021 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
6022 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
6024 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
6025 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
6026 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
6030 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
6031 struct intel_crtc_config
*pipe_config
)
6033 if (crtc
->config
.has_pch_encoder
)
6034 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
6036 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6037 &pipe_config
->dp_m_n
);
6040 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
6041 struct intel_crtc_config
*pipe_config
)
6043 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
6044 &pipe_config
->fdi_m_n
);
6047 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
6048 struct intel_crtc_config
*pipe_config
)
6050 struct drm_device
*dev
= crtc
->base
.dev
;
6051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6054 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
6056 if (tmp
& PF_ENABLE
) {
6057 pipe_config
->pch_pfit
.enabled
= true;
6058 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
6059 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
6061 /* We currently do not free assignements of panel fitters on
6062 * ivb/hsw (since we don't use the higher upscaling modes which
6063 * differentiates them) so just WARN about this case for now. */
6065 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
6066 PF_PIPE_SEL_IVB(crtc
->pipe
));
6071 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
6072 struct intel_crtc_config
*pipe_config
)
6074 struct drm_device
*dev
= crtc
->base
.dev
;
6075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6078 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6079 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6081 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6082 if (!(tmp
& PIPECONF_ENABLE
))
6085 switch (tmp
& PIPECONF_BPC_MASK
) {
6087 pipe_config
->pipe_bpp
= 18;
6090 pipe_config
->pipe_bpp
= 24;
6092 case PIPECONF_10BPC
:
6093 pipe_config
->pipe_bpp
= 30;
6095 case PIPECONF_12BPC
:
6096 pipe_config
->pipe_bpp
= 36;
6102 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
6103 struct intel_shared_dpll
*pll
;
6105 pipe_config
->has_pch_encoder
= true;
6107 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
6108 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6109 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6111 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6113 if (HAS_PCH_IBX(dev_priv
->dev
)) {
6114 pipe_config
->shared_dpll
=
6115 (enum intel_dpll_id
) crtc
->pipe
;
6117 tmp
= I915_READ(PCH_DPLL_SEL
);
6118 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
6119 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
6121 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
6124 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
6126 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
6127 &pipe_config
->dpll_hw_state
));
6129 tmp
= pipe_config
->dpll_hw_state
.dpll
;
6130 pipe_config
->pixel_multiplier
=
6131 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
6132 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
6134 ironlake_pch_clock_get(crtc
, pipe_config
);
6136 pipe_config
->pixel_multiplier
= 1;
6139 intel_get_pipe_timings(crtc
, pipe_config
);
6141 ironlake_get_pfit_config(crtc
, pipe_config
);
6146 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
6148 struct drm_device
*dev
= dev_priv
->dev
;
6149 struct intel_ddi_plls
*plls
= &dev_priv
->ddi_plls
;
6150 struct intel_crtc
*crtc
;
6151 unsigned long irqflags
;
6154 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6155 WARN(crtc
->base
.enabled
, "CRTC for pipe %c enabled\n",
6156 pipe_name(crtc
->pipe
));
6158 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
6159 WARN(plls
->spll_refcount
, "SPLL enabled\n");
6160 WARN(plls
->wrpll1_refcount
, "WRPLL1 enabled\n");
6161 WARN(plls
->wrpll2_refcount
, "WRPLL2 enabled\n");
6162 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
6163 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
6164 "CPU PWM1 enabled\n");
6165 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
6166 "CPU PWM2 enabled\n");
6167 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
6168 "PCH PWM1 enabled\n");
6169 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
6170 "Utility pin enabled\n");
6171 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
6173 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
6174 val
= I915_READ(DEIMR
);
6175 WARN((val
& ~DE_PCH_EVENT_IVB
) != val
,
6176 "Unexpected DEIMR bits enabled: 0x%x\n", val
);
6177 val
= I915_READ(SDEIMR
);
6178 WARN((val
| SDE_HOTPLUG_MASK_CPT
) != 0xffffffff,
6179 "Unexpected SDEIMR bits enabled: 0x%x\n", val
);
6180 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
6184 * This function implements pieces of two sequences from BSpec:
6185 * - Sequence for display software to disable LCPLL
6186 * - Sequence for display software to allow package C8+
6187 * The steps implemented here are just the steps that actually touch the LCPLL
6188 * register. Callers should take care of disabling all the display engine
6189 * functions, doing the mode unset, fixing interrupts, etc.
6191 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
6192 bool switch_to_fclk
, bool allow_power_down
)
6196 assert_can_disable_lcpll(dev_priv
);
6198 val
= I915_READ(LCPLL_CTL
);
6200 if (switch_to_fclk
) {
6201 val
|= LCPLL_CD_SOURCE_FCLK
;
6202 I915_WRITE(LCPLL_CTL
, val
);
6204 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
6205 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
6206 DRM_ERROR("Switching to FCLK failed\n");
6208 val
= I915_READ(LCPLL_CTL
);
6211 val
|= LCPLL_PLL_DISABLE
;
6212 I915_WRITE(LCPLL_CTL
, val
);
6213 POSTING_READ(LCPLL_CTL
);
6215 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
6216 DRM_ERROR("LCPLL still locked\n");
6218 val
= I915_READ(D_COMP
);
6219 val
|= D_COMP_COMP_DISABLE
;
6220 mutex_lock(&dev_priv
->rps
.hw_lock
);
6221 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6222 DRM_ERROR("Failed to disable D_COMP\n");
6223 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6224 POSTING_READ(D_COMP
);
6227 if (wait_for((I915_READ(D_COMP
) & D_COMP_RCOMP_IN_PROGRESS
) == 0, 1))
6228 DRM_ERROR("D_COMP RCOMP still in progress\n");
6230 if (allow_power_down
) {
6231 val
= I915_READ(LCPLL_CTL
);
6232 val
|= LCPLL_POWER_DOWN_ALLOW
;
6233 I915_WRITE(LCPLL_CTL
, val
);
6234 POSTING_READ(LCPLL_CTL
);
6239 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6242 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
6246 val
= I915_READ(LCPLL_CTL
);
6248 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
6249 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
6252 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6253 * we'll hang the machine! */
6254 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
);
6256 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
6257 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
6258 I915_WRITE(LCPLL_CTL
, val
);
6259 POSTING_READ(LCPLL_CTL
);
6262 val
= I915_READ(D_COMP
);
6263 val
|= D_COMP_COMP_FORCE
;
6264 val
&= ~D_COMP_COMP_DISABLE
;
6265 mutex_lock(&dev_priv
->rps
.hw_lock
);
6266 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
, val
))
6267 DRM_ERROR("Failed to enable D_COMP\n");
6268 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6269 POSTING_READ(D_COMP
);
6271 val
= I915_READ(LCPLL_CTL
);
6272 val
&= ~LCPLL_PLL_DISABLE
;
6273 I915_WRITE(LCPLL_CTL
, val
);
6275 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
6276 DRM_ERROR("LCPLL not locked yet\n");
6278 if (val
& LCPLL_CD_SOURCE_FCLK
) {
6279 val
= I915_READ(LCPLL_CTL
);
6280 val
&= ~LCPLL_CD_SOURCE_FCLK
;
6281 I915_WRITE(LCPLL_CTL
, val
);
6283 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
6284 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
6285 DRM_ERROR("Switching back to LCPLL failed\n");
6288 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
);
6291 void hsw_enable_pc8_work(struct work_struct
*__work
)
6293 struct drm_i915_private
*dev_priv
=
6294 container_of(to_delayed_work(__work
), struct drm_i915_private
,
6296 struct drm_device
*dev
= dev_priv
->dev
;
6299 if (dev_priv
->pc8
.enabled
)
6302 DRM_DEBUG_KMS("Enabling package C8+\n");
6304 dev_priv
->pc8
.enabled
= true;
6306 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6307 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6308 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
6309 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6312 lpt_disable_clkout_dp(dev
);
6313 hsw_pc8_disable_interrupts(dev
);
6314 hsw_disable_lcpll(dev_priv
, true, true);
6317 static void __hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6319 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6320 WARN(dev_priv
->pc8
.disable_count
< 1,
6321 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6323 dev_priv
->pc8
.disable_count
--;
6324 if (dev_priv
->pc8
.disable_count
!= 0)
6327 schedule_delayed_work(&dev_priv
->pc8
.enable_work
,
6328 msecs_to_jiffies(i915_pc8_timeout
));
6331 static void __hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6333 struct drm_device
*dev
= dev_priv
->dev
;
6336 WARN_ON(!mutex_is_locked(&dev_priv
->pc8
.lock
));
6337 WARN(dev_priv
->pc8
.disable_count
< 0,
6338 "pc8.disable_count: %d\n", dev_priv
->pc8
.disable_count
);
6340 dev_priv
->pc8
.disable_count
++;
6341 if (dev_priv
->pc8
.disable_count
!= 1)
6344 cancel_delayed_work_sync(&dev_priv
->pc8
.enable_work
);
6345 if (!dev_priv
->pc8
.enabled
)
6348 DRM_DEBUG_KMS("Disabling package C8+\n");
6350 hsw_restore_lcpll(dev_priv
);
6351 hsw_pc8_restore_interrupts(dev
);
6352 lpt_init_pch_refclk(dev
);
6354 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
6355 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
6356 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
6357 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
6360 intel_prepare_ddi(dev
);
6361 i915_gem_init_swizzling(dev
);
6362 mutex_lock(&dev_priv
->rps
.hw_lock
);
6363 gen6_update_ring_freq(dev
);
6364 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6365 dev_priv
->pc8
.enabled
= false;
6368 void hsw_enable_package_c8(struct drm_i915_private
*dev_priv
)
6370 mutex_lock(&dev_priv
->pc8
.lock
);
6371 __hsw_enable_package_c8(dev_priv
);
6372 mutex_unlock(&dev_priv
->pc8
.lock
);
6375 void hsw_disable_package_c8(struct drm_i915_private
*dev_priv
)
6377 mutex_lock(&dev_priv
->pc8
.lock
);
6378 __hsw_disable_package_c8(dev_priv
);
6379 mutex_unlock(&dev_priv
->pc8
.lock
);
6382 static bool hsw_can_enable_package_c8(struct drm_i915_private
*dev_priv
)
6384 struct drm_device
*dev
= dev_priv
->dev
;
6385 struct intel_crtc
*crtc
;
6388 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
)
6389 if (crtc
->base
.enabled
)
6392 /* This case is still possible since we have the i915.disable_power_well
6393 * parameter and also the KVMr or something else might be requesting the
6395 val
= I915_READ(HSW_PWR_WELL_DRIVER
);
6397 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6404 /* Since we're called from modeset_global_resources there's no way to
6405 * symmetrically increase and decrease the refcount, so we use
6406 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6409 static void hsw_update_package_c8(struct drm_device
*dev
)
6411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6414 if (!i915_enable_pc8
)
6417 mutex_lock(&dev_priv
->pc8
.lock
);
6419 allow
= hsw_can_enable_package_c8(dev_priv
);
6421 if (allow
== dev_priv
->pc8
.requirements_met
)
6424 dev_priv
->pc8
.requirements_met
= allow
;
6427 __hsw_enable_package_c8(dev_priv
);
6429 __hsw_disable_package_c8(dev_priv
);
6432 mutex_unlock(&dev_priv
->pc8
.lock
);
6435 static void hsw_package_c8_gpu_idle(struct drm_i915_private
*dev_priv
)
6437 if (!dev_priv
->pc8
.gpu_idle
) {
6438 dev_priv
->pc8
.gpu_idle
= true;
6439 hsw_enable_package_c8(dev_priv
);
6443 static void hsw_package_c8_gpu_busy(struct drm_i915_private
*dev_priv
)
6445 if (dev_priv
->pc8
.gpu_idle
) {
6446 dev_priv
->pc8
.gpu_idle
= false;
6447 hsw_disable_package_c8(dev_priv
);
6451 static void haswell_modeset_global_resources(struct drm_device
*dev
)
6453 bool enable
= false;
6454 struct intel_crtc
*crtc
;
6456 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
6457 if (!crtc
->base
.enabled
)
6460 if (crtc
->pipe
!= PIPE_A
|| crtc
->config
.pch_pfit
.enabled
||
6461 crtc
->config
.cpu_transcoder
!= TRANSCODER_EDP
)
6465 intel_set_power_well(dev
, enable
);
6467 hsw_update_package_c8(dev
);
6470 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
6472 struct drm_framebuffer
*fb
)
6474 struct drm_device
*dev
= crtc
->dev
;
6475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6476 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6477 int plane
= intel_crtc
->plane
;
6480 if (!intel_ddi_pll_mode_set(crtc
))
6483 if (intel_crtc
->config
.has_dp_encoder
)
6484 intel_dp_set_m_n(intel_crtc
);
6486 intel_crtc
->lowfreq_avail
= false;
6488 intel_set_pipe_timings(intel_crtc
);
6490 if (intel_crtc
->config
.has_pch_encoder
) {
6491 intel_cpu_transcoder_set_m_n(intel_crtc
,
6492 &intel_crtc
->config
.fdi_m_n
);
6495 haswell_set_pipeconf(crtc
);
6497 intel_set_pipe_csc(crtc
);
6499 /* Set up the display plane register */
6500 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
| DISPPLANE_PIPE_CSC_ENABLE
);
6501 POSTING_READ(DSPCNTR(plane
));
6503 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
6508 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
6509 struct intel_crtc_config
*pipe_config
)
6511 struct drm_device
*dev
= crtc
->base
.dev
;
6512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6513 enum intel_display_power_domain pfit_domain
;
6516 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6517 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6519 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
6520 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
6521 enum pipe trans_edp_pipe
;
6522 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
6524 WARN(1, "unknown pipe linked to edp transcoder\n");
6525 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
6526 case TRANS_DDI_EDP_INPUT_A_ON
:
6527 trans_edp_pipe
= PIPE_A
;
6529 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
6530 trans_edp_pipe
= PIPE_B
;
6532 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
6533 trans_edp_pipe
= PIPE_C
;
6537 if (trans_edp_pipe
== crtc
->pipe
)
6538 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
6541 if (!intel_display_power_enabled(dev
,
6542 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
6545 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
6546 if (!(tmp
& PIPECONF_ENABLE
))
6550 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6551 * DDI E. So just check whether this pipe is wired to DDI E and whether
6552 * the PCH transcoder is on.
6554 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
6555 if ((tmp
& TRANS_DDI_PORT_MASK
) == TRANS_DDI_SELECT_PORT(PORT_E
) &&
6556 I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
6557 pipe_config
->has_pch_encoder
= true;
6559 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
6560 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
6561 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
6563 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
6566 intel_get_pipe_timings(crtc
, pipe_config
);
6568 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
6569 if (intel_display_power_enabled(dev
, pfit_domain
))
6570 ironlake_get_pfit_config(crtc
, pipe_config
);
6572 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
6573 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
6575 pipe_config
->pixel_multiplier
= 1;
6580 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
6582 struct drm_framebuffer
*fb
)
6584 struct drm_device
*dev
= crtc
->dev
;
6585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6586 struct intel_encoder
*encoder
;
6587 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6588 struct drm_display_mode
*mode
= &intel_crtc
->config
.requested_mode
;
6589 int pipe
= intel_crtc
->pipe
;
6592 drm_vblank_pre_modeset(dev
, pipe
);
6594 ret
= dev_priv
->display
.crtc_mode_set(crtc
, x
, y
, fb
);
6596 drm_vblank_post_modeset(dev
, pipe
);
6601 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6602 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6603 encoder
->base
.base
.id
,
6604 drm_get_encoder_name(&encoder
->base
),
6605 mode
->base
.id
, mode
->name
);
6606 encoder
->mode_set(encoder
);
6612 static bool intel_eld_uptodate(struct drm_connector
*connector
,
6613 int reg_eldv
, uint32_t bits_eldv
,
6614 int reg_elda
, uint32_t bits_elda
,
6617 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6618 uint8_t *eld
= connector
->eld
;
6621 i
= I915_READ(reg_eldv
);
6630 i
= I915_READ(reg_elda
);
6632 I915_WRITE(reg_elda
, i
);
6634 for (i
= 0; i
< eld
[2]; i
++)
6635 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
6641 static void g4x_write_eld(struct drm_connector
*connector
,
6642 struct drm_crtc
*crtc
)
6644 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6645 uint8_t *eld
= connector
->eld
;
6650 i
= I915_READ(G4X_AUD_VID_DID
);
6652 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
6653 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
6655 eldv
= G4X_ELDV_DEVCTG
;
6657 if (intel_eld_uptodate(connector
,
6658 G4X_AUD_CNTL_ST
, eldv
,
6659 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
6660 G4X_HDMIW_HDMIEDID
))
6663 i
= I915_READ(G4X_AUD_CNTL_ST
);
6664 i
&= ~(eldv
| G4X_ELD_ADDR
);
6665 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
6666 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6671 len
= min_t(uint8_t, eld
[2], len
);
6672 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6673 for (i
= 0; i
< len
; i
++)
6674 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
6676 i
= I915_READ(G4X_AUD_CNTL_ST
);
6678 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
6681 static void haswell_write_eld(struct drm_connector
*connector
,
6682 struct drm_crtc
*crtc
)
6684 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6685 uint8_t *eld
= connector
->eld
;
6686 struct drm_device
*dev
= crtc
->dev
;
6687 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6691 int pipe
= to_intel_crtc(crtc
)->pipe
;
6694 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
6695 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
6696 int aud_config
= HSW_AUD_CFG(pipe
);
6697 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
6700 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6702 /* Audio output enable */
6703 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6704 tmp
= I915_READ(aud_cntrl_st2
);
6705 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
6706 I915_WRITE(aud_cntrl_st2
, tmp
);
6708 /* Wait for 1 vertical blank */
6709 intel_wait_for_vblank(dev
, pipe
);
6711 /* Set ELD valid state */
6712 tmp
= I915_READ(aud_cntrl_st2
);
6713 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
6714 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
6715 I915_WRITE(aud_cntrl_st2
, tmp
);
6716 tmp
= I915_READ(aud_cntrl_st2
);
6717 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
6719 /* Enable HDMI mode */
6720 tmp
= I915_READ(aud_config
);
6721 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
6722 /* clear N_programing_enable and N_value_index */
6723 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
6724 I915_WRITE(aud_config
, tmp
);
6726 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6728 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
6729 intel_crtc
->eld_vld
= true;
6731 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6732 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6733 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6734 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6736 I915_WRITE(aud_config
, 0);
6738 if (intel_eld_uptodate(connector
,
6739 aud_cntrl_st2
, eldv
,
6740 aud_cntl_st
, IBX_ELD_ADDRESS
,
6744 i
= I915_READ(aud_cntrl_st2
);
6746 I915_WRITE(aud_cntrl_st2
, i
);
6751 i
= I915_READ(aud_cntl_st
);
6752 i
&= ~IBX_ELD_ADDRESS
;
6753 I915_WRITE(aud_cntl_st
, i
);
6754 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6755 DRM_DEBUG_DRIVER("port num:%d\n", i
);
6757 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6758 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6759 for (i
= 0; i
< len
; i
++)
6760 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6762 i
= I915_READ(aud_cntrl_st2
);
6764 I915_WRITE(aud_cntrl_st2
, i
);
6768 static void ironlake_write_eld(struct drm_connector
*connector
,
6769 struct drm_crtc
*crtc
)
6771 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
6772 uint8_t *eld
= connector
->eld
;
6780 int pipe
= to_intel_crtc(crtc
)->pipe
;
6782 if (HAS_PCH_IBX(connector
->dev
)) {
6783 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
6784 aud_config
= IBX_AUD_CFG(pipe
);
6785 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
6786 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
6788 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
6789 aud_config
= CPT_AUD_CFG(pipe
);
6790 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
6791 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
6794 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
6796 i
= I915_READ(aud_cntl_st
);
6797 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
6799 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6800 /* operate blindly on all ports */
6801 eldv
= IBX_ELD_VALIDB
;
6802 eldv
|= IBX_ELD_VALIDB
<< 4;
6803 eldv
|= IBX_ELD_VALIDB
<< 8;
6805 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
6806 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
6809 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
6810 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6811 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6812 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
6814 I915_WRITE(aud_config
, 0);
6816 if (intel_eld_uptodate(connector
,
6817 aud_cntrl_st2
, eldv
,
6818 aud_cntl_st
, IBX_ELD_ADDRESS
,
6822 i
= I915_READ(aud_cntrl_st2
);
6824 I915_WRITE(aud_cntrl_st2
, i
);
6829 i
= I915_READ(aud_cntl_st
);
6830 i
&= ~IBX_ELD_ADDRESS
;
6831 I915_WRITE(aud_cntl_st
, i
);
6833 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
6834 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
6835 for (i
= 0; i
< len
; i
++)
6836 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
6838 i
= I915_READ(aud_cntrl_st2
);
6840 I915_WRITE(aud_cntrl_st2
, i
);
6843 void intel_write_eld(struct drm_encoder
*encoder
,
6844 struct drm_display_mode
*mode
)
6846 struct drm_crtc
*crtc
= encoder
->crtc
;
6847 struct drm_connector
*connector
;
6848 struct drm_device
*dev
= encoder
->dev
;
6849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6851 connector
= drm_select_eld(encoder
, mode
);
6855 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6857 drm_get_connector_name(connector
),
6858 connector
->encoder
->base
.id
,
6859 drm_get_encoder_name(connector
->encoder
));
6861 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
6863 if (dev_priv
->display
.write_eld
)
6864 dev_priv
->display
.write_eld(connector
, crtc
);
6867 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6869 struct drm_device
*dev
= crtc
->dev
;
6870 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6872 bool visible
= base
!= 0;
6875 if (intel_crtc
->cursor_visible
== visible
)
6878 cntl
= I915_READ(_CURACNTR
);
6880 /* On these chipsets we can only modify the base whilst
6881 * the cursor is disabled.
6883 I915_WRITE(_CURABASE
, base
);
6885 cntl
&= ~(CURSOR_FORMAT_MASK
);
6886 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6887 cntl
|= CURSOR_ENABLE
|
6888 CURSOR_GAMMA_ENABLE
|
6891 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6892 I915_WRITE(_CURACNTR
, cntl
);
6894 intel_crtc
->cursor_visible
= visible
;
6897 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6899 struct drm_device
*dev
= crtc
->dev
;
6900 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6901 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6902 int pipe
= intel_crtc
->pipe
;
6903 bool visible
= base
!= 0;
6905 if (intel_crtc
->cursor_visible
!= visible
) {
6906 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6908 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6909 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6910 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6912 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6913 cntl
|= CURSOR_MODE_DISABLE
;
6915 I915_WRITE(CURCNTR(pipe
), cntl
);
6917 intel_crtc
->cursor_visible
= visible
;
6919 /* and commit changes on next vblank */
6920 I915_WRITE(CURBASE(pipe
), base
);
6923 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6925 struct drm_device
*dev
= crtc
->dev
;
6926 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6927 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6928 int pipe
= intel_crtc
->pipe
;
6929 bool visible
= base
!= 0;
6931 if (intel_crtc
->cursor_visible
!= visible
) {
6932 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6934 cntl
&= ~CURSOR_MODE
;
6935 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6937 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6938 cntl
|= CURSOR_MODE_DISABLE
;
6940 if (IS_HASWELL(dev
)) {
6941 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
6942 cntl
&= ~CURSOR_TRICKLE_FEED_DISABLE
;
6944 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6946 intel_crtc
->cursor_visible
= visible
;
6948 /* and commit changes on next vblank */
6949 I915_WRITE(CURBASE_IVB(pipe
), base
);
6952 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6953 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6956 struct drm_device
*dev
= crtc
->dev
;
6957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6958 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6959 int pipe
= intel_crtc
->pipe
;
6960 int x
= intel_crtc
->cursor_x
;
6961 int y
= intel_crtc
->cursor_y
;
6962 u32 base
= 0, pos
= 0;
6966 base
= intel_crtc
->cursor_addr
;
6968 if (x
>= intel_crtc
->config
.pipe_src_w
)
6971 if (y
>= intel_crtc
->config
.pipe_src_h
)
6975 if (x
+ intel_crtc
->cursor_width
<= 0)
6978 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6981 pos
|= x
<< CURSOR_X_SHIFT
;
6984 if (y
+ intel_crtc
->cursor_height
<= 0)
6987 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6990 pos
|= y
<< CURSOR_Y_SHIFT
;
6992 visible
= base
!= 0;
6993 if (!visible
&& !intel_crtc
->cursor_visible
)
6996 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6997 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6998 ivb_update_cursor(crtc
, base
);
7000 I915_WRITE(CURPOS(pipe
), pos
);
7001 if (IS_845G(dev
) || IS_I865G(dev
))
7002 i845_update_cursor(crtc
, base
);
7004 i9xx_update_cursor(crtc
, base
);
7008 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
7009 struct drm_file
*file
,
7011 uint32_t width
, uint32_t height
)
7013 struct drm_device
*dev
= crtc
->dev
;
7014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7015 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7016 struct drm_i915_gem_object
*obj
;
7020 /* if we want to turn off the cursor ignore width and height */
7022 DRM_DEBUG_KMS("cursor off\n");
7025 mutex_lock(&dev
->struct_mutex
);
7029 /* Currently we only support 64x64 cursors */
7030 if (width
!= 64 || height
!= 64) {
7031 DRM_ERROR("we currently only support 64x64 cursors\n");
7035 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
7036 if (&obj
->base
== NULL
)
7039 if (obj
->base
.size
< width
* height
* 4) {
7040 DRM_ERROR("buffer is to small\n");
7045 /* we only need to pin inside GTT if cursor is non-phy */
7046 mutex_lock(&dev
->struct_mutex
);
7047 if (!dev_priv
->info
->cursor_needs_physical
) {
7050 if (obj
->tiling_mode
) {
7051 DRM_ERROR("cursor cannot be tiled\n");
7056 /* Note that the w/a also requires 2 PTE of padding following
7057 * the bo. We currently fill all unused PTE with the shadow
7058 * page and so we should always have valid PTE following the
7059 * cursor preventing the VT-d warning.
7062 if (need_vtd_wa(dev
))
7063 alignment
= 64*1024;
7065 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
7067 DRM_ERROR("failed to move cursor bo into the GTT\n");
7071 ret
= i915_gem_object_put_fence(obj
);
7073 DRM_ERROR("failed to release fence for cursor");
7077 addr
= i915_gem_obj_ggtt_offset(obj
);
7079 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
7080 ret
= i915_gem_attach_phys_object(dev
, obj
,
7081 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
7084 DRM_ERROR("failed to attach phys object\n");
7087 addr
= obj
->phys_obj
->handle
->busaddr
;
7091 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
7094 if (intel_crtc
->cursor_bo
) {
7095 if (dev_priv
->info
->cursor_needs_physical
) {
7096 if (intel_crtc
->cursor_bo
!= obj
)
7097 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
7099 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
7100 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
7103 mutex_unlock(&dev
->struct_mutex
);
7105 intel_crtc
->cursor_addr
= addr
;
7106 intel_crtc
->cursor_bo
= obj
;
7107 intel_crtc
->cursor_width
= width
;
7108 intel_crtc
->cursor_height
= height
;
7110 if (intel_crtc
->active
)
7111 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7115 i915_gem_object_unpin_from_display_plane(obj
);
7117 mutex_unlock(&dev
->struct_mutex
);
7119 drm_gem_object_unreference_unlocked(&obj
->base
);
7123 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
7125 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7127 intel_crtc
->cursor_x
= x
;
7128 intel_crtc
->cursor_y
= y
;
7130 if (intel_crtc
->active
)
7131 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
7136 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
7137 u16
*blue
, uint32_t start
, uint32_t size
)
7139 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
7140 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7142 for (i
= start
; i
< end
; i
++) {
7143 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
7144 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
7145 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
7148 intel_crtc_load_lut(crtc
);
7151 /* VESA 640x480x72Hz mode to set on the pipe */
7152 static struct drm_display_mode load_detect_mode
= {
7153 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
7154 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
7157 static struct drm_framebuffer
*
7158 intel_framebuffer_create(struct drm_device
*dev
,
7159 struct drm_mode_fb_cmd2
*mode_cmd
,
7160 struct drm_i915_gem_object
*obj
)
7162 struct intel_framebuffer
*intel_fb
;
7165 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7167 drm_gem_object_unreference_unlocked(&obj
->base
);
7168 return ERR_PTR(-ENOMEM
);
7171 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
7173 drm_gem_object_unreference_unlocked(&obj
->base
);
7175 return ERR_PTR(ret
);
7178 return &intel_fb
->base
;
7182 intel_framebuffer_pitch_for_width(int width
, int bpp
)
7184 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
7185 return ALIGN(pitch
, 64);
7189 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
7191 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
7192 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
7195 static struct drm_framebuffer
*
7196 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
7197 struct drm_display_mode
*mode
,
7200 struct drm_i915_gem_object
*obj
;
7201 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
7203 obj
= i915_gem_alloc_object(dev
,
7204 intel_framebuffer_size_for_mode(mode
, bpp
));
7206 return ERR_PTR(-ENOMEM
);
7208 mode_cmd
.width
= mode
->hdisplay
;
7209 mode_cmd
.height
= mode
->vdisplay
;
7210 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
7212 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
7214 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
7217 static struct drm_framebuffer
*
7218 mode_fits_in_fbdev(struct drm_device
*dev
,
7219 struct drm_display_mode
*mode
)
7221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7222 struct drm_i915_gem_object
*obj
;
7223 struct drm_framebuffer
*fb
;
7225 if (dev_priv
->fbdev
== NULL
)
7228 obj
= dev_priv
->fbdev
->ifb
.obj
;
7232 fb
= &dev_priv
->fbdev
->ifb
.base
;
7233 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
7234 fb
->bits_per_pixel
))
7237 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
7243 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
7244 struct drm_display_mode
*mode
,
7245 struct intel_load_detect_pipe
*old
)
7247 struct intel_crtc
*intel_crtc
;
7248 struct intel_encoder
*intel_encoder
=
7249 intel_attached_encoder(connector
);
7250 struct drm_crtc
*possible_crtc
;
7251 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7252 struct drm_crtc
*crtc
= NULL
;
7253 struct drm_device
*dev
= encoder
->dev
;
7254 struct drm_framebuffer
*fb
;
7257 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7258 connector
->base
.id
, drm_get_connector_name(connector
),
7259 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7262 * Algorithm gets a little messy:
7264 * - if the connector already has an assigned crtc, use it (but make
7265 * sure it's on first)
7267 * - try to find the first unused crtc that can drive this connector,
7268 * and use that if we find one
7271 /* See if we already have a CRTC for this connector */
7272 if (encoder
->crtc
) {
7273 crtc
= encoder
->crtc
;
7275 mutex_lock(&crtc
->mutex
);
7277 old
->dpms_mode
= connector
->dpms
;
7278 old
->load_detect_temp
= false;
7280 /* Make sure the crtc and connector are running */
7281 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
7282 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
7287 /* Find an unused one (if possible) */
7288 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
7290 if (!(encoder
->possible_crtcs
& (1 << i
)))
7292 if (!possible_crtc
->enabled
) {
7293 crtc
= possible_crtc
;
7299 * If we didn't find an unused CRTC, don't use any.
7302 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7306 mutex_lock(&crtc
->mutex
);
7307 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
7308 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
7310 intel_crtc
= to_intel_crtc(crtc
);
7311 old
->dpms_mode
= connector
->dpms
;
7312 old
->load_detect_temp
= true;
7313 old
->release_fb
= NULL
;
7316 mode
= &load_detect_mode
;
7318 /* We need a framebuffer large enough to accommodate all accesses
7319 * that the plane may generate whilst we perform load detection.
7320 * We can not rely on the fbcon either being present (we get called
7321 * during its initialisation to detect all boot displays, or it may
7322 * not even exist) or that it is large enough to satisfy the
7325 fb
= mode_fits_in_fbdev(dev
, mode
);
7327 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7328 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
7329 old
->release_fb
= fb
;
7331 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7333 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7334 mutex_unlock(&crtc
->mutex
);
7338 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
7339 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7340 if (old
->release_fb
)
7341 old
->release_fb
->funcs
->destroy(old
->release_fb
);
7342 mutex_unlock(&crtc
->mutex
);
7346 /* let the connector get through one full cycle before testing */
7347 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
7351 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
7352 struct intel_load_detect_pipe
*old
)
7354 struct intel_encoder
*intel_encoder
=
7355 intel_attached_encoder(connector
);
7356 struct drm_encoder
*encoder
= &intel_encoder
->base
;
7357 struct drm_crtc
*crtc
= encoder
->crtc
;
7359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7360 connector
->base
.id
, drm_get_connector_name(connector
),
7361 encoder
->base
.id
, drm_get_encoder_name(encoder
));
7363 if (old
->load_detect_temp
) {
7364 to_intel_connector(connector
)->new_encoder
= NULL
;
7365 intel_encoder
->new_crtc
= NULL
;
7366 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
7368 if (old
->release_fb
) {
7369 drm_framebuffer_unregister_private(old
->release_fb
);
7370 drm_framebuffer_unreference(old
->release_fb
);
7373 mutex_unlock(&crtc
->mutex
);
7377 /* Switch crtc and encoder back off if necessary */
7378 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
7379 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
7381 mutex_unlock(&crtc
->mutex
);
7384 static int i9xx_pll_refclk(struct drm_device
*dev
,
7385 const struct intel_crtc_config
*pipe_config
)
7387 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7388 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7390 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
7391 return dev_priv
->vbt
.lvds_ssc_freq
* 1000;
7392 else if (HAS_PCH_SPLIT(dev
))
7394 else if (!IS_GEN2(dev
))
7400 /* Returns the clock of the currently programmed mode of the given pipe. */
7401 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
7402 struct intel_crtc_config
*pipe_config
)
7404 struct drm_device
*dev
= crtc
->base
.dev
;
7405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7406 int pipe
= pipe_config
->cpu_transcoder
;
7407 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
7409 intel_clock_t clock
;
7410 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
7412 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
7413 fp
= pipe_config
->dpll_hw_state
.fp0
;
7415 fp
= pipe_config
->dpll_hw_state
.fp1
;
7417 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
7418 if (IS_PINEVIEW(dev
)) {
7419 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
7420 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7422 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
7423 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
7426 if (!IS_GEN2(dev
)) {
7427 if (IS_PINEVIEW(dev
))
7428 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
7429 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
7431 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
7432 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7434 switch (dpll
& DPLL_MODE_MASK
) {
7435 case DPLLB_MODE_DAC_SERIAL
:
7436 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
7439 case DPLLB_MODE_LVDS
:
7440 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
7444 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7445 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
7449 if (IS_PINEVIEW(dev
))
7450 pineview_clock(refclk
, &clock
);
7452 i9xx_clock(refclk
, &clock
);
7454 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
7457 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
7458 DPLL_FPA01_P1_POST_DIV_SHIFT
);
7461 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
7464 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
7465 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
7467 if (dpll
& PLL_P2_DIVIDE_BY_4
)
7473 i9xx_clock(refclk
, &clock
);
7477 * This value includes pixel_multiplier. We will use
7478 * port_clock to compute adjusted_mode.crtc_clock in the
7479 * encoder's get_config() function.
7481 pipe_config
->port_clock
= clock
.dot
;
7484 int intel_dotclock_calculate(int link_freq
,
7485 const struct intel_link_m_n
*m_n
)
7488 * The calculation for the data clock is:
7489 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
7490 * But we want to avoid losing precison if possible, so:
7491 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
7493 * and the link clock is simpler:
7494 * link_clock = (m * link_clock) / n
7500 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
7503 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
7504 struct intel_crtc_config
*pipe_config
)
7506 struct drm_device
*dev
= crtc
->base
.dev
;
7508 /* read out port_clock from the DPLL */
7509 i9xx_crtc_clock_get(crtc
, pipe_config
);
7512 * This value does not include pixel_multiplier.
7513 * We will check that port_clock and adjusted_mode.crtc_clock
7514 * agree once we know their relationship in the encoder's
7515 * get_config() function.
7517 pipe_config
->adjusted_mode
.crtc_clock
=
7518 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
7519 &pipe_config
->fdi_m_n
);
7522 /** Returns the currently programmed mode of the given pipe. */
7523 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
7524 struct drm_crtc
*crtc
)
7526 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7527 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7528 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
7529 struct drm_display_mode
*mode
;
7530 struct intel_crtc_config pipe_config
;
7531 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
7532 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
7533 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
7534 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
7535 enum pipe pipe
= intel_crtc
->pipe
;
7537 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
7542 * Construct a pipe_config sufficient for getting the clock info
7543 * back out of crtc_clock_get.
7545 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7546 * to use a real value here instead.
7548 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
7549 pipe_config
.pixel_multiplier
= 1;
7550 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
7551 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
7552 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
7553 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
7555 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
7556 mode
->hdisplay
= (htot
& 0xffff) + 1;
7557 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
7558 mode
->hsync_start
= (hsync
& 0xffff) + 1;
7559 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
7560 mode
->vdisplay
= (vtot
& 0xffff) + 1;
7561 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
7562 mode
->vsync_start
= (vsync
& 0xffff) + 1;
7563 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
7565 drm_mode_set_name(mode
);
7570 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
7572 struct drm_device
*dev
= crtc
->dev
;
7573 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7574 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7575 int pipe
= intel_crtc
->pipe
;
7576 int dpll_reg
= DPLL(pipe
);
7579 if (HAS_PCH_SPLIT(dev
))
7582 if (!dev_priv
->lvds_downclock_avail
)
7585 dpll
= I915_READ(dpll_reg
);
7586 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
7587 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7589 assert_panel_unlocked(dev_priv
, pipe
);
7591 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
7592 I915_WRITE(dpll_reg
, dpll
);
7593 intel_wait_for_vblank(dev
, pipe
);
7595 dpll
= I915_READ(dpll_reg
);
7596 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
7597 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7601 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
7603 struct drm_device
*dev
= crtc
->dev
;
7604 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7605 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7607 if (HAS_PCH_SPLIT(dev
))
7610 if (!dev_priv
->lvds_downclock_avail
)
7614 * Since this is called by a timer, we should never get here in
7617 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
7618 int pipe
= intel_crtc
->pipe
;
7619 int dpll_reg
= DPLL(pipe
);
7622 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7624 assert_panel_unlocked(dev_priv
, pipe
);
7626 dpll
= I915_READ(dpll_reg
);
7627 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
7628 I915_WRITE(dpll_reg
, dpll
);
7629 intel_wait_for_vblank(dev
, pipe
);
7630 dpll
= I915_READ(dpll_reg
);
7631 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
7632 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7637 void intel_mark_busy(struct drm_device
*dev
)
7639 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7641 hsw_package_c8_gpu_busy(dev_priv
);
7642 i915_update_gfx_val(dev_priv
);
7645 void intel_mark_idle(struct drm_device
*dev
)
7647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7648 struct drm_crtc
*crtc
;
7650 hsw_package_c8_gpu_idle(dev_priv
);
7652 if (!i915_powersave
)
7655 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7659 intel_decrease_pllclock(crtc
);
7663 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
,
7664 struct intel_ring_buffer
*ring
)
7666 struct drm_device
*dev
= obj
->base
.dev
;
7667 struct drm_crtc
*crtc
;
7669 if (!i915_powersave
)
7672 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7676 if (to_intel_framebuffer(crtc
->fb
)->obj
!= obj
)
7679 intel_increase_pllclock(crtc
);
7680 if (ring
&& intel_fbc_enabled(dev
))
7681 ring
->fbc_dirty
= true;
7685 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
7687 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7688 struct drm_device
*dev
= crtc
->dev
;
7689 struct intel_unpin_work
*work
;
7690 unsigned long flags
;
7692 spin_lock_irqsave(&dev
->event_lock
, flags
);
7693 work
= intel_crtc
->unpin_work
;
7694 intel_crtc
->unpin_work
= NULL
;
7695 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7698 cancel_work_sync(&work
->work
);
7702 intel_crtc_cursor_set(crtc
, NULL
, 0, 0, 0);
7704 drm_crtc_cleanup(crtc
);
7709 static void intel_unpin_work_fn(struct work_struct
*__work
)
7711 struct intel_unpin_work
*work
=
7712 container_of(__work
, struct intel_unpin_work
, work
);
7713 struct drm_device
*dev
= work
->crtc
->dev
;
7715 mutex_lock(&dev
->struct_mutex
);
7716 intel_unpin_fb_obj(work
->old_fb_obj
);
7717 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
7718 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7720 intel_update_fbc(dev
);
7721 mutex_unlock(&dev
->struct_mutex
);
7723 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
7724 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
7729 static void do_intel_finish_page_flip(struct drm_device
*dev
,
7730 struct drm_crtc
*crtc
)
7732 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7734 struct intel_unpin_work
*work
;
7735 unsigned long flags
;
7737 /* Ignore early vblank irqs */
7738 if (intel_crtc
== NULL
)
7741 spin_lock_irqsave(&dev
->event_lock
, flags
);
7742 work
= intel_crtc
->unpin_work
;
7744 /* Ensure we don't miss a work->pending update ... */
7747 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
7748 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7752 /* and that the unpin work is consistent wrt ->pending. */
7755 intel_crtc
->unpin_work
= NULL
;
7758 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
7760 drm_vblank_put(dev
, intel_crtc
->pipe
);
7762 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7764 wake_up_all(&dev_priv
->pending_flip_queue
);
7766 queue_work(dev_priv
->wq
, &work
->work
);
7768 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
7771 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
7773 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7774 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
7776 do_intel_finish_page_flip(dev
, crtc
);
7779 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
7781 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7782 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
7784 do_intel_finish_page_flip(dev
, crtc
);
7787 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
7789 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7790 struct intel_crtc
*intel_crtc
=
7791 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
7792 unsigned long flags
;
7794 /* NB: An MMIO update of the plane base pointer will also
7795 * generate a page-flip completion irq, i.e. every modeset
7796 * is also accompanied by a spurious intel_prepare_page_flip().
7798 spin_lock_irqsave(&dev
->event_lock
, flags
);
7799 if (intel_crtc
->unpin_work
)
7800 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
7801 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7804 inline static void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
7806 /* Ensure that the work item is consistent when activating it ... */
7808 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
7809 /* and that it is marked active as soon as the irq could fire. */
7813 static int intel_gen2_queue_flip(struct drm_device
*dev
,
7814 struct drm_crtc
*crtc
,
7815 struct drm_framebuffer
*fb
,
7816 struct drm_i915_gem_object
*obj
,
7819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7822 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7825 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7829 ret
= intel_ring_begin(ring
, 6);
7833 /* Can't queue multiple flips, so wait for the previous
7834 * one to finish before executing the next.
7836 if (intel_crtc
->plane
)
7837 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7839 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7840 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7841 intel_ring_emit(ring
, MI_NOOP
);
7842 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7843 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7844 intel_ring_emit(ring
, fb
->pitches
[0]);
7845 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7846 intel_ring_emit(ring
, 0); /* aux display base address, unused */
7848 intel_mark_page_flip_active(intel_crtc
);
7849 __intel_ring_advance(ring
);
7853 intel_unpin_fb_obj(obj
);
7858 static int intel_gen3_queue_flip(struct drm_device
*dev
,
7859 struct drm_crtc
*crtc
,
7860 struct drm_framebuffer
*fb
,
7861 struct drm_i915_gem_object
*obj
,
7864 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7865 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7867 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7870 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7874 ret
= intel_ring_begin(ring
, 6);
7878 if (intel_crtc
->plane
)
7879 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
7881 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
7882 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
7883 intel_ring_emit(ring
, MI_NOOP
);
7884 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
7885 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7886 intel_ring_emit(ring
, fb
->pitches
[0]);
7887 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7888 intel_ring_emit(ring
, MI_NOOP
);
7890 intel_mark_page_flip_active(intel_crtc
);
7891 __intel_ring_advance(ring
);
7895 intel_unpin_fb_obj(obj
);
7900 static int intel_gen4_queue_flip(struct drm_device
*dev
,
7901 struct drm_crtc
*crtc
,
7902 struct drm_framebuffer
*fb
,
7903 struct drm_i915_gem_object
*obj
,
7906 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7907 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7908 uint32_t pf
, pipesrc
;
7909 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7912 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7916 ret
= intel_ring_begin(ring
, 4);
7920 /* i965+ uses the linear or tiled offsets from the
7921 * Display Registers (which do not change across a page-flip)
7922 * so we need only reprogram the base address.
7924 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7925 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7926 intel_ring_emit(ring
, fb
->pitches
[0]);
7927 intel_ring_emit(ring
,
7928 (i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
) |
7931 /* XXX Enabling the panel-fitter across page-flip is so far
7932 * untested on non-native modes, so ignore it for now.
7933 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7936 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7937 intel_ring_emit(ring
, pf
| pipesrc
);
7939 intel_mark_page_flip_active(intel_crtc
);
7940 __intel_ring_advance(ring
);
7944 intel_unpin_fb_obj(obj
);
7949 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7950 struct drm_crtc
*crtc
,
7951 struct drm_framebuffer
*fb
,
7952 struct drm_i915_gem_object
*obj
,
7955 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7956 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7957 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7958 uint32_t pf
, pipesrc
;
7961 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7965 ret
= intel_ring_begin(ring
, 4);
7969 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7970 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7971 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7972 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
7974 /* Contrary to the suggestions in the documentation,
7975 * "Enable Panel Fitter" does not seem to be required when page
7976 * flipping with a non-native mode, and worse causes a normal
7978 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7981 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7982 intel_ring_emit(ring
, pf
| pipesrc
);
7984 intel_mark_page_flip_active(intel_crtc
);
7985 __intel_ring_advance(ring
);
7989 intel_unpin_fb_obj(obj
);
7994 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7995 struct drm_crtc
*crtc
,
7996 struct drm_framebuffer
*fb
,
7997 struct drm_i915_gem_object
*obj
,
8000 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8001 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8002 struct intel_ring_buffer
*ring
;
8003 uint32_t plane_bit
= 0;
8007 if (IS_VALLEYVIEW(dev
) || ring
== NULL
|| ring
->id
!= RCS
)
8008 ring
= &dev_priv
->ring
[BCS
];
8010 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
8014 switch(intel_crtc
->plane
) {
8016 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
8019 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
8022 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
8025 WARN_ONCE(1, "unknown plane in flip command\n");
8031 if (ring
->id
== RCS
)
8034 ret
= intel_ring_begin(ring
, len
);
8038 /* Unmask the flip-done completion message. Note that the bspec says that
8039 * we should do this for both the BCS and RCS, and that we must not unmask
8040 * more than one flip event at any time (or ensure that one flip message
8041 * can be sent by waiting for flip-done prior to queueing new flips).
8042 * Experimentation says that BCS works despite DERRMR masking all
8043 * flip-done completion events and that unmasking all planes at once
8044 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8045 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8047 if (ring
->id
== RCS
) {
8048 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
8049 intel_ring_emit(ring
, DERRMR
);
8050 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
8051 DERRMR_PIPEB_PRI_FLIP_DONE
|
8052 DERRMR_PIPEC_PRI_FLIP_DONE
));
8053 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1));
8054 intel_ring_emit(ring
, DERRMR
);
8055 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
8058 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
8059 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
8060 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
8061 intel_ring_emit(ring
, (MI_NOOP
));
8063 intel_mark_page_flip_active(intel_crtc
);
8064 __intel_ring_advance(ring
);
8068 intel_unpin_fb_obj(obj
);
8073 static int intel_default_queue_flip(struct drm_device
*dev
,
8074 struct drm_crtc
*crtc
,
8075 struct drm_framebuffer
*fb
,
8076 struct drm_i915_gem_object
*obj
,
8082 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
8083 struct drm_framebuffer
*fb
,
8084 struct drm_pending_vblank_event
*event
,
8085 uint32_t page_flip_flags
)
8087 struct drm_device
*dev
= crtc
->dev
;
8088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8089 struct drm_framebuffer
*old_fb
= crtc
->fb
;
8090 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(fb
)->obj
;
8091 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8092 struct intel_unpin_work
*work
;
8093 unsigned long flags
;
8096 /* Can't change pixel format via MI display flips. */
8097 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
8101 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8102 * Note that pitch changes could also affect these register.
8104 if (INTEL_INFO(dev
)->gen
> 3 &&
8105 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
8106 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
8109 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
8113 work
->event
= event
;
8115 work
->old_fb_obj
= to_intel_framebuffer(old_fb
)->obj
;
8116 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
8118 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
8122 /* We borrow the event spin lock for protecting unpin_work */
8123 spin_lock_irqsave(&dev
->event_lock
, flags
);
8124 if (intel_crtc
->unpin_work
) {
8125 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8127 drm_vblank_put(dev
, intel_crtc
->pipe
);
8129 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8132 intel_crtc
->unpin_work
= work
;
8133 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8135 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
8136 flush_workqueue(dev_priv
->wq
);
8138 ret
= i915_mutex_lock_interruptible(dev
);
8142 /* Reference the objects for the scheduled work. */
8143 drm_gem_object_reference(&work
->old_fb_obj
->base
);
8144 drm_gem_object_reference(&obj
->base
);
8148 work
->pending_flip_obj
= obj
;
8150 work
->enable_stall_check
= true;
8152 atomic_inc(&intel_crtc
->unpin_work_count
);
8153 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
8155 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, page_flip_flags
);
8157 goto cleanup_pending
;
8159 intel_disable_fbc(dev
);
8160 intel_mark_fb_busy(obj
, NULL
);
8161 mutex_unlock(&dev
->struct_mutex
);
8163 trace_i915_flip_request(intel_crtc
->plane
, obj
);
8168 atomic_dec(&intel_crtc
->unpin_work_count
);
8170 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
8171 drm_gem_object_unreference(&obj
->base
);
8172 mutex_unlock(&dev
->struct_mutex
);
8175 spin_lock_irqsave(&dev
->event_lock
, flags
);
8176 intel_crtc
->unpin_work
= NULL
;
8177 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
8179 drm_vblank_put(dev
, intel_crtc
->pipe
);
8186 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
8187 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
8188 .load_lut
= intel_crtc_load_lut
,
8191 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
8192 struct drm_crtc
*crtc
)
8194 struct drm_device
*dev
;
8195 struct drm_crtc
*tmp
;
8198 WARN(!crtc
, "checking null crtc?\n");
8202 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
8208 if (encoder
->possible_crtcs
& crtc_mask
)
8214 * intel_modeset_update_staged_output_state
8216 * Updates the staged output configuration state, e.g. after we've read out the
8219 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
8221 struct intel_encoder
*encoder
;
8222 struct intel_connector
*connector
;
8224 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8226 connector
->new_encoder
=
8227 to_intel_encoder(connector
->base
.encoder
);
8230 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8233 to_intel_crtc(encoder
->base
.crtc
);
8238 * intel_modeset_commit_output_state
8240 * This function copies the stage display pipe configuration to the real one.
8242 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
8244 struct intel_encoder
*encoder
;
8245 struct intel_connector
*connector
;
8247 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8249 connector
->base
.encoder
= &connector
->new_encoder
->base
;
8252 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8254 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
8259 connected_sink_compute_bpp(struct intel_connector
* connector
,
8260 struct intel_crtc_config
*pipe_config
)
8262 int bpp
= pipe_config
->pipe_bpp
;
8264 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8265 connector
->base
.base
.id
,
8266 drm_get_connector_name(&connector
->base
));
8268 /* Don't use an invalid EDID bpc value */
8269 if (connector
->base
.display_info
.bpc
&&
8270 connector
->base
.display_info
.bpc
* 3 < bpp
) {
8271 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8272 bpp
, connector
->base
.display_info
.bpc
*3);
8273 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
8276 /* Clamp bpp to 8 on screens without EDID 1.4 */
8277 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
8278 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8280 pipe_config
->pipe_bpp
= 24;
8285 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
8286 struct drm_framebuffer
*fb
,
8287 struct intel_crtc_config
*pipe_config
)
8289 struct drm_device
*dev
= crtc
->base
.dev
;
8290 struct intel_connector
*connector
;
8293 switch (fb
->pixel_format
) {
8295 bpp
= 8*3; /* since we go through a colormap */
8297 case DRM_FORMAT_XRGB1555
:
8298 case DRM_FORMAT_ARGB1555
:
8299 /* checked in intel_framebuffer_init already */
8300 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
8302 case DRM_FORMAT_RGB565
:
8303 bpp
= 6*3; /* min is 18bpp */
8305 case DRM_FORMAT_XBGR8888
:
8306 case DRM_FORMAT_ABGR8888
:
8307 /* checked in intel_framebuffer_init already */
8308 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8310 case DRM_FORMAT_XRGB8888
:
8311 case DRM_FORMAT_ARGB8888
:
8314 case DRM_FORMAT_XRGB2101010
:
8315 case DRM_FORMAT_ARGB2101010
:
8316 case DRM_FORMAT_XBGR2101010
:
8317 case DRM_FORMAT_ABGR2101010
:
8318 /* checked in intel_framebuffer_init already */
8319 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
8323 /* TODO: gen4+ supports 16 bpc floating point, too. */
8325 DRM_DEBUG_KMS("unsupported depth\n");
8329 pipe_config
->pipe_bpp
= bpp
;
8331 /* Clamp display bpp to EDID value */
8332 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8334 if (!connector
->new_encoder
||
8335 connector
->new_encoder
->new_crtc
!= crtc
)
8338 connected_sink_compute_bpp(connector
, pipe_config
);
8344 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
8346 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8347 "type: 0x%x flags: 0x%x\n",
8349 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
8350 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
8351 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
8352 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
8355 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
8356 struct intel_crtc_config
*pipe_config
,
8357 const char *context
)
8359 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
8360 context
, pipe_name(crtc
->pipe
));
8362 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
8363 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8364 pipe_config
->pipe_bpp
, pipe_config
->dither
);
8365 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8366 pipe_config
->has_pch_encoder
,
8367 pipe_config
->fdi_lanes
,
8368 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
8369 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
8370 pipe_config
->fdi_m_n
.tu
);
8371 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8372 pipe_config
->has_dp_encoder
,
8373 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
8374 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
8375 pipe_config
->dp_m_n
.tu
);
8376 DRM_DEBUG_KMS("requested mode:\n");
8377 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
8378 DRM_DEBUG_KMS("adjusted mode:\n");
8379 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
8380 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
8381 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
8382 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8383 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
8384 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8385 pipe_config
->gmch_pfit
.control
,
8386 pipe_config
->gmch_pfit
.pgm_ratios
,
8387 pipe_config
->gmch_pfit
.lvds_border_bits
);
8388 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8389 pipe_config
->pch_pfit
.pos
,
8390 pipe_config
->pch_pfit
.size
,
8391 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
8392 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
8393 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
8396 static bool check_encoder_cloning(struct drm_crtc
*crtc
)
8398 int num_encoders
= 0;
8399 bool uncloneable_encoders
= false;
8400 struct intel_encoder
*encoder
;
8402 list_for_each_entry(encoder
, &crtc
->dev
->mode_config
.encoder_list
,
8404 if (&encoder
->new_crtc
->base
!= crtc
)
8408 if (!encoder
->cloneable
)
8409 uncloneable_encoders
= true;
8412 return !(num_encoders
> 1 && uncloneable_encoders
);
8415 static struct intel_crtc_config
*
8416 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
8417 struct drm_framebuffer
*fb
,
8418 struct drm_display_mode
*mode
)
8420 struct drm_device
*dev
= crtc
->dev
;
8421 struct intel_encoder
*encoder
;
8422 struct intel_crtc_config
*pipe_config
;
8423 int plane_bpp
, ret
= -EINVAL
;
8426 if (!check_encoder_cloning(crtc
)) {
8427 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8428 return ERR_PTR(-EINVAL
);
8431 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
8433 return ERR_PTR(-ENOMEM
);
8435 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
8436 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
8438 pipe_config
->cpu_transcoder
=
8439 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
8440 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8443 * Sanitize sync polarity flags based on requested ones. If neither
8444 * positive or negative polarity is requested, treat this as meaning
8445 * negative polarity.
8447 if (!(pipe_config
->adjusted_mode
.flags
&
8448 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
8449 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
8451 if (!(pipe_config
->adjusted_mode
.flags
&
8452 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
8453 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
8455 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8456 * plane pixel format and any sink constraints into account. Returns the
8457 * source plane bpp so that dithering can be selected on mismatches
8458 * after encoders and crtc also have had their say. */
8459 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
8465 /* Ensure the port clock defaults are reset when retrying. */
8466 pipe_config
->port_clock
= 0;
8467 pipe_config
->pixel_multiplier
= 1;
8469 /* Fill in default crtc timings, allow encoders to overwrite them. */
8470 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
8472 /* set_crtcinfo() may have adjusted hdisplay/vdisplay */
8473 pipe_config
->pipe_src_w
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
8474 pipe_config
->pipe_src_h
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
8476 /* Pass our mode to the connectors and the CRTC to give them a chance to
8477 * adjust it according to limitations or connector properties, and also
8478 * a chance to reject the mode entirely.
8480 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8483 if (&encoder
->new_crtc
->base
!= crtc
)
8486 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
8487 DRM_DEBUG_KMS("Encoder config failure\n");
8492 /* Set default port clock if not overwritten by the encoder. Needs to be
8493 * done afterwards in case the encoder adjusts the mode. */
8494 if (!pipe_config
->port_clock
)
8495 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
8496 * pipe_config
->pixel_multiplier
;
8498 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
8500 DRM_DEBUG_KMS("CRTC fixup failed\n");
8505 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
8510 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8515 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
8516 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8517 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
8522 return ERR_PTR(ret
);
8525 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
8526 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8528 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
8529 unsigned *prepare_pipes
, unsigned *disable_pipes
)
8531 struct intel_crtc
*intel_crtc
;
8532 struct drm_device
*dev
= crtc
->dev
;
8533 struct intel_encoder
*encoder
;
8534 struct intel_connector
*connector
;
8535 struct drm_crtc
*tmp_crtc
;
8537 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
8539 /* Check which crtcs have changed outputs connected to them, these need
8540 * to be part of the prepare_pipes mask. We don't (yet) support global
8541 * modeset across multiple crtcs, so modeset_pipes will only have one
8542 * bit set at most. */
8543 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8545 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
8548 if (connector
->base
.encoder
) {
8549 tmp_crtc
= connector
->base
.encoder
->crtc
;
8551 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8554 if (connector
->new_encoder
)
8556 1 << connector
->new_encoder
->new_crtc
->pipe
;
8559 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8561 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
8564 if (encoder
->base
.crtc
) {
8565 tmp_crtc
= encoder
->base
.crtc
;
8567 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
8570 if (encoder
->new_crtc
)
8571 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
8574 /* Check for any pipes that will be fully disabled ... */
8575 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8579 /* Don't try to disable disabled crtcs. */
8580 if (!intel_crtc
->base
.enabled
)
8583 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8585 if (encoder
->new_crtc
== intel_crtc
)
8590 *disable_pipes
|= 1 << intel_crtc
->pipe
;
8594 /* set_mode is also used to update properties on life display pipes. */
8595 intel_crtc
= to_intel_crtc(crtc
);
8597 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
8600 * For simplicity do a full modeset on any pipe where the output routing
8601 * changed. We could be more clever, but that would require us to be
8602 * more careful with calling the relevant encoder->mode_set functions.
8605 *modeset_pipes
= *prepare_pipes
;
8607 /* ... and mask these out. */
8608 *modeset_pipes
&= ~(*disable_pipes
);
8609 *prepare_pipes
&= ~(*disable_pipes
);
8612 * HACK: We don't (yet) fully support global modesets. intel_set_config
8613 * obies this rule, but the modeset restore mode of
8614 * intel_modeset_setup_hw_state does not.
8616 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
8617 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
8619 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8620 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
8623 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
8625 struct drm_encoder
*encoder
;
8626 struct drm_device
*dev
= crtc
->dev
;
8628 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
8629 if (encoder
->crtc
== crtc
)
8636 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
8638 struct intel_encoder
*intel_encoder
;
8639 struct intel_crtc
*intel_crtc
;
8640 struct drm_connector
*connector
;
8642 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
8644 if (!intel_encoder
->base
.crtc
)
8647 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
8649 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
8650 intel_encoder
->connectors_active
= false;
8653 intel_modeset_commit_output_state(dev
);
8655 /* Update computed state. */
8656 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
8658 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
8661 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
8662 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
8665 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
8667 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
8668 struct drm_property
*dpms_property
=
8669 dev
->mode_config
.dpms_property
;
8671 connector
->dpms
= DRM_MODE_DPMS_ON
;
8672 drm_object_property_set_value(&connector
->base
,
8676 intel_encoder
= to_intel_encoder(connector
->encoder
);
8677 intel_encoder
->connectors_active
= true;
8683 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
8687 if (clock1
== clock2
)
8690 if (!clock1
|| !clock2
)
8693 diff
= abs(clock1
- clock2
);
8695 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
8701 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8702 list_for_each_entry((intel_crtc), \
8703 &(dev)->mode_config.crtc_list, \
8705 if (mask & (1 <<(intel_crtc)->pipe))
8708 intel_pipe_config_compare(struct drm_device
*dev
,
8709 struct intel_crtc_config
*current_config
,
8710 struct intel_crtc_config
*pipe_config
)
8712 #define PIPE_CONF_CHECK_X(name) \
8713 if (current_config->name != pipe_config->name) { \
8714 DRM_ERROR("mismatch in " #name " " \
8715 "(expected 0x%08x, found 0x%08x)\n", \
8716 current_config->name, \
8717 pipe_config->name); \
8721 #define PIPE_CONF_CHECK_I(name) \
8722 if (current_config->name != pipe_config->name) { \
8723 DRM_ERROR("mismatch in " #name " " \
8724 "(expected %i, found %i)\n", \
8725 current_config->name, \
8726 pipe_config->name); \
8730 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8731 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8732 DRM_ERROR("mismatch in " #name "(" #mask ") " \
8733 "(expected %i, found %i)\n", \
8734 current_config->name & (mask), \
8735 pipe_config->name & (mask)); \
8739 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8740 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8741 DRM_ERROR("mismatch in " #name " " \
8742 "(expected %i, found %i)\n", \
8743 current_config->name, \
8744 pipe_config->name); \
8748 #define PIPE_CONF_QUIRK(quirk) \
8749 ((current_config->quirks | pipe_config->quirks) & (quirk))
8751 PIPE_CONF_CHECK_I(cpu_transcoder
);
8753 PIPE_CONF_CHECK_I(has_pch_encoder
);
8754 PIPE_CONF_CHECK_I(fdi_lanes
);
8755 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
8756 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
8757 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
8758 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
8759 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
8761 PIPE_CONF_CHECK_I(has_dp_encoder
);
8762 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
8763 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
8764 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
8765 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
8766 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
8768 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
8769 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
8770 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
8771 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
8772 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
8773 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
8775 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
8776 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
8777 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
8778 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
8779 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
8780 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
8782 PIPE_CONF_CHECK_I(pixel_multiplier
);
8784 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8785 DRM_MODE_FLAG_INTERLACE
);
8787 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
8788 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8789 DRM_MODE_FLAG_PHSYNC
);
8790 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8791 DRM_MODE_FLAG_NHSYNC
);
8792 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8793 DRM_MODE_FLAG_PVSYNC
);
8794 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
8795 DRM_MODE_FLAG_NVSYNC
);
8798 PIPE_CONF_CHECK_I(pipe_src_w
);
8799 PIPE_CONF_CHECK_I(pipe_src_h
);
8801 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
8802 /* pfit ratios are autocomputed by the hw on gen4+ */
8803 if (INTEL_INFO(dev
)->gen
< 4)
8804 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
8805 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
8806 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
8807 if (current_config
->pch_pfit
.enabled
) {
8808 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
8809 PIPE_CONF_CHECK_I(pch_pfit
.size
);
8812 PIPE_CONF_CHECK_I(ips_enabled
);
8814 PIPE_CONF_CHECK_I(double_wide
);
8816 PIPE_CONF_CHECK_I(shared_dpll
);
8817 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
8818 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
8819 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
8820 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
8822 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
8823 PIPE_CONF_CHECK_I(pipe_bpp
);
8825 if (!IS_HASWELL(dev
)) {
8826 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
8827 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
8830 #undef PIPE_CONF_CHECK_X
8831 #undef PIPE_CONF_CHECK_I
8832 #undef PIPE_CONF_CHECK_FLAGS
8833 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
8834 #undef PIPE_CONF_QUIRK
8840 check_connector_state(struct drm_device
*dev
)
8842 struct intel_connector
*connector
;
8844 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8846 /* This also checks the encoder/connector hw state with the
8847 * ->get_hw_state callbacks. */
8848 intel_connector_check_state(connector
);
8850 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
8851 "connector's staged encoder doesn't match current encoder\n");
8856 check_encoder_state(struct drm_device
*dev
)
8858 struct intel_encoder
*encoder
;
8859 struct intel_connector
*connector
;
8861 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8863 bool enabled
= false;
8864 bool active
= false;
8865 enum pipe pipe
, tracked_pipe
;
8867 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8868 encoder
->base
.base
.id
,
8869 drm_get_encoder_name(&encoder
->base
));
8871 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
8872 "encoder's stage crtc doesn't match current crtc\n");
8873 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
8874 "encoder's active_connectors set, but no crtc\n");
8876 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8878 if (connector
->base
.encoder
!= &encoder
->base
)
8881 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
8884 WARN(!!encoder
->base
.crtc
!= enabled
,
8885 "encoder's enabled state mismatch "
8886 "(expected %i, found %i)\n",
8887 !!encoder
->base
.crtc
, enabled
);
8888 WARN(active
&& !encoder
->base
.crtc
,
8889 "active encoder with no crtc\n");
8891 WARN(encoder
->connectors_active
!= active
,
8892 "encoder's computed active state doesn't match tracked active state "
8893 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
8895 active
= encoder
->get_hw_state(encoder
, &pipe
);
8896 WARN(active
!= encoder
->connectors_active
,
8897 "encoder's hw state doesn't match sw tracking "
8898 "(expected %i, found %i)\n",
8899 encoder
->connectors_active
, active
);
8901 if (!encoder
->base
.crtc
)
8904 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
8905 WARN(active
&& pipe
!= tracked_pipe
,
8906 "active encoder's pipe doesn't match"
8907 "(expected %i, found %i)\n",
8908 tracked_pipe
, pipe
);
8914 check_crtc_state(struct drm_device
*dev
)
8916 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8917 struct intel_crtc
*crtc
;
8918 struct intel_encoder
*encoder
;
8919 struct intel_crtc_config pipe_config
;
8921 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
8923 bool enabled
= false;
8924 bool active
= false;
8926 memset(&pipe_config
, 0, sizeof(pipe_config
));
8928 DRM_DEBUG_KMS("[CRTC:%d]\n",
8929 crtc
->base
.base
.id
);
8931 WARN(crtc
->active
&& !crtc
->base
.enabled
,
8932 "active crtc, but not enabled in sw tracking\n");
8934 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8936 if (encoder
->base
.crtc
!= &crtc
->base
)
8939 if (encoder
->connectors_active
)
8943 WARN(active
!= crtc
->active
,
8944 "crtc's computed active state doesn't match tracked active state "
8945 "(expected %i, found %i)\n", active
, crtc
->active
);
8946 WARN(enabled
!= crtc
->base
.enabled
,
8947 "crtc's computed enabled state doesn't match tracked enabled state "
8948 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
8950 active
= dev_priv
->display
.get_pipe_config(crtc
,
8953 /* hw state is inconsistent with the pipe A quirk */
8954 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
8955 active
= crtc
->active
;
8957 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8960 if (encoder
->base
.crtc
!= &crtc
->base
)
8962 if (encoder
->get_config
&&
8963 encoder
->get_hw_state(encoder
, &pipe
))
8964 encoder
->get_config(encoder
, &pipe_config
);
8967 WARN(crtc
->active
!= active
,
8968 "crtc active state doesn't match with hw state "
8969 "(expected %i, found %i)\n", crtc
->active
, active
);
8972 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
8973 WARN(1, "pipe state doesn't match!\n");
8974 intel_dump_pipe_config(crtc
, &pipe_config
,
8976 intel_dump_pipe_config(crtc
, &crtc
->config
,
8983 check_shared_dpll_state(struct drm_device
*dev
)
8985 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8986 struct intel_crtc
*crtc
;
8987 struct intel_dpll_hw_state dpll_hw_state
;
8990 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
8991 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
8992 int enabled_crtcs
= 0, active_crtcs
= 0;
8995 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
8997 DRM_DEBUG_KMS("%s\n", pll
->name
);
8999 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
9001 WARN(pll
->active
> pll
->refcount
,
9002 "more active pll users than references: %i vs %i\n",
9003 pll
->active
, pll
->refcount
);
9004 WARN(pll
->active
&& !pll
->on
,
9005 "pll in active use but not on in sw tracking\n");
9006 WARN(pll
->on
&& !pll
->active
,
9007 "pll in on but not on in use in sw tracking\n");
9008 WARN(pll
->on
!= active
,
9009 "pll on state mismatch (expected %i, found %i)\n",
9012 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
9014 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9016 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
9019 WARN(pll
->active
!= active_crtcs
,
9020 "pll active crtcs mismatch (expected %i, found %i)\n",
9021 pll
->active
, active_crtcs
);
9022 WARN(pll
->refcount
!= enabled_crtcs
,
9023 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9024 pll
->refcount
, enabled_crtcs
);
9026 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
9027 sizeof(dpll_hw_state
)),
9028 "pll hw state mismatch\n");
9033 intel_modeset_check_state(struct drm_device
*dev
)
9035 check_connector_state(dev
);
9036 check_encoder_state(dev
);
9037 check_crtc_state(dev
);
9038 check_shared_dpll_state(dev
);
9041 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
9045 * FDI already provided one idea for the dotclock.
9046 * Yell if the encoder disagrees.
9048 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
9049 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9050 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
9053 static int __intel_set_mode(struct drm_crtc
*crtc
,
9054 struct drm_display_mode
*mode
,
9055 int x
, int y
, struct drm_framebuffer
*fb
)
9057 struct drm_device
*dev
= crtc
->dev
;
9058 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9059 struct drm_display_mode
*saved_mode
, *saved_hwmode
;
9060 struct intel_crtc_config
*pipe_config
= NULL
;
9061 struct intel_crtc
*intel_crtc
;
9062 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
9065 saved_mode
= kcalloc(2, sizeof(*saved_mode
), GFP_KERNEL
);
9068 saved_hwmode
= saved_mode
+ 1;
9070 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
9071 &prepare_pipes
, &disable_pipes
);
9073 *saved_hwmode
= crtc
->hwmode
;
9074 *saved_mode
= crtc
->mode
;
9076 /* Hack: Because we don't (yet) support global modeset on multiple
9077 * crtcs, we don't keep track of the new mode for more than one crtc.
9078 * Hence simply check whether any bit is set in modeset_pipes in all the
9079 * pieces of code that are not yet converted to deal with mutliple crtcs
9080 * changing their mode at the same time. */
9081 if (modeset_pipes
) {
9082 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
9083 if (IS_ERR(pipe_config
)) {
9084 ret
= PTR_ERR(pipe_config
);
9089 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
9093 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
9094 intel_crtc_disable(&intel_crtc
->base
);
9096 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
9097 if (intel_crtc
->base
.enabled
)
9098 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
9101 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9102 * to set it here already despite that we pass it down the callchain.
9104 if (modeset_pipes
) {
9106 /* mode_set/enable/disable functions rely on a correct pipe
9108 to_intel_crtc(crtc
)->config
= *pipe_config
;
9111 /* Only after disabling all output pipelines that will be changed can we
9112 * update the the output configuration. */
9113 intel_modeset_update_state(dev
, prepare_pipes
);
9115 if (dev_priv
->display
.modeset_global_resources
)
9116 dev_priv
->display
.modeset_global_resources(dev
);
9118 /* Set up the DPLL and any encoders state that needs to adjust or depend
9121 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
9122 ret
= intel_crtc_mode_set(&intel_crtc
->base
,
9128 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9129 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
9130 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
9132 if (modeset_pipes
) {
9133 /* Store real post-adjustment hardware mode. */
9134 crtc
->hwmode
= pipe_config
->adjusted_mode
;
9136 /* Calculate and store various constants which
9137 * are later needed by vblank and swap-completion
9138 * timestamping. They are derived from true hwmode.
9140 drm_calc_timestamping_constants(crtc
);
9143 /* FIXME: add subpixel order */
9145 if (ret
&& crtc
->enabled
) {
9146 crtc
->hwmode
= *saved_hwmode
;
9147 crtc
->mode
= *saved_mode
;
9156 static int intel_set_mode(struct drm_crtc
*crtc
,
9157 struct drm_display_mode
*mode
,
9158 int x
, int y
, struct drm_framebuffer
*fb
)
9162 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
9165 intel_modeset_check_state(crtc
->dev
);
9170 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
9172 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->fb
);
9175 #undef for_each_intel_crtc_masked
9177 static void intel_set_config_free(struct intel_set_config
*config
)
9182 kfree(config
->save_connector_encoders
);
9183 kfree(config
->save_encoder_crtcs
);
9187 static int intel_set_config_save_state(struct drm_device
*dev
,
9188 struct intel_set_config
*config
)
9190 struct drm_encoder
*encoder
;
9191 struct drm_connector
*connector
;
9194 config
->save_encoder_crtcs
=
9195 kcalloc(dev
->mode_config
.num_encoder
,
9196 sizeof(struct drm_crtc
*), GFP_KERNEL
);
9197 if (!config
->save_encoder_crtcs
)
9200 config
->save_connector_encoders
=
9201 kcalloc(dev
->mode_config
.num_connector
,
9202 sizeof(struct drm_encoder
*), GFP_KERNEL
);
9203 if (!config
->save_connector_encoders
)
9206 /* Copy data. Note that driver private data is not affected.
9207 * Should anything bad happen only the expected state is
9208 * restored, not the drivers personal bookkeeping.
9211 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
9212 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
9216 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
9217 config
->save_connector_encoders
[count
++] = connector
->encoder
;
9223 static void intel_set_config_restore_state(struct drm_device
*dev
,
9224 struct intel_set_config
*config
)
9226 struct intel_encoder
*encoder
;
9227 struct intel_connector
*connector
;
9231 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9233 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
9237 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
9238 connector
->new_encoder
=
9239 to_intel_encoder(config
->save_connector_encoders
[count
++]);
9244 is_crtc_connector_off(struct drm_mode_set
*set
)
9248 if (set
->num_connectors
== 0)
9251 if (WARN_ON(set
->connectors
== NULL
))
9254 for (i
= 0; i
< set
->num_connectors
; i
++)
9255 if (set
->connectors
[i
]->encoder
&&
9256 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
9257 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
9264 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
9265 struct intel_set_config
*config
)
9268 /* We should be able to check here if the fb has the same properties
9269 * and then just flip_or_move it */
9270 if (is_crtc_connector_off(set
)) {
9271 config
->mode_changed
= true;
9272 } else if (set
->crtc
->fb
!= set
->fb
) {
9273 /* If we have no fb then treat it as a full mode set */
9274 if (set
->crtc
->fb
== NULL
) {
9275 struct intel_crtc
*intel_crtc
=
9276 to_intel_crtc(set
->crtc
);
9278 if (intel_crtc
->active
&& i915_fastboot
) {
9279 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9280 config
->fb_changed
= true;
9282 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9283 config
->mode_changed
= true;
9285 } else if (set
->fb
== NULL
) {
9286 config
->mode_changed
= true;
9287 } else if (set
->fb
->pixel_format
!=
9288 set
->crtc
->fb
->pixel_format
) {
9289 config
->mode_changed
= true;
9291 config
->fb_changed
= true;
9295 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
9296 config
->fb_changed
= true;
9298 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
9299 DRM_DEBUG_KMS("modes are different, full mode set\n");
9300 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
9301 drm_mode_debug_printmodeline(set
->mode
);
9302 config
->mode_changed
= true;
9305 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9306 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
9310 intel_modeset_stage_output_state(struct drm_device
*dev
,
9311 struct drm_mode_set
*set
,
9312 struct intel_set_config
*config
)
9314 struct drm_crtc
*new_crtc
;
9315 struct intel_connector
*connector
;
9316 struct intel_encoder
*encoder
;
9319 /* The upper layers ensure that we either disable a crtc or have a list
9320 * of connectors. For paranoia, double-check this. */
9321 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
9322 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
9324 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9326 /* Otherwise traverse passed in connector list and get encoders
9328 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9329 if (set
->connectors
[ro
] == &connector
->base
) {
9330 connector
->new_encoder
= connector
->encoder
;
9335 /* If we disable the crtc, disable all its connectors. Also, if
9336 * the connector is on the changing crtc but not on the new
9337 * connector list, disable it. */
9338 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
9339 connector
->base
.encoder
&&
9340 connector
->base
.encoder
->crtc
== set
->crtc
) {
9341 connector
->new_encoder
= NULL
;
9343 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9344 connector
->base
.base
.id
,
9345 drm_get_connector_name(&connector
->base
));
9349 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
9350 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9351 config
->mode_changed
= true;
9354 /* connector->new_encoder is now updated for all connectors. */
9356 /* Update crtc of enabled connectors. */
9357 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9359 if (!connector
->new_encoder
)
9362 new_crtc
= connector
->new_encoder
->base
.crtc
;
9364 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
9365 if (set
->connectors
[ro
] == &connector
->base
)
9366 new_crtc
= set
->crtc
;
9369 /* Make sure the new CRTC will work with the encoder */
9370 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
9374 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
9376 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9377 connector
->base
.base
.id
,
9378 drm_get_connector_name(&connector
->base
),
9382 /* Check for any encoders that needs to be disabled. */
9383 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
9385 list_for_each_entry(connector
,
9386 &dev
->mode_config
.connector_list
,
9388 if (connector
->new_encoder
== encoder
) {
9389 WARN_ON(!connector
->new_encoder
->new_crtc
);
9394 encoder
->new_crtc
= NULL
;
9396 /* Only now check for crtc changes so we don't miss encoders
9397 * that will be disabled. */
9398 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
9399 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9400 config
->mode_changed
= true;
9403 /* Now we've also updated encoder->new_crtc for all encoders. */
9408 static int intel_crtc_set_config(struct drm_mode_set
*set
)
9410 struct drm_device
*dev
;
9411 struct drm_mode_set save_set
;
9412 struct intel_set_config
*config
;
9417 BUG_ON(!set
->crtc
->helper_private
);
9419 /* Enforce sane interface api - has been abused by the fb helper. */
9420 BUG_ON(!set
->mode
&& set
->fb
);
9421 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
9424 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9425 set
->crtc
->base
.id
, set
->fb
->base
.id
,
9426 (int)set
->num_connectors
, set
->x
, set
->y
);
9428 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
9431 dev
= set
->crtc
->dev
;
9434 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
9438 ret
= intel_set_config_save_state(dev
, config
);
9442 save_set
.crtc
= set
->crtc
;
9443 save_set
.mode
= &set
->crtc
->mode
;
9444 save_set
.x
= set
->crtc
->x
;
9445 save_set
.y
= set
->crtc
->y
;
9446 save_set
.fb
= set
->crtc
->fb
;
9448 /* Compute whether we need a full modeset, only an fb base update or no
9449 * change at all. In the future we might also check whether only the
9450 * mode changed, e.g. for LVDS where we only change the panel fitter in
9452 intel_set_config_compute_mode_changes(set
, config
);
9454 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
9458 if (config
->mode_changed
) {
9459 ret
= intel_set_mode(set
->crtc
, set
->mode
,
9460 set
->x
, set
->y
, set
->fb
);
9461 } else if (config
->fb_changed
) {
9462 intel_crtc_wait_for_pending_flips(set
->crtc
);
9464 ret
= intel_pipe_set_base(set
->crtc
,
9465 set
->x
, set
->y
, set
->fb
);
9469 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9470 set
->crtc
->base
.id
, ret
);
9472 intel_set_config_restore_state(dev
, config
);
9474 /* Try to restore the config */
9475 if (config
->mode_changed
&&
9476 intel_set_mode(save_set
.crtc
, save_set
.mode
,
9477 save_set
.x
, save_set
.y
, save_set
.fb
))
9478 DRM_ERROR("failed to restore config after modeset failure\n");
9482 intel_set_config_free(config
);
9486 static const struct drm_crtc_funcs intel_crtc_funcs
= {
9487 .cursor_set
= intel_crtc_cursor_set
,
9488 .cursor_move
= intel_crtc_cursor_move
,
9489 .gamma_set
= intel_crtc_gamma_set
,
9490 .set_config
= intel_crtc_set_config
,
9491 .destroy
= intel_crtc_destroy
,
9492 .page_flip
= intel_crtc_page_flip
,
9495 static void intel_cpu_pll_init(struct drm_device
*dev
)
9498 intel_ddi_pll_init(dev
);
9501 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
9502 struct intel_shared_dpll
*pll
,
9503 struct intel_dpll_hw_state
*hw_state
)
9507 val
= I915_READ(PCH_DPLL(pll
->id
));
9508 hw_state
->dpll
= val
;
9509 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
9510 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
9512 return val
& DPLL_VCO_ENABLE
;
9515 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
9516 struct intel_shared_dpll
*pll
)
9518 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
9519 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
9522 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
9523 struct intel_shared_dpll
*pll
)
9525 /* PCH refclock must be enabled first */
9526 assert_pch_refclk_enabled(dev_priv
);
9528 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9530 /* Wait for the clocks to stabilize. */
9531 POSTING_READ(PCH_DPLL(pll
->id
));
9534 /* The pixel multiplier can only be updated once the
9535 * DPLL is enabled and the clocks are stable.
9537 * So write it again.
9539 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
9540 POSTING_READ(PCH_DPLL(pll
->id
));
9544 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
9545 struct intel_shared_dpll
*pll
)
9547 struct drm_device
*dev
= dev_priv
->dev
;
9548 struct intel_crtc
*crtc
;
9550 /* Make sure no transcoder isn't still depending on us. */
9551 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, base
.head
) {
9552 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
9553 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
9556 I915_WRITE(PCH_DPLL(pll
->id
), 0);
9557 POSTING_READ(PCH_DPLL(pll
->id
));
9561 static char *ibx_pch_dpll_names
[] = {
9566 static void ibx_pch_dpll_init(struct drm_device
*dev
)
9568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9571 dev_priv
->num_shared_dpll
= 2;
9573 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
9574 dev_priv
->shared_dplls
[i
].id
= i
;
9575 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
9576 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
9577 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
9578 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
9579 dev_priv
->shared_dplls
[i
].get_hw_state
=
9580 ibx_pch_dpll_get_hw_state
;
9584 static void intel_shared_dpll_init(struct drm_device
*dev
)
9586 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9588 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
9589 ibx_pch_dpll_init(dev
);
9591 dev_priv
->num_shared_dpll
= 0;
9593 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
9594 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9595 dev_priv
->num_shared_dpll
);
9598 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
9600 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9601 struct intel_crtc
*intel_crtc
;
9604 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
9605 if (intel_crtc
== NULL
)
9608 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
9610 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
9611 for (i
= 0; i
< 256; i
++) {
9612 intel_crtc
->lut_r
[i
] = i
;
9613 intel_crtc
->lut_g
[i
] = i
;
9614 intel_crtc
->lut_b
[i
] = i
;
9617 /* Swap pipes & planes for FBC on pre-965 */
9618 intel_crtc
->pipe
= pipe
;
9619 intel_crtc
->plane
= pipe
;
9620 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
9621 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
9622 intel_crtc
->plane
= !pipe
;
9625 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
9626 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
9627 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
9628 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
9630 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
9633 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
9634 struct drm_file
*file
)
9636 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
9637 struct drm_mode_object
*drmmode_obj
;
9638 struct intel_crtc
*crtc
;
9640 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
9643 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
9644 DRM_MODE_OBJECT_CRTC
);
9647 DRM_ERROR("no such CRTC id\n");
9651 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
9652 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
9657 static int intel_encoder_clones(struct intel_encoder
*encoder
)
9659 struct drm_device
*dev
= encoder
->base
.dev
;
9660 struct intel_encoder
*source_encoder
;
9664 list_for_each_entry(source_encoder
,
9665 &dev
->mode_config
.encoder_list
, base
.head
) {
9667 if (encoder
== source_encoder
)
9668 index_mask
|= (1 << entry
);
9670 /* Intel hw has only one MUX where enocoders could be cloned. */
9671 if (encoder
->cloneable
&& source_encoder
->cloneable
)
9672 index_mask
|= (1 << entry
);
9680 static bool has_edp_a(struct drm_device
*dev
)
9682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9684 if (!IS_MOBILE(dev
))
9687 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
9691 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
9697 static void intel_setup_outputs(struct drm_device
*dev
)
9699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9700 struct intel_encoder
*encoder
;
9701 bool dpd_is_edp
= false;
9703 intel_lvds_init(dev
);
9706 intel_crt_init(dev
);
9711 /* Haswell uses DDI functions to detect digital outputs */
9712 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
9713 /* DDI A only supports eDP */
9715 intel_ddi_init(dev
, PORT_A
);
9717 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9719 found
= I915_READ(SFUSE_STRAP
);
9721 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
9722 intel_ddi_init(dev
, PORT_B
);
9723 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
9724 intel_ddi_init(dev
, PORT_C
);
9725 if (found
& SFUSE_STRAP_DDID_DETECTED
)
9726 intel_ddi_init(dev
, PORT_D
);
9727 } else if (HAS_PCH_SPLIT(dev
)) {
9729 dpd_is_edp
= intel_dpd_is_edp(dev
);
9732 intel_dp_init(dev
, DP_A
, PORT_A
);
9734 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
9735 /* PCH SDVOB multiplex with HDMIB */
9736 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
9738 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
9739 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
9740 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
9743 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
9744 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
9746 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
9747 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
9749 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
9750 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
9752 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
9753 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
9754 } else if (IS_VALLEYVIEW(dev
)) {
9755 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9756 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
9757 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
9759 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
9760 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
,
9764 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
9765 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
9767 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
9768 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
9771 intel_dsi_init(dev
);
9772 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
9775 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9776 DRM_DEBUG_KMS("probing SDVOB\n");
9777 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
9778 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
9779 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9780 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
9783 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
9784 intel_dp_init(dev
, DP_B
, PORT_B
);
9787 /* Before G4X SDVOC doesn't have its own detect register */
9789 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
9790 DRM_DEBUG_KMS("probing SDVOC\n");
9791 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
9794 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
9796 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
9797 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9798 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
9800 if (SUPPORTS_INTEGRATED_DP(dev
))
9801 intel_dp_init(dev
, DP_C
, PORT_C
);
9804 if (SUPPORTS_INTEGRATED_DP(dev
) &&
9805 (I915_READ(DP_D
) & DP_DETECTED
))
9806 intel_dp_init(dev
, DP_D
, PORT_D
);
9807 } else if (IS_GEN2(dev
))
9808 intel_dvo_init(dev
);
9810 if (SUPPORTS_TV(dev
))
9813 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
9814 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
9815 encoder
->base
.possible_clones
=
9816 intel_encoder_clones(encoder
);
9819 intel_init_pch_refclk(dev
);
9821 drm_helper_move_panel_connectors_to_head(dev
);
9824 void intel_framebuffer_fini(struct intel_framebuffer
*fb
)
9826 drm_framebuffer_cleanup(&fb
->base
);
9827 drm_gem_object_unreference_unlocked(&fb
->obj
->base
);
9830 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
9832 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9834 intel_framebuffer_fini(intel_fb
);
9838 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
9839 struct drm_file
*file
,
9840 unsigned int *handle
)
9842 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9843 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9845 return drm_gem_handle_create(file
, &obj
->base
, handle
);
9848 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
9849 .destroy
= intel_user_framebuffer_destroy
,
9850 .create_handle
= intel_user_framebuffer_create_handle
,
9853 int intel_framebuffer_init(struct drm_device
*dev
,
9854 struct intel_framebuffer
*intel_fb
,
9855 struct drm_mode_fb_cmd2
*mode_cmd
,
9856 struct drm_i915_gem_object
*obj
)
9861 if (obj
->tiling_mode
== I915_TILING_Y
) {
9862 DRM_DEBUG("hardware does not support tiling Y\n");
9866 if (mode_cmd
->pitches
[0] & 63) {
9867 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9868 mode_cmd
->pitches
[0]);
9872 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
9873 pitch_limit
= 32*1024;
9874 } else if (INTEL_INFO(dev
)->gen
>= 4) {
9875 if (obj
->tiling_mode
)
9876 pitch_limit
= 16*1024;
9878 pitch_limit
= 32*1024;
9879 } else if (INTEL_INFO(dev
)->gen
>= 3) {
9880 if (obj
->tiling_mode
)
9881 pitch_limit
= 8*1024;
9883 pitch_limit
= 16*1024;
9885 /* XXX DSPC is limited to 4k tiled */
9886 pitch_limit
= 8*1024;
9888 if (mode_cmd
->pitches
[0] > pitch_limit
) {
9889 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9890 obj
->tiling_mode
? "tiled" : "linear",
9891 mode_cmd
->pitches
[0], pitch_limit
);
9895 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
9896 mode_cmd
->pitches
[0] != obj
->stride
) {
9897 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9898 mode_cmd
->pitches
[0], obj
->stride
);
9902 /* Reject formats not supported by any plane early. */
9903 switch (mode_cmd
->pixel_format
) {
9905 case DRM_FORMAT_RGB565
:
9906 case DRM_FORMAT_XRGB8888
:
9907 case DRM_FORMAT_ARGB8888
:
9909 case DRM_FORMAT_XRGB1555
:
9910 case DRM_FORMAT_ARGB1555
:
9911 if (INTEL_INFO(dev
)->gen
> 3) {
9912 DRM_DEBUG("unsupported pixel format: %s\n",
9913 drm_get_format_name(mode_cmd
->pixel_format
));
9917 case DRM_FORMAT_XBGR8888
:
9918 case DRM_FORMAT_ABGR8888
:
9919 case DRM_FORMAT_XRGB2101010
:
9920 case DRM_FORMAT_ARGB2101010
:
9921 case DRM_FORMAT_XBGR2101010
:
9922 case DRM_FORMAT_ABGR2101010
:
9923 if (INTEL_INFO(dev
)->gen
< 4) {
9924 DRM_DEBUG("unsupported pixel format: %s\n",
9925 drm_get_format_name(mode_cmd
->pixel_format
));
9929 case DRM_FORMAT_YUYV
:
9930 case DRM_FORMAT_UYVY
:
9931 case DRM_FORMAT_YVYU
:
9932 case DRM_FORMAT_VYUY
:
9933 if (INTEL_INFO(dev
)->gen
< 5) {
9934 DRM_DEBUG("unsupported pixel format: %s\n",
9935 drm_get_format_name(mode_cmd
->pixel_format
));
9940 DRM_DEBUG("unsupported pixel format: %s\n",
9941 drm_get_format_name(mode_cmd
->pixel_format
));
9945 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9946 if (mode_cmd
->offsets
[0] != 0)
9949 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
9950 intel_fb
->obj
= obj
;
9952 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
9954 DRM_ERROR("framebuffer init failed %d\n", ret
);
9961 static struct drm_framebuffer
*
9962 intel_user_framebuffer_create(struct drm_device
*dev
,
9963 struct drm_file
*filp
,
9964 struct drm_mode_fb_cmd2
*mode_cmd
)
9966 struct drm_i915_gem_object
*obj
;
9968 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
9969 mode_cmd
->handles
[0]));
9970 if (&obj
->base
== NULL
)
9971 return ERR_PTR(-ENOENT
);
9973 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
9976 static const struct drm_mode_config_funcs intel_mode_funcs
= {
9977 .fb_create
= intel_user_framebuffer_create
,
9978 .output_poll_changed
= intel_fb_output_poll_changed
,
9981 /* Set up chip specific display functions */
9982 static void intel_init_display(struct drm_device
*dev
)
9984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9986 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
9987 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
9988 else if (IS_VALLEYVIEW(dev
))
9989 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
9990 else if (IS_PINEVIEW(dev
))
9991 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
9993 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
9996 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
9997 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
9998 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
9999 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
10000 dev_priv
->display
.off
= haswell_crtc_off
;
10001 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10002 } else if (HAS_PCH_SPLIT(dev
)) {
10003 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
10004 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
10005 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
10006 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
10007 dev_priv
->display
.off
= ironlake_crtc_off
;
10008 dev_priv
->display
.update_plane
= ironlake_update_plane
;
10009 } else if (IS_VALLEYVIEW(dev
)) {
10010 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10011 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10012 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
10013 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10014 dev_priv
->display
.off
= i9xx_crtc_off
;
10015 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10017 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
10018 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
10019 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
10020 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
10021 dev_priv
->display
.off
= i9xx_crtc_off
;
10022 dev_priv
->display
.update_plane
= i9xx_update_plane
;
10025 /* Returns the core display clock speed */
10026 if (IS_VALLEYVIEW(dev
))
10027 dev_priv
->display
.get_display_clock_speed
=
10028 valleyview_get_display_clock_speed
;
10029 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
10030 dev_priv
->display
.get_display_clock_speed
=
10031 i945_get_display_clock_speed
;
10032 else if (IS_I915G(dev
))
10033 dev_priv
->display
.get_display_clock_speed
=
10034 i915_get_display_clock_speed
;
10035 else if (IS_I945GM(dev
) || IS_845G(dev
))
10036 dev_priv
->display
.get_display_clock_speed
=
10037 i9xx_misc_get_display_clock_speed
;
10038 else if (IS_PINEVIEW(dev
))
10039 dev_priv
->display
.get_display_clock_speed
=
10040 pnv_get_display_clock_speed
;
10041 else if (IS_I915GM(dev
))
10042 dev_priv
->display
.get_display_clock_speed
=
10043 i915gm_get_display_clock_speed
;
10044 else if (IS_I865G(dev
))
10045 dev_priv
->display
.get_display_clock_speed
=
10046 i865_get_display_clock_speed
;
10047 else if (IS_I85X(dev
))
10048 dev_priv
->display
.get_display_clock_speed
=
10049 i855_get_display_clock_speed
;
10050 else /* 852, 830 */
10051 dev_priv
->display
.get_display_clock_speed
=
10052 i830_get_display_clock_speed
;
10054 if (HAS_PCH_SPLIT(dev
)) {
10055 if (IS_GEN5(dev
)) {
10056 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
10057 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10058 } else if (IS_GEN6(dev
)) {
10059 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
10060 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10061 } else if (IS_IVYBRIDGE(dev
)) {
10062 /* FIXME: detect B0+ stepping and use auto training */
10063 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
10064 dev_priv
->display
.write_eld
= ironlake_write_eld
;
10065 dev_priv
->display
.modeset_global_resources
=
10066 ivb_modeset_global_resources
;
10067 } else if (IS_HASWELL(dev
)) {
10068 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
10069 dev_priv
->display
.write_eld
= haswell_write_eld
;
10070 dev_priv
->display
.modeset_global_resources
=
10071 haswell_modeset_global_resources
;
10073 } else if (IS_G4X(dev
)) {
10074 dev_priv
->display
.write_eld
= g4x_write_eld
;
10077 /* Default just returns -ENODEV to indicate unsupported */
10078 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
10080 switch (INTEL_INFO(dev
)->gen
) {
10082 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
10086 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
10091 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
10095 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
10098 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
10104 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10105 * resume, or other times. This quirk makes sure that's the case for
10106 * affected systems.
10108 static void quirk_pipea_force(struct drm_device
*dev
)
10110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10112 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
10113 DRM_INFO("applying pipe a force quirk\n");
10117 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10119 static void quirk_ssc_force_disable(struct drm_device
*dev
)
10121 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10122 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
10123 DRM_INFO("applying lvds SSC disable quirk\n");
10127 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10130 static void quirk_invert_brightness(struct drm_device
*dev
)
10132 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10133 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
10134 DRM_INFO("applying inverted panel brightness quirk\n");
10138 * Some machines (Dell XPS13) suffer broken backlight controls if
10139 * BLM_PCH_PWM_ENABLE is set.
10141 static void quirk_no_pcm_pwm_enable(struct drm_device
*dev
)
10143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10144 dev_priv
->quirks
|= QUIRK_NO_PCH_PWM_ENABLE
;
10145 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10148 struct intel_quirk
{
10150 int subsystem_vendor
;
10151 int subsystem_device
;
10152 void (*hook
)(struct drm_device
*dev
);
10155 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10156 struct intel_dmi_quirk
{
10157 void (*hook
)(struct drm_device
*dev
);
10158 const struct dmi_system_id (*dmi_id_list
)[];
10161 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
10163 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
10167 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
10169 .dmi_id_list
= &(const struct dmi_system_id
[]) {
10171 .callback
= intel_dmi_reverse_brightness
,
10172 .ident
= "NCR Corporation",
10173 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
10174 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
10177 { } /* terminating entry */
10179 .hook
= quirk_invert_brightness
,
10183 static struct intel_quirk intel_quirks
[] = {
10184 /* HP Mini needs pipe A force quirk (LP: #322104) */
10185 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
10187 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10188 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
10190 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10191 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
10193 /* 830/845 need to leave pipe A & dpll A up */
10194 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10195 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
10197 /* Lenovo U160 cannot use SSC on LVDS */
10198 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
10200 /* Sony Vaio Y cannot use SSC on LVDS */
10201 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
10204 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10205 * seem to use inverted backlight PWM.
10207 { 0x2a42, 0x1025, PCI_ANY_ID
, quirk_invert_brightness
},
10209 /* Dell XPS13 HD Sandy Bridge */
10210 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable
},
10211 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10212 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable
},
10215 static void intel_init_quirks(struct drm_device
*dev
)
10217 struct pci_dev
*d
= dev
->pdev
;
10220 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
10221 struct intel_quirk
*q
= &intel_quirks
[i
];
10223 if (d
->device
== q
->device
&&
10224 (d
->subsystem_vendor
== q
->subsystem_vendor
||
10225 q
->subsystem_vendor
== PCI_ANY_ID
) &&
10226 (d
->subsystem_device
== q
->subsystem_device
||
10227 q
->subsystem_device
== PCI_ANY_ID
))
10230 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
10231 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
10232 intel_dmi_quirks
[i
].hook(dev
);
10236 /* Disable the VGA plane that we never use */
10237 static void i915_disable_vga(struct drm_device
*dev
)
10239 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10241 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10243 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10244 outb(SR01
, VGA_SR_INDEX
);
10245 sr1
= inb(VGA_SR_DATA
);
10246 outb(sr1
| 1<<5, VGA_SR_DATA
);
10247 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10250 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
10251 POSTING_READ(vga_reg
);
10254 static void i915_enable_vga_mem(struct drm_device
*dev
)
10256 /* Enable VGA memory on Intel HD */
10257 if (HAS_PCH_SPLIT(dev
)) {
10258 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10259 outb(inb(VGA_MSR_READ
) | VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10260 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10261 VGA_RSRC_LEGACY_MEM
|
10262 VGA_RSRC_NORMAL_IO
|
10263 VGA_RSRC_NORMAL_MEM
);
10264 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10268 void i915_disable_vga_mem(struct drm_device
*dev
)
10270 /* Disable VGA memory on Intel HD */
10271 if (HAS_PCH_SPLIT(dev
)) {
10272 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10273 outb(inb(VGA_MSR_READ
) & ~VGA_MSR_MEM_EN
, VGA_MSR_WRITE
);
10274 vga_set_legacy_decoding(dev
->pdev
, VGA_RSRC_LEGACY_IO
|
10275 VGA_RSRC_NORMAL_IO
|
10276 VGA_RSRC_NORMAL_MEM
);
10277 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
10281 void intel_modeset_init_hw(struct drm_device
*dev
)
10283 intel_prepare_ddi(dev
);
10285 intel_init_clock_gating(dev
);
10287 mutex_lock(&dev
->struct_mutex
);
10288 intel_enable_gt_powersave(dev
);
10289 mutex_unlock(&dev
->struct_mutex
);
10292 void intel_modeset_suspend_hw(struct drm_device
*dev
)
10294 intel_suspend_hw(dev
);
10297 void intel_modeset_init(struct drm_device
*dev
)
10299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10302 drm_mode_config_init(dev
);
10304 dev
->mode_config
.min_width
= 0;
10305 dev
->mode_config
.min_height
= 0;
10307 dev
->mode_config
.preferred_depth
= 24;
10308 dev
->mode_config
.prefer_shadow
= 1;
10310 dev
->mode_config
.funcs
= &intel_mode_funcs
;
10312 intel_init_quirks(dev
);
10314 intel_init_pm(dev
);
10316 if (INTEL_INFO(dev
)->num_pipes
== 0)
10319 intel_init_display(dev
);
10321 if (IS_GEN2(dev
)) {
10322 dev
->mode_config
.max_width
= 2048;
10323 dev
->mode_config
.max_height
= 2048;
10324 } else if (IS_GEN3(dev
)) {
10325 dev
->mode_config
.max_width
= 4096;
10326 dev
->mode_config
.max_height
= 4096;
10328 dev
->mode_config
.max_width
= 8192;
10329 dev
->mode_config
.max_height
= 8192;
10331 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
10333 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10334 INTEL_INFO(dev
)->num_pipes
,
10335 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
10338 intel_crtc_init(dev
, i
);
10339 for (j
= 0; j
< dev_priv
->num_plane
; j
++) {
10340 ret
= intel_plane_init(dev
, i
, j
);
10342 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10343 pipe_name(i
), sprite_name(i
, j
), ret
);
10347 intel_cpu_pll_init(dev
);
10348 intel_shared_dpll_init(dev
);
10350 /* Just disable it once at startup */
10351 i915_disable_vga(dev
);
10352 intel_setup_outputs(dev
);
10354 /* Just in case the BIOS is doing something questionable. */
10355 intel_disable_fbc(dev
);
10359 intel_connector_break_all_links(struct intel_connector
*connector
)
10361 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10362 connector
->base
.encoder
= NULL
;
10363 connector
->encoder
->connectors_active
= false;
10364 connector
->encoder
->base
.crtc
= NULL
;
10367 static void intel_enable_pipe_a(struct drm_device
*dev
)
10369 struct intel_connector
*connector
;
10370 struct drm_connector
*crt
= NULL
;
10371 struct intel_load_detect_pipe load_detect_temp
;
10373 /* We can't just switch on the pipe A, we need to set things up with a
10374 * proper mode and output configuration. As a gross hack, enable pipe A
10375 * by enabling the load detect pipe once. */
10376 list_for_each_entry(connector
,
10377 &dev
->mode_config
.connector_list
,
10379 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
10380 crt
= &connector
->base
;
10388 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
10389 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
10395 intel_check_plane_mapping(struct intel_crtc
*crtc
)
10397 struct drm_device
*dev
= crtc
->base
.dev
;
10398 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10401 if (INTEL_INFO(dev
)->num_pipes
== 1)
10404 reg
= DSPCNTR(!crtc
->plane
);
10405 val
= I915_READ(reg
);
10407 if ((val
& DISPLAY_PLANE_ENABLE
) &&
10408 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
10414 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
10416 struct drm_device
*dev
= crtc
->base
.dev
;
10417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10420 /* Clear any frame start delays used for debugging left by the BIOS */
10421 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
10422 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
10424 /* We need to sanitize the plane -> pipe mapping first because this will
10425 * disable the crtc (and hence change the state) if it is wrong. Note
10426 * that gen4+ has a fixed plane -> pipe mapping. */
10427 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
10428 struct intel_connector
*connector
;
10431 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10432 crtc
->base
.base
.id
);
10434 /* Pipe has the wrong plane attached and the plane is active.
10435 * Temporarily change the plane mapping and disable everything
10437 plane
= crtc
->plane
;
10438 crtc
->plane
= !plane
;
10439 dev_priv
->display
.crtc_disable(&crtc
->base
);
10440 crtc
->plane
= plane
;
10442 /* ... and break all links. */
10443 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10445 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
10448 intel_connector_break_all_links(connector
);
10451 WARN_ON(crtc
->active
);
10452 crtc
->base
.enabled
= false;
10455 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
10456 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
10457 /* BIOS forgot to enable pipe A, this mostly happens after
10458 * resume. Force-enable the pipe to fix this, the update_dpms
10459 * call below we restore the pipe to the right state, but leave
10460 * the required bits on. */
10461 intel_enable_pipe_a(dev
);
10464 /* Adjust the state of the output pipe according to whether we
10465 * have active connectors/encoders. */
10466 intel_crtc_update_dpms(&crtc
->base
);
10468 if (crtc
->active
!= crtc
->base
.enabled
) {
10469 struct intel_encoder
*encoder
;
10471 /* This can happen either due to bugs in the get_hw_state
10472 * functions or because the pipe is force-enabled due to the
10474 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10475 crtc
->base
.base
.id
,
10476 crtc
->base
.enabled
? "enabled" : "disabled",
10477 crtc
->active
? "enabled" : "disabled");
10479 crtc
->base
.enabled
= crtc
->active
;
10481 /* Because we only establish the connector -> encoder ->
10482 * crtc links if something is active, this means the
10483 * crtc is now deactivated. Break the links. connector
10484 * -> encoder links are only establish when things are
10485 * actually up, hence no need to break them. */
10486 WARN_ON(crtc
->active
);
10488 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
10489 WARN_ON(encoder
->connectors_active
);
10490 encoder
->base
.crtc
= NULL
;
10495 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
10497 struct intel_connector
*connector
;
10498 struct drm_device
*dev
= encoder
->base
.dev
;
10500 /* We need to check both for a crtc link (meaning that the
10501 * encoder is active and trying to read from a pipe) and the
10502 * pipe itself being active. */
10503 bool has_active_crtc
= encoder
->base
.crtc
&&
10504 to_intel_crtc(encoder
->base
.crtc
)->active
;
10506 if (encoder
->connectors_active
&& !has_active_crtc
) {
10507 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10508 encoder
->base
.base
.id
,
10509 drm_get_encoder_name(&encoder
->base
));
10511 /* Connector is active, but has no active pipe. This is
10512 * fallout from our resume register restoring. Disable
10513 * the encoder manually again. */
10514 if (encoder
->base
.crtc
) {
10515 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10516 encoder
->base
.base
.id
,
10517 drm_get_encoder_name(&encoder
->base
));
10518 encoder
->disable(encoder
);
10521 /* Inconsistent output/port/pipe state happens presumably due to
10522 * a bug in one of the get_hw_state functions. Or someplace else
10523 * in our code, like the register restore mess on resume. Clamp
10524 * things to off as a safer default. */
10525 list_for_each_entry(connector
,
10526 &dev
->mode_config
.connector_list
,
10528 if (connector
->encoder
!= encoder
)
10531 intel_connector_break_all_links(connector
);
10534 /* Enabled encoders without active connectors will be fixed in
10535 * the crtc fixup. */
10538 void i915_redisable_vga(struct drm_device
*dev
)
10540 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10541 u32 vga_reg
= i915_vgacntrl_reg(dev
);
10543 /* This function can be called both from intel_modeset_setup_hw_state or
10544 * at a very early point in our resume sequence, where the power well
10545 * structures are not yet restored. Since this function is at a very
10546 * paranoid "someone might have enabled VGA while we were not looking"
10547 * level, just check if the power well is enabled instead of trying to
10548 * follow the "don't touch the power well if we don't need it" policy
10549 * the rest of the driver uses. */
10550 if (HAS_POWER_WELL(dev
) &&
10551 (I915_READ(HSW_PWR_WELL_DRIVER
) & HSW_PWR_WELL_STATE_ENABLED
) == 0)
10554 if (I915_READ(vga_reg
) != VGA_DISP_DISABLE
) {
10555 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
10556 i915_disable_vga(dev
);
10557 i915_disable_vga_mem(dev
);
10561 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
10563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10565 struct intel_crtc
*crtc
;
10566 struct intel_encoder
*encoder
;
10567 struct intel_connector
*connector
;
10570 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10572 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
10574 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
10577 crtc
->base
.enabled
= crtc
->active
;
10579 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10580 crtc
->base
.base
.id
,
10581 crtc
->active
? "enabled" : "disabled");
10584 /* FIXME: Smash this into the new shared dpll infrastructure. */
10586 intel_ddi_setup_hw_pll_state(dev
);
10588 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10589 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10591 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
10593 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10595 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10598 pll
->refcount
= pll
->active
;
10600 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10601 pll
->name
, pll
->refcount
, pll
->on
);
10604 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10608 if (encoder
->get_hw_state(encoder
, &pipe
)) {
10609 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10610 encoder
->base
.crtc
= &crtc
->base
;
10611 if (encoder
->get_config
)
10612 encoder
->get_config(encoder
, &crtc
->config
);
10614 encoder
->base
.crtc
= NULL
;
10617 encoder
->connectors_active
= false;
10618 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10619 encoder
->base
.base
.id
,
10620 drm_get_encoder_name(&encoder
->base
),
10621 encoder
->base
.crtc
? "enabled" : "disabled",
10625 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10627 if (connector
->get_hw_state(connector
)) {
10628 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
10629 connector
->encoder
->connectors_active
= true;
10630 connector
->base
.encoder
= &connector
->encoder
->base
;
10632 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
10633 connector
->base
.encoder
= NULL
;
10635 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10636 connector
->base
.base
.id
,
10637 drm_get_connector_name(&connector
->base
),
10638 connector
->base
.encoder
? "enabled" : "disabled");
10642 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10643 * and i915 state tracking structures. */
10644 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
10645 bool force_restore
)
10647 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10649 struct intel_crtc
*crtc
;
10650 struct intel_encoder
*encoder
;
10653 intel_modeset_readout_hw_state(dev
);
10656 * Now that we have the config, copy it to each CRTC struct
10657 * Note that this could go away if we move to using crtc_config
10658 * checking everywhere.
10660 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
10662 if (crtc
->active
&& i915_fastboot
) {
10663 intel_crtc_mode_from_pipe_config(crtc
, &crtc
->config
);
10665 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10666 crtc
->base
.base
.id
);
10667 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
10671 /* HW state is read out, now we need to sanitize this mess. */
10672 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
10674 intel_sanitize_encoder(encoder
);
10677 for_each_pipe(pipe
) {
10678 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
10679 intel_sanitize_crtc(crtc
);
10680 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
10683 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10684 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10686 if (!pll
->on
|| pll
->active
)
10689 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
10691 pll
->disable(dev_priv
, pll
);
10695 if (force_restore
) {
10696 i915_redisable_vga(dev
);
10699 * We need to use raw interfaces for restoring state to avoid
10700 * checking (bogus) intermediate states.
10702 for_each_pipe(pipe
) {
10703 struct drm_crtc
*crtc
=
10704 dev_priv
->pipe_to_crtc_mapping
[pipe
];
10706 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
10710 intel_modeset_update_staged_output_state(dev
);
10713 intel_modeset_check_state(dev
);
10715 drm_mode_config_reset(dev
);
10718 void intel_modeset_gem_init(struct drm_device
*dev
)
10720 intel_modeset_init_hw(dev
);
10722 intel_setup_overlay(dev
);
10724 intel_modeset_setup_hw_state(dev
, false);
10727 void intel_modeset_cleanup(struct drm_device
*dev
)
10729 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10730 struct drm_crtc
*crtc
;
10733 * Interrupts and polling as the first thing to avoid creating havoc.
10734 * Too much stuff here (turning of rps, connectors, ...) would
10735 * experience fancy races otherwise.
10737 drm_irq_uninstall(dev
);
10738 cancel_work_sync(&dev_priv
->hotplug_work
);
10740 * Due to the hpd irq storm handling the hotplug work can re-arm the
10741 * poll handlers. Hence disable polling after hpd handling is shut down.
10743 drm_kms_helper_poll_fini(dev
);
10745 mutex_lock(&dev
->struct_mutex
);
10747 intel_unregister_dsm_handler();
10749 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
10750 /* Skip inactive CRTCs */
10754 intel_increase_pllclock(crtc
);
10757 intel_disable_fbc(dev
);
10759 i915_enable_vga_mem(dev
);
10761 intel_disable_gt_powersave(dev
);
10763 ironlake_teardown_rc6(dev
);
10765 mutex_unlock(&dev
->struct_mutex
);
10767 /* flush any delayed tasks or pending work */
10768 flush_scheduled_work();
10770 /* destroy backlight, if any, before the connectors */
10771 intel_panel_destroy_backlight(dev
);
10773 drm_mode_config_cleanup(dev
);
10775 intel_cleanup_overlay(dev
);
10779 * Return which encoder is currently attached for connector.
10781 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
10783 return &intel_attached_encoder(connector
)->base
;
10786 void intel_connector_attach_encoder(struct intel_connector
*connector
,
10787 struct intel_encoder
*encoder
)
10789 connector
->encoder
= encoder
;
10790 drm_mode_connector_attach_encoder(&connector
->base
,
10795 * set vga decode state - true == enable VGA decode
10797 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
10799 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10802 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
10804 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
10806 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
10807 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
10811 struct intel_display_error_state
{
10813 u32 power_well_driver
;
10815 int num_transcoders
;
10817 struct intel_cursor_error_state
{
10822 } cursor
[I915_MAX_PIPES
];
10824 struct intel_pipe_error_state
{
10826 } pipe
[I915_MAX_PIPES
];
10828 struct intel_plane_error_state
{
10836 } plane
[I915_MAX_PIPES
];
10838 struct intel_transcoder_error_state
{
10839 enum transcoder cpu_transcoder
;
10852 struct intel_display_error_state
*
10853 intel_display_capture_error_state(struct drm_device
*dev
)
10855 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
10856 struct intel_display_error_state
*error
;
10857 int transcoders
[] = {
10865 if (INTEL_INFO(dev
)->num_pipes
== 0)
10868 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
10872 if (HAS_POWER_WELL(dev
))
10873 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
10876 if (INTEL_INFO(dev
)->gen
<= 6 || IS_VALLEYVIEW(dev
)) {
10877 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
10878 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
10879 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
10881 error
->cursor
[i
].control
= I915_READ(CURCNTR_IVB(i
));
10882 error
->cursor
[i
].position
= I915_READ(CURPOS_IVB(i
));
10883 error
->cursor
[i
].base
= I915_READ(CURBASE_IVB(i
));
10886 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
10887 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
10888 if (INTEL_INFO(dev
)->gen
<= 3) {
10889 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
10890 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
10892 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10893 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
10894 if (INTEL_INFO(dev
)->gen
>= 4) {
10895 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
10896 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
10899 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
10902 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
10903 if (HAS_DDI(dev_priv
->dev
))
10904 error
->num_transcoders
++; /* Account for eDP. */
10906 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10907 enum transcoder cpu_transcoder
= transcoders
[i
];
10909 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
10911 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
10912 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
10913 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
10914 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
10915 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
10916 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
10917 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
10920 /* In the code above we read the registers without checking if the power
10921 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10922 * prevent the next I915_WRITE from detecting it and printing an error
10924 intel_uncore_clear_errors(dev
);
10929 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10932 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
10933 struct drm_device
*dev
,
10934 struct intel_display_error_state
*error
)
10941 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
10942 if (HAS_POWER_WELL(dev
))
10943 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
10944 error
->power_well_driver
);
10946 err_printf(m
, "Pipe [%d]:\n", i
);
10947 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
10949 err_printf(m
, "Plane [%d]:\n", i
);
10950 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
10951 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
10952 if (INTEL_INFO(dev
)->gen
<= 3) {
10953 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
10954 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
10956 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
10957 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
10958 if (INTEL_INFO(dev
)->gen
>= 4) {
10959 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
10960 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
10963 err_printf(m
, "Cursor [%d]:\n", i
);
10964 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
10965 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
10966 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
10969 for (i
= 0; i
< error
->num_transcoders
; i
++) {
10970 err_printf(m
, " CPU transcoder: %c\n",
10971 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
10972 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
10973 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
10974 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
10975 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
10976 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
10977 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
10978 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);