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drm/i915: Disable LP1+ watermarks safely in init
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 static void intel_increase_pllclock(struct drm_crtc *crtc);
45 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
46
47 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
49 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
51
52 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
56 typedef struct {
57 int min, max;
58 } intel_range_t;
59
60 typedef struct {
61 int dot_limit;
62 int p2_slow, p2_fast;
63 } intel_p2_t;
64
65 typedef struct intel_limit intel_limit_t;
66 struct intel_limit {
67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
69 };
70
71 int
72 intel_pch_rawclk(struct drm_device *dev)
73 {
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79 }
80
81 static inline u32 /* units of 100MHz */
82 intel_fdi_link_freq(struct drm_device *dev)
83 {
84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
89 }
90
91 static const intel_limit_t intel_limits_i8xx_dac = {
92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 908000, .max = 1512000 },
94 .n = { .min = 2, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
102 };
103
104 static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 908000, .max = 1512000 },
107 .n = { .min = 2, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115 };
116
117 static const intel_limit_t intel_limits_i8xx_lvds = {
118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 908000, .max = 1512000 },
120 .n = { .min = 2, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
128 };
129
130 static const intel_limit_t intel_limits_i9xx_sdvo = {
131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
141 };
142
143 static const intel_limit_t intel_limits_i9xx_lvds = {
144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
154 };
155
156
157 static const intel_limit_t intel_limits_g4x_sdvo = {
158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
169 },
170 };
171
172 static const intel_limit_t intel_limits_g4x_hdmi = {
173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
183 };
184
185 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
196 },
197 };
198
199 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
210 },
211 };
212
213 static const intel_limit_t intel_limits_pineview_sdvo = {
214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
216 /* Pineview's Ncounter is a ring counter */
217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
219 /* Pineview only has one combined m divider, which we treat as m2. */
220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
226 };
227
228 static const intel_limit_t intel_limits_pineview_lvds = {
229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
239 };
240
241 /* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
246 static const intel_limit_t intel_limits_ironlake_dac = {
247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
257 };
258
259 static const intel_limit_t intel_limits_ironlake_single_lvds = {
260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
270 };
271
272 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
283 };
284
285 /* LVDS 100mhz refclk limits. */
286 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
294 .p1 = { .min = 2, .max = 8 },
295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
307 .p1 = { .min = 2, .max = 6 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
310 };
311
312 static const intel_limit_t intel_limits_vlv = {
313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
324 .p1 = { .min = 2, .max = 3 },
325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
326 };
327
328 static void vlv_clock(int refclk, intel_clock_t *clock)
329 {
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 if (WARN_ON(clock->n == 0 || clock->p == 0))
333 return;
334 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
335 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
336 }
337
338 /**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342 {
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351 }
352
353 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
355 {
356 struct drm_device *dev = crtc->dev;
357 const intel_limit_t *limit;
358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
360 if (intel_is_dual_link_lvds(dev)) {
361 if (refclk == 100000)
362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
366 if (refclk == 100000)
367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
371 } else
372 limit = &intel_limits_ironlake_dac;
373
374 return limit;
375 }
376
377 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378 {
379 struct drm_device *dev = crtc->dev;
380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
383 if (intel_is_dual_link_lvds(dev))
384 limit = &intel_limits_g4x_dual_channel_lvds;
385 else
386 limit = &intel_limits_g4x_single_channel_lvds;
387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
389 limit = &intel_limits_g4x_hdmi;
390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
391 limit = &intel_limits_g4x_sdvo;
392 } else /* The option is for other outputs */
393 limit = &intel_limits_i9xx_sdvo;
394
395 return limit;
396 }
397
398 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
399 {
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
403 if (HAS_PCH_SPLIT(dev))
404 limit = intel_ironlake_limit(crtc, refclk);
405 else if (IS_G4X(dev)) {
406 limit = intel_g4x_limit(crtc);
407 } else if (IS_PINEVIEW(dev)) {
408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
409 limit = &intel_limits_pineview_lvds;
410 else
411 limit = &intel_limits_pineview_sdvo;
412 } else if (IS_VALLEYVIEW(dev)) {
413 limit = &intel_limits_vlv;
414 } else if (!IS_GEN2(dev)) {
415 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
416 limit = &intel_limits_i9xx_lvds;
417 else
418 limit = &intel_limits_i9xx_sdvo;
419 } else {
420 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
421 limit = &intel_limits_i8xx_lvds;
422 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
423 limit = &intel_limits_i8xx_dvo;
424 else
425 limit = &intel_limits_i8xx_dac;
426 }
427 return limit;
428 }
429
430 /* m1 is reserved as 0 in Pineview, n is a ring counter */
431 static void pineview_clock(int refclk, intel_clock_t *clock)
432 {
433 clock->m = clock->m2 + 2;
434 clock->p = clock->p1 * clock->p2;
435 if (WARN_ON(clock->n == 0 || clock->p == 0))
436 return;
437 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
438 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
439 }
440
441 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
442 {
443 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
444 }
445
446 static void i9xx_clock(int refclk, intel_clock_t *clock)
447 {
448 clock->m = i9xx_dpll_compute_m(clock);
449 clock->p = clock->p1 * clock->p2;
450 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
451 return;
452 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
453 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
454 }
455
456 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
457 /**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
462 static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
465 {
466 if (clock->n < limit->n.min || limit->n.max < clock->n)
467 INTELPllInvalid("n out of range\n");
468 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
469 INTELPllInvalid("p1 out of range\n");
470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
471 INTELPllInvalid("m2 out of range\n");
472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
473 INTELPllInvalid("m1 out of range\n");
474
475 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
476 if (clock->m1 <= clock->m2)
477 INTELPllInvalid("m1 <= m2\n");
478
479 if (!IS_VALLEYVIEW(dev)) {
480 if (clock->p < limit->p.min || limit->p.max < clock->p)
481 INTELPllInvalid("p out of range\n");
482 if (clock->m < limit->m.min || limit->m.max < clock->m)
483 INTELPllInvalid("m out of range\n");
484 }
485
486 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
487 INTELPllInvalid("vco out of range\n");
488 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
489 * connector, etc., rather than just a single range.
490 */
491 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
492 INTELPllInvalid("dot out of range\n");
493
494 return true;
495 }
496
497 static bool
498 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
499 int target, int refclk, intel_clock_t *match_clock,
500 intel_clock_t *best_clock)
501 {
502 struct drm_device *dev = crtc->dev;
503 intel_clock_t clock;
504 int err = target;
505
506 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
507 /*
508 * For LVDS just rely on its current settings for dual-channel.
509 * We haven't figured out how to reliably set up different
510 * single/dual channel state, if we even can.
511 */
512 if (intel_is_dual_link_lvds(dev))
513 clock.p2 = limit->p2.p2_fast;
514 else
515 clock.p2 = limit->p2.p2_slow;
516 } else {
517 if (target < limit->p2.dot_limit)
518 clock.p2 = limit->p2.p2_slow;
519 else
520 clock.p2 = limit->p2.p2_fast;
521 }
522
523 memset(best_clock, 0, sizeof(*best_clock));
524
525 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
526 clock.m1++) {
527 for (clock.m2 = limit->m2.min;
528 clock.m2 <= limit->m2.max; clock.m2++) {
529 if (clock.m2 >= clock.m1)
530 break;
531 for (clock.n = limit->n.min;
532 clock.n <= limit->n.max; clock.n++) {
533 for (clock.p1 = limit->p1.min;
534 clock.p1 <= limit->p1.max; clock.p1++) {
535 int this_err;
536
537 i9xx_clock(refclk, &clock);
538 if (!intel_PLL_is_valid(dev, limit,
539 &clock))
540 continue;
541 if (match_clock &&
542 clock.p != match_clock->p)
543 continue;
544
545 this_err = abs(clock.dot - target);
546 if (this_err < err) {
547 *best_clock = clock;
548 err = this_err;
549 }
550 }
551 }
552 }
553 }
554
555 return (err != target);
556 }
557
558 static bool
559 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
560 int target, int refclk, intel_clock_t *match_clock,
561 intel_clock_t *best_clock)
562 {
563 struct drm_device *dev = crtc->dev;
564 intel_clock_t clock;
565 int err = target;
566
567 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
568 /*
569 * For LVDS just rely on its current settings for dual-channel.
570 * We haven't figured out how to reliably set up different
571 * single/dual channel state, if we even can.
572 */
573 if (intel_is_dual_link_lvds(dev))
574 clock.p2 = limit->p2.p2_fast;
575 else
576 clock.p2 = limit->p2.p2_slow;
577 } else {
578 if (target < limit->p2.dot_limit)
579 clock.p2 = limit->p2.p2_slow;
580 else
581 clock.p2 = limit->p2.p2_fast;
582 }
583
584 memset(best_clock, 0, sizeof(*best_clock));
585
586 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
587 clock.m1++) {
588 for (clock.m2 = limit->m2.min;
589 clock.m2 <= limit->m2.max; clock.m2++) {
590 for (clock.n = limit->n.min;
591 clock.n <= limit->n.max; clock.n++) {
592 for (clock.p1 = limit->p1.min;
593 clock.p1 <= limit->p1.max; clock.p1++) {
594 int this_err;
595
596 pineview_clock(refclk, &clock);
597 if (!intel_PLL_is_valid(dev, limit,
598 &clock))
599 continue;
600 if (match_clock &&
601 clock.p != match_clock->p)
602 continue;
603
604 this_err = abs(clock.dot - target);
605 if (this_err < err) {
606 *best_clock = clock;
607 err = this_err;
608 }
609 }
610 }
611 }
612 }
613
614 return (err != target);
615 }
616
617 static bool
618 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
619 int target, int refclk, intel_clock_t *match_clock,
620 intel_clock_t *best_clock)
621 {
622 struct drm_device *dev = crtc->dev;
623 intel_clock_t clock;
624 int max_n;
625 bool found;
626 /* approximately equals target * 0.00585 */
627 int err_most = (target >> 8) + (target >> 9);
628 found = false;
629
630 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
631 if (intel_is_dual_link_lvds(dev))
632 clock.p2 = limit->p2.p2_fast;
633 else
634 clock.p2 = limit->p2.p2_slow;
635 } else {
636 if (target < limit->p2.dot_limit)
637 clock.p2 = limit->p2.p2_slow;
638 else
639 clock.p2 = limit->p2.p2_fast;
640 }
641
642 memset(best_clock, 0, sizeof(*best_clock));
643 max_n = limit->n.max;
644 /* based on hardware requirement, prefer smaller n to precision */
645 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
646 /* based on hardware requirement, prefere larger m1,m2 */
647 for (clock.m1 = limit->m1.max;
648 clock.m1 >= limit->m1.min; clock.m1--) {
649 for (clock.m2 = limit->m2.max;
650 clock.m2 >= limit->m2.min; clock.m2--) {
651 for (clock.p1 = limit->p1.max;
652 clock.p1 >= limit->p1.min; clock.p1--) {
653 int this_err;
654
655 i9xx_clock(refclk, &clock);
656 if (!intel_PLL_is_valid(dev, limit,
657 &clock))
658 continue;
659
660 this_err = abs(clock.dot - target);
661 if (this_err < err_most) {
662 *best_clock = clock;
663 err_most = this_err;
664 max_n = clock.n;
665 found = true;
666 }
667 }
668 }
669 }
670 }
671 return found;
672 }
673
674 static bool
675 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
678 {
679 struct drm_device *dev = crtc->dev;
680 intel_clock_t clock;
681 unsigned int bestppm = 1000000;
682 /* min update 19.2 MHz */
683 int max_n = min(limit->n.max, refclk / 19200);
684 bool found = false;
685
686 target *= 5; /* fast clock */
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
692 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
693 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
694 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
695 clock.p = clock.p1 * clock.p2;
696 /* based on hardware requirement, prefer bigger m1,m2 values */
697 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
698 unsigned int ppm, diff;
699
700 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
701 refclk * clock.m1);
702
703 vlv_clock(refclk, &clock);
704
705 if (!intel_PLL_is_valid(dev, limit,
706 &clock))
707 continue;
708
709 diff = abs(clock.dot - target);
710 ppm = div_u64(1000000ULL * diff, target);
711
712 if (ppm < 100 && clock.p > best_clock->p) {
713 bestppm = 0;
714 *best_clock = clock;
715 found = true;
716 }
717
718 if (bestppm >= 10 && ppm < bestppm - 10) {
719 bestppm = ppm;
720 *best_clock = clock;
721 found = true;
722 }
723 }
724 }
725 }
726 }
727
728 return found;
729 }
730
731 bool intel_crtc_active(struct drm_crtc *crtc)
732 {
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734
735 /* Be paranoid as we can arrive here with only partial
736 * state retrieved from the hardware during setup.
737 *
738 * We can ditch the adjusted_mode.crtc_clock check as soon
739 * as Haswell has gained clock readout/fastboot support.
740 *
741 * We can ditch the crtc->fb check as soon as we can
742 * properly reconstruct framebuffers.
743 */
744 return intel_crtc->active && crtc->fb &&
745 intel_crtc->config.adjusted_mode.crtc_clock;
746 }
747
748 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
749 enum pipe pipe)
750 {
751 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
753
754 return intel_crtc->config.cpu_transcoder;
755 }
756
757 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
758 {
759 struct drm_i915_private *dev_priv = dev->dev_private;
760 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
761
762 frame = I915_READ(frame_reg);
763
764 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
765 DRM_DEBUG_KMS("vblank wait timed out\n");
766 }
767
768 /**
769 * intel_wait_for_vblank - wait for vblank on a given pipe
770 * @dev: drm device
771 * @pipe: pipe to wait for
772 *
773 * Wait for vblank to occur on a given pipe. Needed for various bits of
774 * mode setting code.
775 */
776 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
777 {
778 struct drm_i915_private *dev_priv = dev->dev_private;
779 int pipestat_reg = PIPESTAT(pipe);
780
781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
782 g4x_wait_for_vblank(dev, pipe);
783 return;
784 }
785
786 /* Clear existing vblank status. Note this will clear any other
787 * sticky status fields as well.
788 *
789 * This races with i915_driver_irq_handler() with the result
790 * that either function could miss a vblank event. Here it is not
791 * fatal, as we will either wait upon the next vblank interrupt or
792 * timeout. Generally speaking intel_wait_for_vblank() is only
793 * called during modeset at which time the GPU should be idle and
794 * should *not* be performing page flips and thus not waiting on
795 * vblanks...
796 * Currently, the result of us stealing a vblank from the irq
797 * handler is that a single frame will be skipped during swapbuffers.
798 */
799 I915_WRITE(pipestat_reg,
800 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
801
802 /* Wait for vblank interrupt bit to set */
803 if (wait_for(I915_READ(pipestat_reg) &
804 PIPE_VBLANK_INTERRUPT_STATUS,
805 50))
806 DRM_DEBUG_KMS("vblank wait timed out\n");
807 }
808
809 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
810 {
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 u32 reg = PIPEDSL(pipe);
813 u32 line1, line2;
814 u32 line_mask;
815
816 if (IS_GEN2(dev))
817 line_mask = DSL_LINEMASK_GEN2;
818 else
819 line_mask = DSL_LINEMASK_GEN3;
820
821 line1 = I915_READ(reg) & line_mask;
822 mdelay(5);
823 line2 = I915_READ(reg) & line_mask;
824
825 return line1 == line2;
826 }
827
828 /*
829 * intel_wait_for_pipe_off - wait for pipe to turn off
830 * @dev: drm device
831 * @pipe: pipe to wait for
832 *
833 * After disabling a pipe, we can't wait for vblank in the usual way,
834 * spinning on the vblank interrupt status bit, since we won't actually
835 * see an interrupt when the pipe is disabled.
836 *
837 * On Gen4 and above:
838 * wait for the pipe register state bit to turn off
839 *
840 * Otherwise:
841 * wait for the display line value to settle (it usually
842 * ends up stopping at the start of the next frame).
843 *
844 */
845 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
846 {
847 struct drm_i915_private *dev_priv = dev->dev_private;
848 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
849 pipe);
850
851 if (INTEL_INFO(dev)->gen >= 4) {
852 int reg = PIPECONF(cpu_transcoder);
853
854 /* Wait for the Pipe State to go off */
855 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
856 100))
857 WARN(1, "pipe_off wait timed out\n");
858 } else {
859 /* Wait for the display line to settle */
860 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
861 WARN(1, "pipe_off wait timed out\n");
862 }
863 }
864
865 /*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874 {
875 u32 bit;
876
877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
905 }
906
907 return I915_READ(SDEISR) & bit;
908 }
909
910 static const char *state_string(bool enabled)
911 {
912 return enabled ? "on" : "off";
913 }
914
915 /* Only for pre-ILK configs */
916 void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
918 {
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929 }
930
931 /* XXX: the dsi pll is shared between MIPI DSI ports */
932 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933 {
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945 }
946 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
949 struct intel_shared_dpll *
950 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951 {
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
954 if (crtc->config.shared_dpll < 0)
955 return NULL;
956
957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
958 }
959
960 /* For ILK+ */
961 void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
964 {
965 bool cur_state;
966 struct intel_dpll_hw_state hw_state;
967
968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
973 if (WARN (!pll,
974 "asserting DPLL %s with no DPLL\n", state_string(state)))
975 return;
976
977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
978 WARN(cur_state != state,
979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
981 }
982
983 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985 {
986 int reg;
987 u32 val;
988 bool cur_state;
989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
991
992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
995 val = I915_READ(reg);
996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005 }
1006 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011 {
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022 }
1023 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028 {
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1037 if (HAS_DDI(dev_priv->dev))
1038 return;
1039
1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043 }
1044
1045 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
1047 {
1048 int reg;
1049 u32 val;
1050 bool cur_state;
1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
1058 }
1059
1060 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062 {
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
1066 bool locked = true;
1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
1086 pipe_name(pipe));
1087 }
1088
1089 static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091 {
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105 }
1106 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
1109 void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
1111 {
1112 int reg;
1113 u32 val;
1114 bool cur_state;
1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
1117
1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
1133 pipe_name(pipe), state_string(state), state_string(cur_state));
1134 }
1135
1136 static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
1138 {
1139 int reg;
1140 u32 val;
1141 bool cur_state;
1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
1149 }
1150
1151 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
1154 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156 {
1157 struct drm_device *dev = dev_priv->dev;
1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
1169 return;
1170 }
1171
1172 /* Need to check both planes against the pipe */
1173 for_each_pipe(i) {
1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
1181 }
1182 }
1183
1184 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186 {
1187 struct drm_device *dev = dev_priv->dev;
1188 int reg, i;
1189 u32 val;
1190
1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
1201 val = I915_READ(reg);
1202 WARN((val & SPRITE_ENABLE),
1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
1207 val = I915_READ(reg);
1208 WARN((val & DVS_ENABLE),
1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1210 plane_name(pipe), pipe_name(pipe));
1211 }
1212 }
1213
1214 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215 {
1216 u32 val;
1217 bool enabled;
1218
1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228 }
1229
1230 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
1232 {
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
1237 reg = PCH_TRANSCONF(pipe);
1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
1243 }
1244
1245 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
1247 {
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261 }
1262
1263 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265 {
1266 if ((val & SDVO_ENABLE) == 0)
1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1271 return false;
1272 } else {
1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1274 return false;
1275 }
1276 return true;
1277 }
1278
1279 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281 {
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293 }
1294
1295 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297 {
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308 }
1309
1310 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe, int reg, u32 port_sel)
1312 {
1313 u32 val = I915_READ(reg);
1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1316 reg, pipe_name(pipe));
1317
1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
1320 "IBX PCH dp port still using transcoder B\n");
1321 }
1322
1323 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325 {
1326 u32 val = I915_READ(reg);
1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1329 reg, pipe_name(pipe));
1330
1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1332 && (val & SDVO_PIPE_B_SELECT),
1333 "IBX PCH hdmi port still using transcoder B\n");
1334 }
1335
1336 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338 {
1339 int reg;
1340 u32 val;
1341
1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
1350 pipe_name(pipe));
1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1356 pipe_name(pipe));
1357
1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1361 }
1362
1363 static void intel_init_dpio(struct drm_device *dev)
1364 {
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367 if (!IS_VALLEYVIEW(dev))
1368 return;
1369
1370 /* Enable the CRI clock source so we can get at the display */
1371 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
1372 DPLL_INTEGRATED_CRI_CLK_VLV);
1373
1374 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1375 }
1376
1377 static void intel_reset_dpio(struct drm_device *dev)
1378 {
1379 struct drm_i915_private *dev_priv = dev->dev_private;
1380
1381 if (!IS_VALLEYVIEW(dev))
1382 return;
1383
1384 /*
1385 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1386 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1387 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1388 * b. The other bits such as sfr settings / modesel may all be set
1389 * to 0.
1390 *
1391 * This should only be done on init and resume from S3 with both
1392 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1393 */
1394 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1395 }
1396
1397 static void vlv_enable_pll(struct intel_crtc *crtc)
1398 {
1399 struct drm_device *dev = crtc->base.dev;
1400 struct drm_i915_private *dev_priv = dev->dev_private;
1401 int reg = DPLL(crtc->pipe);
1402 u32 dpll = crtc->config.dpll_hw_state.dpll;
1403
1404 assert_pipe_disabled(dev_priv, crtc->pipe);
1405
1406 /* No really, not for ILK+ */
1407 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1408
1409 /* PLL is protected by panel, make sure we can write it */
1410 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1411 assert_panel_unlocked(dev_priv, crtc->pipe);
1412
1413 I915_WRITE(reg, dpll);
1414 POSTING_READ(reg);
1415 udelay(150);
1416
1417 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1418 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1419
1420 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1421 POSTING_READ(DPLL_MD(crtc->pipe));
1422
1423 /* We do this three times for luck */
1424 I915_WRITE(reg, dpll);
1425 POSTING_READ(reg);
1426 udelay(150); /* wait for warmup */
1427 I915_WRITE(reg, dpll);
1428 POSTING_READ(reg);
1429 udelay(150); /* wait for warmup */
1430 I915_WRITE(reg, dpll);
1431 POSTING_READ(reg);
1432 udelay(150); /* wait for warmup */
1433 }
1434
1435 static void i9xx_enable_pll(struct intel_crtc *crtc)
1436 {
1437 struct drm_device *dev = crtc->base.dev;
1438 struct drm_i915_private *dev_priv = dev->dev_private;
1439 int reg = DPLL(crtc->pipe);
1440 u32 dpll = crtc->config.dpll_hw_state.dpll;
1441
1442 assert_pipe_disabled(dev_priv, crtc->pipe);
1443
1444 /* No really, not for ILK+ */
1445 BUG_ON(dev_priv->info->gen >= 5);
1446
1447 /* PLL is protected by panel, make sure we can write it */
1448 if (IS_MOBILE(dev) && !IS_I830(dev))
1449 assert_panel_unlocked(dev_priv, crtc->pipe);
1450
1451 I915_WRITE(reg, dpll);
1452
1453 /* Wait for the clocks to stabilize. */
1454 POSTING_READ(reg);
1455 udelay(150);
1456
1457 if (INTEL_INFO(dev)->gen >= 4) {
1458 I915_WRITE(DPLL_MD(crtc->pipe),
1459 crtc->config.dpll_hw_state.dpll_md);
1460 } else {
1461 /* The pixel multiplier can only be updated once the
1462 * DPLL is enabled and the clocks are stable.
1463 *
1464 * So write it again.
1465 */
1466 I915_WRITE(reg, dpll);
1467 }
1468
1469 /* We do this three times for luck */
1470 I915_WRITE(reg, dpll);
1471 POSTING_READ(reg);
1472 udelay(150); /* wait for warmup */
1473 I915_WRITE(reg, dpll);
1474 POSTING_READ(reg);
1475 udelay(150); /* wait for warmup */
1476 I915_WRITE(reg, dpll);
1477 POSTING_READ(reg);
1478 udelay(150); /* wait for warmup */
1479 }
1480
1481 /**
1482 * i9xx_disable_pll - disable a PLL
1483 * @dev_priv: i915 private structure
1484 * @pipe: pipe PLL to disable
1485 *
1486 * Disable the PLL for @pipe, making sure the pipe is off first.
1487 *
1488 * Note! This is for pre-ILK only.
1489 */
1490 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1491 {
1492 /* Don't disable pipe A or pipe A PLLs if needed */
1493 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1494 return;
1495
1496 /* Make sure the pipe isn't still relying on us */
1497 assert_pipe_disabled(dev_priv, pipe);
1498
1499 I915_WRITE(DPLL(pipe), 0);
1500 POSTING_READ(DPLL(pipe));
1501 }
1502
1503 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1504 {
1505 u32 val = 0;
1506
1507 /* Make sure the pipe isn't still relying on us */
1508 assert_pipe_disabled(dev_priv, pipe);
1509
1510 /* Leave integrated clock source enabled */
1511 if (pipe == PIPE_B)
1512 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1513 I915_WRITE(DPLL(pipe), val);
1514 POSTING_READ(DPLL(pipe));
1515 }
1516
1517 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1518 struct intel_digital_port *dport)
1519 {
1520 u32 port_mask;
1521
1522 switch (dport->port) {
1523 case PORT_B:
1524 port_mask = DPLL_PORTB_READY_MASK;
1525 break;
1526 case PORT_C:
1527 port_mask = DPLL_PORTC_READY_MASK;
1528 break;
1529 default:
1530 BUG();
1531 }
1532
1533 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1534 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1535 port_name(dport->port), I915_READ(DPLL(0)));
1536 }
1537
1538 /**
1539 * ironlake_enable_shared_dpll - enable PCH PLL
1540 * @dev_priv: i915 private structure
1541 * @pipe: pipe PLL to enable
1542 *
1543 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1544 * drives the transcoder clock.
1545 */
1546 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1547 {
1548 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1549 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1550
1551 /* PCH PLLs only available on ILK, SNB and IVB */
1552 BUG_ON(dev_priv->info->gen < 5);
1553 if (WARN_ON(pll == NULL))
1554 return;
1555
1556 if (WARN_ON(pll->refcount == 0))
1557 return;
1558
1559 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1560 pll->name, pll->active, pll->on,
1561 crtc->base.base.id);
1562
1563 if (pll->active++) {
1564 WARN_ON(!pll->on);
1565 assert_shared_dpll_enabled(dev_priv, pll);
1566 return;
1567 }
1568 WARN_ON(pll->on);
1569
1570 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1571 pll->enable(dev_priv, pll);
1572 pll->on = true;
1573 }
1574
1575 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1576 {
1577 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1578 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1579
1580 /* PCH only available on ILK+ */
1581 BUG_ON(dev_priv->info->gen < 5);
1582 if (WARN_ON(pll == NULL))
1583 return;
1584
1585 if (WARN_ON(pll->refcount == 0))
1586 return;
1587
1588 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1589 pll->name, pll->active, pll->on,
1590 crtc->base.base.id);
1591
1592 if (WARN_ON(pll->active == 0)) {
1593 assert_shared_dpll_disabled(dev_priv, pll);
1594 return;
1595 }
1596
1597 assert_shared_dpll_enabled(dev_priv, pll);
1598 WARN_ON(!pll->on);
1599 if (--pll->active)
1600 return;
1601
1602 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1603 pll->disable(dev_priv, pll);
1604 pll->on = false;
1605 }
1606
1607 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1608 enum pipe pipe)
1609 {
1610 struct drm_device *dev = dev_priv->dev;
1611 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1613 uint32_t reg, val, pipeconf_val;
1614
1615 /* PCH only available on ILK+ */
1616 BUG_ON(dev_priv->info->gen < 5);
1617
1618 /* Make sure PCH DPLL is enabled */
1619 assert_shared_dpll_enabled(dev_priv,
1620 intel_crtc_to_shared_dpll(intel_crtc));
1621
1622 /* FDI must be feeding us bits for PCH ports */
1623 assert_fdi_tx_enabled(dev_priv, pipe);
1624 assert_fdi_rx_enabled(dev_priv, pipe);
1625
1626 if (HAS_PCH_CPT(dev)) {
1627 /* Workaround: Set the timing override bit before enabling the
1628 * pch transcoder. */
1629 reg = TRANS_CHICKEN2(pipe);
1630 val = I915_READ(reg);
1631 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1632 I915_WRITE(reg, val);
1633 }
1634
1635 reg = PCH_TRANSCONF(pipe);
1636 val = I915_READ(reg);
1637 pipeconf_val = I915_READ(PIPECONF(pipe));
1638
1639 if (HAS_PCH_IBX(dev_priv->dev)) {
1640 /*
1641 * make the BPC in transcoder be consistent with
1642 * that in pipeconf reg.
1643 */
1644 val &= ~PIPECONF_BPC_MASK;
1645 val |= pipeconf_val & PIPECONF_BPC_MASK;
1646 }
1647
1648 val &= ~TRANS_INTERLACE_MASK;
1649 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1650 if (HAS_PCH_IBX(dev_priv->dev) &&
1651 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1652 val |= TRANS_LEGACY_INTERLACED_ILK;
1653 else
1654 val |= TRANS_INTERLACED;
1655 else
1656 val |= TRANS_PROGRESSIVE;
1657
1658 I915_WRITE(reg, val | TRANS_ENABLE);
1659 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1660 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1661 }
1662
1663 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1664 enum transcoder cpu_transcoder)
1665 {
1666 u32 val, pipeconf_val;
1667
1668 /* PCH only available on ILK+ */
1669 BUG_ON(dev_priv->info->gen < 5);
1670
1671 /* FDI must be feeding us bits for PCH ports */
1672 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1673 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1674
1675 /* Workaround: set timing override bit. */
1676 val = I915_READ(_TRANSA_CHICKEN2);
1677 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1678 I915_WRITE(_TRANSA_CHICKEN2, val);
1679
1680 val = TRANS_ENABLE;
1681 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1682
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1684 PIPECONF_INTERLACED_ILK)
1685 val |= TRANS_INTERLACED;
1686 else
1687 val |= TRANS_PROGRESSIVE;
1688
1689 I915_WRITE(LPT_TRANSCONF, val);
1690 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1691 DRM_ERROR("Failed to enable PCH transcoder\n");
1692 }
1693
1694 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1695 enum pipe pipe)
1696 {
1697 struct drm_device *dev = dev_priv->dev;
1698 uint32_t reg, val;
1699
1700 /* FDI relies on the transcoder */
1701 assert_fdi_tx_disabled(dev_priv, pipe);
1702 assert_fdi_rx_disabled(dev_priv, pipe);
1703
1704 /* Ports must be off as well */
1705 assert_pch_ports_disabled(dev_priv, pipe);
1706
1707 reg = PCH_TRANSCONF(pipe);
1708 val = I915_READ(reg);
1709 val &= ~TRANS_ENABLE;
1710 I915_WRITE(reg, val);
1711 /* wait for PCH transcoder off, transcoder state */
1712 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1713 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1714
1715 if (!HAS_PCH_IBX(dev)) {
1716 /* Workaround: Clear the timing override chicken bit again. */
1717 reg = TRANS_CHICKEN2(pipe);
1718 val = I915_READ(reg);
1719 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1720 I915_WRITE(reg, val);
1721 }
1722 }
1723
1724 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1725 {
1726 u32 val;
1727
1728 val = I915_READ(LPT_TRANSCONF);
1729 val &= ~TRANS_ENABLE;
1730 I915_WRITE(LPT_TRANSCONF, val);
1731 /* wait for PCH transcoder off, transcoder state */
1732 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1733 DRM_ERROR("Failed to disable PCH transcoder\n");
1734
1735 /* Workaround: clear timing override bit. */
1736 val = I915_READ(_TRANSA_CHICKEN2);
1737 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1738 I915_WRITE(_TRANSA_CHICKEN2, val);
1739 }
1740
1741 /**
1742 * intel_enable_pipe - enable a pipe, asserting requirements
1743 * @dev_priv: i915 private structure
1744 * @pipe: pipe to enable
1745 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1746 *
1747 * Enable @pipe, making sure that various hardware specific requirements
1748 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1749 *
1750 * @pipe should be %PIPE_A or %PIPE_B.
1751 *
1752 * Will wait until the pipe is actually running (i.e. first vblank) before
1753 * returning.
1754 */
1755 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1756 bool pch_port, bool dsi)
1757 {
1758 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1759 pipe);
1760 enum pipe pch_transcoder;
1761 int reg;
1762 u32 val;
1763
1764 assert_planes_disabled(dev_priv, pipe);
1765 assert_cursor_disabled(dev_priv, pipe);
1766 assert_sprites_disabled(dev_priv, pipe);
1767
1768 if (HAS_PCH_LPT(dev_priv->dev))
1769 pch_transcoder = TRANSCODER_A;
1770 else
1771 pch_transcoder = pipe;
1772
1773 /*
1774 * A pipe without a PLL won't actually be able to drive bits from
1775 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1776 * need the check.
1777 */
1778 if (!HAS_PCH_SPLIT(dev_priv->dev))
1779 if (dsi)
1780 assert_dsi_pll_enabled(dev_priv);
1781 else
1782 assert_pll_enabled(dev_priv, pipe);
1783 else {
1784 if (pch_port) {
1785 /* if driving the PCH, we need FDI enabled */
1786 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1787 assert_fdi_tx_pll_enabled(dev_priv,
1788 (enum pipe) cpu_transcoder);
1789 }
1790 /* FIXME: assert CPU port conditions for SNB+ */
1791 }
1792
1793 reg = PIPECONF(cpu_transcoder);
1794 val = I915_READ(reg);
1795 if (val & PIPECONF_ENABLE)
1796 return;
1797
1798 I915_WRITE(reg, val | PIPECONF_ENABLE);
1799 intel_wait_for_vblank(dev_priv->dev, pipe);
1800 }
1801
1802 /**
1803 * intel_disable_pipe - disable a pipe, asserting requirements
1804 * @dev_priv: i915 private structure
1805 * @pipe: pipe to disable
1806 *
1807 * Disable @pipe, making sure that various hardware specific requirements
1808 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1809 *
1810 * @pipe should be %PIPE_A or %PIPE_B.
1811 *
1812 * Will wait until the pipe has shut down before returning.
1813 */
1814 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1815 enum pipe pipe)
1816 {
1817 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1818 pipe);
1819 int reg;
1820 u32 val;
1821
1822 /*
1823 * Make sure planes won't keep trying to pump pixels to us,
1824 * or we might hang the display.
1825 */
1826 assert_planes_disabled(dev_priv, pipe);
1827 assert_cursor_disabled(dev_priv, pipe);
1828 assert_sprites_disabled(dev_priv, pipe);
1829
1830 /* Don't disable pipe A or pipe A PLLs if needed */
1831 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1832 return;
1833
1834 reg = PIPECONF(cpu_transcoder);
1835 val = I915_READ(reg);
1836 if ((val & PIPECONF_ENABLE) == 0)
1837 return;
1838
1839 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1840 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1841 }
1842
1843 /*
1844 * Plane regs are double buffered, going from enabled->disabled needs a
1845 * trigger in order to latch. The display address reg provides this.
1846 */
1847 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane)
1849 {
1850 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1851
1852 I915_WRITE(reg, I915_READ(reg));
1853 POSTING_READ(reg);
1854 }
1855
1856 /**
1857 * intel_enable_primary_plane - enable the primary plane on a given pipe
1858 * @dev_priv: i915 private structure
1859 * @plane: plane to enable
1860 * @pipe: pipe being fed
1861 *
1862 * Enable @plane on @pipe, making sure that @pipe is running first.
1863 */
1864 static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1865 enum plane plane, enum pipe pipe)
1866 {
1867 struct intel_crtc *intel_crtc =
1868 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1869 int reg;
1870 u32 val;
1871
1872 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1873 assert_pipe_enabled(dev_priv, pipe);
1874
1875 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
1876
1877 intel_crtc->primary_enabled = true;
1878
1879 reg = DSPCNTR(plane);
1880 val = I915_READ(reg);
1881 if (val & DISPLAY_PLANE_ENABLE)
1882 return;
1883
1884 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1885 intel_flush_primary_plane(dev_priv, plane);
1886 intel_wait_for_vblank(dev_priv->dev, pipe);
1887 }
1888
1889 /**
1890 * intel_disable_primary_plane - disable the primary plane
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to disable
1893 * @pipe: pipe consuming the data
1894 *
1895 * Disable @plane; should be an independent operation.
1896 */
1897 static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899 {
1900 struct intel_crtc *intel_crtc =
1901 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
1902 int reg;
1903 u32 val;
1904
1905 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
1906
1907 intel_crtc->primary_enabled = false;
1908
1909 reg = DSPCNTR(plane);
1910 val = I915_READ(reg);
1911 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1912 return;
1913
1914 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1915 intel_flush_primary_plane(dev_priv, plane);
1916 intel_wait_for_vblank(dev_priv->dev, pipe);
1917 }
1918
1919 static bool need_vtd_wa(struct drm_device *dev)
1920 {
1921 #ifdef CONFIG_INTEL_IOMMU
1922 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1923 return true;
1924 #endif
1925 return false;
1926 }
1927
1928 int
1929 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1930 struct drm_i915_gem_object *obj,
1931 struct intel_ring_buffer *pipelined)
1932 {
1933 struct drm_i915_private *dev_priv = dev->dev_private;
1934 u32 alignment;
1935 int ret;
1936
1937 switch (obj->tiling_mode) {
1938 case I915_TILING_NONE:
1939 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1940 alignment = 128 * 1024;
1941 else if (INTEL_INFO(dev)->gen >= 4)
1942 alignment = 4 * 1024;
1943 else
1944 alignment = 64 * 1024;
1945 break;
1946 case I915_TILING_X:
1947 /* pin() will align the object as required by fence */
1948 alignment = 0;
1949 break;
1950 case I915_TILING_Y:
1951 WARN(1, "Y tiled bo slipped through, driver bug!\n");
1952 return -EINVAL;
1953 default:
1954 BUG();
1955 }
1956
1957 /* Note that the w/a also requires 64 PTE of padding following the
1958 * bo. We currently fill all unused PTE with the shadow page and so
1959 * we should always have valid PTE following the scanout preventing
1960 * the VT-d warning.
1961 */
1962 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1963 alignment = 256 * 1024;
1964
1965 dev_priv->mm.interruptible = false;
1966 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1967 if (ret)
1968 goto err_interruptible;
1969
1970 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1971 * fence, whereas 965+ only requires a fence if using
1972 * framebuffer compression. For simplicity, we always install
1973 * a fence as the cost is not that onerous.
1974 */
1975 ret = i915_gem_object_get_fence(obj);
1976 if (ret)
1977 goto err_unpin;
1978
1979 i915_gem_object_pin_fence(obj);
1980
1981 dev_priv->mm.interruptible = true;
1982 return 0;
1983
1984 err_unpin:
1985 i915_gem_object_unpin_from_display_plane(obj);
1986 err_interruptible:
1987 dev_priv->mm.interruptible = true;
1988 return ret;
1989 }
1990
1991 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1992 {
1993 i915_gem_object_unpin_fence(obj);
1994 i915_gem_object_unpin_from_display_plane(obj);
1995 }
1996
1997 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1998 * is assumed to be a power-of-two. */
1999 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2000 unsigned int tiling_mode,
2001 unsigned int cpp,
2002 unsigned int pitch)
2003 {
2004 if (tiling_mode != I915_TILING_NONE) {
2005 unsigned int tile_rows, tiles;
2006
2007 tile_rows = *y / 8;
2008 *y %= 8;
2009
2010 tiles = *x / (512/cpp);
2011 *x %= 512/cpp;
2012
2013 return tile_rows * pitch * 8 + tiles * 4096;
2014 } else {
2015 unsigned int offset;
2016
2017 offset = *y * pitch + *x * cpp;
2018 *y = 0;
2019 *x = (offset & 4095) / cpp;
2020 return offset & -4096;
2021 }
2022 }
2023
2024 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2025 int x, int y)
2026 {
2027 struct drm_device *dev = crtc->dev;
2028 struct drm_i915_private *dev_priv = dev->dev_private;
2029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2030 struct intel_framebuffer *intel_fb;
2031 struct drm_i915_gem_object *obj;
2032 int plane = intel_crtc->plane;
2033 unsigned long linear_offset;
2034 u32 dspcntr;
2035 u32 reg;
2036
2037 switch (plane) {
2038 case 0:
2039 case 1:
2040 break;
2041 default:
2042 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2043 return -EINVAL;
2044 }
2045
2046 intel_fb = to_intel_framebuffer(fb);
2047 obj = intel_fb->obj;
2048
2049 reg = DSPCNTR(plane);
2050 dspcntr = I915_READ(reg);
2051 /* Mask out pixel format bits in case we change it */
2052 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2053 switch (fb->pixel_format) {
2054 case DRM_FORMAT_C8:
2055 dspcntr |= DISPPLANE_8BPP;
2056 break;
2057 case DRM_FORMAT_XRGB1555:
2058 case DRM_FORMAT_ARGB1555:
2059 dspcntr |= DISPPLANE_BGRX555;
2060 break;
2061 case DRM_FORMAT_RGB565:
2062 dspcntr |= DISPPLANE_BGRX565;
2063 break;
2064 case DRM_FORMAT_XRGB8888:
2065 case DRM_FORMAT_ARGB8888:
2066 dspcntr |= DISPPLANE_BGRX888;
2067 break;
2068 case DRM_FORMAT_XBGR8888:
2069 case DRM_FORMAT_ABGR8888:
2070 dspcntr |= DISPPLANE_RGBX888;
2071 break;
2072 case DRM_FORMAT_XRGB2101010:
2073 case DRM_FORMAT_ARGB2101010:
2074 dspcntr |= DISPPLANE_BGRX101010;
2075 break;
2076 case DRM_FORMAT_XBGR2101010:
2077 case DRM_FORMAT_ABGR2101010:
2078 dspcntr |= DISPPLANE_RGBX101010;
2079 break;
2080 default:
2081 BUG();
2082 }
2083
2084 if (INTEL_INFO(dev)->gen >= 4) {
2085 if (obj->tiling_mode != I915_TILING_NONE)
2086 dspcntr |= DISPPLANE_TILED;
2087 else
2088 dspcntr &= ~DISPPLANE_TILED;
2089 }
2090
2091 if (IS_G4X(dev))
2092 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2093
2094 I915_WRITE(reg, dspcntr);
2095
2096 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2097
2098 if (INTEL_INFO(dev)->gen >= 4) {
2099 intel_crtc->dspaddr_offset =
2100 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2101 fb->bits_per_pixel / 8,
2102 fb->pitches[0]);
2103 linear_offset -= intel_crtc->dspaddr_offset;
2104 } else {
2105 intel_crtc->dspaddr_offset = linear_offset;
2106 }
2107
2108 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2109 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2110 fb->pitches[0]);
2111 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2112 if (INTEL_INFO(dev)->gen >= 4) {
2113 I915_MODIFY_DISPBASE(DSPSURF(plane),
2114 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2115 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2116 I915_WRITE(DSPLINOFF(plane), linear_offset);
2117 } else
2118 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2119 POSTING_READ(reg);
2120
2121 return 0;
2122 }
2123
2124 static int ironlake_update_plane(struct drm_crtc *crtc,
2125 struct drm_framebuffer *fb, int x, int y)
2126 {
2127 struct drm_device *dev = crtc->dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130 struct intel_framebuffer *intel_fb;
2131 struct drm_i915_gem_object *obj;
2132 int plane = intel_crtc->plane;
2133 unsigned long linear_offset;
2134 u32 dspcntr;
2135 u32 reg;
2136
2137 switch (plane) {
2138 case 0:
2139 case 1:
2140 case 2:
2141 break;
2142 default:
2143 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2144 return -EINVAL;
2145 }
2146
2147 intel_fb = to_intel_framebuffer(fb);
2148 obj = intel_fb->obj;
2149
2150 reg = DSPCNTR(plane);
2151 dspcntr = I915_READ(reg);
2152 /* Mask out pixel format bits in case we change it */
2153 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2154 switch (fb->pixel_format) {
2155 case DRM_FORMAT_C8:
2156 dspcntr |= DISPPLANE_8BPP;
2157 break;
2158 case DRM_FORMAT_RGB565:
2159 dspcntr |= DISPPLANE_BGRX565;
2160 break;
2161 case DRM_FORMAT_XRGB8888:
2162 case DRM_FORMAT_ARGB8888:
2163 dspcntr |= DISPPLANE_BGRX888;
2164 break;
2165 case DRM_FORMAT_XBGR8888:
2166 case DRM_FORMAT_ABGR8888:
2167 dspcntr |= DISPPLANE_RGBX888;
2168 break;
2169 case DRM_FORMAT_XRGB2101010:
2170 case DRM_FORMAT_ARGB2101010:
2171 dspcntr |= DISPPLANE_BGRX101010;
2172 break;
2173 case DRM_FORMAT_XBGR2101010:
2174 case DRM_FORMAT_ABGR2101010:
2175 dspcntr |= DISPPLANE_RGBX101010;
2176 break;
2177 default:
2178 BUG();
2179 }
2180
2181 if (obj->tiling_mode != I915_TILING_NONE)
2182 dspcntr |= DISPPLANE_TILED;
2183 else
2184 dspcntr &= ~DISPPLANE_TILED;
2185
2186 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2187 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2188 else
2189 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2190
2191 I915_WRITE(reg, dspcntr);
2192
2193 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2194 intel_crtc->dspaddr_offset =
2195 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2196 fb->bits_per_pixel / 8,
2197 fb->pitches[0]);
2198 linear_offset -= intel_crtc->dspaddr_offset;
2199
2200 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2201 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2202 fb->pitches[0]);
2203 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2204 I915_MODIFY_DISPBASE(DSPSURF(plane),
2205 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2206 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2207 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2208 } else {
2209 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2210 I915_WRITE(DSPLINOFF(plane), linear_offset);
2211 }
2212 POSTING_READ(reg);
2213
2214 return 0;
2215 }
2216
2217 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2218 static int
2219 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2220 int x, int y, enum mode_set_atomic state)
2221 {
2222 struct drm_device *dev = crtc->dev;
2223 struct drm_i915_private *dev_priv = dev->dev_private;
2224
2225 if (dev_priv->display.disable_fbc)
2226 dev_priv->display.disable_fbc(dev);
2227 intel_increase_pllclock(crtc);
2228
2229 return dev_priv->display.update_plane(crtc, fb, x, y);
2230 }
2231
2232 void intel_display_handle_reset(struct drm_device *dev)
2233 {
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct drm_crtc *crtc;
2236
2237 /*
2238 * Flips in the rings have been nuked by the reset,
2239 * so complete all pending flips so that user space
2240 * will get its events and not get stuck.
2241 *
2242 * Also update the base address of all primary
2243 * planes to the the last fb to make sure we're
2244 * showing the correct fb after a reset.
2245 *
2246 * Need to make two loops over the crtcs so that we
2247 * don't try to grab a crtc mutex before the
2248 * pending_flip_queue really got woken up.
2249 */
2250
2251 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2253 enum plane plane = intel_crtc->plane;
2254
2255 intel_prepare_page_flip(dev, plane);
2256 intel_finish_page_flip_plane(dev, plane);
2257 }
2258
2259 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2260 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2261
2262 mutex_lock(&crtc->mutex);
2263 /*
2264 * FIXME: Once we have proper support for primary planes (and
2265 * disabling them without disabling the entire crtc) allow again
2266 * a NULL crtc->fb.
2267 */
2268 if (intel_crtc->active && crtc->fb)
2269 dev_priv->display.update_plane(crtc, crtc->fb,
2270 crtc->x, crtc->y);
2271 mutex_unlock(&crtc->mutex);
2272 }
2273 }
2274
2275 static int
2276 intel_finish_fb(struct drm_framebuffer *old_fb)
2277 {
2278 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2279 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2280 bool was_interruptible = dev_priv->mm.interruptible;
2281 int ret;
2282
2283 /* Big Hammer, we also need to ensure that any pending
2284 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2285 * current scanout is retired before unpinning the old
2286 * framebuffer.
2287 *
2288 * This should only fail upon a hung GPU, in which case we
2289 * can safely continue.
2290 */
2291 dev_priv->mm.interruptible = false;
2292 ret = i915_gem_object_finish_gpu(obj);
2293 dev_priv->mm.interruptible = was_interruptible;
2294
2295 return ret;
2296 }
2297
2298 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2299 {
2300 struct drm_device *dev = crtc->dev;
2301 struct drm_i915_master_private *master_priv;
2302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2303
2304 if (!dev->primary->master)
2305 return;
2306
2307 master_priv = dev->primary->master->driver_priv;
2308 if (!master_priv->sarea_priv)
2309 return;
2310
2311 switch (intel_crtc->pipe) {
2312 case 0:
2313 master_priv->sarea_priv->pipeA_x = x;
2314 master_priv->sarea_priv->pipeA_y = y;
2315 break;
2316 case 1:
2317 master_priv->sarea_priv->pipeB_x = x;
2318 master_priv->sarea_priv->pipeB_y = y;
2319 break;
2320 default:
2321 break;
2322 }
2323 }
2324
2325 static int
2326 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2327 struct drm_framebuffer *fb)
2328 {
2329 struct drm_device *dev = crtc->dev;
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2332 struct drm_framebuffer *old_fb;
2333 int ret;
2334
2335 /* no fb bound */
2336 if (!fb) {
2337 DRM_ERROR("No FB bound\n");
2338 return 0;
2339 }
2340
2341 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2342 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2343 plane_name(intel_crtc->plane),
2344 INTEL_INFO(dev)->num_pipes);
2345 return -EINVAL;
2346 }
2347
2348 mutex_lock(&dev->struct_mutex);
2349 ret = intel_pin_and_fence_fb_obj(dev,
2350 to_intel_framebuffer(fb)->obj,
2351 NULL);
2352 if (ret != 0) {
2353 mutex_unlock(&dev->struct_mutex);
2354 DRM_ERROR("pin & fence failed\n");
2355 return ret;
2356 }
2357
2358 /*
2359 * Update pipe size and adjust fitter if needed: the reason for this is
2360 * that in compute_mode_changes we check the native mode (not the pfit
2361 * mode) to see if we can flip rather than do a full mode set. In the
2362 * fastboot case, we'll flip, but if we don't update the pipesrc and
2363 * pfit state, we'll end up with a big fb scanned out into the wrong
2364 * sized surface.
2365 *
2366 * To fix this properly, we need to hoist the checks up into
2367 * compute_mode_changes (or above), check the actual pfit state and
2368 * whether the platform allows pfit disable with pipe active, and only
2369 * then update the pipesrc and pfit state, even on the flip path.
2370 */
2371 if (i915_fastboot) {
2372 const struct drm_display_mode *adjusted_mode =
2373 &intel_crtc->config.adjusted_mode;
2374
2375 I915_WRITE(PIPESRC(intel_crtc->pipe),
2376 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2377 (adjusted_mode->crtc_vdisplay - 1));
2378 if (!intel_crtc->config.pch_pfit.enabled &&
2379 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2380 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2381 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2382 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2383 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2384 }
2385 }
2386
2387 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2388 if (ret) {
2389 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2390 mutex_unlock(&dev->struct_mutex);
2391 DRM_ERROR("failed to update base address\n");
2392 return ret;
2393 }
2394
2395 old_fb = crtc->fb;
2396 crtc->fb = fb;
2397 crtc->x = x;
2398 crtc->y = y;
2399
2400 if (old_fb) {
2401 if (intel_crtc->active && old_fb != fb)
2402 intel_wait_for_vblank(dev, intel_crtc->pipe);
2403 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2404 }
2405
2406 intel_update_fbc(dev);
2407 intel_edp_psr_update(dev);
2408 mutex_unlock(&dev->struct_mutex);
2409
2410 intel_crtc_update_sarea_pos(crtc, x, y);
2411
2412 return 0;
2413 }
2414
2415 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2416 {
2417 struct drm_device *dev = crtc->dev;
2418 struct drm_i915_private *dev_priv = dev->dev_private;
2419 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2420 int pipe = intel_crtc->pipe;
2421 u32 reg, temp;
2422
2423 /* enable normal train */
2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
2426 if (IS_IVYBRIDGE(dev)) {
2427 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2428 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2429 } else {
2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2432 }
2433 I915_WRITE(reg, temp);
2434
2435 reg = FDI_RX_CTL(pipe);
2436 temp = I915_READ(reg);
2437 if (HAS_PCH_CPT(dev)) {
2438 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2439 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2440 } else {
2441 temp &= ~FDI_LINK_TRAIN_NONE;
2442 temp |= FDI_LINK_TRAIN_NONE;
2443 }
2444 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2445
2446 /* wait one idle pattern time */
2447 POSTING_READ(reg);
2448 udelay(1000);
2449
2450 /* IVB wants error correction enabled */
2451 if (IS_IVYBRIDGE(dev))
2452 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2453 FDI_FE_ERRC_ENABLE);
2454 }
2455
2456 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2457 {
2458 return crtc->base.enabled && crtc->active &&
2459 crtc->config.has_pch_encoder;
2460 }
2461
2462 static void ivb_modeset_global_resources(struct drm_device *dev)
2463 {
2464 struct drm_i915_private *dev_priv = dev->dev_private;
2465 struct intel_crtc *pipe_B_crtc =
2466 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2467 struct intel_crtc *pipe_C_crtc =
2468 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2469 uint32_t temp;
2470
2471 /*
2472 * When everything is off disable fdi C so that we could enable fdi B
2473 * with all lanes. Note that we don't care about enabled pipes without
2474 * an enabled pch encoder.
2475 */
2476 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2477 !pipe_has_enabled_pch(pipe_C_crtc)) {
2478 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2480
2481 temp = I915_READ(SOUTH_CHICKEN1);
2482 temp &= ~FDI_BC_BIFURCATION_SELECT;
2483 DRM_DEBUG_KMS("disabling fdi C rx\n");
2484 I915_WRITE(SOUTH_CHICKEN1, temp);
2485 }
2486 }
2487
2488 /* The FDI link training functions for ILK/Ibexpeak. */
2489 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2490 {
2491 struct drm_device *dev = crtc->dev;
2492 struct drm_i915_private *dev_priv = dev->dev_private;
2493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2494 int pipe = intel_crtc->pipe;
2495 int plane = intel_crtc->plane;
2496 u32 reg, temp, tries;
2497
2498 /* FDI needs bits from pipe & plane first */
2499 assert_pipe_enabled(dev_priv, pipe);
2500 assert_plane_enabled(dev_priv, plane);
2501
2502 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2503 for train result */
2504 reg = FDI_RX_IMR(pipe);
2505 temp = I915_READ(reg);
2506 temp &= ~FDI_RX_SYMBOL_LOCK;
2507 temp &= ~FDI_RX_BIT_LOCK;
2508 I915_WRITE(reg, temp);
2509 I915_READ(reg);
2510 udelay(150);
2511
2512 /* enable CPU FDI TX and PCH FDI RX */
2513 reg = FDI_TX_CTL(pipe);
2514 temp = I915_READ(reg);
2515 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2516 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2517 temp &= ~FDI_LINK_TRAIN_NONE;
2518 temp |= FDI_LINK_TRAIN_PATTERN_1;
2519 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2520
2521 reg = FDI_RX_CTL(pipe);
2522 temp = I915_READ(reg);
2523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_1;
2525 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2526
2527 POSTING_READ(reg);
2528 udelay(150);
2529
2530 /* Ironlake workaround, enable clock pointer after FDI enable*/
2531 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2532 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2533 FDI_RX_PHASE_SYNC_POINTER_EN);
2534
2535 reg = FDI_RX_IIR(pipe);
2536 for (tries = 0; tries < 5; tries++) {
2537 temp = I915_READ(reg);
2538 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2539
2540 if ((temp & FDI_RX_BIT_LOCK)) {
2541 DRM_DEBUG_KMS("FDI train 1 done.\n");
2542 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2543 break;
2544 }
2545 }
2546 if (tries == 5)
2547 DRM_ERROR("FDI train 1 fail!\n");
2548
2549 /* Train 2 */
2550 reg = FDI_TX_CTL(pipe);
2551 temp = I915_READ(reg);
2552 temp &= ~FDI_LINK_TRAIN_NONE;
2553 temp |= FDI_LINK_TRAIN_PATTERN_2;
2554 I915_WRITE(reg, temp);
2555
2556 reg = FDI_RX_CTL(pipe);
2557 temp = I915_READ(reg);
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
2560 I915_WRITE(reg, temp);
2561
2562 POSTING_READ(reg);
2563 udelay(150);
2564
2565 reg = FDI_RX_IIR(pipe);
2566 for (tries = 0; tries < 5; tries++) {
2567 temp = I915_READ(reg);
2568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2569
2570 if (temp & FDI_RX_SYMBOL_LOCK) {
2571 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2572 DRM_DEBUG_KMS("FDI train 2 done.\n");
2573 break;
2574 }
2575 }
2576 if (tries == 5)
2577 DRM_ERROR("FDI train 2 fail!\n");
2578
2579 DRM_DEBUG_KMS("FDI train done\n");
2580
2581 }
2582
2583 static const int snb_b_fdi_train_param[] = {
2584 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2585 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2586 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2587 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2588 };
2589
2590 /* The FDI link training functions for SNB/Cougarpoint. */
2591 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2592 {
2593 struct drm_device *dev = crtc->dev;
2594 struct drm_i915_private *dev_priv = dev->dev_private;
2595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2596 int pipe = intel_crtc->pipe;
2597 u32 reg, temp, i, retry;
2598
2599 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2600 for train result */
2601 reg = FDI_RX_IMR(pipe);
2602 temp = I915_READ(reg);
2603 temp &= ~FDI_RX_SYMBOL_LOCK;
2604 temp &= ~FDI_RX_BIT_LOCK;
2605 I915_WRITE(reg, temp);
2606
2607 POSTING_READ(reg);
2608 udelay(150);
2609
2610 /* enable CPU FDI TX and PCH FDI RX */
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2614 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2615 temp &= ~FDI_LINK_TRAIN_NONE;
2616 temp |= FDI_LINK_TRAIN_PATTERN_1;
2617 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2618 /* SNB-B */
2619 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2620 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2621
2622 I915_WRITE(FDI_RX_MISC(pipe),
2623 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2624
2625 reg = FDI_RX_CTL(pipe);
2626 temp = I915_READ(reg);
2627 if (HAS_PCH_CPT(dev)) {
2628 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2629 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2630 } else {
2631 temp &= ~FDI_LINK_TRAIN_NONE;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1;
2633 }
2634 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636 POSTING_READ(reg);
2637 udelay(150);
2638
2639 for (i = 0; i < 4; i++) {
2640 reg = FDI_TX_CTL(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2643 temp |= snb_b_fdi_train_param[i];
2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
2647 udelay(500);
2648
2649 for (retry = 0; retry < 5; retry++) {
2650 reg = FDI_RX_IIR(pipe);
2651 temp = I915_READ(reg);
2652 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2653 if (temp & FDI_RX_BIT_LOCK) {
2654 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2655 DRM_DEBUG_KMS("FDI train 1 done.\n");
2656 break;
2657 }
2658 udelay(50);
2659 }
2660 if (retry < 5)
2661 break;
2662 }
2663 if (i == 4)
2664 DRM_ERROR("FDI train 1 fail!\n");
2665
2666 /* Train 2 */
2667 reg = FDI_TX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_NONE;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2;
2671 if (IS_GEN6(dev)) {
2672 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673 /* SNB-B */
2674 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2675 }
2676 I915_WRITE(reg, temp);
2677
2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 if (HAS_PCH_CPT(dev)) {
2681 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2682 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2683 } else {
2684 temp &= ~FDI_LINK_TRAIN_NONE;
2685 temp |= FDI_LINK_TRAIN_PATTERN_2;
2686 }
2687 I915_WRITE(reg, temp);
2688
2689 POSTING_READ(reg);
2690 udelay(150);
2691
2692 for (i = 0; i < 4; i++) {
2693 reg = FDI_TX_CTL(pipe);
2694 temp = I915_READ(reg);
2695 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2696 temp |= snb_b_fdi_train_param[i];
2697 I915_WRITE(reg, temp);
2698
2699 POSTING_READ(reg);
2700 udelay(500);
2701
2702 for (retry = 0; retry < 5; retry++) {
2703 reg = FDI_RX_IIR(pipe);
2704 temp = I915_READ(reg);
2705 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2706 if (temp & FDI_RX_SYMBOL_LOCK) {
2707 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2708 DRM_DEBUG_KMS("FDI train 2 done.\n");
2709 break;
2710 }
2711 udelay(50);
2712 }
2713 if (retry < 5)
2714 break;
2715 }
2716 if (i == 4)
2717 DRM_ERROR("FDI train 2 fail!\n");
2718
2719 DRM_DEBUG_KMS("FDI train done.\n");
2720 }
2721
2722 /* Manual link training for Ivy Bridge A0 parts */
2723 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2724 {
2725 struct drm_device *dev = crtc->dev;
2726 struct drm_i915_private *dev_priv = dev->dev_private;
2727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2728 int pipe = intel_crtc->pipe;
2729 u32 reg, temp, i, j;
2730
2731 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2732 for train result */
2733 reg = FDI_RX_IMR(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_RX_SYMBOL_LOCK;
2736 temp &= ~FDI_RX_BIT_LOCK;
2737 I915_WRITE(reg, temp);
2738
2739 POSTING_READ(reg);
2740 udelay(150);
2741
2742 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2743 I915_READ(FDI_RX_IIR(pipe)));
2744
2745 /* Try each vswing and preemphasis setting twice before moving on */
2746 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2747 /* disable first in case we need to retry */
2748 reg = FDI_TX_CTL(pipe);
2749 temp = I915_READ(reg);
2750 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2751 temp &= ~FDI_TX_ENABLE;
2752 I915_WRITE(reg, temp);
2753
2754 reg = FDI_RX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 temp &= ~FDI_LINK_TRAIN_AUTO;
2757 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2758 temp &= ~FDI_RX_ENABLE;
2759 I915_WRITE(reg, temp);
2760
2761 /* enable CPU FDI TX and PCH FDI RX */
2762 reg = FDI_TX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2765 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2766 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2767 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2768 temp |= snb_b_fdi_train_param[j/2];
2769 temp |= FDI_COMPOSITE_SYNC;
2770 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2771
2772 I915_WRITE(FDI_RX_MISC(pipe),
2773 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2774
2775 reg = FDI_RX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2778 temp |= FDI_COMPOSITE_SYNC;
2779 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2780
2781 POSTING_READ(reg);
2782 udelay(1); /* should be 0.5us */
2783
2784 for (i = 0; i < 4; i++) {
2785 reg = FDI_RX_IIR(pipe);
2786 temp = I915_READ(reg);
2787 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2788
2789 if (temp & FDI_RX_BIT_LOCK ||
2790 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2791 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2792 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2793 i);
2794 break;
2795 }
2796 udelay(1); /* should be 0.5us */
2797 }
2798 if (i == 4) {
2799 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2800 continue;
2801 }
2802
2803 /* Train 2 */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2807 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2808 I915_WRITE(reg, temp);
2809
2810 reg = FDI_RX_CTL(pipe);
2811 temp = I915_READ(reg);
2812 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2813 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2814 I915_WRITE(reg, temp);
2815
2816 POSTING_READ(reg);
2817 udelay(2); /* should be 1.5us */
2818
2819 for (i = 0; i < 4; i++) {
2820 reg = FDI_RX_IIR(pipe);
2821 temp = I915_READ(reg);
2822 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2823
2824 if (temp & FDI_RX_SYMBOL_LOCK ||
2825 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2826 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2827 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2828 i);
2829 goto train_done;
2830 }
2831 udelay(2); /* should be 1.5us */
2832 }
2833 if (i == 4)
2834 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
2835 }
2836
2837 train_done:
2838 DRM_DEBUG_KMS("FDI train done.\n");
2839 }
2840
2841 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2842 {
2843 struct drm_device *dev = intel_crtc->base.dev;
2844 struct drm_i915_private *dev_priv = dev->dev_private;
2845 int pipe = intel_crtc->pipe;
2846 u32 reg, temp;
2847
2848
2849 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2853 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2854 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2855 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2856
2857 POSTING_READ(reg);
2858 udelay(200);
2859
2860 /* Switch from Rawclk to PCDclk */
2861 temp = I915_READ(reg);
2862 I915_WRITE(reg, temp | FDI_PCDCLK);
2863
2864 POSTING_READ(reg);
2865 udelay(200);
2866
2867 /* Enable CPU FDI TX PLL, always on for Ironlake */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2871 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2872
2873 POSTING_READ(reg);
2874 udelay(100);
2875 }
2876 }
2877
2878 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2879 {
2880 struct drm_device *dev = intel_crtc->base.dev;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 int pipe = intel_crtc->pipe;
2883 u32 reg, temp;
2884
2885 /* Switch from PCDclk to Rawclk */
2886 reg = FDI_RX_CTL(pipe);
2887 temp = I915_READ(reg);
2888 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2889
2890 /* Disable CPU FDI TX PLL */
2891 reg = FDI_TX_CTL(pipe);
2892 temp = I915_READ(reg);
2893 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2894
2895 POSTING_READ(reg);
2896 udelay(100);
2897
2898 reg = FDI_RX_CTL(pipe);
2899 temp = I915_READ(reg);
2900 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2901
2902 /* Wait for the clocks to turn off. */
2903 POSTING_READ(reg);
2904 udelay(100);
2905 }
2906
2907 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2908 {
2909 struct drm_device *dev = crtc->dev;
2910 struct drm_i915_private *dev_priv = dev->dev_private;
2911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2912 int pipe = intel_crtc->pipe;
2913 u32 reg, temp;
2914
2915 /* disable CPU FDI tx and PCH FDI rx */
2916 reg = FDI_TX_CTL(pipe);
2917 temp = I915_READ(reg);
2918 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2919 POSTING_READ(reg);
2920
2921 reg = FDI_RX_CTL(pipe);
2922 temp = I915_READ(reg);
2923 temp &= ~(0x7 << 16);
2924 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2925 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2926
2927 POSTING_READ(reg);
2928 udelay(100);
2929
2930 /* Ironlake workaround, disable clock pointer after downing FDI */
2931 if (HAS_PCH_IBX(dev)) {
2932 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2933 }
2934
2935 /* still set train pattern 1 */
2936 reg = FDI_TX_CTL(pipe);
2937 temp = I915_READ(reg);
2938 temp &= ~FDI_LINK_TRAIN_NONE;
2939 temp |= FDI_LINK_TRAIN_PATTERN_1;
2940 I915_WRITE(reg, temp);
2941
2942 reg = FDI_RX_CTL(pipe);
2943 temp = I915_READ(reg);
2944 if (HAS_PCH_CPT(dev)) {
2945 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2946 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2947 } else {
2948 temp &= ~FDI_LINK_TRAIN_NONE;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1;
2950 }
2951 /* BPC in FDI rx is consistent with that in PIPECONF */
2952 temp &= ~(0x07 << 16);
2953 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2954 I915_WRITE(reg, temp);
2955
2956 POSTING_READ(reg);
2957 udelay(100);
2958 }
2959
2960 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2961 {
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 unsigned long flags;
2966 bool pending;
2967
2968 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2969 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2970 return false;
2971
2972 spin_lock_irqsave(&dev->event_lock, flags);
2973 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2974 spin_unlock_irqrestore(&dev->event_lock, flags);
2975
2976 return pending;
2977 }
2978
2979 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2980 {
2981 struct drm_device *dev = crtc->dev;
2982 struct drm_i915_private *dev_priv = dev->dev_private;
2983
2984 if (crtc->fb == NULL)
2985 return;
2986
2987 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2988
2989 wait_event(dev_priv->pending_flip_queue,
2990 !intel_crtc_has_pending_flip(crtc));
2991
2992 mutex_lock(&dev->struct_mutex);
2993 intel_finish_fb(crtc->fb);
2994 mutex_unlock(&dev->struct_mutex);
2995 }
2996
2997 /* Program iCLKIP clock to the desired frequency */
2998 static void lpt_program_iclkip(struct drm_crtc *crtc)
2999 {
3000 struct drm_device *dev = crtc->dev;
3001 struct drm_i915_private *dev_priv = dev->dev_private;
3002 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3003 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3004 u32 temp;
3005
3006 mutex_lock(&dev_priv->dpio_lock);
3007
3008 /* It is necessary to ungate the pixclk gate prior to programming
3009 * the divisors, and gate it back when it is done.
3010 */
3011 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3012
3013 /* Disable SSCCTL */
3014 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3015 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3016 SBI_SSCCTL_DISABLE,
3017 SBI_ICLK);
3018
3019 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3020 if (clock == 20000) {
3021 auxdiv = 1;
3022 divsel = 0x41;
3023 phaseinc = 0x20;
3024 } else {
3025 /* The iCLK virtual clock root frequency is in MHz,
3026 * but the adjusted_mode->crtc_clock in in KHz. To get the
3027 * divisors, it is necessary to divide one by another, so we
3028 * convert the virtual clock precision to KHz here for higher
3029 * precision.
3030 */
3031 u32 iclk_virtual_root_freq = 172800 * 1000;
3032 u32 iclk_pi_range = 64;
3033 u32 desired_divisor, msb_divisor_value, pi_value;
3034
3035 desired_divisor = (iclk_virtual_root_freq / clock);
3036 msb_divisor_value = desired_divisor / iclk_pi_range;
3037 pi_value = desired_divisor % iclk_pi_range;
3038
3039 auxdiv = 0;
3040 divsel = msb_divisor_value - 2;
3041 phaseinc = pi_value;
3042 }
3043
3044 /* This should not happen with any sane values */
3045 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3046 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3047 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3048 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3049
3050 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3051 clock,
3052 auxdiv,
3053 divsel,
3054 phasedir,
3055 phaseinc);
3056
3057 /* Program SSCDIVINTPHASE6 */
3058 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3059 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3060 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3061 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3062 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3063 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3064 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3065 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3066
3067 /* Program SSCAUXDIV */
3068 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3069 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3070 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3071 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3072
3073 /* Enable modulator and associated divider */
3074 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3075 temp &= ~SBI_SSCCTL_DISABLE;
3076 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3077
3078 /* Wait for initialization time */
3079 udelay(24);
3080
3081 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3082
3083 mutex_unlock(&dev_priv->dpio_lock);
3084 }
3085
3086 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3087 enum pipe pch_transcoder)
3088 {
3089 struct drm_device *dev = crtc->base.dev;
3090 struct drm_i915_private *dev_priv = dev->dev_private;
3091 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3092
3093 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3094 I915_READ(HTOTAL(cpu_transcoder)));
3095 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3096 I915_READ(HBLANK(cpu_transcoder)));
3097 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3098 I915_READ(HSYNC(cpu_transcoder)));
3099
3100 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3101 I915_READ(VTOTAL(cpu_transcoder)));
3102 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3103 I915_READ(VBLANK(cpu_transcoder)));
3104 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3105 I915_READ(VSYNC(cpu_transcoder)));
3106 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3107 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3108 }
3109
3110 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3111 {
3112 struct drm_i915_private *dev_priv = dev->dev_private;
3113 uint32_t temp;
3114
3115 temp = I915_READ(SOUTH_CHICKEN1);
3116 if (temp & FDI_BC_BIFURCATION_SELECT)
3117 return;
3118
3119 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3120 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3121
3122 temp |= FDI_BC_BIFURCATION_SELECT;
3123 DRM_DEBUG_KMS("enabling fdi C rx\n");
3124 I915_WRITE(SOUTH_CHICKEN1, temp);
3125 POSTING_READ(SOUTH_CHICKEN1);
3126 }
3127
3128 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3129 {
3130 struct drm_device *dev = intel_crtc->base.dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132
3133 switch (intel_crtc->pipe) {
3134 case PIPE_A:
3135 break;
3136 case PIPE_B:
3137 if (intel_crtc->config.fdi_lanes > 2)
3138 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3139 else
3140 cpt_enable_fdi_bc_bifurcation(dev);
3141
3142 break;
3143 case PIPE_C:
3144 cpt_enable_fdi_bc_bifurcation(dev);
3145
3146 break;
3147 default:
3148 BUG();
3149 }
3150 }
3151
3152 /*
3153 * Enable PCH resources required for PCH ports:
3154 * - PCH PLLs
3155 * - FDI training & RX/TX
3156 * - update transcoder timings
3157 * - DP transcoding bits
3158 * - transcoder
3159 */
3160 static void ironlake_pch_enable(struct drm_crtc *crtc)
3161 {
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3165 int pipe = intel_crtc->pipe;
3166 u32 reg, temp;
3167
3168 assert_pch_transcoder_disabled(dev_priv, pipe);
3169
3170 if (IS_IVYBRIDGE(dev))
3171 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3172
3173 /* Write the TU size bits before fdi link training, so that error
3174 * detection works. */
3175 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3176 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3177
3178 /* For PCH output, training FDI link */
3179 dev_priv->display.fdi_link_train(crtc);
3180
3181 /* We need to program the right clock selection before writing the pixel
3182 * mutliplier into the DPLL. */
3183 if (HAS_PCH_CPT(dev)) {
3184 u32 sel;
3185
3186 temp = I915_READ(PCH_DPLL_SEL);
3187 temp |= TRANS_DPLL_ENABLE(pipe);
3188 sel = TRANS_DPLLB_SEL(pipe);
3189 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3190 temp |= sel;
3191 else
3192 temp &= ~sel;
3193 I915_WRITE(PCH_DPLL_SEL, temp);
3194 }
3195
3196 /* XXX: pch pll's can be enabled any time before we enable the PCH
3197 * transcoder, and we actually should do this to not upset any PCH
3198 * transcoder that already use the clock when we share it.
3199 *
3200 * Note that enable_shared_dpll tries to do the right thing, but
3201 * get_shared_dpll unconditionally resets the pll - we need that to have
3202 * the right LVDS enable sequence. */
3203 ironlake_enable_shared_dpll(intel_crtc);
3204
3205 /* set transcoder timing, panel must allow it */
3206 assert_panel_unlocked(dev_priv, pipe);
3207 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3208
3209 intel_fdi_normal_train(crtc);
3210
3211 /* For PCH DP, enable TRANS_DP_CTL */
3212 if (HAS_PCH_CPT(dev) &&
3213 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3214 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3215 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3216 reg = TRANS_DP_CTL(pipe);
3217 temp = I915_READ(reg);
3218 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3219 TRANS_DP_SYNC_MASK |
3220 TRANS_DP_BPC_MASK);
3221 temp |= (TRANS_DP_OUTPUT_ENABLE |
3222 TRANS_DP_ENH_FRAMING);
3223 temp |= bpc << 9; /* same format but at 11:9 */
3224
3225 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3226 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3227 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3228 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3229
3230 switch (intel_trans_dp_port_sel(crtc)) {
3231 case PCH_DP_B:
3232 temp |= TRANS_DP_PORT_SEL_B;
3233 break;
3234 case PCH_DP_C:
3235 temp |= TRANS_DP_PORT_SEL_C;
3236 break;
3237 case PCH_DP_D:
3238 temp |= TRANS_DP_PORT_SEL_D;
3239 break;
3240 default:
3241 BUG();
3242 }
3243
3244 I915_WRITE(reg, temp);
3245 }
3246
3247 ironlake_enable_pch_transcoder(dev_priv, pipe);
3248 }
3249
3250 static void lpt_pch_enable(struct drm_crtc *crtc)
3251 {
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3255 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3256
3257 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3258
3259 lpt_program_iclkip(crtc);
3260
3261 /* Set transcoder timing. */
3262 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3263
3264 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3265 }
3266
3267 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3268 {
3269 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3270
3271 if (pll == NULL)
3272 return;
3273
3274 if (pll->refcount == 0) {
3275 WARN(1, "bad %s refcount\n", pll->name);
3276 return;
3277 }
3278
3279 if (--pll->refcount == 0) {
3280 WARN_ON(pll->on);
3281 WARN_ON(pll->active);
3282 }
3283
3284 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3285 }
3286
3287 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3288 {
3289 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3290 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3291 enum intel_dpll_id i;
3292
3293 if (pll) {
3294 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3295 crtc->base.base.id, pll->name);
3296 intel_put_shared_dpll(crtc);
3297 }
3298
3299 if (HAS_PCH_IBX(dev_priv->dev)) {
3300 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3301 i = (enum intel_dpll_id) crtc->pipe;
3302 pll = &dev_priv->shared_dplls[i];
3303
3304 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3305 crtc->base.base.id, pll->name);
3306
3307 goto found;
3308 }
3309
3310 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3311 pll = &dev_priv->shared_dplls[i];
3312
3313 /* Only want to check enabled timings first */
3314 if (pll->refcount == 0)
3315 continue;
3316
3317 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3318 sizeof(pll->hw_state)) == 0) {
3319 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3320 crtc->base.base.id,
3321 pll->name, pll->refcount, pll->active);
3322
3323 goto found;
3324 }
3325 }
3326
3327 /* Ok no matching timings, maybe there's a free one? */
3328 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3329 pll = &dev_priv->shared_dplls[i];
3330 if (pll->refcount == 0) {
3331 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3332 crtc->base.base.id, pll->name);
3333 goto found;
3334 }
3335 }
3336
3337 return NULL;
3338
3339 found:
3340 crtc->config.shared_dpll = i;
3341 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3342 pipe_name(crtc->pipe));
3343
3344 if (pll->active == 0) {
3345 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3346 sizeof(pll->hw_state));
3347
3348 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3349 WARN_ON(pll->on);
3350 assert_shared_dpll_disabled(dev_priv, pll);
3351
3352 pll->mode_set(dev_priv, pll);
3353 }
3354 pll->refcount++;
3355
3356 return pll;
3357 }
3358
3359 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3360 {
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 int dslreg = PIPEDSL(pipe);
3363 u32 temp;
3364
3365 temp = I915_READ(dslreg);
3366 udelay(500);
3367 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3368 if (wait_for(I915_READ(dslreg) != temp, 5))
3369 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3370 }
3371 }
3372
3373 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3374 {
3375 struct drm_device *dev = crtc->base.dev;
3376 struct drm_i915_private *dev_priv = dev->dev_private;
3377 int pipe = crtc->pipe;
3378
3379 if (crtc->config.pch_pfit.enabled) {
3380 /* Force use of hard-coded filter coefficients
3381 * as some pre-programmed values are broken,
3382 * e.g. x201.
3383 */
3384 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3385 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3386 PF_PIPE_SEL_IVB(pipe));
3387 else
3388 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3389 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3390 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3391 }
3392 }
3393
3394 static void intel_enable_planes(struct drm_crtc *crtc)
3395 {
3396 struct drm_device *dev = crtc->dev;
3397 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3398 struct intel_plane *intel_plane;
3399
3400 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3401 if (intel_plane->pipe == pipe)
3402 intel_plane_restore(&intel_plane->base);
3403 }
3404
3405 static void intel_disable_planes(struct drm_crtc *crtc)
3406 {
3407 struct drm_device *dev = crtc->dev;
3408 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3409 struct intel_plane *intel_plane;
3410
3411 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3412 if (intel_plane->pipe == pipe)
3413 intel_plane_disable(&intel_plane->base);
3414 }
3415
3416 void hsw_enable_ips(struct intel_crtc *crtc)
3417 {
3418 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3419
3420 if (!crtc->config.ips_enabled)
3421 return;
3422
3423 /* We can only enable IPS after we enable a plane and wait for a vblank.
3424 * We guarantee that the plane is enabled by calling intel_enable_ips
3425 * only after intel_enable_plane. And intel_enable_plane already waits
3426 * for a vblank, so all we need to do here is to enable the IPS bit. */
3427 assert_plane_enabled(dev_priv, crtc->plane);
3428 if (IS_BROADWELL(crtc->base.dev)) {
3429 mutex_lock(&dev_priv->rps.hw_lock);
3430 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3431 mutex_unlock(&dev_priv->rps.hw_lock);
3432 /* Quoting Art Runyan: "its not safe to expect any particular
3433 * value in IPS_CTL bit 31 after enabling IPS through the
3434 * mailbox." Therefore we need to defer waiting on the state
3435 * change.
3436 * TODO: need to fix this for state checker
3437 */
3438 } else {
3439 I915_WRITE(IPS_CTL, IPS_ENABLE);
3440 /* The bit only becomes 1 in the next vblank, so this wait here
3441 * is essentially intel_wait_for_vblank. If we don't have this
3442 * and don't wait for vblanks until the end of crtc_enable, then
3443 * the HW state readout code will complain that the expected
3444 * IPS_CTL value is not the one we read. */
3445 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3446 DRM_ERROR("Timed out waiting for IPS enable\n");
3447 }
3448 }
3449
3450 void hsw_disable_ips(struct intel_crtc *crtc)
3451 {
3452 struct drm_device *dev = crtc->base.dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454
3455 if (!crtc->config.ips_enabled)
3456 return;
3457
3458 assert_plane_enabled(dev_priv, crtc->plane);
3459 if (IS_BROADWELL(crtc->base.dev)) {
3460 mutex_lock(&dev_priv->rps.hw_lock);
3461 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3462 mutex_unlock(&dev_priv->rps.hw_lock);
3463 } else
3464 I915_WRITE(IPS_CTL, 0);
3465 POSTING_READ(IPS_CTL);
3466
3467 /* We need to wait for a vblank before we can disable the plane. */
3468 intel_wait_for_vblank(dev, crtc->pipe);
3469 }
3470
3471 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3472 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3473 {
3474 struct drm_device *dev = crtc->dev;
3475 struct drm_i915_private *dev_priv = dev->dev_private;
3476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3477 enum pipe pipe = intel_crtc->pipe;
3478 int palreg = PALETTE(pipe);
3479 int i;
3480 bool reenable_ips = false;
3481
3482 /* The clocks have to be on to load the palette. */
3483 if (!crtc->enabled || !intel_crtc->active)
3484 return;
3485
3486 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3487 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3488 assert_dsi_pll_enabled(dev_priv);
3489 else
3490 assert_pll_enabled(dev_priv, pipe);
3491 }
3492
3493 /* use legacy palette for Ironlake */
3494 if (HAS_PCH_SPLIT(dev))
3495 palreg = LGC_PALETTE(pipe);
3496
3497 /* Workaround : Do not read or write the pipe palette/gamma data while
3498 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3499 */
3500 if (intel_crtc->config.ips_enabled &&
3501 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3502 GAMMA_MODE_MODE_SPLIT)) {
3503 hsw_disable_ips(intel_crtc);
3504 reenable_ips = true;
3505 }
3506
3507 for (i = 0; i < 256; i++) {
3508 I915_WRITE(palreg + 4 * i,
3509 (intel_crtc->lut_r[i] << 16) |
3510 (intel_crtc->lut_g[i] << 8) |
3511 intel_crtc->lut_b[i]);
3512 }
3513
3514 if (reenable_ips)
3515 hsw_enable_ips(intel_crtc);
3516 }
3517
3518 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3519 {
3520 struct drm_device *dev = crtc->dev;
3521 struct drm_i915_private *dev_priv = dev->dev_private;
3522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3523 struct intel_encoder *encoder;
3524 int pipe = intel_crtc->pipe;
3525 int plane = intel_crtc->plane;
3526
3527 WARN_ON(!crtc->enabled);
3528
3529 if (intel_crtc->active)
3530 return;
3531
3532 intel_crtc->active = true;
3533
3534 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3535 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3536
3537 for_each_encoder_on_crtc(dev, crtc, encoder)
3538 if (encoder->pre_enable)
3539 encoder->pre_enable(encoder);
3540
3541 if (intel_crtc->config.has_pch_encoder) {
3542 /* Note: FDI PLL enabling _must_ be done before we enable the
3543 * cpu pipes, hence this is separate from all the other fdi/pch
3544 * enabling. */
3545 ironlake_fdi_pll_enable(intel_crtc);
3546 } else {
3547 assert_fdi_tx_disabled(dev_priv, pipe);
3548 assert_fdi_rx_disabled(dev_priv, pipe);
3549 }
3550
3551 ironlake_pfit_enable(intel_crtc);
3552
3553 /*
3554 * On ILK+ LUT must be loaded before the pipe is running but with
3555 * clocks enabled
3556 */
3557 intel_crtc_load_lut(crtc);
3558
3559 intel_update_watermarks(crtc);
3560 intel_enable_pipe(dev_priv, pipe,
3561 intel_crtc->config.has_pch_encoder, false);
3562 intel_enable_primary_plane(dev_priv, plane, pipe);
3563 intel_enable_planes(crtc);
3564 intel_crtc_update_cursor(crtc, true);
3565
3566 if (intel_crtc->config.has_pch_encoder)
3567 ironlake_pch_enable(crtc);
3568
3569 mutex_lock(&dev->struct_mutex);
3570 intel_update_fbc(dev);
3571 mutex_unlock(&dev->struct_mutex);
3572
3573 for_each_encoder_on_crtc(dev, crtc, encoder)
3574 encoder->enable(encoder);
3575
3576 if (HAS_PCH_CPT(dev))
3577 cpt_verify_modeset(dev, intel_crtc->pipe);
3578
3579 /*
3580 * There seems to be a race in PCH platform hw (at least on some
3581 * outputs) where an enabled pipe still completes any pageflip right
3582 * away (as if the pipe is off) instead of waiting for vblank. As soon
3583 * as the first vblank happend, everything works as expected. Hence just
3584 * wait for one vblank before returning to avoid strange things
3585 * happening.
3586 */
3587 intel_wait_for_vblank(dev, intel_crtc->pipe);
3588 }
3589
3590 /* IPS only exists on ULT machines and is tied to pipe A. */
3591 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3592 {
3593 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3594 }
3595
3596 static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3597 {
3598 struct drm_device *dev = crtc->dev;
3599 struct drm_i915_private *dev_priv = dev->dev_private;
3600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3601 int pipe = intel_crtc->pipe;
3602 int plane = intel_crtc->plane;
3603
3604 intel_enable_primary_plane(dev_priv, plane, pipe);
3605 intel_enable_planes(crtc);
3606 intel_crtc_update_cursor(crtc, true);
3607
3608 hsw_enable_ips(intel_crtc);
3609
3610 mutex_lock(&dev->struct_mutex);
3611 intel_update_fbc(dev);
3612 mutex_unlock(&dev->struct_mutex);
3613 }
3614
3615 static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3616 {
3617 struct drm_device *dev = crtc->dev;
3618 struct drm_i915_private *dev_priv = dev->dev_private;
3619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3620 int pipe = intel_crtc->pipe;
3621 int plane = intel_crtc->plane;
3622
3623 intel_crtc_wait_for_pending_flips(crtc);
3624 drm_vblank_off(dev, pipe);
3625
3626 /* FBC must be disabled before disabling the plane on HSW. */
3627 if (dev_priv->fbc.plane == plane)
3628 intel_disable_fbc(dev);
3629
3630 hsw_disable_ips(intel_crtc);
3631
3632 intel_crtc_update_cursor(crtc, false);
3633 intel_disable_planes(crtc);
3634 intel_disable_primary_plane(dev_priv, plane, pipe);
3635 }
3636
3637 /*
3638 * This implements the workaround described in the "notes" section of the mode
3639 * set sequence documentation. When going from no pipes or single pipe to
3640 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3641 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3642 */
3643 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3644 {
3645 struct drm_device *dev = crtc->base.dev;
3646 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3647
3648 /* We want to get the other_active_crtc only if there's only 1 other
3649 * active crtc. */
3650 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3651 if (!crtc_it->active || crtc_it == crtc)
3652 continue;
3653
3654 if (other_active_crtc)
3655 return;
3656
3657 other_active_crtc = crtc_it;
3658 }
3659 if (!other_active_crtc)
3660 return;
3661
3662 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3663 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3664 }
3665
3666 static void haswell_crtc_enable(struct drm_crtc *crtc)
3667 {
3668 struct drm_device *dev = crtc->dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3671 struct intel_encoder *encoder;
3672 int pipe = intel_crtc->pipe;
3673
3674 WARN_ON(!crtc->enabled);
3675
3676 if (intel_crtc->active)
3677 return;
3678
3679 intel_crtc->active = true;
3680
3681 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3682 if (intel_crtc->config.has_pch_encoder)
3683 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3684
3685 if (intel_crtc->config.has_pch_encoder)
3686 dev_priv->display.fdi_link_train(crtc);
3687
3688 for_each_encoder_on_crtc(dev, crtc, encoder)
3689 if (encoder->pre_enable)
3690 encoder->pre_enable(encoder);
3691
3692 intel_ddi_enable_pipe_clock(intel_crtc);
3693
3694 ironlake_pfit_enable(intel_crtc);
3695
3696 /*
3697 * On ILK+ LUT must be loaded before the pipe is running but with
3698 * clocks enabled
3699 */
3700 intel_crtc_load_lut(crtc);
3701
3702 intel_ddi_set_pipe_settings(crtc);
3703 intel_ddi_enable_transcoder_func(crtc);
3704
3705 intel_update_watermarks(crtc);
3706 intel_enable_pipe(dev_priv, pipe,
3707 intel_crtc->config.has_pch_encoder, false);
3708
3709 if (intel_crtc->config.has_pch_encoder)
3710 lpt_pch_enable(crtc);
3711
3712 for_each_encoder_on_crtc(dev, crtc, encoder) {
3713 encoder->enable(encoder);
3714 intel_opregion_notify_encoder(encoder, true);
3715 }
3716
3717 /* If we change the relative order between pipe/planes enabling, we need
3718 * to change the workaround. */
3719 haswell_mode_set_planes_workaround(intel_crtc);
3720 haswell_crtc_enable_planes(crtc);
3721
3722 /*
3723 * There seems to be a race in PCH platform hw (at least on some
3724 * outputs) where an enabled pipe still completes any pageflip right
3725 * away (as if the pipe is off) instead of waiting for vblank. As soon
3726 * as the first vblank happend, everything works as expected. Hence just
3727 * wait for one vblank before returning to avoid strange things
3728 * happening.
3729 */
3730 intel_wait_for_vblank(dev, intel_crtc->pipe);
3731 }
3732
3733 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3734 {
3735 struct drm_device *dev = crtc->base.dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 int pipe = crtc->pipe;
3738
3739 /* To avoid upsetting the power well on haswell only disable the pfit if
3740 * it's in use. The hw state code will make sure we get this right. */
3741 if (crtc->config.pch_pfit.enabled) {
3742 I915_WRITE(PF_CTL(pipe), 0);
3743 I915_WRITE(PF_WIN_POS(pipe), 0);
3744 I915_WRITE(PF_WIN_SZ(pipe), 0);
3745 }
3746 }
3747
3748 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3749 {
3750 struct drm_device *dev = crtc->dev;
3751 struct drm_i915_private *dev_priv = dev->dev_private;
3752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3753 struct intel_encoder *encoder;
3754 int pipe = intel_crtc->pipe;
3755 int plane = intel_crtc->plane;
3756 u32 reg, temp;
3757
3758
3759 if (!intel_crtc->active)
3760 return;
3761
3762 for_each_encoder_on_crtc(dev, crtc, encoder)
3763 encoder->disable(encoder);
3764
3765 intel_crtc_wait_for_pending_flips(crtc);
3766 drm_vblank_off(dev, pipe);
3767
3768 if (dev_priv->fbc.plane == plane)
3769 intel_disable_fbc(dev);
3770
3771 intel_crtc_update_cursor(crtc, false);
3772 intel_disable_planes(crtc);
3773 intel_disable_primary_plane(dev_priv, plane, pipe);
3774
3775 if (intel_crtc->config.has_pch_encoder)
3776 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3777
3778 intel_disable_pipe(dev_priv, pipe);
3779
3780 ironlake_pfit_disable(intel_crtc);
3781
3782 for_each_encoder_on_crtc(dev, crtc, encoder)
3783 if (encoder->post_disable)
3784 encoder->post_disable(encoder);
3785
3786 if (intel_crtc->config.has_pch_encoder) {
3787 ironlake_fdi_disable(crtc);
3788
3789 ironlake_disable_pch_transcoder(dev_priv, pipe);
3790 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3791
3792 if (HAS_PCH_CPT(dev)) {
3793 /* disable TRANS_DP_CTL */
3794 reg = TRANS_DP_CTL(pipe);
3795 temp = I915_READ(reg);
3796 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3797 TRANS_DP_PORT_SEL_MASK);
3798 temp |= TRANS_DP_PORT_SEL_NONE;
3799 I915_WRITE(reg, temp);
3800
3801 /* disable DPLL_SEL */
3802 temp = I915_READ(PCH_DPLL_SEL);
3803 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3804 I915_WRITE(PCH_DPLL_SEL, temp);
3805 }
3806
3807 /* disable PCH DPLL */
3808 intel_disable_shared_dpll(intel_crtc);
3809
3810 ironlake_fdi_pll_disable(intel_crtc);
3811 }
3812
3813 intel_crtc->active = false;
3814 intel_update_watermarks(crtc);
3815
3816 mutex_lock(&dev->struct_mutex);
3817 intel_update_fbc(dev);
3818 mutex_unlock(&dev->struct_mutex);
3819 }
3820
3821 static void haswell_crtc_disable(struct drm_crtc *crtc)
3822 {
3823 struct drm_device *dev = crtc->dev;
3824 struct drm_i915_private *dev_priv = dev->dev_private;
3825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3826 struct intel_encoder *encoder;
3827 int pipe = intel_crtc->pipe;
3828 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3829
3830 if (!intel_crtc->active)
3831 return;
3832
3833 haswell_crtc_disable_planes(crtc);
3834
3835 for_each_encoder_on_crtc(dev, crtc, encoder) {
3836 intel_opregion_notify_encoder(encoder, false);
3837 encoder->disable(encoder);
3838 }
3839
3840 if (intel_crtc->config.has_pch_encoder)
3841 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3842 intel_disable_pipe(dev_priv, pipe);
3843
3844 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3845
3846 ironlake_pfit_disable(intel_crtc);
3847
3848 intel_ddi_disable_pipe_clock(intel_crtc);
3849
3850 for_each_encoder_on_crtc(dev, crtc, encoder)
3851 if (encoder->post_disable)
3852 encoder->post_disable(encoder);
3853
3854 if (intel_crtc->config.has_pch_encoder) {
3855 lpt_disable_pch_transcoder(dev_priv);
3856 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3857 intel_ddi_fdi_disable(crtc);
3858 }
3859
3860 intel_crtc->active = false;
3861 intel_update_watermarks(crtc);
3862
3863 mutex_lock(&dev->struct_mutex);
3864 intel_update_fbc(dev);
3865 mutex_unlock(&dev->struct_mutex);
3866 }
3867
3868 static void ironlake_crtc_off(struct drm_crtc *crtc)
3869 {
3870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3871 intel_put_shared_dpll(intel_crtc);
3872 }
3873
3874 static void haswell_crtc_off(struct drm_crtc *crtc)
3875 {
3876 intel_ddi_put_crtc_pll(crtc);
3877 }
3878
3879 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3880 {
3881 if (!enable && intel_crtc->overlay) {
3882 struct drm_device *dev = intel_crtc->base.dev;
3883 struct drm_i915_private *dev_priv = dev->dev_private;
3884
3885 mutex_lock(&dev->struct_mutex);
3886 dev_priv->mm.interruptible = false;
3887 (void) intel_overlay_switch_off(intel_crtc->overlay);
3888 dev_priv->mm.interruptible = true;
3889 mutex_unlock(&dev->struct_mutex);
3890 }
3891
3892 /* Let userspace switch the overlay on again. In most cases userspace
3893 * has to recompute where to put it anyway.
3894 */
3895 }
3896
3897 /**
3898 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3899 * cursor plane briefly if not already running after enabling the display
3900 * plane.
3901 * This workaround avoids occasional blank screens when self refresh is
3902 * enabled.
3903 */
3904 static void
3905 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3906 {
3907 u32 cntl = I915_READ(CURCNTR(pipe));
3908
3909 if ((cntl & CURSOR_MODE) == 0) {
3910 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3911
3912 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3913 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3914 intel_wait_for_vblank(dev_priv->dev, pipe);
3915 I915_WRITE(CURCNTR(pipe), cntl);
3916 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3917 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3918 }
3919 }
3920
3921 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3922 {
3923 struct drm_device *dev = crtc->base.dev;
3924 struct drm_i915_private *dev_priv = dev->dev_private;
3925 struct intel_crtc_config *pipe_config = &crtc->config;
3926
3927 if (!crtc->config.gmch_pfit.control)
3928 return;
3929
3930 /*
3931 * The panel fitter should only be adjusted whilst the pipe is disabled,
3932 * according to register description and PRM.
3933 */
3934 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3935 assert_pipe_disabled(dev_priv, crtc->pipe);
3936
3937 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3938 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3939
3940 /* Border color in case we don't scale up to the full screen. Black by
3941 * default, change to something else for debugging. */
3942 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3943 }
3944
3945 int valleyview_get_vco(struct drm_i915_private *dev_priv)
3946 {
3947 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3948
3949 /* Obtain SKU information */
3950 mutex_lock(&dev_priv->dpio_lock);
3951 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3952 CCK_FUSE_HPLL_FREQ_MASK;
3953 mutex_unlock(&dev_priv->dpio_lock);
3954
3955 return vco_freq[hpll_freq];
3956 }
3957
3958 /* Adjust CDclk dividers to allow high res or save power if possible */
3959 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3960 {
3961 struct drm_i915_private *dev_priv = dev->dev_private;
3962 u32 val, cmd;
3963
3964 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3965 cmd = 2;
3966 else if (cdclk == 266)
3967 cmd = 1;
3968 else
3969 cmd = 0;
3970
3971 mutex_lock(&dev_priv->rps.hw_lock);
3972 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3973 val &= ~DSPFREQGUAR_MASK;
3974 val |= (cmd << DSPFREQGUAR_SHIFT);
3975 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3976 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3977 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3978 50)) {
3979 DRM_ERROR("timed out waiting for CDclk change\n");
3980 }
3981 mutex_unlock(&dev_priv->rps.hw_lock);
3982
3983 if (cdclk == 400) {
3984 u32 divider, vco;
3985
3986 vco = valleyview_get_vco(dev_priv);
3987 divider = ((vco << 1) / cdclk) - 1;
3988
3989 mutex_lock(&dev_priv->dpio_lock);
3990 /* adjust cdclk divider */
3991 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3992 val &= ~0xf;
3993 val |= divider;
3994 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3995 mutex_unlock(&dev_priv->dpio_lock);
3996 }
3997
3998 mutex_lock(&dev_priv->dpio_lock);
3999 /* adjust self-refresh exit latency value */
4000 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4001 val &= ~0x7f;
4002
4003 /*
4004 * For high bandwidth configs, we set a higher latency in the bunit
4005 * so that the core display fetch happens in time to avoid underruns.
4006 */
4007 if (cdclk == 400)
4008 val |= 4500 / 250; /* 4.5 usec */
4009 else
4010 val |= 3000 / 250; /* 3.0 usec */
4011 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4012 mutex_unlock(&dev_priv->dpio_lock);
4013
4014 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4015 intel_i2c_reset(dev);
4016 }
4017
4018 static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4019 {
4020 int cur_cdclk, vco;
4021 int divider;
4022
4023 vco = valleyview_get_vco(dev_priv);
4024
4025 mutex_lock(&dev_priv->dpio_lock);
4026 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4027 mutex_unlock(&dev_priv->dpio_lock);
4028
4029 divider &= 0xf;
4030
4031 cur_cdclk = (vco << 1) / (divider + 1);
4032
4033 return cur_cdclk;
4034 }
4035
4036 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4037 int max_pixclk)
4038 {
4039 int cur_cdclk;
4040
4041 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4042
4043 /*
4044 * Really only a few cases to deal with, as only 4 CDclks are supported:
4045 * 200MHz
4046 * 267MHz
4047 * 320MHz
4048 * 400MHz
4049 * So we check to see whether we're above 90% of the lower bin and
4050 * adjust if needed.
4051 */
4052 if (max_pixclk > 288000) {
4053 return 400;
4054 } else if (max_pixclk > 240000) {
4055 return 320;
4056 } else
4057 return 266;
4058 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4059 }
4060
4061 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4062 unsigned modeset_pipes,
4063 struct intel_crtc_config *pipe_config)
4064 {
4065 struct drm_device *dev = dev_priv->dev;
4066 struct intel_crtc *intel_crtc;
4067 int max_pixclk = 0;
4068
4069 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4070 base.head) {
4071 if (modeset_pipes & (1 << intel_crtc->pipe))
4072 max_pixclk = max(max_pixclk,
4073 pipe_config->adjusted_mode.crtc_clock);
4074 else if (intel_crtc->base.enabled)
4075 max_pixclk = max(max_pixclk,
4076 intel_crtc->config.adjusted_mode.crtc_clock);
4077 }
4078
4079 return max_pixclk;
4080 }
4081
4082 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4083 unsigned *prepare_pipes,
4084 unsigned modeset_pipes,
4085 struct intel_crtc_config *pipe_config)
4086 {
4087 struct drm_i915_private *dev_priv = dev->dev_private;
4088 struct intel_crtc *intel_crtc;
4089 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4090 pipe_config);
4091 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4092
4093 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4094 return;
4095
4096 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4097 base.head)
4098 if (intel_crtc->base.enabled)
4099 *prepare_pipes |= (1 << intel_crtc->pipe);
4100 }
4101
4102 static void valleyview_modeset_global_resources(struct drm_device *dev)
4103 {
4104 struct drm_i915_private *dev_priv = dev->dev_private;
4105 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4106 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4107 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4108
4109 if (req_cdclk != cur_cdclk)
4110 valleyview_set_cdclk(dev, req_cdclk);
4111 }
4112
4113 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4114 {
4115 struct drm_device *dev = crtc->dev;
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4118 struct intel_encoder *encoder;
4119 int pipe = intel_crtc->pipe;
4120 int plane = intel_crtc->plane;
4121 bool is_dsi;
4122
4123 WARN_ON(!crtc->enabled);
4124
4125 if (intel_crtc->active)
4126 return;
4127
4128 intel_crtc->active = true;
4129
4130 for_each_encoder_on_crtc(dev, crtc, encoder)
4131 if (encoder->pre_pll_enable)
4132 encoder->pre_pll_enable(encoder);
4133
4134 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4135
4136 if (!is_dsi)
4137 vlv_enable_pll(intel_crtc);
4138
4139 for_each_encoder_on_crtc(dev, crtc, encoder)
4140 if (encoder->pre_enable)
4141 encoder->pre_enable(encoder);
4142
4143 i9xx_pfit_enable(intel_crtc);
4144
4145 intel_crtc_load_lut(crtc);
4146
4147 intel_update_watermarks(crtc);
4148 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
4149 intel_enable_primary_plane(dev_priv, plane, pipe);
4150 intel_enable_planes(crtc);
4151 intel_crtc_update_cursor(crtc, true);
4152
4153 intel_update_fbc(dev);
4154
4155 for_each_encoder_on_crtc(dev, crtc, encoder)
4156 encoder->enable(encoder);
4157 }
4158
4159 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4160 {
4161 struct drm_device *dev = crtc->dev;
4162 struct drm_i915_private *dev_priv = dev->dev_private;
4163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4164 struct intel_encoder *encoder;
4165 int pipe = intel_crtc->pipe;
4166 int plane = intel_crtc->plane;
4167
4168 WARN_ON(!crtc->enabled);
4169
4170 if (intel_crtc->active)
4171 return;
4172
4173 intel_crtc->active = true;
4174
4175 for_each_encoder_on_crtc(dev, crtc, encoder)
4176 if (encoder->pre_enable)
4177 encoder->pre_enable(encoder);
4178
4179 i9xx_enable_pll(intel_crtc);
4180
4181 i9xx_pfit_enable(intel_crtc);
4182
4183 intel_crtc_load_lut(crtc);
4184
4185 intel_update_watermarks(crtc);
4186 intel_enable_pipe(dev_priv, pipe, false, false);
4187 intel_enable_primary_plane(dev_priv, plane, pipe);
4188 intel_enable_planes(crtc);
4189 /* The fixup needs to happen before cursor is enabled */
4190 if (IS_G4X(dev))
4191 g4x_fixup_plane(dev_priv, pipe);
4192 intel_crtc_update_cursor(crtc, true);
4193
4194 /* Give the overlay scaler a chance to enable if it's on this pipe */
4195 intel_crtc_dpms_overlay(intel_crtc, true);
4196
4197 intel_update_fbc(dev);
4198
4199 for_each_encoder_on_crtc(dev, crtc, encoder)
4200 encoder->enable(encoder);
4201 }
4202
4203 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4204 {
4205 struct drm_device *dev = crtc->base.dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207
4208 if (!crtc->config.gmch_pfit.control)
4209 return;
4210
4211 assert_pipe_disabled(dev_priv, crtc->pipe);
4212
4213 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4214 I915_READ(PFIT_CONTROL));
4215 I915_WRITE(PFIT_CONTROL, 0);
4216 }
4217
4218 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4219 {
4220 struct drm_device *dev = crtc->dev;
4221 struct drm_i915_private *dev_priv = dev->dev_private;
4222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4223 struct intel_encoder *encoder;
4224 int pipe = intel_crtc->pipe;
4225 int plane = intel_crtc->plane;
4226
4227 if (!intel_crtc->active)
4228 return;
4229
4230 for_each_encoder_on_crtc(dev, crtc, encoder)
4231 encoder->disable(encoder);
4232
4233 /* Give the overlay scaler a chance to disable if it's on this pipe */
4234 intel_crtc_wait_for_pending_flips(crtc);
4235 drm_vblank_off(dev, pipe);
4236
4237 if (dev_priv->fbc.plane == plane)
4238 intel_disable_fbc(dev);
4239
4240 intel_crtc_dpms_overlay(intel_crtc, false);
4241 intel_crtc_update_cursor(crtc, false);
4242 intel_disable_planes(crtc);
4243 intel_disable_primary_plane(dev_priv, plane, pipe);
4244
4245 intel_disable_pipe(dev_priv, pipe);
4246
4247 i9xx_pfit_disable(intel_crtc);
4248
4249 for_each_encoder_on_crtc(dev, crtc, encoder)
4250 if (encoder->post_disable)
4251 encoder->post_disable(encoder);
4252
4253 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
4254 vlv_disable_pll(dev_priv, pipe);
4255 else if (!IS_VALLEYVIEW(dev))
4256 i9xx_disable_pll(dev_priv, pipe);
4257
4258 intel_crtc->active = false;
4259 intel_update_watermarks(crtc);
4260
4261 intel_update_fbc(dev);
4262 }
4263
4264 static void i9xx_crtc_off(struct drm_crtc *crtc)
4265 {
4266 }
4267
4268 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4269 bool enabled)
4270 {
4271 struct drm_device *dev = crtc->dev;
4272 struct drm_i915_master_private *master_priv;
4273 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4274 int pipe = intel_crtc->pipe;
4275
4276 if (!dev->primary->master)
4277 return;
4278
4279 master_priv = dev->primary->master->driver_priv;
4280 if (!master_priv->sarea_priv)
4281 return;
4282
4283 switch (pipe) {
4284 case 0:
4285 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4286 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4287 break;
4288 case 1:
4289 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4290 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4291 break;
4292 default:
4293 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4294 break;
4295 }
4296 }
4297
4298 /**
4299 * Sets the power management mode of the pipe and plane.
4300 */
4301 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4302 {
4303 struct drm_device *dev = crtc->dev;
4304 struct drm_i915_private *dev_priv = dev->dev_private;
4305 struct intel_encoder *intel_encoder;
4306 bool enable = false;
4307
4308 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4309 enable |= intel_encoder->connectors_active;
4310
4311 if (enable)
4312 dev_priv->display.crtc_enable(crtc);
4313 else
4314 dev_priv->display.crtc_disable(crtc);
4315
4316 intel_crtc_update_sarea(crtc, enable);
4317 }
4318
4319 static void intel_crtc_disable(struct drm_crtc *crtc)
4320 {
4321 struct drm_device *dev = crtc->dev;
4322 struct drm_connector *connector;
4323 struct drm_i915_private *dev_priv = dev->dev_private;
4324 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4325
4326 /* crtc should still be enabled when we disable it. */
4327 WARN_ON(!crtc->enabled);
4328
4329 dev_priv->display.crtc_disable(crtc);
4330 intel_crtc->eld_vld = false;
4331 intel_crtc_update_sarea(crtc, false);
4332 dev_priv->display.off(crtc);
4333
4334 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4335 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4336 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4337
4338 if (crtc->fb) {
4339 mutex_lock(&dev->struct_mutex);
4340 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
4341 mutex_unlock(&dev->struct_mutex);
4342 crtc->fb = NULL;
4343 }
4344
4345 /* Update computed state. */
4346 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4347 if (!connector->encoder || !connector->encoder->crtc)
4348 continue;
4349
4350 if (connector->encoder->crtc != crtc)
4351 continue;
4352
4353 connector->dpms = DRM_MODE_DPMS_OFF;
4354 to_intel_encoder(connector->encoder)->connectors_active = false;
4355 }
4356 }
4357
4358 void intel_encoder_destroy(struct drm_encoder *encoder)
4359 {
4360 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4361
4362 drm_encoder_cleanup(encoder);
4363 kfree(intel_encoder);
4364 }
4365
4366 /* Simple dpms helper for encoders with just one connector, no cloning and only
4367 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4368 * state of the entire output pipe. */
4369 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4370 {
4371 if (mode == DRM_MODE_DPMS_ON) {
4372 encoder->connectors_active = true;
4373
4374 intel_crtc_update_dpms(encoder->base.crtc);
4375 } else {
4376 encoder->connectors_active = false;
4377
4378 intel_crtc_update_dpms(encoder->base.crtc);
4379 }
4380 }
4381
4382 /* Cross check the actual hw state with our own modeset state tracking (and it's
4383 * internal consistency). */
4384 static void intel_connector_check_state(struct intel_connector *connector)
4385 {
4386 if (connector->get_hw_state(connector)) {
4387 struct intel_encoder *encoder = connector->encoder;
4388 struct drm_crtc *crtc;
4389 bool encoder_enabled;
4390 enum pipe pipe;
4391
4392 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4393 connector->base.base.id,
4394 drm_get_connector_name(&connector->base));
4395
4396 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4397 "wrong connector dpms state\n");
4398 WARN(connector->base.encoder != &encoder->base,
4399 "active connector not linked to encoder\n");
4400 WARN(!encoder->connectors_active,
4401 "encoder->connectors_active not set\n");
4402
4403 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4404 WARN(!encoder_enabled, "encoder not enabled\n");
4405 if (WARN_ON(!encoder->base.crtc))
4406 return;
4407
4408 crtc = encoder->base.crtc;
4409
4410 WARN(!crtc->enabled, "crtc not enabled\n");
4411 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4412 WARN(pipe != to_intel_crtc(crtc)->pipe,
4413 "encoder active on the wrong pipe\n");
4414 }
4415 }
4416
4417 /* Even simpler default implementation, if there's really no special case to
4418 * consider. */
4419 void intel_connector_dpms(struct drm_connector *connector, int mode)
4420 {
4421 /* All the simple cases only support two dpms states. */
4422 if (mode != DRM_MODE_DPMS_ON)
4423 mode = DRM_MODE_DPMS_OFF;
4424
4425 if (mode == connector->dpms)
4426 return;
4427
4428 connector->dpms = mode;
4429
4430 /* Only need to change hw state when actually enabled */
4431 if (connector->encoder)
4432 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
4433
4434 intel_modeset_check_state(connector->dev);
4435 }
4436
4437 /* Simple connector->get_hw_state implementation for encoders that support only
4438 * one connector and no cloning and hence the encoder state determines the state
4439 * of the connector. */
4440 bool intel_connector_get_hw_state(struct intel_connector *connector)
4441 {
4442 enum pipe pipe = 0;
4443 struct intel_encoder *encoder = connector->encoder;
4444
4445 return encoder->get_hw_state(encoder, &pipe);
4446 }
4447
4448 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4449 struct intel_crtc_config *pipe_config)
4450 {
4451 struct drm_i915_private *dev_priv = dev->dev_private;
4452 struct intel_crtc *pipe_B_crtc =
4453 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4454
4455 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4456 pipe_name(pipe), pipe_config->fdi_lanes);
4457 if (pipe_config->fdi_lanes > 4) {
4458 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4459 pipe_name(pipe), pipe_config->fdi_lanes);
4460 return false;
4461 }
4462
4463 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4464 if (pipe_config->fdi_lanes > 2) {
4465 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4466 pipe_config->fdi_lanes);
4467 return false;
4468 } else {
4469 return true;
4470 }
4471 }
4472
4473 if (INTEL_INFO(dev)->num_pipes == 2)
4474 return true;
4475
4476 /* Ivybridge 3 pipe is really complicated */
4477 switch (pipe) {
4478 case PIPE_A:
4479 return true;
4480 case PIPE_B:
4481 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4482 pipe_config->fdi_lanes > 2) {
4483 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4484 pipe_name(pipe), pipe_config->fdi_lanes);
4485 return false;
4486 }
4487 return true;
4488 case PIPE_C:
4489 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4490 pipe_B_crtc->config.fdi_lanes <= 2) {
4491 if (pipe_config->fdi_lanes > 2) {
4492 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4493 pipe_name(pipe), pipe_config->fdi_lanes);
4494 return false;
4495 }
4496 } else {
4497 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4498 return false;
4499 }
4500 return true;
4501 default:
4502 BUG();
4503 }
4504 }
4505
4506 #define RETRY 1
4507 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4508 struct intel_crtc_config *pipe_config)
4509 {
4510 struct drm_device *dev = intel_crtc->base.dev;
4511 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4512 int lane, link_bw, fdi_dotclock;
4513 bool setup_ok, needs_recompute = false;
4514
4515 retry:
4516 /* FDI is a binary signal running at ~2.7GHz, encoding
4517 * each output octet as 10 bits. The actual frequency
4518 * is stored as a divider into a 100MHz clock, and the
4519 * mode pixel clock is stored in units of 1KHz.
4520 * Hence the bw of each lane in terms of the mode signal
4521 * is:
4522 */
4523 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4524
4525 fdi_dotclock = adjusted_mode->crtc_clock;
4526
4527 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4528 pipe_config->pipe_bpp);
4529
4530 pipe_config->fdi_lanes = lane;
4531
4532 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4533 link_bw, &pipe_config->fdi_m_n);
4534
4535 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4536 intel_crtc->pipe, pipe_config);
4537 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4538 pipe_config->pipe_bpp -= 2*3;
4539 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4540 pipe_config->pipe_bpp);
4541 needs_recompute = true;
4542 pipe_config->bw_constrained = true;
4543
4544 goto retry;
4545 }
4546
4547 if (needs_recompute)
4548 return RETRY;
4549
4550 return setup_ok ? 0 : -EINVAL;
4551 }
4552
4553 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4554 struct intel_crtc_config *pipe_config)
4555 {
4556 pipe_config->ips_enabled = i915_enable_ips &&
4557 hsw_crtc_supports_ips(crtc) &&
4558 pipe_config->pipe_bpp <= 24;
4559 }
4560
4561 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4562 struct intel_crtc_config *pipe_config)
4563 {
4564 struct drm_device *dev = crtc->base.dev;
4565 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4566
4567 /* FIXME should check pixel clock limits on all platforms */
4568 if (INTEL_INFO(dev)->gen < 4) {
4569 struct drm_i915_private *dev_priv = dev->dev_private;
4570 int clock_limit =
4571 dev_priv->display.get_display_clock_speed(dev);
4572
4573 /*
4574 * Enable pixel doubling when the dot clock
4575 * is > 90% of the (display) core speed.
4576 *
4577 * GDG double wide on either pipe,
4578 * otherwise pipe A only.
4579 */
4580 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
4581 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
4582 clock_limit *= 2;
4583 pipe_config->double_wide = true;
4584 }
4585
4586 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
4587 return -EINVAL;
4588 }
4589
4590 /*
4591 * Pipe horizontal size must be even in:
4592 * - DVO ganged mode
4593 * - LVDS dual channel mode
4594 * - Double wide pipe
4595 */
4596 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4597 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4598 pipe_config->pipe_src_w &= ~1;
4599
4600 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4601 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4602 */
4603 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4604 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4605 return -EINVAL;
4606
4607 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4608 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4609 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4610 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4611 * for lvds. */
4612 pipe_config->pipe_bpp = 8*3;
4613 }
4614
4615 if (HAS_IPS(dev))
4616 hsw_compute_ips_config(crtc, pipe_config);
4617
4618 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4619 * clock survives for now. */
4620 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4621 pipe_config->shared_dpll = crtc->config.shared_dpll;
4622
4623 if (pipe_config->has_pch_encoder)
4624 return ironlake_fdi_compute_config(crtc, pipe_config);
4625
4626 return 0;
4627 }
4628
4629 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4630 {
4631 return 400000; /* FIXME */
4632 }
4633
4634 static int i945_get_display_clock_speed(struct drm_device *dev)
4635 {
4636 return 400000;
4637 }
4638
4639 static int i915_get_display_clock_speed(struct drm_device *dev)
4640 {
4641 return 333000;
4642 }
4643
4644 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4645 {
4646 return 200000;
4647 }
4648
4649 static int pnv_get_display_clock_speed(struct drm_device *dev)
4650 {
4651 u16 gcfgc = 0;
4652
4653 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4654
4655 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4656 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4657 return 267000;
4658 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4659 return 333000;
4660 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4661 return 444000;
4662 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4663 return 200000;
4664 default:
4665 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4666 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4667 return 133000;
4668 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4669 return 167000;
4670 }
4671 }
4672
4673 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4674 {
4675 u16 gcfgc = 0;
4676
4677 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4678
4679 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4680 return 133000;
4681 else {
4682 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4683 case GC_DISPLAY_CLOCK_333_MHZ:
4684 return 333000;
4685 default:
4686 case GC_DISPLAY_CLOCK_190_200_MHZ:
4687 return 190000;
4688 }
4689 }
4690 }
4691
4692 static int i865_get_display_clock_speed(struct drm_device *dev)
4693 {
4694 return 266000;
4695 }
4696
4697 static int i855_get_display_clock_speed(struct drm_device *dev)
4698 {
4699 u16 hpllcc = 0;
4700 /* Assume that the hardware is in the high speed state. This
4701 * should be the default.
4702 */
4703 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4704 case GC_CLOCK_133_200:
4705 case GC_CLOCK_100_200:
4706 return 200000;
4707 case GC_CLOCK_166_250:
4708 return 250000;
4709 case GC_CLOCK_100_133:
4710 return 133000;
4711 }
4712
4713 /* Shouldn't happen */
4714 return 0;
4715 }
4716
4717 static int i830_get_display_clock_speed(struct drm_device *dev)
4718 {
4719 return 133000;
4720 }
4721
4722 static void
4723 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4724 {
4725 while (*num > DATA_LINK_M_N_MASK ||
4726 *den > DATA_LINK_M_N_MASK) {
4727 *num >>= 1;
4728 *den >>= 1;
4729 }
4730 }
4731
4732 static void compute_m_n(unsigned int m, unsigned int n,
4733 uint32_t *ret_m, uint32_t *ret_n)
4734 {
4735 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4736 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4737 intel_reduce_m_n_ratio(ret_m, ret_n);
4738 }
4739
4740 void
4741 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4742 int pixel_clock, int link_clock,
4743 struct intel_link_m_n *m_n)
4744 {
4745 m_n->tu = 64;
4746
4747 compute_m_n(bits_per_pixel * pixel_clock,
4748 link_clock * nlanes * 8,
4749 &m_n->gmch_m, &m_n->gmch_n);
4750
4751 compute_m_n(pixel_clock, link_clock,
4752 &m_n->link_m, &m_n->link_n);
4753 }
4754
4755 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4756 {
4757 if (i915_panel_use_ssc >= 0)
4758 return i915_panel_use_ssc != 0;
4759 return dev_priv->vbt.lvds_use_ssc
4760 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4761 }
4762
4763 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4764 {
4765 struct drm_device *dev = crtc->dev;
4766 struct drm_i915_private *dev_priv = dev->dev_private;
4767 int refclk;
4768
4769 if (IS_VALLEYVIEW(dev)) {
4770 refclk = 100000;
4771 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4772 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4773 refclk = dev_priv->vbt.lvds_ssc_freq;
4774 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
4775 } else if (!IS_GEN2(dev)) {
4776 refclk = 96000;
4777 } else {
4778 refclk = 48000;
4779 }
4780
4781 return refclk;
4782 }
4783
4784 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4785 {
4786 return (1 << dpll->n) << 16 | dpll->m2;
4787 }
4788
4789 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4790 {
4791 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4792 }
4793
4794 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4795 intel_clock_t *reduced_clock)
4796 {
4797 struct drm_device *dev = crtc->base.dev;
4798 struct drm_i915_private *dev_priv = dev->dev_private;
4799 int pipe = crtc->pipe;
4800 u32 fp, fp2 = 0;
4801
4802 if (IS_PINEVIEW(dev)) {
4803 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4804 if (reduced_clock)
4805 fp2 = pnv_dpll_compute_fp(reduced_clock);
4806 } else {
4807 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4808 if (reduced_clock)
4809 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4810 }
4811
4812 I915_WRITE(FP0(pipe), fp);
4813 crtc->config.dpll_hw_state.fp0 = fp;
4814
4815 crtc->lowfreq_avail = false;
4816 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4817 reduced_clock && i915_powersave) {
4818 I915_WRITE(FP1(pipe), fp2);
4819 crtc->config.dpll_hw_state.fp1 = fp2;
4820 crtc->lowfreq_avail = true;
4821 } else {
4822 I915_WRITE(FP1(pipe), fp);
4823 crtc->config.dpll_hw_state.fp1 = fp;
4824 }
4825 }
4826
4827 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4828 pipe)
4829 {
4830 u32 reg_val;
4831
4832 /*
4833 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4834 * and set it to a reasonable value instead.
4835 */
4836 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4837 reg_val &= 0xffffff00;
4838 reg_val |= 0x00000030;
4839 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4840
4841 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4842 reg_val &= 0x8cffffff;
4843 reg_val = 0x8c000000;
4844 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4845
4846 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4847 reg_val &= 0xffffff00;
4848 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4849
4850 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4851 reg_val &= 0x00ffffff;
4852 reg_val |= 0xb0000000;
4853 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4854 }
4855
4856 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4857 struct intel_link_m_n *m_n)
4858 {
4859 struct drm_device *dev = crtc->base.dev;
4860 struct drm_i915_private *dev_priv = dev->dev_private;
4861 int pipe = crtc->pipe;
4862
4863 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4864 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4865 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4866 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4867 }
4868
4869 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4870 struct intel_link_m_n *m_n)
4871 {
4872 struct drm_device *dev = crtc->base.dev;
4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874 int pipe = crtc->pipe;
4875 enum transcoder transcoder = crtc->config.cpu_transcoder;
4876
4877 if (INTEL_INFO(dev)->gen >= 5) {
4878 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4879 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4880 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4881 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4882 } else {
4883 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4884 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4885 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4886 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4887 }
4888 }
4889
4890 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4891 {
4892 if (crtc->config.has_pch_encoder)
4893 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4894 else
4895 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4896 }
4897
4898 static void vlv_update_pll(struct intel_crtc *crtc)
4899 {
4900 struct drm_device *dev = crtc->base.dev;
4901 struct drm_i915_private *dev_priv = dev->dev_private;
4902 int pipe = crtc->pipe;
4903 u32 dpll, mdiv;
4904 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4905 u32 coreclk, reg_val, dpll_md;
4906
4907 mutex_lock(&dev_priv->dpio_lock);
4908
4909 bestn = crtc->config.dpll.n;
4910 bestm1 = crtc->config.dpll.m1;
4911 bestm2 = crtc->config.dpll.m2;
4912 bestp1 = crtc->config.dpll.p1;
4913 bestp2 = crtc->config.dpll.p2;
4914
4915 /* See eDP HDMI DPIO driver vbios notes doc */
4916
4917 /* PLL B needs special handling */
4918 if (pipe)
4919 vlv_pllb_recal_opamp(dev_priv, pipe);
4920
4921 /* Set up Tx target for periodic Rcomp update */
4922 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4923
4924 /* Disable target IRef on PLL */
4925 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4926 reg_val &= 0x00ffffff;
4927 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4928
4929 /* Disable fast lock */
4930 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4931
4932 /* Set idtafcrecal before PLL is enabled */
4933 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4934 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4935 mdiv |= ((bestn << DPIO_N_SHIFT));
4936 mdiv |= (1 << DPIO_K_SHIFT);
4937
4938 /*
4939 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4940 * but we don't support that).
4941 * Note: don't use the DAC post divider as it seems unstable.
4942 */
4943 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4944 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4945
4946 mdiv |= DPIO_ENABLE_CALIBRATION;
4947 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4948
4949 /* Set HBR and RBR LPF coefficients */
4950 if (crtc->config.port_clock == 162000 ||
4951 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4952 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4954 0x009f0003);
4955 else
4956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4957 0x00d0000f);
4958
4959 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4960 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4961 /* Use SSC source */
4962 if (!pipe)
4963 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4964 0x0df40000);
4965 else
4966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4967 0x0df70000);
4968 } else { /* HDMI or VGA */
4969 /* Use bend source */
4970 if (!pipe)
4971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4972 0x0df70000);
4973 else
4974 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4975 0x0df40000);
4976 }
4977
4978 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4979 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4980 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4981 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4982 coreclk |= 0x01000000;
4983 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4984
4985 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4986
4987 /* Enable DPIO clock input */
4988 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4989 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4990 /* We should never disable this, set it here for state tracking */
4991 if (pipe == PIPE_B)
4992 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4993 dpll |= DPLL_VCO_ENABLE;
4994 crtc->config.dpll_hw_state.dpll = dpll;
4995
4996 dpll_md = (crtc->config.pixel_multiplier - 1)
4997 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4998 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4999
5000 if (crtc->config.has_dp_encoder)
5001 intel_dp_set_m_n(crtc);
5002
5003 mutex_unlock(&dev_priv->dpio_lock);
5004 }
5005
5006 static void i9xx_update_pll(struct intel_crtc *crtc,
5007 intel_clock_t *reduced_clock,
5008 int num_connectors)
5009 {
5010 struct drm_device *dev = crtc->base.dev;
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012 u32 dpll;
5013 bool is_sdvo;
5014 struct dpll *clock = &crtc->config.dpll;
5015
5016 i9xx_update_pll_dividers(crtc, reduced_clock);
5017
5018 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5019 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5020
5021 dpll = DPLL_VGA_MODE_DIS;
5022
5023 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5024 dpll |= DPLLB_MODE_LVDS;
5025 else
5026 dpll |= DPLLB_MODE_DAC_SERIAL;
5027
5028 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5029 dpll |= (crtc->config.pixel_multiplier - 1)
5030 << SDVO_MULTIPLIER_SHIFT_HIRES;
5031 }
5032
5033 if (is_sdvo)
5034 dpll |= DPLL_SDVO_HIGH_SPEED;
5035
5036 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5037 dpll |= DPLL_SDVO_HIGH_SPEED;
5038
5039 /* compute bitmask from p1 value */
5040 if (IS_PINEVIEW(dev))
5041 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5042 else {
5043 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5044 if (IS_G4X(dev) && reduced_clock)
5045 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5046 }
5047 switch (clock->p2) {
5048 case 5:
5049 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5050 break;
5051 case 7:
5052 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5053 break;
5054 case 10:
5055 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5056 break;
5057 case 14:
5058 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5059 break;
5060 }
5061 if (INTEL_INFO(dev)->gen >= 4)
5062 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5063
5064 if (crtc->config.sdvo_tv_clock)
5065 dpll |= PLL_REF_INPUT_TVCLKINBC;
5066 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5067 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5068 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5069 else
5070 dpll |= PLL_REF_INPUT_DREFCLK;
5071
5072 dpll |= DPLL_VCO_ENABLE;
5073 crtc->config.dpll_hw_state.dpll = dpll;
5074
5075 if (INTEL_INFO(dev)->gen >= 4) {
5076 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5077 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5078 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5079 }
5080
5081 if (crtc->config.has_dp_encoder)
5082 intel_dp_set_m_n(crtc);
5083 }
5084
5085 static void i8xx_update_pll(struct intel_crtc *crtc,
5086 intel_clock_t *reduced_clock,
5087 int num_connectors)
5088 {
5089 struct drm_device *dev = crtc->base.dev;
5090 struct drm_i915_private *dev_priv = dev->dev_private;
5091 u32 dpll;
5092 struct dpll *clock = &crtc->config.dpll;
5093
5094 i9xx_update_pll_dividers(crtc, reduced_clock);
5095
5096 dpll = DPLL_VGA_MODE_DIS;
5097
5098 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5099 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5100 } else {
5101 if (clock->p1 == 2)
5102 dpll |= PLL_P1_DIVIDE_BY_TWO;
5103 else
5104 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5105 if (clock->p2 == 4)
5106 dpll |= PLL_P2_DIVIDE_BY_4;
5107 }
5108
5109 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5110 dpll |= DPLL_DVO_2X_MODE;
5111
5112 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5113 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5114 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5115 else
5116 dpll |= PLL_REF_INPUT_DREFCLK;
5117
5118 dpll |= DPLL_VCO_ENABLE;
5119 crtc->config.dpll_hw_state.dpll = dpll;
5120 }
5121
5122 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5123 {
5124 struct drm_device *dev = intel_crtc->base.dev;
5125 struct drm_i915_private *dev_priv = dev->dev_private;
5126 enum pipe pipe = intel_crtc->pipe;
5127 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5128 struct drm_display_mode *adjusted_mode =
5129 &intel_crtc->config.adjusted_mode;
5130 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
5131
5132 /* We need to be careful not to changed the adjusted mode, for otherwise
5133 * the hw state checker will get angry at the mismatch. */
5134 crtc_vtotal = adjusted_mode->crtc_vtotal;
5135 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5136
5137 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5138 /* the chip adds 2 halflines automatically */
5139 crtc_vtotal -= 1;
5140 crtc_vblank_end -= 1;
5141 vsyncshift = adjusted_mode->crtc_hsync_start
5142 - adjusted_mode->crtc_htotal / 2;
5143 } else {
5144 vsyncshift = 0;
5145 }
5146
5147 if (INTEL_INFO(dev)->gen > 3)
5148 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5149
5150 I915_WRITE(HTOTAL(cpu_transcoder),
5151 (adjusted_mode->crtc_hdisplay - 1) |
5152 ((adjusted_mode->crtc_htotal - 1) << 16));
5153 I915_WRITE(HBLANK(cpu_transcoder),
5154 (adjusted_mode->crtc_hblank_start - 1) |
5155 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5156 I915_WRITE(HSYNC(cpu_transcoder),
5157 (adjusted_mode->crtc_hsync_start - 1) |
5158 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5159
5160 I915_WRITE(VTOTAL(cpu_transcoder),
5161 (adjusted_mode->crtc_vdisplay - 1) |
5162 ((crtc_vtotal - 1) << 16));
5163 I915_WRITE(VBLANK(cpu_transcoder),
5164 (adjusted_mode->crtc_vblank_start - 1) |
5165 ((crtc_vblank_end - 1) << 16));
5166 I915_WRITE(VSYNC(cpu_transcoder),
5167 (adjusted_mode->crtc_vsync_start - 1) |
5168 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5169
5170 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5171 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5172 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5173 * bits. */
5174 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5175 (pipe == PIPE_B || pipe == PIPE_C))
5176 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5177
5178 /* pipesrc controls the size that is scaled from, which should
5179 * always be the user's requested size.
5180 */
5181 I915_WRITE(PIPESRC(pipe),
5182 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5183 (intel_crtc->config.pipe_src_h - 1));
5184 }
5185
5186 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5187 struct intel_crtc_config *pipe_config)
5188 {
5189 struct drm_device *dev = crtc->base.dev;
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5192 uint32_t tmp;
5193
5194 tmp = I915_READ(HTOTAL(cpu_transcoder));
5195 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5196 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5197 tmp = I915_READ(HBLANK(cpu_transcoder));
5198 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5199 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5200 tmp = I915_READ(HSYNC(cpu_transcoder));
5201 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5202 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5203
5204 tmp = I915_READ(VTOTAL(cpu_transcoder));
5205 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5206 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5207 tmp = I915_READ(VBLANK(cpu_transcoder));
5208 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5209 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5210 tmp = I915_READ(VSYNC(cpu_transcoder));
5211 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5212 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5213
5214 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5215 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5216 pipe_config->adjusted_mode.crtc_vtotal += 1;
5217 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5218 }
5219
5220 tmp = I915_READ(PIPESRC(crtc->pipe));
5221 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5222 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5223
5224 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5225 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5226 }
5227
5228 static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
5229 struct intel_crtc_config *pipe_config)
5230 {
5231 struct drm_crtc *crtc = &intel_crtc->base;
5232
5233 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5234 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
5235 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5236 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5237
5238 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5239 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5240 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5241 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5242
5243 crtc->mode.flags = pipe_config->adjusted_mode.flags;
5244
5245 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
5246 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
5247 }
5248
5249 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5250 {
5251 struct drm_device *dev = intel_crtc->base.dev;
5252 struct drm_i915_private *dev_priv = dev->dev_private;
5253 uint32_t pipeconf;
5254
5255 pipeconf = 0;
5256
5257 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5258 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5259 pipeconf |= PIPECONF_ENABLE;
5260
5261 if (intel_crtc->config.double_wide)
5262 pipeconf |= PIPECONF_DOUBLE_WIDE;
5263
5264 /* only g4x and later have fancy bpc/dither controls */
5265 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5266 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5267 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5268 pipeconf |= PIPECONF_DITHER_EN |
5269 PIPECONF_DITHER_TYPE_SP;
5270
5271 switch (intel_crtc->config.pipe_bpp) {
5272 case 18:
5273 pipeconf |= PIPECONF_6BPC;
5274 break;
5275 case 24:
5276 pipeconf |= PIPECONF_8BPC;
5277 break;
5278 case 30:
5279 pipeconf |= PIPECONF_10BPC;
5280 break;
5281 default:
5282 /* Case prevented by intel_choose_pipe_bpp_dither. */
5283 BUG();
5284 }
5285 }
5286
5287 if (HAS_PIPE_CXSR(dev)) {
5288 if (intel_crtc->lowfreq_avail) {
5289 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5290 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5291 } else {
5292 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5293 }
5294 }
5295
5296 if (!IS_GEN2(dev) &&
5297 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5298 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5299 else
5300 pipeconf |= PIPECONF_PROGRESSIVE;
5301
5302 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5303 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5304
5305 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5306 POSTING_READ(PIPECONF(intel_crtc->pipe));
5307 }
5308
5309 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5310 int x, int y,
5311 struct drm_framebuffer *fb)
5312 {
5313 struct drm_device *dev = crtc->dev;
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5316 int pipe = intel_crtc->pipe;
5317 int plane = intel_crtc->plane;
5318 int refclk, num_connectors = 0;
5319 intel_clock_t clock, reduced_clock;
5320 u32 dspcntr;
5321 bool ok, has_reduced_clock = false;
5322 bool is_lvds = false, is_dsi = false;
5323 struct intel_encoder *encoder;
5324 const intel_limit_t *limit;
5325 int ret;
5326
5327 for_each_encoder_on_crtc(dev, crtc, encoder) {
5328 switch (encoder->type) {
5329 case INTEL_OUTPUT_LVDS:
5330 is_lvds = true;
5331 break;
5332 case INTEL_OUTPUT_DSI:
5333 is_dsi = true;
5334 break;
5335 }
5336
5337 num_connectors++;
5338 }
5339
5340 if (is_dsi)
5341 goto skip_dpll;
5342
5343 if (!intel_crtc->config.clock_set) {
5344 refclk = i9xx_get_refclk(crtc, num_connectors);
5345
5346 /*
5347 * Returns a set of divisors for the desired target clock with
5348 * the given refclk, or FALSE. The returned values represent
5349 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5350 * 2) / p1 / p2.
5351 */
5352 limit = intel_limit(crtc, refclk);
5353 ok = dev_priv->display.find_dpll(limit, crtc,
5354 intel_crtc->config.port_clock,
5355 refclk, NULL, &clock);
5356 if (!ok) {
5357 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5358 return -EINVAL;
5359 }
5360
5361 if (is_lvds && dev_priv->lvds_downclock_avail) {
5362 /*
5363 * Ensure we match the reduced clock's P to the target
5364 * clock. If the clocks don't match, we can't switch
5365 * the display clock by using the FP0/FP1. In such case
5366 * we will disable the LVDS downclock feature.
5367 */
5368 has_reduced_clock =
5369 dev_priv->display.find_dpll(limit, crtc,
5370 dev_priv->lvds_downclock,
5371 refclk, &clock,
5372 &reduced_clock);
5373 }
5374 /* Compat-code for transition, will disappear. */
5375 intel_crtc->config.dpll.n = clock.n;
5376 intel_crtc->config.dpll.m1 = clock.m1;
5377 intel_crtc->config.dpll.m2 = clock.m2;
5378 intel_crtc->config.dpll.p1 = clock.p1;
5379 intel_crtc->config.dpll.p2 = clock.p2;
5380 }
5381
5382 if (IS_GEN2(dev)) {
5383 i8xx_update_pll(intel_crtc,
5384 has_reduced_clock ? &reduced_clock : NULL,
5385 num_connectors);
5386 } else if (IS_VALLEYVIEW(dev)) {
5387 vlv_update_pll(intel_crtc);
5388 } else {
5389 i9xx_update_pll(intel_crtc,
5390 has_reduced_clock ? &reduced_clock : NULL,
5391 num_connectors);
5392 }
5393
5394 skip_dpll:
5395 /* Set up the display plane register */
5396 dspcntr = DISPPLANE_GAMMA_ENABLE;
5397
5398 if (!IS_VALLEYVIEW(dev)) {
5399 if (pipe == 0)
5400 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5401 else
5402 dspcntr |= DISPPLANE_SEL_PIPE_B;
5403 }
5404
5405 intel_set_pipe_timings(intel_crtc);
5406
5407 /* pipesrc and dspsize control the size that is scaled from,
5408 * which should always be the user's requested size.
5409 */
5410 I915_WRITE(DSPSIZE(plane),
5411 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5412 (intel_crtc->config.pipe_src_w - 1));
5413 I915_WRITE(DSPPOS(plane), 0);
5414
5415 i9xx_set_pipeconf(intel_crtc);
5416
5417 I915_WRITE(DSPCNTR(plane), dspcntr);
5418 POSTING_READ(DSPCNTR(plane));
5419
5420 ret = intel_pipe_set_base(crtc, x, y, fb);
5421
5422 return ret;
5423 }
5424
5425 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5426 struct intel_crtc_config *pipe_config)
5427 {
5428 struct drm_device *dev = crtc->base.dev;
5429 struct drm_i915_private *dev_priv = dev->dev_private;
5430 uint32_t tmp;
5431
5432 tmp = I915_READ(PFIT_CONTROL);
5433 if (!(tmp & PFIT_ENABLE))
5434 return;
5435
5436 /* Check whether the pfit is attached to our pipe. */
5437 if (INTEL_INFO(dev)->gen < 4) {
5438 if (crtc->pipe != PIPE_B)
5439 return;
5440 } else {
5441 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5442 return;
5443 }
5444
5445 pipe_config->gmch_pfit.control = tmp;
5446 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5447 if (INTEL_INFO(dev)->gen < 5)
5448 pipe_config->gmch_pfit.lvds_border_bits =
5449 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5450 }
5451
5452 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5453 struct intel_crtc_config *pipe_config)
5454 {
5455 struct drm_device *dev = crtc->base.dev;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457 int pipe = pipe_config->cpu_transcoder;
5458 intel_clock_t clock;
5459 u32 mdiv;
5460 int refclk = 100000;
5461
5462 mutex_lock(&dev_priv->dpio_lock);
5463 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5464 mutex_unlock(&dev_priv->dpio_lock);
5465
5466 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5467 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5468 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5469 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5470 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5471
5472 vlv_clock(refclk, &clock);
5473
5474 /* clock.dot is the fast clock */
5475 pipe_config->port_clock = clock.dot / 5;
5476 }
5477
5478 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5479 struct intel_crtc_config *pipe_config)
5480 {
5481 struct drm_device *dev = crtc->base.dev;
5482 struct drm_i915_private *dev_priv = dev->dev_private;
5483 uint32_t tmp;
5484
5485 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
5486 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5487
5488 tmp = I915_READ(PIPECONF(crtc->pipe));
5489 if (!(tmp & PIPECONF_ENABLE))
5490 return false;
5491
5492 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5493 switch (tmp & PIPECONF_BPC_MASK) {
5494 case PIPECONF_6BPC:
5495 pipe_config->pipe_bpp = 18;
5496 break;
5497 case PIPECONF_8BPC:
5498 pipe_config->pipe_bpp = 24;
5499 break;
5500 case PIPECONF_10BPC:
5501 pipe_config->pipe_bpp = 30;
5502 break;
5503 default:
5504 break;
5505 }
5506 }
5507
5508 if (INTEL_INFO(dev)->gen < 4)
5509 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5510
5511 intel_get_pipe_timings(crtc, pipe_config);
5512
5513 i9xx_get_pfit_config(crtc, pipe_config);
5514
5515 if (INTEL_INFO(dev)->gen >= 4) {
5516 tmp = I915_READ(DPLL_MD(crtc->pipe));
5517 pipe_config->pixel_multiplier =
5518 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5519 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5520 pipe_config->dpll_hw_state.dpll_md = tmp;
5521 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5522 tmp = I915_READ(DPLL(crtc->pipe));
5523 pipe_config->pixel_multiplier =
5524 ((tmp & SDVO_MULTIPLIER_MASK)
5525 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5526 } else {
5527 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5528 * port and will be fixed up in the encoder->get_config
5529 * function. */
5530 pipe_config->pixel_multiplier = 1;
5531 }
5532 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5533 if (!IS_VALLEYVIEW(dev)) {
5534 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5535 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
5536 } else {
5537 /* Mask out read-only status bits. */
5538 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5539 DPLL_PORTC_READY_MASK |
5540 DPLL_PORTB_READY_MASK);
5541 }
5542
5543 if (IS_VALLEYVIEW(dev))
5544 vlv_crtc_clock_get(crtc, pipe_config);
5545 else
5546 i9xx_crtc_clock_get(crtc, pipe_config);
5547
5548 return true;
5549 }
5550
5551 static void ironlake_init_pch_refclk(struct drm_device *dev)
5552 {
5553 struct drm_i915_private *dev_priv = dev->dev_private;
5554 struct drm_mode_config *mode_config = &dev->mode_config;
5555 struct intel_encoder *encoder;
5556 u32 val, final;
5557 bool has_lvds = false;
5558 bool has_cpu_edp = false;
5559 bool has_panel = false;
5560 bool has_ck505 = false;
5561 bool can_ssc = false;
5562
5563 /* We need to take the global config into account */
5564 list_for_each_entry(encoder, &mode_config->encoder_list,
5565 base.head) {
5566 switch (encoder->type) {
5567 case INTEL_OUTPUT_LVDS:
5568 has_panel = true;
5569 has_lvds = true;
5570 break;
5571 case INTEL_OUTPUT_EDP:
5572 has_panel = true;
5573 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5574 has_cpu_edp = true;
5575 break;
5576 }
5577 }
5578
5579 if (HAS_PCH_IBX(dev)) {
5580 has_ck505 = dev_priv->vbt.display_clock_mode;
5581 can_ssc = has_ck505;
5582 } else {
5583 has_ck505 = false;
5584 can_ssc = true;
5585 }
5586
5587 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5588 has_panel, has_lvds, has_ck505);
5589
5590 /* Ironlake: try to setup display ref clock before DPLL
5591 * enabling. This is only under driver's control after
5592 * PCH B stepping, previous chipset stepping should be
5593 * ignoring this setting.
5594 */
5595 val = I915_READ(PCH_DREF_CONTROL);
5596
5597 /* As we must carefully and slowly disable/enable each source in turn,
5598 * compute the final state we want first and check if we need to
5599 * make any changes at all.
5600 */
5601 final = val;
5602 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5603 if (has_ck505)
5604 final |= DREF_NONSPREAD_CK505_ENABLE;
5605 else
5606 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5607
5608 final &= ~DREF_SSC_SOURCE_MASK;
5609 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5610 final &= ~DREF_SSC1_ENABLE;
5611
5612 if (has_panel) {
5613 final |= DREF_SSC_SOURCE_ENABLE;
5614
5615 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5616 final |= DREF_SSC1_ENABLE;
5617
5618 if (has_cpu_edp) {
5619 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5620 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5621 else
5622 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5623 } else
5624 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5625 } else {
5626 final |= DREF_SSC_SOURCE_DISABLE;
5627 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5628 }
5629
5630 if (final == val)
5631 return;
5632
5633 /* Always enable nonspread source */
5634 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5635
5636 if (has_ck505)
5637 val |= DREF_NONSPREAD_CK505_ENABLE;
5638 else
5639 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5640
5641 if (has_panel) {
5642 val &= ~DREF_SSC_SOURCE_MASK;
5643 val |= DREF_SSC_SOURCE_ENABLE;
5644
5645 /* SSC must be turned on before enabling the CPU output */
5646 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5647 DRM_DEBUG_KMS("Using SSC on panel\n");
5648 val |= DREF_SSC1_ENABLE;
5649 } else
5650 val &= ~DREF_SSC1_ENABLE;
5651
5652 /* Get SSC going before enabling the outputs */
5653 I915_WRITE(PCH_DREF_CONTROL, val);
5654 POSTING_READ(PCH_DREF_CONTROL);
5655 udelay(200);
5656
5657 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5658
5659 /* Enable CPU source on CPU attached eDP */
5660 if (has_cpu_edp) {
5661 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5662 DRM_DEBUG_KMS("Using SSC on eDP\n");
5663 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5664 }
5665 else
5666 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5667 } else
5668 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5669
5670 I915_WRITE(PCH_DREF_CONTROL, val);
5671 POSTING_READ(PCH_DREF_CONTROL);
5672 udelay(200);
5673 } else {
5674 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5675
5676 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5677
5678 /* Turn off CPU output */
5679 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5680
5681 I915_WRITE(PCH_DREF_CONTROL, val);
5682 POSTING_READ(PCH_DREF_CONTROL);
5683 udelay(200);
5684
5685 /* Turn off the SSC source */
5686 val &= ~DREF_SSC_SOURCE_MASK;
5687 val |= DREF_SSC_SOURCE_DISABLE;
5688
5689 /* Turn off SSC1 */
5690 val &= ~DREF_SSC1_ENABLE;
5691
5692 I915_WRITE(PCH_DREF_CONTROL, val);
5693 POSTING_READ(PCH_DREF_CONTROL);
5694 udelay(200);
5695 }
5696
5697 BUG_ON(val != final);
5698 }
5699
5700 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
5701 {
5702 uint32_t tmp;
5703
5704 tmp = I915_READ(SOUTH_CHICKEN2);
5705 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5706 I915_WRITE(SOUTH_CHICKEN2, tmp);
5707
5708 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5709 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5710 DRM_ERROR("FDI mPHY reset assert timeout\n");
5711
5712 tmp = I915_READ(SOUTH_CHICKEN2);
5713 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5714 I915_WRITE(SOUTH_CHICKEN2, tmp);
5715
5716 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5717 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5718 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5719 }
5720
5721 /* WaMPhyProgramming:hsw */
5722 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5723 {
5724 uint32_t tmp;
5725
5726 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5727 tmp &= ~(0xFF << 24);
5728 tmp |= (0x12 << 24);
5729 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5730
5731 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5732 tmp |= (1 << 11);
5733 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5734
5735 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5736 tmp |= (1 << 11);
5737 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5738
5739 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5740 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5741 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5742
5743 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5744 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5745 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5746
5747 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5748 tmp &= ~(7 << 13);
5749 tmp |= (5 << 13);
5750 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5751
5752 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5753 tmp &= ~(7 << 13);
5754 tmp |= (5 << 13);
5755 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5756
5757 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5758 tmp &= ~0xFF;
5759 tmp |= 0x1C;
5760 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5761
5762 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5763 tmp &= ~0xFF;
5764 tmp |= 0x1C;
5765 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5766
5767 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5768 tmp &= ~(0xFF << 16);
5769 tmp |= (0x1C << 16);
5770 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5771
5772 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5773 tmp &= ~(0xFF << 16);
5774 tmp |= (0x1C << 16);
5775 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5776
5777 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5778 tmp |= (1 << 27);
5779 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5780
5781 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5782 tmp |= (1 << 27);
5783 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5784
5785 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5786 tmp &= ~(0xF << 28);
5787 tmp |= (4 << 28);
5788 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5789
5790 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5791 tmp &= ~(0xF << 28);
5792 tmp |= (4 << 28);
5793 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5794 }
5795
5796 /* Implements 3 different sequences from BSpec chapter "Display iCLK
5797 * Programming" based on the parameters passed:
5798 * - Sequence to enable CLKOUT_DP
5799 * - Sequence to enable CLKOUT_DP without spread
5800 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5801 */
5802 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5803 bool with_fdi)
5804 {
5805 struct drm_i915_private *dev_priv = dev->dev_private;
5806 uint32_t reg, tmp;
5807
5808 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5809 with_spread = true;
5810 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5811 with_fdi, "LP PCH doesn't have FDI\n"))
5812 with_fdi = false;
5813
5814 mutex_lock(&dev_priv->dpio_lock);
5815
5816 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5817 tmp &= ~SBI_SSCCTL_DISABLE;
5818 tmp |= SBI_SSCCTL_PATHALT;
5819 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5820
5821 udelay(24);
5822
5823 if (with_spread) {
5824 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5825 tmp &= ~SBI_SSCCTL_PATHALT;
5826 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5827
5828 if (with_fdi) {
5829 lpt_reset_fdi_mphy(dev_priv);
5830 lpt_program_fdi_mphy(dev_priv);
5831 }
5832 }
5833
5834 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5835 SBI_GEN0 : SBI_DBUFF0;
5836 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5837 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5838 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5839
5840 mutex_unlock(&dev_priv->dpio_lock);
5841 }
5842
5843 /* Sequence to disable CLKOUT_DP */
5844 static void lpt_disable_clkout_dp(struct drm_device *dev)
5845 {
5846 struct drm_i915_private *dev_priv = dev->dev_private;
5847 uint32_t reg, tmp;
5848
5849 mutex_lock(&dev_priv->dpio_lock);
5850
5851 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5852 SBI_GEN0 : SBI_DBUFF0;
5853 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5854 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5855 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5856
5857 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5858 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5859 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5860 tmp |= SBI_SSCCTL_PATHALT;
5861 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5862 udelay(32);
5863 }
5864 tmp |= SBI_SSCCTL_DISABLE;
5865 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5866 }
5867
5868 mutex_unlock(&dev_priv->dpio_lock);
5869 }
5870
5871 static void lpt_init_pch_refclk(struct drm_device *dev)
5872 {
5873 struct drm_mode_config *mode_config = &dev->mode_config;
5874 struct intel_encoder *encoder;
5875 bool has_vga = false;
5876
5877 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5878 switch (encoder->type) {
5879 case INTEL_OUTPUT_ANALOG:
5880 has_vga = true;
5881 break;
5882 }
5883 }
5884
5885 if (has_vga)
5886 lpt_enable_clkout_dp(dev, true, true);
5887 else
5888 lpt_disable_clkout_dp(dev);
5889 }
5890
5891 /*
5892 * Initialize reference clocks when the driver loads
5893 */
5894 void intel_init_pch_refclk(struct drm_device *dev)
5895 {
5896 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5897 ironlake_init_pch_refclk(dev);
5898 else if (HAS_PCH_LPT(dev))
5899 lpt_init_pch_refclk(dev);
5900 }
5901
5902 static int ironlake_get_refclk(struct drm_crtc *crtc)
5903 {
5904 struct drm_device *dev = crtc->dev;
5905 struct drm_i915_private *dev_priv = dev->dev_private;
5906 struct intel_encoder *encoder;
5907 int num_connectors = 0;
5908 bool is_lvds = false;
5909
5910 for_each_encoder_on_crtc(dev, crtc, encoder) {
5911 switch (encoder->type) {
5912 case INTEL_OUTPUT_LVDS:
5913 is_lvds = true;
5914 break;
5915 }
5916 num_connectors++;
5917 }
5918
5919 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5920 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
5921 dev_priv->vbt.lvds_ssc_freq);
5922 return dev_priv->vbt.lvds_ssc_freq;
5923 }
5924
5925 return 120000;
5926 }
5927
5928 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5929 {
5930 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5932 int pipe = intel_crtc->pipe;
5933 uint32_t val;
5934
5935 val = 0;
5936
5937 switch (intel_crtc->config.pipe_bpp) {
5938 case 18:
5939 val |= PIPECONF_6BPC;
5940 break;
5941 case 24:
5942 val |= PIPECONF_8BPC;
5943 break;
5944 case 30:
5945 val |= PIPECONF_10BPC;
5946 break;
5947 case 36:
5948 val |= PIPECONF_12BPC;
5949 break;
5950 default:
5951 /* Case prevented by intel_choose_pipe_bpp_dither. */
5952 BUG();
5953 }
5954
5955 if (intel_crtc->config.dither)
5956 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5957
5958 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5959 val |= PIPECONF_INTERLACED_ILK;
5960 else
5961 val |= PIPECONF_PROGRESSIVE;
5962
5963 if (intel_crtc->config.limited_color_range)
5964 val |= PIPECONF_COLOR_RANGE_SELECT;
5965
5966 I915_WRITE(PIPECONF(pipe), val);
5967 POSTING_READ(PIPECONF(pipe));
5968 }
5969
5970 /*
5971 * Set up the pipe CSC unit.
5972 *
5973 * Currently only full range RGB to limited range RGB conversion
5974 * is supported, but eventually this should handle various
5975 * RGB<->YCbCr scenarios as well.
5976 */
5977 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5978 {
5979 struct drm_device *dev = crtc->dev;
5980 struct drm_i915_private *dev_priv = dev->dev_private;
5981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5982 int pipe = intel_crtc->pipe;
5983 uint16_t coeff = 0x7800; /* 1.0 */
5984
5985 /*
5986 * TODO: Check what kind of values actually come out of the pipe
5987 * with these coeff/postoff values and adjust to get the best
5988 * accuracy. Perhaps we even need to take the bpc value into
5989 * consideration.
5990 */
5991
5992 if (intel_crtc->config.limited_color_range)
5993 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5994
5995 /*
5996 * GY/GU and RY/RU should be the other way around according
5997 * to BSpec, but reality doesn't agree. Just set them up in
5998 * a way that results in the correct picture.
5999 */
6000 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6001 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6002
6003 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6004 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6005
6006 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6007 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6008
6009 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6010 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6011 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6012
6013 if (INTEL_INFO(dev)->gen > 6) {
6014 uint16_t postoff = 0;
6015
6016 if (intel_crtc->config.limited_color_range)
6017 postoff = (16 * (1 << 13) / 255) & 0x1fff;
6018
6019 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6020 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6021 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6022
6023 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6024 } else {
6025 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6026
6027 if (intel_crtc->config.limited_color_range)
6028 mode |= CSC_BLACK_SCREEN_OFFSET;
6029
6030 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6031 }
6032 }
6033
6034 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6035 {
6036 struct drm_device *dev = crtc->dev;
6037 struct drm_i915_private *dev_priv = dev->dev_private;
6038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6039 enum pipe pipe = intel_crtc->pipe;
6040 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6041 uint32_t val;
6042
6043 val = 0;
6044
6045 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6046 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6047
6048 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6049 val |= PIPECONF_INTERLACED_ILK;
6050 else
6051 val |= PIPECONF_PROGRESSIVE;
6052
6053 I915_WRITE(PIPECONF(cpu_transcoder), val);
6054 POSTING_READ(PIPECONF(cpu_transcoder));
6055
6056 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6057 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6058
6059 if (IS_BROADWELL(dev)) {
6060 val = 0;
6061
6062 switch (intel_crtc->config.pipe_bpp) {
6063 case 18:
6064 val |= PIPEMISC_DITHER_6_BPC;
6065 break;
6066 case 24:
6067 val |= PIPEMISC_DITHER_8_BPC;
6068 break;
6069 case 30:
6070 val |= PIPEMISC_DITHER_10_BPC;
6071 break;
6072 case 36:
6073 val |= PIPEMISC_DITHER_12_BPC;
6074 break;
6075 default:
6076 /* Case prevented by pipe_config_set_bpp. */
6077 BUG();
6078 }
6079
6080 if (intel_crtc->config.dither)
6081 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6082
6083 I915_WRITE(PIPEMISC(pipe), val);
6084 }
6085 }
6086
6087 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6088 intel_clock_t *clock,
6089 bool *has_reduced_clock,
6090 intel_clock_t *reduced_clock)
6091 {
6092 struct drm_device *dev = crtc->dev;
6093 struct drm_i915_private *dev_priv = dev->dev_private;
6094 struct intel_encoder *intel_encoder;
6095 int refclk;
6096 const intel_limit_t *limit;
6097 bool ret, is_lvds = false;
6098
6099 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6100 switch (intel_encoder->type) {
6101 case INTEL_OUTPUT_LVDS:
6102 is_lvds = true;
6103 break;
6104 }
6105 }
6106
6107 refclk = ironlake_get_refclk(crtc);
6108
6109 /*
6110 * Returns a set of divisors for the desired target clock with the given
6111 * refclk, or FALSE. The returned values represent the clock equation:
6112 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6113 */
6114 limit = intel_limit(crtc, refclk);
6115 ret = dev_priv->display.find_dpll(limit, crtc,
6116 to_intel_crtc(crtc)->config.port_clock,
6117 refclk, NULL, clock);
6118 if (!ret)
6119 return false;
6120
6121 if (is_lvds && dev_priv->lvds_downclock_avail) {
6122 /*
6123 * Ensure we match the reduced clock's P to the target clock.
6124 * If the clocks don't match, we can't switch the display clock
6125 * by using the FP0/FP1. In such case we will disable the LVDS
6126 * downclock feature.
6127 */
6128 *has_reduced_clock =
6129 dev_priv->display.find_dpll(limit, crtc,
6130 dev_priv->lvds_downclock,
6131 refclk, clock,
6132 reduced_clock);
6133 }
6134
6135 return true;
6136 }
6137
6138 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6139 {
6140 /*
6141 * Account for spread spectrum to avoid
6142 * oversubscribing the link. Max center spread
6143 * is 2.5%; use 5% for safety's sake.
6144 */
6145 u32 bps = target_clock * bpp * 21 / 20;
6146 return bps / (link_bw * 8) + 1;
6147 }
6148
6149 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6150 {
6151 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6152 }
6153
6154 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6155 u32 *fp,
6156 intel_clock_t *reduced_clock, u32 *fp2)
6157 {
6158 struct drm_crtc *crtc = &intel_crtc->base;
6159 struct drm_device *dev = crtc->dev;
6160 struct drm_i915_private *dev_priv = dev->dev_private;
6161 struct intel_encoder *intel_encoder;
6162 uint32_t dpll;
6163 int factor, num_connectors = 0;
6164 bool is_lvds = false, is_sdvo = false;
6165
6166 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6167 switch (intel_encoder->type) {
6168 case INTEL_OUTPUT_LVDS:
6169 is_lvds = true;
6170 break;
6171 case INTEL_OUTPUT_SDVO:
6172 case INTEL_OUTPUT_HDMI:
6173 is_sdvo = true;
6174 break;
6175 }
6176
6177 num_connectors++;
6178 }
6179
6180 /* Enable autotuning of the PLL clock (if permissible) */
6181 factor = 21;
6182 if (is_lvds) {
6183 if ((intel_panel_use_ssc(dev_priv) &&
6184 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6185 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6186 factor = 25;
6187 } else if (intel_crtc->config.sdvo_tv_clock)
6188 factor = 20;
6189
6190 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6191 *fp |= FP_CB_TUNE;
6192
6193 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6194 *fp2 |= FP_CB_TUNE;
6195
6196 dpll = 0;
6197
6198 if (is_lvds)
6199 dpll |= DPLLB_MODE_LVDS;
6200 else
6201 dpll |= DPLLB_MODE_DAC_SERIAL;
6202
6203 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6204 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6205
6206 if (is_sdvo)
6207 dpll |= DPLL_SDVO_HIGH_SPEED;
6208 if (intel_crtc->config.has_dp_encoder)
6209 dpll |= DPLL_SDVO_HIGH_SPEED;
6210
6211 /* compute bitmask from p1 value */
6212 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6213 /* also FPA1 */
6214 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6215
6216 switch (intel_crtc->config.dpll.p2) {
6217 case 5:
6218 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6219 break;
6220 case 7:
6221 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6222 break;
6223 case 10:
6224 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6225 break;
6226 case 14:
6227 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6228 break;
6229 }
6230
6231 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6232 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6233 else
6234 dpll |= PLL_REF_INPUT_DREFCLK;
6235
6236 return dpll | DPLL_VCO_ENABLE;
6237 }
6238
6239 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6240 int x, int y,
6241 struct drm_framebuffer *fb)
6242 {
6243 struct drm_device *dev = crtc->dev;
6244 struct drm_i915_private *dev_priv = dev->dev_private;
6245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6246 int pipe = intel_crtc->pipe;
6247 int plane = intel_crtc->plane;
6248 int num_connectors = 0;
6249 intel_clock_t clock, reduced_clock;
6250 u32 dpll = 0, fp = 0, fp2 = 0;
6251 bool ok, has_reduced_clock = false;
6252 bool is_lvds = false;
6253 struct intel_encoder *encoder;
6254 struct intel_shared_dpll *pll;
6255 int ret;
6256
6257 for_each_encoder_on_crtc(dev, crtc, encoder) {
6258 switch (encoder->type) {
6259 case INTEL_OUTPUT_LVDS:
6260 is_lvds = true;
6261 break;
6262 }
6263
6264 num_connectors++;
6265 }
6266
6267 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6268 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
6269
6270 ok = ironlake_compute_clocks(crtc, &clock,
6271 &has_reduced_clock, &reduced_clock);
6272 if (!ok && !intel_crtc->config.clock_set) {
6273 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6274 return -EINVAL;
6275 }
6276 /* Compat-code for transition, will disappear. */
6277 if (!intel_crtc->config.clock_set) {
6278 intel_crtc->config.dpll.n = clock.n;
6279 intel_crtc->config.dpll.m1 = clock.m1;
6280 intel_crtc->config.dpll.m2 = clock.m2;
6281 intel_crtc->config.dpll.p1 = clock.p1;
6282 intel_crtc->config.dpll.p2 = clock.p2;
6283 }
6284
6285 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
6286 if (intel_crtc->config.has_pch_encoder) {
6287 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
6288 if (has_reduced_clock)
6289 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
6290
6291 dpll = ironlake_compute_dpll(intel_crtc,
6292 &fp, &reduced_clock,
6293 has_reduced_clock ? &fp2 : NULL);
6294
6295 intel_crtc->config.dpll_hw_state.dpll = dpll;
6296 intel_crtc->config.dpll_hw_state.fp0 = fp;
6297 if (has_reduced_clock)
6298 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6299 else
6300 intel_crtc->config.dpll_hw_state.fp1 = fp;
6301
6302 pll = intel_get_shared_dpll(intel_crtc);
6303 if (pll == NULL) {
6304 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6305 pipe_name(pipe));
6306 return -EINVAL;
6307 }
6308 } else
6309 intel_put_shared_dpll(intel_crtc);
6310
6311 if (intel_crtc->config.has_dp_encoder)
6312 intel_dp_set_m_n(intel_crtc);
6313
6314 if (is_lvds && has_reduced_clock && i915_powersave)
6315 intel_crtc->lowfreq_avail = true;
6316 else
6317 intel_crtc->lowfreq_avail = false;
6318
6319 intel_set_pipe_timings(intel_crtc);
6320
6321 if (intel_crtc->config.has_pch_encoder) {
6322 intel_cpu_transcoder_set_m_n(intel_crtc,
6323 &intel_crtc->config.fdi_m_n);
6324 }
6325
6326 ironlake_set_pipeconf(crtc);
6327
6328 /* Set up the display plane register */
6329 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
6330 POSTING_READ(DSPCNTR(plane));
6331
6332 ret = intel_pipe_set_base(crtc, x, y, fb);
6333
6334 return ret;
6335 }
6336
6337 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6338 struct intel_link_m_n *m_n)
6339 {
6340 struct drm_device *dev = crtc->base.dev;
6341 struct drm_i915_private *dev_priv = dev->dev_private;
6342 enum pipe pipe = crtc->pipe;
6343
6344 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6345 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6346 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6347 & ~TU_SIZE_MASK;
6348 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6349 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6350 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6351 }
6352
6353 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6354 enum transcoder transcoder,
6355 struct intel_link_m_n *m_n)
6356 {
6357 struct drm_device *dev = crtc->base.dev;
6358 struct drm_i915_private *dev_priv = dev->dev_private;
6359 enum pipe pipe = crtc->pipe;
6360
6361 if (INTEL_INFO(dev)->gen >= 5) {
6362 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6363 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6364 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6365 & ~TU_SIZE_MASK;
6366 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6367 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6368 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6369 } else {
6370 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6371 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6372 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6373 & ~TU_SIZE_MASK;
6374 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6375 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6376 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6377 }
6378 }
6379
6380 void intel_dp_get_m_n(struct intel_crtc *crtc,
6381 struct intel_crtc_config *pipe_config)
6382 {
6383 if (crtc->config.has_pch_encoder)
6384 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6385 else
6386 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6387 &pipe_config->dp_m_n);
6388 }
6389
6390 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6391 struct intel_crtc_config *pipe_config)
6392 {
6393 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6394 &pipe_config->fdi_m_n);
6395 }
6396
6397 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6398 struct intel_crtc_config *pipe_config)
6399 {
6400 struct drm_device *dev = crtc->base.dev;
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6402 uint32_t tmp;
6403
6404 tmp = I915_READ(PF_CTL(crtc->pipe));
6405
6406 if (tmp & PF_ENABLE) {
6407 pipe_config->pch_pfit.enabled = true;
6408 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6409 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
6410
6411 /* We currently do not free assignements of panel fitters on
6412 * ivb/hsw (since we don't use the higher upscaling modes which
6413 * differentiates them) so just WARN about this case for now. */
6414 if (IS_GEN7(dev)) {
6415 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6416 PF_PIPE_SEL_IVB(crtc->pipe));
6417 }
6418 }
6419 }
6420
6421 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6422 struct intel_crtc_config *pipe_config)
6423 {
6424 struct drm_device *dev = crtc->base.dev;
6425 struct drm_i915_private *dev_priv = dev->dev_private;
6426 uint32_t tmp;
6427
6428 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6429 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6430
6431 tmp = I915_READ(PIPECONF(crtc->pipe));
6432 if (!(tmp & PIPECONF_ENABLE))
6433 return false;
6434
6435 switch (tmp & PIPECONF_BPC_MASK) {
6436 case PIPECONF_6BPC:
6437 pipe_config->pipe_bpp = 18;
6438 break;
6439 case PIPECONF_8BPC:
6440 pipe_config->pipe_bpp = 24;
6441 break;
6442 case PIPECONF_10BPC:
6443 pipe_config->pipe_bpp = 30;
6444 break;
6445 case PIPECONF_12BPC:
6446 pipe_config->pipe_bpp = 36;
6447 break;
6448 default:
6449 break;
6450 }
6451
6452 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
6453 struct intel_shared_dpll *pll;
6454
6455 pipe_config->has_pch_encoder = true;
6456
6457 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6458 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6459 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6460
6461 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6462
6463 if (HAS_PCH_IBX(dev_priv->dev)) {
6464 pipe_config->shared_dpll =
6465 (enum intel_dpll_id) crtc->pipe;
6466 } else {
6467 tmp = I915_READ(PCH_DPLL_SEL);
6468 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6469 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6470 else
6471 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6472 }
6473
6474 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6475
6476 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6477 &pipe_config->dpll_hw_state));
6478
6479 tmp = pipe_config->dpll_hw_state.dpll;
6480 pipe_config->pixel_multiplier =
6481 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6482 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6483
6484 ironlake_pch_clock_get(crtc, pipe_config);
6485 } else {
6486 pipe_config->pixel_multiplier = 1;
6487 }
6488
6489 intel_get_pipe_timings(crtc, pipe_config);
6490
6491 ironlake_get_pfit_config(crtc, pipe_config);
6492
6493 return true;
6494 }
6495
6496 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6497 {
6498 struct drm_device *dev = dev_priv->dev;
6499 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6500 struct intel_crtc *crtc;
6501 unsigned long irqflags;
6502 uint32_t val;
6503
6504 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6505 WARN(crtc->active, "CRTC for pipe %c enabled\n",
6506 pipe_name(crtc->pipe));
6507
6508 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6509 WARN(plls->spll_refcount, "SPLL enabled\n");
6510 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6511 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6512 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6513 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6514 "CPU PWM1 enabled\n");
6515 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6516 "CPU PWM2 enabled\n");
6517 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6518 "PCH PWM1 enabled\n");
6519 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6520 "Utility pin enabled\n");
6521 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6522
6523 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6524 val = I915_READ(DEIMR);
6525 WARN((val | DE_PCH_EVENT_IVB) != 0xffffffff,
6526 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6527 val = I915_READ(SDEIMR);
6528 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
6529 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6530 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6531 }
6532
6533 /*
6534 * This function implements pieces of two sequences from BSpec:
6535 * - Sequence for display software to disable LCPLL
6536 * - Sequence for display software to allow package C8+
6537 * The steps implemented here are just the steps that actually touch the LCPLL
6538 * register. Callers should take care of disabling all the display engine
6539 * functions, doing the mode unset, fixing interrupts, etc.
6540 */
6541 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6542 bool switch_to_fclk, bool allow_power_down)
6543 {
6544 uint32_t val;
6545
6546 assert_can_disable_lcpll(dev_priv);
6547
6548 val = I915_READ(LCPLL_CTL);
6549
6550 if (switch_to_fclk) {
6551 val |= LCPLL_CD_SOURCE_FCLK;
6552 I915_WRITE(LCPLL_CTL, val);
6553
6554 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6555 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6556 DRM_ERROR("Switching to FCLK failed\n");
6557
6558 val = I915_READ(LCPLL_CTL);
6559 }
6560
6561 val |= LCPLL_PLL_DISABLE;
6562 I915_WRITE(LCPLL_CTL, val);
6563 POSTING_READ(LCPLL_CTL);
6564
6565 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6566 DRM_ERROR("LCPLL still locked\n");
6567
6568 val = I915_READ(D_COMP);
6569 val |= D_COMP_COMP_DISABLE;
6570 mutex_lock(&dev_priv->rps.hw_lock);
6571 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6572 DRM_ERROR("Failed to disable D_COMP\n");
6573 mutex_unlock(&dev_priv->rps.hw_lock);
6574 POSTING_READ(D_COMP);
6575 ndelay(100);
6576
6577 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6578 DRM_ERROR("D_COMP RCOMP still in progress\n");
6579
6580 if (allow_power_down) {
6581 val = I915_READ(LCPLL_CTL);
6582 val |= LCPLL_POWER_DOWN_ALLOW;
6583 I915_WRITE(LCPLL_CTL, val);
6584 POSTING_READ(LCPLL_CTL);
6585 }
6586 }
6587
6588 /*
6589 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6590 * source.
6591 */
6592 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6593 {
6594 uint32_t val;
6595
6596 val = I915_READ(LCPLL_CTL);
6597
6598 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6599 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6600 return;
6601
6602 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6603 * we'll hang the machine! */
6604 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
6605
6606 if (val & LCPLL_POWER_DOWN_ALLOW) {
6607 val &= ~LCPLL_POWER_DOWN_ALLOW;
6608 I915_WRITE(LCPLL_CTL, val);
6609 POSTING_READ(LCPLL_CTL);
6610 }
6611
6612 val = I915_READ(D_COMP);
6613 val |= D_COMP_COMP_FORCE;
6614 val &= ~D_COMP_COMP_DISABLE;
6615 mutex_lock(&dev_priv->rps.hw_lock);
6616 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6617 DRM_ERROR("Failed to enable D_COMP\n");
6618 mutex_unlock(&dev_priv->rps.hw_lock);
6619 POSTING_READ(D_COMP);
6620
6621 val = I915_READ(LCPLL_CTL);
6622 val &= ~LCPLL_PLL_DISABLE;
6623 I915_WRITE(LCPLL_CTL, val);
6624
6625 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6626 DRM_ERROR("LCPLL not locked yet\n");
6627
6628 if (val & LCPLL_CD_SOURCE_FCLK) {
6629 val = I915_READ(LCPLL_CTL);
6630 val &= ~LCPLL_CD_SOURCE_FCLK;
6631 I915_WRITE(LCPLL_CTL, val);
6632
6633 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6634 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6635 DRM_ERROR("Switching back to LCPLL failed\n");
6636 }
6637
6638 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
6639 }
6640
6641 void hsw_enable_pc8_work(struct work_struct *__work)
6642 {
6643 struct drm_i915_private *dev_priv =
6644 container_of(to_delayed_work(__work), struct drm_i915_private,
6645 pc8.enable_work);
6646 struct drm_device *dev = dev_priv->dev;
6647 uint32_t val;
6648
6649 WARN_ON(!HAS_PC8(dev));
6650
6651 if (dev_priv->pc8.enabled)
6652 return;
6653
6654 DRM_DEBUG_KMS("Enabling package C8+\n");
6655
6656 dev_priv->pc8.enabled = true;
6657
6658 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6659 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6660 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6661 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6662 }
6663
6664 lpt_disable_clkout_dp(dev);
6665 hsw_pc8_disable_interrupts(dev);
6666 hsw_disable_lcpll(dev_priv, true, true);
6667
6668 intel_runtime_pm_put(dev_priv);
6669 }
6670
6671 static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6672 {
6673 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6674 WARN(dev_priv->pc8.disable_count < 1,
6675 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6676
6677 dev_priv->pc8.disable_count--;
6678 if (dev_priv->pc8.disable_count != 0)
6679 return;
6680
6681 schedule_delayed_work(&dev_priv->pc8.enable_work,
6682 msecs_to_jiffies(i915_pc8_timeout));
6683 }
6684
6685 static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6686 {
6687 struct drm_device *dev = dev_priv->dev;
6688 uint32_t val;
6689
6690 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6691 WARN(dev_priv->pc8.disable_count < 0,
6692 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6693
6694 dev_priv->pc8.disable_count++;
6695 if (dev_priv->pc8.disable_count != 1)
6696 return;
6697
6698 WARN_ON(!HAS_PC8(dev));
6699
6700 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6701 if (!dev_priv->pc8.enabled)
6702 return;
6703
6704 DRM_DEBUG_KMS("Disabling package C8+\n");
6705
6706 intel_runtime_pm_get(dev_priv);
6707
6708 hsw_restore_lcpll(dev_priv);
6709 hsw_pc8_restore_interrupts(dev);
6710 lpt_init_pch_refclk(dev);
6711
6712 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6713 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6714 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6715 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6716 }
6717
6718 intel_prepare_ddi(dev);
6719 i915_gem_init_swizzling(dev);
6720 mutex_lock(&dev_priv->rps.hw_lock);
6721 gen6_update_ring_freq(dev);
6722 mutex_unlock(&dev_priv->rps.hw_lock);
6723 dev_priv->pc8.enabled = false;
6724 }
6725
6726 void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6727 {
6728 if (!HAS_PC8(dev_priv->dev))
6729 return;
6730
6731 mutex_lock(&dev_priv->pc8.lock);
6732 __hsw_enable_package_c8(dev_priv);
6733 mutex_unlock(&dev_priv->pc8.lock);
6734 }
6735
6736 void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6737 {
6738 if (!HAS_PC8(dev_priv->dev))
6739 return;
6740
6741 mutex_lock(&dev_priv->pc8.lock);
6742 __hsw_disable_package_c8(dev_priv);
6743 mutex_unlock(&dev_priv->pc8.lock);
6744 }
6745
6746 static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6747 {
6748 struct drm_device *dev = dev_priv->dev;
6749 struct intel_crtc *crtc;
6750 uint32_t val;
6751
6752 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6753 if (crtc->base.enabled)
6754 return false;
6755
6756 /* This case is still possible since we have the i915.disable_power_well
6757 * parameter and also the KVMr or something else might be requesting the
6758 * power well. */
6759 val = I915_READ(HSW_PWR_WELL_DRIVER);
6760 if (val != 0) {
6761 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6762 return false;
6763 }
6764
6765 return true;
6766 }
6767
6768 /* Since we're called from modeset_global_resources there's no way to
6769 * symmetrically increase and decrease the refcount, so we use
6770 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6771 * or not.
6772 */
6773 static void hsw_update_package_c8(struct drm_device *dev)
6774 {
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 bool allow;
6777
6778 if (!HAS_PC8(dev_priv->dev))
6779 return;
6780
6781 if (!i915_enable_pc8)
6782 return;
6783
6784 mutex_lock(&dev_priv->pc8.lock);
6785
6786 allow = hsw_can_enable_package_c8(dev_priv);
6787
6788 if (allow == dev_priv->pc8.requirements_met)
6789 goto done;
6790
6791 dev_priv->pc8.requirements_met = allow;
6792
6793 if (allow)
6794 __hsw_enable_package_c8(dev_priv);
6795 else
6796 __hsw_disable_package_c8(dev_priv);
6797
6798 done:
6799 mutex_unlock(&dev_priv->pc8.lock);
6800 }
6801
6802 static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6803 {
6804 if (!HAS_PC8(dev_priv->dev))
6805 return;
6806
6807 mutex_lock(&dev_priv->pc8.lock);
6808 if (!dev_priv->pc8.gpu_idle) {
6809 dev_priv->pc8.gpu_idle = true;
6810 __hsw_enable_package_c8(dev_priv);
6811 }
6812 mutex_unlock(&dev_priv->pc8.lock);
6813 }
6814
6815 static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6816 {
6817 if (!HAS_PC8(dev_priv->dev))
6818 return;
6819
6820 mutex_lock(&dev_priv->pc8.lock);
6821 if (dev_priv->pc8.gpu_idle) {
6822 dev_priv->pc8.gpu_idle = false;
6823 __hsw_disable_package_c8(dev_priv);
6824 }
6825 mutex_unlock(&dev_priv->pc8.lock);
6826 }
6827
6828 #define for_each_power_domain(domain, mask) \
6829 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
6830 if ((1 << (domain)) & (mask))
6831
6832 static unsigned long get_pipe_power_domains(struct drm_device *dev,
6833 enum pipe pipe, bool pfit_enabled)
6834 {
6835 unsigned long mask;
6836 enum transcoder transcoder;
6837
6838 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
6839
6840 mask = BIT(POWER_DOMAIN_PIPE(pipe));
6841 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6842 if (pfit_enabled)
6843 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
6844
6845 return mask;
6846 }
6847
6848 void intel_display_set_init_power(struct drm_device *dev, bool enable)
6849 {
6850 struct drm_i915_private *dev_priv = dev->dev_private;
6851
6852 if (dev_priv->power_domains.init_power_on == enable)
6853 return;
6854
6855 if (enable)
6856 intel_display_power_get(dev, POWER_DOMAIN_INIT);
6857 else
6858 intel_display_power_put(dev, POWER_DOMAIN_INIT);
6859
6860 dev_priv->power_domains.init_power_on = enable;
6861 }
6862
6863 static void modeset_update_power_wells(struct drm_device *dev)
6864 {
6865 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
6866 struct intel_crtc *crtc;
6867
6868 /*
6869 * First get all needed power domains, then put all unneeded, to avoid
6870 * any unnecessary toggling of the power wells.
6871 */
6872 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6873 enum intel_display_power_domain domain;
6874
6875 if (!crtc->base.enabled)
6876 continue;
6877
6878 pipe_domains[crtc->pipe] = get_pipe_power_domains(dev,
6879 crtc->pipe,
6880 crtc->config.pch_pfit.enabled);
6881
6882 for_each_power_domain(domain, pipe_domains[crtc->pipe])
6883 intel_display_power_get(dev, domain);
6884 }
6885
6886 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
6887 enum intel_display_power_domain domain;
6888
6889 for_each_power_domain(domain, crtc->enabled_power_domains)
6890 intel_display_power_put(dev, domain);
6891
6892 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
6893 }
6894
6895 intel_display_set_init_power(dev, false);
6896 }
6897
6898 static void haswell_modeset_global_resources(struct drm_device *dev)
6899 {
6900 modeset_update_power_wells(dev);
6901 hsw_update_package_c8(dev);
6902 }
6903
6904 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
6905 int x, int y,
6906 struct drm_framebuffer *fb)
6907 {
6908 struct drm_device *dev = crtc->dev;
6909 struct drm_i915_private *dev_priv = dev->dev_private;
6910 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6911 int plane = intel_crtc->plane;
6912 int ret;
6913
6914 if (!intel_ddi_pll_select(intel_crtc))
6915 return -EINVAL;
6916 intel_ddi_pll_enable(intel_crtc);
6917
6918 if (intel_crtc->config.has_dp_encoder)
6919 intel_dp_set_m_n(intel_crtc);
6920
6921 intel_crtc->lowfreq_avail = false;
6922
6923 intel_set_pipe_timings(intel_crtc);
6924
6925 if (intel_crtc->config.has_pch_encoder) {
6926 intel_cpu_transcoder_set_m_n(intel_crtc,
6927 &intel_crtc->config.fdi_m_n);
6928 }
6929
6930 haswell_set_pipeconf(crtc);
6931
6932 intel_set_pipe_csc(crtc);
6933
6934 /* Set up the display plane register */
6935 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6936 POSTING_READ(DSPCNTR(plane));
6937
6938 ret = intel_pipe_set_base(crtc, x, y, fb);
6939
6940 return ret;
6941 }
6942
6943 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6944 struct intel_crtc_config *pipe_config)
6945 {
6946 struct drm_device *dev = crtc->base.dev;
6947 struct drm_i915_private *dev_priv = dev->dev_private;
6948 enum intel_display_power_domain pfit_domain;
6949 uint32_t tmp;
6950
6951 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6952 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6953
6954 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6955 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6956 enum pipe trans_edp_pipe;
6957 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6958 default:
6959 WARN(1, "unknown pipe linked to edp transcoder\n");
6960 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6961 case TRANS_DDI_EDP_INPUT_A_ON:
6962 trans_edp_pipe = PIPE_A;
6963 break;
6964 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6965 trans_edp_pipe = PIPE_B;
6966 break;
6967 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6968 trans_edp_pipe = PIPE_C;
6969 break;
6970 }
6971
6972 if (trans_edp_pipe == crtc->pipe)
6973 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6974 }
6975
6976 if (!intel_display_power_enabled(dev,
6977 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6978 return false;
6979
6980 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6981 if (!(tmp & PIPECONF_ENABLE))
6982 return false;
6983
6984 /*
6985 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6986 * DDI E. So just check whether this pipe is wired to DDI E and whether
6987 * the PCH transcoder is on.
6988 */
6989 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6990 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6991 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6992 pipe_config->has_pch_encoder = true;
6993
6994 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6995 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6996 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6997
6998 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6999 }
7000
7001 intel_get_pipe_timings(crtc, pipe_config);
7002
7003 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7004 if (intel_display_power_enabled(dev, pfit_domain))
7005 ironlake_get_pfit_config(crtc, pipe_config);
7006
7007 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7008 (I915_READ(IPS_CTL) & IPS_ENABLE);
7009
7010 pipe_config->pixel_multiplier = 1;
7011
7012 return true;
7013 }
7014
7015 static int intel_crtc_mode_set(struct drm_crtc *crtc,
7016 int x, int y,
7017 struct drm_framebuffer *fb)
7018 {
7019 struct drm_device *dev = crtc->dev;
7020 struct drm_i915_private *dev_priv = dev->dev_private;
7021 struct intel_encoder *encoder;
7022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7023 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
7024 int pipe = intel_crtc->pipe;
7025 int ret;
7026
7027 drm_vblank_pre_modeset(dev, pipe);
7028
7029 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
7030
7031 drm_vblank_post_modeset(dev, pipe);
7032
7033 if (ret != 0)
7034 return ret;
7035
7036 for_each_encoder_on_crtc(dev, crtc, encoder) {
7037 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7038 encoder->base.base.id,
7039 drm_get_encoder_name(&encoder->base),
7040 mode->base.id, mode->name);
7041 encoder->mode_set(encoder);
7042 }
7043
7044 return 0;
7045 }
7046
7047 static struct {
7048 int clock;
7049 u32 config;
7050 } hdmi_audio_clock[] = {
7051 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7052 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7053 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7054 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7055 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7056 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7057 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7058 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7059 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7060 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7061 };
7062
7063 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7064 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7065 {
7066 int i;
7067
7068 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7069 if (mode->clock == hdmi_audio_clock[i].clock)
7070 break;
7071 }
7072
7073 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7074 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7075 i = 1;
7076 }
7077
7078 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7079 hdmi_audio_clock[i].clock,
7080 hdmi_audio_clock[i].config);
7081
7082 return hdmi_audio_clock[i].config;
7083 }
7084
7085 static bool intel_eld_uptodate(struct drm_connector *connector,
7086 int reg_eldv, uint32_t bits_eldv,
7087 int reg_elda, uint32_t bits_elda,
7088 int reg_edid)
7089 {
7090 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7091 uint8_t *eld = connector->eld;
7092 uint32_t i;
7093
7094 i = I915_READ(reg_eldv);
7095 i &= bits_eldv;
7096
7097 if (!eld[0])
7098 return !i;
7099
7100 if (!i)
7101 return false;
7102
7103 i = I915_READ(reg_elda);
7104 i &= ~bits_elda;
7105 I915_WRITE(reg_elda, i);
7106
7107 for (i = 0; i < eld[2]; i++)
7108 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7109 return false;
7110
7111 return true;
7112 }
7113
7114 static void g4x_write_eld(struct drm_connector *connector,
7115 struct drm_crtc *crtc,
7116 struct drm_display_mode *mode)
7117 {
7118 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7119 uint8_t *eld = connector->eld;
7120 uint32_t eldv;
7121 uint32_t len;
7122 uint32_t i;
7123
7124 i = I915_READ(G4X_AUD_VID_DID);
7125
7126 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7127 eldv = G4X_ELDV_DEVCL_DEVBLC;
7128 else
7129 eldv = G4X_ELDV_DEVCTG;
7130
7131 if (intel_eld_uptodate(connector,
7132 G4X_AUD_CNTL_ST, eldv,
7133 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7134 G4X_HDMIW_HDMIEDID))
7135 return;
7136
7137 i = I915_READ(G4X_AUD_CNTL_ST);
7138 i &= ~(eldv | G4X_ELD_ADDR);
7139 len = (i >> 9) & 0x1f; /* ELD buffer size */
7140 I915_WRITE(G4X_AUD_CNTL_ST, i);
7141
7142 if (!eld[0])
7143 return;
7144
7145 len = min_t(uint8_t, eld[2], len);
7146 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7147 for (i = 0; i < len; i++)
7148 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7149
7150 i = I915_READ(G4X_AUD_CNTL_ST);
7151 i |= eldv;
7152 I915_WRITE(G4X_AUD_CNTL_ST, i);
7153 }
7154
7155 static void haswell_write_eld(struct drm_connector *connector,
7156 struct drm_crtc *crtc,
7157 struct drm_display_mode *mode)
7158 {
7159 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7160 uint8_t *eld = connector->eld;
7161 struct drm_device *dev = crtc->dev;
7162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7163 uint32_t eldv;
7164 uint32_t i;
7165 int len;
7166 int pipe = to_intel_crtc(crtc)->pipe;
7167 int tmp;
7168
7169 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7170 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7171 int aud_config = HSW_AUD_CFG(pipe);
7172 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7173
7174
7175 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
7176
7177 /* Audio output enable */
7178 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7179 tmp = I915_READ(aud_cntrl_st2);
7180 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7181 I915_WRITE(aud_cntrl_st2, tmp);
7182
7183 /* Wait for 1 vertical blank */
7184 intel_wait_for_vblank(dev, pipe);
7185
7186 /* Set ELD valid state */
7187 tmp = I915_READ(aud_cntrl_st2);
7188 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7189 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7190 I915_WRITE(aud_cntrl_st2, tmp);
7191 tmp = I915_READ(aud_cntrl_st2);
7192 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7193
7194 /* Enable HDMI mode */
7195 tmp = I915_READ(aud_config);
7196 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7197 /* clear N_programing_enable and N_value_index */
7198 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7199 I915_WRITE(aud_config, tmp);
7200
7201 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7202
7203 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7204 intel_crtc->eld_vld = true;
7205
7206 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7207 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7208 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7209 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7210 } else {
7211 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7212 }
7213
7214 if (intel_eld_uptodate(connector,
7215 aud_cntrl_st2, eldv,
7216 aud_cntl_st, IBX_ELD_ADDRESS,
7217 hdmiw_hdmiedid))
7218 return;
7219
7220 i = I915_READ(aud_cntrl_st2);
7221 i &= ~eldv;
7222 I915_WRITE(aud_cntrl_st2, i);
7223
7224 if (!eld[0])
7225 return;
7226
7227 i = I915_READ(aud_cntl_st);
7228 i &= ~IBX_ELD_ADDRESS;
7229 I915_WRITE(aud_cntl_st, i);
7230 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7231 DRM_DEBUG_DRIVER("port num:%d\n", i);
7232
7233 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7234 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7235 for (i = 0; i < len; i++)
7236 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7237
7238 i = I915_READ(aud_cntrl_st2);
7239 i |= eldv;
7240 I915_WRITE(aud_cntrl_st2, i);
7241
7242 }
7243
7244 static void ironlake_write_eld(struct drm_connector *connector,
7245 struct drm_crtc *crtc,
7246 struct drm_display_mode *mode)
7247 {
7248 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7249 uint8_t *eld = connector->eld;
7250 uint32_t eldv;
7251 uint32_t i;
7252 int len;
7253 int hdmiw_hdmiedid;
7254 int aud_config;
7255 int aud_cntl_st;
7256 int aud_cntrl_st2;
7257 int pipe = to_intel_crtc(crtc)->pipe;
7258
7259 if (HAS_PCH_IBX(connector->dev)) {
7260 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7261 aud_config = IBX_AUD_CFG(pipe);
7262 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7263 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7264 } else if (IS_VALLEYVIEW(connector->dev)) {
7265 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7266 aud_config = VLV_AUD_CFG(pipe);
7267 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7268 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7269 } else {
7270 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7271 aud_config = CPT_AUD_CFG(pipe);
7272 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7273 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7274 }
7275
7276 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7277
7278 if (IS_VALLEYVIEW(connector->dev)) {
7279 struct intel_encoder *intel_encoder;
7280 struct intel_digital_port *intel_dig_port;
7281
7282 intel_encoder = intel_attached_encoder(connector);
7283 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7284 i = intel_dig_port->port;
7285 } else {
7286 i = I915_READ(aud_cntl_st);
7287 i = (i >> 29) & DIP_PORT_SEL_MASK;
7288 /* DIP_Port_Select, 0x1 = PortB */
7289 }
7290
7291 if (!i) {
7292 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7293 /* operate blindly on all ports */
7294 eldv = IBX_ELD_VALIDB;
7295 eldv |= IBX_ELD_VALIDB << 4;
7296 eldv |= IBX_ELD_VALIDB << 8;
7297 } else {
7298 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7299 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7300 }
7301
7302 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7303 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7304 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7305 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7306 } else {
7307 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7308 }
7309
7310 if (intel_eld_uptodate(connector,
7311 aud_cntrl_st2, eldv,
7312 aud_cntl_st, IBX_ELD_ADDRESS,
7313 hdmiw_hdmiedid))
7314 return;
7315
7316 i = I915_READ(aud_cntrl_st2);
7317 i &= ~eldv;
7318 I915_WRITE(aud_cntrl_st2, i);
7319
7320 if (!eld[0])
7321 return;
7322
7323 i = I915_READ(aud_cntl_st);
7324 i &= ~IBX_ELD_ADDRESS;
7325 I915_WRITE(aud_cntl_st, i);
7326
7327 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7328 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7329 for (i = 0; i < len; i++)
7330 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7331
7332 i = I915_READ(aud_cntrl_st2);
7333 i |= eldv;
7334 I915_WRITE(aud_cntrl_st2, i);
7335 }
7336
7337 void intel_write_eld(struct drm_encoder *encoder,
7338 struct drm_display_mode *mode)
7339 {
7340 struct drm_crtc *crtc = encoder->crtc;
7341 struct drm_connector *connector;
7342 struct drm_device *dev = encoder->dev;
7343 struct drm_i915_private *dev_priv = dev->dev_private;
7344
7345 connector = drm_select_eld(encoder, mode);
7346 if (!connector)
7347 return;
7348
7349 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7350 connector->base.id,
7351 drm_get_connector_name(connector),
7352 connector->encoder->base.id,
7353 drm_get_encoder_name(connector->encoder));
7354
7355 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7356
7357 if (dev_priv->display.write_eld)
7358 dev_priv->display.write_eld(connector, crtc, mode);
7359 }
7360
7361 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7362 {
7363 struct drm_device *dev = crtc->dev;
7364 struct drm_i915_private *dev_priv = dev->dev_private;
7365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7366 bool visible = base != 0;
7367 u32 cntl;
7368
7369 if (intel_crtc->cursor_visible == visible)
7370 return;
7371
7372 cntl = I915_READ(_CURACNTR);
7373 if (visible) {
7374 /* On these chipsets we can only modify the base whilst
7375 * the cursor is disabled.
7376 */
7377 I915_WRITE(_CURABASE, base);
7378
7379 cntl &= ~(CURSOR_FORMAT_MASK);
7380 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7381 cntl |= CURSOR_ENABLE |
7382 CURSOR_GAMMA_ENABLE |
7383 CURSOR_FORMAT_ARGB;
7384 } else
7385 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
7386 I915_WRITE(_CURACNTR, cntl);
7387
7388 intel_crtc->cursor_visible = visible;
7389 }
7390
7391 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7392 {
7393 struct drm_device *dev = crtc->dev;
7394 struct drm_i915_private *dev_priv = dev->dev_private;
7395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7396 int pipe = intel_crtc->pipe;
7397 bool visible = base != 0;
7398
7399 if (intel_crtc->cursor_visible != visible) {
7400 uint32_t cntl = I915_READ(CURCNTR(pipe));
7401 if (base) {
7402 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7403 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7404 cntl |= pipe << 28; /* Connect to correct pipe */
7405 } else {
7406 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7407 cntl |= CURSOR_MODE_DISABLE;
7408 }
7409 I915_WRITE(CURCNTR(pipe), cntl);
7410
7411 intel_crtc->cursor_visible = visible;
7412 }
7413 /* and commit changes on next vblank */
7414 POSTING_READ(CURCNTR(pipe));
7415 I915_WRITE(CURBASE(pipe), base);
7416 POSTING_READ(CURBASE(pipe));
7417 }
7418
7419 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7420 {
7421 struct drm_device *dev = crtc->dev;
7422 struct drm_i915_private *dev_priv = dev->dev_private;
7423 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7424 int pipe = intel_crtc->pipe;
7425 bool visible = base != 0;
7426
7427 if (intel_crtc->cursor_visible != visible) {
7428 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7429 if (base) {
7430 cntl &= ~CURSOR_MODE;
7431 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7432 } else {
7433 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7434 cntl |= CURSOR_MODE_DISABLE;
7435 }
7436 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7437 cntl |= CURSOR_PIPE_CSC_ENABLE;
7438 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7439 }
7440 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7441
7442 intel_crtc->cursor_visible = visible;
7443 }
7444 /* and commit changes on next vblank */
7445 POSTING_READ(CURCNTR_IVB(pipe));
7446 I915_WRITE(CURBASE_IVB(pipe), base);
7447 POSTING_READ(CURBASE_IVB(pipe));
7448 }
7449
7450 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
7451 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7452 bool on)
7453 {
7454 struct drm_device *dev = crtc->dev;
7455 struct drm_i915_private *dev_priv = dev->dev_private;
7456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7457 int pipe = intel_crtc->pipe;
7458 int x = intel_crtc->cursor_x;
7459 int y = intel_crtc->cursor_y;
7460 u32 base = 0, pos = 0;
7461 bool visible;
7462
7463 if (on)
7464 base = intel_crtc->cursor_addr;
7465
7466 if (x >= intel_crtc->config.pipe_src_w)
7467 base = 0;
7468
7469 if (y >= intel_crtc->config.pipe_src_h)
7470 base = 0;
7471
7472 if (x < 0) {
7473 if (x + intel_crtc->cursor_width <= 0)
7474 base = 0;
7475
7476 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7477 x = -x;
7478 }
7479 pos |= x << CURSOR_X_SHIFT;
7480
7481 if (y < 0) {
7482 if (y + intel_crtc->cursor_height <= 0)
7483 base = 0;
7484
7485 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7486 y = -y;
7487 }
7488 pos |= y << CURSOR_Y_SHIFT;
7489
7490 visible = base != 0;
7491 if (!visible && !intel_crtc->cursor_visible)
7492 return;
7493
7494 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7495 I915_WRITE(CURPOS_IVB(pipe), pos);
7496 ivb_update_cursor(crtc, base);
7497 } else {
7498 I915_WRITE(CURPOS(pipe), pos);
7499 if (IS_845G(dev) || IS_I865G(dev))
7500 i845_update_cursor(crtc, base);
7501 else
7502 i9xx_update_cursor(crtc, base);
7503 }
7504 }
7505
7506 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
7507 struct drm_file *file,
7508 uint32_t handle,
7509 uint32_t width, uint32_t height)
7510 {
7511 struct drm_device *dev = crtc->dev;
7512 struct drm_i915_private *dev_priv = dev->dev_private;
7513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7514 struct drm_i915_gem_object *obj;
7515 uint32_t addr;
7516 int ret;
7517
7518 /* if we want to turn off the cursor ignore width and height */
7519 if (!handle) {
7520 DRM_DEBUG_KMS("cursor off\n");
7521 addr = 0;
7522 obj = NULL;
7523 mutex_lock(&dev->struct_mutex);
7524 goto finish;
7525 }
7526
7527 /* Currently we only support 64x64 cursors */
7528 if (width != 64 || height != 64) {
7529 DRM_ERROR("we currently only support 64x64 cursors\n");
7530 return -EINVAL;
7531 }
7532
7533 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
7534 if (&obj->base == NULL)
7535 return -ENOENT;
7536
7537 if (obj->base.size < width * height * 4) {
7538 DRM_ERROR("buffer is to small\n");
7539 ret = -ENOMEM;
7540 goto fail;
7541 }
7542
7543 /* we only need to pin inside GTT if cursor is non-phy */
7544 mutex_lock(&dev->struct_mutex);
7545 if (!dev_priv->info->cursor_needs_physical) {
7546 unsigned alignment;
7547
7548 if (obj->tiling_mode) {
7549 DRM_ERROR("cursor cannot be tiled\n");
7550 ret = -EINVAL;
7551 goto fail_locked;
7552 }
7553
7554 /* Note that the w/a also requires 2 PTE of padding following
7555 * the bo. We currently fill all unused PTE with the shadow
7556 * page and so we should always have valid PTE following the
7557 * cursor preventing the VT-d warning.
7558 */
7559 alignment = 0;
7560 if (need_vtd_wa(dev))
7561 alignment = 64*1024;
7562
7563 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
7564 if (ret) {
7565 DRM_ERROR("failed to move cursor bo into the GTT\n");
7566 goto fail_locked;
7567 }
7568
7569 ret = i915_gem_object_put_fence(obj);
7570 if (ret) {
7571 DRM_ERROR("failed to release fence for cursor");
7572 goto fail_unpin;
7573 }
7574
7575 addr = i915_gem_obj_ggtt_offset(obj);
7576 } else {
7577 int align = IS_I830(dev) ? 16 * 1024 : 256;
7578 ret = i915_gem_attach_phys_object(dev, obj,
7579 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7580 align);
7581 if (ret) {
7582 DRM_ERROR("failed to attach phys object\n");
7583 goto fail_locked;
7584 }
7585 addr = obj->phys_obj->handle->busaddr;
7586 }
7587
7588 if (IS_GEN2(dev))
7589 I915_WRITE(CURSIZE, (height << 12) | width);
7590
7591 finish:
7592 if (intel_crtc->cursor_bo) {
7593 if (dev_priv->info->cursor_needs_physical) {
7594 if (intel_crtc->cursor_bo != obj)
7595 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7596 } else
7597 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
7598 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
7599 }
7600
7601 mutex_unlock(&dev->struct_mutex);
7602
7603 intel_crtc->cursor_addr = addr;
7604 intel_crtc->cursor_bo = obj;
7605 intel_crtc->cursor_width = width;
7606 intel_crtc->cursor_height = height;
7607
7608 if (intel_crtc->active)
7609 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7610
7611 return 0;
7612 fail_unpin:
7613 i915_gem_object_unpin_from_display_plane(obj);
7614 fail_locked:
7615 mutex_unlock(&dev->struct_mutex);
7616 fail:
7617 drm_gem_object_unreference_unlocked(&obj->base);
7618 return ret;
7619 }
7620
7621 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7622 {
7623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7624
7625 intel_crtc->cursor_x = clamp_t(int, x, SHRT_MIN, SHRT_MAX);
7626 intel_crtc->cursor_y = clamp_t(int, y, SHRT_MIN, SHRT_MAX);
7627
7628 if (intel_crtc->active)
7629 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
7630
7631 return 0;
7632 }
7633
7634 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7635 u16 *blue, uint32_t start, uint32_t size)
7636 {
7637 int end = (start + size > 256) ? 256 : start + size, i;
7638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7639
7640 for (i = start; i < end; i++) {
7641 intel_crtc->lut_r[i] = red[i] >> 8;
7642 intel_crtc->lut_g[i] = green[i] >> 8;
7643 intel_crtc->lut_b[i] = blue[i] >> 8;
7644 }
7645
7646 intel_crtc_load_lut(crtc);
7647 }
7648
7649 /* VESA 640x480x72Hz mode to set on the pipe */
7650 static struct drm_display_mode load_detect_mode = {
7651 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7652 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7653 };
7654
7655 static struct drm_framebuffer *
7656 intel_framebuffer_create(struct drm_device *dev,
7657 struct drm_mode_fb_cmd2 *mode_cmd,
7658 struct drm_i915_gem_object *obj)
7659 {
7660 struct intel_framebuffer *intel_fb;
7661 int ret;
7662
7663 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7664 if (!intel_fb) {
7665 drm_gem_object_unreference_unlocked(&obj->base);
7666 return ERR_PTR(-ENOMEM);
7667 }
7668
7669 ret = i915_mutex_lock_interruptible(dev);
7670 if (ret)
7671 goto err;
7672
7673 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7674 mutex_unlock(&dev->struct_mutex);
7675 if (ret)
7676 goto err;
7677
7678 return &intel_fb->base;
7679 err:
7680 drm_gem_object_unreference_unlocked(&obj->base);
7681 kfree(intel_fb);
7682
7683 return ERR_PTR(ret);
7684 }
7685
7686 static u32
7687 intel_framebuffer_pitch_for_width(int width, int bpp)
7688 {
7689 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7690 return ALIGN(pitch, 64);
7691 }
7692
7693 static u32
7694 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7695 {
7696 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7697 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7698 }
7699
7700 static struct drm_framebuffer *
7701 intel_framebuffer_create_for_mode(struct drm_device *dev,
7702 struct drm_display_mode *mode,
7703 int depth, int bpp)
7704 {
7705 struct drm_i915_gem_object *obj;
7706 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
7707
7708 obj = i915_gem_alloc_object(dev,
7709 intel_framebuffer_size_for_mode(mode, bpp));
7710 if (obj == NULL)
7711 return ERR_PTR(-ENOMEM);
7712
7713 mode_cmd.width = mode->hdisplay;
7714 mode_cmd.height = mode->vdisplay;
7715 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7716 bpp);
7717 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
7718
7719 return intel_framebuffer_create(dev, &mode_cmd, obj);
7720 }
7721
7722 static struct drm_framebuffer *
7723 mode_fits_in_fbdev(struct drm_device *dev,
7724 struct drm_display_mode *mode)
7725 {
7726 #ifdef CONFIG_DRM_I915_FBDEV
7727 struct drm_i915_private *dev_priv = dev->dev_private;
7728 struct drm_i915_gem_object *obj;
7729 struct drm_framebuffer *fb;
7730
7731 if (dev_priv->fbdev == NULL)
7732 return NULL;
7733
7734 obj = dev_priv->fbdev->ifb.obj;
7735 if (obj == NULL)
7736 return NULL;
7737
7738 fb = &dev_priv->fbdev->ifb.base;
7739 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7740 fb->bits_per_pixel))
7741 return NULL;
7742
7743 if (obj->base.size < mode->vdisplay * fb->pitches[0])
7744 return NULL;
7745
7746 return fb;
7747 #else
7748 return NULL;
7749 #endif
7750 }
7751
7752 bool intel_get_load_detect_pipe(struct drm_connector *connector,
7753 struct drm_display_mode *mode,
7754 struct intel_load_detect_pipe *old)
7755 {
7756 struct intel_crtc *intel_crtc;
7757 struct intel_encoder *intel_encoder =
7758 intel_attached_encoder(connector);
7759 struct drm_crtc *possible_crtc;
7760 struct drm_encoder *encoder = &intel_encoder->base;
7761 struct drm_crtc *crtc = NULL;
7762 struct drm_device *dev = encoder->dev;
7763 struct drm_framebuffer *fb;
7764 int i = -1;
7765
7766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7767 connector->base.id, drm_get_connector_name(connector),
7768 encoder->base.id, drm_get_encoder_name(encoder));
7769
7770 /*
7771 * Algorithm gets a little messy:
7772 *
7773 * - if the connector already has an assigned crtc, use it (but make
7774 * sure it's on first)
7775 *
7776 * - try to find the first unused crtc that can drive this connector,
7777 * and use that if we find one
7778 */
7779
7780 /* See if we already have a CRTC for this connector */
7781 if (encoder->crtc) {
7782 crtc = encoder->crtc;
7783
7784 mutex_lock(&crtc->mutex);
7785
7786 old->dpms_mode = connector->dpms;
7787 old->load_detect_temp = false;
7788
7789 /* Make sure the crtc and connector are running */
7790 if (connector->dpms != DRM_MODE_DPMS_ON)
7791 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
7792
7793 return true;
7794 }
7795
7796 /* Find an unused one (if possible) */
7797 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7798 i++;
7799 if (!(encoder->possible_crtcs & (1 << i)))
7800 continue;
7801 if (!possible_crtc->enabled) {
7802 crtc = possible_crtc;
7803 break;
7804 }
7805 }
7806
7807 /*
7808 * If we didn't find an unused CRTC, don't use any.
7809 */
7810 if (!crtc) {
7811 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7812 return false;
7813 }
7814
7815 mutex_lock(&crtc->mutex);
7816 intel_encoder->new_crtc = to_intel_crtc(crtc);
7817 to_intel_connector(connector)->new_encoder = intel_encoder;
7818
7819 intel_crtc = to_intel_crtc(crtc);
7820 old->dpms_mode = connector->dpms;
7821 old->load_detect_temp = true;
7822 old->release_fb = NULL;
7823
7824 if (!mode)
7825 mode = &load_detect_mode;
7826
7827 /* We need a framebuffer large enough to accommodate all accesses
7828 * that the plane may generate whilst we perform load detection.
7829 * We can not rely on the fbcon either being present (we get called
7830 * during its initialisation to detect all boot displays, or it may
7831 * not even exist) or that it is large enough to satisfy the
7832 * requested mode.
7833 */
7834 fb = mode_fits_in_fbdev(dev, mode);
7835 if (fb == NULL) {
7836 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
7837 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7838 old->release_fb = fb;
7839 } else
7840 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
7841 if (IS_ERR(fb)) {
7842 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7843 mutex_unlock(&crtc->mutex);
7844 return false;
7845 }
7846
7847 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
7848 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
7849 if (old->release_fb)
7850 old->release_fb->funcs->destroy(old->release_fb);
7851 mutex_unlock(&crtc->mutex);
7852 return false;
7853 }
7854
7855 /* let the connector get through one full cycle before testing */
7856 intel_wait_for_vblank(dev, intel_crtc->pipe);
7857 return true;
7858 }
7859
7860 void intel_release_load_detect_pipe(struct drm_connector *connector,
7861 struct intel_load_detect_pipe *old)
7862 {
7863 struct intel_encoder *intel_encoder =
7864 intel_attached_encoder(connector);
7865 struct drm_encoder *encoder = &intel_encoder->base;
7866 struct drm_crtc *crtc = encoder->crtc;
7867
7868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7869 connector->base.id, drm_get_connector_name(connector),
7870 encoder->base.id, drm_get_encoder_name(encoder));
7871
7872 if (old->load_detect_temp) {
7873 to_intel_connector(connector)->new_encoder = NULL;
7874 intel_encoder->new_crtc = NULL;
7875 intel_set_mode(crtc, NULL, 0, 0, NULL);
7876
7877 if (old->release_fb) {
7878 drm_framebuffer_unregister_private(old->release_fb);
7879 drm_framebuffer_unreference(old->release_fb);
7880 }
7881
7882 mutex_unlock(&crtc->mutex);
7883 return;
7884 }
7885
7886 /* Switch crtc and encoder back off if necessary */
7887 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7888 connector->funcs->dpms(connector, old->dpms_mode);
7889
7890 mutex_unlock(&crtc->mutex);
7891 }
7892
7893 static int i9xx_pll_refclk(struct drm_device *dev,
7894 const struct intel_crtc_config *pipe_config)
7895 {
7896 struct drm_i915_private *dev_priv = dev->dev_private;
7897 u32 dpll = pipe_config->dpll_hw_state.dpll;
7898
7899 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7900 return dev_priv->vbt.lvds_ssc_freq;
7901 else if (HAS_PCH_SPLIT(dev))
7902 return 120000;
7903 else if (!IS_GEN2(dev))
7904 return 96000;
7905 else
7906 return 48000;
7907 }
7908
7909 /* Returns the clock of the currently programmed mode of the given pipe. */
7910 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7911 struct intel_crtc_config *pipe_config)
7912 {
7913 struct drm_device *dev = crtc->base.dev;
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 int pipe = pipe_config->cpu_transcoder;
7916 u32 dpll = pipe_config->dpll_hw_state.dpll;
7917 u32 fp;
7918 intel_clock_t clock;
7919 int refclk = i9xx_pll_refclk(dev, pipe_config);
7920
7921 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
7922 fp = pipe_config->dpll_hw_state.fp0;
7923 else
7924 fp = pipe_config->dpll_hw_state.fp1;
7925
7926 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
7927 if (IS_PINEVIEW(dev)) {
7928 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7929 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
7930 } else {
7931 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7932 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7933 }
7934
7935 if (!IS_GEN2(dev)) {
7936 if (IS_PINEVIEW(dev))
7937 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7938 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
7939 else
7940 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
7941 DPLL_FPA01_P1_POST_DIV_SHIFT);
7942
7943 switch (dpll & DPLL_MODE_MASK) {
7944 case DPLLB_MODE_DAC_SERIAL:
7945 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7946 5 : 10;
7947 break;
7948 case DPLLB_MODE_LVDS:
7949 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7950 7 : 14;
7951 break;
7952 default:
7953 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
7954 "mode\n", (int)(dpll & DPLL_MODE_MASK));
7955 return;
7956 }
7957
7958 if (IS_PINEVIEW(dev))
7959 pineview_clock(refclk, &clock);
7960 else
7961 i9xx_clock(refclk, &clock);
7962 } else {
7963 u32 lvds = I915_READ(LVDS);
7964 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
7965
7966 if (is_lvds) {
7967 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7968 DPLL_FPA01_P1_POST_DIV_SHIFT);
7969
7970 if (lvds & LVDS_CLKB_POWER_UP)
7971 clock.p2 = 7;
7972 else
7973 clock.p2 = 14;
7974 } else {
7975 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7976 clock.p1 = 2;
7977 else {
7978 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7979 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7980 }
7981 if (dpll & PLL_P2_DIVIDE_BY_4)
7982 clock.p2 = 4;
7983 else
7984 clock.p2 = 2;
7985 }
7986
7987 i9xx_clock(refclk, &clock);
7988 }
7989
7990 /*
7991 * This value includes pixel_multiplier. We will use
7992 * port_clock to compute adjusted_mode.crtc_clock in the
7993 * encoder's get_config() function.
7994 */
7995 pipe_config->port_clock = clock.dot;
7996 }
7997
7998 int intel_dotclock_calculate(int link_freq,
7999 const struct intel_link_m_n *m_n)
8000 {
8001 /*
8002 * The calculation for the data clock is:
8003 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8004 * But we want to avoid losing precison if possible, so:
8005 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8006 *
8007 * and the link clock is simpler:
8008 * link_clock = (m * link_clock) / n
8009 */
8010
8011 if (!m_n->link_n)
8012 return 0;
8013
8014 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8015 }
8016
8017 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8018 struct intel_crtc_config *pipe_config)
8019 {
8020 struct drm_device *dev = crtc->base.dev;
8021
8022 /* read out port_clock from the DPLL */
8023 i9xx_crtc_clock_get(crtc, pipe_config);
8024
8025 /*
8026 * This value does not include pixel_multiplier.
8027 * We will check that port_clock and adjusted_mode.crtc_clock
8028 * agree once we know their relationship in the encoder's
8029 * get_config() function.
8030 */
8031 pipe_config->adjusted_mode.crtc_clock =
8032 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8033 &pipe_config->fdi_m_n);
8034 }
8035
8036 /** Returns the currently programmed mode of the given pipe. */
8037 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8038 struct drm_crtc *crtc)
8039 {
8040 struct drm_i915_private *dev_priv = dev->dev_private;
8041 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8042 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8043 struct drm_display_mode *mode;
8044 struct intel_crtc_config pipe_config;
8045 int htot = I915_READ(HTOTAL(cpu_transcoder));
8046 int hsync = I915_READ(HSYNC(cpu_transcoder));
8047 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8048 int vsync = I915_READ(VSYNC(cpu_transcoder));
8049 enum pipe pipe = intel_crtc->pipe;
8050
8051 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8052 if (!mode)
8053 return NULL;
8054
8055 /*
8056 * Construct a pipe_config sufficient for getting the clock info
8057 * back out of crtc_clock_get.
8058 *
8059 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8060 * to use a real value here instead.
8061 */
8062 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8063 pipe_config.pixel_multiplier = 1;
8064 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8065 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8066 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8067 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8068
8069 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8070 mode->hdisplay = (htot & 0xffff) + 1;
8071 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8072 mode->hsync_start = (hsync & 0xffff) + 1;
8073 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8074 mode->vdisplay = (vtot & 0xffff) + 1;
8075 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8076 mode->vsync_start = (vsync & 0xffff) + 1;
8077 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8078
8079 drm_mode_set_name(mode);
8080
8081 return mode;
8082 }
8083
8084 static void intel_increase_pllclock(struct drm_crtc *crtc)
8085 {
8086 struct drm_device *dev = crtc->dev;
8087 drm_i915_private_t *dev_priv = dev->dev_private;
8088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8089 int pipe = intel_crtc->pipe;
8090 int dpll_reg = DPLL(pipe);
8091 int dpll;
8092
8093 if (HAS_PCH_SPLIT(dev))
8094 return;
8095
8096 if (!dev_priv->lvds_downclock_avail)
8097 return;
8098
8099 dpll = I915_READ(dpll_reg);
8100 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8101 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8102
8103 assert_panel_unlocked(dev_priv, pipe);
8104
8105 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8106 I915_WRITE(dpll_reg, dpll);
8107 intel_wait_for_vblank(dev, pipe);
8108
8109 dpll = I915_READ(dpll_reg);
8110 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8111 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8112 }
8113 }
8114
8115 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8116 {
8117 struct drm_device *dev = crtc->dev;
8118 drm_i915_private_t *dev_priv = dev->dev_private;
8119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8120
8121 if (HAS_PCH_SPLIT(dev))
8122 return;
8123
8124 if (!dev_priv->lvds_downclock_avail)
8125 return;
8126
8127 /*
8128 * Since this is called by a timer, we should never get here in
8129 * the manual case.
8130 */
8131 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8132 int pipe = intel_crtc->pipe;
8133 int dpll_reg = DPLL(pipe);
8134 int dpll;
8135
8136 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8137
8138 assert_panel_unlocked(dev_priv, pipe);
8139
8140 dpll = I915_READ(dpll_reg);
8141 dpll |= DISPLAY_RATE_SELECT_FPA1;
8142 I915_WRITE(dpll_reg, dpll);
8143 intel_wait_for_vblank(dev, pipe);
8144 dpll = I915_READ(dpll_reg);
8145 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8146 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8147 }
8148
8149 }
8150
8151 void intel_mark_busy(struct drm_device *dev)
8152 {
8153 struct drm_i915_private *dev_priv = dev->dev_private;
8154
8155 hsw_package_c8_gpu_busy(dev_priv);
8156 i915_update_gfx_val(dev_priv);
8157 }
8158
8159 void intel_mark_idle(struct drm_device *dev)
8160 {
8161 struct drm_i915_private *dev_priv = dev->dev_private;
8162 struct drm_crtc *crtc;
8163
8164 hsw_package_c8_gpu_idle(dev_priv);
8165
8166 if (!i915_powersave)
8167 return;
8168
8169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8170 if (!crtc->fb)
8171 continue;
8172
8173 intel_decrease_pllclock(crtc);
8174 }
8175
8176 if (dev_priv->info->gen >= 6)
8177 gen6_rps_idle(dev->dev_private);
8178 }
8179
8180 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8181 struct intel_ring_buffer *ring)
8182 {
8183 struct drm_device *dev = obj->base.dev;
8184 struct drm_crtc *crtc;
8185
8186 if (!i915_powersave)
8187 return;
8188
8189 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8190 if (!crtc->fb)
8191 continue;
8192
8193 if (to_intel_framebuffer(crtc->fb)->obj != obj)
8194 continue;
8195
8196 intel_increase_pllclock(crtc);
8197 if (ring && intel_fbc_enabled(dev))
8198 ring->fbc_dirty = true;
8199 }
8200 }
8201
8202 static void intel_crtc_destroy(struct drm_crtc *crtc)
8203 {
8204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8205 struct drm_device *dev = crtc->dev;
8206 struct intel_unpin_work *work;
8207 unsigned long flags;
8208
8209 spin_lock_irqsave(&dev->event_lock, flags);
8210 work = intel_crtc->unpin_work;
8211 intel_crtc->unpin_work = NULL;
8212 spin_unlock_irqrestore(&dev->event_lock, flags);
8213
8214 if (work) {
8215 cancel_work_sync(&work->work);
8216 kfree(work);
8217 }
8218
8219 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
8220
8221 drm_crtc_cleanup(crtc);
8222
8223 kfree(intel_crtc);
8224 }
8225
8226 static void intel_unpin_work_fn(struct work_struct *__work)
8227 {
8228 struct intel_unpin_work *work =
8229 container_of(__work, struct intel_unpin_work, work);
8230 struct drm_device *dev = work->crtc->dev;
8231
8232 mutex_lock(&dev->struct_mutex);
8233 intel_unpin_fb_obj(work->old_fb_obj);
8234 drm_gem_object_unreference(&work->pending_flip_obj->base);
8235 drm_gem_object_unreference(&work->old_fb_obj->base);
8236
8237 intel_update_fbc(dev);
8238 mutex_unlock(&dev->struct_mutex);
8239
8240 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8241 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8242
8243 kfree(work);
8244 }
8245
8246 static void do_intel_finish_page_flip(struct drm_device *dev,
8247 struct drm_crtc *crtc)
8248 {
8249 drm_i915_private_t *dev_priv = dev->dev_private;
8250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8251 struct intel_unpin_work *work;
8252 unsigned long flags;
8253
8254 /* Ignore early vblank irqs */
8255 if (intel_crtc == NULL)
8256 return;
8257
8258 spin_lock_irqsave(&dev->event_lock, flags);
8259 work = intel_crtc->unpin_work;
8260
8261 /* Ensure we don't miss a work->pending update ... */
8262 smp_rmb();
8263
8264 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8265 spin_unlock_irqrestore(&dev->event_lock, flags);
8266 return;
8267 }
8268
8269 /* and that the unpin work is consistent wrt ->pending. */
8270 smp_rmb();
8271
8272 intel_crtc->unpin_work = NULL;
8273
8274 if (work->event)
8275 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8276
8277 drm_vblank_put(dev, intel_crtc->pipe);
8278
8279 spin_unlock_irqrestore(&dev->event_lock, flags);
8280
8281 wake_up_all(&dev_priv->pending_flip_queue);
8282
8283 queue_work(dev_priv->wq, &work->work);
8284
8285 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8286 }
8287
8288 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8289 {
8290 drm_i915_private_t *dev_priv = dev->dev_private;
8291 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8292
8293 do_intel_finish_page_flip(dev, crtc);
8294 }
8295
8296 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8297 {
8298 drm_i915_private_t *dev_priv = dev->dev_private;
8299 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8300
8301 do_intel_finish_page_flip(dev, crtc);
8302 }
8303
8304 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8305 {
8306 drm_i915_private_t *dev_priv = dev->dev_private;
8307 struct intel_crtc *intel_crtc =
8308 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8309 unsigned long flags;
8310
8311 /* NB: An MMIO update of the plane base pointer will also
8312 * generate a page-flip completion irq, i.e. every modeset
8313 * is also accompanied by a spurious intel_prepare_page_flip().
8314 */
8315 spin_lock_irqsave(&dev->event_lock, flags);
8316 if (intel_crtc->unpin_work)
8317 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
8318 spin_unlock_irqrestore(&dev->event_lock, flags);
8319 }
8320
8321 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
8322 {
8323 /* Ensure that the work item is consistent when activating it ... */
8324 smp_wmb();
8325 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
8326 /* and that it is marked active as soon as the irq could fire. */
8327 smp_wmb();
8328 }
8329
8330 static int intel_gen2_queue_flip(struct drm_device *dev,
8331 struct drm_crtc *crtc,
8332 struct drm_framebuffer *fb,
8333 struct drm_i915_gem_object *obj,
8334 uint32_t flags)
8335 {
8336 struct drm_i915_private *dev_priv = dev->dev_private;
8337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8338 u32 flip_mask;
8339 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8340 int ret;
8341
8342 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8343 if (ret)
8344 goto err;
8345
8346 ret = intel_ring_begin(ring, 6);
8347 if (ret)
8348 goto err_unpin;
8349
8350 /* Can't queue multiple flips, so wait for the previous
8351 * one to finish before executing the next.
8352 */
8353 if (intel_crtc->plane)
8354 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8355 else
8356 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8357 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8358 intel_ring_emit(ring, MI_NOOP);
8359 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8360 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8361 intel_ring_emit(ring, fb->pitches[0]);
8362 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8363 intel_ring_emit(ring, 0); /* aux display base address, unused */
8364
8365 intel_mark_page_flip_active(intel_crtc);
8366 __intel_ring_advance(ring);
8367 return 0;
8368
8369 err_unpin:
8370 intel_unpin_fb_obj(obj);
8371 err:
8372 return ret;
8373 }
8374
8375 static int intel_gen3_queue_flip(struct drm_device *dev,
8376 struct drm_crtc *crtc,
8377 struct drm_framebuffer *fb,
8378 struct drm_i915_gem_object *obj,
8379 uint32_t flags)
8380 {
8381 struct drm_i915_private *dev_priv = dev->dev_private;
8382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8383 u32 flip_mask;
8384 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8385 int ret;
8386
8387 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8388 if (ret)
8389 goto err;
8390
8391 ret = intel_ring_begin(ring, 6);
8392 if (ret)
8393 goto err_unpin;
8394
8395 if (intel_crtc->plane)
8396 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8397 else
8398 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
8399 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8400 intel_ring_emit(ring, MI_NOOP);
8401 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8402 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8403 intel_ring_emit(ring, fb->pitches[0]);
8404 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8405 intel_ring_emit(ring, MI_NOOP);
8406
8407 intel_mark_page_flip_active(intel_crtc);
8408 __intel_ring_advance(ring);
8409 return 0;
8410
8411 err_unpin:
8412 intel_unpin_fb_obj(obj);
8413 err:
8414 return ret;
8415 }
8416
8417 static int intel_gen4_queue_flip(struct drm_device *dev,
8418 struct drm_crtc *crtc,
8419 struct drm_framebuffer *fb,
8420 struct drm_i915_gem_object *obj,
8421 uint32_t flags)
8422 {
8423 struct drm_i915_private *dev_priv = dev->dev_private;
8424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8425 uint32_t pf, pipesrc;
8426 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8427 int ret;
8428
8429 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8430 if (ret)
8431 goto err;
8432
8433 ret = intel_ring_begin(ring, 4);
8434 if (ret)
8435 goto err_unpin;
8436
8437 /* i965+ uses the linear or tiled offsets from the
8438 * Display Registers (which do not change across a page-flip)
8439 * so we need only reprogram the base address.
8440 */
8441 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8442 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8443 intel_ring_emit(ring, fb->pitches[0]);
8444 intel_ring_emit(ring,
8445 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
8446 obj->tiling_mode);
8447
8448 /* XXX Enabling the panel-fitter across page-flip is so far
8449 * untested on non-native modes, so ignore it for now.
8450 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8451 */
8452 pf = 0;
8453 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8454 intel_ring_emit(ring, pf | pipesrc);
8455
8456 intel_mark_page_flip_active(intel_crtc);
8457 __intel_ring_advance(ring);
8458 return 0;
8459
8460 err_unpin:
8461 intel_unpin_fb_obj(obj);
8462 err:
8463 return ret;
8464 }
8465
8466 static int intel_gen6_queue_flip(struct drm_device *dev,
8467 struct drm_crtc *crtc,
8468 struct drm_framebuffer *fb,
8469 struct drm_i915_gem_object *obj,
8470 uint32_t flags)
8471 {
8472 struct drm_i915_private *dev_priv = dev->dev_private;
8473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8474 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8475 uint32_t pf, pipesrc;
8476 int ret;
8477
8478 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8479 if (ret)
8480 goto err;
8481
8482 ret = intel_ring_begin(ring, 4);
8483 if (ret)
8484 goto err_unpin;
8485
8486 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8487 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8488 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
8489 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8490
8491 /* Contrary to the suggestions in the documentation,
8492 * "Enable Panel Fitter" does not seem to be required when page
8493 * flipping with a non-native mode, and worse causes a normal
8494 * modeset to fail.
8495 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8496 */
8497 pf = 0;
8498 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
8499 intel_ring_emit(ring, pf | pipesrc);
8500
8501 intel_mark_page_flip_active(intel_crtc);
8502 __intel_ring_advance(ring);
8503 return 0;
8504
8505 err_unpin:
8506 intel_unpin_fb_obj(obj);
8507 err:
8508 return ret;
8509 }
8510
8511 static int intel_gen7_queue_flip(struct drm_device *dev,
8512 struct drm_crtc *crtc,
8513 struct drm_framebuffer *fb,
8514 struct drm_i915_gem_object *obj,
8515 uint32_t flags)
8516 {
8517 struct drm_i915_private *dev_priv = dev->dev_private;
8518 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8519 struct intel_ring_buffer *ring;
8520 uint32_t plane_bit = 0;
8521 int len, ret;
8522
8523 ring = obj->ring;
8524 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
8525 ring = &dev_priv->ring[BCS];
8526
8527 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8528 if (ret)
8529 goto err;
8530
8531 switch(intel_crtc->plane) {
8532 case PLANE_A:
8533 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8534 break;
8535 case PLANE_B:
8536 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8537 break;
8538 case PLANE_C:
8539 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8540 break;
8541 default:
8542 WARN_ONCE(1, "unknown plane in flip command\n");
8543 ret = -ENODEV;
8544 goto err_unpin;
8545 }
8546
8547 len = 4;
8548 if (ring->id == RCS)
8549 len += 6;
8550
8551 ret = intel_ring_begin(ring, len);
8552 if (ret)
8553 goto err_unpin;
8554
8555 /* Unmask the flip-done completion message. Note that the bspec says that
8556 * we should do this for both the BCS and RCS, and that we must not unmask
8557 * more than one flip event at any time (or ensure that one flip message
8558 * can be sent by waiting for flip-done prior to queueing new flips).
8559 * Experimentation says that BCS works despite DERRMR masking all
8560 * flip-done completion events and that unmasking all planes at once
8561 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8562 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8563 */
8564 if (ring->id == RCS) {
8565 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8566 intel_ring_emit(ring, DERRMR);
8567 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8568 DERRMR_PIPEB_PRI_FLIP_DONE |
8569 DERRMR_PIPEC_PRI_FLIP_DONE));
8570 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8571 intel_ring_emit(ring, DERRMR);
8572 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8573 }
8574
8575 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
8576 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
8577 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8578 intel_ring_emit(ring, (MI_NOOP));
8579
8580 intel_mark_page_flip_active(intel_crtc);
8581 __intel_ring_advance(ring);
8582 return 0;
8583
8584 err_unpin:
8585 intel_unpin_fb_obj(obj);
8586 err:
8587 return ret;
8588 }
8589
8590 static int intel_default_queue_flip(struct drm_device *dev,
8591 struct drm_crtc *crtc,
8592 struct drm_framebuffer *fb,
8593 struct drm_i915_gem_object *obj,
8594 uint32_t flags)
8595 {
8596 return -ENODEV;
8597 }
8598
8599 static int intel_crtc_page_flip(struct drm_crtc *crtc,
8600 struct drm_framebuffer *fb,
8601 struct drm_pending_vblank_event *event,
8602 uint32_t page_flip_flags)
8603 {
8604 struct drm_device *dev = crtc->dev;
8605 struct drm_i915_private *dev_priv = dev->dev_private;
8606 struct drm_framebuffer *old_fb = crtc->fb;
8607 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
8608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8609 struct intel_unpin_work *work;
8610 unsigned long flags;
8611 int ret;
8612
8613 /* Can't change pixel format via MI display flips. */
8614 if (fb->pixel_format != crtc->fb->pixel_format)
8615 return -EINVAL;
8616
8617 /*
8618 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8619 * Note that pitch changes could also affect these register.
8620 */
8621 if (INTEL_INFO(dev)->gen > 3 &&
8622 (fb->offsets[0] != crtc->fb->offsets[0] ||
8623 fb->pitches[0] != crtc->fb->pitches[0]))
8624 return -EINVAL;
8625
8626 work = kzalloc(sizeof(*work), GFP_KERNEL);
8627 if (work == NULL)
8628 return -ENOMEM;
8629
8630 work->event = event;
8631 work->crtc = crtc;
8632 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
8633 INIT_WORK(&work->work, intel_unpin_work_fn);
8634
8635 ret = drm_vblank_get(dev, intel_crtc->pipe);
8636 if (ret)
8637 goto free_work;
8638
8639 /* We borrow the event spin lock for protecting unpin_work */
8640 spin_lock_irqsave(&dev->event_lock, flags);
8641 if (intel_crtc->unpin_work) {
8642 spin_unlock_irqrestore(&dev->event_lock, flags);
8643 kfree(work);
8644 drm_vblank_put(dev, intel_crtc->pipe);
8645
8646 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
8647 return -EBUSY;
8648 }
8649 intel_crtc->unpin_work = work;
8650 spin_unlock_irqrestore(&dev->event_lock, flags);
8651
8652 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8653 flush_workqueue(dev_priv->wq);
8654
8655 ret = i915_mutex_lock_interruptible(dev);
8656 if (ret)
8657 goto cleanup;
8658
8659 /* Reference the objects for the scheduled work. */
8660 drm_gem_object_reference(&work->old_fb_obj->base);
8661 drm_gem_object_reference(&obj->base);
8662
8663 crtc->fb = fb;
8664
8665 work->pending_flip_obj = obj;
8666
8667 work->enable_stall_check = true;
8668
8669 atomic_inc(&intel_crtc->unpin_work_count);
8670 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
8671
8672 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8673 if (ret)
8674 goto cleanup_pending;
8675
8676 intel_disable_fbc(dev);
8677 intel_mark_fb_busy(obj, NULL);
8678 mutex_unlock(&dev->struct_mutex);
8679
8680 trace_i915_flip_request(intel_crtc->plane, obj);
8681
8682 return 0;
8683
8684 cleanup_pending:
8685 atomic_dec(&intel_crtc->unpin_work_count);
8686 crtc->fb = old_fb;
8687 drm_gem_object_unreference(&work->old_fb_obj->base);
8688 drm_gem_object_unreference(&obj->base);
8689 mutex_unlock(&dev->struct_mutex);
8690
8691 cleanup:
8692 spin_lock_irqsave(&dev->event_lock, flags);
8693 intel_crtc->unpin_work = NULL;
8694 spin_unlock_irqrestore(&dev->event_lock, flags);
8695
8696 drm_vblank_put(dev, intel_crtc->pipe);
8697 free_work:
8698 kfree(work);
8699
8700 return ret;
8701 }
8702
8703 static struct drm_crtc_helper_funcs intel_helper_funcs = {
8704 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8705 .load_lut = intel_crtc_load_lut,
8706 };
8707
8708 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8709 struct drm_crtc *crtc)
8710 {
8711 struct drm_device *dev;
8712 struct drm_crtc *tmp;
8713 int crtc_mask = 1;
8714
8715 WARN(!crtc, "checking null crtc?\n");
8716
8717 dev = crtc->dev;
8718
8719 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8720 if (tmp == crtc)
8721 break;
8722 crtc_mask <<= 1;
8723 }
8724
8725 if (encoder->possible_crtcs & crtc_mask)
8726 return true;
8727 return false;
8728 }
8729
8730 /**
8731 * intel_modeset_update_staged_output_state
8732 *
8733 * Updates the staged output configuration state, e.g. after we've read out the
8734 * current hw state.
8735 */
8736 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
8737 {
8738 struct intel_encoder *encoder;
8739 struct intel_connector *connector;
8740
8741 list_for_each_entry(connector, &dev->mode_config.connector_list,
8742 base.head) {
8743 connector->new_encoder =
8744 to_intel_encoder(connector->base.encoder);
8745 }
8746
8747 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8748 base.head) {
8749 encoder->new_crtc =
8750 to_intel_crtc(encoder->base.crtc);
8751 }
8752 }
8753
8754 /**
8755 * intel_modeset_commit_output_state
8756 *
8757 * This function copies the stage display pipe configuration to the real one.
8758 */
8759 static void intel_modeset_commit_output_state(struct drm_device *dev)
8760 {
8761 struct intel_encoder *encoder;
8762 struct intel_connector *connector;
8763
8764 list_for_each_entry(connector, &dev->mode_config.connector_list,
8765 base.head) {
8766 connector->base.encoder = &connector->new_encoder->base;
8767 }
8768
8769 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8770 base.head) {
8771 encoder->base.crtc = &encoder->new_crtc->base;
8772 }
8773 }
8774
8775 static void
8776 connected_sink_compute_bpp(struct intel_connector * connector,
8777 struct intel_crtc_config *pipe_config)
8778 {
8779 int bpp = pipe_config->pipe_bpp;
8780
8781 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8782 connector->base.base.id,
8783 drm_get_connector_name(&connector->base));
8784
8785 /* Don't use an invalid EDID bpc value */
8786 if (connector->base.display_info.bpc &&
8787 connector->base.display_info.bpc * 3 < bpp) {
8788 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8789 bpp, connector->base.display_info.bpc*3);
8790 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8791 }
8792
8793 /* Clamp bpp to 8 on screens without EDID 1.4 */
8794 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8795 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8796 bpp);
8797 pipe_config->pipe_bpp = 24;
8798 }
8799 }
8800
8801 static int
8802 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8803 struct drm_framebuffer *fb,
8804 struct intel_crtc_config *pipe_config)
8805 {
8806 struct drm_device *dev = crtc->base.dev;
8807 struct intel_connector *connector;
8808 int bpp;
8809
8810 switch (fb->pixel_format) {
8811 case DRM_FORMAT_C8:
8812 bpp = 8*3; /* since we go through a colormap */
8813 break;
8814 case DRM_FORMAT_XRGB1555:
8815 case DRM_FORMAT_ARGB1555:
8816 /* checked in intel_framebuffer_init already */
8817 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8818 return -EINVAL;
8819 case DRM_FORMAT_RGB565:
8820 bpp = 6*3; /* min is 18bpp */
8821 break;
8822 case DRM_FORMAT_XBGR8888:
8823 case DRM_FORMAT_ABGR8888:
8824 /* checked in intel_framebuffer_init already */
8825 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8826 return -EINVAL;
8827 case DRM_FORMAT_XRGB8888:
8828 case DRM_FORMAT_ARGB8888:
8829 bpp = 8*3;
8830 break;
8831 case DRM_FORMAT_XRGB2101010:
8832 case DRM_FORMAT_ARGB2101010:
8833 case DRM_FORMAT_XBGR2101010:
8834 case DRM_FORMAT_ABGR2101010:
8835 /* checked in intel_framebuffer_init already */
8836 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8837 return -EINVAL;
8838 bpp = 10*3;
8839 break;
8840 /* TODO: gen4+ supports 16 bpc floating point, too. */
8841 default:
8842 DRM_DEBUG_KMS("unsupported depth\n");
8843 return -EINVAL;
8844 }
8845
8846 pipe_config->pipe_bpp = bpp;
8847
8848 /* Clamp display bpp to EDID value */
8849 list_for_each_entry(connector, &dev->mode_config.connector_list,
8850 base.head) {
8851 if (!connector->new_encoder ||
8852 connector->new_encoder->new_crtc != crtc)
8853 continue;
8854
8855 connected_sink_compute_bpp(connector, pipe_config);
8856 }
8857
8858 return bpp;
8859 }
8860
8861 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8862 {
8863 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8864 "type: 0x%x flags: 0x%x\n",
8865 mode->crtc_clock,
8866 mode->crtc_hdisplay, mode->crtc_hsync_start,
8867 mode->crtc_hsync_end, mode->crtc_htotal,
8868 mode->crtc_vdisplay, mode->crtc_vsync_start,
8869 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8870 }
8871
8872 static void intel_dump_pipe_config(struct intel_crtc *crtc,
8873 struct intel_crtc_config *pipe_config,
8874 const char *context)
8875 {
8876 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8877 context, pipe_name(crtc->pipe));
8878
8879 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8880 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8881 pipe_config->pipe_bpp, pipe_config->dither);
8882 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8883 pipe_config->has_pch_encoder,
8884 pipe_config->fdi_lanes,
8885 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8886 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8887 pipe_config->fdi_m_n.tu);
8888 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8889 pipe_config->has_dp_encoder,
8890 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8891 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8892 pipe_config->dp_m_n.tu);
8893 DRM_DEBUG_KMS("requested mode:\n");
8894 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8895 DRM_DEBUG_KMS("adjusted mode:\n");
8896 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
8897 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
8898 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
8899 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8900 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
8901 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8902 pipe_config->gmch_pfit.control,
8903 pipe_config->gmch_pfit.pgm_ratios,
8904 pipe_config->gmch_pfit.lvds_border_bits);
8905 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
8906 pipe_config->pch_pfit.pos,
8907 pipe_config->pch_pfit.size,
8908 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
8909 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
8910 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
8911 }
8912
8913 static bool check_encoder_cloning(struct drm_crtc *crtc)
8914 {
8915 int num_encoders = 0;
8916 bool uncloneable_encoders = false;
8917 struct intel_encoder *encoder;
8918
8919 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8920 base.head) {
8921 if (&encoder->new_crtc->base != crtc)
8922 continue;
8923
8924 num_encoders++;
8925 if (!encoder->cloneable)
8926 uncloneable_encoders = true;
8927 }
8928
8929 return !(num_encoders > 1 && uncloneable_encoders);
8930 }
8931
8932 static struct intel_crtc_config *
8933 intel_modeset_pipe_config(struct drm_crtc *crtc,
8934 struct drm_framebuffer *fb,
8935 struct drm_display_mode *mode)
8936 {
8937 struct drm_device *dev = crtc->dev;
8938 struct intel_encoder *encoder;
8939 struct intel_crtc_config *pipe_config;
8940 int plane_bpp, ret = -EINVAL;
8941 bool retry = true;
8942
8943 if (!check_encoder_cloning(crtc)) {
8944 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8945 return ERR_PTR(-EINVAL);
8946 }
8947
8948 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8949 if (!pipe_config)
8950 return ERR_PTR(-ENOMEM);
8951
8952 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8953 drm_mode_copy(&pipe_config->requested_mode, mode);
8954
8955 pipe_config->cpu_transcoder =
8956 (enum transcoder) to_intel_crtc(crtc)->pipe;
8957 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8958
8959 /*
8960 * Sanitize sync polarity flags based on requested ones. If neither
8961 * positive or negative polarity is requested, treat this as meaning
8962 * negative polarity.
8963 */
8964 if (!(pipe_config->adjusted_mode.flags &
8965 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8966 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8967
8968 if (!(pipe_config->adjusted_mode.flags &
8969 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8970 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8971
8972 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8973 * plane pixel format and any sink constraints into account. Returns the
8974 * source plane bpp so that dithering can be selected on mismatches
8975 * after encoders and crtc also have had their say. */
8976 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8977 fb, pipe_config);
8978 if (plane_bpp < 0)
8979 goto fail;
8980
8981 /*
8982 * Determine the real pipe dimensions. Note that stereo modes can
8983 * increase the actual pipe size due to the frame doubling and
8984 * insertion of additional space for blanks between the frame. This
8985 * is stored in the crtc timings. We use the requested mode to do this
8986 * computation to clearly distinguish it from the adjusted mode, which
8987 * can be changed by the connectors in the below retry loop.
8988 */
8989 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8990 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8991 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8992
8993 encoder_retry:
8994 /* Ensure the port clock defaults are reset when retrying. */
8995 pipe_config->port_clock = 0;
8996 pipe_config->pixel_multiplier = 1;
8997
8998 /* Fill in default crtc timings, allow encoders to overwrite them. */
8999 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9000
9001 /* Pass our mode to the connectors and the CRTC to give them a chance to
9002 * adjust it according to limitations or connector properties, and also
9003 * a chance to reject the mode entirely.
9004 */
9005 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9006 base.head) {
9007
9008 if (&encoder->new_crtc->base != crtc)
9009 continue;
9010
9011 if (!(encoder->compute_config(encoder, pipe_config))) {
9012 DRM_DEBUG_KMS("Encoder config failure\n");
9013 goto fail;
9014 }
9015 }
9016
9017 /* Set default port clock if not overwritten by the encoder. Needs to be
9018 * done afterwards in case the encoder adjusts the mode. */
9019 if (!pipe_config->port_clock)
9020 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9021 * pipe_config->pixel_multiplier;
9022
9023 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9024 if (ret < 0) {
9025 DRM_DEBUG_KMS("CRTC fixup failed\n");
9026 goto fail;
9027 }
9028
9029 if (ret == RETRY) {
9030 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9031 ret = -EINVAL;
9032 goto fail;
9033 }
9034
9035 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9036 retry = false;
9037 goto encoder_retry;
9038 }
9039
9040 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9041 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9042 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9043
9044 return pipe_config;
9045 fail:
9046 kfree(pipe_config);
9047 return ERR_PTR(ret);
9048 }
9049
9050 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9051 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9052 static void
9053 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9054 unsigned *prepare_pipes, unsigned *disable_pipes)
9055 {
9056 struct intel_crtc *intel_crtc;
9057 struct drm_device *dev = crtc->dev;
9058 struct intel_encoder *encoder;
9059 struct intel_connector *connector;
9060 struct drm_crtc *tmp_crtc;
9061
9062 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9063
9064 /* Check which crtcs have changed outputs connected to them, these need
9065 * to be part of the prepare_pipes mask. We don't (yet) support global
9066 * modeset across multiple crtcs, so modeset_pipes will only have one
9067 * bit set at most. */
9068 list_for_each_entry(connector, &dev->mode_config.connector_list,
9069 base.head) {
9070 if (connector->base.encoder == &connector->new_encoder->base)
9071 continue;
9072
9073 if (connector->base.encoder) {
9074 tmp_crtc = connector->base.encoder->crtc;
9075
9076 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9077 }
9078
9079 if (connector->new_encoder)
9080 *prepare_pipes |=
9081 1 << connector->new_encoder->new_crtc->pipe;
9082 }
9083
9084 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9085 base.head) {
9086 if (encoder->base.crtc == &encoder->new_crtc->base)
9087 continue;
9088
9089 if (encoder->base.crtc) {
9090 tmp_crtc = encoder->base.crtc;
9091
9092 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9093 }
9094
9095 if (encoder->new_crtc)
9096 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9097 }
9098
9099 /* Check for any pipes that will be fully disabled ... */
9100 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9101 base.head) {
9102 bool used = false;
9103
9104 /* Don't try to disable disabled crtcs. */
9105 if (!intel_crtc->base.enabled)
9106 continue;
9107
9108 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9109 base.head) {
9110 if (encoder->new_crtc == intel_crtc)
9111 used = true;
9112 }
9113
9114 if (!used)
9115 *disable_pipes |= 1 << intel_crtc->pipe;
9116 }
9117
9118
9119 /* set_mode is also used to update properties on life display pipes. */
9120 intel_crtc = to_intel_crtc(crtc);
9121 if (crtc->enabled)
9122 *prepare_pipes |= 1 << intel_crtc->pipe;
9123
9124 /*
9125 * For simplicity do a full modeset on any pipe where the output routing
9126 * changed. We could be more clever, but that would require us to be
9127 * more careful with calling the relevant encoder->mode_set functions.
9128 */
9129 if (*prepare_pipes)
9130 *modeset_pipes = *prepare_pipes;
9131
9132 /* ... and mask these out. */
9133 *modeset_pipes &= ~(*disable_pipes);
9134 *prepare_pipes &= ~(*disable_pipes);
9135
9136 /*
9137 * HACK: We don't (yet) fully support global modesets. intel_set_config
9138 * obies this rule, but the modeset restore mode of
9139 * intel_modeset_setup_hw_state does not.
9140 */
9141 *modeset_pipes &= 1 << intel_crtc->pipe;
9142 *prepare_pipes &= 1 << intel_crtc->pipe;
9143
9144 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9145 *modeset_pipes, *prepare_pipes, *disable_pipes);
9146 }
9147
9148 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9149 {
9150 struct drm_encoder *encoder;
9151 struct drm_device *dev = crtc->dev;
9152
9153 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9154 if (encoder->crtc == crtc)
9155 return true;
9156
9157 return false;
9158 }
9159
9160 static void
9161 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9162 {
9163 struct intel_encoder *intel_encoder;
9164 struct intel_crtc *intel_crtc;
9165 struct drm_connector *connector;
9166
9167 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9168 base.head) {
9169 if (!intel_encoder->base.crtc)
9170 continue;
9171
9172 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9173
9174 if (prepare_pipes & (1 << intel_crtc->pipe))
9175 intel_encoder->connectors_active = false;
9176 }
9177
9178 intel_modeset_commit_output_state(dev);
9179
9180 /* Update computed state. */
9181 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
9182 base.head) {
9183 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
9184 }
9185
9186 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9187 if (!connector->encoder || !connector->encoder->crtc)
9188 continue;
9189
9190 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9191
9192 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9193 struct drm_property *dpms_property =
9194 dev->mode_config.dpms_property;
9195
9196 connector->dpms = DRM_MODE_DPMS_ON;
9197 drm_object_property_set_value(&connector->base,
9198 dpms_property,
9199 DRM_MODE_DPMS_ON);
9200
9201 intel_encoder = to_intel_encoder(connector->encoder);
9202 intel_encoder->connectors_active = true;
9203 }
9204 }
9205
9206 }
9207
9208 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9209 {
9210 int diff;
9211
9212 if (clock1 == clock2)
9213 return true;
9214
9215 if (!clock1 || !clock2)
9216 return false;
9217
9218 diff = abs(clock1 - clock2);
9219
9220 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9221 return true;
9222
9223 return false;
9224 }
9225
9226 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9227 list_for_each_entry((intel_crtc), \
9228 &(dev)->mode_config.crtc_list, \
9229 base.head) \
9230 if (mask & (1 <<(intel_crtc)->pipe))
9231
9232 static bool
9233 intel_pipe_config_compare(struct drm_device *dev,
9234 struct intel_crtc_config *current_config,
9235 struct intel_crtc_config *pipe_config)
9236 {
9237 #define PIPE_CONF_CHECK_X(name) \
9238 if (current_config->name != pipe_config->name) { \
9239 DRM_ERROR("mismatch in " #name " " \
9240 "(expected 0x%08x, found 0x%08x)\n", \
9241 current_config->name, \
9242 pipe_config->name); \
9243 return false; \
9244 }
9245
9246 #define PIPE_CONF_CHECK_I(name) \
9247 if (current_config->name != pipe_config->name) { \
9248 DRM_ERROR("mismatch in " #name " " \
9249 "(expected %i, found %i)\n", \
9250 current_config->name, \
9251 pipe_config->name); \
9252 return false; \
9253 }
9254
9255 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9256 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9257 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9258 "(expected %i, found %i)\n", \
9259 current_config->name & (mask), \
9260 pipe_config->name & (mask)); \
9261 return false; \
9262 }
9263
9264 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9265 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9266 DRM_ERROR("mismatch in " #name " " \
9267 "(expected %i, found %i)\n", \
9268 current_config->name, \
9269 pipe_config->name); \
9270 return false; \
9271 }
9272
9273 #define PIPE_CONF_QUIRK(quirk) \
9274 ((current_config->quirks | pipe_config->quirks) & (quirk))
9275
9276 PIPE_CONF_CHECK_I(cpu_transcoder);
9277
9278 PIPE_CONF_CHECK_I(has_pch_encoder);
9279 PIPE_CONF_CHECK_I(fdi_lanes);
9280 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9281 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9282 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9283 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9284 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9285
9286 PIPE_CONF_CHECK_I(has_dp_encoder);
9287 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9288 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9289 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9290 PIPE_CONF_CHECK_I(dp_m_n.link_n);
9291 PIPE_CONF_CHECK_I(dp_m_n.tu);
9292
9293 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
9294 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
9295 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
9296 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
9297 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
9298 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
9299
9300 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
9301 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
9302 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
9303 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
9304 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
9305 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
9306
9307 PIPE_CONF_CHECK_I(pixel_multiplier);
9308
9309 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9310 DRM_MODE_FLAG_INTERLACE);
9311
9312 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
9313 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9314 DRM_MODE_FLAG_PHSYNC);
9315 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9316 DRM_MODE_FLAG_NHSYNC);
9317 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9318 DRM_MODE_FLAG_PVSYNC);
9319 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
9320 DRM_MODE_FLAG_NVSYNC);
9321 }
9322
9323 PIPE_CONF_CHECK_I(pipe_src_w);
9324 PIPE_CONF_CHECK_I(pipe_src_h);
9325
9326 PIPE_CONF_CHECK_I(gmch_pfit.control);
9327 /* pfit ratios are autocomputed by the hw on gen4+ */
9328 if (INTEL_INFO(dev)->gen < 4)
9329 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
9330 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
9331 PIPE_CONF_CHECK_I(pch_pfit.enabled);
9332 if (current_config->pch_pfit.enabled) {
9333 PIPE_CONF_CHECK_I(pch_pfit.pos);
9334 PIPE_CONF_CHECK_I(pch_pfit.size);
9335 }
9336
9337 PIPE_CONF_CHECK_I(ips_enabled);
9338
9339 PIPE_CONF_CHECK_I(double_wide);
9340
9341 PIPE_CONF_CHECK_I(shared_dpll);
9342 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
9343 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
9344 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
9345 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
9346
9347 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
9348 PIPE_CONF_CHECK_I(pipe_bpp);
9349
9350 if (!IS_HASWELL(dev)) {
9351 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
9352 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
9353 }
9354
9355 #undef PIPE_CONF_CHECK_X
9356 #undef PIPE_CONF_CHECK_I
9357 #undef PIPE_CONF_CHECK_FLAGS
9358 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
9359 #undef PIPE_CONF_QUIRK
9360
9361 return true;
9362 }
9363
9364 static void
9365 check_connector_state(struct drm_device *dev)
9366 {
9367 struct intel_connector *connector;
9368
9369 list_for_each_entry(connector, &dev->mode_config.connector_list,
9370 base.head) {
9371 /* This also checks the encoder/connector hw state with the
9372 * ->get_hw_state callbacks. */
9373 intel_connector_check_state(connector);
9374
9375 WARN(&connector->new_encoder->base != connector->base.encoder,
9376 "connector's staged encoder doesn't match current encoder\n");
9377 }
9378 }
9379
9380 static void
9381 check_encoder_state(struct drm_device *dev)
9382 {
9383 struct intel_encoder *encoder;
9384 struct intel_connector *connector;
9385
9386 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9387 base.head) {
9388 bool enabled = false;
9389 bool active = false;
9390 enum pipe pipe, tracked_pipe;
9391
9392 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9393 encoder->base.base.id,
9394 drm_get_encoder_name(&encoder->base));
9395
9396 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9397 "encoder's stage crtc doesn't match current crtc\n");
9398 WARN(encoder->connectors_active && !encoder->base.crtc,
9399 "encoder's active_connectors set, but no crtc\n");
9400
9401 list_for_each_entry(connector, &dev->mode_config.connector_list,
9402 base.head) {
9403 if (connector->base.encoder != &encoder->base)
9404 continue;
9405 enabled = true;
9406 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9407 active = true;
9408 }
9409 WARN(!!encoder->base.crtc != enabled,
9410 "encoder's enabled state mismatch "
9411 "(expected %i, found %i)\n",
9412 !!encoder->base.crtc, enabled);
9413 WARN(active && !encoder->base.crtc,
9414 "active encoder with no crtc\n");
9415
9416 WARN(encoder->connectors_active != active,
9417 "encoder's computed active state doesn't match tracked active state "
9418 "(expected %i, found %i)\n", active, encoder->connectors_active);
9419
9420 active = encoder->get_hw_state(encoder, &pipe);
9421 WARN(active != encoder->connectors_active,
9422 "encoder's hw state doesn't match sw tracking "
9423 "(expected %i, found %i)\n",
9424 encoder->connectors_active, active);
9425
9426 if (!encoder->base.crtc)
9427 continue;
9428
9429 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9430 WARN(active && pipe != tracked_pipe,
9431 "active encoder's pipe doesn't match"
9432 "(expected %i, found %i)\n",
9433 tracked_pipe, pipe);
9434
9435 }
9436 }
9437
9438 static void
9439 check_crtc_state(struct drm_device *dev)
9440 {
9441 drm_i915_private_t *dev_priv = dev->dev_private;
9442 struct intel_crtc *crtc;
9443 struct intel_encoder *encoder;
9444 struct intel_crtc_config pipe_config;
9445
9446 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9447 base.head) {
9448 bool enabled = false;
9449 bool active = false;
9450
9451 memset(&pipe_config, 0, sizeof(pipe_config));
9452
9453 DRM_DEBUG_KMS("[CRTC:%d]\n",
9454 crtc->base.base.id);
9455
9456 WARN(crtc->active && !crtc->base.enabled,
9457 "active crtc, but not enabled in sw tracking\n");
9458
9459 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9460 base.head) {
9461 if (encoder->base.crtc != &crtc->base)
9462 continue;
9463 enabled = true;
9464 if (encoder->connectors_active)
9465 active = true;
9466 }
9467
9468 WARN(active != crtc->active,
9469 "crtc's computed active state doesn't match tracked active state "
9470 "(expected %i, found %i)\n", active, crtc->active);
9471 WARN(enabled != crtc->base.enabled,
9472 "crtc's computed enabled state doesn't match tracked enabled state "
9473 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9474
9475 active = dev_priv->display.get_pipe_config(crtc,
9476 &pipe_config);
9477
9478 /* hw state is inconsistent with the pipe A quirk */
9479 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9480 active = crtc->active;
9481
9482 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9483 base.head) {
9484 enum pipe pipe;
9485 if (encoder->base.crtc != &crtc->base)
9486 continue;
9487 if (encoder->get_hw_state(encoder, &pipe))
9488 encoder->get_config(encoder, &pipe_config);
9489 }
9490
9491 WARN(crtc->active != active,
9492 "crtc active state doesn't match with hw state "
9493 "(expected %i, found %i)\n", crtc->active, active);
9494
9495 if (active &&
9496 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9497 WARN(1, "pipe state doesn't match!\n");
9498 intel_dump_pipe_config(crtc, &pipe_config,
9499 "[hw state]");
9500 intel_dump_pipe_config(crtc, &crtc->config,
9501 "[sw state]");
9502 }
9503 }
9504 }
9505
9506 static void
9507 check_shared_dpll_state(struct drm_device *dev)
9508 {
9509 drm_i915_private_t *dev_priv = dev->dev_private;
9510 struct intel_crtc *crtc;
9511 struct intel_dpll_hw_state dpll_hw_state;
9512 int i;
9513
9514 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9515 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9516 int enabled_crtcs = 0, active_crtcs = 0;
9517 bool active;
9518
9519 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9520
9521 DRM_DEBUG_KMS("%s\n", pll->name);
9522
9523 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9524
9525 WARN(pll->active > pll->refcount,
9526 "more active pll users than references: %i vs %i\n",
9527 pll->active, pll->refcount);
9528 WARN(pll->active && !pll->on,
9529 "pll in active use but not on in sw tracking\n");
9530 WARN(pll->on && !pll->active,
9531 "pll in on but not on in use in sw tracking\n");
9532 WARN(pll->on != active,
9533 "pll on state mismatch (expected %i, found %i)\n",
9534 pll->on, active);
9535
9536 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9537 base.head) {
9538 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9539 enabled_crtcs++;
9540 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9541 active_crtcs++;
9542 }
9543 WARN(pll->active != active_crtcs,
9544 "pll active crtcs mismatch (expected %i, found %i)\n",
9545 pll->active, active_crtcs);
9546 WARN(pll->refcount != enabled_crtcs,
9547 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9548 pll->refcount, enabled_crtcs);
9549
9550 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9551 sizeof(dpll_hw_state)),
9552 "pll hw state mismatch\n");
9553 }
9554 }
9555
9556 void
9557 intel_modeset_check_state(struct drm_device *dev)
9558 {
9559 check_connector_state(dev);
9560 check_encoder_state(dev);
9561 check_crtc_state(dev);
9562 check_shared_dpll_state(dev);
9563 }
9564
9565 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9566 int dotclock)
9567 {
9568 /*
9569 * FDI already provided one idea for the dotclock.
9570 * Yell if the encoder disagrees.
9571 */
9572 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
9573 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9574 pipe_config->adjusted_mode.crtc_clock, dotclock);
9575 }
9576
9577 static int __intel_set_mode(struct drm_crtc *crtc,
9578 struct drm_display_mode *mode,
9579 int x, int y, struct drm_framebuffer *fb)
9580 {
9581 struct drm_device *dev = crtc->dev;
9582 drm_i915_private_t *dev_priv = dev->dev_private;
9583 struct drm_display_mode *saved_mode, *saved_hwmode;
9584 struct intel_crtc_config *pipe_config = NULL;
9585 struct intel_crtc *intel_crtc;
9586 unsigned disable_pipes, prepare_pipes, modeset_pipes;
9587 int ret = 0;
9588
9589 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
9590 if (!saved_mode)
9591 return -ENOMEM;
9592 saved_hwmode = saved_mode + 1;
9593
9594 intel_modeset_affected_pipes(crtc, &modeset_pipes,
9595 &prepare_pipes, &disable_pipes);
9596
9597 *saved_hwmode = crtc->hwmode;
9598 *saved_mode = crtc->mode;
9599
9600 /* Hack: Because we don't (yet) support global modeset on multiple
9601 * crtcs, we don't keep track of the new mode for more than one crtc.
9602 * Hence simply check whether any bit is set in modeset_pipes in all the
9603 * pieces of code that are not yet converted to deal with mutliple crtcs
9604 * changing their mode at the same time. */
9605 if (modeset_pipes) {
9606 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
9607 if (IS_ERR(pipe_config)) {
9608 ret = PTR_ERR(pipe_config);
9609 pipe_config = NULL;
9610
9611 goto out;
9612 }
9613 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9614 "[modeset]");
9615 }
9616
9617 /*
9618 * See if the config requires any additional preparation, e.g.
9619 * to adjust global state with pipes off. We need to do this
9620 * here so we can get the modeset_pipe updated config for the new
9621 * mode set on this crtc. For other crtcs we need to use the
9622 * adjusted_mode bits in the crtc directly.
9623 */
9624 if (IS_VALLEYVIEW(dev)) {
9625 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9626 modeset_pipes, pipe_config);
9627
9628 /* may have added more to prepare_pipes than we should */
9629 prepare_pipes &= ~disable_pipes;
9630 }
9631
9632 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9633 intel_crtc_disable(&intel_crtc->base);
9634
9635 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9636 if (intel_crtc->base.enabled)
9637 dev_priv->display.crtc_disable(&intel_crtc->base);
9638 }
9639
9640 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9641 * to set it here already despite that we pass it down the callchain.
9642 */
9643 if (modeset_pipes) {
9644 crtc->mode = *mode;
9645 /* mode_set/enable/disable functions rely on a correct pipe
9646 * config. */
9647 to_intel_crtc(crtc)->config = *pipe_config;
9648 }
9649
9650 /* Only after disabling all output pipelines that will be changed can we
9651 * update the the output configuration. */
9652 intel_modeset_update_state(dev, prepare_pipes);
9653
9654 if (dev_priv->display.modeset_global_resources)
9655 dev_priv->display.modeset_global_resources(dev);
9656
9657 /* Set up the DPLL and any encoders state that needs to adjust or depend
9658 * on the DPLL.
9659 */
9660 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
9661 ret = intel_crtc_mode_set(&intel_crtc->base,
9662 x, y, fb);
9663 if (ret)
9664 goto done;
9665 }
9666
9667 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
9668 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9669 dev_priv->display.crtc_enable(&intel_crtc->base);
9670
9671 if (modeset_pipes) {
9672 /* Store real post-adjustment hardware mode. */
9673 crtc->hwmode = pipe_config->adjusted_mode;
9674
9675 /* Calculate and store various constants which
9676 * are later needed by vblank and swap-completion
9677 * timestamping. They are derived from true hwmode.
9678 */
9679 drm_calc_timestamping_constants(crtc);
9680 }
9681
9682 /* FIXME: add subpixel order */
9683 done:
9684 if (ret && crtc->enabled) {
9685 crtc->hwmode = *saved_hwmode;
9686 crtc->mode = *saved_mode;
9687 }
9688
9689 out:
9690 kfree(pipe_config);
9691 kfree(saved_mode);
9692 return ret;
9693 }
9694
9695 static int intel_set_mode(struct drm_crtc *crtc,
9696 struct drm_display_mode *mode,
9697 int x, int y, struct drm_framebuffer *fb)
9698 {
9699 int ret;
9700
9701 ret = __intel_set_mode(crtc, mode, x, y, fb);
9702
9703 if (ret == 0)
9704 intel_modeset_check_state(crtc->dev);
9705
9706 return ret;
9707 }
9708
9709 void intel_crtc_restore_mode(struct drm_crtc *crtc)
9710 {
9711 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9712 }
9713
9714 #undef for_each_intel_crtc_masked
9715
9716 static void intel_set_config_free(struct intel_set_config *config)
9717 {
9718 if (!config)
9719 return;
9720
9721 kfree(config->save_connector_encoders);
9722 kfree(config->save_encoder_crtcs);
9723 kfree(config);
9724 }
9725
9726 static int intel_set_config_save_state(struct drm_device *dev,
9727 struct intel_set_config *config)
9728 {
9729 struct drm_encoder *encoder;
9730 struct drm_connector *connector;
9731 int count;
9732
9733 config->save_encoder_crtcs =
9734 kcalloc(dev->mode_config.num_encoder,
9735 sizeof(struct drm_crtc *), GFP_KERNEL);
9736 if (!config->save_encoder_crtcs)
9737 return -ENOMEM;
9738
9739 config->save_connector_encoders =
9740 kcalloc(dev->mode_config.num_connector,
9741 sizeof(struct drm_encoder *), GFP_KERNEL);
9742 if (!config->save_connector_encoders)
9743 return -ENOMEM;
9744
9745 /* Copy data. Note that driver private data is not affected.
9746 * Should anything bad happen only the expected state is
9747 * restored, not the drivers personal bookkeeping.
9748 */
9749 count = 0;
9750 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
9751 config->save_encoder_crtcs[count++] = encoder->crtc;
9752 }
9753
9754 count = 0;
9755 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9756 config->save_connector_encoders[count++] = connector->encoder;
9757 }
9758
9759 return 0;
9760 }
9761
9762 static void intel_set_config_restore_state(struct drm_device *dev,
9763 struct intel_set_config *config)
9764 {
9765 struct intel_encoder *encoder;
9766 struct intel_connector *connector;
9767 int count;
9768
9769 count = 0;
9770 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9771 encoder->new_crtc =
9772 to_intel_crtc(config->save_encoder_crtcs[count++]);
9773 }
9774
9775 count = 0;
9776 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9777 connector->new_encoder =
9778 to_intel_encoder(config->save_connector_encoders[count++]);
9779 }
9780 }
9781
9782 static bool
9783 is_crtc_connector_off(struct drm_mode_set *set)
9784 {
9785 int i;
9786
9787 if (set->num_connectors == 0)
9788 return false;
9789
9790 if (WARN_ON(set->connectors == NULL))
9791 return false;
9792
9793 for (i = 0; i < set->num_connectors; i++)
9794 if (set->connectors[i]->encoder &&
9795 set->connectors[i]->encoder->crtc == set->crtc &&
9796 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
9797 return true;
9798
9799 return false;
9800 }
9801
9802 static void
9803 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9804 struct intel_set_config *config)
9805 {
9806
9807 /* We should be able to check here if the fb has the same properties
9808 * and then just flip_or_move it */
9809 if (is_crtc_connector_off(set)) {
9810 config->mode_changed = true;
9811 } else if (set->crtc->fb != set->fb) {
9812 /* If we have no fb then treat it as a full mode set */
9813 if (set->crtc->fb == NULL) {
9814 struct intel_crtc *intel_crtc =
9815 to_intel_crtc(set->crtc);
9816
9817 if (intel_crtc->active && i915_fastboot) {
9818 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9819 config->fb_changed = true;
9820 } else {
9821 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9822 config->mode_changed = true;
9823 }
9824 } else if (set->fb == NULL) {
9825 config->mode_changed = true;
9826 } else if (set->fb->pixel_format !=
9827 set->crtc->fb->pixel_format) {
9828 config->mode_changed = true;
9829 } else {
9830 config->fb_changed = true;
9831 }
9832 }
9833
9834 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
9835 config->fb_changed = true;
9836
9837 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9838 DRM_DEBUG_KMS("modes are different, full mode set\n");
9839 drm_mode_debug_printmodeline(&set->crtc->mode);
9840 drm_mode_debug_printmodeline(set->mode);
9841 config->mode_changed = true;
9842 }
9843
9844 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9845 set->crtc->base.id, config->mode_changed, config->fb_changed);
9846 }
9847
9848 static int
9849 intel_modeset_stage_output_state(struct drm_device *dev,
9850 struct drm_mode_set *set,
9851 struct intel_set_config *config)
9852 {
9853 struct drm_crtc *new_crtc;
9854 struct intel_connector *connector;
9855 struct intel_encoder *encoder;
9856 int ro;
9857
9858 /* The upper layers ensure that we either disable a crtc or have a list
9859 * of connectors. For paranoia, double-check this. */
9860 WARN_ON(!set->fb && (set->num_connectors != 0));
9861 WARN_ON(set->fb && (set->num_connectors == 0));
9862
9863 list_for_each_entry(connector, &dev->mode_config.connector_list,
9864 base.head) {
9865 /* Otherwise traverse passed in connector list and get encoders
9866 * for them. */
9867 for (ro = 0; ro < set->num_connectors; ro++) {
9868 if (set->connectors[ro] == &connector->base) {
9869 connector->new_encoder = connector->encoder;
9870 break;
9871 }
9872 }
9873
9874 /* If we disable the crtc, disable all its connectors. Also, if
9875 * the connector is on the changing crtc but not on the new
9876 * connector list, disable it. */
9877 if ((!set->fb || ro == set->num_connectors) &&
9878 connector->base.encoder &&
9879 connector->base.encoder->crtc == set->crtc) {
9880 connector->new_encoder = NULL;
9881
9882 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9883 connector->base.base.id,
9884 drm_get_connector_name(&connector->base));
9885 }
9886
9887
9888 if (&connector->new_encoder->base != connector->base.encoder) {
9889 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
9890 config->mode_changed = true;
9891 }
9892 }
9893 /* connector->new_encoder is now updated for all connectors. */
9894
9895 /* Update crtc of enabled connectors. */
9896 list_for_each_entry(connector, &dev->mode_config.connector_list,
9897 base.head) {
9898 if (!connector->new_encoder)
9899 continue;
9900
9901 new_crtc = connector->new_encoder->base.crtc;
9902
9903 for (ro = 0; ro < set->num_connectors; ro++) {
9904 if (set->connectors[ro] == &connector->base)
9905 new_crtc = set->crtc;
9906 }
9907
9908 /* Make sure the new CRTC will work with the encoder */
9909 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9910 new_crtc)) {
9911 return -EINVAL;
9912 }
9913 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9914
9915 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9916 connector->base.base.id,
9917 drm_get_connector_name(&connector->base),
9918 new_crtc->base.id);
9919 }
9920
9921 /* Check for any encoders that needs to be disabled. */
9922 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9923 base.head) {
9924 list_for_each_entry(connector,
9925 &dev->mode_config.connector_list,
9926 base.head) {
9927 if (connector->new_encoder == encoder) {
9928 WARN_ON(!connector->new_encoder->new_crtc);
9929
9930 goto next_encoder;
9931 }
9932 }
9933 encoder->new_crtc = NULL;
9934 next_encoder:
9935 /* Only now check for crtc changes so we don't miss encoders
9936 * that will be disabled. */
9937 if (&encoder->new_crtc->base != encoder->base.crtc) {
9938 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
9939 config->mode_changed = true;
9940 }
9941 }
9942 /* Now we've also updated encoder->new_crtc for all encoders. */
9943
9944 return 0;
9945 }
9946
9947 static int intel_crtc_set_config(struct drm_mode_set *set)
9948 {
9949 struct drm_device *dev;
9950 struct drm_mode_set save_set;
9951 struct intel_set_config *config;
9952 int ret;
9953
9954 BUG_ON(!set);
9955 BUG_ON(!set->crtc);
9956 BUG_ON(!set->crtc->helper_private);
9957
9958 /* Enforce sane interface api - has been abused by the fb helper. */
9959 BUG_ON(!set->mode && set->fb);
9960 BUG_ON(set->fb && set->num_connectors == 0);
9961
9962 if (set->fb) {
9963 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9964 set->crtc->base.id, set->fb->base.id,
9965 (int)set->num_connectors, set->x, set->y);
9966 } else {
9967 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
9968 }
9969
9970 dev = set->crtc->dev;
9971
9972 ret = -ENOMEM;
9973 config = kzalloc(sizeof(*config), GFP_KERNEL);
9974 if (!config)
9975 goto out_config;
9976
9977 ret = intel_set_config_save_state(dev, config);
9978 if (ret)
9979 goto out_config;
9980
9981 save_set.crtc = set->crtc;
9982 save_set.mode = &set->crtc->mode;
9983 save_set.x = set->crtc->x;
9984 save_set.y = set->crtc->y;
9985 save_set.fb = set->crtc->fb;
9986
9987 /* Compute whether we need a full modeset, only an fb base update or no
9988 * change at all. In the future we might also check whether only the
9989 * mode changed, e.g. for LVDS where we only change the panel fitter in
9990 * such cases. */
9991 intel_set_config_compute_mode_changes(set, config);
9992
9993 ret = intel_modeset_stage_output_state(dev, set, config);
9994 if (ret)
9995 goto fail;
9996
9997 if (config->mode_changed) {
9998 ret = intel_set_mode(set->crtc, set->mode,
9999 set->x, set->y, set->fb);
10000 } else if (config->fb_changed) {
10001 intel_crtc_wait_for_pending_flips(set->crtc);
10002
10003 ret = intel_pipe_set_base(set->crtc,
10004 set->x, set->y, set->fb);
10005 }
10006
10007 if (ret) {
10008 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10009 set->crtc->base.id, ret);
10010 fail:
10011 intel_set_config_restore_state(dev, config);
10012
10013 /* Try to restore the config */
10014 if (config->mode_changed &&
10015 intel_set_mode(save_set.crtc, save_set.mode,
10016 save_set.x, save_set.y, save_set.fb))
10017 DRM_ERROR("failed to restore config after modeset failure\n");
10018 }
10019
10020 out_config:
10021 intel_set_config_free(config);
10022 return ret;
10023 }
10024
10025 static const struct drm_crtc_funcs intel_crtc_funcs = {
10026 .cursor_set = intel_crtc_cursor_set,
10027 .cursor_move = intel_crtc_cursor_move,
10028 .gamma_set = intel_crtc_gamma_set,
10029 .set_config = intel_crtc_set_config,
10030 .destroy = intel_crtc_destroy,
10031 .page_flip = intel_crtc_page_flip,
10032 };
10033
10034 static void intel_cpu_pll_init(struct drm_device *dev)
10035 {
10036 if (HAS_DDI(dev))
10037 intel_ddi_pll_init(dev);
10038 }
10039
10040 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10041 struct intel_shared_dpll *pll,
10042 struct intel_dpll_hw_state *hw_state)
10043 {
10044 uint32_t val;
10045
10046 val = I915_READ(PCH_DPLL(pll->id));
10047 hw_state->dpll = val;
10048 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10049 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10050
10051 return val & DPLL_VCO_ENABLE;
10052 }
10053
10054 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10055 struct intel_shared_dpll *pll)
10056 {
10057 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10058 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10059 }
10060
10061 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10062 struct intel_shared_dpll *pll)
10063 {
10064 /* PCH refclock must be enabled first */
10065 assert_pch_refclk_enabled(dev_priv);
10066
10067 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10068
10069 /* Wait for the clocks to stabilize. */
10070 POSTING_READ(PCH_DPLL(pll->id));
10071 udelay(150);
10072
10073 /* The pixel multiplier can only be updated once the
10074 * DPLL is enabled and the clocks are stable.
10075 *
10076 * So write it again.
10077 */
10078 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10079 POSTING_READ(PCH_DPLL(pll->id));
10080 udelay(200);
10081 }
10082
10083 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10084 struct intel_shared_dpll *pll)
10085 {
10086 struct drm_device *dev = dev_priv->dev;
10087 struct intel_crtc *crtc;
10088
10089 /* Make sure no transcoder isn't still depending on us. */
10090 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
10091 if (intel_crtc_to_shared_dpll(crtc) == pll)
10092 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10093 }
10094
10095 I915_WRITE(PCH_DPLL(pll->id), 0);
10096 POSTING_READ(PCH_DPLL(pll->id));
10097 udelay(200);
10098 }
10099
10100 static char *ibx_pch_dpll_names[] = {
10101 "PCH DPLL A",
10102 "PCH DPLL B",
10103 };
10104
10105 static void ibx_pch_dpll_init(struct drm_device *dev)
10106 {
10107 struct drm_i915_private *dev_priv = dev->dev_private;
10108 int i;
10109
10110 dev_priv->num_shared_dpll = 2;
10111
10112 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10113 dev_priv->shared_dplls[i].id = i;
10114 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
10115 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
10116 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
10117 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
10118 dev_priv->shared_dplls[i].get_hw_state =
10119 ibx_pch_dpll_get_hw_state;
10120 }
10121 }
10122
10123 static void intel_shared_dpll_init(struct drm_device *dev)
10124 {
10125 struct drm_i915_private *dev_priv = dev->dev_private;
10126
10127 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
10128 ibx_pch_dpll_init(dev);
10129 else
10130 dev_priv->num_shared_dpll = 0;
10131
10132 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
10133 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
10134 dev_priv->num_shared_dpll);
10135 }
10136
10137 static void intel_crtc_init(struct drm_device *dev, int pipe)
10138 {
10139 drm_i915_private_t *dev_priv = dev->dev_private;
10140 struct intel_crtc *intel_crtc;
10141 int i;
10142
10143 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
10144 if (intel_crtc == NULL)
10145 return;
10146
10147 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
10148
10149 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
10150 for (i = 0; i < 256; i++) {
10151 intel_crtc->lut_r[i] = i;
10152 intel_crtc->lut_g[i] = i;
10153 intel_crtc->lut_b[i] = i;
10154 }
10155
10156 /*
10157 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
10158 * is hooked to plane B. Hence we want plane A feeding pipe B.
10159 */
10160 intel_crtc->pipe = pipe;
10161 intel_crtc->plane = pipe;
10162 if (IS_MOBILE(dev) && INTEL_INFO(dev)->gen < 4) {
10163 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
10164 intel_crtc->plane = !pipe;
10165 }
10166
10167 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
10168 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
10169 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
10170 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
10171
10172 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
10173 }
10174
10175 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
10176 {
10177 struct drm_encoder *encoder = connector->base.encoder;
10178
10179 WARN_ON(!mutex_is_locked(&connector->base.dev->mode_config.mutex));
10180
10181 if (!encoder)
10182 return INVALID_PIPE;
10183
10184 return to_intel_crtc(encoder->crtc)->pipe;
10185 }
10186
10187 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
10188 struct drm_file *file)
10189 {
10190 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
10191 struct drm_mode_object *drmmode_obj;
10192 struct intel_crtc *crtc;
10193
10194 if (!drm_core_check_feature(dev, DRIVER_MODESET))
10195 return -ENODEV;
10196
10197 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
10198 DRM_MODE_OBJECT_CRTC);
10199
10200 if (!drmmode_obj) {
10201 DRM_ERROR("no such CRTC id\n");
10202 return -ENOENT;
10203 }
10204
10205 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
10206 pipe_from_crtc_id->pipe = crtc->pipe;
10207
10208 return 0;
10209 }
10210
10211 static int intel_encoder_clones(struct intel_encoder *encoder)
10212 {
10213 struct drm_device *dev = encoder->base.dev;
10214 struct intel_encoder *source_encoder;
10215 int index_mask = 0;
10216 int entry = 0;
10217
10218 list_for_each_entry(source_encoder,
10219 &dev->mode_config.encoder_list, base.head) {
10220
10221 if (encoder == source_encoder)
10222 index_mask |= (1 << entry);
10223
10224 /* Intel hw has only one MUX where enocoders could be cloned. */
10225 if (encoder->cloneable && source_encoder->cloneable)
10226 index_mask |= (1 << entry);
10227
10228 entry++;
10229 }
10230
10231 return index_mask;
10232 }
10233
10234 static bool has_edp_a(struct drm_device *dev)
10235 {
10236 struct drm_i915_private *dev_priv = dev->dev_private;
10237
10238 if (!IS_MOBILE(dev))
10239 return false;
10240
10241 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
10242 return false;
10243
10244 if (IS_GEN5(dev) &&
10245 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
10246 return false;
10247
10248 return true;
10249 }
10250
10251 static void intel_setup_outputs(struct drm_device *dev)
10252 {
10253 struct drm_i915_private *dev_priv = dev->dev_private;
10254 struct intel_encoder *encoder;
10255 bool dpd_is_edp = false;
10256
10257 intel_lvds_init(dev);
10258
10259 if (!IS_ULT(dev))
10260 intel_crt_init(dev);
10261
10262 if (HAS_DDI(dev)) {
10263 int found;
10264
10265 /* Haswell uses DDI functions to detect digital outputs */
10266 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
10267 /* DDI A only supports eDP */
10268 if (found)
10269 intel_ddi_init(dev, PORT_A);
10270
10271 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
10272 * register */
10273 found = I915_READ(SFUSE_STRAP);
10274
10275 if (found & SFUSE_STRAP_DDIB_DETECTED)
10276 intel_ddi_init(dev, PORT_B);
10277 if (found & SFUSE_STRAP_DDIC_DETECTED)
10278 intel_ddi_init(dev, PORT_C);
10279 if (found & SFUSE_STRAP_DDID_DETECTED)
10280 intel_ddi_init(dev, PORT_D);
10281 } else if (HAS_PCH_SPLIT(dev)) {
10282 int found;
10283 dpd_is_edp = intel_dpd_is_edp(dev);
10284
10285 if (has_edp_a(dev))
10286 intel_dp_init(dev, DP_A, PORT_A);
10287
10288 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
10289 /* PCH SDVOB multiplex with HDMIB */
10290 found = intel_sdvo_init(dev, PCH_SDVOB, true);
10291 if (!found)
10292 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
10293 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
10294 intel_dp_init(dev, PCH_DP_B, PORT_B);
10295 }
10296
10297 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
10298 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
10299
10300 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
10301 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
10302
10303 if (I915_READ(PCH_DP_C) & DP_DETECTED)
10304 intel_dp_init(dev, PCH_DP_C, PORT_C);
10305
10306 if (I915_READ(PCH_DP_D) & DP_DETECTED)
10307 intel_dp_init(dev, PCH_DP_D, PORT_D);
10308 } else if (IS_VALLEYVIEW(dev)) {
10309 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
10310 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
10311 PORT_B);
10312 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
10313 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
10314 }
10315
10316 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
10317 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
10318 PORT_C);
10319 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
10320 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
10321 PORT_C);
10322 }
10323
10324 intel_dsi_init(dev);
10325 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
10326 bool found = false;
10327
10328 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10329 DRM_DEBUG_KMS("probing SDVOB\n");
10330 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
10331 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
10332 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
10333 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
10334 }
10335
10336 if (!found && SUPPORTS_INTEGRATED_DP(dev))
10337 intel_dp_init(dev, DP_B, PORT_B);
10338 }
10339
10340 /* Before G4X SDVOC doesn't have its own detect register */
10341
10342 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
10343 DRM_DEBUG_KMS("probing SDVOC\n");
10344 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
10345 }
10346
10347 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
10348
10349 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
10350 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
10351 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
10352 }
10353 if (SUPPORTS_INTEGRATED_DP(dev))
10354 intel_dp_init(dev, DP_C, PORT_C);
10355 }
10356
10357 if (SUPPORTS_INTEGRATED_DP(dev) &&
10358 (I915_READ(DP_D) & DP_DETECTED))
10359 intel_dp_init(dev, DP_D, PORT_D);
10360 } else if (IS_GEN2(dev))
10361 intel_dvo_init(dev);
10362
10363 if (SUPPORTS_TV(dev))
10364 intel_tv_init(dev);
10365
10366 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10367 encoder->base.possible_crtcs = encoder->crtc_mask;
10368 encoder->base.possible_clones =
10369 intel_encoder_clones(encoder);
10370 }
10371
10372 intel_init_pch_refclk(dev);
10373
10374 drm_helper_move_panel_connectors_to_head(dev);
10375 }
10376
10377 void intel_framebuffer_fini(struct intel_framebuffer *fb)
10378 {
10379 drm_framebuffer_cleanup(&fb->base);
10380 WARN_ON(!fb->obj->framebuffer_references--);
10381 drm_gem_object_unreference_unlocked(&fb->obj->base);
10382 }
10383
10384 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
10385 {
10386 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10387
10388 intel_framebuffer_fini(intel_fb);
10389 kfree(intel_fb);
10390 }
10391
10392 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
10393 struct drm_file *file,
10394 unsigned int *handle)
10395 {
10396 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
10397 struct drm_i915_gem_object *obj = intel_fb->obj;
10398
10399 return drm_gem_handle_create(file, &obj->base, handle);
10400 }
10401
10402 static const struct drm_framebuffer_funcs intel_fb_funcs = {
10403 .destroy = intel_user_framebuffer_destroy,
10404 .create_handle = intel_user_framebuffer_create_handle,
10405 };
10406
10407 int intel_framebuffer_init(struct drm_device *dev,
10408 struct intel_framebuffer *intel_fb,
10409 struct drm_mode_fb_cmd2 *mode_cmd,
10410 struct drm_i915_gem_object *obj)
10411 {
10412 int aligned_height, tile_height;
10413 int pitch_limit;
10414 int ret;
10415
10416 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10417
10418 if (obj->tiling_mode == I915_TILING_Y) {
10419 DRM_DEBUG("hardware does not support tiling Y\n");
10420 return -EINVAL;
10421 }
10422
10423 if (mode_cmd->pitches[0] & 63) {
10424 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10425 mode_cmd->pitches[0]);
10426 return -EINVAL;
10427 }
10428
10429 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10430 pitch_limit = 32*1024;
10431 } else if (INTEL_INFO(dev)->gen >= 4) {
10432 if (obj->tiling_mode)
10433 pitch_limit = 16*1024;
10434 else
10435 pitch_limit = 32*1024;
10436 } else if (INTEL_INFO(dev)->gen >= 3) {
10437 if (obj->tiling_mode)
10438 pitch_limit = 8*1024;
10439 else
10440 pitch_limit = 16*1024;
10441 } else
10442 /* XXX DSPC is limited to 4k tiled */
10443 pitch_limit = 8*1024;
10444
10445 if (mode_cmd->pitches[0] > pitch_limit) {
10446 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10447 obj->tiling_mode ? "tiled" : "linear",
10448 mode_cmd->pitches[0], pitch_limit);
10449 return -EINVAL;
10450 }
10451
10452 if (obj->tiling_mode != I915_TILING_NONE &&
10453 mode_cmd->pitches[0] != obj->stride) {
10454 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10455 mode_cmd->pitches[0], obj->stride);
10456 return -EINVAL;
10457 }
10458
10459 /* Reject formats not supported by any plane early. */
10460 switch (mode_cmd->pixel_format) {
10461 case DRM_FORMAT_C8:
10462 case DRM_FORMAT_RGB565:
10463 case DRM_FORMAT_XRGB8888:
10464 case DRM_FORMAT_ARGB8888:
10465 break;
10466 case DRM_FORMAT_XRGB1555:
10467 case DRM_FORMAT_ARGB1555:
10468 if (INTEL_INFO(dev)->gen > 3) {
10469 DRM_DEBUG("unsupported pixel format: %s\n",
10470 drm_get_format_name(mode_cmd->pixel_format));
10471 return -EINVAL;
10472 }
10473 break;
10474 case DRM_FORMAT_XBGR8888:
10475 case DRM_FORMAT_ABGR8888:
10476 case DRM_FORMAT_XRGB2101010:
10477 case DRM_FORMAT_ARGB2101010:
10478 case DRM_FORMAT_XBGR2101010:
10479 case DRM_FORMAT_ABGR2101010:
10480 if (INTEL_INFO(dev)->gen < 4) {
10481 DRM_DEBUG("unsupported pixel format: %s\n",
10482 drm_get_format_name(mode_cmd->pixel_format));
10483 return -EINVAL;
10484 }
10485 break;
10486 case DRM_FORMAT_YUYV:
10487 case DRM_FORMAT_UYVY:
10488 case DRM_FORMAT_YVYU:
10489 case DRM_FORMAT_VYUY:
10490 if (INTEL_INFO(dev)->gen < 5) {
10491 DRM_DEBUG("unsupported pixel format: %s\n",
10492 drm_get_format_name(mode_cmd->pixel_format));
10493 return -EINVAL;
10494 }
10495 break;
10496 default:
10497 DRM_DEBUG("unsupported pixel format: %s\n",
10498 drm_get_format_name(mode_cmd->pixel_format));
10499 return -EINVAL;
10500 }
10501
10502 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10503 if (mode_cmd->offsets[0] != 0)
10504 return -EINVAL;
10505
10506 tile_height = IS_GEN2(dev) ? 16 : 8;
10507 aligned_height = ALIGN(mode_cmd->height,
10508 obj->tiling_mode ? tile_height : 1);
10509 /* FIXME drm helper for size checks (especially planar formats)? */
10510 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10511 return -EINVAL;
10512
10513 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10514 intel_fb->obj = obj;
10515 intel_fb->obj->framebuffer_references++;
10516
10517 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10518 if (ret) {
10519 DRM_ERROR("framebuffer init failed %d\n", ret);
10520 return ret;
10521 }
10522
10523 return 0;
10524 }
10525
10526 static struct drm_framebuffer *
10527 intel_user_framebuffer_create(struct drm_device *dev,
10528 struct drm_file *filp,
10529 struct drm_mode_fb_cmd2 *mode_cmd)
10530 {
10531 struct drm_i915_gem_object *obj;
10532
10533 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10534 mode_cmd->handles[0]));
10535 if (&obj->base == NULL)
10536 return ERR_PTR(-ENOENT);
10537
10538 return intel_framebuffer_create(dev, mode_cmd, obj);
10539 }
10540
10541 #ifndef CONFIG_DRM_I915_FBDEV
10542 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
10543 {
10544 }
10545 #endif
10546
10547 static const struct drm_mode_config_funcs intel_mode_funcs = {
10548 .fb_create = intel_user_framebuffer_create,
10549 .output_poll_changed = intel_fbdev_output_poll_changed,
10550 };
10551
10552 /* Set up chip specific display functions */
10553 static void intel_init_display(struct drm_device *dev)
10554 {
10555 struct drm_i915_private *dev_priv = dev->dev_private;
10556
10557 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10558 dev_priv->display.find_dpll = g4x_find_best_dpll;
10559 else if (IS_VALLEYVIEW(dev))
10560 dev_priv->display.find_dpll = vlv_find_best_dpll;
10561 else if (IS_PINEVIEW(dev))
10562 dev_priv->display.find_dpll = pnv_find_best_dpll;
10563 else
10564 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10565
10566 if (HAS_DDI(dev)) {
10567 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
10568 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
10569 dev_priv->display.crtc_enable = haswell_crtc_enable;
10570 dev_priv->display.crtc_disable = haswell_crtc_disable;
10571 dev_priv->display.off = haswell_crtc_off;
10572 dev_priv->display.update_plane = ironlake_update_plane;
10573 } else if (HAS_PCH_SPLIT(dev)) {
10574 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
10575 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
10576 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10577 dev_priv->display.crtc_disable = ironlake_crtc_disable;
10578 dev_priv->display.off = ironlake_crtc_off;
10579 dev_priv->display.update_plane = ironlake_update_plane;
10580 } else if (IS_VALLEYVIEW(dev)) {
10581 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10582 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10583 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10584 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10585 dev_priv->display.off = i9xx_crtc_off;
10586 dev_priv->display.update_plane = i9xx_update_plane;
10587 } else {
10588 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10589 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10590 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10591 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10592 dev_priv->display.off = i9xx_crtc_off;
10593 dev_priv->display.update_plane = i9xx_update_plane;
10594 }
10595
10596 /* Returns the core display clock speed */
10597 if (IS_VALLEYVIEW(dev))
10598 dev_priv->display.get_display_clock_speed =
10599 valleyview_get_display_clock_speed;
10600 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
10601 dev_priv->display.get_display_clock_speed =
10602 i945_get_display_clock_speed;
10603 else if (IS_I915G(dev))
10604 dev_priv->display.get_display_clock_speed =
10605 i915_get_display_clock_speed;
10606 else if (IS_I945GM(dev) || IS_845G(dev))
10607 dev_priv->display.get_display_clock_speed =
10608 i9xx_misc_get_display_clock_speed;
10609 else if (IS_PINEVIEW(dev))
10610 dev_priv->display.get_display_clock_speed =
10611 pnv_get_display_clock_speed;
10612 else if (IS_I915GM(dev))
10613 dev_priv->display.get_display_clock_speed =
10614 i915gm_get_display_clock_speed;
10615 else if (IS_I865G(dev))
10616 dev_priv->display.get_display_clock_speed =
10617 i865_get_display_clock_speed;
10618 else if (IS_I85X(dev))
10619 dev_priv->display.get_display_clock_speed =
10620 i855_get_display_clock_speed;
10621 else /* 852, 830 */
10622 dev_priv->display.get_display_clock_speed =
10623 i830_get_display_clock_speed;
10624
10625 if (HAS_PCH_SPLIT(dev)) {
10626 if (IS_GEN5(dev)) {
10627 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
10628 dev_priv->display.write_eld = ironlake_write_eld;
10629 } else if (IS_GEN6(dev)) {
10630 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
10631 dev_priv->display.write_eld = ironlake_write_eld;
10632 } else if (IS_IVYBRIDGE(dev)) {
10633 /* FIXME: detect B0+ stepping and use auto training */
10634 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
10635 dev_priv->display.write_eld = ironlake_write_eld;
10636 dev_priv->display.modeset_global_resources =
10637 ivb_modeset_global_resources;
10638 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
10639 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
10640 dev_priv->display.write_eld = haswell_write_eld;
10641 dev_priv->display.modeset_global_resources =
10642 haswell_modeset_global_resources;
10643 }
10644 } else if (IS_G4X(dev)) {
10645 dev_priv->display.write_eld = g4x_write_eld;
10646 } else if (IS_VALLEYVIEW(dev)) {
10647 dev_priv->display.modeset_global_resources =
10648 valleyview_modeset_global_resources;
10649 dev_priv->display.write_eld = ironlake_write_eld;
10650 }
10651
10652 /* Default just returns -ENODEV to indicate unsupported */
10653 dev_priv->display.queue_flip = intel_default_queue_flip;
10654
10655 switch (INTEL_INFO(dev)->gen) {
10656 case 2:
10657 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10658 break;
10659
10660 case 3:
10661 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10662 break;
10663
10664 case 4:
10665 case 5:
10666 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10667 break;
10668
10669 case 6:
10670 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10671 break;
10672 case 7:
10673 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
10674 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10675 break;
10676 }
10677
10678 intel_panel_init_backlight_funcs(dev);
10679 }
10680
10681 /*
10682 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10683 * resume, or other times. This quirk makes sure that's the case for
10684 * affected systems.
10685 */
10686 static void quirk_pipea_force(struct drm_device *dev)
10687 {
10688 struct drm_i915_private *dev_priv = dev->dev_private;
10689
10690 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
10691 DRM_INFO("applying pipe a force quirk\n");
10692 }
10693
10694 /*
10695 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10696 */
10697 static void quirk_ssc_force_disable(struct drm_device *dev)
10698 {
10699 struct drm_i915_private *dev_priv = dev->dev_private;
10700 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
10701 DRM_INFO("applying lvds SSC disable quirk\n");
10702 }
10703
10704 /*
10705 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10706 * brightness value
10707 */
10708 static void quirk_invert_brightness(struct drm_device *dev)
10709 {
10710 struct drm_i915_private *dev_priv = dev->dev_private;
10711 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
10712 DRM_INFO("applying inverted panel brightness quirk\n");
10713 }
10714
10715 struct intel_quirk {
10716 int device;
10717 int subsystem_vendor;
10718 int subsystem_device;
10719 void (*hook)(struct drm_device *dev);
10720 };
10721
10722 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10723 struct intel_dmi_quirk {
10724 void (*hook)(struct drm_device *dev);
10725 const struct dmi_system_id (*dmi_id_list)[];
10726 };
10727
10728 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10729 {
10730 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10731 return 1;
10732 }
10733
10734 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10735 {
10736 .dmi_id_list = &(const struct dmi_system_id[]) {
10737 {
10738 .callback = intel_dmi_reverse_brightness,
10739 .ident = "NCR Corporation",
10740 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10741 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10742 },
10743 },
10744 { } /* terminating entry */
10745 },
10746 .hook = quirk_invert_brightness,
10747 },
10748 };
10749
10750 static struct intel_quirk intel_quirks[] = {
10751 /* HP Mini needs pipe A force quirk (LP: #322104) */
10752 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
10753
10754 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10755 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10756
10757 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10758 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10759
10760 /* 830 needs to leave pipe A & dpll A up */
10761 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
10762
10763 /* Lenovo U160 cannot use SSC on LVDS */
10764 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
10765
10766 /* Sony Vaio Y cannot use SSC on LVDS */
10767 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
10768
10769 /*
10770 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10771 * seem to use inverted backlight PWM.
10772 */
10773 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10774 };
10775
10776 static void intel_init_quirks(struct drm_device *dev)
10777 {
10778 struct pci_dev *d = dev->pdev;
10779 int i;
10780
10781 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10782 struct intel_quirk *q = &intel_quirks[i];
10783
10784 if (d->device == q->device &&
10785 (d->subsystem_vendor == q->subsystem_vendor ||
10786 q->subsystem_vendor == PCI_ANY_ID) &&
10787 (d->subsystem_device == q->subsystem_device ||
10788 q->subsystem_device == PCI_ANY_ID))
10789 q->hook(dev);
10790 }
10791 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10792 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10793 intel_dmi_quirks[i].hook(dev);
10794 }
10795 }
10796
10797 /* Disable the VGA plane that we never use */
10798 static void i915_disable_vga(struct drm_device *dev)
10799 {
10800 struct drm_i915_private *dev_priv = dev->dev_private;
10801 u8 sr1;
10802 u32 vga_reg = i915_vgacntrl_reg(dev);
10803
10804 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10805 outb(SR01, VGA_SR_INDEX);
10806 sr1 = inb(VGA_SR_DATA);
10807 outb(sr1 | 1<<5, VGA_SR_DATA);
10808 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10809 udelay(300);
10810
10811 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10812 POSTING_READ(vga_reg);
10813 }
10814
10815 void intel_modeset_init_hw(struct drm_device *dev)
10816 {
10817 intel_prepare_ddi(dev);
10818
10819 intel_init_clock_gating(dev);
10820
10821 intel_reset_dpio(dev);
10822
10823 mutex_lock(&dev->struct_mutex);
10824 intel_enable_gt_powersave(dev);
10825 mutex_unlock(&dev->struct_mutex);
10826 }
10827
10828 void intel_modeset_suspend_hw(struct drm_device *dev)
10829 {
10830 intel_suspend_hw(dev);
10831 }
10832
10833 void intel_modeset_init(struct drm_device *dev)
10834 {
10835 struct drm_i915_private *dev_priv = dev->dev_private;
10836 int i, j, ret;
10837
10838 drm_mode_config_init(dev);
10839
10840 dev->mode_config.min_width = 0;
10841 dev->mode_config.min_height = 0;
10842
10843 dev->mode_config.preferred_depth = 24;
10844 dev->mode_config.prefer_shadow = 1;
10845
10846 dev->mode_config.funcs = &intel_mode_funcs;
10847
10848 intel_init_quirks(dev);
10849
10850 intel_init_pm(dev);
10851
10852 if (INTEL_INFO(dev)->num_pipes == 0)
10853 return;
10854
10855 intel_init_display(dev);
10856
10857 if (IS_GEN2(dev)) {
10858 dev->mode_config.max_width = 2048;
10859 dev->mode_config.max_height = 2048;
10860 } else if (IS_GEN3(dev)) {
10861 dev->mode_config.max_width = 4096;
10862 dev->mode_config.max_height = 4096;
10863 } else {
10864 dev->mode_config.max_width = 8192;
10865 dev->mode_config.max_height = 8192;
10866 }
10867 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
10868
10869 DRM_DEBUG_KMS("%d display pipe%s available.\n",
10870 INTEL_INFO(dev)->num_pipes,
10871 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
10872
10873 for_each_pipe(i) {
10874 intel_crtc_init(dev, i);
10875 for (j = 0; j < dev_priv->num_plane; j++) {
10876 ret = intel_plane_init(dev, i, j);
10877 if (ret)
10878 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10879 pipe_name(i), sprite_name(i, j), ret);
10880 }
10881 }
10882
10883 intel_init_dpio(dev);
10884 intel_reset_dpio(dev);
10885
10886 intel_cpu_pll_init(dev);
10887 intel_shared_dpll_init(dev);
10888
10889 /* Just disable it once at startup */
10890 i915_disable_vga(dev);
10891 intel_setup_outputs(dev);
10892
10893 /* Just in case the BIOS is doing something questionable. */
10894 intel_disable_fbc(dev);
10895 }
10896
10897 static void
10898 intel_connector_break_all_links(struct intel_connector *connector)
10899 {
10900 connector->base.dpms = DRM_MODE_DPMS_OFF;
10901 connector->base.encoder = NULL;
10902 connector->encoder->connectors_active = false;
10903 connector->encoder->base.crtc = NULL;
10904 }
10905
10906 static void intel_enable_pipe_a(struct drm_device *dev)
10907 {
10908 struct intel_connector *connector;
10909 struct drm_connector *crt = NULL;
10910 struct intel_load_detect_pipe load_detect_temp;
10911
10912 /* We can't just switch on the pipe A, we need to set things up with a
10913 * proper mode and output configuration. As a gross hack, enable pipe A
10914 * by enabling the load detect pipe once. */
10915 list_for_each_entry(connector,
10916 &dev->mode_config.connector_list,
10917 base.head) {
10918 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10919 crt = &connector->base;
10920 break;
10921 }
10922 }
10923
10924 if (!crt)
10925 return;
10926
10927 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10928 intel_release_load_detect_pipe(crt, &load_detect_temp);
10929
10930
10931 }
10932
10933 static bool
10934 intel_check_plane_mapping(struct intel_crtc *crtc)
10935 {
10936 struct drm_device *dev = crtc->base.dev;
10937 struct drm_i915_private *dev_priv = dev->dev_private;
10938 u32 reg, val;
10939
10940 if (INTEL_INFO(dev)->num_pipes == 1)
10941 return true;
10942
10943 reg = DSPCNTR(!crtc->plane);
10944 val = I915_READ(reg);
10945
10946 if ((val & DISPLAY_PLANE_ENABLE) &&
10947 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10948 return false;
10949
10950 return true;
10951 }
10952
10953 static void intel_sanitize_crtc(struct intel_crtc *crtc)
10954 {
10955 struct drm_device *dev = crtc->base.dev;
10956 struct drm_i915_private *dev_priv = dev->dev_private;
10957 u32 reg;
10958
10959 /* Clear any frame start delays used for debugging left by the BIOS */
10960 reg = PIPECONF(crtc->config.cpu_transcoder);
10961 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10962
10963 /* We need to sanitize the plane -> pipe mapping first because this will
10964 * disable the crtc (and hence change the state) if it is wrong. Note
10965 * that gen4+ has a fixed plane -> pipe mapping. */
10966 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
10967 struct intel_connector *connector;
10968 bool plane;
10969
10970 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10971 crtc->base.base.id);
10972
10973 /* Pipe has the wrong plane attached and the plane is active.
10974 * Temporarily change the plane mapping and disable everything
10975 * ... */
10976 plane = crtc->plane;
10977 crtc->plane = !plane;
10978 dev_priv->display.crtc_disable(&crtc->base);
10979 crtc->plane = plane;
10980
10981 /* ... and break all links. */
10982 list_for_each_entry(connector, &dev->mode_config.connector_list,
10983 base.head) {
10984 if (connector->encoder->base.crtc != &crtc->base)
10985 continue;
10986
10987 intel_connector_break_all_links(connector);
10988 }
10989
10990 WARN_ON(crtc->active);
10991 crtc->base.enabled = false;
10992 }
10993
10994 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10995 crtc->pipe == PIPE_A && !crtc->active) {
10996 /* BIOS forgot to enable pipe A, this mostly happens after
10997 * resume. Force-enable the pipe to fix this, the update_dpms
10998 * call below we restore the pipe to the right state, but leave
10999 * the required bits on. */
11000 intel_enable_pipe_a(dev);
11001 }
11002
11003 /* Adjust the state of the output pipe according to whether we
11004 * have active connectors/encoders. */
11005 intel_crtc_update_dpms(&crtc->base);
11006
11007 if (crtc->active != crtc->base.enabled) {
11008 struct intel_encoder *encoder;
11009
11010 /* This can happen either due to bugs in the get_hw_state
11011 * functions or because the pipe is force-enabled due to the
11012 * pipe A quirk. */
11013 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
11014 crtc->base.base.id,
11015 crtc->base.enabled ? "enabled" : "disabled",
11016 crtc->active ? "enabled" : "disabled");
11017
11018 crtc->base.enabled = crtc->active;
11019
11020 /* Because we only establish the connector -> encoder ->
11021 * crtc links if something is active, this means the
11022 * crtc is now deactivated. Break the links. connector
11023 * -> encoder links are only establish when things are
11024 * actually up, hence no need to break them. */
11025 WARN_ON(crtc->active);
11026
11027 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
11028 WARN_ON(encoder->connectors_active);
11029 encoder->base.crtc = NULL;
11030 }
11031 }
11032 }
11033
11034 static void intel_sanitize_encoder(struct intel_encoder *encoder)
11035 {
11036 struct intel_connector *connector;
11037 struct drm_device *dev = encoder->base.dev;
11038
11039 /* We need to check both for a crtc link (meaning that the
11040 * encoder is active and trying to read from a pipe) and the
11041 * pipe itself being active. */
11042 bool has_active_crtc = encoder->base.crtc &&
11043 to_intel_crtc(encoder->base.crtc)->active;
11044
11045 if (encoder->connectors_active && !has_active_crtc) {
11046 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
11047 encoder->base.base.id,
11048 drm_get_encoder_name(&encoder->base));
11049
11050 /* Connector is active, but has no active pipe. This is
11051 * fallout from our resume register restoring. Disable
11052 * the encoder manually again. */
11053 if (encoder->base.crtc) {
11054 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
11055 encoder->base.base.id,
11056 drm_get_encoder_name(&encoder->base));
11057 encoder->disable(encoder);
11058 }
11059
11060 /* Inconsistent output/port/pipe state happens presumably due to
11061 * a bug in one of the get_hw_state functions. Or someplace else
11062 * in our code, like the register restore mess on resume. Clamp
11063 * things to off as a safer default. */
11064 list_for_each_entry(connector,
11065 &dev->mode_config.connector_list,
11066 base.head) {
11067 if (connector->encoder != encoder)
11068 continue;
11069
11070 intel_connector_break_all_links(connector);
11071 }
11072 }
11073 /* Enabled encoders without active connectors will be fixed in
11074 * the crtc fixup. */
11075 }
11076
11077 void i915_redisable_vga(struct drm_device *dev)
11078 {
11079 struct drm_i915_private *dev_priv = dev->dev_private;
11080 u32 vga_reg = i915_vgacntrl_reg(dev);
11081
11082 /* This function can be called both from intel_modeset_setup_hw_state or
11083 * at a very early point in our resume sequence, where the power well
11084 * structures are not yet restored. Since this function is at a very
11085 * paranoid "someone might have enabled VGA while we were not looking"
11086 * level, just check if the power well is enabled instead of trying to
11087 * follow the "don't touch the power well if we don't need it" policy
11088 * the rest of the driver uses. */
11089 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
11090 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
11091 return;
11092
11093 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
11094 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
11095 i915_disable_vga(dev);
11096 }
11097 }
11098
11099 static void intel_modeset_readout_hw_state(struct drm_device *dev)
11100 {
11101 struct drm_i915_private *dev_priv = dev->dev_private;
11102 enum pipe pipe;
11103 struct intel_crtc *crtc;
11104 struct intel_encoder *encoder;
11105 struct intel_connector *connector;
11106 int i;
11107
11108 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11109 base.head) {
11110 memset(&crtc->config, 0, sizeof(crtc->config));
11111
11112 crtc->active = dev_priv->display.get_pipe_config(crtc,
11113 &crtc->config);
11114
11115 crtc->base.enabled = crtc->active;
11116 crtc->primary_enabled = crtc->active;
11117
11118 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
11119 crtc->base.base.id,
11120 crtc->active ? "enabled" : "disabled");
11121 }
11122
11123 /* FIXME: Smash this into the new shared dpll infrastructure. */
11124 if (HAS_DDI(dev))
11125 intel_ddi_setup_hw_pll_state(dev);
11126
11127 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11128 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11129
11130 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
11131 pll->active = 0;
11132 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11133 base.head) {
11134 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11135 pll->active++;
11136 }
11137 pll->refcount = pll->active;
11138
11139 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
11140 pll->name, pll->refcount, pll->on);
11141 }
11142
11143 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11144 base.head) {
11145 pipe = 0;
11146
11147 if (encoder->get_hw_state(encoder, &pipe)) {
11148 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11149 encoder->base.crtc = &crtc->base;
11150 encoder->get_config(encoder, &crtc->config);
11151 } else {
11152 encoder->base.crtc = NULL;
11153 }
11154
11155 encoder->connectors_active = false;
11156 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
11157 encoder->base.base.id,
11158 drm_get_encoder_name(&encoder->base),
11159 encoder->base.crtc ? "enabled" : "disabled",
11160 pipe_name(pipe));
11161 }
11162
11163 list_for_each_entry(connector, &dev->mode_config.connector_list,
11164 base.head) {
11165 if (connector->get_hw_state(connector)) {
11166 connector->base.dpms = DRM_MODE_DPMS_ON;
11167 connector->encoder->connectors_active = true;
11168 connector->base.encoder = &connector->encoder->base;
11169 } else {
11170 connector->base.dpms = DRM_MODE_DPMS_OFF;
11171 connector->base.encoder = NULL;
11172 }
11173 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
11174 connector->base.base.id,
11175 drm_get_connector_name(&connector->base),
11176 connector->base.encoder ? "enabled" : "disabled");
11177 }
11178 }
11179
11180 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
11181 * and i915 state tracking structures. */
11182 void intel_modeset_setup_hw_state(struct drm_device *dev,
11183 bool force_restore)
11184 {
11185 struct drm_i915_private *dev_priv = dev->dev_private;
11186 enum pipe pipe;
11187 struct intel_crtc *crtc;
11188 struct intel_encoder *encoder;
11189 int i;
11190
11191 intel_modeset_readout_hw_state(dev);
11192
11193 /*
11194 * Now that we have the config, copy it to each CRTC struct
11195 * Note that this could go away if we move to using crtc_config
11196 * checking everywhere.
11197 */
11198 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
11199 base.head) {
11200 if (crtc->active && i915_fastboot) {
11201 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
11202
11203 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
11204 crtc->base.base.id);
11205 drm_mode_debug_printmodeline(&crtc->base.mode);
11206 }
11207 }
11208
11209 /* HW state is read out, now we need to sanitize this mess. */
11210 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
11211 base.head) {
11212 intel_sanitize_encoder(encoder);
11213 }
11214
11215 for_each_pipe(pipe) {
11216 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
11217 intel_sanitize_crtc(crtc);
11218 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
11219 }
11220
11221 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11222 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11223
11224 if (!pll->on || pll->active)
11225 continue;
11226
11227 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
11228
11229 pll->disable(dev_priv, pll);
11230 pll->on = false;
11231 }
11232
11233 if (IS_HASWELL(dev))
11234 ilk_wm_get_hw_state(dev);
11235
11236 if (force_restore) {
11237 i915_redisable_vga(dev);
11238
11239 /*
11240 * We need to use raw interfaces for restoring state to avoid
11241 * checking (bogus) intermediate states.
11242 */
11243 for_each_pipe(pipe) {
11244 struct drm_crtc *crtc =
11245 dev_priv->pipe_to_crtc_mapping[pipe];
11246
11247 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
11248 crtc->fb);
11249 }
11250 } else {
11251 intel_modeset_update_staged_output_state(dev);
11252 }
11253
11254 intel_modeset_check_state(dev);
11255
11256 drm_mode_config_reset(dev);
11257 }
11258
11259 void intel_modeset_gem_init(struct drm_device *dev)
11260 {
11261 intel_modeset_init_hw(dev);
11262
11263 intel_setup_overlay(dev);
11264
11265 intel_modeset_setup_hw_state(dev, false);
11266 }
11267
11268 void intel_modeset_cleanup(struct drm_device *dev)
11269 {
11270 struct drm_i915_private *dev_priv = dev->dev_private;
11271 struct drm_crtc *crtc;
11272 struct drm_connector *connector;
11273
11274 /*
11275 * Interrupts and polling as the first thing to avoid creating havoc.
11276 * Too much stuff here (turning of rps, connectors, ...) would
11277 * experience fancy races otherwise.
11278 */
11279 drm_irq_uninstall(dev);
11280 cancel_work_sync(&dev_priv->hotplug_work);
11281 /*
11282 * Due to the hpd irq storm handling the hotplug work can re-arm the
11283 * poll handlers. Hence disable polling after hpd handling is shut down.
11284 */
11285 drm_kms_helper_poll_fini(dev);
11286
11287 mutex_lock(&dev->struct_mutex);
11288
11289 intel_unregister_dsm_handler();
11290
11291 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
11292 /* Skip inactive CRTCs */
11293 if (!crtc->fb)
11294 continue;
11295
11296 intel_increase_pllclock(crtc);
11297 }
11298
11299 intel_disable_fbc(dev);
11300
11301 intel_disable_gt_powersave(dev);
11302
11303 ironlake_teardown_rc6(dev);
11304
11305 mutex_unlock(&dev->struct_mutex);
11306
11307 /* flush any delayed tasks or pending work */
11308 flush_scheduled_work();
11309
11310 /* destroy the backlight and sysfs files before encoders/connectors */
11311 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11312 intel_panel_destroy_backlight(connector);
11313 drm_sysfs_connector_remove(connector);
11314 }
11315
11316 drm_mode_config_cleanup(dev);
11317
11318 intel_cleanup_overlay(dev);
11319 }
11320
11321 /*
11322 * Return which encoder is currently attached for connector.
11323 */
11324 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
11325 {
11326 return &intel_attached_encoder(connector)->base;
11327 }
11328
11329 void intel_connector_attach_encoder(struct intel_connector *connector,
11330 struct intel_encoder *encoder)
11331 {
11332 connector->encoder = encoder;
11333 drm_mode_connector_attach_encoder(&connector->base,
11334 &encoder->base);
11335 }
11336
11337 /*
11338 * set vga decode state - true == enable VGA decode
11339 */
11340 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
11341 {
11342 struct drm_i915_private *dev_priv = dev->dev_private;
11343 u16 gmch_ctrl;
11344
11345 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
11346 if (state)
11347 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
11348 else
11349 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
11350 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
11351 return 0;
11352 }
11353
11354 struct intel_display_error_state {
11355
11356 u32 power_well_driver;
11357
11358 int num_transcoders;
11359
11360 struct intel_cursor_error_state {
11361 u32 control;
11362 u32 position;
11363 u32 base;
11364 u32 size;
11365 } cursor[I915_MAX_PIPES];
11366
11367 struct intel_pipe_error_state {
11368 bool power_domain_on;
11369 u32 source;
11370 } pipe[I915_MAX_PIPES];
11371
11372 struct intel_plane_error_state {
11373 u32 control;
11374 u32 stride;
11375 u32 size;
11376 u32 pos;
11377 u32 addr;
11378 u32 surface;
11379 u32 tile_offset;
11380 } plane[I915_MAX_PIPES];
11381
11382 struct intel_transcoder_error_state {
11383 bool power_domain_on;
11384 enum transcoder cpu_transcoder;
11385
11386 u32 conf;
11387
11388 u32 htotal;
11389 u32 hblank;
11390 u32 hsync;
11391 u32 vtotal;
11392 u32 vblank;
11393 u32 vsync;
11394 } transcoder[4];
11395 };
11396
11397 struct intel_display_error_state *
11398 intel_display_capture_error_state(struct drm_device *dev)
11399 {
11400 drm_i915_private_t *dev_priv = dev->dev_private;
11401 struct intel_display_error_state *error;
11402 int transcoders[] = {
11403 TRANSCODER_A,
11404 TRANSCODER_B,
11405 TRANSCODER_C,
11406 TRANSCODER_EDP,
11407 };
11408 int i;
11409
11410 if (INTEL_INFO(dev)->num_pipes == 0)
11411 return NULL;
11412
11413 error = kzalloc(sizeof(*error), GFP_ATOMIC);
11414 if (error == NULL)
11415 return NULL;
11416
11417 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11418 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11419
11420 for_each_pipe(i) {
11421 error->pipe[i].power_domain_on =
11422 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11423 if (!error->pipe[i].power_domain_on)
11424 continue;
11425
11426 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11427 error->cursor[i].control = I915_READ(CURCNTR(i));
11428 error->cursor[i].position = I915_READ(CURPOS(i));
11429 error->cursor[i].base = I915_READ(CURBASE(i));
11430 } else {
11431 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11432 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11433 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11434 }
11435
11436 error->plane[i].control = I915_READ(DSPCNTR(i));
11437 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
11438 if (INTEL_INFO(dev)->gen <= 3) {
11439 error->plane[i].size = I915_READ(DSPSIZE(i));
11440 error->plane[i].pos = I915_READ(DSPPOS(i));
11441 }
11442 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11443 error->plane[i].addr = I915_READ(DSPADDR(i));
11444 if (INTEL_INFO(dev)->gen >= 4) {
11445 error->plane[i].surface = I915_READ(DSPSURF(i));
11446 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11447 }
11448
11449 error->pipe[i].source = I915_READ(PIPESRC(i));
11450 }
11451
11452 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11453 if (HAS_DDI(dev_priv->dev))
11454 error->num_transcoders++; /* Account for eDP. */
11455
11456 for (i = 0; i < error->num_transcoders; i++) {
11457 enum transcoder cpu_transcoder = transcoders[i];
11458
11459 error->transcoder[i].power_domain_on =
11460 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11461 if (!error->transcoder[i].power_domain_on)
11462 continue;
11463
11464 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11465
11466 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11467 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11468 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11469 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11470 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11471 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11472 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
11473 }
11474
11475 return error;
11476 }
11477
11478 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11479
11480 void
11481 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11482 struct drm_device *dev,
11483 struct intel_display_error_state *error)
11484 {
11485 int i;
11486
11487 if (!error)
11488 return;
11489
11490 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11491 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11492 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11493 error->power_well_driver);
11494 for_each_pipe(i) {
11495 err_printf(m, "Pipe [%d]:\n", i);
11496 err_printf(m, " Power: %s\n",
11497 error->pipe[i].power_domain_on ? "on" : "off");
11498 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11499
11500 err_printf(m, "Plane [%d]:\n", i);
11501 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11502 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
11503 if (INTEL_INFO(dev)->gen <= 3) {
11504 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11505 err_printf(m, " POS: %08x\n", error->plane[i].pos);
11506 }
11507 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11508 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
11509 if (INTEL_INFO(dev)->gen >= 4) {
11510 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11511 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
11512 }
11513
11514 err_printf(m, "Cursor [%d]:\n", i);
11515 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11516 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11517 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
11518 }
11519
11520 for (i = 0; i < error->num_transcoders; i++) {
11521 err_printf(m, "CPU transcoder: %c\n",
11522 transcoder_name(error->transcoder[i].cpu_transcoder));
11523 err_printf(m, " Power: %s\n",
11524 error->transcoder[i].power_domain_on ? "on" : "off");
11525 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11526 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11527 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11528 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11529 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11530 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11531 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11532 }
11533 }
Linux kernel - Deliverables
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