2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
52 DRM_FORMAT_XRGB8888, \
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2
[] = {
57 COMMON_PRIMARY_FORMATS
,
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4
[] = {
64 COMMON_PRIMARY_FORMATS
, \
67 DRM_FORMAT_XRGB2101010
,
68 DRM_FORMAT_ARGB2101010
,
69 DRM_FORMAT_XBGR2101010
,
70 DRM_FORMAT_ABGR2101010
,
74 static const uint32_t intel_cursor_formats
[] = {
78 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
80 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_state
*pipe_config
);
82 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
83 struct intel_crtc_state
*pipe_config
);
85 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
86 int x
, int y
, struct drm_framebuffer
*old_fb
,
87 struct drm_atomic_state
*state
);
88 static int intel_framebuffer_init(struct drm_device
*dev
,
89 struct intel_framebuffer
*ifb
,
90 struct drm_mode_fb_cmd2
*mode_cmd
,
91 struct drm_i915_gem_object
*obj
);
92 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
93 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
95 struct intel_link_m_n
*m_n
,
96 struct intel_link_m_n
*m2_n2
);
97 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
98 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
99 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
100 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
101 const struct intel_crtc_state
*pipe_config
);
102 static void chv_prepare_pll(struct intel_crtc
*crtc
,
103 const struct intel_crtc_state
*pipe_config
);
104 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
105 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
106 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
107 struct intel_crtc_state
*crtc_state
);
108 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
110 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
);
111 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
);
113 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
115 if (!connector
->mst_port
)
116 return connector
->encoder
;
118 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
127 int p2_slow
, p2_fast
;
130 typedef struct intel_limit intel_limit_t
;
132 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
137 intel_pch_rawclk(struct drm_device
*dev
)
139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
141 WARN_ON(!HAS_PCH_SPLIT(dev
));
143 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
146 static inline u32
/* units of 100MHz */
147 intel_fdi_link_freq(struct drm_device
*dev
)
150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
151 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
156 static const intel_limit_t intel_limits_i8xx_dac
= {
157 .dot
= { .min
= 25000, .max
= 350000 },
158 .vco
= { .min
= 908000, .max
= 1512000 },
159 .n
= { .min
= 2, .max
= 16 },
160 .m
= { .min
= 96, .max
= 140 },
161 .m1
= { .min
= 18, .max
= 26 },
162 .m2
= { .min
= 6, .max
= 16 },
163 .p
= { .min
= 4, .max
= 128 },
164 .p1
= { .min
= 2, .max
= 33 },
165 .p2
= { .dot_limit
= 165000,
166 .p2_slow
= 4, .p2_fast
= 2 },
169 static const intel_limit_t intel_limits_i8xx_dvo
= {
170 .dot
= { .min
= 25000, .max
= 350000 },
171 .vco
= { .min
= 908000, .max
= 1512000 },
172 .n
= { .min
= 2, .max
= 16 },
173 .m
= { .min
= 96, .max
= 140 },
174 .m1
= { .min
= 18, .max
= 26 },
175 .m2
= { .min
= 6, .max
= 16 },
176 .p
= { .min
= 4, .max
= 128 },
177 .p1
= { .min
= 2, .max
= 33 },
178 .p2
= { .dot_limit
= 165000,
179 .p2_slow
= 4, .p2_fast
= 4 },
182 static const intel_limit_t intel_limits_i8xx_lvds
= {
183 .dot
= { .min
= 25000, .max
= 350000 },
184 .vco
= { .min
= 908000, .max
= 1512000 },
185 .n
= { .min
= 2, .max
= 16 },
186 .m
= { .min
= 96, .max
= 140 },
187 .m1
= { .min
= 18, .max
= 26 },
188 .m2
= { .min
= 6, .max
= 16 },
189 .p
= { .min
= 4, .max
= 128 },
190 .p1
= { .min
= 1, .max
= 6 },
191 .p2
= { .dot_limit
= 165000,
192 .p2_slow
= 14, .p2_fast
= 7 },
195 static const intel_limit_t intel_limits_i9xx_sdvo
= {
196 .dot
= { .min
= 20000, .max
= 400000 },
197 .vco
= { .min
= 1400000, .max
= 2800000 },
198 .n
= { .min
= 1, .max
= 6 },
199 .m
= { .min
= 70, .max
= 120 },
200 .m1
= { .min
= 8, .max
= 18 },
201 .m2
= { .min
= 3, .max
= 7 },
202 .p
= { .min
= 5, .max
= 80 },
203 .p1
= { .min
= 1, .max
= 8 },
204 .p2
= { .dot_limit
= 200000,
205 .p2_slow
= 10, .p2_fast
= 5 },
208 static const intel_limit_t intel_limits_i9xx_lvds
= {
209 .dot
= { .min
= 20000, .max
= 400000 },
210 .vco
= { .min
= 1400000, .max
= 2800000 },
211 .n
= { .min
= 1, .max
= 6 },
212 .m
= { .min
= 70, .max
= 120 },
213 .m1
= { .min
= 8, .max
= 18 },
214 .m2
= { .min
= 3, .max
= 7 },
215 .p
= { .min
= 7, .max
= 98 },
216 .p1
= { .min
= 1, .max
= 8 },
217 .p2
= { .dot_limit
= 112000,
218 .p2_slow
= 14, .p2_fast
= 7 },
222 static const intel_limit_t intel_limits_g4x_sdvo
= {
223 .dot
= { .min
= 25000, .max
= 270000 },
224 .vco
= { .min
= 1750000, .max
= 3500000},
225 .n
= { .min
= 1, .max
= 4 },
226 .m
= { .min
= 104, .max
= 138 },
227 .m1
= { .min
= 17, .max
= 23 },
228 .m2
= { .min
= 5, .max
= 11 },
229 .p
= { .min
= 10, .max
= 30 },
230 .p1
= { .min
= 1, .max
= 3},
231 .p2
= { .dot_limit
= 270000,
237 static const intel_limit_t intel_limits_g4x_hdmi
= {
238 .dot
= { .min
= 22000, .max
= 400000 },
239 .vco
= { .min
= 1750000, .max
= 3500000},
240 .n
= { .min
= 1, .max
= 4 },
241 .m
= { .min
= 104, .max
= 138 },
242 .m1
= { .min
= 16, .max
= 23 },
243 .m2
= { .min
= 5, .max
= 11 },
244 .p
= { .min
= 5, .max
= 80 },
245 .p1
= { .min
= 1, .max
= 8},
246 .p2
= { .dot_limit
= 165000,
247 .p2_slow
= 10, .p2_fast
= 5 },
250 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
251 .dot
= { .min
= 20000, .max
= 115000 },
252 .vco
= { .min
= 1750000, .max
= 3500000 },
253 .n
= { .min
= 1, .max
= 3 },
254 .m
= { .min
= 104, .max
= 138 },
255 .m1
= { .min
= 17, .max
= 23 },
256 .m2
= { .min
= 5, .max
= 11 },
257 .p
= { .min
= 28, .max
= 112 },
258 .p1
= { .min
= 2, .max
= 8 },
259 .p2
= { .dot_limit
= 0,
260 .p2_slow
= 14, .p2_fast
= 14
264 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
265 .dot
= { .min
= 80000, .max
= 224000 },
266 .vco
= { .min
= 1750000, .max
= 3500000 },
267 .n
= { .min
= 1, .max
= 3 },
268 .m
= { .min
= 104, .max
= 138 },
269 .m1
= { .min
= 17, .max
= 23 },
270 .m2
= { .min
= 5, .max
= 11 },
271 .p
= { .min
= 14, .max
= 42 },
272 .p1
= { .min
= 2, .max
= 6 },
273 .p2
= { .dot_limit
= 0,
274 .p2_slow
= 7, .p2_fast
= 7
278 static const intel_limit_t intel_limits_pineview_sdvo
= {
279 .dot
= { .min
= 20000, .max
= 400000},
280 .vco
= { .min
= 1700000, .max
= 3500000 },
281 /* Pineview's Ncounter is a ring counter */
282 .n
= { .min
= 3, .max
= 6 },
283 .m
= { .min
= 2, .max
= 256 },
284 /* Pineview only has one combined m divider, which we treat as m2. */
285 .m1
= { .min
= 0, .max
= 0 },
286 .m2
= { .min
= 0, .max
= 254 },
287 .p
= { .min
= 5, .max
= 80 },
288 .p1
= { .min
= 1, .max
= 8 },
289 .p2
= { .dot_limit
= 200000,
290 .p2_slow
= 10, .p2_fast
= 5 },
293 static const intel_limit_t intel_limits_pineview_lvds
= {
294 .dot
= { .min
= 20000, .max
= 400000 },
295 .vco
= { .min
= 1700000, .max
= 3500000 },
296 .n
= { .min
= 3, .max
= 6 },
297 .m
= { .min
= 2, .max
= 256 },
298 .m1
= { .min
= 0, .max
= 0 },
299 .m2
= { .min
= 0, .max
= 254 },
300 .p
= { .min
= 7, .max
= 112 },
301 .p1
= { .min
= 1, .max
= 8 },
302 .p2
= { .dot_limit
= 112000,
303 .p2_slow
= 14, .p2_fast
= 14 },
306 /* Ironlake / Sandybridge
308 * We calculate clock using (register_value + 2) for N/M1/M2, so here
309 * the range value for them is (actual_value - 2).
311 static const intel_limit_t intel_limits_ironlake_dac
= {
312 .dot
= { .min
= 25000, .max
= 350000 },
313 .vco
= { .min
= 1760000, .max
= 3510000 },
314 .n
= { .min
= 1, .max
= 5 },
315 .m
= { .min
= 79, .max
= 127 },
316 .m1
= { .min
= 12, .max
= 22 },
317 .m2
= { .min
= 5, .max
= 9 },
318 .p
= { .min
= 5, .max
= 80 },
319 .p1
= { .min
= 1, .max
= 8 },
320 .p2
= { .dot_limit
= 225000,
321 .p2_slow
= 10, .p2_fast
= 5 },
324 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
325 .dot
= { .min
= 25000, .max
= 350000 },
326 .vco
= { .min
= 1760000, .max
= 3510000 },
327 .n
= { .min
= 1, .max
= 3 },
328 .m
= { .min
= 79, .max
= 118 },
329 .m1
= { .min
= 12, .max
= 22 },
330 .m2
= { .min
= 5, .max
= 9 },
331 .p
= { .min
= 28, .max
= 112 },
332 .p1
= { .min
= 2, .max
= 8 },
333 .p2
= { .dot_limit
= 225000,
334 .p2_slow
= 14, .p2_fast
= 14 },
337 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
338 .dot
= { .min
= 25000, .max
= 350000 },
339 .vco
= { .min
= 1760000, .max
= 3510000 },
340 .n
= { .min
= 1, .max
= 3 },
341 .m
= { .min
= 79, .max
= 127 },
342 .m1
= { .min
= 12, .max
= 22 },
343 .m2
= { .min
= 5, .max
= 9 },
344 .p
= { .min
= 14, .max
= 56 },
345 .p1
= { .min
= 2, .max
= 8 },
346 .p2
= { .dot_limit
= 225000,
347 .p2_slow
= 7, .p2_fast
= 7 },
350 /* LVDS 100mhz refclk limits. */
351 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
352 .dot
= { .min
= 25000, .max
= 350000 },
353 .vco
= { .min
= 1760000, .max
= 3510000 },
354 .n
= { .min
= 1, .max
= 2 },
355 .m
= { .min
= 79, .max
= 126 },
356 .m1
= { .min
= 12, .max
= 22 },
357 .m2
= { .min
= 5, .max
= 9 },
358 .p
= { .min
= 28, .max
= 112 },
359 .p1
= { .min
= 2, .max
= 8 },
360 .p2
= { .dot_limit
= 225000,
361 .p2_slow
= 14, .p2_fast
= 14 },
364 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
365 .dot
= { .min
= 25000, .max
= 350000 },
366 .vco
= { .min
= 1760000, .max
= 3510000 },
367 .n
= { .min
= 1, .max
= 3 },
368 .m
= { .min
= 79, .max
= 126 },
369 .m1
= { .min
= 12, .max
= 22 },
370 .m2
= { .min
= 5, .max
= 9 },
371 .p
= { .min
= 14, .max
= 42 },
372 .p1
= { .min
= 2, .max
= 6 },
373 .p2
= { .dot_limit
= 225000,
374 .p2_slow
= 7, .p2_fast
= 7 },
377 static const intel_limit_t intel_limits_vlv
= {
379 * These are the data rate limits (measured in fast clocks)
380 * since those are the strictest limits we have. The fast
381 * clock and actual rate limits are more relaxed, so checking
382 * them would make no difference.
384 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
385 .vco
= { .min
= 4000000, .max
= 6000000 },
386 .n
= { .min
= 1, .max
= 7 },
387 .m1
= { .min
= 2, .max
= 3 },
388 .m2
= { .min
= 11, .max
= 156 },
389 .p1
= { .min
= 2, .max
= 3 },
390 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
393 static const intel_limit_t intel_limits_chv
= {
395 * These are the data rate limits (measured in fast clocks)
396 * since those are the strictest limits we have. The fast
397 * clock and actual rate limits are more relaxed, so checking
398 * them would make no difference.
400 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
401 .vco
= { .min
= 4800000, .max
= 6480000 },
402 .n
= { .min
= 1, .max
= 1 },
403 .m1
= { .min
= 2, .max
= 2 },
404 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
405 .p1
= { .min
= 2, .max
= 4 },
406 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
409 static const intel_limit_t intel_limits_bxt
= {
410 /* FIXME: find real dot limits */
411 .dot
= { .min
= 0, .max
= INT_MAX
},
412 .vco
= { .min
= 4800000, .max
= 6480000 },
413 .n
= { .min
= 1, .max
= 1 },
414 .m1
= { .min
= 2, .max
= 2 },
415 /* FIXME: find real m2 limits */
416 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
417 .p1
= { .min
= 2, .max
= 4 },
418 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
421 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
423 clock
->m
= clock
->m1
* clock
->m2
;
424 clock
->p
= clock
->p1
* clock
->p2
;
425 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
427 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
428 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
432 * Returns whether any output on the specified pipe is of the specified type
434 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
436 struct drm_device
*dev
= crtc
->base
.dev
;
437 struct intel_encoder
*encoder
;
439 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
440 if (encoder
->type
== type
)
447 * Returns whether any output on the specified pipe will have the specified
448 * type after a staged modeset is complete, i.e., the same as
449 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
452 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
455 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
456 struct drm_connector
*connector
;
457 struct drm_connector_state
*connector_state
;
458 struct intel_encoder
*encoder
;
459 int i
, num_connectors
= 0;
461 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
462 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
467 encoder
= to_intel_encoder(connector_state
->best_encoder
);
468 if (encoder
->type
== type
)
472 WARN_ON(num_connectors
== 0);
477 static const intel_limit_t
*
478 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
480 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
481 const intel_limit_t
*limit
;
483 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
484 if (intel_is_dual_link_lvds(dev
)) {
485 if (refclk
== 100000)
486 limit
= &intel_limits_ironlake_dual_lvds_100m
;
488 limit
= &intel_limits_ironlake_dual_lvds
;
490 if (refclk
== 100000)
491 limit
= &intel_limits_ironlake_single_lvds_100m
;
493 limit
= &intel_limits_ironlake_single_lvds
;
496 limit
= &intel_limits_ironlake_dac
;
501 static const intel_limit_t
*
502 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
504 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
505 const intel_limit_t
*limit
;
507 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
508 if (intel_is_dual_link_lvds(dev
))
509 limit
= &intel_limits_g4x_dual_channel_lvds
;
511 limit
= &intel_limits_g4x_single_channel_lvds
;
512 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
513 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
514 limit
= &intel_limits_g4x_hdmi
;
515 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
516 limit
= &intel_limits_g4x_sdvo
;
517 } else /* The option is for other outputs */
518 limit
= &intel_limits_i9xx_sdvo
;
523 static const intel_limit_t
*
524 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
526 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
527 const intel_limit_t
*limit
;
530 limit
= &intel_limits_bxt
;
531 else if (HAS_PCH_SPLIT(dev
))
532 limit
= intel_ironlake_limit(crtc_state
, refclk
);
533 else if (IS_G4X(dev
)) {
534 limit
= intel_g4x_limit(crtc_state
);
535 } else if (IS_PINEVIEW(dev
)) {
536 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
537 limit
= &intel_limits_pineview_lvds
;
539 limit
= &intel_limits_pineview_sdvo
;
540 } else if (IS_CHERRYVIEW(dev
)) {
541 limit
= &intel_limits_chv
;
542 } else if (IS_VALLEYVIEW(dev
)) {
543 limit
= &intel_limits_vlv
;
544 } else if (!IS_GEN2(dev
)) {
545 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
546 limit
= &intel_limits_i9xx_lvds
;
548 limit
= &intel_limits_i9xx_sdvo
;
550 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
551 limit
= &intel_limits_i8xx_lvds
;
552 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
553 limit
= &intel_limits_i8xx_dvo
;
555 limit
= &intel_limits_i8xx_dac
;
560 /* m1 is reserved as 0 in Pineview, n is a ring counter */
561 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
563 clock
->m
= clock
->m2
+ 2;
564 clock
->p
= clock
->p1
* clock
->p2
;
565 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
567 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
568 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
571 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
573 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
576 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
578 clock
->m
= i9xx_dpll_compute_m(clock
);
579 clock
->p
= clock
->p1
* clock
->p2
;
580 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
582 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
583 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
586 static void chv_clock(int refclk
, intel_clock_t
*clock
)
588 clock
->m
= clock
->m1
* clock
->m2
;
589 clock
->p
= clock
->p1
* clock
->p2
;
590 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
592 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
594 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
597 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
599 * Returns whether the given set of divisors are valid for a given refclk with
600 * the given connectors.
603 static bool intel_PLL_is_valid(struct drm_device
*dev
,
604 const intel_limit_t
*limit
,
605 const intel_clock_t
*clock
)
607 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
608 INTELPllInvalid("n out of range\n");
609 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
610 INTELPllInvalid("p1 out of range\n");
611 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
612 INTELPllInvalid("m2 out of range\n");
613 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
614 INTELPllInvalid("m1 out of range\n");
616 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
617 if (clock
->m1
<= clock
->m2
)
618 INTELPllInvalid("m1 <= m2\n");
620 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
621 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
622 INTELPllInvalid("p out of range\n");
623 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
624 INTELPllInvalid("m out of range\n");
627 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
628 INTELPllInvalid("vco out of range\n");
629 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
630 * connector, etc., rather than just a single range.
632 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
633 INTELPllInvalid("dot out of range\n");
639 i9xx_find_best_dpll(const intel_limit_t
*limit
,
640 struct intel_crtc_state
*crtc_state
,
641 int target
, int refclk
, intel_clock_t
*match_clock
,
642 intel_clock_t
*best_clock
)
644 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
645 struct drm_device
*dev
= crtc
->base
.dev
;
649 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
651 * For LVDS just rely on its current settings for dual-channel.
652 * We haven't figured out how to reliably set up different
653 * single/dual channel state, if we even can.
655 if (intel_is_dual_link_lvds(dev
))
656 clock
.p2
= limit
->p2
.p2_fast
;
658 clock
.p2
= limit
->p2
.p2_slow
;
660 if (target
< limit
->p2
.dot_limit
)
661 clock
.p2
= limit
->p2
.p2_slow
;
663 clock
.p2
= limit
->p2
.p2_fast
;
666 memset(best_clock
, 0, sizeof(*best_clock
));
668 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
670 for (clock
.m2
= limit
->m2
.min
;
671 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
672 if (clock
.m2
>= clock
.m1
)
674 for (clock
.n
= limit
->n
.min
;
675 clock
.n
<= limit
->n
.max
; clock
.n
++) {
676 for (clock
.p1
= limit
->p1
.min
;
677 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
680 i9xx_clock(refclk
, &clock
);
681 if (!intel_PLL_is_valid(dev
, limit
,
685 clock
.p
!= match_clock
->p
)
688 this_err
= abs(clock
.dot
- target
);
689 if (this_err
< err
) {
698 return (err
!= target
);
702 pnv_find_best_dpll(const intel_limit_t
*limit
,
703 struct intel_crtc_state
*crtc_state
,
704 int target
, int refclk
, intel_clock_t
*match_clock
,
705 intel_clock_t
*best_clock
)
707 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
708 struct drm_device
*dev
= crtc
->base
.dev
;
712 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
714 * For LVDS just rely on its current settings for dual-channel.
715 * We haven't figured out how to reliably set up different
716 * single/dual channel state, if we even can.
718 if (intel_is_dual_link_lvds(dev
))
719 clock
.p2
= limit
->p2
.p2_fast
;
721 clock
.p2
= limit
->p2
.p2_slow
;
723 if (target
< limit
->p2
.dot_limit
)
724 clock
.p2
= limit
->p2
.p2_slow
;
726 clock
.p2
= limit
->p2
.p2_fast
;
729 memset(best_clock
, 0, sizeof(*best_clock
));
731 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
733 for (clock
.m2
= limit
->m2
.min
;
734 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
735 for (clock
.n
= limit
->n
.min
;
736 clock
.n
<= limit
->n
.max
; clock
.n
++) {
737 for (clock
.p1
= limit
->p1
.min
;
738 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
741 pineview_clock(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 clock
.p
!= match_clock
->p
)
749 this_err
= abs(clock
.dot
- target
);
750 if (this_err
< err
) {
759 return (err
!= target
);
763 g4x_find_best_dpll(const intel_limit_t
*limit
,
764 struct intel_crtc_state
*crtc_state
,
765 int target
, int refclk
, intel_clock_t
*match_clock
,
766 intel_clock_t
*best_clock
)
768 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
769 struct drm_device
*dev
= crtc
->base
.dev
;
773 /* approximately equals target * 0.00585 */
774 int err_most
= (target
>> 8) + (target
>> 9);
777 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
778 if (intel_is_dual_link_lvds(dev
))
779 clock
.p2
= limit
->p2
.p2_fast
;
781 clock
.p2
= limit
->p2
.p2_slow
;
783 if (target
< limit
->p2
.dot_limit
)
784 clock
.p2
= limit
->p2
.p2_slow
;
786 clock
.p2
= limit
->p2
.p2_fast
;
789 memset(best_clock
, 0, sizeof(*best_clock
));
790 max_n
= limit
->n
.max
;
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
793 /* based on hardware requirement, prefere larger m1,m2 */
794 for (clock
.m1
= limit
->m1
.max
;
795 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
796 for (clock
.m2
= limit
->m2
.max
;
797 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
798 for (clock
.p1
= limit
->p1
.max
;
799 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
802 i9xx_clock(refclk
, &clock
);
803 if (!intel_PLL_is_valid(dev
, limit
,
807 this_err
= abs(clock
.dot
- target
);
808 if (this_err
< err_most
) {
822 * Check if the calculated PLL configuration is more optimal compared to the
823 * best configuration and error found so far. Return the calculated error.
825 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
826 const intel_clock_t
*calculated_clock
,
827 const intel_clock_t
*best_clock
,
828 unsigned int best_error_ppm
,
829 unsigned int *error_ppm
)
832 * For CHV ignore the error and consider only the P value.
833 * Prefer a bigger P value based on HW requirements.
835 if (IS_CHERRYVIEW(dev
)) {
838 return calculated_clock
->p
> best_clock
->p
;
841 if (WARN_ON_ONCE(!target_freq
))
844 *error_ppm
= div_u64(1000000ULL *
845 abs(target_freq
- calculated_clock
->dot
),
848 * Prefer a better P value over a better (smaller) error if the error
849 * is small. Ensure this preference for future configurations too by
850 * setting the error to 0.
852 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
858 return *error_ppm
+ 10 < best_error_ppm
;
862 vlv_find_best_dpll(const intel_limit_t
*limit
,
863 struct intel_crtc_state
*crtc_state
,
864 int target
, int refclk
, intel_clock_t
*match_clock
,
865 intel_clock_t
*best_clock
)
867 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
868 struct drm_device
*dev
= crtc
->base
.dev
;
870 unsigned int bestppm
= 1000000;
871 /* min update 19.2 MHz */
872 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
875 target
*= 5; /* fast clock */
877 memset(best_clock
, 0, sizeof(*best_clock
));
879 /* based on hardware requirement, prefer smaller n to precision */
880 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
881 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
882 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
883 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
884 clock
.p
= clock
.p1
* clock
.p2
;
885 /* based on hardware requirement, prefer bigger m1,m2 values */
886 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
889 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
892 vlv_clock(refclk
, &clock
);
894 if (!intel_PLL_is_valid(dev
, limit
,
898 if (!vlv_PLL_is_optimal(dev
, target
,
916 chv_find_best_dpll(const intel_limit_t
*limit
,
917 struct intel_crtc_state
*crtc_state
,
918 int target
, int refclk
, intel_clock_t
*match_clock
,
919 intel_clock_t
*best_clock
)
921 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
922 struct drm_device
*dev
= crtc
->base
.dev
;
923 unsigned int best_error_ppm
;
928 memset(best_clock
, 0, sizeof(*best_clock
));
929 best_error_ppm
= 1000000;
932 * Based on hardware doc, the n always set to 1, and m1 always
933 * set to 2. If requires to support 200Mhz refclk, we need to
934 * revisit this because n may not 1 anymore.
936 clock
.n
= 1, clock
.m1
= 2;
937 target
*= 5; /* fast clock */
939 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
940 for (clock
.p2
= limit
->p2
.p2_fast
;
941 clock
.p2
>= limit
->p2
.p2_slow
;
942 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
943 unsigned int error_ppm
;
945 clock
.p
= clock
.p1
* clock
.p2
;
947 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
948 clock
.n
) << 22, refclk
* clock
.m1
);
950 if (m2
> INT_MAX
/clock
.m1
)
955 chv_clock(refclk
, &clock
);
957 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
960 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
961 best_error_ppm
, &error_ppm
))
965 best_error_ppm
= error_ppm
;
973 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
974 intel_clock_t
*best_clock
)
976 int refclk
= i9xx_get_refclk(crtc_state
, 0);
978 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
979 target_clock
, refclk
, NULL
, best_clock
);
982 bool intel_crtc_active(struct drm_crtc
*crtc
)
984 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
986 /* Be paranoid as we can arrive here with only partial
987 * state retrieved from the hardware during setup.
989 * We can ditch the adjusted_mode.crtc_clock check as soon
990 * as Haswell has gained clock readout/fastboot support.
992 * We can ditch the crtc->primary->fb check as soon as we can
993 * properly reconstruct framebuffers.
995 * FIXME: The intel_crtc->active here should be switched to
996 * crtc->state->active once we have proper CRTC states wired up
999 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1000 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1003 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1006 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1007 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1009 return intel_crtc
->config
->cpu_transcoder
;
1012 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1015 u32 reg
= PIPEDSL(pipe
);
1020 line_mask
= DSL_LINEMASK_GEN2
;
1022 line_mask
= DSL_LINEMASK_GEN3
;
1024 line1
= I915_READ(reg
) & line_mask
;
1026 line2
= I915_READ(reg
) & line_mask
;
1028 return line1
== line2
;
1032 * intel_wait_for_pipe_off - wait for pipe to turn off
1033 * @crtc: crtc whose pipe to wait for
1035 * After disabling a pipe, we can't wait for vblank in the usual way,
1036 * spinning on the vblank interrupt status bit, since we won't actually
1037 * see an interrupt when the pipe is disabled.
1039 * On Gen4 and above:
1040 * wait for the pipe register state bit to turn off
1043 * wait for the display line value to settle (it usually
1044 * ends up stopping at the start of the next frame).
1047 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1049 struct drm_device
*dev
= crtc
->base
.dev
;
1050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1051 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1052 enum pipe pipe
= crtc
->pipe
;
1054 if (INTEL_INFO(dev
)->gen
>= 4) {
1055 int reg
= PIPECONF(cpu_transcoder
);
1057 /* Wait for the Pipe State to go off */
1058 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1060 WARN(1, "pipe_off wait timed out\n");
1062 /* Wait for the display line to settle */
1063 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1064 WARN(1, "pipe_off wait timed out\n");
1069 * ibx_digital_port_connected - is the specified port connected?
1070 * @dev_priv: i915 private structure
1071 * @port: the port to test
1073 * Returns true if @port is connected, false otherwise.
1075 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1076 struct intel_digital_port
*port
)
1080 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1081 switch (port
->port
) {
1083 bit
= SDE_PORTB_HOTPLUG
;
1086 bit
= SDE_PORTC_HOTPLUG
;
1089 bit
= SDE_PORTD_HOTPLUG
;
1095 switch (port
->port
) {
1097 bit
= SDE_PORTB_HOTPLUG_CPT
;
1100 bit
= SDE_PORTC_HOTPLUG_CPT
;
1103 bit
= SDE_PORTD_HOTPLUG_CPT
;
1110 return I915_READ(SDEISR
) & bit
;
1113 static const char *state_string(bool enabled
)
1115 return enabled
? "on" : "off";
1118 /* Only for pre-ILK configs */
1119 void assert_pll(struct drm_i915_private
*dev_priv
,
1120 enum pipe pipe
, bool state
)
1127 val
= I915_READ(reg
);
1128 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1129 I915_STATE_WARN(cur_state
!= state
,
1130 "PLL state assertion failure (expected %s, current %s)\n",
1131 state_string(state
), state_string(cur_state
));
1134 /* XXX: the dsi pll is shared between MIPI DSI ports */
1135 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1140 mutex_lock(&dev_priv
->dpio_lock
);
1141 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1142 mutex_unlock(&dev_priv
->dpio_lock
);
1144 cur_state
= val
& DSI_PLL_VCO_EN
;
1145 I915_STATE_WARN(cur_state
!= state
,
1146 "DSI PLL state assertion failure (expected %s, current %s)\n",
1147 state_string(state
), state_string(cur_state
));
1149 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1150 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1152 struct intel_shared_dpll
*
1153 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1155 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1157 if (crtc
->config
->shared_dpll
< 0)
1160 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1164 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1165 struct intel_shared_dpll
*pll
,
1169 struct intel_dpll_hw_state hw_state
;
1172 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1175 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1176 I915_STATE_WARN(cur_state
!= state
,
1177 "%s assertion failure (expected %s, current %s)\n",
1178 pll
->name
, state_string(state
), state_string(cur_state
));
1181 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1182 enum pipe pipe
, bool state
)
1187 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1190 if (HAS_DDI(dev_priv
->dev
)) {
1191 /* DDI does not have a specific FDI_TX register */
1192 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1193 val
= I915_READ(reg
);
1194 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1196 reg
= FDI_TX_CTL(pipe
);
1197 val
= I915_READ(reg
);
1198 cur_state
= !!(val
& FDI_TX_ENABLE
);
1200 I915_STATE_WARN(cur_state
!= state
,
1201 "FDI TX state assertion failure (expected %s, current %s)\n",
1202 state_string(state
), state_string(cur_state
));
1204 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1205 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1207 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1208 enum pipe pipe
, bool state
)
1214 reg
= FDI_RX_CTL(pipe
);
1215 val
= I915_READ(reg
);
1216 cur_state
= !!(val
& FDI_RX_ENABLE
);
1217 I915_STATE_WARN(cur_state
!= state
,
1218 "FDI RX state assertion failure (expected %s, current %s)\n",
1219 state_string(state
), state_string(cur_state
));
1221 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1222 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1224 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1230 /* ILK FDI PLL is always enabled */
1231 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1234 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1235 if (HAS_DDI(dev_priv
->dev
))
1238 reg
= FDI_TX_CTL(pipe
);
1239 val
= I915_READ(reg
);
1240 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1243 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1244 enum pipe pipe
, bool state
)
1250 reg
= FDI_RX_CTL(pipe
);
1251 val
= I915_READ(reg
);
1252 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1253 I915_STATE_WARN(cur_state
!= state
,
1254 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1255 state_string(state
), state_string(cur_state
));
1258 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1261 struct drm_device
*dev
= dev_priv
->dev
;
1264 enum pipe panel_pipe
= PIPE_A
;
1267 if (WARN_ON(HAS_DDI(dev
)))
1270 if (HAS_PCH_SPLIT(dev
)) {
1273 pp_reg
= PCH_PP_CONTROL
;
1274 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1276 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1277 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1278 panel_pipe
= PIPE_B
;
1279 /* XXX: else fix for eDP */
1280 } else if (IS_VALLEYVIEW(dev
)) {
1281 /* presumably write lock depends on pipe, not port select */
1282 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1285 pp_reg
= PP_CONTROL
;
1286 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1287 panel_pipe
= PIPE_B
;
1290 val
= I915_READ(pp_reg
);
1291 if (!(val
& PANEL_POWER_ON
) ||
1292 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1295 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1296 "panel assertion failure, pipe %c regs locked\n",
1300 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1301 enum pipe pipe
, bool state
)
1303 struct drm_device
*dev
= dev_priv
->dev
;
1306 if (IS_845G(dev
) || IS_I865G(dev
))
1307 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1309 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1311 I915_STATE_WARN(cur_state
!= state
,
1312 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1313 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1315 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1316 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1318 void assert_pipe(struct drm_i915_private
*dev_priv
,
1319 enum pipe pipe
, bool state
)
1324 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1327 /* if we need the pipe quirk it must be always on */
1328 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1329 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1332 if (!intel_display_power_is_enabled(dev_priv
,
1333 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1336 reg
= PIPECONF(cpu_transcoder
);
1337 val
= I915_READ(reg
);
1338 cur_state
= !!(val
& PIPECONF_ENABLE
);
1341 I915_STATE_WARN(cur_state
!= state
,
1342 "pipe %c assertion failure (expected %s, current %s)\n",
1343 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1346 static void assert_plane(struct drm_i915_private
*dev_priv
,
1347 enum plane plane
, bool state
)
1353 reg
= DSPCNTR(plane
);
1354 val
= I915_READ(reg
);
1355 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1356 I915_STATE_WARN(cur_state
!= state
,
1357 "plane %c assertion failure (expected %s, current %s)\n",
1358 plane_name(plane
), state_string(state
), state_string(cur_state
));
1361 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1362 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1364 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1367 struct drm_device
*dev
= dev_priv
->dev
;
1372 /* Primary planes are fixed to pipes on gen4+ */
1373 if (INTEL_INFO(dev
)->gen
>= 4) {
1374 reg
= DSPCNTR(pipe
);
1375 val
= I915_READ(reg
);
1376 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1377 "plane %c assertion failure, should be disabled but not\n",
1382 /* Need to check both planes against the pipe */
1383 for_each_pipe(dev_priv
, i
) {
1385 val
= I915_READ(reg
);
1386 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1387 DISPPLANE_SEL_PIPE_SHIFT
;
1388 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1389 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1390 plane_name(i
), pipe_name(pipe
));
1394 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1397 struct drm_device
*dev
= dev_priv
->dev
;
1401 if (INTEL_INFO(dev
)->gen
>= 9) {
1402 for_each_sprite(dev_priv
, pipe
, sprite
) {
1403 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1404 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1405 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1406 sprite
, pipe_name(pipe
));
1408 } else if (IS_VALLEYVIEW(dev
)) {
1409 for_each_sprite(dev_priv
, pipe
, sprite
) {
1410 reg
= SPCNTR(pipe
, sprite
);
1411 val
= I915_READ(reg
);
1412 I915_STATE_WARN(val
& SP_ENABLE
,
1413 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1414 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1416 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1418 val
= I915_READ(reg
);
1419 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1420 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1421 plane_name(pipe
), pipe_name(pipe
));
1422 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1423 reg
= DVSCNTR(pipe
);
1424 val
= I915_READ(reg
);
1425 I915_STATE_WARN(val
& DVS_ENABLE
,
1426 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1427 plane_name(pipe
), pipe_name(pipe
));
1431 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1433 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1434 drm_crtc_vblank_put(crtc
);
1437 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1442 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1444 val
= I915_READ(PCH_DREF_CONTROL
);
1445 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1446 DREF_SUPERSPREAD_SOURCE_MASK
));
1447 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1450 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1457 reg
= PCH_TRANSCONF(pipe
);
1458 val
= I915_READ(reg
);
1459 enabled
= !!(val
& TRANS_ENABLE
);
1460 I915_STATE_WARN(enabled
,
1461 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1466 enum pipe pipe
, u32 port_sel
, u32 val
)
1468 if ((val
& DP_PORT_EN
) == 0)
1471 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1472 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1473 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1474 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1476 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1477 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1480 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1486 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1487 enum pipe pipe
, u32 val
)
1489 if ((val
& SDVO_ENABLE
) == 0)
1492 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1493 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1495 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1496 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1499 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1505 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1506 enum pipe pipe
, u32 val
)
1508 if ((val
& LVDS_PORT_EN
) == 0)
1511 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1512 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1515 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1521 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1522 enum pipe pipe
, u32 val
)
1524 if ((val
& ADPA_DAC_ENABLE
) == 0)
1526 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1527 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1530 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1536 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1537 enum pipe pipe
, int reg
, u32 port_sel
)
1539 u32 val
= I915_READ(reg
);
1540 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1541 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1542 reg
, pipe_name(pipe
));
1544 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1545 && (val
& DP_PIPEB_SELECT
),
1546 "IBX PCH dp port still using transcoder B\n");
1549 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1550 enum pipe pipe
, int reg
)
1552 u32 val
= I915_READ(reg
);
1553 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1554 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1555 reg
, pipe_name(pipe
));
1557 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1558 && (val
& SDVO_PIPE_B_SELECT
),
1559 "IBX PCH hdmi port still using transcoder B\n");
1562 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1568 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1569 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1570 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1573 val
= I915_READ(reg
);
1574 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1575 "PCH VGA enabled on transcoder %c, should be disabled\n",
1579 val
= I915_READ(reg
);
1580 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1581 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1584 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1585 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1586 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1589 static void intel_init_dpio(struct drm_device
*dev
)
1591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1593 if (!IS_VALLEYVIEW(dev
))
1597 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1598 * CHV x1 PHY (DP/HDMI D)
1599 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1601 if (IS_CHERRYVIEW(dev
)) {
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1609 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1610 const struct intel_crtc_state
*pipe_config
)
1612 struct drm_device
*dev
= crtc
->base
.dev
;
1613 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1614 int reg
= DPLL(crtc
->pipe
);
1615 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1617 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1619 /* No really, not for ILK+ */
1620 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1622 /* PLL is protected by panel, make sure we can write it */
1623 if (IS_MOBILE(dev_priv
->dev
))
1624 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1626 I915_WRITE(reg
, dpll
);
1630 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1631 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1633 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1634 POSTING_READ(DPLL_MD(crtc
->pipe
));
1636 /* We do this three times for luck */
1637 I915_WRITE(reg
, dpll
);
1639 udelay(150); /* wait for warmup */
1640 I915_WRITE(reg
, dpll
);
1642 udelay(150); /* wait for warmup */
1643 I915_WRITE(reg
, dpll
);
1645 udelay(150); /* wait for warmup */
1648 static void chv_enable_pll(struct intel_crtc
*crtc
,
1649 const struct intel_crtc_state
*pipe_config
)
1651 struct drm_device
*dev
= crtc
->base
.dev
;
1652 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1653 int pipe
= crtc
->pipe
;
1654 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1657 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1659 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1661 mutex_lock(&dev_priv
->dpio_lock
);
1663 /* Enable back the 10bit clock to display controller */
1664 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1665 tmp
|= DPIO_DCLKP_EN
;
1666 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1669 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1674 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1676 /* Check PLL is locked */
1677 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1678 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1680 /* not sure when this should be written */
1681 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1682 POSTING_READ(DPLL_MD(pipe
));
1684 mutex_unlock(&dev_priv
->dpio_lock
);
1687 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1689 struct intel_crtc
*crtc
;
1692 for_each_intel_crtc(dev
, crtc
)
1693 count
+= crtc
->active
&&
1694 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1699 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1701 struct drm_device
*dev
= crtc
->base
.dev
;
1702 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1703 int reg
= DPLL(crtc
->pipe
);
1704 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1706 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1708 /* No really, not for ILK+ */
1709 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1711 /* PLL is protected by panel, make sure we can write it */
1712 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1713 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1715 /* Enable DVO 2x clock on both PLLs if necessary */
1716 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1718 * It appears to be important that we don't enable this
1719 * for the current pipe before otherwise configuring the
1720 * PLL. No idea how this should be handled if multiple
1721 * DVO outputs are enabled simultaneosly.
1723 dpll
|= DPLL_DVO_2X_MODE
;
1724 I915_WRITE(DPLL(!crtc
->pipe
),
1725 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1728 /* Wait for the clocks to stabilize. */
1732 if (INTEL_INFO(dev
)->gen
>= 4) {
1733 I915_WRITE(DPLL_MD(crtc
->pipe
),
1734 crtc
->config
->dpll_hw_state
.dpll_md
);
1736 /* The pixel multiplier can only be updated once the
1737 * DPLL is enabled and the clocks are stable.
1739 * So write it again.
1741 I915_WRITE(reg
, dpll
);
1744 /* We do this three times for luck */
1745 I915_WRITE(reg
, dpll
);
1747 udelay(150); /* wait for warmup */
1748 I915_WRITE(reg
, dpll
);
1750 udelay(150); /* wait for warmup */
1751 I915_WRITE(reg
, dpll
);
1753 udelay(150); /* wait for warmup */
1757 * i9xx_disable_pll - disable a PLL
1758 * @dev_priv: i915 private structure
1759 * @pipe: pipe PLL to disable
1761 * Disable the PLL for @pipe, making sure the pipe is off first.
1763 * Note! This is for pre-ILK only.
1765 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1767 struct drm_device
*dev
= crtc
->base
.dev
;
1768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1769 enum pipe pipe
= crtc
->pipe
;
1771 /* Disable DVO 2x clock on both PLLs if necessary */
1773 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1774 intel_num_dvo_pipes(dev
) == 1) {
1775 I915_WRITE(DPLL(PIPE_B
),
1776 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1777 I915_WRITE(DPLL(PIPE_A
),
1778 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1781 /* Don't disable pipe or pipe PLLs if needed */
1782 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1783 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1786 /* Make sure the pipe isn't still relying on us */
1787 assert_pipe_disabled(dev_priv
, pipe
);
1789 I915_WRITE(DPLL(pipe
), 0);
1790 POSTING_READ(DPLL(pipe
));
1793 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1797 /* Make sure the pipe isn't still relying on us */
1798 assert_pipe_disabled(dev_priv
, pipe
);
1801 * Leave integrated clock source and reference clock enabled for pipe B.
1802 * The latter is needed for VGA hotplug / manual detection.
1805 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1806 I915_WRITE(DPLL(pipe
), val
);
1807 POSTING_READ(DPLL(pipe
));
1811 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1813 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1816 /* Make sure the pipe isn't still relying on us */
1817 assert_pipe_disabled(dev_priv
, pipe
);
1819 /* Set PLL en = 0 */
1820 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1822 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1823 I915_WRITE(DPLL(pipe
), val
);
1824 POSTING_READ(DPLL(pipe
));
1826 mutex_lock(&dev_priv
->dpio_lock
);
1828 /* Disable 10bit clock to display controller */
1829 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1830 val
&= ~DPIO_DCLKP_EN
;
1831 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1833 /* disable left/right clock distribution */
1834 if (pipe
!= PIPE_B
) {
1835 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1836 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1837 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1839 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1840 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1841 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1844 mutex_unlock(&dev_priv
->dpio_lock
);
1847 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1848 struct intel_digital_port
*dport
)
1853 switch (dport
->port
) {
1855 port_mask
= DPLL_PORTB_READY_MASK
;
1859 port_mask
= DPLL_PORTC_READY_MASK
;
1863 port_mask
= DPLL_PORTD_READY_MASK
;
1864 dpll_reg
= DPIO_PHY_STATUS
;
1870 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1871 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1872 port_name(dport
->port
), I915_READ(dpll_reg
));
1875 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1877 struct drm_device
*dev
= crtc
->base
.dev
;
1878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1879 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1881 if (WARN_ON(pll
== NULL
))
1884 WARN_ON(!pll
->config
.crtc_mask
);
1885 if (pll
->active
== 0) {
1886 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1888 assert_shared_dpll_disabled(dev_priv
, pll
);
1890 pll
->mode_set(dev_priv
, pll
);
1895 * intel_enable_shared_dpll - enable PCH PLL
1896 * @dev_priv: i915 private structure
1897 * @pipe: pipe PLL to enable
1899 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1900 * drives the transcoder clock.
1902 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1904 struct drm_device
*dev
= crtc
->base
.dev
;
1905 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1906 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1908 if (WARN_ON(pll
== NULL
))
1911 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1914 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1915 pll
->name
, pll
->active
, pll
->on
,
1916 crtc
->base
.base
.id
);
1918 if (pll
->active
++) {
1920 assert_shared_dpll_enabled(dev_priv
, pll
);
1925 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1927 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1928 pll
->enable(dev_priv
, pll
);
1932 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1934 struct drm_device
*dev
= crtc
->base
.dev
;
1935 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1936 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1938 /* PCH only available on ILK+ */
1939 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1940 if (WARN_ON(pll
== NULL
))
1943 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1946 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1947 pll
->name
, pll
->active
, pll
->on
,
1948 crtc
->base
.base
.id
);
1950 if (WARN_ON(pll
->active
== 0)) {
1951 assert_shared_dpll_disabled(dev_priv
, pll
);
1955 assert_shared_dpll_enabled(dev_priv
, pll
);
1960 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1961 pll
->disable(dev_priv
, pll
);
1964 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1967 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1970 struct drm_device
*dev
= dev_priv
->dev
;
1971 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1972 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1973 uint32_t reg
, val
, pipeconf_val
;
1975 /* PCH only available on ILK+ */
1976 BUG_ON(!HAS_PCH_SPLIT(dev
));
1978 /* Make sure PCH DPLL is enabled */
1979 assert_shared_dpll_enabled(dev_priv
,
1980 intel_crtc_to_shared_dpll(intel_crtc
));
1982 /* FDI must be feeding us bits for PCH ports */
1983 assert_fdi_tx_enabled(dev_priv
, pipe
);
1984 assert_fdi_rx_enabled(dev_priv
, pipe
);
1986 if (HAS_PCH_CPT(dev
)) {
1987 /* Workaround: Set the timing override bit before enabling the
1988 * pch transcoder. */
1989 reg
= TRANS_CHICKEN2(pipe
);
1990 val
= I915_READ(reg
);
1991 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1992 I915_WRITE(reg
, val
);
1995 reg
= PCH_TRANSCONF(pipe
);
1996 val
= I915_READ(reg
);
1997 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1999 if (HAS_PCH_IBX(dev_priv
->dev
)) {
2001 * make the BPC in transcoder be consistent with
2002 * that in pipeconf reg.
2004 val
&= ~PIPECONF_BPC_MASK
;
2005 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
2008 val
&= ~TRANS_INTERLACE_MASK
;
2009 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
2010 if (HAS_PCH_IBX(dev_priv
->dev
) &&
2011 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
2012 val
|= TRANS_LEGACY_INTERLACED_ILK
;
2014 val
|= TRANS_INTERLACED
;
2016 val
|= TRANS_PROGRESSIVE
;
2018 I915_WRITE(reg
, val
| TRANS_ENABLE
);
2019 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2020 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
2023 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2024 enum transcoder cpu_transcoder
)
2026 u32 val
, pipeconf_val
;
2028 /* PCH only available on ILK+ */
2029 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2031 /* FDI must be feeding us bits for PCH ports */
2032 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2033 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2035 /* Workaround: set timing override bit. */
2036 val
= I915_READ(_TRANSA_CHICKEN2
);
2037 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2038 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2041 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2043 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2044 PIPECONF_INTERLACED_ILK
)
2045 val
|= TRANS_INTERLACED
;
2047 val
|= TRANS_PROGRESSIVE
;
2049 I915_WRITE(LPT_TRANSCONF
, val
);
2050 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2051 DRM_ERROR("Failed to enable PCH transcoder\n");
2054 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2057 struct drm_device
*dev
= dev_priv
->dev
;
2060 /* FDI relies on the transcoder */
2061 assert_fdi_tx_disabled(dev_priv
, pipe
);
2062 assert_fdi_rx_disabled(dev_priv
, pipe
);
2064 /* Ports must be off as well */
2065 assert_pch_ports_disabled(dev_priv
, pipe
);
2067 reg
= PCH_TRANSCONF(pipe
);
2068 val
= I915_READ(reg
);
2069 val
&= ~TRANS_ENABLE
;
2070 I915_WRITE(reg
, val
);
2071 /* wait for PCH transcoder off, transcoder state */
2072 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2073 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2075 if (!HAS_PCH_IBX(dev
)) {
2076 /* Workaround: Clear the timing override chicken bit again. */
2077 reg
= TRANS_CHICKEN2(pipe
);
2078 val
= I915_READ(reg
);
2079 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2080 I915_WRITE(reg
, val
);
2084 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2088 val
= I915_READ(LPT_TRANSCONF
);
2089 val
&= ~TRANS_ENABLE
;
2090 I915_WRITE(LPT_TRANSCONF
, val
);
2091 /* wait for PCH transcoder off, transcoder state */
2092 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2093 DRM_ERROR("Failed to disable PCH transcoder\n");
2095 /* Workaround: clear timing override bit. */
2096 val
= I915_READ(_TRANSA_CHICKEN2
);
2097 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2098 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2102 * intel_enable_pipe - enable a pipe, asserting requirements
2103 * @crtc: crtc responsible for the pipe
2105 * Enable @crtc's pipe, making sure that various hardware specific requirements
2106 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2108 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2110 struct drm_device
*dev
= crtc
->base
.dev
;
2111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2112 enum pipe pipe
= crtc
->pipe
;
2113 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2115 enum pipe pch_transcoder
;
2119 assert_planes_disabled(dev_priv
, pipe
);
2120 assert_cursor_disabled(dev_priv
, pipe
);
2121 assert_sprites_disabled(dev_priv
, pipe
);
2123 if (HAS_PCH_LPT(dev_priv
->dev
))
2124 pch_transcoder
= TRANSCODER_A
;
2126 pch_transcoder
= pipe
;
2129 * A pipe without a PLL won't actually be able to drive bits from
2130 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2133 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2134 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2135 assert_dsi_pll_enabled(dev_priv
);
2137 assert_pll_enabled(dev_priv
, pipe
);
2139 if (crtc
->config
->has_pch_encoder
) {
2140 /* if driving the PCH, we need FDI enabled */
2141 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2142 assert_fdi_tx_pll_enabled(dev_priv
,
2143 (enum pipe
) cpu_transcoder
);
2145 /* FIXME: assert CPU port conditions for SNB+ */
2148 reg
= PIPECONF(cpu_transcoder
);
2149 val
= I915_READ(reg
);
2150 if (val
& PIPECONF_ENABLE
) {
2151 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2152 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2156 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2161 * intel_disable_pipe - disable a pipe, asserting requirements
2162 * @crtc: crtc whose pipes is to be disabled
2164 * Disable the pipe of @crtc, making sure that various hardware
2165 * specific requirements are met, if applicable, e.g. plane
2166 * disabled, panel fitter off, etc.
2168 * Will wait until the pipe has shut down before returning.
2170 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2172 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2173 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2174 enum pipe pipe
= crtc
->pipe
;
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2182 assert_planes_disabled(dev_priv
, pipe
);
2183 assert_cursor_disabled(dev_priv
, pipe
);
2184 assert_sprites_disabled(dev_priv
, pipe
);
2186 reg
= PIPECONF(cpu_transcoder
);
2187 val
= I915_READ(reg
);
2188 if ((val
& PIPECONF_ENABLE
) == 0)
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2195 if (crtc
->config
->double_wide
)
2196 val
&= ~PIPECONF_DOUBLE_WIDE
;
2198 /* Don't disable pipe or pipe PLLs if needed */
2199 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2200 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2201 val
&= ~PIPECONF_ENABLE
;
2203 I915_WRITE(reg
, val
);
2204 if ((val
& PIPECONF_ENABLE
) == 0)
2205 intel_wait_for_pipe_off(crtc
);
2209 * Plane regs are double buffered, going from enabled->disabled needs a
2210 * trigger in order to latch. The display address reg provides this.
2212 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2215 struct drm_device
*dev
= dev_priv
->dev
;
2216 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2218 I915_WRITE(reg
, I915_READ(reg
));
2223 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2224 * @plane: plane to be enabled
2225 * @crtc: crtc for the plane
2227 * Enable @plane on @crtc, making sure that the pipe is running first.
2229 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2230 struct drm_crtc
*crtc
)
2232 struct drm_device
*dev
= plane
->dev
;
2233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2234 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2236 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2237 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2238 to_intel_plane_state(plane
->state
)->visible
= true;
2240 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2244 static bool need_vtd_wa(struct drm_device
*dev
)
2246 #ifdef CONFIG_INTEL_IOMMU
2247 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2254 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2255 uint64_t fb_format_modifier
)
2257 unsigned int tile_height
;
2258 uint32_t pixel_bytes
;
2260 switch (fb_format_modifier
) {
2261 case DRM_FORMAT_MOD_NONE
:
2264 case I915_FORMAT_MOD_X_TILED
:
2265 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2267 case I915_FORMAT_MOD_Y_TILED
:
2270 case I915_FORMAT_MOD_Yf_TILED
:
2271 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2272 switch (pixel_bytes
) {
2286 "128-bit pixels are not supported for display!");
2292 MISSING_CASE(fb_format_modifier
);
2301 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2302 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2304 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2305 fb_format_modifier
));
2309 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2310 const struct drm_plane_state
*plane_state
)
2312 struct intel_rotation_info
*info
= &view
->rotation_info
;
2314 *view
= i915_ggtt_view_normal
;
2319 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2322 *view
= i915_ggtt_view_rotated
;
2324 info
->height
= fb
->height
;
2325 info
->pixel_format
= fb
->pixel_format
;
2326 info
->pitch
= fb
->pitches
[0];
2327 info
->fb_modifier
= fb
->modifier
[0];
2333 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2334 struct drm_framebuffer
*fb
,
2335 const struct drm_plane_state
*plane_state
,
2336 struct intel_engine_cs
*pipelined
)
2338 struct drm_device
*dev
= fb
->dev
;
2339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2340 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2341 struct i915_ggtt_view view
;
2345 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2347 switch (fb
->modifier
[0]) {
2348 case DRM_FORMAT_MOD_NONE
:
2349 if (INTEL_INFO(dev
)->gen
>= 9)
2350 alignment
= 256 * 1024;
2351 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2352 alignment
= 128 * 1024;
2353 else if (INTEL_INFO(dev
)->gen
>= 4)
2354 alignment
= 4 * 1024;
2356 alignment
= 64 * 1024;
2358 case I915_FORMAT_MOD_X_TILED
:
2359 if (INTEL_INFO(dev
)->gen
>= 9)
2360 alignment
= 256 * 1024;
2362 /* pin() will align the object as required by fence */
2366 case I915_FORMAT_MOD_Y_TILED
:
2367 case I915_FORMAT_MOD_Yf_TILED
:
2368 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2369 "Y tiling bo slipped through, driver bug!\n"))
2371 alignment
= 1 * 1024 * 1024;
2374 MISSING_CASE(fb
->modifier
[0]);
2378 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2382 /* Note that the w/a also requires 64 PTE of padding following the
2383 * bo. We currently fill all unused PTE with the shadow page and so
2384 * we should always have valid PTE following the scanout preventing
2387 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2388 alignment
= 256 * 1024;
2391 * Global gtt pte registers are special registers which actually forward
2392 * writes to a chunk of system memory. Which means that there is no risk
2393 * that the register values disappear as soon as we call
2394 * intel_runtime_pm_put(), so it is correct to wrap only the
2395 * pin/unpin/fence and not more.
2397 intel_runtime_pm_get(dev_priv
);
2399 dev_priv
->mm
.interruptible
= false;
2400 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2403 goto err_interruptible
;
2405 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2406 * fence, whereas 965+ only requires a fence if using
2407 * framebuffer compression. For simplicity, we always install
2408 * a fence as the cost is not that onerous.
2410 ret
= i915_gem_object_get_fence(obj
);
2414 i915_gem_object_pin_fence(obj
);
2416 dev_priv
->mm
.interruptible
= true;
2417 intel_runtime_pm_put(dev_priv
);
2421 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2423 dev_priv
->mm
.interruptible
= true;
2424 intel_runtime_pm_put(dev_priv
);
2428 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2429 const struct drm_plane_state
*plane_state
)
2431 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2432 struct i915_ggtt_view view
;
2435 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2437 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2438 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2440 i915_gem_object_unpin_fence(obj
);
2441 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2444 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2445 * is assumed to be a power-of-two. */
2446 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2447 unsigned int tiling_mode
,
2451 if (tiling_mode
!= I915_TILING_NONE
) {
2452 unsigned int tile_rows
, tiles
;
2457 tiles
= *x
/ (512/cpp
);
2460 return tile_rows
* pitch
* 8 + tiles
* 4096;
2462 unsigned int offset
;
2464 offset
= *y
* pitch
+ *x
* cpp
;
2466 *x
= (offset
& 4095) / cpp
;
2467 return offset
& -4096;
2471 static int i9xx_format_to_fourcc(int format
)
2474 case DISPPLANE_8BPP
:
2475 return DRM_FORMAT_C8
;
2476 case DISPPLANE_BGRX555
:
2477 return DRM_FORMAT_XRGB1555
;
2478 case DISPPLANE_BGRX565
:
2479 return DRM_FORMAT_RGB565
;
2481 case DISPPLANE_BGRX888
:
2482 return DRM_FORMAT_XRGB8888
;
2483 case DISPPLANE_RGBX888
:
2484 return DRM_FORMAT_XBGR8888
;
2485 case DISPPLANE_BGRX101010
:
2486 return DRM_FORMAT_XRGB2101010
;
2487 case DISPPLANE_RGBX101010
:
2488 return DRM_FORMAT_XBGR2101010
;
2492 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2495 case PLANE_CTL_FORMAT_RGB_565
:
2496 return DRM_FORMAT_RGB565
;
2498 case PLANE_CTL_FORMAT_XRGB_8888
:
2501 return DRM_FORMAT_ABGR8888
;
2503 return DRM_FORMAT_XBGR8888
;
2506 return DRM_FORMAT_ARGB8888
;
2508 return DRM_FORMAT_XRGB8888
;
2510 case PLANE_CTL_FORMAT_XRGB_2101010
:
2512 return DRM_FORMAT_XBGR2101010
;
2514 return DRM_FORMAT_XRGB2101010
;
2519 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2520 struct intel_initial_plane_config
*plane_config
)
2522 struct drm_device
*dev
= crtc
->base
.dev
;
2523 struct drm_i915_gem_object
*obj
= NULL
;
2524 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2525 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2526 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2527 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2530 size_aligned
-= base_aligned
;
2532 if (plane_config
->size
== 0)
2535 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2542 obj
->tiling_mode
= plane_config
->tiling
;
2543 if (obj
->tiling_mode
== I915_TILING_X
)
2544 obj
->stride
= fb
->pitches
[0];
2546 mode_cmd
.pixel_format
= fb
->pixel_format
;
2547 mode_cmd
.width
= fb
->width
;
2548 mode_cmd
.height
= fb
->height
;
2549 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2550 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2551 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2553 mutex_lock(&dev
->struct_mutex
);
2554 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2556 DRM_DEBUG_KMS("intel fb init failed\n");
2559 mutex_unlock(&dev
->struct_mutex
);
2561 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2565 drm_gem_object_unreference(&obj
->base
);
2566 mutex_unlock(&dev
->struct_mutex
);
2570 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2572 update_state_fb(struct drm_plane
*plane
)
2574 if (plane
->fb
== plane
->state
->fb
)
2577 if (plane
->state
->fb
)
2578 drm_framebuffer_unreference(plane
->state
->fb
);
2579 plane
->state
->fb
= plane
->fb
;
2580 if (plane
->state
->fb
)
2581 drm_framebuffer_reference(plane
->state
->fb
);
2585 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2586 struct intel_initial_plane_config
*plane_config
)
2588 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2591 struct intel_crtc
*i
;
2592 struct drm_i915_gem_object
*obj
;
2593 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2594 struct drm_framebuffer
*fb
;
2596 if (!plane_config
->fb
)
2599 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2600 fb
= &plane_config
->fb
->base
;
2604 kfree(plane_config
->fb
);
2607 * Failed to alloc the obj, check to see if we should share
2608 * an fb with another CRTC instead
2610 for_each_crtc(dev
, c
) {
2611 i
= to_intel_crtc(c
);
2613 if (c
== &intel_crtc
->base
)
2619 fb
= c
->primary
->fb
;
2623 obj
= intel_fb_obj(fb
);
2624 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2625 drm_framebuffer_reference(fb
);
2633 obj
= intel_fb_obj(fb
);
2634 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2635 dev_priv
->preserve_bios_swizzle
= true;
2638 primary
->state
->crtc
= &intel_crtc
->base
;
2639 primary
->crtc
= &intel_crtc
->base
;
2640 update_state_fb(primary
);
2641 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2644 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2645 struct drm_framebuffer
*fb
,
2648 struct drm_device
*dev
= crtc
->dev
;
2649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2650 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2651 struct drm_plane
*primary
= crtc
->primary
;
2652 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2653 struct drm_i915_gem_object
*obj
;
2654 int plane
= intel_crtc
->plane
;
2655 unsigned long linear_offset
;
2657 u32 reg
= DSPCNTR(plane
);
2660 if (!visible
|| !fb
) {
2662 if (INTEL_INFO(dev
)->gen
>= 4)
2663 I915_WRITE(DSPSURF(plane
), 0);
2665 I915_WRITE(DSPADDR(plane
), 0);
2670 obj
= intel_fb_obj(fb
);
2671 if (WARN_ON(obj
== NULL
))
2674 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2676 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2678 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2680 if (INTEL_INFO(dev
)->gen
< 4) {
2681 if (intel_crtc
->pipe
== PIPE_B
)
2682 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2684 /* pipesrc and dspsize control the size that is scaled from,
2685 * which should always be the user's requested size.
2687 I915_WRITE(DSPSIZE(plane
),
2688 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2689 (intel_crtc
->config
->pipe_src_w
- 1));
2690 I915_WRITE(DSPPOS(plane
), 0);
2691 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2692 I915_WRITE(PRIMSIZE(plane
),
2693 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2694 (intel_crtc
->config
->pipe_src_w
- 1));
2695 I915_WRITE(PRIMPOS(plane
), 0);
2696 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2699 switch (fb
->pixel_format
) {
2701 dspcntr
|= DISPPLANE_8BPP
;
2703 case DRM_FORMAT_XRGB1555
:
2704 case DRM_FORMAT_ARGB1555
:
2705 dspcntr
|= DISPPLANE_BGRX555
;
2707 case DRM_FORMAT_RGB565
:
2708 dspcntr
|= DISPPLANE_BGRX565
;
2710 case DRM_FORMAT_XRGB8888
:
2711 case DRM_FORMAT_ARGB8888
:
2712 dspcntr
|= DISPPLANE_BGRX888
;
2714 case DRM_FORMAT_XBGR8888
:
2715 case DRM_FORMAT_ABGR8888
:
2716 dspcntr
|= DISPPLANE_RGBX888
;
2718 case DRM_FORMAT_XRGB2101010
:
2719 case DRM_FORMAT_ARGB2101010
:
2720 dspcntr
|= DISPPLANE_BGRX101010
;
2722 case DRM_FORMAT_XBGR2101010
:
2723 case DRM_FORMAT_ABGR2101010
:
2724 dspcntr
|= DISPPLANE_RGBX101010
;
2730 if (INTEL_INFO(dev
)->gen
>= 4 &&
2731 obj
->tiling_mode
!= I915_TILING_NONE
)
2732 dspcntr
|= DISPPLANE_TILED
;
2735 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2737 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2739 if (INTEL_INFO(dev
)->gen
>= 4) {
2740 intel_crtc
->dspaddr_offset
=
2741 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2744 linear_offset
-= intel_crtc
->dspaddr_offset
;
2746 intel_crtc
->dspaddr_offset
= linear_offset
;
2749 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2750 dspcntr
|= DISPPLANE_ROTATE_180
;
2752 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2753 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2758 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2759 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2762 I915_WRITE(reg
, dspcntr
);
2764 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2765 if (INTEL_INFO(dev
)->gen
>= 4) {
2766 I915_WRITE(DSPSURF(plane
),
2767 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2768 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2769 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2771 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2775 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2776 struct drm_framebuffer
*fb
,
2779 struct drm_device
*dev
= crtc
->dev
;
2780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2781 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2782 struct drm_plane
*primary
= crtc
->primary
;
2783 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2784 struct drm_i915_gem_object
*obj
;
2785 int plane
= intel_crtc
->plane
;
2786 unsigned long linear_offset
;
2788 u32 reg
= DSPCNTR(plane
);
2791 if (!visible
|| !fb
) {
2793 I915_WRITE(DSPSURF(plane
), 0);
2798 obj
= intel_fb_obj(fb
);
2799 if (WARN_ON(obj
== NULL
))
2802 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2804 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2806 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2808 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2809 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2811 switch (fb
->pixel_format
) {
2813 dspcntr
|= DISPPLANE_8BPP
;
2815 case DRM_FORMAT_RGB565
:
2816 dspcntr
|= DISPPLANE_BGRX565
;
2818 case DRM_FORMAT_XRGB8888
:
2819 case DRM_FORMAT_ARGB8888
:
2820 dspcntr
|= DISPPLANE_BGRX888
;
2822 case DRM_FORMAT_XBGR8888
:
2823 case DRM_FORMAT_ABGR8888
:
2824 dspcntr
|= DISPPLANE_RGBX888
;
2826 case DRM_FORMAT_XRGB2101010
:
2827 case DRM_FORMAT_ARGB2101010
:
2828 dspcntr
|= DISPPLANE_BGRX101010
;
2830 case DRM_FORMAT_XBGR2101010
:
2831 case DRM_FORMAT_ABGR2101010
:
2832 dspcntr
|= DISPPLANE_RGBX101010
;
2838 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2839 dspcntr
|= DISPPLANE_TILED
;
2841 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2842 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2844 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2845 intel_crtc
->dspaddr_offset
=
2846 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2849 linear_offset
-= intel_crtc
->dspaddr_offset
;
2850 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2851 dspcntr
|= DISPPLANE_ROTATE_180
;
2853 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2854 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2855 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2857 /* Finding the last pixel of the last line of the display
2858 data and adding to linear_offset*/
2860 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2861 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2865 I915_WRITE(reg
, dspcntr
);
2867 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2868 I915_WRITE(DSPSURF(plane
),
2869 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2870 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2871 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2873 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2874 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2879 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2880 uint32_t pixel_format
)
2882 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2885 * The stride is either expressed as a multiple of 64 bytes
2886 * chunks for linear buffers or in number of tiles for tiled
2889 switch (fb_modifier
) {
2890 case DRM_FORMAT_MOD_NONE
:
2892 case I915_FORMAT_MOD_X_TILED
:
2893 if (INTEL_INFO(dev
)->gen
== 2)
2896 case I915_FORMAT_MOD_Y_TILED
:
2897 /* No need to check for old gens and Y tiling since this is
2898 * about the display engine and those will be blocked before
2902 case I915_FORMAT_MOD_Yf_TILED
:
2903 if (bits_per_pixel
== 8)
2908 MISSING_CASE(fb_modifier
);
2913 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2914 struct drm_i915_gem_object
*obj
)
2916 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2918 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2919 view
= &i915_ggtt_view_rotated
;
2921 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2925 * This function detaches (aka. unbinds) unused scalers in hardware
2927 void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2929 struct drm_device
*dev
;
2930 struct drm_i915_private
*dev_priv
;
2931 struct intel_crtc_scaler_state
*scaler_state
;
2934 if (!intel_crtc
|| !intel_crtc
->config
)
2937 dev
= intel_crtc
->base
.dev
;
2938 dev_priv
= dev
->dev_private
;
2939 scaler_state
= &intel_crtc
->config
->scaler_state
;
2941 /* loop through and disable scalers that aren't in use */
2942 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2943 if (!scaler_state
->scalers
[i
].in_use
) {
2944 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, i
), 0);
2945 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, i
), 0);
2946 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, i
), 0);
2947 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2948 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, i
);
2953 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2955 u32 plane_ctl_format
= 0;
2956 switch (pixel_format
) {
2957 case DRM_FORMAT_RGB565
:
2958 plane_ctl_format
= PLANE_CTL_FORMAT_RGB_565
;
2960 case DRM_FORMAT_XBGR8888
:
2961 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
2963 case DRM_FORMAT_XRGB8888
:
2964 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_8888
;
2967 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2968 * to be already pre-multiplied. We need to add a knob (or a different
2969 * DRM_FORMAT) for user-space to configure that.
2971 case DRM_FORMAT_ABGR8888
:
2972 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
2973 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2975 case DRM_FORMAT_ARGB8888
:
2976 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_8888
|
2977 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2979 case DRM_FORMAT_XRGB2101010
:
2980 plane_ctl_format
= PLANE_CTL_FORMAT_XRGB_2101010
;
2982 case DRM_FORMAT_XBGR2101010
:
2983 plane_ctl_format
= PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
2985 case DRM_FORMAT_YUYV
:
2986 plane_ctl_format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
2988 case DRM_FORMAT_YVYU
:
2989 plane_ctl_format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
2991 case DRM_FORMAT_UYVY
:
2992 plane_ctl_format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
2994 case DRM_FORMAT_VYUY
:
2995 plane_ctl_format
= PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3000 return plane_ctl_format
;
3003 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
3005 u32 plane_ctl_tiling
= 0;
3006 switch (fb_modifier
) {
3007 case DRM_FORMAT_MOD_NONE
:
3009 case I915_FORMAT_MOD_X_TILED
:
3010 plane_ctl_tiling
= PLANE_CTL_TILED_X
;
3012 case I915_FORMAT_MOD_Y_TILED
:
3013 plane_ctl_tiling
= PLANE_CTL_TILED_Y
;
3015 case I915_FORMAT_MOD_Yf_TILED
:
3016 plane_ctl_tiling
= PLANE_CTL_TILED_YF
;
3019 MISSING_CASE(fb_modifier
);
3021 return plane_ctl_tiling
;
3024 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3026 u32 plane_ctl_rotation
= 0;
3028 case BIT(DRM_ROTATE_0
):
3030 case BIT(DRM_ROTATE_90
):
3031 plane_ctl_rotation
= PLANE_CTL_ROTATE_90
;
3033 case BIT(DRM_ROTATE_180
):
3034 plane_ctl_rotation
= PLANE_CTL_ROTATE_180
;
3036 case BIT(DRM_ROTATE_270
):
3037 plane_ctl_rotation
= PLANE_CTL_ROTATE_270
;
3040 MISSING_CASE(rotation
);
3043 return plane_ctl_rotation
;
3046 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3047 struct drm_framebuffer
*fb
,
3050 struct drm_device
*dev
= crtc
->dev
;
3051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3052 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3053 struct drm_plane
*plane
= crtc
->primary
;
3054 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3055 struct drm_i915_gem_object
*obj
;
3056 int pipe
= intel_crtc
->pipe
;
3057 u32 plane_ctl
, stride_div
, stride
;
3058 u32 tile_height
, plane_offset
, plane_size
;
3059 unsigned int rotation
;
3060 int x_offset
, y_offset
;
3061 unsigned long surf_addr
;
3062 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3063 struct intel_plane_state
*plane_state
;
3064 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3065 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3068 plane_state
= to_intel_plane_state(plane
->state
);
3070 if (!visible
|| !fb
) {
3071 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3072 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3073 POSTING_READ(PLANE_CTL(pipe
, 0));
3077 plane_ctl
= PLANE_CTL_ENABLE
|
3078 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3079 PLANE_CTL_PIPE_CSC_ENABLE
;
3081 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3082 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3083 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3085 rotation
= plane
->state
->rotation
;
3086 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3088 obj
= intel_fb_obj(fb
);
3089 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3091 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
);
3094 * FIXME: intel_plane_state->src, dst aren't set when transitional
3095 * update_plane helpers are called from legacy paths.
3096 * Once full atomic crtc is available, below check can be avoided.
3098 if (drm_rect_width(&plane_state
->src
)) {
3099 scaler_id
= plane_state
->scaler_id
;
3100 src_x
= plane_state
->src
.x1
>> 16;
3101 src_y
= plane_state
->src
.y1
>> 16;
3102 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3103 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3104 dst_x
= plane_state
->dst
.x1
;
3105 dst_y
= plane_state
->dst
.y1
;
3106 dst_w
= drm_rect_width(&plane_state
->dst
);
3107 dst_h
= drm_rect_height(&plane_state
->dst
);
3109 WARN_ON(x
!= src_x
|| y
!= src_y
);
3111 src_w
= intel_crtc
->config
->pipe_src_w
;
3112 src_h
= intel_crtc
->config
->pipe_src_h
;
3115 if (intel_rotation_90_or_270(rotation
)) {
3116 /* stride = Surface height in tiles */
3117 tile_height
= intel_tile_height(dev
, fb
->bits_per_pixel
,
3119 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3120 x_offset
= stride
* tile_height
- y
- src_h
;
3122 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3124 stride
= fb
->pitches
[0] / stride_div
;
3127 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3129 plane_offset
= y_offset
<< 16 | x_offset
;
3131 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3132 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3133 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3134 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3136 if (scaler_id
>= 0) {
3137 uint32_t ps_ctrl
= 0;
3139 WARN_ON(!dst_w
|| !dst_h
);
3140 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3141 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3142 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3143 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3144 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3145 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3146 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3148 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3151 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3153 POSTING_READ(PLANE_SURF(pipe
, 0));
3156 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3158 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3159 int x
, int y
, enum mode_set_atomic state
)
3161 struct drm_device
*dev
= crtc
->dev
;
3162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3164 if (dev_priv
->display
.disable_fbc
)
3165 dev_priv
->display
.disable_fbc(dev
);
3167 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3172 static void intel_complete_page_flips(struct drm_device
*dev
)
3174 struct drm_crtc
*crtc
;
3176 for_each_crtc(dev
, crtc
) {
3177 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3178 enum plane plane
= intel_crtc
->plane
;
3180 intel_prepare_page_flip(dev
, plane
);
3181 intel_finish_page_flip_plane(dev
, plane
);
3185 static void intel_update_primary_planes(struct drm_device
*dev
)
3187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3188 struct drm_crtc
*crtc
;
3190 for_each_crtc(dev
, crtc
) {
3191 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3193 drm_modeset_lock(&crtc
->mutex
, NULL
);
3195 * FIXME: Once we have proper support for primary planes (and
3196 * disabling them without disabling the entire crtc) allow again
3197 * a NULL crtc->primary->fb.
3199 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3200 dev_priv
->display
.update_primary_plane(crtc
,
3204 drm_modeset_unlock(&crtc
->mutex
);
3208 void intel_crtc_reset(struct intel_crtc
*crtc
)
3210 struct drm_i915_private
*dev_priv
= to_i915(crtc
->base
.dev
);
3215 intel_crtc_disable_planes(&crtc
->base
);
3216 dev_priv
->display
.crtc_disable(&crtc
->base
);
3217 dev_priv
->display
.crtc_enable(&crtc
->base
);
3218 intel_crtc_enable_planes(&crtc
->base
);
3221 void intel_prepare_reset(struct drm_device
*dev
)
3223 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3224 struct intel_crtc
*crtc
;
3226 /* no reset support for gen2 */
3230 /* reset doesn't touch the display */
3231 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3234 drm_modeset_lock_all(dev
);
3237 * Disabling the crtcs gracefully seems nicer. Also the
3238 * g33 docs say we should at least disable all the planes.
3240 for_each_intel_crtc(dev
, crtc
) {
3244 intel_crtc_disable_planes(&crtc
->base
);
3245 dev_priv
->display
.crtc_disable(&crtc
->base
);
3249 void intel_finish_reset(struct drm_device
*dev
)
3251 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3254 * Flips in the rings will be nuked by the reset,
3255 * so complete all pending flips so that user space
3256 * will get its events and not get stuck.
3258 intel_complete_page_flips(dev
);
3260 /* no reset support for gen2 */
3264 /* reset doesn't touch the display */
3265 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3267 * Flips in the rings have been nuked by the reset,
3268 * so update the base address of all primary
3269 * planes to the the last fb to make sure we're
3270 * showing the correct fb after a reset.
3272 intel_update_primary_planes(dev
);
3277 * The display has been reset as well,
3278 * so need a full re-initialization.
3280 intel_runtime_pm_disable_interrupts(dev_priv
);
3281 intel_runtime_pm_enable_interrupts(dev_priv
);
3283 intel_modeset_init_hw(dev
);
3285 spin_lock_irq(&dev_priv
->irq_lock
);
3286 if (dev_priv
->display
.hpd_irq_setup
)
3287 dev_priv
->display
.hpd_irq_setup(dev
);
3288 spin_unlock_irq(&dev_priv
->irq_lock
);
3290 intel_modeset_setup_hw_state(dev
, true);
3292 intel_hpd_init(dev_priv
);
3294 drm_modeset_unlock_all(dev
);
3298 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3300 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3301 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3302 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3305 /* Big Hammer, we also need to ensure that any pending
3306 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3307 * current scanout is retired before unpinning the old
3310 * This should only fail upon a hung GPU, in which case we
3311 * can safely continue.
3313 dev_priv
->mm
.interruptible
= false;
3314 ret
= i915_gem_object_finish_gpu(obj
);
3315 dev_priv
->mm
.interruptible
= was_interruptible
;
3320 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3322 struct drm_device
*dev
= crtc
->dev
;
3323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3324 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3327 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3328 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3331 spin_lock_irq(&dev
->event_lock
);
3332 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3333 spin_unlock_irq(&dev
->event_lock
);
3338 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3340 struct drm_device
*dev
= crtc
->base
.dev
;
3341 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3342 const struct drm_display_mode
*adjusted_mode
;
3348 * Update pipe size and adjust fitter if needed: the reason for this is
3349 * that in compute_mode_changes we check the native mode (not the pfit
3350 * mode) to see if we can flip rather than do a full mode set. In the
3351 * fastboot case, we'll flip, but if we don't update the pipesrc and
3352 * pfit state, we'll end up with a big fb scanned out into the wrong
3355 * To fix this properly, we need to hoist the checks up into
3356 * compute_mode_changes (or above), check the actual pfit state and
3357 * whether the platform allows pfit disable with pipe active, and only
3358 * then update the pipesrc and pfit state, even on the flip path.
3361 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3363 I915_WRITE(PIPESRC(crtc
->pipe
),
3364 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3365 (adjusted_mode
->crtc_vdisplay
- 1));
3366 if (!crtc
->config
->pch_pfit
.enabled
&&
3367 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3368 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3369 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3370 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3371 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3373 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3374 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3377 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3379 struct drm_device
*dev
= crtc
->dev
;
3380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3382 int pipe
= intel_crtc
->pipe
;
3385 /* enable normal train */
3386 reg
= FDI_TX_CTL(pipe
);
3387 temp
= I915_READ(reg
);
3388 if (IS_IVYBRIDGE(dev
)) {
3389 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3390 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3392 temp
&= ~FDI_LINK_TRAIN_NONE
;
3393 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3395 I915_WRITE(reg
, temp
);
3397 reg
= FDI_RX_CTL(pipe
);
3398 temp
= I915_READ(reg
);
3399 if (HAS_PCH_CPT(dev
)) {
3400 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3401 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3403 temp
&= ~FDI_LINK_TRAIN_NONE
;
3404 temp
|= FDI_LINK_TRAIN_NONE
;
3406 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3408 /* wait one idle pattern time */
3412 /* IVB wants error correction enabled */
3413 if (IS_IVYBRIDGE(dev
))
3414 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3415 FDI_FE_ERRC_ENABLE
);
3418 /* The FDI link training functions for ILK/Ibexpeak. */
3419 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3421 struct drm_device
*dev
= crtc
->dev
;
3422 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3423 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3424 int pipe
= intel_crtc
->pipe
;
3425 u32 reg
, temp
, tries
;
3427 /* FDI needs bits from pipe first */
3428 assert_pipe_enabled(dev_priv
, pipe
);
3430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3432 reg
= FDI_RX_IMR(pipe
);
3433 temp
= I915_READ(reg
);
3434 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3435 temp
&= ~FDI_RX_BIT_LOCK
;
3436 I915_WRITE(reg
, temp
);
3440 /* enable CPU FDI TX and PCH FDI RX */
3441 reg
= FDI_TX_CTL(pipe
);
3442 temp
= I915_READ(reg
);
3443 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3444 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3445 temp
&= ~FDI_LINK_TRAIN_NONE
;
3446 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3447 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3449 reg
= FDI_RX_CTL(pipe
);
3450 temp
= I915_READ(reg
);
3451 temp
&= ~FDI_LINK_TRAIN_NONE
;
3452 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3453 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3458 /* Ironlake workaround, enable clock pointer after FDI enable*/
3459 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3460 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3461 FDI_RX_PHASE_SYNC_POINTER_EN
);
3463 reg
= FDI_RX_IIR(pipe
);
3464 for (tries
= 0; tries
< 5; tries
++) {
3465 temp
= I915_READ(reg
);
3466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3468 if ((temp
& FDI_RX_BIT_LOCK
)) {
3469 DRM_DEBUG_KMS("FDI train 1 done.\n");
3470 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3475 DRM_ERROR("FDI train 1 fail!\n");
3478 reg
= FDI_TX_CTL(pipe
);
3479 temp
= I915_READ(reg
);
3480 temp
&= ~FDI_LINK_TRAIN_NONE
;
3481 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3482 I915_WRITE(reg
, temp
);
3484 reg
= FDI_RX_CTL(pipe
);
3485 temp
= I915_READ(reg
);
3486 temp
&= ~FDI_LINK_TRAIN_NONE
;
3487 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3488 I915_WRITE(reg
, temp
);
3493 reg
= FDI_RX_IIR(pipe
);
3494 for (tries
= 0; tries
< 5; tries
++) {
3495 temp
= I915_READ(reg
);
3496 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3498 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3499 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3500 DRM_DEBUG_KMS("FDI train 2 done.\n");
3505 DRM_ERROR("FDI train 2 fail!\n");
3507 DRM_DEBUG_KMS("FDI train done\n");
3511 static const int snb_b_fdi_train_param
[] = {
3512 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3513 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3514 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3515 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3518 /* The FDI link training functions for SNB/Cougarpoint. */
3519 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3521 struct drm_device
*dev
= crtc
->dev
;
3522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3523 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3524 int pipe
= intel_crtc
->pipe
;
3525 u32 reg
, temp
, i
, retry
;
3527 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3529 reg
= FDI_RX_IMR(pipe
);
3530 temp
= I915_READ(reg
);
3531 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3532 temp
&= ~FDI_RX_BIT_LOCK
;
3533 I915_WRITE(reg
, temp
);
3538 /* enable CPU FDI TX and PCH FDI RX */
3539 reg
= FDI_TX_CTL(pipe
);
3540 temp
= I915_READ(reg
);
3541 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3542 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3543 temp
&= ~FDI_LINK_TRAIN_NONE
;
3544 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3545 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3547 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3548 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3550 I915_WRITE(FDI_RX_MISC(pipe
),
3551 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3553 reg
= FDI_RX_CTL(pipe
);
3554 temp
= I915_READ(reg
);
3555 if (HAS_PCH_CPT(dev
)) {
3556 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3557 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3559 temp
&= ~FDI_LINK_TRAIN_NONE
;
3560 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3562 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3567 for (i
= 0; i
< 4; i
++) {
3568 reg
= FDI_TX_CTL(pipe
);
3569 temp
= I915_READ(reg
);
3570 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3571 temp
|= snb_b_fdi_train_param
[i
];
3572 I915_WRITE(reg
, temp
);
3577 for (retry
= 0; retry
< 5; retry
++) {
3578 reg
= FDI_RX_IIR(pipe
);
3579 temp
= I915_READ(reg
);
3580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3581 if (temp
& FDI_RX_BIT_LOCK
) {
3582 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3583 DRM_DEBUG_KMS("FDI train 1 done.\n");
3592 DRM_ERROR("FDI train 1 fail!\n");
3595 reg
= FDI_TX_CTL(pipe
);
3596 temp
= I915_READ(reg
);
3597 temp
&= ~FDI_LINK_TRAIN_NONE
;
3598 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3600 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3602 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3604 I915_WRITE(reg
, temp
);
3606 reg
= FDI_RX_CTL(pipe
);
3607 temp
= I915_READ(reg
);
3608 if (HAS_PCH_CPT(dev
)) {
3609 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3610 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3612 temp
&= ~FDI_LINK_TRAIN_NONE
;
3613 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3615 I915_WRITE(reg
, temp
);
3620 for (i
= 0; i
< 4; i
++) {
3621 reg
= FDI_TX_CTL(pipe
);
3622 temp
= I915_READ(reg
);
3623 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3624 temp
|= snb_b_fdi_train_param
[i
];
3625 I915_WRITE(reg
, temp
);
3630 for (retry
= 0; retry
< 5; retry
++) {
3631 reg
= FDI_RX_IIR(pipe
);
3632 temp
= I915_READ(reg
);
3633 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3634 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3635 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3636 DRM_DEBUG_KMS("FDI train 2 done.\n");
3645 DRM_ERROR("FDI train 2 fail!\n");
3647 DRM_DEBUG_KMS("FDI train done.\n");
3650 /* Manual link training for Ivy Bridge A0 parts */
3651 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3653 struct drm_device
*dev
= crtc
->dev
;
3654 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3656 int pipe
= intel_crtc
->pipe
;
3657 u32 reg
, temp
, i
, j
;
3659 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3661 reg
= FDI_RX_IMR(pipe
);
3662 temp
= I915_READ(reg
);
3663 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3664 temp
&= ~FDI_RX_BIT_LOCK
;
3665 I915_WRITE(reg
, temp
);
3670 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3671 I915_READ(FDI_RX_IIR(pipe
)));
3673 /* Try each vswing and preemphasis setting twice before moving on */
3674 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3675 /* disable first in case we need to retry */
3676 reg
= FDI_TX_CTL(pipe
);
3677 temp
= I915_READ(reg
);
3678 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3679 temp
&= ~FDI_TX_ENABLE
;
3680 I915_WRITE(reg
, temp
);
3682 reg
= FDI_RX_CTL(pipe
);
3683 temp
= I915_READ(reg
);
3684 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3685 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3686 temp
&= ~FDI_RX_ENABLE
;
3687 I915_WRITE(reg
, temp
);
3689 /* enable CPU FDI TX and PCH FDI RX */
3690 reg
= FDI_TX_CTL(pipe
);
3691 temp
= I915_READ(reg
);
3692 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3693 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3694 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3695 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3696 temp
|= snb_b_fdi_train_param
[j
/2];
3697 temp
|= FDI_COMPOSITE_SYNC
;
3698 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3700 I915_WRITE(FDI_RX_MISC(pipe
),
3701 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3703 reg
= FDI_RX_CTL(pipe
);
3704 temp
= I915_READ(reg
);
3705 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3706 temp
|= FDI_COMPOSITE_SYNC
;
3707 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3710 udelay(1); /* should be 0.5us */
3712 for (i
= 0; i
< 4; i
++) {
3713 reg
= FDI_RX_IIR(pipe
);
3714 temp
= I915_READ(reg
);
3715 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3717 if (temp
& FDI_RX_BIT_LOCK
||
3718 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3719 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3720 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3724 udelay(1); /* should be 0.5us */
3727 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3732 reg
= FDI_TX_CTL(pipe
);
3733 temp
= I915_READ(reg
);
3734 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3735 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3736 I915_WRITE(reg
, temp
);
3738 reg
= FDI_RX_CTL(pipe
);
3739 temp
= I915_READ(reg
);
3740 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3741 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3742 I915_WRITE(reg
, temp
);
3745 udelay(2); /* should be 1.5us */
3747 for (i
= 0; i
< 4; i
++) {
3748 reg
= FDI_RX_IIR(pipe
);
3749 temp
= I915_READ(reg
);
3750 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3752 if (temp
& FDI_RX_SYMBOL_LOCK
||
3753 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3754 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3755 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3759 udelay(2); /* should be 1.5us */
3762 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3766 DRM_DEBUG_KMS("FDI train done.\n");
3769 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3771 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3772 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3773 int pipe
= intel_crtc
->pipe
;
3777 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3778 reg
= FDI_RX_CTL(pipe
);
3779 temp
= I915_READ(reg
);
3780 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3781 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3782 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3783 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3788 /* Switch from Rawclk to PCDclk */
3789 temp
= I915_READ(reg
);
3790 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3795 /* Enable CPU FDI TX PLL, always on for Ironlake */
3796 reg
= FDI_TX_CTL(pipe
);
3797 temp
= I915_READ(reg
);
3798 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3799 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3806 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3808 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3810 int pipe
= intel_crtc
->pipe
;
3813 /* Switch from PCDclk to Rawclk */
3814 reg
= FDI_RX_CTL(pipe
);
3815 temp
= I915_READ(reg
);
3816 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3818 /* Disable CPU FDI TX PLL */
3819 reg
= FDI_TX_CTL(pipe
);
3820 temp
= I915_READ(reg
);
3821 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3826 reg
= FDI_RX_CTL(pipe
);
3827 temp
= I915_READ(reg
);
3828 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3830 /* Wait for the clocks to turn off. */
3835 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3837 struct drm_device
*dev
= crtc
->dev
;
3838 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3839 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3840 int pipe
= intel_crtc
->pipe
;
3843 /* disable CPU FDI tx and PCH FDI rx */
3844 reg
= FDI_TX_CTL(pipe
);
3845 temp
= I915_READ(reg
);
3846 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3849 reg
= FDI_RX_CTL(pipe
);
3850 temp
= I915_READ(reg
);
3851 temp
&= ~(0x7 << 16);
3852 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3853 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3858 /* Ironlake workaround, disable clock pointer after downing FDI */
3859 if (HAS_PCH_IBX(dev
))
3860 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3862 /* still set train pattern 1 */
3863 reg
= FDI_TX_CTL(pipe
);
3864 temp
= I915_READ(reg
);
3865 temp
&= ~FDI_LINK_TRAIN_NONE
;
3866 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3867 I915_WRITE(reg
, temp
);
3869 reg
= FDI_RX_CTL(pipe
);
3870 temp
= I915_READ(reg
);
3871 if (HAS_PCH_CPT(dev
)) {
3872 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3873 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3875 temp
&= ~FDI_LINK_TRAIN_NONE
;
3876 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3878 /* BPC in FDI rx is consistent with that in PIPECONF */
3879 temp
&= ~(0x07 << 16);
3880 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3881 I915_WRITE(reg
, temp
);
3887 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3889 struct intel_crtc
*crtc
;
3891 /* Note that we don't need to be called with mode_config.lock here
3892 * as our list of CRTC objects is static for the lifetime of the
3893 * device and so cannot disappear as we iterate. Similarly, we can
3894 * happily treat the predicates as racy, atomic checks as userspace
3895 * cannot claim and pin a new fb without at least acquring the
3896 * struct_mutex and so serialising with us.
3898 for_each_intel_crtc(dev
, crtc
) {
3899 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3902 if (crtc
->unpin_work
)
3903 intel_wait_for_vblank(dev
, crtc
->pipe
);
3911 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3913 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3914 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3916 /* ensure that the unpin work is consistent wrt ->pending. */
3918 intel_crtc
->unpin_work
= NULL
;
3921 drm_send_vblank_event(intel_crtc
->base
.dev
,
3925 drm_crtc_vblank_put(&intel_crtc
->base
);
3927 wake_up_all(&dev_priv
->pending_flip_queue
);
3928 queue_work(dev_priv
->wq
, &work
->work
);
3930 trace_i915_flip_complete(intel_crtc
->plane
,
3931 work
->pending_flip_obj
);
3934 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3936 struct drm_device
*dev
= crtc
->dev
;
3937 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3939 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3940 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3941 !intel_crtc_has_pending_flip(crtc
),
3943 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3945 spin_lock_irq(&dev
->event_lock
);
3946 if (intel_crtc
->unpin_work
) {
3947 WARN_ONCE(1, "Removing stuck page flip\n");
3948 page_flip_completed(intel_crtc
);
3950 spin_unlock_irq(&dev
->event_lock
);
3953 if (crtc
->primary
->fb
) {
3954 mutex_lock(&dev
->struct_mutex
);
3955 intel_finish_fb(crtc
->primary
->fb
);
3956 mutex_unlock(&dev
->struct_mutex
);
3960 /* Program iCLKIP clock to the desired frequency */
3961 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3963 struct drm_device
*dev
= crtc
->dev
;
3964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3965 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3966 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3969 mutex_lock(&dev_priv
->dpio_lock
);
3971 /* It is necessary to ungate the pixclk gate prior to programming
3972 * the divisors, and gate it back when it is done.
3974 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3976 /* Disable SSCCTL */
3977 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3978 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3982 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3983 if (clock
== 20000) {
3988 /* The iCLK virtual clock root frequency is in MHz,
3989 * but the adjusted_mode->crtc_clock in in KHz. To get the
3990 * divisors, it is necessary to divide one by another, so we
3991 * convert the virtual clock precision to KHz here for higher
3994 u32 iclk_virtual_root_freq
= 172800 * 1000;
3995 u32 iclk_pi_range
= 64;
3996 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3998 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3999 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
4000 pi_value
= desired_divisor
% iclk_pi_range
;
4003 divsel
= msb_divisor_value
- 2;
4004 phaseinc
= pi_value
;
4007 /* This should not happen with any sane values */
4008 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4009 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4010 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4011 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4013 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4020 /* Program SSCDIVINTPHASE6 */
4021 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4022 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4023 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4024 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4025 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4026 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4027 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4028 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4030 /* Program SSCAUXDIV */
4031 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4032 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4033 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4034 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4036 /* Enable modulator and associated divider */
4037 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4038 temp
&= ~SBI_SSCCTL_DISABLE
;
4039 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4041 /* Wait for initialization time */
4044 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4046 mutex_unlock(&dev_priv
->dpio_lock
);
4049 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4050 enum pipe pch_transcoder
)
4052 struct drm_device
*dev
= crtc
->base
.dev
;
4053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4054 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4056 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4057 I915_READ(HTOTAL(cpu_transcoder
)));
4058 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4059 I915_READ(HBLANK(cpu_transcoder
)));
4060 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4061 I915_READ(HSYNC(cpu_transcoder
)));
4063 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4064 I915_READ(VTOTAL(cpu_transcoder
)));
4065 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4066 I915_READ(VBLANK(cpu_transcoder
)));
4067 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4068 I915_READ(VSYNC(cpu_transcoder
)));
4069 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4070 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4073 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4075 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4078 temp
= I915_READ(SOUTH_CHICKEN1
);
4079 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4082 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4083 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4085 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4087 temp
|= FDI_BC_BIFURCATION_SELECT
;
4089 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4090 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4091 POSTING_READ(SOUTH_CHICKEN1
);
4094 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4096 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4098 switch (intel_crtc
->pipe
) {
4102 if (intel_crtc
->config
->fdi_lanes
> 2)
4103 cpt_set_fdi_bc_bifurcation(dev
, false);
4105 cpt_set_fdi_bc_bifurcation(dev
, true);
4109 cpt_set_fdi_bc_bifurcation(dev
, true);
4118 * Enable PCH resources required for PCH ports:
4120 * - FDI training & RX/TX
4121 * - update transcoder timings
4122 * - DP transcoding bits
4125 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4127 struct drm_device
*dev
= crtc
->dev
;
4128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4129 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4130 int pipe
= intel_crtc
->pipe
;
4133 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4135 if (IS_IVYBRIDGE(dev
))
4136 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4138 /* Write the TU size bits before fdi link training, so that error
4139 * detection works. */
4140 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4141 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4143 /* For PCH output, training FDI link */
4144 dev_priv
->display
.fdi_link_train(crtc
);
4146 /* We need to program the right clock selection before writing the pixel
4147 * mutliplier into the DPLL. */
4148 if (HAS_PCH_CPT(dev
)) {
4151 temp
= I915_READ(PCH_DPLL_SEL
);
4152 temp
|= TRANS_DPLL_ENABLE(pipe
);
4153 sel
= TRANS_DPLLB_SEL(pipe
);
4154 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4158 I915_WRITE(PCH_DPLL_SEL
, temp
);
4161 /* XXX: pch pll's can be enabled any time before we enable the PCH
4162 * transcoder, and we actually should do this to not upset any PCH
4163 * transcoder that already use the clock when we share it.
4165 * Note that enable_shared_dpll tries to do the right thing, but
4166 * get_shared_dpll unconditionally resets the pll - we need that to have
4167 * the right LVDS enable sequence. */
4168 intel_enable_shared_dpll(intel_crtc
);
4170 /* set transcoder timing, panel must allow it */
4171 assert_panel_unlocked(dev_priv
, pipe
);
4172 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4174 intel_fdi_normal_train(crtc
);
4176 /* For PCH DP, enable TRANS_DP_CTL */
4177 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4178 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4179 reg
= TRANS_DP_CTL(pipe
);
4180 temp
= I915_READ(reg
);
4181 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4182 TRANS_DP_SYNC_MASK
|
4184 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
4185 TRANS_DP_ENH_FRAMING
);
4186 temp
|= bpc
<< 9; /* same format but at 11:9 */
4188 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4189 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4190 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4191 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4193 switch (intel_trans_dp_port_sel(crtc
)) {
4195 temp
|= TRANS_DP_PORT_SEL_B
;
4198 temp
|= TRANS_DP_PORT_SEL_C
;
4201 temp
|= TRANS_DP_PORT_SEL_D
;
4207 I915_WRITE(reg
, temp
);
4210 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4213 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4215 struct drm_device
*dev
= crtc
->dev
;
4216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4218 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4220 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4222 lpt_program_iclkip(crtc
);
4224 /* Set transcoder timing. */
4225 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4227 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4230 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
4232 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4237 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4238 WARN(1, "bad %s crtc mask\n", pll
->name
);
4242 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4243 if (pll
->config
.crtc_mask
== 0) {
4245 WARN_ON(pll
->active
);
4248 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4251 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4252 struct intel_crtc_state
*crtc_state
)
4254 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4255 struct intel_shared_dpll
*pll
;
4256 enum intel_dpll_id i
;
4258 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4259 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4260 i
= (enum intel_dpll_id
) crtc
->pipe
;
4261 pll
= &dev_priv
->shared_dplls
[i
];
4263 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4264 crtc
->base
.base
.id
, pll
->name
);
4266 WARN_ON(pll
->new_config
->crtc_mask
);
4271 if (IS_BROXTON(dev_priv
->dev
)) {
4272 /* PLL is attached to port in bxt */
4273 struct intel_encoder
*encoder
;
4274 struct intel_digital_port
*intel_dig_port
;
4276 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4277 if (WARN_ON(!encoder
))
4280 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4281 /* 1:1 mapping between ports and PLLs */
4282 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4283 pll
= &dev_priv
->shared_dplls
[i
];
4284 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4285 crtc
->base
.base
.id
, pll
->name
);
4286 WARN_ON(pll
->new_config
->crtc_mask
);
4291 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4292 pll
= &dev_priv
->shared_dplls
[i
];
4294 /* Only want to check enabled timings first */
4295 if (pll
->new_config
->crtc_mask
== 0)
4298 if (memcmp(&crtc_state
->dpll_hw_state
,
4299 &pll
->new_config
->hw_state
,
4300 sizeof(pll
->new_config
->hw_state
)) == 0) {
4301 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4302 crtc
->base
.base
.id
, pll
->name
,
4303 pll
->new_config
->crtc_mask
,
4309 /* Ok no matching timings, maybe there's a free one? */
4310 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4311 pll
= &dev_priv
->shared_dplls
[i
];
4312 if (pll
->new_config
->crtc_mask
== 0) {
4313 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4314 crtc
->base
.base
.id
, pll
->name
);
4322 if (pll
->new_config
->crtc_mask
== 0)
4323 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4325 crtc_state
->shared_dpll
= i
;
4326 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4327 pipe_name(crtc
->pipe
));
4329 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4335 * intel_shared_dpll_start_config - start a new PLL staged config
4336 * @dev_priv: DRM device
4337 * @clear_pipes: mask of pipes that will have their PLLs freed
4339 * Starts a new PLL staged config, copying the current config but
4340 * releasing the references of pipes specified in clear_pipes.
4342 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4343 unsigned clear_pipes
)
4345 struct intel_shared_dpll
*pll
;
4346 enum intel_dpll_id i
;
4348 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4349 pll
= &dev_priv
->shared_dplls
[i
];
4351 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4353 if (!pll
->new_config
)
4356 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4363 pll
= &dev_priv
->shared_dplls
[i
];
4364 kfree(pll
->new_config
);
4365 pll
->new_config
= NULL
;
4371 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4373 struct intel_shared_dpll
*pll
;
4374 enum intel_dpll_id i
;
4376 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4377 pll
= &dev_priv
->shared_dplls
[i
];
4379 WARN_ON(pll
->new_config
== &pll
->config
);
4381 pll
->config
= *pll
->new_config
;
4382 kfree(pll
->new_config
);
4383 pll
->new_config
= NULL
;
4387 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4389 struct intel_shared_dpll
*pll
;
4390 enum intel_dpll_id i
;
4392 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4393 pll
= &dev_priv
->shared_dplls
[i
];
4395 WARN_ON(pll
->new_config
== &pll
->config
);
4397 kfree(pll
->new_config
);
4398 pll
->new_config
= NULL
;
4402 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4404 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4405 int dslreg
= PIPEDSL(pipe
);
4408 temp
= I915_READ(dslreg
);
4410 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4411 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4412 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4417 * skl_update_scaler_users - Stages update to crtc's scaler state
4419 * @crtc_state: crtc_state
4420 * @plane: plane (NULL indicates crtc is requesting update)
4421 * @plane_state: plane's state
4422 * @force_detach: request unconditional detachment of scaler
4424 * This function updates scaler state for requested plane or crtc.
4425 * To request scaler usage update for a plane, caller shall pass plane pointer.
4426 * To request scaler usage update for crtc, caller shall pass plane pointer
4430 * 0 - scaler_usage updated successfully
4431 * error - requested scaling cannot be supported or other error condition
4434 skl_update_scaler_users(
4435 struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
,
4436 struct intel_plane
*intel_plane
, struct intel_plane_state
*plane_state
,
4441 int src_w
, src_h
, dst_w
, dst_h
;
4443 struct drm_framebuffer
*fb
;
4444 struct intel_crtc_scaler_state
*scaler_state
;
4445 unsigned int rotation
;
4447 if (!intel_crtc
|| !crtc_state
)
4450 scaler_state
= &crtc_state
->scaler_state
;
4452 idx
= intel_plane
? drm_plane_index(&intel_plane
->base
) : SKL_CRTC_INDEX
;
4453 fb
= intel_plane
? plane_state
->base
.fb
: NULL
;
4456 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
4457 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
4458 dst_w
= drm_rect_width(&plane_state
->dst
);
4459 dst_h
= drm_rect_height(&plane_state
->dst
);
4460 scaler_id
= &plane_state
->scaler_id
;
4461 rotation
= plane_state
->base
.rotation
;
4463 struct drm_display_mode
*adjusted_mode
=
4464 &crtc_state
->base
.adjusted_mode
;
4465 src_w
= crtc_state
->pipe_src_w
;
4466 src_h
= crtc_state
->pipe_src_h
;
4467 dst_w
= adjusted_mode
->hdisplay
;
4468 dst_h
= adjusted_mode
->vdisplay
;
4469 scaler_id
= &scaler_state
->scaler_id
;
4470 rotation
= DRM_ROTATE_0
;
4473 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4474 (src_h
!= dst_w
|| src_w
!= dst_h
):
4475 (src_w
!= dst_w
|| src_h
!= dst_h
);
4478 * if plane is being disabled or scaler is no more required or force detach
4479 * - free scaler binded to this plane/crtc
4480 * - in order to do this, update crtc->scaler_usage
4482 * Here scaler state in crtc_state is set free so that
4483 * scaler can be assigned to other user. Actual register
4484 * update to free the scaler is done in plane/panel-fit programming.
4485 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4487 if (force_detach
|| !need_scaling
|| (intel_plane
&&
4488 (!fb
|| !plane_state
->visible
))) {
4489 if (*scaler_id
>= 0) {
4490 scaler_state
->scaler_users
&= ~(1 << idx
);
4491 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4493 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4494 "crtc_state = %p scaler_users = 0x%x\n",
4495 intel_crtc
->pipe
, *scaler_id
, intel_plane
? "PLANE" : "CRTC",
4496 intel_plane
? intel_plane
->base
.base
.id
:
4497 intel_crtc
->base
.base
.id
, crtc_state
,
4498 scaler_state
->scaler_users
);
4505 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4506 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4508 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4509 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4510 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4511 "size is out of scaler range\n",
4512 intel_plane
? "PLANE" : "CRTC",
4513 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4514 intel_crtc
->pipe
, idx
, src_w
, src_h
, dst_w
, dst_h
);
4518 /* check colorkey */
4519 if (intel_plane
&& intel_plane
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4520 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4521 intel_plane
->base
.base
.id
);
4525 /* Check src format */
4527 switch (fb
->pixel_format
) {
4528 case DRM_FORMAT_RGB565
:
4529 case DRM_FORMAT_XBGR8888
:
4530 case DRM_FORMAT_XRGB8888
:
4531 case DRM_FORMAT_ABGR8888
:
4532 case DRM_FORMAT_ARGB8888
:
4533 case DRM_FORMAT_XRGB2101010
:
4534 case DRM_FORMAT_ARGB2101010
:
4535 case DRM_FORMAT_XBGR2101010
:
4536 case DRM_FORMAT_ABGR2101010
:
4537 case DRM_FORMAT_YUYV
:
4538 case DRM_FORMAT_YVYU
:
4539 case DRM_FORMAT_UYVY
:
4540 case DRM_FORMAT_VYUY
:
4543 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4544 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4549 /* mark this plane as a scaler user in crtc_state */
4550 scaler_state
->scaler_users
|= (1 << idx
);
4551 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4552 "crtc_state = %p scaler_users = 0x%x\n",
4553 intel_plane
? "PLANE" : "CRTC",
4554 intel_plane
? intel_plane
->base
.base
.id
: intel_crtc
->base
.base
.id
,
4555 src_w
, src_h
, dst_w
, dst_h
, crtc_state
, scaler_state
->scaler_users
);
4559 static void skylake_pfit_update(struct intel_crtc
*crtc
, int enable
)
4561 struct drm_device
*dev
= crtc
->base
.dev
;
4562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4563 int pipe
= crtc
->pipe
;
4564 struct intel_crtc_scaler_state
*scaler_state
=
4565 &crtc
->config
->scaler_state
;
4567 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4569 /* To update pfit, first update scaler state */
4570 skl_update_scaler_users(crtc
, crtc
->config
, NULL
, NULL
, !enable
);
4571 intel_atomic_setup_scalers(crtc
->base
.dev
, crtc
, crtc
->config
);
4572 skl_detach_scalers(crtc
);
4576 if (crtc
->config
->pch_pfit
.enabled
) {
4579 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4580 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4584 id
= scaler_state
->scaler_id
;
4585 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4586 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4587 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4588 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4590 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4594 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4596 struct drm_device
*dev
= crtc
->base
.dev
;
4597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4598 int pipe
= crtc
->pipe
;
4600 if (crtc
->config
->pch_pfit
.enabled
) {
4601 /* Force use of hard-coded filter coefficients
4602 * as some pre-programmed values are broken,
4605 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4606 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4607 PF_PIPE_SEL_IVB(pipe
));
4609 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4610 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4611 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4615 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4617 struct drm_device
*dev
= crtc
->dev
;
4618 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4619 struct drm_plane
*plane
;
4620 struct intel_plane
*intel_plane
;
4622 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4623 intel_plane
= to_intel_plane(plane
);
4624 if (intel_plane
->pipe
== pipe
)
4625 intel_plane_restore(&intel_plane
->base
);
4629 void hsw_enable_ips(struct intel_crtc
*crtc
)
4631 struct drm_device
*dev
= crtc
->base
.dev
;
4632 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4634 if (!crtc
->config
->ips_enabled
)
4637 /* We can only enable IPS after we enable a plane and wait for a vblank */
4638 intel_wait_for_vblank(dev
, crtc
->pipe
);
4640 assert_plane_enabled(dev_priv
, crtc
->plane
);
4641 if (IS_BROADWELL(dev
)) {
4642 mutex_lock(&dev_priv
->rps
.hw_lock
);
4643 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4644 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4645 /* Quoting Art Runyan: "its not safe to expect any particular
4646 * value in IPS_CTL bit 31 after enabling IPS through the
4647 * mailbox." Moreover, the mailbox may return a bogus state,
4648 * so we need to just enable it and continue on.
4651 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4652 /* The bit only becomes 1 in the next vblank, so this wait here
4653 * is essentially intel_wait_for_vblank. If we don't have this
4654 * and don't wait for vblanks until the end of crtc_enable, then
4655 * the HW state readout code will complain that the expected
4656 * IPS_CTL value is not the one we read. */
4657 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4658 DRM_ERROR("Timed out waiting for IPS enable\n");
4662 void hsw_disable_ips(struct intel_crtc
*crtc
)
4664 struct drm_device
*dev
= crtc
->base
.dev
;
4665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4667 if (!crtc
->config
->ips_enabled
)
4670 assert_plane_enabled(dev_priv
, crtc
->plane
);
4671 if (IS_BROADWELL(dev
)) {
4672 mutex_lock(&dev_priv
->rps
.hw_lock
);
4673 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4674 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4675 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4676 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4677 DRM_ERROR("Timed out waiting for IPS disable\n");
4679 I915_WRITE(IPS_CTL
, 0);
4680 POSTING_READ(IPS_CTL
);
4683 /* We need to wait for a vblank before we can disable the plane. */
4684 intel_wait_for_vblank(dev
, crtc
->pipe
);
4687 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4688 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4690 struct drm_device
*dev
= crtc
->dev
;
4691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4692 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4693 enum pipe pipe
= intel_crtc
->pipe
;
4694 int palreg
= PALETTE(pipe
);
4696 bool reenable_ips
= false;
4698 /* The clocks have to be on to load the palette. */
4699 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4702 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4703 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4704 assert_dsi_pll_enabled(dev_priv
);
4706 assert_pll_enabled(dev_priv
, pipe
);
4709 /* use legacy palette for Ironlake */
4710 if (!HAS_GMCH_DISPLAY(dev
))
4711 palreg
= LGC_PALETTE(pipe
);
4713 /* Workaround : Do not read or write the pipe palette/gamma data while
4714 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4716 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4717 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4718 GAMMA_MODE_MODE_SPLIT
)) {
4719 hsw_disable_ips(intel_crtc
);
4720 reenable_ips
= true;
4723 for (i
= 0; i
< 256; i
++) {
4724 I915_WRITE(palreg
+ 4 * i
,
4725 (intel_crtc
->lut_r
[i
] << 16) |
4726 (intel_crtc
->lut_g
[i
] << 8) |
4727 intel_crtc
->lut_b
[i
]);
4731 hsw_enable_ips(intel_crtc
);
4734 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4736 if (intel_crtc
->overlay
) {
4737 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4740 mutex_lock(&dev
->struct_mutex
);
4741 dev_priv
->mm
.interruptible
= false;
4742 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4743 dev_priv
->mm
.interruptible
= true;
4744 mutex_unlock(&dev
->struct_mutex
);
4747 /* Let userspace switch the overlay on again. In most cases userspace
4748 * has to recompute where to put it anyway.
4753 * intel_post_enable_primary - Perform operations after enabling primary plane
4754 * @crtc: the CRTC whose primary plane was just enabled
4756 * Performs potentially sleeping operations that must be done after the primary
4757 * plane is enabled, such as updating FBC and IPS. Note that this may be
4758 * called due to an explicit primary plane update, or due to an implicit
4759 * re-enable that is caused when a sprite plane is updated to no longer
4760 * completely hide the primary plane.
4763 intel_post_enable_primary(struct drm_crtc
*crtc
)
4765 struct drm_device
*dev
= crtc
->dev
;
4766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4768 int pipe
= intel_crtc
->pipe
;
4771 * BDW signals flip done immediately if the plane
4772 * is disabled, even if the plane enable is already
4773 * armed to occur at the next vblank :(
4775 if (IS_BROADWELL(dev
))
4776 intel_wait_for_vblank(dev
, pipe
);
4779 * FIXME IPS should be fine as long as one plane is
4780 * enabled, but in practice it seems to have problems
4781 * when going from primary only to sprite only and vice
4784 hsw_enable_ips(intel_crtc
);
4786 mutex_lock(&dev
->struct_mutex
);
4787 intel_fbc_update(dev
);
4788 mutex_unlock(&dev
->struct_mutex
);
4791 * Gen2 reports pipe underruns whenever all planes are disabled.
4792 * So don't enable underrun reporting before at least some planes
4794 * FIXME: Need to fix the logic to work when we turn off all planes
4795 * but leave the pipe running.
4798 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4800 /* Underruns don't raise interrupts, so check manually. */
4801 if (HAS_GMCH_DISPLAY(dev
))
4802 i9xx_check_fifo_underruns(dev_priv
);
4806 * intel_pre_disable_primary - Perform operations before disabling primary plane
4807 * @crtc: the CRTC whose primary plane is to be disabled
4809 * Performs potentially sleeping operations that must be done before the
4810 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4811 * be called due to an explicit primary plane update, or due to an implicit
4812 * disable that is caused when a sprite plane completely hides the primary
4816 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4818 struct drm_device
*dev
= crtc
->dev
;
4819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4821 int pipe
= intel_crtc
->pipe
;
4824 * Gen2 reports pipe underruns whenever all planes are disabled.
4825 * So diasble underrun reporting before all the planes get disabled.
4826 * FIXME: Need to fix the logic to work when we turn off all planes
4827 * but leave the pipe running.
4830 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4833 * Vblank time updates from the shadow to live plane control register
4834 * are blocked if the memory self-refresh mode is active at that
4835 * moment. So to make sure the plane gets truly disabled, disable
4836 * first the self-refresh mode. The self-refresh enable bit in turn
4837 * will be checked/applied by the HW only at the next frame start
4838 * event which is after the vblank start event, so we need to have a
4839 * wait-for-vblank between disabling the plane and the pipe.
4841 if (HAS_GMCH_DISPLAY(dev
))
4842 intel_set_memory_cxsr(dev_priv
, false);
4844 mutex_lock(&dev
->struct_mutex
);
4845 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4846 intel_fbc_disable(dev
);
4847 mutex_unlock(&dev
->struct_mutex
);
4850 * FIXME IPS should be fine as long as one plane is
4851 * enabled, but in practice it seems to have problems
4852 * when going from primary only to sprite only and vice
4855 hsw_disable_ips(intel_crtc
);
4858 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4860 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4861 intel_enable_sprite_planes(crtc
);
4862 intel_crtc_update_cursor(crtc
, true);
4864 intel_post_enable_primary(crtc
);
4867 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4869 struct drm_device
*dev
= crtc
->dev
;
4870 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4871 struct intel_plane
*intel_plane
;
4872 int pipe
= intel_crtc
->pipe
;
4874 intel_crtc_wait_for_pending_flips(crtc
);
4876 intel_pre_disable_primary(crtc
);
4878 intel_crtc_dpms_overlay_disable(intel_crtc
);
4879 for_each_intel_plane(dev
, intel_plane
) {
4880 if (intel_plane
->pipe
== pipe
) {
4881 struct drm_crtc
*from
= intel_plane
->base
.crtc
;
4883 intel_plane
->disable_plane(&intel_plane
->base
,
4884 from
?: crtc
, true);
4889 * FIXME: Once we grow proper nuclear flip support out of this we need
4890 * to compute the mask of flip planes precisely. For the time being
4891 * consider this a flip to a NULL plane.
4893 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4896 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4898 struct drm_device
*dev
= crtc
->dev
;
4899 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4900 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4901 struct intel_encoder
*encoder
;
4902 int pipe
= intel_crtc
->pipe
;
4904 WARN_ON(!crtc
->state
->enable
);
4906 if (intel_crtc
->active
)
4909 if (intel_crtc
->config
->has_pch_encoder
)
4910 intel_prepare_shared_dpll(intel_crtc
);
4912 if (intel_crtc
->config
->has_dp_encoder
)
4913 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4915 intel_set_pipe_timings(intel_crtc
);
4917 if (intel_crtc
->config
->has_pch_encoder
) {
4918 intel_cpu_transcoder_set_m_n(intel_crtc
,
4919 &intel_crtc
->config
->fdi_m_n
, NULL
);
4922 ironlake_set_pipeconf(crtc
);
4924 intel_crtc
->active
= true;
4926 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4927 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4929 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4930 if (encoder
->pre_enable
)
4931 encoder
->pre_enable(encoder
);
4933 if (intel_crtc
->config
->has_pch_encoder
) {
4934 /* Note: FDI PLL enabling _must_ be done before we enable the
4935 * cpu pipes, hence this is separate from all the other fdi/pch
4937 ironlake_fdi_pll_enable(intel_crtc
);
4939 assert_fdi_tx_disabled(dev_priv
, pipe
);
4940 assert_fdi_rx_disabled(dev_priv
, pipe
);
4943 ironlake_pfit_enable(intel_crtc
);
4946 * On ILK+ LUT must be loaded before the pipe is running but with
4949 intel_crtc_load_lut(crtc
);
4951 intel_update_watermarks(crtc
);
4952 intel_enable_pipe(intel_crtc
);
4954 if (intel_crtc
->config
->has_pch_encoder
)
4955 ironlake_pch_enable(crtc
);
4957 assert_vblank_disabled(crtc
);
4958 drm_crtc_vblank_on(crtc
);
4960 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4961 encoder
->enable(encoder
);
4963 if (HAS_PCH_CPT(dev
))
4964 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4967 /* IPS only exists on ULT machines and is tied to pipe A. */
4968 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4970 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4974 * This implements the workaround described in the "notes" section of the mode
4975 * set sequence documentation. When going from no pipes or single pipe to
4976 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4977 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4979 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4981 struct drm_device
*dev
= crtc
->base
.dev
;
4982 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4984 /* We want to get the other_active_crtc only if there's only 1 other
4986 for_each_intel_crtc(dev
, crtc_it
) {
4987 if (!crtc_it
->active
|| crtc_it
== crtc
)
4990 if (other_active_crtc
)
4993 other_active_crtc
= crtc_it
;
4995 if (!other_active_crtc
)
4998 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4999 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
5002 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
5004 struct drm_device
*dev
= crtc
->dev
;
5005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5006 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5007 struct intel_encoder
*encoder
;
5008 int pipe
= intel_crtc
->pipe
;
5010 WARN_ON(!crtc
->state
->enable
);
5012 if (intel_crtc
->active
)
5015 if (intel_crtc_to_shared_dpll(intel_crtc
))
5016 intel_enable_shared_dpll(intel_crtc
);
5018 if (intel_crtc
->config
->has_dp_encoder
)
5019 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5021 intel_set_pipe_timings(intel_crtc
);
5023 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
5024 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
5025 intel_crtc
->config
->pixel_multiplier
- 1);
5028 if (intel_crtc
->config
->has_pch_encoder
) {
5029 intel_cpu_transcoder_set_m_n(intel_crtc
,
5030 &intel_crtc
->config
->fdi_m_n
, NULL
);
5033 haswell_set_pipeconf(crtc
);
5035 intel_set_pipe_csc(crtc
);
5037 intel_crtc
->active
= true;
5039 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5040 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5041 if (encoder
->pre_enable
)
5042 encoder
->pre_enable(encoder
);
5044 if (intel_crtc
->config
->has_pch_encoder
) {
5045 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5047 dev_priv
->display
.fdi_link_train(crtc
);
5050 intel_ddi_enable_pipe_clock(intel_crtc
);
5052 if (INTEL_INFO(dev
)->gen
== 9)
5053 skylake_pfit_update(intel_crtc
, 1);
5054 else if (INTEL_INFO(dev
)->gen
< 9)
5055 ironlake_pfit_enable(intel_crtc
);
5057 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5060 * On ILK+ LUT must be loaded before the pipe is running but with
5063 intel_crtc_load_lut(crtc
);
5065 intel_ddi_set_pipe_settings(crtc
);
5066 intel_ddi_enable_transcoder_func(crtc
);
5068 intel_update_watermarks(crtc
);
5069 intel_enable_pipe(intel_crtc
);
5071 if (intel_crtc
->config
->has_pch_encoder
)
5072 lpt_pch_enable(crtc
);
5074 if (intel_crtc
->config
->dp_encoder_is_mst
)
5075 intel_ddi_set_vc_payload_alloc(crtc
, true);
5077 assert_vblank_disabled(crtc
);
5078 drm_crtc_vblank_on(crtc
);
5080 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5081 encoder
->enable(encoder
);
5082 intel_opregion_notify_encoder(encoder
, true);
5085 /* If we change the relative order between pipe/planes enabling, we need
5086 * to change the workaround. */
5087 haswell_mode_set_planes_workaround(intel_crtc
);
5090 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
5092 struct drm_device
*dev
= crtc
->base
.dev
;
5093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5094 int pipe
= crtc
->pipe
;
5096 /* To avoid upsetting the power well on haswell only disable the pfit if
5097 * it's in use. The hw state code will make sure we get this right. */
5098 if (crtc
->config
->pch_pfit
.enabled
) {
5099 I915_WRITE(PF_CTL(pipe
), 0);
5100 I915_WRITE(PF_WIN_POS(pipe
), 0);
5101 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5105 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5107 struct drm_device
*dev
= crtc
->dev
;
5108 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5109 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5110 struct intel_encoder
*encoder
;
5111 int pipe
= intel_crtc
->pipe
;
5114 if (!intel_crtc
->active
)
5117 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5118 encoder
->disable(encoder
);
5120 drm_crtc_vblank_off(crtc
);
5121 assert_vblank_disabled(crtc
);
5123 if (intel_crtc
->config
->has_pch_encoder
)
5124 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5126 intel_disable_pipe(intel_crtc
);
5128 ironlake_pfit_disable(intel_crtc
);
5130 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5131 if (encoder
->post_disable
)
5132 encoder
->post_disable(encoder
);
5134 if (intel_crtc
->config
->has_pch_encoder
) {
5135 ironlake_fdi_disable(crtc
);
5137 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5139 if (HAS_PCH_CPT(dev
)) {
5140 /* disable TRANS_DP_CTL */
5141 reg
= TRANS_DP_CTL(pipe
);
5142 temp
= I915_READ(reg
);
5143 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5144 TRANS_DP_PORT_SEL_MASK
);
5145 temp
|= TRANS_DP_PORT_SEL_NONE
;
5146 I915_WRITE(reg
, temp
);
5148 /* disable DPLL_SEL */
5149 temp
= I915_READ(PCH_DPLL_SEL
);
5150 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5151 I915_WRITE(PCH_DPLL_SEL
, temp
);
5154 /* disable PCH DPLL */
5155 intel_disable_shared_dpll(intel_crtc
);
5157 ironlake_fdi_pll_disable(intel_crtc
);
5160 intel_crtc
->active
= false;
5161 intel_update_watermarks(crtc
);
5163 mutex_lock(&dev
->struct_mutex
);
5164 intel_fbc_update(dev
);
5165 mutex_unlock(&dev
->struct_mutex
);
5168 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5170 struct drm_device
*dev
= crtc
->dev
;
5171 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5172 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5173 struct intel_encoder
*encoder
;
5174 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5176 if (!intel_crtc
->active
)
5179 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5180 intel_opregion_notify_encoder(encoder
, false);
5181 encoder
->disable(encoder
);
5184 drm_crtc_vblank_off(crtc
);
5185 assert_vblank_disabled(crtc
);
5187 if (intel_crtc
->config
->has_pch_encoder
)
5188 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5190 intel_disable_pipe(intel_crtc
);
5192 if (intel_crtc
->config
->dp_encoder_is_mst
)
5193 intel_ddi_set_vc_payload_alloc(crtc
, false);
5195 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5197 if (INTEL_INFO(dev
)->gen
== 9)
5198 skylake_pfit_update(intel_crtc
, 0);
5199 else if (INTEL_INFO(dev
)->gen
< 9)
5200 ironlake_pfit_disable(intel_crtc
);
5202 MISSING_CASE(INTEL_INFO(dev
)->gen
);
5204 intel_ddi_disable_pipe_clock(intel_crtc
);
5206 if (intel_crtc
->config
->has_pch_encoder
) {
5207 lpt_disable_pch_transcoder(dev_priv
);
5208 intel_ddi_fdi_disable(crtc
);
5211 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5212 if (encoder
->post_disable
)
5213 encoder
->post_disable(encoder
);
5215 intel_crtc
->active
= false;
5216 intel_update_watermarks(crtc
);
5218 mutex_lock(&dev
->struct_mutex
);
5219 intel_fbc_update(dev
);
5220 mutex_unlock(&dev
->struct_mutex
);
5222 if (intel_crtc_to_shared_dpll(intel_crtc
))
5223 intel_disable_shared_dpll(intel_crtc
);
5226 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
5228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5229 intel_put_shared_dpll(intel_crtc
);
5233 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5235 struct drm_device
*dev
= crtc
->base
.dev
;
5236 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5237 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5239 if (!pipe_config
->gmch_pfit
.control
)
5243 * The panel fitter should only be adjusted whilst the pipe is disabled,
5244 * according to register description and PRM.
5246 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5247 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5249 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5250 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5252 /* Border color in case we don't scale up to the full screen. Black by
5253 * default, change to something else for debugging. */
5254 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5257 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5261 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5263 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5265 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5267 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5270 return POWER_DOMAIN_PORT_OTHER
;
5274 #define for_each_power_domain(domain, mask) \
5275 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5276 if ((1 << (domain)) & (mask))
5278 enum intel_display_power_domain
5279 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5281 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5282 struct intel_digital_port
*intel_dig_port
;
5284 switch (intel_encoder
->type
) {
5285 case INTEL_OUTPUT_UNKNOWN
:
5286 /* Only DDI platforms should ever use this output type */
5287 WARN_ON_ONCE(!HAS_DDI(dev
));
5288 case INTEL_OUTPUT_DISPLAYPORT
:
5289 case INTEL_OUTPUT_HDMI
:
5290 case INTEL_OUTPUT_EDP
:
5291 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5292 return port_to_power_domain(intel_dig_port
->port
);
5293 case INTEL_OUTPUT_DP_MST
:
5294 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5295 return port_to_power_domain(intel_dig_port
->port
);
5296 case INTEL_OUTPUT_ANALOG
:
5297 return POWER_DOMAIN_PORT_CRT
;
5298 case INTEL_OUTPUT_DSI
:
5299 return POWER_DOMAIN_PORT_DSI
;
5301 return POWER_DOMAIN_PORT_OTHER
;
5305 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5307 struct drm_device
*dev
= crtc
->dev
;
5308 struct intel_encoder
*intel_encoder
;
5309 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5310 enum pipe pipe
= intel_crtc
->pipe
;
5312 enum transcoder transcoder
;
5314 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5316 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5317 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5318 if (intel_crtc
->config
->pch_pfit
.enabled
||
5319 intel_crtc
->config
->pch_pfit
.force_thru
)
5320 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5322 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5323 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5328 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5330 struct drm_device
*dev
= state
->dev
;
5331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5332 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
5333 struct intel_crtc
*crtc
;
5336 * First get all needed power domains, then put all unneeded, to avoid
5337 * any unnecessary toggling of the power wells.
5339 for_each_intel_crtc(dev
, crtc
) {
5340 enum intel_display_power_domain domain
;
5342 if (!crtc
->base
.state
->enable
)
5345 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
5347 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
5348 intel_display_power_get(dev_priv
, domain
);
5351 if (dev_priv
->display
.modeset_global_resources
)
5352 dev_priv
->display
.modeset_global_resources(state
);
5354 for_each_intel_crtc(dev
, crtc
) {
5355 enum intel_display_power_domain domain
;
5357 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
5358 intel_display_power_put(dev_priv
, domain
);
5360 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
5363 intel_display_set_init_power(dev_priv
, false);
5366 void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5371 uint32_t current_freq
;
5374 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5375 switch (frequency
) {
5377 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5378 ratio
= BXT_DE_PLL_RATIO(60);
5381 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5382 ratio
= BXT_DE_PLL_RATIO(60);
5385 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5386 ratio
= BXT_DE_PLL_RATIO(60);
5389 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5390 ratio
= BXT_DE_PLL_RATIO(60);
5393 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5394 ratio
= BXT_DE_PLL_RATIO(65);
5398 * Bypass frequency with DE PLL disabled. Init ratio, divider
5399 * to suppress GCC warning.
5405 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5410 mutex_lock(&dev_priv
->rps
.hw_lock
);
5411 /* Inform power controller of upcoming frequency change */
5412 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5414 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5417 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5422 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5423 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5424 current_freq
= current_freq
* 500 + 1000;
5427 * DE PLL has to be disabled when
5428 * - setting to 19.2MHz (bypass, PLL isn't used)
5429 * - before setting to 624MHz (PLL needs toggling)
5430 * - before setting to any frequency from 624MHz (PLL needs toggling)
5432 if (frequency
== 19200 || frequency
== 624000 ||
5433 current_freq
== 624000) {
5434 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5436 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5438 DRM_ERROR("timout waiting for DE PLL unlock\n");
5441 if (frequency
!= 19200) {
5444 val
= I915_READ(BXT_DE_PLL_CTL
);
5445 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5447 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5449 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5451 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5452 DRM_ERROR("timeout waiting for DE PLL lock\n");
5454 val
= I915_READ(CDCLK_CTL
);
5455 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5458 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5461 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5462 if (frequency
>= 500000)
5463 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5465 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5466 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5467 val
|= (frequency
- 1000) / 500;
5468 I915_WRITE(CDCLK_CTL
, val
);
5471 mutex_lock(&dev_priv
->rps
.hw_lock
);
5472 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5473 DIV_ROUND_UP(frequency
, 25000));
5474 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5477 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5482 dev_priv
->cdclk_freq
= frequency
;
5485 void broxton_init_cdclk(struct drm_device
*dev
)
5487 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5491 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5492 * or else the reset will hang because there is no PCH to respond.
5493 * Move the handshake programming to initialization sequence.
5494 * Previously was left up to BIOS.
5496 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5497 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5498 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5500 /* Enable PG1 for cdclk */
5501 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5503 /* check if cd clock is enabled */
5504 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5505 DRM_DEBUG_KMS("Display already initialized\n");
5511 * - The initial CDCLK needs to be read from VBT.
5512 * Need to make this change after VBT has changes for BXT.
5513 * - check if setting the max (or any) cdclk freq is really necessary
5514 * here, it belongs to modeset time
5516 broxton_set_cdclk(dev
, 624000);
5518 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5519 POSTING_READ(DBUF_CTL
);
5523 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5524 DRM_ERROR("DBuf power enable timeout!\n");
5527 void broxton_uninit_cdclk(struct drm_device
*dev
)
5529 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5531 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5532 POSTING_READ(DBUF_CTL
);
5536 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5537 DRM_ERROR("DBuf power disable timeout!\n");
5539 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5540 broxton_set_cdclk(dev
, 19200);
5542 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5545 /* returns HPLL frequency in kHz */
5546 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5548 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5550 /* Obtain SKU information */
5551 mutex_lock(&dev_priv
->dpio_lock
);
5552 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5553 CCK_FUSE_HPLL_FREQ_MASK
;
5554 mutex_unlock(&dev_priv
->dpio_lock
);
5556 return vco_freq
[hpll_freq
] * 1000;
5559 static void vlv_update_cdclk(struct drm_device
*dev
)
5561 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5563 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5564 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5565 dev_priv
->cdclk_freq
);
5568 * Program the gmbus_freq based on the cdclk frequency.
5569 * BSpec erroneously claims we should aim for 4MHz, but
5570 * in fact 1MHz is the correct frequency.
5572 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5575 /* Adjust CDclk dividers to allow high res or save power if possible */
5576 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5578 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5581 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5582 != dev_priv
->cdclk_freq
);
5584 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5586 else if (cdclk
== 266667)
5591 mutex_lock(&dev_priv
->rps
.hw_lock
);
5592 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5593 val
&= ~DSPFREQGUAR_MASK
;
5594 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5595 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5596 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5597 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5599 DRM_ERROR("timed out waiting for CDclk change\n");
5601 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5603 if (cdclk
== 400000) {
5606 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5608 mutex_lock(&dev_priv
->dpio_lock
);
5609 /* adjust cdclk divider */
5610 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5611 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5613 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5615 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5616 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5618 DRM_ERROR("timed out waiting for CDclk change\n");
5619 mutex_unlock(&dev_priv
->dpio_lock
);
5622 mutex_lock(&dev_priv
->dpio_lock
);
5623 /* adjust self-refresh exit latency value */
5624 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5628 * For high bandwidth configs, we set a higher latency in the bunit
5629 * so that the core display fetch happens in time to avoid underruns.
5631 if (cdclk
== 400000)
5632 val
|= 4500 / 250; /* 4.5 usec */
5634 val
|= 3000 / 250; /* 3.0 usec */
5635 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5636 mutex_unlock(&dev_priv
->dpio_lock
);
5638 vlv_update_cdclk(dev
);
5641 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5643 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5646 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5647 != dev_priv
->cdclk_freq
);
5656 MISSING_CASE(cdclk
);
5661 * Specs are full of misinformation, but testing on actual
5662 * hardware has shown that we just need to write the desired
5663 * CCK divider into the Punit register.
5665 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5667 mutex_lock(&dev_priv
->rps
.hw_lock
);
5668 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5669 val
&= ~DSPFREQGUAR_MASK_CHV
;
5670 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5671 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5672 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5673 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5675 DRM_ERROR("timed out waiting for CDclk change\n");
5677 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5679 vlv_update_cdclk(dev
);
5682 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5685 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5686 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5689 * Really only a few cases to deal with, as only 4 CDclks are supported:
5692 * 320/333MHz (depends on HPLL freq)
5694 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5695 * of the lower bin and adjust if needed.
5697 * We seem to get an unstable or solid color picture at 200MHz.
5698 * Not sure what's wrong. For now use 200MHz only when all pipes
5701 if (!IS_CHERRYVIEW(dev_priv
) &&
5702 max_pixclk
> freq_320
*limit
/100)
5704 else if (max_pixclk
> 266667*limit
/100)
5706 else if (max_pixclk
> 0)
5712 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5717 * - remove the guardband, it's not needed on BXT
5718 * - set 19.2MHz bypass frequency if there are no active pipes
5720 if (max_pixclk
> 576000*9/10)
5722 else if (max_pixclk
> 384000*9/10)
5724 else if (max_pixclk
> 288000*9/10)
5726 else if (max_pixclk
> 144000*9/10)
5732 /* compute the max pixel clock for new configuration */
5733 static int intel_mode_max_pixclk(struct drm_atomic_state
*state
)
5735 struct drm_device
*dev
= state
->dev
;
5736 struct intel_crtc
*intel_crtc
;
5737 struct intel_crtc_state
*crtc_state
;
5740 for_each_intel_crtc(dev
, intel_crtc
) {
5741 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
5742 if (IS_ERR(crtc_state
))
5743 return PTR_ERR(crtc_state
);
5745 if (!crtc_state
->base
.enable
)
5748 max_pixclk
= max(max_pixclk
,
5749 crtc_state
->base
.adjusted_mode
.crtc_clock
);
5755 static int valleyview_modeset_global_pipes(struct drm_atomic_state
*state
)
5757 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
5758 struct drm_crtc
*crtc
;
5759 struct drm_crtc_state
*crtc_state
;
5760 int max_pixclk
= intel_mode_max_pixclk(state
);
5766 if (IS_VALLEYVIEW(dev_priv
))
5767 cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5769 cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
5771 if (cdclk
== dev_priv
->cdclk_freq
)
5774 /* add all active pipes to the state */
5775 for_each_crtc(state
->dev
, crtc
) {
5776 if (!crtc
->state
->enable
)
5779 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
5780 if (IS_ERR(crtc_state
))
5781 return PTR_ERR(crtc_state
);
5784 /* disable/enable all currently active pipes while we change cdclk */
5785 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
5786 if (crtc_state
->enable
)
5787 crtc_state
->mode_changed
= true;
5792 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5794 unsigned int credits
, default_credits
;
5796 if (IS_CHERRYVIEW(dev_priv
))
5797 default_credits
= PFI_CREDIT(12);
5799 default_credits
= PFI_CREDIT(8);
5801 if (DIV_ROUND_CLOSEST(dev_priv
->cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5802 /* CHV suggested value is 31 or 63 */
5803 if (IS_CHERRYVIEW(dev_priv
))
5804 credits
= PFI_CREDIT_31
;
5806 credits
= PFI_CREDIT(15);
5808 credits
= default_credits
;
5812 * WA - write default credits before re-programming
5813 * FIXME: should we also set the resend bit here?
5815 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5818 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5819 credits
| PFI_CREDIT_RESEND
);
5822 * FIXME is this guaranteed to clear
5823 * immediately or should we poll for it?
5825 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
5828 static void valleyview_modeset_global_resources(struct drm_atomic_state
*state
)
5830 struct drm_device
*dev
= state
->dev
;
5831 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5832 int max_pixclk
= intel_mode_max_pixclk(state
);
5835 /* The only reason this can fail is if we fail to add the crtc_state
5836 * to the atomic state. But that can't happen since the call to
5837 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5838 * can't have failed otherwise the mode set would be aborted) added all
5839 * the states already. */
5840 if (WARN_ON(max_pixclk
< 0))
5843 req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5845 if (req_cdclk
!= dev_priv
->cdclk_freq
) {
5847 * FIXME: We can end up here with all power domains off, yet
5848 * with a CDCLK frequency other than the minimum. To account
5849 * for this take the PIPE-A power domain, which covers the HW
5850 * blocks needed for the following programming. This can be
5851 * removed once it's guaranteed that we get here either with
5852 * the minimum CDCLK set, or the required power domains
5855 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5857 if (IS_CHERRYVIEW(dev
))
5858 cherryview_set_cdclk(dev
, req_cdclk
);
5860 valleyview_set_cdclk(dev
, req_cdclk
);
5862 vlv_program_pfi_credits(dev_priv
);
5864 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5868 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5870 struct drm_device
*dev
= crtc
->dev
;
5871 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5872 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5873 struct intel_encoder
*encoder
;
5874 int pipe
= intel_crtc
->pipe
;
5877 WARN_ON(!crtc
->state
->enable
);
5879 if (intel_crtc
->active
)
5882 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5885 if (IS_CHERRYVIEW(dev
))
5886 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5888 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5891 if (intel_crtc
->config
->has_dp_encoder
)
5892 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5894 intel_set_pipe_timings(intel_crtc
);
5896 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5899 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5900 I915_WRITE(CHV_CANVAS(pipe
), 0);
5903 i9xx_set_pipeconf(intel_crtc
);
5905 intel_crtc
->active
= true;
5907 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5909 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5910 if (encoder
->pre_pll_enable
)
5911 encoder
->pre_pll_enable(encoder
);
5914 if (IS_CHERRYVIEW(dev
))
5915 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5917 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5920 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5921 if (encoder
->pre_enable
)
5922 encoder
->pre_enable(encoder
);
5924 i9xx_pfit_enable(intel_crtc
);
5926 intel_crtc_load_lut(crtc
);
5928 intel_update_watermarks(crtc
);
5929 intel_enable_pipe(intel_crtc
);
5931 assert_vblank_disabled(crtc
);
5932 drm_crtc_vblank_on(crtc
);
5934 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5935 encoder
->enable(encoder
);
5938 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5940 struct drm_device
*dev
= crtc
->base
.dev
;
5941 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5943 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5944 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5947 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5949 struct drm_device
*dev
= crtc
->dev
;
5950 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5951 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5952 struct intel_encoder
*encoder
;
5953 int pipe
= intel_crtc
->pipe
;
5955 WARN_ON(!crtc
->state
->enable
);
5957 if (intel_crtc
->active
)
5960 i9xx_set_pll_dividers(intel_crtc
);
5962 if (intel_crtc
->config
->has_dp_encoder
)
5963 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5965 intel_set_pipe_timings(intel_crtc
);
5967 i9xx_set_pipeconf(intel_crtc
);
5969 intel_crtc
->active
= true;
5972 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5974 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5975 if (encoder
->pre_enable
)
5976 encoder
->pre_enable(encoder
);
5978 i9xx_enable_pll(intel_crtc
);
5980 i9xx_pfit_enable(intel_crtc
);
5982 intel_crtc_load_lut(crtc
);
5984 intel_update_watermarks(crtc
);
5985 intel_enable_pipe(intel_crtc
);
5987 assert_vblank_disabled(crtc
);
5988 drm_crtc_vblank_on(crtc
);
5990 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5991 encoder
->enable(encoder
);
5994 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5996 struct drm_device
*dev
= crtc
->base
.dev
;
5997 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5999 if (!crtc
->config
->gmch_pfit
.control
)
6002 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6004 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6005 I915_READ(PFIT_CONTROL
));
6006 I915_WRITE(PFIT_CONTROL
, 0);
6009 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6011 struct drm_device
*dev
= crtc
->dev
;
6012 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6013 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6014 struct intel_encoder
*encoder
;
6015 int pipe
= intel_crtc
->pipe
;
6017 if (!intel_crtc
->active
)
6021 * On gen2 planes are double buffered but the pipe isn't, so we must
6022 * wait for planes to fully turn off before disabling the pipe.
6023 * We also need to wait on all gmch platforms because of the
6024 * self-refresh mode constraint explained above.
6026 intel_wait_for_vblank(dev
, pipe
);
6028 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6029 encoder
->disable(encoder
);
6031 drm_crtc_vblank_off(crtc
);
6032 assert_vblank_disabled(crtc
);
6034 intel_disable_pipe(intel_crtc
);
6036 i9xx_pfit_disable(intel_crtc
);
6038 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6039 if (encoder
->post_disable
)
6040 encoder
->post_disable(encoder
);
6042 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6043 if (IS_CHERRYVIEW(dev
))
6044 chv_disable_pll(dev_priv
, pipe
);
6045 else if (IS_VALLEYVIEW(dev
))
6046 vlv_disable_pll(dev_priv
, pipe
);
6048 i9xx_disable_pll(intel_crtc
);
6052 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6054 intel_crtc
->active
= false;
6055 intel_update_watermarks(crtc
);
6057 mutex_lock(&dev
->struct_mutex
);
6058 intel_fbc_update(dev
);
6059 mutex_unlock(&dev
->struct_mutex
);
6062 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
6066 /* Master function to enable/disable CRTC and corresponding power wells */
6067 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
6069 struct drm_device
*dev
= crtc
->dev
;
6070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6071 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6072 enum intel_display_power_domain domain
;
6073 unsigned long domains
;
6076 if (!intel_crtc
->active
) {
6077 domains
= get_crtc_power_domains(crtc
);
6078 for_each_power_domain(domain
, domains
)
6079 intel_display_power_get(dev_priv
, domain
);
6080 intel_crtc
->enabled_power_domains
= domains
;
6082 dev_priv
->display
.crtc_enable(crtc
);
6083 intel_crtc_enable_planes(crtc
);
6086 if (intel_crtc
->active
) {
6087 intel_crtc_disable_planes(crtc
);
6088 dev_priv
->display
.crtc_disable(crtc
);
6090 domains
= intel_crtc
->enabled_power_domains
;
6091 for_each_power_domain(domain
, domains
)
6092 intel_display_power_put(dev_priv
, domain
);
6093 intel_crtc
->enabled_power_domains
= 0;
6099 * Sets the power management mode of the pipe and plane.
6101 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
6103 struct drm_device
*dev
= crtc
->dev
;
6104 struct intel_encoder
*intel_encoder
;
6105 bool enable
= false;
6107 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
6108 enable
|= intel_encoder
->connectors_active
;
6110 intel_crtc_control(crtc
, enable
);
6113 static void intel_crtc_disable(struct drm_crtc
*crtc
)
6115 struct drm_device
*dev
= crtc
->dev
;
6116 struct drm_connector
*connector
;
6117 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6119 /* crtc should still be enabled when we disable it. */
6120 WARN_ON(!crtc
->state
->enable
);
6122 intel_crtc_disable_planes(crtc
);
6123 dev_priv
->display
.crtc_disable(crtc
);
6124 dev_priv
->display
.off(crtc
);
6126 drm_plane_helper_disable(crtc
->primary
);
6128 /* Update computed state. */
6129 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
6130 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
6133 if (connector
->encoder
->crtc
!= crtc
)
6136 connector
->dpms
= DRM_MODE_DPMS_OFF
;
6137 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
6141 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6143 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6145 drm_encoder_cleanup(encoder
);
6146 kfree(intel_encoder
);
6149 /* Simple dpms helper for encoders with just one connector, no cloning and only
6150 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6151 * state of the entire output pipe. */
6152 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
6154 if (mode
== DRM_MODE_DPMS_ON
) {
6155 encoder
->connectors_active
= true;
6157 intel_crtc_update_dpms(encoder
->base
.crtc
);
6159 encoder
->connectors_active
= false;
6161 intel_crtc_update_dpms(encoder
->base
.crtc
);
6165 /* Cross check the actual hw state with our own modeset state tracking (and it's
6166 * internal consistency). */
6167 static void intel_connector_check_state(struct intel_connector
*connector
)
6169 if (connector
->get_hw_state(connector
)) {
6170 struct intel_encoder
*encoder
= connector
->encoder
;
6171 struct drm_crtc
*crtc
;
6172 bool encoder_enabled
;
6175 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6176 connector
->base
.base
.id
,
6177 connector
->base
.name
);
6179 /* there is no real hw state for MST connectors */
6180 if (connector
->mst_port
)
6183 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
6184 "wrong connector dpms state\n");
6185 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
6186 "active connector not linked to encoder\n");
6189 I915_STATE_WARN(!encoder
->connectors_active
,
6190 "encoder->connectors_active not set\n");
6192 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
6193 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
6194 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
6197 crtc
= encoder
->base
.crtc
;
6199 I915_STATE_WARN(!crtc
->state
->enable
,
6200 "crtc not enabled\n");
6201 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
6202 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
6203 "encoder active on the wrong pipe\n");
6208 int intel_connector_init(struct intel_connector
*connector
)
6210 struct drm_connector_state
*connector_state
;
6212 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6213 if (!connector_state
)
6216 connector
->base
.state
= connector_state
;
6220 struct intel_connector
*intel_connector_alloc(void)
6222 struct intel_connector
*connector
;
6224 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6228 if (intel_connector_init(connector
) < 0) {
6236 /* Even simpler default implementation, if there's really no special case to
6238 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
6240 /* All the simple cases only support two dpms states. */
6241 if (mode
!= DRM_MODE_DPMS_ON
)
6242 mode
= DRM_MODE_DPMS_OFF
;
6244 if (mode
== connector
->dpms
)
6247 connector
->dpms
= mode
;
6249 /* Only need to change hw state when actually enabled */
6250 if (connector
->encoder
)
6251 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
6253 intel_modeset_check_state(connector
->dev
);
6256 /* Simple connector->get_hw_state implementation for encoders that support only
6257 * one connector and no cloning and hence the encoder state determines the state
6258 * of the connector. */
6259 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6262 struct intel_encoder
*encoder
= connector
->encoder
;
6264 return encoder
->get_hw_state(encoder
, &pipe
);
6267 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6269 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6270 return crtc_state
->fdi_lanes
;
6275 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6276 struct intel_crtc_state
*pipe_config
)
6278 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6279 struct intel_crtc
*other_crtc
;
6280 struct intel_crtc_state
*other_crtc_state
;
6282 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6283 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6284 if (pipe_config
->fdi_lanes
> 4) {
6285 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6286 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6290 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6291 if (pipe_config
->fdi_lanes
> 2) {
6292 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6293 pipe_config
->fdi_lanes
);
6300 if (INTEL_INFO(dev
)->num_pipes
== 2)
6303 /* Ivybridge 3 pipe is really complicated */
6308 if (pipe_config
->fdi_lanes
<= 2)
6311 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6313 intel_atomic_get_crtc_state(state
, other_crtc
);
6314 if (IS_ERR(other_crtc_state
))
6315 return PTR_ERR(other_crtc_state
);
6317 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6318 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6319 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6324 if (pipe_config
->fdi_lanes
> 2) {
6325 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6326 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6330 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6332 intel_atomic_get_crtc_state(state
, other_crtc
);
6333 if (IS_ERR(other_crtc_state
))
6334 return PTR_ERR(other_crtc_state
);
6336 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6337 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6347 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6348 struct intel_crtc_state
*pipe_config
)
6350 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6351 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6352 int lane
, link_bw
, fdi_dotclock
, ret
;
6353 bool needs_recompute
= false;
6356 /* FDI is a binary signal running at ~2.7GHz, encoding
6357 * each output octet as 10 bits. The actual frequency
6358 * is stored as a divider into a 100MHz clock, and the
6359 * mode pixel clock is stored in units of 1KHz.
6360 * Hence the bw of each lane in terms of the mode signal
6363 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6365 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6367 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6368 pipe_config
->pipe_bpp
);
6370 pipe_config
->fdi_lanes
= lane
;
6372 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6373 link_bw
, &pipe_config
->fdi_m_n
);
6375 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6376 intel_crtc
->pipe
, pipe_config
);
6377 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6378 pipe_config
->pipe_bpp
-= 2*3;
6379 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6380 pipe_config
->pipe_bpp
);
6381 needs_recompute
= true;
6382 pipe_config
->bw_constrained
= true;
6387 if (needs_recompute
)
6393 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6394 struct intel_crtc_state
*pipe_config
)
6396 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6397 hsw_crtc_supports_ips(crtc
) &&
6398 pipe_config
->pipe_bpp
<= 24;
6401 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6402 struct intel_crtc_state
*pipe_config
)
6404 struct drm_device
*dev
= crtc
->base
.dev
;
6405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6406 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6409 /* FIXME should check pixel clock limits on all platforms */
6410 if (INTEL_INFO(dev
)->gen
< 4) {
6412 dev_priv
->display
.get_display_clock_speed(dev
);
6415 * Enable pixel doubling when the dot clock
6416 * is > 90% of the (display) core speed.
6418 * GDG double wide on either pipe,
6419 * otherwise pipe A only.
6421 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6422 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6424 pipe_config
->double_wide
= true;
6427 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6432 * Pipe horizontal size must be even in:
6434 * - LVDS dual channel mode
6435 * - Double wide pipe
6437 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6438 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6439 pipe_config
->pipe_src_w
&= ~1;
6441 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6442 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6444 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6445 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
6449 hsw_compute_ips_config(crtc
, pipe_config
);
6451 if (pipe_config
->has_pch_encoder
)
6452 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6454 /* FIXME: remove below call once atomic mode set is place and all crtc
6455 * related checks called from atomic_crtc_check function */
6457 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6458 crtc
, pipe_config
->base
.state
);
6459 ret
= intel_atomic_setup_scalers(dev
, crtc
, pipe_config
);
6464 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6466 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6467 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6468 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6471 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
6472 WARN(1, "LCPLL1 not enabled\n");
6473 return 24000; /* 24MHz is the cd freq with NSSC ref */
6476 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6479 linkrate
= (I915_READ(DPLL_CTRL1
) &
6480 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6482 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6483 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6485 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6486 case CDCLK_FREQ_450_432
:
6488 case CDCLK_FREQ_337_308
:
6490 case CDCLK_FREQ_675_617
:
6493 WARN(1, "Unknown cd freq selection\n");
6497 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6498 case CDCLK_FREQ_450_432
:
6500 case CDCLK_FREQ_337_308
:
6502 case CDCLK_FREQ_675_617
:
6505 WARN(1, "Unknown cd freq selection\n");
6509 /* error case, do as if DPLL0 isn't enabled */
6513 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6516 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6517 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6519 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6521 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6523 else if (freq
== LCPLL_CLK_FREQ_450
)
6525 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6527 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6533 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6536 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6537 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6539 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6541 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6543 else if (freq
== LCPLL_CLK_FREQ_450
)
6545 else if (IS_HSW_ULT(dev
))
6551 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6557 if (dev_priv
->hpll_freq
== 0)
6558 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
6560 mutex_lock(&dev_priv
->dpio_lock
);
6561 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
6562 mutex_unlock(&dev_priv
->dpio_lock
);
6564 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
6566 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
6567 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
6568 "cdclk change in progress\n");
6570 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
6573 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6578 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6583 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6588 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6593 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6597 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6599 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6600 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6602 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6604 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6606 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6609 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6610 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6612 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6617 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6621 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6623 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6626 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6627 case GC_DISPLAY_CLOCK_333_MHZ
:
6630 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6636 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6641 static int i855_get_display_clock_speed(struct drm_device
*dev
)
6644 /* Assume that the hardware is in the high speed state. This
6645 * should be the default.
6647 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6648 case GC_CLOCK_133_200
:
6649 case GC_CLOCK_100_200
:
6651 case GC_CLOCK_166_250
:
6653 case GC_CLOCK_100_133
:
6657 /* Shouldn't happen */
6661 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6667 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6669 while (*num
> DATA_LINK_M_N_MASK
||
6670 *den
> DATA_LINK_M_N_MASK
) {
6676 static void compute_m_n(unsigned int m
, unsigned int n
,
6677 uint32_t *ret_m
, uint32_t *ret_n
)
6679 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6680 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6681 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6685 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6686 int pixel_clock
, int link_clock
,
6687 struct intel_link_m_n
*m_n
)
6691 compute_m_n(bits_per_pixel
* pixel_clock
,
6692 link_clock
* nlanes
* 8,
6693 &m_n
->gmch_m
, &m_n
->gmch_n
);
6695 compute_m_n(pixel_clock
, link_clock
,
6696 &m_n
->link_m
, &m_n
->link_n
);
6699 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6701 if (i915
.panel_use_ssc
>= 0)
6702 return i915
.panel_use_ssc
!= 0;
6703 return dev_priv
->vbt
.lvds_use_ssc
6704 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6707 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
6710 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
6711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6714 WARN_ON(!crtc_state
->base
.state
);
6716 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
6718 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6719 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6720 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
6721 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
6722 } else if (!IS_GEN2(dev
)) {
6731 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6733 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6736 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6738 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6741 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6742 struct intel_crtc_state
*crtc_state
,
6743 intel_clock_t
*reduced_clock
)
6745 struct drm_device
*dev
= crtc
->base
.dev
;
6748 if (IS_PINEVIEW(dev
)) {
6749 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6751 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6753 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6755 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6758 crtc_state
->dpll_hw_state
.fp0
= fp
;
6760 crtc
->lowfreq_avail
= false;
6761 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6763 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6764 crtc
->lowfreq_avail
= true;
6766 crtc_state
->dpll_hw_state
.fp1
= fp
;
6770 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6776 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6777 * and set it to a reasonable value instead.
6779 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6780 reg_val
&= 0xffffff00;
6781 reg_val
|= 0x00000030;
6782 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6784 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6785 reg_val
&= 0x8cffffff;
6786 reg_val
= 0x8c000000;
6787 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6789 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6790 reg_val
&= 0xffffff00;
6791 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6793 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6794 reg_val
&= 0x00ffffff;
6795 reg_val
|= 0xb0000000;
6796 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6799 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6800 struct intel_link_m_n
*m_n
)
6802 struct drm_device
*dev
= crtc
->base
.dev
;
6803 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6804 int pipe
= crtc
->pipe
;
6806 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6807 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6808 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6809 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6812 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6813 struct intel_link_m_n
*m_n
,
6814 struct intel_link_m_n
*m2_n2
)
6816 struct drm_device
*dev
= crtc
->base
.dev
;
6817 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6818 int pipe
= crtc
->pipe
;
6819 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
6821 if (INTEL_INFO(dev
)->gen
>= 5) {
6822 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6823 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
6824 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
6825 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
6826 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6827 * for gen < 8) and if DRRS is supported (to make sure the
6828 * registers are not unnecessarily accessed).
6830 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
6831 crtc
->config
->has_drrs
) {
6832 I915_WRITE(PIPE_DATA_M2(transcoder
),
6833 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
6834 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
6835 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
6836 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
6839 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6840 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
6841 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
6842 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
6846 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
6848 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
6851 dp_m_n
= &crtc
->config
->dp_m_n
;
6852 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
6853 } else if (m_n
== M2_N2
) {
6856 * M2_N2 registers are not supported. Hence m2_n2 divider value
6857 * needs to be programmed into M1_N1.
6859 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6861 DRM_ERROR("Unsupported divider value\n");
6865 if (crtc
->config
->has_pch_encoder
)
6866 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6868 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6871 static void vlv_update_pll(struct intel_crtc
*crtc
,
6872 struct intel_crtc_state
*pipe_config
)
6877 * Enable DPIO clock input. We should never disable the reference
6878 * clock for pipe B, since VGA hotplug / manual detection depends
6881 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
6882 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
6883 /* We should never disable this, set it here for state tracking */
6884 if (crtc
->pipe
== PIPE_B
)
6885 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6886 dpll
|= DPLL_VCO_ENABLE
;
6887 pipe_config
->dpll_hw_state
.dpll
= dpll
;
6889 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
6890 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6891 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6894 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6895 const struct intel_crtc_state
*pipe_config
)
6897 struct drm_device
*dev
= crtc
->base
.dev
;
6898 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6899 int pipe
= crtc
->pipe
;
6901 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6902 u32 coreclk
, reg_val
;
6904 mutex_lock(&dev_priv
->dpio_lock
);
6906 bestn
= pipe_config
->dpll
.n
;
6907 bestm1
= pipe_config
->dpll
.m1
;
6908 bestm2
= pipe_config
->dpll
.m2
;
6909 bestp1
= pipe_config
->dpll
.p1
;
6910 bestp2
= pipe_config
->dpll
.p2
;
6912 /* See eDP HDMI DPIO driver vbios notes doc */
6914 /* PLL B needs special handling */
6916 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6918 /* Set up Tx target for periodic Rcomp update */
6919 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6921 /* Disable target IRef on PLL */
6922 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6923 reg_val
&= 0x00ffffff;
6924 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6926 /* Disable fast lock */
6927 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6929 /* Set idtafcrecal before PLL is enabled */
6930 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6931 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6932 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6933 mdiv
|= (1 << DPIO_K_SHIFT
);
6936 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6937 * but we don't support that).
6938 * Note: don't use the DAC post divider as it seems unstable.
6940 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6941 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6943 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6944 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6946 /* Set HBR and RBR LPF coefficients */
6947 if (pipe_config
->port_clock
== 162000 ||
6948 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
6949 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
6950 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6953 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6956 if (pipe_config
->has_dp_encoder
) {
6957 /* Use SSC source */
6959 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6962 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6964 } else { /* HDMI or VGA */
6965 /* Use bend source */
6967 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6970 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6974 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6975 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6976 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6977 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6978 coreclk
|= 0x01000000;
6979 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6981 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6982 mutex_unlock(&dev_priv
->dpio_lock
);
6985 static void chv_update_pll(struct intel_crtc
*crtc
,
6986 struct intel_crtc_state
*pipe_config
)
6988 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
6989 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
6991 if (crtc
->pipe
!= PIPE_A
)
6992 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6994 pipe_config
->dpll_hw_state
.dpll_md
=
6995 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6998 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6999 const struct intel_crtc_state
*pipe_config
)
7001 struct drm_device
*dev
= crtc
->base
.dev
;
7002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7003 int pipe
= crtc
->pipe
;
7004 int dpll_reg
= DPLL(crtc
->pipe
);
7005 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7006 u32 loopfilter
, tribuf_calcntr
;
7007 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7011 bestn
= pipe_config
->dpll
.n
;
7012 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7013 bestm1
= pipe_config
->dpll
.m1
;
7014 bestm2
= pipe_config
->dpll
.m2
>> 22;
7015 bestp1
= pipe_config
->dpll
.p1
;
7016 bestp2
= pipe_config
->dpll
.p2
;
7017 vco
= pipe_config
->dpll
.vco
;
7022 * Enable Refclk and SSC
7024 I915_WRITE(dpll_reg
,
7025 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7027 mutex_lock(&dev_priv
->dpio_lock
);
7029 /* p1 and p2 divider */
7030 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7031 5 << DPIO_CHV_S1_DIV_SHIFT
|
7032 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7033 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7034 1 << DPIO_CHV_K_DIV_SHIFT
);
7036 /* Feedback post-divider - m2 */
7037 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7039 /* Feedback refclk divider - n and m1 */
7040 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7041 DPIO_CHV_M1_DIV_BY_2
|
7042 1 << DPIO_CHV_N_DIV_SHIFT
);
7044 /* M2 fraction division */
7046 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7048 /* M2 fraction division enable */
7049 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7050 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7051 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7053 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7054 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7056 /* Program digital lock detect threshold */
7057 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7058 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7059 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7060 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7062 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7063 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7066 if (vco
== 5400000) {
7067 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7068 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7069 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7070 tribuf_calcntr
= 0x9;
7071 } else if (vco
<= 6200000) {
7072 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7073 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7074 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7075 tribuf_calcntr
= 0x9;
7076 } else if (vco
<= 6480000) {
7077 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7078 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7079 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7080 tribuf_calcntr
= 0x8;
7082 /* Not supported. Apply the same limits as in the max case */
7083 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7084 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7085 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7088 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7090 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7091 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7092 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7093 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7096 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7097 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7100 mutex_unlock(&dev_priv
->dpio_lock
);
7104 * vlv_force_pll_on - forcibly enable just the PLL
7105 * @dev_priv: i915 private structure
7106 * @pipe: pipe PLL to enable
7107 * @dpll: PLL configuration
7109 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7110 * in cases where we need the PLL enabled even when @pipe is not going to
7113 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7114 const struct dpll
*dpll
)
7116 struct intel_crtc
*crtc
=
7117 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7118 struct intel_crtc_state pipe_config
= {
7119 .base
.crtc
= &crtc
->base
,
7120 .pixel_multiplier
= 1,
7124 if (IS_CHERRYVIEW(dev
)) {
7125 chv_update_pll(crtc
, &pipe_config
);
7126 chv_prepare_pll(crtc
, &pipe_config
);
7127 chv_enable_pll(crtc
, &pipe_config
);
7129 vlv_update_pll(crtc
, &pipe_config
);
7130 vlv_prepare_pll(crtc
, &pipe_config
);
7131 vlv_enable_pll(crtc
, &pipe_config
);
7136 * vlv_force_pll_off - forcibly disable just the PLL
7137 * @dev_priv: i915 private structure
7138 * @pipe: pipe PLL to disable
7140 * Disable the PLL for @pipe. To be used in cases where we need
7141 * the PLL enabled even when @pipe is not going to be enabled.
7143 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7145 if (IS_CHERRYVIEW(dev
))
7146 chv_disable_pll(to_i915(dev
), pipe
);
7148 vlv_disable_pll(to_i915(dev
), pipe
);
7151 static void i9xx_update_pll(struct intel_crtc
*crtc
,
7152 struct intel_crtc_state
*crtc_state
,
7153 intel_clock_t
*reduced_clock
,
7156 struct drm_device
*dev
= crtc
->base
.dev
;
7157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7160 struct dpll
*clock
= &crtc_state
->dpll
;
7162 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7164 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7165 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7167 dpll
= DPLL_VGA_MODE_DIS
;
7169 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7170 dpll
|= DPLLB_MODE_LVDS
;
7172 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7174 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7175 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7176 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7180 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7182 if (crtc_state
->has_dp_encoder
)
7183 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7185 /* compute bitmask from p1 value */
7186 if (IS_PINEVIEW(dev
))
7187 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7189 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7190 if (IS_G4X(dev
) && reduced_clock
)
7191 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7193 switch (clock
->p2
) {
7195 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7198 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7201 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7204 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7207 if (INTEL_INFO(dev
)->gen
>= 4)
7208 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7210 if (crtc_state
->sdvo_tv_clock
)
7211 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7212 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7213 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7214 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7216 dpll
|= PLL_REF_INPUT_DREFCLK
;
7218 dpll
|= DPLL_VCO_ENABLE
;
7219 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7221 if (INTEL_INFO(dev
)->gen
>= 4) {
7222 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7223 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7224 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7228 static void i8xx_update_pll(struct intel_crtc
*crtc
,
7229 struct intel_crtc_state
*crtc_state
,
7230 intel_clock_t
*reduced_clock
,
7233 struct drm_device
*dev
= crtc
->base
.dev
;
7234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7236 struct dpll
*clock
= &crtc_state
->dpll
;
7238 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7240 dpll
= DPLL_VGA_MODE_DIS
;
7242 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7243 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7246 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7248 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7250 dpll
|= PLL_P2_DIVIDE_BY_4
;
7253 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7254 dpll
|= DPLL_DVO_2X_MODE
;
7256 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7257 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7258 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7260 dpll
|= PLL_REF_INPUT_DREFCLK
;
7262 dpll
|= DPLL_VCO_ENABLE
;
7263 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7266 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7268 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7270 enum pipe pipe
= intel_crtc
->pipe
;
7271 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7272 struct drm_display_mode
*adjusted_mode
=
7273 &intel_crtc
->config
->base
.adjusted_mode
;
7274 uint32_t crtc_vtotal
, crtc_vblank_end
;
7277 /* We need to be careful not to changed the adjusted mode, for otherwise
7278 * the hw state checker will get angry at the mismatch. */
7279 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7280 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7282 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7283 /* the chip adds 2 halflines automatically */
7285 crtc_vblank_end
-= 1;
7287 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7288 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7290 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7291 adjusted_mode
->crtc_htotal
/ 2;
7293 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7296 if (INTEL_INFO(dev
)->gen
> 3)
7297 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7299 I915_WRITE(HTOTAL(cpu_transcoder
),
7300 (adjusted_mode
->crtc_hdisplay
- 1) |
7301 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7302 I915_WRITE(HBLANK(cpu_transcoder
),
7303 (adjusted_mode
->crtc_hblank_start
- 1) |
7304 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7305 I915_WRITE(HSYNC(cpu_transcoder
),
7306 (adjusted_mode
->crtc_hsync_start
- 1) |
7307 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7309 I915_WRITE(VTOTAL(cpu_transcoder
),
7310 (adjusted_mode
->crtc_vdisplay
- 1) |
7311 ((crtc_vtotal
- 1) << 16));
7312 I915_WRITE(VBLANK(cpu_transcoder
),
7313 (adjusted_mode
->crtc_vblank_start
- 1) |
7314 ((crtc_vblank_end
- 1) << 16));
7315 I915_WRITE(VSYNC(cpu_transcoder
),
7316 (adjusted_mode
->crtc_vsync_start
- 1) |
7317 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7319 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7320 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7321 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7323 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7324 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7325 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7327 /* pipesrc controls the size that is scaled from, which should
7328 * always be the user's requested size.
7330 I915_WRITE(PIPESRC(pipe
),
7331 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7332 (intel_crtc
->config
->pipe_src_h
- 1));
7335 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7336 struct intel_crtc_state
*pipe_config
)
7338 struct drm_device
*dev
= crtc
->base
.dev
;
7339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7340 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7343 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7344 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7345 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7346 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7347 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7348 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7349 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7350 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7351 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7353 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7354 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7355 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7356 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7357 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7358 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7359 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7360 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7361 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7363 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7364 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7365 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7366 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7369 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7370 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7371 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7373 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7374 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7377 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7378 struct intel_crtc_state
*pipe_config
)
7380 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7381 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7382 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7383 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7385 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7386 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7387 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7388 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7390 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7392 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7393 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7396 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7398 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7399 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7404 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7405 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7406 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7408 if (intel_crtc
->config
->double_wide
)
7409 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7411 /* only g4x and later have fancy bpc/dither controls */
7412 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7413 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7414 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7415 pipeconf
|= PIPECONF_DITHER_EN
|
7416 PIPECONF_DITHER_TYPE_SP
;
7418 switch (intel_crtc
->config
->pipe_bpp
) {
7420 pipeconf
|= PIPECONF_6BPC
;
7423 pipeconf
|= PIPECONF_8BPC
;
7426 pipeconf
|= PIPECONF_10BPC
;
7429 /* Case prevented by intel_choose_pipe_bpp_dither. */
7434 if (HAS_PIPE_CXSR(dev
)) {
7435 if (intel_crtc
->lowfreq_avail
) {
7436 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7437 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7439 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7443 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7444 if (INTEL_INFO(dev
)->gen
< 4 ||
7445 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7446 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7448 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7450 pipeconf
|= PIPECONF_PROGRESSIVE
;
7452 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7453 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7455 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7456 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7459 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7460 struct intel_crtc_state
*crtc_state
)
7462 struct drm_device
*dev
= crtc
->base
.dev
;
7463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7464 int refclk
, num_connectors
= 0;
7465 intel_clock_t clock
, reduced_clock
;
7466 bool ok
, has_reduced_clock
= false;
7467 bool is_lvds
= false, is_dsi
= false;
7468 struct intel_encoder
*encoder
;
7469 const intel_limit_t
*limit
;
7470 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7471 struct drm_connector
*connector
;
7472 struct drm_connector_state
*connector_state
;
7475 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7476 if (connector_state
->crtc
!= &crtc
->base
)
7479 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7481 switch (encoder
->type
) {
7482 case INTEL_OUTPUT_LVDS
:
7485 case INTEL_OUTPUT_DSI
:
7498 if (!crtc_state
->clock_set
) {
7499 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7502 * Returns a set of divisors for the desired target clock with
7503 * the given refclk, or FALSE. The returned values represent
7504 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7507 limit
= intel_limit(crtc_state
, refclk
);
7508 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7509 crtc_state
->port_clock
,
7510 refclk
, NULL
, &clock
);
7512 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7516 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7518 * Ensure we match the reduced clock's P to the target
7519 * clock. If the clocks don't match, we can't switch
7520 * the display clock by using the FP0/FP1. In such case
7521 * we will disable the LVDS downclock feature.
7524 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7525 dev_priv
->lvds_downclock
,
7529 /* Compat-code for transition, will disappear. */
7530 crtc_state
->dpll
.n
= clock
.n
;
7531 crtc_state
->dpll
.m1
= clock
.m1
;
7532 crtc_state
->dpll
.m2
= clock
.m2
;
7533 crtc_state
->dpll
.p1
= clock
.p1
;
7534 crtc_state
->dpll
.p2
= clock
.p2
;
7538 i8xx_update_pll(crtc
, crtc_state
,
7539 has_reduced_clock
? &reduced_clock
: NULL
,
7541 } else if (IS_CHERRYVIEW(dev
)) {
7542 chv_update_pll(crtc
, crtc_state
);
7543 } else if (IS_VALLEYVIEW(dev
)) {
7544 vlv_update_pll(crtc
, crtc_state
);
7546 i9xx_update_pll(crtc
, crtc_state
,
7547 has_reduced_clock
? &reduced_clock
: NULL
,
7554 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7555 struct intel_crtc_state
*pipe_config
)
7557 struct drm_device
*dev
= crtc
->base
.dev
;
7558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7561 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7564 tmp
= I915_READ(PFIT_CONTROL
);
7565 if (!(tmp
& PFIT_ENABLE
))
7568 /* Check whether the pfit is attached to our pipe. */
7569 if (INTEL_INFO(dev
)->gen
< 4) {
7570 if (crtc
->pipe
!= PIPE_B
)
7573 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7577 pipe_config
->gmch_pfit
.control
= tmp
;
7578 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7579 if (INTEL_INFO(dev
)->gen
< 5)
7580 pipe_config
->gmch_pfit
.lvds_border_bits
=
7581 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7584 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7585 struct intel_crtc_state
*pipe_config
)
7587 struct drm_device
*dev
= crtc
->base
.dev
;
7588 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7589 int pipe
= pipe_config
->cpu_transcoder
;
7590 intel_clock_t clock
;
7592 int refclk
= 100000;
7594 /* In case of MIPI DPLL will not even be used */
7595 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7598 mutex_lock(&dev_priv
->dpio_lock
);
7599 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7600 mutex_unlock(&dev_priv
->dpio_lock
);
7602 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7603 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7604 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7605 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7606 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7608 vlv_clock(refclk
, &clock
);
7610 /* clock.dot is the fast clock */
7611 pipe_config
->port_clock
= clock
.dot
/ 5;
7615 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7616 struct intel_initial_plane_config
*plane_config
)
7618 struct drm_device
*dev
= crtc
->base
.dev
;
7619 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7620 u32 val
, base
, offset
;
7621 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7622 int fourcc
, pixel_format
;
7623 unsigned int aligned_height
;
7624 struct drm_framebuffer
*fb
;
7625 struct intel_framebuffer
*intel_fb
;
7627 val
= I915_READ(DSPCNTR(plane
));
7628 if (!(val
& DISPLAY_PLANE_ENABLE
))
7631 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7633 DRM_DEBUG_KMS("failed to alloc fb\n");
7637 fb
= &intel_fb
->base
;
7639 if (INTEL_INFO(dev
)->gen
>= 4) {
7640 if (val
& DISPPLANE_TILED
) {
7641 plane_config
->tiling
= I915_TILING_X
;
7642 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7646 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7647 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7648 fb
->pixel_format
= fourcc
;
7649 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7651 if (INTEL_INFO(dev
)->gen
>= 4) {
7652 if (plane_config
->tiling
)
7653 offset
= I915_READ(DSPTILEOFF(plane
));
7655 offset
= I915_READ(DSPLINOFF(plane
));
7656 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7658 base
= I915_READ(DSPADDR(plane
));
7660 plane_config
->base
= base
;
7662 val
= I915_READ(PIPESRC(pipe
));
7663 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7664 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7666 val
= I915_READ(DSPSTRIDE(pipe
));
7667 fb
->pitches
[0] = val
& 0xffffffc0;
7669 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7673 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7675 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7676 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7677 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7678 plane_config
->size
);
7680 plane_config
->fb
= intel_fb
;
7683 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7684 struct intel_crtc_state
*pipe_config
)
7686 struct drm_device
*dev
= crtc
->base
.dev
;
7687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7688 int pipe
= pipe_config
->cpu_transcoder
;
7689 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7690 intel_clock_t clock
;
7691 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
7692 int refclk
= 100000;
7694 mutex_lock(&dev_priv
->dpio_lock
);
7695 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7696 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7697 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7698 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7699 mutex_unlock(&dev_priv
->dpio_lock
);
7701 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7702 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
7703 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7704 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7705 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7707 chv_clock(refclk
, &clock
);
7709 /* clock.dot is the fast clock */
7710 pipe_config
->port_clock
= clock
.dot
/ 5;
7713 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7714 struct intel_crtc_state
*pipe_config
)
7716 struct drm_device
*dev
= crtc
->base
.dev
;
7717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7720 if (!intel_display_power_is_enabled(dev_priv
,
7721 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7724 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7725 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7727 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7728 if (!(tmp
& PIPECONF_ENABLE
))
7731 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7732 switch (tmp
& PIPECONF_BPC_MASK
) {
7734 pipe_config
->pipe_bpp
= 18;
7737 pipe_config
->pipe_bpp
= 24;
7739 case PIPECONF_10BPC
:
7740 pipe_config
->pipe_bpp
= 30;
7747 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7748 pipe_config
->limited_color_range
= true;
7750 if (INTEL_INFO(dev
)->gen
< 4)
7751 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7753 intel_get_pipe_timings(crtc
, pipe_config
);
7755 i9xx_get_pfit_config(crtc
, pipe_config
);
7757 if (INTEL_INFO(dev
)->gen
>= 4) {
7758 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7759 pipe_config
->pixel_multiplier
=
7760 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7761 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7762 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7763 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7764 tmp
= I915_READ(DPLL(crtc
->pipe
));
7765 pipe_config
->pixel_multiplier
=
7766 ((tmp
& SDVO_MULTIPLIER_MASK
)
7767 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7769 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7770 * port and will be fixed up in the encoder->get_config
7772 pipe_config
->pixel_multiplier
= 1;
7774 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7775 if (!IS_VALLEYVIEW(dev
)) {
7777 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7778 * on 830. Filter it out here so that we don't
7779 * report errors due to that.
7782 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7784 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7785 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7787 /* Mask out read-only status bits. */
7788 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7789 DPLL_PORTC_READY_MASK
|
7790 DPLL_PORTB_READY_MASK
);
7793 if (IS_CHERRYVIEW(dev
))
7794 chv_crtc_clock_get(crtc
, pipe_config
);
7795 else if (IS_VALLEYVIEW(dev
))
7796 vlv_crtc_clock_get(crtc
, pipe_config
);
7798 i9xx_crtc_clock_get(crtc
, pipe_config
);
7803 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
7805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7806 struct intel_encoder
*encoder
;
7808 bool has_lvds
= false;
7809 bool has_cpu_edp
= false;
7810 bool has_panel
= false;
7811 bool has_ck505
= false;
7812 bool can_ssc
= false;
7814 /* We need to take the global config into account */
7815 for_each_intel_encoder(dev
, encoder
) {
7816 switch (encoder
->type
) {
7817 case INTEL_OUTPUT_LVDS
:
7821 case INTEL_OUTPUT_EDP
:
7823 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
7831 if (HAS_PCH_IBX(dev
)) {
7832 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
7833 can_ssc
= has_ck505
;
7839 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7840 has_panel
, has_lvds
, has_ck505
);
7842 /* Ironlake: try to setup display ref clock before DPLL
7843 * enabling. This is only under driver's control after
7844 * PCH B stepping, previous chipset stepping should be
7845 * ignoring this setting.
7847 val
= I915_READ(PCH_DREF_CONTROL
);
7849 /* As we must carefully and slowly disable/enable each source in turn,
7850 * compute the final state we want first and check if we need to
7851 * make any changes at all.
7854 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7856 final
|= DREF_NONSPREAD_CK505_ENABLE
;
7858 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7860 final
&= ~DREF_SSC_SOURCE_MASK
;
7861 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7862 final
&= ~DREF_SSC1_ENABLE
;
7865 final
|= DREF_SSC_SOURCE_ENABLE
;
7867 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7868 final
|= DREF_SSC1_ENABLE
;
7871 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7872 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7874 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7876 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7878 final
|= DREF_SSC_SOURCE_DISABLE
;
7879 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7885 /* Always enable nonspread source */
7886 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7889 val
|= DREF_NONSPREAD_CK505_ENABLE
;
7891 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7894 val
&= ~DREF_SSC_SOURCE_MASK
;
7895 val
|= DREF_SSC_SOURCE_ENABLE
;
7897 /* SSC must be turned on before enabling the CPU output */
7898 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7899 DRM_DEBUG_KMS("Using SSC on panel\n");
7900 val
|= DREF_SSC1_ENABLE
;
7902 val
&= ~DREF_SSC1_ENABLE
;
7904 /* Get SSC going before enabling the outputs */
7905 I915_WRITE(PCH_DREF_CONTROL
, val
);
7906 POSTING_READ(PCH_DREF_CONTROL
);
7909 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7911 /* Enable CPU source on CPU attached eDP */
7913 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7914 DRM_DEBUG_KMS("Using SSC on eDP\n");
7915 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7917 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7919 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7921 I915_WRITE(PCH_DREF_CONTROL
, val
);
7922 POSTING_READ(PCH_DREF_CONTROL
);
7925 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7927 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7929 /* Turn off CPU output */
7930 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7932 I915_WRITE(PCH_DREF_CONTROL
, val
);
7933 POSTING_READ(PCH_DREF_CONTROL
);
7936 /* Turn off the SSC source */
7937 val
&= ~DREF_SSC_SOURCE_MASK
;
7938 val
|= DREF_SSC_SOURCE_DISABLE
;
7941 val
&= ~DREF_SSC1_ENABLE
;
7943 I915_WRITE(PCH_DREF_CONTROL
, val
);
7944 POSTING_READ(PCH_DREF_CONTROL
);
7948 BUG_ON(val
!= final
);
7951 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7955 tmp
= I915_READ(SOUTH_CHICKEN2
);
7956 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7957 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7959 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
7960 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7961 DRM_ERROR("FDI mPHY reset assert timeout\n");
7963 tmp
= I915_READ(SOUTH_CHICKEN2
);
7964 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7965 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7967 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
7968 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7969 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7972 /* WaMPhyProgramming:hsw */
7973 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7977 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7978 tmp
&= ~(0xFF << 24);
7979 tmp
|= (0x12 << 24);
7980 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7982 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7984 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7986 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
7988 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
7990 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
7991 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7992 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
7994 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
7995 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7996 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
7998 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8001 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8003 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8006 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8008 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8011 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8013 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8016 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8018 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8019 tmp
&= ~(0xFF << 16);
8020 tmp
|= (0x1C << 16);
8021 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8023 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8024 tmp
&= ~(0xFF << 16);
8025 tmp
|= (0x1C << 16);
8026 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8028 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8030 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8032 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8034 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8036 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8037 tmp
&= ~(0xF << 28);
8039 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8041 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8042 tmp
&= ~(0xF << 28);
8044 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8047 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8048 * Programming" based on the parameters passed:
8049 * - Sequence to enable CLKOUT_DP
8050 * - Sequence to enable CLKOUT_DP without spread
8051 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8053 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8059 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8061 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
8062 with_fdi
, "LP PCH doesn't have FDI\n"))
8065 mutex_lock(&dev_priv
->dpio_lock
);
8067 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8068 tmp
&= ~SBI_SSCCTL_DISABLE
;
8069 tmp
|= SBI_SSCCTL_PATHALT
;
8070 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8075 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8076 tmp
&= ~SBI_SSCCTL_PATHALT
;
8077 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8080 lpt_reset_fdi_mphy(dev_priv
);
8081 lpt_program_fdi_mphy(dev_priv
);
8085 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8086 SBI_GEN0
: SBI_DBUFF0
;
8087 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8088 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8089 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8091 mutex_unlock(&dev_priv
->dpio_lock
);
8094 /* Sequence to disable CLKOUT_DP */
8095 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8100 mutex_lock(&dev_priv
->dpio_lock
);
8102 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
8103 SBI_GEN0
: SBI_DBUFF0
;
8104 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8105 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8106 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8108 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8109 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8110 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8111 tmp
|= SBI_SSCCTL_PATHALT
;
8112 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8115 tmp
|= SBI_SSCCTL_DISABLE
;
8116 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8119 mutex_unlock(&dev_priv
->dpio_lock
);
8122 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8124 struct intel_encoder
*encoder
;
8125 bool has_vga
= false;
8127 for_each_intel_encoder(dev
, encoder
) {
8128 switch (encoder
->type
) {
8129 case INTEL_OUTPUT_ANALOG
:
8138 lpt_enable_clkout_dp(dev
, true, true);
8140 lpt_disable_clkout_dp(dev
);
8144 * Initialize reference clocks when the driver loads
8146 void intel_init_pch_refclk(struct drm_device
*dev
)
8148 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8149 ironlake_init_pch_refclk(dev
);
8150 else if (HAS_PCH_LPT(dev
))
8151 lpt_init_pch_refclk(dev
);
8154 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8156 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8157 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8158 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8159 struct drm_connector
*connector
;
8160 struct drm_connector_state
*connector_state
;
8161 struct intel_encoder
*encoder
;
8162 int num_connectors
= 0, i
;
8163 bool is_lvds
= false;
8165 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8166 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8169 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8171 switch (encoder
->type
) {
8172 case INTEL_OUTPUT_LVDS
:
8181 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8182 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8183 dev_priv
->vbt
.lvds_ssc_freq
);
8184 return dev_priv
->vbt
.lvds_ssc_freq
;
8190 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8192 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8194 int pipe
= intel_crtc
->pipe
;
8199 switch (intel_crtc
->config
->pipe_bpp
) {
8201 val
|= PIPECONF_6BPC
;
8204 val
|= PIPECONF_8BPC
;
8207 val
|= PIPECONF_10BPC
;
8210 val
|= PIPECONF_12BPC
;
8213 /* Case prevented by intel_choose_pipe_bpp_dither. */
8217 if (intel_crtc
->config
->dither
)
8218 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8220 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8221 val
|= PIPECONF_INTERLACED_ILK
;
8223 val
|= PIPECONF_PROGRESSIVE
;
8225 if (intel_crtc
->config
->limited_color_range
)
8226 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8228 I915_WRITE(PIPECONF(pipe
), val
);
8229 POSTING_READ(PIPECONF(pipe
));
8233 * Set up the pipe CSC unit.
8235 * Currently only full range RGB to limited range RGB conversion
8236 * is supported, but eventually this should handle various
8237 * RGB<->YCbCr scenarios as well.
8239 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8241 struct drm_device
*dev
= crtc
->dev
;
8242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8243 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8244 int pipe
= intel_crtc
->pipe
;
8245 uint16_t coeff
= 0x7800; /* 1.0 */
8248 * TODO: Check what kind of values actually come out of the pipe
8249 * with these coeff/postoff values and adjust to get the best
8250 * accuracy. Perhaps we even need to take the bpc value into
8254 if (intel_crtc
->config
->limited_color_range
)
8255 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8258 * GY/GU and RY/RU should be the other way around according
8259 * to BSpec, but reality doesn't agree. Just set them up in
8260 * a way that results in the correct picture.
8262 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8263 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8265 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8266 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8268 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8269 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8271 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8272 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8273 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8275 if (INTEL_INFO(dev
)->gen
> 6) {
8276 uint16_t postoff
= 0;
8278 if (intel_crtc
->config
->limited_color_range
)
8279 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8281 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8282 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8283 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8285 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8287 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8289 if (intel_crtc
->config
->limited_color_range
)
8290 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8292 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8296 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8298 struct drm_device
*dev
= crtc
->dev
;
8299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8301 enum pipe pipe
= intel_crtc
->pipe
;
8302 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8307 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8308 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8310 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8311 val
|= PIPECONF_INTERLACED_ILK
;
8313 val
|= PIPECONF_PROGRESSIVE
;
8315 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8316 POSTING_READ(PIPECONF(cpu_transcoder
));
8318 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8319 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8321 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8324 switch (intel_crtc
->config
->pipe_bpp
) {
8326 val
|= PIPEMISC_DITHER_6_BPC
;
8329 val
|= PIPEMISC_DITHER_8_BPC
;
8332 val
|= PIPEMISC_DITHER_10_BPC
;
8335 val
|= PIPEMISC_DITHER_12_BPC
;
8338 /* Case prevented by pipe_config_set_bpp. */
8342 if (intel_crtc
->config
->dither
)
8343 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8345 I915_WRITE(PIPEMISC(pipe
), val
);
8349 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8350 struct intel_crtc_state
*crtc_state
,
8351 intel_clock_t
*clock
,
8352 bool *has_reduced_clock
,
8353 intel_clock_t
*reduced_clock
)
8355 struct drm_device
*dev
= crtc
->dev
;
8356 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8358 const intel_limit_t
*limit
;
8359 bool ret
, is_lvds
= false;
8361 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
8363 refclk
= ironlake_get_refclk(crtc_state
);
8366 * Returns a set of divisors for the desired target clock with the given
8367 * refclk, or FALSE. The returned values represent the clock equation:
8368 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8370 limit
= intel_limit(crtc_state
, refclk
);
8371 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8372 crtc_state
->port_clock
,
8373 refclk
, NULL
, clock
);
8377 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
8379 * Ensure we match the reduced clock's P to the target clock.
8380 * If the clocks don't match, we can't switch the display clock
8381 * by using the FP0/FP1. In such case we will disable the LVDS
8382 * downclock feature.
8384 *has_reduced_clock
=
8385 dev_priv
->display
.find_dpll(limit
, crtc_state
,
8386 dev_priv
->lvds_downclock
,
8394 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8397 * Account for spread spectrum to avoid
8398 * oversubscribing the link. Max center spread
8399 * is 2.5%; use 5% for safety's sake.
8401 u32 bps
= target_clock
* bpp
* 21 / 20;
8402 return DIV_ROUND_UP(bps
, link_bw
* 8);
8405 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8407 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8410 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8411 struct intel_crtc_state
*crtc_state
,
8413 intel_clock_t
*reduced_clock
, u32
*fp2
)
8415 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8416 struct drm_device
*dev
= crtc
->dev
;
8417 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8418 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8419 struct drm_connector
*connector
;
8420 struct drm_connector_state
*connector_state
;
8421 struct intel_encoder
*encoder
;
8423 int factor
, num_connectors
= 0, i
;
8424 bool is_lvds
= false, is_sdvo
= false;
8426 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8427 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8430 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8432 switch (encoder
->type
) {
8433 case INTEL_OUTPUT_LVDS
:
8436 case INTEL_OUTPUT_SDVO
:
8437 case INTEL_OUTPUT_HDMI
:
8447 /* Enable autotuning of the PLL clock (if permissible) */
8450 if ((intel_panel_use_ssc(dev_priv
) &&
8451 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8452 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8454 } else if (crtc_state
->sdvo_tv_clock
)
8457 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8460 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8466 dpll
|= DPLLB_MODE_LVDS
;
8468 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8470 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8471 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8474 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8475 if (crtc_state
->has_dp_encoder
)
8476 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8478 /* compute bitmask from p1 value */
8479 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8481 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8483 switch (crtc_state
->dpll
.p2
) {
8485 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8488 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8491 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8494 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8498 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8499 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8501 dpll
|= PLL_REF_INPUT_DREFCLK
;
8503 return dpll
| DPLL_VCO_ENABLE
;
8506 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8507 struct intel_crtc_state
*crtc_state
)
8509 struct drm_device
*dev
= crtc
->base
.dev
;
8510 intel_clock_t clock
, reduced_clock
;
8511 u32 dpll
= 0, fp
= 0, fp2
= 0;
8512 bool ok
, has_reduced_clock
= false;
8513 bool is_lvds
= false;
8514 struct intel_shared_dpll
*pll
;
8516 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8518 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8519 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8521 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8522 &has_reduced_clock
, &reduced_clock
);
8523 if (!ok
&& !crtc_state
->clock_set
) {
8524 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8527 /* Compat-code for transition, will disappear. */
8528 if (!crtc_state
->clock_set
) {
8529 crtc_state
->dpll
.n
= clock
.n
;
8530 crtc_state
->dpll
.m1
= clock
.m1
;
8531 crtc_state
->dpll
.m2
= clock
.m2
;
8532 crtc_state
->dpll
.p1
= clock
.p1
;
8533 crtc_state
->dpll
.p2
= clock
.p2
;
8536 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8537 if (crtc_state
->has_pch_encoder
) {
8538 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8539 if (has_reduced_clock
)
8540 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8542 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8543 &fp
, &reduced_clock
,
8544 has_reduced_clock
? &fp2
: NULL
);
8546 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8547 crtc_state
->dpll_hw_state
.fp0
= fp
;
8548 if (has_reduced_clock
)
8549 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8551 crtc_state
->dpll_hw_state
.fp1
= fp
;
8553 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8555 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8556 pipe_name(crtc
->pipe
));
8561 if (is_lvds
&& has_reduced_clock
)
8562 crtc
->lowfreq_avail
= true;
8564 crtc
->lowfreq_avail
= false;
8569 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8570 struct intel_link_m_n
*m_n
)
8572 struct drm_device
*dev
= crtc
->base
.dev
;
8573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8574 enum pipe pipe
= crtc
->pipe
;
8576 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8577 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8578 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8580 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8581 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8582 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8585 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8586 enum transcoder transcoder
,
8587 struct intel_link_m_n
*m_n
,
8588 struct intel_link_m_n
*m2_n2
)
8590 struct drm_device
*dev
= crtc
->base
.dev
;
8591 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8592 enum pipe pipe
= crtc
->pipe
;
8594 if (INTEL_INFO(dev
)->gen
>= 5) {
8595 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8596 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8597 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8599 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8600 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8601 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8602 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8603 * gen < 8) and if DRRS is supported (to make sure the
8604 * registers are not unnecessarily read).
8606 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8607 crtc
->config
->has_drrs
) {
8608 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8609 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8610 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8612 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8613 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8614 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8617 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8618 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8619 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8621 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8622 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8623 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8627 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8628 struct intel_crtc_state
*pipe_config
)
8630 if (pipe_config
->has_pch_encoder
)
8631 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8633 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8634 &pipe_config
->dp_m_n
,
8635 &pipe_config
->dp_m2_n2
);
8638 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8639 struct intel_crtc_state
*pipe_config
)
8641 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8642 &pipe_config
->fdi_m_n
, NULL
);
8645 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8646 struct intel_crtc_state
*pipe_config
)
8648 struct drm_device
*dev
= crtc
->base
.dev
;
8649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8650 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
8651 uint32_t ps_ctrl
= 0;
8655 /* find scaler attached to this pipe */
8656 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
8657 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
8658 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
8660 pipe_config
->pch_pfit
.enabled
= true;
8661 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
8662 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
8667 scaler_state
->scaler_id
= id
;
8669 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
8671 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
8676 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8677 struct intel_initial_plane_config
*plane_config
)
8679 struct drm_device
*dev
= crtc
->base
.dev
;
8680 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8681 u32 val
, base
, offset
, stride_mult
, tiling
;
8682 int pipe
= crtc
->pipe
;
8683 int fourcc
, pixel_format
;
8684 unsigned int aligned_height
;
8685 struct drm_framebuffer
*fb
;
8686 struct intel_framebuffer
*intel_fb
;
8688 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8690 DRM_DEBUG_KMS("failed to alloc fb\n");
8694 fb
= &intel_fb
->base
;
8696 val
= I915_READ(PLANE_CTL(pipe
, 0));
8697 if (!(val
& PLANE_CTL_ENABLE
))
8700 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8701 fourcc
= skl_format_to_fourcc(pixel_format
,
8702 val
& PLANE_CTL_ORDER_RGBX
,
8703 val
& PLANE_CTL_ALPHA_MASK
);
8704 fb
->pixel_format
= fourcc
;
8705 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8707 tiling
= val
& PLANE_CTL_TILED_MASK
;
8709 case PLANE_CTL_TILED_LINEAR
:
8710 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
8712 case PLANE_CTL_TILED_X
:
8713 plane_config
->tiling
= I915_TILING_X
;
8714 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8716 case PLANE_CTL_TILED_Y
:
8717 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
8719 case PLANE_CTL_TILED_YF
:
8720 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
8723 MISSING_CASE(tiling
);
8727 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8728 plane_config
->base
= base
;
8730 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8732 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8733 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8734 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8736 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8737 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
8739 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8741 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8745 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8747 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8748 pipe_name(pipe
), fb
->width
, fb
->height
,
8749 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8750 plane_config
->size
);
8752 plane_config
->fb
= intel_fb
;
8759 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8760 struct intel_crtc_state
*pipe_config
)
8762 struct drm_device
*dev
= crtc
->base
.dev
;
8763 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8766 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8768 if (tmp
& PF_ENABLE
) {
8769 pipe_config
->pch_pfit
.enabled
= true;
8770 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8771 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8773 /* We currently do not free assignements of panel fitters on
8774 * ivb/hsw (since we don't use the higher upscaling modes which
8775 * differentiates them) so just WARN about this case for now. */
8777 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8778 PF_PIPE_SEL_IVB(crtc
->pipe
));
8784 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8785 struct intel_initial_plane_config
*plane_config
)
8787 struct drm_device
*dev
= crtc
->base
.dev
;
8788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8789 u32 val
, base
, offset
;
8790 int pipe
= crtc
->pipe
;
8791 int fourcc
, pixel_format
;
8792 unsigned int aligned_height
;
8793 struct drm_framebuffer
*fb
;
8794 struct intel_framebuffer
*intel_fb
;
8796 val
= I915_READ(DSPCNTR(pipe
));
8797 if (!(val
& DISPLAY_PLANE_ENABLE
))
8800 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8802 DRM_DEBUG_KMS("failed to alloc fb\n");
8806 fb
= &intel_fb
->base
;
8808 if (INTEL_INFO(dev
)->gen
>= 4) {
8809 if (val
& DISPPLANE_TILED
) {
8810 plane_config
->tiling
= I915_TILING_X
;
8811 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8815 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8816 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8817 fb
->pixel_format
= fourcc
;
8818 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8820 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
8821 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
8822 offset
= I915_READ(DSPOFFSET(pipe
));
8824 if (plane_config
->tiling
)
8825 offset
= I915_READ(DSPTILEOFF(pipe
));
8827 offset
= I915_READ(DSPLINOFF(pipe
));
8829 plane_config
->base
= base
;
8831 val
= I915_READ(PIPESRC(pipe
));
8832 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8833 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8835 val
= I915_READ(DSPSTRIDE(pipe
));
8836 fb
->pitches
[0] = val
& 0xffffffc0;
8838 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8842 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8844 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8845 pipe_name(pipe
), fb
->width
, fb
->height
,
8846 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8847 plane_config
->size
);
8849 plane_config
->fb
= intel_fb
;
8852 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
8853 struct intel_crtc_state
*pipe_config
)
8855 struct drm_device
*dev
= crtc
->base
.dev
;
8856 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8859 if (!intel_display_power_is_enabled(dev_priv
,
8860 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8863 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8864 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8866 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8867 if (!(tmp
& PIPECONF_ENABLE
))
8870 switch (tmp
& PIPECONF_BPC_MASK
) {
8872 pipe_config
->pipe_bpp
= 18;
8875 pipe_config
->pipe_bpp
= 24;
8877 case PIPECONF_10BPC
:
8878 pipe_config
->pipe_bpp
= 30;
8880 case PIPECONF_12BPC
:
8881 pipe_config
->pipe_bpp
= 36;
8887 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
8888 pipe_config
->limited_color_range
= true;
8890 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
8891 struct intel_shared_dpll
*pll
;
8893 pipe_config
->has_pch_encoder
= true;
8895 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
8896 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8897 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8899 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8901 if (HAS_PCH_IBX(dev_priv
->dev
)) {
8902 pipe_config
->shared_dpll
=
8903 (enum intel_dpll_id
) crtc
->pipe
;
8905 tmp
= I915_READ(PCH_DPLL_SEL
);
8906 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
8907 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
8909 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
8912 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8914 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8915 &pipe_config
->dpll_hw_state
));
8917 tmp
= pipe_config
->dpll_hw_state
.dpll
;
8918 pipe_config
->pixel_multiplier
=
8919 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
8920 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
8922 ironlake_pch_clock_get(crtc
, pipe_config
);
8924 pipe_config
->pixel_multiplier
= 1;
8927 intel_get_pipe_timings(crtc
, pipe_config
);
8929 ironlake_get_pfit_config(crtc
, pipe_config
);
8934 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8936 struct drm_device
*dev
= dev_priv
->dev
;
8937 struct intel_crtc
*crtc
;
8939 for_each_intel_crtc(dev
, crtc
)
8940 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8941 pipe_name(crtc
->pipe
));
8943 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
8944 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8945 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8946 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8947 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
8948 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8949 "CPU PWM1 enabled\n");
8950 if (IS_HASWELL(dev
))
8951 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8952 "CPU PWM2 enabled\n");
8953 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8954 "PCH PWM1 enabled\n");
8955 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8956 "Utility pin enabled\n");
8957 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8960 * In theory we can still leave IRQs enabled, as long as only the HPD
8961 * interrupts remain enabled. We used to check for that, but since it's
8962 * gen-specific and since we only disable LCPLL after we fully disable
8963 * the interrupts, the check below should be enough.
8965 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8968 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8970 struct drm_device
*dev
= dev_priv
->dev
;
8972 if (IS_HASWELL(dev
))
8973 return I915_READ(D_COMP_HSW
);
8975 return I915_READ(D_COMP_BDW
);
8978 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8980 struct drm_device
*dev
= dev_priv
->dev
;
8982 if (IS_HASWELL(dev
)) {
8983 mutex_lock(&dev_priv
->rps
.hw_lock
);
8984 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8986 DRM_ERROR("Failed to write to D_COMP\n");
8987 mutex_unlock(&dev_priv
->rps
.hw_lock
);
8989 I915_WRITE(D_COMP_BDW
, val
);
8990 POSTING_READ(D_COMP_BDW
);
8995 * This function implements pieces of two sequences from BSpec:
8996 * - Sequence for display software to disable LCPLL
8997 * - Sequence for display software to allow package C8+
8998 * The steps implemented here are just the steps that actually touch the LCPLL
8999 * register. Callers should take care of disabling all the display engine
9000 * functions, doing the mode unset, fixing interrupts, etc.
9002 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9003 bool switch_to_fclk
, bool allow_power_down
)
9007 assert_can_disable_lcpll(dev_priv
);
9009 val
= I915_READ(LCPLL_CTL
);
9011 if (switch_to_fclk
) {
9012 val
|= LCPLL_CD_SOURCE_FCLK
;
9013 I915_WRITE(LCPLL_CTL
, val
);
9015 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9016 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9017 DRM_ERROR("Switching to FCLK failed\n");
9019 val
= I915_READ(LCPLL_CTL
);
9022 val
|= LCPLL_PLL_DISABLE
;
9023 I915_WRITE(LCPLL_CTL
, val
);
9024 POSTING_READ(LCPLL_CTL
);
9026 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9027 DRM_ERROR("LCPLL still locked\n");
9029 val
= hsw_read_dcomp(dev_priv
);
9030 val
|= D_COMP_COMP_DISABLE
;
9031 hsw_write_dcomp(dev_priv
, val
);
9034 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9036 DRM_ERROR("D_COMP RCOMP still in progress\n");
9038 if (allow_power_down
) {
9039 val
= I915_READ(LCPLL_CTL
);
9040 val
|= LCPLL_POWER_DOWN_ALLOW
;
9041 I915_WRITE(LCPLL_CTL
, val
);
9042 POSTING_READ(LCPLL_CTL
);
9047 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9050 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9054 val
= I915_READ(LCPLL_CTL
);
9056 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9057 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9061 * Make sure we're not on PC8 state before disabling PC8, otherwise
9062 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9064 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9066 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9067 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9068 I915_WRITE(LCPLL_CTL
, val
);
9069 POSTING_READ(LCPLL_CTL
);
9072 val
= hsw_read_dcomp(dev_priv
);
9073 val
|= D_COMP_COMP_FORCE
;
9074 val
&= ~D_COMP_COMP_DISABLE
;
9075 hsw_write_dcomp(dev_priv
, val
);
9077 val
= I915_READ(LCPLL_CTL
);
9078 val
&= ~LCPLL_PLL_DISABLE
;
9079 I915_WRITE(LCPLL_CTL
, val
);
9081 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9082 DRM_ERROR("LCPLL not locked yet\n");
9084 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9085 val
= I915_READ(LCPLL_CTL
);
9086 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9087 I915_WRITE(LCPLL_CTL
, val
);
9089 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9090 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9091 DRM_ERROR("Switching back to LCPLL failed\n");
9094 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9098 * Package states C8 and deeper are really deep PC states that can only be
9099 * reached when all the devices on the system allow it, so even if the graphics
9100 * device allows PC8+, it doesn't mean the system will actually get to these
9101 * states. Our driver only allows PC8+ when going into runtime PM.
9103 * The requirements for PC8+ are that all the outputs are disabled, the power
9104 * well is disabled and most interrupts are disabled, and these are also
9105 * requirements for runtime PM. When these conditions are met, we manually do
9106 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9107 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9110 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9111 * the state of some registers, so when we come back from PC8+ we need to
9112 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9113 * need to take care of the registers kept by RC6. Notice that this happens even
9114 * if we don't put the device in PCI D3 state (which is what currently happens
9115 * because of the runtime PM support).
9117 * For more, read "Display Sequences for Package C8" on the hardware
9120 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9122 struct drm_device
*dev
= dev_priv
->dev
;
9125 DRM_DEBUG_KMS("Enabling package C8+\n");
9127 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9128 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9129 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9130 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9133 lpt_disable_clkout_dp(dev
);
9134 hsw_disable_lcpll(dev_priv
, true, true);
9137 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9139 struct drm_device
*dev
= dev_priv
->dev
;
9142 DRM_DEBUG_KMS("Disabling package C8+\n");
9144 hsw_restore_lcpll(dev_priv
);
9145 lpt_init_pch_refclk(dev
);
9147 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
9148 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9149 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9150 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9153 intel_prepare_ddi(dev
);
9156 static void broxton_modeset_global_resources(struct drm_atomic_state
*state
)
9158 struct drm_device
*dev
= state
->dev
;
9159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9160 int max_pixclk
= intel_mode_max_pixclk(state
);
9163 /* see the comment in valleyview_modeset_global_resources */
9164 if (WARN_ON(max_pixclk
< 0))
9167 req_cdclk
= broxton_calc_cdclk(dev_priv
, max_pixclk
);
9169 if (req_cdclk
!= dev_priv
->cdclk_freq
)
9170 broxton_set_cdclk(dev
, req_cdclk
);
9173 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9174 struct intel_crtc_state
*crtc_state
)
9176 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9179 crtc
->lowfreq_avail
= false;
9184 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9186 struct intel_crtc_state
*pipe_config
)
9190 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9191 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9194 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9195 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9198 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9199 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9202 DRM_ERROR("Incorrect port type\n");
9206 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9208 struct intel_crtc_state
*pipe_config
)
9210 u32 temp
, dpll_ctl1
;
9212 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9213 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9215 switch (pipe_config
->ddi_pll_sel
) {
9218 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9219 * of the shared DPLL framework and thus needs to be read out
9222 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9223 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9226 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9229 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9232 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9237 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9239 struct intel_crtc_state
*pipe_config
)
9241 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9243 switch (pipe_config
->ddi_pll_sel
) {
9244 case PORT_CLK_SEL_WRPLL1
:
9245 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9247 case PORT_CLK_SEL_WRPLL2
:
9248 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9253 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9254 struct intel_crtc_state
*pipe_config
)
9256 struct drm_device
*dev
= crtc
->base
.dev
;
9257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9258 struct intel_shared_dpll
*pll
;
9262 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9264 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9266 if (IS_SKYLAKE(dev
))
9267 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9268 else if (IS_BROXTON(dev
))
9269 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9271 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9273 if (pipe_config
->shared_dpll
>= 0) {
9274 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9276 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9277 &pipe_config
->dpll_hw_state
));
9281 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9282 * DDI E. So just check whether this pipe is wired to DDI E and whether
9283 * the PCH transcoder is on.
9285 if (INTEL_INFO(dev
)->gen
< 9 &&
9286 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9287 pipe_config
->has_pch_encoder
= true;
9289 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9290 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9291 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9293 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9297 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9298 struct intel_crtc_state
*pipe_config
)
9300 struct drm_device
*dev
= crtc
->base
.dev
;
9301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9302 enum intel_display_power_domain pfit_domain
;
9305 if (!intel_display_power_is_enabled(dev_priv
,
9306 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9309 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9310 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9312 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9313 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9314 enum pipe trans_edp_pipe
;
9315 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9317 WARN(1, "unknown pipe linked to edp transcoder\n");
9318 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9319 case TRANS_DDI_EDP_INPUT_A_ON
:
9320 trans_edp_pipe
= PIPE_A
;
9322 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9323 trans_edp_pipe
= PIPE_B
;
9325 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9326 trans_edp_pipe
= PIPE_C
;
9330 if (trans_edp_pipe
== crtc
->pipe
)
9331 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9334 if (!intel_display_power_is_enabled(dev_priv
,
9335 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9338 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9339 if (!(tmp
& PIPECONF_ENABLE
))
9342 haswell_get_ddi_port_state(crtc
, pipe_config
);
9344 intel_get_pipe_timings(crtc
, pipe_config
);
9346 if (INTEL_INFO(dev
)->gen
>= 9) {
9347 skl_init_scalers(dev
, crtc
, pipe_config
);
9350 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9351 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9352 if (INTEL_INFO(dev
)->gen
== 9)
9353 skylake_get_pfit_config(crtc
, pipe_config
);
9354 else if (INTEL_INFO(dev
)->gen
< 9)
9355 ironlake_get_pfit_config(crtc
, pipe_config
);
9357 MISSING_CASE(INTEL_INFO(dev
)->gen
);
9360 pipe_config
->scaler_state
.scaler_id
= -1;
9361 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9364 if (IS_HASWELL(dev
))
9365 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9366 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9368 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9369 pipe_config
->pixel_multiplier
=
9370 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9372 pipe_config
->pixel_multiplier
= 1;
9378 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9380 struct drm_device
*dev
= crtc
->dev
;
9381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9382 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9383 uint32_t cntl
= 0, size
= 0;
9386 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
9387 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
9388 unsigned int stride
= roundup_pow_of_two(width
) * 4;
9392 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9403 cntl
|= CURSOR_ENABLE
|
9404 CURSOR_GAMMA_ENABLE
|
9405 CURSOR_FORMAT_ARGB
|
9406 CURSOR_STRIDE(stride
);
9408 size
= (height
<< 12) | width
;
9411 if (intel_crtc
->cursor_cntl
!= 0 &&
9412 (intel_crtc
->cursor_base
!= base
||
9413 intel_crtc
->cursor_size
!= size
||
9414 intel_crtc
->cursor_cntl
!= cntl
)) {
9415 /* On these chipsets we can only modify the base/size/stride
9416 * whilst the cursor is disabled.
9418 I915_WRITE(_CURACNTR
, 0);
9419 POSTING_READ(_CURACNTR
);
9420 intel_crtc
->cursor_cntl
= 0;
9423 if (intel_crtc
->cursor_base
!= base
) {
9424 I915_WRITE(_CURABASE
, base
);
9425 intel_crtc
->cursor_base
= base
;
9428 if (intel_crtc
->cursor_size
!= size
) {
9429 I915_WRITE(CURSIZE
, size
);
9430 intel_crtc
->cursor_size
= size
;
9433 if (intel_crtc
->cursor_cntl
!= cntl
) {
9434 I915_WRITE(_CURACNTR
, cntl
);
9435 POSTING_READ(_CURACNTR
);
9436 intel_crtc
->cursor_cntl
= cntl
;
9440 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9442 struct drm_device
*dev
= crtc
->dev
;
9443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9444 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9445 int pipe
= intel_crtc
->pipe
;
9450 cntl
= MCURSOR_GAMMA_ENABLE
;
9451 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
9453 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9456 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9459 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9462 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
9465 cntl
|= pipe
<< 28; /* Connect to correct pipe */
9467 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
9468 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
9471 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
9472 cntl
|= CURSOR_ROTATE_180
;
9474 if (intel_crtc
->cursor_cntl
!= cntl
) {
9475 I915_WRITE(CURCNTR(pipe
), cntl
);
9476 POSTING_READ(CURCNTR(pipe
));
9477 intel_crtc
->cursor_cntl
= cntl
;
9480 /* and commit changes on next vblank */
9481 I915_WRITE(CURBASE(pipe
), base
);
9482 POSTING_READ(CURBASE(pipe
));
9484 intel_crtc
->cursor_base
= base
;
9487 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9488 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
9491 struct drm_device
*dev
= crtc
->dev
;
9492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9493 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9494 int pipe
= intel_crtc
->pipe
;
9495 int x
= crtc
->cursor_x
;
9496 int y
= crtc
->cursor_y
;
9497 u32 base
= 0, pos
= 0;
9500 base
= intel_crtc
->cursor_addr
;
9502 if (x
>= intel_crtc
->config
->pipe_src_w
)
9505 if (y
>= intel_crtc
->config
->pipe_src_h
)
9509 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
9512 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
9515 pos
|= x
<< CURSOR_X_SHIFT
;
9518 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
9521 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
9524 pos
|= y
<< CURSOR_Y_SHIFT
;
9526 if (base
== 0 && intel_crtc
->cursor_base
== 0)
9529 I915_WRITE(CURPOS(pipe
), pos
);
9531 /* ILK+ do this automagically */
9532 if (HAS_GMCH_DISPLAY(dev
) &&
9533 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
9534 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
9535 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
9538 if (IS_845G(dev
) || IS_I865G(dev
))
9539 i845_update_cursor(crtc
, base
);
9541 i9xx_update_cursor(crtc
, base
);
9544 static bool cursor_size_ok(struct drm_device
*dev
,
9545 uint32_t width
, uint32_t height
)
9547 if (width
== 0 || height
== 0)
9551 * 845g/865g are special in that they are only limited by
9552 * the width of their cursors, the height is arbitrary up to
9553 * the precision of the register. Everything else requires
9554 * square cursors, limited to a few power-of-two sizes.
9556 if (IS_845G(dev
) || IS_I865G(dev
)) {
9557 if ((width
& 63) != 0)
9560 if (width
> (IS_845G(dev
) ? 64 : 512))
9566 switch (width
| height
) {
9581 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
9582 u16
*blue
, uint32_t start
, uint32_t size
)
9584 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
9585 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9587 for (i
= start
; i
< end
; i
++) {
9588 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
9589 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
9590 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
9593 intel_crtc_load_lut(crtc
);
9596 /* VESA 640x480x72Hz mode to set on the pipe */
9597 static struct drm_display_mode load_detect_mode
= {
9598 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
9599 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
9602 struct drm_framebuffer
*
9603 __intel_framebuffer_create(struct drm_device
*dev
,
9604 struct drm_mode_fb_cmd2
*mode_cmd
,
9605 struct drm_i915_gem_object
*obj
)
9607 struct intel_framebuffer
*intel_fb
;
9610 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9612 drm_gem_object_unreference(&obj
->base
);
9613 return ERR_PTR(-ENOMEM
);
9616 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
9620 return &intel_fb
->base
;
9622 drm_gem_object_unreference(&obj
->base
);
9625 return ERR_PTR(ret
);
9628 static struct drm_framebuffer
*
9629 intel_framebuffer_create(struct drm_device
*dev
,
9630 struct drm_mode_fb_cmd2
*mode_cmd
,
9631 struct drm_i915_gem_object
*obj
)
9633 struct drm_framebuffer
*fb
;
9636 ret
= i915_mutex_lock_interruptible(dev
);
9638 return ERR_PTR(ret
);
9639 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
9640 mutex_unlock(&dev
->struct_mutex
);
9646 intel_framebuffer_pitch_for_width(int width
, int bpp
)
9648 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
9649 return ALIGN(pitch
, 64);
9653 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
9655 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9656 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9659 static struct drm_framebuffer
*
9660 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9661 struct drm_display_mode
*mode
,
9664 struct drm_i915_gem_object
*obj
;
9665 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9667 obj
= i915_gem_alloc_object(dev
,
9668 intel_framebuffer_size_for_mode(mode
, bpp
));
9670 return ERR_PTR(-ENOMEM
);
9672 mode_cmd
.width
= mode
->hdisplay
;
9673 mode_cmd
.height
= mode
->vdisplay
;
9674 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9676 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9678 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
9681 static struct drm_framebuffer
*
9682 mode_fits_in_fbdev(struct drm_device
*dev
,
9683 struct drm_display_mode
*mode
)
9685 #ifdef CONFIG_DRM_I915_FBDEV
9686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9687 struct drm_i915_gem_object
*obj
;
9688 struct drm_framebuffer
*fb
;
9690 if (!dev_priv
->fbdev
)
9693 if (!dev_priv
->fbdev
->fb
)
9696 obj
= dev_priv
->fbdev
->fb
->obj
;
9699 fb
= &dev_priv
->fbdev
->fb
->base
;
9700 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9701 fb
->bits_per_pixel
))
9704 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9713 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
9714 struct drm_display_mode
*mode
,
9715 struct intel_load_detect_pipe
*old
,
9716 struct drm_modeset_acquire_ctx
*ctx
)
9718 struct intel_crtc
*intel_crtc
;
9719 struct intel_encoder
*intel_encoder
=
9720 intel_attached_encoder(connector
);
9721 struct drm_crtc
*possible_crtc
;
9722 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9723 struct drm_crtc
*crtc
= NULL
;
9724 struct drm_device
*dev
= encoder
->dev
;
9725 struct drm_framebuffer
*fb
;
9726 struct drm_mode_config
*config
= &dev
->mode_config
;
9727 struct drm_atomic_state
*state
= NULL
;
9728 struct drm_connector_state
*connector_state
;
9729 struct intel_crtc_state
*crtc_state
;
9732 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9733 connector
->base
.id
, connector
->name
,
9734 encoder
->base
.id
, encoder
->name
);
9737 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
9742 * Algorithm gets a little messy:
9744 * - if the connector already has an assigned crtc, use it (but make
9745 * sure it's on first)
9747 * - try to find the first unused crtc that can drive this connector,
9748 * and use that if we find one
9751 /* See if we already have a CRTC for this connector */
9752 if (encoder
->crtc
) {
9753 crtc
= encoder
->crtc
;
9755 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9758 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9762 old
->dpms_mode
= connector
->dpms
;
9763 old
->load_detect_temp
= false;
9765 /* Make sure the crtc and connector are running */
9766 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
9767 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
9772 /* Find an unused one (if possible) */
9773 for_each_crtc(dev
, possible_crtc
) {
9775 if (!(encoder
->possible_crtcs
& (1 << i
)))
9777 if (possible_crtc
->state
->enable
)
9779 /* This can occur when applying the pipe A quirk on resume. */
9780 if (to_intel_crtc(possible_crtc
)->new_enabled
)
9783 crtc
= possible_crtc
;
9788 * If we didn't find an unused CRTC, don't use any.
9791 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9795 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9798 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9801 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
9802 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
9804 intel_crtc
= to_intel_crtc(crtc
);
9805 intel_crtc
->new_enabled
= true;
9806 old
->dpms_mode
= connector
->dpms
;
9807 old
->load_detect_temp
= true;
9808 old
->release_fb
= NULL
;
9810 state
= drm_atomic_state_alloc(dev
);
9814 state
->acquire_ctx
= ctx
;
9816 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9817 if (IS_ERR(connector_state
)) {
9818 ret
= PTR_ERR(connector_state
);
9822 connector_state
->crtc
= crtc
;
9823 connector_state
->best_encoder
= &intel_encoder
->base
;
9825 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9826 if (IS_ERR(crtc_state
)) {
9827 ret
= PTR_ERR(crtc_state
);
9831 crtc_state
->base
.enable
= true;
9834 mode
= &load_detect_mode
;
9836 /* We need a framebuffer large enough to accommodate all accesses
9837 * that the plane may generate whilst we perform load detection.
9838 * We can not rely on the fbcon either being present (we get called
9839 * during its initialisation to detect all boot displays, or it may
9840 * not even exist) or that it is large enough to satisfy the
9843 fb
= mode_fits_in_fbdev(dev
, mode
);
9845 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9846 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
9847 old
->release_fb
= fb
;
9849 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9851 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9855 if (intel_set_mode(crtc
, mode
, 0, 0, fb
, state
)) {
9856 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9857 if (old
->release_fb
)
9858 old
->release_fb
->funcs
->destroy(old
->release_fb
);
9861 crtc
->primary
->crtc
= crtc
;
9863 /* let the connector get through one full cycle before testing */
9864 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
9868 intel_crtc
->new_enabled
= crtc
->state
->enable
;
9870 drm_atomic_state_free(state
);
9873 if (ret
== -EDEADLK
) {
9874 drm_modeset_backoff(ctx
);
9881 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
9882 struct intel_load_detect_pipe
*old
,
9883 struct drm_modeset_acquire_ctx
*ctx
)
9885 struct drm_device
*dev
= connector
->dev
;
9886 struct intel_encoder
*intel_encoder
=
9887 intel_attached_encoder(connector
);
9888 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9889 struct drm_crtc
*crtc
= encoder
->crtc
;
9890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9891 struct drm_atomic_state
*state
;
9892 struct drm_connector_state
*connector_state
;
9893 struct intel_crtc_state
*crtc_state
;
9895 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9896 connector
->base
.id
, connector
->name
,
9897 encoder
->base
.id
, encoder
->name
);
9899 if (old
->load_detect_temp
) {
9900 state
= drm_atomic_state_alloc(dev
);
9904 state
->acquire_ctx
= ctx
;
9906 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9907 if (IS_ERR(connector_state
))
9910 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9911 if (IS_ERR(crtc_state
))
9914 to_intel_connector(connector
)->new_encoder
= NULL
;
9915 intel_encoder
->new_crtc
= NULL
;
9916 intel_crtc
->new_enabled
= false;
9918 connector_state
->best_encoder
= NULL
;
9919 connector_state
->crtc
= NULL
;
9921 crtc_state
->base
.enable
= false;
9923 intel_set_mode(crtc
, NULL
, 0, 0, NULL
, state
);
9925 drm_atomic_state_free(state
);
9927 if (old
->release_fb
) {
9928 drm_framebuffer_unregister_private(old
->release_fb
);
9929 drm_framebuffer_unreference(old
->release_fb
);
9935 /* Switch crtc and encoder back off if necessary */
9936 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
9937 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
9941 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9942 drm_atomic_state_free(state
);
9945 static int i9xx_pll_refclk(struct drm_device
*dev
,
9946 const struct intel_crtc_state
*pipe_config
)
9948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9949 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9951 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
9952 return dev_priv
->vbt
.lvds_ssc_freq
;
9953 else if (HAS_PCH_SPLIT(dev
))
9955 else if (!IS_GEN2(dev
))
9961 /* Returns the clock of the currently programmed mode of the given pipe. */
9962 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
9963 struct intel_crtc_state
*pipe_config
)
9965 struct drm_device
*dev
= crtc
->base
.dev
;
9966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9967 int pipe
= pipe_config
->cpu_transcoder
;
9968 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9970 intel_clock_t clock
;
9971 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
9973 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
9974 fp
= pipe_config
->dpll_hw_state
.fp0
;
9976 fp
= pipe_config
->dpll_hw_state
.fp1
;
9978 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
9979 if (IS_PINEVIEW(dev
)) {
9980 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
9981 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
9983 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
9984 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
9987 if (!IS_GEN2(dev
)) {
9988 if (IS_PINEVIEW(dev
))
9989 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
9990 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
9992 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
9993 DPLL_FPA01_P1_POST_DIV_SHIFT
);
9995 switch (dpll
& DPLL_MODE_MASK
) {
9996 case DPLLB_MODE_DAC_SERIAL
:
9997 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10000 case DPLLB_MODE_LVDS
:
10001 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10005 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10006 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10010 if (IS_PINEVIEW(dev
))
10011 pineview_clock(refclk
, &clock
);
10013 i9xx_clock(refclk
, &clock
);
10015 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10016 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10019 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10020 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10022 if (lvds
& LVDS_CLKB_POWER_UP
)
10027 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10030 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10031 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10033 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10039 i9xx_clock(refclk
, &clock
);
10043 * This value includes pixel_multiplier. We will use
10044 * port_clock to compute adjusted_mode.crtc_clock in the
10045 * encoder's get_config() function.
10047 pipe_config
->port_clock
= clock
.dot
;
10050 int intel_dotclock_calculate(int link_freq
,
10051 const struct intel_link_m_n
*m_n
)
10054 * The calculation for the data clock is:
10055 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10056 * But we want to avoid losing precison if possible, so:
10057 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10059 * and the link clock is simpler:
10060 * link_clock = (m * link_clock) / n
10066 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10069 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10070 struct intel_crtc_state
*pipe_config
)
10072 struct drm_device
*dev
= crtc
->base
.dev
;
10074 /* read out port_clock from the DPLL */
10075 i9xx_crtc_clock_get(crtc
, pipe_config
);
10078 * This value does not include pixel_multiplier.
10079 * We will check that port_clock and adjusted_mode.crtc_clock
10080 * agree once we know their relationship in the encoder's
10081 * get_config() function.
10083 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10084 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10085 &pipe_config
->fdi_m_n
);
10088 /** Returns the currently programmed mode of the given pipe. */
10089 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10090 struct drm_crtc
*crtc
)
10092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10093 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10094 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10095 struct drm_display_mode
*mode
;
10096 struct intel_crtc_state pipe_config
;
10097 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10098 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10099 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10100 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10101 enum pipe pipe
= intel_crtc
->pipe
;
10103 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10108 * Construct a pipe_config sufficient for getting the clock info
10109 * back out of crtc_clock_get.
10111 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10112 * to use a real value here instead.
10114 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10115 pipe_config
.pixel_multiplier
= 1;
10116 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10117 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10118 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10119 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10121 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10122 mode
->hdisplay
= (htot
& 0xffff) + 1;
10123 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10124 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10125 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10126 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10127 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10128 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10129 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10131 drm_mode_set_name(mode
);
10136 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
10138 struct drm_device
*dev
= crtc
->dev
;
10139 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10140 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10142 if (!HAS_GMCH_DISPLAY(dev
))
10145 if (!dev_priv
->lvds_downclock_avail
)
10149 * Since this is called by a timer, we should never get here in
10152 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
10153 int pipe
= intel_crtc
->pipe
;
10154 int dpll_reg
= DPLL(pipe
);
10157 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10159 assert_panel_unlocked(dev_priv
, pipe
);
10161 dpll
= I915_READ(dpll_reg
);
10162 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
10163 I915_WRITE(dpll_reg
, dpll
);
10164 intel_wait_for_vblank(dev
, pipe
);
10165 dpll
= I915_READ(dpll_reg
);
10166 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
10167 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10172 void intel_mark_busy(struct drm_device
*dev
)
10174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10176 if (dev_priv
->mm
.busy
)
10179 intel_runtime_pm_get(dev_priv
);
10180 i915_update_gfx_val(dev_priv
);
10181 if (INTEL_INFO(dev
)->gen
>= 6)
10182 gen6_rps_busy(dev_priv
);
10183 dev_priv
->mm
.busy
= true;
10186 void intel_mark_idle(struct drm_device
*dev
)
10188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10189 struct drm_crtc
*crtc
;
10191 if (!dev_priv
->mm
.busy
)
10194 dev_priv
->mm
.busy
= false;
10196 for_each_crtc(dev
, crtc
) {
10197 if (!crtc
->primary
->fb
)
10200 intel_decrease_pllclock(crtc
);
10203 if (INTEL_INFO(dev
)->gen
>= 6)
10204 gen6_rps_idle(dev
->dev_private
);
10206 intel_runtime_pm_put(dev_priv
);
10209 static void intel_crtc_set_state(struct intel_crtc
*crtc
,
10210 struct intel_crtc_state
*crtc_state
)
10212 kfree(crtc
->config
);
10213 crtc
->config
= crtc_state
;
10214 crtc
->base
.state
= &crtc_state
->base
;
10217 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10219 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10220 struct drm_device
*dev
= crtc
->dev
;
10221 struct intel_unpin_work
*work
;
10223 spin_lock_irq(&dev
->event_lock
);
10224 work
= intel_crtc
->unpin_work
;
10225 intel_crtc
->unpin_work
= NULL
;
10226 spin_unlock_irq(&dev
->event_lock
);
10229 cancel_work_sync(&work
->work
);
10233 intel_crtc_set_state(intel_crtc
, NULL
);
10234 drm_crtc_cleanup(crtc
);
10239 static void intel_unpin_work_fn(struct work_struct
*__work
)
10241 struct intel_unpin_work
*work
=
10242 container_of(__work
, struct intel_unpin_work
, work
);
10243 struct drm_device
*dev
= work
->crtc
->dev
;
10244 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
10246 mutex_lock(&dev
->struct_mutex
);
10247 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
10248 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10250 intel_fbc_update(dev
);
10252 if (work
->flip_queued_req
)
10253 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10254 mutex_unlock(&dev
->struct_mutex
);
10256 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10257 drm_framebuffer_unreference(work
->old_fb
);
10259 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
10260 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
10265 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10266 struct drm_crtc
*crtc
)
10268 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10269 struct intel_unpin_work
*work
;
10270 unsigned long flags
;
10272 /* Ignore early vblank irqs */
10273 if (intel_crtc
== NULL
)
10277 * This is called both by irq handlers and the reset code (to complete
10278 * lost pageflips) so needs the full irqsave spinlocks.
10280 spin_lock_irqsave(&dev
->event_lock
, flags
);
10281 work
= intel_crtc
->unpin_work
;
10283 /* Ensure we don't miss a work->pending update ... */
10286 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10287 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10291 page_flip_completed(intel_crtc
);
10293 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10296 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10298 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10299 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10301 do_intel_finish_page_flip(dev
, crtc
);
10304 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10306 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10307 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10309 do_intel_finish_page_flip(dev
, crtc
);
10312 /* Is 'a' after or equal to 'b'? */
10313 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10315 return !((a
- b
) & 0x80000000);
10318 static bool page_flip_finished(struct intel_crtc
*crtc
)
10320 struct drm_device
*dev
= crtc
->base
.dev
;
10321 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10323 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10324 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10328 * The relevant registers doen't exist on pre-ctg.
10329 * As the flip done interrupt doesn't trigger for mmio
10330 * flips on gmch platforms, a flip count check isn't
10331 * really needed there. But since ctg has the registers,
10332 * include it in the check anyway.
10334 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10338 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10339 * used the same base address. In that case the mmio flip might
10340 * have completed, but the CS hasn't even executed the flip yet.
10342 * A flip count check isn't enough as the CS might have updated
10343 * the base address just after start of vblank, but before we
10344 * managed to process the interrupt. This means we'd complete the
10345 * CS flip too soon.
10347 * Combining both checks should get us a good enough result. It may
10348 * still happen that the CS flip has been executed, but has not
10349 * yet actually completed. But in case the base address is the same
10350 * anyway, we don't really care.
10352 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10353 crtc
->unpin_work
->gtt_offset
&&
10354 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
10355 crtc
->unpin_work
->flip_count
);
10358 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10360 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10361 struct intel_crtc
*intel_crtc
=
10362 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10363 unsigned long flags
;
10367 * This is called both by irq handlers and the reset code (to complete
10368 * lost pageflips) so needs the full irqsave spinlocks.
10370 * NB: An MMIO update of the plane base pointer will also
10371 * generate a page-flip completion irq, i.e. every modeset
10372 * is also accompanied by a spurious intel_prepare_page_flip().
10374 spin_lock_irqsave(&dev
->event_lock
, flags
);
10375 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10376 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10377 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10380 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
10382 /* Ensure that the work item is consistent when activating it ... */
10384 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
10385 /* and that it is marked active as soon as the irq could fire. */
10389 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10390 struct drm_crtc
*crtc
,
10391 struct drm_framebuffer
*fb
,
10392 struct drm_i915_gem_object
*obj
,
10393 struct intel_engine_cs
*ring
,
10396 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10400 ret
= intel_ring_begin(ring
, 6);
10404 /* Can't queue multiple flips, so wait for the previous
10405 * one to finish before executing the next.
10407 if (intel_crtc
->plane
)
10408 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10410 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10411 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10412 intel_ring_emit(ring
, MI_NOOP
);
10413 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10414 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10415 intel_ring_emit(ring
, fb
->pitches
[0]);
10416 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10417 intel_ring_emit(ring
, 0); /* aux display base address, unused */
10419 intel_mark_page_flip_active(intel_crtc
);
10420 __intel_ring_advance(ring
);
10424 static int intel_gen3_queue_flip(struct drm_device
*dev
,
10425 struct drm_crtc
*crtc
,
10426 struct drm_framebuffer
*fb
,
10427 struct drm_i915_gem_object
*obj
,
10428 struct intel_engine_cs
*ring
,
10431 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10435 ret
= intel_ring_begin(ring
, 6);
10439 if (intel_crtc
->plane
)
10440 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10442 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10443 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10444 intel_ring_emit(ring
, MI_NOOP
);
10445 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
10446 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10447 intel_ring_emit(ring
, fb
->pitches
[0]);
10448 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10449 intel_ring_emit(ring
, MI_NOOP
);
10451 intel_mark_page_flip_active(intel_crtc
);
10452 __intel_ring_advance(ring
);
10456 static int intel_gen4_queue_flip(struct drm_device
*dev
,
10457 struct drm_crtc
*crtc
,
10458 struct drm_framebuffer
*fb
,
10459 struct drm_i915_gem_object
*obj
,
10460 struct intel_engine_cs
*ring
,
10463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10465 uint32_t pf
, pipesrc
;
10468 ret
= intel_ring_begin(ring
, 4);
10472 /* i965+ uses the linear or tiled offsets from the
10473 * Display Registers (which do not change across a page-flip)
10474 * so we need only reprogram the base address.
10476 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10477 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10478 intel_ring_emit(ring
, fb
->pitches
[0]);
10479 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
10482 /* XXX Enabling the panel-fitter across page-flip is so far
10483 * untested on non-native modes, so ignore it for now.
10484 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10487 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10488 intel_ring_emit(ring
, pf
| pipesrc
);
10490 intel_mark_page_flip_active(intel_crtc
);
10491 __intel_ring_advance(ring
);
10495 static int intel_gen6_queue_flip(struct drm_device
*dev
,
10496 struct drm_crtc
*crtc
,
10497 struct drm_framebuffer
*fb
,
10498 struct drm_i915_gem_object
*obj
,
10499 struct intel_engine_cs
*ring
,
10502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10503 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10504 uint32_t pf
, pipesrc
;
10507 ret
= intel_ring_begin(ring
, 4);
10511 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10512 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10513 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
10514 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10516 /* Contrary to the suggestions in the documentation,
10517 * "Enable Panel Fitter" does not seem to be required when page
10518 * flipping with a non-native mode, and worse causes a normal
10520 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10523 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
10524 intel_ring_emit(ring
, pf
| pipesrc
);
10526 intel_mark_page_flip_active(intel_crtc
);
10527 __intel_ring_advance(ring
);
10531 static int intel_gen7_queue_flip(struct drm_device
*dev
,
10532 struct drm_crtc
*crtc
,
10533 struct drm_framebuffer
*fb
,
10534 struct drm_i915_gem_object
*obj
,
10535 struct intel_engine_cs
*ring
,
10538 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10539 uint32_t plane_bit
= 0;
10542 switch (intel_crtc
->plane
) {
10544 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
10547 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
10550 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
10553 WARN_ONCE(1, "unknown plane in flip command\n");
10558 if (ring
->id
== RCS
) {
10561 * On Gen 8, SRM is now taking an extra dword to accommodate
10562 * 48bits addresses, and we need a NOOP for the batch size to
10570 * BSpec MI_DISPLAY_FLIP for IVB:
10571 * "The full packet must be contained within the same cache line."
10573 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10574 * cacheline, if we ever start emitting more commands before
10575 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10576 * then do the cacheline alignment, and finally emit the
10579 ret
= intel_ring_cacheline_align(ring
);
10583 ret
= intel_ring_begin(ring
, len
);
10587 /* Unmask the flip-done completion message. Note that the bspec says that
10588 * we should do this for both the BCS and RCS, and that we must not unmask
10589 * more than one flip event at any time (or ensure that one flip message
10590 * can be sent by waiting for flip-done prior to queueing new flips).
10591 * Experimentation says that BCS works despite DERRMR masking all
10592 * flip-done completion events and that unmasking all planes at once
10593 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10594 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10596 if (ring
->id
== RCS
) {
10597 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
10598 intel_ring_emit(ring
, DERRMR
);
10599 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
10600 DERRMR_PIPEB_PRI_FLIP_DONE
|
10601 DERRMR_PIPEC_PRI_FLIP_DONE
));
10603 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
10604 MI_SRM_LRM_GLOBAL_GTT
);
10606 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
10607 MI_SRM_LRM_GLOBAL_GTT
);
10608 intel_ring_emit(ring
, DERRMR
);
10609 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
10610 if (IS_GEN8(dev
)) {
10611 intel_ring_emit(ring
, 0);
10612 intel_ring_emit(ring
, MI_NOOP
);
10616 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
10617 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
10618 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10619 intel_ring_emit(ring
, (MI_NOOP
));
10621 intel_mark_page_flip_active(intel_crtc
);
10622 __intel_ring_advance(ring
);
10626 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
10627 struct drm_i915_gem_object
*obj
)
10630 * This is not being used for older platforms, because
10631 * non-availability of flip done interrupt forces us to use
10632 * CS flips. Older platforms derive flip done using some clever
10633 * tricks involving the flip_pending status bits and vblank irqs.
10634 * So using MMIO flips there would disrupt this mechanism.
10640 if (INTEL_INFO(ring
->dev
)->gen
< 5)
10643 if (i915
.use_mmio_flip
< 0)
10645 else if (i915
.use_mmio_flip
> 0)
10647 else if (i915
.enable_execlists
)
10650 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
10653 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10655 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10657 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
10658 const enum pipe pipe
= intel_crtc
->pipe
;
10661 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
10662 ctl
&= ~PLANE_CTL_TILED_MASK
;
10663 switch (fb
->modifier
[0]) {
10664 case DRM_FORMAT_MOD_NONE
:
10666 case I915_FORMAT_MOD_X_TILED
:
10667 ctl
|= PLANE_CTL_TILED_X
;
10669 case I915_FORMAT_MOD_Y_TILED
:
10670 ctl
|= PLANE_CTL_TILED_Y
;
10672 case I915_FORMAT_MOD_Yf_TILED
:
10673 ctl
|= PLANE_CTL_TILED_YF
;
10676 MISSING_CASE(fb
->modifier
[0]);
10680 * The stride is either expressed as a multiple of 64 bytes chunks for
10681 * linear buffers or in number of tiles for tiled buffers.
10683 stride
= fb
->pitches
[0] /
10684 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
10688 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10689 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10691 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
10692 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
10694 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
10695 POSTING_READ(PLANE_SURF(pipe
, 0));
10698 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10700 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10701 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10702 struct intel_framebuffer
*intel_fb
=
10703 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
10704 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10708 reg
= DSPCNTR(intel_crtc
->plane
);
10709 dspcntr
= I915_READ(reg
);
10711 if (obj
->tiling_mode
!= I915_TILING_NONE
)
10712 dspcntr
|= DISPPLANE_TILED
;
10714 dspcntr
&= ~DISPPLANE_TILED
;
10716 I915_WRITE(reg
, dspcntr
);
10718 I915_WRITE(DSPSURF(intel_crtc
->plane
),
10719 intel_crtc
->unpin_work
->gtt_offset
);
10720 POSTING_READ(DSPSURF(intel_crtc
->plane
));
10725 * XXX: This is the temporary way to update the plane registers until we get
10726 * around to using the usual plane update functions for MMIO flips
10728 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10730 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10731 bool atomic_update
;
10732 u32 start_vbl_count
;
10734 intel_mark_page_flip_active(intel_crtc
);
10736 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
10738 if (INTEL_INFO(dev
)->gen
>= 9)
10739 skl_do_mmio_flip(intel_crtc
);
10741 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10742 ilk_do_mmio_flip(intel_crtc
);
10745 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
10748 static void intel_mmio_flip_work_func(struct work_struct
*work
)
10750 struct intel_crtc
*crtc
=
10751 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
10752 struct intel_mmio_flip
*mmio_flip
;
10754 mmio_flip
= &crtc
->mmio_flip
;
10755 if (mmio_flip
->req
)
10756 WARN_ON(__i915_wait_request(mmio_flip
->req
,
10757 crtc
->reset_counter
,
10758 false, NULL
, NULL
) != 0);
10760 intel_do_mmio_flip(crtc
);
10761 if (mmio_flip
->req
) {
10762 mutex_lock(&crtc
->base
.dev
->struct_mutex
);
10763 i915_gem_request_assign(&mmio_flip
->req
, NULL
);
10764 mutex_unlock(&crtc
->base
.dev
->struct_mutex
);
10768 static int intel_queue_mmio_flip(struct drm_device
*dev
,
10769 struct drm_crtc
*crtc
,
10770 struct drm_framebuffer
*fb
,
10771 struct drm_i915_gem_object
*obj
,
10772 struct intel_engine_cs
*ring
,
10775 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10777 i915_gem_request_assign(&intel_crtc
->mmio_flip
.req
,
10778 obj
->last_write_req
);
10780 schedule_work(&intel_crtc
->mmio_flip
.work
);
10785 static int intel_default_queue_flip(struct drm_device
*dev
,
10786 struct drm_crtc
*crtc
,
10787 struct drm_framebuffer
*fb
,
10788 struct drm_i915_gem_object
*obj
,
10789 struct intel_engine_cs
*ring
,
10795 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
10796 struct drm_crtc
*crtc
)
10798 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10799 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10800 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
10803 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
10806 if (!work
->enable_stall_check
)
10809 if (work
->flip_ready_vblank
== 0) {
10810 if (work
->flip_queued_req
&&
10811 !i915_gem_request_completed(work
->flip_queued_req
, true))
10814 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
10817 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
10820 /* Potential stall - if we see that the flip has happened,
10821 * assume a missed interrupt. */
10822 if (INTEL_INFO(dev
)->gen
>= 4)
10823 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
10825 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
10827 /* There is a potential issue here with a false positive after a flip
10828 * to the same address. We could address this by checking for a
10829 * non-incrementing frame counter.
10831 return addr
== work
->gtt_offset
;
10834 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
10836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10837 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10838 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10839 struct intel_unpin_work
*work
;
10841 WARN_ON(!in_interrupt());
10846 spin_lock(&dev
->event_lock
);
10847 work
= intel_crtc
->unpin_work
;
10848 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
10849 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10850 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
10851 page_flip_completed(intel_crtc
);
10854 if (work
!= NULL
&&
10855 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
10856 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
10857 spin_unlock(&dev
->event_lock
);
10860 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
10861 struct drm_framebuffer
*fb
,
10862 struct drm_pending_vblank_event
*event
,
10863 uint32_t page_flip_flags
)
10865 struct drm_device
*dev
= crtc
->dev
;
10866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10867 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10868 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10869 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10870 struct drm_plane
*primary
= crtc
->primary
;
10871 enum pipe pipe
= intel_crtc
->pipe
;
10872 struct intel_unpin_work
*work
;
10873 struct intel_engine_cs
*ring
;
10878 * drm_mode_page_flip_ioctl() should already catch this, but double
10879 * check to be safe. In the future we may enable pageflipping from
10880 * a disabled primary plane.
10882 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
10885 /* Can't change pixel format via MI display flips. */
10886 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
10890 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10891 * Note that pitch changes could also affect these register.
10893 if (INTEL_INFO(dev
)->gen
> 3 &&
10894 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
10895 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
10898 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
10901 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
10905 work
->event
= event
;
10907 work
->old_fb
= old_fb
;
10908 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
10910 ret
= drm_crtc_vblank_get(crtc
);
10914 /* We borrow the event spin lock for protecting unpin_work */
10915 spin_lock_irq(&dev
->event_lock
);
10916 if (intel_crtc
->unpin_work
) {
10917 /* Before declaring the flip queue wedged, check if
10918 * the hardware completed the operation behind our backs.
10920 if (__intel_pageflip_stall_check(dev
, crtc
)) {
10921 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10922 page_flip_completed(intel_crtc
);
10924 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10925 spin_unlock_irq(&dev
->event_lock
);
10927 drm_crtc_vblank_put(crtc
);
10932 intel_crtc
->unpin_work
= work
;
10933 spin_unlock_irq(&dev
->event_lock
);
10935 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
10936 flush_workqueue(dev_priv
->wq
);
10938 /* Reference the objects for the scheduled work. */
10939 drm_framebuffer_reference(work
->old_fb
);
10940 drm_gem_object_reference(&obj
->base
);
10942 crtc
->primary
->fb
= fb
;
10943 update_state_fb(crtc
->primary
);
10945 work
->pending_flip_obj
= obj
;
10947 ret
= i915_mutex_lock_interruptible(dev
);
10951 atomic_inc(&intel_crtc
->unpin_work_count
);
10952 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
10954 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
10955 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
10957 if (IS_VALLEYVIEW(dev
)) {
10958 ring
= &dev_priv
->ring
[BCS
];
10959 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
10960 /* vlv: DISPLAY_FLIP fails to change tiling */
10962 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
10963 ring
= &dev_priv
->ring
[BCS
];
10964 } else if (INTEL_INFO(dev
)->gen
>= 7) {
10965 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
10966 if (ring
== NULL
|| ring
->id
!= RCS
)
10967 ring
= &dev_priv
->ring
[BCS
];
10969 ring
= &dev_priv
->ring
[RCS
];
10972 mmio_flip
= use_mmio_flip(ring
, obj
);
10974 /* When using CS flips, we want to emit semaphores between rings.
10975 * However, when using mmio flips we will create a task to do the
10976 * synchronisation, so all we want here is to pin the framebuffer
10977 * into the display plane and skip any waits.
10979 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
10980 crtc
->primary
->state
,
10981 mmio_flip
? i915_gem_request_get_ring(obj
->last_read_req
) : ring
);
10983 goto cleanup_pending
;
10985 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
10986 + intel_crtc
->dspaddr_offset
;
10989 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
10992 goto cleanup_unpin
;
10994 i915_gem_request_assign(&work
->flip_queued_req
,
10995 obj
->last_write_req
);
10997 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
11000 goto cleanup_unpin
;
11002 i915_gem_request_assign(&work
->flip_queued_req
,
11003 intel_ring_get_request(ring
));
11006 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11007 work
->enable_stall_check
= true;
11009 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11010 INTEL_FRONTBUFFER_PRIMARY(pipe
));
11012 intel_fbc_disable(dev
);
11013 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
11014 mutex_unlock(&dev
->struct_mutex
);
11016 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11021 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11023 atomic_dec(&intel_crtc
->unpin_work_count
);
11024 mutex_unlock(&dev
->struct_mutex
);
11026 crtc
->primary
->fb
= old_fb
;
11027 update_state_fb(crtc
->primary
);
11029 drm_gem_object_unreference_unlocked(&obj
->base
);
11030 drm_framebuffer_unreference(work
->old_fb
);
11032 spin_lock_irq(&dev
->event_lock
);
11033 intel_crtc
->unpin_work
= NULL
;
11034 spin_unlock_irq(&dev
->event_lock
);
11036 drm_crtc_vblank_put(crtc
);
11042 ret
= intel_plane_restore(primary
);
11043 if (ret
== 0 && event
) {
11044 spin_lock_irq(&dev
->event_lock
);
11045 drm_send_vblank_event(dev
, pipe
, event
);
11046 spin_unlock_irq(&dev
->event_lock
);
11052 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11053 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11054 .load_lut
= intel_crtc_load_lut
,
11055 .atomic_begin
= intel_begin_crtc_commit
,
11056 .atomic_flush
= intel_finish_crtc_commit
,
11060 * intel_modeset_update_staged_output_state
11062 * Updates the staged output configuration state, e.g. after we've read out the
11063 * current hw state.
11065 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
11067 struct intel_crtc
*crtc
;
11068 struct intel_encoder
*encoder
;
11069 struct intel_connector
*connector
;
11071 for_each_intel_connector(dev
, connector
) {
11072 connector
->new_encoder
=
11073 to_intel_encoder(connector
->base
.encoder
);
11076 for_each_intel_encoder(dev
, encoder
) {
11077 encoder
->new_crtc
=
11078 to_intel_crtc(encoder
->base
.crtc
);
11081 for_each_intel_crtc(dev
, crtc
) {
11082 crtc
->new_enabled
= crtc
->base
.state
->enable
;
11086 /* Transitional helper to copy current connector/encoder state to
11087 * connector->state. This is needed so that code that is partially
11088 * converted to atomic does the right thing.
11090 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11092 struct intel_connector
*connector
;
11094 for_each_intel_connector(dev
, connector
) {
11095 if (connector
->base
.encoder
) {
11096 connector
->base
.state
->best_encoder
=
11097 connector
->base
.encoder
;
11098 connector
->base
.state
->crtc
=
11099 connector
->base
.encoder
->crtc
;
11101 connector
->base
.state
->best_encoder
= NULL
;
11102 connector
->base
.state
->crtc
= NULL
;
11108 * intel_modeset_commit_output_state
11110 * This function copies the stage display pipe configuration to the real one.
11112 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
11114 struct intel_crtc
*crtc
;
11115 struct intel_encoder
*encoder
;
11116 struct intel_connector
*connector
;
11118 for_each_intel_connector(dev
, connector
) {
11119 connector
->base
.encoder
= &connector
->new_encoder
->base
;
11122 for_each_intel_encoder(dev
, encoder
) {
11123 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
11126 for_each_intel_crtc(dev
, crtc
) {
11127 crtc
->base
.state
->enable
= crtc
->new_enabled
;
11128 crtc
->base
.enabled
= crtc
->new_enabled
;
11131 intel_modeset_update_connector_atomic_state(dev
);
11135 connected_sink_compute_bpp(struct intel_connector
*connector
,
11136 struct intel_crtc_state
*pipe_config
)
11138 int bpp
= pipe_config
->pipe_bpp
;
11140 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11141 connector
->base
.base
.id
,
11142 connector
->base
.name
);
11144 /* Don't use an invalid EDID bpc value */
11145 if (connector
->base
.display_info
.bpc
&&
11146 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11147 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11148 bpp
, connector
->base
.display_info
.bpc
*3);
11149 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11152 /* Clamp bpp to 8 on screens without EDID 1.4 */
11153 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11154 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11156 pipe_config
->pipe_bpp
= 24;
11161 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11162 struct intel_crtc_state
*pipe_config
)
11164 struct drm_device
*dev
= crtc
->base
.dev
;
11165 struct drm_atomic_state
*state
;
11166 struct drm_connector
*connector
;
11167 struct drm_connector_state
*connector_state
;
11170 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11172 else if (INTEL_INFO(dev
)->gen
>= 5)
11178 pipe_config
->pipe_bpp
= bpp
;
11180 state
= pipe_config
->base
.state
;
11182 /* Clamp display bpp to EDID value */
11183 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11184 if (connector_state
->crtc
!= &crtc
->base
)
11187 connected_sink_compute_bpp(to_intel_connector(connector
),
11194 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11196 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11197 "type: 0x%x flags: 0x%x\n",
11199 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11200 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11201 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11202 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11205 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11206 struct intel_crtc_state
*pipe_config
,
11207 const char *context
)
11209 struct drm_device
*dev
= crtc
->base
.dev
;
11210 struct drm_plane
*plane
;
11211 struct intel_plane
*intel_plane
;
11212 struct intel_plane_state
*state
;
11213 struct drm_framebuffer
*fb
;
11215 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11216 context
, pipe_config
, pipe_name(crtc
->pipe
));
11218 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11219 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11220 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11221 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11222 pipe_config
->has_pch_encoder
,
11223 pipe_config
->fdi_lanes
,
11224 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11225 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11226 pipe_config
->fdi_m_n
.tu
);
11227 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11228 pipe_config
->has_dp_encoder
,
11229 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
11230 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
11231 pipe_config
->dp_m_n
.tu
);
11233 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11234 pipe_config
->has_dp_encoder
,
11235 pipe_config
->dp_m2_n2
.gmch_m
,
11236 pipe_config
->dp_m2_n2
.gmch_n
,
11237 pipe_config
->dp_m2_n2
.link_m
,
11238 pipe_config
->dp_m2_n2
.link_n
,
11239 pipe_config
->dp_m2_n2
.tu
);
11241 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11242 pipe_config
->has_audio
,
11243 pipe_config
->has_infoframe
);
11245 DRM_DEBUG_KMS("requested mode:\n");
11246 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
11247 DRM_DEBUG_KMS("adjusted mode:\n");
11248 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
11249 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
11250 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
11251 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11252 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
11253 DRM_DEBUG_KMS("num_scalers: %d\n", crtc
->num_scalers
);
11254 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config
->scaler_state
.scaler_users
);
11255 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config
->scaler_state
.scaler_id
);
11256 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11257 pipe_config
->gmch_pfit
.control
,
11258 pipe_config
->gmch_pfit
.pgm_ratios
,
11259 pipe_config
->gmch_pfit
.lvds_border_bits
);
11260 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11261 pipe_config
->pch_pfit
.pos
,
11262 pipe_config
->pch_pfit
.size
,
11263 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
11264 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
11265 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
11267 DRM_DEBUG_KMS("planes on this crtc\n");
11268 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
11269 intel_plane
= to_intel_plane(plane
);
11270 if (intel_plane
->pipe
!= crtc
->pipe
)
11273 state
= to_intel_plane_state(plane
->state
);
11274 fb
= state
->base
.fb
;
11276 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11277 "disabled, scaler_id = %d\n",
11278 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11279 plane
->base
.id
, intel_plane
->pipe
,
11280 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
11281 drm_plane_index(plane
), state
->scaler_id
);
11285 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11286 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
11287 plane
->base
.id
, intel_plane
->pipe
,
11288 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
11289 drm_plane_index(plane
));
11290 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11291 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
11292 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11294 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
11295 drm_rect_width(&state
->src
) >> 16,
11296 drm_rect_height(&state
->src
) >> 16,
11297 state
->dst
.x1
, state
->dst
.y1
,
11298 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
11302 static bool encoders_cloneable(const struct intel_encoder
*a
,
11303 const struct intel_encoder
*b
)
11305 /* masks could be asymmetric, so check both ways */
11306 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11307 b
->cloneable
& (1 << a
->type
));
11310 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11311 struct intel_crtc
*crtc
,
11312 struct intel_encoder
*encoder
)
11314 struct intel_encoder
*source_encoder
;
11315 struct drm_connector
*connector
;
11316 struct drm_connector_state
*connector_state
;
11319 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11320 if (connector_state
->crtc
!= &crtc
->base
)
11324 to_intel_encoder(connector_state
->best_encoder
);
11325 if (!encoders_cloneable(encoder
, source_encoder
))
11332 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11333 struct intel_crtc
*crtc
)
11335 struct intel_encoder
*encoder
;
11336 struct drm_connector
*connector
;
11337 struct drm_connector_state
*connector_state
;
11340 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11341 if (connector_state
->crtc
!= &crtc
->base
)
11344 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11345 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11352 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
11354 struct drm_device
*dev
= state
->dev
;
11355 struct intel_encoder
*encoder
;
11356 struct drm_connector
*connector
;
11357 struct drm_connector_state
*connector_state
;
11358 unsigned int used_ports
= 0;
11362 * Walk the connector list instead of the encoder
11363 * list to detect the problem on ddi platforms
11364 * where there's just one encoder per digital port.
11366 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11367 if (!connector_state
->best_encoder
)
11370 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11372 WARN_ON(!connector_state
->crtc
);
11374 switch (encoder
->type
) {
11375 unsigned int port_mask
;
11376 case INTEL_OUTPUT_UNKNOWN
:
11377 if (WARN_ON(!HAS_DDI(dev
)))
11379 case INTEL_OUTPUT_DISPLAYPORT
:
11380 case INTEL_OUTPUT_HDMI
:
11381 case INTEL_OUTPUT_EDP
:
11382 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
11384 /* the same port mustn't appear more than once */
11385 if (used_ports
& port_mask
)
11388 used_ports
|= port_mask
;
11398 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
11400 struct drm_crtc_state tmp_state
;
11401 struct intel_crtc_scaler_state scaler_state
;
11403 /* Clear only the intel specific part of the crtc state excluding scalers */
11404 tmp_state
= crtc_state
->base
;
11405 scaler_state
= crtc_state
->scaler_state
;
11406 memset(crtc_state
, 0, sizeof *crtc_state
);
11407 crtc_state
->base
= tmp_state
;
11408 crtc_state
->scaler_state
= scaler_state
;
11412 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
11413 struct drm_display_mode
*mode
,
11414 struct drm_atomic_state
*state
,
11415 struct intel_crtc_state
*pipe_config
)
11417 struct intel_encoder
*encoder
;
11418 struct drm_connector
*connector
;
11419 struct drm_connector_state
*connector_state
;
11420 int base_bpp
, ret
= -EINVAL
;
11424 if (!check_encoder_cloning(state
, to_intel_crtc(crtc
))) {
11425 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11429 if (!check_digital_port_conflicts(state
)) {
11430 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11434 clear_intel_crtc_state(pipe_config
);
11436 pipe_config
->base
.crtc
= crtc
;
11437 drm_mode_copy(&pipe_config
->base
.adjusted_mode
, mode
);
11438 drm_mode_copy(&pipe_config
->base
.mode
, mode
);
11440 pipe_config
->cpu_transcoder
=
11441 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
11442 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
11445 * Sanitize sync polarity flags based on requested ones. If neither
11446 * positive or negative polarity is requested, treat this as meaning
11447 * negative polarity.
11449 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11450 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
11451 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
11453 if (!(pipe_config
->base
.adjusted_mode
.flags
&
11454 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
11455 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
11457 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11458 * plane pixel format and any sink constraints into account. Returns the
11459 * source plane bpp so that dithering can be selected on mismatches
11460 * after encoders and crtc also have had their say. */
11461 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
11467 * Determine the real pipe dimensions. Note that stereo modes can
11468 * increase the actual pipe size due to the frame doubling and
11469 * insertion of additional space for blanks between the frame. This
11470 * is stored in the crtc timings. We use the requested mode to do this
11471 * computation to clearly distinguish it from the adjusted mode, which
11472 * can be changed by the connectors in the below retry loop.
11474 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
11475 &pipe_config
->pipe_src_w
,
11476 &pipe_config
->pipe_src_h
);
11479 /* Ensure the port clock defaults are reset when retrying. */
11480 pipe_config
->port_clock
= 0;
11481 pipe_config
->pixel_multiplier
= 1;
11483 /* Fill in default crtc timings, allow encoders to overwrite them. */
11484 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
11485 CRTC_STEREO_DOUBLE
);
11487 /* Pass our mode to the connectors and the CRTC to give them a chance to
11488 * adjust it according to limitations or connector properties, and also
11489 * a chance to reject the mode entirely.
11491 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11492 if (connector_state
->crtc
!= crtc
)
11495 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11497 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
11498 DRM_DEBUG_KMS("Encoder config failure\n");
11503 /* Set default port clock if not overwritten by the encoder. Needs to be
11504 * done afterwards in case the encoder adjusts the mode. */
11505 if (!pipe_config
->port_clock
)
11506 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
11507 * pipe_config
->pixel_multiplier
;
11509 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
11511 DRM_DEBUG_KMS("CRTC fixup failed\n");
11515 if (ret
== RETRY
) {
11516 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
11521 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11523 goto encoder_retry
;
11526 pipe_config
->dither
= pipe_config
->pipe_bpp
!= base_bpp
;
11527 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11528 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
11535 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
11537 struct drm_encoder
*encoder
;
11538 struct drm_device
*dev
= crtc
->dev
;
11540 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
11541 if (encoder
->crtc
== crtc
)
11548 needs_modeset(struct drm_crtc_state
*state
)
11550 return state
->mode_changed
|| state
->active_changed
;
11554 intel_modeset_update_state(struct drm_atomic_state
*state
)
11556 struct drm_device
*dev
= state
->dev
;
11557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11558 struct intel_encoder
*intel_encoder
;
11559 struct drm_crtc
*crtc
;
11560 struct drm_crtc_state
*crtc_state
;
11561 struct drm_connector
*connector
;
11564 intel_shared_dpll_commit(dev_priv
);
11566 for_each_intel_encoder(dev
, intel_encoder
) {
11567 if (!intel_encoder
->base
.crtc
)
11570 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
11571 if (crtc
== intel_encoder
->base
.crtc
)
11574 if (crtc
!= intel_encoder
->base
.crtc
)
11577 if (crtc_state
->enable
&& needs_modeset(crtc_state
))
11578 intel_encoder
->connectors_active
= false;
11581 intel_modeset_commit_output_state(dev
);
11583 /* Double check state. */
11584 for_each_crtc(dev
, crtc
) {
11585 WARN_ON(crtc
->state
->enable
!= intel_crtc_in_use(crtc
));
11588 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11589 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
11592 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
)
11593 if (crtc
== connector
->encoder
->crtc
)
11596 if (crtc
!= connector
->encoder
->crtc
)
11599 if (crtc_state
->enable
&& needs_modeset(crtc_state
)) {
11600 struct drm_property
*dpms_property
=
11601 dev
->mode_config
.dpms_property
;
11603 connector
->dpms
= DRM_MODE_DPMS_ON
;
11604 drm_object_property_set_value(&connector
->base
,
11608 intel_encoder
= to_intel_encoder(connector
->encoder
);
11609 intel_encoder
->connectors_active
= true;
11615 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
11619 if (clock1
== clock2
)
11622 if (!clock1
|| !clock2
)
11625 diff
= abs(clock1
- clock2
);
11627 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11633 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11634 list_for_each_entry((intel_crtc), \
11635 &(dev)->mode_config.crtc_list, \
11637 if (mask & (1 <<(intel_crtc)->pipe))
11640 intel_pipe_config_compare(struct drm_device
*dev
,
11641 struct intel_crtc_state
*current_config
,
11642 struct intel_crtc_state
*pipe_config
)
11644 #define PIPE_CONF_CHECK_X(name) \
11645 if (current_config->name != pipe_config->name) { \
11646 DRM_ERROR("mismatch in " #name " " \
11647 "(expected 0x%08x, found 0x%08x)\n", \
11648 current_config->name, \
11649 pipe_config->name); \
11653 #define PIPE_CONF_CHECK_I(name) \
11654 if (current_config->name != pipe_config->name) { \
11655 DRM_ERROR("mismatch in " #name " " \
11656 "(expected %i, found %i)\n", \
11657 current_config->name, \
11658 pipe_config->name); \
11662 /* This is required for BDW+ where there is only one set of registers for
11663 * switching between high and low RR.
11664 * This macro can be used whenever a comparison has to be made between one
11665 * hw state and multiple sw state variables.
11667 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11668 if ((current_config->name != pipe_config->name) && \
11669 (current_config->alt_name != pipe_config->name)) { \
11670 DRM_ERROR("mismatch in " #name " " \
11671 "(expected %i or %i, found %i)\n", \
11672 current_config->name, \
11673 current_config->alt_name, \
11674 pipe_config->name); \
11678 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11679 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11680 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11681 "(expected %i, found %i)\n", \
11682 current_config->name & (mask), \
11683 pipe_config->name & (mask)); \
11687 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11688 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11689 DRM_ERROR("mismatch in " #name " " \
11690 "(expected %i, found %i)\n", \
11691 current_config->name, \
11692 pipe_config->name); \
11696 #define PIPE_CONF_QUIRK(quirk) \
11697 ((current_config->quirks | pipe_config->quirks) & (quirk))
11699 PIPE_CONF_CHECK_I(cpu_transcoder
);
11701 PIPE_CONF_CHECK_I(has_pch_encoder
);
11702 PIPE_CONF_CHECK_I(fdi_lanes
);
11703 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
11704 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
11705 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
11706 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
11707 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
11709 PIPE_CONF_CHECK_I(has_dp_encoder
);
11711 if (INTEL_INFO(dev
)->gen
< 8) {
11712 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
11713 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
11714 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
11715 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
11716 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
11718 if (current_config
->has_drrs
) {
11719 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
11720 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
11721 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
11722 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
11723 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
11726 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
11727 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
11728 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
11729 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
11730 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
11733 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
11734 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
11735 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
11736 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
11737 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
11738 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
11740 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
11741 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
11742 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
11743 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
11744 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
11745 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
11747 PIPE_CONF_CHECK_I(pixel_multiplier
);
11748 PIPE_CONF_CHECK_I(has_hdmi_sink
);
11749 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
11750 IS_VALLEYVIEW(dev
))
11751 PIPE_CONF_CHECK_I(limited_color_range
);
11752 PIPE_CONF_CHECK_I(has_infoframe
);
11754 PIPE_CONF_CHECK_I(has_audio
);
11756 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11757 DRM_MODE_FLAG_INTERLACE
);
11759 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
11760 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11761 DRM_MODE_FLAG_PHSYNC
);
11762 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11763 DRM_MODE_FLAG_NHSYNC
);
11764 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11765 DRM_MODE_FLAG_PVSYNC
);
11766 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11767 DRM_MODE_FLAG_NVSYNC
);
11770 PIPE_CONF_CHECK_I(pipe_src_w
);
11771 PIPE_CONF_CHECK_I(pipe_src_h
);
11774 * FIXME: BIOS likes to set up a cloned config with lvds+external
11775 * screen. Since we don't yet re-compute the pipe config when moving
11776 * just the lvds port away to another pipe the sw tracking won't match.
11778 * Proper atomic modesets with recomputed global state will fix this.
11779 * Until then just don't check gmch state for inherited modes.
11781 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
11782 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
11783 /* pfit ratios are autocomputed by the hw on gen4+ */
11784 if (INTEL_INFO(dev
)->gen
< 4)
11785 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
11786 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
11789 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
11790 if (current_config
->pch_pfit
.enabled
) {
11791 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
11792 PIPE_CONF_CHECK_I(pch_pfit
.size
);
11795 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
11797 /* BDW+ don't expose a synchronous way to read the state */
11798 if (IS_HASWELL(dev
))
11799 PIPE_CONF_CHECK_I(ips_enabled
);
11801 PIPE_CONF_CHECK_I(double_wide
);
11803 PIPE_CONF_CHECK_X(ddi_pll_sel
);
11805 PIPE_CONF_CHECK_I(shared_dpll
);
11806 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
11807 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
11808 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
11809 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
11810 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
11811 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
11812 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
11813 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
11815 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
11816 PIPE_CONF_CHECK_I(pipe_bpp
);
11818 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
11819 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
11821 #undef PIPE_CONF_CHECK_X
11822 #undef PIPE_CONF_CHECK_I
11823 #undef PIPE_CONF_CHECK_I_ALT
11824 #undef PIPE_CONF_CHECK_FLAGS
11825 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11826 #undef PIPE_CONF_QUIRK
11831 static void check_wm_state(struct drm_device
*dev
)
11833 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11834 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
11835 struct intel_crtc
*intel_crtc
;
11838 if (INTEL_INFO(dev
)->gen
< 9)
11841 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
11842 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
11844 for_each_intel_crtc(dev
, intel_crtc
) {
11845 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
11846 const enum pipe pipe
= intel_crtc
->pipe
;
11848 if (!intel_crtc
->active
)
11852 for_each_plane(dev_priv
, pipe
, plane
) {
11853 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
11854 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
11856 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11859 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11860 "(expected (%u,%u), found (%u,%u))\n",
11861 pipe_name(pipe
), plane
+ 1,
11862 sw_entry
->start
, sw_entry
->end
,
11863 hw_entry
->start
, hw_entry
->end
);
11867 hw_entry
= &hw_ddb
.cursor
[pipe
];
11868 sw_entry
= &sw_ddb
->cursor
[pipe
];
11870 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11873 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11874 "(expected (%u,%u), found (%u,%u))\n",
11876 sw_entry
->start
, sw_entry
->end
,
11877 hw_entry
->start
, hw_entry
->end
);
11882 check_connector_state(struct drm_device
*dev
)
11884 struct intel_connector
*connector
;
11886 for_each_intel_connector(dev
, connector
) {
11887 /* This also checks the encoder/connector hw state with the
11888 * ->get_hw_state callbacks. */
11889 intel_connector_check_state(connector
);
11891 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
11892 "connector's staged encoder doesn't match current encoder\n");
11897 check_encoder_state(struct drm_device
*dev
)
11899 struct intel_encoder
*encoder
;
11900 struct intel_connector
*connector
;
11902 for_each_intel_encoder(dev
, encoder
) {
11903 bool enabled
= false;
11904 bool active
= false;
11905 enum pipe pipe
, tracked_pipe
;
11907 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11908 encoder
->base
.base
.id
,
11909 encoder
->base
.name
);
11911 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
11912 "encoder's stage crtc doesn't match current crtc\n");
11913 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
11914 "encoder's active_connectors set, but no crtc\n");
11916 for_each_intel_connector(dev
, connector
) {
11917 if (connector
->base
.encoder
!= &encoder
->base
)
11920 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
11924 * for MST connectors if we unplug the connector is gone
11925 * away but the encoder is still connected to a crtc
11926 * until a modeset happens in response to the hotplug.
11928 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
11931 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
11932 "encoder's enabled state mismatch "
11933 "(expected %i, found %i)\n",
11934 !!encoder
->base
.crtc
, enabled
);
11935 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
11936 "active encoder with no crtc\n");
11938 I915_STATE_WARN(encoder
->connectors_active
!= active
,
11939 "encoder's computed active state doesn't match tracked active state "
11940 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
11942 active
= encoder
->get_hw_state(encoder
, &pipe
);
11943 I915_STATE_WARN(active
!= encoder
->connectors_active
,
11944 "encoder's hw state doesn't match sw tracking "
11945 "(expected %i, found %i)\n",
11946 encoder
->connectors_active
, active
);
11948 if (!encoder
->base
.crtc
)
11951 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
11952 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
11953 "active encoder's pipe doesn't match"
11954 "(expected %i, found %i)\n",
11955 tracked_pipe
, pipe
);
11961 check_crtc_state(struct drm_device
*dev
)
11963 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11964 struct intel_crtc
*crtc
;
11965 struct intel_encoder
*encoder
;
11966 struct intel_crtc_state pipe_config
;
11968 for_each_intel_crtc(dev
, crtc
) {
11969 bool enabled
= false;
11970 bool active
= false;
11972 memset(&pipe_config
, 0, sizeof(pipe_config
));
11974 DRM_DEBUG_KMS("[CRTC:%d]\n",
11975 crtc
->base
.base
.id
);
11977 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
11978 "active crtc, but not enabled in sw tracking\n");
11980 for_each_intel_encoder(dev
, encoder
) {
11981 if (encoder
->base
.crtc
!= &crtc
->base
)
11984 if (encoder
->connectors_active
)
11988 I915_STATE_WARN(active
!= crtc
->active
,
11989 "crtc's computed active state doesn't match tracked active state "
11990 "(expected %i, found %i)\n", active
, crtc
->active
);
11991 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
11992 "crtc's computed enabled state doesn't match tracked enabled state "
11993 "(expected %i, found %i)\n", enabled
,
11994 crtc
->base
.state
->enable
);
11996 active
= dev_priv
->display
.get_pipe_config(crtc
,
11999 /* hw state is inconsistent with the pipe quirk */
12000 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12001 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12002 active
= crtc
->active
;
12004 for_each_intel_encoder(dev
, encoder
) {
12006 if (encoder
->base
.crtc
!= &crtc
->base
)
12008 if (encoder
->get_hw_state(encoder
, &pipe
))
12009 encoder
->get_config(encoder
, &pipe_config
);
12012 I915_STATE_WARN(crtc
->active
!= active
,
12013 "crtc active state doesn't match with hw state "
12014 "(expected %i, found %i)\n", crtc
->active
, active
);
12017 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
12018 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12019 intel_dump_pipe_config(crtc
, &pipe_config
,
12021 intel_dump_pipe_config(crtc
, crtc
->config
,
12028 check_shared_dpll_state(struct drm_device
*dev
)
12030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12031 struct intel_crtc
*crtc
;
12032 struct intel_dpll_hw_state dpll_hw_state
;
12035 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12036 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12037 int enabled_crtcs
= 0, active_crtcs
= 0;
12040 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12042 DRM_DEBUG_KMS("%s\n", pll
->name
);
12044 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12046 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12047 "more active pll users than references: %i vs %i\n",
12048 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12049 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12050 "pll in active use but not on in sw tracking\n");
12051 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12052 "pll in on but not on in use in sw tracking\n");
12053 I915_STATE_WARN(pll
->on
!= active
,
12054 "pll on state mismatch (expected %i, found %i)\n",
12057 for_each_intel_crtc(dev
, crtc
) {
12058 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12060 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12063 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12064 "pll active crtcs mismatch (expected %i, found %i)\n",
12065 pll
->active
, active_crtcs
);
12066 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12067 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12068 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12070 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12071 sizeof(dpll_hw_state
)),
12072 "pll hw state mismatch\n");
12077 intel_modeset_check_state(struct drm_device
*dev
)
12079 check_wm_state(dev
);
12080 check_connector_state(dev
);
12081 check_encoder_state(dev
);
12082 check_crtc_state(dev
);
12083 check_shared_dpll_state(dev
);
12086 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12090 * FDI already provided one idea for the dotclock.
12091 * Yell if the encoder disagrees.
12093 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12094 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12095 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12098 static void update_scanline_offset(struct intel_crtc
*crtc
)
12100 struct drm_device
*dev
= crtc
->base
.dev
;
12103 * The scanline counter increments at the leading edge of hsync.
12105 * On most platforms it starts counting from vtotal-1 on the
12106 * first active line. That means the scanline counter value is
12107 * always one less than what we would expect. Ie. just after
12108 * start of vblank, which also occurs at start of hsync (on the
12109 * last active line), the scanline counter will read vblank_start-1.
12111 * On gen2 the scanline counter starts counting from 1 instead
12112 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12113 * to keep the value positive), instead of adding one.
12115 * On HSW+ the behaviour of the scanline counter depends on the output
12116 * type. For DP ports it behaves like most other platforms, but on HDMI
12117 * there's an extra 1 line difference. So we need to add two instead of
12118 * one to the value.
12120 if (IS_GEN2(dev
)) {
12121 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
12124 vtotal
= mode
->crtc_vtotal
;
12125 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12128 crtc
->scanline_offset
= vtotal
- 1;
12129 } else if (HAS_DDI(dev
) &&
12130 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12131 crtc
->scanline_offset
= 2;
12133 crtc
->scanline_offset
= 1;
12137 intel_atomic_modeset_compute_changed_flags(struct drm_atomic_state
*state
,
12138 struct drm_crtc
*modeset_crtc
)
12140 struct drm_crtc_state
*crtc_state
;
12141 struct drm_crtc
*crtc
;
12144 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12145 if (crtc_state
->enable
!= crtc
->state
->enable
)
12146 crtc_state
->mode_changed
= true;
12148 /* FIXME: Do we need to always set mode_changed for
12149 * modeset_crtc if it is enabled? modeset_affect_pipes()
12154 static struct intel_crtc_state
*
12155 intel_modeset_compute_config(struct drm_crtc
*crtc
,
12156 struct drm_display_mode
*mode
,
12157 struct drm_atomic_state
*state
)
12159 struct intel_crtc_state
*pipe_config
;
12162 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
12164 return ERR_PTR(ret
);
12166 intel_atomic_modeset_compute_changed_flags(state
, crtc
);
12169 * Note this needs changes when we start tracking multiple modes
12170 * and crtcs. At that point we'll need to compute the whole config
12171 * (i.e. one pipe_config for each crtc) rather than just the one
12174 pipe_config
= intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));
12175 if (IS_ERR(pipe_config
))
12176 return pipe_config
;
12178 if (!pipe_config
->base
.enable
)
12179 return pipe_config
;
12181 ret
= intel_modeset_pipe_config(crtc
, mode
, state
, pipe_config
);
12183 return ERR_PTR(ret
);
12185 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,"[modeset]");
12187 return pipe_config
;
12190 static int __intel_set_mode_setup_plls(struct drm_atomic_state
*state
)
12192 struct drm_device
*dev
= state
->dev
;
12193 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12194 unsigned clear_pipes
= 0;
12195 struct intel_crtc
*intel_crtc
;
12196 struct intel_crtc_state
*intel_crtc_state
;
12197 struct drm_crtc
*crtc
;
12198 struct drm_crtc_state
*crtc_state
;
12202 if (!dev_priv
->display
.crtc_compute_clock
)
12205 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12206 intel_crtc
= to_intel_crtc(crtc
);
12208 if (needs_modeset(crtc_state
))
12209 clear_pipes
|= 1 << intel_crtc
->pipe
;
12212 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
12216 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12217 if (!needs_modeset(crtc_state
) || !crtc_state
->enable
)
12220 intel_crtc
= to_intel_crtc(crtc
);
12221 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12223 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
12226 intel_shared_dpll_abort_config(dev_priv
);
12235 static int __intel_set_mode(struct drm_crtc
*modeset_crtc
,
12236 struct drm_display_mode
*mode
,
12237 int x
, int y
, struct drm_framebuffer
*fb
,
12238 struct intel_crtc_state
*pipe_config
)
12240 struct drm_device
*dev
= modeset_crtc
->dev
;
12241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12242 struct drm_display_mode
*saved_mode
;
12243 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12244 struct intel_crtc_state
*crtc_state_copy
= NULL
;
12245 struct intel_crtc
*intel_crtc
;
12246 struct drm_crtc
*crtc
;
12247 struct drm_crtc_state
*crtc_state
;
12251 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
12255 crtc_state_copy
= kmalloc(sizeof(*crtc_state_copy
), GFP_KERNEL
);
12256 if (!crtc_state_copy
) {
12261 *saved_mode
= modeset_crtc
->mode
;
12264 * See if the config requires any additional preparation, e.g.
12265 * to adjust global state with pipes off. We need to do this
12266 * here so we can get the modeset_pipe updated config for the new
12267 * mode set on this crtc. For other crtcs we need to use the
12268 * adjusted_mode bits in the crtc directly.
12270 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
12271 ret
= valleyview_modeset_global_pipes(state
);
12276 ret
= __intel_set_mode_setup_plls(state
);
12280 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12281 if (!needs_modeset(crtc_state
))
12284 if (!crtc_state
->enable
) {
12285 intel_crtc_disable(crtc
);
12286 } else if (crtc
->state
->enable
) {
12287 intel_crtc_disable_planes(crtc
);
12288 dev_priv
->display
.crtc_disable(crtc
);
12292 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12293 * to set it here already despite that we pass it down the callchain.
12295 * Note we'll need to fix this up when we start tracking multiple
12296 * pipes; here we assume a single modeset_pipe and only track the
12297 * single crtc and mode.
12299 if (pipe_config
->base
.enable
&& needs_modeset(&pipe_config
->base
)) {
12300 modeset_crtc
->mode
= *mode
;
12301 /* mode_set/enable/disable functions rely on a correct pipe
12303 intel_crtc_set_state(to_intel_crtc(modeset_crtc
), pipe_config
);
12306 * Calculate and store various constants which
12307 * are later needed by vblank and swap-completion
12308 * timestamping. They are derived from true hwmode.
12310 drm_calc_timestamping_constants(modeset_crtc
,
12311 &pipe_config
->base
.adjusted_mode
);
12314 /* Only after disabling all output pipelines that will be changed can we
12315 * update the the output configuration. */
12316 intel_modeset_update_state(state
);
12318 modeset_update_crtc_power_domains(state
);
12320 if (pipe_config
->base
.enable
&& needs_modeset(&pipe_config
->base
)) {
12321 struct drm_plane
*primary
;
12322 int vdisplay
, hdisplay
;
12324 intel_crtc
= to_intel_crtc(modeset_crtc
);
12325 primary
= intel_crtc
->base
.primary
;
12327 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
12329 ret
= drm_plane_helper_update(primary
, &intel_crtc
->base
,
12331 hdisplay
, vdisplay
,
12333 hdisplay
<< 16, vdisplay
<< 16);
12336 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12337 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12338 if (!needs_modeset(crtc_state
) || !crtc_state
->enable
)
12341 update_scanline_offset(to_intel_crtc(crtc
));
12343 dev_priv
->display
.crtc_enable(crtc
);
12344 intel_crtc_enable_planes(crtc
);
12347 /* FIXME: add subpixel order */
12349 if (ret
&& modeset_crtc
->state
->enable
)
12350 modeset_crtc
->mode
= *saved_mode
;
12352 if (ret
== 0 && pipe_config
) {
12353 struct intel_crtc
*intel_crtc
= to_intel_crtc(modeset_crtc
);
12355 /* The pipe_config will be freed with the atomic state, so
12357 memcpy(crtc_state_copy
, intel_crtc
->config
,
12358 sizeof *crtc_state_copy
);
12359 intel_crtc
->config
= crtc_state_copy
;
12360 intel_crtc
->base
.state
= &crtc_state_copy
->base
;
12362 kfree(crtc_state_copy
);
12369 static int intel_set_mode_with_config(struct drm_crtc
*crtc
,
12370 struct drm_display_mode
*mode
,
12371 int x
, int y
, struct drm_framebuffer
*fb
,
12372 struct intel_crtc_state
*pipe_config
)
12376 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
);
12379 intel_modeset_check_state(crtc
->dev
);
12384 static int intel_set_mode(struct drm_crtc
*crtc
,
12385 struct drm_display_mode
*mode
,
12386 int x
, int y
, struct drm_framebuffer
*fb
,
12387 struct drm_atomic_state
*state
)
12389 struct intel_crtc_state
*pipe_config
;
12392 pipe_config
= intel_modeset_compute_config(crtc
, mode
, state
);
12393 if (IS_ERR(pipe_config
)) {
12394 ret
= PTR_ERR(pipe_config
);
12398 ret
= intel_set_mode_with_config(crtc
, mode
, x
, y
, fb
, pipe_config
);
12406 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
12408 struct drm_device
*dev
= crtc
->dev
;
12409 struct drm_atomic_state
*state
;
12410 struct intel_crtc
*intel_crtc
;
12411 struct intel_encoder
*encoder
;
12412 struct intel_connector
*connector
;
12413 struct drm_connector_state
*connector_state
;
12414 struct intel_crtc_state
*crtc_state
;
12416 state
= drm_atomic_state_alloc(dev
);
12418 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12423 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12425 /* The force restore path in the HW readout code relies on the staged
12426 * config still keeping the user requested config while the actual
12427 * state has been overwritten by the configuration read from HW. We
12428 * need to copy the staged config to the atomic state, otherwise the
12429 * mode set will just reapply the state the HW is already in. */
12430 for_each_intel_encoder(dev
, encoder
) {
12431 if (&encoder
->new_crtc
->base
!= crtc
)
12434 for_each_intel_connector(dev
, connector
) {
12435 if (connector
->new_encoder
!= encoder
)
12438 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
12439 if (IS_ERR(connector_state
)) {
12440 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12441 connector
->base
.base
.id
,
12442 connector
->base
.name
,
12443 PTR_ERR(connector_state
));
12447 connector_state
->crtc
= crtc
;
12448 connector_state
->best_encoder
= &encoder
->base
;
12452 for_each_intel_crtc(dev
, intel_crtc
) {
12453 if (intel_crtc
->new_enabled
== intel_crtc
->base
.enabled
)
12456 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12457 if (IS_ERR(crtc_state
)) {
12458 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12459 intel_crtc
->base
.base
.id
,
12460 PTR_ERR(crtc_state
));
12464 crtc_state
->base
.enable
= intel_crtc
->new_enabled
;
12467 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
,
12470 drm_atomic_state_free(state
);
12473 #undef for_each_intel_crtc_masked
12475 static void intel_set_config_free(struct intel_set_config
*config
)
12480 kfree(config
->save_connector_encoders
);
12481 kfree(config
->save_encoder_crtcs
);
12482 kfree(config
->save_crtc_enabled
);
12486 static int intel_set_config_save_state(struct drm_device
*dev
,
12487 struct intel_set_config
*config
)
12489 struct drm_crtc
*crtc
;
12490 struct drm_encoder
*encoder
;
12491 struct drm_connector
*connector
;
12494 config
->save_crtc_enabled
=
12495 kcalloc(dev
->mode_config
.num_crtc
,
12496 sizeof(bool), GFP_KERNEL
);
12497 if (!config
->save_crtc_enabled
)
12500 config
->save_encoder_crtcs
=
12501 kcalloc(dev
->mode_config
.num_encoder
,
12502 sizeof(struct drm_crtc
*), GFP_KERNEL
);
12503 if (!config
->save_encoder_crtcs
)
12506 config
->save_connector_encoders
=
12507 kcalloc(dev
->mode_config
.num_connector
,
12508 sizeof(struct drm_encoder
*), GFP_KERNEL
);
12509 if (!config
->save_connector_encoders
)
12512 /* Copy data. Note that driver private data is not affected.
12513 * Should anything bad happen only the expected state is
12514 * restored, not the drivers personal bookkeeping.
12517 for_each_crtc(dev
, crtc
) {
12518 config
->save_crtc_enabled
[count
++] = crtc
->state
->enable
;
12522 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
12523 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
12527 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
12528 config
->save_connector_encoders
[count
++] = connector
->encoder
;
12534 static void intel_set_config_restore_state(struct drm_device
*dev
,
12535 struct intel_set_config
*config
)
12537 struct intel_crtc
*crtc
;
12538 struct intel_encoder
*encoder
;
12539 struct intel_connector
*connector
;
12543 for_each_intel_crtc(dev
, crtc
) {
12544 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
12548 for_each_intel_encoder(dev
, encoder
) {
12549 encoder
->new_crtc
=
12550 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
12554 for_each_intel_connector(dev
, connector
) {
12555 connector
->new_encoder
=
12556 to_intel_encoder(config
->save_connector_encoders
[count
++]);
12561 is_crtc_connector_off(struct drm_mode_set
*set
)
12565 if (set
->num_connectors
== 0)
12568 if (WARN_ON(set
->connectors
== NULL
))
12571 for (i
= 0; i
< set
->num_connectors
; i
++)
12572 if (set
->connectors
[i
]->encoder
&&
12573 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
12574 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
12581 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
12582 struct intel_set_config
*config
)
12584 struct drm_device
*dev
= set
->crtc
->dev
;
12585 struct intel_connector
*connector
;
12586 struct intel_encoder
*encoder
;
12587 struct intel_crtc
*crtc
;
12589 /* We should be able to check here if the fb has the same properties
12590 * and then just flip_or_move it */
12591 if (is_crtc_connector_off(set
)) {
12592 config
->mode_changed
= true;
12593 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
12595 * If we have no fb, we can only flip as long as the crtc is
12596 * active, otherwise we need a full mode set. The crtc may
12597 * be active if we've only disabled the primary plane, or
12598 * in fastboot situations.
12600 if (set
->crtc
->primary
->fb
== NULL
) {
12601 struct intel_crtc
*intel_crtc
=
12602 to_intel_crtc(set
->crtc
);
12604 if (intel_crtc
->active
) {
12605 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12606 config
->fb_changed
= true;
12608 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12609 config
->mode_changed
= true;
12611 } else if (set
->fb
== NULL
) {
12612 config
->mode_changed
= true;
12613 } else if (set
->fb
->pixel_format
!=
12614 set
->crtc
->primary
->fb
->pixel_format
) {
12615 config
->mode_changed
= true;
12617 config
->fb_changed
= true;
12621 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
12622 config
->fb_changed
= true;
12624 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
12625 DRM_DEBUG_KMS("modes are different, full mode set\n");
12626 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
12627 drm_mode_debug_printmodeline(set
->mode
);
12628 config
->mode_changed
= true;
12631 for_each_intel_connector(dev
, connector
) {
12632 if (&connector
->new_encoder
->base
== connector
->base
.encoder
)
12635 config
->mode_changed
= true;
12636 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12637 connector
->base
.base
.id
,
12638 connector
->base
.name
);
12641 for_each_intel_encoder(dev
, encoder
) {
12642 if (&encoder
->new_crtc
->base
== encoder
->base
.crtc
)
12645 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12646 encoder
->base
.base
.id
,
12647 encoder
->base
.name
);
12648 config
->mode_changed
= true;
12651 for_each_intel_crtc(dev
, crtc
) {
12652 if (crtc
->new_enabled
== crtc
->base
.state
->enable
)
12655 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12656 crtc
->base
.base
.id
,
12657 crtc
->new_enabled
? "en" : "dis");
12658 config
->mode_changed
= true;
12661 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12662 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
12666 intel_modeset_stage_output_state(struct drm_device
*dev
,
12667 struct drm_mode_set
*set
,
12668 struct drm_atomic_state
*state
)
12670 struct intel_connector
*connector
;
12671 struct drm_connector_state
*connector_state
;
12672 struct intel_encoder
*encoder
;
12673 struct intel_crtc
*crtc
;
12674 struct intel_crtc_state
*crtc_state
;
12677 /* The upper layers ensure that we either disable a crtc or have a list
12678 * of connectors. For paranoia, double-check this. */
12679 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
12680 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
12682 for_each_intel_connector(dev
, connector
) {
12683 /* Otherwise traverse passed in connector list and get encoders
12685 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
12686 if (set
->connectors
[ro
] == &connector
->base
) {
12687 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
12692 /* If we disable the crtc, disable all its connectors. Also, if
12693 * the connector is on the changing crtc but not on the new
12694 * connector list, disable it. */
12695 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
12696 connector
->base
.encoder
&&
12697 connector
->base
.encoder
->crtc
== set
->crtc
) {
12698 connector
->new_encoder
= NULL
;
12700 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12701 connector
->base
.base
.id
,
12702 connector
->base
.name
);
12705 /* connector->new_encoder is now updated for all connectors. */
12707 /* Update crtc of enabled connectors. */
12708 for_each_intel_connector(dev
, connector
) {
12709 struct drm_crtc
*new_crtc
;
12711 if (!connector
->new_encoder
)
12714 new_crtc
= connector
->new_encoder
->base
.crtc
;
12716 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
12717 if (set
->connectors
[ro
] == &connector
->base
)
12718 new_crtc
= set
->crtc
;
12721 /* Make sure the new CRTC will work with the encoder */
12722 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
12726 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
12729 drm_atomic_get_connector_state(state
, &connector
->base
);
12730 if (IS_ERR(connector_state
))
12731 return PTR_ERR(connector_state
);
12733 connector_state
->crtc
= new_crtc
;
12734 connector_state
->best_encoder
= &connector
->new_encoder
->base
;
12736 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12737 connector
->base
.base
.id
,
12738 connector
->base
.name
,
12739 new_crtc
->base
.id
);
12742 /* Check for any encoders that needs to be disabled. */
12743 for_each_intel_encoder(dev
, encoder
) {
12744 int num_connectors
= 0;
12745 for_each_intel_connector(dev
, connector
) {
12746 if (connector
->new_encoder
== encoder
) {
12747 WARN_ON(!connector
->new_encoder
->new_crtc
);
12752 if (num_connectors
== 0)
12753 encoder
->new_crtc
= NULL
;
12754 else if (num_connectors
> 1)
12757 /* Now we've also updated encoder->new_crtc for all encoders. */
12758 for_each_intel_connector(dev
, connector
) {
12760 drm_atomic_get_connector_state(state
, &connector
->base
);
12761 if (IS_ERR(connector_state
))
12762 return PTR_ERR(connector_state
);
12764 if (connector
->new_encoder
) {
12765 if (connector
->new_encoder
!= connector
->encoder
)
12766 connector
->encoder
= connector
->new_encoder
;
12768 connector_state
->crtc
= NULL
;
12769 connector_state
->best_encoder
= NULL
;
12772 for_each_intel_crtc(dev
, crtc
) {
12773 crtc
->new_enabled
= false;
12775 for_each_intel_encoder(dev
, encoder
) {
12776 if (encoder
->new_crtc
== crtc
) {
12777 crtc
->new_enabled
= true;
12782 if (crtc
->new_enabled
!= crtc
->base
.state
->enable
) {
12783 crtc_state
= intel_atomic_get_crtc_state(state
, crtc
);
12784 if (IS_ERR(crtc_state
))
12785 return PTR_ERR(crtc_state
);
12787 crtc_state
->base
.enable
= crtc
->new_enabled
;
12794 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
12796 struct drm_device
*dev
= crtc
->base
.dev
;
12797 struct intel_encoder
*encoder
;
12798 struct intel_connector
*connector
;
12800 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12801 pipe_name(crtc
->pipe
));
12803 for_each_intel_connector(dev
, connector
) {
12804 if (connector
->new_encoder
&&
12805 connector
->new_encoder
->new_crtc
== crtc
)
12806 connector
->new_encoder
= NULL
;
12809 for_each_intel_encoder(dev
, encoder
) {
12810 if (encoder
->new_crtc
== crtc
)
12811 encoder
->new_crtc
= NULL
;
12814 crtc
->new_enabled
= false;
12817 static int intel_crtc_set_config(struct drm_mode_set
*set
)
12819 struct drm_device
*dev
;
12820 struct drm_mode_set save_set
;
12821 struct drm_atomic_state
*state
= NULL
;
12822 struct intel_set_config
*config
;
12823 struct intel_crtc_state
*pipe_config
;
12827 BUG_ON(!set
->crtc
);
12828 BUG_ON(!set
->crtc
->helper_private
);
12830 /* Enforce sane interface api - has been abused by the fb helper. */
12831 BUG_ON(!set
->mode
&& set
->fb
);
12832 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
12835 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12836 set
->crtc
->base
.id
, set
->fb
->base
.id
,
12837 (int)set
->num_connectors
, set
->x
, set
->y
);
12839 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
12842 dev
= set
->crtc
->dev
;
12845 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
12849 ret
= intel_set_config_save_state(dev
, config
);
12853 save_set
.crtc
= set
->crtc
;
12854 save_set
.mode
= &set
->crtc
->mode
;
12855 save_set
.x
= set
->crtc
->x
;
12856 save_set
.y
= set
->crtc
->y
;
12857 save_set
.fb
= set
->crtc
->primary
->fb
;
12859 state
= drm_atomic_state_alloc(dev
);
12865 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12867 ret
= intel_modeset_stage_output_state(dev
, set
, state
);
12871 /* Compute whether we need a full modeset, only an fb base update or no
12872 * change at all. In the future we might also check whether only the
12873 * mode changed, e.g. for LVDS where we only change the panel fitter in
12875 intel_set_config_compute_mode_changes(set
, config
);
12877 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
12879 if (IS_ERR(pipe_config
)) {
12880 ret
= PTR_ERR(pipe_config
);
12882 } else if (pipe_config
) {
12883 if (pipe_config
->has_audio
!=
12884 to_intel_crtc(set
->crtc
)->config
->has_audio
)
12885 config
->mode_changed
= true;
12888 * Note we have an issue here with infoframes: current code
12889 * only updates them on the full mode set path per hw
12890 * requirements. So here we should be checking for any
12891 * required changes and forcing a mode set.
12895 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
12897 if (config
->mode_changed
) {
12898 ret
= intel_set_mode_with_config(set
->crtc
, set
->mode
,
12899 set
->x
, set
->y
, set
->fb
,
12901 } else if (config
->fb_changed
) {
12902 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
12903 struct drm_plane
*primary
= set
->crtc
->primary
;
12904 struct intel_plane_state
*plane_state
=
12905 to_intel_plane_state(primary
->state
);
12906 bool was_visible
= plane_state
->visible
;
12907 int vdisplay
, hdisplay
;
12909 drm_crtc_get_hv_timing(set
->mode
, &hdisplay
, &vdisplay
);
12910 ret
= drm_plane_helper_update(primary
, set
->crtc
, set
->fb
,
12911 0, 0, hdisplay
, vdisplay
,
12912 set
->x
<< 16, set
->y
<< 16,
12913 hdisplay
<< 16, vdisplay
<< 16);
12916 * We need to make sure the primary plane is re-enabled if it
12917 * has previously been turned off.
12919 plane_state
= to_intel_plane_state(primary
->state
);
12920 if (ret
== 0 && !was_visible
&& plane_state
->visible
) {
12921 WARN_ON(!intel_crtc
->active
);
12922 intel_post_enable_primary(set
->crtc
);
12926 * In the fastboot case this may be our only check of the
12927 * state after boot. It would be better to only do it on
12928 * the first update, but we don't have a nice way of doing that
12929 * (and really, set_config isn't used much for high freq page
12930 * flipping, so increasing its cost here shouldn't be a big
12933 if (i915
.fastboot
&& ret
== 0)
12934 intel_modeset_check_state(set
->crtc
->dev
);
12938 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12939 set
->crtc
->base
.id
, ret
);
12941 intel_set_config_restore_state(dev
, config
);
12943 drm_atomic_state_clear(state
);
12946 * HACK: if the pipe was on, but we didn't have a framebuffer,
12947 * force the pipe off to avoid oopsing in the modeset code
12948 * due to fb==NULL. This should only happen during boot since
12949 * we don't yet reconstruct the FB from the hardware state.
12951 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
12952 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
12954 /* Try to restore the config */
12955 if (config
->mode_changed
&&
12956 intel_set_mode(save_set
.crtc
, save_set
.mode
,
12957 save_set
.x
, save_set
.y
, save_set
.fb
,
12959 DRM_ERROR("failed to restore config after modeset failure\n");
12963 drm_atomic_state_free(state
);
12965 intel_set_config_free(config
);
12969 static const struct drm_crtc_funcs intel_crtc_funcs
= {
12970 .gamma_set
= intel_crtc_gamma_set
,
12971 .set_config
= intel_crtc_set_config
,
12972 .destroy
= intel_crtc_destroy
,
12973 .page_flip
= intel_crtc_page_flip
,
12974 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
12975 .atomic_destroy_state
= intel_crtc_destroy_state
,
12978 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
12979 struct intel_shared_dpll
*pll
,
12980 struct intel_dpll_hw_state
*hw_state
)
12984 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
12987 val
= I915_READ(PCH_DPLL(pll
->id
));
12988 hw_state
->dpll
= val
;
12989 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
12990 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
12992 return val
& DPLL_VCO_ENABLE
;
12995 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
12996 struct intel_shared_dpll
*pll
)
12998 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
12999 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
13002 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
13003 struct intel_shared_dpll
*pll
)
13005 /* PCH refclock must be enabled first */
13006 ibx_assert_pch_refclk_enabled(dev_priv
);
13008 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13010 /* Wait for the clocks to stabilize. */
13011 POSTING_READ(PCH_DPLL(pll
->id
));
13014 /* The pixel multiplier can only be updated once the
13015 * DPLL is enabled and the clocks are stable.
13017 * So write it again.
13019 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13020 POSTING_READ(PCH_DPLL(pll
->id
));
13024 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
13025 struct intel_shared_dpll
*pll
)
13027 struct drm_device
*dev
= dev_priv
->dev
;
13028 struct intel_crtc
*crtc
;
13030 /* Make sure no transcoder isn't still depending on us. */
13031 for_each_intel_crtc(dev
, crtc
) {
13032 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
13033 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
13036 I915_WRITE(PCH_DPLL(pll
->id
), 0);
13037 POSTING_READ(PCH_DPLL(pll
->id
));
13041 static char *ibx_pch_dpll_names
[] = {
13046 static void ibx_pch_dpll_init(struct drm_device
*dev
)
13048 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13051 dev_priv
->num_shared_dpll
= 2;
13053 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13054 dev_priv
->shared_dplls
[i
].id
= i
;
13055 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
13056 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
13057 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
13058 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
13059 dev_priv
->shared_dplls
[i
].get_hw_state
=
13060 ibx_pch_dpll_get_hw_state
;
13064 static void intel_shared_dpll_init(struct drm_device
*dev
)
13066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13069 intel_ddi_pll_init(dev
);
13070 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13071 ibx_pch_dpll_init(dev
);
13073 dev_priv
->num_shared_dpll
= 0;
13075 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
13079 * intel_wm_need_update - Check whether watermarks need updating
13080 * @plane: drm plane
13081 * @state: new plane state
13083 * Check current plane state versus the new one to determine whether
13084 * watermarks need to be recalculated.
13086 * Returns true or false.
13088 bool intel_wm_need_update(struct drm_plane
*plane
,
13089 struct drm_plane_state
*state
)
13091 /* Update watermarks on tiling changes. */
13092 if (!plane
->state
->fb
|| !state
->fb
||
13093 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
13094 plane
->state
->rotation
!= state
->rotation
)
13101 * intel_prepare_plane_fb - Prepare fb for usage on plane
13102 * @plane: drm plane to prepare for
13103 * @fb: framebuffer to prepare for presentation
13105 * Prepares a framebuffer for usage on a display plane. Generally this
13106 * involves pinning the underlying object and updating the frontbuffer tracking
13107 * bits. Some older platforms need special physical address handling for
13110 * Returns 0 on success, negative error code on failure.
13113 intel_prepare_plane_fb(struct drm_plane
*plane
,
13114 struct drm_framebuffer
*fb
,
13115 const struct drm_plane_state
*new_state
)
13117 struct drm_device
*dev
= plane
->dev
;
13118 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13119 enum pipe pipe
= intel_plane
->pipe
;
13120 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13121 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
13122 unsigned frontbuffer_bits
= 0;
13128 switch (plane
->type
) {
13129 case DRM_PLANE_TYPE_PRIMARY
:
13130 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13132 case DRM_PLANE_TYPE_CURSOR
:
13133 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13135 case DRM_PLANE_TYPE_OVERLAY
:
13136 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
13140 mutex_lock(&dev
->struct_mutex
);
13142 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13143 INTEL_INFO(dev
)->cursor_needs_physical
) {
13144 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13145 ret
= i915_gem_object_attach_phys(obj
, align
);
13147 DRM_DEBUG_KMS("failed to attach phys object\n");
13149 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
13153 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
13155 mutex_unlock(&dev
->struct_mutex
);
13161 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13162 * @plane: drm plane to clean up for
13163 * @fb: old framebuffer that was on plane
13165 * Cleans up a framebuffer that has just been removed from a plane.
13168 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13169 struct drm_framebuffer
*fb
,
13170 const struct drm_plane_state
*old_state
)
13172 struct drm_device
*dev
= plane
->dev
;
13173 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13178 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13179 !INTEL_INFO(dev
)->cursor_needs_physical
) {
13180 mutex_lock(&dev
->struct_mutex
);
13181 intel_unpin_fb_obj(fb
, old_state
);
13182 mutex_unlock(&dev
->struct_mutex
);
13187 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13190 struct drm_device
*dev
;
13191 struct drm_i915_private
*dev_priv
;
13192 int crtc_clock
, cdclk
;
13194 if (!intel_crtc
|| !crtc_state
)
13195 return DRM_PLANE_HELPER_NO_SCALING
;
13197 dev
= intel_crtc
->base
.dev
;
13198 dev_priv
= dev
->dev_private
;
13199 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13200 cdclk
= dev_priv
->display
.get_display_clock_speed(dev
);
13202 if (!crtc_clock
|| !cdclk
)
13203 return DRM_PLANE_HELPER_NO_SCALING
;
13206 * skl max scale is lower of:
13207 * close to 3 but not 3, -1 is for that purpose
13211 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13217 intel_check_primary_plane(struct drm_plane
*plane
,
13218 struct intel_plane_state
*state
)
13220 struct drm_device
*dev
= plane
->dev
;
13221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13222 struct drm_crtc
*crtc
= state
->base
.crtc
;
13223 struct intel_crtc
*intel_crtc
;
13224 struct intel_crtc_state
*crtc_state
;
13225 struct drm_framebuffer
*fb
= state
->base
.fb
;
13226 struct drm_rect
*dest
= &state
->dst
;
13227 struct drm_rect
*src
= &state
->src
;
13228 const struct drm_rect
*clip
= &state
->clip
;
13229 bool can_position
= false;
13230 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13231 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13234 crtc
= crtc
? crtc
: plane
->crtc
;
13235 intel_crtc
= to_intel_crtc(crtc
);
13236 crtc_state
= state
->base
.state
?
13237 intel_atomic_get_crtc_state(state
->base
.state
, intel_crtc
) : NULL
;
13239 if (INTEL_INFO(dev
)->gen
>= 9) {
13241 max_scale
= skl_max_scale(intel_crtc
, crtc_state
);
13242 can_position
= true;
13245 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13249 can_position
, true,
13254 if (intel_crtc
->active
) {
13255 struct intel_plane_state
*old_state
=
13256 to_intel_plane_state(plane
->state
);
13258 intel_crtc
->atomic
.wait_for_flips
= true;
13261 * FBC does not work on some platforms for rotated
13262 * planes, so disable it when rotation is not 0 and
13263 * update it when rotation is set back to 0.
13265 * FIXME: This is redundant with the fbc update done in
13266 * the primary plane enable function except that that
13267 * one is done too late. We eventually need to unify
13270 if (state
->visible
&&
13271 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
13272 dev_priv
->fbc
.crtc
== intel_crtc
&&
13273 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
13274 intel_crtc
->atomic
.disable_fbc
= true;
13277 if (state
->visible
&& !old_state
->visible
) {
13279 * BDW signals flip done immediately if the plane
13280 * is disabled, even if the plane enable is already
13281 * armed to occur at the next vblank :(
13283 if (IS_BROADWELL(dev
))
13284 intel_crtc
->atomic
.wait_vblank
= true;
13287 intel_crtc
->atomic
.fb_bits
|=
13288 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
13290 intel_crtc
->atomic
.update_fbc
= true;
13292 if (intel_wm_need_update(plane
, &state
->base
))
13293 intel_crtc
->atomic
.update_wm
= true;
13296 if (INTEL_INFO(dev
)->gen
>= 9) {
13297 ret
= skl_update_scaler_users(intel_crtc
, crtc_state
,
13298 to_intel_plane(plane
), state
, 0);
13307 intel_commit_primary_plane(struct drm_plane
*plane
,
13308 struct intel_plane_state
*state
)
13310 struct drm_crtc
*crtc
= state
->base
.crtc
;
13311 struct drm_framebuffer
*fb
= state
->base
.fb
;
13312 struct drm_device
*dev
= plane
->dev
;
13313 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13314 struct intel_crtc
*intel_crtc
;
13315 struct drm_rect
*src
= &state
->src
;
13317 crtc
= crtc
? crtc
: plane
->crtc
;
13318 intel_crtc
= to_intel_crtc(crtc
);
13321 crtc
->x
= src
->x1
>> 16;
13322 crtc
->y
= src
->y1
>> 16;
13324 if (intel_crtc
->active
) {
13325 if (state
->visible
)
13326 /* FIXME: kill this fastboot hack */
13327 intel_update_pipe_size(intel_crtc
);
13329 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
13335 intel_disable_primary_plane(struct drm_plane
*plane
,
13336 struct drm_crtc
*crtc
,
13339 struct drm_device
*dev
= plane
->dev
;
13340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13342 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13345 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
13347 struct drm_device
*dev
= crtc
->dev
;
13348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13349 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13350 struct intel_plane
*intel_plane
;
13351 struct drm_plane
*p
;
13352 unsigned fb_bits
= 0;
13354 /* Track fb's for any planes being disabled */
13355 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
13356 intel_plane
= to_intel_plane(p
);
13358 if (intel_crtc
->atomic
.disabled_planes
&
13359 (1 << drm_plane_index(p
))) {
13361 case DRM_PLANE_TYPE_PRIMARY
:
13362 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
13364 case DRM_PLANE_TYPE_CURSOR
:
13365 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
13367 case DRM_PLANE_TYPE_OVERLAY
:
13368 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
13372 mutex_lock(&dev
->struct_mutex
);
13373 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
13374 mutex_unlock(&dev
->struct_mutex
);
13378 if (intel_crtc
->atomic
.wait_for_flips
)
13379 intel_crtc_wait_for_pending_flips(crtc
);
13381 if (intel_crtc
->atomic
.disable_fbc
)
13382 intel_fbc_disable(dev
);
13384 if (intel_crtc
->atomic
.pre_disable_primary
)
13385 intel_pre_disable_primary(crtc
);
13387 if (intel_crtc
->atomic
.update_wm
)
13388 intel_update_watermarks(crtc
);
13390 intel_runtime_pm_get(dev_priv
);
13392 /* Perform vblank evasion around commit operation */
13393 if (intel_crtc
->active
)
13394 intel_crtc
->atomic
.evade
=
13395 intel_pipe_update_start(intel_crtc
,
13396 &intel_crtc
->atomic
.start_vbl_count
);
13399 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
13401 struct drm_device
*dev
= crtc
->dev
;
13402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13403 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13404 struct drm_plane
*p
;
13406 if (intel_crtc
->atomic
.evade
)
13407 intel_pipe_update_end(intel_crtc
,
13408 intel_crtc
->atomic
.start_vbl_count
);
13410 intel_runtime_pm_put(dev_priv
);
13412 if (intel_crtc
->atomic
.wait_vblank
)
13413 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
13415 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
13417 if (intel_crtc
->atomic
.update_fbc
) {
13418 mutex_lock(&dev
->struct_mutex
);
13419 intel_fbc_update(dev
);
13420 mutex_unlock(&dev
->struct_mutex
);
13423 if (intel_crtc
->atomic
.post_enable_primary
)
13424 intel_post_enable_primary(crtc
);
13426 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
13427 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
13428 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
13431 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
13435 * intel_plane_destroy - destroy a plane
13436 * @plane: plane to destroy
13438 * Common destruction function for all types of planes (primary, cursor,
13441 void intel_plane_destroy(struct drm_plane
*plane
)
13443 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13444 drm_plane_cleanup(plane
);
13445 kfree(intel_plane
);
13448 const struct drm_plane_funcs intel_plane_funcs
= {
13449 .update_plane
= drm_atomic_helper_update_plane
,
13450 .disable_plane
= drm_atomic_helper_disable_plane
,
13451 .destroy
= intel_plane_destroy
,
13452 .set_property
= drm_atomic_helper_plane_set_property
,
13453 .atomic_get_property
= intel_plane_atomic_get_property
,
13454 .atomic_set_property
= intel_plane_atomic_set_property
,
13455 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13456 .atomic_destroy_state
= intel_plane_destroy_state
,
13460 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13463 struct intel_plane
*primary
;
13464 struct intel_plane_state
*state
;
13465 const uint32_t *intel_primary_formats
;
13468 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13469 if (primary
== NULL
)
13472 state
= intel_create_plane_state(&primary
->base
);
13477 primary
->base
.state
= &state
->base
;
13479 primary
->can_scale
= false;
13480 primary
->max_downscale
= 1;
13481 if (INTEL_INFO(dev
)->gen
>= 9) {
13482 primary
->can_scale
= true;
13484 state
->scaler_id
= -1;
13485 primary
->pipe
= pipe
;
13486 primary
->plane
= pipe
;
13487 primary
->check_plane
= intel_check_primary_plane
;
13488 primary
->commit_plane
= intel_commit_primary_plane
;
13489 primary
->disable_plane
= intel_disable_primary_plane
;
13490 primary
->ckey
.flags
= I915_SET_COLORKEY_NONE
;
13491 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13492 primary
->plane
= !pipe
;
13494 if (INTEL_INFO(dev
)->gen
<= 3) {
13495 intel_primary_formats
= intel_primary_formats_gen2
;
13496 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
13498 intel_primary_formats
= intel_primary_formats_gen4
;
13499 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
13502 drm_universal_plane_init(dev
, &primary
->base
, 0,
13503 &intel_plane_funcs
,
13504 intel_primary_formats
, num_formats
,
13505 DRM_PLANE_TYPE_PRIMARY
);
13507 if (INTEL_INFO(dev
)->gen
>= 4)
13508 intel_create_rotation_property(dev
, primary
);
13510 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13512 return &primary
->base
;
13515 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13517 if (!dev
->mode_config
.rotation_property
) {
13518 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13519 BIT(DRM_ROTATE_180
);
13521 if (INTEL_INFO(dev
)->gen
>= 9)
13522 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13524 dev
->mode_config
.rotation_property
=
13525 drm_mode_create_rotation_property(dev
, flags
);
13527 if (dev
->mode_config
.rotation_property
)
13528 drm_object_attach_property(&plane
->base
.base
,
13529 dev
->mode_config
.rotation_property
,
13530 plane
->base
.state
->rotation
);
13534 intel_check_cursor_plane(struct drm_plane
*plane
,
13535 struct intel_plane_state
*state
)
13537 struct drm_crtc
*crtc
= state
->base
.crtc
;
13538 struct drm_device
*dev
= plane
->dev
;
13539 struct drm_framebuffer
*fb
= state
->base
.fb
;
13540 struct drm_rect
*dest
= &state
->dst
;
13541 struct drm_rect
*src
= &state
->src
;
13542 const struct drm_rect
*clip
= &state
->clip
;
13543 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13544 struct intel_crtc
*intel_crtc
;
13548 crtc
= crtc
? crtc
: plane
->crtc
;
13549 intel_crtc
= to_intel_crtc(crtc
);
13551 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
13553 DRM_PLANE_HELPER_NO_SCALING
,
13554 DRM_PLANE_HELPER_NO_SCALING
,
13555 true, true, &state
->visible
);
13560 /* if we want to turn off the cursor ignore width and height */
13564 /* Check for which cursor types we support */
13565 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
13566 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13567 state
->base
.crtc_w
, state
->base
.crtc_h
);
13571 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
13572 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
13573 DRM_DEBUG_KMS("buffer is too small\n");
13577 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
13578 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13583 if (intel_crtc
->active
) {
13584 if (plane
->state
->crtc_w
!= state
->base
.crtc_w
)
13585 intel_crtc
->atomic
.update_wm
= true;
13587 intel_crtc
->atomic
.fb_bits
|=
13588 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
13595 intel_disable_cursor_plane(struct drm_plane
*plane
,
13596 struct drm_crtc
*crtc
,
13599 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13603 intel_crtc
->cursor_bo
= NULL
;
13604 intel_crtc
->cursor_addr
= 0;
13607 intel_crtc_update_cursor(crtc
, false);
13611 intel_commit_cursor_plane(struct drm_plane
*plane
,
13612 struct intel_plane_state
*state
)
13614 struct drm_crtc
*crtc
= state
->base
.crtc
;
13615 struct drm_device
*dev
= plane
->dev
;
13616 struct intel_crtc
*intel_crtc
;
13617 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
13620 crtc
= crtc
? crtc
: plane
->crtc
;
13621 intel_crtc
= to_intel_crtc(crtc
);
13623 plane
->fb
= state
->base
.fb
;
13624 crtc
->cursor_x
= state
->base
.crtc_x
;
13625 crtc
->cursor_y
= state
->base
.crtc_y
;
13627 if (intel_crtc
->cursor_bo
== obj
)
13632 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
13633 addr
= i915_gem_obj_ggtt_offset(obj
);
13635 addr
= obj
->phys_handle
->busaddr
;
13637 intel_crtc
->cursor_addr
= addr
;
13638 intel_crtc
->cursor_bo
= obj
;
13641 if (intel_crtc
->active
)
13642 intel_crtc_update_cursor(crtc
, state
->visible
);
13645 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13648 struct intel_plane
*cursor
;
13649 struct intel_plane_state
*state
;
13651 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13652 if (cursor
== NULL
)
13655 state
= intel_create_plane_state(&cursor
->base
);
13660 cursor
->base
.state
= &state
->base
;
13662 cursor
->can_scale
= false;
13663 cursor
->max_downscale
= 1;
13664 cursor
->pipe
= pipe
;
13665 cursor
->plane
= pipe
;
13666 state
->scaler_id
= -1;
13667 cursor
->check_plane
= intel_check_cursor_plane
;
13668 cursor
->commit_plane
= intel_commit_cursor_plane
;
13669 cursor
->disable_plane
= intel_disable_cursor_plane
;
13671 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13672 &intel_plane_funcs
,
13673 intel_cursor_formats
,
13674 ARRAY_SIZE(intel_cursor_formats
),
13675 DRM_PLANE_TYPE_CURSOR
);
13677 if (INTEL_INFO(dev
)->gen
>= 4) {
13678 if (!dev
->mode_config
.rotation_property
)
13679 dev
->mode_config
.rotation_property
=
13680 drm_mode_create_rotation_property(dev
,
13681 BIT(DRM_ROTATE_0
) |
13682 BIT(DRM_ROTATE_180
));
13683 if (dev
->mode_config
.rotation_property
)
13684 drm_object_attach_property(&cursor
->base
.base
,
13685 dev
->mode_config
.rotation_property
,
13686 state
->base
.rotation
);
13689 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13691 return &cursor
->base
;
13694 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
13695 struct intel_crtc_state
*crtc_state
)
13698 struct intel_scaler
*intel_scaler
;
13699 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
13701 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
13702 intel_scaler
= &scaler_state
->scalers
[i
];
13703 intel_scaler
->in_use
= 0;
13704 intel_scaler
->id
= i
;
13706 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
13709 scaler_state
->scaler_id
= -1;
13712 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13714 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13715 struct intel_crtc
*intel_crtc
;
13716 struct intel_crtc_state
*crtc_state
= NULL
;
13717 struct drm_plane
*primary
= NULL
;
13718 struct drm_plane
*cursor
= NULL
;
13721 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13722 if (intel_crtc
== NULL
)
13725 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13728 intel_crtc_set_state(intel_crtc
, crtc_state
);
13729 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13731 /* initialize shared scalers */
13732 if (INTEL_INFO(dev
)->gen
>= 9) {
13733 if (pipe
== PIPE_C
)
13734 intel_crtc
->num_scalers
= 1;
13736 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
13738 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
13741 primary
= intel_primary_plane_create(dev
, pipe
);
13745 cursor
= intel_cursor_plane_create(dev
, pipe
);
13749 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13750 cursor
, &intel_crtc_funcs
);
13754 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13755 for (i
= 0; i
< 256; i
++) {
13756 intel_crtc
->lut_r
[i
] = i
;
13757 intel_crtc
->lut_g
[i
] = i
;
13758 intel_crtc
->lut_b
[i
] = i
;
13762 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13763 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13765 intel_crtc
->pipe
= pipe
;
13766 intel_crtc
->plane
= pipe
;
13767 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13768 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13769 intel_crtc
->plane
= !pipe
;
13772 intel_crtc
->cursor_base
= ~0;
13773 intel_crtc
->cursor_cntl
= ~0;
13774 intel_crtc
->cursor_size
= ~0;
13776 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13777 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13778 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13779 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13781 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
13783 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13785 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13790 drm_plane_cleanup(primary
);
13792 drm_plane_cleanup(cursor
);
13797 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13799 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13800 struct drm_device
*dev
= connector
->base
.dev
;
13802 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13804 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13805 return INVALID_PIPE
;
13807 return to_intel_crtc(encoder
->crtc
)->pipe
;
13810 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13811 struct drm_file
*file
)
13813 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13814 struct drm_crtc
*drmmode_crtc
;
13815 struct intel_crtc
*crtc
;
13817 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13819 if (!drmmode_crtc
) {
13820 DRM_ERROR("no such CRTC id\n");
13824 crtc
= to_intel_crtc(drmmode_crtc
);
13825 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13830 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13832 struct drm_device
*dev
= encoder
->base
.dev
;
13833 struct intel_encoder
*source_encoder
;
13834 int index_mask
= 0;
13837 for_each_intel_encoder(dev
, source_encoder
) {
13838 if (encoders_cloneable(encoder
, source_encoder
))
13839 index_mask
|= (1 << entry
);
13847 static bool has_edp_a(struct drm_device
*dev
)
13849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13851 if (!IS_MOBILE(dev
))
13854 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13857 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13863 static bool intel_crt_present(struct drm_device
*dev
)
13865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13867 if (INTEL_INFO(dev
)->gen
>= 9)
13870 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13873 if (IS_CHERRYVIEW(dev
))
13876 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13882 static void intel_setup_outputs(struct drm_device
*dev
)
13884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13885 struct intel_encoder
*encoder
;
13886 bool dpd_is_edp
= false;
13888 intel_lvds_init(dev
);
13890 if (intel_crt_present(dev
))
13891 intel_crt_init(dev
);
13893 if (IS_BROXTON(dev
)) {
13895 * FIXME: Broxton doesn't support port detection via the
13896 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13897 * detect the ports.
13899 intel_ddi_init(dev
, PORT_A
);
13900 intel_ddi_init(dev
, PORT_B
);
13901 intel_ddi_init(dev
, PORT_C
);
13902 } else if (HAS_DDI(dev
)) {
13906 * Haswell uses DDI functions to detect digital outputs.
13907 * On SKL pre-D0 the strap isn't connected, so we assume
13910 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13911 /* WaIgnoreDDIAStrap: skl */
13913 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
13914 intel_ddi_init(dev
, PORT_A
);
13916 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13918 found
= I915_READ(SFUSE_STRAP
);
13920 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13921 intel_ddi_init(dev
, PORT_B
);
13922 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13923 intel_ddi_init(dev
, PORT_C
);
13924 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13925 intel_ddi_init(dev
, PORT_D
);
13926 } else if (HAS_PCH_SPLIT(dev
)) {
13928 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
13930 if (has_edp_a(dev
))
13931 intel_dp_init(dev
, DP_A
, PORT_A
);
13933 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13934 /* PCH SDVOB multiplex with HDMIB */
13935 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
13937 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
13938 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13939 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
13942 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13943 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
13945 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13946 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
13948 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13949 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
13951 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13952 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
13953 } else if (IS_VALLEYVIEW(dev
)) {
13955 * The DP_DETECTED bit is the latched state of the DDC
13956 * SDA pin at boot. However since eDP doesn't require DDC
13957 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13958 * eDP ports may have been muxed to an alternate function.
13959 * Thus we can't rely on the DP_DETECTED bit alone to detect
13960 * eDP ports. Consult the VBT as well as DP_DETECTED to
13961 * detect eDP ports.
13963 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
13964 !intel_dp_is_edp(dev
, PORT_B
))
13965 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
13967 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
13968 intel_dp_is_edp(dev
, PORT_B
))
13969 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
13971 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
13972 !intel_dp_is_edp(dev
, PORT_C
))
13973 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
13975 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
13976 intel_dp_is_edp(dev
, PORT_C
))
13977 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
13979 if (IS_CHERRYVIEW(dev
)) {
13980 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
13981 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
13983 /* eDP not supported on port D, so don't check VBT */
13984 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
13985 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
13988 intel_dsi_init(dev
);
13989 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
13990 bool found
= false;
13992 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13993 DRM_DEBUG_KMS("probing SDVOB\n");
13994 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
13995 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
13996 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13997 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14000 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
14001 intel_dp_init(dev
, DP_B
, PORT_B
);
14004 /* Before G4X SDVOC doesn't have its own detect register */
14006 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14007 DRM_DEBUG_KMS("probing SDVOC\n");
14008 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
14011 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14013 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
14014 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14015 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14017 if (SUPPORTS_INTEGRATED_DP(dev
))
14018 intel_dp_init(dev
, DP_C
, PORT_C
);
14021 if (SUPPORTS_INTEGRATED_DP(dev
) &&
14022 (I915_READ(DP_D
) & DP_DETECTED
))
14023 intel_dp_init(dev
, DP_D
, PORT_D
);
14024 } else if (IS_GEN2(dev
))
14025 intel_dvo_init(dev
);
14027 if (SUPPORTS_TV(dev
))
14028 intel_tv_init(dev
);
14030 intel_psr_init(dev
);
14032 for_each_intel_encoder(dev
, encoder
) {
14033 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14034 encoder
->base
.possible_clones
=
14035 intel_encoder_clones(encoder
);
14038 intel_init_pch_refclk(dev
);
14040 drm_helper_move_panel_connectors_to_head(dev
);
14043 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14045 struct drm_device
*dev
= fb
->dev
;
14046 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14048 drm_framebuffer_cleanup(fb
);
14049 mutex_lock(&dev
->struct_mutex
);
14050 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14051 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14052 mutex_unlock(&dev
->struct_mutex
);
14056 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14057 struct drm_file
*file
,
14058 unsigned int *handle
)
14060 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14061 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14063 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14066 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14067 .destroy
= intel_user_framebuffer_destroy
,
14068 .create_handle
= intel_user_framebuffer_create_handle
,
14072 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14073 uint32_t pixel_format
)
14075 u32 gen
= INTEL_INFO(dev
)->gen
;
14078 /* "The stride in bytes must not exceed the of the size of 8K
14079 * pixels and 32K bytes."
14081 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
14082 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
14084 } else if (gen
>= 4) {
14085 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14089 } else if (gen
>= 3) {
14090 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14095 /* XXX DSPC is limited to 4k tiled */
14100 static int intel_framebuffer_init(struct drm_device
*dev
,
14101 struct intel_framebuffer
*intel_fb
,
14102 struct drm_mode_fb_cmd2
*mode_cmd
,
14103 struct drm_i915_gem_object
*obj
)
14105 unsigned int aligned_height
;
14107 u32 pitch_limit
, stride_alignment
;
14109 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14111 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14112 /* Enforce that fb modifier and tiling mode match, but only for
14113 * X-tiled. This is needed for FBC. */
14114 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14115 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14116 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14120 if (obj
->tiling_mode
== I915_TILING_X
)
14121 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14122 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14123 DRM_DEBUG("No Y tiling for legacy addfb\n");
14128 /* Passed in modifier sanity checking. */
14129 switch (mode_cmd
->modifier
[0]) {
14130 case I915_FORMAT_MOD_Y_TILED
:
14131 case I915_FORMAT_MOD_Yf_TILED
:
14132 if (INTEL_INFO(dev
)->gen
< 9) {
14133 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14134 mode_cmd
->modifier
[0]);
14137 case DRM_FORMAT_MOD_NONE
:
14138 case I915_FORMAT_MOD_X_TILED
:
14141 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14142 mode_cmd
->modifier
[0]);
14146 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
14147 mode_cmd
->pixel_format
);
14148 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14149 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14150 mode_cmd
->pitches
[0], stride_alignment
);
14154 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14155 mode_cmd
->pixel_format
);
14156 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14157 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14158 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14159 "tiled" : "linear",
14160 mode_cmd
->pitches
[0], pitch_limit
);
14164 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14165 mode_cmd
->pitches
[0] != obj
->stride
) {
14166 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14167 mode_cmd
->pitches
[0], obj
->stride
);
14171 /* Reject formats not supported by any plane early. */
14172 switch (mode_cmd
->pixel_format
) {
14173 case DRM_FORMAT_C8
:
14174 case DRM_FORMAT_RGB565
:
14175 case DRM_FORMAT_XRGB8888
:
14176 case DRM_FORMAT_ARGB8888
:
14178 case DRM_FORMAT_XRGB1555
:
14179 case DRM_FORMAT_ARGB1555
:
14180 if (INTEL_INFO(dev
)->gen
> 3) {
14181 DRM_DEBUG("unsupported pixel format: %s\n",
14182 drm_get_format_name(mode_cmd
->pixel_format
));
14186 case DRM_FORMAT_XBGR8888
:
14187 case DRM_FORMAT_ABGR8888
:
14188 case DRM_FORMAT_XRGB2101010
:
14189 case DRM_FORMAT_ARGB2101010
:
14190 case DRM_FORMAT_XBGR2101010
:
14191 case DRM_FORMAT_ABGR2101010
:
14192 if (INTEL_INFO(dev
)->gen
< 4) {
14193 DRM_DEBUG("unsupported pixel format: %s\n",
14194 drm_get_format_name(mode_cmd
->pixel_format
));
14198 case DRM_FORMAT_YUYV
:
14199 case DRM_FORMAT_UYVY
:
14200 case DRM_FORMAT_YVYU
:
14201 case DRM_FORMAT_VYUY
:
14202 if (INTEL_INFO(dev
)->gen
< 5) {
14203 DRM_DEBUG("unsupported pixel format: %s\n",
14204 drm_get_format_name(mode_cmd
->pixel_format
));
14209 DRM_DEBUG("unsupported pixel format: %s\n",
14210 drm_get_format_name(mode_cmd
->pixel_format
));
14214 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14215 if (mode_cmd
->offsets
[0] != 0)
14218 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14219 mode_cmd
->pixel_format
,
14220 mode_cmd
->modifier
[0]);
14221 /* FIXME drm helper for size checks (especially planar formats)? */
14222 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14225 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14226 intel_fb
->obj
= obj
;
14227 intel_fb
->obj
->framebuffer_references
++;
14229 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14231 DRM_ERROR("framebuffer init failed %d\n", ret
);
14238 static struct drm_framebuffer
*
14239 intel_user_framebuffer_create(struct drm_device
*dev
,
14240 struct drm_file
*filp
,
14241 struct drm_mode_fb_cmd2
*mode_cmd
)
14243 struct drm_i915_gem_object
*obj
;
14245 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14246 mode_cmd
->handles
[0]));
14247 if (&obj
->base
== NULL
)
14248 return ERR_PTR(-ENOENT
);
14250 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
14253 #ifndef CONFIG_DRM_I915_FBDEV
14254 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14259 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14260 .fb_create
= intel_user_framebuffer_create
,
14261 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14262 .atomic_check
= intel_atomic_check
,
14263 .atomic_commit
= intel_atomic_commit
,
14266 /* Set up chip specific display functions */
14267 static void intel_init_display(struct drm_device
*dev
)
14269 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14271 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14272 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14273 else if (IS_CHERRYVIEW(dev
))
14274 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14275 else if (IS_VALLEYVIEW(dev
))
14276 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14277 else if (IS_PINEVIEW(dev
))
14278 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14280 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14282 if (INTEL_INFO(dev
)->gen
>= 9) {
14283 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14284 dev_priv
->display
.get_initial_plane_config
=
14285 skylake_get_initial_plane_config
;
14286 dev_priv
->display
.crtc_compute_clock
=
14287 haswell_crtc_compute_clock
;
14288 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14289 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14290 dev_priv
->display
.off
= ironlake_crtc_off
;
14291 dev_priv
->display
.update_primary_plane
=
14292 skylake_update_primary_plane
;
14293 } else if (HAS_DDI(dev
)) {
14294 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14295 dev_priv
->display
.get_initial_plane_config
=
14296 ironlake_get_initial_plane_config
;
14297 dev_priv
->display
.crtc_compute_clock
=
14298 haswell_crtc_compute_clock
;
14299 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14300 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14301 dev_priv
->display
.off
= ironlake_crtc_off
;
14302 dev_priv
->display
.update_primary_plane
=
14303 ironlake_update_primary_plane
;
14304 } else if (HAS_PCH_SPLIT(dev
)) {
14305 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14306 dev_priv
->display
.get_initial_plane_config
=
14307 ironlake_get_initial_plane_config
;
14308 dev_priv
->display
.crtc_compute_clock
=
14309 ironlake_crtc_compute_clock
;
14310 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14311 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14312 dev_priv
->display
.off
= ironlake_crtc_off
;
14313 dev_priv
->display
.update_primary_plane
=
14314 ironlake_update_primary_plane
;
14315 } else if (IS_VALLEYVIEW(dev
)) {
14316 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14317 dev_priv
->display
.get_initial_plane_config
=
14318 i9xx_get_initial_plane_config
;
14319 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14320 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14321 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14322 dev_priv
->display
.off
= i9xx_crtc_off
;
14323 dev_priv
->display
.update_primary_plane
=
14324 i9xx_update_primary_plane
;
14326 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14327 dev_priv
->display
.get_initial_plane_config
=
14328 i9xx_get_initial_plane_config
;
14329 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14330 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14331 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14332 dev_priv
->display
.off
= i9xx_crtc_off
;
14333 dev_priv
->display
.update_primary_plane
=
14334 i9xx_update_primary_plane
;
14337 /* Returns the core display clock speed */
14338 if (IS_SKYLAKE(dev
))
14339 dev_priv
->display
.get_display_clock_speed
=
14340 skylake_get_display_clock_speed
;
14341 else if (IS_BROADWELL(dev
))
14342 dev_priv
->display
.get_display_clock_speed
=
14343 broadwell_get_display_clock_speed
;
14344 else if (IS_HASWELL(dev
))
14345 dev_priv
->display
.get_display_clock_speed
=
14346 haswell_get_display_clock_speed
;
14347 else if (IS_VALLEYVIEW(dev
))
14348 dev_priv
->display
.get_display_clock_speed
=
14349 valleyview_get_display_clock_speed
;
14350 else if (IS_GEN5(dev
))
14351 dev_priv
->display
.get_display_clock_speed
=
14352 ilk_get_display_clock_speed
;
14353 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14354 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
14355 dev_priv
->display
.get_display_clock_speed
=
14356 i945_get_display_clock_speed
;
14357 else if (IS_I915G(dev
))
14358 dev_priv
->display
.get_display_clock_speed
=
14359 i915_get_display_clock_speed
;
14360 else if (IS_I945GM(dev
) || IS_845G(dev
))
14361 dev_priv
->display
.get_display_clock_speed
=
14362 i9xx_misc_get_display_clock_speed
;
14363 else if (IS_PINEVIEW(dev
))
14364 dev_priv
->display
.get_display_clock_speed
=
14365 pnv_get_display_clock_speed
;
14366 else if (IS_I915GM(dev
))
14367 dev_priv
->display
.get_display_clock_speed
=
14368 i915gm_get_display_clock_speed
;
14369 else if (IS_I865G(dev
))
14370 dev_priv
->display
.get_display_clock_speed
=
14371 i865_get_display_clock_speed
;
14372 else if (IS_I85X(dev
))
14373 dev_priv
->display
.get_display_clock_speed
=
14374 i855_get_display_clock_speed
;
14375 else /* 852, 830 */
14376 dev_priv
->display
.get_display_clock_speed
=
14377 i830_get_display_clock_speed
;
14379 if (IS_GEN5(dev
)) {
14380 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14381 } else if (IS_GEN6(dev
)) {
14382 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14383 } else if (IS_IVYBRIDGE(dev
)) {
14384 /* FIXME: detect B0+ stepping and use auto training */
14385 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14386 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14387 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14388 } else if (IS_VALLEYVIEW(dev
)) {
14389 dev_priv
->display
.modeset_global_resources
=
14390 valleyview_modeset_global_resources
;
14391 } else if (IS_BROXTON(dev
)) {
14392 dev_priv
->display
.modeset_global_resources
=
14393 broxton_modeset_global_resources
;
14396 switch (INTEL_INFO(dev
)->gen
) {
14398 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14402 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14407 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14411 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14414 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14415 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14418 /* Drop through - unsupported since execlist only. */
14420 /* Default just returns -ENODEV to indicate unsupported */
14421 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14424 intel_panel_init_backlight_funcs(dev
);
14426 mutex_init(&dev_priv
->pps_mutex
);
14430 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14431 * resume, or other times. This quirk makes sure that's the case for
14432 * affected systems.
14434 static void quirk_pipea_force(struct drm_device
*dev
)
14436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14438 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14439 DRM_INFO("applying pipe a force quirk\n");
14442 static void quirk_pipeb_force(struct drm_device
*dev
)
14444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14446 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14447 DRM_INFO("applying pipe b force quirk\n");
14451 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14453 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14456 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14457 DRM_INFO("applying lvds SSC disable quirk\n");
14461 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14464 static void quirk_invert_brightness(struct drm_device
*dev
)
14466 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14467 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14468 DRM_INFO("applying inverted panel brightness quirk\n");
14471 /* Some VBT's incorrectly indicate no backlight is present */
14472 static void quirk_backlight_present(struct drm_device
*dev
)
14474 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14475 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14476 DRM_INFO("applying backlight present quirk\n");
14479 struct intel_quirk
{
14481 int subsystem_vendor
;
14482 int subsystem_device
;
14483 void (*hook
)(struct drm_device
*dev
);
14486 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14487 struct intel_dmi_quirk
{
14488 void (*hook
)(struct drm_device
*dev
);
14489 const struct dmi_system_id (*dmi_id_list
)[];
14492 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14494 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14498 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14500 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14502 .callback
= intel_dmi_reverse_brightness
,
14503 .ident
= "NCR Corporation",
14504 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14505 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14508 { } /* terminating entry */
14510 .hook
= quirk_invert_brightness
,
14514 static struct intel_quirk intel_quirks
[] = {
14515 /* HP Mini needs pipe A force quirk (LP: #322104) */
14516 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
14518 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14519 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14521 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14522 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14524 /* 830 needs to leave pipe A & dpll A up */
14525 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14527 /* 830 needs to leave pipe B & dpll B up */
14528 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14530 /* Lenovo U160 cannot use SSC on LVDS */
14531 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14533 /* Sony Vaio Y cannot use SSC on LVDS */
14534 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14536 /* Acer Aspire 5734Z must invert backlight brightness */
14537 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14539 /* Acer/eMachines G725 */
14540 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14542 /* Acer/eMachines e725 */
14543 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14545 /* Acer/Packard Bell NCL20 */
14546 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14548 /* Acer Aspire 4736Z */
14549 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14551 /* Acer Aspire 5336 */
14552 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14554 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14555 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14557 /* Acer C720 Chromebook (Core i3 4005U) */
14558 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14560 /* Apple Macbook 2,1 (Core 2 T7400) */
14561 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14563 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14564 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14566 /* HP Chromebook 14 (Celeron 2955U) */
14567 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14569 /* Dell Chromebook 11 */
14570 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14573 static void intel_init_quirks(struct drm_device
*dev
)
14575 struct pci_dev
*d
= dev
->pdev
;
14578 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14579 struct intel_quirk
*q
= &intel_quirks
[i
];
14581 if (d
->device
== q
->device
&&
14582 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14583 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14584 (d
->subsystem_device
== q
->subsystem_device
||
14585 q
->subsystem_device
== PCI_ANY_ID
))
14588 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14589 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14590 intel_dmi_quirks
[i
].hook(dev
);
14594 /* Disable the VGA plane that we never use */
14595 static void i915_disable_vga(struct drm_device
*dev
)
14597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14599 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14601 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14602 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14603 outb(SR01
, VGA_SR_INDEX
);
14604 sr1
= inb(VGA_SR_DATA
);
14605 outb(sr1
| 1<<5, VGA_SR_DATA
);
14606 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14609 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14610 POSTING_READ(vga_reg
);
14613 void intel_modeset_init_hw(struct drm_device
*dev
)
14615 intel_prepare_ddi(dev
);
14617 if (IS_VALLEYVIEW(dev
))
14618 vlv_update_cdclk(dev
);
14620 intel_init_clock_gating(dev
);
14622 intel_enable_gt_powersave(dev
);
14625 void intel_modeset_init(struct drm_device
*dev
)
14627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14630 struct intel_crtc
*crtc
;
14632 drm_mode_config_init(dev
);
14634 dev
->mode_config
.min_width
= 0;
14635 dev
->mode_config
.min_height
= 0;
14637 dev
->mode_config
.preferred_depth
= 24;
14638 dev
->mode_config
.prefer_shadow
= 1;
14640 dev
->mode_config
.allow_fb_modifiers
= true;
14642 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14644 intel_init_quirks(dev
);
14646 intel_init_pm(dev
);
14648 if (INTEL_INFO(dev
)->num_pipes
== 0)
14651 intel_init_display(dev
);
14652 intel_init_audio(dev
);
14654 if (IS_GEN2(dev
)) {
14655 dev
->mode_config
.max_width
= 2048;
14656 dev
->mode_config
.max_height
= 2048;
14657 } else if (IS_GEN3(dev
)) {
14658 dev
->mode_config
.max_width
= 4096;
14659 dev
->mode_config
.max_height
= 4096;
14661 dev
->mode_config
.max_width
= 8192;
14662 dev
->mode_config
.max_height
= 8192;
14665 if (IS_845G(dev
) || IS_I865G(dev
)) {
14666 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
14667 dev
->mode_config
.cursor_height
= 1023;
14668 } else if (IS_GEN2(dev
)) {
14669 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14670 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14672 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14673 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14676 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
14678 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14679 INTEL_INFO(dev
)->num_pipes
,
14680 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14682 for_each_pipe(dev_priv
, pipe
) {
14683 intel_crtc_init(dev
, pipe
);
14684 for_each_sprite(dev_priv
, pipe
, sprite
) {
14685 ret
= intel_plane_init(dev
, pipe
, sprite
);
14687 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14688 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14692 intel_init_dpio(dev
);
14694 intel_shared_dpll_init(dev
);
14696 /* Just disable it once at startup */
14697 i915_disable_vga(dev
);
14698 intel_setup_outputs(dev
);
14700 /* Just in case the BIOS is doing something questionable. */
14701 intel_fbc_disable(dev
);
14703 drm_modeset_lock_all(dev
);
14704 intel_modeset_setup_hw_state(dev
, false);
14705 drm_modeset_unlock_all(dev
);
14707 for_each_intel_crtc(dev
, crtc
) {
14712 * Note that reserving the BIOS fb up front prevents us
14713 * from stuffing other stolen allocations like the ring
14714 * on top. This prevents some ugliness at boot time, and
14715 * can even allow for smooth boot transitions if the BIOS
14716 * fb is large enough for the active pipe configuration.
14718 if (dev_priv
->display
.get_initial_plane_config
) {
14719 dev_priv
->display
.get_initial_plane_config(crtc
,
14720 &crtc
->plane_config
);
14722 * If the fb is shared between multiple heads, we'll
14723 * just get the first one.
14725 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
14730 static void intel_enable_pipe_a(struct drm_device
*dev
)
14732 struct intel_connector
*connector
;
14733 struct drm_connector
*crt
= NULL
;
14734 struct intel_load_detect_pipe load_detect_temp
;
14735 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14737 /* We can't just switch on the pipe A, we need to set things up with a
14738 * proper mode and output configuration. As a gross hack, enable pipe A
14739 * by enabling the load detect pipe once. */
14740 for_each_intel_connector(dev
, connector
) {
14741 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14742 crt
= &connector
->base
;
14750 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14751 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14755 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14757 struct drm_device
*dev
= crtc
->base
.dev
;
14758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14761 if (INTEL_INFO(dev
)->num_pipes
== 1)
14764 reg
= DSPCNTR(!crtc
->plane
);
14765 val
= I915_READ(reg
);
14767 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14768 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14774 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14776 struct drm_device
*dev
= crtc
->base
.dev
;
14777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14780 /* Clear any frame start delays used for debugging left by the BIOS */
14781 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14782 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14784 /* restore vblank interrupts to correct state */
14785 drm_crtc_vblank_reset(&crtc
->base
);
14786 if (crtc
->active
) {
14787 update_scanline_offset(crtc
);
14788 drm_crtc_vblank_on(&crtc
->base
);
14791 /* We need to sanitize the plane -> pipe mapping first because this will
14792 * disable the crtc (and hence change the state) if it is wrong. Note
14793 * that gen4+ has a fixed plane -> pipe mapping. */
14794 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14795 struct intel_connector
*connector
;
14798 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14799 crtc
->base
.base
.id
);
14801 /* Pipe has the wrong plane attached and the plane is active.
14802 * Temporarily change the plane mapping and disable everything
14804 plane
= crtc
->plane
;
14805 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
14806 crtc
->plane
= !plane
;
14807 intel_crtc_disable_planes(&crtc
->base
);
14808 dev_priv
->display
.crtc_disable(&crtc
->base
);
14809 crtc
->plane
= plane
;
14811 /* ... and break all links. */
14812 for_each_intel_connector(dev
, connector
) {
14813 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
14816 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14817 connector
->base
.encoder
= NULL
;
14819 /* multiple connectors may have the same encoder:
14820 * handle them and break crtc link separately */
14821 for_each_intel_connector(dev
, connector
)
14822 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
14823 connector
->encoder
->base
.crtc
= NULL
;
14824 connector
->encoder
->connectors_active
= false;
14827 WARN_ON(crtc
->active
);
14828 crtc
->base
.state
->enable
= false;
14829 crtc
->base
.enabled
= false;
14832 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14833 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14834 /* BIOS forgot to enable pipe A, this mostly happens after
14835 * resume. Force-enable the pipe to fix this, the update_dpms
14836 * call below we restore the pipe to the right state, but leave
14837 * the required bits on. */
14838 intel_enable_pipe_a(dev
);
14841 /* Adjust the state of the output pipe according to whether we
14842 * have active connectors/encoders. */
14843 intel_crtc_update_dpms(&crtc
->base
);
14845 if (crtc
->active
!= crtc
->base
.state
->enable
) {
14846 struct intel_encoder
*encoder
;
14848 /* This can happen either due to bugs in the get_hw_state
14849 * functions or because the pipe is force-enabled due to the
14851 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14852 crtc
->base
.base
.id
,
14853 crtc
->base
.state
->enable
? "enabled" : "disabled",
14854 crtc
->active
? "enabled" : "disabled");
14856 crtc
->base
.state
->enable
= crtc
->active
;
14857 crtc
->base
.enabled
= crtc
->active
;
14859 /* Because we only establish the connector -> encoder ->
14860 * crtc links if something is active, this means the
14861 * crtc is now deactivated. Break the links. connector
14862 * -> encoder links are only establish when things are
14863 * actually up, hence no need to break them. */
14864 WARN_ON(crtc
->active
);
14866 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
14867 WARN_ON(encoder
->connectors_active
);
14868 encoder
->base
.crtc
= NULL
;
14872 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
14874 * We start out with underrun reporting disabled to avoid races.
14875 * For correct bookkeeping mark this on active crtcs.
14877 * Also on gmch platforms we dont have any hardware bits to
14878 * disable the underrun reporting. Which means we need to start
14879 * out with underrun reporting disabled also on inactive pipes,
14880 * since otherwise we'll complain about the garbage we read when
14881 * e.g. coming up after runtime pm.
14883 * No protection against concurrent access is required - at
14884 * worst a fifo underrun happens which also sets this to false.
14886 crtc
->cpu_fifo_underrun_disabled
= true;
14887 crtc
->pch_fifo_underrun_disabled
= true;
14891 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14893 struct intel_connector
*connector
;
14894 struct drm_device
*dev
= encoder
->base
.dev
;
14896 /* We need to check both for a crtc link (meaning that the
14897 * encoder is active and trying to read from a pipe) and the
14898 * pipe itself being active. */
14899 bool has_active_crtc
= encoder
->base
.crtc
&&
14900 to_intel_crtc(encoder
->base
.crtc
)->active
;
14902 if (encoder
->connectors_active
&& !has_active_crtc
) {
14903 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14904 encoder
->base
.base
.id
,
14905 encoder
->base
.name
);
14907 /* Connector is active, but has no active pipe. This is
14908 * fallout from our resume register restoring. Disable
14909 * the encoder manually again. */
14910 if (encoder
->base
.crtc
) {
14911 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14912 encoder
->base
.base
.id
,
14913 encoder
->base
.name
);
14914 encoder
->disable(encoder
);
14915 if (encoder
->post_disable
)
14916 encoder
->post_disable(encoder
);
14918 encoder
->base
.crtc
= NULL
;
14919 encoder
->connectors_active
= false;
14921 /* Inconsistent output/port/pipe state happens presumably due to
14922 * a bug in one of the get_hw_state functions. Or someplace else
14923 * in our code, like the register restore mess on resume. Clamp
14924 * things to off as a safer default. */
14925 for_each_intel_connector(dev
, connector
) {
14926 if (connector
->encoder
!= encoder
)
14928 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14929 connector
->base
.encoder
= NULL
;
14932 /* Enabled encoders without active connectors will be fixed in
14933 * the crtc fixup. */
14936 void i915_redisable_vga_power_on(struct drm_device
*dev
)
14938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14939 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14941 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14942 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14943 i915_disable_vga(dev
);
14947 void i915_redisable_vga(struct drm_device
*dev
)
14949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14951 /* This function can be called both from intel_modeset_setup_hw_state or
14952 * at a very early point in our resume sequence, where the power well
14953 * structures are not yet restored. Since this function is at a very
14954 * paranoid "someone might have enabled VGA while we were not looking"
14955 * level, just check if the power well is enabled instead of trying to
14956 * follow the "don't touch the power well if we don't need it" policy
14957 * the rest of the driver uses. */
14958 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14961 i915_redisable_vga_power_on(dev
);
14964 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
14966 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
14971 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
14974 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
14976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14978 struct intel_crtc
*crtc
;
14979 struct intel_encoder
*encoder
;
14980 struct intel_connector
*connector
;
14983 for_each_intel_crtc(dev
, crtc
) {
14984 struct drm_plane
*primary
= crtc
->base
.primary
;
14985 struct intel_plane_state
*plane_state
;
14987 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
14989 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
14991 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
14994 crtc
->base
.state
->enable
= crtc
->active
;
14995 crtc
->base
.enabled
= crtc
->active
;
14997 plane_state
= to_intel_plane_state(primary
->state
);
14998 plane_state
->visible
= primary_get_hw_state(crtc
);
15000 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15001 crtc
->base
.base
.id
,
15002 crtc
->active
? "enabled" : "disabled");
15005 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15006 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15008 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
15009 &pll
->config
.hw_state
);
15011 pll
->config
.crtc_mask
= 0;
15012 for_each_intel_crtc(dev
, crtc
) {
15013 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
15015 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15019 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15020 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15022 if (pll
->config
.crtc_mask
)
15023 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
15026 for_each_intel_encoder(dev
, encoder
) {
15029 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15030 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15031 encoder
->base
.crtc
= &crtc
->base
;
15032 encoder
->get_config(encoder
, crtc
->config
);
15034 encoder
->base
.crtc
= NULL
;
15037 encoder
->connectors_active
= false;
15038 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15039 encoder
->base
.base
.id
,
15040 encoder
->base
.name
,
15041 encoder
->base
.crtc
? "enabled" : "disabled",
15045 for_each_intel_connector(dev
, connector
) {
15046 if (connector
->get_hw_state(connector
)) {
15047 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15048 connector
->encoder
->connectors_active
= true;
15049 connector
->base
.encoder
= &connector
->encoder
->base
;
15051 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15052 connector
->base
.encoder
= NULL
;
15054 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15055 connector
->base
.base
.id
,
15056 connector
->base
.name
,
15057 connector
->base
.encoder
? "enabled" : "disabled");
15061 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15062 * and i915 state tracking structures. */
15063 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
15064 bool force_restore
)
15066 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15068 struct intel_crtc
*crtc
;
15069 struct intel_encoder
*encoder
;
15072 intel_modeset_readout_hw_state(dev
);
15075 * Now that we have the config, copy it to each CRTC struct
15076 * Note that this could go away if we move to using crtc_config
15077 * checking everywhere.
15079 for_each_intel_crtc(dev
, crtc
) {
15080 if (crtc
->active
&& i915
.fastboot
) {
15081 intel_mode_from_pipe_config(&crtc
->base
.mode
,
15083 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15084 crtc
->base
.base
.id
);
15085 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
15089 /* HW state is read out, now we need to sanitize this mess. */
15090 for_each_intel_encoder(dev
, encoder
) {
15091 intel_sanitize_encoder(encoder
);
15094 for_each_pipe(dev_priv
, pipe
) {
15095 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15096 intel_sanitize_crtc(crtc
);
15097 intel_dump_pipe_config(crtc
, crtc
->config
,
15098 "[setup_hw_state]");
15101 intel_modeset_update_connector_atomic_state(dev
);
15103 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15104 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15106 if (!pll
->on
|| pll
->active
)
15109 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15111 pll
->disable(dev_priv
, pll
);
15116 skl_wm_get_hw_state(dev
);
15117 else if (HAS_PCH_SPLIT(dev
))
15118 ilk_wm_get_hw_state(dev
);
15120 if (force_restore
) {
15121 i915_redisable_vga(dev
);
15124 * We need to use raw interfaces for restoring state to avoid
15125 * checking (bogus) intermediate states.
15127 for_each_pipe(dev_priv
, pipe
) {
15128 struct drm_crtc
*crtc
=
15129 dev_priv
->pipe_to_crtc_mapping
[pipe
];
15131 intel_crtc_restore_mode(crtc
);
15134 intel_modeset_update_staged_output_state(dev
);
15137 intel_modeset_check_state(dev
);
15140 void intel_modeset_gem_init(struct drm_device
*dev
)
15142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15143 struct drm_crtc
*c
;
15144 struct drm_i915_gem_object
*obj
;
15147 mutex_lock(&dev
->struct_mutex
);
15148 intel_init_gt_powersave(dev
);
15149 mutex_unlock(&dev
->struct_mutex
);
15152 * There may be no VBT; and if the BIOS enabled SSC we can
15153 * just keep using it to avoid unnecessary flicker. Whereas if the
15154 * BIOS isn't using it, don't assume it will work even if the VBT
15155 * indicates as much.
15157 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
15158 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
15161 intel_modeset_init_hw(dev
);
15163 intel_setup_overlay(dev
);
15166 * Make sure any fbs we allocated at startup are properly
15167 * pinned & fenced. When we do the allocation it's too early
15170 for_each_crtc(dev
, c
) {
15171 obj
= intel_fb_obj(c
->primary
->fb
);
15175 mutex_lock(&dev
->struct_mutex
);
15176 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
15180 mutex_unlock(&dev
->struct_mutex
);
15182 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15183 to_intel_crtc(c
)->pipe
);
15184 drm_framebuffer_unreference(c
->primary
->fb
);
15185 c
->primary
->fb
= NULL
;
15186 update_state_fb(c
->primary
);
15190 intel_backlight_register(dev
);
15193 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15195 struct drm_connector
*connector
= &intel_connector
->base
;
15197 intel_panel_destroy_backlight(connector
);
15198 drm_connector_unregister(connector
);
15201 void intel_modeset_cleanup(struct drm_device
*dev
)
15203 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15204 struct drm_connector
*connector
;
15206 intel_disable_gt_powersave(dev
);
15208 intel_backlight_unregister(dev
);
15211 * Interrupts and polling as the first thing to avoid creating havoc.
15212 * Too much stuff here (turning of connectors, ...) would
15213 * experience fancy races otherwise.
15215 intel_irq_uninstall(dev_priv
);
15218 * Due to the hpd irq storm handling the hotplug work can re-arm the
15219 * poll handlers. Hence disable polling after hpd handling is shut down.
15221 drm_kms_helper_poll_fini(dev
);
15223 mutex_lock(&dev
->struct_mutex
);
15225 intel_unregister_dsm_handler();
15227 intel_fbc_disable(dev
);
15229 mutex_unlock(&dev
->struct_mutex
);
15231 /* flush any delayed tasks or pending work */
15232 flush_scheduled_work();
15234 /* destroy the backlight and sysfs files before encoders/connectors */
15235 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15236 struct intel_connector
*intel_connector
;
15238 intel_connector
= to_intel_connector(connector
);
15239 intel_connector
->unregister(intel_connector
);
15242 drm_mode_config_cleanup(dev
);
15244 intel_cleanup_overlay(dev
);
15246 mutex_lock(&dev
->struct_mutex
);
15247 intel_cleanup_gt_powersave(dev
);
15248 mutex_unlock(&dev
->struct_mutex
);
15252 * Return which encoder is currently attached for connector.
15254 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15256 return &intel_attached_encoder(connector
)->base
;
15259 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15260 struct intel_encoder
*encoder
)
15262 connector
->encoder
= encoder
;
15263 drm_mode_connector_attach_encoder(&connector
->base
,
15268 * set vga decode state - true == enable VGA decode
15270 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15273 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15276 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15277 DRM_ERROR("failed to read control word\n");
15281 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15285 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15287 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15289 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15290 DRM_ERROR("failed to write control word\n");
15297 struct intel_display_error_state
{
15299 u32 power_well_driver
;
15301 int num_transcoders
;
15303 struct intel_cursor_error_state
{
15308 } cursor
[I915_MAX_PIPES
];
15310 struct intel_pipe_error_state
{
15311 bool power_domain_on
;
15314 } pipe
[I915_MAX_PIPES
];
15316 struct intel_plane_error_state
{
15324 } plane
[I915_MAX_PIPES
];
15326 struct intel_transcoder_error_state
{
15327 bool power_domain_on
;
15328 enum transcoder cpu_transcoder
;
15341 struct intel_display_error_state
*
15342 intel_display_capture_error_state(struct drm_device
*dev
)
15344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15345 struct intel_display_error_state
*error
;
15346 int transcoders
[] = {
15354 if (INTEL_INFO(dev
)->num_pipes
== 0)
15357 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15361 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15362 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15364 for_each_pipe(dev_priv
, i
) {
15365 error
->pipe
[i
].power_domain_on
=
15366 __intel_display_power_is_enabled(dev_priv
,
15367 POWER_DOMAIN_PIPE(i
));
15368 if (!error
->pipe
[i
].power_domain_on
)
15371 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15372 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15373 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15375 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15376 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15377 if (INTEL_INFO(dev
)->gen
<= 3) {
15378 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15379 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15381 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15382 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15383 if (INTEL_INFO(dev
)->gen
>= 4) {
15384 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15385 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15388 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15390 if (HAS_GMCH_DISPLAY(dev
))
15391 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15394 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15395 if (HAS_DDI(dev_priv
->dev
))
15396 error
->num_transcoders
++; /* Account for eDP. */
15398 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15399 enum transcoder cpu_transcoder
= transcoders
[i
];
15401 error
->transcoder
[i
].power_domain_on
=
15402 __intel_display_power_is_enabled(dev_priv
,
15403 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15404 if (!error
->transcoder
[i
].power_domain_on
)
15407 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15409 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15410 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15411 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15412 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15413 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15414 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15415 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15421 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15424 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15425 struct drm_device
*dev
,
15426 struct intel_display_error_state
*error
)
15428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15434 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15435 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15436 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15437 error
->power_well_driver
);
15438 for_each_pipe(dev_priv
, i
) {
15439 err_printf(m
, "Pipe [%d]:\n", i
);
15440 err_printf(m
, " Power: %s\n",
15441 error
->pipe
[i
].power_domain_on
? "on" : "off");
15442 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15443 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15445 err_printf(m
, "Plane [%d]:\n", i
);
15446 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15447 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15448 if (INTEL_INFO(dev
)->gen
<= 3) {
15449 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15450 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15452 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15453 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15454 if (INTEL_INFO(dev
)->gen
>= 4) {
15455 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15456 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15459 err_printf(m
, "Cursor [%d]:\n", i
);
15460 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15461 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15462 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15465 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15466 err_printf(m
, "CPU transcoder: %c\n",
15467 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15468 err_printf(m
, " Power: %s\n",
15469 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15470 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15471 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15472 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15473 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15474 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15475 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15476 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15480 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15482 struct intel_crtc
*crtc
;
15484 for_each_intel_crtc(dev
, crtc
) {
15485 struct intel_unpin_work
*work
;
15487 spin_lock_irq(&dev
->event_lock
);
15489 work
= crtc
->unpin_work
;
15491 if (work
&& work
->event
&&
15492 work
->event
->base
.file_priv
== file
) {
15493 kfree(work
->event
);
15494 work
->event
= NULL
;
15497 spin_unlock_irq(&dev
->event_lock
);