2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t
;
74 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
76 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
77 int, int, intel_clock_t
*, intel_clock_t
*);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_pch_rawclk(struct drm_device
*dev
)
86 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
88 WARN_ON(!HAS_PCH_SPLIT(dev
));
90 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
94 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
95 int target
, int refclk
, intel_clock_t
*match_clock
,
96 intel_clock_t
*best_clock
);
98 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
99 int target
, int refclk
, intel_clock_t
*match_clock
,
100 intel_clock_t
*best_clock
);
103 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
104 int target
, int refclk
, intel_clock_t
*match_clock
,
105 intel_clock_t
*best_clock
);
107 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
108 int target
, int refclk
, intel_clock_t
*match_clock
,
109 intel_clock_t
*best_clock
);
112 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
113 int target
, int refclk
, intel_clock_t
*match_clock
,
114 intel_clock_t
*best_clock
);
116 static inline u32
/* units of 100MHz */
117 intel_fdi_link_freq(struct drm_device
*dev
)
120 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
121 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
126 static const intel_limit_t intel_limits_i8xx_dvo
= {
127 .dot
= { .min
= 25000, .max
= 350000 },
128 .vco
= { .min
= 930000, .max
= 1400000 },
129 .n
= { .min
= 3, .max
= 16 },
130 .m
= { .min
= 96, .max
= 140 },
131 .m1
= { .min
= 18, .max
= 26 },
132 .m2
= { .min
= 6, .max
= 16 },
133 .p
= { .min
= 4, .max
= 128 },
134 .p1
= { .min
= 2, .max
= 33 },
135 .p2
= { .dot_limit
= 165000,
136 .p2_slow
= 4, .p2_fast
= 2 },
137 .find_pll
= intel_find_best_PLL
,
140 static const intel_limit_t intel_limits_i8xx_lvds
= {
141 .dot
= { .min
= 25000, .max
= 350000 },
142 .vco
= { .min
= 930000, .max
= 1400000 },
143 .n
= { .min
= 3, .max
= 16 },
144 .m
= { .min
= 96, .max
= 140 },
145 .m1
= { .min
= 18, .max
= 26 },
146 .m2
= { .min
= 6, .max
= 16 },
147 .p
= { .min
= 4, .max
= 128 },
148 .p1
= { .min
= 1, .max
= 6 },
149 .p2
= { .dot_limit
= 165000,
150 .p2_slow
= 14, .p2_fast
= 7 },
151 .find_pll
= intel_find_best_PLL
,
154 static const intel_limit_t intel_limits_i9xx_sdvo
= {
155 .dot
= { .min
= 20000, .max
= 400000 },
156 .vco
= { .min
= 1400000, .max
= 2800000 },
157 .n
= { .min
= 1, .max
= 6 },
158 .m
= { .min
= 70, .max
= 120 },
159 .m1
= { .min
= 10, .max
= 22 },
160 .m2
= { .min
= 5, .max
= 9 },
161 .p
= { .min
= 5, .max
= 80 },
162 .p1
= { .min
= 1, .max
= 8 },
163 .p2
= { .dot_limit
= 200000,
164 .p2_slow
= 10, .p2_fast
= 5 },
165 .find_pll
= intel_find_best_PLL
,
168 static const intel_limit_t intel_limits_i9xx_lvds
= {
169 .dot
= { .min
= 20000, .max
= 400000 },
170 .vco
= { .min
= 1400000, .max
= 2800000 },
171 .n
= { .min
= 1, .max
= 6 },
172 .m
= { .min
= 70, .max
= 120 },
173 .m1
= { .min
= 10, .max
= 22 },
174 .m2
= { .min
= 5, .max
= 9 },
175 .p
= { .min
= 7, .max
= 98 },
176 .p1
= { .min
= 1, .max
= 8 },
177 .p2
= { .dot_limit
= 112000,
178 .p2_slow
= 14, .p2_fast
= 7 },
179 .find_pll
= intel_find_best_PLL
,
183 static const intel_limit_t intel_limits_g4x_sdvo
= {
184 .dot
= { .min
= 25000, .max
= 270000 },
185 .vco
= { .min
= 1750000, .max
= 3500000},
186 .n
= { .min
= 1, .max
= 4 },
187 .m
= { .min
= 104, .max
= 138 },
188 .m1
= { .min
= 17, .max
= 23 },
189 .m2
= { .min
= 5, .max
= 11 },
190 .p
= { .min
= 10, .max
= 30 },
191 .p1
= { .min
= 1, .max
= 3},
192 .p2
= { .dot_limit
= 270000,
196 .find_pll
= intel_g4x_find_best_PLL
,
199 static const intel_limit_t intel_limits_g4x_hdmi
= {
200 .dot
= { .min
= 22000, .max
= 400000 },
201 .vco
= { .min
= 1750000, .max
= 3500000},
202 .n
= { .min
= 1, .max
= 4 },
203 .m
= { .min
= 104, .max
= 138 },
204 .m1
= { .min
= 16, .max
= 23 },
205 .m2
= { .min
= 5, .max
= 11 },
206 .p
= { .min
= 5, .max
= 80 },
207 .p1
= { .min
= 1, .max
= 8},
208 .p2
= { .dot_limit
= 165000,
209 .p2_slow
= 10, .p2_fast
= 5 },
210 .find_pll
= intel_g4x_find_best_PLL
,
213 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
214 .dot
= { .min
= 20000, .max
= 115000 },
215 .vco
= { .min
= 1750000, .max
= 3500000 },
216 .n
= { .min
= 1, .max
= 3 },
217 .m
= { .min
= 104, .max
= 138 },
218 .m1
= { .min
= 17, .max
= 23 },
219 .m2
= { .min
= 5, .max
= 11 },
220 .p
= { .min
= 28, .max
= 112 },
221 .p1
= { .min
= 2, .max
= 8 },
222 .p2
= { .dot_limit
= 0,
223 .p2_slow
= 14, .p2_fast
= 14
225 .find_pll
= intel_g4x_find_best_PLL
,
228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
229 .dot
= { .min
= 80000, .max
= 224000 },
230 .vco
= { .min
= 1750000, .max
= 3500000 },
231 .n
= { .min
= 1, .max
= 3 },
232 .m
= { .min
= 104, .max
= 138 },
233 .m1
= { .min
= 17, .max
= 23 },
234 .m2
= { .min
= 5, .max
= 11 },
235 .p
= { .min
= 14, .max
= 42 },
236 .p1
= { .min
= 2, .max
= 6 },
237 .p2
= { .dot_limit
= 0,
238 .p2_slow
= 7, .p2_fast
= 7
240 .find_pll
= intel_g4x_find_best_PLL
,
243 static const intel_limit_t intel_limits_g4x_display_port
= {
244 .dot
= { .min
= 161670, .max
= 227000 },
245 .vco
= { .min
= 1750000, .max
= 3500000},
246 .n
= { .min
= 1, .max
= 2 },
247 .m
= { .min
= 97, .max
= 108 },
248 .m1
= { .min
= 0x10, .max
= 0x12 },
249 .m2
= { .min
= 0x05, .max
= 0x06 },
250 .p
= { .min
= 10, .max
= 20 },
251 .p1
= { .min
= 1, .max
= 2},
252 .p2
= { .dot_limit
= 0,
253 .p2_slow
= 10, .p2_fast
= 10 },
254 .find_pll
= intel_find_pll_g4x_dp
,
257 static const intel_limit_t intel_limits_pineview_sdvo
= {
258 .dot
= { .min
= 20000, .max
= 400000},
259 .vco
= { .min
= 1700000, .max
= 3500000 },
260 /* Pineview's Ncounter is a ring counter */
261 .n
= { .min
= 3, .max
= 6 },
262 .m
= { .min
= 2, .max
= 256 },
263 /* Pineview only has one combined m divider, which we treat as m2. */
264 .m1
= { .min
= 0, .max
= 0 },
265 .m2
= { .min
= 0, .max
= 254 },
266 .p
= { .min
= 5, .max
= 80 },
267 .p1
= { .min
= 1, .max
= 8 },
268 .p2
= { .dot_limit
= 200000,
269 .p2_slow
= 10, .p2_fast
= 5 },
270 .find_pll
= intel_find_best_PLL
,
273 static const intel_limit_t intel_limits_pineview_lvds
= {
274 .dot
= { .min
= 20000, .max
= 400000 },
275 .vco
= { .min
= 1700000, .max
= 3500000 },
276 .n
= { .min
= 3, .max
= 6 },
277 .m
= { .min
= 2, .max
= 256 },
278 .m1
= { .min
= 0, .max
= 0 },
279 .m2
= { .min
= 0, .max
= 254 },
280 .p
= { .min
= 7, .max
= 112 },
281 .p1
= { .min
= 1, .max
= 8 },
282 .p2
= { .dot_limit
= 112000,
283 .p2_slow
= 14, .p2_fast
= 14 },
284 .find_pll
= intel_find_best_PLL
,
287 /* Ironlake / Sandybridge
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
292 static const intel_limit_t intel_limits_ironlake_dac
= {
293 .dot
= { .min
= 25000, .max
= 350000 },
294 .vco
= { .min
= 1760000, .max
= 3510000 },
295 .n
= { .min
= 1, .max
= 5 },
296 .m
= { .min
= 79, .max
= 127 },
297 .m1
= { .min
= 12, .max
= 22 },
298 .m2
= { .min
= 5, .max
= 9 },
299 .p
= { .min
= 5, .max
= 80 },
300 .p1
= { .min
= 1, .max
= 8 },
301 .p2
= { .dot_limit
= 225000,
302 .p2_slow
= 10, .p2_fast
= 5 },
303 .find_pll
= intel_g4x_find_best_PLL
,
306 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
307 .dot
= { .min
= 25000, .max
= 350000 },
308 .vco
= { .min
= 1760000, .max
= 3510000 },
309 .n
= { .min
= 1, .max
= 3 },
310 .m
= { .min
= 79, .max
= 118 },
311 .m1
= { .min
= 12, .max
= 22 },
312 .m2
= { .min
= 5, .max
= 9 },
313 .p
= { .min
= 28, .max
= 112 },
314 .p1
= { .min
= 2, .max
= 8 },
315 .p2
= { .dot_limit
= 225000,
316 .p2_slow
= 14, .p2_fast
= 14 },
317 .find_pll
= intel_g4x_find_best_PLL
,
320 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
321 .dot
= { .min
= 25000, .max
= 350000 },
322 .vco
= { .min
= 1760000, .max
= 3510000 },
323 .n
= { .min
= 1, .max
= 3 },
324 .m
= { .min
= 79, .max
= 127 },
325 .m1
= { .min
= 12, .max
= 22 },
326 .m2
= { .min
= 5, .max
= 9 },
327 .p
= { .min
= 14, .max
= 56 },
328 .p1
= { .min
= 2, .max
= 8 },
329 .p2
= { .dot_limit
= 225000,
330 .p2_slow
= 7, .p2_fast
= 7 },
331 .find_pll
= intel_g4x_find_best_PLL
,
334 /* LVDS 100mhz refclk limits. */
335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
336 .dot
= { .min
= 25000, .max
= 350000 },
337 .vco
= { .min
= 1760000, .max
= 3510000 },
338 .n
= { .min
= 1, .max
= 2 },
339 .m
= { .min
= 79, .max
= 126 },
340 .m1
= { .min
= 12, .max
= 22 },
341 .m2
= { .min
= 5, .max
= 9 },
342 .p
= { .min
= 28, .max
= 112 },
343 .p1
= { .min
= 2, .max
= 8 },
344 .p2
= { .dot_limit
= 225000,
345 .p2_slow
= 14, .p2_fast
= 14 },
346 .find_pll
= intel_g4x_find_best_PLL
,
349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
350 .dot
= { .min
= 25000, .max
= 350000 },
351 .vco
= { .min
= 1760000, .max
= 3510000 },
352 .n
= { .min
= 1, .max
= 3 },
353 .m
= { .min
= 79, .max
= 126 },
354 .m1
= { .min
= 12, .max
= 22 },
355 .m2
= { .min
= 5, .max
= 9 },
356 .p
= { .min
= 14, .max
= 42 },
357 .p1
= { .min
= 2, .max
= 6 },
358 .p2
= { .dot_limit
= 225000,
359 .p2_slow
= 7, .p2_fast
= 7 },
360 .find_pll
= intel_g4x_find_best_PLL
,
363 static const intel_limit_t intel_limits_ironlake_display_port
= {
364 .dot
= { .min
= 25000, .max
= 350000 },
365 .vco
= { .min
= 1760000, .max
= 3510000},
366 .n
= { .min
= 1, .max
= 2 },
367 .m
= { .min
= 81, .max
= 90 },
368 .m1
= { .min
= 12, .max
= 22 },
369 .m2
= { .min
= 5, .max
= 9 },
370 .p
= { .min
= 10, .max
= 20 },
371 .p1
= { .min
= 1, .max
= 2},
372 .p2
= { .dot_limit
= 0,
373 .p2_slow
= 10, .p2_fast
= 10 },
374 .find_pll
= intel_find_pll_ironlake_dp
,
377 static const intel_limit_t intel_limits_vlv_dac
= {
378 .dot
= { .min
= 25000, .max
= 270000 },
379 .vco
= { .min
= 4000000, .max
= 6000000 },
380 .n
= { .min
= 1, .max
= 7 },
381 .m
= { .min
= 22, .max
= 450 }, /* guess */
382 .m1
= { .min
= 2, .max
= 3 },
383 .m2
= { .min
= 11, .max
= 156 },
384 .p
= { .min
= 10, .max
= 30 },
385 .p1
= { .min
= 2, .max
= 3 },
386 .p2
= { .dot_limit
= 270000,
387 .p2_slow
= 2, .p2_fast
= 20 },
388 .find_pll
= intel_vlv_find_best_pll
,
391 static const intel_limit_t intel_limits_vlv_hdmi
= {
392 .dot
= { .min
= 20000, .max
= 165000 },
393 .vco
= { .min
= 4000000, .max
= 5994000},
394 .n
= { .min
= 1, .max
= 7 },
395 .m
= { .min
= 60, .max
= 300 }, /* guess */
396 .m1
= { .min
= 2, .max
= 3 },
397 .m2
= { .min
= 11, .max
= 156 },
398 .p
= { .min
= 10, .max
= 30 },
399 .p1
= { .min
= 2, .max
= 3 },
400 .p2
= { .dot_limit
= 270000,
401 .p2_slow
= 2, .p2_fast
= 20 },
402 .find_pll
= intel_vlv_find_best_pll
,
405 static const intel_limit_t intel_limits_vlv_dp
= {
406 .dot
= { .min
= 25000, .max
= 270000 },
407 .vco
= { .min
= 4000000, .max
= 6000000 },
408 .n
= { .min
= 1, .max
= 7 },
409 .m
= { .min
= 22, .max
= 450 },
410 .m1
= { .min
= 2, .max
= 3 },
411 .m2
= { .min
= 11, .max
= 156 },
412 .p
= { .min
= 10, .max
= 30 },
413 .p1
= { .min
= 2, .max
= 3 },
414 .p2
= { .dot_limit
= 270000,
415 .p2_slow
= 2, .p2_fast
= 20 },
416 .find_pll
= intel_vlv_find_best_pll
,
419 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
424 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
430 I915_WRITE(DPIO_REG
, reg
);
431 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
437 val
= I915_READ(DPIO_DATA
);
440 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
444 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
449 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
455 I915_WRITE(DPIO_DATA
, val
);
456 I915_WRITE(DPIO_REG
, reg
);
457 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
463 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
466 static void vlv_init_dpio(struct drm_device
*dev
)
468 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL
, 0);
472 POSTING_READ(DPIO_CTL
);
473 I915_WRITE(DPIO_CTL
, 1);
474 POSTING_READ(DPIO_CTL
);
477 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
483 static const struct dmi_system_id intel_dual_link_lvds
[] = {
485 .callback
= intel_dual_link_lvds_callback
,
486 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
488 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
492 { } /* terminating entry */
495 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode
> 0)
502 return i915_lvds_channel_mode
== 2;
504 if (dmi_check_system(intel_dual_link_lvds
))
507 if (dev_priv
->lvds_val
)
508 val
= dev_priv
->lvds_val
;
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
515 val
= I915_READ(reg
);
516 if (!(val
& ~(LVDS_PIPE_MASK
| LVDS_DETECTED
)))
517 val
= dev_priv
->bios_lvds_val
;
518 dev_priv
->lvds_val
= val
;
520 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
523 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
526 struct drm_device
*dev
= crtc
->dev
;
527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
528 const intel_limit_t
*limit
;
530 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
531 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
532 /* LVDS dual channel */
533 if (refclk
== 100000)
534 limit
= &intel_limits_ironlake_dual_lvds_100m
;
536 limit
= &intel_limits_ironlake_dual_lvds
;
538 if (refclk
== 100000)
539 limit
= &intel_limits_ironlake_single_lvds_100m
;
541 limit
= &intel_limits_ironlake_single_lvds
;
543 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
545 limit
= &intel_limits_ironlake_display_port
;
547 limit
= &intel_limits_ironlake_dac
;
552 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
554 struct drm_device
*dev
= crtc
->dev
;
555 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
556 const intel_limit_t
*limit
;
558 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
559 if (is_dual_link_lvds(dev_priv
, LVDS
))
560 /* LVDS with dual channel */
561 limit
= &intel_limits_g4x_dual_channel_lvds
;
563 /* LVDS with dual channel */
564 limit
= &intel_limits_g4x_single_channel_lvds
;
565 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
566 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
567 limit
= &intel_limits_g4x_hdmi
;
568 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
569 limit
= &intel_limits_g4x_sdvo
;
570 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
571 limit
= &intel_limits_g4x_display_port
;
572 } else /* The option is for other outputs */
573 limit
= &intel_limits_i9xx_sdvo
;
578 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
580 struct drm_device
*dev
= crtc
->dev
;
581 const intel_limit_t
*limit
;
583 if (HAS_PCH_SPLIT(dev
))
584 limit
= intel_ironlake_limit(crtc
, refclk
);
585 else if (IS_G4X(dev
)) {
586 limit
= intel_g4x_limit(crtc
);
587 } else if (IS_PINEVIEW(dev
)) {
588 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
589 limit
= &intel_limits_pineview_lvds
;
591 limit
= &intel_limits_pineview_sdvo
;
592 } else if (IS_VALLEYVIEW(dev
)) {
593 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
594 limit
= &intel_limits_vlv_dac
;
595 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
596 limit
= &intel_limits_vlv_hdmi
;
598 limit
= &intel_limits_vlv_dp
;
599 } else if (!IS_GEN2(dev
)) {
600 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
601 limit
= &intel_limits_i9xx_lvds
;
603 limit
= &intel_limits_i9xx_sdvo
;
605 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
606 limit
= &intel_limits_i8xx_lvds
;
608 limit
= &intel_limits_i8xx_dvo
;
613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
614 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
616 clock
->m
= clock
->m2
+ 2;
617 clock
->p
= clock
->p1
* clock
->p2
;
618 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
619 clock
->dot
= clock
->vco
/ clock
->p
;
622 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
624 if (IS_PINEVIEW(dev
)) {
625 pineview_clock(refclk
, clock
);
628 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
629 clock
->p
= clock
->p1
* clock
->p2
;
630 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
631 clock
->dot
= clock
->vco
/ clock
->p
;
635 * Returns whether any output on the specified pipe is of the specified type
637 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
639 struct drm_device
*dev
= crtc
->dev
;
640 struct intel_encoder
*encoder
;
642 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
643 if (encoder
->type
== type
)
649 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
655 static bool intel_PLL_is_valid(struct drm_device
*dev
,
656 const intel_limit_t
*limit
,
657 const intel_clock_t
*clock
)
659 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
660 INTELPllInvalid("p1 out of range\n");
661 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
662 INTELPllInvalid("p out of range\n");
663 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
664 INTELPllInvalid("m2 out of range\n");
665 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
666 INTELPllInvalid("m1 out of range\n");
667 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
668 INTELPllInvalid("m1 <= m2\n");
669 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
670 INTELPllInvalid("m out of range\n");
671 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
672 INTELPllInvalid("n out of range\n");
673 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
678 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
679 INTELPllInvalid("dot out of range\n");
685 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
686 int target
, int refclk
, intel_clock_t
*match_clock
,
687 intel_clock_t
*best_clock
)
690 struct drm_device
*dev
= crtc
->dev
;
691 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
695 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
696 (I915_READ(LVDS
)) != 0) {
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
703 if (is_dual_link_lvds(dev_priv
, LVDS
))
704 clock
.p2
= limit
->p2
.p2_fast
;
706 clock
.p2
= limit
->p2
.p2_slow
;
708 if (target
< limit
->p2
.dot_limit
)
709 clock
.p2
= limit
->p2
.p2_slow
;
711 clock
.p2
= limit
->p2
.p2_fast
;
714 memset(best_clock
, 0, sizeof(*best_clock
));
716 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
718 for (clock
.m2
= limit
->m2
.min
;
719 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
720 /* m1 is always 0 in Pineview */
721 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
723 for (clock
.n
= limit
->n
.min
;
724 clock
.n
<= limit
->n
.max
; clock
.n
++) {
725 for (clock
.p1
= limit
->p1
.min
;
726 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
729 intel_clock(dev
, refclk
, &clock
);
730 if (!intel_PLL_is_valid(dev
, limit
,
734 clock
.p
!= match_clock
->p
)
737 this_err
= abs(clock
.dot
- target
);
738 if (this_err
< err
) {
747 return (err
!= target
);
751 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
752 int target
, int refclk
, intel_clock_t
*match_clock
,
753 intel_clock_t
*best_clock
)
755 struct drm_device
*dev
= crtc
->dev
;
756 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
760 /* approximately equals target * 0.00585 */
761 int err_most
= (target
>> 8) + (target
>> 9);
764 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
767 if (HAS_PCH_SPLIT(dev
))
771 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
773 clock
.p2
= limit
->p2
.p2_fast
;
775 clock
.p2
= limit
->p2
.p2_slow
;
777 if (target
< limit
->p2
.dot_limit
)
778 clock
.p2
= limit
->p2
.p2_slow
;
780 clock
.p2
= limit
->p2
.p2_fast
;
783 memset(best_clock
, 0, sizeof(*best_clock
));
784 max_n
= limit
->n
.max
;
785 /* based on hardware requirement, prefer smaller n to precision */
786 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
787 /* based on hardware requirement, prefere larger m1,m2 */
788 for (clock
.m1
= limit
->m1
.max
;
789 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
790 for (clock
.m2
= limit
->m2
.max
;
791 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
792 for (clock
.p1
= limit
->p1
.max
;
793 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
796 intel_clock(dev
, refclk
, &clock
);
797 if (!intel_PLL_is_valid(dev
, limit
,
801 clock
.p
!= match_clock
->p
)
804 this_err
= abs(clock
.dot
- target
);
805 if (this_err
< err_most
) {
819 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
820 int target
, int refclk
, intel_clock_t
*match_clock
,
821 intel_clock_t
*best_clock
)
823 struct drm_device
*dev
= crtc
->dev
;
826 if (target
< 200000) {
839 intel_clock(dev
, refclk
, &clock
);
840 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
846 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
847 int target
, int refclk
, intel_clock_t
*match_clock
,
848 intel_clock_t
*best_clock
)
851 if (target
< 200000) {
864 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
865 clock
.p
= (clock
.p1
* clock
.p2
);
866 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
868 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
872 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
873 int target
, int refclk
, intel_clock_t
*match_clock
,
874 intel_clock_t
*best_clock
)
876 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
878 u32 updrate
, minupdate
, fracbits
, p
;
879 unsigned long bestppm
, ppm
, absppm
;
883 dotclk
= target
* 1000;
886 fastclk
= dotclk
/ (2*100);
890 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
891 bestm1
= bestm2
= bestp1
= bestp2
= 0;
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
895 updrate
= refclk
/ n
;
896 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
897 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
903 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
904 refclk
) / (2*refclk
));
907 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
908 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
909 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
910 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
914 if (absppm
< bestppm
- 10) {
931 best_clock
->n
= bestn
;
932 best_clock
->m1
= bestm1
;
933 best_clock
->m2
= bestm2
;
934 best_clock
->p1
= bestp1
;
935 best_clock
->p2
= bestp2
;
940 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
943 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
944 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
946 return intel_crtc
->cpu_transcoder
;
949 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
954 frame
= I915_READ(frame_reg
);
956 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
961 * intel_wait_for_vblank - wait for vblank on a given pipe
963 * @pipe: pipe to wait for
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
968 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
971 int pipestat_reg
= PIPESTAT(pipe
);
973 if (INTEL_INFO(dev
)->gen
>= 5) {
974 ironlake_wait_for_vblank(dev
, pipe
);
978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
991 I915_WRITE(pipestat_reg
,
992 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
994 /* Wait for vblank interrupt bit to set */
995 if (wait_for(I915_READ(pipestat_reg
) &
996 PIPE_VBLANK_INTERRUPT_STATUS
,
998 DRM_DEBUG_KMS("vblank wait timed out\n");
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
1004 * @pipe: pipe to wait for
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
1018 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1021 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1024 if (INTEL_INFO(dev
)->gen
>= 4) {
1025 int reg
= PIPECONF(cpu_transcoder
);
1027 /* Wait for the Pipe State to go off */
1028 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1030 WARN(1, "pipe_off wait timed out\n");
1032 u32 last_line
, line_mask
;
1033 int reg
= PIPEDSL(pipe
);
1034 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1037 line_mask
= DSL_LINEMASK_GEN2
;
1039 line_mask
= DSL_LINEMASK_GEN3
;
1041 /* Wait for the display line to settle */
1043 last_line
= I915_READ(reg
) & line_mask
;
1045 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
1046 time_after(timeout
, jiffies
));
1047 if (time_after(jiffies
, timeout
))
1048 WARN(1, "pipe_off wait timed out\n");
1052 static const char *state_string(bool enabled
)
1054 return enabled
? "on" : "off";
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private
*dev_priv
,
1059 enum pipe pipe
, bool state
)
1066 val
= I915_READ(reg
);
1067 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1068 WARN(cur_state
!= state
,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state
), state_string(cur_state
));
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1076 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1077 struct intel_pch_pll
*pll
,
1078 struct intel_crtc
*crtc
,
1084 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1090 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1093 val
= I915_READ(pll
->pll_reg
);
1094 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1095 WARN(cur_state
!= state
,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1103 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1104 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1105 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state
, crtc
->pipe
, pch_dpll
)) {
1108 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1109 WARN(cur_state
!= state
,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll
->pll_reg
== _PCH_DPLL_B
,
1112 state_string(state
),
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1121 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1122 enum pipe pipe
, bool state
)
1127 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1130 if (IS_HASWELL(dev_priv
->dev
)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1133 val
= I915_READ(reg
);
1134 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1136 reg
= FDI_TX_CTL(pipe
);
1137 val
= I915_READ(reg
);
1138 cur_state
= !!(val
& FDI_TX_ENABLE
);
1140 WARN(cur_state
!= state
,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state
), state_string(cur_state
));
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1147 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1148 enum pipe pipe
, bool state
)
1154 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1158 reg
= FDI_RX_CTL(pipe
);
1159 val
= I915_READ(reg
);
1160 cur_state
= !!(val
& FDI_RX_ENABLE
);
1162 WARN(cur_state
!= state
,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state
), state_string(cur_state
));
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv
->info
->gen
== 5)
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv
->dev
))
1183 reg
= FDI_TX_CTL(pipe
);
1184 val
= I915_READ(reg
);
1185 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1194 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1198 reg
= FDI_RX_CTL(pipe
);
1199 val
= I915_READ(reg
);
1200 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1203 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1206 int pp_reg
, lvds_reg
;
1208 enum pipe panel_pipe
= PIPE_A
;
1211 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1212 pp_reg
= PCH_PP_CONTROL
;
1213 lvds_reg
= PCH_LVDS
;
1215 pp_reg
= PP_CONTROL
;
1219 val
= I915_READ(pp_reg
);
1220 if (!(val
& PANEL_POWER_ON
) ||
1221 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1224 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1225 panel_pipe
= PIPE_B
;
1227 WARN(panel_pipe
== pipe
&& locked
,
1228 "panel assertion failure, pipe %c regs locked\n",
1232 void assert_pipe(struct drm_i915_private
*dev_priv
,
1233 enum pipe pipe
, bool state
)
1238 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1245 reg
= PIPECONF(cpu_transcoder
);
1246 val
= I915_READ(reg
);
1247 cur_state
= !!(val
& PIPECONF_ENABLE
);
1248 WARN(cur_state
!= state
,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1253 static void assert_plane(struct drm_i915_private
*dev_priv
,
1254 enum plane plane
, bool state
)
1260 reg
= DSPCNTR(plane
);
1261 val
= I915_READ(reg
);
1262 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1263 WARN(cur_state
!= state
,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane
), state_string(state
), state_string(cur_state
));
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1271 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1278 /* Planes are fixed to pipes on ILK+ */
1279 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1280 reg
= DSPCNTR(pipe
);
1281 val
= I915_READ(reg
);
1282 WARN((val
& DISPLAY_PLANE_ENABLE
),
1283 "plane %c assertion failure, should be disabled but not\n",
1288 /* Need to check both planes against the pipe */
1289 for (i
= 0; i
< 2; i
++) {
1291 val
= I915_READ(reg
);
1292 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1293 DISPPLANE_SEL_PIPE_SHIFT
;
1294 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i
), pipe_name(pipe
));
1300 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1305 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1310 val
= I915_READ(PCH_DREF_CONTROL
);
1311 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1312 DREF_SUPERSPREAD_SOURCE_MASK
));
1313 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1316 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1323 reg
= TRANSCONF(pipe
);
1324 val
= I915_READ(reg
);
1325 enabled
= !!(val
& TRANS_ENABLE
);
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1331 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1332 enum pipe pipe
, u32 port_sel
, u32 val
)
1334 if ((val
& DP_PORT_EN
) == 0)
1337 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1338 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1339 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1340 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1343 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1349 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1350 enum pipe pipe
, u32 val
)
1352 if ((val
& PORT_ENABLE
) == 0)
1355 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1356 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1359 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1365 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1366 enum pipe pipe
, u32 val
)
1368 if ((val
& LVDS_PORT_EN
) == 0)
1371 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1372 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1375 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1381 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1382 enum pipe pipe
, u32 val
)
1384 if ((val
& ADPA_DAC_ENABLE
) == 0)
1386 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1387 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1390 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1396 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1397 enum pipe pipe
, int reg
, u32 port_sel
)
1399 u32 val
= I915_READ(reg
);
1400 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402 reg
, pipe_name(pipe
));
1404 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1405 && (val
& DP_PIPEB_SELECT
),
1406 "IBX PCH dp port still using transcoder B\n");
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1410 enum pipe pipe
, int reg
)
1412 u32 val
= I915_READ(reg
);
1413 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415 reg
, pipe_name(pipe
));
1417 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& PORT_ENABLE
) == 0
1418 && (val
& SDVO_PIPE_B_SELECT
),
1419 "IBX PCH hdmi port still using transcoder B\n");
1422 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1428 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1429 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1430 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1433 val
= I915_READ(reg
);
1434 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
1439 val
= I915_READ(reg
);
1440 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1444 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1445 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1446 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1458 * Note! This is for pre-ILK only.
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1462 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1467 /* No really, not for ILK+ */
1468 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1472 assert_panel_unlocked(dev_priv
, pipe
);
1475 val
= I915_READ(reg
);
1476 val
|= DPLL_VCO_ENABLE
;
1478 /* We do this three times for luck */
1479 I915_WRITE(reg
, val
);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg
, val
);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg
, val
);
1487 udelay(150); /* wait for warmup */
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1497 * Note! This is for pre-ILK only.
1499 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv
, pipe
);
1512 val
= I915_READ(reg
);
1513 val
&= ~DPLL_VCO_ENABLE
;
1514 I915_WRITE(reg
, val
);
1520 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1522 unsigned long flags
;
1524 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1525 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1531 I915_WRITE(SBI_ADDR
,
1533 I915_WRITE(SBI_DATA
,
1535 I915_WRITE(SBI_CTL_STAT
,
1539 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1546 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1550 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1552 unsigned long flags
;
1555 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1556 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1562 I915_WRITE(SBI_ADDR
,
1564 I915_WRITE(SBI_CTL_STAT
,
1568 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1574 value
= I915_READ(SBI_DATA
);
1577 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1582 * intel_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1589 static void intel_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1591 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1592 struct intel_pch_pll
*pll
;
1596 /* PCH PLLs only available on ILK, SNB and IVB */
1597 BUG_ON(dev_priv
->info
->gen
< 5);
1598 pll
= intel_crtc
->pch_pll
;
1602 if (WARN_ON(pll
->refcount
== 0))
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll
->pll_reg
, pll
->active
, pll
->on
,
1607 intel_crtc
->base
.base
.id
);
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv
);
1612 if (pll
->active
++ && pll
->on
) {
1613 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1620 val
= I915_READ(reg
);
1621 val
|= DPLL_VCO_ENABLE
;
1622 I915_WRITE(reg
, val
);
1629 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1631 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1632 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv
->info
->gen
< 5);
1641 if (WARN_ON(pll
->refcount
== 0))
1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll
->pll_reg
, pll
->active
, pll
->on
,
1646 intel_crtc
->base
.base
.id
);
1648 if (WARN_ON(pll
->active
== 0)) {
1649 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1653 if (--pll
->active
) {
1654 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1664 val
= I915_READ(reg
);
1665 val
&= ~DPLL_VCO_ENABLE
;
1666 I915_WRITE(reg
, val
);
1673 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1677 u32 val
, pipeconf_val
;
1678 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv
->info
->gen
< 5);
1683 /* Make sure PCH DPLL is enabled */
1684 assert_pch_pll_enabled(dev_priv
,
1685 to_intel_crtc(crtc
)->pch_pll
,
1686 to_intel_crtc(crtc
));
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv
, pipe
);
1690 assert_fdi_rx_enabled(dev_priv
, pipe
);
1692 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1693 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1696 reg
= TRANSCONF(pipe
);
1697 val
= I915_READ(reg
);
1698 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1700 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1702 * make the BPC in transcoder be consistent with
1703 * that in pipeconf reg.
1705 val
&= ~PIPE_BPC_MASK
;
1706 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1709 val
&= ~TRANS_INTERLACE_MASK
;
1710 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1711 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1712 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1713 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1715 val
|= TRANS_INTERLACED
;
1717 val
|= TRANS_PROGRESSIVE
;
1719 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1720 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1721 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1724 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1730 /* FDI relies on the transcoder */
1731 assert_fdi_tx_disabled(dev_priv
, pipe
);
1732 assert_fdi_rx_disabled(dev_priv
, pipe
);
1734 /* Ports must be off as well */
1735 assert_pch_ports_disabled(dev_priv
, pipe
);
1737 reg
= TRANSCONF(pipe
);
1738 val
= I915_READ(reg
);
1739 val
&= ~TRANS_ENABLE
;
1740 I915_WRITE(reg
, val
);
1741 /* wait for PCH transcoder off, transcoder state */
1742 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1743 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1747 * intel_enable_pipe - enable a pipe, asserting requirements
1748 * @dev_priv: i915 private structure
1749 * @pipe: pipe to enable
1750 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1752 * Enable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1755 * @pipe should be %PIPE_A or %PIPE_B.
1757 * Will wait until the pipe is actually running (i.e. first vblank) before
1760 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1763 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1769 * A pipe without a PLL won't actually be able to drive bits from
1770 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1773 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1774 assert_pll_enabled(dev_priv
, pipe
);
1777 /* if driving the PCH, we need FDI enabled */
1778 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1779 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1781 /* FIXME: assert CPU port conditions for SNB+ */
1784 reg
= PIPECONF(cpu_transcoder
);
1785 val
= I915_READ(reg
);
1786 if (val
& PIPECONF_ENABLE
)
1789 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1790 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1794 * intel_disable_pipe - disable a pipe, asserting requirements
1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to disable
1798 * Disable @pipe, making sure that various hardware specific requirements
1799 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1801 * @pipe should be %PIPE_A or %PIPE_B.
1803 * Will wait until the pipe has shut down before returning.
1805 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1808 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1814 * Make sure planes won't keep trying to pump pixels to us,
1815 * or we might hang the display.
1817 assert_planes_disabled(dev_priv
, pipe
);
1819 /* Don't disable pipe A or pipe A PLLs if needed */
1820 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1823 reg
= PIPECONF(cpu_transcoder
);
1824 val
= I915_READ(reg
);
1825 if ((val
& PIPECONF_ENABLE
) == 0)
1828 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1829 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1833 * Plane regs are double buffered, going from enabled->disabled needs a
1834 * trigger in order to latch. The display address reg provides this.
1836 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1839 if (dev_priv
->info
->gen
>= 4)
1840 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1842 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1846 * intel_enable_plane - enable a display plane on a given pipe
1847 * @dev_priv: i915 private structure
1848 * @plane: plane to enable
1849 * @pipe: pipe being fed
1851 * Enable @plane on @pipe, making sure that @pipe is running first.
1853 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1854 enum plane plane
, enum pipe pipe
)
1859 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1860 assert_pipe_enabled(dev_priv
, pipe
);
1862 reg
= DSPCNTR(plane
);
1863 val
= I915_READ(reg
);
1864 if (val
& DISPLAY_PLANE_ENABLE
)
1867 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1868 intel_flush_display_plane(dev_priv
, plane
);
1869 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1873 * intel_disable_plane - disable a display plane
1874 * @dev_priv: i915 private structure
1875 * @plane: plane to disable
1876 * @pipe: pipe consuming the data
1878 * Disable @plane; should be an independent operation.
1880 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1881 enum plane plane
, enum pipe pipe
)
1886 reg
= DSPCNTR(plane
);
1887 val
= I915_READ(reg
);
1888 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1891 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1892 intel_flush_display_plane(dev_priv
, plane
);
1893 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1897 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1898 struct drm_i915_gem_object
*obj
,
1899 struct intel_ring_buffer
*pipelined
)
1901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1905 switch (obj
->tiling_mode
) {
1906 case I915_TILING_NONE
:
1907 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1908 alignment
= 128 * 1024;
1909 else if (INTEL_INFO(dev
)->gen
>= 4)
1910 alignment
= 4 * 1024;
1912 alignment
= 64 * 1024;
1915 /* pin() will align the object as required by fence */
1919 /* FIXME: Is this true? */
1920 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1926 dev_priv
->mm
.interruptible
= false;
1927 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1929 goto err_interruptible
;
1931 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1932 * fence, whereas 965+ only requires a fence if using
1933 * framebuffer compression. For simplicity, we always install
1934 * a fence as the cost is not that onerous.
1936 ret
= i915_gem_object_get_fence(obj
);
1940 i915_gem_object_pin_fence(obj
);
1942 dev_priv
->mm
.interruptible
= true;
1946 i915_gem_object_unpin(obj
);
1948 dev_priv
->mm
.interruptible
= true;
1952 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1954 i915_gem_object_unpin_fence(obj
);
1955 i915_gem_object_unpin(obj
);
1958 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1959 * is assumed to be a power-of-two. */
1960 unsigned long intel_gen4_compute_offset_xtiled(int *x
, int *y
,
1964 int tile_rows
, tiles
;
1968 tiles
= *x
/ (512/bpp
);
1971 return tile_rows
* pitch
* 8 + tiles
* 4096;
1974 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1977 struct drm_device
*dev
= crtc
->dev
;
1978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1979 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1980 struct intel_framebuffer
*intel_fb
;
1981 struct drm_i915_gem_object
*obj
;
1982 int plane
= intel_crtc
->plane
;
1983 unsigned long linear_offset
;
1992 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1996 intel_fb
= to_intel_framebuffer(fb
);
1997 obj
= intel_fb
->obj
;
1999 reg
= DSPCNTR(plane
);
2000 dspcntr
= I915_READ(reg
);
2001 /* Mask out pixel format bits in case we change it */
2002 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2003 switch (fb
->bits_per_pixel
) {
2005 dspcntr
|= DISPPLANE_8BPP
;
2008 if (fb
->depth
== 15)
2009 dspcntr
|= DISPPLANE_15_16BPP
;
2011 dspcntr
|= DISPPLANE_16BPP
;
2015 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2018 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2021 if (INTEL_INFO(dev
)->gen
>= 4) {
2022 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2023 dspcntr
|= DISPPLANE_TILED
;
2025 dspcntr
&= ~DISPPLANE_TILED
;
2028 I915_WRITE(reg
, dspcntr
);
2030 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2032 if (INTEL_INFO(dev
)->gen
>= 4) {
2033 intel_crtc
->dspaddr_offset
=
2034 intel_gen4_compute_offset_xtiled(&x
, &y
,
2035 fb
->bits_per_pixel
/ 8,
2037 linear_offset
-= intel_crtc
->dspaddr_offset
;
2039 intel_crtc
->dspaddr_offset
= linear_offset
;
2042 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2043 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2044 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2045 if (INTEL_INFO(dev
)->gen
>= 4) {
2046 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2047 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2048 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2049 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2051 I915_WRITE(DSPADDR(plane
), obj
->gtt_offset
+ linear_offset
);
2057 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2058 struct drm_framebuffer
*fb
, int x
, int y
)
2060 struct drm_device
*dev
= crtc
->dev
;
2061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2062 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2063 struct intel_framebuffer
*intel_fb
;
2064 struct drm_i915_gem_object
*obj
;
2065 int plane
= intel_crtc
->plane
;
2066 unsigned long linear_offset
;
2076 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2080 intel_fb
= to_intel_framebuffer(fb
);
2081 obj
= intel_fb
->obj
;
2083 reg
= DSPCNTR(plane
);
2084 dspcntr
= I915_READ(reg
);
2085 /* Mask out pixel format bits in case we change it */
2086 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2087 switch (fb
->bits_per_pixel
) {
2089 dspcntr
|= DISPPLANE_8BPP
;
2092 if (fb
->depth
!= 16)
2095 dspcntr
|= DISPPLANE_16BPP
;
2099 if (fb
->depth
== 24)
2100 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2101 else if (fb
->depth
== 30)
2102 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2107 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2111 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2112 dspcntr
|= DISPPLANE_TILED
;
2114 dspcntr
&= ~DISPPLANE_TILED
;
2117 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2119 I915_WRITE(reg
, dspcntr
);
2121 linear_offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2122 intel_crtc
->dspaddr_offset
=
2123 intel_gen4_compute_offset_xtiled(&x
, &y
,
2124 fb
->bits_per_pixel
/ 8,
2126 linear_offset
-= intel_crtc
->dspaddr_offset
;
2128 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2129 obj
->gtt_offset
, linear_offset
, x
, y
, fb
->pitches
[0]);
2130 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2131 I915_MODIFY_DISPBASE(DSPSURF(plane
),
2132 obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
2133 if (IS_HASWELL(dev
)) {
2134 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2136 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2137 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2144 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2146 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2147 int x
, int y
, enum mode_set_atomic state
)
2149 struct drm_device
*dev
= crtc
->dev
;
2150 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2152 if (dev_priv
->display
.disable_fbc
)
2153 dev_priv
->display
.disable_fbc(dev
);
2154 intel_increase_pllclock(crtc
);
2156 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2160 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2162 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2163 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2164 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2167 wait_event(dev_priv
->pending_flip_queue
,
2168 atomic_read(&dev_priv
->mm
.wedged
) ||
2169 atomic_read(&obj
->pending_flip
) == 0);
2171 /* Big Hammer, we also need to ensure that any pending
2172 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2173 * current scanout is retired before unpinning the old
2176 * This should only fail upon a hung GPU, in which case we
2177 * can safely continue.
2179 dev_priv
->mm
.interruptible
= false;
2180 ret
= i915_gem_object_finish_gpu(obj
);
2181 dev_priv
->mm
.interruptible
= was_interruptible
;
2187 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2188 struct drm_framebuffer
*fb
)
2190 struct drm_device
*dev
= crtc
->dev
;
2191 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2192 struct drm_i915_master_private
*master_priv
;
2193 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2194 struct drm_framebuffer
*old_fb
;
2199 DRM_ERROR("No FB bound\n");
2203 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2204 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2206 dev_priv
->num_pipe
);
2210 mutex_lock(&dev
->struct_mutex
);
2211 ret
= intel_pin_and_fence_fb_obj(dev
,
2212 to_intel_framebuffer(fb
)->obj
,
2215 mutex_unlock(&dev
->struct_mutex
);
2216 DRM_ERROR("pin & fence failed\n");
2221 intel_finish_fb(crtc
->fb
);
2223 ret
= dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2225 intel_unpin_fb_obj(to_intel_framebuffer(fb
)->obj
);
2226 mutex_unlock(&dev
->struct_mutex
);
2227 DRM_ERROR("failed to update base address\n");
2237 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2238 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2241 intel_update_fbc(dev
);
2242 mutex_unlock(&dev
->struct_mutex
);
2244 if (!dev
->primary
->master
)
2247 master_priv
= dev
->primary
->master
->driver_priv
;
2248 if (!master_priv
->sarea_priv
)
2251 if (intel_crtc
->pipe
) {
2252 master_priv
->sarea_priv
->pipeB_x
= x
;
2253 master_priv
->sarea_priv
->pipeB_y
= y
;
2255 master_priv
->sarea_priv
->pipeA_x
= x
;
2256 master_priv
->sarea_priv
->pipeA_y
= y
;
2262 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2264 struct drm_device
*dev
= crtc
->dev
;
2265 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2268 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2269 dpa_ctl
= I915_READ(DP_A
);
2270 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2272 if (clock
< 200000) {
2274 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2275 /* workaround for 160Mhz:
2276 1) program 0x4600c bits 15:0 = 0x8124
2277 2) program 0x46010 bit 0 = 1
2278 3) program 0x46034 bit 24 = 1
2279 4) program 0x64000 bit 14 = 1
2281 temp
= I915_READ(0x4600c);
2283 I915_WRITE(0x4600c, temp
| 0x8124);
2285 temp
= I915_READ(0x46010);
2286 I915_WRITE(0x46010, temp
| 1);
2288 temp
= I915_READ(0x46034);
2289 I915_WRITE(0x46034, temp
| (1 << 24));
2291 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2293 I915_WRITE(DP_A
, dpa_ctl
);
2299 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2301 struct drm_device
*dev
= crtc
->dev
;
2302 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2303 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2304 int pipe
= intel_crtc
->pipe
;
2307 /* enable normal train */
2308 reg
= FDI_TX_CTL(pipe
);
2309 temp
= I915_READ(reg
);
2310 if (IS_IVYBRIDGE(dev
)) {
2311 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2312 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2314 temp
&= ~FDI_LINK_TRAIN_NONE
;
2315 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2317 I915_WRITE(reg
, temp
);
2319 reg
= FDI_RX_CTL(pipe
);
2320 temp
= I915_READ(reg
);
2321 if (HAS_PCH_CPT(dev
)) {
2322 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2323 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2325 temp
&= ~FDI_LINK_TRAIN_NONE
;
2326 temp
|= FDI_LINK_TRAIN_NONE
;
2328 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2330 /* wait one idle pattern time */
2334 /* IVB wants error correction enabled */
2335 if (IS_IVYBRIDGE(dev
))
2336 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2337 FDI_FE_ERRC_ENABLE
);
2340 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2343 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2345 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2346 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2347 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2348 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2349 POSTING_READ(SOUTH_CHICKEN1
);
2352 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2354 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2355 struct intel_crtc
*pipe_B_crtc
=
2356 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2357 struct intel_crtc
*pipe_C_crtc
=
2358 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2361 /* When everything is off disable fdi C so that we could enable fdi B
2362 * with all lanes. XXX: This misses the case where a pipe is not using
2363 * any pch resources and so doesn't need any fdi lanes. */
2364 if (!pipe_B_crtc
->base
.enabled
&& !pipe_C_crtc
->base
.enabled
) {
2365 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2366 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2368 temp
= I915_READ(SOUTH_CHICKEN1
);
2369 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2370 DRM_DEBUG_KMS("disabling fdi C rx\n");
2371 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2375 /* The FDI link training functions for ILK/Ibexpeak. */
2376 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2378 struct drm_device
*dev
= crtc
->dev
;
2379 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2380 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2381 int pipe
= intel_crtc
->pipe
;
2382 int plane
= intel_crtc
->plane
;
2383 u32 reg
, temp
, tries
;
2385 /* FDI needs bits from pipe & plane first */
2386 assert_pipe_enabled(dev_priv
, pipe
);
2387 assert_plane_enabled(dev_priv
, plane
);
2389 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2391 reg
= FDI_RX_IMR(pipe
);
2392 temp
= I915_READ(reg
);
2393 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2394 temp
&= ~FDI_RX_BIT_LOCK
;
2395 I915_WRITE(reg
, temp
);
2399 /* enable CPU FDI TX and PCH FDI RX */
2400 reg
= FDI_TX_CTL(pipe
);
2401 temp
= I915_READ(reg
);
2403 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2404 temp
&= ~FDI_LINK_TRAIN_NONE
;
2405 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2406 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2408 reg
= FDI_RX_CTL(pipe
);
2409 temp
= I915_READ(reg
);
2410 temp
&= ~FDI_LINK_TRAIN_NONE
;
2411 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2412 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2417 /* Ironlake workaround, enable clock pointer after FDI enable*/
2418 if (HAS_PCH_IBX(dev
)) {
2419 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2420 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2421 FDI_RX_PHASE_SYNC_POINTER_EN
);
2424 reg
= FDI_RX_IIR(pipe
);
2425 for (tries
= 0; tries
< 5; tries
++) {
2426 temp
= I915_READ(reg
);
2427 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2429 if ((temp
& FDI_RX_BIT_LOCK
)) {
2430 DRM_DEBUG_KMS("FDI train 1 done.\n");
2431 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2436 DRM_ERROR("FDI train 1 fail!\n");
2439 reg
= FDI_TX_CTL(pipe
);
2440 temp
= I915_READ(reg
);
2441 temp
&= ~FDI_LINK_TRAIN_NONE
;
2442 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2443 I915_WRITE(reg
, temp
);
2445 reg
= FDI_RX_CTL(pipe
);
2446 temp
= I915_READ(reg
);
2447 temp
&= ~FDI_LINK_TRAIN_NONE
;
2448 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2449 I915_WRITE(reg
, temp
);
2454 reg
= FDI_RX_IIR(pipe
);
2455 for (tries
= 0; tries
< 5; tries
++) {
2456 temp
= I915_READ(reg
);
2457 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2459 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2460 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2461 DRM_DEBUG_KMS("FDI train 2 done.\n");
2466 DRM_ERROR("FDI train 2 fail!\n");
2468 DRM_DEBUG_KMS("FDI train done\n");
2472 static const int snb_b_fdi_train_param
[] = {
2473 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2474 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2475 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2476 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2479 /* The FDI link training functions for SNB/Cougarpoint. */
2480 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2482 struct drm_device
*dev
= crtc
->dev
;
2483 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2484 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2485 int pipe
= intel_crtc
->pipe
;
2486 u32 reg
, temp
, i
, retry
;
2488 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2490 reg
= FDI_RX_IMR(pipe
);
2491 temp
= I915_READ(reg
);
2492 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2493 temp
&= ~FDI_RX_BIT_LOCK
;
2494 I915_WRITE(reg
, temp
);
2499 /* enable CPU FDI TX and PCH FDI RX */
2500 reg
= FDI_TX_CTL(pipe
);
2501 temp
= I915_READ(reg
);
2503 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2504 temp
&= ~FDI_LINK_TRAIN_NONE
;
2505 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2506 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2508 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2509 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2511 I915_WRITE(FDI_RX_MISC(pipe
),
2512 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2514 reg
= FDI_RX_CTL(pipe
);
2515 temp
= I915_READ(reg
);
2516 if (HAS_PCH_CPT(dev
)) {
2517 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2518 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2520 temp
&= ~FDI_LINK_TRAIN_NONE
;
2521 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2523 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2528 if (HAS_PCH_CPT(dev
))
2529 cpt_phase_pointer_enable(dev
, pipe
);
2531 for (i
= 0; i
< 4; i
++) {
2532 reg
= FDI_TX_CTL(pipe
);
2533 temp
= I915_READ(reg
);
2534 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2535 temp
|= snb_b_fdi_train_param
[i
];
2536 I915_WRITE(reg
, temp
);
2541 for (retry
= 0; retry
< 5; retry
++) {
2542 reg
= FDI_RX_IIR(pipe
);
2543 temp
= I915_READ(reg
);
2544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2545 if (temp
& FDI_RX_BIT_LOCK
) {
2546 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2547 DRM_DEBUG_KMS("FDI train 1 done.\n");
2556 DRM_ERROR("FDI train 1 fail!\n");
2559 reg
= FDI_TX_CTL(pipe
);
2560 temp
= I915_READ(reg
);
2561 temp
&= ~FDI_LINK_TRAIN_NONE
;
2562 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2564 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2566 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2568 I915_WRITE(reg
, temp
);
2570 reg
= FDI_RX_CTL(pipe
);
2571 temp
= I915_READ(reg
);
2572 if (HAS_PCH_CPT(dev
)) {
2573 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2574 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2576 temp
&= ~FDI_LINK_TRAIN_NONE
;
2577 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2579 I915_WRITE(reg
, temp
);
2584 for (i
= 0; i
< 4; i
++) {
2585 reg
= FDI_TX_CTL(pipe
);
2586 temp
= I915_READ(reg
);
2587 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2588 temp
|= snb_b_fdi_train_param
[i
];
2589 I915_WRITE(reg
, temp
);
2594 for (retry
= 0; retry
< 5; retry
++) {
2595 reg
= FDI_RX_IIR(pipe
);
2596 temp
= I915_READ(reg
);
2597 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2598 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2599 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2600 DRM_DEBUG_KMS("FDI train 2 done.\n");
2609 DRM_ERROR("FDI train 2 fail!\n");
2611 DRM_DEBUG_KMS("FDI train done.\n");
2614 /* Manual link training for Ivy Bridge A0 parts */
2615 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2617 struct drm_device
*dev
= crtc
->dev
;
2618 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2619 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2620 int pipe
= intel_crtc
->pipe
;
2623 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2625 reg
= FDI_RX_IMR(pipe
);
2626 temp
= I915_READ(reg
);
2627 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2628 temp
&= ~FDI_RX_BIT_LOCK
;
2629 I915_WRITE(reg
, temp
);
2634 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2635 I915_READ(FDI_RX_IIR(pipe
)));
2637 /* enable CPU FDI TX and PCH FDI RX */
2638 reg
= FDI_TX_CTL(pipe
);
2639 temp
= I915_READ(reg
);
2641 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2642 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2643 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2644 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2645 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2646 temp
|= FDI_COMPOSITE_SYNC
;
2647 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2649 I915_WRITE(FDI_RX_MISC(pipe
),
2650 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
2652 reg
= FDI_RX_CTL(pipe
);
2653 temp
= I915_READ(reg
);
2654 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2655 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2656 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2657 temp
|= FDI_COMPOSITE_SYNC
;
2658 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2663 if (HAS_PCH_CPT(dev
))
2664 cpt_phase_pointer_enable(dev
, pipe
);
2666 for (i
= 0; i
< 4; i
++) {
2667 reg
= FDI_TX_CTL(pipe
);
2668 temp
= I915_READ(reg
);
2669 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2670 temp
|= snb_b_fdi_train_param
[i
];
2671 I915_WRITE(reg
, temp
);
2676 reg
= FDI_RX_IIR(pipe
);
2677 temp
= I915_READ(reg
);
2678 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2680 if (temp
& FDI_RX_BIT_LOCK
||
2681 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2682 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2683 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i
);
2688 DRM_ERROR("FDI train 1 fail!\n");
2691 reg
= FDI_TX_CTL(pipe
);
2692 temp
= I915_READ(reg
);
2693 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2694 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2695 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2696 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2697 I915_WRITE(reg
, temp
);
2699 reg
= FDI_RX_CTL(pipe
);
2700 temp
= I915_READ(reg
);
2701 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2702 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2703 I915_WRITE(reg
, temp
);
2708 for (i
= 0; i
< 4; i
++) {
2709 reg
= FDI_TX_CTL(pipe
);
2710 temp
= I915_READ(reg
);
2711 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2712 temp
|= snb_b_fdi_train_param
[i
];
2713 I915_WRITE(reg
, temp
);
2718 reg
= FDI_RX_IIR(pipe
);
2719 temp
= I915_READ(reg
);
2720 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2722 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2723 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2724 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i
);
2729 DRM_ERROR("FDI train 2 fail!\n");
2731 DRM_DEBUG_KMS("FDI train done.\n");
2734 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
2736 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2738 int pipe
= intel_crtc
->pipe
;
2742 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2743 reg
= FDI_RX_CTL(pipe
);
2744 temp
= I915_READ(reg
);
2745 temp
&= ~((0x7 << 19) | (0x7 << 16));
2746 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2747 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2748 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2753 /* Switch from Rawclk to PCDclk */
2754 temp
= I915_READ(reg
);
2755 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2760 /* On Haswell, the PLL configuration for ports and pipes is handled
2761 * separately, as part of DDI setup */
2762 if (!IS_HASWELL(dev
)) {
2763 /* Enable CPU FDI TX PLL, always on for Ironlake */
2764 reg
= FDI_TX_CTL(pipe
);
2765 temp
= I915_READ(reg
);
2766 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2767 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2775 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
2777 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2779 int pipe
= intel_crtc
->pipe
;
2782 /* Switch from PCDclk to Rawclk */
2783 reg
= FDI_RX_CTL(pipe
);
2784 temp
= I915_READ(reg
);
2785 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
2787 /* Disable CPU FDI TX PLL */
2788 reg
= FDI_TX_CTL(pipe
);
2789 temp
= I915_READ(reg
);
2790 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2795 reg
= FDI_RX_CTL(pipe
);
2796 temp
= I915_READ(reg
);
2797 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
2799 /* Wait for the clocks to turn off. */
2804 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2806 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2807 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2809 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2810 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2811 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2812 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2813 POSTING_READ(SOUTH_CHICKEN1
);
2815 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2817 struct drm_device
*dev
= crtc
->dev
;
2818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2819 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2820 int pipe
= intel_crtc
->pipe
;
2823 /* disable CPU FDI tx and PCH FDI rx */
2824 reg
= FDI_TX_CTL(pipe
);
2825 temp
= I915_READ(reg
);
2826 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2829 reg
= FDI_RX_CTL(pipe
);
2830 temp
= I915_READ(reg
);
2831 temp
&= ~(0x7 << 16);
2832 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2833 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2838 /* Ironlake workaround, disable clock pointer after downing FDI */
2839 if (HAS_PCH_IBX(dev
)) {
2840 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2841 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2842 I915_READ(FDI_RX_CHICKEN(pipe
) &
2843 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2844 } else if (HAS_PCH_CPT(dev
)) {
2845 cpt_phase_pointer_disable(dev
, pipe
);
2848 /* still set train pattern 1 */
2849 reg
= FDI_TX_CTL(pipe
);
2850 temp
= I915_READ(reg
);
2851 temp
&= ~FDI_LINK_TRAIN_NONE
;
2852 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2853 I915_WRITE(reg
, temp
);
2855 reg
= FDI_RX_CTL(pipe
);
2856 temp
= I915_READ(reg
);
2857 if (HAS_PCH_CPT(dev
)) {
2858 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2859 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2861 temp
&= ~FDI_LINK_TRAIN_NONE
;
2862 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp
&= ~(0x07 << 16);
2866 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2867 I915_WRITE(reg
, temp
);
2873 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2875 struct drm_device
*dev
= crtc
->dev
;
2876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2877 unsigned long flags
;
2880 if (atomic_read(&dev_priv
->mm
.wedged
))
2883 spin_lock_irqsave(&dev
->event_lock
, flags
);
2884 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2885 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2890 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2892 struct drm_device
*dev
= crtc
->dev
;
2893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2895 if (crtc
->fb
== NULL
)
2898 wait_event(dev_priv
->pending_flip_queue
,
2899 !intel_crtc_has_pending_flip(crtc
));
2901 mutex_lock(&dev
->struct_mutex
);
2902 intel_finish_fb(crtc
->fb
);
2903 mutex_unlock(&dev
->struct_mutex
);
2906 static bool ironlake_crtc_driving_pch(struct drm_crtc
*crtc
)
2908 struct drm_device
*dev
= crtc
->dev
;
2909 struct intel_encoder
*intel_encoder
;
2912 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2913 * must be driven by its own crtc; no sharing is possible.
2915 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
2916 switch (intel_encoder
->type
) {
2917 case INTEL_OUTPUT_EDP
:
2918 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
2927 static bool haswell_crtc_driving_pch(struct drm_crtc
*crtc
)
2929 return intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
);
2932 /* Program iCLKIP clock to the desired frequency */
2933 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2935 struct drm_device
*dev
= crtc
->dev
;
2936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2937 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2940 /* It is necessary to ungate the pixclk gate prior to programming
2941 * the divisors, and gate it back when it is done.
2943 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2945 /* Disable SSCCTL */
2946 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2947 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
2948 SBI_SSCCTL_DISABLE
);
2950 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2951 if (crtc
->mode
.clock
== 20000) {
2956 /* The iCLK virtual clock root frequency is in MHz,
2957 * but the crtc->mode.clock in in KHz. To get the divisors,
2958 * it is necessary to divide one by another, so we
2959 * convert the virtual clock precision to KHz here for higher
2962 u32 iclk_virtual_root_freq
= 172800 * 1000;
2963 u32 iclk_pi_range
= 64;
2964 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2966 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2967 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2968 pi_value
= desired_divisor
% iclk_pi_range
;
2971 divsel
= msb_divisor_value
- 2;
2972 phaseinc
= pi_value
;
2975 /* This should not happen with any sane values */
2976 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2977 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2978 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2979 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2981 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2988 /* Program SSCDIVINTPHASE6 */
2989 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
2990 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2991 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2992 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2993 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2994 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2995 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2997 intel_sbi_write(dev_priv
,
2998 SBI_SSCDIVINTPHASE6
,
3001 /* Program SSCAUXDIV */
3002 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
3003 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3004 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3005 intel_sbi_write(dev_priv
,
3010 /* Enable modulator and associated divider */
3011 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
3012 temp
&= ~SBI_SSCCTL_DISABLE
;
3013 intel_sbi_write(dev_priv
,
3017 /* Wait for initialization time */
3020 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3024 * Enable PCH resources required for PCH ports:
3026 * - FDI training & RX/TX
3027 * - update transcoder timings
3028 * - DP transcoding bits
3031 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3033 struct drm_device
*dev
= crtc
->dev
;
3034 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3035 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3036 int pipe
= intel_crtc
->pipe
;
3039 assert_transcoder_disabled(dev_priv
, pipe
);
3041 /* Write the TU size bits before fdi link training, so that error
3042 * detection works. */
3043 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3044 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3046 /* For PCH output, training FDI link */
3047 dev_priv
->display
.fdi_link_train(crtc
);
3049 /* XXX: pch pll's can be enabled any time before we enable the PCH
3050 * transcoder, and we actually should do this to not upset any PCH
3051 * transcoder that already use the clock when we share it.
3053 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3054 * unconditionally resets the pll - we need that to have the right LVDS
3055 * enable sequence. */
3056 intel_enable_pch_pll(intel_crtc
);
3058 if (HAS_PCH_LPT(dev
)) {
3059 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3060 lpt_program_iclkip(crtc
);
3061 } else if (HAS_PCH_CPT(dev
)) {
3064 temp
= I915_READ(PCH_DPLL_SEL
);
3068 temp
|= TRANSA_DPLL_ENABLE
;
3069 sel
= TRANSA_DPLLB_SEL
;
3072 temp
|= TRANSB_DPLL_ENABLE
;
3073 sel
= TRANSB_DPLLB_SEL
;
3076 temp
|= TRANSC_DPLL_ENABLE
;
3077 sel
= TRANSC_DPLLB_SEL
;
3080 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
3084 I915_WRITE(PCH_DPLL_SEL
, temp
);
3087 /* set transcoder timing, panel must allow it */
3088 assert_panel_unlocked(dev_priv
, pipe
);
3089 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
3090 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
3091 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
3093 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
3094 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
3095 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
3096 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3098 if (!IS_HASWELL(dev
))
3099 intel_fdi_normal_train(crtc
);
3101 /* For PCH DP, enable TRANS_DP_CTL */
3102 if (HAS_PCH_CPT(dev
) &&
3103 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3104 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3105 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3106 reg
= TRANS_DP_CTL(pipe
);
3107 temp
= I915_READ(reg
);
3108 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3109 TRANS_DP_SYNC_MASK
|
3111 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3112 TRANS_DP_ENH_FRAMING
);
3113 temp
|= bpc
<< 9; /* same format but at 11:9 */
3115 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3116 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3117 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3118 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3120 switch (intel_trans_dp_port_sel(crtc
)) {
3122 temp
|= TRANS_DP_PORT_SEL_B
;
3125 temp
|= TRANS_DP_PORT_SEL_C
;
3128 temp
|= TRANS_DP_PORT_SEL_D
;
3134 I915_WRITE(reg
, temp
);
3137 intel_enable_transcoder(dev_priv
, pipe
);
3140 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3142 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3147 if (pll
->refcount
== 0) {
3148 WARN(1, "bad PCH PLL refcount\n");
3153 intel_crtc
->pch_pll
= NULL
;
3156 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3158 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3159 struct intel_pch_pll
*pll
;
3162 pll
= intel_crtc
->pch_pll
;
3164 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3165 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3169 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3171 i
= intel_crtc
->pipe
;
3172 pll
= &dev_priv
->pch_plls
[i
];
3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3175 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3180 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3181 pll
= &dev_priv
->pch_plls
[i
];
3183 /* Only want to check enabled timings first */
3184 if (pll
->refcount
== 0)
3187 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3188 fp
== I915_READ(pll
->fp0_reg
)) {
3189 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3190 intel_crtc
->base
.base
.id
,
3191 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3197 /* Ok no matching timings, maybe there's a free one? */
3198 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3199 pll
= &dev_priv
->pch_plls
[i
];
3200 if (pll
->refcount
== 0) {
3201 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3202 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3210 intel_crtc
->pch_pll
= pll
;
3212 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3213 prepare
: /* separate function? */
3214 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3216 /* Wait for the clocks to stabilize before rewriting the regs */
3217 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3218 POSTING_READ(pll
->pll_reg
);
3221 I915_WRITE(pll
->fp0_reg
, fp
);
3222 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3227 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3230 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3233 temp
= I915_READ(dslreg
);
3235 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3236 /* Without this, mode sets may fail silently on FDI */
3237 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3239 I915_WRITE(tc2reg
, 0);
3240 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3241 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3245 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3247 struct drm_device
*dev
= crtc
->dev
;
3248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3249 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3250 struct intel_encoder
*encoder
;
3251 int pipe
= intel_crtc
->pipe
;
3252 int plane
= intel_crtc
->plane
;
3256 WARN_ON(!crtc
->enabled
);
3258 if (intel_crtc
->active
)
3261 intel_crtc
->active
= true;
3262 intel_update_watermarks(dev
);
3264 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3265 temp
= I915_READ(PCH_LVDS
);
3266 if ((temp
& LVDS_PORT_EN
) == 0)
3267 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3270 is_pch_port
= ironlake_crtc_driving_pch(crtc
);
3273 /* Note: FDI PLL enabling _must_ be done before we enable the
3274 * cpu pipes, hence this is separate from all the other fdi/pch
3276 ironlake_fdi_pll_enable(intel_crtc
);
3278 assert_fdi_tx_disabled(dev_priv
, pipe
);
3279 assert_fdi_rx_disabled(dev_priv
, pipe
);
3282 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3283 if (encoder
->pre_enable
)
3284 encoder
->pre_enable(encoder
);
3286 /* Enable panel fitting for LVDS */
3287 if (dev_priv
->pch_pf_size
&&
3288 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3289 /* Force use of hard-coded filter coefficients
3290 * as some pre-programmed values are broken,
3293 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3294 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3295 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3299 * On ILK+ LUT must be loaded before the pipe is running but with
3302 intel_crtc_load_lut(crtc
);
3304 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3305 intel_enable_plane(dev_priv
, plane
, pipe
);
3308 ironlake_pch_enable(crtc
);
3310 mutex_lock(&dev
->struct_mutex
);
3311 intel_update_fbc(dev
);
3312 mutex_unlock(&dev
->struct_mutex
);
3314 intel_crtc_update_cursor(crtc
, true);
3316 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3317 encoder
->enable(encoder
);
3319 if (HAS_PCH_CPT(dev
))
3320 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3323 * There seems to be a race in PCH platform hw (at least on some
3324 * outputs) where an enabled pipe still completes any pageflip right
3325 * away (as if the pipe is off) instead of waiting for vblank. As soon
3326 * as the first vblank happend, everything works as expected. Hence just
3327 * wait for one vblank before returning to avoid strange things
3330 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3333 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
3335 struct drm_device
*dev
= crtc
->dev
;
3336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3337 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3338 struct intel_encoder
*encoder
;
3339 int pipe
= intel_crtc
->pipe
;
3340 int plane
= intel_crtc
->plane
;
3343 WARN_ON(!crtc
->enabled
);
3345 if (intel_crtc
->active
)
3348 intel_crtc
->active
= true;
3349 intel_update_watermarks(dev
);
3351 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3354 ironlake_fdi_pll_enable(intel_crtc
);
3356 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3357 if (encoder
->pre_enable
)
3358 encoder
->pre_enable(encoder
);
3360 intel_ddi_enable_pipe_clock(intel_crtc
);
3362 /* Enable panel fitting for eDP */
3363 if (dev_priv
->pch_pf_size
&& HAS_eDP
) {
3364 /* Force use of hard-coded filter coefficients
3365 * as some pre-programmed values are broken,
3368 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3369 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3370 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3374 * On ILK+ LUT must be loaded before the pipe is running but with
3377 intel_crtc_load_lut(crtc
);
3379 intel_ddi_set_pipe_settings(crtc
);
3380 intel_ddi_enable_pipe_func(crtc
);
3382 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3383 intel_enable_plane(dev_priv
, plane
, pipe
);
3386 ironlake_pch_enable(crtc
);
3388 mutex_lock(&dev
->struct_mutex
);
3389 intel_update_fbc(dev
);
3390 mutex_unlock(&dev
->struct_mutex
);
3392 intel_crtc_update_cursor(crtc
, true);
3394 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3395 encoder
->enable(encoder
);
3398 * There seems to be a race in PCH platform hw (at least on some
3399 * outputs) where an enabled pipe still completes any pageflip right
3400 * away (as if the pipe is off) instead of waiting for vblank. As soon
3401 * as the first vblank happend, everything works as expected. Hence just
3402 * wait for one vblank before returning to avoid strange things
3405 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
3408 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3410 struct drm_device
*dev
= crtc
->dev
;
3411 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3412 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3413 struct intel_encoder
*encoder
;
3414 int pipe
= intel_crtc
->pipe
;
3415 int plane
= intel_crtc
->plane
;
3419 if (!intel_crtc
->active
)
3422 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3423 encoder
->disable(encoder
);
3425 intel_crtc_wait_for_pending_flips(crtc
);
3426 drm_vblank_off(dev
, pipe
);
3427 intel_crtc_update_cursor(crtc
, false);
3429 intel_disable_plane(dev_priv
, plane
, pipe
);
3431 if (dev_priv
->cfb_plane
== plane
)
3432 intel_disable_fbc(dev
);
3434 intel_disable_pipe(dev_priv
, pipe
);
3437 I915_WRITE(PF_CTL(pipe
), 0);
3438 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3440 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3441 if (encoder
->post_disable
)
3442 encoder
->post_disable(encoder
);
3444 ironlake_fdi_disable(crtc
);
3446 intel_disable_transcoder(dev_priv
, pipe
);
3448 if (HAS_PCH_CPT(dev
)) {
3449 /* disable TRANS_DP_CTL */
3450 reg
= TRANS_DP_CTL(pipe
);
3451 temp
= I915_READ(reg
);
3452 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3453 temp
|= TRANS_DP_PORT_SEL_NONE
;
3454 I915_WRITE(reg
, temp
);
3456 /* disable DPLL_SEL */
3457 temp
= I915_READ(PCH_DPLL_SEL
);
3460 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3463 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3466 /* C shares PLL A or B */
3467 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3472 I915_WRITE(PCH_DPLL_SEL
, temp
);
3475 /* disable PCH DPLL */
3476 intel_disable_pch_pll(intel_crtc
);
3478 ironlake_fdi_pll_disable(intel_crtc
);
3480 intel_crtc
->active
= false;
3481 intel_update_watermarks(dev
);
3483 mutex_lock(&dev
->struct_mutex
);
3484 intel_update_fbc(dev
);
3485 mutex_unlock(&dev
->struct_mutex
);
3488 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
3490 struct drm_device
*dev
= crtc
->dev
;
3491 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3492 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3493 struct intel_encoder
*encoder
;
3494 int pipe
= intel_crtc
->pipe
;
3495 int plane
= intel_crtc
->plane
;
3496 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
3499 if (!intel_crtc
->active
)
3502 is_pch_port
= haswell_crtc_driving_pch(crtc
);
3504 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3505 encoder
->disable(encoder
);
3507 intel_crtc_wait_for_pending_flips(crtc
);
3508 drm_vblank_off(dev
, pipe
);
3509 intel_crtc_update_cursor(crtc
, false);
3511 intel_disable_plane(dev_priv
, plane
, pipe
);
3513 if (dev_priv
->cfb_plane
== plane
)
3514 intel_disable_fbc(dev
);
3516 intel_disable_pipe(dev_priv
, pipe
);
3518 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
3521 I915_WRITE(PF_CTL(pipe
), 0);
3522 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3524 intel_ddi_disable_pipe_clock(intel_crtc
);
3526 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3527 if (encoder
->post_disable
)
3528 encoder
->post_disable(encoder
);
3531 ironlake_fdi_disable(crtc
);
3532 intel_disable_transcoder(dev_priv
, pipe
);
3533 intel_disable_pch_pll(intel_crtc
);
3534 ironlake_fdi_pll_disable(intel_crtc
);
3537 intel_crtc
->active
= false;
3538 intel_update_watermarks(dev
);
3540 mutex_lock(&dev
->struct_mutex
);
3541 intel_update_fbc(dev
);
3542 mutex_unlock(&dev
->struct_mutex
);
3545 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3547 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3548 intel_put_pch_pll(intel_crtc
);
3551 static void haswell_crtc_off(struct drm_crtc
*crtc
)
3553 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3555 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3556 * start using it. */
3557 intel_crtc
->cpu_transcoder
= intel_crtc
->pipe
;
3559 intel_ddi_put_crtc_pll(crtc
);
3562 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3564 if (!enable
&& intel_crtc
->overlay
) {
3565 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3568 mutex_lock(&dev
->struct_mutex
);
3569 dev_priv
->mm
.interruptible
= false;
3570 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3571 dev_priv
->mm
.interruptible
= true;
3572 mutex_unlock(&dev
->struct_mutex
);
3575 /* Let userspace switch the overlay on again. In most cases userspace
3576 * has to recompute where to put it anyway.
3580 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3582 struct drm_device
*dev
= crtc
->dev
;
3583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3584 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3585 struct intel_encoder
*encoder
;
3586 int pipe
= intel_crtc
->pipe
;
3587 int plane
= intel_crtc
->plane
;
3589 WARN_ON(!crtc
->enabled
);
3591 if (intel_crtc
->active
)
3594 intel_crtc
->active
= true;
3595 intel_update_watermarks(dev
);
3597 intel_enable_pll(dev_priv
, pipe
);
3598 intel_enable_pipe(dev_priv
, pipe
, false);
3599 intel_enable_plane(dev_priv
, plane
, pipe
);
3601 intel_crtc_load_lut(crtc
);
3602 intel_update_fbc(dev
);
3604 /* Give the overlay scaler a chance to enable if it's on this pipe */
3605 intel_crtc_dpms_overlay(intel_crtc
, true);
3606 intel_crtc_update_cursor(crtc
, true);
3608 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3609 encoder
->enable(encoder
);
3612 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3614 struct drm_device
*dev
= crtc
->dev
;
3615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3616 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3617 struct intel_encoder
*encoder
;
3618 int pipe
= intel_crtc
->pipe
;
3619 int plane
= intel_crtc
->plane
;
3622 if (!intel_crtc
->active
)
3625 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
3626 encoder
->disable(encoder
);
3628 /* Give the overlay scaler a chance to disable if it's on this pipe */
3629 intel_crtc_wait_for_pending_flips(crtc
);
3630 drm_vblank_off(dev
, pipe
);
3631 intel_crtc_dpms_overlay(intel_crtc
, false);
3632 intel_crtc_update_cursor(crtc
, false);
3634 if (dev_priv
->cfb_plane
== plane
)
3635 intel_disable_fbc(dev
);
3637 intel_disable_plane(dev_priv
, plane
, pipe
);
3638 intel_disable_pipe(dev_priv
, pipe
);
3639 intel_disable_pll(dev_priv
, pipe
);
3641 intel_crtc
->active
= false;
3642 intel_update_fbc(dev
);
3643 intel_update_watermarks(dev
);
3646 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3650 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
3653 struct drm_device
*dev
= crtc
->dev
;
3654 struct drm_i915_master_private
*master_priv
;
3655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3656 int pipe
= intel_crtc
->pipe
;
3658 if (!dev
->primary
->master
)
3661 master_priv
= dev
->primary
->master
->driver_priv
;
3662 if (!master_priv
->sarea_priv
)
3667 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3668 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3671 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3672 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3675 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3681 * Sets the power management mode of the pipe and plane.
3683 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
3685 struct drm_device
*dev
= crtc
->dev
;
3686 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3687 struct intel_encoder
*intel_encoder
;
3688 bool enable
= false;
3690 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
3691 enable
|= intel_encoder
->connectors_active
;
3694 dev_priv
->display
.crtc_enable(crtc
);
3696 dev_priv
->display
.crtc_disable(crtc
);
3698 intel_crtc_update_sarea(crtc
, enable
);
3701 static void intel_crtc_noop(struct drm_crtc
*crtc
)
3705 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3707 struct drm_device
*dev
= crtc
->dev
;
3708 struct drm_connector
*connector
;
3709 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3711 /* crtc should still be enabled when we disable it. */
3712 WARN_ON(!crtc
->enabled
);
3714 dev_priv
->display
.crtc_disable(crtc
);
3715 intel_crtc_update_sarea(crtc
, false);
3716 dev_priv
->display
.off(crtc
);
3718 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3719 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3722 mutex_lock(&dev
->struct_mutex
);
3723 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3724 mutex_unlock(&dev
->struct_mutex
);
3728 /* Update computed state. */
3729 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
3730 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
3733 if (connector
->encoder
->crtc
!= crtc
)
3736 connector
->dpms
= DRM_MODE_DPMS_OFF
;
3737 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
3741 void intel_modeset_disable(struct drm_device
*dev
)
3743 struct drm_crtc
*crtc
;
3745 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3747 intel_crtc_disable(crtc
);
3751 void intel_encoder_noop(struct drm_encoder
*encoder
)
3755 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3757 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3759 drm_encoder_cleanup(encoder
);
3760 kfree(intel_encoder
);
3763 /* Simple dpms helper for encodres with just one connector, no cloning and only
3764 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3765 * state of the entire output pipe. */
3766 void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
3768 if (mode
== DRM_MODE_DPMS_ON
) {
3769 encoder
->connectors_active
= true;
3771 intel_crtc_update_dpms(encoder
->base
.crtc
);
3773 encoder
->connectors_active
= false;
3775 intel_crtc_update_dpms(encoder
->base
.crtc
);
3779 /* Cross check the actual hw state with our own modeset state tracking (and it's
3780 * internal consistency). */
3781 static void intel_connector_check_state(struct intel_connector
*connector
)
3783 if (connector
->get_hw_state(connector
)) {
3784 struct intel_encoder
*encoder
= connector
->encoder
;
3785 struct drm_crtc
*crtc
;
3786 bool encoder_enabled
;
3789 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3790 connector
->base
.base
.id
,
3791 drm_get_connector_name(&connector
->base
));
3793 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
3794 "wrong connector dpms state\n");
3795 WARN(connector
->base
.encoder
!= &encoder
->base
,
3796 "active connector not linked to encoder\n");
3797 WARN(!encoder
->connectors_active
,
3798 "encoder->connectors_active not set\n");
3800 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
3801 WARN(!encoder_enabled
, "encoder not enabled\n");
3802 if (WARN_ON(!encoder
->base
.crtc
))
3805 crtc
= encoder
->base
.crtc
;
3807 WARN(!crtc
->enabled
, "crtc not enabled\n");
3808 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
3809 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
3810 "encoder active on the wrong pipe\n");
3814 /* Even simpler default implementation, if there's really no special case to
3816 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
3818 struct intel_encoder
*encoder
= intel_attached_encoder(connector
);
3820 /* All the simple cases only support two dpms states. */
3821 if (mode
!= DRM_MODE_DPMS_ON
)
3822 mode
= DRM_MODE_DPMS_OFF
;
3824 if (mode
== connector
->dpms
)
3827 connector
->dpms
= mode
;
3829 /* Only need to change hw state when actually enabled */
3830 if (encoder
->base
.crtc
)
3831 intel_encoder_dpms(encoder
, mode
);
3833 WARN_ON(encoder
->connectors_active
!= false);
3835 intel_modeset_check_state(connector
->dev
);
3838 /* Simple connector->get_hw_state implementation for encoders that support only
3839 * one connector and no cloning and hence the encoder state determines the state
3840 * of the connector. */
3841 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
3844 struct intel_encoder
*encoder
= connector
->encoder
;
3846 return encoder
->get_hw_state(encoder
, &pipe
);
3849 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3850 const struct drm_display_mode
*mode
,
3851 struct drm_display_mode
*adjusted_mode
)
3853 struct drm_device
*dev
= crtc
->dev
;
3855 if (HAS_PCH_SPLIT(dev
)) {
3856 /* FDI link clock is fixed at 2.7G */
3857 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3861 /* All interlaced capable intel hw wants timings in frames. Note though
3862 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3863 * timings, so we need to be careful not to clobber these.*/
3864 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3865 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3867 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3868 * with a hsync front porch of 0.
3870 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
3871 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
3877 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3879 return 400000; /* FIXME */
3882 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3887 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3892 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3897 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3901 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3903 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3906 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3907 case GC_DISPLAY_CLOCK_333_MHZ
:
3910 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3916 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3921 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3924 /* Assume that the hardware is in the high speed state. This
3925 * should be the default.
3927 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3928 case GC_CLOCK_133_200
:
3929 case GC_CLOCK_100_200
:
3931 case GC_CLOCK_166_250
:
3933 case GC_CLOCK_100_133
:
3937 /* Shouldn't happen */
3941 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3955 fdi_reduce_ratio(u32
*num
, u32
*den
)
3957 while (*num
> 0xffffff || *den
> 0xffffff) {
3964 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3965 int link_clock
, struct fdi_m_n
*m_n
)
3967 m_n
->tu
= 64; /* default size */
3969 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3970 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3971 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3972 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3974 m_n
->link_m
= pixel_clock
;
3975 m_n
->link_n
= link_clock
;
3976 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3979 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3981 if (i915_panel_use_ssc
>= 0)
3982 return i915_panel_use_ssc
!= 0;
3983 return dev_priv
->lvds_use_ssc
3984 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3988 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3989 * @crtc: CRTC structure
3990 * @mode: requested mode
3992 * A pipe may be connected to one or more outputs. Based on the depth of the
3993 * attached framebuffer, choose a good color depth to use on the pipe.
3995 * If possible, match the pipe depth to the fb depth. In some cases, this
3996 * isn't ideal, because the connected output supports a lesser or restricted
3997 * set of depths. Resolve that here:
3998 * LVDS typically supports only 6bpc, so clamp down in that case
3999 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4000 * Displays may support a restricted set as well, check EDID and clamp as
4002 * DP may want to dither down to 6bpc to fit larger modes
4005 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4006 * true if they don't match).
4008 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
4009 struct drm_framebuffer
*fb
,
4010 unsigned int *pipe_bpp
,
4011 struct drm_display_mode
*mode
)
4013 struct drm_device
*dev
= crtc
->dev
;
4014 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4015 struct drm_connector
*connector
;
4016 struct intel_encoder
*intel_encoder
;
4017 unsigned int display_bpc
= UINT_MAX
, bpc
;
4019 /* Walk the encoders & connectors on this crtc, get min bpc */
4020 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4022 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
4023 unsigned int lvds_bpc
;
4025 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
4031 if (lvds_bpc
< display_bpc
) {
4032 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
4033 display_bpc
= lvds_bpc
;
4038 /* Not one of the known troublemakers, check the EDID */
4039 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
4041 if (connector
->encoder
!= &intel_encoder
->base
)
4044 /* Don't use an invalid EDID bpc value */
4045 if (connector
->display_info
.bpc
&&
4046 connector
->display_info
.bpc
< display_bpc
) {
4047 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
4048 display_bpc
= connector
->display_info
.bpc
;
4053 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4054 * through, clamp it down. (Note: >12bpc will be caught below.)
4056 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
4057 if (display_bpc
> 8 && display_bpc
< 12) {
4058 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4061 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4067 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4068 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4073 * We could just drive the pipe at the highest bpc all the time and
4074 * enable dithering as needed, but that costs bandwidth. So choose
4075 * the minimum value that expresses the full color range of the fb but
4076 * also stays within the max display bpc discovered above.
4079 switch (fb
->depth
) {
4081 bpc
= 8; /* since we go through a colormap */
4085 bpc
= 6; /* min is 18bpp */
4097 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4098 bpc
= min((unsigned int)8, display_bpc
);
4102 display_bpc
= min(display_bpc
, bpc
);
4104 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4107 *pipe_bpp
= display_bpc
* 3;
4109 return display_bpc
!= bpc
;
4112 static int vlv_get_refclk(struct drm_crtc
*crtc
)
4114 struct drm_device
*dev
= crtc
->dev
;
4115 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4116 int refclk
= 27000; /* for DP & HDMI */
4118 return 100000; /* only one validated so far */
4120 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
4122 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4123 if (intel_panel_use_ssc(dev_priv
))
4127 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4134 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
4136 struct drm_device
*dev
= crtc
->dev
;
4137 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4140 if (IS_VALLEYVIEW(dev
)) {
4141 refclk
= vlv_get_refclk(crtc
);
4142 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4143 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4144 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
4145 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4147 } else if (!IS_GEN2(dev
)) {
4156 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
4157 intel_clock_t
*clock
)
4159 /* SDVO TV has fixed PLL values depend on its clock range,
4160 this mirrors vbios setting. */
4161 if (adjusted_mode
->clock
>= 100000
4162 && adjusted_mode
->clock
< 140500) {
4168 } else if (adjusted_mode
->clock
>= 140500
4169 && adjusted_mode
->clock
<= 200000) {
4178 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
4179 intel_clock_t
*clock
,
4180 intel_clock_t
*reduced_clock
)
4182 struct drm_device
*dev
= crtc
->dev
;
4183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4184 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4185 int pipe
= intel_crtc
->pipe
;
4188 if (IS_PINEVIEW(dev
)) {
4189 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
4191 fp2
= (1 << reduced_clock
->n
) << 16 |
4192 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
4194 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
4196 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
4200 I915_WRITE(FP0(pipe
), fp
);
4202 intel_crtc
->lowfreq_avail
= false;
4203 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4204 reduced_clock
&& i915_powersave
) {
4205 I915_WRITE(FP1(pipe
), fp2
);
4206 intel_crtc
->lowfreq_avail
= true;
4208 I915_WRITE(FP1(pipe
), fp
);
4212 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
4213 struct drm_display_mode
*adjusted_mode
)
4215 struct drm_device
*dev
= crtc
->dev
;
4216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4217 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4218 int pipe
= intel_crtc
->pipe
;
4221 temp
= I915_READ(LVDS
);
4222 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4224 temp
|= LVDS_PIPEB_SELECT
;
4226 temp
&= ~LVDS_PIPEB_SELECT
;
4228 /* set the corresponsding LVDS_BORDER bit */
4229 temp
|= dev_priv
->lvds_border_bits
;
4230 /* Set the B0-B3 data pairs corresponding to whether we're going to
4231 * set the DPLLs for dual-channel mode or not.
4234 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4236 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4238 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4239 * appropriately here, but we need to look more thoroughly into how
4240 * panels behave in the two modes.
4242 /* set the dithering flag on LVDS as needed */
4243 if (INTEL_INFO(dev
)->gen
>= 4) {
4244 if (dev_priv
->lvds_dither
)
4245 temp
|= LVDS_ENABLE_DITHER
;
4247 temp
&= ~LVDS_ENABLE_DITHER
;
4249 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4250 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4251 temp
|= LVDS_HSYNC_POLARITY
;
4252 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4253 temp
|= LVDS_VSYNC_POLARITY
;
4254 I915_WRITE(LVDS
, temp
);
4257 static void vlv_update_pll(struct drm_crtc
*crtc
,
4258 struct drm_display_mode
*mode
,
4259 struct drm_display_mode
*adjusted_mode
,
4260 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4263 struct drm_device
*dev
= crtc
->dev
;
4264 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4265 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4266 int pipe
= intel_crtc
->pipe
;
4267 u32 dpll
, mdiv
, pdiv
;
4268 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
4272 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4273 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4275 dpll
= DPLL_VGA_MODE_DIS
;
4276 dpll
|= DPLL_EXT_BUFFER_ENABLE_VLV
;
4277 dpll
|= DPLL_REFA_CLK_ENABLE_VLV
;
4278 dpll
|= DPLL_INTEGRATED_CLOCK_VLV
;
4280 I915_WRITE(DPLL(pipe
), dpll
);
4281 POSTING_READ(DPLL(pipe
));
4290 * In Valleyview PLL and program lane counter registers are exposed
4291 * through DPIO interface
4293 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
4294 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
4295 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
4296 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
4297 mdiv
|= (1 << DPIO_K_SHIFT
);
4298 mdiv
|= DPIO_ENABLE_CALIBRATION
;
4299 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
4301 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4303 pdiv
= (1 << DPIO_REFSEL_OVERRIDE
) | (5 << DPIO_PLL_MODESEL_SHIFT
) |
4304 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4305 (7 << DPIO_PLL_REFCLK_SEL_SHIFT
) | (8 << DPIO_DRIVER_CTL_SHIFT
) |
4306 (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4307 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4309 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x005f003b);
4311 dpll
|= DPLL_VCO_ENABLE
;
4312 I915_WRITE(DPLL(pipe
), dpll
);
4313 POSTING_READ(DPLL(pipe
));
4314 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4315 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4317 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x620);
4319 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4320 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4322 I915_WRITE(DPLL(pipe
), dpll
);
4324 /* Wait for the clocks to stabilize. */
4325 POSTING_READ(DPLL(pipe
));
4330 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4332 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4336 I915_WRITE(DPLL_MD(pipe
), temp
);
4337 POSTING_READ(DPLL_MD(pipe
));
4339 /* Now program lane control registers */
4340 if(intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)
4341 || intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
4346 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL1
, temp
);
4348 if(intel_pipe_has_type(crtc
,INTEL_OUTPUT_EDP
))
4353 intel_dpio_write(dev_priv
, DPIO_DATA_CHANNEL2
, temp
);
4357 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4358 struct drm_display_mode
*mode
,
4359 struct drm_display_mode
*adjusted_mode
,
4360 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4363 struct drm_device
*dev
= crtc
->dev
;
4364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4365 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4366 int pipe
= intel_crtc
->pipe
;
4370 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4372 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4373 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4375 dpll
= DPLL_VGA_MODE_DIS
;
4377 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4378 dpll
|= DPLLB_MODE_LVDS
;
4380 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4382 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4383 if (pixel_multiplier
> 1) {
4384 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4385 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4387 dpll
|= DPLL_DVO_HIGH_SPEED
;
4389 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4390 dpll
|= DPLL_DVO_HIGH_SPEED
;
4392 /* compute bitmask from p1 value */
4393 if (IS_PINEVIEW(dev
))
4394 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4396 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4397 if (IS_G4X(dev
) && reduced_clock
)
4398 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4400 switch (clock
->p2
) {
4402 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4405 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4408 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4411 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4414 if (INTEL_INFO(dev
)->gen
>= 4)
4415 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4417 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4418 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4419 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4420 /* XXX: just matching BIOS for now */
4421 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4423 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4424 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4425 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4427 dpll
|= PLL_REF_INPUT_DREFCLK
;
4429 dpll
|= DPLL_VCO_ENABLE
;
4430 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4431 POSTING_READ(DPLL(pipe
));
4434 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4435 * This is an exception to the general rule that mode_set doesn't turn
4438 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4439 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4441 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4442 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4444 I915_WRITE(DPLL(pipe
), dpll
);
4446 /* Wait for the clocks to stabilize. */
4447 POSTING_READ(DPLL(pipe
));
4450 if (INTEL_INFO(dev
)->gen
>= 4) {
4453 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4455 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4459 I915_WRITE(DPLL_MD(pipe
), temp
);
4461 /* The pixel multiplier can only be updated once the
4462 * DPLL is enabled and the clocks are stable.
4464 * So write it again.
4466 I915_WRITE(DPLL(pipe
), dpll
);
4470 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4471 struct drm_display_mode
*adjusted_mode
,
4472 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4475 struct drm_device
*dev
= crtc
->dev
;
4476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4477 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4478 int pipe
= intel_crtc
->pipe
;
4481 i9xx_update_pll_dividers(crtc
, clock
, reduced_clock
);
4483 dpll
= DPLL_VGA_MODE_DIS
;
4485 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4486 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4489 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4491 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4493 dpll
|= PLL_P2_DIVIDE_BY_4
;
4496 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4497 /* XXX: just matching BIOS for now */
4498 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4500 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4501 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4502 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4504 dpll
|= PLL_REF_INPUT_DREFCLK
;
4506 dpll
|= DPLL_VCO_ENABLE
;
4507 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4508 POSTING_READ(DPLL(pipe
));
4511 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4512 * This is an exception to the general rule that mode_set doesn't turn
4515 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4516 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4518 I915_WRITE(DPLL(pipe
), dpll
);
4520 /* Wait for the clocks to stabilize. */
4521 POSTING_READ(DPLL(pipe
));
4524 /* The pixel multiplier can only be updated once the
4525 * DPLL is enabled and the clocks are stable.
4527 * So write it again.
4529 I915_WRITE(DPLL(pipe
), dpll
);
4532 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
,
4533 struct drm_display_mode
*mode
,
4534 struct drm_display_mode
*adjusted_mode
)
4536 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4538 enum pipe pipe
= intel_crtc
->pipe
;
4539 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4540 uint32_t vsyncshift
;
4542 if (!IS_GEN2(dev
) && adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4543 /* the chip adds 2 halflines automatically */
4544 adjusted_mode
->crtc_vtotal
-= 1;
4545 adjusted_mode
->crtc_vblank_end
-= 1;
4546 vsyncshift
= adjusted_mode
->crtc_hsync_start
4547 - adjusted_mode
->crtc_htotal
/ 2;
4552 if (INTEL_INFO(dev
)->gen
> 3)
4553 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
4555 I915_WRITE(HTOTAL(cpu_transcoder
),
4556 (adjusted_mode
->crtc_hdisplay
- 1) |
4557 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4558 I915_WRITE(HBLANK(cpu_transcoder
),
4559 (adjusted_mode
->crtc_hblank_start
- 1) |
4560 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4561 I915_WRITE(HSYNC(cpu_transcoder
),
4562 (adjusted_mode
->crtc_hsync_start
- 1) |
4563 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4565 I915_WRITE(VTOTAL(cpu_transcoder
),
4566 (adjusted_mode
->crtc_vdisplay
- 1) |
4567 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4568 I915_WRITE(VBLANK(cpu_transcoder
),
4569 (adjusted_mode
->crtc_vblank_start
- 1) |
4570 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4571 I915_WRITE(VSYNC(cpu_transcoder
),
4572 (adjusted_mode
->crtc_vsync_start
- 1) |
4573 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4575 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4576 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4577 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4579 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
4580 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
4581 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
4583 /* pipesrc controls the size that is scaled from, which should
4584 * always be the user's requested size.
4586 I915_WRITE(PIPESRC(pipe
),
4587 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4590 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4591 struct drm_display_mode
*mode
,
4592 struct drm_display_mode
*adjusted_mode
,
4594 struct drm_framebuffer
*fb
)
4596 struct drm_device
*dev
= crtc
->dev
;
4597 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4598 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4599 int pipe
= intel_crtc
->pipe
;
4600 int plane
= intel_crtc
->plane
;
4601 int refclk
, num_connectors
= 0;
4602 intel_clock_t clock
, reduced_clock
;
4603 u32 dspcntr
, pipeconf
;
4604 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4605 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4606 struct intel_encoder
*encoder
;
4607 const intel_limit_t
*limit
;
4610 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4611 switch (encoder
->type
) {
4612 case INTEL_OUTPUT_LVDS
:
4615 case INTEL_OUTPUT_SDVO
:
4616 case INTEL_OUTPUT_HDMI
:
4618 if (encoder
->needs_tv_clock
)
4621 case INTEL_OUTPUT_TVOUT
:
4624 case INTEL_OUTPUT_DISPLAYPORT
:
4632 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4635 * Returns a set of divisors for the desired target clock with the given
4636 * refclk, or FALSE. The returned values represent the clock equation:
4637 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4639 limit
= intel_limit(crtc
, refclk
);
4640 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4643 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4647 /* Ensure that the cursor is valid for the new mode before changing... */
4648 intel_crtc_update_cursor(crtc
, true);
4650 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4652 * Ensure we match the reduced clock's P to the target clock.
4653 * If the clocks don't match, we can't switch the display clock
4654 * by using the FP0/FP1. In such case we will disable the LVDS
4655 * downclock feature.
4657 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4658 dev_priv
->lvds_downclock
,
4664 if (is_sdvo
&& is_tv
)
4665 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4668 i8xx_update_pll(crtc
, adjusted_mode
, &clock
,
4669 has_reduced_clock
? &reduced_clock
: NULL
,
4671 else if (IS_VALLEYVIEW(dev
))
4672 vlv_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4673 has_reduced_clock
? &reduced_clock
: NULL
,
4676 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4677 has_reduced_clock
? &reduced_clock
: NULL
,
4680 /* setup pipeconf */
4681 pipeconf
= I915_READ(PIPECONF(pipe
));
4683 /* Set up the display plane register */
4684 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4687 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4689 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4691 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4692 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4695 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4699 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4700 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4702 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4705 /* default to 8bpc */
4706 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4708 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4709 pipeconf
|= PIPECONF_BPP_6
|
4710 PIPECONF_DITHER_EN
|
4711 PIPECONF_DITHER_TYPE_SP
;
4715 if (IS_VALLEYVIEW(dev
) && intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
4716 if (adjusted_mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4717 pipeconf
|= PIPECONF_BPP_6
|
4719 I965_PIPECONF_ACTIVE
;
4723 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4724 drm_mode_debug_printmodeline(mode
);
4726 if (HAS_PIPE_CXSR(dev
)) {
4727 if (intel_crtc
->lowfreq_avail
) {
4728 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4729 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4731 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4732 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4736 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4737 if (!IS_GEN2(dev
) &&
4738 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4739 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4741 pipeconf
|= PIPECONF_PROGRESSIVE
;
4743 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
4745 /* pipesrc and dspsize control the size that is scaled from,
4746 * which should always be the user's requested size.
4748 I915_WRITE(DSPSIZE(plane
),
4749 ((mode
->vdisplay
- 1) << 16) |
4750 (mode
->hdisplay
- 1));
4751 I915_WRITE(DSPPOS(plane
), 0);
4753 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4754 POSTING_READ(PIPECONF(pipe
));
4755 intel_enable_pipe(dev_priv
, pipe
, false);
4757 intel_wait_for_vblank(dev
, pipe
);
4759 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4760 POSTING_READ(DSPCNTR(plane
));
4762 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
4764 intel_update_watermarks(dev
);
4770 * Initialize reference clocks when the driver loads
4772 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4774 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4775 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4776 struct intel_encoder
*encoder
;
4778 bool has_lvds
= false;
4779 bool has_cpu_edp
= false;
4780 bool has_pch_edp
= false;
4781 bool has_panel
= false;
4782 bool has_ck505
= false;
4783 bool can_ssc
= false;
4785 /* We need to take the global config into account */
4786 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4788 switch (encoder
->type
) {
4789 case INTEL_OUTPUT_LVDS
:
4793 case INTEL_OUTPUT_EDP
:
4795 if (intel_encoder_is_pch_edp(&encoder
->base
))
4803 if (HAS_PCH_IBX(dev
)) {
4804 has_ck505
= dev_priv
->display_clock_mode
;
4805 can_ssc
= has_ck505
;
4811 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4812 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4815 /* Ironlake: try to setup display ref clock before DPLL
4816 * enabling. This is only under driver's control after
4817 * PCH B stepping, previous chipset stepping should be
4818 * ignoring this setting.
4820 temp
= I915_READ(PCH_DREF_CONTROL
);
4821 /* Always enable nonspread source */
4822 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4825 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4827 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4830 temp
&= ~DREF_SSC_SOURCE_MASK
;
4831 temp
|= DREF_SSC_SOURCE_ENABLE
;
4833 /* SSC must be turned on before enabling the CPU output */
4834 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4835 DRM_DEBUG_KMS("Using SSC on panel\n");
4836 temp
|= DREF_SSC1_ENABLE
;
4838 temp
&= ~DREF_SSC1_ENABLE
;
4840 /* Get SSC going before enabling the outputs */
4841 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4842 POSTING_READ(PCH_DREF_CONTROL
);
4845 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4847 /* Enable CPU source on CPU attached eDP */
4849 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4850 DRM_DEBUG_KMS("Using SSC on eDP\n");
4851 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4854 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4856 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4858 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4859 POSTING_READ(PCH_DREF_CONTROL
);
4862 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4864 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4866 /* Turn off CPU output */
4867 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4869 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4870 POSTING_READ(PCH_DREF_CONTROL
);
4873 /* Turn off the SSC source */
4874 temp
&= ~DREF_SSC_SOURCE_MASK
;
4875 temp
|= DREF_SSC_SOURCE_DISABLE
;
4878 temp
&= ~ DREF_SSC1_ENABLE
;
4880 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4881 POSTING_READ(PCH_DREF_CONTROL
);
4886 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4888 struct drm_device
*dev
= crtc
->dev
;
4889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4890 struct intel_encoder
*encoder
;
4891 struct intel_encoder
*edp_encoder
= NULL
;
4892 int num_connectors
= 0;
4893 bool is_lvds
= false;
4895 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4896 switch (encoder
->type
) {
4897 case INTEL_OUTPUT_LVDS
:
4900 case INTEL_OUTPUT_EDP
:
4901 edp_encoder
= encoder
;
4907 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4908 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4909 dev_priv
->lvds_ssc_freq
);
4910 return dev_priv
->lvds_ssc_freq
* 1000;
4916 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
,
4917 struct drm_display_mode
*adjusted_mode
,
4920 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4922 int pipe
= intel_crtc
->pipe
;
4925 val
= I915_READ(PIPECONF(pipe
));
4927 val
&= ~PIPE_BPC_MASK
;
4928 switch (intel_crtc
->bpp
) {
4942 /* Case prevented by intel_choose_pipe_bpp_dither. */
4946 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
4948 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
4950 val
&= ~PIPECONF_INTERLACE_MASK
;
4951 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4952 val
|= PIPECONF_INTERLACED_ILK
;
4954 val
|= PIPECONF_PROGRESSIVE
;
4956 I915_WRITE(PIPECONF(pipe
), val
);
4957 POSTING_READ(PIPECONF(pipe
));
4960 static void haswell_set_pipeconf(struct drm_crtc
*crtc
,
4961 struct drm_display_mode
*adjusted_mode
,
4964 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
4965 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4966 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
4969 val
= I915_READ(PIPECONF(cpu_transcoder
));
4971 val
&= ~(PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_MASK
);
4973 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
4975 val
&= ~PIPECONF_INTERLACE_MASK_HSW
;
4976 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
4977 val
|= PIPECONF_INTERLACED_ILK
;
4979 val
|= PIPECONF_PROGRESSIVE
;
4981 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
4982 POSTING_READ(PIPECONF(cpu_transcoder
));
4985 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
4986 struct drm_display_mode
*adjusted_mode
,
4987 intel_clock_t
*clock
,
4988 bool *has_reduced_clock
,
4989 intel_clock_t
*reduced_clock
)
4991 struct drm_device
*dev
= crtc
->dev
;
4992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4993 struct intel_encoder
*intel_encoder
;
4995 const intel_limit_t
*limit
;
4996 bool ret
, is_sdvo
= false, is_tv
= false, is_lvds
= false;
4998 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
4999 switch (intel_encoder
->type
) {
5000 case INTEL_OUTPUT_LVDS
:
5003 case INTEL_OUTPUT_SDVO
:
5004 case INTEL_OUTPUT_HDMI
:
5006 if (intel_encoder
->needs_tv_clock
)
5009 case INTEL_OUTPUT_TVOUT
:
5015 refclk
= ironlake_get_refclk(crtc
);
5018 * Returns a set of divisors for the desired target clock with the given
5019 * refclk, or FALSE. The returned values represent the clock equation:
5020 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5022 limit
= intel_limit(crtc
, refclk
);
5023 ret
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
5028 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
5030 * Ensure we match the reduced clock's P to the target clock.
5031 * If the clocks don't match, we can't switch the display clock
5032 * by using the FP0/FP1. In such case we will disable the LVDS
5033 * downclock feature.
5035 *has_reduced_clock
= limit
->find_pll(limit
, crtc
,
5036 dev_priv
->lvds_downclock
,
5042 if (is_sdvo
&& is_tv
)
5043 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, clock
);
5048 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
5050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5053 temp
= I915_READ(SOUTH_CHICKEN1
);
5054 if (temp
& FDI_BC_BIFURCATION_SELECT
)
5057 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
5058 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
5060 temp
|= FDI_BC_BIFURCATION_SELECT
;
5061 DRM_DEBUG_KMS("enabling fdi C rx\n");
5062 I915_WRITE(SOUTH_CHICKEN1
, temp
);
5063 POSTING_READ(SOUTH_CHICKEN1
);
5066 static bool ironlake_check_fdi_lanes(struct intel_crtc
*intel_crtc
)
5068 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5069 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5070 struct intel_crtc
*pipe_B_crtc
=
5071 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5073 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5074 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5075 if (intel_crtc
->fdi_lanes
> 4) {
5076 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5077 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5078 /* Clamp lanes to avoid programming the hw with bogus values. */
5079 intel_crtc
->fdi_lanes
= 4;
5084 if (dev_priv
->num_pipe
== 2)
5087 switch (intel_crtc
->pipe
) {
5091 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5092 intel_crtc
->fdi_lanes
> 2) {
5093 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5094 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5095 /* Clamp lanes to avoid programming the hw with bogus values. */
5096 intel_crtc
->fdi_lanes
= 2;
5101 if (intel_crtc
->fdi_lanes
> 2)
5102 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
5104 cpt_enable_fdi_bc_bifurcation(dev
);
5108 if (!pipe_B_crtc
->base
.enabled
|| pipe_B_crtc
->fdi_lanes
<= 2) {
5109 if (intel_crtc
->fdi_lanes
> 2) {
5110 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5111 intel_crtc
->pipe
, intel_crtc
->fdi_lanes
);
5112 /* Clamp lanes to avoid programming the hw with bogus values. */
5113 intel_crtc
->fdi_lanes
= 2;
5118 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5122 cpt_enable_fdi_bc_bifurcation(dev
);
5130 static void ironlake_set_m_n(struct drm_crtc
*crtc
,
5131 struct drm_display_mode
*mode
,
5132 struct drm_display_mode
*adjusted_mode
)
5134 struct drm_device
*dev
= crtc
->dev
;
5135 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5136 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5137 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
5138 struct intel_encoder
*intel_encoder
, *edp_encoder
= NULL
;
5139 struct fdi_m_n m_n
= {0};
5140 int target_clock
, pixel_multiplier
, lane
, link_bw
;
5141 bool is_dp
= false, is_cpu_edp
= false;
5143 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5144 switch (intel_encoder
->type
) {
5145 case INTEL_OUTPUT_DISPLAYPORT
:
5148 case INTEL_OUTPUT_EDP
:
5150 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5152 edp_encoder
= intel_encoder
;
5158 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5160 /* CPU eDP doesn't require FDI link, so just set DP M/N
5161 according to current link config */
5163 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
5165 /* FDI is a binary signal running at ~2.7GHz, encoding
5166 * each output octet as 10 bits. The actual frequency
5167 * is stored as a divider into a 100MHz clock, and the
5168 * mode pixel clock is stored in units of 1KHz.
5169 * Hence the bw of each lane in terms of the mode signal
5172 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5175 /* [e]DP over FDI requires target mode clock instead of link clock. */
5177 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
5179 target_clock
= mode
->clock
;
5181 target_clock
= adjusted_mode
->clock
;
5185 * Account for spread spectrum to avoid
5186 * oversubscribing the link. Max center spread
5187 * is 2.5%; use 5% for safety's sake.
5189 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
5190 lane
= bps
/ (link_bw
* 8) + 1;
5193 intel_crtc
->fdi_lanes
= lane
;
5195 if (pixel_multiplier
> 1)
5196 link_bw
*= pixel_multiplier
;
5197 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
5200 I915_WRITE(PIPE_DATA_M1(cpu_transcoder
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
5201 I915_WRITE(PIPE_DATA_N1(cpu_transcoder
), m_n
.gmch_n
);
5202 I915_WRITE(PIPE_LINK_M1(cpu_transcoder
), m_n
.link_m
);
5203 I915_WRITE(PIPE_LINK_N1(cpu_transcoder
), m_n
.link_n
);
5206 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
5207 struct drm_display_mode
*adjusted_mode
,
5208 intel_clock_t
*clock
, u32 fp
)
5210 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5211 struct drm_device
*dev
= crtc
->dev
;
5212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5213 struct intel_encoder
*intel_encoder
;
5215 int factor
, pixel_multiplier
, num_connectors
= 0;
5216 bool is_lvds
= false, is_sdvo
= false, is_tv
= false;
5217 bool is_dp
= false, is_cpu_edp
= false;
5219 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
5220 switch (intel_encoder
->type
) {
5221 case INTEL_OUTPUT_LVDS
:
5224 case INTEL_OUTPUT_SDVO
:
5225 case INTEL_OUTPUT_HDMI
:
5227 if (intel_encoder
->needs_tv_clock
)
5230 case INTEL_OUTPUT_TVOUT
:
5233 case INTEL_OUTPUT_DISPLAYPORT
:
5236 case INTEL_OUTPUT_EDP
:
5238 if (!intel_encoder_is_pch_edp(&intel_encoder
->base
))
5246 /* Enable autotuning of the PLL clock (if permissible) */
5249 if ((intel_panel_use_ssc(dev_priv
) &&
5250 dev_priv
->lvds_ssc_freq
== 100) ||
5251 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
5253 } else if (is_sdvo
&& is_tv
)
5256 if (clock
->m
< factor
* clock
->n
)
5262 dpll
|= DPLLB_MODE_LVDS
;
5264 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5266 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
5267 if (pixel_multiplier
> 1) {
5268 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
5270 dpll
|= DPLL_DVO_HIGH_SPEED
;
5272 if (is_dp
&& !is_cpu_edp
)
5273 dpll
|= DPLL_DVO_HIGH_SPEED
;
5275 /* compute bitmask from p1 value */
5276 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5278 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5280 switch (clock
->p2
) {
5282 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5285 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5288 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5291 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5295 if (is_sdvo
&& is_tv
)
5296 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5298 /* XXX: just matching BIOS for now */
5299 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5301 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5302 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5304 dpll
|= PLL_REF_INPUT_DREFCLK
;
5309 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
5310 struct drm_display_mode
*mode
,
5311 struct drm_display_mode
*adjusted_mode
,
5313 struct drm_framebuffer
*fb
)
5315 struct drm_device
*dev
= crtc
->dev
;
5316 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5317 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5318 int pipe
= intel_crtc
->pipe
;
5319 int plane
= intel_crtc
->plane
;
5320 int num_connectors
= 0;
5321 intel_clock_t clock
, reduced_clock
;
5322 u32 dpll
, fp
= 0, fp2
= 0;
5323 bool ok
, has_reduced_clock
= false;
5324 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5325 struct intel_encoder
*encoder
;
5328 bool dither
, fdi_config_ok
;
5330 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5331 switch (encoder
->type
) {
5332 case INTEL_OUTPUT_LVDS
:
5335 case INTEL_OUTPUT_DISPLAYPORT
:
5338 case INTEL_OUTPUT_EDP
:
5340 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5348 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
5349 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
5351 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5352 &has_reduced_clock
, &reduced_clock
);
5354 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5358 /* Ensure that the cursor is valid for the new mode before changing... */
5359 intel_crtc_update_cursor(crtc
, true);
5361 /* determine panel color depth */
5362 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5364 if (is_lvds
&& dev_priv
->lvds_dither
)
5367 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5368 if (has_reduced_clock
)
5369 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5372 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
, fp
);
5374 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5375 drm_mode_debug_printmodeline(mode
);
5377 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5379 struct intel_pch_pll
*pll
;
5381 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5383 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5388 intel_put_pch_pll(intel_crtc
);
5390 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5391 * This is an exception to the general rule that mode_set doesn't turn
5395 temp
= I915_READ(PCH_LVDS
);
5396 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5397 if (HAS_PCH_CPT(dev
)) {
5398 temp
&= ~PORT_TRANS_SEL_MASK
;
5399 temp
|= PORT_TRANS_SEL_CPT(pipe
);
5402 temp
|= LVDS_PIPEB_SELECT
;
5404 temp
&= ~LVDS_PIPEB_SELECT
;
5407 /* set the corresponsding LVDS_BORDER bit */
5408 temp
|= dev_priv
->lvds_border_bits
;
5409 /* Set the B0-B3 data pairs corresponding to whether we're going to
5410 * set the DPLLs for dual-channel mode or not.
5413 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5415 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
5417 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5418 * appropriately here, but we need to look more thoroughly into how
5419 * panels behave in the two modes.
5421 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5422 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5423 temp
|= LVDS_HSYNC_POLARITY
;
5424 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5425 temp
|= LVDS_VSYNC_POLARITY
;
5426 I915_WRITE(PCH_LVDS
, temp
);
5429 if (is_dp
&& !is_cpu_edp
) {
5430 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5432 /* For non-DP output, clear any trans DP clock recovery setting.*/
5433 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5434 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5435 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5436 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5439 if (intel_crtc
->pch_pll
) {
5440 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5442 /* Wait for the clocks to stabilize. */
5443 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5446 /* The pixel multiplier can only be updated once the
5447 * DPLL is enabled and the clocks are stable.
5449 * So write it again.
5451 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5454 intel_crtc
->lowfreq_avail
= false;
5455 if (intel_crtc
->pch_pll
) {
5456 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5457 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5458 intel_crtc
->lowfreq_avail
= true;
5460 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5464 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5466 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5467 * ironlake_check_fdi_lanes. */
5468 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5470 fdi_config_ok
= ironlake_check_fdi_lanes(intel_crtc
);
5473 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5475 ironlake_set_pipeconf(crtc
, adjusted_mode
, dither
);
5477 intel_wait_for_vblank(dev
, pipe
);
5479 /* Set up the display plane register */
5480 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5481 POSTING_READ(DSPCNTR(plane
));
5483 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5485 intel_update_watermarks(dev
);
5487 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5489 return fdi_config_ok
? ret
: -EINVAL
;
5492 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
5493 struct drm_display_mode
*mode
,
5494 struct drm_display_mode
*adjusted_mode
,
5496 struct drm_framebuffer
*fb
)
5498 struct drm_device
*dev
= crtc
->dev
;
5499 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5500 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5501 int pipe
= intel_crtc
->pipe
;
5502 int plane
= intel_crtc
->plane
;
5503 int num_connectors
= 0;
5504 intel_clock_t clock
, reduced_clock
;
5505 u32 dpll
= 0, fp
= 0, fp2
= 0;
5506 bool ok
, has_reduced_clock
= false;
5507 bool is_lvds
= false, is_dp
= false, is_cpu_edp
= false;
5508 struct intel_encoder
*encoder
;
5513 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5514 switch (encoder
->type
) {
5515 case INTEL_OUTPUT_LVDS
:
5518 case INTEL_OUTPUT_DISPLAYPORT
:
5521 case INTEL_OUTPUT_EDP
:
5523 if (!intel_encoder_is_pch_edp(&encoder
->base
))
5532 intel_crtc
->cpu_transcoder
= TRANSCODER_EDP
;
5534 intel_crtc
->cpu_transcoder
= pipe
;
5536 /* We are not sure yet this won't happen. */
5537 WARN(!HAS_PCH_LPT(dev
), "Unexpected PCH type %d\n",
5538 INTEL_PCH_TYPE(dev
));
5540 WARN(num_connectors
!= 1, "%d connectors attached to pipe %c\n",
5541 num_connectors
, pipe_name(pipe
));
5543 WARN_ON(I915_READ(PIPECONF(intel_crtc
->cpu_transcoder
)) &
5544 (PIPECONF_ENABLE
| I965_PIPECONF_ACTIVE
));
5546 WARN_ON(I915_READ(DSPCNTR(plane
)) & DISPLAY_PLANE_ENABLE
);
5548 if (!intel_ddi_pll_mode_set(crtc
, adjusted_mode
->clock
))
5551 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5552 ok
= ironlake_compute_clocks(crtc
, adjusted_mode
, &clock
,
5556 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5561 /* Ensure that the cursor is valid for the new mode before changing... */
5562 intel_crtc_update_cursor(crtc
, true);
5564 /* determine panel color depth */
5565 dither
= intel_choose_pipe_bpp_dither(crtc
, fb
, &intel_crtc
->bpp
,
5567 if (is_lvds
&& dev_priv
->lvds_dither
)
5570 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
5571 drm_mode_debug_printmodeline(mode
);
5573 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5574 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
5575 if (has_reduced_clock
)
5576 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
5579 dpll
= ironlake_compute_dpll(intel_crtc
, adjusted_mode
, &clock
,
5582 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5583 * own on pre-Haswell/LPT generation */
5585 struct intel_pch_pll
*pll
;
5587 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
5589 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5594 intel_put_pch_pll(intel_crtc
);
5596 /* The LVDS pin pair needs to be on before the DPLLs are
5597 * enabled. This is an exception to the general rule that
5598 * mode_set doesn't turn things on.
5601 temp
= I915_READ(PCH_LVDS
);
5602 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
5603 if (HAS_PCH_CPT(dev
)) {
5604 temp
&= ~PORT_TRANS_SEL_MASK
;
5605 temp
|= PORT_TRANS_SEL_CPT(pipe
);
5608 temp
|= LVDS_PIPEB_SELECT
;
5610 temp
&= ~LVDS_PIPEB_SELECT
;
5613 /* set the corresponsding LVDS_BORDER bit */
5614 temp
|= dev_priv
->lvds_border_bits
;
5615 /* Set the B0-B3 data pairs corresponding to whether
5616 * we're going to set the DPLLs for dual-channel mode or
5620 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
5622 temp
&= ~(LVDS_B0B3_POWER_UP
|
5623 LVDS_CLKB_POWER_UP
);
5625 /* It would be nice to set 24 vs 18-bit mode
5626 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5627 * look more thoroughly into how panels behave in the
5630 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
5631 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
5632 temp
|= LVDS_HSYNC_POLARITY
;
5633 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
5634 temp
|= LVDS_VSYNC_POLARITY
;
5635 I915_WRITE(PCH_LVDS
, temp
);
5639 if (is_dp
&& !is_cpu_edp
) {
5640 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
5642 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5643 /* For non-DP output, clear any trans DP clock recovery
5645 I915_WRITE(TRANSDATA_M1(pipe
), 0);
5646 I915_WRITE(TRANSDATA_N1(pipe
), 0);
5647 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
5648 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
5652 intel_crtc
->lowfreq_avail
= false;
5653 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
5654 if (intel_crtc
->pch_pll
) {
5655 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5657 /* Wait for the clocks to stabilize. */
5658 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
5661 /* The pixel multiplier can only be updated once the
5662 * DPLL is enabled and the clocks are stable.
5664 * So write it again.
5666 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
5669 if (intel_crtc
->pch_pll
) {
5670 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
5671 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
5672 intel_crtc
->lowfreq_avail
= true;
5674 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
5679 intel_set_pipe_timings(intel_crtc
, mode
, adjusted_mode
);
5681 if (!is_dp
|| is_cpu_edp
)
5682 ironlake_set_m_n(crtc
, mode
, adjusted_mode
);
5684 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
5686 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
5688 haswell_set_pipeconf(crtc
, adjusted_mode
, dither
);
5690 /* Set up the display plane register */
5691 I915_WRITE(DSPCNTR(plane
), DISPPLANE_GAMMA_ENABLE
);
5692 POSTING_READ(DSPCNTR(plane
));
5694 ret
= intel_pipe_set_base(crtc
, x
, y
, fb
);
5696 intel_update_watermarks(dev
);
5698 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
5703 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
5704 struct drm_display_mode
*mode
,
5705 struct drm_display_mode
*adjusted_mode
,
5707 struct drm_framebuffer
*fb
)
5709 struct drm_device
*dev
= crtc
->dev
;
5710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5711 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5712 int pipe
= intel_crtc
->pipe
;
5715 drm_vblank_pre_modeset(dev
, pipe
);
5717 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
5719 drm_vblank_post_modeset(dev
, pipe
);
5724 static bool intel_eld_uptodate(struct drm_connector
*connector
,
5725 int reg_eldv
, uint32_t bits_eldv
,
5726 int reg_elda
, uint32_t bits_elda
,
5729 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5730 uint8_t *eld
= connector
->eld
;
5733 i
= I915_READ(reg_eldv
);
5742 i
= I915_READ(reg_elda
);
5744 I915_WRITE(reg_elda
, i
);
5746 for (i
= 0; i
< eld
[2]; i
++)
5747 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5753 static void g4x_write_eld(struct drm_connector
*connector
,
5754 struct drm_crtc
*crtc
)
5756 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5757 uint8_t *eld
= connector
->eld
;
5762 i
= I915_READ(G4X_AUD_VID_DID
);
5764 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5765 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5767 eldv
= G4X_ELDV_DEVCTG
;
5769 if (intel_eld_uptodate(connector
,
5770 G4X_AUD_CNTL_ST
, eldv
,
5771 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5772 G4X_HDMIW_HDMIEDID
))
5775 i
= I915_READ(G4X_AUD_CNTL_ST
);
5776 i
&= ~(eldv
| G4X_ELD_ADDR
);
5777 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5778 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5783 len
= min_t(uint8_t, eld
[2], len
);
5784 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5785 for (i
= 0; i
< len
; i
++)
5786 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5788 i
= I915_READ(G4X_AUD_CNTL_ST
);
5790 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5793 static void haswell_write_eld(struct drm_connector
*connector
,
5794 struct drm_crtc
*crtc
)
5796 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5797 uint8_t *eld
= connector
->eld
;
5798 struct drm_device
*dev
= crtc
->dev
;
5802 int pipe
= to_intel_crtc(crtc
)->pipe
;
5805 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
5806 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
5807 int aud_config
= HSW_AUD_CFG(pipe
);
5808 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
5811 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5813 /* Audio output enable */
5814 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5815 tmp
= I915_READ(aud_cntrl_st2
);
5816 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
5817 I915_WRITE(aud_cntrl_st2
, tmp
);
5819 /* Wait for 1 vertical blank */
5820 intel_wait_for_vblank(dev
, pipe
);
5822 /* Set ELD valid state */
5823 tmp
= I915_READ(aud_cntrl_st2
);
5824 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp
);
5825 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
5826 I915_WRITE(aud_cntrl_st2
, tmp
);
5827 tmp
= I915_READ(aud_cntrl_st2
);
5828 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp
);
5830 /* Enable HDMI mode */
5831 tmp
= I915_READ(aud_config
);
5832 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp
);
5833 /* clear N_programing_enable and N_value_index */
5834 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
5835 I915_WRITE(aud_config
, tmp
);
5837 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5839 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
5841 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5842 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5843 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5844 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5846 I915_WRITE(aud_config
, 0);
5848 if (intel_eld_uptodate(connector
,
5849 aud_cntrl_st2
, eldv
,
5850 aud_cntl_st
, IBX_ELD_ADDRESS
,
5854 i
= I915_READ(aud_cntrl_st2
);
5856 I915_WRITE(aud_cntrl_st2
, i
);
5861 i
= I915_READ(aud_cntl_st
);
5862 i
&= ~IBX_ELD_ADDRESS
;
5863 I915_WRITE(aud_cntl_st
, i
);
5864 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5865 DRM_DEBUG_DRIVER("port num:%d\n", i
);
5867 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5868 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5869 for (i
= 0; i
< len
; i
++)
5870 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5872 i
= I915_READ(aud_cntrl_st2
);
5874 I915_WRITE(aud_cntrl_st2
, i
);
5878 static void ironlake_write_eld(struct drm_connector
*connector
,
5879 struct drm_crtc
*crtc
)
5881 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5882 uint8_t *eld
= connector
->eld
;
5890 int pipe
= to_intel_crtc(crtc
)->pipe
;
5892 if (HAS_PCH_IBX(connector
->dev
)) {
5893 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
5894 aud_config
= IBX_AUD_CFG(pipe
);
5895 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
5896 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5898 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
5899 aud_config
= CPT_AUD_CFG(pipe
);
5900 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
5901 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5904 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
5906 i
= I915_READ(aud_cntl_st
);
5907 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
5909 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5910 /* operate blindly on all ports */
5911 eldv
= IBX_ELD_VALIDB
;
5912 eldv
|= IBX_ELD_VALIDB
<< 4;
5913 eldv
|= IBX_ELD_VALIDB
<< 8;
5915 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5916 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5919 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5920 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5921 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5922 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5924 I915_WRITE(aud_config
, 0);
5926 if (intel_eld_uptodate(connector
,
5927 aud_cntrl_st2
, eldv
,
5928 aud_cntl_st
, IBX_ELD_ADDRESS
,
5932 i
= I915_READ(aud_cntrl_st2
);
5934 I915_WRITE(aud_cntrl_st2
, i
);
5939 i
= I915_READ(aud_cntl_st
);
5940 i
&= ~IBX_ELD_ADDRESS
;
5941 I915_WRITE(aud_cntl_st
, i
);
5943 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5944 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5945 for (i
= 0; i
< len
; i
++)
5946 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5948 i
= I915_READ(aud_cntrl_st2
);
5950 I915_WRITE(aud_cntrl_st2
, i
);
5953 void intel_write_eld(struct drm_encoder
*encoder
,
5954 struct drm_display_mode
*mode
)
5956 struct drm_crtc
*crtc
= encoder
->crtc
;
5957 struct drm_connector
*connector
;
5958 struct drm_device
*dev
= encoder
->dev
;
5959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5961 connector
= drm_select_eld(encoder
, mode
);
5965 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5967 drm_get_connector_name(connector
),
5968 connector
->encoder
->base
.id
,
5969 drm_get_encoder_name(connector
->encoder
));
5971 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
5973 if (dev_priv
->display
.write_eld
)
5974 dev_priv
->display
.write_eld(connector
, crtc
);
5977 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5978 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5980 struct drm_device
*dev
= crtc
->dev
;
5981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5982 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5983 int palreg
= PALETTE(intel_crtc
->pipe
);
5986 /* The clocks have to be on to load the palette. */
5987 if (!crtc
->enabled
|| !intel_crtc
->active
)
5990 /* use legacy palette for Ironlake */
5991 if (HAS_PCH_SPLIT(dev
))
5992 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5994 for (i
= 0; i
< 256; i
++) {
5995 I915_WRITE(palreg
+ 4 * i
,
5996 (intel_crtc
->lut_r
[i
] << 16) |
5997 (intel_crtc
->lut_g
[i
] << 8) |
5998 intel_crtc
->lut_b
[i
]);
6002 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6004 struct drm_device
*dev
= crtc
->dev
;
6005 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6006 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6007 bool visible
= base
!= 0;
6010 if (intel_crtc
->cursor_visible
== visible
)
6013 cntl
= I915_READ(_CURACNTR
);
6015 /* On these chipsets we can only modify the base whilst
6016 * the cursor is disabled.
6018 I915_WRITE(_CURABASE
, base
);
6020 cntl
&= ~(CURSOR_FORMAT_MASK
);
6021 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6022 cntl
|= CURSOR_ENABLE
|
6023 CURSOR_GAMMA_ENABLE
|
6026 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
6027 I915_WRITE(_CURACNTR
, cntl
);
6029 intel_crtc
->cursor_visible
= visible
;
6032 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6034 struct drm_device
*dev
= crtc
->dev
;
6035 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6036 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6037 int pipe
= intel_crtc
->pipe
;
6038 bool visible
= base
!= 0;
6040 if (intel_crtc
->cursor_visible
!= visible
) {
6041 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
6043 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
6044 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6045 cntl
|= pipe
<< 28; /* Connect to correct pipe */
6047 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6048 cntl
|= CURSOR_MODE_DISABLE
;
6050 I915_WRITE(CURCNTR(pipe
), cntl
);
6052 intel_crtc
->cursor_visible
= visible
;
6054 /* and commit changes on next vblank */
6055 I915_WRITE(CURBASE(pipe
), base
);
6058 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
6060 struct drm_device
*dev
= crtc
->dev
;
6061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6062 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6063 int pipe
= intel_crtc
->pipe
;
6064 bool visible
= base
!= 0;
6066 if (intel_crtc
->cursor_visible
!= visible
) {
6067 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
6069 cntl
&= ~CURSOR_MODE
;
6070 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
6072 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
6073 cntl
|= CURSOR_MODE_DISABLE
;
6075 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
6077 intel_crtc
->cursor_visible
= visible
;
6079 /* and commit changes on next vblank */
6080 I915_WRITE(CURBASE_IVB(pipe
), base
);
6083 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6084 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
6087 struct drm_device
*dev
= crtc
->dev
;
6088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6089 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6090 int pipe
= intel_crtc
->pipe
;
6091 int x
= intel_crtc
->cursor_x
;
6092 int y
= intel_crtc
->cursor_y
;
6098 if (on
&& crtc
->enabled
&& crtc
->fb
) {
6099 base
= intel_crtc
->cursor_addr
;
6100 if (x
> (int) crtc
->fb
->width
)
6103 if (y
> (int) crtc
->fb
->height
)
6109 if (x
+ intel_crtc
->cursor_width
< 0)
6112 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
6115 pos
|= x
<< CURSOR_X_SHIFT
;
6118 if (y
+ intel_crtc
->cursor_height
< 0)
6121 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
6124 pos
|= y
<< CURSOR_Y_SHIFT
;
6126 visible
= base
!= 0;
6127 if (!visible
&& !intel_crtc
->cursor_visible
)
6130 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
6131 I915_WRITE(CURPOS_IVB(pipe
), pos
);
6132 ivb_update_cursor(crtc
, base
);
6134 I915_WRITE(CURPOS(pipe
), pos
);
6135 if (IS_845G(dev
) || IS_I865G(dev
))
6136 i845_update_cursor(crtc
, base
);
6138 i9xx_update_cursor(crtc
, base
);
6142 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
6143 struct drm_file
*file
,
6145 uint32_t width
, uint32_t height
)
6147 struct drm_device
*dev
= crtc
->dev
;
6148 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6149 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6150 struct drm_i915_gem_object
*obj
;
6154 /* if we want to turn off the cursor ignore width and height */
6156 DRM_DEBUG_KMS("cursor off\n");
6159 mutex_lock(&dev
->struct_mutex
);
6163 /* Currently we only support 64x64 cursors */
6164 if (width
!= 64 || height
!= 64) {
6165 DRM_ERROR("we currently only support 64x64 cursors\n");
6169 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
6170 if (&obj
->base
== NULL
)
6173 if (obj
->base
.size
< width
* height
* 4) {
6174 DRM_ERROR("buffer is to small\n");
6179 /* we only need to pin inside GTT if cursor is non-phy */
6180 mutex_lock(&dev
->struct_mutex
);
6181 if (!dev_priv
->info
->cursor_needs_physical
) {
6182 if (obj
->tiling_mode
) {
6183 DRM_ERROR("cursor cannot be tiled\n");
6188 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
6190 DRM_ERROR("failed to move cursor bo into the GTT\n");
6194 ret
= i915_gem_object_put_fence(obj
);
6196 DRM_ERROR("failed to release fence for cursor");
6200 addr
= obj
->gtt_offset
;
6202 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
6203 ret
= i915_gem_attach_phys_object(dev
, obj
,
6204 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
6207 DRM_ERROR("failed to attach phys object\n");
6210 addr
= obj
->phys_obj
->handle
->busaddr
;
6214 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
6217 if (intel_crtc
->cursor_bo
) {
6218 if (dev_priv
->info
->cursor_needs_physical
) {
6219 if (intel_crtc
->cursor_bo
!= obj
)
6220 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
6222 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
6223 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
6226 mutex_unlock(&dev
->struct_mutex
);
6228 intel_crtc
->cursor_addr
= addr
;
6229 intel_crtc
->cursor_bo
= obj
;
6230 intel_crtc
->cursor_width
= width
;
6231 intel_crtc
->cursor_height
= height
;
6233 intel_crtc_update_cursor(crtc
, true);
6237 i915_gem_object_unpin(obj
);
6239 mutex_unlock(&dev
->struct_mutex
);
6241 drm_gem_object_unreference_unlocked(&obj
->base
);
6245 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
6247 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6249 intel_crtc
->cursor_x
= x
;
6250 intel_crtc
->cursor_y
= y
;
6252 intel_crtc_update_cursor(crtc
, true);
6257 /** Sets the color ramps on behalf of RandR */
6258 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
6259 u16 blue
, int regno
)
6261 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6263 intel_crtc
->lut_r
[regno
] = red
>> 8;
6264 intel_crtc
->lut_g
[regno
] = green
>> 8;
6265 intel_crtc
->lut_b
[regno
] = blue
>> 8;
6268 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6269 u16
*blue
, int regno
)
6271 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6273 *red
= intel_crtc
->lut_r
[regno
] << 8;
6274 *green
= intel_crtc
->lut_g
[regno
] << 8;
6275 *blue
= intel_crtc
->lut_b
[regno
] << 8;
6278 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
6279 u16
*blue
, uint32_t start
, uint32_t size
)
6281 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
6282 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6284 for (i
= start
; i
< end
; i
++) {
6285 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
6286 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
6287 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
6290 intel_crtc_load_lut(crtc
);
6294 * Get a pipe with a simple mode set on it for doing load-based monitor
6297 * It will be up to the load-detect code to adjust the pipe as appropriate for
6298 * its requirements. The pipe will be connected to no other encoders.
6300 * Currently this code will only succeed if there is a pipe with no encoders
6301 * configured for it. In the future, it could choose to temporarily disable
6302 * some outputs to free up a pipe for its use.
6304 * \return crtc, or NULL if no pipes are available.
6307 /* VESA 640x480x72Hz mode to set on the pipe */
6308 static struct drm_display_mode load_detect_mode
= {
6309 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
6310 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
6313 static struct drm_framebuffer
*
6314 intel_framebuffer_create(struct drm_device
*dev
,
6315 struct drm_mode_fb_cmd2
*mode_cmd
,
6316 struct drm_i915_gem_object
*obj
)
6318 struct intel_framebuffer
*intel_fb
;
6321 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
6323 drm_gem_object_unreference_unlocked(&obj
->base
);
6324 return ERR_PTR(-ENOMEM
);
6327 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
6329 drm_gem_object_unreference_unlocked(&obj
->base
);
6331 return ERR_PTR(ret
);
6334 return &intel_fb
->base
;
6338 intel_framebuffer_pitch_for_width(int width
, int bpp
)
6340 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
6341 return ALIGN(pitch
, 64);
6345 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
6347 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
6348 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
6351 static struct drm_framebuffer
*
6352 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
6353 struct drm_display_mode
*mode
,
6356 struct drm_i915_gem_object
*obj
;
6357 struct drm_mode_fb_cmd2 mode_cmd
;
6359 obj
= i915_gem_alloc_object(dev
,
6360 intel_framebuffer_size_for_mode(mode
, bpp
));
6362 return ERR_PTR(-ENOMEM
);
6364 mode_cmd
.width
= mode
->hdisplay
;
6365 mode_cmd
.height
= mode
->vdisplay
;
6366 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
6368 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
6370 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
6373 static struct drm_framebuffer
*
6374 mode_fits_in_fbdev(struct drm_device
*dev
,
6375 struct drm_display_mode
*mode
)
6377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6378 struct drm_i915_gem_object
*obj
;
6379 struct drm_framebuffer
*fb
;
6381 if (dev_priv
->fbdev
== NULL
)
6384 obj
= dev_priv
->fbdev
->ifb
.obj
;
6388 fb
= &dev_priv
->fbdev
->ifb
.base
;
6389 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
6390 fb
->bits_per_pixel
))
6393 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
6399 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
6400 struct drm_display_mode
*mode
,
6401 struct intel_load_detect_pipe
*old
)
6403 struct intel_crtc
*intel_crtc
;
6404 struct intel_encoder
*intel_encoder
=
6405 intel_attached_encoder(connector
);
6406 struct drm_crtc
*possible_crtc
;
6407 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6408 struct drm_crtc
*crtc
= NULL
;
6409 struct drm_device
*dev
= encoder
->dev
;
6410 struct drm_framebuffer
*fb
;
6413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6414 connector
->base
.id
, drm_get_connector_name(connector
),
6415 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6418 * Algorithm gets a little messy:
6420 * - if the connector already has an assigned crtc, use it (but make
6421 * sure it's on first)
6423 * - try to find the first unused crtc that can drive this connector,
6424 * and use that if we find one
6427 /* See if we already have a CRTC for this connector */
6428 if (encoder
->crtc
) {
6429 crtc
= encoder
->crtc
;
6431 old
->dpms_mode
= connector
->dpms
;
6432 old
->load_detect_temp
= false;
6434 /* Make sure the crtc and connector are running */
6435 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
6436 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
6441 /* Find an unused one (if possible) */
6442 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
6444 if (!(encoder
->possible_crtcs
& (1 << i
)))
6446 if (!possible_crtc
->enabled
) {
6447 crtc
= possible_crtc
;
6453 * If we didn't find an unused CRTC, don't use any.
6456 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6460 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
6461 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
6463 intel_crtc
= to_intel_crtc(crtc
);
6464 old
->dpms_mode
= connector
->dpms
;
6465 old
->load_detect_temp
= true;
6466 old
->release_fb
= NULL
;
6469 mode
= &load_detect_mode
;
6471 /* We need a framebuffer large enough to accommodate all accesses
6472 * that the plane may generate whilst we perform load detection.
6473 * We can not rely on the fbcon either being present (we get called
6474 * during its initialisation to detect all boot displays, or it may
6475 * not even exist) or that it is large enough to satisfy the
6478 fb
= mode_fits_in_fbdev(dev
, mode
);
6480 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6481 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
6482 old
->release_fb
= fb
;
6484 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6486 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6490 if (!intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
6491 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6492 if (old
->release_fb
)
6493 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6497 /* let the connector get through one full cycle before testing */
6498 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
6502 connector
->encoder
= NULL
;
6503 encoder
->crtc
= NULL
;
6507 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
6508 struct intel_load_detect_pipe
*old
)
6510 struct intel_encoder
*intel_encoder
=
6511 intel_attached_encoder(connector
);
6512 struct drm_encoder
*encoder
= &intel_encoder
->base
;
6514 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6515 connector
->base
.id
, drm_get_connector_name(connector
),
6516 encoder
->base
.id
, drm_get_encoder_name(encoder
));
6518 if (old
->load_detect_temp
) {
6519 struct drm_crtc
*crtc
= encoder
->crtc
;
6521 to_intel_connector(connector
)->new_encoder
= NULL
;
6522 intel_encoder
->new_crtc
= NULL
;
6523 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
6525 if (old
->release_fb
)
6526 old
->release_fb
->funcs
->destroy(old
->release_fb
);
6531 /* Switch crtc and encoder back off if necessary */
6532 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
6533 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
6536 /* Returns the clock of the currently programmed mode of the given pipe. */
6537 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
6539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6540 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6541 int pipe
= intel_crtc
->pipe
;
6542 u32 dpll
= I915_READ(DPLL(pipe
));
6544 intel_clock_t clock
;
6546 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
6547 fp
= I915_READ(FP0(pipe
));
6549 fp
= I915_READ(FP1(pipe
));
6551 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
6552 if (IS_PINEVIEW(dev
)) {
6553 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
6554 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6556 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
6557 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
6560 if (!IS_GEN2(dev
)) {
6561 if (IS_PINEVIEW(dev
))
6562 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
6563 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
6565 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
6566 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6568 switch (dpll
& DPLL_MODE_MASK
) {
6569 case DPLLB_MODE_DAC_SERIAL
:
6570 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
6573 case DPLLB_MODE_LVDS
:
6574 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
6578 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6579 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
6583 /* XXX: Handle the 100Mhz refclk */
6584 intel_clock(dev
, 96000, &clock
);
6586 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
6589 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
6590 DPLL_FPA01_P1_POST_DIV_SHIFT
);
6593 if ((dpll
& PLL_REF_INPUT_MASK
) ==
6594 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
6595 /* XXX: might not be 66MHz */
6596 intel_clock(dev
, 66000, &clock
);
6598 intel_clock(dev
, 48000, &clock
);
6600 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
6603 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
6604 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
6606 if (dpll
& PLL_P2_DIVIDE_BY_4
)
6611 intel_clock(dev
, 48000, &clock
);
6615 /* XXX: It would be nice to validate the clocks, but we can't reuse
6616 * i830PllIsValid() because it relies on the xf86_config connector
6617 * configuration being accurate, which it isn't necessarily.
6623 /** Returns the currently programmed mode of the given pipe. */
6624 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
6625 struct drm_crtc
*crtc
)
6627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6629 enum transcoder cpu_transcoder
= intel_crtc
->cpu_transcoder
;
6630 struct drm_display_mode
*mode
;
6631 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
6632 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
6633 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
6634 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
6636 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
6640 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
6641 mode
->hdisplay
= (htot
& 0xffff) + 1;
6642 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
6643 mode
->hsync_start
= (hsync
& 0xffff) + 1;
6644 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
6645 mode
->vdisplay
= (vtot
& 0xffff) + 1;
6646 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
6647 mode
->vsync_start
= (vsync
& 0xffff) + 1;
6648 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
6650 drm_mode_set_name(mode
);
6655 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
6657 struct drm_device
*dev
= crtc
->dev
;
6658 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6659 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6660 int pipe
= intel_crtc
->pipe
;
6661 int dpll_reg
= DPLL(pipe
);
6664 if (HAS_PCH_SPLIT(dev
))
6667 if (!dev_priv
->lvds_downclock_avail
)
6670 dpll
= I915_READ(dpll_reg
);
6671 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
6672 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6674 assert_panel_unlocked(dev_priv
, pipe
);
6676 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
6677 I915_WRITE(dpll_reg
, dpll
);
6678 intel_wait_for_vblank(dev
, pipe
);
6680 dpll
= I915_READ(dpll_reg
);
6681 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
6682 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6686 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
6688 struct drm_device
*dev
= crtc
->dev
;
6689 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6690 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6692 if (HAS_PCH_SPLIT(dev
))
6695 if (!dev_priv
->lvds_downclock_avail
)
6699 * Since this is called by a timer, we should never get here in
6702 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
6703 int pipe
= intel_crtc
->pipe
;
6704 int dpll_reg
= DPLL(pipe
);
6707 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6709 assert_panel_unlocked(dev_priv
, pipe
);
6711 dpll
= I915_READ(dpll_reg
);
6712 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
6713 I915_WRITE(dpll_reg
, dpll
);
6714 intel_wait_for_vblank(dev
, pipe
);
6715 dpll
= I915_READ(dpll_reg
);
6716 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
6717 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6722 void intel_mark_busy(struct drm_device
*dev
)
6724 i915_update_gfx_val(dev
->dev_private
);
6727 void intel_mark_idle(struct drm_device
*dev
)
6731 void intel_mark_fb_busy(struct drm_i915_gem_object
*obj
)
6733 struct drm_device
*dev
= obj
->base
.dev
;
6734 struct drm_crtc
*crtc
;
6736 if (!i915_powersave
)
6739 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6743 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6744 intel_increase_pllclock(crtc
);
6748 void intel_mark_fb_idle(struct drm_i915_gem_object
*obj
)
6750 struct drm_device
*dev
= obj
->base
.dev
;
6751 struct drm_crtc
*crtc
;
6753 if (!i915_powersave
)
6756 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6760 if (to_intel_framebuffer(crtc
->fb
)->obj
== obj
)
6761 intel_decrease_pllclock(crtc
);
6765 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6767 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6768 struct drm_device
*dev
= crtc
->dev
;
6769 struct intel_unpin_work
*work
;
6770 unsigned long flags
;
6772 spin_lock_irqsave(&dev
->event_lock
, flags
);
6773 work
= intel_crtc
->unpin_work
;
6774 intel_crtc
->unpin_work
= NULL
;
6775 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6778 cancel_work_sync(&work
->work
);
6782 drm_crtc_cleanup(crtc
);
6787 static void intel_unpin_work_fn(struct work_struct
*__work
)
6789 struct intel_unpin_work
*work
=
6790 container_of(__work
, struct intel_unpin_work
, work
);
6792 mutex_lock(&work
->dev
->struct_mutex
);
6793 intel_unpin_fb_obj(work
->old_fb_obj
);
6794 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6795 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6797 intel_update_fbc(work
->dev
);
6798 mutex_unlock(&work
->dev
->struct_mutex
);
6802 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6803 struct drm_crtc
*crtc
)
6805 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6807 struct intel_unpin_work
*work
;
6808 struct drm_i915_gem_object
*obj
;
6809 struct drm_pending_vblank_event
*e
;
6810 struct timeval tvbl
;
6811 unsigned long flags
;
6813 /* Ignore early vblank irqs */
6814 if (intel_crtc
== NULL
)
6817 spin_lock_irqsave(&dev
->event_lock
, flags
);
6818 work
= intel_crtc
->unpin_work
;
6819 if (work
== NULL
|| !work
->pending
) {
6820 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6824 intel_crtc
->unpin_work
= NULL
;
6828 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6830 e
->event
.tv_sec
= tvbl
.tv_sec
;
6831 e
->event
.tv_usec
= tvbl
.tv_usec
;
6833 list_add_tail(&e
->base
.link
,
6834 &e
->base
.file_priv
->event_list
);
6835 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6838 drm_vblank_put(dev
, intel_crtc
->pipe
);
6840 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6842 obj
= work
->old_fb_obj
;
6844 atomic_clear_mask(1 << intel_crtc
->plane
,
6845 &obj
->pending_flip
.counter
);
6847 wake_up(&dev_priv
->pending_flip_queue
);
6848 schedule_work(&work
->work
);
6850 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6853 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6855 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6856 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6858 do_intel_finish_page_flip(dev
, crtc
);
6861 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6863 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6864 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6866 do_intel_finish_page_flip(dev
, crtc
);
6869 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6871 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6872 struct intel_crtc
*intel_crtc
=
6873 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6874 unsigned long flags
;
6876 spin_lock_irqsave(&dev
->event_lock
, flags
);
6877 if (intel_crtc
->unpin_work
) {
6878 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6879 DRM_ERROR("Prepared flip multiple times\n");
6881 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6883 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6886 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6887 struct drm_crtc
*crtc
,
6888 struct drm_framebuffer
*fb
,
6889 struct drm_i915_gem_object
*obj
)
6891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6892 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6894 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6897 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6901 ret
= intel_ring_begin(ring
, 6);
6905 /* Can't queue multiple flips, so wait for the previous
6906 * one to finish before executing the next.
6908 if (intel_crtc
->plane
)
6909 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6911 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6912 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6913 intel_ring_emit(ring
, MI_NOOP
);
6914 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6915 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6916 intel_ring_emit(ring
, fb
->pitches
[0]);
6917 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6918 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6919 intel_ring_advance(ring
);
6923 intel_unpin_fb_obj(obj
);
6928 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6929 struct drm_crtc
*crtc
,
6930 struct drm_framebuffer
*fb
,
6931 struct drm_i915_gem_object
*obj
)
6933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6934 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6936 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6939 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6943 ret
= intel_ring_begin(ring
, 6);
6947 if (intel_crtc
->plane
)
6948 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6950 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6951 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6952 intel_ring_emit(ring
, MI_NOOP
);
6953 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6954 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6955 intel_ring_emit(ring
, fb
->pitches
[0]);
6956 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
6957 intel_ring_emit(ring
, MI_NOOP
);
6959 intel_ring_advance(ring
);
6963 intel_unpin_fb_obj(obj
);
6968 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6969 struct drm_crtc
*crtc
,
6970 struct drm_framebuffer
*fb
,
6971 struct drm_i915_gem_object
*obj
)
6973 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6974 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6975 uint32_t pf
, pipesrc
;
6976 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6979 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6983 ret
= intel_ring_begin(ring
, 4);
6987 /* i965+ uses the linear or tiled offsets from the
6988 * Display Registers (which do not change across a page-flip)
6989 * so we need only reprogram the base address.
6991 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6992 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6993 intel_ring_emit(ring
, fb
->pitches
[0]);
6994 intel_ring_emit(ring
,
6995 (obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
) |
6998 /* XXX Enabling the panel-fitter across page-flip is so far
6999 * untested on non-native modes, so ignore it for now.
7000 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7003 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7004 intel_ring_emit(ring
, pf
| pipesrc
);
7005 intel_ring_advance(ring
);
7009 intel_unpin_fb_obj(obj
);
7014 static int intel_gen6_queue_flip(struct drm_device
*dev
,
7015 struct drm_crtc
*crtc
,
7016 struct drm_framebuffer
*fb
,
7017 struct drm_i915_gem_object
*obj
)
7019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7020 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7021 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
7022 uint32_t pf
, pipesrc
;
7025 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7029 ret
= intel_ring_begin(ring
, 4);
7033 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
7034 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
7035 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
7036 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7038 /* Contrary to the suggestions in the documentation,
7039 * "Enable Panel Fitter" does not seem to be required when page
7040 * flipping with a non-native mode, and worse causes a normal
7042 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7045 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
7046 intel_ring_emit(ring
, pf
| pipesrc
);
7047 intel_ring_advance(ring
);
7051 intel_unpin_fb_obj(obj
);
7057 * On gen7 we currently use the blit ring because (in early silicon at least)
7058 * the render ring doesn't give us interrpts for page flip completion, which
7059 * means clients will hang after the first flip is queued. Fortunately the
7060 * blit ring generates interrupts properly, so use it instead.
7062 static int intel_gen7_queue_flip(struct drm_device
*dev
,
7063 struct drm_crtc
*crtc
,
7064 struct drm_framebuffer
*fb
,
7065 struct drm_i915_gem_object
*obj
)
7067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7068 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7069 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
7070 uint32_t plane_bit
= 0;
7073 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
7077 switch(intel_crtc
->plane
) {
7079 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
7082 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
7085 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
7088 WARN_ONCE(1, "unknown plane in flip command\n");
7093 ret
= intel_ring_begin(ring
, 4);
7097 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
7098 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
7099 intel_ring_emit(ring
, obj
->gtt_offset
+ intel_crtc
->dspaddr_offset
);
7100 intel_ring_emit(ring
, (MI_NOOP
));
7101 intel_ring_advance(ring
);
7105 intel_unpin_fb_obj(obj
);
7110 static int intel_default_queue_flip(struct drm_device
*dev
,
7111 struct drm_crtc
*crtc
,
7112 struct drm_framebuffer
*fb
,
7113 struct drm_i915_gem_object
*obj
)
7118 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
7119 struct drm_framebuffer
*fb
,
7120 struct drm_pending_vblank_event
*event
)
7122 struct drm_device
*dev
= crtc
->dev
;
7123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7124 struct intel_framebuffer
*intel_fb
;
7125 struct drm_i915_gem_object
*obj
;
7126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7127 struct intel_unpin_work
*work
;
7128 unsigned long flags
;
7131 /* Can't change pixel format via MI display flips. */
7132 if (fb
->pixel_format
!= crtc
->fb
->pixel_format
)
7136 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7137 * Note that pitch changes could also affect these register.
7139 if (INTEL_INFO(dev
)->gen
> 3 &&
7140 (fb
->offsets
[0] != crtc
->fb
->offsets
[0] ||
7141 fb
->pitches
[0] != crtc
->fb
->pitches
[0]))
7144 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
7148 work
->event
= event
;
7149 work
->dev
= crtc
->dev
;
7150 intel_fb
= to_intel_framebuffer(crtc
->fb
);
7151 work
->old_fb_obj
= intel_fb
->obj
;
7152 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
7154 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
7158 /* We borrow the event spin lock for protecting unpin_work */
7159 spin_lock_irqsave(&dev
->event_lock
, flags
);
7160 if (intel_crtc
->unpin_work
) {
7161 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7163 drm_vblank_put(dev
, intel_crtc
->pipe
);
7165 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7168 intel_crtc
->unpin_work
= work
;
7169 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7171 intel_fb
= to_intel_framebuffer(fb
);
7172 obj
= intel_fb
->obj
;
7174 ret
= i915_mutex_lock_interruptible(dev
);
7178 /* Reference the objects for the scheduled work. */
7179 drm_gem_object_reference(&work
->old_fb_obj
->base
);
7180 drm_gem_object_reference(&obj
->base
);
7184 work
->pending_flip_obj
= obj
;
7186 work
->enable_stall_check
= true;
7188 /* Block clients from rendering to the new back buffer until
7189 * the flip occurs and the object is no longer visible.
7191 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7193 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
7195 goto cleanup_pending
;
7197 intel_disable_fbc(dev
);
7198 intel_mark_fb_busy(obj
);
7199 mutex_unlock(&dev
->struct_mutex
);
7201 trace_i915_flip_request(intel_crtc
->plane
, obj
);
7206 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
7207 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
7208 drm_gem_object_unreference(&obj
->base
);
7209 mutex_unlock(&dev
->struct_mutex
);
7212 spin_lock_irqsave(&dev
->event_lock
, flags
);
7213 intel_crtc
->unpin_work
= NULL
;
7214 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
7216 drm_vblank_put(dev
, intel_crtc
->pipe
);
7223 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
7224 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
7225 .load_lut
= intel_crtc_load_lut
,
7226 .disable
= intel_crtc_noop
,
7229 bool intel_encoder_check_is_cloned(struct intel_encoder
*encoder
)
7231 struct intel_encoder
*other_encoder
;
7232 struct drm_crtc
*crtc
= &encoder
->new_crtc
->base
;
7237 list_for_each_entry(other_encoder
,
7238 &crtc
->dev
->mode_config
.encoder_list
,
7241 if (&other_encoder
->new_crtc
->base
!= crtc
||
7242 encoder
== other_encoder
)
7251 static bool intel_encoder_crtc_ok(struct drm_encoder
*encoder
,
7252 struct drm_crtc
*crtc
)
7254 struct drm_device
*dev
;
7255 struct drm_crtc
*tmp
;
7258 WARN(!crtc
, "checking null crtc?\n");
7262 list_for_each_entry(tmp
, &dev
->mode_config
.crtc_list
, head
) {
7268 if (encoder
->possible_crtcs
& crtc_mask
)
7274 * intel_modeset_update_staged_output_state
7276 * Updates the staged output configuration state, e.g. after we've read out the
7279 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
7281 struct intel_encoder
*encoder
;
7282 struct intel_connector
*connector
;
7284 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7286 connector
->new_encoder
=
7287 to_intel_encoder(connector
->base
.encoder
);
7290 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7293 to_intel_crtc(encoder
->base
.crtc
);
7298 * intel_modeset_commit_output_state
7300 * This function copies the stage display pipe configuration to the real one.
7302 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
7304 struct intel_encoder
*encoder
;
7305 struct intel_connector
*connector
;
7307 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7309 connector
->base
.encoder
= &connector
->new_encoder
->base
;
7312 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7314 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
7318 static struct drm_display_mode
*
7319 intel_modeset_adjusted_mode(struct drm_crtc
*crtc
,
7320 struct drm_display_mode
*mode
)
7322 struct drm_device
*dev
= crtc
->dev
;
7323 struct drm_display_mode
*adjusted_mode
;
7324 struct drm_encoder_helper_funcs
*encoder_funcs
;
7325 struct intel_encoder
*encoder
;
7327 adjusted_mode
= drm_mode_duplicate(dev
, mode
);
7329 return ERR_PTR(-ENOMEM
);
7331 /* Pass our mode to the connectors and the CRTC to give them a chance to
7332 * adjust it according to limitations or connector properties, and also
7333 * a chance to reject the mode entirely.
7335 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7338 if (&encoder
->new_crtc
->base
!= crtc
)
7340 encoder_funcs
= encoder
->base
.helper_private
;
7341 if (!(encoder_funcs
->mode_fixup(&encoder
->base
, mode
,
7343 DRM_DEBUG_KMS("Encoder fixup failed\n");
7348 if (!(intel_crtc_mode_fixup(crtc
, mode
, adjusted_mode
))) {
7349 DRM_DEBUG_KMS("CRTC fixup failed\n");
7352 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc
->base
.id
);
7354 return adjusted_mode
;
7356 drm_mode_destroy(dev
, adjusted_mode
);
7357 return ERR_PTR(-EINVAL
);
7360 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7361 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7363 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
7364 unsigned *prepare_pipes
, unsigned *disable_pipes
)
7366 struct intel_crtc
*intel_crtc
;
7367 struct drm_device
*dev
= crtc
->dev
;
7368 struct intel_encoder
*encoder
;
7369 struct intel_connector
*connector
;
7370 struct drm_crtc
*tmp_crtc
;
7372 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
7374 /* Check which crtcs have changed outputs connected to them, these need
7375 * to be part of the prepare_pipes mask. We don't (yet) support global
7376 * modeset across multiple crtcs, so modeset_pipes will only have one
7377 * bit set at most. */
7378 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7380 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
7383 if (connector
->base
.encoder
) {
7384 tmp_crtc
= connector
->base
.encoder
->crtc
;
7386 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7389 if (connector
->new_encoder
)
7391 1 << connector
->new_encoder
->new_crtc
->pipe
;
7394 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7396 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
7399 if (encoder
->base
.crtc
) {
7400 tmp_crtc
= encoder
->base
.crtc
;
7402 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
7405 if (encoder
->new_crtc
)
7406 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
7409 /* Check for any pipes that will be fully disabled ... */
7410 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7414 /* Don't try to disable disabled crtcs. */
7415 if (!intel_crtc
->base
.enabled
)
7418 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7420 if (encoder
->new_crtc
== intel_crtc
)
7425 *disable_pipes
|= 1 << intel_crtc
->pipe
;
7429 /* set_mode is also used to update properties on life display pipes. */
7430 intel_crtc
= to_intel_crtc(crtc
);
7432 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
7434 /* We only support modeset on one single crtc, hence we need to do that
7435 * only for the passed in crtc iff we change anything else than just
7438 * This is actually not true, to be fully compatible with the old crtc
7439 * helper we automatically disable _any_ output (i.e. doesn't need to be
7440 * connected to the crtc we're modesetting on) if it's disconnected.
7441 * Which is a rather nutty api (since changed the output configuration
7442 * without userspace's explicit request can lead to confusion), but
7443 * alas. Hence we currently need to modeset on all pipes we prepare. */
7445 *modeset_pipes
= *prepare_pipes
;
7447 /* ... and mask these out. */
7448 *modeset_pipes
&= ~(*disable_pipes
);
7449 *prepare_pipes
&= ~(*disable_pipes
);
7452 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
7454 struct drm_encoder
*encoder
;
7455 struct drm_device
*dev
= crtc
->dev
;
7457 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
7458 if (encoder
->crtc
== crtc
)
7465 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
7467 struct intel_encoder
*intel_encoder
;
7468 struct intel_crtc
*intel_crtc
;
7469 struct drm_connector
*connector
;
7471 list_for_each_entry(intel_encoder
, &dev
->mode_config
.encoder_list
,
7473 if (!intel_encoder
->base
.crtc
)
7476 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
7478 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
7479 intel_encoder
->connectors_active
= false;
7482 intel_modeset_commit_output_state(dev
);
7484 /* Update computed state. */
7485 list_for_each_entry(intel_crtc
, &dev
->mode_config
.crtc_list
,
7487 intel_crtc
->base
.enabled
= intel_crtc_in_use(&intel_crtc
->base
);
7490 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7491 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
7494 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
7496 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
7497 struct drm_property
*dpms_property
=
7498 dev
->mode_config
.dpms_property
;
7500 connector
->dpms
= DRM_MODE_DPMS_ON
;
7501 drm_connector_property_set_value(connector
,
7505 intel_encoder
= to_intel_encoder(connector
->encoder
);
7506 intel_encoder
->connectors_active
= true;
7512 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7513 list_for_each_entry((intel_crtc), \
7514 &(dev)->mode_config.crtc_list, \
7516 if (mask & (1 <<(intel_crtc)->pipe)) \
7519 intel_modeset_check_state(struct drm_device
*dev
)
7521 struct intel_crtc
*crtc
;
7522 struct intel_encoder
*encoder
;
7523 struct intel_connector
*connector
;
7525 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7527 /* This also checks the encoder/connector hw state with the
7528 * ->get_hw_state callbacks. */
7529 intel_connector_check_state(connector
);
7531 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
7532 "connector's staged encoder doesn't match current encoder\n");
7535 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7537 bool enabled
= false;
7538 bool active
= false;
7539 enum pipe pipe
, tracked_pipe
;
7541 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7542 encoder
->base
.base
.id
,
7543 drm_get_encoder_name(&encoder
->base
));
7545 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
7546 "encoder's stage crtc doesn't match current crtc\n");
7547 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
7548 "encoder's active_connectors set, but no crtc\n");
7550 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7552 if (connector
->base
.encoder
!= &encoder
->base
)
7555 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
7558 WARN(!!encoder
->base
.crtc
!= enabled
,
7559 "encoder's enabled state mismatch "
7560 "(expected %i, found %i)\n",
7561 !!encoder
->base
.crtc
, enabled
);
7562 WARN(active
&& !encoder
->base
.crtc
,
7563 "active encoder with no crtc\n");
7565 WARN(encoder
->connectors_active
!= active
,
7566 "encoder's computed active state doesn't match tracked active state "
7567 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
7569 active
= encoder
->get_hw_state(encoder
, &pipe
);
7570 WARN(active
!= encoder
->connectors_active
,
7571 "encoder's hw state doesn't match sw tracking "
7572 "(expected %i, found %i)\n",
7573 encoder
->connectors_active
, active
);
7575 if (!encoder
->base
.crtc
)
7578 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
7579 WARN(active
&& pipe
!= tracked_pipe
,
7580 "active encoder's pipe doesn't match"
7581 "(expected %i, found %i)\n",
7582 tracked_pipe
, pipe
);
7586 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
,
7588 bool enabled
= false;
7589 bool active
= false;
7591 DRM_DEBUG_KMS("[CRTC:%d]\n",
7592 crtc
->base
.base
.id
);
7594 WARN(crtc
->active
&& !crtc
->base
.enabled
,
7595 "active crtc, but not enabled in sw tracking\n");
7597 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7599 if (encoder
->base
.crtc
!= &crtc
->base
)
7602 if (encoder
->connectors_active
)
7605 WARN(active
!= crtc
->active
,
7606 "crtc's computed active state doesn't match tracked active state "
7607 "(expected %i, found %i)\n", active
, crtc
->active
);
7608 WARN(enabled
!= crtc
->base
.enabled
,
7609 "crtc's computed enabled state doesn't match tracked enabled state "
7610 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
7612 assert_pipe(dev
->dev_private
, crtc
->pipe
, crtc
->active
);
7616 bool intel_set_mode(struct drm_crtc
*crtc
,
7617 struct drm_display_mode
*mode
,
7618 int x
, int y
, struct drm_framebuffer
*fb
)
7620 struct drm_device
*dev
= crtc
->dev
;
7621 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7622 struct drm_display_mode
*adjusted_mode
, saved_mode
, saved_hwmode
;
7623 struct drm_encoder_helper_funcs
*encoder_funcs
;
7624 struct drm_encoder
*encoder
;
7625 struct intel_crtc
*intel_crtc
;
7626 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
7629 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
7630 &prepare_pipes
, &disable_pipes
);
7632 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7633 modeset_pipes
, prepare_pipes
, disable_pipes
);
7635 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
7636 intel_crtc_disable(&intel_crtc
->base
);
7638 saved_hwmode
= crtc
->hwmode
;
7639 saved_mode
= crtc
->mode
;
7641 /* Hack: Because we don't (yet) support global modeset on multiple
7642 * crtcs, we don't keep track of the new mode for more than one crtc.
7643 * Hence simply check whether any bit is set in modeset_pipes in all the
7644 * pieces of code that are not yet converted to deal with mutliple crtcs
7645 * changing their mode at the same time. */
7646 adjusted_mode
= NULL
;
7647 if (modeset_pipes
) {
7648 adjusted_mode
= intel_modeset_adjusted_mode(crtc
, mode
);
7649 if (IS_ERR(adjusted_mode
)) {
7654 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
7655 if (intel_crtc
->base
.enabled
)
7656 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
7659 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7660 * to set it here already despite that we pass it down the callchain.
7665 /* Only after disabling all output pipelines that will be changed can we
7666 * update the the output configuration. */
7667 intel_modeset_update_state(dev
, prepare_pipes
);
7669 if (dev_priv
->display
.modeset_global_resources
)
7670 dev_priv
->display
.modeset_global_resources(dev
);
7672 /* Set up the DPLL and any encoders state that needs to adjust or depend
7675 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
7676 ret
= !intel_crtc_mode_set(&intel_crtc
->base
,
7677 mode
, adjusted_mode
,
7682 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7684 if (encoder
->crtc
!= &intel_crtc
->base
)
7687 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
7688 encoder
->base
.id
, drm_get_encoder_name(encoder
),
7689 mode
->base
.id
, mode
->name
);
7690 encoder_funcs
= encoder
->helper_private
;
7691 encoder_funcs
->mode_set(encoder
, mode
, adjusted_mode
);
7695 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7696 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
)
7697 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
7699 if (modeset_pipes
) {
7700 /* Store real post-adjustment hardware mode. */
7701 crtc
->hwmode
= *adjusted_mode
;
7703 /* Calculate and store various constants which
7704 * are later needed by vblank and swap-completion
7705 * timestamping. They are derived from true hwmode.
7707 drm_calc_timestamping_constants(crtc
);
7710 /* FIXME: add subpixel order */
7712 drm_mode_destroy(dev
, adjusted_mode
);
7713 if (!ret
&& crtc
->enabled
) {
7714 crtc
->hwmode
= saved_hwmode
;
7715 crtc
->mode
= saved_mode
;
7717 intel_modeset_check_state(dev
);
7723 #undef for_each_intel_crtc_masked
7725 static void intel_set_config_free(struct intel_set_config
*config
)
7730 kfree(config
->save_connector_encoders
);
7731 kfree(config
->save_encoder_crtcs
);
7735 static int intel_set_config_save_state(struct drm_device
*dev
,
7736 struct intel_set_config
*config
)
7738 struct drm_encoder
*encoder
;
7739 struct drm_connector
*connector
;
7742 config
->save_encoder_crtcs
=
7743 kcalloc(dev
->mode_config
.num_encoder
,
7744 sizeof(struct drm_crtc
*), GFP_KERNEL
);
7745 if (!config
->save_encoder_crtcs
)
7748 config
->save_connector_encoders
=
7749 kcalloc(dev
->mode_config
.num_connector
,
7750 sizeof(struct drm_encoder
*), GFP_KERNEL
);
7751 if (!config
->save_connector_encoders
)
7754 /* Copy data. Note that driver private data is not affected.
7755 * Should anything bad happen only the expected state is
7756 * restored, not the drivers personal bookkeeping.
7759 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
7760 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
7764 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
7765 config
->save_connector_encoders
[count
++] = connector
->encoder
;
7771 static void intel_set_config_restore_state(struct drm_device
*dev
,
7772 struct intel_set_config
*config
)
7774 struct intel_encoder
*encoder
;
7775 struct intel_connector
*connector
;
7779 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
7781 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
7785 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
7786 connector
->new_encoder
=
7787 to_intel_encoder(config
->save_connector_encoders
[count
++]);
7792 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
7793 struct intel_set_config
*config
)
7796 /* We should be able to check here if the fb has the same properties
7797 * and then just flip_or_move it */
7798 if (set
->crtc
->fb
!= set
->fb
) {
7799 /* If we have no fb then treat it as a full mode set */
7800 if (set
->crtc
->fb
== NULL
) {
7801 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7802 config
->mode_changed
= true;
7803 } else if (set
->fb
== NULL
) {
7804 config
->mode_changed
= true;
7805 } else if (set
->fb
->depth
!= set
->crtc
->fb
->depth
) {
7806 config
->mode_changed
= true;
7807 } else if (set
->fb
->bits_per_pixel
!=
7808 set
->crtc
->fb
->bits_per_pixel
) {
7809 config
->mode_changed
= true;
7811 config
->fb_changed
= true;
7814 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
7815 config
->fb_changed
= true;
7817 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
7818 DRM_DEBUG_KMS("modes are different, full mode set\n");
7819 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
7820 drm_mode_debug_printmodeline(set
->mode
);
7821 config
->mode_changed
= true;
7826 intel_modeset_stage_output_state(struct drm_device
*dev
,
7827 struct drm_mode_set
*set
,
7828 struct intel_set_config
*config
)
7830 struct drm_crtc
*new_crtc
;
7831 struct intel_connector
*connector
;
7832 struct intel_encoder
*encoder
;
7835 /* The upper layers ensure that we either disabl a crtc or have a list
7836 * of connectors. For paranoia, double-check this. */
7837 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
7838 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
7841 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7843 /* Otherwise traverse passed in connector list and get encoders
7845 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7846 if (set
->connectors
[ro
] == &connector
->base
) {
7847 connector
->new_encoder
= connector
->encoder
;
7852 /* If we disable the crtc, disable all its connectors. Also, if
7853 * the connector is on the changing crtc but not on the new
7854 * connector list, disable it. */
7855 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
7856 connector
->base
.encoder
&&
7857 connector
->base
.encoder
->crtc
== set
->crtc
) {
7858 connector
->new_encoder
= NULL
;
7860 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7861 connector
->base
.base
.id
,
7862 drm_get_connector_name(&connector
->base
));
7866 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
7867 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7868 config
->mode_changed
= true;
7871 /* Disable all disconnected encoders. */
7872 if (connector
->base
.status
== connector_status_disconnected
)
7873 connector
->new_encoder
= NULL
;
7875 /* connector->new_encoder is now updated for all connectors. */
7877 /* Update crtc of enabled connectors. */
7879 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
7881 if (!connector
->new_encoder
)
7884 new_crtc
= connector
->new_encoder
->base
.crtc
;
7886 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
7887 if (set
->connectors
[ro
] == &connector
->base
)
7888 new_crtc
= set
->crtc
;
7891 /* Make sure the new CRTC will work with the encoder */
7892 if (!intel_encoder_crtc_ok(&connector
->new_encoder
->base
,
7896 connector
->encoder
->new_crtc
= to_intel_crtc(new_crtc
);
7898 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7899 connector
->base
.base
.id
,
7900 drm_get_connector_name(&connector
->base
),
7904 /* Check for any encoders that needs to be disabled. */
7905 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
7907 list_for_each_entry(connector
,
7908 &dev
->mode_config
.connector_list
,
7910 if (connector
->new_encoder
== encoder
) {
7911 WARN_ON(!connector
->new_encoder
->new_crtc
);
7916 encoder
->new_crtc
= NULL
;
7918 /* Only now check for crtc changes so we don't miss encoders
7919 * that will be disabled. */
7920 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
7921 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7922 config
->mode_changed
= true;
7925 /* Now we've also updated encoder->new_crtc for all encoders. */
7930 static int intel_crtc_set_config(struct drm_mode_set
*set
)
7932 struct drm_device
*dev
;
7933 struct drm_mode_set save_set
;
7934 struct intel_set_config
*config
;
7939 BUG_ON(!set
->crtc
->helper_private
);
7944 /* The fb helper likes to play gross jokes with ->mode_set_config.
7945 * Unfortunately the crtc helper doesn't do much at all for this case,
7946 * so we have to cope with this madness until the fb helper is fixed up. */
7947 if (set
->fb
&& set
->num_connectors
== 0)
7951 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7952 set
->crtc
->base
.id
, set
->fb
->base
.id
,
7953 (int)set
->num_connectors
, set
->x
, set
->y
);
7955 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
7958 dev
= set
->crtc
->dev
;
7961 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
7965 ret
= intel_set_config_save_state(dev
, config
);
7969 save_set
.crtc
= set
->crtc
;
7970 save_set
.mode
= &set
->crtc
->mode
;
7971 save_set
.x
= set
->crtc
->x
;
7972 save_set
.y
= set
->crtc
->y
;
7973 save_set
.fb
= set
->crtc
->fb
;
7975 /* Compute whether we need a full modeset, only an fb base update or no
7976 * change at all. In the future we might also check whether only the
7977 * mode changed, e.g. for LVDS where we only change the panel fitter in
7979 intel_set_config_compute_mode_changes(set
, config
);
7981 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
7985 if (config
->mode_changed
) {
7987 DRM_DEBUG_KMS("attempting to set mode from"
7989 drm_mode_debug_printmodeline(set
->mode
);
7992 if (!intel_set_mode(set
->crtc
, set
->mode
,
7993 set
->x
, set
->y
, set
->fb
)) {
7994 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7995 set
->crtc
->base
.id
);
7999 } else if (config
->fb_changed
) {
8000 ret
= intel_pipe_set_base(set
->crtc
,
8001 set
->x
, set
->y
, set
->fb
);
8004 intel_set_config_free(config
);
8009 intel_set_config_restore_state(dev
, config
);
8011 /* Try to restore the config */
8012 if (config
->mode_changed
&&
8013 !intel_set_mode(save_set
.crtc
, save_set
.mode
,
8014 save_set
.x
, save_set
.y
, save_set
.fb
))
8015 DRM_ERROR("failed to restore config after modeset failure\n");
8018 intel_set_config_free(config
);
8022 static const struct drm_crtc_funcs intel_crtc_funcs
= {
8023 .cursor_set
= intel_crtc_cursor_set
,
8024 .cursor_move
= intel_crtc_cursor_move
,
8025 .gamma_set
= intel_crtc_gamma_set
,
8026 .set_config
= intel_crtc_set_config
,
8027 .destroy
= intel_crtc_destroy
,
8028 .page_flip
= intel_crtc_page_flip
,
8031 static void intel_cpu_pll_init(struct drm_device
*dev
)
8033 if (IS_HASWELL(dev
))
8034 intel_ddi_pll_init(dev
);
8037 static void intel_pch_pll_init(struct drm_device
*dev
)
8039 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8042 if (dev_priv
->num_pch_pll
== 0) {
8043 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8047 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
8048 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
8049 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
8050 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
8054 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
8056 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
8057 struct intel_crtc
*intel_crtc
;
8060 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
8061 if (intel_crtc
== NULL
)
8064 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
8066 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
8067 for (i
= 0; i
< 256; i
++) {
8068 intel_crtc
->lut_r
[i
] = i
;
8069 intel_crtc
->lut_g
[i
] = i
;
8070 intel_crtc
->lut_b
[i
] = i
;
8073 /* Swap pipes & planes for FBC on pre-965 */
8074 intel_crtc
->pipe
= pipe
;
8075 intel_crtc
->plane
= pipe
;
8076 intel_crtc
->cpu_transcoder
= pipe
;
8077 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
8078 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8079 intel_crtc
->plane
= !pipe
;
8082 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
8083 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
8084 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
8085 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
8087 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
8089 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
8092 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
8093 struct drm_file
*file
)
8095 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
8096 struct drm_mode_object
*drmmode_obj
;
8097 struct intel_crtc
*crtc
;
8099 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
8102 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
8103 DRM_MODE_OBJECT_CRTC
);
8106 DRM_ERROR("no such CRTC id\n");
8110 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
8111 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
8116 static int intel_encoder_clones(struct intel_encoder
*encoder
)
8118 struct drm_device
*dev
= encoder
->base
.dev
;
8119 struct intel_encoder
*source_encoder
;
8123 list_for_each_entry(source_encoder
,
8124 &dev
->mode_config
.encoder_list
, base
.head
) {
8126 if (encoder
== source_encoder
)
8127 index_mask
|= (1 << entry
);
8129 /* Intel hw has only one MUX where enocoders could be cloned. */
8130 if (encoder
->cloneable
&& source_encoder
->cloneable
)
8131 index_mask
|= (1 << entry
);
8139 static bool has_edp_a(struct drm_device
*dev
)
8141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8143 if (!IS_MOBILE(dev
))
8146 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
8150 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
8156 static void intel_setup_outputs(struct drm_device
*dev
)
8158 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8159 struct intel_encoder
*encoder
;
8160 bool dpd_is_edp
= false;
8163 has_lvds
= intel_lvds_init(dev
);
8164 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
8165 /* disable the panel fitter on everything but LVDS */
8166 I915_WRITE(PFIT_CONTROL
, 0);
8169 if (HAS_PCH_SPLIT(dev
)) {
8170 dpd_is_edp
= intel_dpd_is_edp(dev
);
8173 intel_dp_init(dev
, DP_A
, PORT_A
);
8175 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
8176 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8179 intel_crt_init(dev
);
8181 if (IS_HASWELL(dev
)) {
8184 /* Haswell uses DDI functions to detect digital outputs */
8185 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
8186 /* DDI A only supports eDP */
8188 intel_ddi_init(dev
, PORT_A
);
8190 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8192 found
= I915_READ(SFUSE_STRAP
);
8194 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
8195 intel_ddi_init(dev
, PORT_B
);
8196 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
8197 intel_ddi_init(dev
, PORT_C
);
8198 if (found
& SFUSE_STRAP_DDID_DETECTED
)
8199 intel_ddi_init(dev
, PORT_D
);
8200 } else if (HAS_PCH_SPLIT(dev
)) {
8203 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
8204 /* PCH SDVOB multiplex with HDMIB */
8205 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
8207 intel_hdmi_init(dev
, HDMIB
, PORT_B
);
8208 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
8209 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
8212 if (I915_READ(HDMIC
) & PORT_DETECTED
)
8213 intel_hdmi_init(dev
, HDMIC
, PORT_C
);
8215 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
8216 intel_hdmi_init(dev
, HDMID
, PORT_D
);
8218 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
8219 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
8221 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
8222 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
8223 } else if (IS_VALLEYVIEW(dev
)) {
8226 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8227 if (I915_READ(DP_C
) & DP_DETECTED
)
8228 intel_dp_init(dev
, DP_C
, PORT_C
);
8230 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
8231 /* SDVOB multiplex with HDMIB */
8232 found
= intel_sdvo_init(dev
, SDVOB
, true);
8234 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
8235 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
8236 intel_dp_init(dev
, DP_B
, PORT_B
);
8239 if (I915_READ(SDVOC
) & PORT_DETECTED
)
8240 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
8242 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
8245 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8246 DRM_DEBUG_KMS("probing SDVOB\n");
8247 found
= intel_sdvo_init(dev
, SDVOB
, true);
8248 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
8249 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8250 intel_hdmi_init(dev
, SDVOB
, PORT_B
);
8253 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
8254 DRM_DEBUG_KMS("probing DP_B\n");
8255 intel_dp_init(dev
, DP_B
, PORT_B
);
8259 /* Before G4X SDVOC doesn't have its own detect register */
8261 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
8262 DRM_DEBUG_KMS("probing SDVOC\n");
8263 found
= intel_sdvo_init(dev
, SDVOC
, false);
8266 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
8268 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
8269 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8270 intel_hdmi_init(dev
, SDVOC
, PORT_C
);
8272 if (SUPPORTS_INTEGRATED_DP(dev
)) {
8273 DRM_DEBUG_KMS("probing DP_C\n");
8274 intel_dp_init(dev
, DP_C
, PORT_C
);
8278 if (SUPPORTS_INTEGRATED_DP(dev
) &&
8279 (I915_READ(DP_D
) & DP_DETECTED
)) {
8280 DRM_DEBUG_KMS("probing DP_D\n");
8281 intel_dp_init(dev
, DP_D
, PORT_D
);
8283 } else if (IS_GEN2(dev
))
8284 intel_dvo_init(dev
);
8286 if (SUPPORTS_TV(dev
))
8289 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
8290 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
8291 encoder
->base
.possible_clones
=
8292 intel_encoder_clones(encoder
);
8295 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8296 ironlake_init_pch_refclk(dev
);
8299 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
8301 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8303 drm_framebuffer_cleanup(fb
);
8304 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
8309 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
8310 struct drm_file
*file
,
8311 unsigned int *handle
)
8313 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
8314 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
8316 return drm_gem_handle_create(file
, &obj
->base
, handle
);
8319 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
8320 .destroy
= intel_user_framebuffer_destroy
,
8321 .create_handle
= intel_user_framebuffer_create_handle
,
8324 int intel_framebuffer_init(struct drm_device
*dev
,
8325 struct intel_framebuffer
*intel_fb
,
8326 struct drm_mode_fb_cmd2
*mode_cmd
,
8327 struct drm_i915_gem_object
*obj
)
8331 if (obj
->tiling_mode
== I915_TILING_Y
)
8334 if (mode_cmd
->pitches
[0] & 63)
8337 switch (mode_cmd
->pixel_format
) {
8338 case DRM_FORMAT_RGB332
:
8339 case DRM_FORMAT_RGB565
:
8340 case DRM_FORMAT_XRGB8888
:
8341 case DRM_FORMAT_XBGR8888
:
8342 case DRM_FORMAT_ARGB8888
:
8343 case DRM_FORMAT_XRGB2101010
:
8344 case DRM_FORMAT_ARGB2101010
:
8345 /* RGB formats are common across chipsets */
8347 case DRM_FORMAT_YUYV
:
8348 case DRM_FORMAT_UYVY
:
8349 case DRM_FORMAT_YVYU
:
8350 case DRM_FORMAT_VYUY
:
8353 DRM_DEBUG_KMS("unsupported pixel format %u\n",
8354 mode_cmd
->pixel_format
);
8358 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
8360 DRM_ERROR("framebuffer init failed %d\n", ret
);
8364 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
8365 intel_fb
->obj
= obj
;
8369 static struct drm_framebuffer
*
8370 intel_user_framebuffer_create(struct drm_device
*dev
,
8371 struct drm_file
*filp
,
8372 struct drm_mode_fb_cmd2
*mode_cmd
)
8374 struct drm_i915_gem_object
*obj
;
8376 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
8377 mode_cmd
->handles
[0]));
8378 if (&obj
->base
== NULL
)
8379 return ERR_PTR(-ENOENT
);
8381 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
8384 static const struct drm_mode_config_funcs intel_mode_funcs
= {
8385 .fb_create
= intel_user_framebuffer_create
,
8386 .output_poll_changed
= intel_fb_output_poll_changed
,
8389 /* Set up chip specific display functions */
8390 static void intel_init_display(struct drm_device
*dev
)
8392 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8394 /* We always want a DPMS function */
8395 if (IS_HASWELL(dev
)) {
8396 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
8397 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
8398 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
8399 dev_priv
->display
.off
= haswell_crtc_off
;
8400 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8401 } else if (HAS_PCH_SPLIT(dev
)) {
8402 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
8403 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
8404 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
8405 dev_priv
->display
.off
= ironlake_crtc_off
;
8406 dev_priv
->display
.update_plane
= ironlake_update_plane
;
8408 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
8409 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
8410 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
8411 dev_priv
->display
.off
= i9xx_crtc_off
;
8412 dev_priv
->display
.update_plane
= i9xx_update_plane
;
8415 /* Returns the core display clock speed */
8416 if (IS_VALLEYVIEW(dev
))
8417 dev_priv
->display
.get_display_clock_speed
=
8418 valleyview_get_display_clock_speed
;
8419 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
8420 dev_priv
->display
.get_display_clock_speed
=
8421 i945_get_display_clock_speed
;
8422 else if (IS_I915G(dev
))
8423 dev_priv
->display
.get_display_clock_speed
=
8424 i915_get_display_clock_speed
;
8425 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
8426 dev_priv
->display
.get_display_clock_speed
=
8427 i9xx_misc_get_display_clock_speed
;
8428 else if (IS_I915GM(dev
))
8429 dev_priv
->display
.get_display_clock_speed
=
8430 i915gm_get_display_clock_speed
;
8431 else if (IS_I865G(dev
))
8432 dev_priv
->display
.get_display_clock_speed
=
8433 i865_get_display_clock_speed
;
8434 else if (IS_I85X(dev
))
8435 dev_priv
->display
.get_display_clock_speed
=
8436 i855_get_display_clock_speed
;
8438 dev_priv
->display
.get_display_clock_speed
=
8439 i830_get_display_clock_speed
;
8441 if (HAS_PCH_SPLIT(dev
)) {
8443 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
8444 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8445 } else if (IS_GEN6(dev
)) {
8446 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
8447 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8448 } else if (IS_IVYBRIDGE(dev
)) {
8449 /* FIXME: detect B0+ stepping and use auto training */
8450 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
8451 dev_priv
->display
.write_eld
= ironlake_write_eld
;
8452 dev_priv
->display
.modeset_global_resources
=
8453 ivb_modeset_global_resources
;
8454 } else if (IS_HASWELL(dev
)) {
8455 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
8456 dev_priv
->display
.write_eld
= haswell_write_eld
;
8458 dev_priv
->display
.update_wm
= NULL
;
8459 } else if (IS_G4X(dev
)) {
8460 dev_priv
->display
.write_eld
= g4x_write_eld
;
8463 /* Default just returns -ENODEV to indicate unsupported */
8464 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
8466 switch (INTEL_INFO(dev
)->gen
) {
8468 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
8472 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
8477 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
8481 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
8484 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
8490 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8491 * resume, or other times. This quirk makes sure that's the case for
8494 static void quirk_pipea_force(struct drm_device
*dev
)
8496 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8498 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
8499 DRM_INFO("applying pipe a force quirk\n");
8503 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8505 static void quirk_ssc_force_disable(struct drm_device
*dev
)
8507 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8508 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
8509 DRM_INFO("applying lvds SSC disable quirk\n");
8513 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8516 static void quirk_invert_brightness(struct drm_device
*dev
)
8518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8519 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
8520 DRM_INFO("applying inverted panel brightness quirk\n");
8523 struct intel_quirk
{
8525 int subsystem_vendor
;
8526 int subsystem_device
;
8527 void (*hook
)(struct drm_device
*dev
);
8530 static struct intel_quirk intel_quirks
[] = {
8531 /* HP Mini needs pipe A force quirk (LP: #322104) */
8532 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
8534 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8535 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
8537 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8538 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
8540 /* 830/845 need to leave pipe A & dpll A up */
8541 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8542 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
8544 /* Lenovo U160 cannot use SSC on LVDS */
8545 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
8547 /* Sony Vaio Y cannot use SSC on LVDS */
8548 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
8550 /* Acer Aspire 5734Z must invert backlight brightness */
8551 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
8554 static void intel_init_quirks(struct drm_device
*dev
)
8556 struct pci_dev
*d
= dev
->pdev
;
8559 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
8560 struct intel_quirk
*q
= &intel_quirks
[i
];
8562 if (d
->device
== q
->device
&&
8563 (d
->subsystem_vendor
== q
->subsystem_vendor
||
8564 q
->subsystem_vendor
== PCI_ANY_ID
) &&
8565 (d
->subsystem_device
== q
->subsystem_device
||
8566 q
->subsystem_device
== PCI_ANY_ID
))
8571 /* Disable the VGA plane that we never use */
8572 static void i915_disable_vga(struct drm_device
*dev
)
8574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8578 if (HAS_PCH_SPLIT(dev
))
8579 vga_reg
= CPU_VGACNTRL
;
8583 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8584 outb(SR01
, VGA_SR_INDEX
);
8585 sr1
= inb(VGA_SR_DATA
);
8586 outb(sr1
| 1<<5, VGA_SR_DATA
);
8587 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
8590 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
8591 POSTING_READ(vga_reg
);
8594 void intel_modeset_init_hw(struct drm_device
*dev
)
8596 /* We attempt to init the necessary power wells early in the initialization
8597 * time, so the subsystems that expect power to be enabled can work.
8599 intel_init_power_wells(dev
);
8601 intel_prepare_ddi(dev
);
8603 intel_init_clock_gating(dev
);
8605 mutex_lock(&dev
->struct_mutex
);
8606 intel_enable_gt_powersave(dev
);
8607 mutex_unlock(&dev
->struct_mutex
);
8610 void intel_modeset_init(struct drm_device
*dev
)
8612 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8615 drm_mode_config_init(dev
);
8617 dev
->mode_config
.min_width
= 0;
8618 dev
->mode_config
.min_height
= 0;
8620 dev
->mode_config
.preferred_depth
= 24;
8621 dev
->mode_config
.prefer_shadow
= 1;
8623 dev
->mode_config
.funcs
= &intel_mode_funcs
;
8625 intel_init_quirks(dev
);
8629 intel_init_display(dev
);
8632 dev
->mode_config
.max_width
= 2048;
8633 dev
->mode_config
.max_height
= 2048;
8634 } else if (IS_GEN3(dev
)) {
8635 dev
->mode_config
.max_width
= 4096;
8636 dev
->mode_config
.max_height
= 4096;
8638 dev
->mode_config
.max_width
= 8192;
8639 dev
->mode_config
.max_height
= 8192;
8641 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
8643 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8644 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
8646 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
8647 intel_crtc_init(dev
, i
);
8648 ret
= intel_plane_init(dev
, i
);
8650 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
8653 intel_cpu_pll_init(dev
);
8654 intel_pch_pll_init(dev
);
8656 /* Just disable it once at startup */
8657 i915_disable_vga(dev
);
8658 intel_setup_outputs(dev
);
8662 intel_connector_break_all_links(struct intel_connector
*connector
)
8664 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8665 connector
->base
.encoder
= NULL
;
8666 connector
->encoder
->connectors_active
= false;
8667 connector
->encoder
->base
.crtc
= NULL
;
8670 static void intel_enable_pipe_a(struct drm_device
*dev
)
8672 struct intel_connector
*connector
;
8673 struct drm_connector
*crt
= NULL
;
8674 struct intel_load_detect_pipe load_detect_temp
;
8676 /* We can't just switch on the pipe A, we need to set things up with a
8677 * proper mode and output configuration. As a gross hack, enable pipe A
8678 * by enabling the load detect pipe once. */
8679 list_for_each_entry(connector
,
8680 &dev
->mode_config
.connector_list
,
8682 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
8683 crt
= &connector
->base
;
8691 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
))
8692 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
8698 intel_check_plane_mapping(struct intel_crtc
*crtc
)
8700 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
8703 if (dev_priv
->num_pipe
== 1)
8706 reg
= DSPCNTR(!crtc
->plane
);
8707 val
= I915_READ(reg
);
8709 if ((val
& DISPLAY_PLANE_ENABLE
) &&
8710 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
8716 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
8718 struct drm_device
*dev
= crtc
->base
.dev
;
8719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8722 /* Clear any frame start delays used for debugging left by the BIOS */
8723 reg
= PIPECONF(crtc
->cpu_transcoder
);
8724 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
8726 /* We need to sanitize the plane -> pipe mapping first because this will
8727 * disable the crtc (and hence change the state) if it is wrong. Note
8728 * that gen4+ has a fixed plane -> pipe mapping. */
8729 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
8730 struct intel_connector
*connector
;
8733 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8734 crtc
->base
.base
.id
);
8736 /* Pipe has the wrong plane attached and the plane is active.
8737 * Temporarily change the plane mapping and disable everything
8739 plane
= crtc
->plane
;
8740 crtc
->plane
= !plane
;
8741 dev_priv
->display
.crtc_disable(&crtc
->base
);
8742 crtc
->plane
= plane
;
8744 /* ... and break all links. */
8745 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8747 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
8750 intel_connector_break_all_links(connector
);
8753 WARN_ON(crtc
->active
);
8754 crtc
->base
.enabled
= false;
8757 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
8758 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
8759 /* BIOS forgot to enable pipe A, this mostly happens after
8760 * resume. Force-enable the pipe to fix this, the update_dpms
8761 * call below we restore the pipe to the right state, but leave
8762 * the required bits on. */
8763 intel_enable_pipe_a(dev
);
8766 /* Adjust the state of the output pipe according to whether we
8767 * have active connectors/encoders. */
8768 intel_crtc_update_dpms(&crtc
->base
);
8770 if (crtc
->active
!= crtc
->base
.enabled
) {
8771 struct intel_encoder
*encoder
;
8773 /* This can happen either due to bugs in the get_hw_state
8774 * functions or because the pipe is force-enabled due to the
8776 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8778 crtc
->base
.enabled
? "enabled" : "disabled",
8779 crtc
->active
? "enabled" : "disabled");
8781 crtc
->base
.enabled
= crtc
->active
;
8783 /* Because we only establish the connector -> encoder ->
8784 * crtc links if something is active, this means the
8785 * crtc is now deactivated. Break the links. connector
8786 * -> encoder links are only establish when things are
8787 * actually up, hence no need to break them. */
8788 WARN_ON(crtc
->active
);
8790 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
8791 WARN_ON(encoder
->connectors_active
);
8792 encoder
->base
.crtc
= NULL
;
8797 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
8799 struct intel_connector
*connector
;
8800 struct drm_device
*dev
= encoder
->base
.dev
;
8802 /* We need to check both for a crtc link (meaning that the
8803 * encoder is active and trying to read from a pipe) and the
8804 * pipe itself being active. */
8805 bool has_active_crtc
= encoder
->base
.crtc
&&
8806 to_intel_crtc(encoder
->base
.crtc
)->active
;
8808 if (encoder
->connectors_active
&& !has_active_crtc
) {
8809 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8810 encoder
->base
.base
.id
,
8811 drm_get_encoder_name(&encoder
->base
));
8813 /* Connector is active, but has no active pipe. This is
8814 * fallout from our resume register restoring. Disable
8815 * the encoder manually again. */
8816 if (encoder
->base
.crtc
) {
8817 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8818 encoder
->base
.base
.id
,
8819 drm_get_encoder_name(&encoder
->base
));
8820 encoder
->disable(encoder
);
8823 /* Inconsistent output/port/pipe state happens presumably due to
8824 * a bug in one of the get_hw_state functions. Or someplace else
8825 * in our code, like the register restore mess on resume. Clamp
8826 * things to off as a safer default. */
8827 list_for_each_entry(connector
,
8828 &dev
->mode_config
.connector_list
,
8830 if (connector
->encoder
!= encoder
)
8833 intel_connector_break_all_links(connector
);
8836 /* Enabled encoders without active connectors will be fixed in
8837 * the crtc fixup. */
8840 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8841 * and i915 state tracking structures. */
8842 void intel_modeset_setup_hw_state(struct drm_device
*dev
)
8844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8847 struct intel_crtc
*crtc
;
8848 struct intel_encoder
*encoder
;
8849 struct intel_connector
*connector
;
8851 if (IS_HASWELL(dev
)) {
8852 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8854 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8855 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8856 case TRANS_DDI_EDP_INPUT_A_ON
:
8857 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8860 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8863 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8868 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8869 crtc
->cpu_transcoder
= TRANSCODER_EDP
;
8871 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8876 for_each_pipe(pipe
) {
8877 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8879 tmp
= I915_READ(PIPECONF(crtc
->cpu_transcoder
));
8880 if (tmp
& PIPECONF_ENABLE
)
8881 crtc
->active
= true;
8883 crtc
->active
= false;
8885 crtc
->base
.enabled
= crtc
->active
;
8887 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8889 crtc
->active
? "enabled" : "disabled");
8892 if (IS_HASWELL(dev
))
8893 intel_ddi_setup_hw_pll_state(dev
);
8895 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8899 if (encoder
->get_hw_state(encoder
, &pipe
)) {
8900 encoder
->base
.crtc
=
8901 dev_priv
->pipe_to_crtc_mapping
[pipe
];
8903 encoder
->base
.crtc
= NULL
;
8906 encoder
->connectors_active
= false;
8907 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8908 encoder
->base
.base
.id
,
8909 drm_get_encoder_name(&encoder
->base
),
8910 encoder
->base
.crtc
? "enabled" : "disabled",
8914 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
8916 if (connector
->get_hw_state(connector
)) {
8917 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
8918 connector
->encoder
->connectors_active
= true;
8919 connector
->base
.encoder
= &connector
->encoder
->base
;
8921 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
8922 connector
->base
.encoder
= NULL
;
8924 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8925 connector
->base
.base
.id
,
8926 drm_get_connector_name(&connector
->base
),
8927 connector
->base
.encoder
? "enabled" : "disabled");
8930 /* HW state is read out, now we need to sanitize this mess. */
8931 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
,
8933 intel_sanitize_encoder(encoder
);
8936 for_each_pipe(pipe
) {
8937 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
8938 intel_sanitize_crtc(crtc
);
8941 intel_modeset_update_staged_output_state(dev
);
8943 intel_modeset_check_state(dev
);
8945 drm_mode_config_reset(dev
);
8948 void intel_modeset_gem_init(struct drm_device
*dev
)
8950 intel_modeset_init_hw(dev
);
8952 intel_setup_overlay(dev
);
8954 intel_modeset_setup_hw_state(dev
);
8957 void intel_modeset_cleanup(struct drm_device
*dev
)
8959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8960 struct drm_crtc
*crtc
;
8961 struct intel_crtc
*intel_crtc
;
8963 drm_kms_helper_poll_fini(dev
);
8964 mutex_lock(&dev
->struct_mutex
);
8966 intel_unregister_dsm_handler();
8969 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
8970 /* Skip inactive CRTCs */
8974 intel_crtc
= to_intel_crtc(crtc
);
8975 intel_increase_pllclock(crtc
);
8978 intel_disable_fbc(dev
);
8980 intel_disable_gt_powersave(dev
);
8982 ironlake_teardown_rc6(dev
);
8984 if (IS_VALLEYVIEW(dev
))
8987 mutex_unlock(&dev
->struct_mutex
);
8989 /* Disable the irq before mode object teardown, for the irq might
8990 * enqueue unpin/hotplug work. */
8991 drm_irq_uninstall(dev
);
8992 cancel_work_sync(&dev_priv
->hotplug_work
);
8993 cancel_work_sync(&dev_priv
->rps
.work
);
8995 /* flush any delayed tasks or pending work */
8996 flush_scheduled_work();
8998 drm_mode_config_cleanup(dev
);
9002 * Return which encoder is currently attached for connector.
9004 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
9006 return &intel_attached_encoder(connector
)->base
;
9009 void intel_connector_attach_encoder(struct intel_connector
*connector
,
9010 struct intel_encoder
*encoder
)
9012 connector
->encoder
= encoder
;
9013 drm_mode_connector_attach_encoder(&connector
->base
,
9018 * set vga decode state - true == enable VGA decode
9020 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
9022 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9025 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
9027 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
9029 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
9030 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
9034 #ifdef CONFIG_DEBUG_FS
9035 #include <linux/seq_file.h>
9037 struct intel_display_error_state
{
9038 struct intel_cursor_error_state
{
9043 } cursor
[I915_MAX_PIPES
];
9045 struct intel_pipe_error_state
{
9055 } pipe
[I915_MAX_PIPES
];
9057 struct intel_plane_error_state
{
9065 } plane
[I915_MAX_PIPES
];
9068 struct intel_display_error_state
*
9069 intel_display_capture_error_state(struct drm_device
*dev
)
9071 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9072 struct intel_display_error_state
*error
;
9073 enum transcoder cpu_transcoder
;
9076 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
9081 cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
, i
);
9083 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
9084 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
9085 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
9087 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
9088 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
9089 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
9090 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
9091 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
9092 if (INTEL_INFO(dev
)->gen
>= 4) {
9093 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
9094 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
9097 error
->pipe
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
9098 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
9099 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
9100 error
->pipe
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
9101 error
->pipe
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
9102 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
9103 error
->pipe
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
9104 error
->pipe
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
9111 intel_display_print_error_state(struct seq_file
*m
,
9112 struct drm_device
*dev
,
9113 struct intel_display_error_state
*error
)
9115 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
9118 seq_printf(m
, "Num Pipes: %d\n", dev_priv
->num_pipe
);
9120 seq_printf(m
, "Pipe [%d]:\n", i
);
9121 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
9122 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
9123 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
9124 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
9125 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
9126 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
9127 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
9128 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
9130 seq_printf(m
, "Plane [%d]:\n", i
);
9131 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
9132 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
9133 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
9134 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
9135 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
9136 if (INTEL_INFO(dev
)->gen
>= 4) {
9137 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
9138 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
9141 seq_printf(m
, "Cursor [%d]:\n", i
);
9142 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
9143 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
9144 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);