2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
52 DRM_FORMAT_XRGB8888, \
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2
[] = {
57 COMMON_PRIMARY_FORMATS
,
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4
[] = {
64 COMMON_PRIMARY_FORMATS
, \
67 DRM_FORMAT_XRGB2101010
,
68 DRM_FORMAT_ARGB2101010
,
69 DRM_FORMAT_XBGR2101010
,
70 DRM_FORMAT_ABGR2101010
,
74 static const uint32_t intel_cursor_formats
[] = {
78 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
80 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
81 struct intel_crtc_state
*pipe_config
);
82 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
83 struct intel_crtc_state
*pipe_config
);
85 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
86 int x
, int y
, struct drm_framebuffer
*old_fb
,
87 struct drm_atomic_state
*state
);
88 static int intel_framebuffer_init(struct drm_device
*dev
,
89 struct intel_framebuffer
*ifb
,
90 struct drm_mode_fb_cmd2
*mode_cmd
,
91 struct drm_i915_gem_object
*obj
);
92 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
93 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
94 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
95 struct intel_link_m_n
*m_n
,
96 struct intel_link_m_n
*m2_n2
);
97 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
98 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
99 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
100 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
101 const struct intel_crtc_state
*pipe_config
);
102 static void chv_prepare_pll(struct intel_crtc
*crtc
,
103 const struct intel_crtc_state
*pipe_config
);
104 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
);
105 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
);
107 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
109 if (!connector
->mst_port
)
110 return connector
->encoder
;
112 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
121 int p2_slow
, p2_fast
;
124 typedef struct intel_limit intel_limit_t
;
126 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
131 intel_pch_rawclk(struct drm_device
*dev
)
133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 WARN_ON(!HAS_PCH_SPLIT(dev
));
137 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
140 static inline u32
/* units of 100MHz */
141 intel_fdi_link_freq(struct drm_device
*dev
)
144 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
145 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
150 static const intel_limit_t intel_limits_i8xx_dac
= {
151 .dot
= { .min
= 25000, .max
= 350000 },
152 .vco
= { .min
= 908000, .max
= 1512000 },
153 .n
= { .min
= 2, .max
= 16 },
154 .m
= { .min
= 96, .max
= 140 },
155 .m1
= { .min
= 18, .max
= 26 },
156 .m2
= { .min
= 6, .max
= 16 },
157 .p
= { .min
= 4, .max
= 128 },
158 .p1
= { .min
= 2, .max
= 33 },
159 .p2
= { .dot_limit
= 165000,
160 .p2_slow
= 4, .p2_fast
= 2 },
163 static const intel_limit_t intel_limits_i8xx_dvo
= {
164 .dot
= { .min
= 25000, .max
= 350000 },
165 .vco
= { .min
= 908000, .max
= 1512000 },
166 .n
= { .min
= 2, .max
= 16 },
167 .m
= { .min
= 96, .max
= 140 },
168 .m1
= { .min
= 18, .max
= 26 },
169 .m2
= { .min
= 6, .max
= 16 },
170 .p
= { .min
= 4, .max
= 128 },
171 .p1
= { .min
= 2, .max
= 33 },
172 .p2
= { .dot_limit
= 165000,
173 .p2_slow
= 4, .p2_fast
= 4 },
176 static const intel_limit_t intel_limits_i8xx_lvds
= {
177 .dot
= { .min
= 25000, .max
= 350000 },
178 .vco
= { .min
= 908000, .max
= 1512000 },
179 .n
= { .min
= 2, .max
= 16 },
180 .m
= { .min
= 96, .max
= 140 },
181 .m1
= { .min
= 18, .max
= 26 },
182 .m2
= { .min
= 6, .max
= 16 },
183 .p
= { .min
= 4, .max
= 128 },
184 .p1
= { .min
= 1, .max
= 6 },
185 .p2
= { .dot_limit
= 165000,
186 .p2_slow
= 14, .p2_fast
= 7 },
189 static const intel_limit_t intel_limits_i9xx_sdvo
= {
190 .dot
= { .min
= 20000, .max
= 400000 },
191 .vco
= { .min
= 1400000, .max
= 2800000 },
192 .n
= { .min
= 1, .max
= 6 },
193 .m
= { .min
= 70, .max
= 120 },
194 .m1
= { .min
= 8, .max
= 18 },
195 .m2
= { .min
= 3, .max
= 7 },
196 .p
= { .min
= 5, .max
= 80 },
197 .p1
= { .min
= 1, .max
= 8 },
198 .p2
= { .dot_limit
= 200000,
199 .p2_slow
= 10, .p2_fast
= 5 },
202 static const intel_limit_t intel_limits_i9xx_lvds
= {
203 .dot
= { .min
= 20000, .max
= 400000 },
204 .vco
= { .min
= 1400000, .max
= 2800000 },
205 .n
= { .min
= 1, .max
= 6 },
206 .m
= { .min
= 70, .max
= 120 },
207 .m1
= { .min
= 8, .max
= 18 },
208 .m2
= { .min
= 3, .max
= 7 },
209 .p
= { .min
= 7, .max
= 98 },
210 .p1
= { .min
= 1, .max
= 8 },
211 .p2
= { .dot_limit
= 112000,
212 .p2_slow
= 14, .p2_fast
= 7 },
216 static const intel_limit_t intel_limits_g4x_sdvo
= {
217 .dot
= { .min
= 25000, .max
= 270000 },
218 .vco
= { .min
= 1750000, .max
= 3500000},
219 .n
= { .min
= 1, .max
= 4 },
220 .m
= { .min
= 104, .max
= 138 },
221 .m1
= { .min
= 17, .max
= 23 },
222 .m2
= { .min
= 5, .max
= 11 },
223 .p
= { .min
= 10, .max
= 30 },
224 .p1
= { .min
= 1, .max
= 3},
225 .p2
= { .dot_limit
= 270000,
231 static const intel_limit_t intel_limits_g4x_hdmi
= {
232 .dot
= { .min
= 22000, .max
= 400000 },
233 .vco
= { .min
= 1750000, .max
= 3500000},
234 .n
= { .min
= 1, .max
= 4 },
235 .m
= { .min
= 104, .max
= 138 },
236 .m1
= { .min
= 16, .max
= 23 },
237 .m2
= { .min
= 5, .max
= 11 },
238 .p
= { .min
= 5, .max
= 80 },
239 .p1
= { .min
= 1, .max
= 8},
240 .p2
= { .dot_limit
= 165000,
241 .p2_slow
= 10, .p2_fast
= 5 },
244 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
245 .dot
= { .min
= 20000, .max
= 115000 },
246 .vco
= { .min
= 1750000, .max
= 3500000 },
247 .n
= { .min
= 1, .max
= 3 },
248 .m
= { .min
= 104, .max
= 138 },
249 .m1
= { .min
= 17, .max
= 23 },
250 .m2
= { .min
= 5, .max
= 11 },
251 .p
= { .min
= 28, .max
= 112 },
252 .p1
= { .min
= 2, .max
= 8 },
253 .p2
= { .dot_limit
= 0,
254 .p2_slow
= 14, .p2_fast
= 14
258 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
259 .dot
= { .min
= 80000, .max
= 224000 },
260 .vco
= { .min
= 1750000, .max
= 3500000 },
261 .n
= { .min
= 1, .max
= 3 },
262 .m
= { .min
= 104, .max
= 138 },
263 .m1
= { .min
= 17, .max
= 23 },
264 .m2
= { .min
= 5, .max
= 11 },
265 .p
= { .min
= 14, .max
= 42 },
266 .p1
= { .min
= 2, .max
= 6 },
267 .p2
= { .dot_limit
= 0,
268 .p2_slow
= 7, .p2_fast
= 7
272 static const intel_limit_t intel_limits_pineview_sdvo
= {
273 .dot
= { .min
= 20000, .max
= 400000},
274 .vco
= { .min
= 1700000, .max
= 3500000 },
275 /* Pineview's Ncounter is a ring counter */
276 .n
= { .min
= 3, .max
= 6 },
277 .m
= { .min
= 2, .max
= 256 },
278 /* Pineview only has one combined m divider, which we treat as m2. */
279 .m1
= { .min
= 0, .max
= 0 },
280 .m2
= { .min
= 0, .max
= 254 },
281 .p
= { .min
= 5, .max
= 80 },
282 .p1
= { .min
= 1, .max
= 8 },
283 .p2
= { .dot_limit
= 200000,
284 .p2_slow
= 10, .p2_fast
= 5 },
287 static const intel_limit_t intel_limits_pineview_lvds
= {
288 .dot
= { .min
= 20000, .max
= 400000 },
289 .vco
= { .min
= 1700000, .max
= 3500000 },
290 .n
= { .min
= 3, .max
= 6 },
291 .m
= { .min
= 2, .max
= 256 },
292 .m1
= { .min
= 0, .max
= 0 },
293 .m2
= { .min
= 0, .max
= 254 },
294 .p
= { .min
= 7, .max
= 112 },
295 .p1
= { .min
= 1, .max
= 8 },
296 .p2
= { .dot_limit
= 112000,
297 .p2_slow
= 14, .p2_fast
= 14 },
300 /* Ironlake / Sandybridge
302 * We calculate clock using (register_value + 2) for N/M1/M2, so here
303 * the range value for them is (actual_value - 2).
305 static const intel_limit_t intel_limits_ironlake_dac
= {
306 .dot
= { .min
= 25000, .max
= 350000 },
307 .vco
= { .min
= 1760000, .max
= 3510000 },
308 .n
= { .min
= 1, .max
= 5 },
309 .m
= { .min
= 79, .max
= 127 },
310 .m1
= { .min
= 12, .max
= 22 },
311 .m2
= { .min
= 5, .max
= 9 },
312 .p
= { .min
= 5, .max
= 80 },
313 .p1
= { .min
= 1, .max
= 8 },
314 .p2
= { .dot_limit
= 225000,
315 .p2_slow
= 10, .p2_fast
= 5 },
318 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
319 .dot
= { .min
= 25000, .max
= 350000 },
320 .vco
= { .min
= 1760000, .max
= 3510000 },
321 .n
= { .min
= 1, .max
= 3 },
322 .m
= { .min
= 79, .max
= 118 },
323 .m1
= { .min
= 12, .max
= 22 },
324 .m2
= { .min
= 5, .max
= 9 },
325 .p
= { .min
= 28, .max
= 112 },
326 .p1
= { .min
= 2, .max
= 8 },
327 .p2
= { .dot_limit
= 225000,
328 .p2_slow
= 14, .p2_fast
= 14 },
331 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
332 .dot
= { .min
= 25000, .max
= 350000 },
333 .vco
= { .min
= 1760000, .max
= 3510000 },
334 .n
= { .min
= 1, .max
= 3 },
335 .m
= { .min
= 79, .max
= 127 },
336 .m1
= { .min
= 12, .max
= 22 },
337 .m2
= { .min
= 5, .max
= 9 },
338 .p
= { .min
= 14, .max
= 56 },
339 .p1
= { .min
= 2, .max
= 8 },
340 .p2
= { .dot_limit
= 225000,
341 .p2_slow
= 7, .p2_fast
= 7 },
344 /* LVDS 100mhz refclk limits. */
345 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
346 .dot
= { .min
= 25000, .max
= 350000 },
347 .vco
= { .min
= 1760000, .max
= 3510000 },
348 .n
= { .min
= 1, .max
= 2 },
349 .m
= { .min
= 79, .max
= 126 },
350 .m1
= { .min
= 12, .max
= 22 },
351 .m2
= { .min
= 5, .max
= 9 },
352 .p
= { .min
= 28, .max
= 112 },
353 .p1
= { .min
= 2, .max
= 8 },
354 .p2
= { .dot_limit
= 225000,
355 .p2_slow
= 14, .p2_fast
= 14 },
358 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
359 .dot
= { .min
= 25000, .max
= 350000 },
360 .vco
= { .min
= 1760000, .max
= 3510000 },
361 .n
= { .min
= 1, .max
= 3 },
362 .m
= { .min
= 79, .max
= 126 },
363 .m1
= { .min
= 12, .max
= 22 },
364 .m2
= { .min
= 5, .max
= 9 },
365 .p
= { .min
= 14, .max
= 42 },
366 .p1
= { .min
= 2, .max
= 6 },
367 .p2
= { .dot_limit
= 225000,
368 .p2_slow
= 7, .p2_fast
= 7 },
371 static const intel_limit_t intel_limits_vlv
= {
373 * These are the data rate limits (measured in fast clocks)
374 * since those are the strictest limits we have. The fast
375 * clock and actual rate limits are more relaxed, so checking
376 * them would make no difference.
378 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
379 .vco
= { .min
= 4000000, .max
= 6000000 },
380 .n
= { .min
= 1, .max
= 7 },
381 .m1
= { .min
= 2, .max
= 3 },
382 .m2
= { .min
= 11, .max
= 156 },
383 .p1
= { .min
= 2, .max
= 3 },
384 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
387 static const intel_limit_t intel_limits_chv
= {
389 * These are the data rate limits (measured in fast clocks)
390 * since those are the strictest limits we have. The fast
391 * clock and actual rate limits are more relaxed, so checking
392 * them would make no difference.
394 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
395 .vco
= { .min
= 4800000, .max
= 6480000 },
396 .n
= { .min
= 1, .max
= 1 },
397 .m1
= { .min
= 2, .max
= 2 },
398 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
399 .p1
= { .min
= 2, .max
= 4 },
400 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
403 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
405 clock
->m
= clock
->m1
* clock
->m2
;
406 clock
->p
= clock
->p1
* clock
->p2
;
407 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
409 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
410 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
414 * Returns whether any output on the specified pipe is of the specified type
416 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
418 struct drm_device
*dev
= crtc
->base
.dev
;
419 struct intel_encoder
*encoder
;
421 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
422 if (encoder
->type
== type
)
429 * Returns whether any output on the specified pipe will have the specified
430 * type after a staged modeset is complete, i.e., the same as
431 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
434 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
437 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
438 struct drm_connector_state
*connector_state
;
439 struct intel_encoder
*encoder
;
440 int i
, num_connectors
= 0;
442 for (i
= 0; i
< state
->num_connector
; i
++) {
443 if (!state
->connectors
[i
])
446 connector_state
= state
->connector_states
[i
];
447 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
452 encoder
= to_intel_encoder(connector_state
->best_encoder
);
453 if (encoder
->type
== type
)
457 WARN_ON(num_connectors
== 0);
462 static const intel_limit_t
*
463 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
465 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
466 const intel_limit_t
*limit
;
468 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
469 if (intel_is_dual_link_lvds(dev
)) {
470 if (refclk
== 100000)
471 limit
= &intel_limits_ironlake_dual_lvds_100m
;
473 limit
= &intel_limits_ironlake_dual_lvds
;
475 if (refclk
== 100000)
476 limit
= &intel_limits_ironlake_single_lvds_100m
;
478 limit
= &intel_limits_ironlake_single_lvds
;
481 limit
= &intel_limits_ironlake_dac
;
486 static const intel_limit_t
*
487 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
489 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
490 const intel_limit_t
*limit
;
492 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
493 if (intel_is_dual_link_lvds(dev
))
494 limit
= &intel_limits_g4x_dual_channel_lvds
;
496 limit
= &intel_limits_g4x_single_channel_lvds
;
497 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
498 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
499 limit
= &intel_limits_g4x_hdmi
;
500 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
501 limit
= &intel_limits_g4x_sdvo
;
502 } else /* The option is for other outputs */
503 limit
= &intel_limits_i9xx_sdvo
;
508 static const intel_limit_t
*
509 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
511 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
512 const intel_limit_t
*limit
;
514 if (HAS_PCH_SPLIT(dev
))
515 limit
= intel_ironlake_limit(crtc_state
, refclk
);
516 else if (IS_G4X(dev
)) {
517 limit
= intel_g4x_limit(crtc_state
);
518 } else if (IS_PINEVIEW(dev
)) {
519 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
520 limit
= &intel_limits_pineview_lvds
;
522 limit
= &intel_limits_pineview_sdvo
;
523 } else if (IS_CHERRYVIEW(dev
)) {
524 limit
= &intel_limits_chv
;
525 } else if (IS_VALLEYVIEW(dev
)) {
526 limit
= &intel_limits_vlv
;
527 } else if (!IS_GEN2(dev
)) {
528 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
529 limit
= &intel_limits_i9xx_lvds
;
531 limit
= &intel_limits_i9xx_sdvo
;
533 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
534 limit
= &intel_limits_i8xx_lvds
;
535 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
536 limit
= &intel_limits_i8xx_dvo
;
538 limit
= &intel_limits_i8xx_dac
;
543 /* m1 is reserved as 0 in Pineview, n is a ring counter */
544 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
546 clock
->m
= clock
->m2
+ 2;
547 clock
->p
= clock
->p1
* clock
->p2
;
548 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
550 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
551 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
554 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
556 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
559 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
561 clock
->m
= i9xx_dpll_compute_m(clock
);
562 clock
->p
= clock
->p1
* clock
->p2
;
563 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
565 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
566 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
569 static void chv_clock(int refclk
, intel_clock_t
*clock
)
571 clock
->m
= clock
->m1
* clock
->m2
;
572 clock
->p
= clock
->p1
* clock
->p2
;
573 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
575 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
577 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
580 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
582 * Returns whether the given set of divisors are valid for a given refclk with
583 * the given connectors.
586 static bool intel_PLL_is_valid(struct drm_device
*dev
,
587 const intel_limit_t
*limit
,
588 const intel_clock_t
*clock
)
590 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
591 INTELPllInvalid("n out of range\n");
592 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
593 INTELPllInvalid("p1 out of range\n");
594 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
595 INTELPllInvalid("m2 out of range\n");
596 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
597 INTELPllInvalid("m1 out of range\n");
599 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
600 if (clock
->m1
<= clock
->m2
)
601 INTELPllInvalid("m1 <= m2\n");
603 if (!IS_VALLEYVIEW(dev
)) {
604 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
605 INTELPllInvalid("p out of range\n");
606 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
607 INTELPllInvalid("m out of range\n");
610 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
611 INTELPllInvalid("vco out of range\n");
612 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
613 * connector, etc., rather than just a single range.
615 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
616 INTELPllInvalid("dot out of range\n");
622 i9xx_find_best_dpll(const intel_limit_t
*limit
,
623 struct intel_crtc_state
*crtc_state
,
624 int target
, int refclk
, intel_clock_t
*match_clock
,
625 intel_clock_t
*best_clock
)
627 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
628 struct drm_device
*dev
= crtc
->base
.dev
;
632 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
634 * For LVDS just rely on its current settings for dual-channel.
635 * We haven't figured out how to reliably set up different
636 * single/dual channel state, if we even can.
638 if (intel_is_dual_link_lvds(dev
))
639 clock
.p2
= limit
->p2
.p2_fast
;
641 clock
.p2
= limit
->p2
.p2_slow
;
643 if (target
< limit
->p2
.dot_limit
)
644 clock
.p2
= limit
->p2
.p2_slow
;
646 clock
.p2
= limit
->p2
.p2_fast
;
649 memset(best_clock
, 0, sizeof(*best_clock
));
651 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
653 for (clock
.m2
= limit
->m2
.min
;
654 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
655 if (clock
.m2
>= clock
.m1
)
657 for (clock
.n
= limit
->n
.min
;
658 clock
.n
<= limit
->n
.max
; clock
.n
++) {
659 for (clock
.p1
= limit
->p1
.min
;
660 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
663 i9xx_clock(refclk
, &clock
);
664 if (!intel_PLL_is_valid(dev
, limit
,
668 clock
.p
!= match_clock
->p
)
671 this_err
= abs(clock
.dot
- target
);
672 if (this_err
< err
) {
681 return (err
!= target
);
685 pnv_find_best_dpll(const intel_limit_t
*limit
,
686 struct intel_crtc_state
*crtc_state
,
687 int target
, int refclk
, intel_clock_t
*match_clock
,
688 intel_clock_t
*best_clock
)
690 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
691 struct drm_device
*dev
= crtc
->base
.dev
;
695 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
697 * For LVDS just rely on its current settings for dual-channel.
698 * We haven't figured out how to reliably set up different
699 * single/dual channel state, if we even can.
701 if (intel_is_dual_link_lvds(dev
))
702 clock
.p2
= limit
->p2
.p2_fast
;
704 clock
.p2
= limit
->p2
.p2_slow
;
706 if (target
< limit
->p2
.dot_limit
)
707 clock
.p2
= limit
->p2
.p2_slow
;
709 clock
.p2
= limit
->p2
.p2_fast
;
712 memset(best_clock
, 0, sizeof(*best_clock
));
714 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
716 for (clock
.m2
= limit
->m2
.min
;
717 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
718 for (clock
.n
= limit
->n
.min
;
719 clock
.n
<= limit
->n
.max
; clock
.n
++) {
720 for (clock
.p1
= limit
->p1
.min
;
721 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
724 pineview_clock(refclk
, &clock
);
725 if (!intel_PLL_is_valid(dev
, limit
,
729 clock
.p
!= match_clock
->p
)
732 this_err
= abs(clock
.dot
- target
);
733 if (this_err
< err
) {
742 return (err
!= target
);
746 g4x_find_best_dpll(const intel_limit_t
*limit
,
747 struct intel_crtc_state
*crtc_state
,
748 int target
, int refclk
, intel_clock_t
*match_clock
,
749 intel_clock_t
*best_clock
)
751 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
752 struct drm_device
*dev
= crtc
->base
.dev
;
756 /* approximately equals target * 0.00585 */
757 int err_most
= (target
>> 8) + (target
>> 9);
760 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
761 if (intel_is_dual_link_lvds(dev
))
762 clock
.p2
= limit
->p2
.p2_fast
;
764 clock
.p2
= limit
->p2
.p2_slow
;
766 if (target
< limit
->p2
.dot_limit
)
767 clock
.p2
= limit
->p2
.p2_slow
;
769 clock
.p2
= limit
->p2
.p2_fast
;
772 memset(best_clock
, 0, sizeof(*best_clock
));
773 max_n
= limit
->n
.max
;
774 /* based on hardware requirement, prefer smaller n to precision */
775 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
776 /* based on hardware requirement, prefere larger m1,m2 */
777 for (clock
.m1
= limit
->m1
.max
;
778 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
779 for (clock
.m2
= limit
->m2
.max
;
780 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
781 for (clock
.p1
= limit
->p1
.max
;
782 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
785 i9xx_clock(refclk
, &clock
);
786 if (!intel_PLL_is_valid(dev
, limit
,
790 this_err
= abs(clock
.dot
- target
);
791 if (this_err
< err_most
) {
805 * Check if the calculated PLL configuration is more optimal compared to the
806 * best configuration and error found so far. Return the calculated error.
808 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
809 const intel_clock_t
*calculated_clock
,
810 const intel_clock_t
*best_clock
,
811 unsigned int best_error_ppm
,
812 unsigned int *error_ppm
)
815 * For CHV ignore the error and consider only the P value.
816 * Prefer a bigger P value based on HW requirements.
818 if (IS_CHERRYVIEW(dev
)) {
821 return calculated_clock
->p
> best_clock
->p
;
824 if (WARN_ON_ONCE(!target_freq
))
827 *error_ppm
= div_u64(1000000ULL *
828 abs(target_freq
- calculated_clock
->dot
),
831 * Prefer a better P value over a better (smaller) error if the error
832 * is small. Ensure this preference for future configurations too by
833 * setting the error to 0.
835 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
841 return *error_ppm
+ 10 < best_error_ppm
;
845 vlv_find_best_dpll(const intel_limit_t
*limit
,
846 struct intel_crtc_state
*crtc_state
,
847 int target
, int refclk
, intel_clock_t
*match_clock
,
848 intel_clock_t
*best_clock
)
850 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
851 struct drm_device
*dev
= crtc
->base
.dev
;
853 unsigned int bestppm
= 1000000;
854 /* min update 19.2 MHz */
855 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
858 target
*= 5; /* fast clock */
860 memset(best_clock
, 0, sizeof(*best_clock
));
862 /* based on hardware requirement, prefer smaller n to precision */
863 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
864 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
865 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
866 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
867 clock
.p
= clock
.p1
* clock
.p2
;
868 /* based on hardware requirement, prefer bigger m1,m2 values */
869 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
872 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
875 vlv_clock(refclk
, &clock
);
877 if (!intel_PLL_is_valid(dev
, limit
,
881 if (!vlv_PLL_is_optimal(dev
, target
,
899 chv_find_best_dpll(const intel_limit_t
*limit
,
900 struct intel_crtc_state
*crtc_state
,
901 int target
, int refclk
, intel_clock_t
*match_clock
,
902 intel_clock_t
*best_clock
)
904 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
905 struct drm_device
*dev
= crtc
->base
.dev
;
906 unsigned int best_error_ppm
;
911 memset(best_clock
, 0, sizeof(*best_clock
));
912 best_error_ppm
= 1000000;
915 * Based on hardware doc, the n always set to 1, and m1 always
916 * set to 2. If requires to support 200Mhz refclk, we need to
917 * revisit this because n may not 1 anymore.
919 clock
.n
= 1, clock
.m1
= 2;
920 target
*= 5; /* fast clock */
922 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
923 for (clock
.p2
= limit
->p2
.p2_fast
;
924 clock
.p2
>= limit
->p2
.p2_slow
;
925 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
926 unsigned int error_ppm
;
928 clock
.p
= clock
.p1
* clock
.p2
;
930 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
931 clock
.n
) << 22, refclk
* clock
.m1
);
933 if (m2
> INT_MAX
/clock
.m1
)
938 chv_clock(refclk
, &clock
);
940 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
943 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
944 best_error_ppm
, &error_ppm
))
948 best_error_ppm
= error_ppm
;
956 bool intel_crtc_active(struct drm_crtc
*crtc
)
958 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
960 /* Be paranoid as we can arrive here with only partial
961 * state retrieved from the hardware during setup.
963 * We can ditch the adjusted_mode.crtc_clock check as soon
964 * as Haswell has gained clock readout/fastboot support.
966 * We can ditch the crtc->primary->fb check as soon as we can
967 * properly reconstruct framebuffers.
969 * FIXME: The intel_crtc->active here should be switched to
970 * crtc->state->active once we have proper CRTC states wired up
973 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
974 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
977 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
980 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
981 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
983 return intel_crtc
->config
->cpu_transcoder
;
986 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
988 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
989 u32 reg
= PIPEDSL(pipe
);
994 line_mask
= DSL_LINEMASK_GEN2
;
996 line_mask
= DSL_LINEMASK_GEN3
;
998 line1
= I915_READ(reg
) & line_mask
;
1000 line2
= I915_READ(reg
) & line_mask
;
1002 return line1
== line2
;
1006 * intel_wait_for_pipe_off - wait for pipe to turn off
1007 * @crtc: crtc whose pipe to wait for
1009 * After disabling a pipe, we can't wait for vblank in the usual way,
1010 * spinning on the vblank interrupt status bit, since we won't actually
1011 * see an interrupt when the pipe is disabled.
1013 * On Gen4 and above:
1014 * wait for the pipe register state bit to turn off
1017 * wait for the display line value to settle (it usually
1018 * ends up stopping at the start of the next frame).
1021 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1023 struct drm_device
*dev
= crtc
->base
.dev
;
1024 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1025 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1026 enum pipe pipe
= crtc
->pipe
;
1028 if (INTEL_INFO(dev
)->gen
>= 4) {
1029 int reg
= PIPECONF(cpu_transcoder
);
1031 /* Wait for the Pipe State to go off */
1032 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1034 WARN(1, "pipe_off wait timed out\n");
1036 /* Wait for the display line to settle */
1037 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1038 WARN(1, "pipe_off wait timed out\n");
1043 * ibx_digital_port_connected - is the specified port connected?
1044 * @dev_priv: i915 private structure
1045 * @port: the port to test
1047 * Returns true if @port is connected, false otherwise.
1049 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1050 struct intel_digital_port
*port
)
1054 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1055 switch (port
->port
) {
1057 bit
= SDE_PORTB_HOTPLUG
;
1060 bit
= SDE_PORTC_HOTPLUG
;
1063 bit
= SDE_PORTD_HOTPLUG
;
1069 switch (port
->port
) {
1071 bit
= SDE_PORTB_HOTPLUG_CPT
;
1074 bit
= SDE_PORTC_HOTPLUG_CPT
;
1077 bit
= SDE_PORTD_HOTPLUG_CPT
;
1084 return I915_READ(SDEISR
) & bit
;
1087 static const char *state_string(bool enabled
)
1089 return enabled
? "on" : "off";
1092 /* Only for pre-ILK configs */
1093 void assert_pll(struct drm_i915_private
*dev_priv
,
1094 enum pipe pipe
, bool state
)
1101 val
= I915_READ(reg
);
1102 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1103 I915_STATE_WARN(cur_state
!= state
,
1104 "PLL state assertion failure (expected %s, current %s)\n",
1105 state_string(state
), state_string(cur_state
));
1108 /* XXX: the dsi pll is shared between MIPI DSI ports */
1109 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1114 mutex_lock(&dev_priv
->dpio_lock
);
1115 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1116 mutex_unlock(&dev_priv
->dpio_lock
);
1118 cur_state
= val
& DSI_PLL_VCO_EN
;
1119 I915_STATE_WARN(cur_state
!= state
,
1120 "DSI PLL state assertion failure (expected %s, current %s)\n",
1121 state_string(state
), state_string(cur_state
));
1123 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1124 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1126 struct intel_shared_dpll
*
1127 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1129 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1131 if (crtc
->config
->shared_dpll
< 0)
1134 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1138 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1139 struct intel_shared_dpll
*pll
,
1143 struct intel_dpll_hw_state hw_state
;
1146 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1149 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1150 I915_STATE_WARN(cur_state
!= state
,
1151 "%s assertion failure (expected %s, current %s)\n",
1152 pll
->name
, state_string(state
), state_string(cur_state
));
1155 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1156 enum pipe pipe
, bool state
)
1161 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1164 if (HAS_DDI(dev_priv
->dev
)) {
1165 /* DDI does not have a specific FDI_TX register */
1166 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1167 val
= I915_READ(reg
);
1168 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1170 reg
= FDI_TX_CTL(pipe
);
1171 val
= I915_READ(reg
);
1172 cur_state
= !!(val
& FDI_TX_ENABLE
);
1174 I915_STATE_WARN(cur_state
!= state
,
1175 "FDI TX state assertion failure (expected %s, current %s)\n",
1176 state_string(state
), state_string(cur_state
));
1178 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1179 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1181 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1182 enum pipe pipe
, bool state
)
1188 reg
= FDI_RX_CTL(pipe
);
1189 val
= I915_READ(reg
);
1190 cur_state
= !!(val
& FDI_RX_ENABLE
);
1191 I915_STATE_WARN(cur_state
!= state
,
1192 "FDI RX state assertion failure (expected %s, current %s)\n",
1193 state_string(state
), state_string(cur_state
));
1195 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1196 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1198 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1204 /* ILK FDI PLL is always enabled */
1205 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1208 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1209 if (HAS_DDI(dev_priv
->dev
))
1212 reg
= FDI_TX_CTL(pipe
);
1213 val
= I915_READ(reg
);
1214 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1217 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1224 reg
= FDI_RX_CTL(pipe
);
1225 val
= I915_READ(reg
);
1226 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1227 I915_STATE_WARN(cur_state
!= state
,
1228 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1229 state_string(state
), state_string(cur_state
));
1232 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1235 struct drm_device
*dev
= dev_priv
->dev
;
1238 enum pipe panel_pipe
= PIPE_A
;
1241 if (WARN_ON(HAS_DDI(dev
)))
1244 if (HAS_PCH_SPLIT(dev
)) {
1247 pp_reg
= PCH_PP_CONTROL
;
1248 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1250 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1251 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1252 panel_pipe
= PIPE_B
;
1253 /* XXX: else fix for eDP */
1254 } else if (IS_VALLEYVIEW(dev
)) {
1255 /* presumably write lock depends on pipe, not port select */
1256 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1259 pp_reg
= PP_CONTROL
;
1260 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1261 panel_pipe
= PIPE_B
;
1264 val
= I915_READ(pp_reg
);
1265 if (!(val
& PANEL_POWER_ON
) ||
1266 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1269 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1270 "panel assertion failure, pipe %c regs locked\n",
1274 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1275 enum pipe pipe
, bool state
)
1277 struct drm_device
*dev
= dev_priv
->dev
;
1280 if (IS_845G(dev
) || IS_I865G(dev
))
1281 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1283 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1285 I915_STATE_WARN(cur_state
!= state
,
1286 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1287 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1289 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1290 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1292 void assert_pipe(struct drm_i915_private
*dev_priv
,
1293 enum pipe pipe
, bool state
)
1298 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1301 /* if we need the pipe quirk it must be always on */
1302 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1303 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1306 if (!intel_display_power_is_enabled(dev_priv
,
1307 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1310 reg
= PIPECONF(cpu_transcoder
);
1311 val
= I915_READ(reg
);
1312 cur_state
= !!(val
& PIPECONF_ENABLE
);
1315 I915_STATE_WARN(cur_state
!= state
,
1316 "pipe %c assertion failure (expected %s, current %s)\n",
1317 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1320 static void assert_plane(struct drm_i915_private
*dev_priv
,
1321 enum plane plane
, bool state
)
1327 reg
= DSPCNTR(plane
);
1328 val
= I915_READ(reg
);
1329 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1330 I915_STATE_WARN(cur_state
!= state
,
1331 "plane %c assertion failure (expected %s, current %s)\n",
1332 plane_name(plane
), state_string(state
), state_string(cur_state
));
1335 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1336 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1338 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1341 struct drm_device
*dev
= dev_priv
->dev
;
1346 /* Primary planes are fixed to pipes on gen4+ */
1347 if (INTEL_INFO(dev
)->gen
>= 4) {
1348 reg
= DSPCNTR(pipe
);
1349 val
= I915_READ(reg
);
1350 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1351 "plane %c assertion failure, should be disabled but not\n",
1356 /* Need to check both planes against the pipe */
1357 for_each_pipe(dev_priv
, i
) {
1359 val
= I915_READ(reg
);
1360 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1361 DISPPLANE_SEL_PIPE_SHIFT
;
1362 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1363 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1364 plane_name(i
), pipe_name(pipe
));
1368 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1371 struct drm_device
*dev
= dev_priv
->dev
;
1375 if (INTEL_INFO(dev
)->gen
>= 9) {
1376 for_each_sprite(dev_priv
, pipe
, sprite
) {
1377 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1378 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1379 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1380 sprite
, pipe_name(pipe
));
1382 } else if (IS_VALLEYVIEW(dev
)) {
1383 for_each_sprite(dev_priv
, pipe
, sprite
) {
1384 reg
= SPCNTR(pipe
, sprite
);
1385 val
= I915_READ(reg
);
1386 I915_STATE_WARN(val
& SP_ENABLE
,
1387 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1388 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1390 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1392 val
= I915_READ(reg
);
1393 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1394 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1395 plane_name(pipe
), pipe_name(pipe
));
1396 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1397 reg
= DVSCNTR(pipe
);
1398 val
= I915_READ(reg
);
1399 I915_STATE_WARN(val
& DVS_ENABLE
,
1400 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1401 plane_name(pipe
), pipe_name(pipe
));
1405 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1407 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1408 drm_crtc_vblank_put(crtc
);
1411 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1416 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1418 val
= I915_READ(PCH_DREF_CONTROL
);
1419 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1420 DREF_SUPERSPREAD_SOURCE_MASK
));
1421 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1424 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1431 reg
= PCH_TRANSCONF(pipe
);
1432 val
= I915_READ(reg
);
1433 enabled
= !!(val
& TRANS_ENABLE
);
1434 I915_STATE_WARN(enabled
,
1435 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1439 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1440 enum pipe pipe
, u32 port_sel
, u32 val
)
1442 if ((val
& DP_PORT_EN
) == 0)
1445 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1446 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1447 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1448 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1450 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1451 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1454 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1460 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1461 enum pipe pipe
, u32 val
)
1463 if ((val
& SDVO_ENABLE
) == 0)
1466 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1467 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1469 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1470 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1473 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1479 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1480 enum pipe pipe
, u32 val
)
1482 if ((val
& LVDS_PORT_EN
) == 0)
1485 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1486 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1489 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1495 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1496 enum pipe pipe
, u32 val
)
1498 if ((val
& ADPA_DAC_ENABLE
) == 0)
1500 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1501 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1504 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1510 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1511 enum pipe pipe
, int reg
, u32 port_sel
)
1513 u32 val
= I915_READ(reg
);
1514 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1516 reg
, pipe_name(pipe
));
1518 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1519 && (val
& DP_PIPEB_SELECT
),
1520 "IBX PCH dp port still using transcoder B\n");
1523 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1524 enum pipe pipe
, int reg
)
1526 u32 val
= I915_READ(reg
);
1527 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1529 reg
, pipe_name(pipe
));
1531 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1532 && (val
& SDVO_PIPE_B_SELECT
),
1533 "IBX PCH hdmi port still using transcoder B\n");
1536 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1542 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1543 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1544 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1547 val
= I915_READ(reg
);
1548 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1549 "PCH VGA enabled on transcoder %c, should be disabled\n",
1553 val
= I915_READ(reg
);
1554 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1555 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1558 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1559 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1560 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1563 static void intel_init_dpio(struct drm_device
*dev
)
1565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1567 if (!IS_VALLEYVIEW(dev
))
1571 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1572 * CHV x1 PHY (DP/HDMI D)
1573 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1575 if (IS_CHERRYVIEW(dev
)) {
1576 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1577 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1579 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1583 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1584 const struct intel_crtc_state
*pipe_config
)
1586 struct drm_device
*dev
= crtc
->base
.dev
;
1587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1588 int reg
= DPLL(crtc
->pipe
);
1589 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1591 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1593 /* No really, not for ILK+ */
1594 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1596 /* PLL is protected by panel, make sure we can write it */
1597 if (IS_MOBILE(dev_priv
->dev
))
1598 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1600 I915_WRITE(reg
, dpll
);
1604 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1605 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1607 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1608 POSTING_READ(DPLL_MD(crtc
->pipe
));
1610 /* We do this three times for luck */
1611 I915_WRITE(reg
, dpll
);
1613 udelay(150); /* wait for warmup */
1614 I915_WRITE(reg
, dpll
);
1616 udelay(150); /* wait for warmup */
1617 I915_WRITE(reg
, dpll
);
1619 udelay(150); /* wait for warmup */
1622 static void chv_enable_pll(struct intel_crtc
*crtc
,
1623 const struct intel_crtc_state
*pipe_config
)
1625 struct drm_device
*dev
= crtc
->base
.dev
;
1626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1627 int pipe
= crtc
->pipe
;
1628 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1631 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1633 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1635 mutex_lock(&dev_priv
->dpio_lock
);
1637 /* Enable back the 10bit clock to display controller */
1638 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1639 tmp
|= DPIO_DCLKP_EN
;
1640 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1643 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1648 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1650 /* Check PLL is locked */
1651 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1652 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1654 /* not sure when this should be written */
1655 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1656 POSTING_READ(DPLL_MD(pipe
));
1658 mutex_unlock(&dev_priv
->dpio_lock
);
1661 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1663 struct intel_crtc
*crtc
;
1666 for_each_intel_crtc(dev
, crtc
)
1667 count
+= crtc
->active
&&
1668 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1673 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1675 struct drm_device
*dev
= crtc
->base
.dev
;
1676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1677 int reg
= DPLL(crtc
->pipe
);
1678 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1680 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1682 /* No really, not for ILK+ */
1683 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1685 /* PLL is protected by panel, make sure we can write it */
1686 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1687 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1689 /* Enable DVO 2x clock on both PLLs if necessary */
1690 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1692 * It appears to be important that we don't enable this
1693 * for the current pipe before otherwise configuring the
1694 * PLL. No idea how this should be handled if multiple
1695 * DVO outputs are enabled simultaneosly.
1697 dpll
|= DPLL_DVO_2X_MODE
;
1698 I915_WRITE(DPLL(!crtc
->pipe
),
1699 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1702 /* Wait for the clocks to stabilize. */
1706 if (INTEL_INFO(dev
)->gen
>= 4) {
1707 I915_WRITE(DPLL_MD(crtc
->pipe
),
1708 crtc
->config
->dpll_hw_state
.dpll_md
);
1710 /* The pixel multiplier can only be updated once the
1711 * DPLL is enabled and the clocks are stable.
1713 * So write it again.
1715 I915_WRITE(reg
, dpll
);
1718 /* We do this three times for luck */
1719 I915_WRITE(reg
, dpll
);
1721 udelay(150); /* wait for warmup */
1722 I915_WRITE(reg
, dpll
);
1724 udelay(150); /* wait for warmup */
1725 I915_WRITE(reg
, dpll
);
1727 udelay(150); /* wait for warmup */
1731 * i9xx_disable_pll - disable a PLL
1732 * @dev_priv: i915 private structure
1733 * @pipe: pipe PLL to disable
1735 * Disable the PLL for @pipe, making sure the pipe is off first.
1737 * Note! This is for pre-ILK only.
1739 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1741 struct drm_device
*dev
= crtc
->base
.dev
;
1742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1743 enum pipe pipe
= crtc
->pipe
;
1745 /* Disable DVO 2x clock on both PLLs if necessary */
1747 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1748 intel_num_dvo_pipes(dev
) == 1) {
1749 I915_WRITE(DPLL(PIPE_B
),
1750 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1751 I915_WRITE(DPLL(PIPE_A
),
1752 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1755 /* Don't disable pipe or pipe PLLs if needed */
1756 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1757 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1760 /* Make sure the pipe isn't still relying on us */
1761 assert_pipe_disabled(dev_priv
, pipe
);
1763 I915_WRITE(DPLL(pipe
), 0);
1764 POSTING_READ(DPLL(pipe
));
1767 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1771 /* Make sure the pipe isn't still relying on us */
1772 assert_pipe_disabled(dev_priv
, pipe
);
1775 * Leave integrated clock source and reference clock enabled for pipe B.
1776 * The latter is needed for VGA hotplug / manual detection.
1779 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1780 I915_WRITE(DPLL(pipe
), val
);
1781 POSTING_READ(DPLL(pipe
));
1785 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1787 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1790 /* Make sure the pipe isn't still relying on us */
1791 assert_pipe_disabled(dev_priv
, pipe
);
1793 /* Set PLL en = 0 */
1794 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1796 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1797 I915_WRITE(DPLL(pipe
), val
);
1798 POSTING_READ(DPLL(pipe
));
1800 mutex_lock(&dev_priv
->dpio_lock
);
1802 /* Disable 10bit clock to display controller */
1803 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1804 val
&= ~DPIO_DCLKP_EN
;
1805 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1807 /* disable left/right clock distribution */
1808 if (pipe
!= PIPE_B
) {
1809 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1810 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1811 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1813 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1814 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1815 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1818 mutex_unlock(&dev_priv
->dpio_lock
);
1821 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1822 struct intel_digital_port
*dport
)
1827 switch (dport
->port
) {
1829 port_mask
= DPLL_PORTB_READY_MASK
;
1833 port_mask
= DPLL_PORTC_READY_MASK
;
1837 port_mask
= DPLL_PORTD_READY_MASK
;
1838 dpll_reg
= DPIO_PHY_STATUS
;
1844 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1845 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1846 port_name(dport
->port
), I915_READ(dpll_reg
));
1849 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1851 struct drm_device
*dev
= crtc
->base
.dev
;
1852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1853 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1855 if (WARN_ON(pll
== NULL
))
1858 WARN_ON(!pll
->config
.crtc_mask
);
1859 if (pll
->active
== 0) {
1860 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1862 assert_shared_dpll_disabled(dev_priv
, pll
);
1864 pll
->mode_set(dev_priv
, pll
);
1869 * intel_enable_shared_dpll - enable PCH PLL
1870 * @dev_priv: i915 private structure
1871 * @pipe: pipe PLL to enable
1873 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1874 * drives the transcoder clock.
1876 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1878 struct drm_device
*dev
= crtc
->base
.dev
;
1879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1880 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1882 if (WARN_ON(pll
== NULL
))
1885 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1888 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1889 pll
->name
, pll
->active
, pll
->on
,
1890 crtc
->base
.base
.id
);
1892 if (pll
->active
++) {
1894 assert_shared_dpll_enabled(dev_priv
, pll
);
1899 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1901 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1902 pll
->enable(dev_priv
, pll
);
1906 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1908 struct drm_device
*dev
= crtc
->base
.dev
;
1909 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1910 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1912 /* PCH only available on ILK+ */
1913 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1914 if (WARN_ON(pll
== NULL
))
1917 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1920 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1921 pll
->name
, pll
->active
, pll
->on
,
1922 crtc
->base
.base
.id
);
1924 if (WARN_ON(pll
->active
== 0)) {
1925 assert_shared_dpll_disabled(dev_priv
, pll
);
1929 assert_shared_dpll_enabled(dev_priv
, pll
);
1934 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1935 pll
->disable(dev_priv
, pll
);
1938 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1941 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1944 struct drm_device
*dev
= dev_priv
->dev
;
1945 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1946 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1947 uint32_t reg
, val
, pipeconf_val
;
1949 /* PCH only available on ILK+ */
1950 BUG_ON(!HAS_PCH_SPLIT(dev
));
1952 /* Make sure PCH DPLL is enabled */
1953 assert_shared_dpll_enabled(dev_priv
,
1954 intel_crtc_to_shared_dpll(intel_crtc
));
1956 /* FDI must be feeding us bits for PCH ports */
1957 assert_fdi_tx_enabled(dev_priv
, pipe
);
1958 assert_fdi_rx_enabled(dev_priv
, pipe
);
1960 if (HAS_PCH_CPT(dev
)) {
1961 /* Workaround: Set the timing override bit before enabling the
1962 * pch transcoder. */
1963 reg
= TRANS_CHICKEN2(pipe
);
1964 val
= I915_READ(reg
);
1965 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1966 I915_WRITE(reg
, val
);
1969 reg
= PCH_TRANSCONF(pipe
);
1970 val
= I915_READ(reg
);
1971 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1973 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1975 * make the BPC in transcoder be consistent with
1976 * that in pipeconf reg.
1978 val
&= ~PIPECONF_BPC_MASK
;
1979 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1982 val
&= ~TRANS_INTERLACE_MASK
;
1983 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1984 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1985 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
1986 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1988 val
|= TRANS_INTERLACED
;
1990 val
|= TRANS_PROGRESSIVE
;
1992 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1993 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1994 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1997 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1998 enum transcoder cpu_transcoder
)
2000 u32 val
, pipeconf_val
;
2002 /* PCH only available on ILK+ */
2003 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2005 /* FDI must be feeding us bits for PCH ports */
2006 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2007 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2009 /* Workaround: set timing override bit. */
2010 val
= I915_READ(_TRANSA_CHICKEN2
);
2011 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2012 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2015 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2017 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2018 PIPECONF_INTERLACED_ILK
)
2019 val
|= TRANS_INTERLACED
;
2021 val
|= TRANS_PROGRESSIVE
;
2023 I915_WRITE(LPT_TRANSCONF
, val
);
2024 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2025 DRM_ERROR("Failed to enable PCH transcoder\n");
2028 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2031 struct drm_device
*dev
= dev_priv
->dev
;
2034 /* FDI relies on the transcoder */
2035 assert_fdi_tx_disabled(dev_priv
, pipe
);
2036 assert_fdi_rx_disabled(dev_priv
, pipe
);
2038 /* Ports must be off as well */
2039 assert_pch_ports_disabled(dev_priv
, pipe
);
2041 reg
= PCH_TRANSCONF(pipe
);
2042 val
= I915_READ(reg
);
2043 val
&= ~TRANS_ENABLE
;
2044 I915_WRITE(reg
, val
);
2045 /* wait for PCH transcoder off, transcoder state */
2046 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2047 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2049 if (!HAS_PCH_IBX(dev
)) {
2050 /* Workaround: Clear the timing override chicken bit again. */
2051 reg
= TRANS_CHICKEN2(pipe
);
2052 val
= I915_READ(reg
);
2053 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2054 I915_WRITE(reg
, val
);
2058 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2062 val
= I915_READ(LPT_TRANSCONF
);
2063 val
&= ~TRANS_ENABLE
;
2064 I915_WRITE(LPT_TRANSCONF
, val
);
2065 /* wait for PCH transcoder off, transcoder state */
2066 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2067 DRM_ERROR("Failed to disable PCH transcoder\n");
2069 /* Workaround: clear timing override bit. */
2070 val
= I915_READ(_TRANSA_CHICKEN2
);
2071 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2072 I915_WRITE(_TRANSA_CHICKEN2
, val
);
2076 * intel_enable_pipe - enable a pipe, asserting requirements
2077 * @crtc: crtc responsible for the pipe
2079 * Enable @crtc's pipe, making sure that various hardware specific requirements
2080 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2082 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2084 struct drm_device
*dev
= crtc
->base
.dev
;
2085 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2086 enum pipe pipe
= crtc
->pipe
;
2087 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2089 enum pipe pch_transcoder
;
2093 assert_planes_disabled(dev_priv
, pipe
);
2094 assert_cursor_disabled(dev_priv
, pipe
);
2095 assert_sprites_disabled(dev_priv
, pipe
);
2097 if (HAS_PCH_LPT(dev_priv
->dev
))
2098 pch_transcoder
= TRANSCODER_A
;
2100 pch_transcoder
= pipe
;
2103 * A pipe without a PLL won't actually be able to drive bits from
2104 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2107 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2108 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2109 assert_dsi_pll_enabled(dev_priv
);
2111 assert_pll_enabled(dev_priv
, pipe
);
2113 if (crtc
->config
->has_pch_encoder
) {
2114 /* if driving the PCH, we need FDI enabled */
2115 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2116 assert_fdi_tx_pll_enabled(dev_priv
,
2117 (enum pipe
) cpu_transcoder
);
2119 /* FIXME: assert CPU port conditions for SNB+ */
2122 reg
= PIPECONF(cpu_transcoder
);
2123 val
= I915_READ(reg
);
2124 if (val
& PIPECONF_ENABLE
) {
2125 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2126 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2130 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2135 * intel_disable_pipe - disable a pipe, asserting requirements
2136 * @crtc: crtc whose pipes is to be disabled
2138 * Disable the pipe of @crtc, making sure that various hardware
2139 * specific requirements are met, if applicable, e.g. plane
2140 * disabled, panel fitter off, etc.
2142 * Will wait until the pipe has shut down before returning.
2144 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2146 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2147 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2148 enum pipe pipe
= crtc
->pipe
;
2153 * Make sure planes won't keep trying to pump pixels to us,
2154 * or we might hang the display.
2156 assert_planes_disabled(dev_priv
, pipe
);
2157 assert_cursor_disabled(dev_priv
, pipe
);
2158 assert_sprites_disabled(dev_priv
, pipe
);
2160 reg
= PIPECONF(cpu_transcoder
);
2161 val
= I915_READ(reg
);
2162 if ((val
& PIPECONF_ENABLE
) == 0)
2166 * Double wide has implications for planes
2167 * so best keep it disabled when not needed.
2169 if (crtc
->config
->double_wide
)
2170 val
&= ~PIPECONF_DOUBLE_WIDE
;
2172 /* Don't disable pipe or pipe PLLs if needed */
2173 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2174 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2175 val
&= ~PIPECONF_ENABLE
;
2177 I915_WRITE(reg
, val
);
2178 if ((val
& PIPECONF_ENABLE
) == 0)
2179 intel_wait_for_pipe_off(crtc
);
2183 * Plane regs are double buffered, going from enabled->disabled needs a
2184 * trigger in order to latch. The display address reg provides this.
2186 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2189 struct drm_device
*dev
= dev_priv
->dev
;
2190 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2192 I915_WRITE(reg
, I915_READ(reg
));
2197 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2198 * @plane: plane to be enabled
2199 * @crtc: crtc for the plane
2201 * Enable @plane on @crtc, making sure that the pipe is running first.
2203 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2204 struct drm_crtc
*crtc
)
2206 struct drm_device
*dev
= plane
->dev
;
2207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2208 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2210 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2211 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2213 if (intel_crtc
->primary_enabled
)
2216 intel_crtc
->primary_enabled
= true;
2218 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2222 * BDW signals flip done immediately if the plane
2223 * is disabled, even if the plane enable is already
2224 * armed to occur at the next vblank :(
2226 if (IS_BROADWELL(dev
))
2227 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2231 * intel_disable_primary_hw_plane - disable the primary hardware plane
2232 * @plane: plane to be disabled
2233 * @crtc: crtc for the plane
2235 * Disable @plane on @crtc, making sure that the pipe is running first.
2237 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2238 struct drm_crtc
*crtc
)
2240 struct drm_device
*dev
= plane
->dev
;
2241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2244 if (WARN_ON(!intel_crtc
->active
))
2247 if (!intel_crtc
->primary_enabled
)
2250 intel_crtc
->primary_enabled
= false;
2252 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2256 static bool need_vtd_wa(struct drm_device
*dev
)
2258 #ifdef CONFIG_INTEL_IOMMU
2259 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2266 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2267 uint64_t fb_format_modifier
)
2269 unsigned int tile_height
;
2270 uint32_t pixel_bytes
;
2272 switch (fb_format_modifier
) {
2273 case DRM_FORMAT_MOD_NONE
:
2276 case I915_FORMAT_MOD_X_TILED
:
2277 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2279 case I915_FORMAT_MOD_Y_TILED
:
2282 case I915_FORMAT_MOD_Yf_TILED
:
2283 pixel_bytes
= drm_format_plane_cpp(pixel_format
, 0);
2284 switch (pixel_bytes
) {
2298 "128-bit pixels are not supported for display!");
2304 MISSING_CASE(fb_format_modifier
);
2313 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2314 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2316 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2317 fb_format_modifier
));
2321 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2322 const struct drm_plane_state
*plane_state
)
2324 struct intel_rotation_info
*info
= &view
->rotation_info
;
2326 *view
= i915_ggtt_view_normal
;
2331 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2334 *view
= i915_ggtt_view_rotated
;
2336 info
->height
= fb
->height
;
2337 info
->pixel_format
= fb
->pixel_format
;
2338 info
->pitch
= fb
->pitches
[0];
2339 info
->fb_modifier
= fb
->modifier
[0];
2341 if (!(info
->fb_modifier
== I915_FORMAT_MOD_Y_TILED
||
2342 info
->fb_modifier
== I915_FORMAT_MOD_Yf_TILED
)) {
2344 "Y or Yf tiling is needed for 90/270 rotation!\n");
2352 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2353 struct drm_framebuffer
*fb
,
2354 const struct drm_plane_state
*plane_state
,
2355 struct intel_engine_cs
*pipelined
)
2357 struct drm_device
*dev
= fb
->dev
;
2358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2359 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2360 struct i915_ggtt_view view
;
2364 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2366 switch (fb
->modifier
[0]) {
2367 case DRM_FORMAT_MOD_NONE
:
2368 if (INTEL_INFO(dev
)->gen
>= 9)
2369 alignment
= 256 * 1024;
2370 else if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2371 alignment
= 128 * 1024;
2372 else if (INTEL_INFO(dev
)->gen
>= 4)
2373 alignment
= 4 * 1024;
2375 alignment
= 64 * 1024;
2377 case I915_FORMAT_MOD_X_TILED
:
2378 if (INTEL_INFO(dev
)->gen
>= 9)
2379 alignment
= 256 * 1024;
2381 /* pin() will align the object as required by fence */
2385 case I915_FORMAT_MOD_Y_TILED
:
2386 case I915_FORMAT_MOD_Yf_TILED
:
2387 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2388 "Y tiling bo slipped through, driver bug!\n"))
2390 alignment
= 1 * 1024 * 1024;
2393 MISSING_CASE(fb
->modifier
[0]);
2397 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2401 /* Note that the w/a also requires 64 PTE of padding following the
2402 * bo. We currently fill all unused PTE with the shadow page and so
2403 * we should always have valid PTE following the scanout preventing
2406 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2407 alignment
= 256 * 1024;
2410 * Global gtt pte registers are special registers which actually forward
2411 * writes to a chunk of system memory. Which means that there is no risk
2412 * that the register values disappear as soon as we call
2413 * intel_runtime_pm_put(), so it is correct to wrap only the
2414 * pin/unpin/fence and not more.
2416 intel_runtime_pm_get(dev_priv
);
2418 dev_priv
->mm
.interruptible
= false;
2419 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2422 goto err_interruptible
;
2424 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2425 * fence, whereas 965+ only requires a fence if using
2426 * framebuffer compression. For simplicity, we always install
2427 * a fence as the cost is not that onerous.
2429 ret
= i915_gem_object_get_fence(obj
);
2433 i915_gem_object_pin_fence(obj
);
2435 dev_priv
->mm
.interruptible
= true;
2436 intel_runtime_pm_put(dev_priv
);
2440 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2442 dev_priv
->mm
.interruptible
= true;
2443 intel_runtime_pm_put(dev_priv
);
2447 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2448 const struct drm_plane_state
*plane_state
)
2450 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2451 struct i915_ggtt_view view
;
2454 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2456 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2457 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2459 i915_gem_object_unpin_fence(obj
);
2460 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2463 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2464 * is assumed to be a power-of-two. */
2465 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2466 unsigned int tiling_mode
,
2470 if (tiling_mode
!= I915_TILING_NONE
) {
2471 unsigned int tile_rows
, tiles
;
2476 tiles
= *x
/ (512/cpp
);
2479 return tile_rows
* pitch
* 8 + tiles
* 4096;
2481 unsigned int offset
;
2483 offset
= *y
* pitch
+ *x
* cpp
;
2485 *x
= (offset
& 4095) / cpp
;
2486 return offset
& -4096;
2490 static int i9xx_format_to_fourcc(int format
)
2493 case DISPPLANE_8BPP
:
2494 return DRM_FORMAT_C8
;
2495 case DISPPLANE_BGRX555
:
2496 return DRM_FORMAT_XRGB1555
;
2497 case DISPPLANE_BGRX565
:
2498 return DRM_FORMAT_RGB565
;
2500 case DISPPLANE_BGRX888
:
2501 return DRM_FORMAT_XRGB8888
;
2502 case DISPPLANE_RGBX888
:
2503 return DRM_FORMAT_XBGR8888
;
2504 case DISPPLANE_BGRX101010
:
2505 return DRM_FORMAT_XRGB2101010
;
2506 case DISPPLANE_RGBX101010
:
2507 return DRM_FORMAT_XBGR2101010
;
2511 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2514 case PLANE_CTL_FORMAT_RGB_565
:
2515 return DRM_FORMAT_RGB565
;
2517 case PLANE_CTL_FORMAT_XRGB_8888
:
2520 return DRM_FORMAT_ABGR8888
;
2522 return DRM_FORMAT_XBGR8888
;
2525 return DRM_FORMAT_ARGB8888
;
2527 return DRM_FORMAT_XRGB8888
;
2529 case PLANE_CTL_FORMAT_XRGB_2101010
:
2531 return DRM_FORMAT_XBGR2101010
;
2533 return DRM_FORMAT_XRGB2101010
;
2538 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2539 struct intel_initial_plane_config
*plane_config
)
2541 struct drm_device
*dev
= crtc
->base
.dev
;
2542 struct drm_i915_gem_object
*obj
= NULL
;
2543 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2544 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2545 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2546 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2549 size_aligned
-= base_aligned
;
2551 if (plane_config
->size
== 0)
2554 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2561 obj
->tiling_mode
= plane_config
->tiling
;
2562 if (obj
->tiling_mode
== I915_TILING_X
)
2563 obj
->stride
= fb
->pitches
[0];
2565 mode_cmd
.pixel_format
= fb
->pixel_format
;
2566 mode_cmd
.width
= fb
->width
;
2567 mode_cmd
.height
= fb
->height
;
2568 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2569 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2570 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2572 mutex_lock(&dev
->struct_mutex
);
2573 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2575 DRM_DEBUG_KMS("intel fb init failed\n");
2578 mutex_unlock(&dev
->struct_mutex
);
2580 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2584 drm_gem_object_unreference(&obj
->base
);
2585 mutex_unlock(&dev
->struct_mutex
);
2589 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2591 update_state_fb(struct drm_plane
*plane
)
2593 if (plane
->fb
== plane
->state
->fb
)
2596 if (plane
->state
->fb
)
2597 drm_framebuffer_unreference(plane
->state
->fb
);
2598 plane
->state
->fb
= plane
->fb
;
2599 if (plane
->state
->fb
)
2600 drm_framebuffer_reference(plane
->state
->fb
);
2604 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2605 struct intel_initial_plane_config
*plane_config
)
2607 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2608 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2610 struct intel_crtc
*i
;
2611 struct drm_i915_gem_object
*obj
;
2612 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2613 struct drm_framebuffer
*fb
;
2615 if (!plane_config
->fb
)
2618 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2619 fb
= &plane_config
->fb
->base
;
2623 kfree(plane_config
->fb
);
2626 * Failed to alloc the obj, check to see if we should share
2627 * an fb with another CRTC instead
2629 for_each_crtc(dev
, c
) {
2630 i
= to_intel_crtc(c
);
2632 if (c
== &intel_crtc
->base
)
2638 fb
= c
->primary
->fb
;
2642 obj
= intel_fb_obj(fb
);
2643 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2644 drm_framebuffer_reference(fb
);
2652 obj
= intel_fb_obj(fb
);
2653 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2654 dev_priv
->preserve_bios_swizzle
= true;
2657 primary
->state
->crtc
= &intel_crtc
->base
;
2658 primary
->crtc
= &intel_crtc
->base
;
2659 update_state_fb(primary
);
2660 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2663 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2664 struct drm_framebuffer
*fb
,
2667 struct drm_device
*dev
= crtc
->dev
;
2668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2669 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2670 struct drm_i915_gem_object
*obj
;
2671 int plane
= intel_crtc
->plane
;
2672 unsigned long linear_offset
;
2674 u32 reg
= DSPCNTR(plane
);
2677 if (!intel_crtc
->primary_enabled
) {
2679 if (INTEL_INFO(dev
)->gen
>= 4)
2680 I915_WRITE(DSPSURF(plane
), 0);
2682 I915_WRITE(DSPADDR(plane
), 0);
2687 obj
= intel_fb_obj(fb
);
2688 if (WARN_ON(obj
== NULL
))
2691 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2693 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2695 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2697 if (INTEL_INFO(dev
)->gen
< 4) {
2698 if (intel_crtc
->pipe
== PIPE_B
)
2699 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2701 /* pipesrc and dspsize control the size that is scaled from,
2702 * which should always be the user's requested size.
2704 I915_WRITE(DSPSIZE(plane
),
2705 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2706 (intel_crtc
->config
->pipe_src_w
- 1));
2707 I915_WRITE(DSPPOS(plane
), 0);
2708 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2709 I915_WRITE(PRIMSIZE(plane
),
2710 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2711 (intel_crtc
->config
->pipe_src_w
- 1));
2712 I915_WRITE(PRIMPOS(plane
), 0);
2713 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2716 switch (fb
->pixel_format
) {
2718 dspcntr
|= DISPPLANE_8BPP
;
2720 case DRM_FORMAT_XRGB1555
:
2721 case DRM_FORMAT_ARGB1555
:
2722 dspcntr
|= DISPPLANE_BGRX555
;
2724 case DRM_FORMAT_RGB565
:
2725 dspcntr
|= DISPPLANE_BGRX565
;
2727 case DRM_FORMAT_XRGB8888
:
2728 case DRM_FORMAT_ARGB8888
:
2729 dspcntr
|= DISPPLANE_BGRX888
;
2731 case DRM_FORMAT_XBGR8888
:
2732 case DRM_FORMAT_ABGR8888
:
2733 dspcntr
|= DISPPLANE_RGBX888
;
2735 case DRM_FORMAT_XRGB2101010
:
2736 case DRM_FORMAT_ARGB2101010
:
2737 dspcntr
|= DISPPLANE_BGRX101010
;
2739 case DRM_FORMAT_XBGR2101010
:
2740 case DRM_FORMAT_ABGR2101010
:
2741 dspcntr
|= DISPPLANE_RGBX101010
;
2747 if (INTEL_INFO(dev
)->gen
>= 4 &&
2748 obj
->tiling_mode
!= I915_TILING_NONE
)
2749 dspcntr
|= DISPPLANE_TILED
;
2752 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2754 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2756 if (INTEL_INFO(dev
)->gen
>= 4) {
2757 intel_crtc
->dspaddr_offset
=
2758 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2761 linear_offset
-= intel_crtc
->dspaddr_offset
;
2763 intel_crtc
->dspaddr_offset
= linear_offset
;
2766 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2767 dspcntr
|= DISPPLANE_ROTATE_180
;
2769 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2770 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2772 /* Finding the last pixel of the last line of the display
2773 data and adding to linear_offset*/
2775 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2776 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2779 I915_WRITE(reg
, dspcntr
);
2781 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2782 if (INTEL_INFO(dev
)->gen
>= 4) {
2783 I915_WRITE(DSPSURF(plane
),
2784 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2785 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2786 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2788 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2792 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2793 struct drm_framebuffer
*fb
,
2796 struct drm_device
*dev
= crtc
->dev
;
2797 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2798 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2799 struct drm_i915_gem_object
*obj
;
2800 int plane
= intel_crtc
->plane
;
2801 unsigned long linear_offset
;
2803 u32 reg
= DSPCNTR(plane
);
2806 if (!intel_crtc
->primary_enabled
) {
2808 I915_WRITE(DSPSURF(plane
), 0);
2813 obj
= intel_fb_obj(fb
);
2814 if (WARN_ON(obj
== NULL
))
2817 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2819 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2821 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2823 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2824 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2826 switch (fb
->pixel_format
) {
2828 dspcntr
|= DISPPLANE_8BPP
;
2830 case DRM_FORMAT_RGB565
:
2831 dspcntr
|= DISPPLANE_BGRX565
;
2833 case DRM_FORMAT_XRGB8888
:
2834 case DRM_FORMAT_ARGB8888
:
2835 dspcntr
|= DISPPLANE_BGRX888
;
2837 case DRM_FORMAT_XBGR8888
:
2838 case DRM_FORMAT_ABGR8888
:
2839 dspcntr
|= DISPPLANE_RGBX888
;
2841 case DRM_FORMAT_XRGB2101010
:
2842 case DRM_FORMAT_ARGB2101010
:
2843 dspcntr
|= DISPPLANE_BGRX101010
;
2845 case DRM_FORMAT_XBGR2101010
:
2846 case DRM_FORMAT_ABGR2101010
:
2847 dspcntr
|= DISPPLANE_RGBX101010
;
2853 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2854 dspcntr
|= DISPPLANE_TILED
;
2856 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2857 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2859 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2860 intel_crtc
->dspaddr_offset
=
2861 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2864 linear_offset
-= intel_crtc
->dspaddr_offset
;
2865 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2866 dspcntr
|= DISPPLANE_ROTATE_180
;
2868 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2869 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2870 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2872 /* Finding the last pixel of the last line of the display
2873 data and adding to linear_offset*/
2875 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2876 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2880 I915_WRITE(reg
, dspcntr
);
2882 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2883 I915_WRITE(DSPSURF(plane
),
2884 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2885 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2886 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2888 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2889 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2894 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2895 uint32_t pixel_format
)
2897 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2900 * The stride is either expressed as a multiple of 64 bytes
2901 * chunks for linear buffers or in number of tiles for tiled
2904 switch (fb_modifier
) {
2905 case DRM_FORMAT_MOD_NONE
:
2907 case I915_FORMAT_MOD_X_TILED
:
2908 if (INTEL_INFO(dev
)->gen
== 2)
2911 case I915_FORMAT_MOD_Y_TILED
:
2912 /* No need to check for old gens and Y tiling since this is
2913 * about the display engine and those will be blocked before
2917 case I915_FORMAT_MOD_Yf_TILED
:
2918 if (bits_per_pixel
== 8)
2923 MISSING_CASE(fb_modifier
);
2928 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2929 struct drm_i915_gem_object
*obj
)
2931 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2933 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2934 view
= &i915_ggtt_view_rotated
;
2936 return i915_gem_obj_ggtt_offset_view(obj
, view
);
2939 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
2940 struct drm_framebuffer
*fb
,
2943 struct drm_device
*dev
= crtc
->dev
;
2944 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2945 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2946 struct drm_i915_gem_object
*obj
;
2947 int pipe
= intel_crtc
->pipe
;
2948 u32 plane_ctl
, stride_div
;
2949 unsigned long surf_addr
;
2951 if (!intel_crtc
->primary_enabled
) {
2952 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
2953 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
2954 POSTING_READ(PLANE_CTL(pipe
, 0));
2958 plane_ctl
= PLANE_CTL_ENABLE
|
2959 PLANE_CTL_PIPE_GAMMA_ENABLE
|
2960 PLANE_CTL_PIPE_CSC_ENABLE
;
2962 switch (fb
->pixel_format
) {
2963 case DRM_FORMAT_RGB565
:
2964 plane_ctl
|= PLANE_CTL_FORMAT_RGB_565
;
2966 case DRM_FORMAT_XRGB8888
:
2967 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2969 case DRM_FORMAT_ARGB8888
:
2970 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2971 plane_ctl
|= PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2973 case DRM_FORMAT_XBGR8888
:
2974 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2975 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2977 case DRM_FORMAT_ABGR8888
:
2978 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2979 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_8888
;
2980 plane_ctl
|= PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
2982 case DRM_FORMAT_XRGB2101010
:
2983 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2985 case DRM_FORMAT_XBGR2101010
:
2986 plane_ctl
|= PLANE_CTL_ORDER_RGBX
;
2987 plane_ctl
|= PLANE_CTL_FORMAT_XRGB_2101010
;
2993 switch (fb
->modifier
[0]) {
2994 case DRM_FORMAT_MOD_NONE
:
2996 case I915_FORMAT_MOD_X_TILED
:
2997 plane_ctl
|= PLANE_CTL_TILED_X
;
2999 case I915_FORMAT_MOD_Y_TILED
:
3000 plane_ctl
|= PLANE_CTL_TILED_Y
;
3002 case I915_FORMAT_MOD_Yf_TILED
:
3003 plane_ctl
|= PLANE_CTL_TILED_YF
;
3006 MISSING_CASE(fb
->modifier
[0]);
3009 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3010 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
))
3011 plane_ctl
|= PLANE_CTL_ROTATE_180
;
3013 obj
= intel_fb_obj(fb
);
3014 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3016 surf_addr
= intel_plane_obj_offset(to_intel_plane(crtc
->primary
), obj
);
3018 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3019 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3020 I915_WRITE(PLANE_OFFSET(pipe
, 0), (y
<< 16) | x
);
3021 I915_WRITE(PLANE_SIZE(pipe
, 0),
3022 (intel_crtc
->config
->pipe_src_h
- 1) << 16 |
3023 (intel_crtc
->config
->pipe_src_w
- 1));
3024 I915_WRITE(PLANE_STRIDE(pipe
, 0), fb
->pitches
[0] / stride_div
);
3025 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3027 POSTING_READ(PLANE_SURF(pipe
, 0));
3030 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3032 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3033 int x
, int y
, enum mode_set_atomic state
)
3035 struct drm_device
*dev
= crtc
->dev
;
3036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3038 if (dev_priv
->display
.disable_fbc
)
3039 dev_priv
->display
.disable_fbc(dev
);
3041 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3046 static void intel_complete_page_flips(struct drm_device
*dev
)
3048 struct drm_crtc
*crtc
;
3050 for_each_crtc(dev
, crtc
) {
3051 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3052 enum plane plane
= intel_crtc
->plane
;
3054 intel_prepare_page_flip(dev
, plane
);
3055 intel_finish_page_flip_plane(dev
, plane
);
3059 static void intel_update_primary_planes(struct drm_device
*dev
)
3061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3062 struct drm_crtc
*crtc
;
3064 for_each_crtc(dev
, crtc
) {
3065 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3067 drm_modeset_lock(&crtc
->mutex
, NULL
);
3069 * FIXME: Once we have proper support for primary planes (and
3070 * disabling them without disabling the entire crtc) allow again
3071 * a NULL crtc->primary->fb.
3073 if (intel_crtc
->active
&& crtc
->primary
->fb
)
3074 dev_priv
->display
.update_primary_plane(crtc
,
3078 drm_modeset_unlock(&crtc
->mutex
);
3082 void intel_prepare_reset(struct drm_device
*dev
)
3084 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3085 struct intel_crtc
*crtc
;
3087 /* no reset support for gen2 */
3091 /* reset doesn't touch the display */
3092 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3095 drm_modeset_lock_all(dev
);
3098 * Disabling the crtcs gracefully seems nicer. Also the
3099 * g33 docs say we should at least disable all the planes.
3101 for_each_intel_crtc(dev
, crtc
) {
3103 dev_priv
->display
.crtc_disable(&crtc
->base
);
3107 void intel_finish_reset(struct drm_device
*dev
)
3109 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3112 * Flips in the rings will be nuked by the reset,
3113 * so complete all pending flips so that user space
3114 * will get its events and not get stuck.
3116 intel_complete_page_flips(dev
);
3118 /* no reset support for gen2 */
3122 /* reset doesn't touch the display */
3123 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3125 * Flips in the rings have been nuked by the reset,
3126 * so update the base address of all primary
3127 * planes to the the last fb to make sure we're
3128 * showing the correct fb after a reset.
3130 intel_update_primary_planes(dev
);
3135 * The display has been reset as well,
3136 * so need a full re-initialization.
3138 intel_runtime_pm_disable_interrupts(dev_priv
);
3139 intel_runtime_pm_enable_interrupts(dev_priv
);
3141 intel_modeset_init_hw(dev
);
3143 spin_lock_irq(&dev_priv
->irq_lock
);
3144 if (dev_priv
->display
.hpd_irq_setup
)
3145 dev_priv
->display
.hpd_irq_setup(dev
);
3146 spin_unlock_irq(&dev_priv
->irq_lock
);
3148 intel_modeset_setup_hw_state(dev
, true);
3150 intel_hpd_init(dev_priv
);
3152 drm_modeset_unlock_all(dev
);
3156 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3158 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3159 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3160 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3163 /* Big Hammer, we also need to ensure that any pending
3164 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3165 * current scanout is retired before unpinning the old
3168 * This should only fail upon a hung GPU, in which case we
3169 * can safely continue.
3171 dev_priv
->mm
.interruptible
= false;
3172 ret
= i915_gem_object_finish_gpu(obj
);
3173 dev_priv
->mm
.interruptible
= was_interruptible
;
3178 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3180 struct drm_device
*dev
= crtc
->dev
;
3181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3182 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3185 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3186 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3189 spin_lock_irq(&dev
->event_lock
);
3190 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3191 spin_unlock_irq(&dev
->event_lock
);
3196 static void intel_update_pipe_size(struct intel_crtc
*crtc
)
3198 struct drm_device
*dev
= crtc
->base
.dev
;
3199 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3200 const struct drm_display_mode
*adjusted_mode
;
3206 * Update pipe size and adjust fitter if needed: the reason for this is
3207 * that in compute_mode_changes we check the native mode (not the pfit
3208 * mode) to see if we can flip rather than do a full mode set. In the
3209 * fastboot case, we'll flip, but if we don't update the pipesrc and
3210 * pfit state, we'll end up with a big fb scanned out into the wrong
3213 * To fix this properly, we need to hoist the checks up into
3214 * compute_mode_changes (or above), check the actual pfit state and
3215 * whether the platform allows pfit disable with pipe active, and only
3216 * then update the pipesrc and pfit state, even on the flip path.
3219 adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
3221 I915_WRITE(PIPESRC(crtc
->pipe
),
3222 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
3223 (adjusted_mode
->crtc_vdisplay
- 1));
3224 if (!crtc
->config
->pch_pfit
.enabled
&&
3225 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
3226 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3227 I915_WRITE(PF_CTL(crtc
->pipe
), 0);
3228 I915_WRITE(PF_WIN_POS(crtc
->pipe
), 0);
3229 I915_WRITE(PF_WIN_SZ(crtc
->pipe
), 0);
3231 crtc
->config
->pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
3232 crtc
->config
->pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
3235 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3237 struct drm_device
*dev
= crtc
->dev
;
3238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3239 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3240 int pipe
= intel_crtc
->pipe
;
3243 /* enable normal train */
3244 reg
= FDI_TX_CTL(pipe
);
3245 temp
= I915_READ(reg
);
3246 if (IS_IVYBRIDGE(dev
)) {
3247 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3248 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3250 temp
&= ~FDI_LINK_TRAIN_NONE
;
3251 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3253 I915_WRITE(reg
, temp
);
3255 reg
= FDI_RX_CTL(pipe
);
3256 temp
= I915_READ(reg
);
3257 if (HAS_PCH_CPT(dev
)) {
3258 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3259 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3261 temp
&= ~FDI_LINK_TRAIN_NONE
;
3262 temp
|= FDI_LINK_TRAIN_NONE
;
3264 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3266 /* wait one idle pattern time */
3270 /* IVB wants error correction enabled */
3271 if (IS_IVYBRIDGE(dev
))
3272 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3273 FDI_FE_ERRC_ENABLE
);
3276 /* The FDI link training functions for ILK/Ibexpeak. */
3277 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3279 struct drm_device
*dev
= crtc
->dev
;
3280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3281 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3282 int pipe
= intel_crtc
->pipe
;
3283 u32 reg
, temp
, tries
;
3285 /* FDI needs bits from pipe first */
3286 assert_pipe_enabled(dev_priv
, pipe
);
3288 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3290 reg
= FDI_RX_IMR(pipe
);
3291 temp
= I915_READ(reg
);
3292 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3293 temp
&= ~FDI_RX_BIT_LOCK
;
3294 I915_WRITE(reg
, temp
);
3298 /* enable CPU FDI TX and PCH FDI RX */
3299 reg
= FDI_TX_CTL(pipe
);
3300 temp
= I915_READ(reg
);
3301 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3302 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3303 temp
&= ~FDI_LINK_TRAIN_NONE
;
3304 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3305 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3307 reg
= FDI_RX_CTL(pipe
);
3308 temp
= I915_READ(reg
);
3309 temp
&= ~FDI_LINK_TRAIN_NONE
;
3310 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3311 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3316 /* Ironlake workaround, enable clock pointer after FDI enable*/
3317 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3318 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3319 FDI_RX_PHASE_SYNC_POINTER_EN
);
3321 reg
= FDI_RX_IIR(pipe
);
3322 for (tries
= 0; tries
< 5; tries
++) {
3323 temp
= I915_READ(reg
);
3324 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3326 if ((temp
& FDI_RX_BIT_LOCK
)) {
3327 DRM_DEBUG_KMS("FDI train 1 done.\n");
3328 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3333 DRM_ERROR("FDI train 1 fail!\n");
3336 reg
= FDI_TX_CTL(pipe
);
3337 temp
= I915_READ(reg
);
3338 temp
&= ~FDI_LINK_TRAIN_NONE
;
3339 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3340 I915_WRITE(reg
, temp
);
3342 reg
= FDI_RX_CTL(pipe
);
3343 temp
= I915_READ(reg
);
3344 temp
&= ~FDI_LINK_TRAIN_NONE
;
3345 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3346 I915_WRITE(reg
, temp
);
3351 reg
= FDI_RX_IIR(pipe
);
3352 for (tries
= 0; tries
< 5; tries
++) {
3353 temp
= I915_READ(reg
);
3354 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3356 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3357 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3358 DRM_DEBUG_KMS("FDI train 2 done.\n");
3363 DRM_ERROR("FDI train 2 fail!\n");
3365 DRM_DEBUG_KMS("FDI train done\n");
3369 static const int snb_b_fdi_train_param
[] = {
3370 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3371 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3372 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3373 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3376 /* The FDI link training functions for SNB/Cougarpoint. */
3377 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3379 struct drm_device
*dev
= crtc
->dev
;
3380 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3381 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3382 int pipe
= intel_crtc
->pipe
;
3383 u32 reg
, temp
, i
, retry
;
3385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3387 reg
= FDI_RX_IMR(pipe
);
3388 temp
= I915_READ(reg
);
3389 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3390 temp
&= ~FDI_RX_BIT_LOCK
;
3391 I915_WRITE(reg
, temp
);
3396 /* enable CPU FDI TX and PCH FDI RX */
3397 reg
= FDI_TX_CTL(pipe
);
3398 temp
= I915_READ(reg
);
3399 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3400 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3401 temp
&= ~FDI_LINK_TRAIN_NONE
;
3402 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3403 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3405 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3406 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3408 I915_WRITE(FDI_RX_MISC(pipe
),
3409 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3411 reg
= FDI_RX_CTL(pipe
);
3412 temp
= I915_READ(reg
);
3413 if (HAS_PCH_CPT(dev
)) {
3414 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3415 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3417 temp
&= ~FDI_LINK_TRAIN_NONE
;
3418 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3420 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3425 for (i
= 0; i
< 4; i
++) {
3426 reg
= FDI_TX_CTL(pipe
);
3427 temp
= I915_READ(reg
);
3428 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3429 temp
|= snb_b_fdi_train_param
[i
];
3430 I915_WRITE(reg
, temp
);
3435 for (retry
= 0; retry
< 5; retry
++) {
3436 reg
= FDI_RX_IIR(pipe
);
3437 temp
= I915_READ(reg
);
3438 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3439 if (temp
& FDI_RX_BIT_LOCK
) {
3440 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3441 DRM_DEBUG_KMS("FDI train 1 done.\n");
3450 DRM_ERROR("FDI train 1 fail!\n");
3453 reg
= FDI_TX_CTL(pipe
);
3454 temp
= I915_READ(reg
);
3455 temp
&= ~FDI_LINK_TRAIN_NONE
;
3456 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3458 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3460 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3462 I915_WRITE(reg
, temp
);
3464 reg
= FDI_RX_CTL(pipe
);
3465 temp
= I915_READ(reg
);
3466 if (HAS_PCH_CPT(dev
)) {
3467 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3468 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3470 temp
&= ~FDI_LINK_TRAIN_NONE
;
3471 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3473 I915_WRITE(reg
, temp
);
3478 for (i
= 0; i
< 4; i
++) {
3479 reg
= FDI_TX_CTL(pipe
);
3480 temp
= I915_READ(reg
);
3481 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3482 temp
|= snb_b_fdi_train_param
[i
];
3483 I915_WRITE(reg
, temp
);
3488 for (retry
= 0; retry
< 5; retry
++) {
3489 reg
= FDI_RX_IIR(pipe
);
3490 temp
= I915_READ(reg
);
3491 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3492 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3493 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3494 DRM_DEBUG_KMS("FDI train 2 done.\n");
3503 DRM_ERROR("FDI train 2 fail!\n");
3505 DRM_DEBUG_KMS("FDI train done.\n");
3508 /* Manual link training for Ivy Bridge A0 parts */
3509 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3511 struct drm_device
*dev
= crtc
->dev
;
3512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3514 int pipe
= intel_crtc
->pipe
;
3515 u32 reg
, temp
, i
, j
;
3517 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3519 reg
= FDI_RX_IMR(pipe
);
3520 temp
= I915_READ(reg
);
3521 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3522 temp
&= ~FDI_RX_BIT_LOCK
;
3523 I915_WRITE(reg
, temp
);
3528 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3529 I915_READ(FDI_RX_IIR(pipe
)));
3531 /* Try each vswing and preemphasis setting twice before moving on */
3532 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3533 /* disable first in case we need to retry */
3534 reg
= FDI_TX_CTL(pipe
);
3535 temp
= I915_READ(reg
);
3536 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3537 temp
&= ~FDI_TX_ENABLE
;
3538 I915_WRITE(reg
, temp
);
3540 reg
= FDI_RX_CTL(pipe
);
3541 temp
= I915_READ(reg
);
3542 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3543 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3544 temp
&= ~FDI_RX_ENABLE
;
3545 I915_WRITE(reg
, temp
);
3547 /* enable CPU FDI TX and PCH FDI RX */
3548 reg
= FDI_TX_CTL(pipe
);
3549 temp
= I915_READ(reg
);
3550 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3551 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3552 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3553 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3554 temp
|= snb_b_fdi_train_param
[j
/2];
3555 temp
|= FDI_COMPOSITE_SYNC
;
3556 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3558 I915_WRITE(FDI_RX_MISC(pipe
),
3559 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3561 reg
= FDI_RX_CTL(pipe
);
3562 temp
= I915_READ(reg
);
3563 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3564 temp
|= FDI_COMPOSITE_SYNC
;
3565 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3568 udelay(1); /* should be 0.5us */
3570 for (i
= 0; i
< 4; i
++) {
3571 reg
= FDI_RX_IIR(pipe
);
3572 temp
= I915_READ(reg
);
3573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3575 if (temp
& FDI_RX_BIT_LOCK
||
3576 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3577 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3578 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3582 udelay(1); /* should be 0.5us */
3585 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3590 reg
= FDI_TX_CTL(pipe
);
3591 temp
= I915_READ(reg
);
3592 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3593 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3594 I915_WRITE(reg
, temp
);
3596 reg
= FDI_RX_CTL(pipe
);
3597 temp
= I915_READ(reg
);
3598 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3599 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3600 I915_WRITE(reg
, temp
);
3603 udelay(2); /* should be 1.5us */
3605 for (i
= 0; i
< 4; i
++) {
3606 reg
= FDI_RX_IIR(pipe
);
3607 temp
= I915_READ(reg
);
3608 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3610 if (temp
& FDI_RX_SYMBOL_LOCK
||
3611 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3612 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3613 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3617 udelay(2); /* should be 1.5us */
3620 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3624 DRM_DEBUG_KMS("FDI train done.\n");
3627 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3629 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3630 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3631 int pipe
= intel_crtc
->pipe
;
3635 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3636 reg
= FDI_RX_CTL(pipe
);
3637 temp
= I915_READ(reg
);
3638 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3639 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3640 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3641 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3646 /* Switch from Rawclk to PCDclk */
3647 temp
= I915_READ(reg
);
3648 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3653 /* Enable CPU FDI TX PLL, always on for Ironlake */
3654 reg
= FDI_TX_CTL(pipe
);
3655 temp
= I915_READ(reg
);
3656 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3657 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3664 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3666 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3667 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3668 int pipe
= intel_crtc
->pipe
;
3671 /* Switch from PCDclk to Rawclk */
3672 reg
= FDI_RX_CTL(pipe
);
3673 temp
= I915_READ(reg
);
3674 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3676 /* Disable CPU FDI TX PLL */
3677 reg
= FDI_TX_CTL(pipe
);
3678 temp
= I915_READ(reg
);
3679 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3684 reg
= FDI_RX_CTL(pipe
);
3685 temp
= I915_READ(reg
);
3686 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3688 /* Wait for the clocks to turn off. */
3693 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3695 struct drm_device
*dev
= crtc
->dev
;
3696 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3697 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3698 int pipe
= intel_crtc
->pipe
;
3701 /* disable CPU FDI tx and PCH FDI rx */
3702 reg
= FDI_TX_CTL(pipe
);
3703 temp
= I915_READ(reg
);
3704 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3707 reg
= FDI_RX_CTL(pipe
);
3708 temp
= I915_READ(reg
);
3709 temp
&= ~(0x7 << 16);
3710 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3711 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3716 /* Ironlake workaround, disable clock pointer after downing FDI */
3717 if (HAS_PCH_IBX(dev
))
3718 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3720 /* still set train pattern 1 */
3721 reg
= FDI_TX_CTL(pipe
);
3722 temp
= I915_READ(reg
);
3723 temp
&= ~FDI_LINK_TRAIN_NONE
;
3724 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3725 I915_WRITE(reg
, temp
);
3727 reg
= FDI_RX_CTL(pipe
);
3728 temp
= I915_READ(reg
);
3729 if (HAS_PCH_CPT(dev
)) {
3730 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3731 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3733 temp
&= ~FDI_LINK_TRAIN_NONE
;
3734 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3736 /* BPC in FDI rx is consistent with that in PIPECONF */
3737 temp
&= ~(0x07 << 16);
3738 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3739 I915_WRITE(reg
, temp
);
3745 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3747 struct intel_crtc
*crtc
;
3749 /* Note that we don't need to be called with mode_config.lock here
3750 * as our list of CRTC objects is static for the lifetime of the
3751 * device and so cannot disappear as we iterate. Similarly, we can
3752 * happily treat the predicates as racy, atomic checks as userspace
3753 * cannot claim and pin a new fb without at least acquring the
3754 * struct_mutex and so serialising with us.
3756 for_each_intel_crtc(dev
, crtc
) {
3757 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3760 if (crtc
->unpin_work
)
3761 intel_wait_for_vblank(dev
, crtc
->pipe
);
3769 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3771 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3772 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3774 /* ensure that the unpin work is consistent wrt ->pending. */
3776 intel_crtc
->unpin_work
= NULL
;
3779 drm_send_vblank_event(intel_crtc
->base
.dev
,
3783 drm_crtc_vblank_put(&intel_crtc
->base
);
3785 wake_up_all(&dev_priv
->pending_flip_queue
);
3786 queue_work(dev_priv
->wq
, &work
->work
);
3788 trace_i915_flip_complete(intel_crtc
->plane
,
3789 work
->pending_flip_obj
);
3792 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3794 struct drm_device
*dev
= crtc
->dev
;
3795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3797 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3798 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3799 !intel_crtc_has_pending_flip(crtc
),
3801 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3803 spin_lock_irq(&dev
->event_lock
);
3804 if (intel_crtc
->unpin_work
) {
3805 WARN_ONCE(1, "Removing stuck page flip\n");
3806 page_flip_completed(intel_crtc
);
3808 spin_unlock_irq(&dev
->event_lock
);
3811 if (crtc
->primary
->fb
) {
3812 mutex_lock(&dev
->struct_mutex
);
3813 intel_finish_fb(crtc
->primary
->fb
);
3814 mutex_unlock(&dev
->struct_mutex
);
3818 /* Program iCLKIP clock to the desired frequency */
3819 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3821 struct drm_device
*dev
= crtc
->dev
;
3822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3823 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3824 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3827 mutex_lock(&dev_priv
->dpio_lock
);
3829 /* It is necessary to ungate the pixclk gate prior to programming
3830 * the divisors, and gate it back when it is done.
3832 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3834 /* Disable SSCCTL */
3835 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3836 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3840 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3841 if (clock
== 20000) {
3846 /* The iCLK virtual clock root frequency is in MHz,
3847 * but the adjusted_mode->crtc_clock in in KHz. To get the
3848 * divisors, it is necessary to divide one by another, so we
3849 * convert the virtual clock precision to KHz here for higher
3852 u32 iclk_virtual_root_freq
= 172800 * 1000;
3853 u32 iclk_pi_range
= 64;
3854 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3856 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3857 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3858 pi_value
= desired_divisor
% iclk_pi_range
;
3861 divsel
= msb_divisor_value
- 2;
3862 phaseinc
= pi_value
;
3865 /* This should not happen with any sane values */
3866 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3867 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3868 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3869 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3871 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3878 /* Program SSCDIVINTPHASE6 */
3879 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3880 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3881 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3882 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3883 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3884 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3885 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3886 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3888 /* Program SSCAUXDIV */
3889 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3890 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3891 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3892 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3894 /* Enable modulator and associated divider */
3895 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3896 temp
&= ~SBI_SSCCTL_DISABLE
;
3897 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3899 /* Wait for initialization time */
3902 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3904 mutex_unlock(&dev_priv
->dpio_lock
);
3907 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3908 enum pipe pch_transcoder
)
3910 struct drm_device
*dev
= crtc
->base
.dev
;
3911 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3912 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
3914 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3915 I915_READ(HTOTAL(cpu_transcoder
)));
3916 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3917 I915_READ(HBLANK(cpu_transcoder
)));
3918 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3919 I915_READ(HSYNC(cpu_transcoder
)));
3921 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3922 I915_READ(VTOTAL(cpu_transcoder
)));
3923 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3924 I915_READ(VBLANK(cpu_transcoder
)));
3925 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3926 I915_READ(VSYNC(cpu_transcoder
)));
3927 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3928 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3931 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
3933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3936 temp
= I915_READ(SOUTH_CHICKEN1
);
3937 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
3940 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3941 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3943 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
3945 temp
|= FDI_BC_BIFURCATION_SELECT
;
3947 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
3948 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3949 POSTING_READ(SOUTH_CHICKEN1
);
3952 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3954 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3956 switch (intel_crtc
->pipe
) {
3960 if (intel_crtc
->config
->fdi_lanes
> 2)
3961 cpt_set_fdi_bc_bifurcation(dev
, false);
3963 cpt_set_fdi_bc_bifurcation(dev
, true);
3967 cpt_set_fdi_bc_bifurcation(dev
, true);
3976 * Enable PCH resources required for PCH ports:
3978 * - FDI training & RX/TX
3979 * - update transcoder timings
3980 * - DP transcoding bits
3983 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3985 struct drm_device
*dev
= crtc
->dev
;
3986 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3987 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3988 int pipe
= intel_crtc
->pipe
;
3991 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3993 if (IS_IVYBRIDGE(dev
))
3994 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3996 /* Write the TU size bits before fdi link training, so that error
3997 * detection works. */
3998 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3999 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4001 /* For PCH output, training FDI link */
4002 dev_priv
->display
.fdi_link_train(crtc
);
4004 /* We need to program the right clock selection before writing the pixel
4005 * mutliplier into the DPLL. */
4006 if (HAS_PCH_CPT(dev
)) {
4009 temp
= I915_READ(PCH_DPLL_SEL
);
4010 temp
|= TRANS_DPLL_ENABLE(pipe
);
4011 sel
= TRANS_DPLLB_SEL(pipe
);
4012 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4016 I915_WRITE(PCH_DPLL_SEL
, temp
);
4019 /* XXX: pch pll's can be enabled any time before we enable the PCH
4020 * transcoder, and we actually should do this to not upset any PCH
4021 * transcoder that already use the clock when we share it.
4023 * Note that enable_shared_dpll tries to do the right thing, but
4024 * get_shared_dpll unconditionally resets the pll - we need that to have
4025 * the right LVDS enable sequence. */
4026 intel_enable_shared_dpll(intel_crtc
);
4028 /* set transcoder timing, panel must allow it */
4029 assert_panel_unlocked(dev_priv
, pipe
);
4030 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4032 intel_fdi_normal_train(crtc
);
4034 /* For PCH DP, enable TRANS_DP_CTL */
4035 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4036 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4037 reg
= TRANS_DP_CTL(pipe
);
4038 temp
= I915_READ(reg
);
4039 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4040 TRANS_DP_SYNC_MASK
|
4042 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
4043 TRANS_DP_ENH_FRAMING
);
4044 temp
|= bpc
<< 9; /* same format but at 11:9 */
4046 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4047 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4048 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4049 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4051 switch (intel_trans_dp_port_sel(crtc
)) {
4053 temp
|= TRANS_DP_PORT_SEL_B
;
4056 temp
|= TRANS_DP_PORT_SEL_C
;
4059 temp
|= TRANS_DP_PORT_SEL_D
;
4065 I915_WRITE(reg
, temp
);
4068 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4071 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4073 struct drm_device
*dev
= crtc
->dev
;
4074 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4075 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4076 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4078 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4080 lpt_program_iclkip(crtc
);
4082 /* Set transcoder timing. */
4083 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4085 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4088 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
4090 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
4095 if (!(pll
->config
.crtc_mask
& (1 << crtc
->pipe
))) {
4096 WARN(1, "bad %s crtc mask\n", pll
->name
);
4100 pll
->config
.crtc_mask
&= ~(1 << crtc
->pipe
);
4101 if (pll
->config
.crtc_mask
== 0) {
4103 WARN_ON(pll
->active
);
4106 crtc
->config
->shared_dpll
= DPLL_ID_PRIVATE
;
4109 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4110 struct intel_crtc_state
*crtc_state
)
4112 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4113 struct intel_shared_dpll
*pll
;
4114 enum intel_dpll_id i
;
4116 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4117 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4118 i
= (enum intel_dpll_id
) crtc
->pipe
;
4119 pll
= &dev_priv
->shared_dplls
[i
];
4121 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4122 crtc
->base
.base
.id
, pll
->name
);
4124 WARN_ON(pll
->new_config
->crtc_mask
);
4129 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4130 pll
= &dev_priv
->shared_dplls
[i
];
4132 /* Only want to check enabled timings first */
4133 if (pll
->new_config
->crtc_mask
== 0)
4136 if (memcmp(&crtc_state
->dpll_hw_state
,
4137 &pll
->new_config
->hw_state
,
4138 sizeof(pll
->new_config
->hw_state
)) == 0) {
4139 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4140 crtc
->base
.base
.id
, pll
->name
,
4141 pll
->new_config
->crtc_mask
,
4147 /* Ok no matching timings, maybe there's a free one? */
4148 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4149 pll
= &dev_priv
->shared_dplls
[i
];
4150 if (pll
->new_config
->crtc_mask
== 0) {
4151 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4152 crtc
->base
.base
.id
, pll
->name
);
4160 if (pll
->new_config
->crtc_mask
== 0)
4161 pll
->new_config
->hw_state
= crtc_state
->dpll_hw_state
;
4163 crtc_state
->shared_dpll
= i
;
4164 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4165 pipe_name(crtc
->pipe
));
4167 pll
->new_config
->crtc_mask
|= 1 << crtc
->pipe
;
4173 * intel_shared_dpll_start_config - start a new PLL staged config
4174 * @dev_priv: DRM device
4175 * @clear_pipes: mask of pipes that will have their PLLs freed
4177 * Starts a new PLL staged config, copying the current config but
4178 * releasing the references of pipes specified in clear_pipes.
4180 static int intel_shared_dpll_start_config(struct drm_i915_private
*dev_priv
,
4181 unsigned clear_pipes
)
4183 struct intel_shared_dpll
*pll
;
4184 enum intel_dpll_id i
;
4186 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4187 pll
= &dev_priv
->shared_dplls
[i
];
4189 pll
->new_config
= kmemdup(&pll
->config
, sizeof pll
->config
,
4191 if (!pll
->new_config
)
4194 pll
->new_config
->crtc_mask
&= ~clear_pipes
;
4201 pll
= &dev_priv
->shared_dplls
[i
];
4202 kfree(pll
->new_config
);
4203 pll
->new_config
= NULL
;
4209 static void intel_shared_dpll_commit(struct drm_i915_private
*dev_priv
)
4211 struct intel_shared_dpll
*pll
;
4212 enum intel_dpll_id i
;
4214 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4215 pll
= &dev_priv
->shared_dplls
[i
];
4217 WARN_ON(pll
->new_config
== &pll
->config
);
4219 pll
->config
= *pll
->new_config
;
4220 kfree(pll
->new_config
);
4221 pll
->new_config
= NULL
;
4225 static void intel_shared_dpll_abort_config(struct drm_i915_private
*dev_priv
)
4227 struct intel_shared_dpll
*pll
;
4228 enum intel_dpll_id i
;
4230 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4231 pll
= &dev_priv
->shared_dplls
[i
];
4233 WARN_ON(pll
->new_config
== &pll
->config
);
4235 kfree(pll
->new_config
);
4236 pll
->new_config
= NULL
;
4240 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4243 int dslreg
= PIPEDSL(pipe
);
4246 temp
= I915_READ(dslreg
);
4248 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4249 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4250 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4254 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4256 struct drm_device
*dev
= crtc
->base
.dev
;
4257 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4258 int pipe
= crtc
->pipe
;
4260 if (crtc
->config
->pch_pfit
.enabled
) {
4261 I915_WRITE(PS_CTL(pipe
), PS_ENABLE
);
4262 I915_WRITE(PS_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4263 I915_WRITE(PS_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4267 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4269 struct drm_device
*dev
= crtc
->base
.dev
;
4270 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4271 int pipe
= crtc
->pipe
;
4273 if (crtc
->config
->pch_pfit
.enabled
) {
4274 /* Force use of hard-coded filter coefficients
4275 * as some pre-programmed values are broken,
4278 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4279 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4280 PF_PIPE_SEL_IVB(pipe
));
4282 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4283 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4284 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4288 static void intel_enable_sprite_planes(struct drm_crtc
*crtc
)
4290 struct drm_device
*dev
= crtc
->dev
;
4291 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4292 struct drm_plane
*plane
;
4293 struct intel_plane
*intel_plane
;
4295 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4296 intel_plane
= to_intel_plane(plane
);
4297 if (intel_plane
->pipe
== pipe
)
4298 intel_plane_restore(&intel_plane
->base
);
4303 * Disable a plane internally without actually modifying the plane's state.
4304 * This will allow us to easily restore the plane later by just reprogramming
4307 static void disable_plane_internal(struct drm_plane
*plane
)
4309 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
4310 struct drm_plane_state
*state
=
4311 plane
->funcs
->atomic_duplicate_state(plane
);
4312 struct intel_plane_state
*intel_state
= to_intel_plane_state(state
);
4314 intel_state
->visible
= false;
4315 intel_plane
->commit_plane(plane
, intel_state
);
4317 intel_plane_destroy_state(plane
, state
);
4320 static void intel_disable_sprite_planes(struct drm_crtc
*crtc
)
4322 struct drm_device
*dev
= crtc
->dev
;
4323 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4324 struct drm_plane
*plane
;
4325 struct intel_plane
*intel_plane
;
4327 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
4328 intel_plane
= to_intel_plane(plane
);
4329 if (plane
->fb
&& intel_plane
->pipe
== pipe
)
4330 disable_plane_internal(plane
);
4334 void hsw_enable_ips(struct intel_crtc
*crtc
)
4336 struct drm_device
*dev
= crtc
->base
.dev
;
4337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4339 if (!crtc
->config
->ips_enabled
)
4342 /* We can only enable IPS after we enable a plane and wait for a vblank */
4343 intel_wait_for_vblank(dev
, crtc
->pipe
);
4345 assert_plane_enabled(dev_priv
, crtc
->plane
);
4346 if (IS_BROADWELL(dev
)) {
4347 mutex_lock(&dev_priv
->rps
.hw_lock
);
4348 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4349 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4350 /* Quoting Art Runyan: "its not safe to expect any particular
4351 * value in IPS_CTL bit 31 after enabling IPS through the
4352 * mailbox." Moreover, the mailbox may return a bogus state,
4353 * so we need to just enable it and continue on.
4356 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4357 /* The bit only becomes 1 in the next vblank, so this wait here
4358 * is essentially intel_wait_for_vblank. If we don't have this
4359 * and don't wait for vblanks until the end of crtc_enable, then
4360 * the HW state readout code will complain that the expected
4361 * IPS_CTL value is not the one we read. */
4362 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4363 DRM_ERROR("Timed out waiting for IPS enable\n");
4367 void hsw_disable_ips(struct intel_crtc
*crtc
)
4369 struct drm_device
*dev
= crtc
->base
.dev
;
4370 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4372 if (!crtc
->config
->ips_enabled
)
4375 assert_plane_enabled(dev_priv
, crtc
->plane
);
4376 if (IS_BROADWELL(dev
)) {
4377 mutex_lock(&dev_priv
->rps
.hw_lock
);
4378 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4379 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4380 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4381 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4382 DRM_ERROR("Timed out waiting for IPS disable\n");
4384 I915_WRITE(IPS_CTL
, 0);
4385 POSTING_READ(IPS_CTL
);
4388 /* We need to wait for a vblank before we can disable the plane. */
4389 intel_wait_for_vblank(dev
, crtc
->pipe
);
4392 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4393 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4395 struct drm_device
*dev
= crtc
->dev
;
4396 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4397 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4398 enum pipe pipe
= intel_crtc
->pipe
;
4399 int palreg
= PALETTE(pipe
);
4401 bool reenable_ips
= false;
4403 /* The clocks have to be on to load the palette. */
4404 if (!crtc
->state
->enable
|| !intel_crtc
->active
)
4407 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
4408 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4409 assert_dsi_pll_enabled(dev_priv
);
4411 assert_pll_enabled(dev_priv
, pipe
);
4414 /* use legacy palette for Ironlake */
4415 if (!HAS_GMCH_DISPLAY(dev
))
4416 palreg
= LGC_PALETTE(pipe
);
4418 /* Workaround : Do not read or write the pipe palette/gamma data while
4419 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4421 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4422 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4423 GAMMA_MODE_MODE_SPLIT
)) {
4424 hsw_disable_ips(intel_crtc
);
4425 reenable_ips
= true;
4428 for (i
= 0; i
< 256; i
++) {
4429 I915_WRITE(palreg
+ 4 * i
,
4430 (intel_crtc
->lut_r
[i
] << 16) |
4431 (intel_crtc
->lut_g
[i
] << 8) |
4432 intel_crtc
->lut_b
[i
]);
4436 hsw_enable_ips(intel_crtc
);
4439 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
4441 if (!enable
&& intel_crtc
->overlay
) {
4442 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4443 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4445 mutex_lock(&dev
->struct_mutex
);
4446 dev_priv
->mm
.interruptible
= false;
4447 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4448 dev_priv
->mm
.interruptible
= true;
4449 mutex_unlock(&dev
->struct_mutex
);
4452 /* Let userspace switch the overlay on again. In most cases userspace
4453 * has to recompute where to put it anyway.
4457 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
4459 struct drm_device
*dev
= crtc
->dev
;
4460 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4461 int pipe
= intel_crtc
->pipe
;
4463 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
4464 intel_enable_sprite_planes(crtc
);
4465 intel_crtc_update_cursor(crtc
, true);
4466 intel_crtc_dpms_overlay(intel_crtc
, true);
4468 hsw_enable_ips(intel_crtc
);
4470 mutex_lock(&dev
->struct_mutex
);
4471 intel_fbc_update(dev
);
4472 mutex_unlock(&dev
->struct_mutex
);
4475 * FIXME: Once we grow proper nuclear flip support out of this we need
4476 * to compute the mask of flip planes precisely. For the time being
4477 * consider this a flip from a NULL plane.
4479 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4482 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
4484 struct drm_device
*dev
= crtc
->dev
;
4485 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4486 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4487 int pipe
= intel_crtc
->pipe
;
4489 intel_crtc_wait_for_pending_flips(crtc
);
4491 if (dev_priv
->fbc
.crtc
== intel_crtc
)
4492 intel_fbc_disable(dev
);
4494 hsw_disable_ips(intel_crtc
);
4496 intel_crtc_dpms_overlay(intel_crtc
, false);
4497 intel_crtc_update_cursor(crtc
, false);
4498 intel_disable_sprite_planes(crtc
);
4499 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
4502 * FIXME: Once we grow proper nuclear flip support out of this we need
4503 * to compute the mask of flip planes precisely. For the time being
4504 * consider this a flip to a NULL plane.
4506 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4509 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4511 struct drm_device
*dev
= crtc
->dev
;
4512 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4513 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4514 struct intel_encoder
*encoder
;
4515 int pipe
= intel_crtc
->pipe
;
4517 WARN_ON(!crtc
->state
->enable
);
4519 if (intel_crtc
->active
)
4522 if (intel_crtc
->config
->has_pch_encoder
)
4523 intel_prepare_shared_dpll(intel_crtc
);
4525 if (intel_crtc
->config
->has_dp_encoder
)
4526 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4528 intel_set_pipe_timings(intel_crtc
);
4530 if (intel_crtc
->config
->has_pch_encoder
) {
4531 intel_cpu_transcoder_set_m_n(intel_crtc
,
4532 &intel_crtc
->config
->fdi_m_n
, NULL
);
4535 ironlake_set_pipeconf(crtc
);
4537 intel_crtc
->active
= true;
4539 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4540 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4542 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4543 if (encoder
->pre_enable
)
4544 encoder
->pre_enable(encoder
);
4546 if (intel_crtc
->config
->has_pch_encoder
) {
4547 /* Note: FDI PLL enabling _must_ be done before we enable the
4548 * cpu pipes, hence this is separate from all the other fdi/pch
4550 ironlake_fdi_pll_enable(intel_crtc
);
4552 assert_fdi_tx_disabled(dev_priv
, pipe
);
4553 assert_fdi_rx_disabled(dev_priv
, pipe
);
4556 ironlake_pfit_enable(intel_crtc
);
4559 * On ILK+ LUT must be loaded before the pipe is running but with
4562 intel_crtc_load_lut(crtc
);
4564 intel_update_watermarks(crtc
);
4565 intel_enable_pipe(intel_crtc
);
4567 if (intel_crtc
->config
->has_pch_encoder
)
4568 ironlake_pch_enable(crtc
);
4570 assert_vblank_disabled(crtc
);
4571 drm_crtc_vblank_on(crtc
);
4573 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4574 encoder
->enable(encoder
);
4576 if (HAS_PCH_CPT(dev
))
4577 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4579 intel_crtc_enable_planes(crtc
);
4582 /* IPS only exists on ULT machines and is tied to pipe A. */
4583 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4585 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4589 * This implements the workaround described in the "notes" section of the mode
4590 * set sequence documentation. When going from no pipes or single pipe to
4591 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4592 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4594 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4596 struct drm_device
*dev
= crtc
->base
.dev
;
4597 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4599 /* We want to get the other_active_crtc only if there's only 1 other
4601 for_each_intel_crtc(dev
, crtc_it
) {
4602 if (!crtc_it
->active
|| crtc_it
== crtc
)
4605 if (other_active_crtc
)
4608 other_active_crtc
= crtc_it
;
4610 if (!other_active_crtc
)
4613 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4614 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4617 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4619 struct drm_device
*dev
= crtc
->dev
;
4620 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4621 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4622 struct intel_encoder
*encoder
;
4623 int pipe
= intel_crtc
->pipe
;
4625 WARN_ON(!crtc
->state
->enable
);
4627 if (intel_crtc
->active
)
4630 if (intel_crtc_to_shared_dpll(intel_crtc
))
4631 intel_enable_shared_dpll(intel_crtc
);
4633 if (intel_crtc
->config
->has_dp_encoder
)
4634 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4636 intel_set_pipe_timings(intel_crtc
);
4638 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4639 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4640 intel_crtc
->config
->pixel_multiplier
- 1);
4643 if (intel_crtc
->config
->has_pch_encoder
) {
4644 intel_cpu_transcoder_set_m_n(intel_crtc
,
4645 &intel_crtc
->config
->fdi_m_n
, NULL
);
4648 haswell_set_pipeconf(crtc
);
4650 intel_set_pipe_csc(crtc
);
4652 intel_crtc
->active
= true;
4654 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4655 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4656 if (encoder
->pre_enable
)
4657 encoder
->pre_enable(encoder
);
4659 if (intel_crtc
->config
->has_pch_encoder
) {
4660 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4662 dev_priv
->display
.fdi_link_train(crtc
);
4665 intel_ddi_enable_pipe_clock(intel_crtc
);
4667 if (IS_SKYLAKE(dev
))
4668 skylake_pfit_enable(intel_crtc
);
4670 ironlake_pfit_enable(intel_crtc
);
4673 * On ILK+ LUT must be loaded before the pipe is running but with
4676 intel_crtc_load_lut(crtc
);
4678 intel_ddi_set_pipe_settings(crtc
);
4679 intel_ddi_enable_transcoder_func(crtc
);
4681 intel_update_watermarks(crtc
);
4682 intel_enable_pipe(intel_crtc
);
4684 if (intel_crtc
->config
->has_pch_encoder
)
4685 lpt_pch_enable(crtc
);
4687 if (intel_crtc
->config
->dp_encoder_is_mst
)
4688 intel_ddi_set_vc_payload_alloc(crtc
, true);
4690 assert_vblank_disabled(crtc
);
4691 drm_crtc_vblank_on(crtc
);
4693 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4694 encoder
->enable(encoder
);
4695 intel_opregion_notify_encoder(encoder
, true);
4698 /* If we change the relative order between pipe/planes enabling, we need
4699 * to change the workaround. */
4700 haswell_mode_set_planes_workaround(intel_crtc
);
4701 intel_crtc_enable_planes(crtc
);
4704 static void skylake_pfit_disable(struct intel_crtc
*crtc
)
4706 struct drm_device
*dev
= crtc
->base
.dev
;
4707 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4708 int pipe
= crtc
->pipe
;
4710 /* To avoid upsetting the power well on haswell only disable the pfit if
4711 * it's in use. The hw state code will make sure we get this right. */
4712 if (crtc
->config
->pch_pfit
.enabled
) {
4713 I915_WRITE(PS_CTL(pipe
), 0);
4714 I915_WRITE(PS_WIN_POS(pipe
), 0);
4715 I915_WRITE(PS_WIN_SZ(pipe
), 0);
4719 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4721 struct drm_device
*dev
= crtc
->base
.dev
;
4722 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4723 int pipe
= crtc
->pipe
;
4725 /* To avoid upsetting the power well on haswell only disable the pfit if
4726 * it's in use. The hw state code will make sure we get this right. */
4727 if (crtc
->config
->pch_pfit
.enabled
) {
4728 I915_WRITE(PF_CTL(pipe
), 0);
4729 I915_WRITE(PF_WIN_POS(pipe
), 0);
4730 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4734 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4736 struct drm_device
*dev
= crtc
->dev
;
4737 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4738 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4739 struct intel_encoder
*encoder
;
4740 int pipe
= intel_crtc
->pipe
;
4743 if (!intel_crtc
->active
)
4746 intel_crtc_disable_planes(crtc
);
4748 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4749 encoder
->disable(encoder
);
4751 drm_crtc_vblank_off(crtc
);
4752 assert_vblank_disabled(crtc
);
4754 if (intel_crtc
->config
->has_pch_encoder
)
4755 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
4757 intel_disable_pipe(intel_crtc
);
4759 ironlake_pfit_disable(intel_crtc
);
4761 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4762 if (encoder
->post_disable
)
4763 encoder
->post_disable(encoder
);
4765 if (intel_crtc
->config
->has_pch_encoder
) {
4766 ironlake_fdi_disable(crtc
);
4768 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4770 if (HAS_PCH_CPT(dev
)) {
4771 /* disable TRANS_DP_CTL */
4772 reg
= TRANS_DP_CTL(pipe
);
4773 temp
= I915_READ(reg
);
4774 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4775 TRANS_DP_PORT_SEL_MASK
);
4776 temp
|= TRANS_DP_PORT_SEL_NONE
;
4777 I915_WRITE(reg
, temp
);
4779 /* disable DPLL_SEL */
4780 temp
= I915_READ(PCH_DPLL_SEL
);
4781 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4782 I915_WRITE(PCH_DPLL_SEL
, temp
);
4785 /* disable PCH DPLL */
4786 intel_disable_shared_dpll(intel_crtc
);
4788 ironlake_fdi_pll_disable(intel_crtc
);
4791 intel_crtc
->active
= false;
4792 intel_update_watermarks(crtc
);
4794 mutex_lock(&dev
->struct_mutex
);
4795 intel_fbc_update(dev
);
4796 mutex_unlock(&dev
->struct_mutex
);
4799 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4801 struct drm_device
*dev
= crtc
->dev
;
4802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4803 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4804 struct intel_encoder
*encoder
;
4805 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4807 if (!intel_crtc
->active
)
4810 intel_crtc_disable_planes(crtc
);
4812 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4813 intel_opregion_notify_encoder(encoder
, false);
4814 encoder
->disable(encoder
);
4817 drm_crtc_vblank_off(crtc
);
4818 assert_vblank_disabled(crtc
);
4820 if (intel_crtc
->config
->has_pch_encoder
)
4821 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
4823 intel_disable_pipe(intel_crtc
);
4825 if (intel_crtc
->config
->dp_encoder_is_mst
)
4826 intel_ddi_set_vc_payload_alloc(crtc
, false);
4828 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4830 if (IS_SKYLAKE(dev
))
4831 skylake_pfit_disable(intel_crtc
);
4833 ironlake_pfit_disable(intel_crtc
);
4835 intel_ddi_disable_pipe_clock(intel_crtc
);
4837 if (intel_crtc
->config
->has_pch_encoder
) {
4838 lpt_disable_pch_transcoder(dev_priv
);
4839 intel_ddi_fdi_disable(crtc
);
4842 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4843 if (encoder
->post_disable
)
4844 encoder
->post_disable(encoder
);
4846 intel_crtc
->active
= false;
4847 intel_update_watermarks(crtc
);
4849 mutex_lock(&dev
->struct_mutex
);
4850 intel_fbc_update(dev
);
4851 mutex_unlock(&dev
->struct_mutex
);
4853 if (intel_crtc_to_shared_dpll(intel_crtc
))
4854 intel_disable_shared_dpll(intel_crtc
);
4857 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4860 intel_put_shared_dpll(intel_crtc
);
4864 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4866 struct drm_device
*dev
= crtc
->base
.dev
;
4867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4868 struct intel_crtc_state
*pipe_config
= crtc
->config
;
4870 if (!pipe_config
->gmch_pfit
.control
)
4874 * The panel fitter should only be adjusted whilst the pipe is disabled,
4875 * according to register description and PRM.
4877 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4878 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4880 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4881 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4883 /* Border color in case we don't scale up to the full screen. Black by
4884 * default, change to something else for debugging. */
4885 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4888 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4892 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4894 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4896 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4898 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4901 return POWER_DOMAIN_PORT_OTHER
;
4905 #define for_each_power_domain(domain, mask) \
4906 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4907 if ((1 << (domain)) & (mask))
4909 enum intel_display_power_domain
4910 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4912 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4913 struct intel_digital_port
*intel_dig_port
;
4915 switch (intel_encoder
->type
) {
4916 case INTEL_OUTPUT_UNKNOWN
:
4917 /* Only DDI platforms should ever use this output type */
4918 WARN_ON_ONCE(!HAS_DDI(dev
));
4919 case INTEL_OUTPUT_DISPLAYPORT
:
4920 case INTEL_OUTPUT_HDMI
:
4921 case INTEL_OUTPUT_EDP
:
4922 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4923 return port_to_power_domain(intel_dig_port
->port
);
4924 case INTEL_OUTPUT_DP_MST
:
4925 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4926 return port_to_power_domain(intel_dig_port
->port
);
4927 case INTEL_OUTPUT_ANALOG
:
4928 return POWER_DOMAIN_PORT_CRT
;
4929 case INTEL_OUTPUT_DSI
:
4930 return POWER_DOMAIN_PORT_DSI
;
4932 return POWER_DOMAIN_PORT_OTHER
;
4936 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4938 struct drm_device
*dev
= crtc
->dev
;
4939 struct intel_encoder
*intel_encoder
;
4940 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4941 enum pipe pipe
= intel_crtc
->pipe
;
4943 enum transcoder transcoder
;
4945 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4947 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4948 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4949 if (intel_crtc
->config
->pch_pfit
.enabled
||
4950 intel_crtc
->config
->pch_pfit
.force_thru
)
4951 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4953 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4954 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4959 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
4961 struct drm_device
*dev
= state
->dev
;
4962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4963 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4964 struct intel_crtc
*crtc
;
4967 * First get all needed power domains, then put all unneeded, to avoid
4968 * any unnecessary toggling of the power wells.
4970 for_each_intel_crtc(dev
, crtc
) {
4971 enum intel_display_power_domain domain
;
4973 if (!crtc
->base
.state
->enable
)
4976 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4978 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4979 intel_display_power_get(dev_priv
, domain
);
4982 if (dev_priv
->display
.modeset_global_resources
)
4983 dev_priv
->display
.modeset_global_resources(state
);
4985 for_each_intel_crtc(dev
, crtc
) {
4986 enum intel_display_power_domain domain
;
4988 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4989 intel_display_power_put(dev_priv
, domain
);
4991 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4994 intel_display_set_init_power(dev_priv
, false);
4997 /* returns HPLL frequency in kHz */
4998 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
5000 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
5002 /* Obtain SKU information */
5003 mutex_lock(&dev_priv
->dpio_lock
);
5004 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
5005 CCK_FUSE_HPLL_FREQ_MASK
;
5006 mutex_unlock(&dev_priv
->dpio_lock
);
5008 return vco_freq
[hpll_freq
] * 1000;
5011 static void vlv_update_cdclk(struct drm_device
*dev
)
5013 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5015 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5016 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5017 dev_priv
->vlv_cdclk_freq
);
5020 * Program the gmbus_freq based on the cdclk frequency.
5021 * BSpec erroneously claims we should aim for 4MHz, but
5022 * in fact 1MHz is the correct frequency.
5024 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->vlv_cdclk_freq
, 1000));
5027 /* Adjust CDclk dividers to allow high res or save power if possible */
5028 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5033 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
5035 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5037 else if (cdclk
== 266667)
5042 mutex_lock(&dev_priv
->rps
.hw_lock
);
5043 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5044 val
&= ~DSPFREQGUAR_MASK
;
5045 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5046 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5047 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5048 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5050 DRM_ERROR("timed out waiting for CDclk change\n");
5052 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5054 if (cdclk
== 400000) {
5057 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5059 mutex_lock(&dev_priv
->dpio_lock
);
5060 /* adjust cdclk divider */
5061 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5062 val
&= ~DISPLAY_FREQUENCY_VALUES
;
5064 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5066 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5067 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5069 DRM_ERROR("timed out waiting for CDclk change\n");
5070 mutex_unlock(&dev_priv
->dpio_lock
);
5073 mutex_lock(&dev_priv
->dpio_lock
);
5074 /* adjust self-refresh exit latency value */
5075 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5079 * For high bandwidth configs, we set a higher latency in the bunit
5080 * so that the core display fetch happens in time to avoid underruns.
5082 if (cdclk
== 400000)
5083 val
|= 4500 / 250; /* 4.5 usec */
5085 val
|= 3000 / 250; /* 3.0 usec */
5086 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5087 mutex_unlock(&dev_priv
->dpio_lock
);
5089 vlv_update_cdclk(dev
);
5092 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5094 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5097 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
5106 MISSING_CASE(cdclk
);
5111 * Specs are full of misinformation, but testing on actual
5112 * hardware has shown that we just need to write the desired
5113 * CCK divider into the Punit register.
5115 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5117 mutex_lock(&dev_priv
->rps
.hw_lock
);
5118 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5119 val
&= ~DSPFREQGUAR_MASK_CHV
;
5120 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5121 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5122 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5123 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5125 DRM_ERROR("timed out waiting for CDclk change\n");
5127 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5129 vlv_update_cdclk(dev
);
5132 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5135 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5136 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5139 * Really only a few cases to deal with, as only 4 CDclks are supported:
5142 * 320/333MHz (depends on HPLL freq)
5144 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5145 * of the lower bin and adjust if needed.
5147 * We seem to get an unstable or solid color picture at 200MHz.
5148 * Not sure what's wrong. For now use 200MHz only when all pipes
5151 if (!IS_CHERRYVIEW(dev_priv
) &&
5152 max_pixclk
> freq_320
*limit
/100)
5154 else if (max_pixclk
> 266667*limit
/100)
5156 else if (max_pixclk
> 0)
5162 /* compute the max pixel clock for new configuration */
5163 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
5165 struct drm_device
*dev
= dev_priv
->dev
;
5166 struct intel_crtc
*intel_crtc
;
5169 for_each_intel_crtc(dev
, intel_crtc
) {
5170 if (intel_crtc
->new_enabled
)
5171 max_pixclk
= max(max_pixclk
,
5172 intel_crtc
->new_config
->base
.adjusted_mode
.crtc_clock
);
5178 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
5179 unsigned *prepare_pipes
)
5181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5182 struct intel_crtc
*intel_crtc
;
5183 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
5185 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
5186 dev_priv
->vlv_cdclk_freq
)
5189 /* disable/enable all currently active pipes while we change cdclk */
5190 for_each_intel_crtc(dev
, intel_crtc
)
5191 if (intel_crtc
->base
.state
->enable
)
5192 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
5195 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
5197 unsigned int credits
, default_credits
;
5199 if (IS_CHERRYVIEW(dev_priv
))
5200 default_credits
= PFI_CREDIT(12);
5202 default_credits
= PFI_CREDIT(8);
5204 if (DIV_ROUND_CLOSEST(dev_priv
->vlv_cdclk_freq
, 1000) >= dev_priv
->rps
.cz_freq
) {
5205 /* CHV suggested value is 31 or 63 */
5206 if (IS_CHERRYVIEW(dev_priv
))
5207 credits
= PFI_CREDIT_31
;
5209 credits
= PFI_CREDIT(15);
5211 credits
= default_credits
;
5215 * WA - write default credits before re-programming
5216 * FIXME: should we also set the resend bit here?
5218 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5221 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
5222 credits
| PFI_CREDIT_RESEND
);
5225 * FIXME is this guaranteed to clear
5226 * immediately or should we poll for it?
5228 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
5231 static void valleyview_modeset_global_resources(struct drm_atomic_state
*state
)
5233 struct drm_device
*dev
= state
->dev
;
5234 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5235 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
5236 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
5238 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
5240 * FIXME: We can end up here with all power domains off, yet
5241 * with a CDCLK frequency other than the minimum. To account
5242 * for this take the PIPE-A power domain, which covers the HW
5243 * blocks needed for the following programming. This can be
5244 * removed once it's guaranteed that we get here either with
5245 * the minimum CDCLK set, or the required power domains
5248 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
5250 if (IS_CHERRYVIEW(dev
))
5251 cherryview_set_cdclk(dev
, req_cdclk
);
5253 valleyview_set_cdclk(dev
, req_cdclk
);
5255 vlv_program_pfi_credits(dev_priv
);
5257 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
5261 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
5263 struct drm_device
*dev
= crtc
->dev
;
5264 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5265 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5266 struct intel_encoder
*encoder
;
5267 int pipe
= intel_crtc
->pipe
;
5270 WARN_ON(!crtc
->state
->enable
);
5272 if (intel_crtc
->active
)
5275 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5278 if (IS_CHERRYVIEW(dev
))
5279 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5281 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
5284 if (intel_crtc
->config
->has_dp_encoder
)
5285 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5287 intel_set_pipe_timings(intel_crtc
);
5289 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
5290 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5292 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
5293 I915_WRITE(CHV_CANVAS(pipe
), 0);
5296 i9xx_set_pipeconf(intel_crtc
);
5298 intel_crtc
->active
= true;
5300 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5302 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5303 if (encoder
->pre_pll_enable
)
5304 encoder
->pre_pll_enable(encoder
);
5307 if (IS_CHERRYVIEW(dev
))
5308 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
5310 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
5313 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5314 if (encoder
->pre_enable
)
5315 encoder
->pre_enable(encoder
);
5317 i9xx_pfit_enable(intel_crtc
);
5319 intel_crtc_load_lut(crtc
);
5321 intel_update_watermarks(crtc
);
5322 intel_enable_pipe(intel_crtc
);
5324 assert_vblank_disabled(crtc
);
5325 drm_crtc_vblank_on(crtc
);
5327 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5328 encoder
->enable(encoder
);
5330 intel_crtc_enable_planes(crtc
);
5332 /* Underruns don't raise interrupts, so check manually. */
5333 i9xx_check_fifo_underruns(dev_priv
);
5336 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
5338 struct drm_device
*dev
= crtc
->base
.dev
;
5339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5341 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
5342 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
5345 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
5347 struct drm_device
*dev
= crtc
->dev
;
5348 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5349 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5350 struct intel_encoder
*encoder
;
5351 int pipe
= intel_crtc
->pipe
;
5353 WARN_ON(!crtc
->state
->enable
);
5355 if (intel_crtc
->active
)
5358 i9xx_set_pll_dividers(intel_crtc
);
5360 if (intel_crtc
->config
->has_dp_encoder
)
5361 intel_dp_set_m_n(intel_crtc
, M1_N1
);
5363 intel_set_pipe_timings(intel_crtc
);
5365 i9xx_set_pipeconf(intel_crtc
);
5367 intel_crtc
->active
= true;
5370 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5372 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5373 if (encoder
->pre_enable
)
5374 encoder
->pre_enable(encoder
);
5376 i9xx_enable_pll(intel_crtc
);
5378 i9xx_pfit_enable(intel_crtc
);
5380 intel_crtc_load_lut(crtc
);
5382 intel_update_watermarks(crtc
);
5383 intel_enable_pipe(intel_crtc
);
5385 assert_vblank_disabled(crtc
);
5386 drm_crtc_vblank_on(crtc
);
5388 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5389 encoder
->enable(encoder
);
5391 intel_crtc_enable_planes(crtc
);
5394 * Gen2 reports pipe underruns whenever all planes are disabled.
5395 * So don't enable underrun reporting before at least some planes
5397 * FIXME: Need to fix the logic to work when we turn off all planes
5398 * but leave the pipe running.
5401 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
5403 /* Underruns don't raise interrupts, so check manually. */
5404 i9xx_check_fifo_underruns(dev_priv
);
5407 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
5409 struct drm_device
*dev
= crtc
->base
.dev
;
5410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5412 if (!crtc
->config
->gmch_pfit
.control
)
5415 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5417 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5418 I915_READ(PFIT_CONTROL
));
5419 I915_WRITE(PFIT_CONTROL
, 0);
5422 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
5424 struct drm_device
*dev
= crtc
->dev
;
5425 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5426 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5427 struct intel_encoder
*encoder
;
5428 int pipe
= intel_crtc
->pipe
;
5430 if (!intel_crtc
->active
)
5434 * Gen2 reports pipe underruns whenever all planes are disabled.
5435 * So diasble underrun reporting before all the planes get disabled.
5436 * FIXME: Need to fix the logic to work when we turn off all planes
5437 * but leave the pipe running.
5440 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5443 * Vblank time updates from the shadow to live plane control register
5444 * are blocked if the memory self-refresh mode is active at that
5445 * moment. So to make sure the plane gets truly disabled, disable
5446 * first the self-refresh mode. The self-refresh enable bit in turn
5447 * will be checked/applied by the HW only at the next frame start
5448 * event which is after the vblank start event, so we need to have a
5449 * wait-for-vblank between disabling the plane and the pipe.
5451 intel_set_memory_cxsr(dev_priv
, false);
5452 intel_crtc_disable_planes(crtc
);
5455 * On gen2 planes are double buffered but the pipe isn't, so we must
5456 * wait for planes to fully turn off before disabling the pipe.
5457 * We also need to wait on all gmch platforms because of the
5458 * self-refresh mode constraint explained above.
5460 intel_wait_for_vblank(dev
, pipe
);
5462 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5463 encoder
->disable(encoder
);
5465 drm_crtc_vblank_off(crtc
);
5466 assert_vblank_disabled(crtc
);
5468 intel_disable_pipe(intel_crtc
);
5470 i9xx_pfit_disable(intel_crtc
);
5472 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5473 if (encoder
->post_disable
)
5474 encoder
->post_disable(encoder
);
5476 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
5477 if (IS_CHERRYVIEW(dev
))
5478 chv_disable_pll(dev_priv
, pipe
);
5479 else if (IS_VALLEYVIEW(dev
))
5480 vlv_disable_pll(dev_priv
, pipe
);
5482 i9xx_disable_pll(intel_crtc
);
5486 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
5488 intel_crtc
->active
= false;
5489 intel_update_watermarks(crtc
);
5491 mutex_lock(&dev
->struct_mutex
);
5492 intel_fbc_update(dev
);
5493 mutex_unlock(&dev
->struct_mutex
);
5496 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
5500 /* Master function to enable/disable CRTC and corresponding power wells */
5501 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
5503 struct drm_device
*dev
= crtc
->dev
;
5504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5505 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5506 enum intel_display_power_domain domain
;
5507 unsigned long domains
;
5510 if (!intel_crtc
->active
) {
5511 domains
= get_crtc_power_domains(crtc
);
5512 for_each_power_domain(domain
, domains
)
5513 intel_display_power_get(dev_priv
, domain
);
5514 intel_crtc
->enabled_power_domains
= domains
;
5516 dev_priv
->display
.crtc_enable(crtc
);
5519 if (intel_crtc
->active
) {
5520 dev_priv
->display
.crtc_disable(crtc
);
5522 domains
= intel_crtc
->enabled_power_domains
;
5523 for_each_power_domain(domain
, domains
)
5524 intel_display_power_put(dev_priv
, domain
);
5525 intel_crtc
->enabled_power_domains
= 0;
5531 * Sets the power management mode of the pipe and plane.
5533 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
5535 struct drm_device
*dev
= crtc
->dev
;
5536 struct intel_encoder
*intel_encoder
;
5537 bool enable
= false;
5539 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5540 enable
|= intel_encoder
->connectors_active
;
5542 intel_crtc_control(crtc
, enable
);
5545 static void intel_crtc_disable(struct drm_crtc
*crtc
)
5547 struct drm_device
*dev
= crtc
->dev
;
5548 struct drm_connector
*connector
;
5549 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5551 /* crtc should still be enabled when we disable it. */
5552 WARN_ON(!crtc
->state
->enable
);
5554 dev_priv
->display
.crtc_disable(crtc
);
5555 dev_priv
->display
.off(crtc
);
5557 crtc
->primary
->funcs
->disable_plane(crtc
->primary
);
5559 /* Update computed state. */
5560 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5561 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5564 if (connector
->encoder
->crtc
!= crtc
)
5567 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5568 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5572 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5574 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5576 drm_encoder_cleanup(encoder
);
5577 kfree(intel_encoder
);
5580 /* Simple dpms helper for encoders with just one connector, no cloning and only
5581 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5582 * state of the entire output pipe. */
5583 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5585 if (mode
== DRM_MODE_DPMS_ON
) {
5586 encoder
->connectors_active
= true;
5588 intel_crtc_update_dpms(encoder
->base
.crtc
);
5590 encoder
->connectors_active
= false;
5592 intel_crtc_update_dpms(encoder
->base
.crtc
);
5596 /* Cross check the actual hw state with our own modeset state tracking (and it's
5597 * internal consistency). */
5598 static void intel_connector_check_state(struct intel_connector
*connector
)
5600 if (connector
->get_hw_state(connector
)) {
5601 struct intel_encoder
*encoder
= connector
->encoder
;
5602 struct drm_crtc
*crtc
;
5603 bool encoder_enabled
;
5606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5607 connector
->base
.base
.id
,
5608 connector
->base
.name
);
5610 /* there is no real hw state for MST connectors */
5611 if (connector
->mst_port
)
5614 I915_STATE_WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5615 "wrong connector dpms state\n");
5616 I915_STATE_WARN(connector
->base
.encoder
!= &encoder
->base
,
5617 "active connector not linked to encoder\n");
5620 I915_STATE_WARN(!encoder
->connectors_active
,
5621 "encoder->connectors_active not set\n");
5623 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5624 I915_STATE_WARN(!encoder_enabled
, "encoder not enabled\n");
5625 if (I915_STATE_WARN_ON(!encoder
->base
.crtc
))
5628 crtc
= encoder
->base
.crtc
;
5630 I915_STATE_WARN(!crtc
->state
->enable
,
5631 "crtc not enabled\n");
5632 I915_STATE_WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5633 I915_STATE_WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5634 "encoder active on the wrong pipe\n");
5639 /* Even simpler default implementation, if there's really no special case to
5641 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5643 /* All the simple cases only support two dpms states. */
5644 if (mode
!= DRM_MODE_DPMS_ON
)
5645 mode
= DRM_MODE_DPMS_OFF
;
5647 if (mode
== connector
->dpms
)
5650 connector
->dpms
= mode
;
5652 /* Only need to change hw state when actually enabled */
5653 if (connector
->encoder
)
5654 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5656 intel_modeset_check_state(connector
->dev
);
5659 /* Simple connector->get_hw_state implementation for encoders that support only
5660 * one connector and no cloning and hence the encoder state determines the state
5661 * of the connector. */
5662 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5665 struct intel_encoder
*encoder
= connector
->encoder
;
5667 return encoder
->get_hw_state(encoder
, &pipe
);
5670 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
5672 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
5673 return crtc_state
->fdi_lanes
;
5678 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5679 struct intel_crtc_state
*pipe_config
)
5681 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
5682 struct intel_crtc
*other_crtc
;
5683 struct intel_crtc_state
*other_crtc_state
;
5685 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5686 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5687 if (pipe_config
->fdi_lanes
> 4) {
5688 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5689 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5693 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5694 if (pipe_config
->fdi_lanes
> 2) {
5695 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5696 pipe_config
->fdi_lanes
);
5703 if (INTEL_INFO(dev
)->num_pipes
== 2)
5706 /* Ivybridge 3 pipe is really complicated */
5711 if (pipe_config
->fdi_lanes
<= 2)
5714 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
5716 intel_atomic_get_crtc_state(state
, other_crtc
);
5717 if (IS_ERR(other_crtc_state
))
5718 return PTR_ERR(other_crtc_state
);
5720 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
5721 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5722 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5727 if (pipe_config
->fdi_lanes
> 2) {
5728 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5729 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5733 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
5735 intel_atomic_get_crtc_state(state
, other_crtc
);
5736 if (IS_ERR(other_crtc_state
))
5737 return PTR_ERR(other_crtc_state
);
5739 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
5740 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5750 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5751 struct intel_crtc_state
*pipe_config
)
5753 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5754 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5755 int lane
, link_bw
, fdi_dotclock
, ret
;
5756 bool needs_recompute
= false;
5759 /* FDI is a binary signal running at ~2.7GHz, encoding
5760 * each output octet as 10 bits. The actual frequency
5761 * is stored as a divider into a 100MHz clock, and the
5762 * mode pixel clock is stored in units of 1KHz.
5763 * Hence the bw of each lane in terms of the mode signal
5766 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5768 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5770 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5771 pipe_config
->pipe_bpp
);
5773 pipe_config
->fdi_lanes
= lane
;
5775 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5776 link_bw
, &pipe_config
->fdi_m_n
);
5778 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5779 intel_crtc
->pipe
, pipe_config
);
5780 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
5781 pipe_config
->pipe_bpp
-= 2*3;
5782 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5783 pipe_config
->pipe_bpp
);
5784 needs_recompute
= true;
5785 pipe_config
->bw_constrained
= true;
5790 if (needs_recompute
)
5796 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5797 struct intel_crtc_state
*pipe_config
)
5799 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5800 hsw_crtc_supports_ips(crtc
) &&
5801 pipe_config
->pipe_bpp
<= 24;
5804 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5805 struct intel_crtc_state
*pipe_config
)
5807 struct drm_device
*dev
= crtc
->base
.dev
;
5808 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5809 struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
5811 /* FIXME should check pixel clock limits on all platforms */
5812 if (INTEL_INFO(dev
)->gen
< 4) {
5814 dev_priv
->display
.get_display_clock_speed(dev
);
5817 * Enable pixel doubling when the dot clock
5818 * is > 90% of the (display) core speed.
5820 * GDG double wide on either pipe,
5821 * otherwise pipe A only.
5823 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5824 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5826 pipe_config
->double_wide
= true;
5829 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5834 * Pipe horizontal size must be even in:
5836 * - LVDS dual channel mode
5837 * - Double wide pipe
5839 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
5840 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5841 pipe_config
->pipe_src_w
&= ~1;
5843 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5844 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5846 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5847 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5850 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5851 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5852 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5853 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5855 pipe_config
->pipe_bpp
= 8*3;
5859 hsw_compute_ips_config(crtc
, pipe_config
);
5861 if (pipe_config
->has_pch_encoder
)
5862 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5867 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
5869 struct drm_i915_private
*dev_priv
= to_i915(dev
);
5870 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
5871 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
5874 if (!(lcpll1
& LCPLL_PLL_ENABLE
)) {
5875 WARN(1, "LCPLL1 not enabled\n");
5876 return 24000; /* 24MHz is the cd freq with NSSC ref */
5879 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
5882 linkrate
= (I915_READ(DPLL_CTRL1
) &
5883 DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
5885 if (linkrate
== DPLL_CRTL1_LINK_RATE_2160
||
5886 linkrate
== DPLL_CRTL1_LINK_RATE_1080
) {
5888 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
5889 case CDCLK_FREQ_450_432
:
5891 case CDCLK_FREQ_337_308
:
5893 case CDCLK_FREQ_675_617
:
5896 WARN(1, "Unknown cd freq selection\n");
5900 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
5901 case CDCLK_FREQ_450_432
:
5903 case CDCLK_FREQ_337_308
:
5905 case CDCLK_FREQ_675_617
:
5908 WARN(1, "Unknown cd freq selection\n");
5912 /* error case, do as if DPLL0 isn't enabled */
5916 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
5918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5919 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
5920 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
5922 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
5924 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5926 else if (freq
== LCPLL_CLK_FREQ_450
)
5928 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
5930 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
5936 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
5938 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5939 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
5940 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
5942 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
5944 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5946 else if (freq
== LCPLL_CLK_FREQ_450
)
5948 else if (IS_HSW_ULT(dev
))
5954 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5960 if (dev_priv
->hpll_freq
== 0)
5961 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
5963 mutex_lock(&dev_priv
->dpio_lock
);
5964 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5965 mutex_unlock(&dev_priv
->dpio_lock
);
5967 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5969 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5970 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5971 "cdclk change in progress\n");
5973 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
5976 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
5981 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5986 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5991 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5996 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6000 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6002 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6003 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6005 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6007 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6009 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6012 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6013 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6015 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6020 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6024 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6026 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6029 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6030 case GC_DISPLAY_CLOCK_333_MHZ
:
6033 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6039 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6044 static int i855_get_display_clock_speed(struct drm_device
*dev
)
6047 /* Assume that the hardware is in the high speed state. This
6048 * should be the default.
6050 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6051 case GC_CLOCK_133_200
:
6052 case GC_CLOCK_100_200
:
6054 case GC_CLOCK_166_250
:
6056 case GC_CLOCK_100_133
:
6060 /* Shouldn't happen */
6064 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6070 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
6072 while (*num
> DATA_LINK_M_N_MASK
||
6073 *den
> DATA_LINK_M_N_MASK
) {
6079 static void compute_m_n(unsigned int m
, unsigned int n
,
6080 uint32_t *ret_m
, uint32_t *ret_n
)
6082 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
6083 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
6084 intel_reduce_m_n_ratio(ret_m
, ret_n
);
6088 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
6089 int pixel_clock
, int link_clock
,
6090 struct intel_link_m_n
*m_n
)
6094 compute_m_n(bits_per_pixel
* pixel_clock
,
6095 link_clock
* nlanes
* 8,
6096 &m_n
->gmch_m
, &m_n
->gmch_n
);
6098 compute_m_n(pixel_clock
, link_clock
,
6099 &m_n
->link_m
, &m_n
->link_n
);
6102 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
6104 if (i915
.panel_use_ssc
>= 0)
6105 return i915
.panel_use_ssc
!= 0;
6106 return dev_priv
->vbt
.lvds_use_ssc
6107 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
6110 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
6113 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
6114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6117 WARN_ON(!crtc_state
->base
.state
);
6119 if (IS_VALLEYVIEW(dev
)) {
6121 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6122 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6123 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
6124 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
6125 } else if (!IS_GEN2(dev
)) {
6134 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
6136 return (1 << dpll
->n
) << 16 | dpll
->m2
;
6139 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
6141 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
6144 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
6145 struct intel_crtc_state
*crtc_state
,
6146 intel_clock_t
*reduced_clock
)
6148 struct drm_device
*dev
= crtc
->base
.dev
;
6151 if (IS_PINEVIEW(dev
)) {
6152 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
6154 fp2
= pnv_dpll_compute_fp(reduced_clock
);
6156 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
6158 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
6161 crtc_state
->dpll_hw_state
.fp0
= fp
;
6163 crtc
->lowfreq_avail
= false;
6164 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6166 crtc_state
->dpll_hw_state
.fp1
= fp2
;
6167 crtc
->lowfreq_avail
= true;
6169 crtc_state
->dpll_hw_state
.fp1
= fp
;
6173 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
6179 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6180 * and set it to a reasonable value instead.
6182 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6183 reg_val
&= 0xffffff00;
6184 reg_val
|= 0x00000030;
6185 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6187 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6188 reg_val
&= 0x8cffffff;
6189 reg_val
= 0x8c000000;
6190 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6192 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
6193 reg_val
&= 0xffffff00;
6194 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
6196 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
6197 reg_val
&= 0x00ffffff;
6198 reg_val
|= 0xb0000000;
6199 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
6202 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
6203 struct intel_link_m_n
*m_n
)
6205 struct drm_device
*dev
= crtc
->base
.dev
;
6206 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6207 int pipe
= crtc
->pipe
;
6209 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6210 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
6211 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
6212 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
6215 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
6216 struct intel_link_m_n
*m_n
,
6217 struct intel_link_m_n
*m2_n2
)
6219 struct drm_device
*dev
= crtc
->base
.dev
;
6220 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6221 int pipe
= crtc
->pipe
;
6222 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
6224 if (INTEL_INFO(dev
)->gen
>= 5) {
6225 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6226 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
6227 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
6228 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
6229 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6230 * for gen < 8) and if DRRS is supported (to make sure the
6231 * registers are not unnecessarily accessed).
6233 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
6234 crtc
->config
->has_drrs
) {
6235 I915_WRITE(PIPE_DATA_M2(transcoder
),
6236 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
6237 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
6238 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
6239 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
6242 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
6243 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
6244 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
6245 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
6249 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
6251 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
6254 dp_m_n
= &crtc
->config
->dp_m_n
;
6255 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
6256 } else if (m_n
== M2_N2
) {
6259 * M2_N2 registers are not supported. Hence m2_n2 divider value
6260 * needs to be programmed into M1_N1.
6262 dp_m_n
= &crtc
->config
->dp_m2_n2
;
6264 DRM_ERROR("Unsupported divider value\n");
6268 if (crtc
->config
->has_pch_encoder
)
6269 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
6271 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
6274 static void vlv_update_pll(struct intel_crtc
*crtc
,
6275 struct intel_crtc_state
*pipe_config
)
6280 * Enable DPIO clock input. We should never disable the reference
6281 * clock for pipe B, since VGA hotplug / manual detection depends
6284 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
6285 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
6286 /* We should never disable this, set it here for state tracking */
6287 if (crtc
->pipe
== PIPE_B
)
6288 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6289 dpll
|= DPLL_VCO_ENABLE
;
6290 pipe_config
->dpll_hw_state
.dpll
= dpll
;
6292 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
6293 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6294 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
6297 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
6298 const struct intel_crtc_state
*pipe_config
)
6300 struct drm_device
*dev
= crtc
->base
.dev
;
6301 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6302 int pipe
= crtc
->pipe
;
6304 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
6305 u32 coreclk
, reg_val
;
6307 mutex_lock(&dev_priv
->dpio_lock
);
6309 bestn
= pipe_config
->dpll
.n
;
6310 bestm1
= pipe_config
->dpll
.m1
;
6311 bestm2
= pipe_config
->dpll
.m2
;
6312 bestp1
= pipe_config
->dpll
.p1
;
6313 bestp2
= pipe_config
->dpll
.p2
;
6315 /* See eDP HDMI DPIO driver vbios notes doc */
6317 /* PLL B needs special handling */
6319 vlv_pllb_recal_opamp(dev_priv
, pipe
);
6321 /* Set up Tx target for periodic Rcomp update */
6322 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
6324 /* Disable target IRef on PLL */
6325 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
6326 reg_val
&= 0x00ffffff;
6327 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
6329 /* Disable fast lock */
6330 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
6332 /* Set idtafcrecal before PLL is enabled */
6333 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
6334 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
6335 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
6336 mdiv
|= (1 << DPIO_K_SHIFT
);
6339 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6340 * but we don't support that).
6341 * Note: don't use the DAC post divider as it seems unstable.
6343 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
6344 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6346 mdiv
|= DPIO_ENABLE_CALIBRATION
;
6347 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
6349 /* Set HBR and RBR LPF coefficients */
6350 if (pipe_config
->port_clock
== 162000 ||
6351 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
6352 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
6353 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6356 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
6359 if (pipe_config
->has_dp_encoder
) {
6360 /* Use SSC source */
6362 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6365 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6367 } else { /* HDMI or VGA */
6368 /* Use bend source */
6370 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6373 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
6377 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
6378 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
6379 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
6380 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
6381 coreclk
|= 0x01000000;
6382 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
6384 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
6385 mutex_unlock(&dev_priv
->dpio_lock
);
6388 static void chv_update_pll(struct intel_crtc
*crtc
,
6389 struct intel_crtc_state
*pipe_config
)
6391 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
6392 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
6394 if (crtc
->pipe
!= PIPE_A
)
6395 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
6397 pipe_config
->dpll_hw_state
.dpll_md
=
6398 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6401 static void chv_prepare_pll(struct intel_crtc
*crtc
,
6402 const struct intel_crtc_state
*pipe_config
)
6404 struct drm_device
*dev
= crtc
->base
.dev
;
6405 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6406 int pipe
= crtc
->pipe
;
6407 int dpll_reg
= DPLL(crtc
->pipe
);
6408 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6409 u32 loopfilter
, tribuf_calcntr
;
6410 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
6414 bestn
= pipe_config
->dpll
.n
;
6415 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
6416 bestm1
= pipe_config
->dpll
.m1
;
6417 bestm2
= pipe_config
->dpll
.m2
>> 22;
6418 bestp1
= pipe_config
->dpll
.p1
;
6419 bestp2
= pipe_config
->dpll
.p2
;
6420 vco
= pipe_config
->dpll
.vco
;
6425 * Enable Refclk and SSC
6427 I915_WRITE(dpll_reg
,
6428 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
6430 mutex_lock(&dev_priv
->dpio_lock
);
6432 /* p1 and p2 divider */
6433 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
6434 5 << DPIO_CHV_S1_DIV_SHIFT
|
6435 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
6436 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
6437 1 << DPIO_CHV_K_DIV_SHIFT
);
6439 /* Feedback post-divider - m2 */
6440 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
6442 /* Feedback refclk divider - n and m1 */
6443 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
6444 DPIO_CHV_M1_DIV_BY_2
|
6445 1 << DPIO_CHV_N_DIV_SHIFT
);
6447 /* M2 fraction division */
6449 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
6451 /* M2 fraction division enable */
6452 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
6453 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
6454 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
6456 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
6457 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
6459 /* Program digital lock detect threshold */
6460 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
6461 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
6462 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
6463 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
6465 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
6466 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
6469 if (vco
== 5400000) {
6470 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
6471 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
6472 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6473 tribuf_calcntr
= 0x9;
6474 } else if (vco
<= 6200000) {
6475 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
6476 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
6477 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6478 tribuf_calcntr
= 0x9;
6479 } else if (vco
<= 6480000) {
6480 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
6481 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
6482 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6483 tribuf_calcntr
= 0x8;
6485 /* Not supported. Apply the same limits as in the max case */
6486 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
6487 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
6488 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
6491 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
6493 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
6494 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
6495 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
6496 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
6499 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
6500 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
6503 mutex_unlock(&dev_priv
->dpio_lock
);
6507 * vlv_force_pll_on - forcibly enable just the PLL
6508 * @dev_priv: i915 private structure
6509 * @pipe: pipe PLL to enable
6510 * @dpll: PLL configuration
6512 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6513 * in cases where we need the PLL enabled even when @pipe is not going to
6516 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
6517 const struct dpll
*dpll
)
6519 struct intel_crtc
*crtc
=
6520 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
6521 struct intel_crtc_state pipe_config
= {
6522 .base
.crtc
= &crtc
->base
,
6523 .pixel_multiplier
= 1,
6527 if (IS_CHERRYVIEW(dev
)) {
6528 chv_update_pll(crtc
, &pipe_config
);
6529 chv_prepare_pll(crtc
, &pipe_config
);
6530 chv_enable_pll(crtc
, &pipe_config
);
6532 vlv_update_pll(crtc
, &pipe_config
);
6533 vlv_prepare_pll(crtc
, &pipe_config
);
6534 vlv_enable_pll(crtc
, &pipe_config
);
6539 * vlv_force_pll_off - forcibly disable just the PLL
6540 * @dev_priv: i915 private structure
6541 * @pipe: pipe PLL to disable
6543 * Disable the PLL for @pipe. To be used in cases where we need
6544 * the PLL enabled even when @pipe is not going to be enabled.
6546 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
6548 if (IS_CHERRYVIEW(dev
))
6549 chv_disable_pll(to_i915(dev
), pipe
);
6551 vlv_disable_pll(to_i915(dev
), pipe
);
6554 static void i9xx_update_pll(struct intel_crtc
*crtc
,
6555 struct intel_crtc_state
*crtc_state
,
6556 intel_clock_t
*reduced_clock
,
6559 struct drm_device
*dev
= crtc
->base
.dev
;
6560 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6563 struct dpll
*clock
= &crtc_state
->dpll
;
6565 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6567 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
6568 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
6570 dpll
= DPLL_VGA_MODE_DIS
;
6572 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
6573 dpll
|= DPLLB_MODE_LVDS
;
6575 dpll
|= DPLLB_MODE_DAC_SERIAL
;
6577 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6578 dpll
|= (crtc_state
->pixel_multiplier
- 1)
6579 << SDVO_MULTIPLIER_SHIFT_HIRES
;
6583 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6585 if (crtc_state
->has_dp_encoder
)
6586 dpll
|= DPLL_SDVO_HIGH_SPEED
;
6588 /* compute bitmask from p1 value */
6589 if (IS_PINEVIEW(dev
))
6590 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
6592 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6593 if (IS_G4X(dev
) && reduced_clock
)
6594 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
6596 switch (clock
->p2
) {
6598 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
6601 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
6604 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
6607 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
6610 if (INTEL_INFO(dev
)->gen
>= 4)
6611 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
6613 if (crtc_state
->sdvo_tv_clock
)
6614 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
6615 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6616 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6617 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6619 dpll
|= PLL_REF_INPUT_DREFCLK
;
6621 dpll
|= DPLL_VCO_ENABLE
;
6622 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6624 if (INTEL_INFO(dev
)->gen
>= 4) {
6625 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
6626 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
6627 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
6631 static void i8xx_update_pll(struct intel_crtc
*crtc
,
6632 struct intel_crtc_state
*crtc_state
,
6633 intel_clock_t
*reduced_clock
,
6636 struct drm_device
*dev
= crtc
->base
.dev
;
6637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6639 struct dpll
*clock
= &crtc_state
->dpll
;
6641 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
6643 dpll
= DPLL_VGA_MODE_DIS
;
6645 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
6646 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6649 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
6651 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
6653 dpll
|= PLL_P2_DIVIDE_BY_4
;
6656 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
6657 dpll
|= DPLL_DVO_2X_MODE
;
6659 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
6660 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
6661 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
6663 dpll
|= PLL_REF_INPUT_DREFCLK
;
6665 dpll
|= DPLL_VCO_ENABLE
;
6666 crtc_state
->dpll_hw_state
.dpll
= dpll
;
6669 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
6671 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6672 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6673 enum pipe pipe
= intel_crtc
->pipe
;
6674 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
6675 struct drm_display_mode
*adjusted_mode
=
6676 &intel_crtc
->config
->base
.adjusted_mode
;
6677 uint32_t crtc_vtotal
, crtc_vblank_end
;
6680 /* We need to be careful not to changed the adjusted mode, for otherwise
6681 * the hw state checker will get angry at the mismatch. */
6682 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
6683 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
6685 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
6686 /* the chip adds 2 halflines automatically */
6688 crtc_vblank_end
-= 1;
6690 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6691 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
6693 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
6694 adjusted_mode
->crtc_htotal
/ 2;
6696 vsyncshift
+= adjusted_mode
->crtc_htotal
;
6699 if (INTEL_INFO(dev
)->gen
> 3)
6700 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
6702 I915_WRITE(HTOTAL(cpu_transcoder
),
6703 (adjusted_mode
->crtc_hdisplay
- 1) |
6704 ((adjusted_mode
->crtc_htotal
- 1) << 16));
6705 I915_WRITE(HBLANK(cpu_transcoder
),
6706 (adjusted_mode
->crtc_hblank_start
- 1) |
6707 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
6708 I915_WRITE(HSYNC(cpu_transcoder
),
6709 (adjusted_mode
->crtc_hsync_start
- 1) |
6710 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
6712 I915_WRITE(VTOTAL(cpu_transcoder
),
6713 (adjusted_mode
->crtc_vdisplay
- 1) |
6714 ((crtc_vtotal
- 1) << 16));
6715 I915_WRITE(VBLANK(cpu_transcoder
),
6716 (adjusted_mode
->crtc_vblank_start
- 1) |
6717 ((crtc_vblank_end
- 1) << 16));
6718 I915_WRITE(VSYNC(cpu_transcoder
),
6719 (adjusted_mode
->crtc_vsync_start
- 1) |
6720 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
6722 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6723 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6724 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6726 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
6727 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
6728 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
6730 /* pipesrc controls the size that is scaled from, which should
6731 * always be the user's requested size.
6733 I915_WRITE(PIPESRC(pipe
),
6734 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
6735 (intel_crtc
->config
->pipe_src_h
- 1));
6738 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
6739 struct intel_crtc_state
*pipe_config
)
6741 struct drm_device
*dev
= crtc
->base
.dev
;
6742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6743 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
6746 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
6747 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
6748 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
6749 tmp
= I915_READ(HBLANK(cpu_transcoder
));
6750 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
6751 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6752 tmp
= I915_READ(HSYNC(cpu_transcoder
));
6753 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
6754 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6756 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
6757 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
6758 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
6759 tmp
= I915_READ(VBLANK(cpu_transcoder
));
6760 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
6761 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
6762 tmp
= I915_READ(VSYNC(cpu_transcoder
));
6763 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
6764 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
6766 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
6767 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
6768 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
6769 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
6772 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6773 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6774 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6776 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
6777 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
6780 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6781 struct intel_crtc_state
*pipe_config
)
6783 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
6784 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
6785 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
6786 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
6788 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
6789 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
6790 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
6791 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
6793 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
6795 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
6796 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
6799 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6801 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6807 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
6808 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
6809 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
6811 if (intel_crtc
->config
->double_wide
)
6812 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6814 /* only g4x and later have fancy bpc/dither controls */
6815 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6816 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6817 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
6818 pipeconf
|= PIPECONF_DITHER_EN
|
6819 PIPECONF_DITHER_TYPE_SP
;
6821 switch (intel_crtc
->config
->pipe_bpp
) {
6823 pipeconf
|= PIPECONF_6BPC
;
6826 pipeconf
|= PIPECONF_8BPC
;
6829 pipeconf
|= PIPECONF_10BPC
;
6832 /* Case prevented by intel_choose_pipe_bpp_dither. */
6837 if (HAS_PIPE_CXSR(dev
)) {
6838 if (intel_crtc
->lowfreq_avail
) {
6839 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6840 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6842 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6846 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6847 if (INTEL_INFO(dev
)->gen
< 4 ||
6848 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
6849 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6851 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6853 pipeconf
|= PIPECONF_PROGRESSIVE
;
6855 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
6856 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6858 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6859 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6862 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
6863 struct intel_crtc_state
*crtc_state
)
6865 struct drm_device
*dev
= crtc
->base
.dev
;
6866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6867 int refclk
, num_connectors
= 0;
6868 intel_clock_t clock
, reduced_clock
;
6869 bool ok
, has_reduced_clock
= false;
6870 bool is_lvds
= false, is_dsi
= false;
6871 struct intel_encoder
*encoder
;
6872 const intel_limit_t
*limit
;
6873 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
6874 struct drm_connector_state
*connector_state
;
6877 for (i
= 0; i
< state
->num_connector
; i
++) {
6878 if (!state
->connectors
[i
])
6881 connector_state
= state
->connector_states
[i
];
6882 if (connector_state
->crtc
!= &crtc
->base
)
6885 encoder
= to_intel_encoder(connector_state
->best_encoder
);
6887 switch (encoder
->type
) {
6888 case INTEL_OUTPUT_LVDS
:
6891 case INTEL_OUTPUT_DSI
:
6904 if (!crtc_state
->clock_set
) {
6905 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
6908 * Returns a set of divisors for the desired target clock with
6909 * the given refclk, or FALSE. The returned values represent
6910 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6913 limit
= intel_limit(crtc_state
, refclk
);
6914 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
6915 crtc_state
->port_clock
,
6916 refclk
, NULL
, &clock
);
6918 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6922 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6924 * Ensure we match the reduced clock's P to the target
6925 * clock. If the clocks don't match, we can't switch
6926 * the display clock by using the FP0/FP1. In such case
6927 * we will disable the LVDS downclock feature.
6930 dev_priv
->display
.find_dpll(limit
, crtc_state
,
6931 dev_priv
->lvds_downclock
,
6935 /* Compat-code for transition, will disappear. */
6936 crtc_state
->dpll
.n
= clock
.n
;
6937 crtc_state
->dpll
.m1
= clock
.m1
;
6938 crtc_state
->dpll
.m2
= clock
.m2
;
6939 crtc_state
->dpll
.p1
= clock
.p1
;
6940 crtc_state
->dpll
.p2
= clock
.p2
;
6944 i8xx_update_pll(crtc
, crtc_state
,
6945 has_reduced_clock
? &reduced_clock
: NULL
,
6947 } else if (IS_CHERRYVIEW(dev
)) {
6948 chv_update_pll(crtc
, crtc_state
);
6949 } else if (IS_VALLEYVIEW(dev
)) {
6950 vlv_update_pll(crtc
, crtc_state
);
6952 i9xx_update_pll(crtc
, crtc_state
,
6953 has_reduced_clock
? &reduced_clock
: NULL
,
6960 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6961 struct intel_crtc_state
*pipe_config
)
6963 struct drm_device
*dev
= crtc
->base
.dev
;
6964 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6967 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6970 tmp
= I915_READ(PFIT_CONTROL
);
6971 if (!(tmp
& PFIT_ENABLE
))
6974 /* Check whether the pfit is attached to our pipe. */
6975 if (INTEL_INFO(dev
)->gen
< 4) {
6976 if (crtc
->pipe
!= PIPE_B
)
6979 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6983 pipe_config
->gmch_pfit
.control
= tmp
;
6984 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6985 if (INTEL_INFO(dev
)->gen
< 5)
6986 pipe_config
->gmch_pfit
.lvds_border_bits
=
6987 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6990 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6991 struct intel_crtc_state
*pipe_config
)
6993 struct drm_device
*dev
= crtc
->base
.dev
;
6994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6995 int pipe
= pipe_config
->cpu_transcoder
;
6996 intel_clock_t clock
;
6998 int refclk
= 100000;
7000 /* In case of MIPI DPLL will not even be used */
7001 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
7004 mutex_lock(&dev_priv
->dpio_lock
);
7005 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
7006 mutex_unlock(&dev_priv
->dpio_lock
);
7008 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
7009 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
7010 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
7011 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
7012 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
7014 vlv_clock(refclk
, &clock
);
7016 /* clock.dot is the fast clock */
7017 pipe_config
->port_clock
= clock
.dot
/ 5;
7021 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
7022 struct intel_initial_plane_config
*plane_config
)
7024 struct drm_device
*dev
= crtc
->base
.dev
;
7025 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7026 u32 val
, base
, offset
;
7027 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7028 int fourcc
, pixel_format
;
7029 unsigned int aligned_height
;
7030 struct drm_framebuffer
*fb
;
7031 struct intel_framebuffer
*intel_fb
;
7033 val
= I915_READ(DSPCNTR(plane
));
7034 if (!(val
& DISPLAY_PLANE_ENABLE
))
7037 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
7039 DRM_DEBUG_KMS("failed to alloc fb\n");
7043 fb
= &intel_fb
->base
;
7045 if (INTEL_INFO(dev
)->gen
>= 4) {
7046 if (val
& DISPPLANE_TILED
) {
7047 plane_config
->tiling
= I915_TILING_X
;
7048 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
7052 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7053 fourcc
= i9xx_format_to_fourcc(pixel_format
);
7054 fb
->pixel_format
= fourcc
;
7055 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
7057 if (INTEL_INFO(dev
)->gen
>= 4) {
7058 if (plane_config
->tiling
)
7059 offset
= I915_READ(DSPTILEOFF(plane
));
7061 offset
= I915_READ(DSPLINOFF(plane
));
7062 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7064 base
= I915_READ(DSPADDR(plane
));
7066 plane_config
->base
= base
;
7068 val
= I915_READ(PIPESRC(pipe
));
7069 fb
->width
= ((val
>> 16) & 0xfff) + 1;
7070 fb
->height
= ((val
>> 0) & 0xfff) + 1;
7072 val
= I915_READ(DSPSTRIDE(pipe
));
7073 fb
->pitches
[0] = val
& 0xffffffc0;
7075 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
7079 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
7081 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7082 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
7083 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
7084 plane_config
->size
);
7086 plane_config
->fb
= intel_fb
;
7089 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
7090 struct intel_crtc_state
*pipe_config
)
7092 struct drm_device
*dev
= crtc
->base
.dev
;
7093 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7094 int pipe
= pipe_config
->cpu_transcoder
;
7095 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7096 intel_clock_t clock
;
7097 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
7098 int refclk
= 100000;
7100 mutex_lock(&dev_priv
->dpio_lock
);
7101 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
7102 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
7103 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
7104 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
7105 mutex_unlock(&dev_priv
->dpio_lock
);
7107 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
7108 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
7109 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
7110 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
7111 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
7113 chv_clock(refclk
, &clock
);
7115 /* clock.dot is the fast clock */
7116 pipe_config
->port_clock
= clock
.dot
/ 5;
7119 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
7120 struct intel_crtc_state
*pipe_config
)
7122 struct drm_device
*dev
= crtc
->base
.dev
;
7123 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7126 if (!intel_display_power_is_enabled(dev_priv
,
7127 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7130 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7131 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7133 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7134 if (!(tmp
& PIPECONF_ENABLE
))
7137 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7138 switch (tmp
& PIPECONF_BPC_MASK
) {
7140 pipe_config
->pipe_bpp
= 18;
7143 pipe_config
->pipe_bpp
= 24;
7145 case PIPECONF_10BPC
:
7146 pipe_config
->pipe_bpp
= 30;
7153 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
7154 pipe_config
->limited_color_range
= true;
7156 if (INTEL_INFO(dev
)->gen
< 4)
7157 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
7159 intel_get_pipe_timings(crtc
, pipe_config
);
7161 i9xx_get_pfit_config(crtc
, pipe_config
);
7163 if (INTEL_INFO(dev
)->gen
>= 4) {
7164 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
7165 pipe_config
->pixel_multiplier
=
7166 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
7167 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
7168 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
7169 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7170 tmp
= I915_READ(DPLL(crtc
->pipe
));
7171 pipe_config
->pixel_multiplier
=
7172 ((tmp
& SDVO_MULTIPLIER_MASK
)
7173 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
7175 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7176 * port and will be fixed up in the encoder->get_config
7178 pipe_config
->pixel_multiplier
= 1;
7180 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
7181 if (!IS_VALLEYVIEW(dev
)) {
7183 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7184 * on 830. Filter it out here so that we don't
7185 * report errors due to that.
7188 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
7190 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
7191 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
7193 /* Mask out read-only status bits. */
7194 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
7195 DPLL_PORTC_READY_MASK
|
7196 DPLL_PORTB_READY_MASK
);
7199 if (IS_CHERRYVIEW(dev
))
7200 chv_crtc_clock_get(crtc
, pipe_config
);
7201 else if (IS_VALLEYVIEW(dev
))
7202 vlv_crtc_clock_get(crtc
, pipe_config
);
7204 i9xx_crtc_clock_get(crtc
, pipe_config
);
7209 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
7211 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7212 struct intel_encoder
*encoder
;
7214 bool has_lvds
= false;
7215 bool has_cpu_edp
= false;
7216 bool has_panel
= false;
7217 bool has_ck505
= false;
7218 bool can_ssc
= false;
7220 /* We need to take the global config into account */
7221 for_each_intel_encoder(dev
, encoder
) {
7222 switch (encoder
->type
) {
7223 case INTEL_OUTPUT_LVDS
:
7227 case INTEL_OUTPUT_EDP
:
7229 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
7237 if (HAS_PCH_IBX(dev
)) {
7238 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
7239 can_ssc
= has_ck505
;
7245 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7246 has_panel
, has_lvds
, has_ck505
);
7248 /* Ironlake: try to setup display ref clock before DPLL
7249 * enabling. This is only under driver's control after
7250 * PCH B stepping, previous chipset stepping should be
7251 * ignoring this setting.
7253 val
= I915_READ(PCH_DREF_CONTROL
);
7255 /* As we must carefully and slowly disable/enable each source in turn,
7256 * compute the final state we want first and check if we need to
7257 * make any changes at all.
7260 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7262 final
|= DREF_NONSPREAD_CK505_ENABLE
;
7264 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7266 final
&= ~DREF_SSC_SOURCE_MASK
;
7267 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7268 final
&= ~DREF_SSC1_ENABLE
;
7271 final
|= DREF_SSC_SOURCE_ENABLE
;
7273 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7274 final
|= DREF_SSC1_ENABLE
;
7277 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
7278 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7280 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7282 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7284 final
|= DREF_SSC_SOURCE_DISABLE
;
7285 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7291 /* Always enable nonspread source */
7292 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
7295 val
|= DREF_NONSPREAD_CK505_ENABLE
;
7297 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
7300 val
&= ~DREF_SSC_SOURCE_MASK
;
7301 val
|= DREF_SSC_SOURCE_ENABLE
;
7303 /* SSC must be turned on before enabling the CPU output */
7304 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7305 DRM_DEBUG_KMS("Using SSC on panel\n");
7306 val
|= DREF_SSC1_ENABLE
;
7308 val
&= ~DREF_SSC1_ENABLE
;
7310 /* Get SSC going before enabling the outputs */
7311 I915_WRITE(PCH_DREF_CONTROL
, val
);
7312 POSTING_READ(PCH_DREF_CONTROL
);
7315 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7317 /* Enable CPU source on CPU attached eDP */
7319 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
7320 DRM_DEBUG_KMS("Using SSC on eDP\n");
7321 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
7323 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
7325 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7327 I915_WRITE(PCH_DREF_CONTROL
, val
);
7328 POSTING_READ(PCH_DREF_CONTROL
);
7331 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7333 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
7335 /* Turn off CPU output */
7336 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
7338 I915_WRITE(PCH_DREF_CONTROL
, val
);
7339 POSTING_READ(PCH_DREF_CONTROL
);
7342 /* Turn off the SSC source */
7343 val
&= ~DREF_SSC_SOURCE_MASK
;
7344 val
|= DREF_SSC_SOURCE_DISABLE
;
7347 val
&= ~DREF_SSC1_ENABLE
;
7349 I915_WRITE(PCH_DREF_CONTROL
, val
);
7350 POSTING_READ(PCH_DREF_CONTROL
);
7354 BUG_ON(val
!= final
);
7357 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
7361 tmp
= I915_READ(SOUTH_CHICKEN2
);
7362 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
7363 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7365 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
7366 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
7367 DRM_ERROR("FDI mPHY reset assert timeout\n");
7369 tmp
= I915_READ(SOUTH_CHICKEN2
);
7370 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
7371 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
7373 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
7374 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
7375 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7378 /* WaMPhyProgramming:hsw */
7379 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
7383 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
7384 tmp
&= ~(0xFF << 24);
7385 tmp
|= (0x12 << 24);
7386 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
7388 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
7390 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
7392 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
7394 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
7396 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
7397 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7398 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
7400 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
7401 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
7402 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
7404 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
7407 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
7409 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
7412 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
7414 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
7417 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
7419 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
7422 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
7424 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
7425 tmp
&= ~(0xFF << 16);
7426 tmp
|= (0x1C << 16);
7427 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
7429 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
7430 tmp
&= ~(0xFF << 16);
7431 tmp
|= (0x1C << 16);
7432 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
7434 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
7436 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
7438 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
7440 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
7442 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
7443 tmp
&= ~(0xF << 28);
7445 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
7447 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
7448 tmp
&= ~(0xF << 28);
7450 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
7453 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7454 * Programming" based on the parameters passed:
7455 * - Sequence to enable CLKOUT_DP
7456 * - Sequence to enable CLKOUT_DP without spread
7457 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7459 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
7462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7465 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
7467 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
7468 with_fdi
, "LP PCH doesn't have FDI\n"))
7471 mutex_lock(&dev_priv
->dpio_lock
);
7473 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7474 tmp
&= ~SBI_SSCCTL_DISABLE
;
7475 tmp
|= SBI_SSCCTL_PATHALT
;
7476 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7481 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7482 tmp
&= ~SBI_SSCCTL_PATHALT
;
7483 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7486 lpt_reset_fdi_mphy(dev_priv
);
7487 lpt_program_fdi_mphy(dev_priv
);
7491 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7492 SBI_GEN0
: SBI_DBUFF0
;
7493 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7494 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7495 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7497 mutex_unlock(&dev_priv
->dpio_lock
);
7500 /* Sequence to disable CLKOUT_DP */
7501 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
7503 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7506 mutex_lock(&dev_priv
->dpio_lock
);
7508 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
7509 SBI_GEN0
: SBI_DBUFF0
;
7510 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
7511 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
7512 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
7514 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
7515 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
7516 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
7517 tmp
|= SBI_SSCCTL_PATHALT
;
7518 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7521 tmp
|= SBI_SSCCTL_DISABLE
;
7522 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
7525 mutex_unlock(&dev_priv
->dpio_lock
);
7528 static void lpt_init_pch_refclk(struct drm_device
*dev
)
7530 struct intel_encoder
*encoder
;
7531 bool has_vga
= false;
7533 for_each_intel_encoder(dev
, encoder
) {
7534 switch (encoder
->type
) {
7535 case INTEL_OUTPUT_ANALOG
:
7544 lpt_enable_clkout_dp(dev
, true, true);
7546 lpt_disable_clkout_dp(dev
);
7550 * Initialize reference clocks when the driver loads
7552 void intel_init_pch_refclk(struct drm_device
*dev
)
7554 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
7555 ironlake_init_pch_refclk(dev
);
7556 else if (HAS_PCH_LPT(dev
))
7557 lpt_init_pch_refclk(dev
);
7560 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
7562 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
7563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7564 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7565 struct drm_connector_state
*connector_state
;
7566 struct intel_encoder
*encoder
;
7567 int num_connectors
= 0, i
;
7568 bool is_lvds
= false;
7570 for (i
= 0; i
< state
->num_connector
; i
++) {
7571 if (!state
->connectors
[i
])
7574 connector_state
= state
->connector_states
[i
];
7575 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
7578 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7580 switch (encoder
->type
) {
7581 case INTEL_OUTPUT_LVDS
:
7590 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7591 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7592 dev_priv
->vbt
.lvds_ssc_freq
);
7593 return dev_priv
->vbt
.lvds_ssc_freq
;
7599 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
7601 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
7602 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7603 int pipe
= intel_crtc
->pipe
;
7608 switch (intel_crtc
->config
->pipe_bpp
) {
7610 val
|= PIPECONF_6BPC
;
7613 val
|= PIPECONF_8BPC
;
7616 val
|= PIPECONF_10BPC
;
7619 val
|= PIPECONF_12BPC
;
7622 /* Case prevented by intel_choose_pipe_bpp_dither. */
7626 if (intel_crtc
->config
->dither
)
7627 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7629 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7630 val
|= PIPECONF_INTERLACED_ILK
;
7632 val
|= PIPECONF_PROGRESSIVE
;
7634 if (intel_crtc
->config
->limited_color_range
)
7635 val
|= PIPECONF_COLOR_RANGE_SELECT
;
7637 I915_WRITE(PIPECONF(pipe
), val
);
7638 POSTING_READ(PIPECONF(pipe
));
7642 * Set up the pipe CSC unit.
7644 * Currently only full range RGB to limited range RGB conversion
7645 * is supported, but eventually this should handle various
7646 * RGB<->YCbCr scenarios as well.
7648 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
7650 struct drm_device
*dev
= crtc
->dev
;
7651 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7653 int pipe
= intel_crtc
->pipe
;
7654 uint16_t coeff
= 0x7800; /* 1.0 */
7657 * TODO: Check what kind of values actually come out of the pipe
7658 * with these coeff/postoff values and adjust to get the best
7659 * accuracy. Perhaps we even need to take the bpc value into
7663 if (intel_crtc
->config
->limited_color_range
)
7664 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7667 * GY/GU and RY/RU should be the other way around according
7668 * to BSpec, but reality doesn't agree. Just set them up in
7669 * a way that results in the correct picture.
7671 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
7672 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
7674 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
7675 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
7677 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
7678 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
7680 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
7681 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
7682 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
7684 if (INTEL_INFO(dev
)->gen
> 6) {
7685 uint16_t postoff
= 0;
7687 if (intel_crtc
->config
->limited_color_range
)
7688 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
7690 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
7691 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
7692 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
7694 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
7696 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
7698 if (intel_crtc
->config
->limited_color_range
)
7699 mode
|= CSC_BLACK_SCREEN_OFFSET
;
7701 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
7705 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
7707 struct drm_device
*dev
= crtc
->dev
;
7708 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7709 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7710 enum pipe pipe
= intel_crtc
->pipe
;
7711 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7716 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
7717 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
7719 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
7720 val
|= PIPECONF_INTERLACED_ILK
;
7722 val
|= PIPECONF_PROGRESSIVE
;
7724 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
7725 POSTING_READ(PIPECONF(cpu_transcoder
));
7727 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
7728 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
7730 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
7733 switch (intel_crtc
->config
->pipe_bpp
) {
7735 val
|= PIPEMISC_DITHER_6_BPC
;
7738 val
|= PIPEMISC_DITHER_8_BPC
;
7741 val
|= PIPEMISC_DITHER_10_BPC
;
7744 val
|= PIPEMISC_DITHER_12_BPC
;
7747 /* Case prevented by pipe_config_set_bpp. */
7751 if (intel_crtc
->config
->dither
)
7752 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
7754 I915_WRITE(PIPEMISC(pipe
), val
);
7758 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
7759 struct intel_crtc_state
*crtc_state
,
7760 intel_clock_t
*clock
,
7761 bool *has_reduced_clock
,
7762 intel_clock_t
*reduced_clock
)
7764 struct drm_device
*dev
= crtc
->dev
;
7765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7767 const intel_limit_t
*limit
;
7768 bool ret
, is_lvds
= false;
7770 is_lvds
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
);
7772 refclk
= ironlake_get_refclk(crtc_state
);
7775 * Returns a set of divisors for the desired target clock with the given
7776 * refclk, or FALSE. The returned values represent the clock equation:
7777 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7779 limit
= intel_limit(crtc_state
, refclk
);
7780 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7781 crtc_state
->port_clock
,
7782 refclk
, NULL
, clock
);
7786 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
7788 * Ensure we match the reduced clock's P to the target clock.
7789 * If the clocks don't match, we can't switch the display clock
7790 * by using the FP0/FP1. In such case we will disable the LVDS
7791 * downclock feature.
7793 *has_reduced_clock
=
7794 dev_priv
->display
.find_dpll(limit
, crtc_state
,
7795 dev_priv
->lvds_downclock
,
7803 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
7806 * Account for spread spectrum to avoid
7807 * oversubscribing the link. Max center spread
7808 * is 2.5%; use 5% for safety's sake.
7810 u32 bps
= target_clock
* bpp
* 21 / 20;
7811 return DIV_ROUND_UP(bps
, link_bw
* 8);
7814 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7816 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7819 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7820 struct intel_crtc_state
*crtc_state
,
7822 intel_clock_t
*reduced_clock
, u32
*fp2
)
7824 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7825 struct drm_device
*dev
= crtc
->dev
;
7826 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7827 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7828 struct drm_connector_state
*connector_state
;
7829 struct intel_encoder
*encoder
;
7831 int factor
, num_connectors
= 0, i
;
7832 bool is_lvds
= false, is_sdvo
= false;
7834 for (i
= 0; i
< state
->num_connector
; i
++) {
7835 if (!state
->connectors
[i
])
7838 connector_state
= state
->connector_states
[i
];
7839 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
7842 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7844 switch (encoder
->type
) {
7845 case INTEL_OUTPUT_LVDS
:
7848 case INTEL_OUTPUT_SDVO
:
7849 case INTEL_OUTPUT_HDMI
:
7859 /* Enable autotuning of the PLL clock (if permissible) */
7862 if ((intel_panel_use_ssc(dev_priv
) &&
7863 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7864 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7866 } else if (crtc_state
->sdvo_tv_clock
)
7869 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
7872 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7878 dpll
|= DPLLB_MODE_LVDS
;
7880 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7882 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7883 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7886 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7887 if (crtc_state
->has_dp_encoder
)
7888 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7890 /* compute bitmask from p1 value */
7891 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7893 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7895 switch (crtc_state
->dpll
.p2
) {
7897 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7900 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7903 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7906 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7910 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7911 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7913 dpll
|= PLL_REF_INPUT_DREFCLK
;
7915 return dpll
| DPLL_VCO_ENABLE
;
7918 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
7919 struct intel_crtc_state
*crtc_state
)
7921 struct drm_device
*dev
= crtc
->base
.dev
;
7922 intel_clock_t clock
, reduced_clock
;
7923 u32 dpll
= 0, fp
= 0, fp2
= 0;
7924 bool ok
, has_reduced_clock
= false;
7925 bool is_lvds
= false;
7926 struct intel_shared_dpll
*pll
;
7928 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
7930 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7931 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7933 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
7934 &has_reduced_clock
, &reduced_clock
);
7935 if (!ok
&& !crtc_state
->clock_set
) {
7936 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7939 /* Compat-code for transition, will disappear. */
7940 if (!crtc_state
->clock_set
) {
7941 crtc_state
->dpll
.n
= clock
.n
;
7942 crtc_state
->dpll
.m1
= clock
.m1
;
7943 crtc_state
->dpll
.m2
= clock
.m2
;
7944 crtc_state
->dpll
.p1
= clock
.p1
;
7945 crtc_state
->dpll
.p2
= clock
.p2
;
7948 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7949 if (crtc_state
->has_pch_encoder
) {
7950 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7951 if (has_reduced_clock
)
7952 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7954 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
7955 &fp
, &reduced_clock
,
7956 has_reduced_clock
? &fp2
: NULL
);
7958 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7959 crtc_state
->dpll_hw_state
.fp0
= fp
;
7960 if (has_reduced_clock
)
7961 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7963 crtc_state
->dpll_hw_state
.fp1
= fp
;
7965 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
7967 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7968 pipe_name(crtc
->pipe
));
7973 if (is_lvds
&& has_reduced_clock
)
7974 crtc
->lowfreq_avail
= true;
7976 crtc
->lowfreq_avail
= false;
7981 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7982 struct intel_link_m_n
*m_n
)
7984 struct drm_device
*dev
= crtc
->base
.dev
;
7985 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7986 enum pipe pipe
= crtc
->pipe
;
7988 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7989 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7990 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7992 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7993 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7994 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7997 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7998 enum transcoder transcoder
,
7999 struct intel_link_m_n
*m_n
,
8000 struct intel_link_m_n
*m2_n2
)
8002 struct drm_device
*dev
= crtc
->base
.dev
;
8003 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8004 enum pipe pipe
= crtc
->pipe
;
8006 if (INTEL_INFO(dev
)->gen
>= 5) {
8007 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8008 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8009 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8011 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8012 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8013 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8014 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8015 * gen < 8) and if DRRS is supported (to make sure the
8016 * registers are not unnecessarily read).
8018 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
8019 crtc
->config
->has_drrs
) {
8020 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
8021 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
8022 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
8024 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
8025 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
8026 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8029 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
8030 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
8031 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
8033 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
8034 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
8035 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8039 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
8040 struct intel_crtc_state
*pipe_config
)
8042 if (pipe_config
->has_pch_encoder
)
8043 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
8045 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8046 &pipe_config
->dp_m_n
,
8047 &pipe_config
->dp_m2_n2
);
8050 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
8051 struct intel_crtc_state
*pipe_config
)
8053 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
8054 &pipe_config
->fdi_m_n
, NULL
);
8057 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
8058 struct intel_crtc_state
*pipe_config
)
8060 struct drm_device
*dev
= crtc
->base
.dev
;
8061 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8064 tmp
= I915_READ(PS_CTL(crtc
->pipe
));
8066 if (tmp
& PS_ENABLE
) {
8067 pipe_config
->pch_pfit
.enabled
= true;
8068 pipe_config
->pch_pfit
.pos
= I915_READ(PS_WIN_POS(crtc
->pipe
));
8069 pipe_config
->pch_pfit
.size
= I915_READ(PS_WIN_SZ(crtc
->pipe
));
8074 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
8075 struct intel_initial_plane_config
*plane_config
)
8077 struct drm_device
*dev
= crtc
->base
.dev
;
8078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8079 u32 val
, base
, offset
, stride_mult
, tiling
;
8080 int pipe
= crtc
->pipe
;
8081 int fourcc
, pixel_format
;
8082 unsigned int aligned_height
;
8083 struct drm_framebuffer
*fb
;
8084 struct intel_framebuffer
*intel_fb
;
8086 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8088 DRM_DEBUG_KMS("failed to alloc fb\n");
8092 fb
= &intel_fb
->base
;
8094 val
= I915_READ(PLANE_CTL(pipe
, 0));
8095 if (!(val
& PLANE_CTL_ENABLE
))
8098 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
8099 fourcc
= skl_format_to_fourcc(pixel_format
,
8100 val
& PLANE_CTL_ORDER_RGBX
,
8101 val
& PLANE_CTL_ALPHA_MASK
);
8102 fb
->pixel_format
= fourcc
;
8103 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8105 tiling
= val
& PLANE_CTL_TILED_MASK
;
8107 case PLANE_CTL_TILED_LINEAR
:
8108 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
8110 case PLANE_CTL_TILED_X
:
8111 plane_config
->tiling
= I915_TILING_X
;
8112 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8114 case PLANE_CTL_TILED_Y
:
8115 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
8117 case PLANE_CTL_TILED_YF
:
8118 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
8121 MISSING_CASE(tiling
);
8125 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
8126 plane_config
->base
= base
;
8128 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
8130 val
= I915_READ(PLANE_SIZE(pipe
, 0));
8131 fb
->height
= ((val
>> 16) & 0xfff) + 1;
8132 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
8134 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
8135 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
8137 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
8139 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8143 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8145 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8146 pipe_name(pipe
), fb
->width
, fb
->height
,
8147 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8148 plane_config
->size
);
8150 plane_config
->fb
= intel_fb
;
8157 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
8158 struct intel_crtc_state
*pipe_config
)
8160 struct drm_device
*dev
= crtc
->base
.dev
;
8161 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8164 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
8166 if (tmp
& PF_ENABLE
) {
8167 pipe_config
->pch_pfit
.enabled
= true;
8168 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
8169 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
8171 /* We currently do not free assignements of panel fitters on
8172 * ivb/hsw (since we don't use the higher upscaling modes which
8173 * differentiates them) so just WARN about this case for now. */
8175 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
8176 PF_PIPE_SEL_IVB(crtc
->pipe
));
8182 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
8183 struct intel_initial_plane_config
*plane_config
)
8185 struct drm_device
*dev
= crtc
->base
.dev
;
8186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8187 u32 val
, base
, offset
;
8188 int pipe
= crtc
->pipe
;
8189 int fourcc
, pixel_format
;
8190 unsigned int aligned_height
;
8191 struct drm_framebuffer
*fb
;
8192 struct intel_framebuffer
*intel_fb
;
8194 val
= I915_READ(DSPCNTR(pipe
));
8195 if (!(val
& DISPLAY_PLANE_ENABLE
))
8198 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8200 DRM_DEBUG_KMS("failed to alloc fb\n");
8204 fb
= &intel_fb
->base
;
8206 if (INTEL_INFO(dev
)->gen
>= 4) {
8207 if (val
& DISPPLANE_TILED
) {
8208 plane_config
->tiling
= I915_TILING_X
;
8209 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8213 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8214 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8215 fb
->pixel_format
= fourcc
;
8216 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8218 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
8219 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
8220 offset
= I915_READ(DSPOFFSET(pipe
));
8222 if (plane_config
->tiling
)
8223 offset
= I915_READ(DSPTILEOFF(pipe
));
8225 offset
= I915_READ(DSPLINOFF(pipe
));
8227 plane_config
->base
= base
;
8229 val
= I915_READ(PIPESRC(pipe
));
8230 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8231 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8233 val
= I915_READ(DSPSTRIDE(pipe
));
8234 fb
->pitches
[0] = val
& 0xffffffc0;
8236 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8240 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8242 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8243 pipe_name(pipe
), fb
->width
, fb
->height
,
8244 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8245 plane_config
->size
);
8247 plane_config
->fb
= intel_fb
;
8250 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
8251 struct intel_crtc_state
*pipe_config
)
8253 struct drm_device
*dev
= crtc
->base
.dev
;
8254 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8257 if (!intel_display_power_is_enabled(dev_priv
,
8258 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8261 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8262 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8264 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8265 if (!(tmp
& PIPECONF_ENABLE
))
8268 switch (tmp
& PIPECONF_BPC_MASK
) {
8270 pipe_config
->pipe_bpp
= 18;
8273 pipe_config
->pipe_bpp
= 24;
8275 case PIPECONF_10BPC
:
8276 pipe_config
->pipe_bpp
= 30;
8278 case PIPECONF_12BPC
:
8279 pipe_config
->pipe_bpp
= 36;
8285 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
8286 pipe_config
->limited_color_range
= true;
8288 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
8289 struct intel_shared_dpll
*pll
;
8291 pipe_config
->has_pch_encoder
= true;
8293 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
8294 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8295 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8297 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8299 if (HAS_PCH_IBX(dev_priv
->dev
)) {
8300 pipe_config
->shared_dpll
=
8301 (enum intel_dpll_id
) crtc
->pipe
;
8303 tmp
= I915_READ(PCH_DPLL_SEL
);
8304 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
8305 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
8307 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
8310 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8312 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8313 &pipe_config
->dpll_hw_state
));
8315 tmp
= pipe_config
->dpll_hw_state
.dpll
;
8316 pipe_config
->pixel_multiplier
=
8317 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
8318 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
8320 ironlake_pch_clock_get(crtc
, pipe_config
);
8322 pipe_config
->pixel_multiplier
= 1;
8325 intel_get_pipe_timings(crtc
, pipe_config
);
8327 ironlake_get_pfit_config(crtc
, pipe_config
);
8332 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
8334 struct drm_device
*dev
= dev_priv
->dev
;
8335 struct intel_crtc
*crtc
;
8337 for_each_intel_crtc(dev
, crtc
)
8338 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
8339 pipe_name(crtc
->pipe
));
8341 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
8342 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
8343 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
8344 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
8345 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
8346 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
8347 "CPU PWM1 enabled\n");
8348 if (IS_HASWELL(dev
))
8349 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
8350 "CPU PWM2 enabled\n");
8351 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
8352 "PCH PWM1 enabled\n");
8353 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
8354 "Utility pin enabled\n");
8355 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
8358 * In theory we can still leave IRQs enabled, as long as only the HPD
8359 * interrupts remain enabled. We used to check for that, but since it's
8360 * gen-specific and since we only disable LCPLL after we fully disable
8361 * the interrupts, the check below should be enough.
8363 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
8366 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
8368 struct drm_device
*dev
= dev_priv
->dev
;
8370 if (IS_HASWELL(dev
))
8371 return I915_READ(D_COMP_HSW
);
8373 return I915_READ(D_COMP_BDW
);
8376 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
8378 struct drm_device
*dev
= dev_priv
->dev
;
8380 if (IS_HASWELL(dev
)) {
8381 mutex_lock(&dev_priv
->rps
.hw_lock
);
8382 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
8384 DRM_ERROR("Failed to write to D_COMP\n");
8385 mutex_unlock(&dev_priv
->rps
.hw_lock
);
8387 I915_WRITE(D_COMP_BDW
, val
);
8388 POSTING_READ(D_COMP_BDW
);
8393 * This function implements pieces of two sequences from BSpec:
8394 * - Sequence for display software to disable LCPLL
8395 * - Sequence for display software to allow package C8+
8396 * The steps implemented here are just the steps that actually touch the LCPLL
8397 * register. Callers should take care of disabling all the display engine
8398 * functions, doing the mode unset, fixing interrupts, etc.
8400 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
8401 bool switch_to_fclk
, bool allow_power_down
)
8405 assert_can_disable_lcpll(dev_priv
);
8407 val
= I915_READ(LCPLL_CTL
);
8409 if (switch_to_fclk
) {
8410 val
|= LCPLL_CD_SOURCE_FCLK
;
8411 I915_WRITE(LCPLL_CTL
, val
);
8413 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
8414 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
8415 DRM_ERROR("Switching to FCLK failed\n");
8417 val
= I915_READ(LCPLL_CTL
);
8420 val
|= LCPLL_PLL_DISABLE
;
8421 I915_WRITE(LCPLL_CTL
, val
);
8422 POSTING_READ(LCPLL_CTL
);
8424 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
8425 DRM_ERROR("LCPLL still locked\n");
8427 val
= hsw_read_dcomp(dev_priv
);
8428 val
|= D_COMP_COMP_DISABLE
;
8429 hsw_write_dcomp(dev_priv
, val
);
8432 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
8434 DRM_ERROR("D_COMP RCOMP still in progress\n");
8436 if (allow_power_down
) {
8437 val
= I915_READ(LCPLL_CTL
);
8438 val
|= LCPLL_POWER_DOWN_ALLOW
;
8439 I915_WRITE(LCPLL_CTL
, val
);
8440 POSTING_READ(LCPLL_CTL
);
8445 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8448 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
8452 val
= I915_READ(LCPLL_CTL
);
8454 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
8455 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
8459 * Make sure we're not on PC8 state before disabling PC8, otherwise
8460 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8462 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
8464 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
8465 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
8466 I915_WRITE(LCPLL_CTL
, val
);
8467 POSTING_READ(LCPLL_CTL
);
8470 val
= hsw_read_dcomp(dev_priv
);
8471 val
|= D_COMP_COMP_FORCE
;
8472 val
&= ~D_COMP_COMP_DISABLE
;
8473 hsw_write_dcomp(dev_priv
, val
);
8475 val
= I915_READ(LCPLL_CTL
);
8476 val
&= ~LCPLL_PLL_DISABLE
;
8477 I915_WRITE(LCPLL_CTL
, val
);
8479 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
8480 DRM_ERROR("LCPLL not locked yet\n");
8482 if (val
& LCPLL_CD_SOURCE_FCLK
) {
8483 val
= I915_READ(LCPLL_CTL
);
8484 val
&= ~LCPLL_CD_SOURCE_FCLK
;
8485 I915_WRITE(LCPLL_CTL
, val
);
8487 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
8488 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
8489 DRM_ERROR("Switching back to LCPLL failed\n");
8492 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
8496 * Package states C8 and deeper are really deep PC states that can only be
8497 * reached when all the devices on the system allow it, so even if the graphics
8498 * device allows PC8+, it doesn't mean the system will actually get to these
8499 * states. Our driver only allows PC8+ when going into runtime PM.
8501 * The requirements for PC8+ are that all the outputs are disabled, the power
8502 * well is disabled and most interrupts are disabled, and these are also
8503 * requirements for runtime PM. When these conditions are met, we manually do
8504 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8505 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8508 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8509 * the state of some registers, so when we come back from PC8+ we need to
8510 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8511 * need to take care of the registers kept by RC6. Notice that this happens even
8512 * if we don't put the device in PCI D3 state (which is what currently happens
8513 * because of the runtime PM support).
8515 * For more, read "Display Sequences for Package C8" on the hardware
8518 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
8520 struct drm_device
*dev
= dev_priv
->dev
;
8523 DRM_DEBUG_KMS("Enabling package C8+\n");
8525 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8526 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8527 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
8528 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8531 lpt_disable_clkout_dp(dev
);
8532 hsw_disable_lcpll(dev_priv
, true, true);
8535 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
8537 struct drm_device
*dev
= dev_priv
->dev
;
8540 DRM_DEBUG_KMS("Disabling package C8+\n");
8542 hsw_restore_lcpll(dev_priv
);
8543 lpt_init_pch_refclk(dev
);
8545 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
8546 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
8547 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
8548 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
8551 intel_prepare_ddi(dev
);
8554 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
8555 struct intel_crtc_state
*crtc_state
)
8557 if (!intel_ddi_pll_select(crtc
, crtc_state
))
8560 crtc
->lowfreq_avail
= false;
8565 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8567 struct intel_crtc_state
*pipe_config
)
8569 u32 temp
, dpll_ctl1
;
8571 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
8572 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
8574 switch (pipe_config
->ddi_pll_sel
) {
8577 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8578 * of the shared DPLL framework and thus needs to be read out
8581 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
8582 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
8585 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
8588 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
8591 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
8596 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
8598 struct intel_crtc_state
*pipe_config
)
8600 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
8602 switch (pipe_config
->ddi_pll_sel
) {
8603 case PORT_CLK_SEL_WRPLL1
:
8604 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
8606 case PORT_CLK_SEL_WRPLL2
:
8607 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
8612 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
8613 struct intel_crtc_state
*pipe_config
)
8615 struct drm_device
*dev
= crtc
->base
.dev
;
8616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8617 struct intel_shared_dpll
*pll
;
8621 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
8623 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
8625 if (IS_SKYLAKE(dev
))
8626 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
8628 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
8630 if (pipe_config
->shared_dpll
>= 0) {
8631 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
8633 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
8634 &pipe_config
->dpll_hw_state
));
8638 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8639 * DDI E. So just check whether this pipe is wired to DDI E and whether
8640 * the PCH transcoder is on.
8642 if (INTEL_INFO(dev
)->gen
< 9 &&
8643 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
8644 pipe_config
->has_pch_encoder
= true;
8646 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
8647 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
8648 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
8650 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
8654 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
8655 struct intel_crtc_state
*pipe_config
)
8657 struct drm_device
*dev
= crtc
->base
.dev
;
8658 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8659 enum intel_display_power_domain pfit_domain
;
8662 if (!intel_display_power_is_enabled(dev_priv
,
8663 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8666 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8667 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8669 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
8670 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
8671 enum pipe trans_edp_pipe
;
8672 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
8674 WARN(1, "unknown pipe linked to edp transcoder\n");
8675 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
8676 case TRANS_DDI_EDP_INPUT_A_ON
:
8677 trans_edp_pipe
= PIPE_A
;
8679 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
8680 trans_edp_pipe
= PIPE_B
;
8682 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
8683 trans_edp_pipe
= PIPE_C
;
8687 if (trans_edp_pipe
== crtc
->pipe
)
8688 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
8691 if (!intel_display_power_is_enabled(dev_priv
,
8692 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
8695 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
8696 if (!(tmp
& PIPECONF_ENABLE
))
8699 haswell_get_ddi_port_state(crtc
, pipe_config
);
8701 intel_get_pipe_timings(crtc
, pipe_config
);
8703 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
8704 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
8705 if (IS_SKYLAKE(dev
))
8706 skylake_get_pfit_config(crtc
, pipe_config
);
8708 ironlake_get_pfit_config(crtc
, pipe_config
);
8711 if (IS_HASWELL(dev
))
8712 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
8713 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
8715 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
8716 pipe_config
->pixel_multiplier
=
8717 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
8719 pipe_config
->pixel_multiplier
= 1;
8725 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8727 struct drm_device
*dev
= crtc
->dev
;
8728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8729 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8730 uint32_t cntl
= 0, size
= 0;
8733 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
8734 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
8735 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8739 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8750 cntl
|= CURSOR_ENABLE
|
8751 CURSOR_GAMMA_ENABLE
|
8752 CURSOR_FORMAT_ARGB
|
8753 CURSOR_STRIDE(stride
);
8755 size
= (height
<< 12) | width
;
8758 if (intel_crtc
->cursor_cntl
!= 0 &&
8759 (intel_crtc
->cursor_base
!= base
||
8760 intel_crtc
->cursor_size
!= size
||
8761 intel_crtc
->cursor_cntl
!= cntl
)) {
8762 /* On these chipsets we can only modify the base/size/stride
8763 * whilst the cursor is disabled.
8765 I915_WRITE(_CURACNTR
, 0);
8766 POSTING_READ(_CURACNTR
);
8767 intel_crtc
->cursor_cntl
= 0;
8770 if (intel_crtc
->cursor_base
!= base
) {
8771 I915_WRITE(_CURABASE
, base
);
8772 intel_crtc
->cursor_base
= base
;
8775 if (intel_crtc
->cursor_size
!= size
) {
8776 I915_WRITE(CURSIZE
, size
);
8777 intel_crtc
->cursor_size
= size
;
8780 if (intel_crtc
->cursor_cntl
!= cntl
) {
8781 I915_WRITE(_CURACNTR
, cntl
);
8782 POSTING_READ(_CURACNTR
);
8783 intel_crtc
->cursor_cntl
= cntl
;
8787 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8789 struct drm_device
*dev
= crtc
->dev
;
8790 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8791 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8792 int pipe
= intel_crtc
->pipe
;
8797 cntl
= MCURSOR_GAMMA_ENABLE
;
8798 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
8800 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8803 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8806 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8809 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
8812 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8814 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8815 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8818 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
8819 cntl
|= CURSOR_ROTATE_180
;
8821 if (intel_crtc
->cursor_cntl
!= cntl
) {
8822 I915_WRITE(CURCNTR(pipe
), cntl
);
8823 POSTING_READ(CURCNTR(pipe
));
8824 intel_crtc
->cursor_cntl
= cntl
;
8827 /* and commit changes on next vblank */
8828 I915_WRITE(CURBASE(pipe
), base
);
8829 POSTING_READ(CURBASE(pipe
));
8831 intel_crtc
->cursor_base
= base
;
8834 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8835 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8838 struct drm_device
*dev
= crtc
->dev
;
8839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8840 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8841 int pipe
= intel_crtc
->pipe
;
8842 int x
= crtc
->cursor_x
;
8843 int y
= crtc
->cursor_y
;
8844 u32 base
= 0, pos
= 0;
8847 base
= intel_crtc
->cursor_addr
;
8849 if (x
>= intel_crtc
->config
->pipe_src_w
)
8852 if (y
>= intel_crtc
->config
->pipe_src_h
)
8856 if (x
+ intel_crtc
->base
.cursor
->state
->crtc_w
<= 0)
8859 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8862 pos
|= x
<< CURSOR_X_SHIFT
;
8865 if (y
+ intel_crtc
->base
.cursor
->state
->crtc_h
<= 0)
8868 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8871 pos
|= y
<< CURSOR_Y_SHIFT
;
8873 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8876 I915_WRITE(CURPOS(pipe
), pos
);
8878 /* ILK+ do this automagically */
8879 if (HAS_GMCH_DISPLAY(dev
) &&
8880 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
8881 base
+= (intel_crtc
->base
.cursor
->state
->crtc_h
*
8882 intel_crtc
->base
.cursor
->state
->crtc_w
- 1) * 4;
8885 if (IS_845G(dev
) || IS_I865G(dev
))
8886 i845_update_cursor(crtc
, base
);
8888 i9xx_update_cursor(crtc
, base
);
8891 static bool cursor_size_ok(struct drm_device
*dev
,
8892 uint32_t width
, uint32_t height
)
8894 if (width
== 0 || height
== 0)
8898 * 845g/865g are special in that they are only limited by
8899 * the width of their cursors, the height is arbitrary up to
8900 * the precision of the register. Everything else requires
8901 * square cursors, limited to a few power-of-two sizes.
8903 if (IS_845G(dev
) || IS_I865G(dev
)) {
8904 if ((width
& 63) != 0)
8907 if (width
> (IS_845G(dev
) ? 64 : 512))
8913 switch (width
| height
) {
8928 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8929 u16
*blue
, uint32_t start
, uint32_t size
)
8931 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8932 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8934 for (i
= start
; i
< end
; i
++) {
8935 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8936 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8937 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8940 intel_crtc_load_lut(crtc
);
8943 /* VESA 640x480x72Hz mode to set on the pipe */
8944 static struct drm_display_mode load_detect_mode
= {
8945 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8946 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8949 struct drm_framebuffer
*
8950 __intel_framebuffer_create(struct drm_device
*dev
,
8951 struct drm_mode_fb_cmd2
*mode_cmd
,
8952 struct drm_i915_gem_object
*obj
)
8954 struct intel_framebuffer
*intel_fb
;
8957 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8959 drm_gem_object_unreference(&obj
->base
);
8960 return ERR_PTR(-ENOMEM
);
8963 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8967 return &intel_fb
->base
;
8969 drm_gem_object_unreference(&obj
->base
);
8972 return ERR_PTR(ret
);
8975 static struct drm_framebuffer
*
8976 intel_framebuffer_create(struct drm_device
*dev
,
8977 struct drm_mode_fb_cmd2
*mode_cmd
,
8978 struct drm_i915_gem_object
*obj
)
8980 struct drm_framebuffer
*fb
;
8983 ret
= i915_mutex_lock_interruptible(dev
);
8985 return ERR_PTR(ret
);
8986 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8987 mutex_unlock(&dev
->struct_mutex
);
8993 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8995 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8996 return ALIGN(pitch
, 64);
9000 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
9002 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
9003 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
9006 static struct drm_framebuffer
*
9007 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
9008 struct drm_display_mode
*mode
,
9011 struct drm_i915_gem_object
*obj
;
9012 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
9014 obj
= i915_gem_alloc_object(dev
,
9015 intel_framebuffer_size_for_mode(mode
, bpp
));
9017 return ERR_PTR(-ENOMEM
);
9019 mode_cmd
.width
= mode
->hdisplay
;
9020 mode_cmd
.height
= mode
->vdisplay
;
9021 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
9023 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
9025 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
9028 static struct drm_framebuffer
*
9029 mode_fits_in_fbdev(struct drm_device
*dev
,
9030 struct drm_display_mode
*mode
)
9032 #ifdef CONFIG_DRM_I915_FBDEV
9033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9034 struct drm_i915_gem_object
*obj
;
9035 struct drm_framebuffer
*fb
;
9037 if (!dev_priv
->fbdev
)
9040 if (!dev_priv
->fbdev
->fb
)
9043 obj
= dev_priv
->fbdev
->fb
->obj
;
9046 fb
= &dev_priv
->fbdev
->fb
->base
;
9047 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
9048 fb
->bits_per_pixel
))
9051 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
9060 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
9061 struct drm_display_mode
*mode
,
9062 struct intel_load_detect_pipe
*old
,
9063 struct drm_modeset_acquire_ctx
*ctx
)
9065 struct intel_crtc
*intel_crtc
;
9066 struct intel_encoder
*intel_encoder
=
9067 intel_attached_encoder(connector
);
9068 struct drm_crtc
*possible_crtc
;
9069 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9070 struct drm_crtc
*crtc
= NULL
;
9071 struct drm_device
*dev
= encoder
->dev
;
9072 struct drm_framebuffer
*fb
;
9073 struct drm_mode_config
*config
= &dev
->mode_config
;
9074 struct drm_atomic_state
*state
= NULL
;
9075 struct drm_connector_state
*connector_state
;
9078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9079 connector
->base
.id
, connector
->name
,
9080 encoder
->base
.id
, encoder
->name
);
9083 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
9088 * Algorithm gets a little messy:
9090 * - if the connector already has an assigned crtc, use it (but make
9091 * sure it's on first)
9093 * - try to find the first unused crtc that can drive this connector,
9094 * and use that if we find one
9097 /* See if we already have a CRTC for this connector */
9098 if (encoder
->crtc
) {
9099 crtc
= encoder
->crtc
;
9101 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9104 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9108 old
->dpms_mode
= connector
->dpms
;
9109 old
->load_detect_temp
= false;
9111 /* Make sure the crtc and connector are running */
9112 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
9113 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
9118 /* Find an unused one (if possible) */
9119 for_each_crtc(dev
, possible_crtc
) {
9121 if (!(encoder
->possible_crtcs
& (1 << i
)))
9123 if (possible_crtc
->state
->enable
)
9125 /* This can occur when applying the pipe A quirk on resume. */
9126 if (to_intel_crtc(possible_crtc
)->new_enabled
)
9129 crtc
= possible_crtc
;
9134 * If we didn't find an unused CRTC, don't use any.
9137 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9141 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
9144 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
9147 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
9148 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
9150 intel_crtc
= to_intel_crtc(crtc
);
9151 intel_crtc
->new_enabled
= true;
9152 intel_crtc
->new_config
= intel_crtc
->config
;
9153 old
->dpms_mode
= connector
->dpms
;
9154 old
->load_detect_temp
= true;
9155 old
->release_fb
= NULL
;
9157 state
= drm_atomic_state_alloc(dev
);
9161 state
->acquire_ctx
= ctx
;
9163 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9164 if (IS_ERR(connector_state
)) {
9165 ret
= PTR_ERR(connector_state
);
9169 connector_state
->crtc
= crtc
;
9170 connector_state
->best_encoder
= &intel_encoder
->base
;
9173 mode
= &load_detect_mode
;
9175 /* We need a framebuffer large enough to accommodate all accesses
9176 * that the plane may generate whilst we perform load detection.
9177 * We can not rely on the fbcon either being present (we get called
9178 * during its initialisation to detect all boot displays, or it may
9179 * not even exist) or that it is large enough to satisfy the
9182 fb
= mode_fits_in_fbdev(dev
, mode
);
9184 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9185 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
9186 old
->release_fb
= fb
;
9188 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9190 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9194 if (intel_set_mode(crtc
, mode
, 0, 0, fb
, state
)) {
9195 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9196 if (old
->release_fb
)
9197 old
->release_fb
->funcs
->destroy(old
->release_fb
);
9200 crtc
->primary
->crtc
= crtc
;
9202 /* let the connector get through one full cycle before testing */
9203 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
9207 intel_crtc
->new_enabled
= crtc
->state
->enable
;
9208 if (intel_crtc
->new_enabled
)
9209 intel_crtc
->new_config
= intel_crtc
->config
;
9211 intel_crtc
->new_config
= NULL
;
9214 drm_atomic_state_free(state
);
9218 if (ret
== -EDEADLK
) {
9219 drm_modeset_backoff(ctx
);
9226 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
9227 struct intel_load_detect_pipe
*old
,
9228 struct drm_modeset_acquire_ctx
*ctx
)
9230 struct drm_device
*dev
= connector
->dev
;
9231 struct intel_encoder
*intel_encoder
=
9232 intel_attached_encoder(connector
);
9233 struct drm_encoder
*encoder
= &intel_encoder
->base
;
9234 struct drm_crtc
*crtc
= encoder
->crtc
;
9235 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9236 struct drm_atomic_state
*state
;
9237 struct drm_connector_state
*connector_state
;
9239 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9240 connector
->base
.id
, connector
->name
,
9241 encoder
->base
.id
, encoder
->name
);
9243 if (old
->load_detect_temp
) {
9244 state
= drm_atomic_state_alloc(dev
);
9248 state
->acquire_ctx
= ctx
;
9250 connector_state
= drm_atomic_get_connector_state(state
, connector
);
9251 if (IS_ERR(connector_state
))
9254 to_intel_connector(connector
)->new_encoder
= NULL
;
9255 intel_encoder
->new_crtc
= NULL
;
9256 intel_crtc
->new_enabled
= false;
9257 intel_crtc
->new_config
= NULL
;
9259 connector_state
->best_encoder
= NULL
;
9260 connector_state
->crtc
= NULL
;
9262 intel_set_mode(crtc
, NULL
, 0, 0, NULL
, state
);
9264 drm_atomic_state_free(state
);
9266 if (old
->release_fb
) {
9267 drm_framebuffer_unregister_private(old
->release_fb
);
9268 drm_framebuffer_unreference(old
->release_fb
);
9274 /* Switch crtc and encoder back off if necessary */
9275 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
9276 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
9280 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9281 drm_atomic_state_free(state
);
9284 static int i9xx_pll_refclk(struct drm_device
*dev
,
9285 const struct intel_crtc_state
*pipe_config
)
9287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9288 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9290 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
9291 return dev_priv
->vbt
.lvds_ssc_freq
;
9292 else if (HAS_PCH_SPLIT(dev
))
9294 else if (!IS_GEN2(dev
))
9300 /* Returns the clock of the currently programmed mode of the given pipe. */
9301 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
9302 struct intel_crtc_state
*pipe_config
)
9304 struct drm_device
*dev
= crtc
->base
.dev
;
9305 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9306 int pipe
= pipe_config
->cpu_transcoder
;
9307 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
9309 intel_clock_t clock
;
9310 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
9312 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
9313 fp
= pipe_config
->dpll_hw_state
.fp0
;
9315 fp
= pipe_config
->dpll_hw_state
.fp1
;
9317 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
9318 if (IS_PINEVIEW(dev
)) {
9319 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
9320 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
9322 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
9323 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
9326 if (!IS_GEN2(dev
)) {
9327 if (IS_PINEVIEW(dev
))
9328 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
9329 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
9331 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
9332 DPLL_FPA01_P1_POST_DIV_SHIFT
);
9334 switch (dpll
& DPLL_MODE_MASK
) {
9335 case DPLLB_MODE_DAC_SERIAL
:
9336 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
9339 case DPLLB_MODE_LVDS
:
9340 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
9344 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9345 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
9349 if (IS_PINEVIEW(dev
))
9350 pineview_clock(refclk
, &clock
);
9352 i9xx_clock(refclk
, &clock
);
9354 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
9355 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
9358 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
9359 DPLL_FPA01_P1_POST_DIV_SHIFT
);
9361 if (lvds
& LVDS_CLKB_POWER_UP
)
9366 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
9369 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
9370 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
9372 if (dpll
& PLL_P2_DIVIDE_BY_4
)
9378 i9xx_clock(refclk
, &clock
);
9382 * This value includes pixel_multiplier. We will use
9383 * port_clock to compute adjusted_mode.crtc_clock in the
9384 * encoder's get_config() function.
9386 pipe_config
->port_clock
= clock
.dot
;
9389 int intel_dotclock_calculate(int link_freq
,
9390 const struct intel_link_m_n
*m_n
)
9393 * The calculation for the data clock is:
9394 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9395 * But we want to avoid losing precison if possible, so:
9396 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9398 * and the link clock is simpler:
9399 * link_clock = (m * link_clock) / n
9405 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
9408 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
9409 struct intel_crtc_state
*pipe_config
)
9411 struct drm_device
*dev
= crtc
->base
.dev
;
9413 /* read out port_clock from the DPLL */
9414 i9xx_crtc_clock_get(crtc
, pipe_config
);
9417 * This value does not include pixel_multiplier.
9418 * We will check that port_clock and adjusted_mode.crtc_clock
9419 * agree once we know their relationship in the encoder's
9420 * get_config() function.
9422 pipe_config
->base
.adjusted_mode
.crtc_clock
=
9423 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
9424 &pipe_config
->fdi_m_n
);
9427 /** Returns the currently programmed mode of the given pipe. */
9428 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
9429 struct drm_crtc
*crtc
)
9431 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9432 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9433 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
9434 struct drm_display_mode
*mode
;
9435 struct intel_crtc_state pipe_config
;
9436 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
9437 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
9438 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
9439 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
9440 enum pipe pipe
= intel_crtc
->pipe
;
9442 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
9447 * Construct a pipe_config sufficient for getting the clock info
9448 * back out of crtc_clock_get.
9450 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9451 * to use a real value here instead.
9453 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
9454 pipe_config
.pixel_multiplier
= 1;
9455 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
9456 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
9457 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
9458 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
9460 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
9461 mode
->hdisplay
= (htot
& 0xffff) + 1;
9462 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
9463 mode
->hsync_start
= (hsync
& 0xffff) + 1;
9464 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
9465 mode
->vdisplay
= (vtot
& 0xffff) + 1;
9466 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
9467 mode
->vsync_start
= (vsync
& 0xffff) + 1;
9468 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
9470 drm_mode_set_name(mode
);
9475 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
9477 struct drm_device
*dev
= crtc
->dev
;
9478 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9479 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9481 if (!HAS_GMCH_DISPLAY(dev
))
9484 if (!dev_priv
->lvds_downclock_avail
)
9488 * Since this is called by a timer, we should never get here in
9491 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
9492 int pipe
= intel_crtc
->pipe
;
9493 int dpll_reg
= DPLL(pipe
);
9496 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9498 assert_panel_unlocked(dev_priv
, pipe
);
9500 dpll
= I915_READ(dpll_reg
);
9501 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
9502 I915_WRITE(dpll_reg
, dpll
);
9503 intel_wait_for_vblank(dev
, pipe
);
9504 dpll
= I915_READ(dpll_reg
);
9505 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
9506 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9511 void intel_mark_busy(struct drm_device
*dev
)
9513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9515 if (dev_priv
->mm
.busy
)
9518 intel_runtime_pm_get(dev_priv
);
9519 i915_update_gfx_val(dev_priv
);
9520 if (INTEL_INFO(dev
)->gen
>= 6)
9521 gen6_rps_busy(dev_priv
);
9522 dev_priv
->mm
.busy
= true;
9525 void intel_mark_idle(struct drm_device
*dev
)
9527 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9528 struct drm_crtc
*crtc
;
9530 if (!dev_priv
->mm
.busy
)
9533 dev_priv
->mm
.busy
= false;
9535 for_each_crtc(dev
, crtc
) {
9536 if (!crtc
->primary
->fb
)
9539 intel_decrease_pllclock(crtc
);
9542 if (INTEL_INFO(dev
)->gen
>= 6)
9543 gen6_rps_idle(dev
->dev_private
);
9545 intel_runtime_pm_put(dev_priv
);
9548 static void intel_crtc_set_state(struct intel_crtc
*crtc
,
9549 struct intel_crtc_state
*crtc_state
)
9551 kfree(crtc
->config
);
9552 crtc
->config
= crtc_state
;
9553 crtc
->base
.state
= &crtc_state
->base
;
9556 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9558 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9559 struct drm_device
*dev
= crtc
->dev
;
9560 struct intel_unpin_work
*work
;
9562 spin_lock_irq(&dev
->event_lock
);
9563 work
= intel_crtc
->unpin_work
;
9564 intel_crtc
->unpin_work
= NULL
;
9565 spin_unlock_irq(&dev
->event_lock
);
9568 cancel_work_sync(&work
->work
);
9572 intel_crtc_set_state(intel_crtc
, NULL
);
9573 drm_crtc_cleanup(crtc
);
9578 static void intel_unpin_work_fn(struct work_struct
*__work
)
9580 struct intel_unpin_work
*work
=
9581 container_of(__work
, struct intel_unpin_work
, work
);
9582 struct drm_device
*dev
= work
->crtc
->dev
;
9583 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9585 mutex_lock(&dev
->struct_mutex
);
9586 intel_unpin_fb_obj(work
->old_fb
, work
->crtc
->primary
->state
);
9587 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9589 intel_fbc_update(dev
);
9591 if (work
->flip_queued_req
)
9592 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
9593 mutex_unlock(&dev
->struct_mutex
);
9595 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9596 drm_framebuffer_unreference(work
->old_fb
);
9598 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9599 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9604 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9605 struct drm_crtc
*crtc
)
9607 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9608 struct intel_unpin_work
*work
;
9609 unsigned long flags
;
9611 /* Ignore early vblank irqs */
9612 if (intel_crtc
== NULL
)
9616 * This is called both by irq handlers and the reset code (to complete
9617 * lost pageflips) so needs the full irqsave spinlocks.
9619 spin_lock_irqsave(&dev
->event_lock
, flags
);
9620 work
= intel_crtc
->unpin_work
;
9622 /* Ensure we don't miss a work->pending update ... */
9625 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9626 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9630 page_flip_completed(intel_crtc
);
9632 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9635 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9638 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9640 do_intel_finish_page_flip(dev
, crtc
);
9643 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9645 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9646 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9648 do_intel_finish_page_flip(dev
, crtc
);
9651 /* Is 'a' after or equal to 'b'? */
9652 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9654 return !((a
- b
) & 0x80000000);
9657 static bool page_flip_finished(struct intel_crtc
*crtc
)
9659 struct drm_device
*dev
= crtc
->base
.dev
;
9660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9662 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
9663 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
9667 * The relevant registers doen't exist on pre-ctg.
9668 * As the flip done interrupt doesn't trigger for mmio
9669 * flips on gmch platforms, a flip count check isn't
9670 * really needed there. But since ctg has the registers,
9671 * include it in the check anyway.
9673 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9677 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9678 * used the same base address. In that case the mmio flip might
9679 * have completed, but the CS hasn't even executed the flip yet.
9681 * A flip count check isn't enough as the CS might have updated
9682 * the base address just after start of vblank, but before we
9683 * managed to process the interrupt. This means we'd complete the
9686 * Combining both checks should get us a good enough result. It may
9687 * still happen that the CS flip has been executed, but has not
9688 * yet actually completed. But in case the base address is the same
9689 * anyway, we don't really care.
9691 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9692 crtc
->unpin_work
->gtt_offset
&&
9693 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9694 crtc
->unpin_work
->flip_count
);
9697 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9699 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9700 struct intel_crtc
*intel_crtc
=
9701 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9702 unsigned long flags
;
9706 * This is called both by irq handlers and the reset code (to complete
9707 * lost pageflips) so needs the full irqsave spinlocks.
9709 * NB: An MMIO update of the plane base pointer will also
9710 * generate a page-flip completion irq, i.e. every modeset
9711 * is also accompanied by a spurious intel_prepare_page_flip().
9713 spin_lock_irqsave(&dev
->event_lock
, flags
);
9714 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9715 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9716 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9719 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9721 /* Ensure that the work item is consistent when activating it ... */
9723 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9724 /* and that it is marked active as soon as the irq could fire. */
9728 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9729 struct drm_crtc
*crtc
,
9730 struct drm_framebuffer
*fb
,
9731 struct drm_i915_gem_object
*obj
,
9732 struct intel_engine_cs
*ring
,
9735 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9739 ret
= intel_ring_begin(ring
, 6);
9743 /* Can't queue multiple flips, so wait for the previous
9744 * one to finish before executing the next.
9746 if (intel_crtc
->plane
)
9747 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9749 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9750 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9751 intel_ring_emit(ring
, MI_NOOP
);
9752 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9753 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9754 intel_ring_emit(ring
, fb
->pitches
[0]);
9755 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9756 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9758 intel_mark_page_flip_active(intel_crtc
);
9759 __intel_ring_advance(ring
);
9763 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9764 struct drm_crtc
*crtc
,
9765 struct drm_framebuffer
*fb
,
9766 struct drm_i915_gem_object
*obj
,
9767 struct intel_engine_cs
*ring
,
9770 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9774 ret
= intel_ring_begin(ring
, 6);
9778 if (intel_crtc
->plane
)
9779 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9781 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9782 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9783 intel_ring_emit(ring
, MI_NOOP
);
9784 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9785 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9786 intel_ring_emit(ring
, fb
->pitches
[0]);
9787 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9788 intel_ring_emit(ring
, MI_NOOP
);
9790 intel_mark_page_flip_active(intel_crtc
);
9791 __intel_ring_advance(ring
);
9795 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9796 struct drm_crtc
*crtc
,
9797 struct drm_framebuffer
*fb
,
9798 struct drm_i915_gem_object
*obj
,
9799 struct intel_engine_cs
*ring
,
9802 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9803 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9804 uint32_t pf
, pipesrc
;
9807 ret
= intel_ring_begin(ring
, 4);
9811 /* i965+ uses the linear or tiled offsets from the
9812 * Display Registers (which do not change across a page-flip)
9813 * so we need only reprogram the base address.
9815 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9816 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9817 intel_ring_emit(ring
, fb
->pitches
[0]);
9818 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9821 /* XXX Enabling the panel-fitter across page-flip is so far
9822 * untested on non-native modes, so ignore it for now.
9823 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9826 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9827 intel_ring_emit(ring
, pf
| pipesrc
);
9829 intel_mark_page_flip_active(intel_crtc
);
9830 __intel_ring_advance(ring
);
9834 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9835 struct drm_crtc
*crtc
,
9836 struct drm_framebuffer
*fb
,
9837 struct drm_i915_gem_object
*obj
,
9838 struct intel_engine_cs
*ring
,
9841 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9842 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9843 uint32_t pf
, pipesrc
;
9846 ret
= intel_ring_begin(ring
, 4);
9850 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9851 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9852 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9853 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9855 /* Contrary to the suggestions in the documentation,
9856 * "Enable Panel Fitter" does not seem to be required when page
9857 * flipping with a non-native mode, and worse causes a normal
9859 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9862 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9863 intel_ring_emit(ring
, pf
| pipesrc
);
9865 intel_mark_page_flip_active(intel_crtc
);
9866 __intel_ring_advance(ring
);
9870 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9871 struct drm_crtc
*crtc
,
9872 struct drm_framebuffer
*fb
,
9873 struct drm_i915_gem_object
*obj
,
9874 struct intel_engine_cs
*ring
,
9877 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9878 uint32_t plane_bit
= 0;
9881 switch (intel_crtc
->plane
) {
9883 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9886 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9889 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9892 WARN_ONCE(1, "unknown plane in flip command\n");
9897 if (ring
->id
== RCS
) {
9900 * On Gen 8, SRM is now taking an extra dword to accommodate
9901 * 48bits addresses, and we need a NOOP for the batch size to
9909 * BSpec MI_DISPLAY_FLIP for IVB:
9910 * "The full packet must be contained within the same cache line."
9912 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9913 * cacheline, if we ever start emitting more commands before
9914 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9915 * then do the cacheline alignment, and finally emit the
9918 ret
= intel_ring_cacheline_align(ring
);
9922 ret
= intel_ring_begin(ring
, len
);
9926 /* Unmask the flip-done completion message. Note that the bspec says that
9927 * we should do this for both the BCS and RCS, and that we must not unmask
9928 * more than one flip event at any time (or ensure that one flip message
9929 * can be sent by waiting for flip-done prior to queueing new flips).
9930 * Experimentation says that BCS works despite DERRMR masking all
9931 * flip-done completion events and that unmasking all planes at once
9932 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9933 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9935 if (ring
->id
== RCS
) {
9936 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9937 intel_ring_emit(ring
, DERRMR
);
9938 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9939 DERRMR_PIPEB_PRI_FLIP_DONE
|
9940 DERRMR_PIPEC_PRI_FLIP_DONE
));
9942 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9943 MI_SRM_LRM_GLOBAL_GTT
);
9945 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9946 MI_SRM_LRM_GLOBAL_GTT
);
9947 intel_ring_emit(ring
, DERRMR
);
9948 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9950 intel_ring_emit(ring
, 0);
9951 intel_ring_emit(ring
, MI_NOOP
);
9955 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9956 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9957 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9958 intel_ring_emit(ring
, (MI_NOOP
));
9960 intel_mark_page_flip_active(intel_crtc
);
9961 __intel_ring_advance(ring
);
9965 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9966 struct drm_i915_gem_object
*obj
)
9969 * This is not being used for older platforms, because
9970 * non-availability of flip done interrupt forces us to use
9971 * CS flips. Older platforms derive flip done using some clever
9972 * tricks involving the flip_pending status bits and vblank irqs.
9973 * So using MMIO flips there would disrupt this mechanism.
9979 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9982 if (i915
.use_mmio_flip
< 0)
9984 else if (i915
.use_mmio_flip
> 0)
9986 else if (i915
.enable_execlists
)
9989 return ring
!= i915_gem_request_get_ring(obj
->last_read_req
);
9992 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9994 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9995 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9996 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
9997 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
9998 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9999 const enum pipe pipe
= intel_crtc
->pipe
;
10002 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
10003 ctl
&= ~PLANE_CTL_TILED_MASK
;
10004 if (obj
->tiling_mode
== I915_TILING_X
)
10005 ctl
|= PLANE_CTL_TILED_X
;
10008 * The stride is either expressed as a multiple of 64 bytes chunks for
10009 * linear buffers or in number of tiles for tiled buffers.
10011 stride
= fb
->pitches
[0] >> 6;
10012 if (obj
->tiling_mode
== I915_TILING_X
)
10013 stride
= fb
->pitches
[0] >> 9; /* X tiles are 512 bytes wide */
10016 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10017 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10019 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
10020 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
10022 I915_WRITE(PLANE_SURF(pipe
, 0), intel_crtc
->unpin_work
->gtt_offset
);
10023 POSTING_READ(PLANE_SURF(pipe
, 0));
10026 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10028 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10029 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10030 struct intel_framebuffer
*intel_fb
=
10031 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
10032 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
10036 reg
= DSPCNTR(intel_crtc
->plane
);
10037 dspcntr
= I915_READ(reg
);
10039 if (obj
->tiling_mode
!= I915_TILING_NONE
)
10040 dspcntr
|= DISPPLANE_TILED
;
10042 dspcntr
&= ~DISPPLANE_TILED
;
10044 I915_WRITE(reg
, dspcntr
);
10046 I915_WRITE(DSPSURF(intel_crtc
->plane
),
10047 intel_crtc
->unpin_work
->gtt_offset
);
10048 POSTING_READ(DSPSURF(intel_crtc
->plane
));
10053 * XXX: This is the temporary way to update the plane registers until we get
10054 * around to using the usual plane update functions for MMIO flips
10056 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
10058 struct drm_device
*dev
= intel_crtc
->base
.dev
;
10059 bool atomic_update
;
10060 u32 start_vbl_count
;
10062 intel_mark_page_flip_active(intel_crtc
);
10064 atomic_update
= intel_pipe_update_start(intel_crtc
, &start_vbl_count
);
10066 if (INTEL_INFO(dev
)->gen
>= 9)
10067 skl_do_mmio_flip(intel_crtc
);
10069 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10070 ilk_do_mmio_flip(intel_crtc
);
10073 intel_pipe_update_end(intel_crtc
, start_vbl_count
);
10076 static void intel_mmio_flip_work_func(struct work_struct
*work
)
10078 struct intel_crtc
*crtc
=
10079 container_of(work
, struct intel_crtc
, mmio_flip
.work
);
10080 struct intel_mmio_flip
*mmio_flip
;
10082 mmio_flip
= &crtc
->mmio_flip
;
10083 if (mmio_flip
->req
)
10084 WARN_ON(__i915_wait_request(mmio_flip
->req
,
10085 crtc
->reset_counter
,
10086 false, NULL
, NULL
) != 0);
10088 intel_do_mmio_flip(crtc
);
10089 if (mmio_flip
->req
) {
10090 mutex_lock(&crtc
->base
.dev
->struct_mutex
);
10091 i915_gem_request_assign(&mmio_flip
->req
, NULL
);
10092 mutex_unlock(&crtc
->base
.dev
->struct_mutex
);
10096 static int intel_queue_mmio_flip(struct drm_device
*dev
,
10097 struct drm_crtc
*crtc
,
10098 struct drm_framebuffer
*fb
,
10099 struct drm_i915_gem_object
*obj
,
10100 struct intel_engine_cs
*ring
,
10103 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10105 i915_gem_request_assign(&intel_crtc
->mmio_flip
.req
,
10106 obj
->last_write_req
);
10108 schedule_work(&intel_crtc
->mmio_flip
.work
);
10113 static int intel_default_queue_flip(struct drm_device
*dev
,
10114 struct drm_crtc
*crtc
,
10115 struct drm_framebuffer
*fb
,
10116 struct drm_i915_gem_object
*obj
,
10117 struct intel_engine_cs
*ring
,
10123 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
10124 struct drm_crtc
*crtc
)
10126 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10127 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10128 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
10131 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
10134 if (!work
->enable_stall_check
)
10137 if (work
->flip_ready_vblank
== 0) {
10138 if (work
->flip_queued_req
&&
10139 !i915_gem_request_completed(work
->flip_queued_req
, true))
10142 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
10145 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
10148 /* Potential stall - if we see that the flip has happened,
10149 * assume a missed interrupt. */
10150 if (INTEL_INFO(dev
)->gen
>= 4)
10151 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
10153 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
10155 /* There is a potential issue here with a false positive after a flip
10156 * to the same address. We could address this by checking for a
10157 * non-incrementing frame counter.
10159 return addr
== work
->gtt_offset
;
10162 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
10164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10165 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10166 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10168 WARN_ON(!in_interrupt());
10173 spin_lock(&dev
->event_lock
);
10174 if (intel_crtc
->unpin_work
&& __intel_pageflip_stall_check(dev
, crtc
)) {
10175 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10176 intel_crtc
->unpin_work
->flip_queued_vblank
,
10177 drm_vblank_count(dev
, pipe
));
10178 page_flip_completed(intel_crtc
);
10180 spin_unlock(&dev
->event_lock
);
10183 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
10184 struct drm_framebuffer
*fb
,
10185 struct drm_pending_vblank_event
*event
,
10186 uint32_t page_flip_flags
)
10188 struct drm_device
*dev
= crtc
->dev
;
10189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10190 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10191 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10192 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10193 struct drm_plane
*primary
= crtc
->primary
;
10194 enum pipe pipe
= intel_crtc
->pipe
;
10195 struct intel_unpin_work
*work
;
10196 struct intel_engine_cs
*ring
;
10200 * drm_mode_page_flip_ioctl() should already catch this, but double
10201 * check to be safe. In the future we may enable pageflipping from
10202 * a disabled primary plane.
10204 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
10207 /* Can't change pixel format via MI display flips. */
10208 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
10212 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10213 * Note that pitch changes could also affect these register.
10215 if (INTEL_INFO(dev
)->gen
> 3 &&
10216 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
10217 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
10220 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
10223 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
10227 work
->event
= event
;
10229 work
->old_fb
= old_fb
;
10230 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
10232 ret
= drm_crtc_vblank_get(crtc
);
10236 /* We borrow the event spin lock for protecting unpin_work */
10237 spin_lock_irq(&dev
->event_lock
);
10238 if (intel_crtc
->unpin_work
) {
10239 /* Before declaring the flip queue wedged, check if
10240 * the hardware completed the operation behind our backs.
10242 if (__intel_pageflip_stall_check(dev
, crtc
)) {
10243 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10244 page_flip_completed(intel_crtc
);
10246 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10247 spin_unlock_irq(&dev
->event_lock
);
10249 drm_crtc_vblank_put(crtc
);
10254 intel_crtc
->unpin_work
= work
;
10255 spin_unlock_irq(&dev
->event_lock
);
10257 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
10258 flush_workqueue(dev_priv
->wq
);
10260 /* Reference the objects for the scheduled work. */
10261 drm_framebuffer_reference(work
->old_fb
);
10262 drm_gem_object_reference(&obj
->base
);
10264 crtc
->primary
->fb
= fb
;
10265 update_state_fb(crtc
->primary
);
10267 work
->pending_flip_obj
= obj
;
10269 ret
= i915_mutex_lock_interruptible(dev
);
10273 atomic_inc(&intel_crtc
->unpin_work_count
);
10274 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
10276 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
10277 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
10279 if (IS_VALLEYVIEW(dev
)) {
10280 ring
= &dev_priv
->ring
[BCS
];
10281 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
10282 /* vlv: DISPLAY_FLIP fails to change tiling */
10284 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
10285 ring
= &dev_priv
->ring
[BCS
];
10286 } else if (INTEL_INFO(dev
)->gen
>= 7) {
10287 ring
= i915_gem_request_get_ring(obj
->last_read_req
);
10288 if (ring
== NULL
|| ring
->id
!= RCS
)
10289 ring
= &dev_priv
->ring
[BCS
];
10291 ring
= &dev_priv
->ring
[RCS
];
10294 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
10295 crtc
->primary
->state
, ring
);
10297 goto cleanup_pending
;
10299 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
), obj
)
10300 + intel_crtc
->dspaddr_offset
;
10302 if (use_mmio_flip(ring
, obj
)) {
10303 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
10306 goto cleanup_unpin
;
10308 i915_gem_request_assign(&work
->flip_queued_req
,
10309 obj
->last_write_req
);
10311 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
10314 goto cleanup_unpin
;
10316 i915_gem_request_assign(&work
->flip_queued_req
,
10317 intel_ring_get_request(ring
));
10320 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
10321 work
->enable_stall_check
= true;
10323 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
10324 INTEL_FRONTBUFFER_PRIMARY(pipe
));
10326 intel_fbc_disable(dev
);
10327 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
10328 mutex_unlock(&dev
->struct_mutex
);
10330 trace_i915_flip_request(intel_crtc
->plane
, obj
);
10335 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
10337 atomic_dec(&intel_crtc
->unpin_work_count
);
10338 mutex_unlock(&dev
->struct_mutex
);
10340 crtc
->primary
->fb
= old_fb
;
10341 update_state_fb(crtc
->primary
);
10343 drm_gem_object_unreference_unlocked(&obj
->base
);
10344 drm_framebuffer_unreference(work
->old_fb
);
10346 spin_lock_irq(&dev
->event_lock
);
10347 intel_crtc
->unpin_work
= NULL
;
10348 spin_unlock_irq(&dev
->event_lock
);
10350 drm_crtc_vblank_put(crtc
);
10356 ret
= intel_plane_restore(primary
);
10357 if (ret
== 0 && event
) {
10358 spin_lock_irq(&dev
->event_lock
);
10359 drm_send_vblank_event(dev
, pipe
, event
);
10360 spin_unlock_irq(&dev
->event_lock
);
10366 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
10367 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
10368 .load_lut
= intel_crtc_load_lut
,
10369 .atomic_begin
= intel_begin_crtc_commit
,
10370 .atomic_flush
= intel_finish_crtc_commit
,
10374 * intel_modeset_update_staged_output_state
10376 * Updates the staged output configuration state, e.g. after we've read out the
10377 * current hw state.
10379 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
10381 struct intel_crtc
*crtc
;
10382 struct intel_encoder
*encoder
;
10383 struct intel_connector
*connector
;
10385 for_each_intel_connector(dev
, connector
) {
10386 connector
->new_encoder
=
10387 to_intel_encoder(connector
->base
.encoder
);
10390 for_each_intel_encoder(dev
, encoder
) {
10391 encoder
->new_crtc
=
10392 to_intel_crtc(encoder
->base
.crtc
);
10395 for_each_intel_crtc(dev
, crtc
) {
10396 crtc
->new_enabled
= crtc
->base
.state
->enable
;
10398 if (crtc
->new_enabled
)
10399 crtc
->new_config
= crtc
->config
;
10401 crtc
->new_config
= NULL
;
10405 /* Transitional helper to copy current connector/encoder state to
10406 * connector->state. This is needed so that code that is partially
10407 * converted to atomic does the right thing.
10409 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
10411 struct intel_connector
*connector
;
10413 for_each_intel_connector(dev
, connector
) {
10414 if (connector
->base
.encoder
) {
10415 connector
->base
.state
->best_encoder
=
10416 connector
->base
.encoder
;
10417 connector
->base
.state
->crtc
=
10418 connector
->base
.encoder
->crtc
;
10420 connector
->base
.state
->best_encoder
= NULL
;
10421 connector
->base
.state
->crtc
= NULL
;
10427 * intel_modeset_commit_output_state
10429 * This function copies the stage display pipe configuration to the real one.
10431 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
10433 struct intel_crtc
*crtc
;
10434 struct intel_encoder
*encoder
;
10435 struct intel_connector
*connector
;
10437 for_each_intel_connector(dev
, connector
) {
10438 connector
->base
.encoder
= &connector
->new_encoder
->base
;
10441 for_each_intel_encoder(dev
, encoder
) {
10442 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
10445 for_each_intel_crtc(dev
, crtc
) {
10446 crtc
->base
.state
->enable
= crtc
->new_enabled
;
10447 crtc
->base
.enabled
= crtc
->new_enabled
;
10450 intel_modeset_update_connector_atomic_state(dev
);
10454 connected_sink_compute_bpp(struct intel_connector
*connector
,
10455 struct intel_crtc_state
*pipe_config
)
10457 int bpp
= pipe_config
->pipe_bpp
;
10459 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10460 connector
->base
.base
.id
,
10461 connector
->base
.name
);
10463 /* Don't use an invalid EDID bpc value */
10464 if (connector
->base
.display_info
.bpc
&&
10465 connector
->base
.display_info
.bpc
* 3 < bpp
) {
10466 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10467 bpp
, connector
->base
.display_info
.bpc
*3);
10468 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
10471 /* Clamp bpp to 8 on screens without EDID 1.4 */
10472 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
10473 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10475 pipe_config
->pipe_bpp
= 24;
10480 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
10481 struct drm_framebuffer
*fb
,
10482 struct intel_crtc_state
*pipe_config
)
10484 struct drm_device
*dev
= crtc
->base
.dev
;
10485 struct drm_atomic_state
*state
;
10486 struct intel_connector
*connector
;
10489 switch (fb
->pixel_format
) {
10490 case DRM_FORMAT_C8
:
10491 bpp
= 8*3; /* since we go through a colormap */
10493 case DRM_FORMAT_XRGB1555
:
10494 case DRM_FORMAT_ARGB1555
:
10495 /* checked in intel_framebuffer_init already */
10496 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10498 case DRM_FORMAT_RGB565
:
10499 bpp
= 6*3; /* min is 18bpp */
10501 case DRM_FORMAT_XBGR8888
:
10502 case DRM_FORMAT_ABGR8888
:
10503 /* checked in intel_framebuffer_init already */
10504 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10506 case DRM_FORMAT_XRGB8888
:
10507 case DRM_FORMAT_ARGB8888
:
10510 case DRM_FORMAT_XRGB2101010
:
10511 case DRM_FORMAT_ARGB2101010
:
10512 case DRM_FORMAT_XBGR2101010
:
10513 case DRM_FORMAT_ABGR2101010
:
10514 /* checked in intel_framebuffer_init already */
10515 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10519 /* TODO: gen4+ supports 16 bpc floating point, too. */
10521 DRM_DEBUG_KMS("unsupported depth\n");
10525 pipe_config
->pipe_bpp
= bpp
;
10527 state
= pipe_config
->base
.state
;
10529 /* Clamp display bpp to EDID value */
10530 for (i
= 0; i
< state
->num_connector
; i
++) {
10531 if (!state
->connectors
[i
])
10534 connector
= to_intel_connector(state
->connectors
[i
]);
10535 if (state
->connector_states
[i
]->crtc
!= &crtc
->base
)
10538 connected_sink_compute_bpp(connector
, pipe_config
);
10544 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10546 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10547 "type: 0x%x flags: 0x%x\n",
10549 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10550 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10551 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10552 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10555 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10556 struct intel_crtc_state
*pipe_config
,
10557 const char *context
)
10559 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10560 context
, pipe_name(crtc
->pipe
));
10562 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10563 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10564 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10565 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10566 pipe_config
->has_pch_encoder
,
10567 pipe_config
->fdi_lanes
,
10568 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10569 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10570 pipe_config
->fdi_m_n
.tu
);
10571 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10572 pipe_config
->has_dp_encoder
,
10573 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10574 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10575 pipe_config
->dp_m_n
.tu
);
10577 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10578 pipe_config
->has_dp_encoder
,
10579 pipe_config
->dp_m2_n2
.gmch_m
,
10580 pipe_config
->dp_m2_n2
.gmch_n
,
10581 pipe_config
->dp_m2_n2
.link_m
,
10582 pipe_config
->dp_m2_n2
.link_n
,
10583 pipe_config
->dp_m2_n2
.tu
);
10585 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10586 pipe_config
->has_audio
,
10587 pipe_config
->has_infoframe
);
10589 DRM_DEBUG_KMS("requested mode:\n");
10590 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
10591 DRM_DEBUG_KMS("adjusted mode:\n");
10592 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
10593 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
10594 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10595 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10596 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10597 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10598 pipe_config
->gmch_pfit
.control
,
10599 pipe_config
->gmch_pfit
.pgm_ratios
,
10600 pipe_config
->gmch_pfit
.lvds_border_bits
);
10601 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10602 pipe_config
->pch_pfit
.pos
,
10603 pipe_config
->pch_pfit
.size
,
10604 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10605 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10606 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10609 static bool encoders_cloneable(const struct intel_encoder
*a
,
10610 const struct intel_encoder
*b
)
10612 /* masks could be asymmetric, so check both ways */
10613 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10614 b
->cloneable
& (1 << a
->type
));
10617 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10618 struct intel_encoder
*encoder
)
10620 struct drm_device
*dev
= crtc
->base
.dev
;
10621 struct intel_encoder
*source_encoder
;
10623 for_each_intel_encoder(dev
, source_encoder
) {
10624 if (source_encoder
->new_crtc
!= crtc
)
10627 if (!encoders_cloneable(encoder
, source_encoder
))
10634 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10636 struct drm_device
*dev
= crtc
->base
.dev
;
10637 struct intel_encoder
*encoder
;
10639 for_each_intel_encoder(dev
, encoder
) {
10640 if (encoder
->new_crtc
!= crtc
)
10643 if (!check_single_encoder_cloning(crtc
, encoder
))
10650 static bool check_digital_port_conflicts(struct drm_device
*dev
)
10652 struct intel_connector
*connector
;
10653 unsigned int used_ports
= 0;
10656 * Walk the connector list instead of the encoder
10657 * list to detect the problem on ddi platforms
10658 * where there's just one encoder per digital port.
10660 for_each_intel_connector(dev
, connector
) {
10661 struct intel_encoder
*encoder
= connector
->new_encoder
;
10666 WARN_ON(!encoder
->new_crtc
);
10668 switch (encoder
->type
) {
10669 unsigned int port_mask
;
10670 case INTEL_OUTPUT_UNKNOWN
:
10671 if (WARN_ON(!HAS_DDI(dev
)))
10673 case INTEL_OUTPUT_DISPLAYPORT
:
10674 case INTEL_OUTPUT_HDMI
:
10675 case INTEL_OUTPUT_EDP
:
10676 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
10678 /* the same port mustn't appear more than once */
10679 if (used_ports
& port_mask
)
10682 used_ports
|= port_mask
;
10692 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
10694 struct drm_crtc_state tmp_state
;
10696 /* Clear only the intel specific part of the crtc state */
10697 tmp_state
= crtc_state
->base
;
10698 memset(crtc_state
, 0, sizeof *crtc_state
);
10699 crtc_state
->base
= tmp_state
;
10702 static struct intel_crtc_state
*
10703 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10704 struct drm_framebuffer
*fb
,
10705 struct drm_display_mode
*mode
,
10706 struct drm_atomic_state
*state
)
10708 struct drm_device
*dev
= crtc
->dev
;
10709 struct intel_encoder
*encoder
;
10710 struct intel_connector
*connector
;
10711 struct drm_connector_state
*connector_state
;
10712 struct intel_crtc_state
*pipe_config
;
10713 int plane_bpp
, ret
= -EINVAL
;
10717 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10718 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10719 return ERR_PTR(-EINVAL
);
10722 if (!check_digital_port_conflicts(dev
)) {
10723 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10724 return ERR_PTR(-EINVAL
);
10727 pipe_config
= intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));
10728 if (IS_ERR(pipe_config
))
10729 return pipe_config
;
10731 clear_intel_crtc_state(pipe_config
);
10733 pipe_config
->base
.crtc
= crtc
;
10734 drm_mode_copy(&pipe_config
->base
.adjusted_mode
, mode
);
10735 drm_mode_copy(&pipe_config
->base
.mode
, mode
);
10737 pipe_config
->cpu_transcoder
=
10738 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10739 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10742 * Sanitize sync polarity flags based on requested ones. If neither
10743 * positive or negative polarity is requested, treat this as meaning
10744 * negative polarity.
10746 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10747 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10748 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10750 if (!(pipe_config
->base
.adjusted_mode
.flags
&
10751 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10752 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10754 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10755 * plane pixel format and any sink constraints into account. Returns the
10756 * source plane bpp so that dithering can be selected on mismatches
10757 * after encoders and crtc also have had their say. */
10758 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10764 * Determine the real pipe dimensions. Note that stereo modes can
10765 * increase the actual pipe size due to the frame doubling and
10766 * insertion of additional space for blanks between the frame. This
10767 * is stored in the crtc timings. We use the requested mode to do this
10768 * computation to clearly distinguish it from the adjusted mode, which
10769 * can be changed by the connectors in the below retry loop.
10771 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
10772 &pipe_config
->pipe_src_w
,
10773 &pipe_config
->pipe_src_h
);
10776 /* Ensure the port clock defaults are reset when retrying. */
10777 pipe_config
->port_clock
= 0;
10778 pipe_config
->pixel_multiplier
= 1;
10780 /* Fill in default crtc timings, allow encoders to overwrite them. */
10781 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
10782 CRTC_STEREO_DOUBLE
);
10784 /* Pass our mode to the connectors and the CRTC to give them a chance to
10785 * adjust it according to limitations or connector properties, and also
10786 * a chance to reject the mode entirely.
10788 for (i
= 0; i
< state
->num_connector
; i
++) {
10789 connector
= to_intel_connector(state
->connectors
[i
]);
10793 connector_state
= state
->connector_states
[i
];
10794 if (connector_state
->crtc
!= crtc
)
10797 encoder
= to_intel_encoder(connector_state
->best_encoder
);
10799 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10800 DRM_DEBUG_KMS("Encoder config failure\n");
10805 /* Set default port clock if not overwritten by the encoder. Needs to be
10806 * done afterwards in case the encoder adjusts the mode. */
10807 if (!pipe_config
->port_clock
)
10808 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
10809 * pipe_config
->pixel_multiplier
;
10811 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10813 DRM_DEBUG_KMS("CRTC fixup failed\n");
10817 if (ret
== RETRY
) {
10818 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10823 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10825 goto encoder_retry
;
10828 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10829 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10830 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10832 return pipe_config
;
10834 return ERR_PTR(ret
);
10837 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10838 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10840 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10841 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10843 struct intel_crtc
*intel_crtc
;
10844 struct drm_device
*dev
= crtc
->dev
;
10845 struct intel_encoder
*encoder
;
10846 struct intel_connector
*connector
;
10847 struct drm_crtc
*tmp_crtc
;
10849 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10851 /* Check which crtcs have changed outputs connected to them, these need
10852 * to be part of the prepare_pipes mask. We don't (yet) support global
10853 * modeset across multiple crtcs, so modeset_pipes will only have one
10854 * bit set at most. */
10855 for_each_intel_connector(dev
, connector
) {
10856 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10859 if (connector
->base
.encoder
) {
10860 tmp_crtc
= connector
->base
.encoder
->crtc
;
10862 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10865 if (connector
->new_encoder
)
10867 1 << connector
->new_encoder
->new_crtc
->pipe
;
10870 for_each_intel_encoder(dev
, encoder
) {
10871 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10874 if (encoder
->base
.crtc
) {
10875 tmp_crtc
= encoder
->base
.crtc
;
10877 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10880 if (encoder
->new_crtc
)
10881 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10884 /* Check for pipes that will be enabled/disabled ... */
10885 for_each_intel_crtc(dev
, intel_crtc
) {
10886 if (intel_crtc
->base
.state
->enable
== intel_crtc
->new_enabled
)
10889 if (!intel_crtc
->new_enabled
)
10890 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10892 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10896 /* set_mode is also used to update properties on life display pipes. */
10897 intel_crtc
= to_intel_crtc(crtc
);
10898 if (intel_crtc
->new_enabled
)
10899 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10902 * For simplicity do a full modeset on any pipe where the output routing
10903 * changed. We could be more clever, but that would require us to be
10904 * more careful with calling the relevant encoder->mode_set functions.
10906 if (*prepare_pipes
)
10907 *modeset_pipes
= *prepare_pipes
;
10909 /* ... and mask these out. */
10910 *modeset_pipes
&= ~(*disable_pipes
);
10911 *prepare_pipes
&= ~(*disable_pipes
);
10914 * HACK: We don't (yet) fully support global modesets. intel_set_config
10915 * obies this rule, but the modeset restore mode of
10916 * intel_modeset_setup_hw_state does not.
10918 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10919 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10921 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10922 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10925 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10927 struct drm_encoder
*encoder
;
10928 struct drm_device
*dev
= crtc
->dev
;
10930 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10931 if (encoder
->crtc
== crtc
)
10938 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10940 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10941 struct intel_encoder
*intel_encoder
;
10942 struct intel_crtc
*intel_crtc
;
10943 struct drm_connector
*connector
;
10945 intel_shared_dpll_commit(dev_priv
);
10947 for_each_intel_encoder(dev
, intel_encoder
) {
10948 if (!intel_encoder
->base
.crtc
)
10951 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10953 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10954 intel_encoder
->connectors_active
= false;
10957 intel_modeset_commit_output_state(dev
);
10959 /* Double check state. */
10960 for_each_intel_crtc(dev
, intel_crtc
) {
10961 WARN_ON(intel_crtc
->base
.state
->enable
!= intel_crtc_in_use(&intel_crtc
->base
));
10962 WARN_ON(intel_crtc
->new_config
&&
10963 intel_crtc
->new_config
!= intel_crtc
->config
);
10964 WARN_ON(intel_crtc
->base
.state
->enable
!= !!intel_crtc
->new_config
);
10967 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10968 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10971 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10973 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10974 struct drm_property
*dpms_property
=
10975 dev
->mode_config
.dpms_property
;
10977 connector
->dpms
= DRM_MODE_DPMS_ON
;
10978 drm_object_property_set_value(&connector
->base
,
10982 intel_encoder
= to_intel_encoder(connector
->encoder
);
10983 intel_encoder
->connectors_active
= true;
10989 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10993 if (clock1
== clock2
)
10996 if (!clock1
|| !clock2
)
10999 diff
= abs(clock1
- clock2
);
11001 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
11007 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11008 list_for_each_entry((intel_crtc), \
11009 &(dev)->mode_config.crtc_list, \
11011 if (mask & (1 <<(intel_crtc)->pipe))
11014 intel_pipe_config_compare(struct drm_device
*dev
,
11015 struct intel_crtc_state
*current_config
,
11016 struct intel_crtc_state
*pipe_config
)
11018 #define PIPE_CONF_CHECK_X(name) \
11019 if (current_config->name != pipe_config->name) { \
11020 DRM_ERROR("mismatch in " #name " " \
11021 "(expected 0x%08x, found 0x%08x)\n", \
11022 current_config->name, \
11023 pipe_config->name); \
11027 #define PIPE_CONF_CHECK_I(name) \
11028 if (current_config->name != pipe_config->name) { \
11029 DRM_ERROR("mismatch in " #name " " \
11030 "(expected %i, found %i)\n", \
11031 current_config->name, \
11032 pipe_config->name); \
11036 /* This is required for BDW+ where there is only one set of registers for
11037 * switching between high and low RR.
11038 * This macro can be used whenever a comparison has to be made between one
11039 * hw state and multiple sw state variables.
11041 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11042 if ((current_config->name != pipe_config->name) && \
11043 (current_config->alt_name != pipe_config->name)) { \
11044 DRM_ERROR("mismatch in " #name " " \
11045 "(expected %i or %i, found %i)\n", \
11046 current_config->name, \
11047 current_config->alt_name, \
11048 pipe_config->name); \
11052 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11053 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11054 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11055 "(expected %i, found %i)\n", \
11056 current_config->name & (mask), \
11057 pipe_config->name & (mask)); \
11061 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11062 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11063 DRM_ERROR("mismatch in " #name " " \
11064 "(expected %i, found %i)\n", \
11065 current_config->name, \
11066 pipe_config->name); \
11070 #define PIPE_CONF_QUIRK(quirk) \
11071 ((current_config->quirks | pipe_config->quirks) & (quirk))
11073 PIPE_CONF_CHECK_I(cpu_transcoder
);
11075 PIPE_CONF_CHECK_I(has_pch_encoder
);
11076 PIPE_CONF_CHECK_I(fdi_lanes
);
11077 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
11078 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
11079 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
11080 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
11081 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
11083 PIPE_CONF_CHECK_I(has_dp_encoder
);
11085 if (INTEL_INFO(dev
)->gen
< 8) {
11086 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
11087 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
11088 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
11089 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
11090 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
11092 if (current_config
->has_drrs
) {
11093 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
11094 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
11095 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
11096 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
11097 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
11100 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
11101 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
11102 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
11103 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
11104 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
11107 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
11108 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
11109 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
11110 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
11111 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
11112 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
11114 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
11115 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
11116 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
11117 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
11118 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
11119 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
11121 PIPE_CONF_CHECK_I(pixel_multiplier
);
11122 PIPE_CONF_CHECK_I(has_hdmi_sink
);
11123 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
11124 IS_VALLEYVIEW(dev
))
11125 PIPE_CONF_CHECK_I(limited_color_range
);
11126 PIPE_CONF_CHECK_I(has_infoframe
);
11128 PIPE_CONF_CHECK_I(has_audio
);
11130 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11131 DRM_MODE_FLAG_INTERLACE
);
11133 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
11134 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11135 DRM_MODE_FLAG_PHSYNC
);
11136 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11137 DRM_MODE_FLAG_NHSYNC
);
11138 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11139 DRM_MODE_FLAG_PVSYNC
);
11140 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
11141 DRM_MODE_FLAG_NVSYNC
);
11144 PIPE_CONF_CHECK_I(pipe_src_w
);
11145 PIPE_CONF_CHECK_I(pipe_src_h
);
11148 * FIXME: BIOS likes to set up a cloned config with lvds+external
11149 * screen. Since we don't yet re-compute the pipe config when moving
11150 * just the lvds port away to another pipe the sw tracking won't match.
11152 * Proper atomic modesets with recomputed global state will fix this.
11153 * Until then just don't check gmch state for inherited modes.
11155 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
11156 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
11157 /* pfit ratios are autocomputed by the hw on gen4+ */
11158 if (INTEL_INFO(dev
)->gen
< 4)
11159 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
11160 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
11163 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
11164 if (current_config
->pch_pfit
.enabled
) {
11165 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
11166 PIPE_CONF_CHECK_I(pch_pfit
.size
);
11169 /* BDW+ don't expose a synchronous way to read the state */
11170 if (IS_HASWELL(dev
))
11171 PIPE_CONF_CHECK_I(ips_enabled
);
11173 PIPE_CONF_CHECK_I(double_wide
);
11175 PIPE_CONF_CHECK_X(ddi_pll_sel
);
11177 PIPE_CONF_CHECK_I(shared_dpll
);
11178 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
11179 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
11180 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
11181 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
11182 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
11183 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
11184 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
11185 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
11187 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
11188 PIPE_CONF_CHECK_I(pipe_bpp
);
11190 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
11191 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
11193 #undef PIPE_CONF_CHECK_X
11194 #undef PIPE_CONF_CHECK_I
11195 #undef PIPE_CONF_CHECK_I_ALT
11196 #undef PIPE_CONF_CHECK_FLAGS
11197 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11198 #undef PIPE_CONF_QUIRK
11203 static void check_wm_state(struct drm_device
*dev
)
11205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11206 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
11207 struct intel_crtc
*intel_crtc
;
11210 if (INTEL_INFO(dev
)->gen
< 9)
11213 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
11214 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
11216 for_each_intel_crtc(dev
, intel_crtc
) {
11217 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
11218 const enum pipe pipe
= intel_crtc
->pipe
;
11220 if (!intel_crtc
->active
)
11224 for_each_plane(dev_priv
, pipe
, plane
) {
11225 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
11226 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
11228 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11231 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11232 "(expected (%u,%u), found (%u,%u))\n",
11233 pipe_name(pipe
), plane
+ 1,
11234 sw_entry
->start
, sw_entry
->end
,
11235 hw_entry
->start
, hw_entry
->end
);
11239 hw_entry
= &hw_ddb
.cursor
[pipe
];
11240 sw_entry
= &sw_ddb
->cursor
[pipe
];
11242 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
11245 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11246 "(expected (%u,%u), found (%u,%u))\n",
11248 sw_entry
->start
, sw_entry
->end
,
11249 hw_entry
->start
, hw_entry
->end
);
11254 check_connector_state(struct drm_device
*dev
)
11256 struct intel_connector
*connector
;
11258 for_each_intel_connector(dev
, connector
) {
11259 /* This also checks the encoder/connector hw state with the
11260 * ->get_hw_state callbacks. */
11261 intel_connector_check_state(connector
);
11263 I915_STATE_WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
11264 "connector's staged encoder doesn't match current encoder\n");
11269 check_encoder_state(struct drm_device
*dev
)
11271 struct intel_encoder
*encoder
;
11272 struct intel_connector
*connector
;
11274 for_each_intel_encoder(dev
, encoder
) {
11275 bool enabled
= false;
11276 bool active
= false;
11277 enum pipe pipe
, tracked_pipe
;
11279 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11280 encoder
->base
.base
.id
,
11281 encoder
->base
.name
);
11283 I915_STATE_WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
11284 "encoder's stage crtc doesn't match current crtc\n");
11285 I915_STATE_WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
11286 "encoder's active_connectors set, but no crtc\n");
11288 for_each_intel_connector(dev
, connector
) {
11289 if (connector
->base
.encoder
!= &encoder
->base
)
11292 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
11296 * for MST connectors if we unplug the connector is gone
11297 * away but the encoder is still connected to a crtc
11298 * until a modeset happens in response to the hotplug.
11300 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
11303 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
11304 "encoder's enabled state mismatch "
11305 "(expected %i, found %i)\n",
11306 !!encoder
->base
.crtc
, enabled
);
11307 I915_STATE_WARN(active
&& !encoder
->base
.crtc
,
11308 "active encoder with no crtc\n");
11310 I915_STATE_WARN(encoder
->connectors_active
!= active
,
11311 "encoder's computed active state doesn't match tracked active state "
11312 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
11314 active
= encoder
->get_hw_state(encoder
, &pipe
);
11315 I915_STATE_WARN(active
!= encoder
->connectors_active
,
11316 "encoder's hw state doesn't match sw tracking "
11317 "(expected %i, found %i)\n",
11318 encoder
->connectors_active
, active
);
11320 if (!encoder
->base
.crtc
)
11323 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
11324 I915_STATE_WARN(active
&& pipe
!= tracked_pipe
,
11325 "active encoder's pipe doesn't match"
11326 "(expected %i, found %i)\n",
11327 tracked_pipe
, pipe
);
11333 check_crtc_state(struct drm_device
*dev
)
11335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11336 struct intel_crtc
*crtc
;
11337 struct intel_encoder
*encoder
;
11338 struct intel_crtc_state pipe_config
;
11340 for_each_intel_crtc(dev
, crtc
) {
11341 bool enabled
= false;
11342 bool active
= false;
11344 memset(&pipe_config
, 0, sizeof(pipe_config
));
11346 DRM_DEBUG_KMS("[CRTC:%d]\n",
11347 crtc
->base
.base
.id
);
11349 I915_STATE_WARN(crtc
->active
&& !crtc
->base
.state
->enable
,
11350 "active crtc, but not enabled in sw tracking\n");
11352 for_each_intel_encoder(dev
, encoder
) {
11353 if (encoder
->base
.crtc
!= &crtc
->base
)
11356 if (encoder
->connectors_active
)
11360 I915_STATE_WARN(active
!= crtc
->active
,
11361 "crtc's computed active state doesn't match tracked active state "
11362 "(expected %i, found %i)\n", active
, crtc
->active
);
11363 I915_STATE_WARN(enabled
!= crtc
->base
.state
->enable
,
11364 "crtc's computed enabled state doesn't match tracked enabled state "
11365 "(expected %i, found %i)\n", enabled
,
11366 crtc
->base
.state
->enable
);
11368 active
= dev_priv
->display
.get_pipe_config(crtc
,
11371 /* hw state is inconsistent with the pipe quirk */
11372 if ((crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
11373 (crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
11374 active
= crtc
->active
;
11376 for_each_intel_encoder(dev
, encoder
) {
11378 if (encoder
->base
.crtc
!= &crtc
->base
)
11380 if (encoder
->get_hw_state(encoder
, &pipe
))
11381 encoder
->get_config(encoder
, &pipe_config
);
11384 I915_STATE_WARN(crtc
->active
!= active
,
11385 "crtc active state doesn't match with hw state "
11386 "(expected %i, found %i)\n", crtc
->active
, active
);
11389 !intel_pipe_config_compare(dev
, crtc
->config
, &pipe_config
)) {
11390 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11391 intel_dump_pipe_config(crtc
, &pipe_config
,
11393 intel_dump_pipe_config(crtc
, crtc
->config
,
11400 check_shared_dpll_state(struct drm_device
*dev
)
11402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11403 struct intel_crtc
*crtc
;
11404 struct intel_dpll_hw_state dpll_hw_state
;
11407 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11408 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
11409 int enabled_crtcs
= 0, active_crtcs
= 0;
11412 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
11414 DRM_DEBUG_KMS("%s\n", pll
->name
);
11416 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
11418 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
11419 "more active pll users than references: %i vs %i\n",
11420 pll
->active
, hweight32(pll
->config
.crtc_mask
));
11421 I915_STATE_WARN(pll
->active
&& !pll
->on
,
11422 "pll in active use but not on in sw tracking\n");
11423 I915_STATE_WARN(pll
->on
&& !pll
->active
,
11424 "pll in on but not on in use in sw tracking\n");
11425 I915_STATE_WARN(pll
->on
!= active
,
11426 "pll on state mismatch (expected %i, found %i)\n",
11429 for_each_intel_crtc(dev
, crtc
) {
11430 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11432 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
11435 I915_STATE_WARN(pll
->active
!= active_crtcs
,
11436 "pll active crtcs mismatch (expected %i, found %i)\n",
11437 pll
->active
, active_crtcs
);
11438 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
11439 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11440 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
11442 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
11443 sizeof(dpll_hw_state
)),
11444 "pll hw state mismatch\n");
11449 intel_modeset_check_state(struct drm_device
*dev
)
11451 check_wm_state(dev
);
11452 check_connector_state(dev
);
11453 check_encoder_state(dev
);
11454 check_crtc_state(dev
);
11455 check_shared_dpll_state(dev
);
11458 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
11462 * FDI already provided one idea for the dotclock.
11463 * Yell if the encoder disagrees.
11465 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
11466 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11467 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
11470 static void update_scanline_offset(struct intel_crtc
*crtc
)
11472 struct drm_device
*dev
= crtc
->base
.dev
;
11475 * The scanline counter increments at the leading edge of hsync.
11477 * On most platforms it starts counting from vtotal-1 on the
11478 * first active line. That means the scanline counter value is
11479 * always one less than what we would expect. Ie. just after
11480 * start of vblank, which also occurs at start of hsync (on the
11481 * last active line), the scanline counter will read vblank_start-1.
11483 * On gen2 the scanline counter starts counting from 1 instead
11484 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11485 * to keep the value positive), instead of adding one.
11487 * On HSW+ the behaviour of the scanline counter depends on the output
11488 * type. For DP ports it behaves like most other platforms, but on HDMI
11489 * there's an extra 1 line difference. So we need to add two instead of
11490 * one to the value.
11492 if (IS_GEN2(dev
)) {
11493 const struct drm_display_mode
*mode
= &crtc
->config
->base
.adjusted_mode
;
11496 vtotal
= mode
->crtc_vtotal
;
11497 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
11500 crtc
->scanline_offset
= vtotal
- 1;
11501 } else if (HAS_DDI(dev
) &&
11502 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
11503 crtc
->scanline_offset
= 2;
11505 crtc
->scanline_offset
= 1;
11508 static struct intel_crtc_state
*
11509 intel_modeset_compute_config(struct drm_crtc
*crtc
,
11510 struct drm_display_mode
*mode
,
11511 struct drm_framebuffer
*fb
,
11512 struct drm_atomic_state
*state
,
11513 unsigned *modeset_pipes
,
11514 unsigned *prepare_pipes
,
11515 unsigned *disable_pipes
)
11517 struct drm_device
*dev
= crtc
->dev
;
11518 struct intel_crtc_state
*pipe_config
= NULL
;
11519 struct intel_crtc
*intel_crtc
;
11522 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
11524 return ERR_PTR(ret
);
11526 intel_modeset_affected_pipes(crtc
, modeset_pipes
,
11527 prepare_pipes
, disable_pipes
);
11529 for_each_intel_crtc_masked(dev
, *disable_pipes
, intel_crtc
) {
11530 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
11531 if (IS_ERR(pipe_config
))
11532 return pipe_config
;
11534 pipe_config
->base
.enable
= false;
11538 * Note this needs changes when we start tracking multiple modes
11539 * and crtcs. At that point we'll need to compute the whole config
11540 * (i.e. one pipe_config for each crtc) rather than just the one
11543 for_each_intel_crtc_masked(dev
, *modeset_pipes
, intel_crtc
) {
11544 /* FIXME: For now we still expect modeset_pipes has at most
11546 if (WARN_ON(&intel_crtc
->base
!= crtc
))
11549 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
, state
);
11550 if (IS_ERR(pipe_config
))
11551 return pipe_config
;
11553 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
11557 return intel_atomic_get_crtc_state(state
, to_intel_crtc(crtc
));;
11560 static int __intel_set_mode_setup_plls(struct drm_device
*dev
,
11561 unsigned modeset_pipes
,
11562 unsigned disable_pipes
)
11564 struct drm_i915_private
*dev_priv
= to_i915(dev
);
11565 unsigned clear_pipes
= modeset_pipes
| disable_pipes
;
11566 struct intel_crtc
*intel_crtc
;
11569 if (!dev_priv
->display
.crtc_compute_clock
)
11572 ret
= intel_shared_dpll_start_config(dev_priv
, clear_pipes
);
11576 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11577 struct intel_crtc_state
*state
= intel_crtc
->new_config
;
11578 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11581 intel_shared_dpll_abort_config(dev_priv
);
11590 static int __intel_set_mode(struct drm_crtc
*crtc
,
11591 struct drm_display_mode
*mode
,
11592 int x
, int y
, struct drm_framebuffer
*fb
,
11593 struct intel_crtc_state
*pipe_config
,
11594 unsigned modeset_pipes
,
11595 unsigned prepare_pipes
,
11596 unsigned disable_pipes
)
11598 struct drm_device
*dev
= crtc
->dev
;
11599 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11600 struct drm_display_mode
*saved_mode
;
11601 struct intel_crtc_state
*crtc_state_copy
= NULL
;
11602 struct intel_crtc
*intel_crtc
;
11605 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
11609 crtc_state_copy
= kmalloc(sizeof(*crtc_state_copy
), GFP_KERNEL
);
11610 if (!crtc_state_copy
) {
11615 *saved_mode
= crtc
->mode
;
11618 to_intel_crtc(crtc
)->new_config
= pipe_config
;
11621 * See if the config requires any additional preparation, e.g.
11622 * to adjust global state with pipes off. We need to do this
11623 * here so we can get the modeset_pipe updated config for the new
11624 * mode set on this crtc. For other crtcs we need to use the
11625 * adjusted_mode bits in the crtc directly.
11627 if (IS_VALLEYVIEW(dev
)) {
11628 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
11630 /* may have added more to prepare_pipes than we should */
11631 prepare_pipes
&= ~disable_pipes
;
11634 ret
= __intel_set_mode_setup_plls(dev
, modeset_pipes
, disable_pipes
);
11638 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
11639 intel_crtc_disable(&intel_crtc
->base
);
11641 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11642 if (intel_crtc
->base
.state
->enable
)
11643 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
11646 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11647 * to set it here already despite that we pass it down the callchain.
11649 * Note we'll need to fix this up when we start tracking multiple
11650 * pipes; here we assume a single modeset_pipe and only track the
11651 * single crtc and mode.
11653 if (modeset_pipes
) {
11654 crtc
->mode
= *mode
;
11655 /* mode_set/enable/disable functions rely on a correct pipe
11657 intel_crtc_set_state(to_intel_crtc(crtc
), pipe_config
);
11660 * Calculate and store various constants which
11661 * are later needed by vblank and swap-completion
11662 * timestamping. They are derived from true hwmode.
11664 drm_calc_timestamping_constants(crtc
,
11665 &pipe_config
->base
.adjusted_mode
);
11668 /* Only after disabling all output pipelines that will be changed can we
11669 * update the the output configuration. */
11670 intel_modeset_update_state(dev
, prepare_pipes
);
11672 modeset_update_crtc_power_domains(pipe_config
->base
.state
);
11674 /* Set up the DPLL and any encoders state that needs to adjust or depend
11677 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
11678 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
11679 int vdisplay
, hdisplay
;
11681 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
11682 ret
= primary
->funcs
->update_plane(primary
, &intel_crtc
->base
,
11684 hdisplay
, vdisplay
,
11686 hdisplay
<< 16, vdisplay
<< 16);
11689 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11690 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11691 update_scanline_offset(intel_crtc
);
11693 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11696 /* FIXME: add subpixel order */
11698 if (ret
&& crtc
->state
->enable
)
11699 crtc
->mode
= *saved_mode
;
11701 if (ret
== 0 && pipe_config
) {
11702 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11704 /* The pipe_config will be freed with the atomic state, so
11706 memcpy(crtc_state_copy
, intel_crtc
->config
,
11707 sizeof *crtc_state_copy
);
11708 intel_crtc
->config
= crtc_state_copy
;
11709 intel_crtc
->base
.state
= &crtc_state_copy
->base
;
11712 intel_crtc
->new_config
= intel_crtc
->config
;
11714 kfree(crtc_state_copy
);
11721 static int intel_set_mode_pipes(struct drm_crtc
*crtc
,
11722 struct drm_display_mode
*mode
,
11723 int x
, int y
, struct drm_framebuffer
*fb
,
11724 struct intel_crtc_state
*pipe_config
,
11725 unsigned modeset_pipes
,
11726 unsigned prepare_pipes
,
11727 unsigned disable_pipes
)
11731 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
, pipe_config
, modeset_pipes
,
11732 prepare_pipes
, disable_pipes
);
11735 intel_modeset_check_state(crtc
->dev
);
11740 static int intel_set_mode(struct drm_crtc
*crtc
,
11741 struct drm_display_mode
*mode
,
11742 int x
, int y
, struct drm_framebuffer
*fb
,
11743 struct drm_atomic_state
*state
)
11745 struct intel_crtc_state
*pipe_config
;
11746 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
11749 pipe_config
= intel_modeset_compute_config(crtc
, mode
, fb
, state
,
11754 if (IS_ERR(pipe_config
)) {
11755 ret
= PTR_ERR(pipe_config
);
11759 ret
= intel_set_mode_pipes(crtc
, mode
, x
, y
, fb
, pipe_config
,
11760 modeset_pipes
, prepare_pipes
,
11769 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11771 struct drm_device
*dev
= crtc
->dev
;
11772 struct drm_atomic_state
*state
;
11773 struct intel_encoder
*encoder
;
11774 struct intel_connector
*connector
;
11775 struct drm_connector_state
*connector_state
;
11777 state
= drm_atomic_state_alloc(dev
);
11779 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
11784 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
11786 /* The force restore path in the HW readout code relies on the staged
11787 * config still keeping the user requested config while the actual
11788 * state has been overwritten by the configuration read from HW. We
11789 * need to copy the staged config to the atomic state, otherwise the
11790 * mode set will just reapply the state the HW is already in. */
11791 for_each_intel_encoder(dev
, encoder
) {
11792 if (&encoder
->new_crtc
->base
!= crtc
)
11795 for_each_intel_connector(dev
, connector
) {
11796 if (connector
->new_encoder
!= encoder
)
11799 connector_state
= drm_atomic_get_connector_state(state
, &connector
->base
);
11800 if (IS_ERR(connector_state
)) {
11801 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
11802 connector
->base
.base
.id
,
11803 connector
->base
.name
,
11804 PTR_ERR(connector_state
));
11808 connector_state
->crtc
= crtc
;
11809 connector_state
->best_encoder
= &encoder
->base
;
11813 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
,
11816 drm_atomic_state_free(state
);
11819 #undef for_each_intel_crtc_masked
11821 static void intel_set_config_free(struct intel_set_config
*config
)
11826 kfree(config
->save_connector_encoders
);
11827 kfree(config
->save_encoder_crtcs
);
11828 kfree(config
->save_crtc_enabled
);
11832 static int intel_set_config_save_state(struct drm_device
*dev
,
11833 struct intel_set_config
*config
)
11835 struct drm_crtc
*crtc
;
11836 struct drm_encoder
*encoder
;
11837 struct drm_connector
*connector
;
11840 config
->save_crtc_enabled
=
11841 kcalloc(dev
->mode_config
.num_crtc
,
11842 sizeof(bool), GFP_KERNEL
);
11843 if (!config
->save_crtc_enabled
)
11846 config
->save_encoder_crtcs
=
11847 kcalloc(dev
->mode_config
.num_encoder
,
11848 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11849 if (!config
->save_encoder_crtcs
)
11852 config
->save_connector_encoders
=
11853 kcalloc(dev
->mode_config
.num_connector
,
11854 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11855 if (!config
->save_connector_encoders
)
11858 /* Copy data. Note that driver private data is not affected.
11859 * Should anything bad happen only the expected state is
11860 * restored, not the drivers personal bookkeeping.
11863 for_each_crtc(dev
, crtc
) {
11864 config
->save_crtc_enabled
[count
++] = crtc
->state
->enable
;
11868 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11869 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11873 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11874 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11880 static void intel_set_config_restore_state(struct drm_device
*dev
,
11881 struct intel_set_config
*config
)
11883 struct intel_crtc
*crtc
;
11884 struct intel_encoder
*encoder
;
11885 struct intel_connector
*connector
;
11889 for_each_intel_crtc(dev
, crtc
) {
11890 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11892 if (crtc
->new_enabled
)
11893 crtc
->new_config
= crtc
->config
;
11895 crtc
->new_config
= NULL
;
11899 for_each_intel_encoder(dev
, encoder
) {
11900 encoder
->new_crtc
=
11901 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11905 for_each_intel_connector(dev
, connector
) {
11906 connector
->new_encoder
=
11907 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11912 is_crtc_connector_off(struct drm_mode_set
*set
)
11916 if (set
->num_connectors
== 0)
11919 if (WARN_ON(set
->connectors
== NULL
))
11922 for (i
= 0; i
< set
->num_connectors
; i
++)
11923 if (set
->connectors
[i
]->encoder
&&
11924 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11925 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11932 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11933 struct intel_set_config
*config
)
11936 /* We should be able to check here if the fb has the same properties
11937 * and then just flip_or_move it */
11938 if (is_crtc_connector_off(set
)) {
11939 config
->mode_changed
= true;
11940 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11942 * If we have no fb, we can only flip as long as the crtc is
11943 * active, otherwise we need a full mode set. The crtc may
11944 * be active if we've only disabled the primary plane, or
11945 * in fastboot situations.
11947 if (set
->crtc
->primary
->fb
== NULL
) {
11948 struct intel_crtc
*intel_crtc
=
11949 to_intel_crtc(set
->crtc
);
11951 if (intel_crtc
->active
) {
11952 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11953 config
->fb_changed
= true;
11955 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11956 config
->mode_changed
= true;
11958 } else if (set
->fb
== NULL
) {
11959 config
->mode_changed
= true;
11960 } else if (set
->fb
->pixel_format
!=
11961 set
->crtc
->primary
->fb
->pixel_format
) {
11962 config
->mode_changed
= true;
11964 config
->fb_changed
= true;
11968 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11969 config
->fb_changed
= true;
11971 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11972 DRM_DEBUG_KMS("modes are different, full mode set\n");
11973 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11974 drm_mode_debug_printmodeline(set
->mode
);
11975 config
->mode_changed
= true;
11978 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11979 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11983 intel_modeset_stage_output_state(struct drm_device
*dev
,
11984 struct drm_mode_set
*set
,
11985 struct intel_set_config
*config
,
11986 struct drm_atomic_state
*state
)
11988 struct intel_connector
*connector
;
11989 struct drm_connector_state
*connector_state
;
11990 struct intel_encoder
*encoder
;
11991 struct intel_crtc
*crtc
;
11994 /* The upper layers ensure that we either disable a crtc or have a list
11995 * of connectors. For paranoia, double-check this. */
11996 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11997 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11999 for_each_intel_connector(dev
, connector
) {
12000 /* Otherwise traverse passed in connector list and get encoders
12002 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
12003 if (set
->connectors
[ro
] == &connector
->base
) {
12004 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
12009 /* If we disable the crtc, disable all its connectors. Also, if
12010 * the connector is on the changing crtc but not on the new
12011 * connector list, disable it. */
12012 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
12013 connector
->base
.encoder
&&
12014 connector
->base
.encoder
->crtc
== set
->crtc
) {
12015 connector
->new_encoder
= NULL
;
12017 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12018 connector
->base
.base
.id
,
12019 connector
->base
.name
);
12023 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
12024 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12025 connector
->base
.base
.id
,
12026 connector
->base
.name
);
12027 config
->mode_changed
= true;
12030 /* connector->new_encoder is now updated for all connectors. */
12032 /* Update crtc of enabled connectors. */
12033 for_each_intel_connector(dev
, connector
) {
12034 struct drm_crtc
*new_crtc
;
12036 if (!connector
->new_encoder
)
12039 new_crtc
= connector
->new_encoder
->base
.crtc
;
12041 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
12042 if (set
->connectors
[ro
] == &connector
->base
)
12043 new_crtc
= set
->crtc
;
12046 /* Make sure the new CRTC will work with the encoder */
12047 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
12051 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
12054 drm_atomic_get_connector_state(state
, &connector
->base
);
12055 if (IS_ERR(connector_state
))
12056 return PTR_ERR(connector_state
);
12058 connector_state
->crtc
= new_crtc
;
12059 connector_state
->best_encoder
= &connector
->new_encoder
->base
;
12061 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12062 connector
->base
.base
.id
,
12063 connector
->base
.name
,
12064 new_crtc
->base
.id
);
12067 /* Check for any encoders that needs to be disabled. */
12068 for_each_intel_encoder(dev
, encoder
) {
12069 int num_connectors
= 0;
12070 for_each_intel_connector(dev
, connector
) {
12071 if (connector
->new_encoder
== encoder
) {
12072 WARN_ON(!connector
->new_encoder
->new_crtc
);
12077 if (num_connectors
== 0)
12078 encoder
->new_crtc
= NULL
;
12079 else if (num_connectors
> 1)
12082 /* Only now check for crtc changes so we don't miss encoders
12083 * that will be disabled. */
12084 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
12085 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12086 encoder
->base
.base
.id
,
12087 encoder
->base
.name
);
12088 config
->mode_changed
= true;
12091 /* Now we've also updated encoder->new_crtc for all encoders. */
12092 for_each_intel_connector(dev
, connector
) {
12094 drm_atomic_get_connector_state(state
, &connector
->base
);
12095 if (IS_ERR(connector_state
))
12096 return PTR_ERR(connector_state
);
12098 if (connector
->new_encoder
) {
12099 if (connector
->new_encoder
!= connector
->encoder
)
12100 connector
->encoder
= connector
->new_encoder
;
12102 connector_state
->crtc
= NULL
;
12105 for_each_intel_crtc(dev
, crtc
) {
12106 crtc
->new_enabled
= false;
12108 for_each_intel_encoder(dev
, encoder
) {
12109 if (encoder
->new_crtc
== crtc
) {
12110 crtc
->new_enabled
= true;
12115 if (crtc
->new_enabled
!= crtc
->base
.state
->enable
) {
12116 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12117 crtc
->base
.base
.id
,
12118 crtc
->new_enabled
? "en" : "dis");
12119 config
->mode_changed
= true;
12122 if (crtc
->new_enabled
)
12123 crtc
->new_config
= crtc
->config
;
12125 crtc
->new_config
= NULL
;
12131 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
12133 struct drm_device
*dev
= crtc
->base
.dev
;
12134 struct intel_encoder
*encoder
;
12135 struct intel_connector
*connector
;
12137 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12138 pipe_name(crtc
->pipe
));
12140 for_each_intel_connector(dev
, connector
) {
12141 if (connector
->new_encoder
&&
12142 connector
->new_encoder
->new_crtc
== crtc
)
12143 connector
->new_encoder
= NULL
;
12146 for_each_intel_encoder(dev
, encoder
) {
12147 if (encoder
->new_crtc
== crtc
)
12148 encoder
->new_crtc
= NULL
;
12151 crtc
->new_enabled
= false;
12152 crtc
->new_config
= NULL
;
12155 static int intel_crtc_set_config(struct drm_mode_set
*set
)
12157 struct drm_device
*dev
;
12158 struct drm_mode_set save_set
;
12159 struct drm_atomic_state
*state
= NULL
;
12160 struct intel_set_config
*config
;
12161 struct intel_crtc_state
*pipe_config
;
12162 unsigned modeset_pipes
, prepare_pipes
, disable_pipes
;
12166 BUG_ON(!set
->crtc
);
12167 BUG_ON(!set
->crtc
->helper_private
);
12169 /* Enforce sane interface api - has been abused by the fb helper. */
12170 BUG_ON(!set
->mode
&& set
->fb
);
12171 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
12174 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12175 set
->crtc
->base
.id
, set
->fb
->base
.id
,
12176 (int)set
->num_connectors
, set
->x
, set
->y
);
12178 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
12181 dev
= set
->crtc
->dev
;
12184 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
12188 ret
= intel_set_config_save_state(dev
, config
);
12192 save_set
.crtc
= set
->crtc
;
12193 save_set
.mode
= &set
->crtc
->mode
;
12194 save_set
.x
= set
->crtc
->x
;
12195 save_set
.y
= set
->crtc
->y
;
12196 save_set
.fb
= set
->crtc
->primary
->fb
;
12198 /* Compute whether we need a full modeset, only an fb base update or no
12199 * change at all. In the future we might also check whether only the
12200 * mode changed, e.g. for LVDS where we only change the panel fitter in
12202 intel_set_config_compute_mode_changes(set
, config
);
12204 state
= drm_atomic_state_alloc(dev
);
12210 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
12212 ret
= intel_modeset_stage_output_state(dev
, set
, config
, state
);
12216 pipe_config
= intel_modeset_compute_config(set
->crtc
, set
->mode
,
12221 if (IS_ERR(pipe_config
)) {
12222 ret
= PTR_ERR(pipe_config
);
12224 } else if (pipe_config
) {
12225 if (pipe_config
->has_audio
!=
12226 to_intel_crtc(set
->crtc
)->config
->has_audio
)
12227 config
->mode_changed
= true;
12230 * Note we have an issue here with infoframes: current code
12231 * only updates them on the full mode set path per hw
12232 * requirements. So here we should be checking for any
12233 * required changes and forcing a mode set.
12237 intel_update_pipe_size(to_intel_crtc(set
->crtc
));
12239 if (config
->mode_changed
) {
12240 ret
= intel_set_mode_pipes(set
->crtc
, set
->mode
,
12241 set
->x
, set
->y
, set
->fb
, pipe_config
,
12242 modeset_pipes
, prepare_pipes
,
12244 } else if (config
->fb_changed
) {
12245 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
12246 struct drm_plane
*primary
= set
->crtc
->primary
;
12247 int vdisplay
, hdisplay
;
12249 drm_crtc_get_hv_timing(set
->mode
, &hdisplay
, &vdisplay
);
12250 ret
= primary
->funcs
->update_plane(primary
, set
->crtc
, set
->fb
,
12251 0, 0, hdisplay
, vdisplay
,
12252 set
->x
<< 16, set
->y
<< 16,
12253 hdisplay
<< 16, vdisplay
<< 16);
12256 * We need to make sure the primary plane is re-enabled if it
12257 * has previously been turned off.
12259 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
12260 WARN_ON(!intel_crtc
->active
);
12261 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
12265 * In the fastboot case this may be our only check of the
12266 * state after boot. It would be better to only do it on
12267 * the first update, but we don't have a nice way of doing that
12268 * (and really, set_config isn't used much for high freq page
12269 * flipping, so increasing its cost here shouldn't be a big
12272 if (i915
.fastboot
&& ret
== 0)
12273 intel_modeset_check_state(set
->crtc
->dev
);
12277 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12278 set
->crtc
->base
.id
, ret
);
12280 intel_set_config_restore_state(dev
, config
);
12282 drm_atomic_state_clear(state
);
12285 * HACK: if the pipe was on, but we didn't have a framebuffer,
12286 * force the pipe off to avoid oopsing in the modeset code
12287 * due to fb==NULL. This should only happen during boot since
12288 * we don't yet reconstruct the FB from the hardware state.
12290 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
12291 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
12293 /* Try to restore the config */
12294 if (config
->mode_changed
&&
12295 intel_set_mode(save_set
.crtc
, save_set
.mode
,
12296 save_set
.x
, save_set
.y
, save_set
.fb
,
12298 DRM_ERROR("failed to restore config after modeset failure\n");
12303 drm_atomic_state_free(state
);
12305 intel_set_config_free(config
);
12309 static const struct drm_crtc_funcs intel_crtc_funcs
= {
12310 .gamma_set
= intel_crtc_gamma_set
,
12311 .set_config
= intel_crtc_set_config
,
12312 .destroy
= intel_crtc_destroy
,
12313 .page_flip
= intel_crtc_page_flip
,
12314 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
12315 .atomic_destroy_state
= intel_crtc_destroy_state
,
12318 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
12319 struct intel_shared_dpll
*pll
,
12320 struct intel_dpll_hw_state
*hw_state
)
12324 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
12327 val
= I915_READ(PCH_DPLL(pll
->id
));
12328 hw_state
->dpll
= val
;
12329 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
12330 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
12332 return val
& DPLL_VCO_ENABLE
;
12335 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
12336 struct intel_shared_dpll
*pll
)
12338 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
12339 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
12342 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
12343 struct intel_shared_dpll
*pll
)
12345 /* PCH refclock must be enabled first */
12346 ibx_assert_pch_refclk_enabled(dev_priv
);
12348 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
12350 /* Wait for the clocks to stabilize. */
12351 POSTING_READ(PCH_DPLL(pll
->id
));
12354 /* The pixel multiplier can only be updated once the
12355 * DPLL is enabled and the clocks are stable.
12357 * So write it again.
12359 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
12360 POSTING_READ(PCH_DPLL(pll
->id
));
12364 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
12365 struct intel_shared_dpll
*pll
)
12367 struct drm_device
*dev
= dev_priv
->dev
;
12368 struct intel_crtc
*crtc
;
12370 /* Make sure no transcoder isn't still depending on us. */
12371 for_each_intel_crtc(dev
, crtc
) {
12372 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
12373 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
12376 I915_WRITE(PCH_DPLL(pll
->id
), 0);
12377 POSTING_READ(PCH_DPLL(pll
->id
));
12381 static char *ibx_pch_dpll_names
[] = {
12386 static void ibx_pch_dpll_init(struct drm_device
*dev
)
12388 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12391 dev_priv
->num_shared_dpll
= 2;
12393 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12394 dev_priv
->shared_dplls
[i
].id
= i
;
12395 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
12396 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
12397 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
12398 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
12399 dev_priv
->shared_dplls
[i
].get_hw_state
=
12400 ibx_pch_dpll_get_hw_state
;
12404 static void intel_shared_dpll_init(struct drm_device
*dev
)
12406 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12409 intel_ddi_pll_init(dev
);
12410 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
12411 ibx_pch_dpll_init(dev
);
12413 dev_priv
->num_shared_dpll
= 0;
12415 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
12419 * intel_wm_need_update - Check whether watermarks need updating
12420 * @plane: drm plane
12421 * @state: new plane state
12423 * Check current plane state versus the new one to determine whether
12424 * watermarks need to be recalculated.
12426 * Returns true or false.
12428 bool intel_wm_need_update(struct drm_plane
*plane
,
12429 struct drm_plane_state
*state
)
12431 /* Update watermarks on tiling changes. */
12432 if (!plane
->state
->fb
|| !state
->fb
||
12433 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
12434 plane
->state
->rotation
!= state
->rotation
)
12441 * intel_prepare_plane_fb - Prepare fb for usage on plane
12442 * @plane: drm plane to prepare for
12443 * @fb: framebuffer to prepare for presentation
12445 * Prepares a framebuffer for usage on a display plane. Generally this
12446 * involves pinning the underlying object and updating the frontbuffer tracking
12447 * bits. Some older platforms need special physical address handling for
12450 * Returns 0 on success, negative error code on failure.
12453 intel_prepare_plane_fb(struct drm_plane
*plane
,
12454 struct drm_framebuffer
*fb
,
12455 const struct drm_plane_state
*new_state
)
12457 struct drm_device
*dev
= plane
->dev
;
12458 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12459 enum pipe pipe
= intel_plane
->pipe
;
12460 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12461 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
12462 unsigned frontbuffer_bits
= 0;
12468 switch (plane
->type
) {
12469 case DRM_PLANE_TYPE_PRIMARY
:
12470 frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
12472 case DRM_PLANE_TYPE_CURSOR
:
12473 frontbuffer_bits
= INTEL_FRONTBUFFER_CURSOR(pipe
);
12475 case DRM_PLANE_TYPE_OVERLAY
:
12476 frontbuffer_bits
= INTEL_FRONTBUFFER_SPRITE(pipe
);
12480 mutex_lock(&dev
->struct_mutex
);
12482 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
12483 INTEL_INFO(dev
)->cursor_needs_physical
) {
12484 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
12485 ret
= i915_gem_object_attach_phys(obj
, align
);
12487 DRM_DEBUG_KMS("failed to attach phys object\n");
12489 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
);
12493 i915_gem_track_fb(old_obj
, obj
, frontbuffer_bits
);
12495 mutex_unlock(&dev
->struct_mutex
);
12501 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12502 * @plane: drm plane to clean up for
12503 * @fb: old framebuffer that was on plane
12505 * Cleans up a framebuffer that has just been removed from a plane.
12508 intel_cleanup_plane_fb(struct drm_plane
*plane
,
12509 struct drm_framebuffer
*fb
,
12510 const struct drm_plane_state
*old_state
)
12512 struct drm_device
*dev
= plane
->dev
;
12513 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12518 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
12519 !INTEL_INFO(dev
)->cursor_needs_physical
) {
12520 mutex_lock(&dev
->struct_mutex
);
12521 intel_unpin_fb_obj(fb
, old_state
);
12522 mutex_unlock(&dev
->struct_mutex
);
12527 intel_check_primary_plane(struct drm_plane
*plane
,
12528 struct intel_plane_state
*state
)
12530 struct drm_device
*dev
= plane
->dev
;
12531 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12532 struct drm_crtc
*crtc
= state
->base
.crtc
;
12533 struct intel_crtc
*intel_crtc
;
12534 struct drm_framebuffer
*fb
= state
->base
.fb
;
12535 struct drm_rect
*dest
= &state
->dst
;
12536 struct drm_rect
*src
= &state
->src
;
12537 const struct drm_rect
*clip
= &state
->clip
;
12540 crtc
= crtc
? crtc
: plane
->crtc
;
12541 intel_crtc
= to_intel_crtc(crtc
);
12543 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12545 DRM_PLANE_HELPER_NO_SCALING
,
12546 DRM_PLANE_HELPER_NO_SCALING
,
12547 false, true, &state
->visible
);
12551 if (intel_crtc
->active
) {
12552 intel_crtc
->atomic
.wait_for_flips
= true;
12555 * FBC does not work on some platforms for rotated
12556 * planes, so disable it when rotation is not 0 and
12557 * update it when rotation is set back to 0.
12559 * FIXME: This is redundant with the fbc update done in
12560 * the primary plane enable function except that that
12561 * one is done too late. We eventually need to unify
12564 if (intel_crtc
->primary_enabled
&&
12565 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
12566 dev_priv
->fbc
.crtc
== intel_crtc
&&
12567 state
->base
.rotation
!= BIT(DRM_ROTATE_0
)) {
12568 intel_crtc
->atomic
.disable_fbc
= true;
12571 if (state
->visible
) {
12573 * BDW signals flip done immediately if the plane
12574 * is disabled, even if the plane enable is already
12575 * armed to occur at the next vblank :(
12577 if (IS_BROADWELL(dev
) && !intel_crtc
->primary_enabled
)
12578 intel_crtc
->atomic
.wait_vblank
= true;
12581 intel_crtc
->atomic
.fb_bits
|=
12582 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
12584 intel_crtc
->atomic
.update_fbc
= true;
12586 if (intel_wm_need_update(plane
, &state
->base
))
12587 intel_crtc
->atomic
.update_wm
= true;
12594 intel_commit_primary_plane(struct drm_plane
*plane
,
12595 struct intel_plane_state
*state
)
12597 struct drm_crtc
*crtc
= state
->base
.crtc
;
12598 struct drm_framebuffer
*fb
= state
->base
.fb
;
12599 struct drm_device
*dev
= plane
->dev
;
12600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12601 struct intel_crtc
*intel_crtc
;
12602 struct drm_rect
*src
= &state
->src
;
12604 crtc
= crtc
? crtc
: plane
->crtc
;
12605 intel_crtc
= to_intel_crtc(crtc
);
12608 crtc
->x
= src
->x1
>> 16;
12609 crtc
->y
= src
->y1
>> 16;
12611 if (intel_crtc
->active
) {
12612 if (state
->visible
) {
12613 /* FIXME: kill this fastboot hack */
12614 intel_update_pipe_size(intel_crtc
);
12616 intel_crtc
->primary_enabled
= true;
12618 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
12622 * If clipping results in a non-visible primary plane,
12623 * we'll disable the primary plane. Note that this is
12624 * a bit different than what happens if userspace
12625 * explicitly disables the plane by passing fb=0
12626 * because plane->fb still gets set and pinned.
12628 intel_disable_primary_hw_plane(plane
, crtc
);
12633 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
)
12635 struct drm_device
*dev
= crtc
->dev
;
12636 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12637 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12638 struct intel_plane
*intel_plane
;
12639 struct drm_plane
*p
;
12640 unsigned fb_bits
= 0;
12642 /* Track fb's for any planes being disabled */
12643 list_for_each_entry(p
, &dev
->mode_config
.plane_list
, head
) {
12644 intel_plane
= to_intel_plane(p
);
12646 if (intel_crtc
->atomic
.disabled_planes
&
12647 (1 << drm_plane_index(p
))) {
12649 case DRM_PLANE_TYPE_PRIMARY
:
12650 fb_bits
= INTEL_FRONTBUFFER_PRIMARY(intel_plane
->pipe
);
12652 case DRM_PLANE_TYPE_CURSOR
:
12653 fb_bits
= INTEL_FRONTBUFFER_CURSOR(intel_plane
->pipe
);
12655 case DRM_PLANE_TYPE_OVERLAY
:
12656 fb_bits
= INTEL_FRONTBUFFER_SPRITE(intel_plane
->pipe
);
12660 mutex_lock(&dev
->struct_mutex
);
12661 i915_gem_track_fb(intel_fb_obj(p
->fb
), NULL
, fb_bits
);
12662 mutex_unlock(&dev
->struct_mutex
);
12666 if (intel_crtc
->atomic
.wait_for_flips
)
12667 intel_crtc_wait_for_pending_flips(crtc
);
12669 if (intel_crtc
->atomic
.disable_fbc
)
12670 intel_fbc_disable(dev
);
12672 if (intel_crtc
->atomic
.pre_disable_primary
)
12673 intel_pre_disable_primary(crtc
);
12675 if (intel_crtc
->atomic
.update_wm
)
12676 intel_update_watermarks(crtc
);
12678 intel_runtime_pm_get(dev_priv
);
12680 /* Perform vblank evasion around commit operation */
12681 if (intel_crtc
->active
)
12682 intel_crtc
->atomic
.evade
=
12683 intel_pipe_update_start(intel_crtc
,
12684 &intel_crtc
->atomic
.start_vbl_count
);
12687 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
)
12689 struct drm_device
*dev
= crtc
->dev
;
12690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12691 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12692 struct drm_plane
*p
;
12694 if (intel_crtc
->atomic
.evade
)
12695 intel_pipe_update_end(intel_crtc
,
12696 intel_crtc
->atomic
.start_vbl_count
);
12698 intel_runtime_pm_put(dev_priv
);
12700 if (intel_crtc
->atomic
.wait_vblank
)
12701 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
12703 intel_frontbuffer_flip(dev
, intel_crtc
->atomic
.fb_bits
);
12705 if (intel_crtc
->atomic
.update_fbc
) {
12706 mutex_lock(&dev
->struct_mutex
);
12707 intel_fbc_update(dev
);
12708 mutex_unlock(&dev
->struct_mutex
);
12711 if (intel_crtc
->atomic
.post_enable_primary
)
12712 intel_post_enable_primary(crtc
);
12714 drm_for_each_legacy_plane(p
, &dev
->mode_config
.plane_list
)
12715 if (intel_crtc
->atomic
.update_sprite_watermarks
& drm_plane_index(p
))
12716 intel_update_sprite_watermarks(p
, crtc
, 0, 0, 0,
12719 memset(&intel_crtc
->atomic
, 0, sizeof(intel_crtc
->atomic
));
12723 * intel_plane_destroy - destroy a plane
12724 * @plane: plane to destroy
12726 * Common destruction function for all types of planes (primary, cursor,
12729 void intel_plane_destroy(struct drm_plane
*plane
)
12731 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
12732 drm_plane_cleanup(plane
);
12733 kfree(intel_plane
);
12736 const struct drm_plane_funcs intel_plane_funcs
= {
12737 .update_plane
= drm_plane_helper_update
,
12738 .disable_plane
= drm_plane_helper_disable
,
12739 .destroy
= intel_plane_destroy
,
12740 .set_property
= drm_atomic_helper_plane_set_property
,
12741 .atomic_get_property
= intel_plane_atomic_get_property
,
12742 .atomic_set_property
= intel_plane_atomic_set_property
,
12743 .atomic_duplicate_state
= intel_plane_duplicate_state
,
12744 .atomic_destroy_state
= intel_plane_destroy_state
,
12748 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
12751 struct intel_plane
*primary
;
12752 struct intel_plane_state
*state
;
12753 const uint32_t *intel_primary_formats
;
12756 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
12757 if (primary
== NULL
)
12760 state
= intel_create_plane_state(&primary
->base
);
12765 primary
->base
.state
= &state
->base
;
12767 primary
->can_scale
= false;
12768 primary
->max_downscale
= 1;
12769 primary
->pipe
= pipe
;
12770 primary
->plane
= pipe
;
12771 primary
->check_plane
= intel_check_primary_plane
;
12772 primary
->commit_plane
= intel_commit_primary_plane
;
12773 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
12774 primary
->plane
= !pipe
;
12776 if (INTEL_INFO(dev
)->gen
<= 3) {
12777 intel_primary_formats
= intel_primary_formats_gen2
;
12778 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
12780 intel_primary_formats
= intel_primary_formats_gen4
;
12781 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
12784 drm_universal_plane_init(dev
, &primary
->base
, 0,
12785 &intel_plane_funcs
,
12786 intel_primary_formats
, num_formats
,
12787 DRM_PLANE_TYPE_PRIMARY
);
12789 if (INTEL_INFO(dev
)->gen
>= 4) {
12790 if (!dev
->mode_config
.rotation_property
)
12791 dev
->mode_config
.rotation_property
=
12792 drm_mode_create_rotation_property(dev
,
12793 BIT(DRM_ROTATE_0
) |
12794 BIT(DRM_ROTATE_180
));
12795 if (dev
->mode_config
.rotation_property
)
12796 drm_object_attach_property(&primary
->base
.base
,
12797 dev
->mode_config
.rotation_property
,
12798 state
->base
.rotation
);
12801 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
12803 return &primary
->base
;
12807 intel_check_cursor_plane(struct drm_plane
*plane
,
12808 struct intel_plane_state
*state
)
12810 struct drm_crtc
*crtc
= state
->base
.crtc
;
12811 struct drm_device
*dev
= plane
->dev
;
12812 struct drm_framebuffer
*fb
= state
->base
.fb
;
12813 struct drm_rect
*dest
= &state
->dst
;
12814 struct drm_rect
*src
= &state
->src
;
12815 const struct drm_rect
*clip
= &state
->clip
;
12816 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
12817 struct intel_crtc
*intel_crtc
;
12821 crtc
= crtc
? crtc
: plane
->crtc
;
12822 intel_crtc
= to_intel_crtc(crtc
);
12824 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
12826 DRM_PLANE_HELPER_NO_SCALING
,
12827 DRM_PLANE_HELPER_NO_SCALING
,
12828 true, true, &state
->visible
);
12833 /* if we want to turn off the cursor ignore width and height */
12837 /* Check for which cursor types we support */
12838 if (!cursor_size_ok(dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
12839 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12840 state
->base
.crtc_w
, state
->base
.crtc_h
);
12844 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
12845 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
12846 DRM_DEBUG_KMS("buffer is too small\n");
12850 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
12851 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12856 if (intel_crtc
->active
) {
12857 if (plane
->state
->crtc_w
!= state
->base
.crtc_w
)
12858 intel_crtc
->atomic
.update_wm
= true;
12860 intel_crtc
->atomic
.fb_bits
|=
12861 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
);
12868 intel_commit_cursor_plane(struct drm_plane
*plane
,
12869 struct intel_plane_state
*state
)
12871 struct drm_crtc
*crtc
= state
->base
.crtc
;
12872 struct drm_device
*dev
= plane
->dev
;
12873 struct intel_crtc
*intel_crtc
;
12874 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
12877 crtc
= crtc
? crtc
: plane
->crtc
;
12878 intel_crtc
= to_intel_crtc(crtc
);
12880 plane
->fb
= state
->base
.fb
;
12881 crtc
->cursor_x
= state
->base
.crtc_x
;
12882 crtc
->cursor_y
= state
->base
.crtc_y
;
12884 if (intel_crtc
->cursor_bo
== obj
)
12889 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
12890 addr
= i915_gem_obj_ggtt_offset(obj
);
12892 addr
= obj
->phys_handle
->busaddr
;
12894 intel_crtc
->cursor_addr
= addr
;
12895 intel_crtc
->cursor_bo
= obj
;
12898 if (intel_crtc
->active
)
12899 intel_crtc_update_cursor(crtc
, state
->visible
);
12902 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
12905 struct intel_plane
*cursor
;
12906 struct intel_plane_state
*state
;
12908 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
12909 if (cursor
== NULL
)
12912 state
= intel_create_plane_state(&cursor
->base
);
12917 cursor
->base
.state
= &state
->base
;
12919 cursor
->can_scale
= false;
12920 cursor
->max_downscale
= 1;
12921 cursor
->pipe
= pipe
;
12922 cursor
->plane
= pipe
;
12923 cursor
->check_plane
= intel_check_cursor_plane
;
12924 cursor
->commit_plane
= intel_commit_cursor_plane
;
12926 drm_universal_plane_init(dev
, &cursor
->base
, 0,
12927 &intel_plane_funcs
,
12928 intel_cursor_formats
,
12929 ARRAY_SIZE(intel_cursor_formats
),
12930 DRM_PLANE_TYPE_CURSOR
);
12932 if (INTEL_INFO(dev
)->gen
>= 4) {
12933 if (!dev
->mode_config
.rotation_property
)
12934 dev
->mode_config
.rotation_property
=
12935 drm_mode_create_rotation_property(dev
,
12936 BIT(DRM_ROTATE_0
) |
12937 BIT(DRM_ROTATE_180
));
12938 if (dev
->mode_config
.rotation_property
)
12939 drm_object_attach_property(&cursor
->base
.base
,
12940 dev
->mode_config
.rotation_property
,
12941 state
->base
.rotation
);
12944 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
12946 return &cursor
->base
;
12949 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
12951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12952 struct intel_crtc
*intel_crtc
;
12953 struct intel_crtc_state
*crtc_state
= NULL
;
12954 struct drm_plane
*primary
= NULL
;
12955 struct drm_plane
*cursor
= NULL
;
12958 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
12959 if (intel_crtc
== NULL
)
12962 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
12965 intel_crtc_set_state(intel_crtc
, crtc_state
);
12966 crtc_state
->base
.crtc
= &intel_crtc
->base
;
12968 primary
= intel_primary_plane_create(dev
, pipe
);
12972 cursor
= intel_cursor_plane_create(dev
, pipe
);
12976 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
12977 cursor
, &intel_crtc_funcs
);
12981 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
12982 for (i
= 0; i
< 256; i
++) {
12983 intel_crtc
->lut_r
[i
] = i
;
12984 intel_crtc
->lut_g
[i
] = i
;
12985 intel_crtc
->lut_b
[i
] = i
;
12989 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12990 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12992 intel_crtc
->pipe
= pipe
;
12993 intel_crtc
->plane
= pipe
;
12994 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
12995 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12996 intel_crtc
->plane
= !pipe
;
12999 intel_crtc
->cursor_base
= ~0;
13000 intel_crtc
->cursor_cntl
= ~0;
13001 intel_crtc
->cursor_size
= ~0;
13003 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13004 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13005 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13006 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13008 INIT_WORK(&intel_crtc
->mmio_flip
.work
, intel_mmio_flip_work_func
);
13010 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13012 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13017 drm_plane_cleanup(primary
);
13019 drm_plane_cleanup(cursor
);
13024 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13026 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13027 struct drm_device
*dev
= connector
->base
.dev
;
13029 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13031 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13032 return INVALID_PIPE
;
13034 return to_intel_crtc(encoder
->crtc
)->pipe
;
13037 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13038 struct drm_file
*file
)
13040 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13041 struct drm_crtc
*drmmode_crtc
;
13042 struct intel_crtc
*crtc
;
13044 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13046 if (!drmmode_crtc
) {
13047 DRM_ERROR("no such CRTC id\n");
13051 crtc
= to_intel_crtc(drmmode_crtc
);
13052 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13057 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13059 struct drm_device
*dev
= encoder
->base
.dev
;
13060 struct intel_encoder
*source_encoder
;
13061 int index_mask
= 0;
13064 for_each_intel_encoder(dev
, source_encoder
) {
13065 if (encoders_cloneable(encoder
, source_encoder
))
13066 index_mask
|= (1 << entry
);
13074 static bool has_edp_a(struct drm_device
*dev
)
13076 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13078 if (!IS_MOBILE(dev
))
13081 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
13084 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
13090 static bool intel_crt_present(struct drm_device
*dev
)
13092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13094 if (INTEL_INFO(dev
)->gen
>= 9)
13097 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
13100 if (IS_CHERRYVIEW(dev
))
13103 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
13109 static void intel_setup_outputs(struct drm_device
*dev
)
13111 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13112 struct intel_encoder
*encoder
;
13113 struct drm_connector
*connector
;
13114 bool dpd_is_edp
= false;
13116 intel_lvds_init(dev
);
13118 if (intel_crt_present(dev
))
13119 intel_crt_init(dev
);
13121 if (HAS_DDI(dev
)) {
13125 * Haswell uses DDI functions to detect digital outputs.
13126 * On SKL pre-D0 the strap isn't connected, so we assume
13129 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
13130 /* WaIgnoreDDIAStrap: skl */
13132 (IS_SKYLAKE(dev
) && INTEL_REVID(dev
) < SKL_REVID_D0
))
13133 intel_ddi_init(dev
, PORT_A
);
13135 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13137 found
= I915_READ(SFUSE_STRAP
);
13139 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
13140 intel_ddi_init(dev
, PORT_B
);
13141 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
13142 intel_ddi_init(dev
, PORT_C
);
13143 if (found
& SFUSE_STRAP_DDID_DETECTED
)
13144 intel_ddi_init(dev
, PORT_D
);
13145 } else if (HAS_PCH_SPLIT(dev
)) {
13147 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
13149 if (has_edp_a(dev
))
13150 intel_dp_init(dev
, DP_A
, PORT_A
);
13152 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
13153 /* PCH SDVOB multiplex with HDMIB */
13154 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
13156 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
13157 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
13158 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
13161 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
13162 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
13164 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
13165 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
13167 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
13168 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
13170 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
13171 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
13172 } else if (IS_VALLEYVIEW(dev
)) {
13174 * The DP_DETECTED bit is the latched state of the DDC
13175 * SDA pin at boot. However since eDP doesn't require DDC
13176 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13177 * eDP ports may have been muxed to an alternate function.
13178 * Thus we can't rely on the DP_DETECTED bit alone to detect
13179 * eDP ports. Consult the VBT as well as DP_DETECTED to
13180 * detect eDP ports.
13182 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
&&
13183 !intel_dp_is_edp(dev
, PORT_B
))
13184 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
13186 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
||
13187 intel_dp_is_edp(dev
, PORT_B
))
13188 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
13190 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
&&
13191 !intel_dp_is_edp(dev
, PORT_C
))
13192 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
13194 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
||
13195 intel_dp_is_edp(dev
, PORT_C
))
13196 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
13198 if (IS_CHERRYVIEW(dev
)) {
13199 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
)
13200 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
13202 /* eDP not supported on port D, so don't check VBT */
13203 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
13204 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
13207 intel_dsi_init(dev
);
13208 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
13209 bool found
= false;
13211 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13212 DRM_DEBUG_KMS("probing SDVOB\n");
13213 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
13214 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
13215 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13216 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
13219 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
13220 intel_dp_init(dev
, DP_B
, PORT_B
);
13223 /* Before G4X SDVOC doesn't have its own detect register */
13225 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
13226 DRM_DEBUG_KMS("probing SDVOC\n");
13227 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
13230 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
13232 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
13233 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13234 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
13236 if (SUPPORTS_INTEGRATED_DP(dev
))
13237 intel_dp_init(dev
, DP_C
, PORT_C
);
13240 if (SUPPORTS_INTEGRATED_DP(dev
) &&
13241 (I915_READ(DP_D
) & DP_DETECTED
))
13242 intel_dp_init(dev
, DP_D
, PORT_D
);
13243 } else if (IS_GEN2(dev
))
13244 intel_dvo_init(dev
);
13246 if (SUPPORTS_TV(dev
))
13247 intel_tv_init(dev
);
13250 * FIXME: We don't have full atomic support yet, but we want to be
13251 * able to enable/test plane updates via the atomic interface in the
13252 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
13253 * will take some atomic codepaths to lookup properties during
13254 * drmModeGetConnector() that unconditionally dereference
13255 * connector->state.
13257 * We create a dummy connector state here for each connector to ensure
13258 * the DRM core doesn't try to dereference a NULL connector->state.
13259 * The actual connector properties will never be updated or contain
13260 * useful information, but since we're doing this specifically for
13261 * testing/debug of the plane operations (and only when a specific
13262 * kernel module option is given), that shouldn't really matter.
13264 * We are also relying on these states to convert the legacy mode set
13265 * to use a drm_atomic_state struct. The states are kept consistent
13266 * with actual state, so that it is safe to rely on that instead of
13267 * the staged config.
13269 * Once atomic support for crtc's + connectors lands, this loop should
13270 * be removed since we'll be setting up real connector state, which
13271 * will contain Intel-specific properties.
13273 list_for_each_entry(connector
,
13274 &dev
->mode_config
.connector_list
,
13276 if (!WARN_ON(connector
->state
)) {
13277 connector
->state
= kzalloc(sizeof(*connector
->state
),
13282 intel_psr_init(dev
);
13284 for_each_intel_encoder(dev
, encoder
) {
13285 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
13286 encoder
->base
.possible_clones
=
13287 intel_encoder_clones(encoder
);
13290 intel_init_pch_refclk(dev
);
13292 drm_helper_move_panel_connectors_to_head(dev
);
13295 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
13297 struct drm_device
*dev
= fb
->dev
;
13298 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13300 drm_framebuffer_cleanup(fb
);
13301 mutex_lock(&dev
->struct_mutex
);
13302 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
13303 drm_gem_object_unreference(&intel_fb
->obj
->base
);
13304 mutex_unlock(&dev
->struct_mutex
);
13308 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
13309 struct drm_file
*file
,
13310 unsigned int *handle
)
13312 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
13313 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
13315 return drm_gem_handle_create(file
, &obj
->base
, handle
);
13318 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
13319 .destroy
= intel_user_framebuffer_destroy
,
13320 .create_handle
= intel_user_framebuffer_create_handle
,
13324 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
13325 uint32_t pixel_format
)
13327 u32 gen
= INTEL_INFO(dev
)->gen
;
13330 /* "The stride in bytes must not exceed the of the size of 8K
13331 * pixels and 32K bytes."
13333 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
13334 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
13336 } else if (gen
>= 4) {
13337 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13341 } else if (gen
>= 3) {
13342 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
13347 /* XXX DSPC is limited to 4k tiled */
13352 static int intel_framebuffer_init(struct drm_device
*dev
,
13353 struct intel_framebuffer
*intel_fb
,
13354 struct drm_mode_fb_cmd2
*mode_cmd
,
13355 struct drm_i915_gem_object
*obj
)
13357 unsigned int aligned_height
;
13359 u32 pitch_limit
, stride_alignment
;
13361 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
13363 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
13364 /* Enforce that fb modifier and tiling mode match, but only for
13365 * X-tiled. This is needed for FBC. */
13366 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
13367 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
13368 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13372 if (obj
->tiling_mode
== I915_TILING_X
)
13373 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
13374 else if (obj
->tiling_mode
== I915_TILING_Y
) {
13375 DRM_DEBUG("No Y tiling for legacy addfb\n");
13380 /* Passed in modifier sanity checking. */
13381 switch (mode_cmd
->modifier
[0]) {
13382 case I915_FORMAT_MOD_Y_TILED
:
13383 case I915_FORMAT_MOD_Yf_TILED
:
13384 if (INTEL_INFO(dev
)->gen
< 9) {
13385 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13386 mode_cmd
->modifier
[0]);
13389 case DRM_FORMAT_MOD_NONE
:
13390 case I915_FORMAT_MOD_X_TILED
:
13393 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13394 mode_cmd
->modifier
[0]);
13398 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
13399 mode_cmd
->pixel_format
);
13400 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
13401 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13402 mode_cmd
->pitches
[0], stride_alignment
);
13406 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
13407 mode_cmd
->pixel_format
);
13408 if (mode_cmd
->pitches
[0] > pitch_limit
) {
13409 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13410 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
13411 "tiled" : "linear",
13412 mode_cmd
->pitches
[0], pitch_limit
);
13416 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
13417 mode_cmd
->pitches
[0] != obj
->stride
) {
13418 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13419 mode_cmd
->pitches
[0], obj
->stride
);
13423 /* Reject formats not supported by any plane early. */
13424 switch (mode_cmd
->pixel_format
) {
13425 case DRM_FORMAT_C8
:
13426 case DRM_FORMAT_RGB565
:
13427 case DRM_FORMAT_XRGB8888
:
13428 case DRM_FORMAT_ARGB8888
:
13430 case DRM_FORMAT_XRGB1555
:
13431 case DRM_FORMAT_ARGB1555
:
13432 if (INTEL_INFO(dev
)->gen
> 3) {
13433 DRM_DEBUG("unsupported pixel format: %s\n",
13434 drm_get_format_name(mode_cmd
->pixel_format
));
13438 case DRM_FORMAT_XBGR8888
:
13439 case DRM_FORMAT_ABGR8888
:
13440 case DRM_FORMAT_XRGB2101010
:
13441 case DRM_FORMAT_ARGB2101010
:
13442 case DRM_FORMAT_XBGR2101010
:
13443 case DRM_FORMAT_ABGR2101010
:
13444 if (INTEL_INFO(dev
)->gen
< 4) {
13445 DRM_DEBUG("unsupported pixel format: %s\n",
13446 drm_get_format_name(mode_cmd
->pixel_format
));
13450 case DRM_FORMAT_YUYV
:
13451 case DRM_FORMAT_UYVY
:
13452 case DRM_FORMAT_YVYU
:
13453 case DRM_FORMAT_VYUY
:
13454 if (INTEL_INFO(dev
)->gen
< 5) {
13455 DRM_DEBUG("unsupported pixel format: %s\n",
13456 drm_get_format_name(mode_cmd
->pixel_format
));
13461 DRM_DEBUG("unsupported pixel format: %s\n",
13462 drm_get_format_name(mode_cmd
->pixel_format
));
13466 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13467 if (mode_cmd
->offsets
[0] != 0)
13470 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
13471 mode_cmd
->pixel_format
,
13472 mode_cmd
->modifier
[0]);
13473 /* FIXME drm helper for size checks (especially planar formats)? */
13474 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
13477 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
13478 intel_fb
->obj
= obj
;
13479 intel_fb
->obj
->framebuffer_references
++;
13481 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
13483 DRM_ERROR("framebuffer init failed %d\n", ret
);
13490 static struct drm_framebuffer
*
13491 intel_user_framebuffer_create(struct drm_device
*dev
,
13492 struct drm_file
*filp
,
13493 struct drm_mode_fb_cmd2
*mode_cmd
)
13495 struct drm_i915_gem_object
*obj
;
13497 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
13498 mode_cmd
->handles
[0]));
13499 if (&obj
->base
== NULL
)
13500 return ERR_PTR(-ENOENT
);
13502 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
13505 #ifndef CONFIG_DRM_I915_FBDEV
13506 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
13511 static const struct drm_mode_config_funcs intel_mode_funcs
= {
13512 .fb_create
= intel_user_framebuffer_create
,
13513 .output_poll_changed
= intel_fbdev_output_poll_changed
,
13514 .atomic_check
= intel_atomic_check
,
13515 .atomic_commit
= intel_atomic_commit
,
13518 /* Set up chip specific display functions */
13519 static void intel_init_display(struct drm_device
*dev
)
13521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13523 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
13524 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
13525 else if (IS_CHERRYVIEW(dev
))
13526 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
13527 else if (IS_VALLEYVIEW(dev
))
13528 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
13529 else if (IS_PINEVIEW(dev
))
13530 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
13532 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
13534 if (INTEL_INFO(dev
)->gen
>= 9) {
13535 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
13536 dev_priv
->display
.get_initial_plane_config
=
13537 skylake_get_initial_plane_config
;
13538 dev_priv
->display
.crtc_compute_clock
=
13539 haswell_crtc_compute_clock
;
13540 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
13541 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
13542 dev_priv
->display
.off
= ironlake_crtc_off
;
13543 dev_priv
->display
.update_primary_plane
=
13544 skylake_update_primary_plane
;
13545 } else if (HAS_DDI(dev
)) {
13546 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
13547 dev_priv
->display
.get_initial_plane_config
=
13548 ironlake_get_initial_plane_config
;
13549 dev_priv
->display
.crtc_compute_clock
=
13550 haswell_crtc_compute_clock
;
13551 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
13552 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
13553 dev_priv
->display
.off
= ironlake_crtc_off
;
13554 dev_priv
->display
.update_primary_plane
=
13555 ironlake_update_primary_plane
;
13556 } else if (HAS_PCH_SPLIT(dev
)) {
13557 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
13558 dev_priv
->display
.get_initial_plane_config
=
13559 ironlake_get_initial_plane_config
;
13560 dev_priv
->display
.crtc_compute_clock
=
13561 ironlake_crtc_compute_clock
;
13562 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
13563 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
13564 dev_priv
->display
.off
= ironlake_crtc_off
;
13565 dev_priv
->display
.update_primary_plane
=
13566 ironlake_update_primary_plane
;
13567 } else if (IS_VALLEYVIEW(dev
)) {
13568 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
13569 dev_priv
->display
.get_initial_plane_config
=
13570 i9xx_get_initial_plane_config
;
13571 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
13572 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
13573 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
13574 dev_priv
->display
.off
= i9xx_crtc_off
;
13575 dev_priv
->display
.update_primary_plane
=
13576 i9xx_update_primary_plane
;
13578 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
13579 dev_priv
->display
.get_initial_plane_config
=
13580 i9xx_get_initial_plane_config
;
13581 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
13582 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
13583 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
13584 dev_priv
->display
.off
= i9xx_crtc_off
;
13585 dev_priv
->display
.update_primary_plane
=
13586 i9xx_update_primary_plane
;
13589 /* Returns the core display clock speed */
13590 if (IS_SKYLAKE(dev
))
13591 dev_priv
->display
.get_display_clock_speed
=
13592 skylake_get_display_clock_speed
;
13593 else if (IS_BROADWELL(dev
))
13594 dev_priv
->display
.get_display_clock_speed
=
13595 broadwell_get_display_clock_speed
;
13596 else if (IS_HASWELL(dev
))
13597 dev_priv
->display
.get_display_clock_speed
=
13598 haswell_get_display_clock_speed
;
13599 else if (IS_VALLEYVIEW(dev
))
13600 dev_priv
->display
.get_display_clock_speed
=
13601 valleyview_get_display_clock_speed
;
13602 else if (IS_GEN5(dev
))
13603 dev_priv
->display
.get_display_clock_speed
=
13604 ilk_get_display_clock_speed
;
13605 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
13606 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
13607 dev_priv
->display
.get_display_clock_speed
=
13608 i945_get_display_clock_speed
;
13609 else if (IS_I915G(dev
))
13610 dev_priv
->display
.get_display_clock_speed
=
13611 i915_get_display_clock_speed
;
13612 else if (IS_I945GM(dev
) || IS_845G(dev
))
13613 dev_priv
->display
.get_display_clock_speed
=
13614 i9xx_misc_get_display_clock_speed
;
13615 else if (IS_PINEVIEW(dev
))
13616 dev_priv
->display
.get_display_clock_speed
=
13617 pnv_get_display_clock_speed
;
13618 else if (IS_I915GM(dev
))
13619 dev_priv
->display
.get_display_clock_speed
=
13620 i915gm_get_display_clock_speed
;
13621 else if (IS_I865G(dev
))
13622 dev_priv
->display
.get_display_clock_speed
=
13623 i865_get_display_clock_speed
;
13624 else if (IS_I85X(dev
))
13625 dev_priv
->display
.get_display_clock_speed
=
13626 i855_get_display_clock_speed
;
13627 else /* 852, 830 */
13628 dev_priv
->display
.get_display_clock_speed
=
13629 i830_get_display_clock_speed
;
13631 if (IS_GEN5(dev
)) {
13632 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
13633 } else if (IS_GEN6(dev
)) {
13634 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
13635 } else if (IS_IVYBRIDGE(dev
)) {
13636 /* FIXME: detect B0+ stepping and use auto training */
13637 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
13638 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
13639 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
13640 } else if (IS_VALLEYVIEW(dev
)) {
13641 dev_priv
->display
.modeset_global_resources
=
13642 valleyview_modeset_global_resources
;
13645 switch (INTEL_INFO(dev
)->gen
) {
13647 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
13651 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
13656 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
13660 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
13663 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13664 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
13667 /* Drop through - unsupported since execlist only. */
13669 /* Default just returns -ENODEV to indicate unsupported */
13670 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
13673 intel_panel_init_backlight_funcs(dev
);
13675 mutex_init(&dev_priv
->pps_mutex
);
13679 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13680 * resume, or other times. This quirk makes sure that's the case for
13681 * affected systems.
13683 static void quirk_pipea_force(struct drm_device
*dev
)
13685 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13687 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
13688 DRM_INFO("applying pipe a force quirk\n");
13691 static void quirk_pipeb_force(struct drm_device
*dev
)
13693 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13695 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
13696 DRM_INFO("applying pipe b force quirk\n");
13700 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13702 static void quirk_ssc_force_disable(struct drm_device
*dev
)
13704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13705 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
13706 DRM_INFO("applying lvds SSC disable quirk\n");
13710 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13713 static void quirk_invert_brightness(struct drm_device
*dev
)
13715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13716 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
13717 DRM_INFO("applying inverted panel brightness quirk\n");
13720 /* Some VBT's incorrectly indicate no backlight is present */
13721 static void quirk_backlight_present(struct drm_device
*dev
)
13723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13724 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
13725 DRM_INFO("applying backlight present quirk\n");
13728 struct intel_quirk
{
13730 int subsystem_vendor
;
13731 int subsystem_device
;
13732 void (*hook
)(struct drm_device
*dev
);
13735 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13736 struct intel_dmi_quirk
{
13737 void (*hook
)(struct drm_device
*dev
);
13738 const struct dmi_system_id (*dmi_id_list
)[];
13741 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
13743 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
13747 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
13749 .dmi_id_list
= &(const struct dmi_system_id
[]) {
13751 .callback
= intel_dmi_reverse_brightness
,
13752 .ident
= "NCR Corporation",
13753 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
13754 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
13757 { } /* terminating entry */
13759 .hook
= quirk_invert_brightness
,
13763 static struct intel_quirk intel_quirks
[] = {
13764 /* HP Mini needs pipe A force quirk (LP: #322104) */
13765 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
13767 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13768 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
13770 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13771 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
13773 /* 830 needs to leave pipe A & dpll A up */
13774 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
13776 /* 830 needs to leave pipe B & dpll B up */
13777 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
13779 /* Lenovo U160 cannot use SSC on LVDS */
13780 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
13782 /* Sony Vaio Y cannot use SSC on LVDS */
13783 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
13785 /* Acer Aspire 5734Z must invert backlight brightness */
13786 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
13788 /* Acer/eMachines G725 */
13789 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
13791 /* Acer/eMachines e725 */
13792 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
13794 /* Acer/Packard Bell NCL20 */
13795 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
13797 /* Acer Aspire 4736Z */
13798 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
13800 /* Acer Aspire 5336 */
13801 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
13803 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13804 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
13806 /* Acer C720 Chromebook (Core i3 4005U) */
13807 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
13809 /* Apple Macbook 2,1 (Core 2 T7400) */
13810 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
13812 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13813 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
13815 /* HP Chromebook 14 (Celeron 2955U) */
13816 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
13818 /* Dell Chromebook 11 */
13819 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
13822 static void intel_init_quirks(struct drm_device
*dev
)
13824 struct pci_dev
*d
= dev
->pdev
;
13827 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
13828 struct intel_quirk
*q
= &intel_quirks
[i
];
13830 if (d
->device
== q
->device
&&
13831 (d
->subsystem_vendor
== q
->subsystem_vendor
||
13832 q
->subsystem_vendor
== PCI_ANY_ID
) &&
13833 (d
->subsystem_device
== q
->subsystem_device
||
13834 q
->subsystem_device
== PCI_ANY_ID
))
13837 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
13838 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
13839 intel_dmi_quirks
[i
].hook(dev
);
13843 /* Disable the VGA plane that we never use */
13844 static void i915_disable_vga(struct drm_device
*dev
)
13846 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13848 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13850 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13851 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13852 outb(SR01
, VGA_SR_INDEX
);
13853 sr1
= inb(VGA_SR_DATA
);
13854 outb(sr1
| 1<<5, VGA_SR_DATA
);
13855 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
13858 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
13859 POSTING_READ(vga_reg
);
13862 void intel_modeset_init_hw(struct drm_device
*dev
)
13864 intel_prepare_ddi(dev
);
13866 if (IS_VALLEYVIEW(dev
))
13867 vlv_update_cdclk(dev
);
13869 intel_init_clock_gating(dev
);
13871 intel_enable_gt_powersave(dev
);
13874 void intel_modeset_init(struct drm_device
*dev
)
13876 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13879 struct intel_crtc
*crtc
;
13881 drm_mode_config_init(dev
);
13883 dev
->mode_config
.min_width
= 0;
13884 dev
->mode_config
.min_height
= 0;
13886 dev
->mode_config
.preferred_depth
= 24;
13887 dev
->mode_config
.prefer_shadow
= 1;
13889 dev
->mode_config
.allow_fb_modifiers
= true;
13891 dev
->mode_config
.funcs
= &intel_mode_funcs
;
13893 intel_init_quirks(dev
);
13895 intel_init_pm(dev
);
13897 if (INTEL_INFO(dev
)->num_pipes
== 0)
13900 intel_init_display(dev
);
13901 intel_init_audio(dev
);
13903 if (IS_GEN2(dev
)) {
13904 dev
->mode_config
.max_width
= 2048;
13905 dev
->mode_config
.max_height
= 2048;
13906 } else if (IS_GEN3(dev
)) {
13907 dev
->mode_config
.max_width
= 4096;
13908 dev
->mode_config
.max_height
= 4096;
13910 dev
->mode_config
.max_width
= 8192;
13911 dev
->mode_config
.max_height
= 8192;
13914 if (IS_845G(dev
) || IS_I865G(dev
)) {
13915 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
13916 dev
->mode_config
.cursor_height
= 1023;
13917 } else if (IS_GEN2(dev
)) {
13918 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
13919 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
13921 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
13922 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
13925 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
13927 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13928 INTEL_INFO(dev
)->num_pipes
,
13929 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
13931 for_each_pipe(dev_priv
, pipe
) {
13932 intel_crtc_init(dev
, pipe
);
13933 for_each_sprite(dev_priv
, pipe
, sprite
) {
13934 ret
= intel_plane_init(dev
, pipe
, sprite
);
13936 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13937 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
13941 intel_init_dpio(dev
);
13943 intel_shared_dpll_init(dev
);
13945 /* Just disable it once at startup */
13946 i915_disable_vga(dev
);
13947 intel_setup_outputs(dev
);
13949 /* Just in case the BIOS is doing something questionable. */
13950 intel_fbc_disable(dev
);
13952 drm_modeset_lock_all(dev
);
13953 intel_modeset_setup_hw_state(dev
, false);
13954 drm_modeset_unlock_all(dev
);
13956 for_each_intel_crtc(dev
, crtc
) {
13961 * Note that reserving the BIOS fb up front prevents us
13962 * from stuffing other stolen allocations like the ring
13963 * on top. This prevents some ugliness at boot time, and
13964 * can even allow for smooth boot transitions if the BIOS
13965 * fb is large enough for the active pipe configuration.
13967 if (dev_priv
->display
.get_initial_plane_config
) {
13968 dev_priv
->display
.get_initial_plane_config(crtc
,
13969 &crtc
->plane_config
);
13971 * If the fb is shared between multiple heads, we'll
13972 * just get the first one.
13974 intel_find_initial_plane_obj(crtc
, &crtc
->plane_config
);
13979 static void intel_enable_pipe_a(struct drm_device
*dev
)
13981 struct intel_connector
*connector
;
13982 struct drm_connector
*crt
= NULL
;
13983 struct intel_load_detect_pipe load_detect_temp
;
13984 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
13986 /* We can't just switch on the pipe A, we need to set things up with a
13987 * proper mode and output configuration. As a gross hack, enable pipe A
13988 * by enabling the load detect pipe once. */
13989 for_each_intel_connector(dev
, connector
) {
13990 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
13991 crt
= &connector
->base
;
13999 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14000 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14004 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14006 struct drm_device
*dev
= crtc
->base
.dev
;
14007 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14010 if (INTEL_INFO(dev
)->num_pipes
== 1)
14013 reg
= DSPCNTR(!crtc
->plane
);
14014 val
= I915_READ(reg
);
14016 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14017 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
14023 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
14025 struct drm_device
*dev
= crtc
->base
.dev
;
14026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14029 /* Clear any frame start delays used for debugging left by the BIOS */
14030 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
14031 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
14033 /* restore vblank interrupts to correct state */
14034 drm_crtc_vblank_reset(&crtc
->base
);
14035 if (crtc
->active
) {
14036 update_scanline_offset(crtc
);
14037 drm_crtc_vblank_on(&crtc
->base
);
14040 /* We need to sanitize the plane -> pipe mapping first because this will
14041 * disable the crtc (and hence change the state) if it is wrong. Note
14042 * that gen4+ has a fixed plane -> pipe mapping. */
14043 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
14044 struct intel_connector
*connector
;
14047 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14048 crtc
->base
.base
.id
);
14050 /* Pipe has the wrong plane attached and the plane is active.
14051 * Temporarily change the plane mapping and disable everything
14053 plane
= crtc
->plane
;
14054 crtc
->plane
= !plane
;
14055 crtc
->primary_enabled
= true;
14056 dev_priv
->display
.crtc_disable(&crtc
->base
);
14057 crtc
->plane
= plane
;
14059 /* ... and break all links. */
14060 for_each_intel_connector(dev
, connector
) {
14061 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
14064 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14065 connector
->base
.encoder
= NULL
;
14067 /* multiple connectors may have the same encoder:
14068 * handle them and break crtc link separately */
14069 for_each_intel_connector(dev
, connector
)
14070 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
14071 connector
->encoder
->base
.crtc
= NULL
;
14072 connector
->encoder
->connectors_active
= false;
14075 WARN_ON(crtc
->active
);
14076 crtc
->base
.state
->enable
= false;
14077 crtc
->base
.enabled
= false;
14080 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
14081 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
14082 /* BIOS forgot to enable pipe A, this mostly happens after
14083 * resume. Force-enable the pipe to fix this, the update_dpms
14084 * call below we restore the pipe to the right state, but leave
14085 * the required bits on. */
14086 intel_enable_pipe_a(dev
);
14089 /* Adjust the state of the output pipe according to whether we
14090 * have active connectors/encoders. */
14091 intel_crtc_update_dpms(&crtc
->base
);
14093 if (crtc
->active
!= crtc
->base
.state
->enable
) {
14094 struct intel_encoder
*encoder
;
14096 /* This can happen either due to bugs in the get_hw_state
14097 * functions or because the pipe is force-enabled due to the
14099 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14100 crtc
->base
.base
.id
,
14101 crtc
->base
.state
->enable
? "enabled" : "disabled",
14102 crtc
->active
? "enabled" : "disabled");
14104 crtc
->base
.state
->enable
= crtc
->active
;
14105 crtc
->base
.enabled
= crtc
->active
;
14107 /* Because we only establish the connector -> encoder ->
14108 * crtc links if something is active, this means the
14109 * crtc is now deactivated. Break the links. connector
14110 * -> encoder links are only establish when things are
14111 * actually up, hence no need to break them. */
14112 WARN_ON(crtc
->active
);
14114 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
14115 WARN_ON(encoder
->connectors_active
);
14116 encoder
->base
.crtc
= NULL
;
14120 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
14122 * We start out with underrun reporting disabled to avoid races.
14123 * For correct bookkeeping mark this on active crtcs.
14125 * Also on gmch platforms we dont have any hardware bits to
14126 * disable the underrun reporting. Which means we need to start
14127 * out with underrun reporting disabled also on inactive pipes,
14128 * since otherwise we'll complain about the garbage we read when
14129 * e.g. coming up after runtime pm.
14131 * No protection against concurrent access is required - at
14132 * worst a fifo underrun happens which also sets this to false.
14134 crtc
->cpu_fifo_underrun_disabled
= true;
14135 crtc
->pch_fifo_underrun_disabled
= true;
14139 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
14141 struct intel_connector
*connector
;
14142 struct drm_device
*dev
= encoder
->base
.dev
;
14144 /* We need to check both for a crtc link (meaning that the
14145 * encoder is active and trying to read from a pipe) and the
14146 * pipe itself being active. */
14147 bool has_active_crtc
= encoder
->base
.crtc
&&
14148 to_intel_crtc(encoder
->base
.crtc
)->active
;
14150 if (encoder
->connectors_active
&& !has_active_crtc
) {
14151 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14152 encoder
->base
.base
.id
,
14153 encoder
->base
.name
);
14155 /* Connector is active, but has no active pipe. This is
14156 * fallout from our resume register restoring. Disable
14157 * the encoder manually again. */
14158 if (encoder
->base
.crtc
) {
14159 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14160 encoder
->base
.base
.id
,
14161 encoder
->base
.name
);
14162 encoder
->disable(encoder
);
14163 if (encoder
->post_disable
)
14164 encoder
->post_disable(encoder
);
14166 encoder
->base
.crtc
= NULL
;
14167 encoder
->connectors_active
= false;
14169 /* Inconsistent output/port/pipe state happens presumably due to
14170 * a bug in one of the get_hw_state functions. Or someplace else
14171 * in our code, like the register restore mess on resume. Clamp
14172 * things to off as a safer default. */
14173 for_each_intel_connector(dev
, connector
) {
14174 if (connector
->encoder
!= encoder
)
14176 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14177 connector
->base
.encoder
= NULL
;
14180 /* Enabled encoders without active connectors will be fixed in
14181 * the crtc fixup. */
14184 void i915_redisable_vga_power_on(struct drm_device
*dev
)
14186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14187 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14189 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
14190 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14191 i915_disable_vga(dev
);
14195 void i915_redisable_vga(struct drm_device
*dev
)
14197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14199 /* This function can be called both from intel_modeset_setup_hw_state or
14200 * at a very early point in our resume sequence, where the power well
14201 * structures are not yet restored. Since this function is at a very
14202 * paranoid "someone might have enabled VGA while we were not looking"
14203 * level, just check if the power well is enabled instead of trying to
14204 * follow the "don't touch the power well if we don't need it" policy
14205 * the rest of the driver uses. */
14206 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
14209 i915_redisable_vga_power_on(dev
);
14212 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
14214 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
14219 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
14222 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
14224 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14226 struct intel_crtc
*crtc
;
14227 struct intel_encoder
*encoder
;
14228 struct intel_connector
*connector
;
14231 for_each_intel_crtc(dev
, crtc
) {
14232 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
14234 crtc
->config
->quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
14236 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
14239 crtc
->base
.state
->enable
= crtc
->active
;
14240 crtc
->base
.enabled
= crtc
->active
;
14241 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
14243 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14244 crtc
->base
.base
.id
,
14245 crtc
->active
? "enabled" : "disabled");
14248 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14249 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14251 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
14252 &pll
->config
.hw_state
);
14254 pll
->config
.crtc_mask
= 0;
14255 for_each_intel_crtc(dev
, crtc
) {
14256 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
14258 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
14262 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14263 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
14265 if (pll
->config
.crtc_mask
)
14266 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
14269 for_each_intel_encoder(dev
, encoder
) {
14272 if (encoder
->get_hw_state(encoder
, &pipe
)) {
14273 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
14274 encoder
->base
.crtc
= &crtc
->base
;
14275 encoder
->get_config(encoder
, crtc
->config
);
14277 encoder
->base
.crtc
= NULL
;
14280 encoder
->connectors_active
= false;
14281 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14282 encoder
->base
.base
.id
,
14283 encoder
->base
.name
,
14284 encoder
->base
.crtc
? "enabled" : "disabled",
14288 for_each_intel_connector(dev
, connector
) {
14289 if (connector
->get_hw_state(connector
)) {
14290 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
14291 connector
->encoder
->connectors_active
= true;
14292 connector
->base
.encoder
= &connector
->encoder
->base
;
14294 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
14295 connector
->base
.encoder
= NULL
;
14297 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14298 connector
->base
.base
.id
,
14299 connector
->base
.name
,
14300 connector
->base
.encoder
? "enabled" : "disabled");
14304 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14305 * and i915 state tracking structures. */
14306 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
14307 bool force_restore
)
14309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14311 struct intel_crtc
*crtc
;
14312 struct intel_encoder
*encoder
;
14315 intel_modeset_readout_hw_state(dev
);
14318 * Now that we have the config, copy it to each CRTC struct
14319 * Note that this could go away if we move to using crtc_config
14320 * checking everywhere.
14322 for_each_intel_crtc(dev
, crtc
) {
14323 if (crtc
->active
&& i915
.fastboot
) {
14324 intel_mode_from_pipe_config(&crtc
->base
.mode
,
14326 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14327 crtc
->base
.base
.id
);
14328 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
14332 /* HW state is read out, now we need to sanitize this mess. */
14333 for_each_intel_encoder(dev
, encoder
) {
14334 intel_sanitize_encoder(encoder
);
14337 for_each_pipe(dev_priv
, pipe
) {
14338 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
14339 intel_sanitize_crtc(crtc
);
14340 intel_dump_pipe_config(crtc
, crtc
->config
,
14341 "[setup_hw_state]");
14344 intel_modeset_update_connector_atomic_state(dev
);
14346 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
14347 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
14349 if (!pll
->on
|| pll
->active
)
14352 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
14354 pll
->disable(dev_priv
, pll
);
14359 skl_wm_get_hw_state(dev
);
14360 else if (HAS_PCH_SPLIT(dev
))
14361 ilk_wm_get_hw_state(dev
);
14363 if (force_restore
) {
14364 i915_redisable_vga(dev
);
14367 * We need to use raw interfaces for restoring state to avoid
14368 * checking (bogus) intermediate states.
14370 for_each_pipe(dev_priv
, pipe
) {
14371 struct drm_crtc
*crtc
=
14372 dev_priv
->pipe_to_crtc_mapping
[pipe
];
14374 intel_crtc_restore_mode(crtc
);
14377 intel_modeset_update_staged_output_state(dev
);
14380 intel_modeset_check_state(dev
);
14383 void intel_modeset_gem_init(struct drm_device
*dev
)
14385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14386 struct drm_crtc
*c
;
14387 struct drm_i915_gem_object
*obj
;
14389 mutex_lock(&dev
->struct_mutex
);
14390 intel_init_gt_powersave(dev
);
14391 mutex_unlock(&dev
->struct_mutex
);
14394 * There may be no VBT; and if the BIOS enabled SSC we can
14395 * just keep using it to avoid unnecessary flicker. Whereas if the
14396 * BIOS isn't using it, don't assume it will work even if the VBT
14397 * indicates as much.
14399 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
14400 dev_priv
->vbt
.lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14403 intel_modeset_init_hw(dev
);
14405 intel_setup_overlay(dev
);
14408 * Make sure any fbs we allocated at startup are properly
14409 * pinned & fenced. When we do the allocation it's too early
14412 mutex_lock(&dev
->struct_mutex
);
14413 for_each_crtc(dev
, c
) {
14414 obj
= intel_fb_obj(c
->primary
->fb
);
14418 if (intel_pin_and_fence_fb_obj(c
->primary
,
14422 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14423 to_intel_crtc(c
)->pipe
);
14424 drm_framebuffer_unreference(c
->primary
->fb
);
14425 c
->primary
->fb
= NULL
;
14426 update_state_fb(c
->primary
);
14429 mutex_unlock(&dev
->struct_mutex
);
14431 intel_backlight_register(dev
);
14434 void intel_connector_unregister(struct intel_connector
*intel_connector
)
14436 struct drm_connector
*connector
= &intel_connector
->base
;
14438 intel_panel_destroy_backlight(connector
);
14439 drm_connector_unregister(connector
);
14442 void intel_modeset_cleanup(struct drm_device
*dev
)
14444 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14445 struct drm_connector
*connector
;
14447 intel_disable_gt_powersave(dev
);
14449 intel_backlight_unregister(dev
);
14452 * Interrupts and polling as the first thing to avoid creating havoc.
14453 * Too much stuff here (turning of connectors, ...) would
14454 * experience fancy races otherwise.
14456 intel_irq_uninstall(dev_priv
);
14459 * Due to the hpd irq storm handling the hotplug work can re-arm the
14460 * poll handlers. Hence disable polling after hpd handling is shut down.
14462 drm_kms_helper_poll_fini(dev
);
14464 mutex_lock(&dev
->struct_mutex
);
14466 intel_unregister_dsm_handler();
14468 intel_fbc_disable(dev
);
14470 mutex_unlock(&dev
->struct_mutex
);
14472 /* flush any delayed tasks or pending work */
14473 flush_scheduled_work();
14475 /* destroy the backlight and sysfs files before encoders/connectors */
14476 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
14477 struct intel_connector
*intel_connector
;
14479 intel_connector
= to_intel_connector(connector
);
14480 intel_connector
->unregister(intel_connector
);
14483 drm_mode_config_cleanup(dev
);
14485 intel_cleanup_overlay(dev
);
14487 mutex_lock(&dev
->struct_mutex
);
14488 intel_cleanup_gt_powersave(dev
);
14489 mutex_unlock(&dev
->struct_mutex
);
14493 * Return which encoder is currently attached for connector.
14495 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
14497 return &intel_attached_encoder(connector
)->base
;
14500 void intel_connector_attach_encoder(struct intel_connector
*connector
,
14501 struct intel_encoder
*encoder
)
14503 connector
->encoder
= encoder
;
14504 drm_mode_connector_attach_encoder(&connector
->base
,
14509 * set vga decode state - true == enable VGA decode
14511 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
14513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14514 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
14517 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
14518 DRM_ERROR("failed to read control word\n");
14522 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
14526 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
14528 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
14530 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
14531 DRM_ERROR("failed to write control word\n");
14538 struct intel_display_error_state
{
14540 u32 power_well_driver
;
14542 int num_transcoders
;
14544 struct intel_cursor_error_state
{
14549 } cursor
[I915_MAX_PIPES
];
14551 struct intel_pipe_error_state
{
14552 bool power_domain_on
;
14555 } pipe
[I915_MAX_PIPES
];
14557 struct intel_plane_error_state
{
14565 } plane
[I915_MAX_PIPES
];
14567 struct intel_transcoder_error_state
{
14568 bool power_domain_on
;
14569 enum transcoder cpu_transcoder
;
14582 struct intel_display_error_state
*
14583 intel_display_capture_error_state(struct drm_device
*dev
)
14585 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14586 struct intel_display_error_state
*error
;
14587 int transcoders
[] = {
14595 if (INTEL_INFO(dev
)->num_pipes
== 0)
14598 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
14602 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
14603 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
14605 for_each_pipe(dev_priv
, i
) {
14606 error
->pipe
[i
].power_domain_on
=
14607 __intel_display_power_is_enabled(dev_priv
,
14608 POWER_DOMAIN_PIPE(i
));
14609 if (!error
->pipe
[i
].power_domain_on
)
14612 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
14613 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
14614 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
14616 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
14617 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
14618 if (INTEL_INFO(dev
)->gen
<= 3) {
14619 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
14620 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
14622 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
14623 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
14624 if (INTEL_INFO(dev
)->gen
>= 4) {
14625 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
14626 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
14629 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
14631 if (HAS_GMCH_DISPLAY(dev
))
14632 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
14635 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
14636 if (HAS_DDI(dev_priv
->dev
))
14637 error
->num_transcoders
++; /* Account for eDP. */
14639 for (i
= 0; i
< error
->num_transcoders
; i
++) {
14640 enum transcoder cpu_transcoder
= transcoders
[i
];
14642 error
->transcoder
[i
].power_domain_on
=
14643 __intel_display_power_is_enabled(dev_priv
,
14644 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
14645 if (!error
->transcoder
[i
].power_domain_on
)
14648 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
14650 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
14651 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
14652 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
14653 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
14654 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
14655 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
14656 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
14662 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14665 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
14666 struct drm_device
*dev
,
14667 struct intel_display_error_state
*error
)
14669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14675 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
14676 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
14677 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
14678 error
->power_well_driver
);
14679 for_each_pipe(dev_priv
, i
) {
14680 err_printf(m
, "Pipe [%d]:\n", i
);
14681 err_printf(m
, " Power: %s\n",
14682 error
->pipe
[i
].power_domain_on
? "on" : "off");
14683 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
14684 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
14686 err_printf(m
, "Plane [%d]:\n", i
);
14687 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
14688 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
14689 if (INTEL_INFO(dev
)->gen
<= 3) {
14690 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
14691 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
14693 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
14694 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
14695 if (INTEL_INFO(dev
)->gen
>= 4) {
14696 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
14697 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
14700 err_printf(m
, "Cursor [%d]:\n", i
);
14701 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
14702 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
14703 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
14706 for (i
= 0; i
< error
->num_transcoders
; i
++) {
14707 err_printf(m
, "CPU transcoder: %c\n",
14708 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
14709 err_printf(m
, " Power: %s\n",
14710 error
->transcoder
[i
].power_domain_on
? "on" : "off");
14711 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
14712 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
14713 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
14714 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
14715 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
14716 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
14717 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
14721 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
14723 struct intel_crtc
*crtc
;
14725 for_each_intel_crtc(dev
, crtc
) {
14726 struct intel_unpin_work
*work
;
14728 spin_lock_irq(&dev
->event_lock
);
14730 work
= crtc
->unpin_work
;
14732 if (work
&& work
->event
&&
14733 work
->event
->base
.file_priv
== file
) {
14734 kfree(work
->event
);
14735 work
->event
= NULL
;
14738 spin_unlock_irq(&dev
->event_lock
);