2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/module.h>
28 #include <linux/input.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/slab.h>
33 #include "intel_drv.h"
36 #include "i915_trace.h"
37 #include "drm_dp_helper.h"
39 #include "drm_crtc_helper.h"
41 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
43 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
);
44 static void intel_update_watermarks(struct drm_device
*dev
);
45 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
);
46 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t
;
72 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
74 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
75 int, int, intel_clock_t
*);
78 #define I8XX_DOT_MIN 25000
79 #define I8XX_DOT_MAX 350000
80 #define I8XX_VCO_MIN 930000
81 #define I8XX_VCO_MAX 1400000
85 #define I8XX_M_MAX 140
86 #define I8XX_M1_MIN 18
87 #define I8XX_M1_MAX 26
89 #define I8XX_M2_MAX 16
91 #define I8XX_P_MAX 128
93 #define I8XX_P1_MAX 33
94 #define I8XX_P1_LVDS_MIN 1
95 #define I8XX_P1_LVDS_MAX 6
96 #define I8XX_P2_SLOW 4
97 #define I8XX_P2_FAST 2
98 #define I8XX_P2_LVDS_SLOW 14
99 #define I8XX_P2_LVDS_FAST 7
100 #define I8XX_P2_SLOW_LIMIT 165000
102 #define I9XX_DOT_MIN 20000
103 #define I9XX_DOT_MAX 400000
104 #define I9XX_VCO_MIN 1400000
105 #define I9XX_VCO_MAX 2800000
106 #define PINEVIEW_VCO_MIN 1700000
107 #define PINEVIEW_VCO_MAX 3500000
110 /* Pineview's Ncounter is a ring counter */
111 #define PINEVIEW_N_MIN 3
112 #define PINEVIEW_N_MAX 6
113 #define I9XX_M_MIN 70
114 #define I9XX_M_MAX 120
115 #define PINEVIEW_M_MIN 2
116 #define PINEVIEW_M_MAX 256
117 #define I9XX_M1_MIN 10
118 #define I9XX_M1_MAX 22
119 #define I9XX_M2_MIN 5
120 #define I9XX_M2_MAX 9
121 /* Pineview M1 is reserved, and must be 0 */
122 #define PINEVIEW_M1_MIN 0
123 #define PINEVIEW_M1_MAX 0
124 #define PINEVIEW_M2_MIN 0
125 #define PINEVIEW_M2_MAX 254
126 #define I9XX_P_SDVO_DAC_MIN 5
127 #define I9XX_P_SDVO_DAC_MAX 80
128 #define I9XX_P_LVDS_MIN 7
129 #define I9XX_P_LVDS_MAX 98
130 #define PINEVIEW_P_LVDS_MIN 7
131 #define PINEVIEW_P_LVDS_MAX 112
132 #define I9XX_P1_MIN 1
133 #define I9XX_P1_MAX 8
134 #define I9XX_P2_SDVO_DAC_SLOW 10
135 #define I9XX_P2_SDVO_DAC_FAST 5
136 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
137 #define I9XX_P2_LVDS_SLOW 14
138 #define I9XX_P2_LVDS_FAST 7
139 #define I9XX_P2_LVDS_SLOW_LIMIT 112000
141 /*The parameter is for SDVO on G4x platform*/
142 #define G4X_DOT_SDVO_MIN 25000
143 #define G4X_DOT_SDVO_MAX 270000
144 #define G4X_VCO_MIN 1750000
145 #define G4X_VCO_MAX 3500000
146 #define G4X_N_SDVO_MIN 1
147 #define G4X_N_SDVO_MAX 4
148 #define G4X_M_SDVO_MIN 104
149 #define G4X_M_SDVO_MAX 138
150 #define G4X_M1_SDVO_MIN 17
151 #define G4X_M1_SDVO_MAX 23
152 #define G4X_M2_SDVO_MIN 5
153 #define G4X_M2_SDVO_MAX 11
154 #define G4X_P_SDVO_MIN 10
155 #define G4X_P_SDVO_MAX 30
156 #define G4X_P1_SDVO_MIN 1
157 #define G4X_P1_SDVO_MAX 3
158 #define G4X_P2_SDVO_SLOW 10
159 #define G4X_P2_SDVO_FAST 10
160 #define G4X_P2_SDVO_LIMIT 270000
162 /*The parameter is for HDMI_DAC on G4x platform*/
163 #define G4X_DOT_HDMI_DAC_MIN 22000
164 #define G4X_DOT_HDMI_DAC_MAX 400000
165 #define G4X_N_HDMI_DAC_MIN 1
166 #define G4X_N_HDMI_DAC_MAX 4
167 #define G4X_M_HDMI_DAC_MIN 104
168 #define G4X_M_HDMI_DAC_MAX 138
169 #define G4X_M1_HDMI_DAC_MIN 16
170 #define G4X_M1_HDMI_DAC_MAX 23
171 #define G4X_M2_HDMI_DAC_MIN 5
172 #define G4X_M2_HDMI_DAC_MAX 11
173 #define G4X_P_HDMI_DAC_MIN 5
174 #define G4X_P_HDMI_DAC_MAX 80
175 #define G4X_P1_HDMI_DAC_MIN 1
176 #define G4X_P1_HDMI_DAC_MAX 8
177 #define G4X_P2_HDMI_DAC_SLOW 10
178 #define G4X_P2_HDMI_DAC_FAST 5
179 #define G4X_P2_HDMI_DAC_LIMIT 165000
181 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
182 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
184 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
185 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
186 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
187 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
188 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
190 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
192 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
193 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
194 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
196 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
197 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
198 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
200 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
201 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
203 #define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
204 #define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
205 #define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
206 #define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
207 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
208 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
209 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
210 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
211 #define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
212 #define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
213 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
214 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
215 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
216 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
217 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
219 /*The parameter is for DISPLAY PORT on G4x platform*/
220 #define G4X_DOT_DISPLAY_PORT_MIN 161670
221 #define G4X_DOT_DISPLAY_PORT_MAX 227000
222 #define G4X_N_DISPLAY_PORT_MIN 1
223 #define G4X_N_DISPLAY_PORT_MAX 2
224 #define G4X_M_DISPLAY_PORT_MIN 97
225 #define G4X_M_DISPLAY_PORT_MAX 108
226 #define G4X_M1_DISPLAY_PORT_MIN 0x10
227 #define G4X_M1_DISPLAY_PORT_MAX 0x12
228 #define G4X_M2_DISPLAY_PORT_MIN 0x05
229 #define G4X_M2_DISPLAY_PORT_MAX 0x06
230 #define G4X_P_DISPLAY_PORT_MIN 10
231 #define G4X_P_DISPLAY_PORT_MAX 20
232 #define G4X_P1_DISPLAY_PORT_MIN 1
233 #define G4X_P1_DISPLAY_PORT_MAX 2
234 #define G4X_P2_DISPLAY_PORT_SLOW 10
235 #define G4X_P2_DISPLAY_PORT_FAST 10
236 #define G4X_P2_DISPLAY_PORT_LIMIT 0
238 /* Ironlake / Sandybridge */
239 /* as we calculate clock using (register_value + 2) for
240 N/M1/M2, so here the range value for them is (actual_value-2).
242 #define IRONLAKE_DOT_MIN 25000
243 #define IRONLAKE_DOT_MAX 350000
244 #define IRONLAKE_VCO_MIN 1760000
245 #define IRONLAKE_VCO_MAX 3510000
246 #define IRONLAKE_M1_MIN 12
247 #define IRONLAKE_M1_MAX 22
248 #define IRONLAKE_M2_MIN 5
249 #define IRONLAKE_M2_MAX 9
250 #define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
252 /* We have parameter ranges for different type of outputs. */
254 /* DAC & HDMI Refclk 120Mhz */
255 #define IRONLAKE_DAC_N_MIN 1
256 #define IRONLAKE_DAC_N_MAX 5
257 #define IRONLAKE_DAC_M_MIN 79
258 #define IRONLAKE_DAC_M_MAX 127
259 #define IRONLAKE_DAC_P_MIN 5
260 #define IRONLAKE_DAC_P_MAX 80
261 #define IRONLAKE_DAC_P1_MIN 1
262 #define IRONLAKE_DAC_P1_MAX 8
263 #define IRONLAKE_DAC_P2_SLOW 10
264 #define IRONLAKE_DAC_P2_FAST 5
266 /* LVDS single-channel 120Mhz refclk */
267 #define IRONLAKE_LVDS_S_N_MIN 1
268 #define IRONLAKE_LVDS_S_N_MAX 3
269 #define IRONLAKE_LVDS_S_M_MIN 79
270 #define IRONLAKE_LVDS_S_M_MAX 118
271 #define IRONLAKE_LVDS_S_P_MIN 28
272 #define IRONLAKE_LVDS_S_P_MAX 112
273 #define IRONLAKE_LVDS_S_P1_MIN 2
274 #define IRONLAKE_LVDS_S_P1_MAX 8
275 #define IRONLAKE_LVDS_S_P2_SLOW 14
276 #define IRONLAKE_LVDS_S_P2_FAST 14
278 /* LVDS dual-channel 120Mhz refclk */
279 #define IRONLAKE_LVDS_D_N_MIN 1
280 #define IRONLAKE_LVDS_D_N_MAX 3
281 #define IRONLAKE_LVDS_D_M_MIN 79
282 #define IRONLAKE_LVDS_D_M_MAX 127
283 #define IRONLAKE_LVDS_D_P_MIN 14
284 #define IRONLAKE_LVDS_D_P_MAX 56
285 #define IRONLAKE_LVDS_D_P1_MIN 2
286 #define IRONLAKE_LVDS_D_P1_MAX 8
287 #define IRONLAKE_LVDS_D_P2_SLOW 7
288 #define IRONLAKE_LVDS_D_P2_FAST 7
290 /* LVDS single-channel 100Mhz refclk */
291 #define IRONLAKE_LVDS_S_SSC_N_MIN 1
292 #define IRONLAKE_LVDS_S_SSC_N_MAX 2
293 #define IRONLAKE_LVDS_S_SSC_M_MIN 79
294 #define IRONLAKE_LVDS_S_SSC_M_MAX 126
295 #define IRONLAKE_LVDS_S_SSC_P_MIN 28
296 #define IRONLAKE_LVDS_S_SSC_P_MAX 112
297 #define IRONLAKE_LVDS_S_SSC_P1_MIN 2
298 #define IRONLAKE_LVDS_S_SSC_P1_MAX 8
299 #define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
300 #define IRONLAKE_LVDS_S_SSC_P2_FAST 14
302 /* LVDS dual-channel 100Mhz refclk */
303 #define IRONLAKE_LVDS_D_SSC_N_MIN 1
304 #define IRONLAKE_LVDS_D_SSC_N_MAX 3
305 #define IRONLAKE_LVDS_D_SSC_M_MIN 79
306 #define IRONLAKE_LVDS_D_SSC_M_MAX 126
307 #define IRONLAKE_LVDS_D_SSC_P_MIN 14
308 #define IRONLAKE_LVDS_D_SSC_P_MAX 42
309 #define IRONLAKE_LVDS_D_SSC_P1_MIN 2
310 #define IRONLAKE_LVDS_D_SSC_P1_MAX 6
311 #define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
312 #define IRONLAKE_LVDS_D_SSC_P2_FAST 7
315 #define IRONLAKE_DP_N_MIN 1
316 #define IRONLAKE_DP_N_MAX 2
317 #define IRONLAKE_DP_M_MIN 81
318 #define IRONLAKE_DP_M_MAX 90
319 #define IRONLAKE_DP_P_MIN 10
320 #define IRONLAKE_DP_P_MAX 20
321 #define IRONLAKE_DP_P2_FAST 10
322 #define IRONLAKE_DP_P2_SLOW 10
323 #define IRONLAKE_DP_P2_LIMIT 0
324 #define IRONLAKE_DP_P1_MIN 1
325 #define IRONLAKE_DP_P1_MAX 2
328 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
331 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
332 int target
, int refclk
, intel_clock_t
*best_clock
);
334 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
335 int target
, int refclk
, intel_clock_t
*best_clock
);
338 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
339 int target
, int refclk
, intel_clock_t
*best_clock
);
341 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
342 int target
, int refclk
, intel_clock_t
*best_clock
);
344 static const intel_limit_t intel_limits_i8xx_dvo
= {
345 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
346 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
347 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
348 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
349 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
350 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
351 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
352 .p1
= { .min
= I8XX_P1_MIN
, .max
= I8XX_P1_MAX
},
353 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
354 .p2_slow
= I8XX_P2_SLOW
, .p2_fast
= I8XX_P2_FAST
},
355 .find_pll
= intel_find_best_PLL
,
358 static const intel_limit_t intel_limits_i8xx_lvds
= {
359 .dot
= { .min
= I8XX_DOT_MIN
, .max
= I8XX_DOT_MAX
},
360 .vco
= { .min
= I8XX_VCO_MIN
, .max
= I8XX_VCO_MAX
},
361 .n
= { .min
= I8XX_N_MIN
, .max
= I8XX_N_MAX
},
362 .m
= { .min
= I8XX_M_MIN
, .max
= I8XX_M_MAX
},
363 .m1
= { .min
= I8XX_M1_MIN
, .max
= I8XX_M1_MAX
},
364 .m2
= { .min
= I8XX_M2_MIN
, .max
= I8XX_M2_MAX
},
365 .p
= { .min
= I8XX_P_MIN
, .max
= I8XX_P_MAX
},
366 .p1
= { .min
= I8XX_P1_LVDS_MIN
, .max
= I8XX_P1_LVDS_MAX
},
367 .p2
= { .dot_limit
= I8XX_P2_SLOW_LIMIT
,
368 .p2_slow
= I8XX_P2_LVDS_SLOW
, .p2_fast
= I8XX_P2_LVDS_FAST
},
369 .find_pll
= intel_find_best_PLL
,
372 static const intel_limit_t intel_limits_i9xx_sdvo
= {
373 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
374 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
375 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
376 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
377 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
378 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
379 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
380 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
381 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
382 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
383 .find_pll
= intel_find_best_PLL
,
386 static const intel_limit_t intel_limits_i9xx_lvds
= {
387 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
388 .vco
= { .min
= I9XX_VCO_MIN
, .max
= I9XX_VCO_MAX
},
389 .n
= { .min
= I9XX_N_MIN
, .max
= I9XX_N_MAX
},
390 .m
= { .min
= I9XX_M_MIN
, .max
= I9XX_M_MAX
},
391 .m1
= { .min
= I9XX_M1_MIN
, .max
= I9XX_M1_MAX
},
392 .m2
= { .min
= I9XX_M2_MIN
, .max
= I9XX_M2_MAX
},
393 .p
= { .min
= I9XX_P_LVDS_MIN
, .max
= I9XX_P_LVDS_MAX
},
394 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
395 /* The single-channel range is 25-112Mhz, and dual-channel
396 * is 80-224Mhz. Prefer single channel as much as possible.
398 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
399 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_FAST
},
400 .find_pll
= intel_find_best_PLL
,
403 /* below parameter and function is for G4X Chipset Family*/
404 static const intel_limit_t intel_limits_g4x_sdvo
= {
405 .dot
= { .min
= G4X_DOT_SDVO_MIN
, .max
= G4X_DOT_SDVO_MAX
},
406 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
407 .n
= { .min
= G4X_N_SDVO_MIN
, .max
= G4X_N_SDVO_MAX
},
408 .m
= { .min
= G4X_M_SDVO_MIN
, .max
= G4X_M_SDVO_MAX
},
409 .m1
= { .min
= G4X_M1_SDVO_MIN
, .max
= G4X_M1_SDVO_MAX
},
410 .m2
= { .min
= G4X_M2_SDVO_MIN
, .max
= G4X_M2_SDVO_MAX
},
411 .p
= { .min
= G4X_P_SDVO_MIN
, .max
= G4X_P_SDVO_MAX
},
412 .p1
= { .min
= G4X_P1_SDVO_MIN
, .max
= G4X_P1_SDVO_MAX
},
413 .p2
= { .dot_limit
= G4X_P2_SDVO_LIMIT
,
414 .p2_slow
= G4X_P2_SDVO_SLOW
,
415 .p2_fast
= G4X_P2_SDVO_FAST
417 .find_pll
= intel_g4x_find_best_PLL
,
420 static const intel_limit_t intel_limits_g4x_hdmi
= {
421 .dot
= { .min
= G4X_DOT_HDMI_DAC_MIN
, .max
= G4X_DOT_HDMI_DAC_MAX
},
422 .vco
= { .min
= G4X_VCO_MIN
, .max
= G4X_VCO_MAX
},
423 .n
= { .min
= G4X_N_HDMI_DAC_MIN
, .max
= G4X_N_HDMI_DAC_MAX
},
424 .m
= { .min
= G4X_M_HDMI_DAC_MIN
, .max
= G4X_M_HDMI_DAC_MAX
},
425 .m1
= { .min
= G4X_M1_HDMI_DAC_MIN
, .max
= G4X_M1_HDMI_DAC_MAX
},
426 .m2
= { .min
= G4X_M2_HDMI_DAC_MIN
, .max
= G4X_M2_HDMI_DAC_MAX
},
427 .p
= { .min
= G4X_P_HDMI_DAC_MIN
, .max
= G4X_P_HDMI_DAC_MAX
},
428 .p1
= { .min
= G4X_P1_HDMI_DAC_MIN
, .max
= G4X_P1_HDMI_DAC_MAX
},
429 .p2
= { .dot_limit
= G4X_P2_HDMI_DAC_LIMIT
,
430 .p2_slow
= G4X_P2_HDMI_DAC_SLOW
,
431 .p2_fast
= G4X_P2_HDMI_DAC_FAST
433 .find_pll
= intel_g4x_find_best_PLL
,
436 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
437 .dot
= { .min
= G4X_DOT_SINGLE_CHANNEL_LVDS_MIN
,
438 .max
= G4X_DOT_SINGLE_CHANNEL_LVDS_MAX
},
439 .vco
= { .min
= G4X_VCO_MIN
,
440 .max
= G4X_VCO_MAX
},
441 .n
= { .min
= G4X_N_SINGLE_CHANNEL_LVDS_MIN
,
442 .max
= G4X_N_SINGLE_CHANNEL_LVDS_MAX
},
443 .m
= { .min
= G4X_M_SINGLE_CHANNEL_LVDS_MIN
,
444 .max
= G4X_M_SINGLE_CHANNEL_LVDS_MAX
},
445 .m1
= { .min
= G4X_M1_SINGLE_CHANNEL_LVDS_MIN
,
446 .max
= G4X_M1_SINGLE_CHANNEL_LVDS_MAX
},
447 .m2
= { .min
= G4X_M2_SINGLE_CHANNEL_LVDS_MIN
,
448 .max
= G4X_M2_SINGLE_CHANNEL_LVDS_MAX
},
449 .p
= { .min
= G4X_P_SINGLE_CHANNEL_LVDS_MIN
,
450 .max
= G4X_P_SINGLE_CHANNEL_LVDS_MAX
},
451 .p1
= { .min
= G4X_P1_SINGLE_CHANNEL_LVDS_MIN
,
452 .max
= G4X_P1_SINGLE_CHANNEL_LVDS_MAX
},
453 .p2
= { .dot_limit
= G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT
,
454 .p2_slow
= G4X_P2_SINGLE_CHANNEL_LVDS_SLOW
,
455 .p2_fast
= G4X_P2_SINGLE_CHANNEL_LVDS_FAST
457 .find_pll
= intel_g4x_find_best_PLL
,
460 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
461 .dot
= { .min
= G4X_DOT_DUAL_CHANNEL_LVDS_MIN
,
462 .max
= G4X_DOT_DUAL_CHANNEL_LVDS_MAX
},
463 .vco
= { .min
= G4X_VCO_MIN
,
464 .max
= G4X_VCO_MAX
},
465 .n
= { .min
= G4X_N_DUAL_CHANNEL_LVDS_MIN
,
466 .max
= G4X_N_DUAL_CHANNEL_LVDS_MAX
},
467 .m
= { .min
= G4X_M_DUAL_CHANNEL_LVDS_MIN
,
468 .max
= G4X_M_DUAL_CHANNEL_LVDS_MAX
},
469 .m1
= { .min
= G4X_M1_DUAL_CHANNEL_LVDS_MIN
,
470 .max
= G4X_M1_DUAL_CHANNEL_LVDS_MAX
},
471 .m2
= { .min
= G4X_M2_DUAL_CHANNEL_LVDS_MIN
,
472 .max
= G4X_M2_DUAL_CHANNEL_LVDS_MAX
},
473 .p
= { .min
= G4X_P_DUAL_CHANNEL_LVDS_MIN
,
474 .max
= G4X_P_DUAL_CHANNEL_LVDS_MAX
},
475 .p1
= { .min
= G4X_P1_DUAL_CHANNEL_LVDS_MIN
,
476 .max
= G4X_P1_DUAL_CHANNEL_LVDS_MAX
},
477 .p2
= { .dot_limit
= G4X_P2_DUAL_CHANNEL_LVDS_LIMIT
,
478 .p2_slow
= G4X_P2_DUAL_CHANNEL_LVDS_SLOW
,
479 .p2_fast
= G4X_P2_DUAL_CHANNEL_LVDS_FAST
481 .find_pll
= intel_g4x_find_best_PLL
,
484 static const intel_limit_t intel_limits_g4x_display_port
= {
485 .dot
= { .min
= G4X_DOT_DISPLAY_PORT_MIN
,
486 .max
= G4X_DOT_DISPLAY_PORT_MAX
},
487 .vco
= { .min
= G4X_VCO_MIN
,
489 .n
= { .min
= G4X_N_DISPLAY_PORT_MIN
,
490 .max
= G4X_N_DISPLAY_PORT_MAX
},
491 .m
= { .min
= G4X_M_DISPLAY_PORT_MIN
,
492 .max
= G4X_M_DISPLAY_PORT_MAX
},
493 .m1
= { .min
= G4X_M1_DISPLAY_PORT_MIN
,
494 .max
= G4X_M1_DISPLAY_PORT_MAX
},
495 .m2
= { .min
= G4X_M2_DISPLAY_PORT_MIN
,
496 .max
= G4X_M2_DISPLAY_PORT_MAX
},
497 .p
= { .min
= G4X_P_DISPLAY_PORT_MIN
,
498 .max
= G4X_P_DISPLAY_PORT_MAX
},
499 .p1
= { .min
= G4X_P1_DISPLAY_PORT_MIN
,
500 .max
= G4X_P1_DISPLAY_PORT_MAX
},
501 .p2
= { .dot_limit
= G4X_P2_DISPLAY_PORT_LIMIT
,
502 .p2_slow
= G4X_P2_DISPLAY_PORT_SLOW
,
503 .p2_fast
= G4X_P2_DISPLAY_PORT_FAST
},
504 .find_pll
= intel_find_pll_g4x_dp
,
507 static const intel_limit_t intel_limits_pineview_sdvo
= {
508 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
509 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
510 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
511 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
512 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
513 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
514 .p
= { .min
= I9XX_P_SDVO_DAC_MIN
, .max
= I9XX_P_SDVO_DAC_MAX
},
515 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
516 .p2
= { .dot_limit
= I9XX_P2_SDVO_DAC_SLOW_LIMIT
,
517 .p2_slow
= I9XX_P2_SDVO_DAC_SLOW
, .p2_fast
= I9XX_P2_SDVO_DAC_FAST
},
518 .find_pll
= intel_find_best_PLL
,
521 static const intel_limit_t intel_limits_pineview_lvds
= {
522 .dot
= { .min
= I9XX_DOT_MIN
, .max
= I9XX_DOT_MAX
},
523 .vco
= { .min
= PINEVIEW_VCO_MIN
, .max
= PINEVIEW_VCO_MAX
},
524 .n
= { .min
= PINEVIEW_N_MIN
, .max
= PINEVIEW_N_MAX
},
525 .m
= { .min
= PINEVIEW_M_MIN
, .max
= PINEVIEW_M_MAX
},
526 .m1
= { .min
= PINEVIEW_M1_MIN
, .max
= PINEVIEW_M1_MAX
},
527 .m2
= { .min
= PINEVIEW_M2_MIN
, .max
= PINEVIEW_M2_MAX
},
528 .p
= { .min
= PINEVIEW_P_LVDS_MIN
, .max
= PINEVIEW_P_LVDS_MAX
},
529 .p1
= { .min
= I9XX_P1_MIN
, .max
= I9XX_P1_MAX
},
530 /* Pineview only supports single-channel mode. */
531 .p2
= { .dot_limit
= I9XX_P2_LVDS_SLOW_LIMIT
,
532 .p2_slow
= I9XX_P2_LVDS_SLOW
, .p2_fast
= I9XX_P2_LVDS_SLOW
},
533 .find_pll
= intel_find_best_PLL
,
536 static const intel_limit_t intel_limits_ironlake_dac
= {
537 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
538 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
539 .n
= { .min
= IRONLAKE_DAC_N_MIN
, .max
= IRONLAKE_DAC_N_MAX
},
540 .m
= { .min
= IRONLAKE_DAC_M_MIN
, .max
= IRONLAKE_DAC_M_MAX
},
541 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
542 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
543 .p
= { .min
= IRONLAKE_DAC_P_MIN
, .max
= IRONLAKE_DAC_P_MAX
},
544 .p1
= { .min
= IRONLAKE_DAC_P1_MIN
, .max
= IRONLAKE_DAC_P1_MAX
},
545 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
546 .p2_slow
= IRONLAKE_DAC_P2_SLOW
,
547 .p2_fast
= IRONLAKE_DAC_P2_FAST
},
548 .find_pll
= intel_g4x_find_best_PLL
,
551 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
552 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
553 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
554 .n
= { .min
= IRONLAKE_LVDS_S_N_MIN
, .max
= IRONLAKE_LVDS_S_N_MAX
},
555 .m
= { .min
= IRONLAKE_LVDS_S_M_MIN
, .max
= IRONLAKE_LVDS_S_M_MAX
},
556 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
557 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
558 .p
= { .min
= IRONLAKE_LVDS_S_P_MIN
, .max
= IRONLAKE_LVDS_S_P_MAX
},
559 .p1
= { .min
= IRONLAKE_LVDS_S_P1_MIN
, .max
= IRONLAKE_LVDS_S_P1_MAX
},
560 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
561 .p2_slow
= IRONLAKE_LVDS_S_P2_SLOW
,
562 .p2_fast
= IRONLAKE_LVDS_S_P2_FAST
},
563 .find_pll
= intel_g4x_find_best_PLL
,
566 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
567 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
568 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
569 .n
= { .min
= IRONLAKE_LVDS_D_N_MIN
, .max
= IRONLAKE_LVDS_D_N_MAX
},
570 .m
= { .min
= IRONLAKE_LVDS_D_M_MIN
, .max
= IRONLAKE_LVDS_D_M_MAX
},
571 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
572 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
573 .p
= { .min
= IRONLAKE_LVDS_D_P_MIN
, .max
= IRONLAKE_LVDS_D_P_MAX
},
574 .p1
= { .min
= IRONLAKE_LVDS_D_P1_MIN
, .max
= IRONLAKE_LVDS_D_P1_MAX
},
575 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
576 .p2_slow
= IRONLAKE_LVDS_D_P2_SLOW
,
577 .p2_fast
= IRONLAKE_LVDS_D_P2_FAST
},
578 .find_pll
= intel_g4x_find_best_PLL
,
581 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
582 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
583 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
584 .n
= { .min
= IRONLAKE_LVDS_S_SSC_N_MIN
, .max
= IRONLAKE_LVDS_S_SSC_N_MAX
},
585 .m
= { .min
= IRONLAKE_LVDS_S_SSC_M_MIN
, .max
= IRONLAKE_LVDS_S_SSC_M_MAX
},
586 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
587 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
588 .p
= { .min
= IRONLAKE_LVDS_S_SSC_P_MIN
, .max
= IRONLAKE_LVDS_S_SSC_P_MAX
},
589 .p1
= { .min
= IRONLAKE_LVDS_S_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_S_SSC_P1_MAX
},
590 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
591 .p2_slow
= IRONLAKE_LVDS_S_SSC_P2_SLOW
,
592 .p2_fast
= IRONLAKE_LVDS_S_SSC_P2_FAST
},
593 .find_pll
= intel_g4x_find_best_PLL
,
596 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
597 .dot
= { .min
= IRONLAKE_DOT_MIN
, .max
= IRONLAKE_DOT_MAX
},
598 .vco
= { .min
= IRONLAKE_VCO_MIN
, .max
= IRONLAKE_VCO_MAX
},
599 .n
= { .min
= IRONLAKE_LVDS_D_SSC_N_MIN
, .max
= IRONLAKE_LVDS_D_SSC_N_MAX
},
600 .m
= { .min
= IRONLAKE_LVDS_D_SSC_M_MIN
, .max
= IRONLAKE_LVDS_D_SSC_M_MAX
},
601 .m1
= { .min
= IRONLAKE_M1_MIN
, .max
= IRONLAKE_M1_MAX
},
602 .m2
= { .min
= IRONLAKE_M2_MIN
, .max
= IRONLAKE_M2_MAX
},
603 .p
= { .min
= IRONLAKE_LVDS_D_SSC_P_MIN
, .max
= IRONLAKE_LVDS_D_SSC_P_MAX
},
604 .p1
= { .min
= IRONLAKE_LVDS_D_SSC_P1_MIN
,.max
= IRONLAKE_LVDS_D_SSC_P1_MAX
},
605 .p2
= { .dot_limit
= IRONLAKE_P2_DOT_LIMIT
,
606 .p2_slow
= IRONLAKE_LVDS_D_SSC_P2_SLOW
,
607 .p2_fast
= IRONLAKE_LVDS_D_SSC_P2_FAST
},
608 .find_pll
= intel_g4x_find_best_PLL
,
611 static const intel_limit_t intel_limits_ironlake_display_port
= {
612 .dot
= { .min
= IRONLAKE_DOT_MIN
,
613 .max
= IRONLAKE_DOT_MAX
},
614 .vco
= { .min
= IRONLAKE_VCO_MIN
,
615 .max
= IRONLAKE_VCO_MAX
},
616 .n
= { .min
= IRONLAKE_DP_N_MIN
,
617 .max
= IRONLAKE_DP_N_MAX
},
618 .m
= { .min
= IRONLAKE_DP_M_MIN
,
619 .max
= IRONLAKE_DP_M_MAX
},
620 .m1
= { .min
= IRONLAKE_M1_MIN
,
621 .max
= IRONLAKE_M1_MAX
},
622 .m2
= { .min
= IRONLAKE_M2_MIN
,
623 .max
= IRONLAKE_M2_MAX
},
624 .p
= { .min
= IRONLAKE_DP_P_MIN
,
625 .max
= IRONLAKE_DP_P_MAX
},
626 .p1
= { .min
= IRONLAKE_DP_P1_MIN
,
627 .max
= IRONLAKE_DP_P1_MAX
},
628 .p2
= { .dot_limit
= IRONLAKE_DP_P2_LIMIT
,
629 .p2_slow
= IRONLAKE_DP_P2_SLOW
,
630 .p2_fast
= IRONLAKE_DP_P2_FAST
},
631 .find_pll
= intel_find_pll_ironlake_dp
,
634 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
)
636 struct drm_device
*dev
= crtc
->dev
;
637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
638 const intel_limit_t
*limit
;
641 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
642 if (dev_priv
->lvds_use_ssc
&& dev_priv
->lvds_ssc_freq
== 100)
645 if ((I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) ==
646 LVDS_CLKB_POWER_UP
) {
647 /* LVDS dual channel */
649 limit
= &intel_limits_ironlake_dual_lvds_100m
;
651 limit
= &intel_limits_ironlake_dual_lvds
;
654 limit
= &intel_limits_ironlake_single_lvds_100m
;
656 limit
= &intel_limits_ironlake_single_lvds
;
658 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
660 limit
= &intel_limits_ironlake_display_port
;
662 limit
= &intel_limits_ironlake_dac
;
667 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
669 struct drm_device
*dev
= crtc
->dev
;
670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
671 const intel_limit_t
*limit
;
673 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
674 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
676 /* LVDS with dual channel */
677 limit
= &intel_limits_g4x_dual_channel_lvds
;
679 /* LVDS with dual channel */
680 limit
= &intel_limits_g4x_single_channel_lvds
;
681 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
682 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
683 limit
= &intel_limits_g4x_hdmi
;
684 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
685 limit
= &intel_limits_g4x_sdvo
;
686 } else if (intel_pipe_has_type (crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
687 limit
= &intel_limits_g4x_display_port
;
688 } else /* The option is for other outputs */
689 limit
= &intel_limits_i9xx_sdvo
;
694 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
)
696 struct drm_device
*dev
= crtc
->dev
;
697 const intel_limit_t
*limit
;
699 if (HAS_PCH_SPLIT(dev
))
700 limit
= intel_ironlake_limit(crtc
);
701 else if (IS_G4X(dev
)) {
702 limit
= intel_g4x_limit(crtc
);
703 } else if (IS_I9XX(dev
) && !IS_PINEVIEW(dev
)) {
704 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
705 limit
= &intel_limits_i9xx_lvds
;
707 limit
= &intel_limits_i9xx_sdvo
;
708 } else if (IS_PINEVIEW(dev
)) {
709 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
710 limit
= &intel_limits_pineview_lvds
;
712 limit
= &intel_limits_pineview_sdvo
;
714 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
715 limit
= &intel_limits_i8xx_lvds
;
717 limit
= &intel_limits_i8xx_dvo
;
722 /* m1 is reserved as 0 in Pineview, n is a ring counter */
723 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
725 clock
->m
= clock
->m2
+ 2;
726 clock
->p
= clock
->p1
* clock
->p2
;
727 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
728 clock
->dot
= clock
->vco
/ clock
->p
;
731 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
733 if (IS_PINEVIEW(dev
)) {
734 pineview_clock(refclk
, clock
);
737 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
738 clock
->p
= clock
->p1
* clock
->p2
;
739 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
740 clock
->dot
= clock
->vco
/ clock
->p
;
744 * Returns whether any output on the specified pipe is of the specified type
746 bool intel_pipe_has_type (struct drm_crtc
*crtc
, int type
)
748 struct drm_device
*dev
= crtc
->dev
;
749 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
750 struct drm_encoder
*l_entry
;
752 list_for_each_entry(l_entry
, &mode_config
->encoder_list
, head
) {
753 if (l_entry
&& l_entry
->crtc
== crtc
) {
754 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(l_entry
);
755 if (intel_encoder
->type
== type
)
762 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
764 * Returns whether the given set of divisors are valid for a given refclk with
765 * the given connectors.
768 static bool intel_PLL_is_valid(struct drm_crtc
*crtc
, intel_clock_t
*clock
)
770 const intel_limit_t
*limit
= intel_limit (crtc
);
771 struct drm_device
*dev
= crtc
->dev
;
773 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
774 INTELPllInvalid ("p1 out of range\n");
775 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
776 INTELPllInvalid ("p out of range\n");
777 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
778 INTELPllInvalid ("m2 out of range\n");
779 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
780 INTELPllInvalid ("m1 out of range\n");
781 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
782 INTELPllInvalid ("m1 <= m2\n");
783 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
784 INTELPllInvalid ("m out of range\n");
785 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
786 INTELPllInvalid ("n out of range\n");
787 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
788 INTELPllInvalid ("vco out of range\n");
789 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
790 * connector, etc., rather than just a single range.
792 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
793 INTELPllInvalid ("dot out of range\n");
799 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
800 int target
, int refclk
, intel_clock_t
*best_clock
)
803 struct drm_device
*dev
= crtc
->dev
;
804 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
808 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
809 (I915_READ(LVDS
)) != 0) {
811 * For LVDS, if the panel is on, just rely on its current
812 * settings for dual-channel. We haven't figured out how to
813 * reliably set up different single/dual channel state, if we
816 if ((I915_READ(LVDS
) & LVDS_CLKB_POWER_MASK
) ==
818 clock
.p2
= limit
->p2
.p2_fast
;
820 clock
.p2
= limit
->p2
.p2_slow
;
822 if (target
< limit
->p2
.dot_limit
)
823 clock
.p2
= limit
->p2
.p2_slow
;
825 clock
.p2
= limit
->p2
.p2_fast
;
828 memset (best_clock
, 0, sizeof (*best_clock
));
830 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
832 for (clock
.m2
= limit
->m2
.min
;
833 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
834 /* m1 is always 0 in Pineview */
835 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
837 for (clock
.n
= limit
->n
.min
;
838 clock
.n
<= limit
->n
.max
; clock
.n
++) {
839 for (clock
.p1
= limit
->p1
.min
;
840 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
843 intel_clock(dev
, refclk
, &clock
);
845 if (!intel_PLL_is_valid(crtc
, &clock
))
848 this_err
= abs(clock
.dot
- target
);
849 if (this_err
< err
) {
858 return (err
!= target
);
862 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
863 int target
, int refclk
, intel_clock_t
*best_clock
)
865 struct drm_device
*dev
= crtc
->dev
;
866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
870 /* approximately equals target * 0.00585 */
871 int err_most
= (target
>> 8) + (target
>> 9);
874 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
877 if (HAS_PCH_SPLIT(dev
))
881 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
883 clock
.p2
= limit
->p2
.p2_fast
;
885 clock
.p2
= limit
->p2
.p2_slow
;
887 if (target
< limit
->p2
.dot_limit
)
888 clock
.p2
= limit
->p2
.p2_slow
;
890 clock
.p2
= limit
->p2
.p2_fast
;
893 memset(best_clock
, 0, sizeof(*best_clock
));
894 max_n
= limit
->n
.max
;
895 /* based on hardware requirement, prefer smaller n to precision */
896 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
897 /* based on hardware requirement, prefere larger m1,m2 */
898 for (clock
.m1
= limit
->m1
.max
;
899 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
900 for (clock
.m2
= limit
->m2
.max
;
901 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
902 for (clock
.p1
= limit
->p1
.max
;
903 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
906 intel_clock(dev
, refclk
, &clock
);
907 if (!intel_PLL_is_valid(crtc
, &clock
))
909 this_err
= abs(clock
.dot
- target
) ;
910 if (this_err
< err_most
) {
924 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
925 int target
, int refclk
, intel_clock_t
*best_clock
)
927 struct drm_device
*dev
= crtc
->dev
;
930 /* return directly when it is eDP */
934 if (target
< 200000) {
947 intel_clock(dev
, refclk
, &clock
);
948 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
952 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
954 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
955 int target
, int refclk
, intel_clock_t
*best_clock
)
958 if (target
< 200000) {
971 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
972 clock
.p
= (clock
.p1
* clock
.p2
);
973 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
975 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
980 intel_wait_for_vblank(struct drm_device
*dev
)
982 /* Wait for 20ms, i.e. one cycle at 50hz. */
984 mdelay(20); /* The kernel debugger cannot call msleep() */
989 /* Parameters have changed, update FBC info */
990 static void i8xx_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
992 struct drm_device
*dev
= crtc
->dev
;
993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
994 struct drm_framebuffer
*fb
= crtc
->fb
;
995 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
996 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
997 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
999 u32 fbc_ctl
, fbc_ctl2
;
1001 dev_priv
->cfb_pitch
= dev_priv
->cfb_size
/ FBC_LL_SIZE
;
1003 if (fb
->pitch
< dev_priv
->cfb_pitch
)
1004 dev_priv
->cfb_pitch
= fb
->pitch
;
1006 /* FBC_CTL wants 64B units */
1007 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1008 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1009 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1010 plane
= dev_priv
->cfb_plane
== 0 ? FBC_CTL_PLANEA
: FBC_CTL_PLANEB
;
1012 /* Clear old tags */
1013 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
1014 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
1017 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| plane
;
1018 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1019 fbc_ctl2
|= FBC_CTL_CPU_FENCE
;
1020 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
1021 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
1024 fbc_ctl
= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
1026 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
1027 fbc_ctl
|= (dev_priv
->cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
1028 fbc_ctl
|= (interval
& 0x2fff) << FBC_CTL_INTERVAL_SHIFT
;
1029 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1030 fbc_ctl
|= dev_priv
->cfb_fence
;
1031 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1033 DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1034 dev_priv
->cfb_pitch
, crtc
->y
, dev_priv
->cfb_plane
);
1037 void i8xx_disable_fbc(struct drm_device
*dev
)
1039 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1040 unsigned long timeout
= jiffies
+ msecs_to_jiffies(1);
1043 if (!I915_HAS_FBC(dev
))
1046 if (!(I915_READ(FBC_CONTROL
) & FBC_CTL_EN
))
1047 return; /* Already off, just return */
1049 /* Disable compression */
1050 fbc_ctl
= I915_READ(FBC_CONTROL
);
1051 fbc_ctl
&= ~FBC_CTL_EN
;
1052 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
1054 /* Wait for compressing bit to clear */
1055 while (I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) {
1056 if (time_after(jiffies
, timeout
)) {
1057 DRM_DEBUG_DRIVER("FBC idle timed out\n");
1063 intel_wait_for_vblank(dev
);
1065 DRM_DEBUG_KMS("disabled FBC\n");
1068 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
1070 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1072 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
1075 static void g4x_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1077 struct drm_device
*dev
= crtc
->dev
;
1078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1079 struct drm_framebuffer
*fb
= crtc
->fb
;
1080 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1081 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1082 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1083 int plane
= (intel_crtc
->plane
== 0 ? DPFC_CTL_PLANEA
:
1085 unsigned long stall_watermark
= 200;
1088 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1089 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1090 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1092 dpfc_ctl
= plane
| DPFC_SR_EN
| DPFC_CTL_LIMIT_1X
;
1093 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1094 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
;
1095 I915_WRITE(DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1097 I915_WRITE(DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1100 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1101 I915_WRITE(DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1102 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1103 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1104 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
1107 I915_WRITE(DPFC_CONTROL
, I915_READ(DPFC_CONTROL
) | DPFC_CTL_EN
);
1109 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1112 void g4x_disable_fbc(struct drm_device
*dev
)
1114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1117 /* Disable compression */
1118 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
1119 dpfc_ctl
&= ~DPFC_CTL_EN
;
1120 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
1121 intel_wait_for_vblank(dev
);
1123 DRM_DEBUG_KMS("disabled FBC\n");
1126 static bool g4x_fbc_enabled(struct drm_device
*dev
)
1128 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1130 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
1133 static void ironlake_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1135 struct drm_device
*dev
= crtc
->dev
;
1136 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1137 struct drm_framebuffer
*fb
= crtc
->fb
;
1138 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
1139 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(intel_fb
->obj
);
1140 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1141 int plane
= (intel_crtc
->plane
== 0) ? DPFC_CTL_PLANEA
:
1143 unsigned long stall_watermark
= 200;
1146 dev_priv
->cfb_pitch
= (dev_priv
->cfb_pitch
/ 64) - 1;
1147 dev_priv
->cfb_fence
= obj_priv
->fence_reg
;
1148 dev_priv
->cfb_plane
= intel_crtc
->plane
;
1150 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1151 dpfc_ctl
&= DPFC_RESERVED
;
1152 dpfc_ctl
|= (plane
| DPFC_CTL_LIMIT_1X
);
1153 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1154 dpfc_ctl
|= (DPFC_CTL_FENCE_EN
| dev_priv
->cfb_fence
);
1155 I915_WRITE(ILK_DPFC_CHICKEN
, DPFC_HT_MODIFY
);
1157 I915_WRITE(ILK_DPFC_CHICKEN
, ~DPFC_HT_MODIFY
);
1160 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1161 I915_WRITE(ILK_DPFC_RECOMP_CTL
, DPFC_RECOMP_STALL_EN
|
1162 (stall_watermark
<< DPFC_RECOMP_STALL_WM_SHIFT
) |
1163 (interval
<< DPFC_RECOMP_TIMER_COUNT_SHIFT
));
1164 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
1165 I915_WRITE(ILK_FBC_RT_BASE
, obj_priv
->gtt_offset
| ILK_FBC_RT_VALID
);
1167 I915_WRITE(ILK_DPFC_CONTROL
, I915_READ(ILK_DPFC_CONTROL
) |
1170 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc
->plane
);
1173 void ironlake_disable_fbc(struct drm_device
*dev
)
1175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1178 /* Disable compression */
1179 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
1180 dpfc_ctl
&= ~DPFC_CTL_EN
;
1181 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
1182 intel_wait_for_vblank(dev
);
1184 DRM_DEBUG_KMS("disabled FBC\n");
1187 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
1189 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1191 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
1194 bool intel_fbc_enabled(struct drm_device
*dev
)
1196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1198 if (!dev_priv
->display
.fbc_enabled
)
1201 return dev_priv
->display
.fbc_enabled(dev
);
1204 void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
)
1206 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
1208 if (!dev_priv
->display
.enable_fbc
)
1211 dev_priv
->display
.enable_fbc(crtc
, interval
);
1214 void intel_disable_fbc(struct drm_device
*dev
)
1216 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1218 if (!dev_priv
->display
.disable_fbc
)
1221 dev_priv
->display
.disable_fbc(dev
);
1225 * intel_update_fbc - enable/disable FBC as needed
1226 * @crtc: CRTC to point the compressor at
1227 * @mode: mode in use
1229 * Set up the framebuffer compression hardware at mode set time. We
1230 * enable it if possible:
1231 * - plane A only (on pre-965)
1232 * - no pixel mulitply/line duplication
1233 * - no alpha buffer discard
1235 * - framebuffer <= 2048 in width, 1536 in height
1237 * We can't assume that any compression will take place (worst case),
1238 * so the compressed buffer has to be the same size as the uncompressed
1239 * one. It also must reside (along with the line length buffer) in
1242 * We need to enable/disable FBC on a global basis.
1244 static void intel_update_fbc(struct drm_crtc
*crtc
,
1245 struct drm_display_mode
*mode
)
1247 struct drm_device
*dev
= crtc
->dev
;
1248 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1249 struct drm_framebuffer
*fb
= crtc
->fb
;
1250 struct intel_framebuffer
*intel_fb
;
1251 struct drm_i915_gem_object
*obj_priv
;
1252 struct drm_crtc
*tmp_crtc
;
1253 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1254 int plane
= intel_crtc
->plane
;
1255 int crtcs_enabled
= 0;
1257 DRM_DEBUG_KMS("\n");
1259 if (!i915_powersave
)
1262 if (!I915_HAS_FBC(dev
))
1268 intel_fb
= to_intel_framebuffer(fb
);
1269 obj_priv
= to_intel_bo(intel_fb
->obj
);
1272 * If FBC is already on, we just have to verify that we can
1273 * keep it that way...
1274 * Need to disable if:
1275 * - more than one pipe is active
1276 * - changing FBC params (stride, fence, mode)
1277 * - new fb is too large to fit in compressed buffer
1278 * - going to an unsupported config (interlace, pixel multiply, etc.)
1280 list_for_each_entry(tmp_crtc
, &dev
->mode_config
.crtc_list
, head
) {
1281 if (tmp_crtc
->enabled
)
1284 DRM_DEBUG_KMS("%d pipes active\n", crtcs_enabled
);
1285 if (crtcs_enabled
> 1) {
1286 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1287 dev_priv
->no_fbc_reason
= FBC_MULTIPLE_PIPES
;
1290 if (intel_fb
->obj
->size
> dev_priv
->cfb_size
) {
1291 DRM_DEBUG_KMS("framebuffer too large, disabling "
1293 dev_priv
->no_fbc_reason
= FBC_STOLEN_TOO_SMALL
;
1296 if ((mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
1297 (mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
1298 DRM_DEBUG_KMS("mode incompatible with compression, "
1300 dev_priv
->no_fbc_reason
= FBC_UNSUPPORTED_MODE
;
1303 if ((mode
->hdisplay
> 2048) ||
1304 (mode
->vdisplay
> 1536)) {
1305 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1306 dev_priv
->no_fbc_reason
= FBC_MODE_TOO_LARGE
;
1309 if ((IS_I915GM(dev
) || IS_I945GM(dev
)) && plane
!= 0) {
1310 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1311 dev_priv
->no_fbc_reason
= FBC_BAD_PLANE
;
1314 if (obj_priv
->tiling_mode
!= I915_TILING_X
) {
1315 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1316 dev_priv
->no_fbc_reason
= FBC_NOT_TILED
;
1320 /* If the kernel debugger is active, always disable compression */
1321 if (in_dbg_master())
1324 if (intel_fbc_enabled(dev
)) {
1325 /* We can re-enable it in this case, but need to update pitch */
1326 if ((fb
->pitch
> dev_priv
->cfb_pitch
) ||
1327 (obj_priv
->fence_reg
!= dev_priv
->cfb_fence
) ||
1328 (plane
!= dev_priv
->cfb_plane
))
1329 intel_disable_fbc(dev
);
1332 /* Now try to turn it back on if possible */
1333 if (!intel_fbc_enabled(dev
))
1334 intel_enable_fbc(crtc
, 500);
1339 /* Multiple disables should be harmless */
1340 if (intel_fbc_enabled(dev
)) {
1341 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1342 intel_disable_fbc(dev
);
1347 intel_pin_and_fence_fb_obj(struct drm_device
*dev
, struct drm_gem_object
*obj
)
1349 struct drm_i915_gem_object
*obj_priv
= to_intel_bo(obj
);
1353 switch (obj_priv
->tiling_mode
) {
1354 case I915_TILING_NONE
:
1355 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1356 alignment
= 128 * 1024;
1357 else if (IS_I965G(dev
))
1358 alignment
= 4 * 1024;
1360 alignment
= 64 * 1024;
1363 /* pin() will align the object as required by fence */
1367 /* FIXME: Is this true? */
1368 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1374 ret
= i915_gem_object_pin(obj
, alignment
);
1378 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1379 * fence, whereas 965+ only requires a fence if using
1380 * framebuffer compression. For simplicity, we always install
1381 * a fence as the cost is not that onerous.
1383 if (obj_priv
->fence_reg
== I915_FENCE_REG_NONE
&&
1384 obj_priv
->tiling_mode
!= I915_TILING_NONE
) {
1385 ret
= i915_gem_object_get_fence_reg(obj
);
1387 i915_gem_object_unpin(obj
);
1395 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1397 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1400 struct drm_device
*dev
= crtc
->dev
;
1401 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1402 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1403 struct intel_framebuffer
*intel_fb
;
1404 struct drm_i915_gem_object
*obj_priv
;
1405 struct drm_gem_object
*obj
;
1406 int plane
= intel_crtc
->plane
;
1407 unsigned long Start
, Offset
;
1408 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1409 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1410 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1411 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1412 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1420 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1424 intel_fb
= to_intel_framebuffer(fb
);
1425 obj
= intel_fb
->obj
;
1426 obj_priv
= to_intel_bo(obj
);
1428 dspcntr
= I915_READ(dspcntr_reg
);
1429 /* Mask out pixel format bits in case we change it */
1430 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1431 switch (fb
->bits_per_pixel
) {
1433 dspcntr
|= DISPPLANE_8BPP
;
1436 if (fb
->depth
== 15)
1437 dspcntr
|= DISPPLANE_15_16BPP
;
1439 dspcntr
|= DISPPLANE_16BPP
;
1443 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1446 DRM_ERROR("Unknown color depth\n");
1449 if (IS_I965G(dev
)) {
1450 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1451 dspcntr
|= DISPPLANE_TILED
;
1453 dspcntr
&= ~DISPPLANE_TILED
;
1456 if (IS_IRONLAKE(dev
))
1458 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1460 I915_WRITE(dspcntr_reg
, dspcntr
);
1462 Start
= obj_priv
->gtt_offset
;
1463 Offset
= y
* fb
->pitch
+ x
* (fb
->bits_per_pixel
/ 8);
1465 DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start
, Offset
, x
, y
);
1466 I915_WRITE(dspstride
, fb
->pitch
);
1467 if (IS_I965G(dev
)) {
1468 I915_WRITE(dspbase
, Offset
);
1470 I915_WRITE(dspsurf
, Start
);
1472 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1474 I915_WRITE(dspbase
, Start
+ Offset
);
1478 if ((IS_I965G(dev
) || plane
== 0))
1479 intel_update_fbc(crtc
, &crtc
->mode
);
1481 intel_wait_for_vblank(dev
);
1482 intel_increase_pllclock(crtc
, true);
1488 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
1489 struct drm_framebuffer
*old_fb
)
1491 struct drm_device
*dev
= crtc
->dev
;
1492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1493 struct drm_i915_master_private
*master_priv
;
1494 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1495 struct intel_framebuffer
*intel_fb
;
1496 struct drm_i915_gem_object
*obj_priv
;
1497 struct drm_gem_object
*obj
;
1498 int pipe
= intel_crtc
->pipe
;
1499 int plane
= intel_crtc
->plane
;
1500 unsigned long Start
, Offset
;
1501 int dspbase
= (plane
== 0 ? DSPAADDR
: DSPBADDR
);
1502 int dspsurf
= (plane
== 0 ? DSPASURF
: DSPBSURF
);
1503 int dspstride
= (plane
== 0) ? DSPASTRIDE
: DSPBSTRIDE
;
1504 int dsptileoff
= (plane
== 0 ? DSPATILEOFF
: DSPBTILEOFF
);
1505 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1511 DRM_DEBUG_KMS("No FB bound\n");
1520 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1524 intel_fb
= to_intel_framebuffer(crtc
->fb
);
1525 obj
= intel_fb
->obj
;
1526 obj_priv
= to_intel_bo(obj
);
1528 mutex_lock(&dev
->struct_mutex
);
1529 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
1531 mutex_unlock(&dev
->struct_mutex
);
1535 ret
= i915_gem_object_set_to_display_plane(obj
);
1537 i915_gem_object_unpin(obj
);
1538 mutex_unlock(&dev
->struct_mutex
);
1542 dspcntr
= I915_READ(dspcntr_reg
);
1543 /* Mask out pixel format bits in case we change it */
1544 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
1545 switch (crtc
->fb
->bits_per_pixel
) {
1547 dspcntr
|= DISPPLANE_8BPP
;
1550 if (crtc
->fb
->depth
== 15)
1551 dspcntr
|= DISPPLANE_15_16BPP
;
1553 dspcntr
|= DISPPLANE_16BPP
;
1557 if (crtc
->fb
->depth
== 30)
1558 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
1560 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
1563 DRM_ERROR("Unknown color depth\n");
1564 i915_gem_object_unpin(obj
);
1565 mutex_unlock(&dev
->struct_mutex
);
1568 if (IS_I965G(dev
)) {
1569 if (obj_priv
->tiling_mode
!= I915_TILING_NONE
)
1570 dspcntr
|= DISPPLANE_TILED
;
1572 dspcntr
&= ~DISPPLANE_TILED
;
1575 if (HAS_PCH_SPLIT(dev
))
1577 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
1579 I915_WRITE(dspcntr_reg
, dspcntr
);
1581 Start
= obj_priv
->gtt_offset
;
1582 Offset
= y
* crtc
->fb
->pitch
+ x
* (crtc
->fb
->bits_per_pixel
/ 8);
1584 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1585 Start
, Offset
, x
, y
, crtc
->fb
->pitch
);
1586 I915_WRITE(dspstride
, crtc
->fb
->pitch
);
1587 if (IS_I965G(dev
)) {
1588 I915_WRITE(dspbase
, Offset
);
1590 I915_WRITE(dspsurf
, Start
);
1592 I915_WRITE(dsptileoff
, (y
<< 16) | x
);
1594 I915_WRITE(dspbase
, Start
+ Offset
);
1598 if ((IS_I965G(dev
) || plane
== 0))
1599 intel_update_fbc(crtc
, &crtc
->mode
);
1601 intel_wait_for_vblank(dev
);
1604 intel_fb
= to_intel_framebuffer(old_fb
);
1605 obj_priv
= to_intel_bo(intel_fb
->obj
);
1606 i915_gem_object_unpin(intel_fb
->obj
);
1608 intel_increase_pllclock(crtc
, true);
1610 mutex_unlock(&dev
->struct_mutex
);
1612 if (!dev
->primary
->master
)
1615 master_priv
= dev
->primary
->master
->driver_priv
;
1616 if (!master_priv
->sarea_priv
)
1620 master_priv
->sarea_priv
->pipeB_x
= x
;
1621 master_priv
->sarea_priv
->pipeB_y
= y
;
1623 master_priv
->sarea_priv
->pipeA_x
= x
;
1624 master_priv
->sarea_priv
->pipeA_y
= y
;
1630 /* Disable the VGA plane that we never use */
1631 static void i915_disable_vga (struct drm_device
*dev
)
1633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1637 if (HAS_PCH_SPLIT(dev
))
1638 vga_reg
= CPU_VGACNTRL
;
1642 if (I915_READ(vga_reg
) & VGA_DISP_DISABLE
)
1645 I915_WRITE8(VGA_SR_INDEX
, 1);
1646 sr1
= I915_READ8(VGA_SR_DATA
);
1647 I915_WRITE8(VGA_SR_DATA
, sr1
| (1 << 5));
1650 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
1653 static void ironlake_disable_pll_edp (struct drm_crtc
*crtc
)
1655 struct drm_device
*dev
= crtc
->dev
;
1656 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1659 DRM_DEBUG_KMS("\n");
1660 dpa_ctl
= I915_READ(DP_A
);
1661 dpa_ctl
&= ~DP_PLL_ENABLE
;
1662 I915_WRITE(DP_A
, dpa_ctl
);
1665 static void ironlake_enable_pll_edp (struct drm_crtc
*crtc
)
1667 struct drm_device
*dev
= crtc
->dev
;
1668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1671 dpa_ctl
= I915_READ(DP_A
);
1672 dpa_ctl
|= DP_PLL_ENABLE
;
1673 I915_WRITE(DP_A
, dpa_ctl
);
1678 static void ironlake_set_pll_edp (struct drm_crtc
*crtc
, int clock
)
1680 struct drm_device
*dev
= crtc
->dev
;
1681 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1684 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
1685 dpa_ctl
= I915_READ(DP_A
);
1686 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
1688 if (clock
< 200000) {
1690 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
1691 /* workaround for 160Mhz:
1692 1) program 0x4600c bits 15:0 = 0x8124
1693 2) program 0x46010 bit 0 = 1
1694 3) program 0x46034 bit 24 = 1
1695 4) program 0x64000 bit 14 = 1
1697 temp
= I915_READ(0x4600c);
1699 I915_WRITE(0x4600c, temp
| 0x8124);
1701 temp
= I915_READ(0x46010);
1702 I915_WRITE(0x46010, temp
| 1);
1704 temp
= I915_READ(0x46034);
1705 I915_WRITE(0x46034, temp
| (1 << 24));
1707 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
1709 I915_WRITE(DP_A
, dpa_ctl
);
1714 /* The FDI link training functions for ILK/Ibexpeak. */
1715 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
1717 struct drm_device
*dev
= crtc
->dev
;
1718 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1719 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1720 int pipe
= intel_crtc
->pipe
;
1721 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1722 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1723 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1724 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1725 u32 temp
, tries
= 0;
1727 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1729 temp
= I915_READ(fdi_rx_imr_reg
);
1730 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1731 temp
&= ~FDI_RX_BIT_LOCK
;
1732 I915_WRITE(fdi_rx_imr_reg
, temp
);
1733 I915_READ(fdi_rx_imr_reg
);
1736 /* enable CPU FDI TX and PCH FDI RX */
1737 temp
= I915_READ(fdi_tx_reg
);
1738 temp
|= FDI_TX_ENABLE
;
1740 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1741 temp
&= ~FDI_LINK_TRAIN_NONE
;
1742 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1743 I915_WRITE(fdi_tx_reg
, temp
);
1744 I915_READ(fdi_tx_reg
);
1746 temp
= I915_READ(fdi_rx_reg
);
1747 temp
&= ~FDI_LINK_TRAIN_NONE
;
1748 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1749 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1750 I915_READ(fdi_rx_reg
);
1753 for (tries
= 0; tries
< 5; tries
++) {
1754 temp
= I915_READ(fdi_rx_iir_reg
);
1755 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1757 if ((temp
& FDI_RX_BIT_LOCK
)) {
1758 DRM_DEBUG_KMS("FDI train 1 done.\n");
1759 I915_WRITE(fdi_rx_iir_reg
,
1760 temp
| FDI_RX_BIT_LOCK
);
1765 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1768 temp
= I915_READ(fdi_tx_reg
);
1769 temp
&= ~FDI_LINK_TRAIN_NONE
;
1770 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1771 I915_WRITE(fdi_tx_reg
, temp
);
1773 temp
= I915_READ(fdi_rx_reg
);
1774 temp
&= ~FDI_LINK_TRAIN_NONE
;
1775 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1776 I915_WRITE(fdi_rx_reg
, temp
);
1781 for (tries
= 0; tries
< 5; tries
++) {
1782 temp
= I915_READ(fdi_rx_iir_reg
);
1783 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1785 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1786 I915_WRITE(fdi_rx_iir_reg
,
1787 temp
| FDI_RX_SYMBOL_LOCK
);
1788 DRM_DEBUG_KMS("FDI train 2 done.\n");
1793 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1795 DRM_DEBUG_KMS("FDI train done\n");
1798 static int snb_b_fdi_train_param
[] = {
1799 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
1800 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
1801 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
1802 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
1805 /* The FDI link training functions for SNB/Cougarpoint. */
1806 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
1808 struct drm_device
*dev
= crtc
->dev
;
1809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1810 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1811 int pipe
= intel_crtc
->pipe
;
1812 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1813 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1814 int fdi_rx_iir_reg
= (pipe
== 0) ? FDI_RXA_IIR
: FDI_RXB_IIR
;
1815 int fdi_rx_imr_reg
= (pipe
== 0) ? FDI_RXA_IMR
: FDI_RXB_IMR
;
1818 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1820 temp
= I915_READ(fdi_rx_imr_reg
);
1821 temp
&= ~FDI_RX_SYMBOL_LOCK
;
1822 temp
&= ~FDI_RX_BIT_LOCK
;
1823 I915_WRITE(fdi_rx_imr_reg
, temp
);
1824 I915_READ(fdi_rx_imr_reg
);
1827 /* enable CPU FDI TX and PCH FDI RX */
1828 temp
= I915_READ(fdi_tx_reg
);
1829 temp
|= FDI_TX_ENABLE
;
1831 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1832 temp
&= ~FDI_LINK_TRAIN_NONE
;
1833 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1834 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1836 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1837 I915_WRITE(fdi_tx_reg
, temp
);
1838 I915_READ(fdi_tx_reg
);
1840 temp
= I915_READ(fdi_rx_reg
);
1841 if (HAS_PCH_CPT(dev
)) {
1842 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1843 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
1845 temp
&= ~FDI_LINK_TRAIN_NONE
;
1846 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
1848 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENABLE
);
1849 I915_READ(fdi_rx_reg
);
1852 for (i
= 0; i
< 4; i
++ ) {
1853 temp
= I915_READ(fdi_tx_reg
);
1854 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1855 temp
|= snb_b_fdi_train_param
[i
];
1856 I915_WRITE(fdi_tx_reg
, temp
);
1859 temp
= I915_READ(fdi_rx_iir_reg
);
1860 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1862 if (temp
& FDI_RX_BIT_LOCK
) {
1863 I915_WRITE(fdi_rx_iir_reg
,
1864 temp
| FDI_RX_BIT_LOCK
);
1865 DRM_DEBUG_KMS("FDI train 1 done.\n");
1870 DRM_DEBUG_KMS("FDI train 1 fail!\n");
1873 temp
= I915_READ(fdi_tx_reg
);
1874 temp
&= ~FDI_LINK_TRAIN_NONE
;
1875 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1877 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1879 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
1881 I915_WRITE(fdi_tx_reg
, temp
);
1883 temp
= I915_READ(fdi_rx_reg
);
1884 if (HAS_PCH_CPT(dev
)) {
1885 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
1886 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
1888 temp
&= ~FDI_LINK_TRAIN_NONE
;
1889 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
1891 I915_WRITE(fdi_rx_reg
, temp
);
1894 for (i
= 0; i
< 4; i
++ ) {
1895 temp
= I915_READ(fdi_tx_reg
);
1896 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
1897 temp
|= snb_b_fdi_train_param
[i
];
1898 I915_WRITE(fdi_tx_reg
, temp
);
1901 temp
= I915_READ(fdi_rx_iir_reg
);
1902 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
1904 if (temp
& FDI_RX_SYMBOL_LOCK
) {
1905 I915_WRITE(fdi_rx_iir_reg
,
1906 temp
| FDI_RX_SYMBOL_LOCK
);
1907 DRM_DEBUG_KMS("FDI train 2 done.\n");
1912 DRM_DEBUG_KMS("FDI train 2 fail!\n");
1914 DRM_DEBUG_KMS("FDI train done.\n");
1917 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
1919 struct drm_device
*dev
= crtc
->dev
;
1920 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1921 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1922 int pipe
= intel_crtc
->pipe
;
1923 int plane
= intel_crtc
->plane
;
1924 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
1925 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
1926 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
1927 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
1928 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
1929 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
1930 int transconf_reg
= (pipe
== 0) ? TRANSACONF
: TRANSBCONF
;
1931 int pf_ctl_reg
= (pipe
== 0) ? PFA_CTL_1
: PFB_CTL_1
;
1932 int pf_win_size
= (pipe
== 0) ? PFA_WIN_SZ
: PFB_WIN_SZ
;
1933 int pf_win_pos
= (pipe
== 0) ? PFA_WIN_POS
: PFB_WIN_POS
;
1934 int cpu_htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
1935 int cpu_hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
1936 int cpu_hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
1937 int cpu_vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
1938 int cpu_vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
1939 int cpu_vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
1940 int trans_htot_reg
= (pipe
== 0) ? TRANS_HTOTAL_A
: TRANS_HTOTAL_B
;
1941 int trans_hblank_reg
= (pipe
== 0) ? TRANS_HBLANK_A
: TRANS_HBLANK_B
;
1942 int trans_hsync_reg
= (pipe
== 0) ? TRANS_HSYNC_A
: TRANS_HSYNC_B
;
1943 int trans_vtot_reg
= (pipe
== 0) ? TRANS_VTOTAL_A
: TRANS_VTOTAL_B
;
1944 int trans_vblank_reg
= (pipe
== 0) ? TRANS_VBLANK_A
: TRANS_VBLANK_B
;
1945 int trans_vsync_reg
= (pipe
== 0) ? TRANS_VSYNC_A
: TRANS_VSYNC_B
;
1946 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
1951 temp
= I915_READ(pipeconf_reg
);
1952 pipe_bpc
= temp
& PIPE_BPC_MASK
;
1954 /* XXX: When our outputs are all unaware of DPMS modes other than off
1955 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1958 case DRM_MODE_DPMS_ON
:
1959 case DRM_MODE_DPMS_STANDBY
:
1960 case DRM_MODE_DPMS_SUSPEND
:
1961 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe
);
1963 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
1964 temp
= I915_READ(PCH_LVDS
);
1965 if ((temp
& LVDS_PORT_EN
) == 0) {
1966 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
1967 POSTING_READ(PCH_LVDS
);
1972 /* enable eDP PLL */
1973 ironlake_enable_pll_edp(crtc
);
1976 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1977 temp
= I915_READ(fdi_rx_reg
);
1979 * make the BPC in FDI Rx be consistent with that in
1982 temp
&= ~(0x7 << 16);
1983 temp
|= (pipe_bpc
<< 11);
1985 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
1986 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
1987 I915_READ(fdi_rx_reg
);
1990 /* Switch from Rawclk to PCDclk */
1991 temp
= I915_READ(fdi_rx_reg
);
1992 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
1993 I915_READ(fdi_rx_reg
);
1996 /* Enable CPU FDI TX PLL, always on for Ironlake */
1997 temp
= I915_READ(fdi_tx_reg
);
1998 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
1999 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
2000 I915_READ(fdi_tx_reg
);
2005 /* Enable panel fitting for LVDS */
2006 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)
2007 || HAS_eDP
|| intel_pch_has_edp(crtc
)) {
2008 temp
= I915_READ(pf_ctl_reg
);
2009 I915_WRITE(pf_ctl_reg
, temp
| PF_ENABLE
| PF_FILTER_MED_3x3
);
2011 /* currently full aspect */
2012 I915_WRITE(pf_win_pos
, 0);
2014 I915_WRITE(pf_win_size
,
2015 (dev_priv
->panel_fixed_mode
->hdisplay
<< 16) |
2016 (dev_priv
->panel_fixed_mode
->vdisplay
));
2019 /* Enable CPU pipe */
2020 temp
= I915_READ(pipeconf_reg
);
2021 if ((temp
& PIPEACONF_ENABLE
) == 0) {
2022 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
2023 I915_READ(pipeconf_reg
);
2027 /* configure and enable CPU plane */
2028 temp
= I915_READ(dspcntr_reg
);
2029 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2030 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
2031 /* Flush the plane changes */
2032 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2036 /* For PCH output, training FDI link */
2038 gen6_fdi_link_train(crtc
);
2040 ironlake_fdi_link_train(crtc
);
2042 /* enable PCH DPLL */
2043 temp
= I915_READ(pch_dpll_reg
);
2044 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2045 I915_WRITE(pch_dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2046 I915_READ(pch_dpll_reg
);
2050 if (HAS_PCH_CPT(dev
)) {
2051 /* Be sure PCH DPLL SEL is set */
2052 temp
= I915_READ(PCH_DPLL_SEL
);
2053 if (trans_dpll_sel
== 0 &&
2054 (temp
& TRANSA_DPLL_ENABLE
) == 0)
2055 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
2056 else if (trans_dpll_sel
== 1 &&
2057 (temp
& TRANSB_DPLL_ENABLE
) == 0)
2058 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2059 I915_WRITE(PCH_DPLL_SEL
, temp
);
2060 I915_READ(PCH_DPLL_SEL
);
2063 /* set transcoder timing */
2064 I915_WRITE(trans_htot_reg
, I915_READ(cpu_htot_reg
));
2065 I915_WRITE(trans_hblank_reg
, I915_READ(cpu_hblank_reg
));
2066 I915_WRITE(trans_hsync_reg
, I915_READ(cpu_hsync_reg
));
2068 I915_WRITE(trans_vtot_reg
, I915_READ(cpu_vtot_reg
));
2069 I915_WRITE(trans_vblank_reg
, I915_READ(cpu_vblank_reg
));
2070 I915_WRITE(trans_vsync_reg
, I915_READ(cpu_vsync_reg
));
2072 /* enable normal train */
2073 temp
= I915_READ(fdi_tx_reg
);
2074 temp
&= ~FDI_LINK_TRAIN_NONE
;
2075 I915_WRITE(fdi_tx_reg
, temp
| FDI_LINK_TRAIN_NONE
|
2076 FDI_TX_ENHANCE_FRAME_ENABLE
);
2077 I915_READ(fdi_tx_reg
);
2079 temp
= I915_READ(fdi_rx_reg
);
2080 if (HAS_PCH_CPT(dev
)) {
2081 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2082 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2084 temp
&= ~FDI_LINK_TRAIN_NONE
;
2085 temp
|= FDI_LINK_TRAIN_NONE
;
2087 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2088 I915_READ(fdi_rx_reg
);
2090 /* wait one idle pattern time */
2093 /* For PCH DP, enable TRANS_DP_CTL */
2094 if (HAS_PCH_CPT(dev
) &&
2095 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
2096 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2099 reg
= I915_READ(trans_dp_ctl
);
2100 reg
&= ~TRANS_DP_PORT_SEL_MASK
;
2101 reg
= TRANS_DP_OUTPUT_ENABLE
|
2102 TRANS_DP_ENH_FRAMING
;
2104 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
2105 reg
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
2106 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
2107 reg
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
2109 switch (intel_trans_dp_port_sel(crtc
)) {
2111 reg
|= TRANS_DP_PORT_SEL_B
;
2114 reg
|= TRANS_DP_PORT_SEL_C
;
2117 reg
|= TRANS_DP_PORT_SEL_D
;
2120 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2121 reg
|= TRANS_DP_PORT_SEL_B
;
2125 I915_WRITE(trans_dp_ctl
, reg
);
2126 POSTING_READ(trans_dp_ctl
);
2129 /* enable PCH transcoder */
2130 temp
= I915_READ(transconf_reg
);
2132 * make the BPC in transcoder be consistent with
2133 * that in pipeconf reg.
2135 temp
&= ~PIPE_BPC_MASK
;
2137 I915_WRITE(transconf_reg
, temp
| TRANS_ENABLE
);
2138 I915_READ(transconf_reg
);
2140 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) == 0)
2145 intel_crtc_load_lut(crtc
);
2147 intel_update_fbc(crtc
, &crtc
->mode
);
2150 case DRM_MODE_DPMS_OFF
:
2151 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe
);
2153 drm_vblank_off(dev
, pipe
);
2154 /* Disable display plane */
2155 temp
= I915_READ(dspcntr_reg
);
2156 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2157 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2158 /* Flush the plane changes */
2159 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2160 I915_READ(dspbase_reg
);
2163 if (dev_priv
->cfb_plane
== plane
&&
2164 dev_priv
->display
.disable_fbc
)
2165 dev_priv
->display
.disable_fbc(dev
);
2167 i915_disable_vga(dev
);
2169 /* disable cpu pipe, disable after all planes disabled */
2170 temp
= I915_READ(pipeconf_reg
);
2171 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2172 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2173 I915_READ(pipeconf_reg
);
2175 /* wait for cpu pipe off, pipe state */
2176 while ((I915_READ(pipeconf_reg
) & I965_PIPECONF_ACTIVE
) != 0) {
2182 DRM_DEBUG_KMS("pipe %d off delay\n",
2188 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe
);
2193 temp
= I915_READ(pf_ctl_reg
);
2194 if ((temp
& PF_ENABLE
) != 0) {
2195 I915_WRITE(pf_ctl_reg
, temp
& ~PF_ENABLE
);
2196 I915_READ(pf_ctl_reg
);
2198 I915_WRITE(pf_win_size
, 0);
2199 POSTING_READ(pf_win_size
);
2202 /* disable CPU FDI tx and PCH FDI rx */
2203 temp
= I915_READ(fdi_tx_reg
);
2204 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_ENABLE
);
2205 I915_READ(fdi_tx_reg
);
2207 temp
= I915_READ(fdi_rx_reg
);
2208 /* BPC in FDI rx is consistent with that in pipeconf */
2209 temp
&= ~(0x07 << 16);
2210 temp
|= (pipe_bpc
<< 11);
2211 I915_WRITE(fdi_rx_reg
, temp
& ~FDI_RX_ENABLE
);
2212 I915_READ(fdi_rx_reg
);
2216 /* still set train pattern 1 */
2217 temp
= I915_READ(fdi_tx_reg
);
2218 temp
&= ~FDI_LINK_TRAIN_NONE
;
2219 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2220 I915_WRITE(fdi_tx_reg
, temp
);
2221 POSTING_READ(fdi_tx_reg
);
2223 temp
= I915_READ(fdi_rx_reg
);
2224 if (HAS_PCH_CPT(dev
)) {
2225 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2226 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2228 temp
&= ~FDI_LINK_TRAIN_NONE
;
2229 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2231 I915_WRITE(fdi_rx_reg
, temp
);
2232 POSTING_READ(fdi_rx_reg
);
2236 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
2237 temp
= I915_READ(PCH_LVDS
);
2238 I915_WRITE(PCH_LVDS
, temp
& ~LVDS_PORT_EN
);
2239 I915_READ(PCH_LVDS
);
2243 /* disable PCH transcoder */
2244 temp
= I915_READ(transconf_reg
);
2245 if ((temp
& TRANS_ENABLE
) != 0) {
2246 I915_WRITE(transconf_reg
, temp
& ~TRANS_ENABLE
);
2247 I915_READ(transconf_reg
);
2249 /* wait for PCH transcoder off, transcoder state */
2250 while ((I915_READ(transconf_reg
) & TRANS_STATE_ENABLE
) != 0) {
2256 DRM_DEBUG_KMS("transcoder %d off "
2263 temp
= I915_READ(transconf_reg
);
2264 /* BPC in transcoder is consistent with that in pipeconf */
2265 temp
&= ~PIPE_BPC_MASK
;
2267 I915_WRITE(transconf_reg
, temp
);
2268 I915_READ(transconf_reg
);
2271 if (HAS_PCH_CPT(dev
)) {
2272 /* disable TRANS_DP_CTL */
2273 int trans_dp_ctl
= (pipe
== 0) ? TRANS_DP_CTL_A
: TRANS_DP_CTL_B
;
2276 reg
= I915_READ(trans_dp_ctl
);
2277 reg
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
2278 I915_WRITE(trans_dp_ctl
, reg
);
2279 POSTING_READ(trans_dp_ctl
);
2281 /* disable DPLL_SEL */
2282 temp
= I915_READ(PCH_DPLL_SEL
);
2283 if (trans_dpll_sel
== 0)
2284 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
2286 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
2287 I915_WRITE(PCH_DPLL_SEL
, temp
);
2288 I915_READ(PCH_DPLL_SEL
);
2292 /* disable PCH DPLL */
2293 temp
= I915_READ(pch_dpll_reg
);
2294 I915_WRITE(pch_dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2295 I915_READ(pch_dpll_reg
);
2298 ironlake_disable_pll_edp(crtc
);
2301 /* Switch from PCDclk to Rawclk */
2302 temp
= I915_READ(fdi_rx_reg
);
2303 temp
&= ~FDI_SEL_PCDCLK
;
2304 I915_WRITE(fdi_rx_reg
, temp
);
2305 I915_READ(fdi_rx_reg
);
2307 /* Disable CPU FDI TX PLL */
2308 temp
= I915_READ(fdi_tx_reg
);
2309 I915_WRITE(fdi_tx_reg
, temp
& ~FDI_TX_PLL_ENABLE
);
2310 I915_READ(fdi_tx_reg
);
2313 temp
= I915_READ(fdi_rx_reg
);
2314 temp
&= ~FDI_RX_PLL_ENABLE
;
2315 I915_WRITE(fdi_rx_reg
, temp
);
2316 I915_READ(fdi_rx_reg
);
2318 /* Wait for the clocks to turn off. */
2324 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
2326 struct intel_overlay
*overlay
;
2329 if (!enable
&& intel_crtc
->overlay
) {
2330 overlay
= intel_crtc
->overlay
;
2331 mutex_lock(&overlay
->dev
->struct_mutex
);
2333 ret
= intel_overlay_switch_off(overlay
);
2337 ret
= intel_overlay_recover_from_interrupt(overlay
, 0);
2339 /* overlay doesn't react anymore. Usually
2340 * results in a black screen and an unkillable
2343 overlay
->hw_wedged
= HW_WEDGED
;
2347 mutex_unlock(&overlay
->dev
->struct_mutex
);
2349 /* Let userspace switch the overlay on again. In most cases userspace
2350 * has to recompute where to put it anyway. */
2355 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2357 struct drm_device
*dev
= crtc
->dev
;
2358 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2359 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2360 int pipe
= intel_crtc
->pipe
;
2361 int plane
= intel_crtc
->plane
;
2362 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
2363 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
2364 int dspbase_reg
= (plane
== 0) ? DSPAADDR
: DSPBADDR
;
2365 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
2368 /* XXX: When our outputs are all unaware of DPMS modes other than off
2369 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2372 case DRM_MODE_DPMS_ON
:
2373 case DRM_MODE_DPMS_STANDBY
:
2374 case DRM_MODE_DPMS_SUSPEND
:
2375 intel_update_watermarks(dev
);
2377 /* Enable the DPLL */
2378 temp
= I915_READ(dpll_reg
);
2379 if ((temp
& DPLL_VCO_ENABLE
) == 0) {
2380 I915_WRITE(dpll_reg
, temp
);
2381 I915_READ(dpll_reg
);
2382 /* Wait for the clocks to stabilize. */
2384 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2385 I915_READ(dpll_reg
);
2386 /* Wait for the clocks to stabilize. */
2388 I915_WRITE(dpll_reg
, temp
| DPLL_VCO_ENABLE
);
2389 I915_READ(dpll_reg
);
2390 /* Wait for the clocks to stabilize. */
2394 /* Enable the pipe */
2395 temp
= I915_READ(pipeconf_reg
);
2396 if ((temp
& PIPEACONF_ENABLE
) == 0)
2397 I915_WRITE(pipeconf_reg
, temp
| PIPEACONF_ENABLE
);
2399 /* Enable the plane */
2400 temp
= I915_READ(dspcntr_reg
);
2401 if ((temp
& DISPLAY_PLANE_ENABLE
) == 0) {
2402 I915_WRITE(dspcntr_reg
, temp
| DISPLAY_PLANE_ENABLE
);
2403 /* Flush the plane changes */
2404 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2407 intel_crtc_load_lut(crtc
);
2409 if ((IS_I965G(dev
) || plane
== 0))
2410 intel_update_fbc(crtc
, &crtc
->mode
);
2412 /* Give the overlay scaler a chance to enable if it's on this pipe */
2413 intel_crtc_dpms_overlay(intel_crtc
, true);
2415 case DRM_MODE_DPMS_OFF
:
2416 intel_update_watermarks(dev
);
2418 /* Give the overlay scaler a chance to disable if it's on this pipe */
2419 intel_crtc_dpms_overlay(intel_crtc
, false);
2420 drm_vblank_off(dev
, pipe
);
2422 if (dev_priv
->cfb_plane
== plane
&&
2423 dev_priv
->display
.disable_fbc
)
2424 dev_priv
->display
.disable_fbc(dev
);
2426 /* Disable the VGA plane that we never use */
2427 i915_disable_vga(dev
);
2429 /* Disable display plane */
2430 temp
= I915_READ(dspcntr_reg
);
2431 if ((temp
& DISPLAY_PLANE_ENABLE
) != 0) {
2432 I915_WRITE(dspcntr_reg
, temp
& ~DISPLAY_PLANE_ENABLE
);
2433 /* Flush the plane changes */
2434 I915_WRITE(dspbase_reg
, I915_READ(dspbase_reg
));
2435 I915_READ(dspbase_reg
);
2438 if (!IS_I9XX(dev
)) {
2439 /* Wait for vblank for the disable to take effect */
2440 intel_wait_for_vblank(dev
);
2443 /* Don't disable pipe A or pipe A PLLs if needed */
2444 if (pipeconf_reg
== PIPEACONF
&&
2445 (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2448 /* Next, disable display pipes */
2449 temp
= I915_READ(pipeconf_reg
);
2450 if ((temp
& PIPEACONF_ENABLE
) != 0) {
2451 I915_WRITE(pipeconf_reg
, temp
& ~PIPEACONF_ENABLE
);
2452 I915_READ(pipeconf_reg
);
2455 /* Wait for vblank for the disable to take effect. */
2456 intel_wait_for_vblank(dev
);
2458 temp
= I915_READ(dpll_reg
);
2459 if ((temp
& DPLL_VCO_ENABLE
) != 0) {
2460 I915_WRITE(dpll_reg
, temp
& ~DPLL_VCO_ENABLE
);
2461 I915_READ(dpll_reg
);
2464 /* Wait for the clocks to turn off. */
2471 * Sets the power management mode of the pipe and plane.
2473 * This code should probably grow support for turning the cursor off and back
2474 * on appropriately at the same time as we're turning the pipe off/on.
2476 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
2478 struct drm_device
*dev
= crtc
->dev
;
2479 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2480 struct drm_i915_master_private
*master_priv
;
2481 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2482 int pipe
= intel_crtc
->pipe
;
2485 dev_priv
->display
.dpms(crtc
, mode
);
2487 intel_crtc
->dpms_mode
= mode
;
2489 if (!dev
->primary
->master
)
2492 master_priv
= dev
->primary
->master
->driver_priv
;
2493 if (!master_priv
->sarea_priv
)
2496 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
2500 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2501 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2504 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
2505 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
2508 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe
);
2513 static void intel_crtc_prepare (struct drm_crtc
*crtc
)
2515 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2516 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
2519 static void intel_crtc_commit (struct drm_crtc
*crtc
)
2521 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
2522 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
2525 void intel_encoder_prepare (struct drm_encoder
*encoder
)
2527 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2528 /* lvds has its own version of prepare see intel_lvds_prepare */
2529 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
2532 void intel_encoder_commit (struct drm_encoder
*encoder
)
2534 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
2535 /* lvds has its own version of commit see intel_lvds_commit */
2536 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
2539 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
2540 struct drm_display_mode
*mode
,
2541 struct drm_display_mode
*adjusted_mode
)
2543 struct drm_device
*dev
= crtc
->dev
;
2544 if (HAS_PCH_SPLIT(dev
)) {
2545 /* FDI link clock is fixed at 2.7G */
2546 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
2552 static int i945_get_display_clock_speed(struct drm_device
*dev
)
2557 static int i915_get_display_clock_speed(struct drm_device
*dev
)
2562 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
2567 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
2571 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
2573 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
2576 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
2577 case GC_DISPLAY_CLOCK_333_MHZ
:
2580 case GC_DISPLAY_CLOCK_190_200_MHZ
:
2586 static int i865_get_display_clock_speed(struct drm_device
*dev
)
2591 static int i855_get_display_clock_speed(struct drm_device
*dev
)
2594 /* Assume that the hardware is in the high speed state. This
2595 * should be the default.
2597 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
2598 case GC_CLOCK_133_200
:
2599 case GC_CLOCK_100_200
:
2601 case GC_CLOCK_166_250
:
2603 case GC_CLOCK_100_133
:
2607 /* Shouldn't happen */
2611 static int i830_get_display_clock_speed(struct drm_device
*dev
)
2617 * Return the pipe currently connected to the panel fitter,
2618 * or -1 if the panel fitter is not present or not in use
2620 int intel_panel_fitter_pipe (struct drm_device
*dev
)
2622 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2625 /* i830 doesn't have a panel fitter */
2629 pfit_control
= I915_READ(PFIT_CONTROL
);
2631 /* See if the panel fitter is in use */
2632 if ((pfit_control
& PFIT_ENABLE
) == 0)
2635 /* 965 can place panel fitter on either pipe */
2637 return (pfit_control
>> 29) & 0x3;
2639 /* older chips can only use pipe 1 */
2652 fdi_reduce_ratio(u32
*num
, u32
*den
)
2654 while (*num
> 0xffffff || *den
> 0xffffff) {
2660 #define DATA_N 0x800000
2661 #define LINK_N 0x80000
2664 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
2665 int link_clock
, struct fdi_m_n
*m_n
)
2669 m_n
->tu
= 64; /* default size */
2671 temp
= (u64
) DATA_N
* pixel_clock
;
2672 temp
= div_u64(temp
, link_clock
);
2673 m_n
->gmch_m
= div_u64(temp
* bits_per_pixel
, nlanes
);
2674 m_n
->gmch_m
>>= 3; /* convert to bytes_per_pixel */
2675 m_n
->gmch_n
= DATA_N
;
2676 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
2678 temp
= (u64
) LINK_N
* pixel_clock
;
2679 m_n
->link_m
= div_u64(temp
, link_clock
);
2680 m_n
->link_n
= LINK_N
;
2681 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
2685 struct intel_watermark_params
{
2686 unsigned long fifo_size
;
2687 unsigned long max_wm
;
2688 unsigned long default_wm
;
2689 unsigned long guard_size
;
2690 unsigned long cacheline_size
;
2693 /* Pineview has different values for various configs */
2694 static struct intel_watermark_params pineview_display_wm
= {
2695 PINEVIEW_DISPLAY_FIFO
,
2699 PINEVIEW_FIFO_LINE_SIZE
2701 static struct intel_watermark_params pineview_display_hplloff_wm
= {
2702 PINEVIEW_DISPLAY_FIFO
,
2704 PINEVIEW_DFT_HPLLOFF_WM
,
2706 PINEVIEW_FIFO_LINE_SIZE
2708 static struct intel_watermark_params pineview_cursor_wm
= {
2709 PINEVIEW_CURSOR_FIFO
,
2710 PINEVIEW_CURSOR_MAX_WM
,
2711 PINEVIEW_CURSOR_DFT_WM
,
2712 PINEVIEW_CURSOR_GUARD_WM
,
2713 PINEVIEW_FIFO_LINE_SIZE
,
2715 static struct intel_watermark_params pineview_cursor_hplloff_wm
= {
2716 PINEVIEW_CURSOR_FIFO
,
2717 PINEVIEW_CURSOR_MAX_WM
,
2718 PINEVIEW_CURSOR_DFT_WM
,
2719 PINEVIEW_CURSOR_GUARD_WM
,
2720 PINEVIEW_FIFO_LINE_SIZE
2722 static struct intel_watermark_params g4x_wm_info
= {
2729 static struct intel_watermark_params g4x_cursor_wm_info
= {
2736 static struct intel_watermark_params i965_cursor_wm_info
= {
2741 I915_FIFO_LINE_SIZE
,
2743 static struct intel_watermark_params i945_wm_info
= {
2750 static struct intel_watermark_params i915_wm_info
= {
2757 static struct intel_watermark_params i855_wm_info
= {
2764 static struct intel_watermark_params i830_wm_info
= {
2772 static struct intel_watermark_params ironlake_display_wm_info
= {
2780 static struct intel_watermark_params ironlake_cursor_wm_info
= {
2788 static struct intel_watermark_params ironlake_display_srwm_info
= {
2789 ILK_DISPLAY_SR_FIFO
,
2790 ILK_DISPLAY_MAX_SRWM
,
2791 ILK_DISPLAY_DFT_SRWM
,
2796 static struct intel_watermark_params ironlake_cursor_srwm_info
= {
2798 ILK_CURSOR_MAX_SRWM
,
2799 ILK_CURSOR_DFT_SRWM
,
2805 * intel_calculate_wm - calculate watermark level
2806 * @clock_in_khz: pixel clock
2807 * @wm: chip FIFO params
2808 * @pixel_size: display pixel size
2809 * @latency_ns: memory latency for the platform
2811 * Calculate the watermark level (the level at which the display plane will
2812 * start fetching from memory again). Each chip has a different display
2813 * FIFO size and allocation, so the caller needs to figure that out and pass
2814 * in the correct intel_watermark_params structure.
2816 * As the pixel clock runs, the FIFO will be drained at a rate that depends
2817 * on the pixel size. When it reaches the watermark level, it'll start
2818 * fetching FIFO line sized based chunks from memory until the FIFO fills
2819 * past the watermark point. If the FIFO drains completely, a FIFO underrun
2820 * will occur, and a display engine hang could result.
2822 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
2823 struct intel_watermark_params
*wm
,
2825 unsigned long latency_ns
)
2827 long entries_required
, wm_size
;
2830 * Note: we need to make sure we don't overflow for various clock &
2832 * clocks go from a few thousand to several hundred thousand.
2833 * latency is usually a few thousand
2835 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
2837 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
2839 DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required
);
2841 wm_size
= wm
->fifo_size
- (entries_required
+ wm
->guard_size
);
2843 DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size
);
2845 /* Don't promote wm_size to unsigned... */
2846 if (wm_size
> (long)wm
->max_wm
)
2847 wm_size
= wm
->max_wm
;
2849 wm_size
= wm
->default_wm
;
2850 DRM_ERROR("Insufficient FIFO for plane, expect flickering:"
2851 " entries required = %ld, available = %lu.\n",
2852 entries_required
+ wm
->guard_size
,
2859 struct cxsr_latency
{
2862 unsigned long fsb_freq
;
2863 unsigned long mem_freq
;
2864 unsigned long display_sr
;
2865 unsigned long display_hpll_disable
;
2866 unsigned long cursor_sr
;
2867 unsigned long cursor_hpll_disable
;
2870 static struct cxsr_latency cxsr_latency_table
[] = {
2871 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
2872 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
2873 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
2874 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
2875 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
2877 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
2878 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
2879 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
2880 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
2881 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
2883 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
2884 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
2885 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
2886 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
2887 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
2889 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
2890 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
2891 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
2892 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
2893 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
2895 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
2896 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
2897 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
2898 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
2899 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
2901 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
2902 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
2903 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
2904 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
2905 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
2908 static struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
, int is_ddr3
,
2912 struct cxsr_latency
*latency
;
2914 if (fsb
== 0 || mem
== 0)
2917 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
2918 latency
= &cxsr_latency_table
[i
];
2919 if (is_desktop
== latency
->is_desktop
&&
2920 is_ddr3
== latency
->is_ddr3
&&
2921 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
2925 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2930 static void pineview_disable_cxsr(struct drm_device
*dev
)
2932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2935 /* deactivate cxsr */
2936 reg
= I915_READ(DSPFW3
);
2937 reg
&= ~(PINEVIEW_SELF_REFRESH_EN
);
2938 I915_WRITE(DSPFW3
, reg
);
2939 DRM_INFO("Big FIFO is disabled\n");
2943 * Latency for FIFO fetches is dependent on several factors:
2944 * - memory configuration (speed, channels)
2946 * - current MCH state
2947 * It can be fairly high in some situations, so here we assume a fairly
2948 * pessimal value. It's a tradeoff between extra memory fetches (if we
2949 * set this value too high, the FIFO will fetch frequently to stay full)
2950 * and power consumption (set it too low to save power and we might see
2951 * FIFO underruns and display "flicker").
2953 * A value of 5us seems to be a good balance; safe for very low end
2954 * platforms but not overly aggressive on lower latency configs.
2956 static const int latency_ns
= 5000;
2958 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
2960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2961 uint32_t dsparb
= I915_READ(DSPARB
);
2964 size
= dsparb
& 0x7f;
2966 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
2968 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2969 plane
? "B" : "A", size
);
2974 static int i85x_get_fifo_size(struct drm_device
*dev
, int plane
)
2976 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2977 uint32_t dsparb
= I915_READ(DSPARB
);
2980 size
= dsparb
& 0x1ff;
2982 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
2983 size
>>= 1; /* Convert to cachelines */
2985 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
2986 plane
? "B" : "A", size
);
2991 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
2993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2994 uint32_t dsparb
= I915_READ(DSPARB
);
2997 size
= dsparb
& 0x7f;
2998 size
>>= 2; /* Convert to cachelines */
3000 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3007 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
3009 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3010 uint32_t dsparb
= I915_READ(DSPARB
);
3013 size
= dsparb
& 0x7f;
3014 size
>>= 1; /* Convert to cachelines */
3016 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
3017 plane
? "B" : "A", size
);
3022 static void pineview_update_wm(struct drm_device
*dev
, int planea_clock
,
3023 int planeb_clock
, int sr_hdisplay
, int unused
,
3026 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3029 struct cxsr_latency
*latency
;
3032 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
3033 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
3035 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3036 pineview_disable_cxsr(dev
);
3040 if (!planea_clock
|| !planeb_clock
) {
3041 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3044 wm
= intel_calculate_wm(sr_clock
, &pineview_display_wm
,
3045 pixel_size
, latency
->display_sr
);
3046 reg
= I915_READ(DSPFW1
);
3047 reg
&= ~DSPFW_SR_MASK
;
3048 reg
|= wm
<< DSPFW_SR_SHIFT
;
3049 I915_WRITE(DSPFW1
, reg
);
3050 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
3053 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_wm
,
3054 pixel_size
, latency
->cursor_sr
);
3055 reg
= I915_READ(DSPFW3
);
3056 reg
&= ~DSPFW_CURSOR_SR_MASK
;
3057 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
3058 I915_WRITE(DSPFW3
, reg
);
3060 /* Display HPLL off SR */
3061 wm
= intel_calculate_wm(sr_clock
, &pineview_display_hplloff_wm
,
3062 pixel_size
, latency
->display_hpll_disable
);
3063 reg
= I915_READ(DSPFW3
);
3064 reg
&= ~DSPFW_HPLL_SR_MASK
;
3065 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
3066 I915_WRITE(DSPFW3
, reg
);
3068 /* cursor HPLL off SR */
3069 wm
= intel_calculate_wm(sr_clock
, &pineview_cursor_hplloff_wm
,
3070 pixel_size
, latency
->cursor_hpll_disable
);
3071 reg
= I915_READ(DSPFW3
);
3072 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
3073 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
3074 I915_WRITE(DSPFW3
, reg
);
3075 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
3078 reg
= I915_READ(DSPFW3
);
3079 reg
|= PINEVIEW_SELF_REFRESH_EN
;
3080 I915_WRITE(DSPFW3
, reg
);
3081 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3083 pineview_disable_cxsr(dev
);
3084 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3088 static void g4x_update_wm(struct drm_device
*dev
, int planea_clock
,
3089 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3092 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3093 int total_size
, cacheline_size
;
3094 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
, cursor_sr
;
3095 struct intel_watermark_params planea_params
, planeb_params
;
3096 unsigned long line_time_us
;
3097 int sr_clock
, sr_entries
= 0, entries_required
;
3099 /* Create copies of the base settings for each pipe */
3100 planea_params
= planeb_params
= g4x_wm_info
;
3102 /* Grab a couple of global values before we overwrite them */
3103 total_size
= planea_params
.fifo_size
;
3104 cacheline_size
= planea_params
.cacheline_size
;
3107 * Note: we need to make sure we don't overflow for various clock &
3109 * clocks go from a few thousand to several hundred thousand.
3110 * latency is usually a few thousand
3112 entries_required
= ((planea_clock
/ 1000) * pixel_size
* latency_ns
) /
3114 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3115 planea_wm
= entries_required
+ planea_params
.guard_size
;
3117 entries_required
= ((planeb_clock
/ 1000) * pixel_size
* latency_ns
) /
3119 entries_required
= DIV_ROUND_UP(entries_required
, G4X_FIFO_LINE_SIZE
);
3120 planeb_wm
= entries_required
+ planeb_params
.guard_size
;
3122 cursora_wm
= cursorb_wm
= 16;
3125 DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3127 /* Calc sr entries for one plane configs */
3128 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3129 /* self-refresh has much higher latency */
3130 static const int sr_latency_ns
= 12000;
3132 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3133 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3135 /* Use ns/us then divide to preserve precision */
3136 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3137 pixel_size
* sr_hdisplay
;
3138 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3140 entries_required
= (((sr_latency_ns
/ line_time_us
) +
3141 1000) / 1000) * pixel_size
* 64;
3142 entries_required
= DIV_ROUND_UP(entries_required
,
3143 g4x_cursor_wm_info
.cacheline_size
);
3144 cursor_sr
= entries_required
+ g4x_cursor_wm_info
.guard_size
;
3146 if (cursor_sr
> g4x_cursor_wm_info
.max_wm
)
3147 cursor_sr
= g4x_cursor_wm_info
.max_wm
;
3148 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3149 "cursor %d\n", sr_entries
, cursor_sr
);
3151 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3153 /* Turn off self refresh if both pipes are enabled */
3154 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3158 DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3159 planea_wm
, planeb_wm
, sr_entries
);
3164 I915_WRITE(DSPFW1
, (sr_entries
<< DSPFW_SR_SHIFT
) |
3165 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
3166 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) | planea_wm
);
3167 I915_WRITE(DSPFW2
, (I915_READ(DSPFW2
) & DSPFW_CURSORA_MASK
) |
3168 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
3169 /* HPLL off in SR has some issues on G4x... disable it */
3170 I915_WRITE(DSPFW3
, (I915_READ(DSPFW3
) & ~DSPFW_HPLL_SR_EN
) |
3171 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3174 static void i965_update_wm(struct drm_device
*dev
, int planea_clock
,
3175 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3179 unsigned long line_time_us
;
3180 int sr_clock
, sr_entries
, srwm
= 1;
3183 /* Calc sr entries for one plane configs */
3184 if (sr_hdisplay
&& (!planea_clock
|| !planeb_clock
)) {
3185 /* self-refresh has much higher latency */
3186 static const int sr_latency_ns
= 12000;
3188 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3189 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3191 /* Use ns/us then divide to preserve precision */
3192 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3193 pixel_size
* sr_hdisplay
;
3194 sr_entries
= DIV_ROUND_UP(sr_entries
, I915_FIFO_LINE_SIZE
);
3195 DRM_DEBUG("self-refresh entries: %d\n", sr_entries
);
3196 srwm
= I965_FIFO_SIZE
- sr_entries
;
3201 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3203 sr_entries
= DIV_ROUND_UP(sr_entries
,
3204 i965_cursor_wm_info
.cacheline_size
);
3205 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
3206 (sr_entries
+ i965_cursor_wm_info
.guard_size
);
3208 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
3209 cursor_sr
= i965_cursor_wm_info
.max_wm
;
3211 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3212 "cursor %d\n", srwm
, cursor_sr
);
3215 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
3217 /* Turn off self refresh if both pipes are enabled */
3219 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3223 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3226 /* 965 has limitations... */
3227 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) | (8 << 16) | (8 << 8) |
3229 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
3230 /* update cursor SR watermark */
3231 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
3234 static void i9xx_update_wm(struct drm_device
*dev
, int planea_clock
,
3235 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3238 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3241 int total_size
, cacheline_size
, cwm
, srwm
= 1;
3242 int planea_wm
, planeb_wm
;
3243 struct intel_watermark_params planea_params
, planeb_params
;
3244 unsigned long line_time_us
;
3245 int sr_clock
, sr_entries
= 0;
3247 /* Create copies of the base settings for each pipe */
3248 if (IS_I965GM(dev
) || IS_I945GM(dev
))
3249 planea_params
= planeb_params
= i945_wm_info
;
3250 else if (IS_I9XX(dev
))
3251 planea_params
= planeb_params
= i915_wm_info
;
3253 planea_params
= planeb_params
= i855_wm_info
;
3255 /* Grab a couple of global values before we overwrite them */
3256 total_size
= planea_params
.fifo_size
;
3257 cacheline_size
= planea_params
.cacheline_size
;
3259 /* Update per-plane FIFO sizes */
3260 planea_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3261 planeb_params
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
3263 planea_wm
= intel_calculate_wm(planea_clock
, &planea_params
,
3264 pixel_size
, latency_ns
);
3265 planeb_wm
= intel_calculate_wm(planeb_clock
, &planeb_params
,
3266 pixel_size
, latency_ns
);
3267 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
3270 * Overlay gets an aggressive default since video jitter is bad.
3274 /* Calc sr entries for one plane configs */
3275 if (HAS_FW_BLC(dev
) && sr_hdisplay
&&
3276 (!planea_clock
|| !planeb_clock
)) {
3277 /* self-refresh has much higher latency */
3278 static const int sr_latency_ns
= 6000;
3280 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3281 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3283 /* Use ns/us then divide to preserve precision */
3284 sr_entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
3285 pixel_size
* sr_hdisplay
;
3286 sr_entries
= DIV_ROUND_UP(sr_entries
, cacheline_size
);
3287 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries
);
3288 srwm
= total_size
- sr_entries
;
3292 if (IS_I945G(dev
) || IS_I945GM(dev
))
3293 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
3294 else if (IS_I915GM(dev
)) {
3295 /* 915M has a smaller SRWM field */
3296 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
3297 I915_WRITE(INSTPM
, I915_READ(INSTPM
) | INSTPM_SELF_EN
);
3300 /* Turn off self refresh if both pipes are enabled */
3301 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
3302 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
3304 } else if (IS_I915GM(dev
)) {
3305 I915_WRITE(INSTPM
, I915_READ(INSTPM
) & ~INSTPM_SELF_EN
);
3309 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3310 planea_wm
, planeb_wm
, cwm
, srwm
);
3312 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
3313 fwater_hi
= (cwm
& 0x1f);
3315 /* Set request length to 8 cachelines per fetch */
3316 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
3317 fwater_hi
= fwater_hi
| (1 << 8);
3319 I915_WRITE(FW_BLC
, fwater_lo
);
3320 I915_WRITE(FW_BLC2
, fwater_hi
);
3323 static void i830_update_wm(struct drm_device
*dev
, int planea_clock
, int unused
,
3324 int unused2
, int unused3
, int pixel_size
)
3326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3327 uint32_t fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
3330 i830_wm_info
.fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
3332 planea_wm
= intel_calculate_wm(planea_clock
, &i830_wm_info
,
3333 pixel_size
, latency_ns
);
3334 fwater_lo
|= (3<<8) | planea_wm
;
3336 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
3338 I915_WRITE(FW_BLC
, fwater_lo
);
3341 #define ILK_LP0_PLANE_LATENCY 700
3342 #define ILK_LP0_CURSOR_LATENCY 1300
3344 static void ironlake_update_wm(struct drm_device
*dev
, int planea_clock
,
3345 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
3348 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3349 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
3350 int sr_wm
, cursor_wm
;
3351 unsigned long line_time_us
;
3352 int sr_clock
, entries_required
;
3355 int planea_htotal
= 0, planeb_htotal
= 0;
3356 struct drm_crtc
*crtc
;
3357 struct intel_crtc
*intel_crtc
;
3359 /* Need htotal for all active display plane */
3360 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3361 intel_crtc
= to_intel_crtc(crtc
);
3362 if (crtc
->enabled
) {
3363 if (intel_crtc
->plane
== 0)
3364 planea_htotal
= crtc
->mode
.htotal
;
3366 planeb_htotal
= crtc
->mode
.htotal
;
3370 /* Calculate and update the watermark for plane A */
3372 entries_required
= ((planea_clock
/ 1000) * pixel_size
*
3373 ILK_LP0_PLANE_LATENCY
) / 1000;
3374 entries_required
= DIV_ROUND_UP(entries_required
,
3375 ironlake_display_wm_info
.cacheline_size
);
3376 planea_wm
= entries_required
+
3377 ironlake_display_wm_info
.guard_size
;
3379 if (planea_wm
> (int)ironlake_display_wm_info
.max_wm
)
3380 planea_wm
= ironlake_display_wm_info
.max_wm
;
3382 /* Use the large buffer method to calculate cursor watermark */
3383 line_time_us
= (planea_htotal
* 1000) / planea_clock
;
3385 /* Use ns/us then divide to preserve precision */
3386 line_count
= (ILK_LP0_CURSOR_LATENCY
/ line_time_us
+ 1000) / 1000;
3388 /* calculate the cursor watermark for cursor A */
3389 entries_required
= line_count
* 64 * pixel_size
;
3390 entries_required
= DIV_ROUND_UP(entries_required
,
3391 ironlake_cursor_wm_info
.cacheline_size
);
3392 cursora_wm
= entries_required
+ ironlake_cursor_wm_info
.guard_size
;
3393 if (cursora_wm
> ironlake_cursor_wm_info
.max_wm
)
3394 cursora_wm
= ironlake_cursor_wm_info
.max_wm
;
3396 reg_value
= I915_READ(WM0_PIPEA_ILK
);
3397 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3398 reg_value
|= (planea_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3399 (cursora_wm
& WM0_PIPE_CURSOR_MASK
);
3400 I915_WRITE(WM0_PIPEA_ILK
, reg_value
);
3401 DRM_DEBUG_KMS("FIFO watermarks For pipe A - plane %d, "
3402 "cursor: %d\n", planea_wm
, cursora_wm
);
3404 /* Calculate and update the watermark for plane B */
3406 entries_required
= ((planeb_clock
/ 1000) * pixel_size
*
3407 ILK_LP0_PLANE_LATENCY
) / 1000;
3408 entries_required
= DIV_ROUND_UP(entries_required
,
3409 ironlake_display_wm_info
.cacheline_size
);
3410 planeb_wm
= entries_required
+
3411 ironlake_display_wm_info
.guard_size
;
3413 if (planeb_wm
> (int)ironlake_display_wm_info
.max_wm
)
3414 planeb_wm
= ironlake_display_wm_info
.max_wm
;
3416 /* Use the large buffer method to calculate cursor watermark */
3417 line_time_us
= (planeb_htotal
* 1000) / planeb_clock
;
3419 /* Use ns/us then divide to preserve precision */
3420 line_count
= (ILK_LP0_CURSOR_LATENCY
/ line_time_us
+ 1000) / 1000;
3422 /* calculate the cursor watermark for cursor B */
3423 entries_required
= line_count
* 64 * pixel_size
;
3424 entries_required
= DIV_ROUND_UP(entries_required
,
3425 ironlake_cursor_wm_info
.cacheline_size
);
3426 cursorb_wm
= entries_required
+ ironlake_cursor_wm_info
.guard_size
;
3427 if (cursorb_wm
> ironlake_cursor_wm_info
.max_wm
)
3428 cursorb_wm
= ironlake_cursor_wm_info
.max_wm
;
3430 reg_value
= I915_READ(WM0_PIPEB_ILK
);
3431 reg_value
&= ~(WM0_PIPE_PLANE_MASK
| WM0_PIPE_CURSOR_MASK
);
3432 reg_value
|= (planeb_wm
<< WM0_PIPE_PLANE_SHIFT
) |
3433 (cursorb_wm
& WM0_PIPE_CURSOR_MASK
);
3434 I915_WRITE(WM0_PIPEB_ILK
, reg_value
);
3435 DRM_DEBUG_KMS("FIFO watermarks For pipe B - plane %d, "
3436 "cursor: %d\n", planeb_wm
, cursorb_wm
);
3440 * Calculate and update the self-refresh watermark only when one
3441 * display plane is used.
3443 if (!planea_clock
|| !planeb_clock
) {
3445 /* Read the self-refresh latency. The unit is 0.5us */
3446 int ilk_sr_latency
= I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
;
3448 sr_clock
= planea_clock
? planea_clock
: planeb_clock
;
3449 line_time_us
= ((sr_htotal
* 1000) / sr_clock
);
3451 /* Use ns/us then divide to preserve precision */
3452 line_count
= ((ilk_sr_latency
* 500) / line_time_us
+ 1000)
3455 /* calculate the self-refresh watermark for display plane */
3456 entries_required
= line_count
* sr_hdisplay
* pixel_size
;
3457 entries_required
= DIV_ROUND_UP(entries_required
,
3458 ironlake_display_srwm_info
.cacheline_size
);
3459 sr_wm
= entries_required
+
3460 ironlake_display_srwm_info
.guard_size
;
3462 /* calculate the self-refresh watermark for display cursor */
3463 entries_required
= line_count
* pixel_size
* 64;
3464 entries_required
= DIV_ROUND_UP(entries_required
,
3465 ironlake_cursor_srwm_info
.cacheline_size
);
3466 cursor_wm
= entries_required
+
3467 ironlake_cursor_srwm_info
.guard_size
;
3469 /* configure watermark and enable self-refresh */
3470 reg_value
= I915_READ(WM1_LP_ILK
);
3471 reg_value
&= ~(WM1_LP_LATENCY_MASK
| WM1_LP_SR_MASK
|
3472 WM1_LP_CURSOR_MASK
);
3473 reg_value
|= WM1_LP_SR_EN
|
3474 (ilk_sr_latency
<< WM1_LP_LATENCY_SHIFT
) |
3475 (sr_wm
<< WM1_LP_SR_SHIFT
) | cursor_wm
;
3477 I915_WRITE(WM1_LP_ILK
, reg_value
);
3478 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3479 "cursor %d\n", sr_wm
, cursor_wm
);
3482 /* Turn off self refresh if both pipes are enabled */
3483 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
3487 * intel_update_watermarks - update FIFO watermark values based on current modes
3489 * Calculate watermark values for the various WM regs based on current mode
3490 * and plane configuration.
3492 * There are several cases to deal with here:
3493 * - normal (i.e. non-self-refresh)
3494 * - self-refresh (SR) mode
3495 * - lines are large relative to FIFO size (buffer can hold up to 2)
3496 * - lines are small relative to FIFO size (buffer can hold more than 2
3497 * lines), so need to account for TLB latency
3499 * The normal calculation is:
3500 * watermark = dotclock * bytes per pixel * latency
3501 * where latency is platform & configuration dependent (we assume pessimal
3504 * The SR calculation is:
3505 * watermark = (trunc(latency/line time)+1) * surface width *
3508 * line time = htotal / dotclock
3509 * surface width = hdisplay for normal plane and 64 for cursor
3510 * and latency is assumed to be high, as above.
3512 * The final value programmed to the register should always be rounded up,
3513 * and include an extra 2 entries to account for clock crossings.
3515 * We don't use the sprite, so we can ignore that. And on Crestline we have
3516 * to set the non-SR watermarks to 8.
3518 static void intel_update_watermarks(struct drm_device
*dev
)
3520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3521 struct drm_crtc
*crtc
;
3522 struct intel_crtc
*intel_crtc
;
3523 int sr_hdisplay
= 0;
3524 unsigned long planea_clock
= 0, planeb_clock
= 0, sr_clock
= 0;
3525 int enabled
= 0, pixel_size
= 0;
3528 if (!dev_priv
->display
.update_wm
)
3531 /* Get the clock config from both planes */
3532 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
3533 intel_crtc
= to_intel_crtc(crtc
);
3534 if (crtc
->enabled
) {
3536 if (intel_crtc
->plane
== 0) {
3537 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3538 intel_crtc
->pipe
, crtc
->mode
.clock
);
3539 planea_clock
= crtc
->mode
.clock
;
3541 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3542 intel_crtc
->pipe
, crtc
->mode
.clock
);
3543 planeb_clock
= crtc
->mode
.clock
;
3545 sr_hdisplay
= crtc
->mode
.hdisplay
;
3546 sr_clock
= crtc
->mode
.clock
;
3547 sr_htotal
= crtc
->mode
.htotal
;
3549 pixel_size
= crtc
->fb
->bits_per_pixel
/ 8;
3551 pixel_size
= 4; /* by default */
3558 dev_priv
->display
.update_wm(dev
, planea_clock
, planeb_clock
,
3559 sr_hdisplay
, sr_htotal
, pixel_size
);
3562 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
3563 struct drm_display_mode
*mode
,
3564 struct drm_display_mode
*adjusted_mode
,
3566 struct drm_framebuffer
*old_fb
)
3568 struct drm_device
*dev
= crtc
->dev
;
3569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3570 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3571 int pipe
= intel_crtc
->pipe
;
3572 int plane
= intel_crtc
->plane
;
3573 int fp_reg
= (pipe
== 0) ? FPA0
: FPB0
;
3574 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
3575 int dpll_md_reg
= (intel_crtc
->pipe
== 0) ? DPLL_A_MD
: DPLL_B_MD
;
3576 int dspcntr_reg
= (plane
== 0) ? DSPACNTR
: DSPBCNTR
;
3577 int pipeconf_reg
= (pipe
== 0) ? PIPEACONF
: PIPEBCONF
;
3578 int htot_reg
= (pipe
== 0) ? HTOTAL_A
: HTOTAL_B
;
3579 int hblank_reg
= (pipe
== 0) ? HBLANK_A
: HBLANK_B
;
3580 int hsync_reg
= (pipe
== 0) ? HSYNC_A
: HSYNC_B
;
3581 int vtot_reg
= (pipe
== 0) ? VTOTAL_A
: VTOTAL_B
;
3582 int vblank_reg
= (pipe
== 0) ? VBLANK_A
: VBLANK_B
;
3583 int vsync_reg
= (pipe
== 0) ? VSYNC_A
: VSYNC_B
;
3584 int dspsize_reg
= (plane
== 0) ? DSPASIZE
: DSPBSIZE
;
3585 int dsppos_reg
= (plane
== 0) ? DSPAPOS
: DSPBPOS
;
3586 int pipesrc_reg
= (pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
3587 int refclk
, num_connectors
= 0;
3588 intel_clock_t clock
, reduced_clock
;
3589 u32 dpll
= 0, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
3590 bool ok
, has_reduced_clock
= false, is_sdvo
= false, is_dvo
= false;
3591 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
3592 bool is_edp
= false;
3593 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
3594 struct drm_encoder
*encoder
;
3595 struct intel_encoder
*intel_encoder
= NULL
;
3596 const intel_limit_t
*limit
;
3598 struct fdi_m_n m_n
= {0};
3599 int data_m1_reg
= (pipe
== 0) ? PIPEA_DATA_M1
: PIPEB_DATA_M1
;
3600 int data_n1_reg
= (pipe
== 0) ? PIPEA_DATA_N1
: PIPEB_DATA_N1
;
3601 int link_m1_reg
= (pipe
== 0) ? PIPEA_LINK_M1
: PIPEB_LINK_M1
;
3602 int link_n1_reg
= (pipe
== 0) ? PIPEA_LINK_N1
: PIPEB_LINK_N1
;
3603 int pch_fp_reg
= (pipe
== 0) ? PCH_FPA0
: PCH_FPB0
;
3604 int pch_dpll_reg
= (pipe
== 0) ? PCH_DPLL_A
: PCH_DPLL_B
;
3605 int fdi_rx_reg
= (pipe
== 0) ? FDI_RXA_CTL
: FDI_RXB_CTL
;
3606 int fdi_tx_reg
= (pipe
== 0) ? FDI_TXA_CTL
: FDI_TXB_CTL
;
3607 int trans_dpll_sel
= (pipe
== 0) ? 0 : 1;
3608 int lvds_reg
= LVDS
;
3610 int sdvo_pixel_multiply
;
3613 drm_vblank_pre_modeset(dev
, pipe
);
3615 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
3617 if (!encoder
|| encoder
->crtc
!= crtc
)
3620 intel_encoder
= enc_to_intel_encoder(encoder
);
3622 switch (intel_encoder
->type
) {
3623 case INTEL_OUTPUT_LVDS
:
3626 case INTEL_OUTPUT_SDVO
:
3627 case INTEL_OUTPUT_HDMI
:
3629 if (intel_encoder
->needs_tv_clock
)
3632 case INTEL_OUTPUT_DVO
:
3635 case INTEL_OUTPUT_TVOUT
:
3638 case INTEL_OUTPUT_ANALOG
:
3641 case INTEL_OUTPUT_DISPLAYPORT
:
3644 case INTEL_OUTPUT_EDP
:
3652 if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2) {
3653 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3654 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3656 } else if (IS_I9XX(dev
)) {
3658 if (HAS_PCH_SPLIT(dev
))
3659 refclk
= 120000; /* 120Mhz refclk */
3666 * Returns a set of divisors for the desired target clock with the given
3667 * refclk, or FALSE. The returned values represent the clock equation:
3668 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3670 limit
= intel_limit(crtc
);
3671 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, &clock
);
3673 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3674 drm_vblank_post_modeset(dev
, pipe
);
3678 /* Ensure that the cursor is valid for the new mode before changing... */
3679 intel_crtc_update_cursor(crtc
);
3681 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
3682 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
3683 dev_priv
->lvds_downclock
,
3686 if (has_reduced_clock
&& (clock
.p
!= reduced_clock
.p
)) {
3688 * If the different P is found, it means that we can't
3689 * switch the display clock by using the FP0/FP1.
3690 * In such case we will disable the LVDS downclock
3693 DRM_DEBUG_KMS("Different P is found for "
3694 "LVDS clock/downclock\n");
3695 has_reduced_clock
= 0;
3698 /* SDVO TV has fixed PLL values depend on its clock range,
3699 this mirrors vbios setting. */
3700 if (is_sdvo
&& is_tv
) {
3701 if (adjusted_mode
->clock
>= 100000
3702 && adjusted_mode
->clock
< 140500) {
3708 } else if (adjusted_mode
->clock
>= 140500
3709 && adjusted_mode
->clock
<= 200000) {
3719 if (HAS_PCH_SPLIT(dev
)) {
3720 int lane
= 0, link_bw
, bpp
;
3721 /* eDP doesn't require FDI link, so just set DP M/N
3722 according to current link config */
3724 target_clock
= mode
->clock
;
3725 intel_edp_link_config(intel_encoder
,
3728 /* DP over FDI requires target mode clock
3729 instead of link clock */
3731 target_clock
= mode
->clock
;
3733 target_clock
= adjusted_mode
->clock
;
3737 /* determine panel color depth */
3738 temp
= I915_READ(pipeconf_reg
);
3739 temp
&= ~PIPE_BPC_MASK
;
3741 int lvds_reg
= I915_READ(PCH_LVDS
);
3742 /* the BPC will be 6 if it is 18-bit LVDS panel */
3743 if ((lvds_reg
& LVDS_A3_POWER_MASK
) == LVDS_A3_POWER_UP
)
3747 } else if (is_edp
|| (is_dp
&& intel_pch_has_edp(crtc
))) {
3748 switch (dev_priv
->edp_bpp
/3) {
3764 I915_WRITE(pipeconf_reg
, temp
);
3765 I915_READ(pipeconf_reg
);
3767 switch (temp
& PIPE_BPC_MASK
) {
3781 DRM_ERROR("unknown pipe bpc value\n");
3787 * Account for spread spectrum to avoid
3788 * oversubscribing the link. Max center spread
3789 * is 2.5%; use 5% for safety's sake.
3791 u32 bps
= target_clock
* bpp
* 21 / 20;
3792 lane
= bps
/ (link_bw
* 8) + 1;
3795 intel_crtc
->fdi_lanes
= lane
;
3797 ironlake_compute_m_n(bpp
, lane
, target_clock
, link_bw
, &m_n
);
3800 /* Ironlake: try to setup display ref clock before DPLL
3801 * enabling. This is only under driver's control after
3802 * PCH B stepping, previous chipset stepping should be
3803 * ignoring this setting.
3805 if (HAS_PCH_SPLIT(dev
)) {
3806 temp
= I915_READ(PCH_DREF_CONTROL
);
3807 /* Always enable nonspread source */
3808 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
3809 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
3810 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3811 POSTING_READ(PCH_DREF_CONTROL
);
3813 temp
&= ~DREF_SSC_SOURCE_MASK
;
3814 temp
|= DREF_SSC_SOURCE_ENABLE
;
3815 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3816 POSTING_READ(PCH_DREF_CONTROL
);
3821 if (dev_priv
->lvds_use_ssc
) {
3822 temp
|= DREF_SSC1_ENABLE
;
3823 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3824 POSTING_READ(PCH_DREF_CONTROL
);
3828 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
3829 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
3830 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3831 POSTING_READ(PCH_DREF_CONTROL
);
3833 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
3834 I915_WRITE(PCH_DREF_CONTROL
, temp
);
3835 POSTING_READ(PCH_DREF_CONTROL
);
3840 if (IS_PINEVIEW(dev
)) {
3841 fp
= (1 << clock
.n
) << 16 | clock
.m1
<< 8 | clock
.m2
;
3842 if (has_reduced_clock
)
3843 fp2
= (1 << reduced_clock
.n
) << 16 |
3844 reduced_clock
.m1
<< 8 | reduced_clock
.m2
;
3846 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
3847 if (has_reduced_clock
)
3848 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
3852 if (!HAS_PCH_SPLIT(dev
))
3853 dpll
= DPLL_VGA_MODE_DIS
;
3857 dpll
|= DPLLB_MODE_LVDS
;
3859 dpll
|= DPLLB_MODE_DAC_SERIAL
;
3861 dpll
|= DPLL_DVO_HIGH_SPEED
;
3862 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
3863 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
3864 dpll
|= (sdvo_pixel_multiply
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
3865 else if (HAS_PCH_SPLIT(dev
))
3866 dpll
|= (sdvo_pixel_multiply
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
3869 dpll
|= DPLL_DVO_HIGH_SPEED
;
3871 /* compute bitmask from p1 value */
3872 if (IS_PINEVIEW(dev
))
3873 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
3875 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3877 if (HAS_PCH_SPLIT(dev
))
3878 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3879 if (IS_G4X(dev
) && has_reduced_clock
)
3880 dpll
|= (1 << (reduced_clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
3884 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
3887 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
3890 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
3893 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
3896 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
))
3897 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
3900 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3903 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
3905 dpll
|= (clock
.p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
3907 dpll
|= PLL_P2_DIVIDE_BY_4
;
3911 if (is_sdvo
&& is_tv
)
3912 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
3914 /* XXX: just matching BIOS for now */
3915 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
3917 else if (is_lvds
&& dev_priv
->lvds_use_ssc
&& num_connectors
< 2)
3918 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
3920 dpll
|= PLL_REF_INPUT_DREFCLK
;
3922 /* setup pipeconf */
3923 pipeconf
= I915_READ(pipeconf_reg
);
3925 /* Set up the display plane register */
3926 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
3928 /* Ironlake's plane is forced to pipe, bit 24 is to
3929 enable color space conversion */
3930 if (!HAS_PCH_SPLIT(dev
)) {
3932 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
3934 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
3937 if (pipe
== 0 && !IS_I965G(dev
)) {
3938 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3941 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3945 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
3946 pipeconf
|= PIPEACONF_DOUBLE_WIDE
;
3948 pipeconf
&= ~PIPEACONF_DOUBLE_WIDE
;
3951 dspcntr
|= DISPLAY_PLANE_ENABLE
;
3952 pipeconf
|= PIPEACONF_ENABLE
;
3953 dpll
|= DPLL_VCO_ENABLE
;
3956 /* Disable the panel fitter if it was on our pipe */
3957 if (!HAS_PCH_SPLIT(dev
) && intel_panel_fitter_pipe(dev
) == pipe
)
3958 I915_WRITE(PFIT_CONTROL
, 0);
3960 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
3961 drm_mode_debug_printmodeline(mode
);
3963 /* assign to Ironlake registers */
3964 if (HAS_PCH_SPLIT(dev
)) {
3965 fp_reg
= pch_fp_reg
;
3966 dpll_reg
= pch_dpll_reg
;
3970 ironlake_disable_pll_edp(crtc
);
3971 } else if ((dpll
& DPLL_VCO_ENABLE
)) {
3972 I915_WRITE(fp_reg
, fp
);
3973 I915_WRITE(dpll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3974 I915_READ(dpll_reg
);
3978 /* enable transcoder DPLL */
3979 if (HAS_PCH_CPT(dev
)) {
3980 temp
= I915_READ(PCH_DPLL_SEL
);
3981 if (trans_dpll_sel
== 0)
3982 temp
|= (TRANSA_DPLL_ENABLE
| TRANSA_DPLLA_SEL
);
3984 temp
|= (TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3985 I915_WRITE(PCH_DPLL_SEL
, temp
);
3986 I915_READ(PCH_DPLL_SEL
);
3990 if (HAS_PCH_SPLIT(dev
)) {
3991 pipeconf
&= ~PIPE_ENABLE_DITHER
;
3992 pipeconf
&= ~PIPE_DITHER_TYPE_MASK
;
3995 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3996 * This is an exception to the general rule that mode_set doesn't turn
4002 if (HAS_PCH_SPLIT(dev
))
4003 lvds_reg
= PCH_LVDS
;
4005 lvds
= I915_READ(lvds_reg
);
4006 lvds
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4008 if (HAS_PCH_CPT(dev
))
4009 lvds
|= PORT_TRANS_B_SEL_CPT
;
4011 lvds
|= LVDS_PIPEB_SELECT
;
4013 if (HAS_PCH_CPT(dev
))
4014 lvds
&= ~PORT_TRANS_SEL_MASK
;
4016 lvds
&= ~LVDS_PIPEB_SELECT
;
4018 /* set the corresponsding LVDS_BORDER bit */
4019 lvds
|= dev_priv
->lvds_border_bits
;
4020 /* Set the B0-B3 data pairs corresponding to whether we're going to
4021 * set the DPLLs for dual-channel mode or not.
4024 lvds
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4026 lvds
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4028 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4029 * appropriately here, but we need to look more thoroughly into how
4030 * panels behave in the two modes.
4032 /* set the dithering flag */
4033 if (IS_I965G(dev
)) {
4034 if (dev_priv
->lvds_dither
) {
4035 if (HAS_PCH_SPLIT(dev
)) {
4036 pipeconf
|= PIPE_ENABLE_DITHER
;
4037 pipeconf
|= PIPE_DITHER_TYPE_ST01
;
4039 lvds
|= LVDS_ENABLE_DITHER
;
4041 if (!HAS_PCH_SPLIT(dev
)) {
4042 lvds
&= ~LVDS_ENABLE_DITHER
;
4046 I915_WRITE(lvds_reg
, lvds
);
4047 I915_READ(lvds_reg
);
4050 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4051 else if (HAS_PCH_SPLIT(dev
)) {
4052 /* For non-DP output, clear any trans DP clock recovery setting.*/
4054 I915_WRITE(TRANSA_DATA_M1
, 0);
4055 I915_WRITE(TRANSA_DATA_N1
, 0);
4056 I915_WRITE(TRANSA_DP_LINK_M1
, 0);
4057 I915_WRITE(TRANSA_DP_LINK_N1
, 0);
4059 I915_WRITE(TRANSB_DATA_M1
, 0);
4060 I915_WRITE(TRANSB_DATA_N1
, 0);
4061 I915_WRITE(TRANSB_DP_LINK_M1
, 0);
4062 I915_WRITE(TRANSB_DP_LINK_N1
, 0);
4067 I915_WRITE(fp_reg
, fp
);
4068 I915_WRITE(dpll_reg
, dpll
);
4069 I915_READ(dpll_reg
);
4070 /* Wait for the clocks to stabilize. */
4073 if (IS_I965G(dev
) && !HAS_PCH_SPLIT(dev
)) {
4075 sdvo_pixel_multiply
= adjusted_mode
->clock
/ mode
->clock
;
4076 I915_WRITE(dpll_md_reg
, (0 << DPLL_MD_UDI_DIVIDER_SHIFT
) |
4077 ((sdvo_pixel_multiply
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
));
4079 I915_WRITE(dpll_md_reg
, 0);
4081 /* write it again -- the BIOS does, after all */
4082 I915_WRITE(dpll_reg
, dpll
);
4084 I915_READ(dpll_reg
);
4085 /* Wait for the clocks to stabilize. */
4089 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4090 I915_WRITE(fp_reg
+ 4, fp2
);
4091 intel_crtc
->lowfreq_avail
= true;
4092 if (HAS_PIPE_CXSR(dev
)) {
4093 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4094 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4097 I915_WRITE(fp_reg
+ 4, fp
);
4098 intel_crtc
->lowfreq_avail
= false;
4099 if (HAS_PIPE_CXSR(dev
)) {
4100 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4101 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4105 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4106 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4107 /* the chip adds 2 halflines automatically */
4108 adjusted_mode
->crtc_vdisplay
-= 1;
4109 adjusted_mode
->crtc_vtotal
-= 1;
4110 adjusted_mode
->crtc_vblank_start
-= 1;
4111 adjusted_mode
->crtc_vblank_end
-= 1;
4112 adjusted_mode
->crtc_vsync_end
-= 1;
4113 adjusted_mode
->crtc_vsync_start
-= 1;
4115 pipeconf
&= ~PIPECONF_INTERLACE_W_FIELD_INDICATION
; /* progressive */
4117 I915_WRITE(htot_reg
, (adjusted_mode
->crtc_hdisplay
- 1) |
4118 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4119 I915_WRITE(hblank_reg
, (adjusted_mode
->crtc_hblank_start
- 1) |
4120 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4121 I915_WRITE(hsync_reg
, (adjusted_mode
->crtc_hsync_start
- 1) |
4122 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4123 I915_WRITE(vtot_reg
, (adjusted_mode
->crtc_vdisplay
- 1) |
4124 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4125 I915_WRITE(vblank_reg
, (adjusted_mode
->crtc_vblank_start
- 1) |
4126 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4127 I915_WRITE(vsync_reg
, (adjusted_mode
->crtc_vsync_start
- 1) |
4128 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4129 /* pipesrc and dspsize control the size that is scaled from, which should
4130 * always be the user's requested size.
4132 if (!HAS_PCH_SPLIT(dev
)) {
4133 I915_WRITE(dspsize_reg
, ((mode
->vdisplay
- 1) << 16) |
4134 (mode
->hdisplay
- 1));
4135 I915_WRITE(dsppos_reg
, 0);
4137 I915_WRITE(pipesrc_reg
, ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4139 if (HAS_PCH_SPLIT(dev
)) {
4140 I915_WRITE(data_m1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4141 I915_WRITE(data_n1_reg
, TU_SIZE(m_n
.tu
) | m_n
.gmch_n
);
4142 I915_WRITE(link_m1_reg
, m_n
.link_m
);
4143 I915_WRITE(link_n1_reg
, m_n
.link_n
);
4146 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4148 /* enable FDI RX PLL too */
4149 temp
= I915_READ(fdi_rx_reg
);
4150 I915_WRITE(fdi_rx_reg
, temp
| FDI_RX_PLL_ENABLE
);
4151 I915_READ(fdi_rx_reg
);
4154 /* enable FDI TX PLL too */
4155 temp
= I915_READ(fdi_tx_reg
);
4156 I915_WRITE(fdi_tx_reg
, temp
| FDI_TX_PLL_ENABLE
);
4157 I915_READ(fdi_tx_reg
);
4159 /* enable FDI RX PCDCLK */
4160 temp
= I915_READ(fdi_rx_reg
);
4161 I915_WRITE(fdi_rx_reg
, temp
| FDI_SEL_PCDCLK
);
4162 I915_READ(fdi_rx_reg
);
4167 I915_WRITE(pipeconf_reg
, pipeconf
);
4168 I915_READ(pipeconf_reg
);
4170 intel_wait_for_vblank(dev
);
4172 if (IS_IRONLAKE(dev
)) {
4173 /* enable address swizzle for tiling buffer */
4174 temp
= I915_READ(DISP_ARB_CTL
);
4175 I915_WRITE(DISP_ARB_CTL
, temp
| DISP_TILE_SURFACE_SWIZZLING
);
4178 I915_WRITE(dspcntr_reg
, dspcntr
);
4180 /* Flush the plane changes */
4181 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4183 if ((IS_I965G(dev
) || plane
== 0))
4184 intel_update_fbc(crtc
, &crtc
->mode
);
4186 intel_update_watermarks(dev
);
4188 drm_vblank_post_modeset(dev
, pipe
);
4193 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4194 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4196 struct drm_device
*dev
= crtc
->dev
;
4197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4199 int palreg
= (intel_crtc
->pipe
== 0) ? PALETTE_A
: PALETTE_B
;
4202 /* The clocks have to be on to load the palette. */
4206 /* use legacy palette for Ironlake */
4207 if (HAS_PCH_SPLIT(dev
))
4208 palreg
= (intel_crtc
->pipe
== 0) ? LGC_PALETTE_A
:
4211 for (i
= 0; i
< 256; i
++) {
4212 I915_WRITE(palreg
+ 4 * i
,
4213 (intel_crtc
->lut_r
[i
] << 16) |
4214 (intel_crtc
->lut_g
[i
] << 8) |
4215 intel_crtc
->lut_b
[i
]);
4219 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4220 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
)
4222 struct drm_device
*dev
= crtc
->dev
;
4223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4224 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4225 int pipe
= intel_crtc
->pipe
;
4226 int x
= intel_crtc
->cursor_x
;
4227 int y
= intel_crtc
->cursor_y
;
4234 base
= intel_crtc
->cursor_addr
;
4235 if (x
> (int) crtc
->fb
->width
)
4238 if (y
> (int) crtc
->fb
->height
)
4244 if (x
+ intel_crtc
->cursor_width
< 0)
4247 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
4250 pos
|= x
<< CURSOR_X_SHIFT
;
4253 if (y
+ intel_crtc
->cursor_height
< 0)
4256 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
4259 pos
|= y
<< CURSOR_Y_SHIFT
;
4261 visible
= base
!= 0;
4262 if (!visible
&& !intel_crtc
->cursor_visble
)
4265 I915_WRITE(pipe
== 0 ? CURAPOS
: CURBPOS
, pos
);
4266 if (intel_crtc
->cursor_visble
!= visible
) {
4267 uint32_t cntl
= I915_READ(pipe
== 0 ? CURACNTR
: CURBCNTR
);
4269 /* Hooray for CUR*CNTR differences */
4270 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
4271 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
4272 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
4273 cntl
|= pipe
<< 28; /* Connect to correct pipe */
4275 cntl
&= ~(CURSOR_FORMAT_MASK
);
4276 cntl
|= CURSOR_ENABLE
;
4277 cntl
|= CURSOR_FORMAT_ARGB
| CURSOR_GAMMA_ENABLE
;
4280 if (IS_MOBILE(dev
) || IS_I9XX(dev
)) {
4281 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
4282 cntl
|= CURSOR_MODE_DISABLE
;
4284 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
4287 I915_WRITE(pipe
== 0 ? CURACNTR
: CURBCNTR
, cntl
);
4289 intel_crtc
->cursor_visble
= visible
;
4291 /* and commit changes on next vblank */
4292 I915_WRITE(pipe
== 0 ? CURABASE
: CURBBASE
, base
);
4295 intel_mark_busy(dev
, to_intel_framebuffer(crtc
->fb
)->obj
);
4298 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
4299 struct drm_file
*file_priv
,
4301 uint32_t width
, uint32_t height
)
4303 struct drm_device
*dev
= crtc
->dev
;
4304 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4305 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4306 struct drm_gem_object
*bo
;
4307 struct drm_i915_gem_object
*obj_priv
;
4311 DRM_DEBUG_KMS("\n");
4313 /* if we want to turn off the cursor ignore width and height */
4315 DRM_DEBUG_KMS("cursor off\n");
4318 mutex_lock(&dev
->struct_mutex
);
4322 /* Currently we only support 64x64 cursors */
4323 if (width
!= 64 || height
!= 64) {
4324 DRM_ERROR("we currently only support 64x64 cursors\n");
4328 bo
= drm_gem_object_lookup(dev
, file_priv
, handle
);
4332 obj_priv
= to_intel_bo(bo
);
4334 if (bo
->size
< width
* height
* 4) {
4335 DRM_ERROR("buffer is to small\n");
4340 /* we only need to pin inside GTT if cursor is non-phy */
4341 mutex_lock(&dev
->struct_mutex
);
4342 if (!dev_priv
->info
->cursor_needs_physical
) {
4343 ret
= i915_gem_object_pin(bo
, PAGE_SIZE
);
4345 DRM_ERROR("failed to pin cursor bo\n");
4349 ret
= i915_gem_object_set_to_gtt_domain(bo
, 0);
4351 DRM_ERROR("failed to move cursor bo into the GTT\n");
4355 addr
= obj_priv
->gtt_offset
;
4357 ret
= i915_gem_attach_phys_object(dev
, bo
,
4358 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
);
4360 DRM_ERROR("failed to attach phys object\n");
4363 addr
= obj_priv
->phys_obj
->handle
->busaddr
;
4367 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
4370 if (intel_crtc
->cursor_bo
) {
4371 if (dev_priv
->info
->cursor_needs_physical
) {
4372 if (intel_crtc
->cursor_bo
!= bo
)
4373 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
4375 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
4376 drm_gem_object_unreference(intel_crtc
->cursor_bo
);
4379 mutex_unlock(&dev
->struct_mutex
);
4381 intel_crtc
->cursor_addr
= addr
;
4382 intel_crtc
->cursor_bo
= bo
;
4383 intel_crtc
->cursor_width
= width
;
4384 intel_crtc
->cursor_height
= height
;
4386 intel_crtc_update_cursor(crtc
);
4390 i915_gem_object_unpin(bo
);
4392 mutex_unlock(&dev
->struct_mutex
);
4394 drm_gem_object_unreference_unlocked(bo
);
4398 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
4400 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4402 intel_crtc
->cursor_x
= x
;
4403 intel_crtc
->cursor_y
= y
;
4405 intel_crtc_update_cursor(crtc
);
4410 /** Sets the color ramps on behalf of RandR */
4411 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
4412 u16 blue
, int regno
)
4414 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4416 intel_crtc
->lut_r
[regno
] = red
>> 8;
4417 intel_crtc
->lut_g
[regno
] = green
>> 8;
4418 intel_crtc
->lut_b
[regno
] = blue
>> 8;
4421 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4422 u16
*blue
, int regno
)
4424 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4426 *red
= intel_crtc
->lut_r
[regno
] << 8;
4427 *green
= intel_crtc
->lut_g
[regno
] << 8;
4428 *blue
= intel_crtc
->lut_b
[regno
] << 8;
4431 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
4432 u16
*blue
, uint32_t size
)
4434 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4440 for (i
= 0; i
< 256; i
++) {
4441 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
4442 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
4443 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
4446 intel_crtc_load_lut(crtc
);
4450 * Get a pipe with a simple mode set on it for doing load-based monitor
4453 * It will be up to the load-detect code to adjust the pipe as appropriate for
4454 * its requirements. The pipe will be connected to no other encoders.
4456 * Currently this code will only succeed if there is a pipe with no encoders
4457 * configured for it. In the future, it could choose to temporarily disable
4458 * some outputs to free up a pipe for its use.
4460 * \return crtc, or NULL if no pipes are available.
4463 /* VESA 640x480x72Hz mode to set on the pipe */
4464 static struct drm_display_mode load_detect_mode
= {
4465 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
4466 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
4469 struct drm_crtc
*intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4470 struct drm_connector
*connector
,
4471 struct drm_display_mode
*mode
,
4474 struct intel_crtc
*intel_crtc
;
4475 struct drm_crtc
*possible_crtc
;
4476 struct drm_crtc
*supported_crtc
=NULL
;
4477 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4478 struct drm_crtc
*crtc
= NULL
;
4479 struct drm_device
*dev
= encoder
->dev
;
4480 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4481 struct drm_crtc_helper_funcs
*crtc_funcs
;
4485 * Algorithm gets a little messy:
4486 * - if the connector already has an assigned crtc, use it (but make
4487 * sure it's on first)
4488 * - try to find the first unused crtc that can drive this connector,
4489 * and use that if we find one
4490 * - if there are no unused crtcs available, try to use the first
4491 * one we found that supports the connector
4494 /* See if we already have a CRTC for this connector */
4495 if (encoder
->crtc
) {
4496 crtc
= encoder
->crtc
;
4497 /* Make sure the crtc and connector are running */
4498 intel_crtc
= to_intel_crtc(crtc
);
4499 *dpms_mode
= intel_crtc
->dpms_mode
;
4500 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4501 crtc_funcs
= crtc
->helper_private
;
4502 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4503 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
4508 /* Find an unused one (if possible) */
4509 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
4511 if (!(encoder
->possible_crtcs
& (1 << i
)))
4513 if (!possible_crtc
->enabled
) {
4514 crtc
= possible_crtc
;
4517 if (!supported_crtc
)
4518 supported_crtc
= possible_crtc
;
4522 * If we didn't find an unused CRTC, don't use any.
4528 encoder
->crtc
= crtc
;
4529 connector
->encoder
= encoder
;
4530 intel_encoder
->load_detect_temp
= true;
4532 intel_crtc
= to_intel_crtc(crtc
);
4533 *dpms_mode
= intel_crtc
->dpms_mode
;
4535 if (!crtc
->enabled
) {
4537 mode
= &load_detect_mode
;
4538 drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, crtc
->fb
);
4540 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
4541 crtc_funcs
= crtc
->helper_private
;
4542 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
4545 /* Add this connector to the crtc */
4546 encoder_funcs
->mode_set(encoder
, &crtc
->mode
, &crtc
->mode
);
4547 encoder_funcs
->commit(encoder
);
4549 /* let the connector get through one full cycle before testing */
4550 intel_wait_for_vblank(dev
);
4555 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
4556 struct drm_connector
*connector
, int dpms_mode
)
4558 struct drm_encoder
*encoder
= &intel_encoder
->enc
;
4559 struct drm_device
*dev
= encoder
->dev
;
4560 struct drm_crtc
*crtc
= encoder
->crtc
;
4561 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
4562 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
4564 if (intel_encoder
->load_detect_temp
) {
4565 encoder
->crtc
= NULL
;
4566 connector
->encoder
= NULL
;
4567 intel_encoder
->load_detect_temp
= false;
4568 crtc
->enabled
= drm_helper_crtc_in_use(crtc
);
4569 drm_helper_disable_unused_functions(dev
);
4572 /* Switch crtc and encoder back off if necessary */
4573 if (crtc
->enabled
&& dpms_mode
!= DRM_MODE_DPMS_ON
) {
4574 if (encoder
->crtc
== crtc
)
4575 encoder_funcs
->dpms(encoder
, dpms_mode
);
4576 crtc_funcs
->dpms(crtc
, dpms_mode
);
4580 /* Returns the clock of the currently programmed mode of the given pipe. */
4581 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
4583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4584 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4585 int pipe
= intel_crtc
->pipe
;
4586 u32 dpll
= I915_READ((pipe
== 0) ? DPLL_A
: DPLL_B
);
4588 intel_clock_t clock
;
4590 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
4591 fp
= I915_READ((pipe
== 0) ? FPA0
: FPB0
);
4593 fp
= I915_READ((pipe
== 0) ? FPA1
: FPB1
);
4595 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
4596 if (IS_PINEVIEW(dev
)) {
4597 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
4598 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4600 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
4601 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
4605 if (IS_PINEVIEW(dev
))
4606 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
4607 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
4609 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
4610 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4612 switch (dpll
& DPLL_MODE_MASK
) {
4613 case DPLLB_MODE_DAC_SERIAL
:
4614 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
4617 case DPLLB_MODE_LVDS
:
4618 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
4622 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4623 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
4627 /* XXX: Handle the 100Mhz refclk */
4628 intel_clock(dev
, 96000, &clock
);
4630 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
4633 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
4634 DPLL_FPA01_P1_POST_DIV_SHIFT
);
4637 if ((dpll
& PLL_REF_INPUT_MASK
) ==
4638 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
4639 /* XXX: might not be 66MHz */
4640 intel_clock(dev
, 66000, &clock
);
4642 intel_clock(dev
, 48000, &clock
);
4644 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
4647 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
4648 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
4650 if (dpll
& PLL_P2_DIVIDE_BY_4
)
4655 intel_clock(dev
, 48000, &clock
);
4659 /* XXX: It would be nice to validate the clocks, but we can't reuse
4660 * i830PllIsValid() because it relies on the xf86_config connector
4661 * configuration being accurate, which it isn't necessarily.
4667 /** Returns the currently programmed mode of the given pipe. */
4668 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
4669 struct drm_crtc
*crtc
)
4671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4672 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4673 int pipe
= intel_crtc
->pipe
;
4674 struct drm_display_mode
*mode
;
4675 int htot
= I915_READ((pipe
== 0) ? HTOTAL_A
: HTOTAL_B
);
4676 int hsync
= I915_READ((pipe
== 0) ? HSYNC_A
: HSYNC_B
);
4677 int vtot
= I915_READ((pipe
== 0) ? VTOTAL_A
: VTOTAL_B
);
4678 int vsync
= I915_READ((pipe
== 0) ? VSYNC_A
: VSYNC_B
);
4680 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
4684 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
4685 mode
->hdisplay
= (htot
& 0xffff) + 1;
4686 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
4687 mode
->hsync_start
= (hsync
& 0xffff) + 1;
4688 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
4689 mode
->vdisplay
= (vtot
& 0xffff) + 1;
4690 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
4691 mode
->vsync_start
= (vsync
& 0xffff) + 1;
4692 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
4694 drm_mode_set_name(mode
);
4695 drm_mode_set_crtcinfo(mode
, 0);
4700 #define GPU_IDLE_TIMEOUT 500 /* ms */
4702 /* When this timer fires, we've been idle for awhile */
4703 static void intel_gpu_idle_timer(unsigned long arg
)
4705 struct drm_device
*dev
= (struct drm_device
*)arg
;
4706 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4708 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4710 dev_priv
->busy
= false;
4712 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4715 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4717 static void intel_crtc_idle_timer(unsigned long arg
)
4719 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
4720 struct drm_crtc
*crtc
= &intel_crtc
->base
;
4721 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
4723 DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4725 intel_crtc
->busy
= false;
4727 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
4730 static void intel_increase_pllclock(struct drm_crtc
*crtc
, bool schedule
)
4732 struct drm_device
*dev
= crtc
->dev
;
4733 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4734 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4735 int pipe
= intel_crtc
->pipe
;
4736 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4737 int dpll
= I915_READ(dpll_reg
);
4739 if (HAS_PCH_SPLIT(dev
))
4742 if (!dev_priv
->lvds_downclock_avail
)
4745 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
4746 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4748 /* Unlock panel regs */
4749 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4752 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
4753 I915_WRITE(dpll_reg
, dpll
);
4754 dpll
= I915_READ(dpll_reg
);
4755 intel_wait_for_vblank(dev
);
4756 dpll
= I915_READ(dpll_reg
);
4757 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
4758 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4760 /* ...and lock them again */
4761 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4764 /* Schedule downclock */
4766 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4767 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4770 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
4772 struct drm_device
*dev
= crtc
->dev
;
4773 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4774 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4775 int pipe
= intel_crtc
->pipe
;
4776 int dpll_reg
= (pipe
== 0) ? DPLL_A
: DPLL_B
;
4777 int dpll
= I915_READ(dpll_reg
);
4779 if (HAS_PCH_SPLIT(dev
))
4782 if (!dev_priv
->lvds_downclock_avail
)
4786 * Since this is called by a timer, we should never get here in
4789 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
4790 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4792 /* Unlock panel regs */
4793 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) |
4796 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
4797 I915_WRITE(dpll_reg
, dpll
);
4798 dpll
= I915_READ(dpll_reg
);
4799 intel_wait_for_vblank(dev
);
4800 dpll
= I915_READ(dpll_reg
);
4801 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
4802 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4804 /* ...and lock them again */
4805 I915_WRITE(PP_CONTROL
, I915_READ(PP_CONTROL
) & 0x3);
4811 * intel_idle_update - adjust clocks for idleness
4812 * @work: work struct
4814 * Either the GPU or display (or both) went idle. Check the busy status
4815 * here and adjust the CRTC and GPU clocks as necessary.
4817 static void intel_idle_update(struct work_struct
*work
)
4819 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
4821 struct drm_device
*dev
= dev_priv
->dev
;
4822 struct drm_crtc
*crtc
;
4823 struct intel_crtc
*intel_crtc
;
4826 if (!i915_powersave
)
4829 mutex_lock(&dev
->struct_mutex
);
4831 i915_update_gfx_val(dev_priv
);
4833 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4834 /* Skip inactive CRTCs */
4839 intel_crtc
= to_intel_crtc(crtc
);
4840 if (!intel_crtc
->busy
)
4841 intel_decrease_pllclock(crtc
);
4844 if ((enabled
== 1) && (IS_I945G(dev
) || IS_I945GM(dev
))) {
4845 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4846 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
4849 mutex_unlock(&dev
->struct_mutex
);
4853 * intel_mark_busy - mark the GPU and possibly the display busy
4855 * @obj: object we're operating on
4857 * Callers can use this function to indicate that the GPU is busy processing
4858 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
4859 * buffer), we'll also mark the display as busy, so we know to increase its
4862 void intel_mark_busy(struct drm_device
*dev
, struct drm_gem_object
*obj
)
4864 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4865 struct drm_crtc
*crtc
= NULL
;
4866 struct intel_framebuffer
*intel_fb
;
4867 struct intel_crtc
*intel_crtc
;
4869 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4872 if (!dev_priv
->busy
) {
4873 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4876 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4877 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4878 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4879 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4881 dev_priv
->busy
= true;
4883 mod_timer(&dev_priv
->idle_timer
, jiffies
+
4884 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
4886 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
4890 intel_crtc
= to_intel_crtc(crtc
);
4891 intel_fb
= to_intel_framebuffer(crtc
->fb
);
4892 if (intel_fb
->obj
== obj
) {
4893 if (!intel_crtc
->busy
) {
4894 if (IS_I945G(dev
) || IS_I945GM(dev
)) {
4897 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4898 fw_blc_self
= I915_READ(FW_BLC_SELF
);
4899 fw_blc_self
&= ~FW_BLC_SELF_EN
;
4900 I915_WRITE(FW_BLC_SELF
, fw_blc_self
| FW_BLC_SELF_EN_MASK
);
4902 /* Non-busy -> busy, upclock */
4903 intel_increase_pllclock(crtc
, true);
4904 intel_crtc
->busy
= true;
4906 /* Busy -> busy, put off timer */
4907 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
4908 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
4914 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
4916 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4918 drm_crtc_cleanup(crtc
);
4922 struct intel_unpin_work
{
4923 struct work_struct work
;
4924 struct drm_device
*dev
;
4925 struct drm_gem_object
*old_fb_obj
;
4926 struct drm_gem_object
*pending_flip_obj
;
4927 struct drm_pending_vblank_event
*event
;
4931 static void intel_unpin_work_fn(struct work_struct
*__work
)
4933 struct intel_unpin_work
*work
=
4934 container_of(__work
, struct intel_unpin_work
, work
);
4936 mutex_lock(&work
->dev
->struct_mutex
);
4937 i915_gem_object_unpin(work
->old_fb_obj
);
4938 drm_gem_object_unreference(work
->pending_flip_obj
);
4939 drm_gem_object_unreference(work
->old_fb_obj
);
4940 mutex_unlock(&work
->dev
->struct_mutex
);
4944 static void do_intel_finish_page_flip(struct drm_device
*dev
,
4945 struct drm_crtc
*crtc
)
4947 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4948 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4949 struct intel_unpin_work
*work
;
4950 struct drm_i915_gem_object
*obj_priv
;
4951 struct drm_pending_vblank_event
*e
;
4953 unsigned long flags
;
4955 /* Ignore early vblank irqs */
4956 if (intel_crtc
== NULL
)
4959 spin_lock_irqsave(&dev
->event_lock
, flags
);
4960 work
= intel_crtc
->unpin_work
;
4961 if (work
== NULL
|| !work
->pending
) {
4962 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4966 intel_crtc
->unpin_work
= NULL
;
4967 drm_vblank_put(dev
, intel_crtc
->pipe
);
4971 do_gettimeofday(&now
);
4972 e
->event
.sequence
= drm_vblank_count(dev
, intel_crtc
->pipe
);
4973 e
->event
.tv_sec
= now
.tv_sec
;
4974 e
->event
.tv_usec
= now
.tv_usec
;
4975 list_add_tail(&e
->base
.link
,
4976 &e
->base
.file_priv
->event_list
);
4977 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
4980 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
4982 obj_priv
= to_intel_bo(work
->pending_flip_obj
);
4984 /* Initial scanout buffer will have a 0 pending flip count */
4985 if ((atomic_read(&obj_priv
->pending_flip
) == 0) ||
4986 atomic_dec_and_test(&obj_priv
->pending_flip
))
4987 DRM_WAKEUP(&dev_priv
->pending_flip_queue
);
4988 schedule_work(&work
->work
);
4990 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
4993 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
4995 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
4996 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
4998 do_intel_finish_page_flip(dev
, crtc
);
5001 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
5003 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5004 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
5006 do_intel_finish_page_flip(dev
, crtc
);
5009 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
5011 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5012 struct intel_crtc
*intel_crtc
=
5013 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
5014 unsigned long flags
;
5016 spin_lock_irqsave(&dev
->event_lock
, flags
);
5017 if (intel_crtc
->unpin_work
) {
5018 intel_crtc
->unpin_work
->pending
= 1;
5020 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5022 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5025 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
5026 struct drm_framebuffer
*fb
,
5027 struct drm_pending_vblank_event
*event
)
5029 struct drm_device
*dev
= crtc
->dev
;
5030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5031 struct intel_framebuffer
*intel_fb
;
5032 struct drm_i915_gem_object
*obj_priv
;
5033 struct drm_gem_object
*obj
;
5034 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5035 struct intel_unpin_work
*work
;
5036 unsigned long flags
, offset
;
5037 int pipesrc_reg
= (intel_crtc
->pipe
== 0) ? PIPEASRC
: PIPEBSRC
;
5041 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
5045 work
->event
= event
;
5046 work
->dev
= crtc
->dev
;
5047 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5048 work
->old_fb_obj
= intel_fb
->obj
;
5049 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
5051 /* We borrow the event spin lock for protecting unpin_work */
5052 spin_lock_irqsave(&dev
->event_lock
, flags
);
5053 if (intel_crtc
->unpin_work
) {
5054 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5057 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5060 intel_crtc
->unpin_work
= work
;
5061 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5063 intel_fb
= to_intel_framebuffer(fb
);
5064 obj
= intel_fb
->obj
;
5066 mutex_lock(&dev
->struct_mutex
);
5067 ret
= intel_pin_and_fence_fb_obj(dev
, obj
);
5071 /* Reference the objects for the scheduled work. */
5072 drm_gem_object_reference(work
->old_fb_obj
);
5073 drm_gem_object_reference(obj
);
5076 ret
= i915_gem_object_flush_write_domain(obj
);
5080 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
5084 obj_priv
= to_intel_bo(obj
);
5085 atomic_inc(&obj_priv
->pending_flip
);
5086 work
->pending_flip_obj
= obj
;
5088 if (intel_crtc
->plane
)
5089 flip_mask
= I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT
;
5091 flip_mask
= I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT
;
5093 /* Wait for any previous flip to finish */
5095 while (I915_READ(ISR
) & flip_mask
)
5098 /* Offset into the new buffer for cases of shared fbs between CRTCs */
5099 offset
= obj_priv
->gtt_offset
;
5100 offset
+= (crtc
->y
* fb
->pitch
) + (crtc
->x
* (fb
->bits_per_pixel
) / 8);
5103 if (IS_I965G(dev
)) {
5104 OUT_RING(MI_DISPLAY_FLIP
|
5105 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5106 OUT_RING(fb
->pitch
);
5107 OUT_RING(offset
| obj_priv
->tiling_mode
);
5108 pipesrc
= I915_READ(pipesrc_reg
);
5109 OUT_RING(pipesrc
& 0x0fff0fff);
5111 OUT_RING(MI_DISPLAY_FLIP_I915
|
5112 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
5113 OUT_RING(fb
->pitch
);
5119 mutex_unlock(&dev
->struct_mutex
);
5121 trace_i915_flip_request(intel_crtc
->plane
, obj
);
5126 drm_gem_object_unreference(work
->old_fb_obj
);
5127 drm_gem_object_unreference(obj
);
5129 mutex_unlock(&dev
->struct_mutex
);
5131 spin_lock_irqsave(&dev
->event_lock
, flags
);
5132 intel_crtc
->unpin_work
= NULL
;
5133 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
5140 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
5141 .dpms
= intel_crtc_dpms
,
5142 .mode_fixup
= intel_crtc_mode_fixup
,
5143 .mode_set
= intel_crtc_mode_set
,
5144 .mode_set_base
= intel_pipe_set_base
,
5145 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
5146 .prepare
= intel_crtc_prepare
,
5147 .commit
= intel_crtc_commit
,
5148 .load_lut
= intel_crtc_load_lut
,
5151 static const struct drm_crtc_funcs intel_crtc_funcs
= {
5152 .cursor_set
= intel_crtc_cursor_set
,
5153 .cursor_move
= intel_crtc_cursor_move
,
5154 .gamma_set
= intel_crtc_gamma_set
,
5155 .set_config
= drm_crtc_helper_set_config
,
5156 .destroy
= intel_crtc_destroy
,
5157 .page_flip
= intel_crtc_page_flip
,
5161 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
5163 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5164 struct intel_crtc
*intel_crtc
;
5167 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
5168 if (intel_crtc
== NULL
)
5171 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
5173 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
5174 intel_crtc
->pipe
= pipe
;
5175 intel_crtc
->plane
= pipe
;
5176 for (i
= 0; i
< 256; i
++) {
5177 intel_crtc
->lut_r
[i
] = i
;
5178 intel_crtc
->lut_g
[i
] = i
;
5179 intel_crtc
->lut_b
[i
] = i
;
5182 /* Swap pipes & planes for FBC on pre-965 */
5183 intel_crtc
->pipe
= pipe
;
5184 intel_crtc
->plane
= pipe
;
5185 if (IS_MOBILE(dev
) && (IS_I9XX(dev
) && !IS_I965G(dev
))) {
5186 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5187 intel_crtc
->plane
= ((pipe
== 0) ? 1 : 0);
5190 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
5191 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
5192 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
5193 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
5195 intel_crtc
->cursor_addr
= 0;
5196 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
5197 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
5199 intel_crtc
->busy
= false;
5201 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
5202 (unsigned long)intel_crtc
);
5205 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
5206 struct drm_file
*file_priv
)
5208 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5209 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
5210 struct drm_mode_object
*drmmode_obj
;
5211 struct intel_crtc
*crtc
;
5214 DRM_ERROR("called with no initialization\n");
5218 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
5219 DRM_MODE_OBJECT_CRTC
);
5222 DRM_ERROR("no such CRTC id\n");
5226 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
5227 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
5232 struct drm_crtc
*intel_get_crtc_from_pipe(struct drm_device
*dev
, int pipe
)
5234 struct drm_crtc
*crtc
= NULL
;
5236 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5237 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5238 if (intel_crtc
->pipe
== pipe
)
5244 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
5247 struct drm_encoder
*encoder
;
5250 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
5251 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
5252 if (type_mask
& intel_encoder
->clone_mask
)
5253 index_mask
|= (1 << entry
);
5260 static void intel_setup_outputs(struct drm_device
*dev
)
5262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5263 struct drm_encoder
*encoder
;
5264 bool dpd_is_edp
= false;
5266 if (IS_MOBILE(dev
) && !IS_I830(dev
))
5267 intel_lvds_init(dev
);
5269 if (HAS_PCH_SPLIT(dev
)) {
5270 dpd_is_edp
= intel_dpd_is_edp(dev
);
5272 if (IS_MOBILE(dev
) && (I915_READ(DP_A
) & DP_DETECTED
))
5273 intel_dp_init(dev
, DP_A
);
5275 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5276 intel_dp_init(dev
, PCH_DP_D
);
5279 intel_crt_init(dev
);
5281 if (HAS_PCH_SPLIT(dev
)) {
5284 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
5285 /* PCH SDVOB multiplex with HDMIB */
5286 found
= intel_sdvo_init(dev
, PCH_SDVOB
);
5288 intel_hdmi_init(dev
, HDMIB
);
5289 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
5290 intel_dp_init(dev
, PCH_DP_B
);
5293 if (I915_READ(HDMIC
) & PORT_DETECTED
)
5294 intel_hdmi_init(dev
, HDMIC
);
5296 if (I915_READ(HDMID
) & PORT_DETECTED
)
5297 intel_hdmi_init(dev
, HDMID
);
5299 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
5300 intel_dp_init(dev
, PCH_DP_C
);
5302 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
5303 intel_dp_init(dev
, PCH_DP_D
);
5305 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
5308 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5309 DRM_DEBUG_KMS("probing SDVOB\n");
5310 found
= intel_sdvo_init(dev
, SDVOB
);
5311 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
5312 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5313 intel_hdmi_init(dev
, SDVOB
);
5316 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
5317 DRM_DEBUG_KMS("probing DP_B\n");
5318 intel_dp_init(dev
, DP_B
);
5322 /* Before G4X SDVOC doesn't have its own detect register */
5324 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
5325 DRM_DEBUG_KMS("probing SDVOC\n");
5326 found
= intel_sdvo_init(dev
, SDVOC
);
5329 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
5331 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
5332 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5333 intel_hdmi_init(dev
, SDVOC
);
5335 if (SUPPORTS_INTEGRATED_DP(dev
)) {
5336 DRM_DEBUG_KMS("probing DP_C\n");
5337 intel_dp_init(dev
, DP_C
);
5341 if (SUPPORTS_INTEGRATED_DP(dev
) &&
5342 (I915_READ(DP_D
) & DP_DETECTED
)) {
5343 DRM_DEBUG_KMS("probing DP_D\n");
5344 intel_dp_init(dev
, DP_D
);
5346 } else if (IS_GEN2(dev
))
5347 intel_dvo_init(dev
);
5349 if (SUPPORTS_TV(dev
))
5352 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
5353 struct intel_encoder
*intel_encoder
= enc_to_intel_encoder(encoder
);
5355 encoder
->possible_crtcs
= intel_encoder
->crtc_mask
;
5356 encoder
->possible_clones
= intel_encoder_clones(dev
,
5357 intel_encoder
->clone_mask
);
5361 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
5363 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5365 drm_framebuffer_cleanup(fb
);
5366 drm_gem_object_unreference_unlocked(intel_fb
->obj
);
5371 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
5372 struct drm_file
*file_priv
,
5373 unsigned int *handle
)
5375 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
5376 struct drm_gem_object
*object
= intel_fb
->obj
;
5378 return drm_gem_handle_create(file_priv
, object
, handle
);
5381 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
5382 .destroy
= intel_user_framebuffer_destroy
,
5383 .create_handle
= intel_user_framebuffer_create_handle
,
5386 int intel_framebuffer_init(struct drm_device
*dev
,
5387 struct intel_framebuffer
*intel_fb
,
5388 struct drm_mode_fb_cmd
*mode_cmd
,
5389 struct drm_gem_object
*obj
)
5393 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
5395 DRM_ERROR("framebuffer init failed %d\n", ret
);
5399 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
5400 intel_fb
->obj
= obj
;
5404 static struct drm_framebuffer
*
5405 intel_user_framebuffer_create(struct drm_device
*dev
,
5406 struct drm_file
*filp
,
5407 struct drm_mode_fb_cmd
*mode_cmd
)
5409 struct drm_gem_object
*obj
;
5410 struct intel_framebuffer
*intel_fb
;
5413 obj
= drm_gem_object_lookup(dev
, filp
, mode_cmd
->handle
);
5417 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5421 ret
= intel_framebuffer_init(dev
, intel_fb
,
5424 drm_gem_object_unreference_unlocked(obj
);
5429 return &intel_fb
->base
;
5432 static const struct drm_mode_config_funcs intel_mode_funcs
= {
5433 .fb_create
= intel_user_framebuffer_create
,
5434 .output_poll_changed
= intel_fb_output_poll_changed
,
5437 static struct drm_gem_object
*
5438 intel_alloc_power_context(struct drm_device
*dev
)
5440 struct drm_gem_object
*pwrctx
;
5443 pwrctx
= i915_gem_alloc_object(dev
, 4096);
5445 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5449 mutex_lock(&dev
->struct_mutex
);
5450 ret
= i915_gem_object_pin(pwrctx
, 4096);
5452 DRM_ERROR("failed to pin power context: %d\n", ret
);
5456 ret
= i915_gem_object_set_to_gtt_domain(pwrctx
, 1);
5458 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
5461 mutex_unlock(&dev
->struct_mutex
);
5466 i915_gem_object_unpin(pwrctx
);
5468 drm_gem_object_unreference(pwrctx
);
5469 mutex_unlock(&dev
->struct_mutex
);
5473 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
5475 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5478 rgvswctl
= I915_READ16(MEMSWCTL
);
5479 if (rgvswctl
& MEMCTL_CMD_STS
) {
5480 DRM_DEBUG("gpu busy, RCS change rejected\n");
5481 return false; /* still busy with another command */
5484 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
5485 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
5486 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5487 POSTING_READ16(MEMSWCTL
);
5489 rgvswctl
|= MEMCTL_CMD_STS
;
5490 I915_WRITE16(MEMSWCTL
, rgvswctl
);
5495 void ironlake_enable_drps(struct drm_device
*dev
)
5497 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5498 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
5499 u8 fmax
, fmin
, fstart
, vstart
;
5502 /* 100ms RC evaluation intervals */
5503 I915_WRITE(RCUPEI
, 100000);
5504 I915_WRITE(RCDNEI
, 100000);
5506 /* Set max/min thresholds to 90ms and 80ms respectively */
5507 I915_WRITE(RCBMAXAVG
, 90000);
5508 I915_WRITE(RCBMINAVG
, 80000);
5510 I915_WRITE(MEMIHYST
, 1);
5512 /* Set up min, max, and cur for interrupt handling */
5513 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
5514 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
5515 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
5516 MEMMODE_FSTART_SHIFT
;
5519 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
5522 dev_priv
->fmax
= fstart
; /* IPS callback will increase this */
5523 dev_priv
->fstart
= fstart
;
5525 dev_priv
->max_delay
= fmax
;
5526 dev_priv
->min_delay
= fmin
;
5527 dev_priv
->cur_delay
= fstart
;
5529 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax
, fmin
,
5532 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
5535 * Interrupts will be enabled in ironlake_irq_postinstall
5538 I915_WRITE(VIDSTART
, vstart
);
5539 POSTING_READ(VIDSTART
);
5541 rgvmodectl
|= MEMMODE_SWMODE_EN
;
5542 I915_WRITE(MEMMODECTL
, rgvmodectl
);
5544 while (I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) {
5546 DRM_ERROR("stuck trying to change perf mode\n");
5553 ironlake_set_drps(dev
, fstart
);
5555 dev_priv
->last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
5557 dev_priv
->last_time1
= jiffies_to_msecs(jiffies
);
5558 dev_priv
->last_count2
= I915_READ(0x112f4);
5559 getrawmonotonic(&dev_priv
->last_time2
);
5562 void ironlake_disable_drps(struct drm_device
*dev
)
5564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5565 u16 rgvswctl
= I915_READ16(MEMSWCTL
);
5567 /* Ack interrupts, disable EFC interrupt */
5568 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
5569 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
5570 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
5571 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
5572 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
5574 /* Go back to the starting frequency */
5575 ironlake_set_drps(dev
, dev_priv
->fstart
);
5577 rgvswctl
|= MEMCTL_CMD_STS
;
5578 I915_WRITE(MEMSWCTL
, rgvswctl
);
5583 static unsigned long intel_pxfreq(u32 vidfreq
)
5586 int div
= (vidfreq
& 0x3f0000) >> 16;
5587 int post
= (vidfreq
& 0x3000) >> 12;
5588 int pre
= (vidfreq
& 0x7);
5593 freq
= ((div
* 133333) / ((1<<post
) * pre
));
5598 void intel_init_emon(struct drm_device
*dev
)
5600 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5605 /* Disable to program */
5609 /* Program energy weights for various events */
5610 I915_WRITE(SDEW
, 0x15040d00);
5611 I915_WRITE(CSIEW0
, 0x007f0000);
5612 I915_WRITE(CSIEW1
, 0x1e220004);
5613 I915_WRITE(CSIEW2
, 0x04000004);
5615 for (i
= 0; i
< 5; i
++)
5616 I915_WRITE(PEW
+ (i
* 4), 0);
5617 for (i
= 0; i
< 3; i
++)
5618 I915_WRITE(DEW
+ (i
* 4), 0);
5620 /* Program P-state weights to account for frequency power adjustment */
5621 for (i
= 0; i
< 16; i
++) {
5622 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
5623 unsigned long freq
= intel_pxfreq(pxvidfreq
);
5624 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
5629 val
*= (freq
/ 1000);
5631 val
/= (127*127*900);
5633 DRM_ERROR("bad pxval: %ld\n", val
);
5636 /* Render standby states get 0 weight */
5640 for (i
= 0; i
< 4; i
++) {
5641 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
5642 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
5643 I915_WRITE(PXW
+ (i
* 4), val
);
5646 /* Adjust magic regs to magic values (more experimental results) */
5647 I915_WRITE(OGW0
, 0);
5648 I915_WRITE(OGW1
, 0);
5649 I915_WRITE(EG0
, 0x00007f00);
5650 I915_WRITE(EG1
, 0x0000000e);
5651 I915_WRITE(EG2
, 0x000e0000);
5652 I915_WRITE(EG3
, 0x68000300);
5653 I915_WRITE(EG4
, 0x42000000);
5654 I915_WRITE(EG5
, 0x00140031);
5658 for (i
= 0; i
< 8; i
++)
5659 I915_WRITE(PXWL
+ (i
* 4), 0);
5661 /* Enable PMON + select events */
5662 I915_WRITE(ECR
, 0x80000019);
5664 lcfuse
= I915_READ(LCFUSE02
);
5666 dev_priv
->corr
= (lcfuse
& LCFUSE_HIV_MASK
);
5669 void intel_init_clock_gating(struct drm_device
*dev
)
5671 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5674 * Disable clock gating reported to work incorrectly according to the
5675 * specs, but enable as much else as we can.
5677 if (HAS_PCH_SPLIT(dev
)) {
5678 uint32_t dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
;
5680 if (IS_IRONLAKE(dev
)) {
5681 /* Required for FBC */
5682 dspclk_gate
|= DPFDUNIT_CLOCK_GATE_DISABLE
;
5683 /* Required for CxSR */
5684 dspclk_gate
|= DPARBUNIT_CLOCK_GATE_DISABLE
;
5686 I915_WRITE(PCH_3DCGDIS0
,
5687 MARIUNIT_CLOCK_GATE_DISABLE
|
5688 SVSMUNIT_CLOCK_GATE_DISABLE
);
5691 I915_WRITE(PCH_DSPCLK_GATE_D
, dspclk_gate
);
5694 * According to the spec the following bits should be set in
5695 * order to enable memory self-refresh
5696 * The bit 22/21 of 0x42004
5697 * The bit 5 of 0x42020
5698 * The bit 15 of 0x45000
5700 if (IS_IRONLAKE(dev
)) {
5701 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5702 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5703 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5704 I915_WRITE(ILK_DSPCLK_GATE
,
5705 (I915_READ(ILK_DSPCLK_GATE
) |
5706 ILK_DPARB_CLK_GATE
));
5707 I915_WRITE(DISP_ARB_CTL
,
5708 (I915_READ(DISP_ARB_CTL
) |
5712 * Based on the document from hardware guys the following bits
5713 * should be set unconditionally in order to enable FBC.
5714 * The bit 22 of 0x42000
5715 * The bit 22 of 0x42004
5716 * The bit 7,8,9 of 0x42020.
5718 if (IS_IRONLAKE_M(dev
)) {
5719 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5720 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5722 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5723 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5725 I915_WRITE(ILK_DSPCLK_GATE
,
5726 I915_READ(ILK_DSPCLK_GATE
) |
5732 } else if (IS_G4X(dev
)) {
5733 uint32_t dspclk_gate
;
5734 I915_WRITE(RENCLK_GATE_D1
, 0);
5735 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5736 GS_UNIT_CLOCK_GATE_DISABLE
|
5737 CL_UNIT_CLOCK_GATE_DISABLE
);
5738 I915_WRITE(RAMCLK_GATE_D
, 0);
5739 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5740 OVRUNIT_CLOCK_GATE_DISABLE
|
5741 OVCUNIT_CLOCK_GATE_DISABLE
;
5743 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5744 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5745 } else if (IS_I965GM(dev
)) {
5746 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5747 I915_WRITE(RENCLK_GATE_D2
, 0);
5748 I915_WRITE(DSPCLK_GATE_D
, 0);
5749 I915_WRITE(RAMCLK_GATE_D
, 0);
5750 I915_WRITE16(DEUC
, 0);
5751 } else if (IS_I965G(dev
)) {
5752 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5753 I965_RCC_CLOCK_GATE_DISABLE
|
5754 I965_RCPB_CLOCK_GATE_DISABLE
|
5755 I965_ISC_CLOCK_GATE_DISABLE
|
5756 I965_FBC_CLOCK_GATE_DISABLE
);
5757 I915_WRITE(RENCLK_GATE_D2
, 0);
5758 } else if (IS_I9XX(dev
)) {
5759 u32 dstate
= I915_READ(D_STATE
);
5761 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5762 DSTATE_DOT_CLOCK_GATING
;
5763 I915_WRITE(D_STATE
, dstate
);
5764 } else if (IS_I85X(dev
) || IS_I865G(dev
)) {
5765 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5766 } else if (IS_I830(dev
)) {
5767 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5771 * GPU can automatically power down the render unit if given a page
5774 if (I915_HAS_RC6(dev
) && drm_core_check_feature(dev
, DRIVER_MODESET
)) {
5775 struct drm_i915_gem_object
*obj_priv
= NULL
;
5777 if (dev_priv
->pwrctx
) {
5778 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
5780 struct drm_gem_object
*pwrctx
;
5782 pwrctx
= intel_alloc_power_context(dev
);
5784 dev_priv
->pwrctx
= pwrctx
;
5785 obj_priv
= to_intel_bo(pwrctx
);
5790 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
| PWRCTX_EN
);
5791 I915_WRITE(MCHBAR_RENDER_STANDBY
,
5792 I915_READ(MCHBAR_RENDER_STANDBY
) & ~RCX_SW_EXIT
);
5797 /* Set up chip specific display functions */
5798 static void intel_init_display(struct drm_device
*dev
)
5800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5802 /* We always want a DPMS function */
5803 if (HAS_PCH_SPLIT(dev
))
5804 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
5806 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
5808 if (I915_HAS_FBC(dev
)) {
5809 if (IS_IRONLAKE_M(dev
)) {
5810 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
5811 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
5812 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
5813 } else if (IS_GM45(dev
)) {
5814 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
5815 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
5816 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
5817 } else if (IS_I965GM(dev
)) {
5818 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
5819 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
5820 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
5822 /* 855GM needs testing */
5825 /* Returns the core display clock speed */
5826 if (IS_I945G(dev
) || (IS_G33(dev
) && ! IS_PINEVIEW_M(dev
)))
5827 dev_priv
->display
.get_display_clock_speed
=
5828 i945_get_display_clock_speed
;
5829 else if (IS_I915G(dev
))
5830 dev_priv
->display
.get_display_clock_speed
=
5831 i915_get_display_clock_speed
;
5832 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
5833 dev_priv
->display
.get_display_clock_speed
=
5834 i9xx_misc_get_display_clock_speed
;
5835 else if (IS_I915GM(dev
))
5836 dev_priv
->display
.get_display_clock_speed
=
5837 i915gm_get_display_clock_speed
;
5838 else if (IS_I865G(dev
))
5839 dev_priv
->display
.get_display_clock_speed
=
5840 i865_get_display_clock_speed
;
5841 else if (IS_I85X(dev
))
5842 dev_priv
->display
.get_display_clock_speed
=
5843 i855_get_display_clock_speed
;
5845 dev_priv
->display
.get_display_clock_speed
=
5846 i830_get_display_clock_speed
;
5848 /* For FIFO watermark updates */
5849 if (HAS_PCH_SPLIT(dev
)) {
5850 if (IS_IRONLAKE(dev
)) {
5851 if (I915_READ(MLTR_ILK
) & ILK_SRLT_MASK
)
5852 dev_priv
->display
.update_wm
= ironlake_update_wm
;
5854 DRM_DEBUG_KMS("Failed to get proper latency. "
5856 dev_priv
->display
.update_wm
= NULL
;
5859 dev_priv
->display
.update_wm
= NULL
;
5860 } else if (IS_PINEVIEW(dev
)) {
5861 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
5864 dev_priv
->mem_freq
)) {
5865 DRM_INFO("failed to find known CxSR latency "
5866 "(found ddr%s fsb freq %d, mem freq %d), "
5868 (dev_priv
->is_ddr3
== 1) ? "3": "2",
5869 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
5870 /* Disable CxSR and never update its watermark again */
5871 pineview_disable_cxsr(dev
);
5872 dev_priv
->display
.update_wm
= NULL
;
5874 dev_priv
->display
.update_wm
= pineview_update_wm
;
5875 } else if (IS_G4X(dev
))
5876 dev_priv
->display
.update_wm
= g4x_update_wm
;
5877 else if (IS_I965G(dev
))
5878 dev_priv
->display
.update_wm
= i965_update_wm
;
5879 else if (IS_I9XX(dev
)) {
5880 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5881 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
5882 } else if (IS_I85X(dev
)) {
5883 dev_priv
->display
.update_wm
= i9xx_update_wm
;
5884 dev_priv
->display
.get_fifo_size
= i85x_get_fifo_size
;
5886 dev_priv
->display
.update_wm
= i830_update_wm
;
5888 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
5890 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
5895 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5896 * resume, or other times. This quirk makes sure that's the case for
5899 static void quirk_pipea_force (struct drm_device
*dev
)
5901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5903 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
5904 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5907 struct intel_quirk
{
5909 int subsystem_vendor
;
5910 int subsystem_device
;
5911 void (*hook
)(struct drm_device
*dev
);
5914 struct intel_quirk intel_quirks
[] = {
5915 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5916 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force
},
5917 /* HP Mini needs pipe A force quirk (LP: #322104) */
5918 { 0x27ae,0x103c, 0x361a, quirk_pipea_force
},
5920 /* Thinkpad R31 needs pipe A force quirk */
5921 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
5922 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5923 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
5925 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5926 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
5927 /* ThinkPad X40 needs pipe A force quirk */
5929 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5930 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
5932 /* 855 & before need to leave pipe A & dpll A up */
5933 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
5934 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
5937 static void intel_init_quirks(struct drm_device
*dev
)
5939 struct pci_dev
*d
= dev
->pdev
;
5942 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
5943 struct intel_quirk
*q
= &intel_quirks
[i
];
5945 if (d
->device
== q
->device
&&
5946 (d
->subsystem_vendor
== q
->subsystem_vendor
||
5947 q
->subsystem_vendor
== PCI_ANY_ID
) &&
5948 (d
->subsystem_device
== q
->subsystem_device
||
5949 q
->subsystem_device
== PCI_ANY_ID
))
5954 void intel_modeset_init(struct drm_device
*dev
)
5956 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5959 drm_mode_config_init(dev
);
5961 dev
->mode_config
.min_width
= 0;
5962 dev
->mode_config
.min_height
= 0;
5964 dev
->mode_config
.funcs
= (void *)&intel_mode_funcs
;
5966 intel_init_quirks(dev
);
5968 intel_init_display(dev
);
5970 if (IS_I965G(dev
)) {
5971 dev
->mode_config
.max_width
= 8192;
5972 dev
->mode_config
.max_height
= 8192;
5973 } else if (IS_I9XX(dev
)) {
5974 dev
->mode_config
.max_width
= 4096;
5975 dev
->mode_config
.max_height
= 4096;
5977 dev
->mode_config
.max_width
= 2048;
5978 dev
->mode_config
.max_height
= 2048;
5981 /* set memory base */
5983 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 2);
5985 dev
->mode_config
.fb_base
= pci_resource_start(dev
->pdev
, 0);
5987 if (IS_MOBILE(dev
) || IS_I9XX(dev
))
5988 dev_priv
->num_pipe
= 2;
5990 dev_priv
->num_pipe
= 1;
5991 DRM_DEBUG_KMS("%d display pipe%s available.\n",
5992 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
5994 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
5995 intel_crtc_init(dev
, i
);
5998 intel_setup_outputs(dev
);
6000 intel_init_clock_gating(dev
);
6002 if (IS_IRONLAKE_M(dev
)) {
6003 ironlake_enable_drps(dev
);
6004 intel_init_emon(dev
);
6007 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
6008 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
6009 (unsigned long)dev
);
6011 intel_setup_overlay(dev
);
6014 void intel_modeset_cleanup(struct drm_device
*dev
)
6016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6017 struct drm_crtc
*crtc
;
6018 struct intel_crtc
*intel_crtc
;
6020 mutex_lock(&dev
->struct_mutex
);
6022 drm_kms_helper_poll_fini(dev
);
6023 intel_fbdev_fini(dev
);
6025 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6026 /* Skip inactive CRTCs */
6030 intel_crtc
= to_intel_crtc(crtc
);
6031 intel_increase_pllclock(crtc
, false);
6032 del_timer_sync(&intel_crtc
->idle_timer
);
6035 del_timer_sync(&dev_priv
->idle_timer
);
6037 if (dev_priv
->display
.disable_fbc
)
6038 dev_priv
->display
.disable_fbc(dev
);
6040 if (dev_priv
->pwrctx
) {
6041 struct drm_i915_gem_object
*obj_priv
;
6043 obj_priv
= to_intel_bo(dev_priv
->pwrctx
);
6044 I915_WRITE(PWRCTXA
, obj_priv
->gtt_offset
&~ PWRCTX_EN
);
6046 i915_gem_object_unpin(dev_priv
->pwrctx
);
6047 drm_gem_object_unreference(dev_priv
->pwrctx
);
6050 if (IS_IRONLAKE_M(dev
))
6051 ironlake_disable_drps(dev
);
6053 mutex_unlock(&dev
->struct_mutex
);
6055 drm_mode_config_cleanup(dev
);
6060 * Return which encoder is currently attached for connector.
6062 struct drm_encoder
*intel_attached_encoder (struct drm_connector
*connector
)
6064 struct drm_mode_object
*obj
;
6065 struct drm_encoder
*encoder
;
6068 for (i
= 0; i
< DRM_CONNECTOR_MAX_ENCODER
; i
++) {
6069 if (connector
->encoder_ids
[i
] == 0)
6072 obj
= drm_mode_object_find(connector
->dev
,
6073 connector
->encoder_ids
[i
],
6074 DRM_MODE_OBJECT_ENCODER
);
6078 encoder
= obj_to_encoder(obj
);
6085 * set vga decode state - true == enable VGA decode
6087 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
6089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6092 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
6094 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
6096 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
6097 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);