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Merge branch 'linux-3.19' of git://anongit.freedesktop.org/git/nouveau/linux-2.6...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
77
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
82
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
101
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103 {
104 if (!connector->mst_port)
105 return connector->encoder;
106 else
107 return &connector->mst_port->mst_encoders[pipe]->base;
108 }
109
110 typedef struct {
111 int min, max;
112 } intel_range_t;
113
114 typedef struct {
115 int dot_limit;
116 int p2_slow, p2_fast;
117 } intel_p2_t;
118
119 typedef struct intel_limit intel_limit_t;
120 struct intel_limit {
121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
122 intel_p2_t p2;
123 };
124
125 int
126 intel_pch_rawclk(struct drm_device *dev)
127 {
128 struct drm_i915_private *dev_priv = dev->dev_private;
129
130 WARN_ON(!HAS_PCH_SPLIT(dev));
131
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133 }
134
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
137 {
138 if (IS_GEN5(dev)) {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141 } else
142 return 27;
143 }
144
145 static const intel_limit_t intel_limits_i8xx_dac = {
146 .dot = { .min = 25000, .max = 350000 },
147 .vco = { .min = 908000, .max = 1512000 },
148 .n = { .min = 2, .max = 16 },
149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
156 };
157
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
182 };
183
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
208 };
209
210
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
221 .p2_slow = 10,
222 .p2_fast = 10
223 },
224 };
225
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
250 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
264 },
265 };
266
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
280 };
281
282 static const intel_limit_t intel_limits_pineview_lvds = {
283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
293 };
294
295 /* Ironlake / Sandybridge
296 *
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
299 */
300 static const intel_limit_t intel_limits_ironlake_dac = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
311 };
312
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
337 };
338
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
361 .p1 = { .min = 2, .max = 6 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
364 };
365
366 static const intel_limit_t intel_limits_vlv = {
367 /*
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
372 */
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374 .vco = { .min = 4000000, .max = 6000000 },
375 .n = { .min = 1, .max = 7 },
376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
378 .p1 = { .min = 2, .max = 3 },
379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
380 };
381
382 static const intel_limit_t intel_limits_chv = {
383 /*
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
388 */
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396 };
397
398 static void vlv_clock(int refclk, intel_clock_t *clock)
399 {
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
402 if (WARN_ON(clock->n == 0 || clock->p == 0))
403 return;
404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
406 }
407
408 /**
409 * Returns whether any output on the specified pipe is of the specified type
410 */
411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
412 {
413 struct drm_device *dev = crtc->base.dev;
414 struct intel_encoder *encoder;
415
416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
417 if (encoder->type == type)
418 return true;
419
420 return false;
421 }
422
423 /**
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427 * encoder->crtc.
428 */
429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
430 {
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
433
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
436 return true;
437
438 return false;
439 }
440
441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
442 int refclk)
443 {
444 struct drm_device *dev = crtc->base.dev;
445 const intel_limit_t *limit;
446
447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
448 if (intel_is_dual_link_lvds(dev)) {
449 if (refclk == 100000)
450 limit = &intel_limits_ironlake_dual_lvds_100m;
451 else
452 limit = &intel_limits_ironlake_dual_lvds;
453 } else {
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_single_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_single_lvds;
458 }
459 } else
460 limit = &intel_limits_ironlake_dac;
461
462 return limit;
463 }
464
465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
466 {
467 struct drm_device *dev = crtc->base.dev;
468 const intel_limit_t *limit;
469
470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
471 if (intel_is_dual_link_lvds(dev))
472 limit = &intel_limits_g4x_dual_channel_lvds;
473 else
474 limit = &intel_limits_g4x_single_channel_lvds;
475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
477 limit = &intel_limits_g4x_hdmi;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
479 limit = &intel_limits_g4x_sdvo;
480 } else /* The option is for other outputs */
481 limit = &intel_limits_i9xx_sdvo;
482
483 return limit;
484 }
485
486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
487 {
488 struct drm_device *dev = crtc->base.dev;
489 const intel_limit_t *limit;
490
491 if (HAS_PCH_SPLIT(dev))
492 limit = intel_ironlake_limit(crtc, refclk);
493 else if (IS_G4X(dev)) {
494 limit = intel_g4x_limit(crtc);
495 } else if (IS_PINEVIEW(dev)) {
496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
497 limit = &intel_limits_pineview_lvds;
498 else
499 limit = &intel_limits_pineview_sdvo;
500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
502 } else if (IS_VALLEYVIEW(dev)) {
503 limit = &intel_limits_vlv;
504 } else if (!IS_GEN2(dev)) {
505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
506 limit = &intel_limits_i9xx_lvds;
507 else
508 limit = &intel_limits_i9xx_sdvo;
509 } else {
510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
511 limit = &intel_limits_i8xx_lvds;
512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
513 limit = &intel_limits_i8xx_dvo;
514 else
515 limit = &intel_limits_i8xx_dac;
516 }
517 return limit;
518 }
519
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532 {
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534 }
535
536 static void i9xx_clock(int refclk, intel_clock_t *clock)
537 {
538 clock->m = i9xx_dpll_compute_m(clock);
539 clock->p = clock->p1 * clock->p2;
540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
541 return;
542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
544 }
545
546 static void chv_clock(int refclk, intel_clock_t *clock)
547 {
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
553 clock->n << 22);
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555 }
556
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
558 /**
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
561 */
562
563 static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
566 {
567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
574 INTELPllInvalid("m1 out of range\n");
575
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
579
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
585 }
586
587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
591 */
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
593 INTELPllInvalid("dot out of range\n");
594
595 return true;
596 }
597
598 static bool
599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
602 {
603 struct drm_device *dev = crtc->base.dev;
604 intel_clock_t clock;
605 int err = target;
606
607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
608 /*
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
612 */
613 if (intel_is_dual_link_lvds(dev))
614 clock.p2 = limit->p2.p2_fast;
615 else
616 clock.p2 = limit->p2.p2_slow;
617 } else {
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
620 else
621 clock.p2 = limit->p2.p2_fast;
622 }
623
624 memset(best_clock, 0, sizeof(*best_clock));
625
626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
627 clock.m1++) {
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
630 if (clock.m2 >= clock.m1)
631 break;
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
636 int this_err;
637
638 i9xx_clock(refclk, &clock);
639 if (!intel_PLL_is_valid(dev, limit,
640 &clock))
641 continue;
642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657 }
658
659 static bool
660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
663 {
664 struct drm_device *dev = crtc->base.dev;
665 intel_clock_t clock;
666 int err = target;
667
668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
669 /*
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
673 */
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
676 else
677 clock.p2 = limit->p2.p2_slow;
678 } else {
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
681 else
682 clock.p2 = limit->p2.p2_fast;
683 }
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pineview_clock(refclk, &clock);
698 if (!intel_PLL_is_valid(dev, limit,
699 &clock))
700 continue;
701 if (match_clock &&
702 clock.p != match_clock->p)
703 continue;
704
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
707 *best_clock = clock;
708 err = this_err;
709 }
710 }
711 }
712 }
713 }
714
715 return (err != target);
716 }
717
718 static bool
719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722 {
723 struct drm_device *dev = crtc->base.dev;
724 intel_clock_t clock;
725 int max_n;
726 bool found;
727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
729 found = false;
730
731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
732 if (intel_is_dual_link_lvds(dev))
733 clock.p2 = limit->p2.p2_fast;
734 else
735 clock.p2 = limit->p2.p2_slow;
736 } else {
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
739 else
740 clock.p2 = limit->p2.p2_fast;
741 }
742
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
754 int this_err;
755
756 i9xx_clock(refclk, &clock);
757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
759 continue;
760
761 this_err = abs(clock.dot - target);
762 if (this_err < err_most) {
763 *best_clock = clock;
764 err_most = this_err;
765 max_n = clock.n;
766 found = true;
767 }
768 }
769 }
770 }
771 }
772 return found;
773 }
774
775 static bool
776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779 {
780 struct drm_device *dev = crtc->base.dev;
781 intel_clock_t clock;
782 unsigned int bestppm = 1000000;
783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
785 bool found = false;
786
787 target *= 5; /* fast clock */
788
789 memset(best_clock, 0, sizeof(*best_clock));
790
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
796 clock.p = clock.p1 * clock.p2;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
799 unsigned int ppm, diff;
800
801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
802 refclk * clock.m1);
803
804 vlv_clock(refclk, &clock);
805
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
808 continue;
809
810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
812
813 if (ppm < 100 && clock.p > best_clock->p) {
814 bestppm = 0;
815 *best_clock = clock;
816 found = true;
817 }
818
819 if (bestppm >= 10 && ppm < bestppm - 10) {
820 bestppm = ppm;
821 *best_clock = clock;
822 found = true;
823 }
824 }
825 }
826 }
827 }
828
829 return found;
830 }
831
832 static bool
833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
836 {
837 struct drm_device *dev = crtc->base.dev;
838 intel_clock_t clock;
839 uint64_t m2;
840 int found = false;
841
842 memset(best_clock, 0, sizeof(*best_clock));
843
844 /*
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
848 */
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
851
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856
857 clock.p = clock.p1 * clock.p2;
858
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
861
862 if (m2 > INT_MAX/clock.m1)
863 continue;
864
865 clock.m2 = m2;
866
867 chv_clock(refclk, &clock);
868
869 if (!intel_PLL_is_valid(dev, limit, &clock))
870 continue;
871
872 /* based on hardware requirement, prefer bigger p
873 */
874 if (clock.p > best_clock->p) {
875 *best_clock = clock;
876 found = true;
877 }
878 }
879 }
880
881 return found;
882 }
883
884 bool intel_crtc_active(struct drm_crtc *crtc)
885 {
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
890 *
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
893 *
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
896 */
897 return intel_crtc->active && crtc->primary->fb &&
898 intel_crtc->config.adjusted_mode.crtc_clock;
899 }
900
901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902 enum pipe pipe)
903 {
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906
907 return intel_crtc->config.cpu_transcoder;
908 }
909
910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
911 {
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
914 u32 line1, line2;
915 u32 line_mask;
916
917 if (IS_GEN2(dev))
918 line_mask = DSL_LINEMASK_GEN2;
919 else
920 line_mask = DSL_LINEMASK_GEN3;
921
922 line1 = I915_READ(reg) & line_mask;
923 mdelay(5);
924 line2 = I915_READ(reg) & line_mask;
925
926 return line1 == line2;
927 }
928
929 /*
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
932 *
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
936 *
937 * On Gen4 and above:
938 * wait for the pipe register state bit to turn off
939 *
940 * Otherwise:
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
943 *
944 */
945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
946 {
947 struct drm_device *dev = crtc->base.dev;
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
951
952 if (INTEL_INFO(dev)->gen >= 4) {
953 int reg = PIPECONF(cpu_transcoder);
954
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
957 100))
958 WARN(1, "pipe_off wait timed out\n");
959 } else {
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
962 WARN(1, "pipe_off wait timed out\n");
963 }
964 }
965
966 /*
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
970 *
971 * Returns true if @port is connected, false otherwise.
972 */
973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
975 {
976 u32 bit;
977
978 if (HAS_PCH_IBX(dev_priv->dev)) {
979 switch (port->port) {
980 case PORT_B:
981 bit = SDE_PORTB_HOTPLUG;
982 break;
983 case PORT_C:
984 bit = SDE_PORTC_HOTPLUG;
985 break;
986 case PORT_D:
987 bit = SDE_PORTD_HOTPLUG;
988 break;
989 default:
990 return true;
991 }
992 } else {
993 switch (port->port) {
994 case PORT_B:
995 bit = SDE_PORTB_HOTPLUG_CPT;
996 break;
997 case PORT_C:
998 bit = SDE_PORTC_HOTPLUG_CPT;
999 break;
1000 case PORT_D:
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1002 break;
1003 default:
1004 return true;
1005 }
1006 }
1007
1008 return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013 return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
1019 {
1020 int reg;
1021 u32 val;
1022 bool cur_state;
1023
1024 reg = DPLL(pipe);
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035 u32 val;
1036 bool cur_state;
1037
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1041
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055 if (crtc->config.shared_dpll < 0)
1056 return NULL;
1057
1058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1064 bool state)
1065 {
1066 bool cur_state;
1067 struct intel_dpll_hw_state hw_state;
1068
1069 if (WARN (!pll,
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1071 return;
1072
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081 {
1082 int reg;
1083 u32 val;
1084 bool cur_state;
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
1087
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124 {
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130 return;
1131
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1134 return;
1135
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158 {
1159 struct drm_device *dev = dev_priv->dev;
1160 int pp_reg;
1161 u32 val;
1162 enum pipe panel_pipe = PIPE_A;
1163 bool locked = true;
1164
1165 if (WARN_ON(HAS_DDI(dev)))
1166 return;
1167
1168 if (HAS_PCH_SPLIT(dev)) {
1169 u32 port_sel;
1170
1171 pp_reg = PCH_PP_CONTROL;
1172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181 panel_pipe = pipe;
1182 } else {
1183 pp_reg = PP_CONTROL;
1184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
1186 }
1187
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
1190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191 locked = false;
1192
1193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
1195 pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200 {
1201 struct drm_device *dev = dev_priv->dev;
1202 bool cur_state;
1203
1204 if (IS_845G(dev) || IS_I865G(dev))
1205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206 else
1207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1218 {
1219 int reg;
1220 u32 val;
1221 bool cur_state;
1222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223 pipe);
1224
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228 state = true;
1229
1230 if (!intel_display_power_is_enabled(dev_priv,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1246 {
1247 int reg;
1248 u32 val;
1249 bool cur_state;
1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 struct drm_device *dev = dev_priv->dev;
1266 int reg, i;
1267 u32 val;
1268 int cur_pipe;
1269
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
1272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
1274 WARN(val & DISPLAY_PLANE_ENABLE,
1275 "plane %c assertion failure, should be disabled but not\n",
1276 plane_name(pipe));
1277 return;
1278 }
1279
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv, i) {
1282 reg = DSPCNTR(i);
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
1289 }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe)
1294 {
1295 struct drm_device *dev = dev_priv->dev;
1296 int reg, sprite;
1297 u32 val;
1298
1299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1305 }
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
1309 val = I915_READ(reg);
1310 WARN(val & SP_ENABLE,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe, sprite), pipe_name(pipe));
1313 }
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1315 reg = SPRCTL(pipe);
1316 val = I915_READ(reg);
1317 WARN(val & SPRITE_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
1323 WARN(val & DVS_ENABLE,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
1326 }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337 u32 val;
1338 bool enabled;
1339
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349 enum pipe pipe)
1350 {
1351 int reg;
1352 u32 val;
1353 bool enabled;
1354
1355 reg = PCH_TRANSCONF(pipe);
1356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
1358 WARN(enabled,
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360 pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366 if ((val & DP_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373 return false;
1374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376 return false;
1377 } else {
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379 return false;
1380 }
1381 return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1386 {
1387 if ((val & SDVO_ENABLE) == 0)
1388 return false;
1389
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
1391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392 return false;
1393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395 return false;
1396 } else {
1397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398 return false;
1399 }
1400 return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1405 {
1406 if ((val & LVDS_PORT_EN) == 0)
1407 return false;
1408
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411 return false;
1412 } else {
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414 return false;
1415 }
1416 return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421 {
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1423 return false;
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426 return false;
1427 } else {
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429 return false;
1430 }
1431 return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435 enum pipe pipe, int reg, u32 port_sel)
1436 {
1437 u32 val = I915_READ(reg);
1438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg, pipe_name(pipe));
1441
1442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
1444 "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1449 {
1450 u32 val = I915_READ(reg);
1451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg, pipe_name(pipe));
1454
1455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456 && (val & SDVO_PIPE_B_SELECT),
1457 "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe)
1462 {
1463 int reg;
1464 u32 val;
1465
1466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470 reg = PCH_ADPA;
1471 val = I915_READ(reg);
1472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1474 pipe_name(pipe));
1475
1476 reg = PCH_LVDS;
1477 val = I915_READ(reg);
1478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491 if (!IS_VALLEYVIEW(dev))
1492 return;
1493
1494 /*
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498 */
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502 } else {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504 }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
1509 {
1510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
1513 u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv->dev))
1522 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524 I915_WRITE(reg, dpll);
1525 POSTING_READ(reg);
1526 udelay(150);
1527
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532 POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534 /* We do this three times for luck */
1535 I915_WRITE(reg, dpll);
1536 POSTING_READ(reg);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
1548 {
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553 u32 tmp;
1554
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559 mutex_lock(&dev_priv->dpio_lock);
1560
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566 /*
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568 */
1569 udelay(1);
1570
1571 /* Enable PLL */
1572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580 POSTING_READ(DPLL_MD(pipe));
1581
1582 mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587 struct intel_crtc *crtc;
1588 int count = 0;
1589
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
1592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594 return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604 assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615 /*
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1620 */
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624 }
1625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
1641
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1668
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) &&
1671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677 }
1678
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682 return;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
1687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693 u32 val = 0;
1694
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1697
1698 /*
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1701 */
1702 if (pipe == PIPE_B)
1703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712 u32 val;
1713
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1716
1717 /* Set PLL en = 0 */
1718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719 if (pipe != PIPE_A)
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1723
1724 mutex_lock(&dev_priv->dpio_lock);
1725
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736 } else {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740 }
1741
1742 mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
1747 {
1748 u32 port_mask;
1749 int dpll_reg;
1750
1751 switch (dport->port) {
1752 case PORT_B:
1753 port_mask = DPLL_PORTB_READY_MASK;
1754 dpll_reg = DPLL(0);
1755 break;
1756 case PORT_C:
1757 port_mask = DPLL_PORTC_READY_MASK;
1758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_D:
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
1763 break;
1764 default:
1765 BUG();
1766 }
1767
1768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779 if (WARN_ON(pll == NULL))
1780 return;
1781
1782 WARN_ON(!pll->config.crtc_mask);
1783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785 WARN_ON(pll->on);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788 pll->mode_set(dev_priv, pll);
1789 }
1790 }
1791
1792 /**
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1796 *
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1799 */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806 if (WARN_ON(pll == NULL))
1807 return;
1808
1809 if (WARN_ON(pll->config.crtc_mask == 0))
1810 return;
1811
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1815
1816 if (pll->active++) {
1817 WARN_ON(!pll->on);
1818 assert_shared_dpll_enabled(dev_priv, pll);
1819 return;
1820 }
1821 WARN_ON(pll->on);
1822
1823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826 pll->enable(dev_priv, pll);
1827 pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev)->gen < 5);
1838 if (WARN_ON(pll == NULL))
1839 return;
1840
1841 if (WARN_ON(pll->config.crtc_mask == 0))
1842 return;
1843
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
1846 crtc->base.base.id);
1847
1848 if (WARN_ON(pll->active == 0)) {
1849 assert_shared_dpll_disabled(dev_priv, pll);
1850 return;
1851 }
1852
1853 assert_shared_dpll_enabled(dev_priv, pll);
1854 WARN_ON(!pll->on);
1855 if (--pll->active)
1856 return;
1857
1858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859 pll->disable(dev_priv, pll);
1860 pll->on = false;
1861
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
1867 {
1868 struct drm_device *dev = dev_priv->dev;
1869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871 uint32_t reg, val, pipeconf_val;
1872
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv,
1878 intel_crtc_to_shared_dpll(intel_crtc));
1879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
1891 }
1892
1893 reg = PCH_TRANSCONF(pipe);
1894 val = I915_READ(reg);
1895 pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1898 /*
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1901 */
1902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904 }
1905
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908 if (HAS_PCH_IBX(dev_priv->dev) &&
1909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910 val |= TRANS_LEGACY_INTERLACED_ILK;
1911 else
1912 val |= TRANS_INTERLACED;
1913 else
1914 val |= TRANS_PROGRESSIVE;
1915
1916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 enum transcoder cpu_transcoder)
1923 {
1924 u32 val, pipeconf_val;
1925
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
1935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936 I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938 val = TRANS_ENABLE;
1939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
1943 val |= TRANS_INTERLACED;
1944 else
1945 val |= TRANS_PROGRESSIVE;
1946
1947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 enum pipe pipe)
1954 {
1955 struct drm_device *dev = dev_priv->dev;
1956 uint32_t reg, val;
1957
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1964
1965 reg = PCH_TRANSCONF(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1979 }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984 u32 val;
1985
1986 val = I915_READ(LPT_TRANSCONF);
1987 val &= ~TRANS_ENABLE;
1988 I915_WRITE(LPT_TRANSCONF, val);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
1995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996 I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2002 *
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005 */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
2011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012 pipe);
2013 enum pipe pch_transcoder;
2014 int reg;
2015 u32 val;
2016
2017 assert_planes_disabled(dev_priv, pipe);
2018 assert_cursor_disabled(dev_priv, pipe);
2019 assert_sprites_disabled(dev_priv, pipe);
2020
2021 if (HAS_PCH_LPT(dev_priv->dev))
2022 pch_transcoder = TRANSCODER_A;
2023 else
2024 pch_transcoder = pipe;
2025
2026 /*
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2029 * need the check.
2030 */
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
2032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033 assert_dsi_pll_enabled(dev_priv);
2034 else
2035 assert_pll_enabled(dev_priv, pipe);
2036 else {
2037 if (crtc->config.has_pch_encoder) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
2042 }
2043 /* FIXME: assert CPU port conditions for SNB+ */
2044 }
2045
2046 reg = PIPECONF(cpu_transcoder);
2047 val = I915_READ(reg);
2048 if (val & PIPECONF_ENABLE) {
2049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051 return;
2052 }
2053
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
2055 POSTING_READ(reg);
2056 }
2057
2058 /**
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2061 *
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2065 *
2066 * Will wait until the pipe has shut down before returning.
2067 */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
2073 int reg;
2074 u32 val;
2075
2076 /*
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2079 */
2080 assert_planes_disabled(dev_priv, pipe);
2081 assert_cursor_disabled(dev_priv, pipe);
2082 assert_sprites_disabled(dev_priv, pipe);
2083
2084 reg = PIPECONF(cpu_transcoder);
2085 val = I915_READ(reg);
2086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
2089 /*
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2092 */
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099 val &= ~PIPECONF_ENABLE;
2100
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2109 */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane)
2112 {
2113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116 I915_WRITE(reg, I915_READ(reg));
2117 POSTING_READ(reg);
2118 }
2119
2120 /**
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2124 *
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2126 */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
2129 {
2130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137 if (intel_crtc->primary_enabled)
2138 return;
2139
2140 intel_crtc->primary_enabled = true;
2141
2142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2143 crtc->x, crtc->y);
2144
2145 /*
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2149 */
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2158 *
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2160 */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
2163 {
2164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170 if (!intel_crtc->primary_enabled)
2171 return;
2172
2173 intel_crtc->primary_enabled = false;
2174
2175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184 #endif
2185 return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190 int tile_height;
2191
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198 struct drm_framebuffer *fb,
2199 struct intel_engine_cs *pipelined)
2200 {
2201 struct drm_device *dev = fb->dev;
2202 struct drm_i915_private *dev_priv = dev->dev_private;
2203 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204 u32 alignment;
2205 int ret;
2206
2207 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209 switch (obj->tiling_mode) {
2210 case I915_TILING_NONE:
2211 if (INTEL_INFO(dev)->gen >= 9)
2212 alignment = 256 * 1024;
2213 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214 alignment = 128 * 1024;
2215 else if (INTEL_INFO(dev)->gen >= 4)
2216 alignment = 4 * 1024;
2217 else
2218 alignment = 64 * 1024;
2219 break;
2220 case I915_TILING_X:
2221 if (INTEL_INFO(dev)->gen >= 9)
2222 alignment = 256 * 1024;
2223 else {
2224 /* pin() will align the object as required by fence */
2225 alignment = 0;
2226 }
2227 break;
2228 case I915_TILING_Y:
2229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230 return -EINVAL;
2231 default:
2232 BUG();
2233 }
2234
2235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2238 * the VT-d warning.
2239 */
2240 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241 alignment = 256 * 1024;
2242
2243 /*
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2249 */
2250 intel_runtime_pm_get(dev_priv);
2251
2252 dev_priv->mm.interruptible = false;
2253 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254 if (ret)
2255 goto err_interruptible;
2256
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2261 */
2262 ret = i915_gem_object_get_fence(obj);
2263 if (ret)
2264 goto err_unpin;
2265
2266 i915_gem_object_pin_fence(obj);
2267
2268 dev_priv->mm.interruptible = true;
2269 intel_runtime_pm_put(dev_priv);
2270 return 0;
2271
2272 err_unpin:
2273 i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275 dev_priv->mm.interruptible = true;
2276 intel_runtime_pm_put(dev_priv);
2277 return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284 i915_gem_object_unpin_fence(obj);
2285 i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291 unsigned int tiling_mode,
2292 unsigned int cpp,
2293 unsigned int pitch)
2294 {
2295 if (tiling_mode != I915_TILING_NONE) {
2296 unsigned int tile_rows, tiles;
2297
2298 tile_rows = *y / 8;
2299 *y %= 8;
2300
2301 tiles = *x / (512/cpp);
2302 *x %= 512/cpp;
2303
2304 return tile_rows * pitch * 8 + tiles * 4096;
2305 } else {
2306 unsigned int offset;
2307
2308 offset = *y * pitch + *x * cpp;
2309 *y = 0;
2310 *x = (offset & 4095) / cpp;
2311 return offset & -4096;
2312 }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317 switch (format) {
2318 case DISPPLANE_8BPP:
2319 return DRM_FORMAT_C8;
2320 case DISPPLANE_BGRX555:
2321 return DRM_FORMAT_XRGB1555;
2322 case DISPPLANE_BGRX565:
2323 return DRM_FORMAT_RGB565;
2324 default:
2325 case DISPPLANE_BGRX888:
2326 return DRM_FORMAT_XRGB8888;
2327 case DISPPLANE_RGBX888:
2328 return DRM_FORMAT_XBGR8888;
2329 case DISPPLANE_BGRX101010:
2330 return DRM_FORMAT_XRGB2101010;
2331 case DISPPLANE_RGBX101010:
2332 return DRM_FORMAT_XBGR2101010;
2333 }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337 struct intel_plane_config *plane_config)
2338 {
2339 struct drm_device *dev = crtc->base.dev;
2340 struct drm_i915_gem_object *obj = NULL;
2341 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342 u32 base = plane_config->base;
2343
2344 if (plane_config->size == 0)
2345 return false;
2346
2347 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348 plane_config->size);
2349 if (!obj)
2350 return false;
2351
2352 if (plane_config->tiled) {
2353 obj->tiling_mode = I915_TILING_X;
2354 obj->stride = crtc->base.primary->fb->pitches[0];
2355 }
2356
2357 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358 mode_cmd.width = crtc->base.primary->fb->width;
2359 mode_cmd.height = crtc->base.primary->fb->height;
2360 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362 mutex_lock(&dev->struct_mutex);
2363
2364 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365 &mode_cmd, obj)) {
2366 DRM_DEBUG_KMS("intel fb init failed\n");
2367 goto out_unref_obj;
2368 }
2369
2370 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371 mutex_unlock(&dev->struct_mutex);
2372
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374 return true;
2375
2376 out_unref_obj:
2377 drm_gem_object_unreference(&obj->base);
2378 mutex_unlock(&dev->struct_mutex);
2379 return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383 struct intel_plane_config *plane_config)
2384 {
2385 struct drm_device *dev = intel_crtc->base.dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct drm_crtc *c;
2388 struct intel_crtc *i;
2389 struct drm_i915_gem_object *obj;
2390
2391 if (!intel_crtc->base.primary->fb)
2392 return;
2393
2394 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395 return;
2396
2397 kfree(intel_crtc->base.primary->fb);
2398 intel_crtc->base.primary->fb = NULL;
2399
2400 /*
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2403 */
2404 for_each_crtc(dev, c) {
2405 i = to_intel_crtc(c);
2406
2407 if (c == &intel_crtc->base)
2408 continue;
2409
2410 if (!i->active)
2411 continue;
2412
2413 obj = intel_fb_obj(c->primary->fb);
2414 if (obj == NULL)
2415 continue;
2416
2417 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418 if (obj->tiling_mode != I915_TILING_NONE)
2419 dev_priv->preserve_bios_swizzle = true;
2420
2421 drm_framebuffer_reference(c->primary->fb);
2422 intel_crtc->base.primary->fb = c->primary->fb;
2423 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424 break;
2425 }
2426 }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430 struct drm_framebuffer *fb,
2431 int x, int y)
2432 {
2433 struct drm_device *dev = crtc->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436 struct drm_i915_gem_object *obj;
2437 int plane = intel_crtc->plane;
2438 unsigned long linear_offset;
2439 u32 dspcntr;
2440 u32 reg = DSPCNTR(plane);
2441 int pixel_size;
2442
2443 if (!intel_crtc->primary_enabled) {
2444 I915_WRITE(reg, 0);
2445 if (INTEL_INFO(dev)->gen >= 4)
2446 I915_WRITE(DSPSURF(plane), 0);
2447 else
2448 I915_WRITE(DSPADDR(plane), 0);
2449 POSTING_READ(reg);
2450 return;
2451 }
2452
2453 obj = intel_fb_obj(fb);
2454 if (WARN_ON(obj == NULL))
2455 return;
2456
2457 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459 dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461 dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463 if (INTEL_INFO(dev)->gen < 4) {
2464 if (intel_crtc->pipe == PIPE_B)
2465 dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2469 */
2470 I915_WRITE(DSPSIZE(plane),
2471 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472 (intel_crtc->config.pipe_src_w - 1));
2473 I915_WRITE(DSPPOS(plane), 0);
2474 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475 I915_WRITE(PRIMSIZE(plane),
2476 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477 (intel_crtc->config.pipe_src_w - 1));
2478 I915_WRITE(PRIMPOS(plane), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480 }
2481
2482 switch (fb->pixel_format) {
2483 case DRM_FORMAT_C8:
2484 dspcntr |= DISPPLANE_8BPP;
2485 break;
2486 case DRM_FORMAT_XRGB1555:
2487 case DRM_FORMAT_ARGB1555:
2488 dspcntr |= DISPPLANE_BGRX555;
2489 break;
2490 case DRM_FORMAT_RGB565:
2491 dspcntr |= DISPPLANE_BGRX565;
2492 break;
2493 case DRM_FORMAT_XRGB8888:
2494 case DRM_FORMAT_ARGB8888:
2495 dspcntr |= DISPPLANE_BGRX888;
2496 break;
2497 case DRM_FORMAT_XBGR8888:
2498 case DRM_FORMAT_ABGR8888:
2499 dspcntr |= DISPPLANE_RGBX888;
2500 break;
2501 case DRM_FORMAT_XRGB2101010:
2502 case DRM_FORMAT_ARGB2101010:
2503 dspcntr |= DISPPLANE_BGRX101010;
2504 break;
2505 case DRM_FORMAT_XBGR2101010:
2506 case DRM_FORMAT_ABGR2101010:
2507 dspcntr |= DISPPLANE_RGBX101010;
2508 break;
2509 default:
2510 BUG();
2511 }
2512
2513 if (INTEL_INFO(dev)->gen >= 4 &&
2514 obj->tiling_mode != I915_TILING_NONE)
2515 dspcntr |= DISPPLANE_TILED;
2516
2517 if (IS_G4X(dev))
2518 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520 linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522 if (INTEL_INFO(dev)->gen >= 4) {
2523 intel_crtc->dspaddr_offset =
2524 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525 pixel_size,
2526 fb->pitches[0]);
2527 linear_offset -= intel_crtc->dspaddr_offset;
2528 } else {
2529 intel_crtc->dspaddr_offset = linear_offset;
2530 }
2531
2532 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535 x += (intel_crtc->config.pipe_src_w - 1);
2536 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2540 linear_offset +=
2541 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543 }
2544
2545 I915_WRITE(reg, dspcntr);
2546
2547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549 fb->pitches[0]);
2550 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551 if (INTEL_INFO(dev)->gen >= 4) {
2552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556 } else
2557 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558 POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562 struct drm_framebuffer *fb,
2563 int x, int y)
2564 {
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 struct drm_i915_gem_object *obj;
2569 int plane = intel_crtc->plane;
2570 unsigned long linear_offset;
2571 u32 dspcntr;
2572 u32 reg = DSPCNTR(plane);
2573 int pixel_size;
2574
2575 if (!intel_crtc->primary_enabled) {
2576 I915_WRITE(reg, 0);
2577 I915_WRITE(DSPSURF(plane), 0);
2578 POSTING_READ(reg);
2579 return;
2580 }
2581
2582 obj = intel_fb_obj(fb);
2583 if (WARN_ON(obj == NULL))
2584 return;
2585
2586 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588 dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590 dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595 switch (fb->pixel_format) {
2596 case DRM_FORMAT_C8:
2597 dspcntr |= DISPPLANE_8BPP;
2598 break;
2599 case DRM_FORMAT_RGB565:
2600 dspcntr |= DISPPLANE_BGRX565;
2601 break;
2602 case DRM_FORMAT_XRGB8888:
2603 case DRM_FORMAT_ARGB8888:
2604 dspcntr |= DISPPLANE_BGRX888;
2605 break;
2606 case DRM_FORMAT_XBGR8888:
2607 case DRM_FORMAT_ABGR8888:
2608 dspcntr |= DISPPLANE_RGBX888;
2609 break;
2610 case DRM_FORMAT_XRGB2101010:
2611 case DRM_FORMAT_ARGB2101010:
2612 dspcntr |= DISPPLANE_BGRX101010;
2613 break;
2614 case DRM_FORMAT_XBGR2101010:
2615 case DRM_FORMAT_ABGR2101010:
2616 dspcntr |= DISPPLANE_RGBX101010;
2617 break;
2618 default:
2619 BUG();
2620 }
2621
2622 if (obj->tiling_mode != I915_TILING_NONE)
2623 dspcntr |= DISPPLANE_TILED;
2624
2625 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628 linear_offset = y * fb->pitches[0] + x * pixel_size;
2629 intel_crtc->dspaddr_offset =
2630 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631 pixel_size,
2632 fb->pitches[0]);
2633 linear_offset -= intel_crtc->dspaddr_offset;
2634 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638 x += (intel_crtc->config.pipe_src_w - 1);
2639 y += (intel_crtc->config.pipe_src_h - 1);
2640
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2643 linear_offset +=
2644 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646 }
2647 }
2648
2649 I915_WRITE(reg, dspcntr);
2650
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653 fb->pitches[0]);
2654 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655 I915_WRITE(DSPSURF(plane),
2656 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659 } else {
2660 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662 }
2663 POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667 struct drm_framebuffer *fb,
2668 int x, int y)
2669 {
2670 struct drm_device *dev = crtc->dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673 struct intel_framebuffer *intel_fb;
2674 struct drm_i915_gem_object *obj;
2675 int pipe = intel_crtc->pipe;
2676 u32 plane_ctl, stride;
2677
2678 if (!intel_crtc->primary_enabled) {
2679 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe, 0));
2682 return;
2683 }
2684
2685 plane_ctl = PLANE_CTL_ENABLE |
2686 PLANE_CTL_PIPE_GAMMA_ENABLE |
2687 PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689 switch (fb->pixel_format) {
2690 case DRM_FORMAT_RGB565:
2691 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692 break;
2693 case DRM_FORMAT_XRGB8888:
2694 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695 break;
2696 case DRM_FORMAT_XBGR8888:
2697 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699 break;
2700 case DRM_FORMAT_XRGB2101010:
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702 break;
2703 case DRM_FORMAT_XBGR2101010:
2704 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706 break;
2707 default:
2708 BUG();
2709 }
2710
2711 intel_fb = to_intel_framebuffer(fb);
2712 obj = intel_fb->obj;
2713
2714 /*
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2717 */
2718 switch (obj->tiling_mode) {
2719 case I915_TILING_NONE:
2720 stride = fb->pitches[0] >> 6;
2721 break;
2722 case I915_TILING_X:
2723 plane_ctl |= PLANE_CTL_TILED_X;
2724 stride = fb->pitches[0] >> 9;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj),
2738 x, y, fb->width, fb->height,
2739 fb->pitches[0]);
2740
2741 I915_WRITE(PLANE_POS(pipe, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743 I915_WRITE(PLANE_SIZE(pipe, 0),
2744 (intel_crtc->config.pipe_src_h - 1) << 16 |
2745 (intel_crtc->config.pipe_src_w - 1));
2746 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749 POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755 int x, int y, enum mode_set_atomic state)
2756 {
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760 if (dev_priv->display.disable_fbc)
2761 dev_priv->display.disable_fbc(dev);
2762
2763 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765 return 0;
2766 }
2767
2768 void intel_display_handle_reset(struct drm_device *dev)
2769 {
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct drm_crtc *crtc;
2772
2773 /*
2774 * Flips in the rings have been nuked by the reset,
2775 * so complete all pending flips so that user space
2776 * will get its events and not get stuck.
2777 *
2778 * Also update the base address of all primary
2779 * planes to the the last fb to make sure we're
2780 * showing the correct fb after a reset.
2781 *
2782 * Need to make two loops over the crtcs so that we
2783 * don't try to grab a crtc mutex before the
2784 * pending_flip_queue really got woken up.
2785 */
2786
2787 for_each_crtc(dev, crtc) {
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 enum plane plane = intel_crtc->plane;
2790
2791 intel_prepare_page_flip(dev, plane);
2792 intel_finish_page_flip_plane(dev, plane);
2793 }
2794
2795 for_each_crtc(dev, crtc) {
2796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
2798 drm_modeset_lock(&crtc->mutex, NULL);
2799 /*
2800 * FIXME: Once we have proper support for primary planes (and
2801 * disabling them without disabling the entire crtc) allow again
2802 * a NULL crtc->primary->fb.
2803 */
2804 if (intel_crtc->active && crtc->primary->fb)
2805 dev_priv->display.update_primary_plane(crtc,
2806 crtc->primary->fb,
2807 crtc->x,
2808 crtc->y);
2809 drm_modeset_unlock(&crtc->mutex);
2810 }
2811 }
2812
2813 static int
2814 intel_finish_fb(struct drm_framebuffer *old_fb)
2815 {
2816 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2817 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818 bool was_interruptible = dev_priv->mm.interruptible;
2819 int ret;
2820
2821 /* Big Hammer, we also need to ensure that any pending
2822 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823 * current scanout is retired before unpinning the old
2824 * framebuffer.
2825 *
2826 * This should only fail upon a hung GPU, in which case we
2827 * can safely continue.
2828 */
2829 dev_priv->mm.interruptible = false;
2830 ret = i915_gem_object_finish_gpu(obj);
2831 dev_priv->mm.interruptible = was_interruptible;
2832
2833 return ret;
2834 }
2835
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837 {
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 bool pending;
2842
2843 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845 return false;
2846
2847 spin_lock_irq(&dev->event_lock);
2848 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2849 spin_unlock_irq(&dev->event_lock);
2850
2851 return pending;
2852 }
2853
2854 static void intel_update_pipe_size(struct intel_crtc *crtc)
2855 {
2856 struct drm_device *dev = crtc->base.dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858 const struct drm_display_mode *adjusted_mode;
2859
2860 if (!i915.fastboot)
2861 return;
2862
2863 /*
2864 * Update pipe size and adjust fitter if needed: the reason for this is
2865 * that in compute_mode_changes we check the native mode (not the pfit
2866 * mode) to see if we can flip rather than do a full mode set. In the
2867 * fastboot case, we'll flip, but if we don't update the pipesrc and
2868 * pfit state, we'll end up with a big fb scanned out into the wrong
2869 * sized surface.
2870 *
2871 * To fix this properly, we need to hoist the checks up into
2872 * compute_mode_changes (or above), check the actual pfit state and
2873 * whether the platform allows pfit disable with pipe active, and only
2874 * then update the pipesrc and pfit state, even on the flip path.
2875 */
2876
2877 adjusted_mode = &crtc->config.adjusted_mode;
2878
2879 I915_WRITE(PIPESRC(crtc->pipe),
2880 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881 (adjusted_mode->crtc_vdisplay - 1));
2882 if (!crtc->config.pch_pfit.enabled &&
2883 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2885 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888 }
2889 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891 }
2892
2893 static int
2894 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2895 struct drm_framebuffer *fb)
2896 {
2897 struct drm_device *dev = crtc->dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900 enum pipe pipe = intel_crtc->pipe;
2901 struct drm_framebuffer *old_fb = crtc->primary->fb;
2902 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2903 int ret;
2904
2905 if (intel_crtc_has_pending_flip(crtc)) {
2906 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907 return -EBUSY;
2908 }
2909
2910 /* no fb bound */
2911 if (!fb) {
2912 DRM_ERROR("No FB bound\n");
2913 return 0;
2914 }
2915
2916 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2917 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918 plane_name(intel_crtc->plane),
2919 INTEL_INFO(dev)->num_pipes);
2920 return -EINVAL;
2921 }
2922
2923 mutex_lock(&dev->struct_mutex);
2924 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2925 if (ret == 0)
2926 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2927 INTEL_FRONTBUFFER_PRIMARY(pipe));
2928 mutex_unlock(&dev->struct_mutex);
2929 if (ret != 0) {
2930 DRM_ERROR("pin & fence failed\n");
2931 return ret;
2932 }
2933
2934 intel_update_pipe_size(intel_crtc);
2935
2936 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2937
2938 if (intel_crtc->active)
2939 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2940
2941 crtc->primary->fb = fb;
2942 crtc->x = x;
2943 crtc->y = y;
2944
2945 if (old_fb) {
2946 if (intel_crtc->active && old_fb != fb)
2947 intel_wait_for_vblank(dev, intel_crtc->pipe);
2948 mutex_lock(&dev->struct_mutex);
2949 intel_unpin_fb_obj(old_obj);
2950 mutex_unlock(&dev->struct_mutex);
2951 }
2952
2953 mutex_lock(&dev->struct_mutex);
2954 intel_update_fbc(dev);
2955 mutex_unlock(&dev->struct_mutex);
2956
2957 return 0;
2958 }
2959
2960 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2961 {
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 int pipe = intel_crtc->pipe;
2966 u32 reg, temp;
2967
2968 /* enable normal train */
2969 reg = FDI_TX_CTL(pipe);
2970 temp = I915_READ(reg);
2971 if (IS_IVYBRIDGE(dev)) {
2972 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2973 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2974 } else {
2975 temp &= ~FDI_LINK_TRAIN_NONE;
2976 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2977 }
2978 I915_WRITE(reg, temp);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2985 } else {
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_NONE;
2988 }
2989 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2990
2991 /* wait one idle pattern time */
2992 POSTING_READ(reg);
2993 udelay(1000);
2994
2995 /* IVB wants error correction enabled */
2996 if (IS_IVYBRIDGE(dev))
2997 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2998 FDI_FE_ERRC_ENABLE);
2999 }
3000
3001 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3002 {
3003 return crtc->base.enabled && crtc->active &&
3004 crtc->config.has_pch_encoder;
3005 }
3006
3007 static void ivb_modeset_global_resources(struct drm_device *dev)
3008 {
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *pipe_B_crtc =
3011 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3012 struct intel_crtc *pipe_C_crtc =
3013 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3014 uint32_t temp;
3015
3016 /*
3017 * When everything is off disable fdi C so that we could enable fdi B
3018 * with all lanes. Note that we don't care about enabled pipes without
3019 * an enabled pch encoder.
3020 */
3021 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3022 !pipe_has_enabled_pch(pipe_C_crtc)) {
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3025
3026 temp = I915_READ(SOUTH_CHICKEN1);
3027 temp &= ~FDI_BC_BIFURCATION_SELECT;
3028 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029 I915_WRITE(SOUTH_CHICKEN1, temp);
3030 }
3031 }
3032
3033 /* The FDI link training functions for ILK/Ibexpeak. */
3034 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3035 {
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
3040 u32 reg, temp, tries;
3041
3042 /* FDI needs bits from pipe first */
3043 assert_pipe_enabled(dev_priv, pipe);
3044
3045 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046 for train result */
3047 reg = FDI_RX_IMR(pipe);
3048 temp = I915_READ(reg);
3049 temp &= ~FDI_RX_SYMBOL_LOCK;
3050 temp &= ~FDI_RX_BIT_LOCK;
3051 I915_WRITE(reg, temp);
3052 I915_READ(reg);
3053 udelay(150);
3054
3055 /* enable CPU FDI TX and PCH FDI RX */
3056 reg = FDI_TX_CTL(pipe);
3057 temp = I915_READ(reg);
3058 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3059 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3060 temp &= ~FDI_LINK_TRAIN_NONE;
3061 temp |= FDI_LINK_TRAIN_PATTERN_1;
3062 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3063
3064 reg = FDI_RX_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~FDI_LINK_TRAIN_NONE;
3067 temp |= FDI_LINK_TRAIN_PATTERN_1;
3068 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3069
3070 POSTING_READ(reg);
3071 udelay(150);
3072
3073 /* Ironlake workaround, enable clock pointer after FDI enable*/
3074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3075 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3076 FDI_RX_PHASE_SYNC_POINTER_EN);
3077
3078 reg = FDI_RX_IIR(pipe);
3079 for (tries = 0; tries < 5; tries++) {
3080 temp = I915_READ(reg);
3081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082
3083 if ((temp & FDI_RX_BIT_LOCK)) {
3084 DRM_DEBUG_KMS("FDI train 1 done.\n");
3085 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3086 break;
3087 }
3088 }
3089 if (tries == 5)
3090 DRM_ERROR("FDI train 1 fail!\n");
3091
3092 /* Train 2 */
3093 reg = FDI_TX_CTL(pipe);
3094 temp = I915_READ(reg);
3095 temp &= ~FDI_LINK_TRAIN_NONE;
3096 temp |= FDI_LINK_TRAIN_PATTERN_2;
3097 I915_WRITE(reg, temp);
3098
3099 reg = FDI_RX_CTL(pipe);
3100 temp = I915_READ(reg);
3101 temp &= ~FDI_LINK_TRAIN_NONE;
3102 temp |= FDI_LINK_TRAIN_PATTERN_2;
3103 I915_WRITE(reg, temp);
3104
3105 POSTING_READ(reg);
3106 udelay(150);
3107
3108 reg = FDI_RX_IIR(pipe);
3109 for (tries = 0; tries < 5; tries++) {
3110 temp = I915_READ(reg);
3111 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112
3113 if (temp & FDI_RX_SYMBOL_LOCK) {
3114 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3115 DRM_DEBUG_KMS("FDI train 2 done.\n");
3116 break;
3117 }
3118 }
3119 if (tries == 5)
3120 DRM_ERROR("FDI train 2 fail!\n");
3121
3122 DRM_DEBUG_KMS("FDI train done\n");
3123
3124 }
3125
3126 static const int snb_b_fdi_train_param[] = {
3127 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3128 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3129 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3130 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3131 };
3132
3133 /* The FDI link training functions for SNB/Cougarpoint. */
3134 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3135 {
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139 int pipe = intel_crtc->pipe;
3140 u32 reg, temp, i, retry;
3141
3142 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143 for train result */
3144 reg = FDI_RX_IMR(pipe);
3145 temp = I915_READ(reg);
3146 temp &= ~FDI_RX_SYMBOL_LOCK;
3147 temp &= ~FDI_RX_BIT_LOCK;
3148 I915_WRITE(reg, temp);
3149
3150 POSTING_READ(reg);
3151 udelay(150);
3152
3153 /* enable CPU FDI TX and PCH FDI RX */
3154 reg = FDI_TX_CTL(pipe);
3155 temp = I915_READ(reg);
3156 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3157 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3158 temp &= ~FDI_LINK_TRAIN_NONE;
3159 temp |= FDI_LINK_TRAIN_PATTERN_1;
3160 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161 /* SNB-B */
3162 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3163 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3164
3165 I915_WRITE(FDI_RX_MISC(pipe),
3166 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3167
3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 if (HAS_PCH_CPT(dev)) {
3171 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3172 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3173 } else {
3174 temp &= ~FDI_LINK_TRAIN_NONE;
3175 temp |= FDI_LINK_TRAIN_PATTERN_1;
3176 }
3177 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3178
3179 POSTING_READ(reg);
3180 udelay(150);
3181
3182 for (i = 0; i < 4; i++) {
3183 reg = FDI_TX_CTL(pipe);
3184 temp = I915_READ(reg);
3185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3186 temp |= snb_b_fdi_train_param[i];
3187 I915_WRITE(reg, temp);
3188
3189 POSTING_READ(reg);
3190 udelay(500);
3191
3192 for (retry = 0; retry < 5; retry++) {
3193 reg = FDI_RX_IIR(pipe);
3194 temp = I915_READ(reg);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196 if (temp & FDI_RX_BIT_LOCK) {
3197 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3198 DRM_DEBUG_KMS("FDI train 1 done.\n");
3199 break;
3200 }
3201 udelay(50);
3202 }
3203 if (retry < 5)
3204 break;
3205 }
3206 if (i == 4)
3207 DRM_ERROR("FDI train 1 fail!\n");
3208
3209 /* Train 2 */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~FDI_LINK_TRAIN_NONE;
3213 temp |= FDI_LINK_TRAIN_PATTERN_2;
3214 if (IS_GEN6(dev)) {
3215 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216 /* SNB-B */
3217 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218 }
3219 I915_WRITE(reg, temp);
3220
3221 reg = FDI_RX_CTL(pipe);
3222 temp = I915_READ(reg);
3223 if (HAS_PCH_CPT(dev)) {
3224 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3225 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3226 } else {
3227 temp &= ~FDI_LINK_TRAIN_NONE;
3228 temp |= FDI_LINK_TRAIN_PATTERN_2;
3229 }
3230 I915_WRITE(reg, temp);
3231
3232 POSTING_READ(reg);
3233 udelay(150);
3234
3235 for (i = 0; i < 4; i++) {
3236 reg = FDI_TX_CTL(pipe);
3237 temp = I915_READ(reg);
3238 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3239 temp |= snb_b_fdi_train_param[i];
3240 I915_WRITE(reg, temp);
3241
3242 POSTING_READ(reg);
3243 udelay(500);
3244
3245 for (retry = 0; retry < 5; retry++) {
3246 reg = FDI_RX_IIR(pipe);
3247 temp = I915_READ(reg);
3248 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3249 if (temp & FDI_RX_SYMBOL_LOCK) {
3250 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3251 DRM_DEBUG_KMS("FDI train 2 done.\n");
3252 break;
3253 }
3254 udelay(50);
3255 }
3256 if (retry < 5)
3257 break;
3258 }
3259 if (i == 4)
3260 DRM_ERROR("FDI train 2 fail!\n");
3261
3262 DRM_DEBUG_KMS("FDI train done.\n");
3263 }
3264
3265 /* Manual link training for Ivy Bridge A0 parts */
3266 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3267 {
3268 struct drm_device *dev = crtc->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271 int pipe = intel_crtc->pipe;
3272 u32 reg, temp, i, j;
3273
3274 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275 for train result */
3276 reg = FDI_RX_IMR(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~FDI_RX_SYMBOL_LOCK;
3279 temp &= ~FDI_RX_BIT_LOCK;
3280 I915_WRITE(reg, temp);
3281
3282 POSTING_READ(reg);
3283 udelay(150);
3284
3285 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286 I915_READ(FDI_RX_IIR(pipe)));
3287
3288 /* Try each vswing and preemphasis setting twice before moving on */
3289 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3290 /* disable first in case we need to retry */
3291 reg = FDI_TX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3294 temp &= ~FDI_TX_ENABLE;
3295 I915_WRITE(reg, temp);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp &= ~FDI_LINK_TRAIN_AUTO;
3300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3301 temp &= ~FDI_RX_ENABLE;
3302 I915_WRITE(reg, temp);
3303
3304 /* enable CPU FDI TX and PCH FDI RX */
3305 reg = FDI_TX_CTL(pipe);
3306 temp = I915_READ(reg);
3307 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3308 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3309 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311 temp |= snb_b_fdi_train_param[j/2];
3312 temp |= FDI_COMPOSITE_SYNC;
3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3321 temp |= FDI_COMPOSITE_SYNC;
3322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3323
3324 POSTING_READ(reg);
3325 udelay(1); /* should be 0.5us */
3326
3327 for (i = 0; i < 4; i++) {
3328 reg = FDI_RX_IIR(pipe);
3329 temp = I915_READ(reg);
3330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332 if (temp & FDI_RX_BIT_LOCK ||
3333 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3334 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3335 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3336 i);
3337 break;
3338 }
3339 udelay(1); /* should be 0.5us */
3340 }
3341 if (i == 4) {
3342 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3343 continue;
3344 }
3345
3346 /* Train 2 */
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3351 I915_WRITE(reg, temp);
3352
3353 reg = FDI_RX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3357 I915_WRITE(reg, temp);
3358
3359 POSTING_READ(reg);
3360 udelay(2); /* should be 1.5us */
3361
3362 for (i = 0; i < 4; i++) {
3363 reg = FDI_RX_IIR(pipe);
3364 temp = I915_READ(reg);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366
3367 if (temp & FDI_RX_SYMBOL_LOCK ||
3368 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3369 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3370 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3371 i);
3372 goto train_done;
3373 }
3374 udelay(2); /* should be 1.5us */
3375 }
3376 if (i == 4)
3377 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3378 }
3379
3380 train_done:
3381 DRM_DEBUG_KMS("FDI train done.\n");
3382 }
3383
3384 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3385 {
3386 struct drm_device *dev = intel_crtc->base.dev;
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3388 int pipe = intel_crtc->pipe;
3389 u32 reg, temp;
3390
3391
3392 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3393 reg = FDI_RX_CTL(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3396 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3397 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3398 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3399
3400 POSTING_READ(reg);
3401 udelay(200);
3402
3403 /* Switch from Rawclk to PCDclk */
3404 temp = I915_READ(reg);
3405 I915_WRITE(reg, temp | FDI_PCDCLK);
3406
3407 POSTING_READ(reg);
3408 udelay(200);
3409
3410 /* Enable CPU FDI TX PLL, always on for Ironlake */
3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
3413 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3414 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3415
3416 POSTING_READ(reg);
3417 udelay(100);
3418 }
3419 }
3420
3421 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3422 {
3423 struct drm_device *dev = intel_crtc->base.dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 int pipe = intel_crtc->pipe;
3426 u32 reg, temp;
3427
3428 /* Switch from PCDclk to Rawclk */
3429 reg = FDI_RX_CTL(pipe);
3430 temp = I915_READ(reg);
3431 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3432
3433 /* Disable CPU FDI TX PLL */
3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
3436 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3437
3438 POSTING_READ(reg);
3439 udelay(100);
3440
3441 reg = FDI_RX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3444
3445 /* Wait for the clocks to turn off. */
3446 POSTING_READ(reg);
3447 udelay(100);
3448 }
3449
3450 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3451 {
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455 int pipe = intel_crtc->pipe;
3456 u32 reg, temp;
3457
3458 /* disable CPU FDI tx and PCH FDI rx */
3459 reg = FDI_TX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3462 POSTING_READ(reg);
3463
3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~(0x7 << 16);
3467 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3468 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3469
3470 POSTING_READ(reg);
3471 udelay(100);
3472
3473 /* Ironlake workaround, disable clock pointer after downing FDI */
3474 if (HAS_PCH_IBX(dev))
3475 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3476
3477 /* still set train pattern 1 */
3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_1;
3482 I915_WRITE(reg, temp);
3483
3484 reg = FDI_RX_CTL(pipe);
3485 temp = I915_READ(reg);
3486 if (HAS_PCH_CPT(dev)) {
3487 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3488 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3489 } else {
3490 temp &= ~FDI_LINK_TRAIN_NONE;
3491 temp |= FDI_LINK_TRAIN_PATTERN_1;
3492 }
3493 /* BPC in FDI rx is consistent with that in PIPECONF */
3494 temp &= ~(0x07 << 16);
3495 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3496 I915_WRITE(reg, temp);
3497
3498 POSTING_READ(reg);
3499 udelay(100);
3500 }
3501
3502 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3503 {
3504 struct intel_crtc *crtc;
3505
3506 /* Note that we don't need to be called with mode_config.lock here
3507 * as our list of CRTC objects is static for the lifetime of the
3508 * device and so cannot disappear as we iterate. Similarly, we can
3509 * happily treat the predicates as racy, atomic checks as userspace
3510 * cannot claim and pin a new fb without at least acquring the
3511 * struct_mutex and so serialising with us.
3512 */
3513 for_each_intel_crtc(dev, crtc) {
3514 if (atomic_read(&crtc->unpin_work_count) == 0)
3515 continue;
3516
3517 if (crtc->unpin_work)
3518 intel_wait_for_vblank(dev, crtc->pipe);
3519
3520 return true;
3521 }
3522
3523 return false;
3524 }
3525
3526 static void page_flip_completed(struct intel_crtc *intel_crtc)
3527 {
3528 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3529 struct intel_unpin_work *work = intel_crtc->unpin_work;
3530
3531 /* ensure that the unpin work is consistent wrt ->pending. */
3532 smp_rmb();
3533 intel_crtc->unpin_work = NULL;
3534
3535 if (work->event)
3536 drm_send_vblank_event(intel_crtc->base.dev,
3537 intel_crtc->pipe,
3538 work->event);
3539
3540 drm_crtc_vblank_put(&intel_crtc->base);
3541
3542 wake_up_all(&dev_priv->pending_flip_queue);
3543 queue_work(dev_priv->wq, &work->work);
3544
3545 trace_i915_flip_complete(intel_crtc->plane,
3546 work->pending_flip_obj);
3547 }
3548
3549 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553
3554 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3555 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3556 !intel_crtc_has_pending_flip(crtc),
3557 60*HZ) == 0)) {
3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559
3560 spin_lock_irq(&dev->event_lock);
3561 if (intel_crtc->unpin_work) {
3562 WARN_ONCE(1, "Removing stuck page flip\n");
3563 page_flip_completed(intel_crtc);
3564 }
3565 spin_unlock_irq(&dev->event_lock);
3566 }
3567
3568 if (crtc->primary->fb) {
3569 mutex_lock(&dev->struct_mutex);
3570 intel_finish_fb(crtc->primary->fb);
3571 mutex_unlock(&dev->struct_mutex);
3572 }
3573 }
3574
3575 /* Program iCLKIP clock to the desired frequency */
3576 static void lpt_program_iclkip(struct drm_crtc *crtc)
3577 {
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3581 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3582 u32 temp;
3583
3584 mutex_lock(&dev_priv->dpio_lock);
3585
3586 /* It is necessary to ungate the pixclk gate prior to programming
3587 * the divisors, and gate it back when it is done.
3588 */
3589 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3590
3591 /* Disable SSCCTL */
3592 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3593 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3594 SBI_SSCCTL_DISABLE,
3595 SBI_ICLK);
3596
3597 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3598 if (clock == 20000) {
3599 auxdiv = 1;
3600 divsel = 0x41;
3601 phaseinc = 0x20;
3602 } else {
3603 /* The iCLK virtual clock root frequency is in MHz,
3604 * but the adjusted_mode->crtc_clock in in KHz. To get the
3605 * divisors, it is necessary to divide one by another, so we
3606 * convert the virtual clock precision to KHz here for higher
3607 * precision.
3608 */
3609 u32 iclk_virtual_root_freq = 172800 * 1000;
3610 u32 iclk_pi_range = 64;
3611 u32 desired_divisor, msb_divisor_value, pi_value;
3612
3613 desired_divisor = (iclk_virtual_root_freq / clock);
3614 msb_divisor_value = desired_divisor / iclk_pi_range;
3615 pi_value = desired_divisor % iclk_pi_range;
3616
3617 auxdiv = 0;
3618 divsel = msb_divisor_value - 2;
3619 phaseinc = pi_value;
3620 }
3621
3622 /* This should not happen with any sane values */
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3624 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3625 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3626 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3627
3628 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3629 clock,
3630 auxdiv,
3631 divsel,
3632 phasedir,
3633 phaseinc);
3634
3635 /* Program SSCDIVINTPHASE6 */
3636 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3637 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3638 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3639 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3640 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3641 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3642 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3643 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3644
3645 /* Program SSCAUXDIV */
3646 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3647 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3649 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3650
3651 /* Enable modulator and associated divider */
3652 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3653 temp &= ~SBI_SSCCTL_DISABLE;
3654 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3655
3656 /* Wait for initialization time */
3657 udelay(24);
3658
3659 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3660
3661 mutex_unlock(&dev_priv->dpio_lock);
3662 }
3663
3664 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3665 enum pipe pch_transcoder)
3666 {
3667 struct drm_device *dev = crtc->base.dev;
3668 struct drm_i915_private *dev_priv = dev->dev_private;
3669 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3670
3671 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3672 I915_READ(HTOTAL(cpu_transcoder)));
3673 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3674 I915_READ(HBLANK(cpu_transcoder)));
3675 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3676 I915_READ(HSYNC(cpu_transcoder)));
3677
3678 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3679 I915_READ(VTOTAL(cpu_transcoder)));
3680 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3681 I915_READ(VBLANK(cpu_transcoder)));
3682 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3683 I915_READ(VSYNC(cpu_transcoder)));
3684 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3685 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3686 }
3687
3688 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3689 {
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 uint32_t temp;
3692
3693 temp = I915_READ(SOUTH_CHICKEN1);
3694 if (temp & FDI_BC_BIFURCATION_SELECT)
3695 return;
3696
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3698 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3699
3700 temp |= FDI_BC_BIFURCATION_SELECT;
3701 DRM_DEBUG_KMS("enabling fdi C rx\n");
3702 I915_WRITE(SOUTH_CHICKEN1, temp);
3703 POSTING_READ(SOUTH_CHICKEN1);
3704 }
3705
3706 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3707 {
3708 struct drm_device *dev = intel_crtc->base.dev;
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710
3711 switch (intel_crtc->pipe) {
3712 case PIPE_A:
3713 break;
3714 case PIPE_B:
3715 if (intel_crtc->config.fdi_lanes > 2)
3716 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717 else
3718 cpt_enable_fdi_bc_bifurcation(dev);
3719
3720 break;
3721 case PIPE_C:
3722 cpt_enable_fdi_bc_bifurcation(dev);
3723
3724 break;
3725 default:
3726 BUG();
3727 }
3728 }
3729
3730 /*
3731 * Enable PCH resources required for PCH ports:
3732 * - PCH PLLs
3733 * - FDI training & RX/TX
3734 * - update transcoder timings
3735 * - DP transcoding bits
3736 * - transcoder
3737 */
3738 static void ironlake_pch_enable(struct drm_crtc *crtc)
3739 {
3740 struct drm_device *dev = crtc->dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743 int pipe = intel_crtc->pipe;
3744 u32 reg, temp;
3745
3746 assert_pch_transcoder_disabled(dev_priv, pipe);
3747
3748 if (IS_IVYBRIDGE(dev))
3749 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3750
3751 /* Write the TU size bits before fdi link training, so that error
3752 * detection works. */
3753 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3754 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3755
3756 /* For PCH output, training FDI link */
3757 dev_priv->display.fdi_link_train(crtc);
3758
3759 /* We need to program the right clock selection before writing the pixel
3760 * mutliplier into the DPLL. */
3761 if (HAS_PCH_CPT(dev)) {
3762 u32 sel;
3763
3764 temp = I915_READ(PCH_DPLL_SEL);
3765 temp |= TRANS_DPLL_ENABLE(pipe);
3766 sel = TRANS_DPLLB_SEL(pipe);
3767 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3768 temp |= sel;
3769 else
3770 temp &= ~sel;
3771 I915_WRITE(PCH_DPLL_SEL, temp);
3772 }
3773
3774 /* XXX: pch pll's can be enabled any time before we enable the PCH
3775 * transcoder, and we actually should do this to not upset any PCH
3776 * transcoder that already use the clock when we share it.
3777 *
3778 * Note that enable_shared_dpll tries to do the right thing, but
3779 * get_shared_dpll unconditionally resets the pll - we need that to have
3780 * the right LVDS enable sequence. */
3781 intel_enable_shared_dpll(intel_crtc);
3782
3783 /* set transcoder timing, panel must allow it */
3784 assert_panel_unlocked(dev_priv, pipe);
3785 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3786
3787 intel_fdi_normal_train(crtc);
3788
3789 /* For PCH DP, enable TRANS_DP_CTL */
3790 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3791 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3792 reg = TRANS_DP_CTL(pipe);
3793 temp = I915_READ(reg);
3794 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3795 TRANS_DP_SYNC_MASK |
3796 TRANS_DP_BPC_MASK);
3797 temp |= (TRANS_DP_OUTPUT_ENABLE |
3798 TRANS_DP_ENH_FRAMING);
3799 temp |= bpc << 9; /* same format but at 11:9 */
3800
3801 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3802 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3803 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3804 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3805
3806 switch (intel_trans_dp_port_sel(crtc)) {
3807 case PCH_DP_B:
3808 temp |= TRANS_DP_PORT_SEL_B;
3809 break;
3810 case PCH_DP_C:
3811 temp |= TRANS_DP_PORT_SEL_C;
3812 break;
3813 case PCH_DP_D:
3814 temp |= TRANS_DP_PORT_SEL_D;
3815 break;
3816 default:
3817 BUG();
3818 }
3819
3820 I915_WRITE(reg, temp);
3821 }
3822
3823 ironlake_enable_pch_transcoder(dev_priv, pipe);
3824 }
3825
3826 static void lpt_pch_enable(struct drm_crtc *crtc)
3827 {
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3832
3833 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3834
3835 lpt_program_iclkip(crtc);
3836
3837 /* Set transcoder timing. */
3838 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3839
3840 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3841 }
3842
3843 void intel_put_shared_dpll(struct intel_crtc *crtc)
3844 {
3845 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3846
3847 if (pll == NULL)
3848 return;
3849
3850 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3851 WARN(1, "bad %s crtc mask\n", pll->name);
3852 return;
3853 }
3854
3855 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3856 if (pll->config.crtc_mask == 0) {
3857 WARN_ON(pll->on);
3858 WARN_ON(pll->active);
3859 }
3860
3861 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3862 }
3863
3864 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3865 {
3866 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3867 struct intel_shared_dpll *pll;
3868 enum intel_dpll_id i;
3869
3870 if (HAS_PCH_IBX(dev_priv->dev)) {
3871 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3872 i = (enum intel_dpll_id) crtc->pipe;
3873 pll = &dev_priv->shared_dplls[i];
3874
3875 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3876 crtc->base.base.id, pll->name);
3877
3878 WARN_ON(pll->new_config->crtc_mask);
3879
3880 goto found;
3881 }
3882
3883 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3884 pll = &dev_priv->shared_dplls[i];
3885
3886 /* Only want to check enabled timings first */
3887 if (pll->new_config->crtc_mask == 0)
3888 continue;
3889
3890 if (memcmp(&crtc->new_config->dpll_hw_state,
3891 &pll->new_config->hw_state,
3892 sizeof(pll->new_config->hw_state)) == 0) {
3893 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3894 crtc->base.base.id, pll->name,
3895 pll->new_config->crtc_mask,
3896 pll->active);
3897 goto found;
3898 }
3899 }
3900
3901 /* Ok no matching timings, maybe there's a free one? */
3902 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3903 pll = &dev_priv->shared_dplls[i];
3904 if (pll->new_config->crtc_mask == 0) {
3905 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3906 crtc->base.base.id, pll->name);
3907 goto found;
3908 }
3909 }
3910
3911 return NULL;
3912
3913 found:
3914 if (pll->new_config->crtc_mask == 0)
3915 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3916
3917 crtc->new_config->shared_dpll = i;
3918 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3919 pipe_name(crtc->pipe));
3920
3921 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3922
3923 return pll;
3924 }
3925
3926 /**
3927 * intel_shared_dpll_start_config - start a new PLL staged config
3928 * @dev_priv: DRM device
3929 * @clear_pipes: mask of pipes that will have their PLLs freed
3930 *
3931 * Starts a new PLL staged config, copying the current config but
3932 * releasing the references of pipes specified in clear_pipes.
3933 */
3934 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3935 unsigned clear_pipes)
3936 {
3937 struct intel_shared_dpll *pll;
3938 enum intel_dpll_id i;
3939
3940 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3941 pll = &dev_priv->shared_dplls[i];
3942
3943 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3944 GFP_KERNEL);
3945 if (!pll->new_config)
3946 goto cleanup;
3947
3948 pll->new_config->crtc_mask &= ~clear_pipes;
3949 }
3950
3951 return 0;
3952
3953 cleanup:
3954 while (--i >= 0) {
3955 pll = &dev_priv->shared_dplls[i];
3956 kfree(pll->new_config);
3957 pll->new_config = NULL;
3958 }
3959
3960 return -ENOMEM;
3961 }
3962
3963 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3964 {
3965 struct intel_shared_dpll *pll;
3966 enum intel_dpll_id i;
3967
3968 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3969 pll = &dev_priv->shared_dplls[i];
3970
3971 WARN_ON(pll->new_config == &pll->config);
3972
3973 pll->config = *pll->new_config;
3974 kfree(pll->new_config);
3975 pll->new_config = NULL;
3976 }
3977 }
3978
3979 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3980 {
3981 struct intel_shared_dpll *pll;
3982 enum intel_dpll_id i;
3983
3984 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3985 pll = &dev_priv->shared_dplls[i];
3986
3987 WARN_ON(pll->new_config == &pll->config);
3988
3989 kfree(pll->new_config);
3990 pll->new_config = NULL;
3991 }
3992 }
3993
3994 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3995 {
3996 struct drm_i915_private *dev_priv = dev->dev_private;
3997 int dslreg = PIPEDSL(pipe);
3998 u32 temp;
3999
4000 temp = I915_READ(dslreg);
4001 udelay(500);
4002 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4003 if (wait_for(I915_READ(dslreg) != temp, 5))
4004 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4005 }
4006 }
4007
4008 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4009 {
4010 struct drm_device *dev = crtc->base.dev;
4011 struct drm_i915_private *dev_priv = dev->dev_private;
4012 int pipe = crtc->pipe;
4013
4014 if (crtc->config.pch_pfit.enabled) {
4015 /* Force use of hard-coded filter coefficients
4016 * as some pre-programmed values are broken,
4017 * e.g. x201.
4018 */
4019 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4020 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4021 PF_PIPE_SEL_IVB(pipe));
4022 else
4023 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4024 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4025 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4026 }
4027 }
4028
4029 static void intel_enable_planes(struct drm_crtc *crtc)
4030 {
4031 struct drm_device *dev = crtc->dev;
4032 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4033 struct drm_plane *plane;
4034 struct intel_plane *intel_plane;
4035
4036 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4037 intel_plane = to_intel_plane(plane);
4038 if (intel_plane->pipe == pipe)
4039 intel_plane_restore(&intel_plane->base);
4040 }
4041 }
4042
4043 static void intel_disable_planes(struct drm_crtc *crtc)
4044 {
4045 struct drm_device *dev = crtc->dev;
4046 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4047 struct drm_plane *plane;
4048 struct intel_plane *intel_plane;
4049
4050 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4051 intel_plane = to_intel_plane(plane);
4052 if (intel_plane->pipe == pipe)
4053 intel_plane_disable(&intel_plane->base);
4054 }
4055 }
4056
4057 void hsw_enable_ips(struct intel_crtc *crtc)
4058 {
4059 struct drm_device *dev = crtc->base.dev;
4060 struct drm_i915_private *dev_priv = dev->dev_private;
4061
4062 if (!crtc->config.ips_enabled)
4063 return;
4064
4065 /* We can only enable IPS after we enable a plane and wait for a vblank */
4066 intel_wait_for_vblank(dev, crtc->pipe);
4067
4068 assert_plane_enabled(dev_priv, crtc->plane);
4069 if (IS_BROADWELL(dev)) {
4070 mutex_lock(&dev_priv->rps.hw_lock);
4071 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4072 mutex_unlock(&dev_priv->rps.hw_lock);
4073 /* Quoting Art Runyan: "its not safe to expect any particular
4074 * value in IPS_CTL bit 31 after enabling IPS through the
4075 * mailbox." Moreover, the mailbox may return a bogus state,
4076 * so we need to just enable it and continue on.
4077 */
4078 } else {
4079 I915_WRITE(IPS_CTL, IPS_ENABLE);
4080 /* The bit only becomes 1 in the next vblank, so this wait here
4081 * is essentially intel_wait_for_vblank. If we don't have this
4082 * and don't wait for vblanks until the end of crtc_enable, then
4083 * the HW state readout code will complain that the expected
4084 * IPS_CTL value is not the one we read. */
4085 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4086 DRM_ERROR("Timed out waiting for IPS enable\n");
4087 }
4088 }
4089
4090 void hsw_disable_ips(struct intel_crtc *crtc)
4091 {
4092 struct drm_device *dev = crtc->base.dev;
4093 struct drm_i915_private *dev_priv = dev->dev_private;
4094
4095 if (!crtc->config.ips_enabled)
4096 return;
4097
4098 assert_plane_enabled(dev_priv, crtc->plane);
4099 if (IS_BROADWELL(dev)) {
4100 mutex_lock(&dev_priv->rps.hw_lock);
4101 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4102 mutex_unlock(&dev_priv->rps.hw_lock);
4103 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4104 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4105 DRM_ERROR("Timed out waiting for IPS disable\n");
4106 } else {
4107 I915_WRITE(IPS_CTL, 0);
4108 POSTING_READ(IPS_CTL);
4109 }
4110
4111 /* We need to wait for a vblank before we can disable the plane. */
4112 intel_wait_for_vblank(dev, crtc->pipe);
4113 }
4114
4115 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4116 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4117 {
4118 struct drm_device *dev = crtc->dev;
4119 struct drm_i915_private *dev_priv = dev->dev_private;
4120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4121 enum pipe pipe = intel_crtc->pipe;
4122 int palreg = PALETTE(pipe);
4123 int i;
4124 bool reenable_ips = false;
4125
4126 /* The clocks have to be on to load the palette. */
4127 if (!crtc->enabled || !intel_crtc->active)
4128 return;
4129
4130 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4131 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4132 assert_dsi_pll_enabled(dev_priv);
4133 else
4134 assert_pll_enabled(dev_priv, pipe);
4135 }
4136
4137 /* use legacy palette for Ironlake */
4138 if (!HAS_GMCH_DISPLAY(dev))
4139 palreg = LGC_PALETTE(pipe);
4140
4141 /* Workaround : Do not read or write the pipe palette/gamma data while
4142 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4143 */
4144 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4145 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4146 GAMMA_MODE_MODE_SPLIT)) {
4147 hsw_disable_ips(intel_crtc);
4148 reenable_ips = true;
4149 }
4150
4151 for (i = 0; i < 256; i++) {
4152 I915_WRITE(palreg + 4 * i,
4153 (intel_crtc->lut_r[i] << 16) |
4154 (intel_crtc->lut_g[i] << 8) |
4155 intel_crtc->lut_b[i]);
4156 }
4157
4158 if (reenable_ips)
4159 hsw_enable_ips(intel_crtc);
4160 }
4161
4162 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4163 {
4164 if (!enable && intel_crtc->overlay) {
4165 struct drm_device *dev = intel_crtc->base.dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167
4168 mutex_lock(&dev->struct_mutex);
4169 dev_priv->mm.interruptible = false;
4170 (void) intel_overlay_switch_off(intel_crtc->overlay);
4171 dev_priv->mm.interruptible = true;
4172 mutex_unlock(&dev->struct_mutex);
4173 }
4174
4175 /* Let userspace switch the overlay on again. In most cases userspace
4176 * has to recompute where to put it anyway.
4177 */
4178 }
4179
4180 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4181 {
4182 struct drm_device *dev = crtc->dev;
4183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184 int pipe = intel_crtc->pipe;
4185
4186 intel_enable_primary_hw_plane(crtc->primary, crtc);
4187 intel_enable_planes(crtc);
4188 intel_crtc_update_cursor(crtc, true);
4189 intel_crtc_dpms_overlay(intel_crtc, true);
4190
4191 hsw_enable_ips(intel_crtc);
4192
4193 mutex_lock(&dev->struct_mutex);
4194 intel_update_fbc(dev);
4195 mutex_unlock(&dev->struct_mutex);
4196
4197 /*
4198 * FIXME: Once we grow proper nuclear flip support out of this we need
4199 * to compute the mask of flip planes precisely. For the time being
4200 * consider this a flip from a NULL plane.
4201 */
4202 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4203 }
4204
4205 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4206 {
4207 struct drm_device *dev = crtc->dev;
4208 struct drm_i915_private *dev_priv = dev->dev_private;
4209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4210 int pipe = intel_crtc->pipe;
4211 int plane = intel_crtc->plane;
4212
4213 intel_crtc_wait_for_pending_flips(crtc);
4214
4215 if (dev_priv->fbc.plane == plane)
4216 intel_disable_fbc(dev);
4217
4218 hsw_disable_ips(intel_crtc);
4219
4220 intel_crtc_dpms_overlay(intel_crtc, false);
4221 intel_crtc_update_cursor(crtc, false);
4222 intel_disable_planes(crtc);
4223 intel_disable_primary_hw_plane(crtc->primary, crtc);
4224
4225 /*
4226 * FIXME: Once we grow proper nuclear flip support out of this we need
4227 * to compute the mask of flip planes precisely. For the time being
4228 * consider this a flip to a NULL plane.
4229 */
4230 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4231 }
4232
4233 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4234 {
4235 struct drm_device *dev = crtc->dev;
4236 struct drm_i915_private *dev_priv = dev->dev_private;
4237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4238 struct intel_encoder *encoder;
4239 int pipe = intel_crtc->pipe;
4240
4241 WARN_ON(!crtc->enabled);
4242
4243 if (intel_crtc->active)
4244 return;
4245
4246 if (intel_crtc->config.has_pch_encoder)
4247 intel_prepare_shared_dpll(intel_crtc);
4248
4249 if (intel_crtc->config.has_dp_encoder)
4250 intel_dp_set_m_n(intel_crtc);
4251
4252 intel_set_pipe_timings(intel_crtc);
4253
4254 if (intel_crtc->config.has_pch_encoder) {
4255 intel_cpu_transcoder_set_m_n(intel_crtc,
4256 &intel_crtc->config.fdi_m_n, NULL);
4257 }
4258
4259 ironlake_set_pipeconf(crtc);
4260
4261 intel_crtc->active = true;
4262
4263 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4264 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4265
4266 for_each_encoder_on_crtc(dev, crtc, encoder)
4267 if (encoder->pre_enable)
4268 encoder->pre_enable(encoder);
4269
4270 if (intel_crtc->config.has_pch_encoder) {
4271 /* Note: FDI PLL enabling _must_ be done before we enable the
4272 * cpu pipes, hence this is separate from all the other fdi/pch
4273 * enabling. */
4274 ironlake_fdi_pll_enable(intel_crtc);
4275 } else {
4276 assert_fdi_tx_disabled(dev_priv, pipe);
4277 assert_fdi_rx_disabled(dev_priv, pipe);
4278 }
4279
4280 ironlake_pfit_enable(intel_crtc);
4281
4282 /*
4283 * On ILK+ LUT must be loaded before the pipe is running but with
4284 * clocks enabled
4285 */
4286 intel_crtc_load_lut(crtc);
4287
4288 intel_update_watermarks(crtc);
4289 intel_enable_pipe(intel_crtc);
4290
4291 if (intel_crtc->config.has_pch_encoder)
4292 ironlake_pch_enable(crtc);
4293
4294 for_each_encoder_on_crtc(dev, crtc, encoder)
4295 encoder->enable(encoder);
4296
4297 if (HAS_PCH_CPT(dev))
4298 cpt_verify_modeset(dev, intel_crtc->pipe);
4299
4300 assert_vblank_disabled(crtc);
4301 drm_crtc_vblank_on(crtc);
4302
4303 intel_crtc_enable_planes(crtc);
4304 }
4305
4306 /* IPS only exists on ULT machines and is tied to pipe A. */
4307 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4308 {
4309 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4310 }
4311
4312 /*
4313 * This implements the workaround described in the "notes" section of the mode
4314 * set sequence documentation. When going from no pipes or single pipe to
4315 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4316 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4317 */
4318 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4319 {
4320 struct drm_device *dev = crtc->base.dev;
4321 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4322
4323 /* We want to get the other_active_crtc only if there's only 1 other
4324 * active crtc. */
4325 for_each_intel_crtc(dev, crtc_it) {
4326 if (!crtc_it->active || crtc_it == crtc)
4327 continue;
4328
4329 if (other_active_crtc)
4330 return;
4331
4332 other_active_crtc = crtc_it;
4333 }
4334 if (!other_active_crtc)
4335 return;
4336
4337 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4338 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4339 }
4340
4341 static void haswell_crtc_enable(struct drm_crtc *crtc)
4342 {
4343 struct drm_device *dev = crtc->dev;
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4346 struct intel_encoder *encoder;
4347 int pipe = intel_crtc->pipe;
4348
4349 WARN_ON(!crtc->enabled);
4350
4351 if (intel_crtc->active)
4352 return;
4353
4354 if (intel_crtc_to_shared_dpll(intel_crtc))
4355 intel_enable_shared_dpll(intel_crtc);
4356
4357 if (intel_crtc->config.has_dp_encoder)
4358 intel_dp_set_m_n(intel_crtc);
4359
4360 intel_set_pipe_timings(intel_crtc);
4361
4362 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4363 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4364 intel_crtc->config.pixel_multiplier - 1);
4365 }
4366
4367 if (intel_crtc->config.has_pch_encoder) {
4368 intel_cpu_transcoder_set_m_n(intel_crtc,
4369 &intel_crtc->config.fdi_m_n, NULL);
4370 }
4371
4372 haswell_set_pipeconf(crtc);
4373
4374 intel_set_pipe_csc(crtc);
4375
4376 intel_crtc->active = true;
4377
4378 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4379 for_each_encoder_on_crtc(dev, crtc, encoder)
4380 if (encoder->pre_enable)
4381 encoder->pre_enable(encoder);
4382
4383 if (intel_crtc->config.has_pch_encoder) {
4384 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4385 true);
4386 dev_priv->display.fdi_link_train(crtc);
4387 }
4388
4389 intel_ddi_enable_pipe_clock(intel_crtc);
4390
4391 ironlake_pfit_enable(intel_crtc);
4392
4393 /*
4394 * On ILK+ LUT must be loaded before the pipe is running but with
4395 * clocks enabled
4396 */
4397 intel_crtc_load_lut(crtc);
4398
4399 intel_ddi_set_pipe_settings(crtc);
4400 intel_ddi_enable_transcoder_func(crtc);
4401
4402 intel_update_watermarks(crtc);
4403 intel_enable_pipe(intel_crtc);
4404
4405 if (intel_crtc->config.has_pch_encoder)
4406 lpt_pch_enable(crtc);
4407
4408 if (intel_crtc->config.dp_encoder_is_mst)
4409 intel_ddi_set_vc_payload_alloc(crtc, true);
4410
4411 for_each_encoder_on_crtc(dev, crtc, encoder) {
4412 encoder->enable(encoder);
4413 intel_opregion_notify_encoder(encoder, true);
4414 }
4415
4416 assert_vblank_disabled(crtc);
4417 drm_crtc_vblank_on(crtc);
4418
4419 /* If we change the relative order between pipe/planes enabling, we need
4420 * to change the workaround. */
4421 haswell_mode_set_planes_workaround(intel_crtc);
4422 intel_crtc_enable_planes(crtc);
4423 }
4424
4425 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4426 {
4427 struct drm_device *dev = crtc->base.dev;
4428 struct drm_i915_private *dev_priv = dev->dev_private;
4429 int pipe = crtc->pipe;
4430
4431 /* To avoid upsetting the power well on haswell only disable the pfit if
4432 * it's in use. The hw state code will make sure we get this right. */
4433 if (crtc->config.pch_pfit.enabled) {
4434 I915_WRITE(PF_CTL(pipe), 0);
4435 I915_WRITE(PF_WIN_POS(pipe), 0);
4436 I915_WRITE(PF_WIN_SZ(pipe), 0);
4437 }
4438 }
4439
4440 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4441 {
4442 struct drm_device *dev = crtc->dev;
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4445 struct intel_encoder *encoder;
4446 int pipe = intel_crtc->pipe;
4447 u32 reg, temp;
4448
4449 if (!intel_crtc->active)
4450 return;
4451
4452 intel_crtc_disable_planes(crtc);
4453
4454 drm_crtc_vblank_off(crtc);
4455 assert_vblank_disabled(crtc);
4456
4457 for_each_encoder_on_crtc(dev, crtc, encoder)
4458 encoder->disable(encoder);
4459
4460 if (intel_crtc->config.has_pch_encoder)
4461 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4462
4463 intel_disable_pipe(intel_crtc);
4464
4465 ironlake_pfit_disable(intel_crtc);
4466
4467 for_each_encoder_on_crtc(dev, crtc, encoder)
4468 if (encoder->post_disable)
4469 encoder->post_disable(encoder);
4470
4471 if (intel_crtc->config.has_pch_encoder) {
4472 ironlake_fdi_disable(crtc);
4473
4474 ironlake_disable_pch_transcoder(dev_priv, pipe);
4475 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4476
4477 if (HAS_PCH_CPT(dev)) {
4478 /* disable TRANS_DP_CTL */
4479 reg = TRANS_DP_CTL(pipe);
4480 temp = I915_READ(reg);
4481 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4482 TRANS_DP_PORT_SEL_MASK);
4483 temp |= TRANS_DP_PORT_SEL_NONE;
4484 I915_WRITE(reg, temp);
4485
4486 /* disable DPLL_SEL */
4487 temp = I915_READ(PCH_DPLL_SEL);
4488 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4489 I915_WRITE(PCH_DPLL_SEL, temp);
4490 }
4491
4492 /* disable PCH DPLL */
4493 intel_disable_shared_dpll(intel_crtc);
4494
4495 ironlake_fdi_pll_disable(intel_crtc);
4496 }
4497
4498 intel_crtc->active = false;
4499 intel_update_watermarks(crtc);
4500
4501 mutex_lock(&dev->struct_mutex);
4502 intel_update_fbc(dev);
4503 mutex_unlock(&dev->struct_mutex);
4504 }
4505
4506 static void haswell_crtc_disable(struct drm_crtc *crtc)
4507 {
4508 struct drm_device *dev = crtc->dev;
4509 struct drm_i915_private *dev_priv = dev->dev_private;
4510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4511 struct intel_encoder *encoder;
4512 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4513
4514 if (!intel_crtc->active)
4515 return;
4516
4517 intel_crtc_disable_planes(crtc);
4518
4519 drm_crtc_vblank_off(crtc);
4520 assert_vblank_disabled(crtc);
4521
4522 for_each_encoder_on_crtc(dev, crtc, encoder) {
4523 intel_opregion_notify_encoder(encoder, false);
4524 encoder->disable(encoder);
4525 }
4526
4527 if (intel_crtc->config.has_pch_encoder)
4528 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4529 false);
4530 intel_disable_pipe(intel_crtc);
4531
4532 if (intel_crtc->config.dp_encoder_is_mst)
4533 intel_ddi_set_vc_payload_alloc(crtc, false);
4534
4535 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4536
4537 ironlake_pfit_disable(intel_crtc);
4538
4539 intel_ddi_disable_pipe_clock(intel_crtc);
4540
4541 if (intel_crtc->config.has_pch_encoder) {
4542 lpt_disable_pch_transcoder(dev_priv);
4543 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4544 true);
4545 intel_ddi_fdi_disable(crtc);
4546 }
4547
4548 for_each_encoder_on_crtc(dev, crtc, encoder)
4549 if (encoder->post_disable)
4550 encoder->post_disable(encoder);
4551
4552 intel_crtc->active = false;
4553 intel_update_watermarks(crtc);
4554
4555 mutex_lock(&dev->struct_mutex);
4556 intel_update_fbc(dev);
4557 mutex_unlock(&dev->struct_mutex);
4558
4559 if (intel_crtc_to_shared_dpll(intel_crtc))
4560 intel_disable_shared_dpll(intel_crtc);
4561 }
4562
4563 static void ironlake_crtc_off(struct drm_crtc *crtc)
4564 {
4565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4566 intel_put_shared_dpll(intel_crtc);
4567 }
4568
4569
4570 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4571 {
4572 struct drm_device *dev = crtc->base.dev;
4573 struct drm_i915_private *dev_priv = dev->dev_private;
4574 struct intel_crtc_config *pipe_config = &crtc->config;
4575
4576 if (!crtc->config.gmch_pfit.control)
4577 return;
4578
4579 /*
4580 * The panel fitter should only be adjusted whilst the pipe is disabled,
4581 * according to register description and PRM.
4582 */
4583 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4584 assert_pipe_disabled(dev_priv, crtc->pipe);
4585
4586 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4587 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4588
4589 /* Border color in case we don't scale up to the full screen. Black by
4590 * default, change to something else for debugging. */
4591 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4592 }
4593
4594 static enum intel_display_power_domain port_to_power_domain(enum port port)
4595 {
4596 switch (port) {
4597 case PORT_A:
4598 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4599 case PORT_B:
4600 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4601 case PORT_C:
4602 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4603 case PORT_D:
4604 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4605 default:
4606 WARN_ON_ONCE(1);
4607 return POWER_DOMAIN_PORT_OTHER;
4608 }
4609 }
4610
4611 #define for_each_power_domain(domain, mask) \
4612 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4613 if ((1 << (domain)) & (mask))
4614
4615 enum intel_display_power_domain
4616 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4617 {
4618 struct drm_device *dev = intel_encoder->base.dev;
4619 struct intel_digital_port *intel_dig_port;
4620
4621 switch (intel_encoder->type) {
4622 case INTEL_OUTPUT_UNKNOWN:
4623 /* Only DDI platforms should ever use this output type */
4624 WARN_ON_ONCE(!HAS_DDI(dev));
4625 case INTEL_OUTPUT_DISPLAYPORT:
4626 case INTEL_OUTPUT_HDMI:
4627 case INTEL_OUTPUT_EDP:
4628 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4629 return port_to_power_domain(intel_dig_port->port);
4630 case INTEL_OUTPUT_DP_MST:
4631 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4632 return port_to_power_domain(intel_dig_port->port);
4633 case INTEL_OUTPUT_ANALOG:
4634 return POWER_DOMAIN_PORT_CRT;
4635 case INTEL_OUTPUT_DSI:
4636 return POWER_DOMAIN_PORT_DSI;
4637 default:
4638 return POWER_DOMAIN_PORT_OTHER;
4639 }
4640 }
4641
4642 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4643 {
4644 struct drm_device *dev = crtc->dev;
4645 struct intel_encoder *intel_encoder;
4646 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4647 enum pipe pipe = intel_crtc->pipe;
4648 unsigned long mask;
4649 enum transcoder transcoder;
4650
4651 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4652
4653 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4654 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4655 if (intel_crtc->config.pch_pfit.enabled ||
4656 intel_crtc->config.pch_pfit.force_thru)
4657 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4658
4659 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4660 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4661
4662 return mask;
4663 }
4664
4665 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4666 {
4667 struct drm_i915_private *dev_priv = dev->dev_private;
4668 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4669 struct intel_crtc *crtc;
4670
4671 /*
4672 * First get all needed power domains, then put all unneeded, to avoid
4673 * any unnecessary toggling of the power wells.
4674 */
4675 for_each_intel_crtc(dev, crtc) {
4676 enum intel_display_power_domain domain;
4677
4678 if (!crtc->base.enabled)
4679 continue;
4680
4681 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4682
4683 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4684 intel_display_power_get(dev_priv, domain);
4685 }
4686
4687 if (dev_priv->display.modeset_global_resources)
4688 dev_priv->display.modeset_global_resources(dev);
4689
4690 for_each_intel_crtc(dev, crtc) {
4691 enum intel_display_power_domain domain;
4692
4693 for_each_power_domain(domain, crtc->enabled_power_domains)
4694 intel_display_power_put(dev_priv, domain);
4695
4696 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4697 }
4698
4699 intel_display_set_init_power(dev_priv, false);
4700 }
4701
4702 /* returns HPLL frequency in kHz */
4703 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4704 {
4705 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4706
4707 /* Obtain SKU information */
4708 mutex_lock(&dev_priv->dpio_lock);
4709 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4710 CCK_FUSE_HPLL_FREQ_MASK;
4711 mutex_unlock(&dev_priv->dpio_lock);
4712
4713 return vco_freq[hpll_freq] * 1000;
4714 }
4715
4716 static void vlv_update_cdclk(struct drm_device *dev)
4717 {
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719
4720 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4721 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4722 dev_priv->vlv_cdclk_freq);
4723
4724 /*
4725 * Program the gmbus_freq based on the cdclk frequency.
4726 * BSpec erroneously claims we should aim for 4MHz, but
4727 * in fact 1MHz is the correct frequency.
4728 */
4729 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4730 }
4731
4732 /* Adjust CDclk dividers to allow high res or save power if possible */
4733 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4734 {
4735 struct drm_i915_private *dev_priv = dev->dev_private;
4736 u32 val, cmd;
4737
4738 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4739
4740 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4741 cmd = 2;
4742 else if (cdclk == 266667)
4743 cmd = 1;
4744 else
4745 cmd = 0;
4746
4747 mutex_lock(&dev_priv->rps.hw_lock);
4748 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4749 val &= ~DSPFREQGUAR_MASK;
4750 val |= (cmd << DSPFREQGUAR_SHIFT);
4751 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4752 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4753 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4754 50)) {
4755 DRM_ERROR("timed out waiting for CDclk change\n");
4756 }
4757 mutex_unlock(&dev_priv->rps.hw_lock);
4758
4759 if (cdclk == 400000) {
4760 u32 divider;
4761
4762 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4763
4764 mutex_lock(&dev_priv->dpio_lock);
4765 /* adjust cdclk divider */
4766 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4767 val &= ~DISPLAY_FREQUENCY_VALUES;
4768 val |= divider;
4769 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4770
4771 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4772 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4773 50))
4774 DRM_ERROR("timed out waiting for CDclk change\n");
4775 mutex_unlock(&dev_priv->dpio_lock);
4776 }
4777
4778 mutex_lock(&dev_priv->dpio_lock);
4779 /* adjust self-refresh exit latency value */
4780 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4781 val &= ~0x7f;
4782
4783 /*
4784 * For high bandwidth configs, we set a higher latency in the bunit
4785 * so that the core display fetch happens in time to avoid underruns.
4786 */
4787 if (cdclk == 400000)
4788 val |= 4500 / 250; /* 4.5 usec */
4789 else
4790 val |= 3000 / 250; /* 3.0 usec */
4791 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4792 mutex_unlock(&dev_priv->dpio_lock);
4793
4794 vlv_update_cdclk(dev);
4795 }
4796
4797 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4798 {
4799 struct drm_i915_private *dev_priv = dev->dev_private;
4800 u32 val, cmd;
4801
4802 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4803
4804 switch (cdclk) {
4805 case 400000:
4806 cmd = 3;
4807 break;
4808 case 333333:
4809 case 320000:
4810 cmd = 2;
4811 break;
4812 case 266667:
4813 cmd = 1;
4814 break;
4815 case 200000:
4816 cmd = 0;
4817 break;
4818 default:
4819 WARN_ON(1);
4820 return;
4821 }
4822
4823 mutex_lock(&dev_priv->rps.hw_lock);
4824 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4825 val &= ~DSPFREQGUAR_MASK_CHV;
4826 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4827 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4828 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4829 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4830 50)) {
4831 DRM_ERROR("timed out waiting for CDclk change\n");
4832 }
4833 mutex_unlock(&dev_priv->rps.hw_lock);
4834
4835 vlv_update_cdclk(dev);
4836 }
4837
4838 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4839 int max_pixclk)
4840 {
4841 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
4842
4843 /* FIXME: Punit isn't quite ready yet */
4844 if (IS_CHERRYVIEW(dev_priv->dev))
4845 return 400000;
4846
4847 /*
4848 * Really only a few cases to deal with, as only 4 CDclks are supported:
4849 * 200MHz
4850 * 267MHz
4851 * 320/333MHz (depends on HPLL freq)
4852 * 400MHz
4853 * So we check to see whether we're above 90% of the lower bin and
4854 * adjust if needed.
4855 *
4856 * We seem to get an unstable or solid color picture at 200MHz.
4857 * Not sure what's wrong. For now use 200MHz only when all pipes
4858 * are off.
4859 */
4860 if (max_pixclk > freq_320*9/10)
4861 return 400000;
4862 else if (max_pixclk > 266667*9/10)
4863 return freq_320;
4864 else if (max_pixclk > 0)
4865 return 266667;
4866 else
4867 return 200000;
4868 }
4869
4870 /* compute the max pixel clock for new configuration */
4871 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4872 {
4873 struct drm_device *dev = dev_priv->dev;
4874 struct intel_crtc *intel_crtc;
4875 int max_pixclk = 0;
4876
4877 for_each_intel_crtc(dev, intel_crtc) {
4878 if (intel_crtc->new_enabled)
4879 max_pixclk = max(max_pixclk,
4880 intel_crtc->new_config->adjusted_mode.crtc_clock);
4881 }
4882
4883 return max_pixclk;
4884 }
4885
4886 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4887 unsigned *prepare_pipes)
4888 {
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 struct intel_crtc *intel_crtc;
4891 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4892
4893 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4894 dev_priv->vlv_cdclk_freq)
4895 return;
4896
4897 /* disable/enable all currently active pipes while we change cdclk */
4898 for_each_intel_crtc(dev, intel_crtc)
4899 if (intel_crtc->base.enabled)
4900 *prepare_pipes |= (1 << intel_crtc->pipe);
4901 }
4902
4903 static void valleyview_modeset_global_resources(struct drm_device *dev)
4904 {
4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4907 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4908
4909 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4910 if (IS_CHERRYVIEW(dev))
4911 cherryview_set_cdclk(dev, req_cdclk);
4912 else
4913 valleyview_set_cdclk(dev, req_cdclk);
4914 }
4915 }
4916
4917 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4918 {
4919 struct drm_device *dev = crtc->dev;
4920 struct drm_i915_private *dev_priv = to_i915(dev);
4921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4922 struct intel_encoder *encoder;
4923 int pipe = intel_crtc->pipe;
4924 bool is_dsi;
4925
4926 WARN_ON(!crtc->enabled);
4927
4928 if (intel_crtc->active)
4929 return;
4930
4931 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4932
4933 if (!is_dsi) {
4934 if (IS_CHERRYVIEW(dev))
4935 chv_prepare_pll(intel_crtc, &intel_crtc->config);
4936 else
4937 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4938 }
4939
4940 if (intel_crtc->config.has_dp_encoder)
4941 intel_dp_set_m_n(intel_crtc);
4942
4943 intel_set_pipe_timings(intel_crtc);
4944
4945 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947
4948 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4949 I915_WRITE(CHV_CANVAS(pipe), 0);
4950 }
4951
4952 i9xx_set_pipeconf(intel_crtc);
4953
4954 intel_crtc->active = true;
4955
4956 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957
4958 for_each_encoder_on_crtc(dev, crtc, encoder)
4959 if (encoder->pre_pll_enable)
4960 encoder->pre_pll_enable(encoder);
4961
4962 if (!is_dsi) {
4963 if (IS_CHERRYVIEW(dev))
4964 chv_enable_pll(intel_crtc, &intel_crtc->config);
4965 else
4966 vlv_enable_pll(intel_crtc, &intel_crtc->config);
4967 }
4968
4969 for_each_encoder_on_crtc(dev, crtc, encoder)
4970 if (encoder->pre_enable)
4971 encoder->pre_enable(encoder);
4972
4973 i9xx_pfit_enable(intel_crtc);
4974
4975 intel_crtc_load_lut(crtc);
4976
4977 intel_update_watermarks(crtc);
4978 intel_enable_pipe(intel_crtc);
4979
4980 for_each_encoder_on_crtc(dev, crtc, encoder)
4981 encoder->enable(encoder);
4982
4983 assert_vblank_disabled(crtc);
4984 drm_crtc_vblank_on(crtc);
4985
4986 intel_crtc_enable_planes(crtc);
4987
4988 /* Underruns don't raise interrupts, so check manually. */
4989 i9xx_check_fifo_underruns(dev_priv);
4990 }
4991
4992 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4993 {
4994 struct drm_device *dev = crtc->base.dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996
4997 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4998 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4999 }
5000
5001 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5002 {
5003 struct drm_device *dev = crtc->dev;
5004 struct drm_i915_private *dev_priv = to_i915(dev);
5005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5006 struct intel_encoder *encoder;
5007 int pipe = intel_crtc->pipe;
5008
5009 WARN_ON(!crtc->enabled);
5010
5011 if (intel_crtc->active)
5012 return;
5013
5014 i9xx_set_pll_dividers(intel_crtc);
5015
5016 if (intel_crtc->config.has_dp_encoder)
5017 intel_dp_set_m_n(intel_crtc);
5018
5019 intel_set_pipe_timings(intel_crtc);
5020
5021 i9xx_set_pipeconf(intel_crtc);
5022
5023 intel_crtc->active = true;
5024
5025 if (!IS_GEN2(dev))
5026 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5027
5028 for_each_encoder_on_crtc(dev, crtc, encoder)
5029 if (encoder->pre_enable)
5030 encoder->pre_enable(encoder);
5031
5032 i9xx_enable_pll(intel_crtc);
5033
5034 i9xx_pfit_enable(intel_crtc);
5035
5036 intel_crtc_load_lut(crtc);
5037
5038 intel_update_watermarks(crtc);
5039 intel_enable_pipe(intel_crtc);
5040
5041 for_each_encoder_on_crtc(dev, crtc, encoder)
5042 encoder->enable(encoder);
5043
5044 assert_vblank_disabled(crtc);
5045 drm_crtc_vblank_on(crtc);
5046
5047 intel_crtc_enable_planes(crtc);
5048
5049 /*
5050 * Gen2 reports pipe underruns whenever all planes are disabled.
5051 * So don't enable underrun reporting before at least some planes
5052 * are enabled.
5053 * FIXME: Need to fix the logic to work when we turn off all planes
5054 * but leave the pipe running.
5055 */
5056 if (IS_GEN2(dev))
5057 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5058
5059 /* Underruns don't raise interrupts, so check manually. */
5060 i9xx_check_fifo_underruns(dev_priv);
5061 }
5062
5063 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5064 {
5065 struct drm_device *dev = crtc->base.dev;
5066 struct drm_i915_private *dev_priv = dev->dev_private;
5067
5068 if (!crtc->config.gmch_pfit.control)
5069 return;
5070
5071 assert_pipe_disabled(dev_priv, crtc->pipe);
5072
5073 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5074 I915_READ(PFIT_CONTROL));
5075 I915_WRITE(PFIT_CONTROL, 0);
5076 }
5077
5078 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5079 {
5080 struct drm_device *dev = crtc->dev;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083 struct intel_encoder *encoder;
5084 int pipe = intel_crtc->pipe;
5085
5086 if (!intel_crtc->active)
5087 return;
5088
5089 /*
5090 * Gen2 reports pipe underruns whenever all planes are disabled.
5091 * So diasble underrun reporting before all the planes get disabled.
5092 * FIXME: Need to fix the logic to work when we turn off all planes
5093 * but leave the pipe running.
5094 */
5095 if (IS_GEN2(dev))
5096 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5097
5098 /*
5099 * Vblank time updates from the shadow to live plane control register
5100 * are blocked if the memory self-refresh mode is active at that
5101 * moment. So to make sure the plane gets truly disabled, disable
5102 * first the self-refresh mode. The self-refresh enable bit in turn
5103 * will be checked/applied by the HW only at the next frame start
5104 * event which is after the vblank start event, so we need to have a
5105 * wait-for-vblank between disabling the plane and the pipe.
5106 */
5107 intel_set_memory_cxsr(dev_priv, false);
5108 intel_crtc_disable_planes(crtc);
5109
5110 /*
5111 * On gen2 planes are double buffered but the pipe isn't, so we must
5112 * wait for planes to fully turn off before disabling the pipe.
5113 * We also need to wait on all gmch platforms because of the
5114 * self-refresh mode constraint explained above.
5115 */
5116 intel_wait_for_vblank(dev, pipe);
5117
5118 drm_crtc_vblank_off(crtc);
5119 assert_vblank_disabled(crtc);
5120
5121 for_each_encoder_on_crtc(dev, crtc, encoder)
5122 encoder->disable(encoder);
5123
5124 intel_disable_pipe(intel_crtc);
5125
5126 i9xx_pfit_disable(intel_crtc);
5127
5128 for_each_encoder_on_crtc(dev, crtc, encoder)
5129 if (encoder->post_disable)
5130 encoder->post_disable(encoder);
5131
5132 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5133 if (IS_CHERRYVIEW(dev))
5134 chv_disable_pll(dev_priv, pipe);
5135 else if (IS_VALLEYVIEW(dev))
5136 vlv_disable_pll(dev_priv, pipe);
5137 else
5138 i9xx_disable_pll(intel_crtc);
5139 }
5140
5141 if (!IS_GEN2(dev))
5142 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5143
5144 intel_crtc->active = false;
5145 intel_update_watermarks(crtc);
5146
5147 mutex_lock(&dev->struct_mutex);
5148 intel_update_fbc(dev);
5149 mutex_unlock(&dev->struct_mutex);
5150 }
5151
5152 static void i9xx_crtc_off(struct drm_crtc *crtc)
5153 {
5154 }
5155
5156 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5157 bool enabled)
5158 {
5159 struct drm_device *dev = crtc->dev;
5160 struct drm_i915_master_private *master_priv;
5161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5162 int pipe = intel_crtc->pipe;
5163
5164 if (!dev->primary->master)
5165 return;
5166
5167 master_priv = dev->primary->master->driver_priv;
5168 if (!master_priv->sarea_priv)
5169 return;
5170
5171 switch (pipe) {
5172 case 0:
5173 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5174 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5175 break;
5176 case 1:
5177 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5178 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5179 break;
5180 default:
5181 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5182 break;
5183 }
5184 }
5185
5186 /* Master function to enable/disable CRTC and corresponding power wells */
5187 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5188 {
5189 struct drm_device *dev = crtc->dev;
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5192 enum intel_display_power_domain domain;
5193 unsigned long domains;
5194
5195 if (enable) {
5196 if (!intel_crtc->active) {
5197 domains = get_crtc_power_domains(crtc);
5198 for_each_power_domain(domain, domains)
5199 intel_display_power_get(dev_priv, domain);
5200 intel_crtc->enabled_power_domains = domains;
5201
5202 dev_priv->display.crtc_enable(crtc);
5203 }
5204 } else {
5205 if (intel_crtc->active) {
5206 dev_priv->display.crtc_disable(crtc);
5207
5208 domains = intel_crtc->enabled_power_domains;
5209 for_each_power_domain(domain, domains)
5210 intel_display_power_put(dev_priv, domain);
5211 intel_crtc->enabled_power_domains = 0;
5212 }
5213 }
5214 }
5215
5216 /**
5217 * Sets the power management mode of the pipe and plane.
5218 */
5219 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5220 {
5221 struct drm_device *dev = crtc->dev;
5222 struct intel_encoder *intel_encoder;
5223 bool enable = false;
5224
5225 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5226 enable |= intel_encoder->connectors_active;
5227
5228 intel_crtc_control(crtc, enable);
5229
5230 intel_crtc_update_sarea(crtc, enable);
5231 }
5232
5233 static void intel_crtc_disable(struct drm_crtc *crtc)
5234 {
5235 struct drm_device *dev = crtc->dev;
5236 struct drm_connector *connector;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5239 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5240
5241 /* crtc should still be enabled when we disable it. */
5242 WARN_ON(!crtc->enabled);
5243
5244 dev_priv->display.crtc_disable(crtc);
5245 intel_crtc_update_sarea(crtc, false);
5246 dev_priv->display.off(crtc);
5247
5248 if (crtc->primary->fb) {
5249 mutex_lock(&dev->struct_mutex);
5250 intel_unpin_fb_obj(old_obj);
5251 i915_gem_track_fb(old_obj, NULL,
5252 INTEL_FRONTBUFFER_PRIMARY(pipe));
5253 mutex_unlock(&dev->struct_mutex);
5254 crtc->primary->fb = NULL;
5255 }
5256
5257 /* Update computed state. */
5258 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5259 if (!connector->encoder || !connector->encoder->crtc)
5260 continue;
5261
5262 if (connector->encoder->crtc != crtc)
5263 continue;
5264
5265 connector->dpms = DRM_MODE_DPMS_OFF;
5266 to_intel_encoder(connector->encoder)->connectors_active = false;
5267 }
5268 }
5269
5270 void intel_encoder_destroy(struct drm_encoder *encoder)
5271 {
5272 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5273
5274 drm_encoder_cleanup(encoder);
5275 kfree(intel_encoder);
5276 }
5277
5278 /* Simple dpms helper for encoders with just one connector, no cloning and only
5279 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5280 * state of the entire output pipe. */
5281 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5282 {
5283 if (mode == DRM_MODE_DPMS_ON) {
5284 encoder->connectors_active = true;
5285
5286 intel_crtc_update_dpms(encoder->base.crtc);
5287 } else {
5288 encoder->connectors_active = false;
5289
5290 intel_crtc_update_dpms(encoder->base.crtc);
5291 }
5292 }
5293
5294 /* Cross check the actual hw state with our own modeset state tracking (and it's
5295 * internal consistency). */
5296 static void intel_connector_check_state(struct intel_connector *connector)
5297 {
5298 if (connector->get_hw_state(connector)) {
5299 struct intel_encoder *encoder = connector->encoder;
5300 struct drm_crtc *crtc;
5301 bool encoder_enabled;
5302 enum pipe pipe;
5303
5304 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5305 connector->base.base.id,
5306 connector->base.name);
5307
5308 /* there is no real hw state for MST connectors */
5309 if (connector->mst_port)
5310 return;
5311
5312 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5313 "wrong connector dpms state\n");
5314 WARN(connector->base.encoder != &encoder->base,
5315 "active connector not linked to encoder\n");
5316
5317 if (encoder) {
5318 WARN(!encoder->connectors_active,
5319 "encoder->connectors_active not set\n");
5320
5321 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5322 WARN(!encoder_enabled, "encoder not enabled\n");
5323 if (WARN_ON(!encoder->base.crtc))
5324 return;
5325
5326 crtc = encoder->base.crtc;
5327
5328 WARN(!crtc->enabled, "crtc not enabled\n");
5329 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5330 WARN(pipe != to_intel_crtc(crtc)->pipe,
5331 "encoder active on the wrong pipe\n");
5332 }
5333 }
5334 }
5335
5336 /* Even simpler default implementation, if there's really no special case to
5337 * consider. */
5338 void intel_connector_dpms(struct drm_connector *connector, int mode)
5339 {
5340 /* All the simple cases only support two dpms states. */
5341 if (mode != DRM_MODE_DPMS_ON)
5342 mode = DRM_MODE_DPMS_OFF;
5343
5344 if (mode == connector->dpms)
5345 return;
5346
5347 connector->dpms = mode;
5348
5349 /* Only need to change hw state when actually enabled */
5350 if (connector->encoder)
5351 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5352
5353 intel_modeset_check_state(connector->dev);
5354 }
5355
5356 /* Simple connector->get_hw_state implementation for encoders that support only
5357 * one connector and no cloning and hence the encoder state determines the state
5358 * of the connector. */
5359 bool intel_connector_get_hw_state(struct intel_connector *connector)
5360 {
5361 enum pipe pipe = 0;
5362 struct intel_encoder *encoder = connector->encoder;
5363
5364 return encoder->get_hw_state(encoder, &pipe);
5365 }
5366
5367 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5368 struct intel_crtc_config *pipe_config)
5369 {
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5371 struct intel_crtc *pipe_B_crtc =
5372 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5373
5374 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5375 pipe_name(pipe), pipe_config->fdi_lanes);
5376 if (pipe_config->fdi_lanes > 4) {
5377 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5378 pipe_name(pipe), pipe_config->fdi_lanes);
5379 return false;
5380 }
5381
5382 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5383 if (pipe_config->fdi_lanes > 2) {
5384 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5385 pipe_config->fdi_lanes);
5386 return false;
5387 } else {
5388 return true;
5389 }
5390 }
5391
5392 if (INTEL_INFO(dev)->num_pipes == 2)
5393 return true;
5394
5395 /* Ivybridge 3 pipe is really complicated */
5396 switch (pipe) {
5397 case PIPE_A:
5398 return true;
5399 case PIPE_B:
5400 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5401 pipe_config->fdi_lanes > 2) {
5402 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5403 pipe_name(pipe), pipe_config->fdi_lanes);
5404 return false;
5405 }
5406 return true;
5407 case PIPE_C:
5408 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5409 pipe_B_crtc->config.fdi_lanes <= 2) {
5410 if (pipe_config->fdi_lanes > 2) {
5411 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5412 pipe_name(pipe), pipe_config->fdi_lanes);
5413 return false;
5414 }
5415 } else {
5416 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5417 return false;
5418 }
5419 return true;
5420 default:
5421 BUG();
5422 }
5423 }
5424
5425 #define RETRY 1
5426 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5427 struct intel_crtc_config *pipe_config)
5428 {
5429 struct drm_device *dev = intel_crtc->base.dev;
5430 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5431 int lane, link_bw, fdi_dotclock;
5432 bool setup_ok, needs_recompute = false;
5433
5434 retry:
5435 /* FDI is a binary signal running at ~2.7GHz, encoding
5436 * each output octet as 10 bits. The actual frequency
5437 * is stored as a divider into a 100MHz clock, and the
5438 * mode pixel clock is stored in units of 1KHz.
5439 * Hence the bw of each lane in terms of the mode signal
5440 * is:
5441 */
5442 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5443
5444 fdi_dotclock = adjusted_mode->crtc_clock;
5445
5446 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5447 pipe_config->pipe_bpp);
5448
5449 pipe_config->fdi_lanes = lane;
5450
5451 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5452 link_bw, &pipe_config->fdi_m_n);
5453
5454 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5455 intel_crtc->pipe, pipe_config);
5456 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5457 pipe_config->pipe_bpp -= 2*3;
5458 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5459 pipe_config->pipe_bpp);
5460 needs_recompute = true;
5461 pipe_config->bw_constrained = true;
5462
5463 goto retry;
5464 }
5465
5466 if (needs_recompute)
5467 return RETRY;
5468
5469 return setup_ok ? 0 : -EINVAL;
5470 }
5471
5472 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5473 struct intel_crtc_config *pipe_config)
5474 {
5475 pipe_config->ips_enabled = i915.enable_ips &&
5476 hsw_crtc_supports_ips(crtc) &&
5477 pipe_config->pipe_bpp <= 24;
5478 }
5479
5480 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5481 struct intel_crtc_config *pipe_config)
5482 {
5483 struct drm_device *dev = crtc->base.dev;
5484 struct drm_i915_private *dev_priv = dev->dev_private;
5485 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5486
5487 /* FIXME should check pixel clock limits on all platforms */
5488 if (INTEL_INFO(dev)->gen < 4) {
5489 int clock_limit =
5490 dev_priv->display.get_display_clock_speed(dev);
5491
5492 /*
5493 * Enable pixel doubling when the dot clock
5494 * is > 90% of the (display) core speed.
5495 *
5496 * GDG double wide on either pipe,
5497 * otherwise pipe A only.
5498 */
5499 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5500 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5501 clock_limit *= 2;
5502 pipe_config->double_wide = true;
5503 }
5504
5505 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5506 return -EINVAL;
5507 }
5508
5509 /*
5510 * Pipe horizontal size must be even in:
5511 * - DVO ganged mode
5512 * - LVDS dual channel mode
5513 * - Double wide pipe
5514 */
5515 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5516 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5517 pipe_config->pipe_src_w &= ~1;
5518
5519 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5520 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5521 */
5522 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5523 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5524 return -EINVAL;
5525
5526 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5527 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5528 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5529 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5530 * for lvds. */
5531 pipe_config->pipe_bpp = 8*3;
5532 }
5533
5534 if (HAS_IPS(dev))
5535 hsw_compute_ips_config(crtc, pipe_config);
5536
5537 if (pipe_config->has_pch_encoder)
5538 return ironlake_fdi_compute_config(crtc, pipe_config);
5539
5540 return 0;
5541 }
5542
5543 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5544 {
5545 struct drm_i915_private *dev_priv = dev->dev_private;
5546 u32 val;
5547 int divider;
5548
5549 /* FIXME: Punit isn't quite ready yet */
5550 if (IS_CHERRYVIEW(dev))
5551 return 400000;
5552
5553 if (dev_priv->hpll_freq == 0)
5554 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5555
5556 mutex_lock(&dev_priv->dpio_lock);
5557 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5558 mutex_unlock(&dev_priv->dpio_lock);
5559
5560 divider = val & DISPLAY_FREQUENCY_VALUES;
5561
5562 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5563 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5564 "cdclk change in progress\n");
5565
5566 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5567 }
5568
5569 static int i945_get_display_clock_speed(struct drm_device *dev)
5570 {
5571 return 400000;
5572 }
5573
5574 static int i915_get_display_clock_speed(struct drm_device *dev)
5575 {
5576 return 333000;
5577 }
5578
5579 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5580 {
5581 return 200000;
5582 }
5583
5584 static int pnv_get_display_clock_speed(struct drm_device *dev)
5585 {
5586 u16 gcfgc = 0;
5587
5588 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5589
5590 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5591 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5592 return 267000;
5593 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5594 return 333000;
5595 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5596 return 444000;
5597 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5598 return 200000;
5599 default:
5600 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5601 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5602 return 133000;
5603 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5604 return 167000;
5605 }
5606 }
5607
5608 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5609 {
5610 u16 gcfgc = 0;
5611
5612 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5613
5614 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5615 return 133000;
5616 else {
5617 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5618 case GC_DISPLAY_CLOCK_333_MHZ:
5619 return 333000;
5620 default:
5621 case GC_DISPLAY_CLOCK_190_200_MHZ:
5622 return 190000;
5623 }
5624 }
5625 }
5626
5627 static int i865_get_display_clock_speed(struct drm_device *dev)
5628 {
5629 return 266000;
5630 }
5631
5632 static int i855_get_display_clock_speed(struct drm_device *dev)
5633 {
5634 u16 hpllcc = 0;
5635 /* Assume that the hardware is in the high speed state. This
5636 * should be the default.
5637 */
5638 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5639 case GC_CLOCK_133_200:
5640 case GC_CLOCK_100_200:
5641 return 200000;
5642 case GC_CLOCK_166_250:
5643 return 250000;
5644 case GC_CLOCK_100_133:
5645 return 133000;
5646 }
5647
5648 /* Shouldn't happen */
5649 return 0;
5650 }
5651
5652 static int i830_get_display_clock_speed(struct drm_device *dev)
5653 {
5654 return 133000;
5655 }
5656
5657 static void
5658 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5659 {
5660 while (*num > DATA_LINK_M_N_MASK ||
5661 *den > DATA_LINK_M_N_MASK) {
5662 *num >>= 1;
5663 *den >>= 1;
5664 }
5665 }
5666
5667 static void compute_m_n(unsigned int m, unsigned int n,
5668 uint32_t *ret_m, uint32_t *ret_n)
5669 {
5670 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5671 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5672 intel_reduce_m_n_ratio(ret_m, ret_n);
5673 }
5674
5675 void
5676 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5677 int pixel_clock, int link_clock,
5678 struct intel_link_m_n *m_n)
5679 {
5680 m_n->tu = 64;
5681
5682 compute_m_n(bits_per_pixel * pixel_clock,
5683 link_clock * nlanes * 8,
5684 &m_n->gmch_m, &m_n->gmch_n);
5685
5686 compute_m_n(pixel_clock, link_clock,
5687 &m_n->link_m, &m_n->link_n);
5688 }
5689
5690 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5691 {
5692 if (i915.panel_use_ssc >= 0)
5693 return i915.panel_use_ssc != 0;
5694 return dev_priv->vbt.lvds_use_ssc
5695 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5696 }
5697
5698 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5699 {
5700 struct drm_device *dev = crtc->base.dev;
5701 struct drm_i915_private *dev_priv = dev->dev_private;
5702 int refclk;
5703
5704 if (IS_VALLEYVIEW(dev)) {
5705 refclk = 100000;
5706 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5707 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5708 refclk = dev_priv->vbt.lvds_ssc_freq;
5709 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5710 } else if (!IS_GEN2(dev)) {
5711 refclk = 96000;
5712 } else {
5713 refclk = 48000;
5714 }
5715
5716 return refclk;
5717 }
5718
5719 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5720 {
5721 return (1 << dpll->n) << 16 | dpll->m2;
5722 }
5723
5724 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5725 {
5726 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5727 }
5728
5729 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5730 intel_clock_t *reduced_clock)
5731 {
5732 struct drm_device *dev = crtc->base.dev;
5733 u32 fp, fp2 = 0;
5734
5735 if (IS_PINEVIEW(dev)) {
5736 fp = pnv_dpll_compute_fp(&crtc->new_config->dpll);
5737 if (reduced_clock)
5738 fp2 = pnv_dpll_compute_fp(reduced_clock);
5739 } else {
5740 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
5741 if (reduced_clock)
5742 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5743 }
5744
5745 crtc->new_config->dpll_hw_state.fp0 = fp;
5746
5747 crtc->lowfreq_avail = false;
5748 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5749 reduced_clock && i915.powersave) {
5750 crtc->new_config->dpll_hw_state.fp1 = fp2;
5751 crtc->lowfreq_avail = true;
5752 } else {
5753 crtc->new_config->dpll_hw_state.fp1 = fp;
5754 }
5755 }
5756
5757 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5758 pipe)
5759 {
5760 u32 reg_val;
5761
5762 /*
5763 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5764 * and set it to a reasonable value instead.
5765 */
5766 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5767 reg_val &= 0xffffff00;
5768 reg_val |= 0x00000030;
5769 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5770
5771 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5772 reg_val &= 0x8cffffff;
5773 reg_val = 0x8c000000;
5774 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5775
5776 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5777 reg_val &= 0xffffff00;
5778 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5779
5780 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5781 reg_val &= 0x00ffffff;
5782 reg_val |= 0xb0000000;
5783 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5784 }
5785
5786 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5787 struct intel_link_m_n *m_n)
5788 {
5789 struct drm_device *dev = crtc->base.dev;
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791 int pipe = crtc->pipe;
5792
5793 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5794 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5795 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5796 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5797 }
5798
5799 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5800 struct intel_link_m_n *m_n,
5801 struct intel_link_m_n *m2_n2)
5802 {
5803 struct drm_device *dev = crtc->base.dev;
5804 struct drm_i915_private *dev_priv = dev->dev_private;
5805 int pipe = crtc->pipe;
5806 enum transcoder transcoder = crtc->config.cpu_transcoder;
5807
5808 if (INTEL_INFO(dev)->gen >= 5) {
5809 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5810 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5811 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5812 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5813 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5814 * for gen < 8) and if DRRS is supported (to make sure the
5815 * registers are not unnecessarily accessed).
5816 */
5817 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5818 crtc->config.has_drrs) {
5819 I915_WRITE(PIPE_DATA_M2(transcoder),
5820 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5821 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5822 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5823 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5824 }
5825 } else {
5826 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5827 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5828 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5829 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5830 }
5831 }
5832
5833 void intel_dp_set_m_n(struct intel_crtc *crtc)
5834 {
5835 if (crtc->config.has_pch_encoder)
5836 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5837 else
5838 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5839 &crtc->config.dp_m2_n2);
5840 }
5841
5842 static void vlv_update_pll(struct intel_crtc *crtc,
5843 struct intel_crtc_config *pipe_config)
5844 {
5845 u32 dpll, dpll_md;
5846
5847 /*
5848 * Enable DPIO clock input. We should never disable the reference
5849 * clock for pipe B, since VGA hotplug / manual detection depends
5850 * on it.
5851 */
5852 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5853 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5854 /* We should never disable this, set it here for state tracking */
5855 if (crtc->pipe == PIPE_B)
5856 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5857 dpll |= DPLL_VCO_ENABLE;
5858 pipe_config->dpll_hw_state.dpll = dpll;
5859
5860 dpll_md = (pipe_config->pixel_multiplier - 1)
5861 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5862 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5863 }
5864
5865 static void vlv_prepare_pll(struct intel_crtc *crtc,
5866 const struct intel_crtc_config *pipe_config)
5867 {
5868 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 int pipe = crtc->pipe;
5871 u32 mdiv;
5872 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5873 u32 coreclk, reg_val;
5874
5875 mutex_lock(&dev_priv->dpio_lock);
5876
5877 bestn = pipe_config->dpll.n;
5878 bestm1 = pipe_config->dpll.m1;
5879 bestm2 = pipe_config->dpll.m2;
5880 bestp1 = pipe_config->dpll.p1;
5881 bestp2 = pipe_config->dpll.p2;
5882
5883 /* See eDP HDMI DPIO driver vbios notes doc */
5884
5885 /* PLL B needs special handling */
5886 if (pipe == PIPE_B)
5887 vlv_pllb_recal_opamp(dev_priv, pipe);
5888
5889 /* Set up Tx target for periodic Rcomp update */
5890 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5891
5892 /* Disable target IRef on PLL */
5893 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5894 reg_val &= 0x00ffffff;
5895 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5896
5897 /* Disable fast lock */
5898 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5899
5900 /* Set idtafcrecal before PLL is enabled */
5901 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5902 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5903 mdiv |= ((bestn << DPIO_N_SHIFT));
5904 mdiv |= (1 << DPIO_K_SHIFT);
5905
5906 /*
5907 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5908 * but we don't support that).
5909 * Note: don't use the DAC post divider as it seems unstable.
5910 */
5911 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5912 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5913
5914 mdiv |= DPIO_ENABLE_CALIBRATION;
5915 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5916
5917 /* Set HBR and RBR LPF coefficients */
5918 if (pipe_config->port_clock == 162000 ||
5919 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5920 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5921 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5922 0x009f0003);
5923 else
5924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5925 0x00d0000f);
5926
5927 if (crtc->config.has_dp_encoder) {
5928 /* Use SSC source */
5929 if (pipe == PIPE_A)
5930 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5931 0x0df40000);
5932 else
5933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5934 0x0df70000);
5935 } else { /* HDMI or VGA */
5936 /* Use bend source */
5937 if (pipe == PIPE_A)
5938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5939 0x0df70000);
5940 else
5941 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5942 0x0df40000);
5943 }
5944
5945 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5946 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5947 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5948 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5949 coreclk |= 0x01000000;
5950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5951
5952 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5953 mutex_unlock(&dev_priv->dpio_lock);
5954 }
5955
5956 static void chv_update_pll(struct intel_crtc *crtc,
5957 struct intel_crtc_config *pipe_config)
5958 {
5959 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5960 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5961 DPLL_VCO_ENABLE;
5962 if (crtc->pipe != PIPE_A)
5963 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5964
5965 pipe_config->dpll_hw_state.dpll_md =
5966 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5967 }
5968
5969 static void chv_prepare_pll(struct intel_crtc *crtc,
5970 const struct intel_crtc_config *pipe_config)
5971 {
5972 struct drm_device *dev = crtc->base.dev;
5973 struct drm_i915_private *dev_priv = dev->dev_private;
5974 int pipe = crtc->pipe;
5975 int dpll_reg = DPLL(crtc->pipe);
5976 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5977 u32 loopfilter, intcoeff;
5978 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5979 int refclk;
5980
5981 bestn = pipe_config->dpll.n;
5982 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5983 bestm1 = pipe_config->dpll.m1;
5984 bestm2 = pipe_config->dpll.m2 >> 22;
5985 bestp1 = pipe_config->dpll.p1;
5986 bestp2 = pipe_config->dpll.p2;
5987
5988 /*
5989 * Enable Refclk and SSC
5990 */
5991 I915_WRITE(dpll_reg,
5992 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5993
5994 mutex_lock(&dev_priv->dpio_lock);
5995
5996 /* p1 and p2 divider */
5997 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5998 5 << DPIO_CHV_S1_DIV_SHIFT |
5999 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6000 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6001 1 << DPIO_CHV_K_DIV_SHIFT);
6002
6003 /* Feedback post-divider - m2 */
6004 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6005
6006 /* Feedback refclk divider - n and m1 */
6007 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6008 DPIO_CHV_M1_DIV_BY_2 |
6009 1 << DPIO_CHV_N_DIV_SHIFT);
6010
6011 /* M2 fraction division */
6012 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6013
6014 /* M2 fraction division enable */
6015 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6016 DPIO_CHV_FRAC_DIV_EN |
6017 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6018
6019 /* Loop filter */
6020 refclk = i9xx_get_refclk(crtc, 0);
6021 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6022 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6023 if (refclk == 100000)
6024 intcoeff = 11;
6025 else if (refclk == 38400)
6026 intcoeff = 10;
6027 else
6028 intcoeff = 9;
6029 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6030 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6031
6032 /* AFC Recal */
6033 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6034 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6035 DPIO_AFC_RECAL);
6036
6037 mutex_unlock(&dev_priv->dpio_lock);
6038 }
6039
6040 /**
6041 * vlv_force_pll_on - forcibly enable just the PLL
6042 * @dev_priv: i915 private structure
6043 * @pipe: pipe PLL to enable
6044 * @dpll: PLL configuration
6045 *
6046 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6047 * in cases where we need the PLL enabled even when @pipe is not going to
6048 * be enabled.
6049 */
6050 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6051 const struct dpll *dpll)
6052 {
6053 struct intel_crtc *crtc =
6054 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6055 struct intel_crtc_config pipe_config = {
6056 .pixel_multiplier = 1,
6057 .dpll = *dpll,
6058 };
6059
6060 if (IS_CHERRYVIEW(dev)) {
6061 chv_update_pll(crtc, &pipe_config);
6062 chv_prepare_pll(crtc, &pipe_config);
6063 chv_enable_pll(crtc, &pipe_config);
6064 } else {
6065 vlv_update_pll(crtc, &pipe_config);
6066 vlv_prepare_pll(crtc, &pipe_config);
6067 vlv_enable_pll(crtc, &pipe_config);
6068 }
6069 }
6070
6071 /**
6072 * vlv_force_pll_off - forcibly disable just the PLL
6073 * @dev_priv: i915 private structure
6074 * @pipe: pipe PLL to disable
6075 *
6076 * Disable the PLL for @pipe. To be used in cases where we need
6077 * the PLL enabled even when @pipe is not going to be enabled.
6078 */
6079 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6080 {
6081 if (IS_CHERRYVIEW(dev))
6082 chv_disable_pll(to_i915(dev), pipe);
6083 else
6084 vlv_disable_pll(to_i915(dev), pipe);
6085 }
6086
6087 static void i9xx_update_pll(struct intel_crtc *crtc,
6088 intel_clock_t *reduced_clock,
6089 int num_connectors)
6090 {
6091 struct drm_device *dev = crtc->base.dev;
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093 u32 dpll;
6094 bool is_sdvo;
6095 struct dpll *clock = &crtc->new_config->dpll;
6096
6097 i9xx_update_pll_dividers(crtc, reduced_clock);
6098
6099 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6100 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6101
6102 dpll = DPLL_VGA_MODE_DIS;
6103
6104 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6105 dpll |= DPLLB_MODE_LVDS;
6106 else
6107 dpll |= DPLLB_MODE_DAC_SERIAL;
6108
6109 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6110 dpll |= (crtc->new_config->pixel_multiplier - 1)
6111 << SDVO_MULTIPLIER_SHIFT_HIRES;
6112 }
6113
6114 if (is_sdvo)
6115 dpll |= DPLL_SDVO_HIGH_SPEED;
6116
6117 if (crtc->new_config->has_dp_encoder)
6118 dpll |= DPLL_SDVO_HIGH_SPEED;
6119
6120 /* compute bitmask from p1 value */
6121 if (IS_PINEVIEW(dev))
6122 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6123 else {
6124 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6125 if (IS_G4X(dev) && reduced_clock)
6126 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6127 }
6128 switch (clock->p2) {
6129 case 5:
6130 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6131 break;
6132 case 7:
6133 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6134 break;
6135 case 10:
6136 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6137 break;
6138 case 14:
6139 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6140 break;
6141 }
6142 if (INTEL_INFO(dev)->gen >= 4)
6143 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6144
6145 if (crtc->new_config->sdvo_tv_clock)
6146 dpll |= PLL_REF_INPUT_TVCLKINBC;
6147 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6148 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6149 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6150 else
6151 dpll |= PLL_REF_INPUT_DREFCLK;
6152
6153 dpll |= DPLL_VCO_ENABLE;
6154 crtc->new_config->dpll_hw_state.dpll = dpll;
6155
6156 if (INTEL_INFO(dev)->gen >= 4) {
6157 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6158 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6159 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6160 }
6161 }
6162
6163 static void i8xx_update_pll(struct intel_crtc *crtc,
6164 intel_clock_t *reduced_clock,
6165 int num_connectors)
6166 {
6167 struct drm_device *dev = crtc->base.dev;
6168 struct drm_i915_private *dev_priv = dev->dev_private;
6169 u32 dpll;
6170 struct dpll *clock = &crtc->new_config->dpll;
6171
6172 i9xx_update_pll_dividers(crtc, reduced_clock);
6173
6174 dpll = DPLL_VGA_MODE_DIS;
6175
6176 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6177 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6178 } else {
6179 if (clock->p1 == 2)
6180 dpll |= PLL_P1_DIVIDE_BY_TWO;
6181 else
6182 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6183 if (clock->p2 == 4)
6184 dpll |= PLL_P2_DIVIDE_BY_4;
6185 }
6186
6187 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6188 dpll |= DPLL_DVO_2X_MODE;
6189
6190 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6191 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6192 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6193 else
6194 dpll |= PLL_REF_INPUT_DREFCLK;
6195
6196 dpll |= DPLL_VCO_ENABLE;
6197 crtc->new_config->dpll_hw_state.dpll = dpll;
6198 }
6199
6200 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6201 {
6202 struct drm_device *dev = intel_crtc->base.dev;
6203 struct drm_i915_private *dev_priv = dev->dev_private;
6204 enum pipe pipe = intel_crtc->pipe;
6205 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6206 struct drm_display_mode *adjusted_mode =
6207 &intel_crtc->config.adjusted_mode;
6208 uint32_t crtc_vtotal, crtc_vblank_end;
6209 int vsyncshift = 0;
6210
6211 /* We need to be careful not to changed the adjusted mode, for otherwise
6212 * the hw state checker will get angry at the mismatch. */
6213 crtc_vtotal = adjusted_mode->crtc_vtotal;
6214 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6215
6216 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6217 /* the chip adds 2 halflines automatically */
6218 crtc_vtotal -= 1;
6219 crtc_vblank_end -= 1;
6220
6221 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6222 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6223 else
6224 vsyncshift = adjusted_mode->crtc_hsync_start -
6225 adjusted_mode->crtc_htotal / 2;
6226 if (vsyncshift < 0)
6227 vsyncshift += adjusted_mode->crtc_htotal;
6228 }
6229
6230 if (INTEL_INFO(dev)->gen > 3)
6231 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6232
6233 I915_WRITE(HTOTAL(cpu_transcoder),
6234 (adjusted_mode->crtc_hdisplay - 1) |
6235 ((adjusted_mode->crtc_htotal - 1) << 16));
6236 I915_WRITE(HBLANK(cpu_transcoder),
6237 (adjusted_mode->crtc_hblank_start - 1) |
6238 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6239 I915_WRITE(HSYNC(cpu_transcoder),
6240 (adjusted_mode->crtc_hsync_start - 1) |
6241 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6242
6243 I915_WRITE(VTOTAL(cpu_transcoder),
6244 (adjusted_mode->crtc_vdisplay - 1) |
6245 ((crtc_vtotal - 1) << 16));
6246 I915_WRITE(VBLANK(cpu_transcoder),
6247 (adjusted_mode->crtc_vblank_start - 1) |
6248 ((crtc_vblank_end - 1) << 16));
6249 I915_WRITE(VSYNC(cpu_transcoder),
6250 (adjusted_mode->crtc_vsync_start - 1) |
6251 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6252
6253 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6254 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6255 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6256 * bits. */
6257 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6258 (pipe == PIPE_B || pipe == PIPE_C))
6259 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6260
6261 /* pipesrc controls the size that is scaled from, which should
6262 * always be the user's requested size.
6263 */
6264 I915_WRITE(PIPESRC(pipe),
6265 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6266 (intel_crtc->config.pipe_src_h - 1));
6267 }
6268
6269 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6270 struct intel_crtc_config *pipe_config)
6271 {
6272 struct drm_device *dev = crtc->base.dev;
6273 struct drm_i915_private *dev_priv = dev->dev_private;
6274 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6275 uint32_t tmp;
6276
6277 tmp = I915_READ(HTOTAL(cpu_transcoder));
6278 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6279 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6280 tmp = I915_READ(HBLANK(cpu_transcoder));
6281 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6282 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6283 tmp = I915_READ(HSYNC(cpu_transcoder));
6284 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6285 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6286
6287 tmp = I915_READ(VTOTAL(cpu_transcoder));
6288 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6289 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6290 tmp = I915_READ(VBLANK(cpu_transcoder));
6291 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6292 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6293 tmp = I915_READ(VSYNC(cpu_transcoder));
6294 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6295 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6296
6297 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6298 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6299 pipe_config->adjusted_mode.crtc_vtotal += 1;
6300 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6301 }
6302
6303 tmp = I915_READ(PIPESRC(crtc->pipe));
6304 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6305 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6306
6307 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6308 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6309 }
6310
6311 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6312 struct intel_crtc_config *pipe_config)
6313 {
6314 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6315 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6316 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6317 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6318
6319 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6320 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6321 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6322 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6323
6324 mode->flags = pipe_config->adjusted_mode.flags;
6325
6326 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6327 mode->flags |= pipe_config->adjusted_mode.flags;
6328 }
6329
6330 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6331 {
6332 struct drm_device *dev = intel_crtc->base.dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334 uint32_t pipeconf;
6335
6336 pipeconf = 0;
6337
6338 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6339 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6340 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6341
6342 if (intel_crtc->config.double_wide)
6343 pipeconf |= PIPECONF_DOUBLE_WIDE;
6344
6345 /* only g4x and later have fancy bpc/dither controls */
6346 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6347 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6348 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6349 pipeconf |= PIPECONF_DITHER_EN |
6350 PIPECONF_DITHER_TYPE_SP;
6351
6352 switch (intel_crtc->config.pipe_bpp) {
6353 case 18:
6354 pipeconf |= PIPECONF_6BPC;
6355 break;
6356 case 24:
6357 pipeconf |= PIPECONF_8BPC;
6358 break;
6359 case 30:
6360 pipeconf |= PIPECONF_10BPC;
6361 break;
6362 default:
6363 /* Case prevented by intel_choose_pipe_bpp_dither. */
6364 BUG();
6365 }
6366 }
6367
6368 if (HAS_PIPE_CXSR(dev)) {
6369 if (intel_crtc->lowfreq_avail) {
6370 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6371 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6372 } else {
6373 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6374 }
6375 }
6376
6377 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6378 if (INTEL_INFO(dev)->gen < 4 ||
6379 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6380 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6381 else
6382 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6383 } else
6384 pipeconf |= PIPECONF_PROGRESSIVE;
6385
6386 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6387 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6388
6389 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6390 POSTING_READ(PIPECONF(intel_crtc->pipe));
6391 }
6392
6393 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6394 {
6395 struct drm_device *dev = crtc->base.dev;
6396 struct drm_i915_private *dev_priv = dev->dev_private;
6397 int refclk, num_connectors = 0;
6398 intel_clock_t clock, reduced_clock;
6399 bool ok, has_reduced_clock = false;
6400 bool is_lvds = false, is_dsi = false;
6401 struct intel_encoder *encoder;
6402 const intel_limit_t *limit;
6403
6404 for_each_intel_encoder(dev, encoder) {
6405 if (encoder->new_crtc != crtc)
6406 continue;
6407
6408 switch (encoder->type) {
6409 case INTEL_OUTPUT_LVDS:
6410 is_lvds = true;
6411 break;
6412 case INTEL_OUTPUT_DSI:
6413 is_dsi = true;
6414 break;
6415 default:
6416 break;
6417 }
6418
6419 num_connectors++;
6420 }
6421
6422 if (is_dsi)
6423 return 0;
6424
6425 if (!crtc->new_config->clock_set) {
6426 refclk = i9xx_get_refclk(crtc, num_connectors);
6427
6428 /*
6429 * Returns a set of divisors for the desired target clock with
6430 * the given refclk, or FALSE. The returned values represent
6431 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6432 * 2) / p1 / p2.
6433 */
6434 limit = intel_limit(crtc, refclk);
6435 ok = dev_priv->display.find_dpll(limit, crtc,
6436 crtc->new_config->port_clock,
6437 refclk, NULL, &clock);
6438 if (!ok) {
6439 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6440 return -EINVAL;
6441 }
6442
6443 if (is_lvds && dev_priv->lvds_downclock_avail) {
6444 /*
6445 * Ensure we match the reduced clock's P to the target
6446 * clock. If the clocks don't match, we can't switch
6447 * the display clock by using the FP0/FP1. In such case
6448 * we will disable the LVDS downclock feature.
6449 */
6450 has_reduced_clock =
6451 dev_priv->display.find_dpll(limit, crtc,
6452 dev_priv->lvds_downclock,
6453 refclk, &clock,
6454 &reduced_clock);
6455 }
6456 /* Compat-code for transition, will disappear. */
6457 crtc->new_config->dpll.n = clock.n;
6458 crtc->new_config->dpll.m1 = clock.m1;
6459 crtc->new_config->dpll.m2 = clock.m2;
6460 crtc->new_config->dpll.p1 = clock.p1;
6461 crtc->new_config->dpll.p2 = clock.p2;
6462 }
6463
6464 if (IS_GEN2(dev)) {
6465 i8xx_update_pll(crtc,
6466 has_reduced_clock ? &reduced_clock : NULL,
6467 num_connectors);
6468 } else if (IS_CHERRYVIEW(dev)) {
6469 chv_update_pll(crtc, crtc->new_config);
6470 } else if (IS_VALLEYVIEW(dev)) {
6471 vlv_update_pll(crtc, crtc->new_config);
6472 } else {
6473 i9xx_update_pll(crtc,
6474 has_reduced_clock ? &reduced_clock : NULL,
6475 num_connectors);
6476 }
6477
6478 return 0;
6479 }
6480
6481 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6482 struct intel_crtc_config *pipe_config)
6483 {
6484 struct drm_device *dev = crtc->base.dev;
6485 struct drm_i915_private *dev_priv = dev->dev_private;
6486 uint32_t tmp;
6487
6488 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6489 return;
6490
6491 tmp = I915_READ(PFIT_CONTROL);
6492 if (!(tmp & PFIT_ENABLE))
6493 return;
6494
6495 /* Check whether the pfit is attached to our pipe. */
6496 if (INTEL_INFO(dev)->gen < 4) {
6497 if (crtc->pipe != PIPE_B)
6498 return;
6499 } else {
6500 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6501 return;
6502 }
6503
6504 pipe_config->gmch_pfit.control = tmp;
6505 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6506 if (INTEL_INFO(dev)->gen < 5)
6507 pipe_config->gmch_pfit.lvds_border_bits =
6508 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6509 }
6510
6511 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6512 struct intel_crtc_config *pipe_config)
6513 {
6514 struct drm_device *dev = crtc->base.dev;
6515 struct drm_i915_private *dev_priv = dev->dev_private;
6516 int pipe = pipe_config->cpu_transcoder;
6517 intel_clock_t clock;
6518 u32 mdiv;
6519 int refclk = 100000;
6520
6521 /* In case of MIPI DPLL will not even be used */
6522 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6523 return;
6524
6525 mutex_lock(&dev_priv->dpio_lock);
6526 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6527 mutex_unlock(&dev_priv->dpio_lock);
6528
6529 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6530 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6531 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6532 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6533 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6534
6535 vlv_clock(refclk, &clock);
6536
6537 /* clock.dot is the fast clock */
6538 pipe_config->port_clock = clock.dot / 5;
6539 }
6540
6541 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6542 struct intel_plane_config *plane_config)
6543 {
6544 struct drm_device *dev = crtc->base.dev;
6545 struct drm_i915_private *dev_priv = dev->dev_private;
6546 u32 val, base, offset;
6547 int pipe = crtc->pipe, plane = crtc->plane;
6548 int fourcc, pixel_format;
6549 int aligned_height;
6550
6551 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6552 if (!crtc->base.primary->fb) {
6553 DRM_DEBUG_KMS("failed to alloc fb\n");
6554 return;
6555 }
6556
6557 val = I915_READ(DSPCNTR(plane));
6558
6559 if (INTEL_INFO(dev)->gen >= 4)
6560 if (val & DISPPLANE_TILED)
6561 plane_config->tiled = true;
6562
6563 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6564 fourcc = intel_format_to_fourcc(pixel_format);
6565 crtc->base.primary->fb->pixel_format = fourcc;
6566 crtc->base.primary->fb->bits_per_pixel =
6567 drm_format_plane_cpp(fourcc, 0) * 8;
6568
6569 if (INTEL_INFO(dev)->gen >= 4) {
6570 if (plane_config->tiled)
6571 offset = I915_READ(DSPTILEOFF(plane));
6572 else
6573 offset = I915_READ(DSPLINOFF(plane));
6574 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6575 } else {
6576 base = I915_READ(DSPADDR(plane));
6577 }
6578 plane_config->base = base;
6579
6580 val = I915_READ(PIPESRC(pipe));
6581 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6582 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6583
6584 val = I915_READ(DSPSTRIDE(pipe));
6585 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6586
6587 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6588 plane_config->tiled);
6589
6590 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6591 aligned_height);
6592
6593 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6594 pipe, plane, crtc->base.primary->fb->width,
6595 crtc->base.primary->fb->height,
6596 crtc->base.primary->fb->bits_per_pixel, base,
6597 crtc->base.primary->fb->pitches[0],
6598 plane_config->size);
6599
6600 }
6601
6602 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6603 struct intel_crtc_config *pipe_config)
6604 {
6605 struct drm_device *dev = crtc->base.dev;
6606 struct drm_i915_private *dev_priv = dev->dev_private;
6607 int pipe = pipe_config->cpu_transcoder;
6608 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6609 intel_clock_t clock;
6610 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6611 int refclk = 100000;
6612
6613 mutex_lock(&dev_priv->dpio_lock);
6614 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6615 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6616 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6617 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6618 mutex_unlock(&dev_priv->dpio_lock);
6619
6620 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6621 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6622 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6623 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6624 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6625
6626 chv_clock(refclk, &clock);
6627
6628 /* clock.dot is the fast clock */
6629 pipe_config->port_clock = clock.dot / 5;
6630 }
6631
6632 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6633 struct intel_crtc_config *pipe_config)
6634 {
6635 struct drm_device *dev = crtc->base.dev;
6636 struct drm_i915_private *dev_priv = dev->dev_private;
6637 uint32_t tmp;
6638
6639 if (!intel_display_power_is_enabled(dev_priv,
6640 POWER_DOMAIN_PIPE(crtc->pipe)))
6641 return false;
6642
6643 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6644 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6645
6646 tmp = I915_READ(PIPECONF(crtc->pipe));
6647 if (!(tmp & PIPECONF_ENABLE))
6648 return false;
6649
6650 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6651 switch (tmp & PIPECONF_BPC_MASK) {
6652 case PIPECONF_6BPC:
6653 pipe_config->pipe_bpp = 18;
6654 break;
6655 case PIPECONF_8BPC:
6656 pipe_config->pipe_bpp = 24;
6657 break;
6658 case PIPECONF_10BPC:
6659 pipe_config->pipe_bpp = 30;
6660 break;
6661 default:
6662 break;
6663 }
6664 }
6665
6666 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6667 pipe_config->limited_color_range = true;
6668
6669 if (INTEL_INFO(dev)->gen < 4)
6670 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6671
6672 intel_get_pipe_timings(crtc, pipe_config);
6673
6674 i9xx_get_pfit_config(crtc, pipe_config);
6675
6676 if (INTEL_INFO(dev)->gen >= 4) {
6677 tmp = I915_READ(DPLL_MD(crtc->pipe));
6678 pipe_config->pixel_multiplier =
6679 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6680 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6681 pipe_config->dpll_hw_state.dpll_md = tmp;
6682 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6683 tmp = I915_READ(DPLL(crtc->pipe));
6684 pipe_config->pixel_multiplier =
6685 ((tmp & SDVO_MULTIPLIER_MASK)
6686 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6687 } else {
6688 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6689 * port and will be fixed up in the encoder->get_config
6690 * function. */
6691 pipe_config->pixel_multiplier = 1;
6692 }
6693 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6694 if (!IS_VALLEYVIEW(dev)) {
6695 /*
6696 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6697 * on 830. Filter it out here so that we don't
6698 * report errors due to that.
6699 */
6700 if (IS_I830(dev))
6701 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6702
6703 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6704 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6705 } else {
6706 /* Mask out read-only status bits. */
6707 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6708 DPLL_PORTC_READY_MASK |
6709 DPLL_PORTB_READY_MASK);
6710 }
6711
6712 if (IS_CHERRYVIEW(dev))
6713 chv_crtc_clock_get(crtc, pipe_config);
6714 else if (IS_VALLEYVIEW(dev))
6715 vlv_crtc_clock_get(crtc, pipe_config);
6716 else
6717 i9xx_crtc_clock_get(crtc, pipe_config);
6718
6719 return true;
6720 }
6721
6722 static void ironlake_init_pch_refclk(struct drm_device *dev)
6723 {
6724 struct drm_i915_private *dev_priv = dev->dev_private;
6725 struct intel_encoder *encoder;
6726 u32 val, final;
6727 bool has_lvds = false;
6728 bool has_cpu_edp = false;
6729 bool has_panel = false;
6730 bool has_ck505 = false;
6731 bool can_ssc = false;
6732
6733 /* We need to take the global config into account */
6734 for_each_intel_encoder(dev, encoder) {
6735 switch (encoder->type) {
6736 case INTEL_OUTPUT_LVDS:
6737 has_panel = true;
6738 has_lvds = true;
6739 break;
6740 case INTEL_OUTPUT_EDP:
6741 has_panel = true;
6742 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6743 has_cpu_edp = true;
6744 break;
6745 default:
6746 break;
6747 }
6748 }
6749
6750 if (HAS_PCH_IBX(dev)) {
6751 has_ck505 = dev_priv->vbt.display_clock_mode;
6752 can_ssc = has_ck505;
6753 } else {
6754 has_ck505 = false;
6755 can_ssc = true;
6756 }
6757
6758 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6759 has_panel, has_lvds, has_ck505);
6760
6761 /* Ironlake: try to setup display ref clock before DPLL
6762 * enabling. This is only under driver's control after
6763 * PCH B stepping, previous chipset stepping should be
6764 * ignoring this setting.
6765 */
6766 val = I915_READ(PCH_DREF_CONTROL);
6767
6768 /* As we must carefully and slowly disable/enable each source in turn,
6769 * compute the final state we want first and check if we need to
6770 * make any changes at all.
6771 */
6772 final = val;
6773 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6774 if (has_ck505)
6775 final |= DREF_NONSPREAD_CK505_ENABLE;
6776 else
6777 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6778
6779 final &= ~DREF_SSC_SOURCE_MASK;
6780 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6781 final &= ~DREF_SSC1_ENABLE;
6782
6783 if (has_panel) {
6784 final |= DREF_SSC_SOURCE_ENABLE;
6785
6786 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6787 final |= DREF_SSC1_ENABLE;
6788
6789 if (has_cpu_edp) {
6790 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6791 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6792 else
6793 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6794 } else
6795 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6796 } else {
6797 final |= DREF_SSC_SOURCE_DISABLE;
6798 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6799 }
6800
6801 if (final == val)
6802 return;
6803
6804 /* Always enable nonspread source */
6805 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6806
6807 if (has_ck505)
6808 val |= DREF_NONSPREAD_CK505_ENABLE;
6809 else
6810 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6811
6812 if (has_panel) {
6813 val &= ~DREF_SSC_SOURCE_MASK;
6814 val |= DREF_SSC_SOURCE_ENABLE;
6815
6816 /* SSC must be turned on before enabling the CPU output */
6817 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6818 DRM_DEBUG_KMS("Using SSC on panel\n");
6819 val |= DREF_SSC1_ENABLE;
6820 } else
6821 val &= ~DREF_SSC1_ENABLE;
6822
6823 /* Get SSC going before enabling the outputs */
6824 I915_WRITE(PCH_DREF_CONTROL, val);
6825 POSTING_READ(PCH_DREF_CONTROL);
6826 udelay(200);
6827
6828 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6829
6830 /* Enable CPU source on CPU attached eDP */
6831 if (has_cpu_edp) {
6832 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6833 DRM_DEBUG_KMS("Using SSC on eDP\n");
6834 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6835 } else
6836 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6837 } else
6838 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6839
6840 I915_WRITE(PCH_DREF_CONTROL, val);
6841 POSTING_READ(PCH_DREF_CONTROL);
6842 udelay(200);
6843 } else {
6844 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6845
6846 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6847
6848 /* Turn off CPU output */
6849 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6850
6851 I915_WRITE(PCH_DREF_CONTROL, val);
6852 POSTING_READ(PCH_DREF_CONTROL);
6853 udelay(200);
6854
6855 /* Turn off the SSC source */
6856 val &= ~DREF_SSC_SOURCE_MASK;
6857 val |= DREF_SSC_SOURCE_DISABLE;
6858
6859 /* Turn off SSC1 */
6860 val &= ~DREF_SSC1_ENABLE;
6861
6862 I915_WRITE(PCH_DREF_CONTROL, val);
6863 POSTING_READ(PCH_DREF_CONTROL);
6864 udelay(200);
6865 }
6866
6867 BUG_ON(val != final);
6868 }
6869
6870 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6871 {
6872 uint32_t tmp;
6873
6874 tmp = I915_READ(SOUTH_CHICKEN2);
6875 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6876 I915_WRITE(SOUTH_CHICKEN2, tmp);
6877
6878 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6879 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6880 DRM_ERROR("FDI mPHY reset assert timeout\n");
6881
6882 tmp = I915_READ(SOUTH_CHICKEN2);
6883 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6884 I915_WRITE(SOUTH_CHICKEN2, tmp);
6885
6886 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6887 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6888 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6889 }
6890
6891 /* WaMPhyProgramming:hsw */
6892 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6893 {
6894 uint32_t tmp;
6895
6896 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6897 tmp &= ~(0xFF << 24);
6898 tmp |= (0x12 << 24);
6899 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6900
6901 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6902 tmp |= (1 << 11);
6903 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6904
6905 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6906 tmp |= (1 << 11);
6907 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6908
6909 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6910 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6911 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6912
6913 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6914 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6915 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6916
6917 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6918 tmp &= ~(7 << 13);
6919 tmp |= (5 << 13);
6920 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6921
6922 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6923 tmp &= ~(7 << 13);
6924 tmp |= (5 << 13);
6925 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6926
6927 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6928 tmp &= ~0xFF;
6929 tmp |= 0x1C;
6930 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6931
6932 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6933 tmp &= ~0xFF;
6934 tmp |= 0x1C;
6935 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6936
6937 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6938 tmp &= ~(0xFF << 16);
6939 tmp |= (0x1C << 16);
6940 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6941
6942 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6943 tmp &= ~(0xFF << 16);
6944 tmp |= (0x1C << 16);
6945 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6946
6947 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6948 tmp |= (1 << 27);
6949 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6950
6951 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6952 tmp |= (1 << 27);
6953 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6954
6955 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6956 tmp &= ~(0xF << 28);
6957 tmp |= (4 << 28);
6958 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6959
6960 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6961 tmp &= ~(0xF << 28);
6962 tmp |= (4 << 28);
6963 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6964 }
6965
6966 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6967 * Programming" based on the parameters passed:
6968 * - Sequence to enable CLKOUT_DP
6969 * - Sequence to enable CLKOUT_DP without spread
6970 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6971 */
6972 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6973 bool with_fdi)
6974 {
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6976 uint32_t reg, tmp;
6977
6978 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6979 with_spread = true;
6980 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6981 with_fdi, "LP PCH doesn't have FDI\n"))
6982 with_fdi = false;
6983
6984 mutex_lock(&dev_priv->dpio_lock);
6985
6986 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6987 tmp &= ~SBI_SSCCTL_DISABLE;
6988 tmp |= SBI_SSCCTL_PATHALT;
6989 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6990
6991 udelay(24);
6992
6993 if (with_spread) {
6994 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6995 tmp &= ~SBI_SSCCTL_PATHALT;
6996 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6997
6998 if (with_fdi) {
6999 lpt_reset_fdi_mphy(dev_priv);
7000 lpt_program_fdi_mphy(dev_priv);
7001 }
7002 }
7003
7004 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7005 SBI_GEN0 : SBI_DBUFF0;
7006 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7007 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7008 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7009
7010 mutex_unlock(&dev_priv->dpio_lock);
7011 }
7012
7013 /* Sequence to disable CLKOUT_DP */
7014 static void lpt_disable_clkout_dp(struct drm_device *dev)
7015 {
7016 struct drm_i915_private *dev_priv = dev->dev_private;
7017 uint32_t reg, tmp;
7018
7019 mutex_lock(&dev_priv->dpio_lock);
7020
7021 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7022 SBI_GEN0 : SBI_DBUFF0;
7023 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7024 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7025 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7026
7027 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7028 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7029 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7030 tmp |= SBI_SSCCTL_PATHALT;
7031 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7032 udelay(32);
7033 }
7034 tmp |= SBI_SSCCTL_DISABLE;
7035 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7036 }
7037
7038 mutex_unlock(&dev_priv->dpio_lock);
7039 }
7040
7041 static void lpt_init_pch_refclk(struct drm_device *dev)
7042 {
7043 struct intel_encoder *encoder;
7044 bool has_vga = false;
7045
7046 for_each_intel_encoder(dev, encoder) {
7047 switch (encoder->type) {
7048 case INTEL_OUTPUT_ANALOG:
7049 has_vga = true;
7050 break;
7051 default:
7052 break;
7053 }
7054 }
7055
7056 if (has_vga)
7057 lpt_enable_clkout_dp(dev, true, true);
7058 else
7059 lpt_disable_clkout_dp(dev);
7060 }
7061
7062 /*
7063 * Initialize reference clocks when the driver loads
7064 */
7065 void intel_init_pch_refclk(struct drm_device *dev)
7066 {
7067 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7068 ironlake_init_pch_refclk(dev);
7069 else if (HAS_PCH_LPT(dev))
7070 lpt_init_pch_refclk(dev);
7071 }
7072
7073 static int ironlake_get_refclk(struct drm_crtc *crtc)
7074 {
7075 struct drm_device *dev = crtc->dev;
7076 struct drm_i915_private *dev_priv = dev->dev_private;
7077 struct intel_encoder *encoder;
7078 int num_connectors = 0;
7079 bool is_lvds = false;
7080
7081 for_each_intel_encoder(dev, encoder) {
7082 if (encoder->new_crtc != to_intel_crtc(crtc))
7083 continue;
7084
7085 switch (encoder->type) {
7086 case INTEL_OUTPUT_LVDS:
7087 is_lvds = true;
7088 break;
7089 default:
7090 break;
7091 }
7092 num_connectors++;
7093 }
7094
7095 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7096 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7097 dev_priv->vbt.lvds_ssc_freq);
7098 return dev_priv->vbt.lvds_ssc_freq;
7099 }
7100
7101 return 120000;
7102 }
7103
7104 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7105 {
7106 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7108 int pipe = intel_crtc->pipe;
7109 uint32_t val;
7110
7111 val = 0;
7112
7113 switch (intel_crtc->config.pipe_bpp) {
7114 case 18:
7115 val |= PIPECONF_6BPC;
7116 break;
7117 case 24:
7118 val |= PIPECONF_8BPC;
7119 break;
7120 case 30:
7121 val |= PIPECONF_10BPC;
7122 break;
7123 case 36:
7124 val |= PIPECONF_12BPC;
7125 break;
7126 default:
7127 /* Case prevented by intel_choose_pipe_bpp_dither. */
7128 BUG();
7129 }
7130
7131 if (intel_crtc->config.dither)
7132 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7133
7134 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7135 val |= PIPECONF_INTERLACED_ILK;
7136 else
7137 val |= PIPECONF_PROGRESSIVE;
7138
7139 if (intel_crtc->config.limited_color_range)
7140 val |= PIPECONF_COLOR_RANGE_SELECT;
7141
7142 I915_WRITE(PIPECONF(pipe), val);
7143 POSTING_READ(PIPECONF(pipe));
7144 }
7145
7146 /*
7147 * Set up the pipe CSC unit.
7148 *
7149 * Currently only full range RGB to limited range RGB conversion
7150 * is supported, but eventually this should handle various
7151 * RGB<->YCbCr scenarios as well.
7152 */
7153 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7154 {
7155 struct drm_device *dev = crtc->dev;
7156 struct drm_i915_private *dev_priv = dev->dev_private;
7157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7158 int pipe = intel_crtc->pipe;
7159 uint16_t coeff = 0x7800; /* 1.0 */
7160
7161 /*
7162 * TODO: Check what kind of values actually come out of the pipe
7163 * with these coeff/postoff values and adjust to get the best
7164 * accuracy. Perhaps we even need to take the bpc value into
7165 * consideration.
7166 */
7167
7168 if (intel_crtc->config.limited_color_range)
7169 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7170
7171 /*
7172 * GY/GU and RY/RU should be the other way around according
7173 * to BSpec, but reality doesn't agree. Just set them up in
7174 * a way that results in the correct picture.
7175 */
7176 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7177 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7178
7179 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7180 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7181
7182 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7183 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7184
7185 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7186 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7187 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7188
7189 if (INTEL_INFO(dev)->gen > 6) {
7190 uint16_t postoff = 0;
7191
7192 if (intel_crtc->config.limited_color_range)
7193 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7194
7195 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7196 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7197 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7198
7199 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7200 } else {
7201 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7202
7203 if (intel_crtc->config.limited_color_range)
7204 mode |= CSC_BLACK_SCREEN_OFFSET;
7205
7206 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7207 }
7208 }
7209
7210 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7211 {
7212 struct drm_device *dev = crtc->dev;
7213 struct drm_i915_private *dev_priv = dev->dev_private;
7214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7215 enum pipe pipe = intel_crtc->pipe;
7216 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7217 uint32_t val;
7218
7219 val = 0;
7220
7221 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7222 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7223
7224 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7225 val |= PIPECONF_INTERLACED_ILK;
7226 else
7227 val |= PIPECONF_PROGRESSIVE;
7228
7229 I915_WRITE(PIPECONF(cpu_transcoder), val);
7230 POSTING_READ(PIPECONF(cpu_transcoder));
7231
7232 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7233 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7234
7235 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7236 val = 0;
7237
7238 switch (intel_crtc->config.pipe_bpp) {
7239 case 18:
7240 val |= PIPEMISC_DITHER_6_BPC;
7241 break;
7242 case 24:
7243 val |= PIPEMISC_DITHER_8_BPC;
7244 break;
7245 case 30:
7246 val |= PIPEMISC_DITHER_10_BPC;
7247 break;
7248 case 36:
7249 val |= PIPEMISC_DITHER_12_BPC;
7250 break;
7251 default:
7252 /* Case prevented by pipe_config_set_bpp. */
7253 BUG();
7254 }
7255
7256 if (intel_crtc->config.dither)
7257 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7258
7259 I915_WRITE(PIPEMISC(pipe), val);
7260 }
7261 }
7262
7263 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7264 intel_clock_t *clock,
7265 bool *has_reduced_clock,
7266 intel_clock_t *reduced_clock)
7267 {
7268 struct drm_device *dev = crtc->dev;
7269 struct drm_i915_private *dev_priv = dev->dev_private;
7270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7271 int refclk;
7272 const intel_limit_t *limit;
7273 bool ret, is_lvds = false;
7274
7275 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7276
7277 refclk = ironlake_get_refclk(crtc);
7278
7279 /*
7280 * Returns a set of divisors for the desired target clock with the given
7281 * refclk, or FALSE. The returned values represent the clock equation:
7282 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7283 */
7284 limit = intel_limit(intel_crtc, refclk);
7285 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7286 intel_crtc->new_config->port_clock,
7287 refclk, NULL, clock);
7288 if (!ret)
7289 return false;
7290
7291 if (is_lvds && dev_priv->lvds_downclock_avail) {
7292 /*
7293 * Ensure we match the reduced clock's P to the target clock.
7294 * If the clocks don't match, we can't switch the display clock
7295 * by using the FP0/FP1. In such case we will disable the LVDS
7296 * downclock feature.
7297 */
7298 *has_reduced_clock =
7299 dev_priv->display.find_dpll(limit, intel_crtc,
7300 dev_priv->lvds_downclock,
7301 refclk, clock,
7302 reduced_clock);
7303 }
7304
7305 return true;
7306 }
7307
7308 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7309 {
7310 /*
7311 * Account for spread spectrum to avoid
7312 * oversubscribing the link. Max center spread
7313 * is 2.5%; use 5% for safety's sake.
7314 */
7315 u32 bps = target_clock * bpp * 21 / 20;
7316 return DIV_ROUND_UP(bps, link_bw * 8);
7317 }
7318
7319 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7320 {
7321 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7322 }
7323
7324 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7325 u32 *fp,
7326 intel_clock_t *reduced_clock, u32 *fp2)
7327 {
7328 struct drm_crtc *crtc = &intel_crtc->base;
7329 struct drm_device *dev = crtc->dev;
7330 struct drm_i915_private *dev_priv = dev->dev_private;
7331 struct intel_encoder *intel_encoder;
7332 uint32_t dpll;
7333 int factor, num_connectors = 0;
7334 bool is_lvds = false, is_sdvo = false;
7335
7336 for_each_intel_encoder(dev, intel_encoder) {
7337 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7338 continue;
7339
7340 switch (intel_encoder->type) {
7341 case INTEL_OUTPUT_LVDS:
7342 is_lvds = true;
7343 break;
7344 case INTEL_OUTPUT_SDVO:
7345 case INTEL_OUTPUT_HDMI:
7346 is_sdvo = true;
7347 break;
7348 default:
7349 break;
7350 }
7351
7352 num_connectors++;
7353 }
7354
7355 /* Enable autotuning of the PLL clock (if permissible) */
7356 factor = 21;
7357 if (is_lvds) {
7358 if ((intel_panel_use_ssc(dev_priv) &&
7359 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7360 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7361 factor = 25;
7362 } else if (intel_crtc->new_config->sdvo_tv_clock)
7363 factor = 20;
7364
7365 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7366 *fp |= FP_CB_TUNE;
7367
7368 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7369 *fp2 |= FP_CB_TUNE;
7370
7371 dpll = 0;
7372
7373 if (is_lvds)
7374 dpll |= DPLLB_MODE_LVDS;
7375 else
7376 dpll |= DPLLB_MODE_DAC_SERIAL;
7377
7378 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7379 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7380
7381 if (is_sdvo)
7382 dpll |= DPLL_SDVO_HIGH_SPEED;
7383 if (intel_crtc->new_config->has_dp_encoder)
7384 dpll |= DPLL_SDVO_HIGH_SPEED;
7385
7386 /* compute bitmask from p1 value */
7387 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7388 /* also FPA1 */
7389 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7390
7391 switch (intel_crtc->new_config->dpll.p2) {
7392 case 5:
7393 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7394 break;
7395 case 7:
7396 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7397 break;
7398 case 10:
7399 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7400 break;
7401 case 14:
7402 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7403 break;
7404 }
7405
7406 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7407 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7408 else
7409 dpll |= PLL_REF_INPUT_DREFCLK;
7410
7411 return dpll | DPLL_VCO_ENABLE;
7412 }
7413
7414 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7415 {
7416 struct drm_device *dev = crtc->base.dev;
7417 intel_clock_t clock, reduced_clock;
7418 u32 dpll = 0, fp = 0, fp2 = 0;
7419 bool ok, has_reduced_clock = false;
7420 bool is_lvds = false;
7421 struct intel_shared_dpll *pll;
7422
7423 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7424
7425 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7426 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7427
7428 ok = ironlake_compute_clocks(&crtc->base, &clock,
7429 &has_reduced_clock, &reduced_clock);
7430 if (!ok && !crtc->new_config->clock_set) {
7431 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7432 return -EINVAL;
7433 }
7434 /* Compat-code for transition, will disappear. */
7435 if (!crtc->new_config->clock_set) {
7436 crtc->new_config->dpll.n = clock.n;
7437 crtc->new_config->dpll.m1 = clock.m1;
7438 crtc->new_config->dpll.m2 = clock.m2;
7439 crtc->new_config->dpll.p1 = clock.p1;
7440 crtc->new_config->dpll.p2 = clock.p2;
7441 }
7442
7443 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7444 if (crtc->new_config->has_pch_encoder) {
7445 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7446 if (has_reduced_clock)
7447 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7448
7449 dpll = ironlake_compute_dpll(crtc,
7450 &fp, &reduced_clock,
7451 has_reduced_clock ? &fp2 : NULL);
7452
7453 crtc->new_config->dpll_hw_state.dpll = dpll;
7454 crtc->new_config->dpll_hw_state.fp0 = fp;
7455 if (has_reduced_clock)
7456 crtc->new_config->dpll_hw_state.fp1 = fp2;
7457 else
7458 crtc->new_config->dpll_hw_state.fp1 = fp;
7459
7460 pll = intel_get_shared_dpll(crtc);
7461 if (pll == NULL) {
7462 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7463 pipe_name(crtc->pipe));
7464 return -EINVAL;
7465 }
7466 }
7467
7468 if (is_lvds && has_reduced_clock && i915.powersave)
7469 crtc->lowfreq_avail = true;
7470 else
7471 crtc->lowfreq_avail = false;
7472
7473 return 0;
7474 }
7475
7476 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7477 struct intel_link_m_n *m_n)
7478 {
7479 struct drm_device *dev = crtc->base.dev;
7480 struct drm_i915_private *dev_priv = dev->dev_private;
7481 enum pipe pipe = crtc->pipe;
7482
7483 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7484 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7485 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7486 & ~TU_SIZE_MASK;
7487 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7488 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7489 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7490 }
7491
7492 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7493 enum transcoder transcoder,
7494 struct intel_link_m_n *m_n,
7495 struct intel_link_m_n *m2_n2)
7496 {
7497 struct drm_device *dev = crtc->base.dev;
7498 struct drm_i915_private *dev_priv = dev->dev_private;
7499 enum pipe pipe = crtc->pipe;
7500
7501 if (INTEL_INFO(dev)->gen >= 5) {
7502 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7503 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7504 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7505 & ~TU_SIZE_MASK;
7506 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7507 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7508 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7509 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7510 * gen < 8) and if DRRS is supported (to make sure the
7511 * registers are not unnecessarily read).
7512 */
7513 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7514 crtc->config.has_drrs) {
7515 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7516 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7517 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7518 & ~TU_SIZE_MASK;
7519 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7520 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7521 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7522 }
7523 } else {
7524 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7525 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7526 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7527 & ~TU_SIZE_MASK;
7528 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7529 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7530 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7531 }
7532 }
7533
7534 void intel_dp_get_m_n(struct intel_crtc *crtc,
7535 struct intel_crtc_config *pipe_config)
7536 {
7537 if (crtc->config.has_pch_encoder)
7538 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7539 else
7540 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7541 &pipe_config->dp_m_n,
7542 &pipe_config->dp_m2_n2);
7543 }
7544
7545 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7546 struct intel_crtc_config *pipe_config)
7547 {
7548 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7549 &pipe_config->fdi_m_n, NULL);
7550 }
7551
7552 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7553 struct intel_crtc_config *pipe_config)
7554 {
7555 struct drm_device *dev = crtc->base.dev;
7556 struct drm_i915_private *dev_priv = dev->dev_private;
7557 uint32_t tmp;
7558
7559 tmp = I915_READ(PF_CTL(crtc->pipe));
7560
7561 if (tmp & PF_ENABLE) {
7562 pipe_config->pch_pfit.enabled = true;
7563 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7564 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7565
7566 /* We currently do not free assignements of panel fitters on
7567 * ivb/hsw (since we don't use the higher upscaling modes which
7568 * differentiates them) so just WARN about this case for now. */
7569 if (IS_GEN7(dev)) {
7570 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7571 PF_PIPE_SEL_IVB(crtc->pipe));
7572 }
7573 }
7574 }
7575
7576 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7577 struct intel_plane_config *plane_config)
7578 {
7579 struct drm_device *dev = crtc->base.dev;
7580 struct drm_i915_private *dev_priv = dev->dev_private;
7581 u32 val, base, offset;
7582 int pipe = crtc->pipe, plane = crtc->plane;
7583 int fourcc, pixel_format;
7584 int aligned_height;
7585
7586 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7587 if (!crtc->base.primary->fb) {
7588 DRM_DEBUG_KMS("failed to alloc fb\n");
7589 return;
7590 }
7591
7592 val = I915_READ(DSPCNTR(plane));
7593
7594 if (INTEL_INFO(dev)->gen >= 4)
7595 if (val & DISPPLANE_TILED)
7596 plane_config->tiled = true;
7597
7598 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7599 fourcc = intel_format_to_fourcc(pixel_format);
7600 crtc->base.primary->fb->pixel_format = fourcc;
7601 crtc->base.primary->fb->bits_per_pixel =
7602 drm_format_plane_cpp(fourcc, 0) * 8;
7603
7604 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7605 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7606 offset = I915_READ(DSPOFFSET(plane));
7607 } else {
7608 if (plane_config->tiled)
7609 offset = I915_READ(DSPTILEOFF(plane));
7610 else
7611 offset = I915_READ(DSPLINOFF(plane));
7612 }
7613 plane_config->base = base;
7614
7615 val = I915_READ(PIPESRC(pipe));
7616 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7617 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7618
7619 val = I915_READ(DSPSTRIDE(pipe));
7620 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7621
7622 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7623 plane_config->tiled);
7624
7625 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7626 aligned_height);
7627
7628 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7629 pipe, plane, crtc->base.primary->fb->width,
7630 crtc->base.primary->fb->height,
7631 crtc->base.primary->fb->bits_per_pixel, base,
7632 crtc->base.primary->fb->pitches[0],
7633 plane_config->size);
7634 }
7635
7636 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7637 struct intel_crtc_config *pipe_config)
7638 {
7639 struct drm_device *dev = crtc->base.dev;
7640 struct drm_i915_private *dev_priv = dev->dev_private;
7641 uint32_t tmp;
7642
7643 if (!intel_display_power_is_enabled(dev_priv,
7644 POWER_DOMAIN_PIPE(crtc->pipe)))
7645 return false;
7646
7647 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7648 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7649
7650 tmp = I915_READ(PIPECONF(crtc->pipe));
7651 if (!(tmp & PIPECONF_ENABLE))
7652 return false;
7653
7654 switch (tmp & PIPECONF_BPC_MASK) {
7655 case PIPECONF_6BPC:
7656 pipe_config->pipe_bpp = 18;
7657 break;
7658 case PIPECONF_8BPC:
7659 pipe_config->pipe_bpp = 24;
7660 break;
7661 case PIPECONF_10BPC:
7662 pipe_config->pipe_bpp = 30;
7663 break;
7664 case PIPECONF_12BPC:
7665 pipe_config->pipe_bpp = 36;
7666 break;
7667 default:
7668 break;
7669 }
7670
7671 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7672 pipe_config->limited_color_range = true;
7673
7674 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7675 struct intel_shared_dpll *pll;
7676
7677 pipe_config->has_pch_encoder = true;
7678
7679 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7680 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7681 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7682
7683 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7684
7685 if (HAS_PCH_IBX(dev_priv->dev)) {
7686 pipe_config->shared_dpll =
7687 (enum intel_dpll_id) crtc->pipe;
7688 } else {
7689 tmp = I915_READ(PCH_DPLL_SEL);
7690 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7691 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7692 else
7693 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7694 }
7695
7696 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7697
7698 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7699 &pipe_config->dpll_hw_state));
7700
7701 tmp = pipe_config->dpll_hw_state.dpll;
7702 pipe_config->pixel_multiplier =
7703 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7704 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7705
7706 ironlake_pch_clock_get(crtc, pipe_config);
7707 } else {
7708 pipe_config->pixel_multiplier = 1;
7709 }
7710
7711 intel_get_pipe_timings(crtc, pipe_config);
7712
7713 ironlake_get_pfit_config(crtc, pipe_config);
7714
7715 return true;
7716 }
7717
7718 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7719 {
7720 struct drm_device *dev = dev_priv->dev;
7721 struct intel_crtc *crtc;
7722
7723 for_each_intel_crtc(dev, crtc)
7724 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7725 pipe_name(crtc->pipe));
7726
7727 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7728 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7729 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7730 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7731 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7732 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7733 "CPU PWM1 enabled\n");
7734 if (IS_HASWELL(dev))
7735 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7736 "CPU PWM2 enabled\n");
7737 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7738 "PCH PWM1 enabled\n");
7739 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7740 "Utility pin enabled\n");
7741 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7742
7743 /*
7744 * In theory we can still leave IRQs enabled, as long as only the HPD
7745 * interrupts remain enabled. We used to check for that, but since it's
7746 * gen-specific and since we only disable LCPLL after we fully disable
7747 * the interrupts, the check below should be enough.
7748 */
7749 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7750 }
7751
7752 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7753 {
7754 struct drm_device *dev = dev_priv->dev;
7755
7756 if (IS_HASWELL(dev))
7757 return I915_READ(D_COMP_HSW);
7758 else
7759 return I915_READ(D_COMP_BDW);
7760 }
7761
7762 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7763 {
7764 struct drm_device *dev = dev_priv->dev;
7765
7766 if (IS_HASWELL(dev)) {
7767 mutex_lock(&dev_priv->rps.hw_lock);
7768 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7769 val))
7770 DRM_ERROR("Failed to write to D_COMP\n");
7771 mutex_unlock(&dev_priv->rps.hw_lock);
7772 } else {
7773 I915_WRITE(D_COMP_BDW, val);
7774 POSTING_READ(D_COMP_BDW);
7775 }
7776 }
7777
7778 /*
7779 * This function implements pieces of two sequences from BSpec:
7780 * - Sequence for display software to disable LCPLL
7781 * - Sequence for display software to allow package C8+
7782 * The steps implemented here are just the steps that actually touch the LCPLL
7783 * register. Callers should take care of disabling all the display engine
7784 * functions, doing the mode unset, fixing interrupts, etc.
7785 */
7786 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7787 bool switch_to_fclk, bool allow_power_down)
7788 {
7789 uint32_t val;
7790
7791 assert_can_disable_lcpll(dev_priv);
7792
7793 val = I915_READ(LCPLL_CTL);
7794
7795 if (switch_to_fclk) {
7796 val |= LCPLL_CD_SOURCE_FCLK;
7797 I915_WRITE(LCPLL_CTL, val);
7798
7799 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7800 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7801 DRM_ERROR("Switching to FCLK failed\n");
7802
7803 val = I915_READ(LCPLL_CTL);
7804 }
7805
7806 val |= LCPLL_PLL_DISABLE;
7807 I915_WRITE(LCPLL_CTL, val);
7808 POSTING_READ(LCPLL_CTL);
7809
7810 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7811 DRM_ERROR("LCPLL still locked\n");
7812
7813 val = hsw_read_dcomp(dev_priv);
7814 val |= D_COMP_COMP_DISABLE;
7815 hsw_write_dcomp(dev_priv, val);
7816 ndelay(100);
7817
7818 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7819 1))
7820 DRM_ERROR("D_COMP RCOMP still in progress\n");
7821
7822 if (allow_power_down) {
7823 val = I915_READ(LCPLL_CTL);
7824 val |= LCPLL_POWER_DOWN_ALLOW;
7825 I915_WRITE(LCPLL_CTL, val);
7826 POSTING_READ(LCPLL_CTL);
7827 }
7828 }
7829
7830 /*
7831 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7832 * source.
7833 */
7834 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7835 {
7836 uint32_t val;
7837
7838 val = I915_READ(LCPLL_CTL);
7839
7840 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7841 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7842 return;
7843
7844 /*
7845 * Make sure we're not on PC8 state before disabling PC8, otherwise
7846 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7847 *
7848 * The other problem is that hsw_restore_lcpll() is called as part of
7849 * the runtime PM resume sequence, so we can't just call
7850 * gen6_gt_force_wake_get() because that function calls
7851 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7852 * while we are on the resume sequence. So to solve this problem we have
7853 * to call special forcewake code that doesn't touch runtime PM and
7854 * doesn't enable the forcewake delayed work.
7855 */
7856 spin_lock_irq(&dev_priv->uncore.lock);
7857 if (dev_priv->uncore.forcewake_count++ == 0)
7858 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7859 spin_unlock_irq(&dev_priv->uncore.lock);
7860
7861 if (val & LCPLL_POWER_DOWN_ALLOW) {
7862 val &= ~LCPLL_POWER_DOWN_ALLOW;
7863 I915_WRITE(LCPLL_CTL, val);
7864 POSTING_READ(LCPLL_CTL);
7865 }
7866
7867 val = hsw_read_dcomp(dev_priv);
7868 val |= D_COMP_COMP_FORCE;
7869 val &= ~D_COMP_COMP_DISABLE;
7870 hsw_write_dcomp(dev_priv, val);
7871
7872 val = I915_READ(LCPLL_CTL);
7873 val &= ~LCPLL_PLL_DISABLE;
7874 I915_WRITE(LCPLL_CTL, val);
7875
7876 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7877 DRM_ERROR("LCPLL not locked yet\n");
7878
7879 if (val & LCPLL_CD_SOURCE_FCLK) {
7880 val = I915_READ(LCPLL_CTL);
7881 val &= ~LCPLL_CD_SOURCE_FCLK;
7882 I915_WRITE(LCPLL_CTL, val);
7883
7884 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7885 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7886 DRM_ERROR("Switching back to LCPLL failed\n");
7887 }
7888
7889 /* See the big comment above. */
7890 spin_lock_irq(&dev_priv->uncore.lock);
7891 if (--dev_priv->uncore.forcewake_count == 0)
7892 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7893 spin_unlock_irq(&dev_priv->uncore.lock);
7894 }
7895
7896 /*
7897 * Package states C8 and deeper are really deep PC states that can only be
7898 * reached when all the devices on the system allow it, so even if the graphics
7899 * device allows PC8+, it doesn't mean the system will actually get to these
7900 * states. Our driver only allows PC8+ when going into runtime PM.
7901 *
7902 * The requirements for PC8+ are that all the outputs are disabled, the power
7903 * well is disabled and most interrupts are disabled, and these are also
7904 * requirements for runtime PM. When these conditions are met, we manually do
7905 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7906 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7907 * hang the machine.
7908 *
7909 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7910 * the state of some registers, so when we come back from PC8+ we need to
7911 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7912 * need to take care of the registers kept by RC6. Notice that this happens even
7913 * if we don't put the device in PCI D3 state (which is what currently happens
7914 * because of the runtime PM support).
7915 *
7916 * For more, read "Display Sequences for Package C8" on the hardware
7917 * documentation.
7918 */
7919 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7920 {
7921 struct drm_device *dev = dev_priv->dev;
7922 uint32_t val;
7923
7924 DRM_DEBUG_KMS("Enabling package C8+\n");
7925
7926 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7927 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7928 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7929 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7930 }
7931
7932 lpt_disable_clkout_dp(dev);
7933 hsw_disable_lcpll(dev_priv, true, true);
7934 }
7935
7936 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7937 {
7938 struct drm_device *dev = dev_priv->dev;
7939 uint32_t val;
7940
7941 DRM_DEBUG_KMS("Disabling package C8+\n");
7942
7943 hsw_restore_lcpll(dev_priv);
7944 lpt_init_pch_refclk(dev);
7945
7946 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7947 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7948 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7949 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7950 }
7951
7952 intel_prepare_ddi(dev);
7953 }
7954
7955 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7956 {
7957 if (!intel_ddi_pll_select(crtc))
7958 return -EINVAL;
7959
7960 crtc->lowfreq_avail = false;
7961
7962 return 0;
7963 }
7964
7965 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7966 enum port port,
7967 struct intel_crtc_config *pipe_config)
7968 {
7969 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7970
7971 switch (pipe_config->ddi_pll_sel) {
7972 case PORT_CLK_SEL_WRPLL1:
7973 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7974 break;
7975 case PORT_CLK_SEL_WRPLL2:
7976 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7977 break;
7978 }
7979 }
7980
7981 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7982 struct intel_crtc_config *pipe_config)
7983 {
7984 struct drm_device *dev = crtc->base.dev;
7985 struct drm_i915_private *dev_priv = dev->dev_private;
7986 struct intel_shared_dpll *pll;
7987 enum port port;
7988 uint32_t tmp;
7989
7990 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7991
7992 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
7993
7994 haswell_get_ddi_pll(dev_priv, port, pipe_config);
7995
7996 if (pipe_config->shared_dpll >= 0) {
7997 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7998
7999 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8000 &pipe_config->dpll_hw_state));
8001 }
8002
8003 /*
8004 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8005 * DDI E. So just check whether this pipe is wired to DDI E and whether
8006 * the PCH transcoder is on.
8007 */
8008 if (INTEL_INFO(dev)->gen < 9 &&
8009 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8010 pipe_config->has_pch_encoder = true;
8011
8012 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8013 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8014 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8015
8016 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8017 }
8018 }
8019
8020 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8021 struct intel_crtc_config *pipe_config)
8022 {
8023 struct drm_device *dev = crtc->base.dev;
8024 struct drm_i915_private *dev_priv = dev->dev_private;
8025 enum intel_display_power_domain pfit_domain;
8026 uint32_t tmp;
8027
8028 if (!intel_display_power_is_enabled(dev_priv,
8029 POWER_DOMAIN_PIPE(crtc->pipe)))
8030 return false;
8031
8032 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8033 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8034
8035 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8036 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8037 enum pipe trans_edp_pipe;
8038 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8039 default:
8040 WARN(1, "unknown pipe linked to edp transcoder\n");
8041 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8042 case TRANS_DDI_EDP_INPUT_A_ON:
8043 trans_edp_pipe = PIPE_A;
8044 break;
8045 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8046 trans_edp_pipe = PIPE_B;
8047 break;
8048 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8049 trans_edp_pipe = PIPE_C;
8050 break;
8051 }
8052
8053 if (trans_edp_pipe == crtc->pipe)
8054 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8055 }
8056
8057 if (!intel_display_power_is_enabled(dev_priv,
8058 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8059 return false;
8060
8061 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8062 if (!(tmp & PIPECONF_ENABLE))
8063 return false;
8064
8065 haswell_get_ddi_port_state(crtc, pipe_config);
8066
8067 intel_get_pipe_timings(crtc, pipe_config);
8068
8069 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8070 if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8071 ironlake_get_pfit_config(crtc, pipe_config);
8072
8073 if (IS_HASWELL(dev))
8074 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8075 (I915_READ(IPS_CTL) & IPS_ENABLE);
8076
8077 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8078 pipe_config->pixel_multiplier =
8079 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8080 } else {
8081 pipe_config->pixel_multiplier = 1;
8082 }
8083
8084 return true;
8085 }
8086
8087 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8088 {
8089 struct drm_device *dev = crtc->dev;
8090 struct drm_i915_private *dev_priv = dev->dev_private;
8091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8092 uint32_t cntl = 0, size = 0;
8093
8094 if (base) {
8095 unsigned int width = intel_crtc->cursor_width;
8096 unsigned int height = intel_crtc->cursor_height;
8097 unsigned int stride = roundup_pow_of_two(width) * 4;
8098
8099 switch (stride) {
8100 default:
8101 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8102 width, stride);
8103 stride = 256;
8104 /* fallthrough */
8105 case 256:
8106 case 512:
8107 case 1024:
8108 case 2048:
8109 break;
8110 }
8111
8112 cntl |= CURSOR_ENABLE |
8113 CURSOR_GAMMA_ENABLE |
8114 CURSOR_FORMAT_ARGB |
8115 CURSOR_STRIDE(stride);
8116
8117 size = (height << 12) | width;
8118 }
8119
8120 if (intel_crtc->cursor_cntl != 0 &&
8121 (intel_crtc->cursor_base != base ||
8122 intel_crtc->cursor_size != size ||
8123 intel_crtc->cursor_cntl != cntl)) {
8124 /* On these chipsets we can only modify the base/size/stride
8125 * whilst the cursor is disabled.
8126 */
8127 I915_WRITE(_CURACNTR, 0);
8128 POSTING_READ(_CURACNTR);
8129 intel_crtc->cursor_cntl = 0;
8130 }
8131
8132 if (intel_crtc->cursor_base != base) {
8133 I915_WRITE(_CURABASE, base);
8134 intel_crtc->cursor_base = base;
8135 }
8136
8137 if (intel_crtc->cursor_size != size) {
8138 I915_WRITE(CURSIZE, size);
8139 intel_crtc->cursor_size = size;
8140 }
8141
8142 if (intel_crtc->cursor_cntl != cntl) {
8143 I915_WRITE(_CURACNTR, cntl);
8144 POSTING_READ(_CURACNTR);
8145 intel_crtc->cursor_cntl = cntl;
8146 }
8147 }
8148
8149 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8150 {
8151 struct drm_device *dev = crtc->dev;
8152 struct drm_i915_private *dev_priv = dev->dev_private;
8153 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8154 int pipe = intel_crtc->pipe;
8155 uint32_t cntl;
8156
8157 cntl = 0;
8158 if (base) {
8159 cntl = MCURSOR_GAMMA_ENABLE;
8160 switch (intel_crtc->cursor_width) {
8161 case 64:
8162 cntl |= CURSOR_MODE_64_ARGB_AX;
8163 break;
8164 case 128:
8165 cntl |= CURSOR_MODE_128_ARGB_AX;
8166 break;
8167 case 256:
8168 cntl |= CURSOR_MODE_256_ARGB_AX;
8169 break;
8170 default:
8171 WARN_ON(1);
8172 return;
8173 }
8174 cntl |= pipe << 28; /* Connect to correct pipe */
8175
8176 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8177 cntl |= CURSOR_PIPE_CSC_ENABLE;
8178 }
8179
8180 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8181 cntl |= CURSOR_ROTATE_180;
8182
8183 if (intel_crtc->cursor_cntl != cntl) {
8184 I915_WRITE(CURCNTR(pipe), cntl);
8185 POSTING_READ(CURCNTR(pipe));
8186 intel_crtc->cursor_cntl = cntl;
8187 }
8188
8189 /* and commit changes on next vblank */
8190 I915_WRITE(CURBASE(pipe), base);
8191 POSTING_READ(CURBASE(pipe));
8192
8193 intel_crtc->cursor_base = base;
8194 }
8195
8196 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8197 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8198 bool on)
8199 {
8200 struct drm_device *dev = crtc->dev;
8201 struct drm_i915_private *dev_priv = dev->dev_private;
8202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8203 int pipe = intel_crtc->pipe;
8204 int x = crtc->cursor_x;
8205 int y = crtc->cursor_y;
8206 u32 base = 0, pos = 0;
8207
8208 if (on)
8209 base = intel_crtc->cursor_addr;
8210
8211 if (x >= intel_crtc->config.pipe_src_w)
8212 base = 0;
8213
8214 if (y >= intel_crtc->config.pipe_src_h)
8215 base = 0;
8216
8217 if (x < 0) {
8218 if (x + intel_crtc->cursor_width <= 0)
8219 base = 0;
8220
8221 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8222 x = -x;
8223 }
8224 pos |= x << CURSOR_X_SHIFT;
8225
8226 if (y < 0) {
8227 if (y + intel_crtc->cursor_height <= 0)
8228 base = 0;
8229
8230 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8231 y = -y;
8232 }
8233 pos |= y << CURSOR_Y_SHIFT;
8234
8235 if (base == 0 && intel_crtc->cursor_base == 0)
8236 return;
8237
8238 I915_WRITE(CURPOS(pipe), pos);
8239
8240 /* ILK+ do this automagically */
8241 if (HAS_GMCH_DISPLAY(dev) &&
8242 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8243 base += (intel_crtc->cursor_height *
8244 intel_crtc->cursor_width - 1) * 4;
8245 }
8246
8247 if (IS_845G(dev) || IS_I865G(dev))
8248 i845_update_cursor(crtc, base);
8249 else
8250 i9xx_update_cursor(crtc, base);
8251 }
8252
8253 static bool cursor_size_ok(struct drm_device *dev,
8254 uint32_t width, uint32_t height)
8255 {
8256 if (width == 0 || height == 0)
8257 return false;
8258
8259 /*
8260 * 845g/865g are special in that they are only limited by
8261 * the width of their cursors, the height is arbitrary up to
8262 * the precision of the register. Everything else requires
8263 * square cursors, limited to a few power-of-two sizes.
8264 */
8265 if (IS_845G(dev) || IS_I865G(dev)) {
8266 if ((width & 63) != 0)
8267 return false;
8268
8269 if (width > (IS_845G(dev) ? 64 : 512))
8270 return false;
8271
8272 if (height > 1023)
8273 return false;
8274 } else {
8275 switch (width | height) {
8276 case 256:
8277 case 128:
8278 if (IS_GEN2(dev))
8279 return false;
8280 case 64:
8281 break;
8282 default:
8283 return false;
8284 }
8285 }
8286
8287 return true;
8288 }
8289
8290 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8291 struct drm_i915_gem_object *obj,
8292 uint32_t width, uint32_t height)
8293 {
8294 struct drm_device *dev = crtc->dev;
8295 struct drm_i915_private *dev_priv = dev->dev_private;
8296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8297 enum pipe pipe = intel_crtc->pipe;
8298 unsigned old_width;
8299 uint32_t addr;
8300 int ret;
8301
8302 /* if we want to turn off the cursor ignore width and height */
8303 if (!obj) {
8304 DRM_DEBUG_KMS("cursor off\n");
8305 addr = 0;
8306 mutex_lock(&dev->struct_mutex);
8307 goto finish;
8308 }
8309
8310 /* we only need to pin inside GTT if cursor is non-phy */
8311 mutex_lock(&dev->struct_mutex);
8312 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8313 unsigned alignment;
8314
8315 /*
8316 * Global gtt pte registers are special registers which actually
8317 * forward writes to a chunk of system memory. Which means that
8318 * there is no risk that the register values disappear as soon
8319 * as we call intel_runtime_pm_put(), so it is correct to wrap
8320 * only the pin/unpin/fence and not more.
8321 */
8322 intel_runtime_pm_get(dev_priv);
8323
8324 /* Note that the w/a also requires 2 PTE of padding following
8325 * the bo. We currently fill all unused PTE with the shadow
8326 * page and so we should always have valid PTE following the
8327 * cursor preventing the VT-d warning.
8328 */
8329 alignment = 0;
8330 if (need_vtd_wa(dev))
8331 alignment = 64*1024;
8332
8333 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8334 if (ret) {
8335 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8336 intel_runtime_pm_put(dev_priv);
8337 goto fail_locked;
8338 }
8339
8340 ret = i915_gem_object_put_fence(obj);
8341 if (ret) {
8342 DRM_DEBUG_KMS("failed to release fence for cursor");
8343 intel_runtime_pm_put(dev_priv);
8344 goto fail_unpin;
8345 }
8346
8347 addr = i915_gem_obj_ggtt_offset(obj);
8348
8349 intel_runtime_pm_put(dev_priv);
8350 } else {
8351 int align = IS_I830(dev) ? 16 * 1024 : 256;
8352 ret = i915_gem_object_attach_phys(obj, align);
8353 if (ret) {
8354 DRM_DEBUG_KMS("failed to attach phys object\n");
8355 goto fail_locked;
8356 }
8357 addr = obj->phys_handle->busaddr;
8358 }
8359
8360 finish:
8361 if (intel_crtc->cursor_bo) {
8362 if (!INTEL_INFO(dev)->cursor_needs_physical)
8363 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8364 }
8365
8366 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8367 INTEL_FRONTBUFFER_CURSOR(pipe));
8368 mutex_unlock(&dev->struct_mutex);
8369
8370 old_width = intel_crtc->cursor_width;
8371
8372 intel_crtc->cursor_addr = addr;
8373 intel_crtc->cursor_bo = obj;
8374 intel_crtc->cursor_width = width;
8375 intel_crtc->cursor_height = height;
8376
8377 if (intel_crtc->active) {
8378 if (old_width != width)
8379 intel_update_watermarks(crtc);
8380 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8381
8382 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8383 }
8384
8385 return 0;
8386 fail_unpin:
8387 i915_gem_object_unpin_from_display_plane(obj);
8388 fail_locked:
8389 mutex_unlock(&dev->struct_mutex);
8390 return ret;
8391 }
8392
8393 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8394 u16 *blue, uint32_t start, uint32_t size)
8395 {
8396 int end = (start + size > 256) ? 256 : start + size, i;
8397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8398
8399 for (i = start; i < end; i++) {
8400 intel_crtc->lut_r[i] = red[i] >> 8;
8401 intel_crtc->lut_g[i] = green[i] >> 8;
8402 intel_crtc->lut_b[i] = blue[i] >> 8;
8403 }
8404
8405 intel_crtc_load_lut(crtc);
8406 }
8407
8408 /* VESA 640x480x72Hz mode to set on the pipe */
8409 static struct drm_display_mode load_detect_mode = {
8410 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8411 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8412 };
8413
8414 struct drm_framebuffer *
8415 __intel_framebuffer_create(struct drm_device *dev,
8416 struct drm_mode_fb_cmd2 *mode_cmd,
8417 struct drm_i915_gem_object *obj)
8418 {
8419 struct intel_framebuffer *intel_fb;
8420 int ret;
8421
8422 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8423 if (!intel_fb) {
8424 drm_gem_object_unreference_unlocked(&obj->base);
8425 return ERR_PTR(-ENOMEM);
8426 }
8427
8428 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8429 if (ret)
8430 goto err;
8431
8432 return &intel_fb->base;
8433 err:
8434 drm_gem_object_unreference_unlocked(&obj->base);
8435 kfree(intel_fb);
8436
8437 return ERR_PTR(ret);
8438 }
8439
8440 static struct drm_framebuffer *
8441 intel_framebuffer_create(struct drm_device *dev,
8442 struct drm_mode_fb_cmd2 *mode_cmd,
8443 struct drm_i915_gem_object *obj)
8444 {
8445 struct drm_framebuffer *fb;
8446 int ret;
8447
8448 ret = i915_mutex_lock_interruptible(dev);
8449 if (ret)
8450 return ERR_PTR(ret);
8451 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8452 mutex_unlock(&dev->struct_mutex);
8453
8454 return fb;
8455 }
8456
8457 static u32
8458 intel_framebuffer_pitch_for_width(int width, int bpp)
8459 {
8460 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8461 return ALIGN(pitch, 64);
8462 }
8463
8464 static u32
8465 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8466 {
8467 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8468 return PAGE_ALIGN(pitch * mode->vdisplay);
8469 }
8470
8471 static struct drm_framebuffer *
8472 intel_framebuffer_create_for_mode(struct drm_device *dev,
8473 struct drm_display_mode *mode,
8474 int depth, int bpp)
8475 {
8476 struct drm_i915_gem_object *obj;
8477 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8478
8479 obj = i915_gem_alloc_object(dev,
8480 intel_framebuffer_size_for_mode(mode, bpp));
8481 if (obj == NULL)
8482 return ERR_PTR(-ENOMEM);
8483
8484 mode_cmd.width = mode->hdisplay;
8485 mode_cmd.height = mode->vdisplay;
8486 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8487 bpp);
8488 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8489
8490 return intel_framebuffer_create(dev, &mode_cmd, obj);
8491 }
8492
8493 static struct drm_framebuffer *
8494 mode_fits_in_fbdev(struct drm_device *dev,
8495 struct drm_display_mode *mode)
8496 {
8497 #ifdef CONFIG_DRM_I915_FBDEV
8498 struct drm_i915_private *dev_priv = dev->dev_private;
8499 struct drm_i915_gem_object *obj;
8500 struct drm_framebuffer *fb;
8501
8502 if (!dev_priv->fbdev)
8503 return NULL;
8504
8505 if (!dev_priv->fbdev->fb)
8506 return NULL;
8507
8508 obj = dev_priv->fbdev->fb->obj;
8509 BUG_ON(!obj);
8510
8511 fb = &dev_priv->fbdev->fb->base;
8512 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8513 fb->bits_per_pixel))
8514 return NULL;
8515
8516 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8517 return NULL;
8518
8519 return fb;
8520 #else
8521 return NULL;
8522 #endif
8523 }
8524
8525 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8526 struct drm_display_mode *mode,
8527 struct intel_load_detect_pipe *old,
8528 struct drm_modeset_acquire_ctx *ctx)
8529 {
8530 struct intel_crtc *intel_crtc;
8531 struct intel_encoder *intel_encoder =
8532 intel_attached_encoder(connector);
8533 struct drm_crtc *possible_crtc;
8534 struct drm_encoder *encoder = &intel_encoder->base;
8535 struct drm_crtc *crtc = NULL;
8536 struct drm_device *dev = encoder->dev;
8537 struct drm_framebuffer *fb;
8538 struct drm_mode_config *config = &dev->mode_config;
8539 int ret, i = -1;
8540
8541 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8542 connector->base.id, connector->name,
8543 encoder->base.id, encoder->name);
8544
8545 retry:
8546 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8547 if (ret)
8548 goto fail_unlock;
8549
8550 /*
8551 * Algorithm gets a little messy:
8552 *
8553 * - if the connector already has an assigned crtc, use it (but make
8554 * sure it's on first)
8555 *
8556 * - try to find the first unused crtc that can drive this connector,
8557 * and use that if we find one
8558 */
8559
8560 /* See if we already have a CRTC for this connector */
8561 if (encoder->crtc) {
8562 crtc = encoder->crtc;
8563
8564 ret = drm_modeset_lock(&crtc->mutex, ctx);
8565 if (ret)
8566 goto fail_unlock;
8567 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8568 if (ret)
8569 goto fail_unlock;
8570
8571 old->dpms_mode = connector->dpms;
8572 old->load_detect_temp = false;
8573
8574 /* Make sure the crtc and connector are running */
8575 if (connector->dpms != DRM_MODE_DPMS_ON)
8576 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8577
8578 return true;
8579 }
8580
8581 /* Find an unused one (if possible) */
8582 for_each_crtc(dev, possible_crtc) {
8583 i++;
8584 if (!(encoder->possible_crtcs & (1 << i)))
8585 continue;
8586 if (possible_crtc->enabled)
8587 continue;
8588 /* This can occur when applying the pipe A quirk on resume. */
8589 if (to_intel_crtc(possible_crtc)->new_enabled)
8590 continue;
8591
8592 crtc = possible_crtc;
8593 break;
8594 }
8595
8596 /*
8597 * If we didn't find an unused CRTC, don't use any.
8598 */
8599 if (!crtc) {
8600 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8601 goto fail_unlock;
8602 }
8603
8604 ret = drm_modeset_lock(&crtc->mutex, ctx);
8605 if (ret)
8606 goto fail_unlock;
8607 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8608 if (ret)
8609 goto fail_unlock;
8610 intel_encoder->new_crtc = to_intel_crtc(crtc);
8611 to_intel_connector(connector)->new_encoder = intel_encoder;
8612
8613 intel_crtc = to_intel_crtc(crtc);
8614 intel_crtc->new_enabled = true;
8615 intel_crtc->new_config = &intel_crtc->config;
8616 old->dpms_mode = connector->dpms;
8617 old->load_detect_temp = true;
8618 old->release_fb = NULL;
8619
8620 if (!mode)
8621 mode = &load_detect_mode;
8622
8623 /* We need a framebuffer large enough to accommodate all accesses
8624 * that the plane may generate whilst we perform load detection.
8625 * We can not rely on the fbcon either being present (we get called
8626 * during its initialisation to detect all boot displays, or it may
8627 * not even exist) or that it is large enough to satisfy the
8628 * requested mode.
8629 */
8630 fb = mode_fits_in_fbdev(dev, mode);
8631 if (fb == NULL) {
8632 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8633 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8634 old->release_fb = fb;
8635 } else
8636 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8637 if (IS_ERR(fb)) {
8638 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8639 goto fail;
8640 }
8641
8642 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8643 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8644 if (old->release_fb)
8645 old->release_fb->funcs->destroy(old->release_fb);
8646 goto fail;
8647 }
8648
8649 /* let the connector get through one full cycle before testing */
8650 intel_wait_for_vblank(dev, intel_crtc->pipe);
8651 return true;
8652
8653 fail:
8654 intel_crtc->new_enabled = crtc->enabled;
8655 if (intel_crtc->new_enabled)
8656 intel_crtc->new_config = &intel_crtc->config;
8657 else
8658 intel_crtc->new_config = NULL;
8659 fail_unlock:
8660 if (ret == -EDEADLK) {
8661 drm_modeset_backoff(ctx);
8662 goto retry;
8663 }
8664
8665 return false;
8666 }
8667
8668 void intel_release_load_detect_pipe(struct drm_connector *connector,
8669 struct intel_load_detect_pipe *old)
8670 {
8671 struct intel_encoder *intel_encoder =
8672 intel_attached_encoder(connector);
8673 struct drm_encoder *encoder = &intel_encoder->base;
8674 struct drm_crtc *crtc = encoder->crtc;
8675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8676
8677 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8678 connector->base.id, connector->name,
8679 encoder->base.id, encoder->name);
8680
8681 if (old->load_detect_temp) {
8682 to_intel_connector(connector)->new_encoder = NULL;
8683 intel_encoder->new_crtc = NULL;
8684 intel_crtc->new_enabled = false;
8685 intel_crtc->new_config = NULL;
8686 intel_set_mode(crtc, NULL, 0, 0, NULL);
8687
8688 if (old->release_fb) {
8689 drm_framebuffer_unregister_private(old->release_fb);
8690 drm_framebuffer_unreference(old->release_fb);
8691 }
8692
8693 return;
8694 }
8695
8696 /* Switch crtc and encoder back off if necessary */
8697 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8698 connector->funcs->dpms(connector, old->dpms_mode);
8699 }
8700
8701 static int i9xx_pll_refclk(struct drm_device *dev,
8702 const struct intel_crtc_config *pipe_config)
8703 {
8704 struct drm_i915_private *dev_priv = dev->dev_private;
8705 u32 dpll = pipe_config->dpll_hw_state.dpll;
8706
8707 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8708 return dev_priv->vbt.lvds_ssc_freq;
8709 else if (HAS_PCH_SPLIT(dev))
8710 return 120000;
8711 else if (!IS_GEN2(dev))
8712 return 96000;
8713 else
8714 return 48000;
8715 }
8716
8717 /* Returns the clock of the currently programmed mode of the given pipe. */
8718 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8719 struct intel_crtc_config *pipe_config)
8720 {
8721 struct drm_device *dev = crtc->base.dev;
8722 struct drm_i915_private *dev_priv = dev->dev_private;
8723 int pipe = pipe_config->cpu_transcoder;
8724 u32 dpll = pipe_config->dpll_hw_state.dpll;
8725 u32 fp;
8726 intel_clock_t clock;
8727 int refclk = i9xx_pll_refclk(dev, pipe_config);
8728
8729 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8730 fp = pipe_config->dpll_hw_state.fp0;
8731 else
8732 fp = pipe_config->dpll_hw_state.fp1;
8733
8734 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8735 if (IS_PINEVIEW(dev)) {
8736 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8737 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8738 } else {
8739 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8740 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8741 }
8742
8743 if (!IS_GEN2(dev)) {
8744 if (IS_PINEVIEW(dev))
8745 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8746 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8747 else
8748 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8749 DPLL_FPA01_P1_POST_DIV_SHIFT);
8750
8751 switch (dpll & DPLL_MODE_MASK) {
8752 case DPLLB_MODE_DAC_SERIAL:
8753 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8754 5 : 10;
8755 break;
8756 case DPLLB_MODE_LVDS:
8757 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8758 7 : 14;
8759 break;
8760 default:
8761 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8762 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8763 return;
8764 }
8765
8766 if (IS_PINEVIEW(dev))
8767 pineview_clock(refclk, &clock);
8768 else
8769 i9xx_clock(refclk, &clock);
8770 } else {
8771 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8772 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8773
8774 if (is_lvds) {
8775 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8776 DPLL_FPA01_P1_POST_DIV_SHIFT);
8777
8778 if (lvds & LVDS_CLKB_POWER_UP)
8779 clock.p2 = 7;
8780 else
8781 clock.p2 = 14;
8782 } else {
8783 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8784 clock.p1 = 2;
8785 else {
8786 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8787 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8788 }
8789 if (dpll & PLL_P2_DIVIDE_BY_4)
8790 clock.p2 = 4;
8791 else
8792 clock.p2 = 2;
8793 }
8794
8795 i9xx_clock(refclk, &clock);
8796 }
8797
8798 /*
8799 * This value includes pixel_multiplier. We will use
8800 * port_clock to compute adjusted_mode.crtc_clock in the
8801 * encoder's get_config() function.
8802 */
8803 pipe_config->port_clock = clock.dot;
8804 }
8805
8806 int intel_dotclock_calculate(int link_freq,
8807 const struct intel_link_m_n *m_n)
8808 {
8809 /*
8810 * The calculation for the data clock is:
8811 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8812 * But we want to avoid losing precison if possible, so:
8813 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8814 *
8815 * and the link clock is simpler:
8816 * link_clock = (m * link_clock) / n
8817 */
8818
8819 if (!m_n->link_n)
8820 return 0;
8821
8822 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8823 }
8824
8825 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8826 struct intel_crtc_config *pipe_config)
8827 {
8828 struct drm_device *dev = crtc->base.dev;
8829
8830 /* read out port_clock from the DPLL */
8831 i9xx_crtc_clock_get(crtc, pipe_config);
8832
8833 /*
8834 * This value does not include pixel_multiplier.
8835 * We will check that port_clock and adjusted_mode.crtc_clock
8836 * agree once we know their relationship in the encoder's
8837 * get_config() function.
8838 */
8839 pipe_config->adjusted_mode.crtc_clock =
8840 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8841 &pipe_config->fdi_m_n);
8842 }
8843
8844 /** Returns the currently programmed mode of the given pipe. */
8845 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8846 struct drm_crtc *crtc)
8847 {
8848 struct drm_i915_private *dev_priv = dev->dev_private;
8849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8850 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8851 struct drm_display_mode *mode;
8852 struct intel_crtc_config pipe_config;
8853 int htot = I915_READ(HTOTAL(cpu_transcoder));
8854 int hsync = I915_READ(HSYNC(cpu_transcoder));
8855 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8856 int vsync = I915_READ(VSYNC(cpu_transcoder));
8857 enum pipe pipe = intel_crtc->pipe;
8858
8859 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8860 if (!mode)
8861 return NULL;
8862
8863 /*
8864 * Construct a pipe_config sufficient for getting the clock info
8865 * back out of crtc_clock_get.
8866 *
8867 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8868 * to use a real value here instead.
8869 */
8870 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8871 pipe_config.pixel_multiplier = 1;
8872 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8873 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8874 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8875 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8876
8877 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8878 mode->hdisplay = (htot & 0xffff) + 1;
8879 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8880 mode->hsync_start = (hsync & 0xffff) + 1;
8881 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8882 mode->vdisplay = (vtot & 0xffff) + 1;
8883 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8884 mode->vsync_start = (vsync & 0xffff) + 1;
8885 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8886
8887 drm_mode_set_name(mode);
8888
8889 return mode;
8890 }
8891
8892 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8893 {
8894 struct drm_device *dev = crtc->dev;
8895 struct drm_i915_private *dev_priv = dev->dev_private;
8896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8897
8898 if (!HAS_GMCH_DISPLAY(dev))
8899 return;
8900
8901 if (!dev_priv->lvds_downclock_avail)
8902 return;
8903
8904 /*
8905 * Since this is called by a timer, we should never get here in
8906 * the manual case.
8907 */
8908 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8909 int pipe = intel_crtc->pipe;
8910 int dpll_reg = DPLL(pipe);
8911 int dpll;
8912
8913 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8914
8915 assert_panel_unlocked(dev_priv, pipe);
8916
8917 dpll = I915_READ(dpll_reg);
8918 dpll |= DISPLAY_RATE_SELECT_FPA1;
8919 I915_WRITE(dpll_reg, dpll);
8920 intel_wait_for_vblank(dev, pipe);
8921 dpll = I915_READ(dpll_reg);
8922 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8923 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8924 }
8925
8926 }
8927
8928 void intel_mark_busy(struct drm_device *dev)
8929 {
8930 struct drm_i915_private *dev_priv = dev->dev_private;
8931
8932 if (dev_priv->mm.busy)
8933 return;
8934
8935 intel_runtime_pm_get(dev_priv);
8936 i915_update_gfx_val(dev_priv);
8937 dev_priv->mm.busy = true;
8938 }
8939
8940 void intel_mark_idle(struct drm_device *dev)
8941 {
8942 struct drm_i915_private *dev_priv = dev->dev_private;
8943 struct drm_crtc *crtc;
8944
8945 if (!dev_priv->mm.busy)
8946 return;
8947
8948 dev_priv->mm.busy = false;
8949
8950 if (!i915.powersave)
8951 goto out;
8952
8953 for_each_crtc(dev, crtc) {
8954 if (!crtc->primary->fb)
8955 continue;
8956
8957 intel_decrease_pllclock(crtc);
8958 }
8959
8960 if (INTEL_INFO(dev)->gen >= 6)
8961 gen6_rps_idle(dev->dev_private);
8962
8963 out:
8964 intel_runtime_pm_put(dev_priv);
8965 }
8966
8967 static void intel_crtc_destroy(struct drm_crtc *crtc)
8968 {
8969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8970 struct drm_device *dev = crtc->dev;
8971 struct intel_unpin_work *work;
8972
8973 spin_lock_irq(&dev->event_lock);
8974 work = intel_crtc->unpin_work;
8975 intel_crtc->unpin_work = NULL;
8976 spin_unlock_irq(&dev->event_lock);
8977
8978 if (work) {
8979 cancel_work_sync(&work->work);
8980 kfree(work);
8981 }
8982
8983 drm_crtc_cleanup(crtc);
8984
8985 kfree(intel_crtc);
8986 }
8987
8988 static void intel_unpin_work_fn(struct work_struct *__work)
8989 {
8990 struct intel_unpin_work *work =
8991 container_of(__work, struct intel_unpin_work, work);
8992 struct drm_device *dev = work->crtc->dev;
8993 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8994
8995 mutex_lock(&dev->struct_mutex);
8996 intel_unpin_fb_obj(work->old_fb_obj);
8997 drm_gem_object_unreference(&work->pending_flip_obj->base);
8998 drm_gem_object_unreference(&work->old_fb_obj->base);
8999
9000 intel_update_fbc(dev);
9001 mutex_unlock(&dev->struct_mutex);
9002
9003 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9004
9005 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9006 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9007
9008 kfree(work);
9009 }
9010
9011 static void do_intel_finish_page_flip(struct drm_device *dev,
9012 struct drm_crtc *crtc)
9013 {
9014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9015 struct intel_unpin_work *work;
9016 unsigned long flags;
9017
9018 /* Ignore early vblank irqs */
9019 if (intel_crtc == NULL)
9020 return;
9021
9022 /*
9023 * This is called both by irq handlers and the reset code (to complete
9024 * lost pageflips) so needs the full irqsave spinlocks.
9025 */
9026 spin_lock_irqsave(&dev->event_lock, flags);
9027 work = intel_crtc->unpin_work;
9028
9029 /* Ensure we don't miss a work->pending update ... */
9030 smp_rmb();
9031
9032 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9033 spin_unlock_irqrestore(&dev->event_lock, flags);
9034 return;
9035 }
9036
9037 page_flip_completed(intel_crtc);
9038
9039 spin_unlock_irqrestore(&dev->event_lock, flags);
9040 }
9041
9042 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9043 {
9044 struct drm_i915_private *dev_priv = dev->dev_private;
9045 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9046
9047 do_intel_finish_page_flip(dev, crtc);
9048 }
9049
9050 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9051 {
9052 struct drm_i915_private *dev_priv = dev->dev_private;
9053 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9054
9055 do_intel_finish_page_flip(dev, crtc);
9056 }
9057
9058 /* Is 'a' after or equal to 'b'? */
9059 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9060 {
9061 return !((a - b) & 0x80000000);
9062 }
9063
9064 static bool page_flip_finished(struct intel_crtc *crtc)
9065 {
9066 struct drm_device *dev = crtc->base.dev;
9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068
9069 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9070 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9071 return true;
9072
9073 /*
9074 * The relevant registers doen't exist on pre-ctg.
9075 * As the flip done interrupt doesn't trigger for mmio
9076 * flips on gmch platforms, a flip count check isn't
9077 * really needed there. But since ctg has the registers,
9078 * include it in the check anyway.
9079 */
9080 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9081 return true;
9082
9083 /*
9084 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9085 * used the same base address. In that case the mmio flip might
9086 * have completed, but the CS hasn't even executed the flip yet.
9087 *
9088 * A flip count check isn't enough as the CS might have updated
9089 * the base address just after start of vblank, but before we
9090 * managed to process the interrupt. This means we'd complete the
9091 * CS flip too soon.
9092 *
9093 * Combining both checks should get us a good enough result. It may
9094 * still happen that the CS flip has been executed, but has not
9095 * yet actually completed. But in case the base address is the same
9096 * anyway, we don't really care.
9097 */
9098 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9099 crtc->unpin_work->gtt_offset &&
9100 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9101 crtc->unpin_work->flip_count);
9102 }
9103
9104 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9105 {
9106 struct drm_i915_private *dev_priv = dev->dev_private;
9107 struct intel_crtc *intel_crtc =
9108 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9109 unsigned long flags;
9110
9111
9112 /*
9113 * This is called both by irq handlers and the reset code (to complete
9114 * lost pageflips) so needs the full irqsave spinlocks.
9115 *
9116 * NB: An MMIO update of the plane base pointer will also
9117 * generate a page-flip completion irq, i.e. every modeset
9118 * is also accompanied by a spurious intel_prepare_page_flip().
9119 */
9120 spin_lock_irqsave(&dev->event_lock, flags);
9121 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9122 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9123 spin_unlock_irqrestore(&dev->event_lock, flags);
9124 }
9125
9126 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9127 {
9128 /* Ensure that the work item is consistent when activating it ... */
9129 smp_wmb();
9130 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9131 /* and that it is marked active as soon as the irq could fire. */
9132 smp_wmb();
9133 }
9134
9135 static int intel_gen2_queue_flip(struct drm_device *dev,
9136 struct drm_crtc *crtc,
9137 struct drm_framebuffer *fb,
9138 struct drm_i915_gem_object *obj,
9139 struct intel_engine_cs *ring,
9140 uint32_t flags)
9141 {
9142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9143 u32 flip_mask;
9144 int ret;
9145
9146 ret = intel_ring_begin(ring, 6);
9147 if (ret)
9148 return ret;
9149
9150 /* Can't queue multiple flips, so wait for the previous
9151 * one to finish before executing the next.
9152 */
9153 if (intel_crtc->plane)
9154 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9155 else
9156 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9157 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9158 intel_ring_emit(ring, MI_NOOP);
9159 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9160 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9161 intel_ring_emit(ring, fb->pitches[0]);
9162 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9163 intel_ring_emit(ring, 0); /* aux display base address, unused */
9164
9165 intel_mark_page_flip_active(intel_crtc);
9166 __intel_ring_advance(ring);
9167 return 0;
9168 }
9169
9170 static int intel_gen3_queue_flip(struct drm_device *dev,
9171 struct drm_crtc *crtc,
9172 struct drm_framebuffer *fb,
9173 struct drm_i915_gem_object *obj,
9174 struct intel_engine_cs *ring,
9175 uint32_t flags)
9176 {
9177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9178 u32 flip_mask;
9179 int ret;
9180
9181 ret = intel_ring_begin(ring, 6);
9182 if (ret)
9183 return ret;
9184
9185 if (intel_crtc->plane)
9186 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9187 else
9188 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9189 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9190 intel_ring_emit(ring, MI_NOOP);
9191 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9192 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9193 intel_ring_emit(ring, fb->pitches[0]);
9194 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9195 intel_ring_emit(ring, MI_NOOP);
9196
9197 intel_mark_page_flip_active(intel_crtc);
9198 __intel_ring_advance(ring);
9199 return 0;
9200 }
9201
9202 static int intel_gen4_queue_flip(struct drm_device *dev,
9203 struct drm_crtc *crtc,
9204 struct drm_framebuffer *fb,
9205 struct drm_i915_gem_object *obj,
9206 struct intel_engine_cs *ring,
9207 uint32_t flags)
9208 {
9209 struct drm_i915_private *dev_priv = dev->dev_private;
9210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9211 uint32_t pf, pipesrc;
9212 int ret;
9213
9214 ret = intel_ring_begin(ring, 4);
9215 if (ret)
9216 return ret;
9217
9218 /* i965+ uses the linear or tiled offsets from the
9219 * Display Registers (which do not change across a page-flip)
9220 * so we need only reprogram the base address.
9221 */
9222 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9223 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9224 intel_ring_emit(ring, fb->pitches[0]);
9225 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9226 obj->tiling_mode);
9227
9228 /* XXX Enabling the panel-fitter across page-flip is so far
9229 * untested on non-native modes, so ignore it for now.
9230 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9231 */
9232 pf = 0;
9233 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9234 intel_ring_emit(ring, pf | pipesrc);
9235
9236 intel_mark_page_flip_active(intel_crtc);
9237 __intel_ring_advance(ring);
9238 return 0;
9239 }
9240
9241 static int intel_gen6_queue_flip(struct drm_device *dev,
9242 struct drm_crtc *crtc,
9243 struct drm_framebuffer *fb,
9244 struct drm_i915_gem_object *obj,
9245 struct intel_engine_cs *ring,
9246 uint32_t flags)
9247 {
9248 struct drm_i915_private *dev_priv = dev->dev_private;
9249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9250 uint32_t pf, pipesrc;
9251 int ret;
9252
9253 ret = intel_ring_begin(ring, 4);
9254 if (ret)
9255 return ret;
9256
9257 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9258 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9259 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9260 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9261
9262 /* Contrary to the suggestions in the documentation,
9263 * "Enable Panel Fitter" does not seem to be required when page
9264 * flipping with a non-native mode, and worse causes a normal
9265 * modeset to fail.
9266 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9267 */
9268 pf = 0;
9269 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9270 intel_ring_emit(ring, pf | pipesrc);
9271
9272 intel_mark_page_flip_active(intel_crtc);
9273 __intel_ring_advance(ring);
9274 return 0;
9275 }
9276
9277 static int intel_gen7_queue_flip(struct drm_device *dev,
9278 struct drm_crtc *crtc,
9279 struct drm_framebuffer *fb,
9280 struct drm_i915_gem_object *obj,
9281 struct intel_engine_cs *ring,
9282 uint32_t flags)
9283 {
9284 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9285 uint32_t plane_bit = 0;
9286 int len, ret;
9287
9288 switch (intel_crtc->plane) {
9289 case PLANE_A:
9290 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9291 break;
9292 case PLANE_B:
9293 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9294 break;
9295 case PLANE_C:
9296 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9297 break;
9298 default:
9299 WARN_ONCE(1, "unknown plane in flip command\n");
9300 return -ENODEV;
9301 }
9302
9303 len = 4;
9304 if (ring->id == RCS) {
9305 len += 6;
9306 /*
9307 * On Gen 8, SRM is now taking an extra dword to accommodate
9308 * 48bits addresses, and we need a NOOP for the batch size to
9309 * stay even.
9310 */
9311 if (IS_GEN8(dev))
9312 len += 2;
9313 }
9314
9315 /*
9316 * BSpec MI_DISPLAY_FLIP for IVB:
9317 * "The full packet must be contained within the same cache line."
9318 *
9319 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9320 * cacheline, if we ever start emitting more commands before
9321 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9322 * then do the cacheline alignment, and finally emit the
9323 * MI_DISPLAY_FLIP.
9324 */
9325 ret = intel_ring_cacheline_align(ring);
9326 if (ret)
9327 return ret;
9328
9329 ret = intel_ring_begin(ring, len);
9330 if (ret)
9331 return ret;
9332
9333 /* Unmask the flip-done completion message. Note that the bspec says that
9334 * we should do this for both the BCS and RCS, and that we must not unmask
9335 * more than one flip event at any time (or ensure that one flip message
9336 * can be sent by waiting for flip-done prior to queueing new flips).
9337 * Experimentation says that BCS works despite DERRMR masking all
9338 * flip-done completion events and that unmasking all planes at once
9339 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9340 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9341 */
9342 if (ring->id == RCS) {
9343 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9344 intel_ring_emit(ring, DERRMR);
9345 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9346 DERRMR_PIPEB_PRI_FLIP_DONE |
9347 DERRMR_PIPEC_PRI_FLIP_DONE));
9348 if (IS_GEN8(dev))
9349 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9350 MI_SRM_LRM_GLOBAL_GTT);
9351 else
9352 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9353 MI_SRM_LRM_GLOBAL_GTT);
9354 intel_ring_emit(ring, DERRMR);
9355 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9356 if (IS_GEN8(dev)) {
9357 intel_ring_emit(ring, 0);
9358 intel_ring_emit(ring, MI_NOOP);
9359 }
9360 }
9361
9362 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9363 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9364 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9365 intel_ring_emit(ring, (MI_NOOP));
9366
9367 intel_mark_page_flip_active(intel_crtc);
9368 __intel_ring_advance(ring);
9369 return 0;
9370 }
9371
9372 static bool use_mmio_flip(struct intel_engine_cs *ring,
9373 struct drm_i915_gem_object *obj)
9374 {
9375 /*
9376 * This is not being used for older platforms, because
9377 * non-availability of flip done interrupt forces us to use
9378 * CS flips. Older platforms derive flip done using some clever
9379 * tricks involving the flip_pending status bits and vblank irqs.
9380 * So using MMIO flips there would disrupt this mechanism.
9381 */
9382
9383 if (ring == NULL)
9384 return true;
9385
9386 if (INTEL_INFO(ring->dev)->gen < 5)
9387 return false;
9388
9389 if (i915.use_mmio_flip < 0)
9390 return false;
9391 else if (i915.use_mmio_flip > 0)
9392 return true;
9393 else if (i915.enable_execlists)
9394 return true;
9395 else
9396 return ring != obj->ring;
9397 }
9398
9399 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9400 {
9401 struct drm_device *dev = intel_crtc->base.dev;
9402 struct drm_i915_private *dev_priv = dev->dev_private;
9403 struct intel_framebuffer *intel_fb =
9404 to_intel_framebuffer(intel_crtc->base.primary->fb);
9405 struct drm_i915_gem_object *obj = intel_fb->obj;
9406 bool atomic_update;
9407 u32 start_vbl_count;
9408 u32 dspcntr;
9409 u32 reg;
9410
9411 intel_mark_page_flip_active(intel_crtc);
9412
9413 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9414
9415 reg = DSPCNTR(intel_crtc->plane);
9416 dspcntr = I915_READ(reg);
9417
9418 if (obj->tiling_mode != I915_TILING_NONE)
9419 dspcntr |= DISPPLANE_TILED;
9420 else
9421 dspcntr &= ~DISPPLANE_TILED;
9422
9423 I915_WRITE(reg, dspcntr);
9424
9425 I915_WRITE(DSPSURF(intel_crtc->plane),
9426 intel_crtc->unpin_work->gtt_offset);
9427 POSTING_READ(DSPSURF(intel_crtc->plane));
9428
9429 if (atomic_update)
9430 intel_pipe_update_end(intel_crtc, start_vbl_count);
9431 }
9432
9433 static void intel_mmio_flip_work_func(struct work_struct *work)
9434 {
9435 struct intel_crtc *intel_crtc =
9436 container_of(work, struct intel_crtc, mmio_flip.work);
9437 struct intel_engine_cs *ring;
9438 uint32_t seqno;
9439
9440 seqno = intel_crtc->mmio_flip.seqno;
9441 ring = intel_crtc->mmio_flip.ring;
9442
9443 if (seqno)
9444 WARN_ON(__i915_wait_seqno(ring, seqno,
9445 intel_crtc->reset_counter,
9446 false, NULL, NULL) != 0);
9447
9448 intel_do_mmio_flip(intel_crtc);
9449 }
9450
9451 static int intel_queue_mmio_flip(struct drm_device *dev,
9452 struct drm_crtc *crtc,
9453 struct drm_framebuffer *fb,
9454 struct drm_i915_gem_object *obj,
9455 struct intel_engine_cs *ring,
9456 uint32_t flags)
9457 {
9458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9459
9460 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9461 intel_crtc->mmio_flip.ring = obj->ring;
9462
9463 schedule_work(&intel_crtc->mmio_flip.work);
9464
9465 return 0;
9466 }
9467
9468 static int intel_default_queue_flip(struct drm_device *dev,
9469 struct drm_crtc *crtc,
9470 struct drm_framebuffer *fb,
9471 struct drm_i915_gem_object *obj,
9472 struct intel_engine_cs *ring,
9473 uint32_t flags)
9474 {
9475 return -ENODEV;
9476 }
9477
9478 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9479 struct drm_crtc *crtc)
9480 {
9481 struct drm_i915_private *dev_priv = dev->dev_private;
9482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9483 struct intel_unpin_work *work = intel_crtc->unpin_work;
9484 u32 addr;
9485
9486 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9487 return true;
9488
9489 if (!work->enable_stall_check)
9490 return false;
9491
9492 if (work->flip_ready_vblank == 0) {
9493 if (work->flip_queued_ring &&
9494 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9495 work->flip_queued_seqno))
9496 return false;
9497
9498 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9499 }
9500
9501 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9502 return false;
9503
9504 /* Potential stall - if we see that the flip has happened,
9505 * assume a missed interrupt. */
9506 if (INTEL_INFO(dev)->gen >= 4)
9507 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9508 else
9509 addr = I915_READ(DSPADDR(intel_crtc->plane));
9510
9511 /* There is a potential issue here with a false positive after a flip
9512 * to the same address. We could address this by checking for a
9513 * non-incrementing frame counter.
9514 */
9515 return addr == work->gtt_offset;
9516 }
9517
9518 void intel_check_page_flip(struct drm_device *dev, int pipe)
9519 {
9520 struct drm_i915_private *dev_priv = dev->dev_private;
9521 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9523
9524 WARN_ON(!in_irq());
9525
9526 if (crtc == NULL)
9527 return;
9528
9529 spin_lock(&dev->event_lock);
9530 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9531 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9532 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9533 page_flip_completed(intel_crtc);
9534 }
9535 spin_unlock(&dev->event_lock);
9536 }
9537
9538 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9539 struct drm_framebuffer *fb,
9540 struct drm_pending_vblank_event *event,
9541 uint32_t page_flip_flags)
9542 {
9543 struct drm_device *dev = crtc->dev;
9544 struct drm_i915_private *dev_priv = dev->dev_private;
9545 struct drm_framebuffer *old_fb = crtc->primary->fb;
9546 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9548 enum pipe pipe = intel_crtc->pipe;
9549 struct intel_unpin_work *work;
9550 struct intel_engine_cs *ring;
9551 int ret;
9552
9553 /*
9554 * drm_mode_page_flip_ioctl() should already catch this, but double
9555 * check to be safe. In the future we may enable pageflipping from
9556 * a disabled primary plane.
9557 */
9558 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9559 return -EBUSY;
9560
9561 /* Can't change pixel format via MI display flips. */
9562 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9563 return -EINVAL;
9564
9565 /*
9566 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9567 * Note that pitch changes could also affect these register.
9568 */
9569 if (INTEL_INFO(dev)->gen > 3 &&
9570 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9571 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9572 return -EINVAL;
9573
9574 if (i915_terminally_wedged(&dev_priv->gpu_error))
9575 goto out_hang;
9576
9577 work = kzalloc(sizeof(*work), GFP_KERNEL);
9578 if (work == NULL)
9579 return -ENOMEM;
9580
9581 work->event = event;
9582 work->crtc = crtc;
9583 work->old_fb_obj = intel_fb_obj(old_fb);
9584 INIT_WORK(&work->work, intel_unpin_work_fn);
9585
9586 ret = drm_crtc_vblank_get(crtc);
9587 if (ret)
9588 goto free_work;
9589
9590 /* We borrow the event spin lock for protecting unpin_work */
9591 spin_lock_irq(&dev->event_lock);
9592 if (intel_crtc->unpin_work) {
9593 /* Before declaring the flip queue wedged, check if
9594 * the hardware completed the operation behind our backs.
9595 */
9596 if (__intel_pageflip_stall_check(dev, crtc)) {
9597 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9598 page_flip_completed(intel_crtc);
9599 } else {
9600 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9601 spin_unlock_irq(&dev->event_lock);
9602
9603 drm_crtc_vblank_put(crtc);
9604 kfree(work);
9605 return -EBUSY;
9606 }
9607 }
9608 intel_crtc->unpin_work = work;
9609 spin_unlock_irq(&dev->event_lock);
9610
9611 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9612 flush_workqueue(dev_priv->wq);
9613
9614 ret = i915_mutex_lock_interruptible(dev);
9615 if (ret)
9616 goto cleanup;
9617
9618 /* Reference the objects for the scheduled work. */
9619 drm_gem_object_reference(&work->old_fb_obj->base);
9620 drm_gem_object_reference(&obj->base);
9621
9622 crtc->primary->fb = fb;
9623
9624 work->pending_flip_obj = obj;
9625
9626 atomic_inc(&intel_crtc->unpin_work_count);
9627 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9628
9629 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9630 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9631
9632 if (IS_VALLEYVIEW(dev)) {
9633 ring = &dev_priv->ring[BCS];
9634 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9635 /* vlv: DISPLAY_FLIP fails to change tiling */
9636 ring = NULL;
9637 } else if (IS_IVYBRIDGE(dev)) {
9638 ring = &dev_priv->ring[BCS];
9639 } else if (INTEL_INFO(dev)->gen >= 7) {
9640 ring = obj->ring;
9641 if (ring == NULL || ring->id != RCS)
9642 ring = &dev_priv->ring[BCS];
9643 } else {
9644 ring = &dev_priv->ring[RCS];
9645 }
9646
9647 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9648 if (ret)
9649 goto cleanup_pending;
9650
9651 work->gtt_offset =
9652 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9653
9654 if (use_mmio_flip(ring, obj)) {
9655 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9656 page_flip_flags);
9657 if (ret)
9658 goto cleanup_unpin;
9659
9660 work->flip_queued_seqno = obj->last_write_seqno;
9661 work->flip_queued_ring = obj->ring;
9662 } else {
9663 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9664 page_flip_flags);
9665 if (ret)
9666 goto cleanup_unpin;
9667
9668 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9669 work->flip_queued_ring = ring;
9670 }
9671
9672 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9673 work->enable_stall_check = true;
9674
9675 i915_gem_track_fb(work->old_fb_obj, obj,
9676 INTEL_FRONTBUFFER_PRIMARY(pipe));
9677
9678 intel_disable_fbc(dev);
9679 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9680 mutex_unlock(&dev->struct_mutex);
9681
9682 trace_i915_flip_request(intel_crtc->plane, obj);
9683
9684 return 0;
9685
9686 cleanup_unpin:
9687 intel_unpin_fb_obj(obj);
9688 cleanup_pending:
9689 atomic_dec(&intel_crtc->unpin_work_count);
9690 crtc->primary->fb = old_fb;
9691 drm_gem_object_unreference(&work->old_fb_obj->base);
9692 drm_gem_object_unreference(&obj->base);
9693 mutex_unlock(&dev->struct_mutex);
9694
9695 cleanup:
9696 spin_lock_irq(&dev->event_lock);
9697 intel_crtc->unpin_work = NULL;
9698 spin_unlock_irq(&dev->event_lock);
9699
9700 drm_crtc_vblank_put(crtc);
9701 free_work:
9702 kfree(work);
9703
9704 if (ret == -EIO) {
9705 out_hang:
9706 intel_crtc_wait_for_pending_flips(crtc);
9707 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9708 if (ret == 0 && event) {
9709 spin_lock_irq(&dev->event_lock);
9710 drm_send_vblank_event(dev, pipe, event);
9711 spin_unlock_irq(&dev->event_lock);
9712 }
9713 }
9714 return ret;
9715 }
9716
9717 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9718 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9719 .load_lut = intel_crtc_load_lut,
9720 };
9721
9722 /**
9723 * intel_modeset_update_staged_output_state
9724 *
9725 * Updates the staged output configuration state, e.g. after we've read out the
9726 * current hw state.
9727 */
9728 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9729 {
9730 struct intel_crtc *crtc;
9731 struct intel_encoder *encoder;
9732 struct intel_connector *connector;
9733
9734 list_for_each_entry(connector, &dev->mode_config.connector_list,
9735 base.head) {
9736 connector->new_encoder =
9737 to_intel_encoder(connector->base.encoder);
9738 }
9739
9740 for_each_intel_encoder(dev, encoder) {
9741 encoder->new_crtc =
9742 to_intel_crtc(encoder->base.crtc);
9743 }
9744
9745 for_each_intel_crtc(dev, crtc) {
9746 crtc->new_enabled = crtc->base.enabled;
9747
9748 if (crtc->new_enabled)
9749 crtc->new_config = &crtc->config;
9750 else
9751 crtc->new_config = NULL;
9752 }
9753 }
9754
9755 /**
9756 * intel_modeset_commit_output_state
9757 *
9758 * This function copies the stage display pipe configuration to the real one.
9759 */
9760 static void intel_modeset_commit_output_state(struct drm_device *dev)
9761 {
9762 struct intel_crtc *crtc;
9763 struct intel_encoder *encoder;
9764 struct intel_connector *connector;
9765
9766 list_for_each_entry(connector, &dev->mode_config.connector_list,
9767 base.head) {
9768 connector->base.encoder = &connector->new_encoder->base;
9769 }
9770
9771 for_each_intel_encoder(dev, encoder) {
9772 encoder->base.crtc = &encoder->new_crtc->base;
9773 }
9774
9775 for_each_intel_crtc(dev, crtc) {
9776 crtc->base.enabled = crtc->new_enabled;
9777 }
9778 }
9779
9780 static void
9781 connected_sink_compute_bpp(struct intel_connector *connector,
9782 struct intel_crtc_config *pipe_config)
9783 {
9784 int bpp = pipe_config->pipe_bpp;
9785
9786 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9787 connector->base.base.id,
9788 connector->base.name);
9789
9790 /* Don't use an invalid EDID bpc value */
9791 if (connector->base.display_info.bpc &&
9792 connector->base.display_info.bpc * 3 < bpp) {
9793 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9794 bpp, connector->base.display_info.bpc*3);
9795 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9796 }
9797
9798 /* Clamp bpp to 8 on screens without EDID 1.4 */
9799 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9800 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9801 bpp);
9802 pipe_config->pipe_bpp = 24;
9803 }
9804 }
9805
9806 static int
9807 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9808 struct drm_framebuffer *fb,
9809 struct intel_crtc_config *pipe_config)
9810 {
9811 struct drm_device *dev = crtc->base.dev;
9812 struct intel_connector *connector;
9813 int bpp;
9814
9815 switch (fb->pixel_format) {
9816 case DRM_FORMAT_C8:
9817 bpp = 8*3; /* since we go through a colormap */
9818 break;
9819 case DRM_FORMAT_XRGB1555:
9820 case DRM_FORMAT_ARGB1555:
9821 /* checked in intel_framebuffer_init already */
9822 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9823 return -EINVAL;
9824 case DRM_FORMAT_RGB565:
9825 bpp = 6*3; /* min is 18bpp */
9826 break;
9827 case DRM_FORMAT_XBGR8888:
9828 case DRM_FORMAT_ABGR8888:
9829 /* checked in intel_framebuffer_init already */
9830 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9831 return -EINVAL;
9832 case DRM_FORMAT_XRGB8888:
9833 case DRM_FORMAT_ARGB8888:
9834 bpp = 8*3;
9835 break;
9836 case DRM_FORMAT_XRGB2101010:
9837 case DRM_FORMAT_ARGB2101010:
9838 case DRM_FORMAT_XBGR2101010:
9839 case DRM_FORMAT_ABGR2101010:
9840 /* checked in intel_framebuffer_init already */
9841 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9842 return -EINVAL;
9843 bpp = 10*3;
9844 break;
9845 /* TODO: gen4+ supports 16 bpc floating point, too. */
9846 default:
9847 DRM_DEBUG_KMS("unsupported depth\n");
9848 return -EINVAL;
9849 }
9850
9851 pipe_config->pipe_bpp = bpp;
9852
9853 /* Clamp display bpp to EDID value */
9854 list_for_each_entry(connector, &dev->mode_config.connector_list,
9855 base.head) {
9856 if (!connector->new_encoder ||
9857 connector->new_encoder->new_crtc != crtc)
9858 continue;
9859
9860 connected_sink_compute_bpp(connector, pipe_config);
9861 }
9862
9863 return bpp;
9864 }
9865
9866 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9867 {
9868 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9869 "type: 0x%x flags: 0x%x\n",
9870 mode->crtc_clock,
9871 mode->crtc_hdisplay, mode->crtc_hsync_start,
9872 mode->crtc_hsync_end, mode->crtc_htotal,
9873 mode->crtc_vdisplay, mode->crtc_vsync_start,
9874 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9875 }
9876
9877 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9878 struct intel_crtc_config *pipe_config,
9879 const char *context)
9880 {
9881 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9882 context, pipe_name(crtc->pipe));
9883
9884 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9885 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9886 pipe_config->pipe_bpp, pipe_config->dither);
9887 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9888 pipe_config->has_pch_encoder,
9889 pipe_config->fdi_lanes,
9890 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9891 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9892 pipe_config->fdi_m_n.tu);
9893 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9894 pipe_config->has_dp_encoder,
9895 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9896 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9897 pipe_config->dp_m_n.tu);
9898
9899 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9900 pipe_config->has_dp_encoder,
9901 pipe_config->dp_m2_n2.gmch_m,
9902 pipe_config->dp_m2_n2.gmch_n,
9903 pipe_config->dp_m2_n2.link_m,
9904 pipe_config->dp_m2_n2.link_n,
9905 pipe_config->dp_m2_n2.tu);
9906
9907 DRM_DEBUG_KMS("requested mode:\n");
9908 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9909 DRM_DEBUG_KMS("adjusted mode:\n");
9910 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9911 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9912 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9913 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9914 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9915 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9916 pipe_config->gmch_pfit.control,
9917 pipe_config->gmch_pfit.pgm_ratios,
9918 pipe_config->gmch_pfit.lvds_border_bits);
9919 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9920 pipe_config->pch_pfit.pos,
9921 pipe_config->pch_pfit.size,
9922 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9923 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9924 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9925 }
9926
9927 static bool encoders_cloneable(const struct intel_encoder *a,
9928 const struct intel_encoder *b)
9929 {
9930 /* masks could be asymmetric, so check both ways */
9931 return a == b || (a->cloneable & (1 << b->type) &&
9932 b->cloneable & (1 << a->type));
9933 }
9934
9935 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9936 struct intel_encoder *encoder)
9937 {
9938 struct drm_device *dev = crtc->base.dev;
9939 struct intel_encoder *source_encoder;
9940
9941 for_each_intel_encoder(dev, source_encoder) {
9942 if (source_encoder->new_crtc != crtc)
9943 continue;
9944
9945 if (!encoders_cloneable(encoder, source_encoder))
9946 return false;
9947 }
9948
9949 return true;
9950 }
9951
9952 static bool check_encoder_cloning(struct intel_crtc *crtc)
9953 {
9954 struct drm_device *dev = crtc->base.dev;
9955 struct intel_encoder *encoder;
9956
9957 for_each_intel_encoder(dev, encoder) {
9958 if (encoder->new_crtc != crtc)
9959 continue;
9960
9961 if (!check_single_encoder_cloning(crtc, encoder))
9962 return false;
9963 }
9964
9965 return true;
9966 }
9967
9968 static struct intel_crtc_config *
9969 intel_modeset_pipe_config(struct drm_crtc *crtc,
9970 struct drm_framebuffer *fb,
9971 struct drm_display_mode *mode)
9972 {
9973 struct drm_device *dev = crtc->dev;
9974 struct intel_encoder *encoder;
9975 struct intel_crtc_config *pipe_config;
9976 int plane_bpp, ret = -EINVAL;
9977 bool retry = true;
9978
9979 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9980 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9981 return ERR_PTR(-EINVAL);
9982 }
9983
9984 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9985 if (!pipe_config)
9986 return ERR_PTR(-ENOMEM);
9987
9988 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9989 drm_mode_copy(&pipe_config->requested_mode, mode);
9990
9991 pipe_config->cpu_transcoder =
9992 (enum transcoder) to_intel_crtc(crtc)->pipe;
9993 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9994
9995 /*
9996 * Sanitize sync polarity flags based on requested ones. If neither
9997 * positive or negative polarity is requested, treat this as meaning
9998 * negative polarity.
9999 */
10000 if (!(pipe_config->adjusted_mode.flags &
10001 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10002 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10003
10004 if (!(pipe_config->adjusted_mode.flags &
10005 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10006 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10007
10008 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10009 * plane pixel format and any sink constraints into account. Returns the
10010 * source plane bpp so that dithering can be selected on mismatches
10011 * after encoders and crtc also have had their say. */
10012 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10013 fb, pipe_config);
10014 if (plane_bpp < 0)
10015 goto fail;
10016
10017 /*
10018 * Determine the real pipe dimensions. Note that stereo modes can
10019 * increase the actual pipe size due to the frame doubling and
10020 * insertion of additional space for blanks between the frame. This
10021 * is stored in the crtc timings. We use the requested mode to do this
10022 * computation to clearly distinguish it from the adjusted mode, which
10023 * can be changed by the connectors in the below retry loop.
10024 */
10025 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10026 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10027 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10028
10029 encoder_retry:
10030 /* Ensure the port clock defaults are reset when retrying. */
10031 pipe_config->port_clock = 0;
10032 pipe_config->pixel_multiplier = 1;
10033
10034 /* Fill in default crtc timings, allow encoders to overwrite them. */
10035 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10036
10037 /* Pass our mode to the connectors and the CRTC to give them a chance to
10038 * adjust it according to limitations or connector properties, and also
10039 * a chance to reject the mode entirely.
10040 */
10041 for_each_intel_encoder(dev, encoder) {
10042
10043 if (&encoder->new_crtc->base != crtc)
10044 continue;
10045
10046 if (!(encoder->compute_config(encoder, pipe_config))) {
10047 DRM_DEBUG_KMS("Encoder config failure\n");
10048 goto fail;
10049 }
10050 }
10051
10052 /* Set default port clock if not overwritten by the encoder. Needs to be
10053 * done afterwards in case the encoder adjusts the mode. */
10054 if (!pipe_config->port_clock)
10055 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10056 * pipe_config->pixel_multiplier;
10057
10058 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10059 if (ret < 0) {
10060 DRM_DEBUG_KMS("CRTC fixup failed\n");
10061 goto fail;
10062 }
10063
10064 if (ret == RETRY) {
10065 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10066 ret = -EINVAL;
10067 goto fail;
10068 }
10069
10070 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10071 retry = false;
10072 goto encoder_retry;
10073 }
10074
10075 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10076 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10077 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10078
10079 return pipe_config;
10080 fail:
10081 kfree(pipe_config);
10082 return ERR_PTR(ret);
10083 }
10084
10085 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10086 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10087 static void
10088 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10089 unsigned *prepare_pipes, unsigned *disable_pipes)
10090 {
10091 struct intel_crtc *intel_crtc;
10092 struct drm_device *dev = crtc->dev;
10093 struct intel_encoder *encoder;
10094 struct intel_connector *connector;
10095 struct drm_crtc *tmp_crtc;
10096
10097 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10098
10099 /* Check which crtcs have changed outputs connected to them, these need
10100 * to be part of the prepare_pipes mask. We don't (yet) support global
10101 * modeset across multiple crtcs, so modeset_pipes will only have one
10102 * bit set at most. */
10103 list_for_each_entry(connector, &dev->mode_config.connector_list,
10104 base.head) {
10105 if (connector->base.encoder == &connector->new_encoder->base)
10106 continue;
10107
10108 if (connector->base.encoder) {
10109 tmp_crtc = connector->base.encoder->crtc;
10110
10111 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10112 }
10113
10114 if (connector->new_encoder)
10115 *prepare_pipes |=
10116 1 << connector->new_encoder->new_crtc->pipe;
10117 }
10118
10119 for_each_intel_encoder(dev, encoder) {
10120 if (encoder->base.crtc == &encoder->new_crtc->base)
10121 continue;
10122
10123 if (encoder->base.crtc) {
10124 tmp_crtc = encoder->base.crtc;
10125
10126 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10127 }
10128
10129 if (encoder->new_crtc)
10130 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10131 }
10132
10133 /* Check for pipes that will be enabled/disabled ... */
10134 for_each_intel_crtc(dev, intel_crtc) {
10135 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10136 continue;
10137
10138 if (!intel_crtc->new_enabled)
10139 *disable_pipes |= 1 << intel_crtc->pipe;
10140 else
10141 *prepare_pipes |= 1 << intel_crtc->pipe;
10142 }
10143
10144
10145 /* set_mode is also used to update properties on life display pipes. */
10146 intel_crtc = to_intel_crtc(crtc);
10147 if (intel_crtc->new_enabled)
10148 *prepare_pipes |= 1 << intel_crtc->pipe;
10149
10150 /*
10151 * For simplicity do a full modeset on any pipe where the output routing
10152 * changed. We could be more clever, but that would require us to be
10153 * more careful with calling the relevant encoder->mode_set functions.
10154 */
10155 if (*prepare_pipes)
10156 *modeset_pipes = *prepare_pipes;
10157
10158 /* ... and mask these out. */
10159 *modeset_pipes &= ~(*disable_pipes);
10160 *prepare_pipes &= ~(*disable_pipes);
10161
10162 /*
10163 * HACK: We don't (yet) fully support global modesets. intel_set_config
10164 * obies this rule, but the modeset restore mode of
10165 * intel_modeset_setup_hw_state does not.
10166 */
10167 *modeset_pipes &= 1 << intel_crtc->pipe;
10168 *prepare_pipes &= 1 << intel_crtc->pipe;
10169
10170 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10171 *modeset_pipes, *prepare_pipes, *disable_pipes);
10172 }
10173
10174 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10175 {
10176 struct drm_encoder *encoder;
10177 struct drm_device *dev = crtc->dev;
10178
10179 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10180 if (encoder->crtc == crtc)
10181 return true;
10182
10183 return false;
10184 }
10185
10186 static void
10187 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10188 {
10189 struct drm_i915_private *dev_priv = dev->dev_private;
10190 struct intel_encoder *intel_encoder;
10191 struct intel_crtc *intel_crtc;
10192 struct drm_connector *connector;
10193
10194 intel_shared_dpll_commit(dev_priv);
10195
10196 for_each_intel_encoder(dev, intel_encoder) {
10197 if (!intel_encoder->base.crtc)
10198 continue;
10199
10200 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10201
10202 if (prepare_pipes & (1 << intel_crtc->pipe))
10203 intel_encoder->connectors_active = false;
10204 }
10205
10206 intel_modeset_commit_output_state(dev);
10207
10208 /* Double check state. */
10209 for_each_intel_crtc(dev, intel_crtc) {
10210 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10211 WARN_ON(intel_crtc->new_config &&
10212 intel_crtc->new_config != &intel_crtc->config);
10213 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10214 }
10215
10216 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10217 if (!connector->encoder || !connector->encoder->crtc)
10218 continue;
10219
10220 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10221
10222 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10223 struct drm_property *dpms_property =
10224 dev->mode_config.dpms_property;
10225
10226 connector->dpms = DRM_MODE_DPMS_ON;
10227 drm_object_property_set_value(&connector->base,
10228 dpms_property,
10229 DRM_MODE_DPMS_ON);
10230
10231 intel_encoder = to_intel_encoder(connector->encoder);
10232 intel_encoder->connectors_active = true;
10233 }
10234 }
10235
10236 }
10237
10238 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10239 {
10240 int diff;
10241
10242 if (clock1 == clock2)
10243 return true;
10244
10245 if (!clock1 || !clock2)
10246 return false;
10247
10248 diff = abs(clock1 - clock2);
10249
10250 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10251 return true;
10252
10253 return false;
10254 }
10255
10256 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10257 list_for_each_entry((intel_crtc), \
10258 &(dev)->mode_config.crtc_list, \
10259 base.head) \
10260 if (mask & (1 <<(intel_crtc)->pipe))
10261
10262 static bool
10263 intel_pipe_config_compare(struct drm_device *dev,
10264 struct intel_crtc_config *current_config,
10265 struct intel_crtc_config *pipe_config)
10266 {
10267 #define PIPE_CONF_CHECK_X(name) \
10268 if (current_config->name != pipe_config->name) { \
10269 DRM_ERROR("mismatch in " #name " " \
10270 "(expected 0x%08x, found 0x%08x)\n", \
10271 current_config->name, \
10272 pipe_config->name); \
10273 return false; \
10274 }
10275
10276 #define PIPE_CONF_CHECK_I(name) \
10277 if (current_config->name != pipe_config->name) { \
10278 DRM_ERROR("mismatch in " #name " " \
10279 "(expected %i, found %i)\n", \
10280 current_config->name, \
10281 pipe_config->name); \
10282 return false; \
10283 }
10284
10285 /* This is required for BDW+ where there is only one set of registers for
10286 * switching between high and low RR.
10287 * This macro can be used whenever a comparison has to be made between one
10288 * hw state and multiple sw state variables.
10289 */
10290 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10291 if ((current_config->name != pipe_config->name) && \
10292 (current_config->alt_name != pipe_config->name)) { \
10293 DRM_ERROR("mismatch in " #name " " \
10294 "(expected %i or %i, found %i)\n", \
10295 current_config->name, \
10296 current_config->alt_name, \
10297 pipe_config->name); \
10298 return false; \
10299 }
10300
10301 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10302 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10303 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10304 "(expected %i, found %i)\n", \
10305 current_config->name & (mask), \
10306 pipe_config->name & (mask)); \
10307 return false; \
10308 }
10309
10310 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10311 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10312 DRM_ERROR("mismatch in " #name " " \
10313 "(expected %i, found %i)\n", \
10314 current_config->name, \
10315 pipe_config->name); \
10316 return false; \
10317 }
10318
10319 #define PIPE_CONF_QUIRK(quirk) \
10320 ((current_config->quirks | pipe_config->quirks) & (quirk))
10321
10322 PIPE_CONF_CHECK_I(cpu_transcoder);
10323
10324 PIPE_CONF_CHECK_I(has_pch_encoder);
10325 PIPE_CONF_CHECK_I(fdi_lanes);
10326 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10327 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10328 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10329 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10330 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10331
10332 PIPE_CONF_CHECK_I(has_dp_encoder);
10333
10334 if (INTEL_INFO(dev)->gen < 8) {
10335 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10336 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10337 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10338 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10339 PIPE_CONF_CHECK_I(dp_m_n.tu);
10340
10341 if (current_config->has_drrs) {
10342 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10343 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10344 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10345 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10346 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10347 }
10348 } else {
10349 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10350 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10351 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10352 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10353 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10354 }
10355
10356 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10357 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10358 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10359 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10360 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10361 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10362
10363 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10364 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10365 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10366 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10367 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10368 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10369
10370 PIPE_CONF_CHECK_I(pixel_multiplier);
10371 PIPE_CONF_CHECK_I(has_hdmi_sink);
10372 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10373 IS_VALLEYVIEW(dev))
10374 PIPE_CONF_CHECK_I(limited_color_range);
10375
10376 PIPE_CONF_CHECK_I(has_audio);
10377
10378 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10379 DRM_MODE_FLAG_INTERLACE);
10380
10381 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10382 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10383 DRM_MODE_FLAG_PHSYNC);
10384 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10385 DRM_MODE_FLAG_NHSYNC);
10386 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10387 DRM_MODE_FLAG_PVSYNC);
10388 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10389 DRM_MODE_FLAG_NVSYNC);
10390 }
10391
10392 PIPE_CONF_CHECK_I(pipe_src_w);
10393 PIPE_CONF_CHECK_I(pipe_src_h);
10394
10395 /*
10396 * FIXME: BIOS likes to set up a cloned config with lvds+external
10397 * screen. Since we don't yet re-compute the pipe config when moving
10398 * just the lvds port away to another pipe the sw tracking won't match.
10399 *
10400 * Proper atomic modesets with recomputed global state will fix this.
10401 * Until then just don't check gmch state for inherited modes.
10402 */
10403 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10404 PIPE_CONF_CHECK_I(gmch_pfit.control);
10405 /* pfit ratios are autocomputed by the hw on gen4+ */
10406 if (INTEL_INFO(dev)->gen < 4)
10407 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10408 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10409 }
10410
10411 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10412 if (current_config->pch_pfit.enabled) {
10413 PIPE_CONF_CHECK_I(pch_pfit.pos);
10414 PIPE_CONF_CHECK_I(pch_pfit.size);
10415 }
10416
10417 /* BDW+ don't expose a synchronous way to read the state */
10418 if (IS_HASWELL(dev))
10419 PIPE_CONF_CHECK_I(ips_enabled);
10420
10421 PIPE_CONF_CHECK_I(double_wide);
10422
10423 PIPE_CONF_CHECK_X(ddi_pll_sel);
10424
10425 PIPE_CONF_CHECK_I(shared_dpll);
10426 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10427 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10428 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10429 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10430 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10431
10432 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10433 PIPE_CONF_CHECK_I(pipe_bpp);
10434
10435 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10436 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10437
10438 #undef PIPE_CONF_CHECK_X
10439 #undef PIPE_CONF_CHECK_I
10440 #undef PIPE_CONF_CHECK_I_ALT
10441 #undef PIPE_CONF_CHECK_FLAGS
10442 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10443 #undef PIPE_CONF_QUIRK
10444
10445 return true;
10446 }
10447
10448 static void check_wm_state(struct drm_device *dev)
10449 {
10450 struct drm_i915_private *dev_priv = dev->dev_private;
10451 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10452 struct intel_crtc *intel_crtc;
10453 int plane;
10454
10455 if (INTEL_INFO(dev)->gen < 9)
10456 return;
10457
10458 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10459 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10460
10461 for_each_intel_crtc(dev, intel_crtc) {
10462 struct skl_ddb_entry *hw_entry, *sw_entry;
10463 const enum pipe pipe = intel_crtc->pipe;
10464
10465 if (!intel_crtc->active)
10466 continue;
10467
10468 /* planes */
10469 for_each_plane(pipe, plane) {
10470 hw_entry = &hw_ddb.plane[pipe][plane];
10471 sw_entry = &sw_ddb->plane[pipe][plane];
10472
10473 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10474 continue;
10475
10476 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10477 "(expected (%u,%u), found (%u,%u))\n",
10478 pipe_name(pipe), plane + 1,
10479 sw_entry->start, sw_entry->end,
10480 hw_entry->start, hw_entry->end);
10481 }
10482
10483 /* cursor */
10484 hw_entry = &hw_ddb.cursor[pipe];
10485 sw_entry = &sw_ddb->cursor[pipe];
10486
10487 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10488 continue;
10489
10490 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10491 "(expected (%u,%u), found (%u,%u))\n",
10492 pipe_name(pipe),
10493 sw_entry->start, sw_entry->end,
10494 hw_entry->start, hw_entry->end);
10495 }
10496 }
10497
10498 static void
10499 check_connector_state(struct drm_device *dev)
10500 {
10501 struct intel_connector *connector;
10502
10503 list_for_each_entry(connector, &dev->mode_config.connector_list,
10504 base.head) {
10505 /* This also checks the encoder/connector hw state with the
10506 * ->get_hw_state callbacks. */
10507 intel_connector_check_state(connector);
10508
10509 WARN(&connector->new_encoder->base != connector->base.encoder,
10510 "connector's staged encoder doesn't match current encoder\n");
10511 }
10512 }
10513
10514 static void
10515 check_encoder_state(struct drm_device *dev)
10516 {
10517 struct intel_encoder *encoder;
10518 struct intel_connector *connector;
10519
10520 for_each_intel_encoder(dev, encoder) {
10521 bool enabled = false;
10522 bool active = false;
10523 enum pipe pipe, tracked_pipe;
10524
10525 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10526 encoder->base.base.id,
10527 encoder->base.name);
10528
10529 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10530 "encoder's stage crtc doesn't match current crtc\n");
10531 WARN(encoder->connectors_active && !encoder->base.crtc,
10532 "encoder's active_connectors set, but no crtc\n");
10533
10534 list_for_each_entry(connector, &dev->mode_config.connector_list,
10535 base.head) {
10536 if (connector->base.encoder != &encoder->base)
10537 continue;
10538 enabled = true;
10539 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10540 active = true;
10541 }
10542 /*
10543 * for MST connectors if we unplug the connector is gone
10544 * away but the encoder is still connected to a crtc
10545 * until a modeset happens in response to the hotplug.
10546 */
10547 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10548 continue;
10549
10550 WARN(!!encoder->base.crtc != enabled,
10551 "encoder's enabled state mismatch "
10552 "(expected %i, found %i)\n",
10553 !!encoder->base.crtc, enabled);
10554 WARN(active && !encoder->base.crtc,
10555 "active encoder with no crtc\n");
10556
10557 WARN(encoder->connectors_active != active,
10558 "encoder's computed active state doesn't match tracked active state "
10559 "(expected %i, found %i)\n", active, encoder->connectors_active);
10560
10561 active = encoder->get_hw_state(encoder, &pipe);
10562 WARN(active != encoder->connectors_active,
10563 "encoder's hw state doesn't match sw tracking "
10564 "(expected %i, found %i)\n",
10565 encoder->connectors_active, active);
10566
10567 if (!encoder->base.crtc)
10568 continue;
10569
10570 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10571 WARN(active && pipe != tracked_pipe,
10572 "active encoder's pipe doesn't match"
10573 "(expected %i, found %i)\n",
10574 tracked_pipe, pipe);
10575
10576 }
10577 }
10578
10579 static void
10580 check_crtc_state(struct drm_device *dev)
10581 {
10582 struct drm_i915_private *dev_priv = dev->dev_private;
10583 struct intel_crtc *crtc;
10584 struct intel_encoder *encoder;
10585 struct intel_crtc_config pipe_config;
10586
10587 for_each_intel_crtc(dev, crtc) {
10588 bool enabled = false;
10589 bool active = false;
10590
10591 memset(&pipe_config, 0, sizeof(pipe_config));
10592
10593 DRM_DEBUG_KMS("[CRTC:%d]\n",
10594 crtc->base.base.id);
10595
10596 WARN(crtc->active && !crtc->base.enabled,
10597 "active crtc, but not enabled in sw tracking\n");
10598
10599 for_each_intel_encoder(dev, encoder) {
10600 if (encoder->base.crtc != &crtc->base)
10601 continue;
10602 enabled = true;
10603 if (encoder->connectors_active)
10604 active = true;
10605 }
10606
10607 WARN(active != crtc->active,
10608 "crtc's computed active state doesn't match tracked active state "
10609 "(expected %i, found %i)\n", active, crtc->active);
10610 WARN(enabled != crtc->base.enabled,
10611 "crtc's computed enabled state doesn't match tracked enabled state "
10612 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10613
10614 active = dev_priv->display.get_pipe_config(crtc,
10615 &pipe_config);
10616
10617 /* hw state is inconsistent with the pipe quirk */
10618 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10619 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10620 active = crtc->active;
10621
10622 for_each_intel_encoder(dev, encoder) {
10623 enum pipe pipe;
10624 if (encoder->base.crtc != &crtc->base)
10625 continue;
10626 if (encoder->get_hw_state(encoder, &pipe))
10627 encoder->get_config(encoder, &pipe_config);
10628 }
10629
10630 WARN(crtc->active != active,
10631 "crtc active state doesn't match with hw state "
10632 "(expected %i, found %i)\n", crtc->active, active);
10633
10634 if (active &&
10635 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10636 WARN(1, "pipe state doesn't match!\n");
10637 intel_dump_pipe_config(crtc, &pipe_config,
10638 "[hw state]");
10639 intel_dump_pipe_config(crtc, &crtc->config,
10640 "[sw state]");
10641 }
10642 }
10643 }
10644
10645 static void
10646 check_shared_dpll_state(struct drm_device *dev)
10647 {
10648 struct drm_i915_private *dev_priv = dev->dev_private;
10649 struct intel_crtc *crtc;
10650 struct intel_dpll_hw_state dpll_hw_state;
10651 int i;
10652
10653 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10654 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10655 int enabled_crtcs = 0, active_crtcs = 0;
10656 bool active;
10657
10658 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10659
10660 DRM_DEBUG_KMS("%s\n", pll->name);
10661
10662 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10663
10664 WARN(pll->active > hweight32(pll->config.crtc_mask),
10665 "more active pll users than references: %i vs %i\n",
10666 pll->active, hweight32(pll->config.crtc_mask));
10667 WARN(pll->active && !pll->on,
10668 "pll in active use but not on in sw tracking\n");
10669 WARN(pll->on && !pll->active,
10670 "pll in on but not on in use in sw tracking\n");
10671 WARN(pll->on != active,
10672 "pll on state mismatch (expected %i, found %i)\n",
10673 pll->on, active);
10674
10675 for_each_intel_crtc(dev, crtc) {
10676 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10677 enabled_crtcs++;
10678 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10679 active_crtcs++;
10680 }
10681 WARN(pll->active != active_crtcs,
10682 "pll active crtcs mismatch (expected %i, found %i)\n",
10683 pll->active, active_crtcs);
10684 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10685 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10686 hweight32(pll->config.crtc_mask), enabled_crtcs);
10687
10688 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10689 sizeof(dpll_hw_state)),
10690 "pll hw state mismatch\n");
10691 }
10692 }
10693
10694 void
10695 intel_modeset_check_state(struct drm_device *dev)
10696 {
10697 check_wm_state(dev);
10698 check_connector_state(dev);
10699 check_encoder_state(dev);
10700 check_crtc_state(dev);
10701 check_shared_dpll_state(dev);
10702 }
10703
10704 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10705 int dotclock)
10706 {
10707 /*
10708 * FDI already provided one idea for the dotclock.
10709 * Yell if the encoder disagrees.
10710 */
10711 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10712 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10713 pipe_config->adjusted_mode.crtc_clock, dotclock);
10714 }
10715
10716 static void update_scanline_offset(struct intel_crtc *crtc)
10717 {
10718 struct drm_device *dev = crtc->base.dev;
10719
10720 /*
10721 * The scanline counter increments at the leading edge of hsync.
10722 *
10723 * On most platforms it starts counting from vtotal-1 on the
10724 * first active line. That means the scanline counter value is
10725 * always one less than what we would expect. Ie. just after
10726 * start of vblank, which also occurs at start of hsync (on the
10727 * last active line), the scanline counter will read vblank_start-1.
10728 *
10729 * On gen2 the scanline counter starts counting from 1 instead
10730 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10731 * to keep the value positive), instead of adding one.
10732 *
10733 * On HSW+ the behaviour of the scanline counter depends on the output
10734 * type. For DP ports it behaves like most other platforms, but on HDMI
10735 * there's an extra 1 line difference. So we need to add two instead of
10736 * one to the value.
10737 */
10738 if (IS_GEN2(dev)) {
10739 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10740 int vtotal;
10741
10742 vtotal = mode->crtc_vtotal;
10743 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10744 vtotal /= 2;
10745
10746 crtc->scanline_offset = vtotal - 1;
10747 } else if (HAS_DDI(dev) &&
10748 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10749 crtc->scanline_offset = 2;
10750 } else
10751 crtc->scanline_offset = 1;
10752 }
10753
10754 static int __intel_set_mode(struct drm_crtc *crtc,
10755 struct drm_display_mode *mode,
10756 int x, int y, struct drm_framebuffer *fb)
10757 {
10758 struct drm_device *dev = crtc->dev;
10759 struct drm_i915_private *dev_priv = dev->dev_private;
10760 struct drm_display_mode *saved_mode;
10761 struct intel_crtc_config *pipe_config = NULL;
10762 struct intel_crtc *intel_crtc;
10763 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10764 int ret = 0;
10765
10766 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10767 if (!saved_mode)
10768 return -ENOMEM;
10769
10770 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10771 &prepare_pipes, &disable_pipes);
10772
10773 *saved_mode = crtc->mode;
10774
10775 /* Hack: Because we don't (yet) support global modeset on multiple
10776 * crtcs, we don't keep track of the new mode for more than one crtc.
10777 * Hence simply check whether any bit is set in modeset_pipes in all the
10778 * pieces of code that are not yet converted to deal with mutliple crtcs
10779 * changing their mode at the same time. */
10780 if (modeset_pipes) {
10781 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10782 if (IS_ERR(pipe_config)) {
10783 ret = PTR_ERR(pipe_config);
10784 pipe_config = NULL;
10785
10786 goto out;
10787 }
10788 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10789 "[modeset]");
10790 to_intel_crtc(crtc)->new_config = pipe_config;
10791 }
10792
10793 /*
10794 * See if the config requires any additional preparation, e.g.
10795 * to adjust global state with pipes off. We need to do this
10796 * here so we can get the modeset_pipe updated config for the new
10797 * mode set on this crtc. For other crtcs we need to use the
10798 * adjusted_mode bits in the crtc directly.
10799 */
10800 if (IS_VALLEYVIEW(dev)) {
10801 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10802
10803 /* may have added more to prepare_pipes than we should */
10804 prepare_pipes &= ~disable_pipes;
10805 }
10806
10807 if (dev_priv->display.crtc_compute_clock) {
10808 unsigned clear_pipes = modeset_pipes | disable_pipes;
10809
10810 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10811 if (ret)
10812 goto done;
10813
10814 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10815 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10816 if (ret) {
10817 intel_shared_dpll_abort_config(dev_priv);
10818 goto done;
10819 }
10820 }
10821 }
10822
10823 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10824 intel_crtc_disable(&intel_crtc->base);
10825
10826 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10827 if (intel_crtc->base.enabled)
10828 dev_priv->display.crtc_disable(&intel_crtc->base);
10829 }
10830
10831 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10832 * to set it here already despite that we pass it down the callchain.
10833 */
10834 if (modeset_pipes) {
10835 crtc->mode = *mode;
10836 /* mode_set/enable/disable functions rely on a correct pipe
10837 * config. */
10838 to_intel_crtc(crtc)->config = *pipe_config;
10839 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10840
10841 /*
10842 * Calculate and store various constants which
10843 * are later needed by vblank and swap-completion
10844 * timestamping. They are derived from true hwmode.
10845 */
10846 drm_calc_timestamping_constants(crtc,
10847 &pipe_config->adjusted_mode);
10848 }
10849
10850 /* Only after disabling all output pipelines that will be changed can we
10851 * update the the output configuration. */
10852 intel_modeset_update_state(dev, prepare_pipes);
10853
10854 modeset_update_crtc_power_domains(dev);
10855
10856 /* Set up the DPLL and any encoders state that needs to adjust or depend
10857 * on the DPLL.
10858 */
10859 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10860 struct drm_framebuffer *old_fb = crtc->primary->fb;
10861 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10862 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10863
10864 mutex_lock(&dev->struct_mutex);
10865 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
10866 if (ret != 0) {
10867 DRM_ERROR("pin & fence failed\n");
10868 mutex_unlock(&dev->struct_mutex);
10869 goto done;
10870 }
10871 if (old_fb)
10872 intel_unpin_fb_obj(old_obj);
10873 i915_gem_track_fb(old_obj, obj,
10874 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10875 mutex_unlock(&dev->struct_mutex);
10876
10877 crtc->primary->fb = fb;
10878 crtc->x = x;
10879 crtc->y = y;
10880 }
10881
10882 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10883 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10884 update_scanline_offset(intel_crtc);
10885
10886 dev_priv->display.crtc_enable(&intel_crtc->base);
10887 }
10888
10889 /* FIXME: add subpixel order */
10890 done:
10891 if (ret && crtc->enabled)
10892 crtc->mode = *saved_mode;
10893
10894 out:
10895 kfree(pipe_config);
10896 kfree(saved_mode);
10897 return ret;
10898 }
10899
10900 static int intel_set_mode(struct drm_crtc *crtc,
10901 struct drm_display_mode *mode,
10902 int x, int y, struct drm_framebuffer *fb)
10903 {
10904 int ret;
10905
10906 ret = __intel_set_mode(crtc, mode, x, y, fb);
10907
10908 if (ret == 0)
10909 intel_modeset_check_state(crtc->dev);
10910
10911 return ret;
10912 }
10913
10914 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10915 {
10916 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10917 }
10918
10919 #undef for_each_intel_crtc_masked
10920
10921 static void intel_set_config_free(struct intel_set_config *config)
10922 {
10923 if (!config)
10924 return;
10925
10926 kfree(config->save_connector_encoders);
10927 kfree(config->save_encoder_crtcs);
10928 kfree(config->save_crtc_enabled);
10929 kfree(config);
10930 }
10931
10932 static int intel_set_config_save_state(struct drm_device *dev,
10933 struct intel_set_config *config)
10934 {
10935 struct drm_crtc *crtc;
10936 struct drm_encoder *encoder;
10937 struct drm_connector *connector;
10938 int count;
10939
10940 config->save_crtc_enabled =
10941 kcalloc(dev->mode_config.num_crtc,
10942 sizeof(bool), GFP_KERNEL);
10943 if (!config->save_crtc_enabled)
10944 return -ENOMEM;
10945
10946 config->save_encoder_crtcs =
10947 kcalloc(dev->mode_config.num_encoder,
10948 sizeof(struct drm_crtc *), GFP_KERNEL);
10949 if (!config->save_encoder_crtcs)
10950 return -ENOMEM;
10951
10952 config->save_connector_encoders =
10953 kcalloc(dev->mode_config.num_connector,
10954 sizeof(struct drm_encoder *), GFP_KERNEL);
10955 if (!config->save_connector_encoders)
10956 return -ENOMEM;
10957
10958 /* Copy data. Note that driver private data is not affected.
10959 * Should anything bad happen only the expected state is
10960 * restored, not the drivers personal bookkeeping.
10961 */
10962 count = 0;
10963 for_each_crtc(dev, crtc) {
10964 config->save_crtc_enabled[count++] = crtc->enabled;
10965 }
10966
10967 count = 0;
10968 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10969 config->save_encoder_crtcs[count++] = encoder->crtc;
10970 }
10971
10972 count = 0;
10973 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10974 config->save_connector_encoders[count++] = connector->encoder;
10975 }
10976
10977 return 0;
10978 }
10979
10980 static void intel_set_config_restore_state(struct drm_device *dev,
10981 struct intel_set_config *config)
10982 {
10983 struct intel_crtc *crtc;
10984 struct intel_encoder *encoder;
10985 struct intel_connector *connector;
10986 int count;
10987
10988 count = 0;
10989 for_each_intel_crtc(dev, crtc) {
10990 crtc->new_enabled = config->save_crtc_enabled[count++];
10991
10992 if (crtc->new_enabled)
10993 crtc->new_config = &crtc->config;
10994 else
10995 crtc->new_config = NULL;
10996 }
10997
10998 count = 0;
10999 for_each_intel_encoder(dev, encoder) {
11000 encoder->new_crtc =
11001 to_intel_crtc(config->save_encoder_crtcs[count++]);
11002 }
11003
11004 count = 0;
11005 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11006 connector->new_encoder =
11007 to_intel_encoder(config->save_connector_encoders[count++]);
11008 }
11009 }
11010
11011 static bool
11012 is_crtc_connector_off(struct drm_mode_set *set)
11013 {
11014 int i;
11015
11016 if (set->num_connectors == 0)
11017 return false;
11018
11019 if (WARN_ON(set->connectors == NULL))
11020 return false;
11021
11022 for (i = 0; i < set->num_connectors; i++)
11023 if (set->connectors[i]->encoder &&
11024 set->connectors[i]->encoder->crtc == set->crtc &&
11025 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11026 return true;
11027
11028 return false;
11029 }
11030
11031 static void
11032 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11033 struct intel_set_config *config)
11034 {
11035
11036 /* We should be able to check here if the fb has the same properties
11037 * and then just flip_or_move it */
11038 if (is_crtc_connector_off(set)) {
11039 config->mode_changed = true;
11040 } else if (set->crtc->primary->fb != set->fb) {
11041 /*
11042 * If we have no fb, we can only flip as long as the crtc is
11043 * active, otherwise we need a full mode set. The crtc may
11044 * be active if we've only disabled the primary plane, or
11045 * in fastboot situations.
11046 */
11047 if (set->crtc->primary->fb == NULL) {
11048 struct intel_crtc *intel_crtc =
11049 to_intel_crtc(set->crtc);
11050
11051 if (intel_crtc->active) {
11052 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11053 config->fb_changed = true;
11054 } else {
11055 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11056 config->mode_changed = true;
11057 }
11058 } else if (set->fb == NULL) {
11059 config->mode_changed = true;
11060 } else if (set->fb->pixel_format !=
11061 set->crtc->primary->fb->pixel_format) {
11062 config->mode_changed = true;
11063 } else {
11064 config->fb_changed = true;
11065 }
11066 }
11067
11068 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11069 config->fb_changed = true;
11070
11071 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11072 DRM_DEBUG_KMS("modes are different, full mode set\n");
11073 drm_mode_debug_printmodeline(&set->crtc->mode);
11074 drm_mode_debug_printmodeline(set->mode);
11075 config->mode_changed = true;
11076 }
11077
11078 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11079 set->crtc->base.id, config->mode_changed, config->fb_changed);
11080 }
11081
11082 static int
11083 intel_modeset_stage_output_state(struct drm_device *dev,
11084 struct drm_mode_set *set,
11085 struct intel_set_config *config)
11086 {
11087 struct intel_connector *connector;
11088 struct intel_encoder *encoder;
11089 struct intel_crtc *crtc;
11090 int ro;
11091
11092 /* The upper layers ensure that we either disable a crtc or have a list
11093 * of connectors. For paranoia, double-check this. */
11094 WARN_ON(!set->fb && (set->num_connectors != 0));
11095 WARN_ON(set->fb && (set->num_connectors == 0));
11096
11097 list_for_each_entry(connector, &dev->mode_config.connector_list,
11098 base.head) {
11099 /* Otherwise traverse passed in connector list and get encoders
11100 * for them. */
11101 for (ro = 0; ro < set->num_connectors; ro++) {
11102 if (set->connectors[ro] == &connector->base) {
11103 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11104 break;
11105 }
11106 }
11107
11108 /* If we disable the crtc, disable all its connectors. Also, if
11109 * the connector is on the changing crtc but not on the new
11110 * connector list, disable it. */
11111 if ((!set->fb || ro == set->num_connectors) &&
11112 connector->base.encoder &&
11113 connector->base.encoder->crtc == set->crtc) {
11114 connector->new_encoder = NULL;
11115
11116 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11117 connector->base.base.id,
11118 connector->base.name);
11119 }
11120
11121
11122 if (&connector->new_encoder->base != connector->base.encoder) {
11123 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11124 config->mode_changed = true;
11125 }
11126 }
11127 /* connector->new_encoder is now updated for all connectors. */
11128
11129 /* Update crtc of enabled connectors. */
11130 list_for_each_entry(connector, &dev->mode_config.connector_list,
11131 base.head) {
11132 struct drm_crtc *new_crtc;
11133
11134 if (!connector->new_encoder)
11135 continue;
11136
11137 new_crtc = connector->new_encoder->base.crtc;
11138
11139 for (ro = 0; ro < set->num_connectors; ro++) {
11140 if (set->connectors[ro] == &connector->base)
11141 new_crtc = set->crtc;
11142 }
11143
11144 /* Make sure the new CRTC will work with the encoder */
11145 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11146 new_crtc)) {
11147 return -EINVAL;
11148 }
11149 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11150
11151 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11152 connector->base.base.id,
11153 connector->base.name,
11154 new_crtc->base.id);
11155 }
11156
11157 /* Check for any encoders that needs to be disabled. */
11158 for_each_intel_encoder(dev, encoder) {
11159 int num_connectors = 0;
11160 list_for_each_entry(connector,
11161 &dev->mode_config.connector_list,
11162 base.head) {
11163 if (connector->new_encoder == encoder) {
11164 WARN_ON(!connector->new_encoder->new_crtc);
11165 num_connectors++;
11166 }
11167 }
11168
11169 if (num_connectors == 0)
11170 encoder->new_crtc = NULL;
11171 else if (num_connectors > 1)
11172 return -EINVAL;
11173
11174 /* Only now check for crtc changes so we don't miss encoders
11175 * that will be disabled. */
11176 if (&encoder->new_crtc->base != encoder->base.crtc) {
11177 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11178 config->mode_changed = true;
11179 }
11180 }
11181 /* Now we've also updated encoder->new_crtc for all encoders. */
11182 list_for_each_entry(connector, &dev->mode_config.connector_list,
11183 base.head) {
11184 if (connector->new_encoder)
11185 if (connector->new_encoder != connector->encoder)
11186 connector->encoder = connector->new_encoder;
11187 }
11188 for_each_intel_crtc(dev, crtc) {
11189 crtc->new_enabled = false;
11190
11191 for_each_intel_encoder(dev, encoder) {
11192 if (encoder->new_crtc == crtc) {
11193 crtc->new_enabled = true;
11194 break;
11195 }
11196 }
11197
11198 if (crtc->new_enabled != crtc->base.enabled) {
11199 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11200 crtc->new_enabled ? "en" : "dis");
11201 config->mode_changed = true;
11202 }
11203
11204 if (crtc->new_enabled)
11205 crtc->new_config = &crtc->config;
11206 else
11207 crtc->new_config = NULL;
11208 }
11209
11210 return 0;
11211 }
11212
11213 static void disable_crtc_nofb(struct intel_crtc *crtc)
11214 {
11215 struct drm_device *dev = crtc->base.dev;
11216 struct intel_encoder *encoder;
11217 struct intel_connector *connector;
11218
11219 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11220 pipe_name(crtc->pipe));
11221
11222 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11223 if (connector->new_encoder &&
11224 connector->new_encoder->new_crtc == crtc)
11225 connector->new_encoder = NULL;
11226 }
11227
11228 for_each_intel_encoder(dev, encoder) {
11229 if (encoder->new_crtc == crtc)
11230 encoder->new_crtc = NULL;
11231 }
11232
11233 crtc->new_enabled = false;
11234 crtc->new_config = NULL;
11235 }
11236
11237 static int intel_crtc_set_config(struct drm_mode_set *set)
11238 {
11239 struct drm_device *dev;
11240 struct drm_mode_set save_set;
11241 struct intel_set_config *config;
11242 int ret;
11243
11244 BUG_ON(!set);
11245 BUG_ON(!set->crtc);
11246 BUG_ON(!set->crtc->helper_private);
11247
11248 /* Enforce sane interface api - has been abused by the fb helper. */
11249 BUG_ON(!set->mode && set->fb);
11250 BUG_ON(set->fb && set->num_connectors == 0);
11251
11252 if (set->fb) {
11253 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11254 set->crtc->base.id, set->fb->base.id,
11255 (int)set->num_connectors, set->x, set->y);
11256 } else {
11257 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11258 }
11259
11260 dev = set->crtc->dev;
11261
11262 ret = -ENOMEM;
11263 config = kzalloc(sizeof(*config), GFP_KERNEL);
11264 if (!config)
11265 goto out_config;
11266
11267 ret = intel_set_config_save_state(dev, config);
11268 if (ret)
11269 goto out_config;
11270
11271 save_set.crtc = set->crtc;
11272 save_set.mode = &set->crtc->mode;
11273 save_set.x = set->crtc->x;
11274 save_set.y = set->crtc->y;
11275 save_set.fb = set->crtc->primary->fb;
11276
11277 /* Compute whether we need a full modeset, only an fb base update or no
11278 * change at all. In the future we might also check whether only the
11279 * mode changed, e.g. for LVDS where we only change the panel fitter in
11280 * such cases. */
11281 intel_set_config_compute_mode_changes(set, config);
11282
11283 ret = intel_modeset_stage_output_state(dev, set, config);
11284 if (ret)
11285 goto fail;
11286
11287 if (config->mode_changed) {
11288 ret = intel_set_mode(set->crtc, set->mode,
11289 set->x, set->y, set->fb);
11290 } else if (config->fb_changed) {
11291 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11292
11293 intel_crtc_wait_for_pending_flips(set->crtc);
11294
11295 ret = intel_pipe_set_base(set->crtc,
11296 set->x, set->y, set->fb);
11297
11298 /*
11299 * We need to make sure the primary plane is re-enabled if it
11300 * has previously been turned off.
11301 */
11302 if (!intel_crtc->primary_enabled && ret == 0) {
11303 WARN_ON(!intel_crtc->active);
11304 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11305 }
11306
11307 /*
11308 * In the fastboot case this may be our only check of the
11309 * state after boot. It would be better to only do it on
11310 * the first update, but we don't have a nice way of doing that
11311 * (and really, set_config isn't used much for high freq page
11312 * flipping, so increasing its cost here shouldn't be a big
11313 * deal).
11314 */
11315 if (i915.fastboot && ret == 0)
11316 intel_modeset_check_state(set->crtc->dev);
11317 }
11318
11319 if (ret) {
11320 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11321 set->crtc->base.id, ret);
11322 fail:
11323 intel_set_config_restore_state(dev, config);
11324
11325 /*
11326 * HACK: if the pipe was on, but we didn't have a framebuffer,
11327 * force the pipe off to avoid oopsing in the modeset code
11328 * due to fb==NULL. This should only happen during boot since
11329 * we don't yet reconstruct the FB from the hardware state.
11330 */
11331 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11332 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11333
11334 /* Try to restore the config */
11335 if (config->mode_changed &&
11336 intel_set_mode(save_set.crtc, save_set.mode,
11337 save_set.x, save_set.y, save_set.fb))
11338 DRM_ERROR("failed to restore config after modeset failure\n");
11339 }
11340
11341 out_config:
11342 intel_set_config_free(config);
11343 return ret;
11344 }
11345
11346 static const struct drm_crtc_funcs intel_crtc_funcs = {
11347 .gamma_set = intel_crtc_gamma_set,
11348 .set_config = intel_crtc_set_config,
11349 .destroy = intel_crtc_destroy,
11350 .page_flip = intel_crtc_page_flip,
11351 };
11352
11353 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11354 struct intel_shared_dpll *pll,
11355 struct intel_dpll_hw_state *hw_state)
11356 {
11357 uint32_t val;
11358
11359 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11360 return false;
11361
11362 val = I915_READ(PCH_DPLL(pll->id));
11363 hw_state->dpll = val;
11364 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11365 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11366
11367 return val & DPLL_VCO_ENABLE;
11368 }
11369
11370 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11371 struct intel_shared_dpll *pll)
11372 {
11373 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11374 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11375 }
11376
11377 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11378 struct intel_shared_dpll *pll)
11379 {
11380 /* PCH refclock must be enabled first */
11381 ibx_assert_pch_refclk_enabled(dev_priv);
11382
11383 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11384
11385 /* Wait for the clocks to stabilize. */
11386 POSTING_READ(PCH_DPLL(pll->id));
11387 udelay(150);
11388
11389 /* The pixel multiplier can only be updated once the
11390 * DPLL is enabled and the clocks are stable.
11391 *
11392 * So write it again.
11393 */
11394 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11395 POSTING_READ(PCH_DPLL(pll->id));
11396 udelay(200);
11397 }
11398
11399 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11400 struct intel_shared_dpll *pll)
11401 {
11402 struct drm_device *dev = dev_priv->dev;
11403 struct intel_crtc *crtc;
11404
11405 /* Make sure no transcoder isn't still depending on us. */
11406 for_each_intel_crtc(dev, crtc) {
11407 if (intel_crtc_to_shared_dpll(crtc) == pll)
11408 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11409 }
11410
11411 I915_WRITE(PCH_DPLL(pll->id), 0);
11412 POSTING_READ(PCH_DPLL(pll->id));
11413 udelay(200);
11414 }
11415
11416 static char *ibx_pch_dpll_names[] = {
11417 "PCH DPLL A",
11418 "PCH DPLL B",
11419 };
11420
11421 static void ibx_pch_dpll_init(struct drm_device *dev)
11422 {
11423 struct drm_i915_private *dev_priv = dev->dev_private;
11424 int i;
11425
11426 dev_priv->num_shared_dpll = 2;
11427
11428 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11429 dev_priv->shared_dplls[i].id = i;
11430 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11431 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11432 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11433 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11434 dev_priv->shared_dplls[i].get_hw_state =
11435 ibx_pch_dpll_get_hw_state;
11436 }
11437 }
11438
11439 static void intel_shared_dpll_init(struct drm_device *dev)
11440 {
11441 struct drm_i915_private *dev_priv = dev->dev_private;
11442
11443 if (HAS_DDI(dev))
11444 intel_ddi_pll_init(dev);
11445 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11446 ibx_pch_dpll_init(dev);
11447 else
11448 dev_priv->num_shared_dpll = 0;
11449
11450 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11451 }
11452
11453 static int
11454 intel_primary_plane_disable(struct drm_plane *plane)
11455 {
11456 struct drm_device *dev = plane->dev;
11457 struct intel_crtc *intel_crtc;
11458
11459 if (!plane->fb)
11460 return 0;
11461
11462 BUG_ON(!plane->crtc);
11463
11464 intel_crtc = to_intel_crtc(plane->crtc);
11465
11466 /*
11467 * Even though we checked plane->fb above, it's still possible that
11468 * the primary plane has been implicitly disabled because the crtc
11469 * coordinates given weren't visible, or because we detected
11470 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11471 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11472 * In either case, we need to unpin the FB and let the fb pointer get
11473 * updated, but otherwise we don't need to touch the hardware.
11474 */
11475 if (!intel_crtc->primary_enabled)
11476 goto disable_unpin;
11477
11478 intel_crtc_wait_for_pending_flips(plane->crtc);
11479 intel_disable_primary_hw_plane(plane, plane->crtc);
11480
11481 disable_unpin:
11482 mutex_lock(&dev->struct_mutex);
11483 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11484 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11485 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11486 mutex_unlock(&dev->struct_mutex);
11487 plane->fb = NULL;
11488
11489 return 0;
11490 }
11491
11492 static int
11493 intel_check_primary_plane(struct drm_plane *plane,
11494 struct intel_plane_state *state)
11495 {
11496 struct drm_crtc *crtc = state->crtc;
11497 struct drm_framebuffer *fb = state->fb;
11498 struct drm_rect *dest = &state->dst;
11499 struct drm_rect *src = &state->src;
11500 const struct drm_rect *clip = &state->clip;
11501
11502 return drm_plane_helper_check_update(plane, crtc, fb,
11503 src, dest, clip,
11504 DRM_PLANE_HELPER_NO_SCALING,
11505 DRM_PLANE_HELPER_NO_SCALING,
11506 false, true, &state->visible);
11507 }
11508
11509 static int
11510 intel_prepare_primary_plane(struct drm_plane *plane,
11511 struct intel_plane_state *state)
11512 {
11513 struct drm_crtc *crtc = state->crtc;
11514 struct drm_framebuffer *fb = state->fb;
11515 struct drm_device *dev = crtc->dev;
11516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11517 enum pipe pipe = intel_crtc->pipe;
11518 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11519 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11520 int ret;
11521
11522 intel_crtc_wait_for_pending_flips(crtc);
11523
11524 if (intel_crtc_has_pending_flip(crtc)) {
11525 DRM_ERROR("pipe is still busy with an old pageflip\n");
11526 return -EBUSY;
11527 }
11528
11529 if (old_obj != obj) {
11530 mutex_lock(&dev->struct_mutex);
11531 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11532 if (ret == 0)
11533 i915_gem_track_fb(old_obj, obj,
11534 INTEL_FRONTBUFFER_PRIMARY(pipe));
11535 mutex_unlock(&dev->struct_mutex);
11536 if (ret != 0) {
11537 DRM_DEBUG_KMS("pin & fence failed\n");
11538 return ret;
11539 }
11540 }
11541
11542 return 0;
11543 }
11544
11545 static void
11546 intel_commit_primary_plane(struct drm_plane *plane,
11547 struct intel_plane_state *state)
11548 {
11549 struct drm_crtc *crtc = state->crtc;
11550 struct drm_framebuffer *fb = state->fb;
11551 struct drm_device *dev = crtc->dev;
11552 struct drm_i915_private *dev_priv = dev->dev_private;
11553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11554 enum pipe pipe = intel_crtc->pipe;
11555 struct drm_framebuffer *old_fb = plane->fb;
11556 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11557 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11558 struct intel_plane *intel_plane = to_intel_plane(plane);
11559 struct drm_rect *src = &state->src;
11560
11561 crtc->primary->fb = fb;
11562 crtc->x = src->x1;
11563 crtc->y = src->y1;
11564
11565 intel_plane->crtc_x = state->orig_dst.x1;
11566 intel_plane->crtc_y = state->orig_dst.y1;
11567 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11568 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11569 intel_plane->src_x = state->orig_src.x1;
11570 intel_plane->src_y = state->orig_src.y1;
11571 intel_plane->src_w = drm_rect_width(&state->orig_src);
11572 intel_plane->src_h = drm_rect_height(&state->orig_src);
11573 intel_plane->obj = obj;
11574
11575 if (intel_crtc->active) {
11576 /*
11577 * FBC does not work on some platforms for rotated
11578 * planes, so disable it when rotation is not 0 and
11579 * update it when rotation is set back to 0.
11580 *
11581 * FIXME: This is redundant with the fbc update done in
11582 * the primary plane enable function except that that
11583 * one is done too late. We eventually need to unify
11584 * this.
11585 */
11586 if (intel_crtc->primary_enabled &&
11587 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11588 dev_priv->fbc.plane == intel_crtc->plane &&
11589 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11590 intel_disable_fbc(dev);
11591 }
11592
11593 if (state->visible) {
11594 bool was_enabled = intel_crtc->primary_enabled;
11595
11596 /* FIXME: kill this fastboot hack */
11597 intel_update_pipe_size(intel_crtc);
11598
11599 intel_crtc->primary_enabled = true;
11600
11601 dev_priv->display.update_primary_plane(crtc, plane->fb,
11602 crtc->x, crtc->y);
11603
11604 /*
11605 * BDW signals flip done immediately if the plane
11606 * is disabled, even if the plane enable is already
11607 * armed to occur at the next vblank :(
11608 */
11609 if (IS_BROADWELL(dev) && !was_enabled)
11610 intel_wait_for_vblank(dev, intel_crtc->pipe);
11611 } else {
11612 /*
11613 * If clipping results in a non-visible primary plane,
11614 * we'll disable the primary plane. Note that this is
11615 * a bit different than what happens if userspace
11616 * explicitly disables the plane by passing fb=0
11617 * because plane->fb still gets set and pinned.
11618 */
11619 intel_disable_primary_hw_plane(plane, crtc);
11620 }
11621
11622 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11623
11624 mutex_lock(&dev->struct_mutex);
11625 intel_update_fbc(dev);
11626 mutex_unlock(&dev->struct_mutex);
11627 }
11628
11629 if (old_fb && old_fb != fb) {
11630 if (intel_crtc->active)
11631 intel_wait_for_vblank(dev, intel_crtc->pipe);
11632
11633 mutex_lock(&dev->struct_mutex);
11634 intel_unpin_fb_obj(old_obj);
11635 mutex_unlock(&dev->struct_mutex);
11636 }
11637 }
11638
11639 static int
11640 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11641 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11642 unsigned int crtc_w, unsigned int crtc_h,
11643 uint32_t src_x, uint32_t src_y,
11644 uint32_t src_w, uint32_t src_h)
11645 {
11646 struct intel_plane_state state;
11647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11648 int ret;
11649
11650 state.crtc = crtc;
11651 state.fb = fb;
11652
11653 /* sample coordinates in 16.16 fixed point */
11654 state.src.x1 = src_x;
11655 state.src.x2 = src_x + src_w;
11656 state.src.y1 = src_y;
11657 state.src.y2 = src_y + src_h;
11658
11659 /* integer pixels */
11660 state.dst.x1 = crtc_x;
11661 state.dst.x2 = crtc_x + crtc_w;
11662 state.dst.y1 = crtc_y;
11663 state.dst.y2 = crtc_y + crtc_h;
11664
11665 state.clip.x1 = 0;
11666 state.clip.y1 = 0;
11667 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11668 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11669
11670 state.orig_src = state.src;
11671 state.orig_dst = state.dst;
11672
11673 ret = intel_check_primary_plane(plane, &state);
11674 if (ret)
11675 return ret;
11676
11677 ret = intel_prepare_primary_plane(plane, &state);
11678 if (ret)
11679 return ret;
11680
11681 intel_commit_primary_plane(plane, &state);
11682
11683 return 0;
11684 }
11685
11686 /* Common destruction function for both primary and cursor planes */
11687 static void intel_plane_destroy(struct drm_plane *plane)
11688 {
11689 struct intel_plane *intel_plane = to_intel_plane(plane);
11690 drm_plane_cleanup(plane);
11691 kfree(intel_plane);
11692 }
11693
11694 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11695 .update_plane = intel_primary_plane_setplane,
11696 .disable_plane = intel_primary_plane_disable,
11697 .destroy = intel_plane_destroy,
11698 .set_property = intel_plane_set_property
11699 };
11700
11701 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11702 int pipe)
11703 {
11704 struct intel_plane *primary;
11705 const uint32_t *intel_primary_formats;
11706 int num_formats;
11707
11708 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11709 if (primary == NULL)
11710 return NULL;
11711
11712 primary->can_scale = false;
11713 primary->max_downscale = 1;
11714 primary->pipe = pipe;
11715 primary->plane = pipe;
11716 primary->rotation = BIT(DRM_ROTATE_0);
11717 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11718 primary->plane = !pipe;
11719
11720 if (INTEL_INFO(dev)->gen <= 3) {
11721 intel_primary_formats = intel_primary_formats_gen2;
11722 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11723 } else {
11724 intel_primary_formats = intel_primary_formats_gen4;
11725 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11726 }
11727
11728 drm_universal_plane_init(dev, &primary->base, 0,
11729 &intel_primary_plane_funcs,
11730 intel_primary_formats, num_formats,
11731 DRM_PLANE_TYPE_PRIMARY);
11732
11733 if (INTEL_INFO(dev)->gen >= 4) {
11734 if (!dev->mode_config.rotation_property)
11735 dev->mode_config.rotation_property =
11736 drm_mode_create_rotation_property(dev,
11737 BIT(DRM_ROTATE_0) |
11738 BIT(DRM_ROTATE_180));
11739 if (dev->mode_config.rotation_property)
11740 drm_object_attach_property(&primary->base.base,
11741 dev->mode_config.rotation_property,
11742 primary->rotation);
11743 }
11744
11745 return &primary->base;
11746 }
11747
11748 static int
11749 intel_cursor_plane_disable(struct drm_plane *plane)
11750 {
11751 if (!plane->fb)
11752 return 0;
11753
11754 BUG_ON(!plane->crtc);
11755
11756 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11757 }
11758
11759 static int
11760 intel_check_cursor_plane(struct drm_plane *plane,
11761 struct intel_plane_state *state)
11762 {
11763 struct drm_crtc *crtc = state->crtc;
11764 struct drm_device *dev = crtc->dev;
11765 struct drm_framebuffer *fb = state->fb;
11766 struct drm_rect *dest = &state->dst;
11767 struct drm_rect *src = &state->src;
11768 const struct drm_rect *clip = &state->clip;
11769 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11770 int crtc_w, crtc_h;
11771 unsigned stride;
11772 int ret;
11773
11774 ret = drm_plane_helper_check_update(plane, crtc, fb,
11775 src, dest, clip,
11776 DRM_PLANE_HELPER_NO_SCALING,
11777 DRM_PLANE_HELPER_NO_SCALING,
11778 true, true, &state->visible);
11779 if (ret)
11780 return ret;
11781
11782
11783 /* if we want to turn off the cursor ignore width and height */
11784 if (!obj)
11785 return 0;
11786
11787 /* Check for which cursor types we support */
11788 crtc_w = drm_rect_width(&state->orig_dst);
11789 crtc_h = drm_rect_height(&state->orig_dst);
11790 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11791 DRM_DEBUG("Cursor dimension not supported\n");
11792 return -EINVAL;
11793 }
11794
11795 stride = roundup_pow_of_two(crtc_w) * 4;
11796 if (obj->base.size < stride * crtc_h) {
11797 DRM_DEBUG_KMS("buffer is too small\n");
11798 return -ENOMEM;
11799 }
11800
11801 if (fb == crtc->cursor->fb)
11802 return 0;
11803
11804 /* we only need to pin inside GTT if cursor is non-phy */
11805 mutex_lock(&dev->struct_mutex);
11806 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11807 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11808 ret = -EINVAL;
11809 }
11810 mutex_unlock(&dev->struct_mutex);
11811
11812 return ret;
11813 }
11814
11815 static int
11816 intel_commit_cursor_plane(struct drm_plane *plane,
11817 struct intel_plane_state *state)
11818 {
11819 struct drm_crtc *crtc = state->crtc;
11820 struct drm_framebuffer *fb = state->fb;
11821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11822 struct intel_plane *intel_plane = to_intel_plane(plane);
11823 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11824 struct drm_i915_gem_object *obj = intel_fb->obj;
11825 int crtc_w, crtc_h;
11826
11827 crtc->cursor_x = state->orig_dst.x1;
11828 crtc->cursor_y = state->orig_dst.y1;
11829
11830 intel_plane->crtc_x = state->orig_dst.x1;
11831 intel_plane->crtc_y = state->orig_dst.y1;
11832 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11833 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11834 intel_plane->src_x = state->orig_src.x1;
11835 intel_plane->src_y = state->orig_src.y1;
11836 intel_plane->src_w = drm_rect_width(&state->orig_src);
11837 intel_plane->src_h = drm_rect_height(&state->orig_src);
11838 intel_plane->obj = obj;
11839
11840 if (fb != crtc->cursor->fb) {
11841 crtc_w = drm_rect_width(&state->orig_dst);
11842 crtc_h = drm_rect_height(&state->orig_dst);
11843 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11844 } else {
11845 intel_crtc_update_cursor(crtc, state->visible);
11846
11847 intel_frontbuffer_flip(crtc->dev,
11848 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11849
11850 return 0;
11851 }
11852 }
11853
11854 static int
11855 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11856 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11857 unsigned int crtc_w, unsigned int crtc_h,
11858 uint32_t src_x, uint32_t src_y,
11859 uint32_t src_w, uint32_t src_h)
11860 {
11861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11862 struct intel_plane_state state;
11863 int ret;
11864
11865 state.crtc = crtc;
11866 state.fb = fb;
11867
11868 /* sample coordinates in 16.16 fixed point */
11869 state.src.x1 = src_x;
11870 state.src.x2 = src_x + src_w;
11871 state.src.y1 = src_y;
11872 state.src.y2 = src_y + src_h;
11873
11874 /* integer pixels */
11875 state.dst.x1 = crtc_x;
11876 state.dst.x2 = crtc_x + crtc_w;
11877 state.dst.y1 = crtc_y;
11878 state.dst.y2 = crtc_y + crtc_h;
11879
11880 state.clip.x1 = 0;
11881 state.clip.y1 = 0;
11882 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11883 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11884
11885 state.orig_src = state.src;
11886 state.orig_dst = state.dst;
11887
11888 ret = intel_check_cursor_plane(plane, &state);
11889 if (ret)
11890 return ret;
11891
11892 return intel_commit_cursor_plane(plane, &state);
11893 }
11894
11895 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11896 .update_plane = intel_cursor_plane_update,
11897 .disable_plane = intel_cursor_plane_disable,
11898 .destroy = intel_plane_destroy,
11899 .set_property = intel_plane_set_property,
11900 };
11901
11902 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11903 int pipe)
11904 {
11905 struct intel_plane *cursor;
11906
11907 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11908 if (cursor == NULL)
11909 return NULL;
11910
11911 cursor->can_scale = false;
11912 cursor->max_downscale = 1;
11913 cursor->pipe = pipe;
11914 cursor->plane = pipe;
11915 cursor->rotation = BIT(DRM_ROTATE_0);
11916
11917 drm_universal_plane_init(dev, &cursor->base, 0,
11918 &intel_cursor_plane_funcs,
11919 intel_cursor_formats,
11920 ARRAY_SIZE(intel_cursor_formats),
11921 DRM_PLANE_TYPE_CURSOR);
11922
11923 if (INTEL_INFO(dev)->gen >= 4) {
11924 if (!dev->mode_config.rotation_property)
11925 dev->mode_config.rotation_property =
11926 drm_mode_create_rotation_property(dev,
11927 BIT(DRM_ROTATE_0) |
11928 BIT(DRM_ROTATE_180));
11929 if (dev->mode_config.rotation_property)
11930 drm_object_attach_property(&cursor->base.base,
11931 dev->mode_config.rotation_property,
11932 cursor->rotation);
11933 }
11934
11935 return &cursor->base;
11936 }
11937
11938 static void intel_crtc_init(struct drm_device *dev, int pipe)
11939 {
11940 struct drm_i915_private *dev_priv = dev->dev_private;
11941 struct intel_crtc *intel_crtc;
11942 struct drm_plane *primary = NULL;
11943 struct drm_plane *cursor = NULL;
11944 int i, ret;
11945
11946 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11947 if (intel_crtc == NULL)
11948 return;
11949
11950 primary = intel_primary_plane_create(dev, pipe);
11951 if (!primary)
11952 goto fail;
11953
11954 cursor = intel_cursor_plane_create(dev, pipe);
11955 if (!cursor)
11956 goto fail;
11957
11958 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11959 cursor, &intel_crtc_funcs);
11960 if (ret)
11961 goto fail;
11962
11963 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11964 for (i = 0; i < 256; i++) {
11965 intel_crtc->lut_r[i] = i;
11966 intel_crtc->lut_g[i] = i;
11967 intel_crtc->lut_b[i] = i;
11968 }
11969
11970 /*
11971 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11972 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11973 */
11974 intel_crtc->pipe = pipe;
11975 intel_crtc->plane = pipe;
11976 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11977 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11978 intel_crtc->plane = !pipe;
11979 }
11980
11981 intel_crtc->cursor_base = ~0;
11982 intel_crtc->cursor_cntl = ~0;
11983 intel_crtc->cursor_size = ~0;
11984
11985 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11986 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11987 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11988 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11989
11990 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
11991
11992 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11993
11994 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11995 return;
11996
11997 fail:
11998 if (primary)
11999 drm_plane_cleanup(primary);
12000 if (cursor)
12001 drm_plane_cleanup(cursor);
12002 kfree(intel_crtc);
12003 }
12004
12005 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12006 {
12007 struct drm_encoder *encoder = connector->base.encoder;
12008 struct drm_device *dev = connector->base.dev;
12009
12010 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12011
12012 if (!encoder)
12013 return INVALID_PIPE;
12014
12015 return to_intel_crtc(encoder->crtc)->pipe;
12016 }
12017
12018 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12019 struct drm_file *file)
12020 {
12021 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12022 struct drm_crtc *drmmode_crtc;
12023 struct intel_crtc *crtc;
12024
12025 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12026 return -ENODEV;
12027
12028 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12029
12030 if (!drmmode_crtc) {
12031 DRM_ERROR("no such CRTC id\n");
12032 return -ENOENT;
12033 }
12034
12035 crtc = to_intel_crtc(drmmode_crtc);
12036 pipe_from_crtc_id->pipe = crtc->pipe;
12037
12038 return 0;
12039 }
12040
12041 static int intel_encoder_clones(struct intel_encoder *encoder)
12042 {
12043 struct drm_device *dev = encoder->base.dev;
12044 struct intel_encoder *source_encoder;
12045 int index_mask = 0;
12046 int entry = 0;
12047
12048 for_each_intel_encoder(dev, source_encoder) {
12049 if (encoders_cloneable(encoder, source_encoder))
12050 index_mask |= (1 << entry);
12051
12052 entry++;
12053 }
12054
12055 return index_mask;
12056 }
12057
12058 static bool has_edp_a(struct drm_device *dev)
12059 {
12060 struct drm_i915_private *dev_priv = dev->dev_private;
12061
12062 if (!IS_MOBILE(dev))
12063 return false;
12064
12065 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12066 return false;
12067
12068 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12069 return false;
12070
12071 return true;
12072 }
12073
12074 const char *intel_output_name(int output)
12075 {
12076 static const char *names[] = {
12077 [INTEL_OUTPUT_UNUSED] = "Unused",
12078 [INTEL_OUTPUT_ANALOG] = "Analog",
12079 [INTEL_OUTPUT_DVO] = "DVO",
12080 [INTEL_OUTPUT_SDVO] = "SDVO",
12081 [INTEL_OUTPUT_LVDS] = "LVDS",
12082 [INTEL_OUTPUT_TVOUT] = "TV",
12083 [INTEL_OUTPUT_HDMI] = "HDMI",
12084 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12085 [INTEL_OUTPUT_EDP] = "eDP",
12086 [INTEL_OUTPUT_DSI] = "DSI",
12087 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12088 };
12089
12090 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12091 return "Invalid";
12092
12093 return names[output];
12094 }
12095
12096 static bool intel_crt_present(struct drm_device *dev)
12097 {
12098 struct drm_i915_private *dev_priv = dev->dev_private;
12099
12100 if (INTEL_INFO(dev)->gen >= 9)
12101 return false;
12102
12103 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12104 return false;
12105
12106 if (IS_CHERRYVIEW(dev))
12107 return false;
12108
12109 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12110 return false;
12111
12112 return true;
12113 }
12114
12115 static void intel_setup_outputs(struct drm_device *dev)
12116 {
12117 struct drm_i915_private *dev_priv = dev->dev_private;
12118 struct intel_encoder *encoder;
12119 bool dpd_is_edp = false;
12120
12121 intel_lvds_init(dev);
12122
12123 if (intel_crt_present(dev))
12124 intel_crt_init(dev);
12125
12126 if (HAS_DDI(dev)) {
12127 int found;
12128
12129 /* Haswell uses DDI functions to detect digital outputs */
12130 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12131 /* DDI A only supports eDP */
12132 if (found)
12133 intel_ddi_init(dev, PORT_A);
12134
12135 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12136 * register */
12137 found = I915_READ(SFUSE_STRAP);
12138
12139 if (found & SFUSE_STRAP_DDIB_DETECTED)
12140 intel_ddi_init(dev, PORT_B);
12141 if (found & SFUSE_STRAP_DDIC_DETECTED)
12142 intel_ddi_init(dev, PORT_C);
12143 if (found & SFUSE_STRAP_DDID_DETECTED)
12144 intel_ddi_init(dev, PORT_D);
12145 } else if (HAS_PCH_SPLIT(dev)) {
12146 int found;
12147 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12148
12149 if (has_edp_a(dev))
12150 intel_dp_init(dev, DP_A, PORT_A);
12151
12152 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12153 /* PCH SDVOB multiplex with HDMIB */
12154 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12155 if (!found)
12156 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12157 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12158 intel_dp_init(dev, PCH_DP_B, PORT_B);
12159 }
12160
12161 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12162 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12163
12164 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12165 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12166
12167 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12168 intel_dp_init(dev, PCH_DP_C, PORT_C);
12169
12170 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12171 intel_dp_init(dev, PCH_DP_D, PORT_D);
12172 } else if (IS_VALLEYVIEW(dev)) {
12173 /*
12174 * The DP_DETECTED bit is the latched state of the DDC
12175 * SDA pin at boot. However since eDP doesn't require DDC
12176 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12177 * eDP ports may have been muxed to an alternate function.
12178 * Thus we can't rely on the DP_DETECTED bit alone to detect
12179 * eDP ports. Consult the VBT as well as DP_DETECTED to
12180 * detect eDP ports.
12181 */
12182 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12183 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12184 PORT_B);
12185 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12186 intel_dp_is_edp(dev, PORT_B))
12187 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12188
12189 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12190 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12191 PORT_C);
12192 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12193 intel_dp_is_edp(dev, PORT_C))
12194 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12195
12196 if (IS_CHERRYVIEW(dev)) {
12197 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12198 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12199 PORT_D);
12200 /* eDP not supported on port D, so don't check VBT */
12201 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12202 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12203 }
12204
12205 intel_dsi_init(dev);
12206 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12207 bool found = false;
12208
12209 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12210 DRM_DEBUG_KMS("probing SDVOB\n");
12211 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12212 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12213 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12214 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12215 }
12216
12217 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12218 intel_dp_init(dev, DP_B, PORT_B);
12219 }
12220
12221 /* Before G4X SDVOC doesn't have its own detect register */
12222
12223 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12224 DRM_DEBUG_KMS("probing SDVOC\n");
12225 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12226 }
12227
12228 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12229
12230 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12231 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12232 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12233 }
12234 if (SUPPORTS_INTEGRATED_DP(dev))
12235 intel_dp_init(dev, DP_C, PORT_C);
12236 }
12237
12238 if (SUPPORTS_INTEGRATED_DP(dev) &&
12239 (I915_READ(DP_D) & DP_DETECTED))
12240 intel_dp_init(dev, DP_D, PORT_D);
12241 } else if (IS_GEN2(dev))
12242 intel_dvo_init(dev);
12243
12244 if (SUPPORTS_TV(dev))
12245 intel_tv_init(dev);
12246
12247 intel_edp_psr_init(dev);
12248
12249 for_each_intel_encoder(dev, encoder) {
12250 encoder->base.possible_crtcs = encoder->crtc_mask;
12251 encoder->base.possible_clones =
12252 intel_encoder_clones(encoder);
12253 }
12254
12255 intel_init_pch_refclk(dev);
12256
12257 drm_helper_move_panel_connectors_to_head(dev);
12258 }
12259
12260 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12261 {
12262 struct drm_device *dev = fb->dev;
12263 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12264
12265 drm_framebuffer_cleanup(fb);
12266 mutex_lock(&dev->struct_mutex);
12267 WARN_ON(!intel_fb->obj->framebuffer_references--);
12268 drm_gem_object_unreference(&intel_fb->obj->base);
12269 mutex_unlock(&dev->struct_mutex);
12270 kfree(intel_fb);
12271 }
12272
12273 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12274 struct drm_file *file,
12275 unsigned int *handle)
12276 {
12277 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12278 struct drm_i915_gem_object *obj = intel_fb->obj;
12279
12280 return drm_gem_handle_create(file, &obj->base, handle);
12281 }
12282
12283 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12284 .destroy = intel_user_framebuffer_destroy,
12285 .create_handle = intel_user_framebuffer_create_handle,
12286 };
12287
12288 static int intel_framebuffer_init(struct drm_device *dev,
12289 struct intel_framebuffer *intel_fb,
12290 struct drm_mode_fb_cmd2 *mode_cmd,
12291 struct drm_i915_gem_object *obj)
12292 {
12293 int aligned_height;
12294 int pitch_limit;
12295 int ret;
12296
12297 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12298
12299 if (obj->tiling_mode == I915_TILING_Y) {
12300 DRM_DEBUG("hardware does not support tiling Y\n");
12301 return -EINVAL;
12302 }
12303
12304 if (mode_cmd->pitches[0] & 63) {
12305 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12306 mode_cmd->pitches[0]);
12307 return -EINVAL;
12308 }
12309
12310 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12311 pitch_limit = 32*1024;
12312 } else if (INTEL_INFO(dev)->gen >= 4) {
12313 if (obj->tiling_mode)
12314 pitch_limit = 16*1024;
12315 else
12316 pitch_limit = 32*1024;
12317 } else if (INTEL_INFO(dev)->gen >= 3) {
12318 if (obj->tiling_mode)
12319 pitch_limit = 8*1024;
12320 else
12321 pitch_limit = 16*1024;
12322 } else
12323 /* XXX DSPC is limited to 4k tiled */
12324 pitch_limit = 8*1024;
12325
12326 if (mode_cmd->pitches[0] > pitch_limit) {
12327 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12328 obj->tiling_mode ? "tiled" : "linear",
12329 mode_cmd->pitches[0], pitch_limit);
12330 return -EINVAL;
12331 }
12332
12333 if (obj->tiling_mode != I915_TILING_NONE &&
12334 mode_cmd->pitches[0] != obj->stride) {
12335 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12336 mode_cmd->pitches[0], obj->stride);
12337 return -EINVAL;
12338 }
12339
12340 /* Reject formats not supported by any plane early. */
12341 switch (mode_cmd->pixel_format) {
12342 case DRM_FORMAT_C8:
12343 case DRM_FORMAT_RGB565:
12344 case DRM_FORMAT_XRGB8888:
12345 case DRM_FORMAT_ARGB8888:
12346 break;
12347 case DRM_FORMAT_XRGB1555:
12348 case DRM_FORMAT_ARGB1555:
12349 if (INTEL_INFO(dev)->gen > 3) {
12350 DRM_DEBUG("unsupported pixel format: %s\n",
12351 drm_get_format_name(mode_cmd->pixel_format));
12352 return -EINVAL;
12353 }
12354 break;
12355 case DRM_FORMAT_XBGR8888:
12356 case DRM_FORMAT_ABGR8888:
12357 case DRM_FORMAT_XRGB2101010:
12358 case DRM_FORMAT_ARGB2101010:
12359 case DRM_FORMAT_XBGR2101010:
12360 case DRM_FORMAT_ABGR2101010:
12361 if (INTEL_INFO(dev)->gen < 4) {
12362 DRM_DEBUG("unsupported pixel format: %s\n",
12363 drm_get_format_name(mode_cmd->pixel_format));
12364 return -EINVAL;
12365 }
12366 break;
12367 case DRM_FORMAT_YUYV:
12368 case DRM_FORMAT_UYVY:
12369 case DRM_FORMAT_YVYU:
12370 case DRM_FORMAT_VYUY:
12371 if (INTEL_INFO(dev)->gen < 5) {
12372 DRM_DEBUG("unsupported pixel format: %s\n",
12373 drm_get_format_name(mode_cmd->pixel_format));
12374 return -EINVAL;
12375 }
12376 break;
12377 default:
12378 DRM_DEBUG("unsupported pixel format: %s\n",
12379 drm_get_format_name(mode_cmd->pixel_format));
12380 return -EINVAL;
12381 }
12382
12383 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12384 if (mode_cmd->offsets[0] != 0)
12385 return -EINVAL;
12386
12387 aligned_height = intel_align_height(dev, mode_cmd->height,
12388 obj->tiling_mode);
12389 /* FIXME drm helper for size checks (especially planar formats)? */
12390 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12391 return -EINVAL;
12392
12393 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12394 intel_fb->obj = obj;
12395 intel_fb->obj->framebuffer_references++;
12396
12397 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12398 if (ret) {
12399 DRM_ERROR("framebuffer init failed %d\n", ret);
12400 return ret;
12401 }
12402
12403 return 0;
12404 }
12405
12406 static struct drm_framebuffer *
12407 intel_user_framebuffer_create(struct drm_device *dev,
12408 struct drm_file *filp,
12409 struct drm_mode_fb_cmd2 *mode_cmd)
12410 {
12411 struct drm_i915_gem_object *obj;
12412
12413 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12414 mode_cmd->handles[0]));
12415 if (&obj->base == NULL)
12416 return ERR_PTR(-ENOENT);
12417
12418 return intel_framebuffer_create(dev, mode_cmd, obj);
12419 }
12420
12421 #ifndef CONFIG_DRM_I915_FBDEV
12422 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12423 {
12424 }
12425 #endif
12426
12427 static const struct drm_mode_config_funcs intel_mode_funcs = {
12428 .fb_create = intel_user_framebuffer_create,
12429 .output_poll_changed = intel_fbdev_output_poll_changed,
12430 };
12431
12432 /* Set up chip specific display functions */
12433 static void intel_init_display(struct drm_device *dev)
12434 {
12435 struct drm_i915_private *dev_priv = dev->dev_private;
12436
12437 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12438 dev_priv->display.find_dpll = g4x_find_best_dpll;
12439 else if (IS_CHERRYVIEW(dev))
12440 dev_priv->display.find_dpll = chv_find_best_dpll;
12441 else if (IS_VALLEYVIEW(dev))
12442 dev_priv->display.find_dpll = vlv_find_best_dpll;
12443 else if (IS_PINEVIEW(dev))
12444 dev_priv->display.find_dpll = pnv_find_best_dpll;
12445 else
12446 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12447
12448 if (HAS_DDI(dev)) {
12449 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12450 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12451 dev_priv->display.crtc_compute_clock =
12452 haswell_crtc_compute_clock;
12453 dev_priv->display.crtc_enable = haswell_crtc_enable;
12454 dev_priv->display.crtc_disable = haswell_crtc_disable;
12455 dev_priv->display.off = ironlake_crtc_off;
12456 if (INTEL_INFO(dev)->gen >= 9)
12457 dev_priv->display.update_primary_plane =
12458 skylake_update_primary_plane;
12459 else
12460 dev_priv->display.update_primary_plane =
12461 ironlake_update_primary_plane;
12462 } else if (HAS_PCH_SPLIT(dev)) {
12463 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12464 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12465 dev_priv->display.crtc_compute_clock =
12466 ironlake_crtc_compute_clock;
12467 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12468 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12469 dev_priv->display.off = ironlake_crtc_off;
12470 dev_priv->display.update_primary_plane =
12471 ironlake_update_primary_plane;
12472 } else if (IS_VALLEYVIEW(dev)) {
12473 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12474 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12475 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12476 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12477 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12478 dev_priv->display.off = i9xx_crtc_off;
12479 dev_priv->display.update_primary_plane =
12480 i9xx_update_primary_plane;
12481 } else {
12482 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12483 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12484 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12485 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12486 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12487 dev_priv->display.off = i9xx_crtc_off;
12488 dev_priv->display.update_primary_plane =
12489 i9xx_update_primary_plane;
12490 }
12491
12492 /* Returns the core display clock speed */
12493 if (IS_VALLEYVIEW(dev))
12494 dev_priv->display.get_display_clock_speed =
12495 valleyview_get_display_clock_speed;
12496 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12497 dev_priv->display.get_display_clock_speed =
12498 i945_get_display_clock_speed;
12499 else if (IS_I915G(dev))
12500 dev_priv->display.get_display_clock_speed =
12501 i915_get_display_clock_speed;
12502 else if (IS_I945GM(dev) || IS_845G(dev))
12503 dev_priv->display.get_display_clock_speed =
12504 i9xx_misc_get_display_clock_speed;
12505 else if (IS_PINEVIEW(dev))
12506 dev_priv->display.get_display_clock_speed =
12507 pnv_get_display_clock_speed;
12508 else if (IS_I915GM(dev))
12509 dev_priv->display.get_display_clock_speed =
12510 i915gm_get_display_clock_speed;
12511 else if (IS_I865G(dev))
12512 dev_priv->display.get_display_clock_speed =
12513 i865_get_display_clock_speed;
12514 else if (IS_I85X(dev))
12515 dev_priv->display.get_display_clock_speed =
12516 i855_get_display_clock_speed;
12517 else /* 852, 830 */
12518 dev_priv->display.get_display_clock_speed =
12519 i830_get_display_clock_speed;
12520
12521 if (IS_GEN5(dev)) {
12522 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12523 } else if (IS_GEN6(dev)) {
12524 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12525 } else if (IS_IVYBRIDGE(dev)) {
12526 /* FIXME: detect B0+ stepping and use auto training */
12527 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12528 dev_priv->display.modeset_global_resources =
12529 ivb_modeset_global_resources;
12530 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12531 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12532 } else if (IS_VALLEYVIEW(dev)) {
12533 dev_priv->display.modeset_global_resources =
12534 valleyview_modeset_global_resources;
12535 }
12536
12537 /* Default just returns -ENODEV to indicate unsupported */
12538 dev_priv->display.queue_flip = intel_default_queue_flip;
12539
12540 switch (INTEL_INFO(dev)->gen) {
12541 case 2:
12542 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12543 break;
12544
12545 case 3:
12546 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12547 break;
12548
12549 case 4:
12550 case 5:
12551 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12552 break;
12553
12554 case 6:
12555 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12556 break;
12557 case 7:
12558 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12559 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12560 break;
12561 }
12562
12563 intel_panel_init_backlight_funcs(dev);
12564
12565 mutex_init(&dev_priv->pps_mutex);
12566 }
12567
12568 /*
12569 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12570 * resume, or other times. This quirk makes sure that's the case for
12571 * affected systems.
12572 */
12573 static void quirk_pipea_force(struct drm_device *dev)
12574 {
12575 struct drm_i915_private *dev_priv = dev->dev_private;
12576
12577 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12578 DRM_INFO("applying pipe a force quirk\n");
12579 }
12580
12581 static void quirk_pipeb_force(struct drm_device *dev)
12582 {
12583 struct drm_i915_private *dev_priv = dev->dev_private;
12584
12585 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12586 DRM_INFO("applying pipe b force quirk\n");
12587 }
12588
12589 /*
12590 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12591 */
12592 static void quirk_ssc_force_disable(struct drm_device *dev)
12593 {
12594 struct drm_i915_private *dev_priv = dev->dev_private;
12595 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12596 DRM_INFO("applying lvds SSC disable quirk\n");
12597 }
12598
12599 /*
12600 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12601 * brightness value
12602 */
12603 static void quirk_invert_brightness(struct drm_device *dev)
12604 {
12605 struct drm_i915_private *dev_priv = dev->dev_private;
12606 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12607 DRM_INFO("applying inverted panel brightness quirk\n");
12608 }
12609
12610 /* Some VBT's incorrectly indicate no backlight is present */
12611 static void quirk_backlight_present(struct drm_device *dev)
12612 {
12613 struct drm_i915_private *dev_priv = dev->dev_private;
12614 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12615 DRM_INFO("applying backlight present quirk\n");
12616 }
12617
12618 struct intel_quirk {
12619 int device;
12620 int subsystem_vendor;
12621 int subsystem_device;
12622 void (*hook)(struct drm_device *dev);
12623 };
12624
12625 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12626 struct intel_dmi_quirk {
12627 void (*hook)(struct drm_device *dev);
12628 const struct dmi_system_id (*dmi_id_list)[];
12629 };
12630
12631 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12632 {
12633 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12634 return 1;
12635 }
12636
12637 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12638 {
12639 .dmi_id_list = &(const struct dmi_system_id[]) {
12640 {
12641 .callback = intel_dmi_reverse_brightness,
12642 .ident = "NCR Corporation",
12643 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12644 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12645 },
12646 },
12647 { } /* terminating entry */
12648 },
12649 .hook = quirk_invert_brightness,
12650 },
12651 };
12652
12653 static struct intel_quirk intel_quirks[] = {
12654 /* HP Mini needs pipe A force quirk (LP: #322104) */
12655 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12656
12657 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12658 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12659
12660 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12661 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12662
12663 /* 830 needs to leave pipe A & dpll A up */
12664 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12665
12666 /* 830 needs to leave pipe B & dpll B up */
12667 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12668
12669 /* Lenovo U160 cannot use SSC on LVDS */
12670 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12671
12672 /* Sony Vaio Y cannot use SSC on LVDS */
12673 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12674
12675 /* Acer Aspire 5734Z must invert backlight brightness */
12676 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12677
12678 /* Acer/eMachines G725 */
12679 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12680
12681 /* Acer/eMachines e725 */
12682 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12683
12684 /* Acer/Packard Bell NCL20 */
12685 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12686
12687 /* Acer Aspire 4736Z */
12688 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12689
12690 /* Acer Aspire 5336 */
12691 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12692
12693 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12694 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12695
12696 /* Acer C720 Chromebook (Core i3 4005U) */
12697 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12698
12699 /* Apple Macbook 2,1 (Core 2 T7400) */
12700 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
12701
12702 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12703 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12704
12705 /* HP Chromebook 14 (Celeron 2955U) */
12706 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12707 };
12708
12709 static void intel_init_quirks(struct drm_device *dev)
12710 {
12711 struct pci_dev *d = dev->pdev;
12712 int i;
12713
12714 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12715 struct intel_quirk *q = &intel_quirks[i];
12716
12717 if (d->device == q->device &&
12718 (d->subsystem_vendor == q->subsystem_vendor ||
12719 q->subsystem_vendor == PCI_ANY_ID) &&
12720 (d->subsystem_device == q->subsystem_device ||
12721 q->subsystem_device == PCI_ANY_ID))
12722 q->hook(dev);
12723 }
12724 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12725 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12726 intel_dmi_quirks[i].hook(dev);
12727 }
12728 }
12729
12730 /* Disable the VGA plane that we never use */
12731 static void i915_disable_vga(struct drm_device *dev)
12732 {
12733 struct drm_i915_private *dev_priv = dev->dev_private;
12734 u8 sr1;
12735 u32 vga_reg = i915_vgacntrl_reg(dev);
12736
12737 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12738 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12739 outb(SR01, VGA_SR_INDEX);
12740 sr1 = inb(VGA_SR_DATA);
12741 outb(sr1 | 1<<5, VGA_SR_DATA);
12742 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12743 udelay(300);
12744
12745 /*
12746 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12747 * from S3 without preserving (some of?) the other bits.
12748 */
12749 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12750 POSTING_READ(vga_reg);
12751 }
12752
12753 void intel_modeset_init_hw(struct drm_device *dev)
12754 {
12755 intel_prepare_ddi(dev);
12756
12757 if (IS_VALLEYVIEW(dev))
12758 vlv_update_cdclk(dev);
12759
12760 intel_init_clock_gating(dev);
12761
12762 intel_enable_gt_powersave(dev);
12763 }
12764
12765 void intel_modeset_init(struct drm_device *dev)
12766 {
12767 struct drm_i915_private *dev_priv = dev->dev_private;
12768 int sprite, ret;
12769 enum pipe pipe;
12770 struct intel_crtc *crtc;
12771
12772 drm_mode_config_init(dev);
12773
12774 dev->mode_config.min_width = 0;
12775 dev->mode_config.min_height = 0;
12776
12777 dev->mode_config.preferred_depth = 24;
12778 dev->mode_config.prefer_shadow = 1;
12779
12780 dev->mode_config.funcs = &intel_mode_funcs;
12781
12782 intel_init_quirks(dev);
12783
12784 intel_init_pm(dev);
12785
12786 if (INTEL_INFO(dev)->num_pipes == 0)
12787 return;
12788
12789 intel_init_display(dev);
12790 intel_init_audio(dev);
12791
12792 if (IS_GEN2(dev)) {
12793 dev->mode_config.max_width = 2048;
12794 dev->mode_config.max_height = 2048;
12795 } else if (IS_GEN3(dev)) {
12796 dev->mode_config.max_width = 4096;
12797 dev->mode_config.max_height = 4096;
12798 } else {
12799 dev->mode_config.max_width = 8192;
12800 dev->mode_config.max_height = 8192;
12801 }
12802
12803 if (IS_845G(dev) || IS_I865G(dev)) {
12804 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12805 dev->mode_config.cursor_height = 1023;
12806 } else if (IS_GEN2(dev)) {
12807 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12808 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12809 } else {
12810 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12811 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12812 }
12813
12814 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12815
12816 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12817 INTEL_INFO(dev)->num_pipes,
12818 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12819
12820 for_each_pipe(dev_priv, pipe) {
12821 intel_crtc_init(dev, pipe);
12822 for_each_sprite(pipe, sprite) {
12823 ret = intel_plane_init(dev, pipe, sprite);
12824 if (ret)
12825 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12826 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12827 }
12828 }
12829
12830 intel_init_dpio(dev);
12831
12832 intel_shared_dpll_init(dev);
12833
12834 /* save the BIOS value before clobbering it */
12835 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12836 /* Just disable it once at startup */
12837 i915_disable_vga(dev);
12838 intel_setup_outputs(dev);
12839
12840 /* Just in case the BIOS is doing something questionable. */
12841 intel_disable_fbc(dev);
12842
12843 drm_modeset_lock_all(dev);
12844 intel_modeset_setup_hw_state(dev, false);
12845 drm_modeset_unlock_all(dev);
12846
12847 for_each_intel_crtc(dev, crtc) {
12848 if (!crtc->active)
12849 continue;
12850
12851 /*
12852 * Note that reserving the BIOS fb up front prevents us
12853 * from stuffing other stolen allocations like the ring
12854 * on top. This prevents some ugliness at boot time, and
12855 * can even allow for smooth boot transitions if the BIOS
12856 * fb is large enough for the active pipe configuration.
12857 */
12858 if (dev_priv->display.get_plane_config) {
12859 dev_priv->display.get_plane_config(crtc,
12860 &crtc->plane_config);
12861 /*
12862 * If the fb is shared between multiple heads, we'll
12863 * just get the first one.
12864 */
12865 intel_find_plane_obj(crtc, &crtc->plane_config);
12866 }
12867 }
12868 }
12869
12870 static void intel_enable_pipe_a(struct drm_device *dev)
12871 {
12872 struct intel_connector *connector;
12873 struct drm_connector *crt = NULL;
12874 struct intel_load_detect_pipe load_detect_temp;
12875 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12876
12877 /* We can't just switch on the pipe A, we need to set things up with a
12878 * proper mode and output configuration. As a gross hack, enable pipe A
12879 * by enabling the load detect pipe once. */
12880 list_for_each_entry(connector,
12881 &dev->mode_config.connector_list,
12882 base.head) {
12883 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12884 crt = &connector->base;
12885 break;
12886 }
12887 }
12888
12889 if (!crt)
12890 return;
12891
12892 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12893 intel_release_load_detect_pipe(crt, &load_detect_temp);
12894 }
12895
12896 static bool
12897 intel_check_plane_mapping(struct intel_crtc *crtc)
12898 {
12899 struct drm_device *dev = crtc->base.dev;
12900 struct drm_i915_private *dev_priv = dev->dev_private;
12901 u32 reg, val;
12902
12903 if (INTEL_INFO(dev)->num_pipes == 1)
12904 return true;
12905
12906 reg = DSPCNTR(!crtc->plane);
12907 val = I915_READ(reg);
12908
12909 if ((val & DISPLAY_PLANE_ENABLE) &&
12910 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12911 return false;
12912
12913 return true;
12914 }
12915
12916 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12917 {
12918 struct drm_device *dev = crtc->base.dev;
12919 struct drm_i915_private *dev_priv = dev->dev_private;
12920 u32 reg;
12921
12922 /* Clear any frame start delays used for debugging left by the BIOS */
12923 reg = PIPECONF(crtc->config.cpu_transcoder);
12924 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12925
12926 /* restore vblank interrupts to correct state */
12927 if (crtc->active) {
12928 update_scanline_offset(crtc);
12929 drm_vblank_on(dev, crtc->pipe);
12930 } else
12931 drm_vblank_off(dev, crtc->pipe);
12932
12933 /* We need to sanitize the plane -> pipe mapping first because this will
12934 * disable the crtc (and hence change the state) if it is wrong. Note
12935 * that gen4+ has a fixed plane -> pipe mapping. */
12936 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12937 struct intel_connector *connector;
12938 bool plane;
12939
12940 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12941 crtc->base.base.id);
12942
12943 /* Pipe has the wrong plane attached and the plane is active.
12944 * Temporarily change the plane mapping and disable everything
12945 * ... */
12946 plane = crtc->plane;
12947 crtc->plane = !plane;
12948 crtc->primary_enabled = true;
12949 dev_priv->display.crtc_disable(&crtc->base);
12950 crtc->plane = plane;
12951
12952 /* ... and break all links. */
12953 list_for_each_entry(connector, &dev->mode_config.connector_list,
12954 base.head) {
12955 if (connector->encoder->base.crtc != &crtc->base)
12956 continue;
12957
12958 connector->base.dpms = DRM_MODE_DPMS_OFF;
12959 connector->base.encoder = NULL;
12960 }
12961 /* multiple connectors may have the same encoder:
12962 * handle them and break crtc link separately */
12963 list_for_each_entry(connector, &dev->mode_config.connector_list,
12964 base.head)
12965 if (connector->encoder->base.crtc == &crtc->base) {
12966 connector->encoder->base.crtc = NULL;
12967 connector->encoder->connectors_active = false;
12968 }
12969
12970 WARN_ON(crtc->active);
12971 crtc->base.enabled = false;
12972 }
12973
12974 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12975 crtc->pipe == PIPE_A && !crtc->active) {
12976 /* BIOS forgot to enable pipe A, this mostly happens after
12977 * resume. Force-enable the pipe to fix this, the update_dpms
12978 * call below we restore the pipe to the right state, but leave
12979 * the required bits on. */
12980 intel_enable_pipe_a(dev);
12981 }
12982
12983 /* Adjust the state of the output pipe according to whether we
12984 * have active connectors/encoders. */
12985 intel_crtc_update_dpms(&crtc->base);
12986
12987 if (crtc->active != crtc->base.enabled) {
12988 struct intel_encoder *encoder;
12989
12990 /* This can happen either due to bugs in the get_hw_state
12991 * functions or because the pipe is force-enabled due to the
12992 * pipe A quirk. */
12993 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12994 crtc->base.base.id,
12995 crtc->base.enabled ? "enabled" : "disabled",
12996 crtc->active ? "enabled" : "disabled");
12997
12998 crtc->base.enabled = crtc->active;
12999
13000 /* Because we only establish the connector -> encoder ->
13001 * crtc links if something is active, this means the
13002 * crtc is now deactivated. Break the links. connector
13003 * -> encoder links are only establish when things are
13004 * actually up, hence no need to break them. */
13005 WARN_ON(crtc->active);
13006
13007 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13008 WARN_ON(encoder->connectors_active);
13009 encoder->base.crtc = NULL;
13010 }
13011 }
13012
13013 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13014 /*
13015 * We start out with underrun reporting disabled to avoid races.
13016 * For correct bookkeeping mark this on active crtcs.
13017 *
13018 * Also on gmch platforms we dont have any hardware bits to
13019 * disable the underrun reporting. Which means we need to start
13020 * out with underrun reporting disabled also on inactive pipes,
13021 * since otherwise we'll complain about the garbage we read when
13022 * e.g. coming up after runtime pm.
13023 *
13024 * No protection against concurrent access is required - at
13025 * worst a fifo underrun happens which also sets this to false.
13026 */
13027 crtc->cpu_fifo_underrun_disabled = true;
13028 crtc->pch_fifo_underrun_disabled = true;
13029 }
13030 }
13031
13032 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13033 {
13034 struct intel_connector *connector;
13035 struct drm_device *dev = encoder->base.dev;
13036
13037 /* We need to check both for a crtc link (meaning that the
13038 * encoder is active and trying to read from a pipe) and the
13039 * pipe itself being active. */
13040 bool has_active_crtc = encoder->base.crtc &&
13041 to_intel_crtc(encoder->base.crtc)->active;
13042
13043 if (encoder->connectors_active && !has_active_crtc) {
13044 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13045 encoder->base.base.id,
13046 encoder->base.name);
13047
13048 /* Connector is active, but has no active pipe. This is
13049 * fallout from our resume register restoring. Disable
13050 * the encoder manually again. */
13051 if (encoder->base.crtc) {
13052 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13053 encoder->base.base.id,
13054 encoder->base.name);
13055 encoder->disable(encoder);
13056 if (encoder->post_disable)
13057 encoder->post_disable(encoder);
13058 }
13059 encoder->base.crtc = NULL;
13060 encoder->connectors_active = false;
13061
13062 /* Inconsistent output/port/pipe state happens presumably due to
13063 * a bug in one of the get_hw_state functions. Or someplace else
13064 * in our code, like the register restore mess on resume. Clamp
13065 * things to off as a safer default. */
13066 list_for_each_entry(connector,
13067 &dev->mode_config.connector_list,
13068 base.head) {
13069 if (connector->encoder != encoder)
13070 continue;
13071 connector->base.dpms = DRM_MODE_DPMS_OFF;
13072 connector->base.encoder = NULL;
13073 }
13074 }
13075 /* Enabled encoders without active connectors will be fixed in
13076 * the crtc fixup. */
13077 }
13078
13079 void i915_redisable_vga_power_on(struct drm_device *dev)
13080 {
13081 struct drm_i915_private *dev_priv = dev->dev_private;
13082 u32 vga_reg = i915_vgacntrl_reg(dev);
13083
13084 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13085 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13086 i915_disable_vga(dev);
13087 }
13088 }
13089
13090 void i915_redisable_vga(struct drm_device *dev)
13091 {
13092 struct drm_i915_private *dev_priv = dev->dev_private;
13093
13094 /* This function can be called both from intel_modeset_setup_hw_state or
13095 * at a very early point in our resume sequence, where the power well
13096 * structures are not yet restored. Since this function is at a very
13097 * paranoid "someone might have enabled VGA while we were not looking"
13098 * level, just check if the power well is enabled instead of trying to
13099 * follow the "don't touch the power well if we don't need it" policy
13100 * the rest of the driver uses. */
13101 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13102 return;
13103
13104 i915_redisable_vga_power_on(dev);
13105 }
13106
13107 static bool primary_get_hw_state(struct intel_crtc *crtc)
13108 {
13109 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13110
13111 if (!crtc->active)
13112 return false;
13113
13114 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13115 }
13116
13117 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13118 {
13119 struct drm_i915_private *dev_priv = dev->dev_private;
13120 enum pipe pipe;
13121 struct intel_crtc *crtc;
13122 struct intel_encoder *encoder;
13123 struct intel_connector *connector;
13124 int i;
13125
13126 for_each_intel_crtc(dev, crtc) {
13127 memset(&crtc->config, 0, sizeof(crtc->config));
13128
13129 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13130
13131 crtc->active = dev_priv->display.get_pipe_config(crtc,
13132 &crtc->config);
13133
13134 crtc->base.enabled = crtc->active;
13135 crtc->primary_enabled = primary_get_hw_state(crtc);
13136
13137 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13138 crtc->base.base.id,
13139 crtc->active ? "enabled" : "disabled");
13140 }
13141
13142 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13143 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13144
13145 pll->on = pll->get_hw_state(dev_priv, pll,
13146 &pll->config.hw_state);
13147 pll->active = 0;
13148 pll->config.crtc_mask = 0;
13149 for_each_intel_crtc(dev, crtc) {
13150 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13151 pll->active++;
13152 pll->config.crtc_mask |= 1 << crtc->pipe;
13153 }
13154 }
13155
13156 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13157 pll->name, pll->config.crtc_mask, pll->on);
13158
13159 if (pll->config.crtc_mask)
13160 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13161 }
13162
13163 for_each_intel_encoder(dev, encoder) {
13164 pipe = 0;
13165
13166 if (encoder->get_hw_state(encoder, &pipe)) {
13167 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13168 encoder->base.crtc = &crtc->base;
13169 encoder->get_config(encoder, &crtc->config);
13170 } else {
13171 encoder->base.crtc = NULL;
13172 }
13173
13174 encoder->connectors_active = false;
13175 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13176 encoder->base.base.id,
13177 encoder->base.name,
13178 encoder->base.crtc ? "enabled" : "disabled",
13179 pipe_name(pipe));
13180 }
13181
13182 list_for_each_entry(connector, &dev->mode_config.connector_list,
13183 base.head) {
13184 if (connector->get_hw_state(connector)) {
13185 connector->base.dpms = DRM_MODE_DPMS_ON;
13186 connector->encoder->connectors_active = true;
13187 connector->base.encoder = &connector->encoder->base;
13188 } else {
13189 connector->base.dpms = DRM_MODE_DPMS_OFF;
13190 connector->base.encoder = NULL;
13191 }
13192 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13193 connector->base.base.id,
13194 connector->base.name,
13195 connector->base.encoder ? "enabled" : "disabled");
13196 }
13197 }
13198
13199 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13200 * and i915 state tracking structures. */
13201 void intel_modeset_setup_hw_state(struct drm_device *dev,
13202 bool force_restore)
13203 {
13204 struct drm_i915_private *dev_priv = dev->dev_private;
13205 enum pipe pipe;
13206 struct intel_crtc *crtc;
13207 struct intel_encoder *encoder;
13208 int i;
13209
13210 intel_modeset_readout_hw_state(dev);
13211
13212 /*
13213 * Now that we have the config, copy it to each CRTC struct
13214 * Note that this could go away if we move to using crtc_config
13215 * checking everywhere.
13216 */
13217 for_each_intel_crtc(dev, crtc) {
13218 if (crtc->active && i915.fastboot) {
13219 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13220 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13221 crtc->base.base.id);
13222 drm_mode_debug_printmodeline(&crtc->base.mode);
13223 }
13224 }
13225
13226 /* HW state is read out, now we need to sanitize this mess. */
13227 for_each_intel_encoder(dev, encoder) {
13228 intel_sanitize_encoder(encoder);
13229 }
13230
13231 for_each_pipe(dev_priv, pipe) {
13232 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13233 intel_sanitize_crtc(crtc);
13234 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13235 }
13236
13237 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13238 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13239
13240 if (!pll->on || pll->active)
13241 continue;
13242
13243 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13244
13245 pll->disable(dev_priv, pll);
13246 pll->on = false;
13247 }
13248
13249 if (IS_GEN9(dev))
13250 skl_wm_get_hw_state(dev);
13251 else if (HAS_PCH_SPLIT(dev))
13252 ilk_wm_get_hw_state(dev);
13253
13254 if (force_restore) {
13255 i915_redisable_vga(dev);
13256
13257 /*
13258 * We need to use raw interfaces for restoring state to avoid
13259 * checking (bogus) intermediate states.
13260 */
13261 for_each_pipe(dev_priv, pipe) {
13262 struct drm_crtc *crtc =
13263 dev_priv->pipe_to_crtc_mapping[pipe];
13264
13265 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13266 crtc->primary->fb);
13267 }
13268 } else {
13269 intel_modeset_update_staged_output_state(dev);
13270 }
13271
13272 intel_modeset_check_state(dev);
13273 }
13274
13275 void intel_modeset_gem_init(struct drm_device *dev)
13276 {
13277 struct drm_crtc *c;
13278 struct drm_i915_gem_object *obj;
13279
13280 mutex_lock(&dev->struct_mutex);
13281 intel_init_gt_powersave(dev);
13282 mutex_unlock(&dev->struct_mutex);
13283
13284 intel_modeset_init_hw(dev);
13285
13286 intel_setup_overlay(dev);
13287
13288 /*
13289 * Make sure any fbs we allocated at startup are properly
13290 * pinned & fenced. When we do the allocation it's too early
13291 * for this.
13292 */
13293 mutex_lock(&dev->struct_mutex);
13294 for_each_crtc(dev, c) {
13295 obj = intel_fb_obj(c->primary->fb);
13296 if (obj == NULL)
13297 continue;
13298
13299 if (intel_pin_and_fence_fb_obj(c->primary,
13300 c->primary->fb,
13301 NULL)) {
13302 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13303 to_intel_crtc(c)->pipe);
13304 drm_framebuffer_unreference(c->primary->fb);
13305 c->primary->fb = NULL;
13306 }
13307 }
13308 mutex_unlock(&dev->struct_mutex);
13309 }
13310
13311 void intel_connector_unregister(struct intel_connector *intel_connector)
13312 {
13313 struct drm_connector *connector = &intel_connector->base;
13314
13315 intel_panel_destroy_backlight(connector);
13316 drm_connector_unregister(connector);
13317 }
13318
13319 void intel_modeset_cleanup(struct drm_device *dev)
13320 {
13321 struct drm_i915_private *dev_priv = dev->dev_private;
13322 struct drm_connector *connector;
13323
13324 /*
13325 * Interrupts and polling as the first thing to avoid creating havoc.
13326 * Too much stuff here (turning of rps, connectors, ...) would
13327 * experience fancy races otherwise.
13328 */
13329 intel_irq_uninstall(dev_priv);
13330
13331 /*
13332 * Due to the hpd irq storm handling the hotplug work can re-arm the
13333 * poll handlers. Hence disable polling after hpd handling is shut down.
13334 */
13335 drm_kms_helper_poll_fini(dev);
13336
13337 mutex_lock(&dev->struct_mutex);
13338
13339 intel_unregister_dsm_handler();
13340
13341 intel_disable_fbc(dev);
13342
13343 intel_disable_gt_powersave(dev);
13344
13345 ironlake_teardown_rc6(dev);
13346
13347 mutex_unlock(&dev->struct_mutex);
13348
13349 /* flush any delayed tasks or pending work */
13350 flush_scheduled_work();
13351
13352 /* destroy the backlight and sysfs files before encoders/connectors */
13353 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13354 struct intel_connector *intel_connector;
13355
13356 intel_connector = to_intel_connector(connector);
13357 intel_connector->unregister(intel_connector);
13358 }
13359
13360 drm_mode_config_cleanup(dev);
13361
13362 intel_cleanup_overlay(dev);
13363
13364 mutex_lock(&dev->struct_mutex);
13365 intel_cleanup_gt_powersave(dev);
13366 mutex_unlock(&dev->struct_mutex);
13367 }
13368
13369 /*
13370 * Return which encoder is currently attached for connector.
13371 */
13372 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13373 {
13374 return &intel_attached_encoder(connector)->base;
13375 }
13376
13377 void intel_connector_attach_encoder(struct intel_connector *connector,
13378 struct intel_encoder *encoder)
13379 {
13380 connector->encoder = encoder;
13381 drm_mode_connector_attach_encoder(&connector->base,
13382 &encoder->base);
13383 }
13384
13385 /*
13386 * set vga decode state - true == enable VGA decode
13387 */
13388 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13389 {
13390 struct drm_i915_private *dev_priv = dev->dev_private;
13391 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13392 u16 gmch_ctrl;
13393
13394 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13395 DRM_ERROR("failed to read control word\n");
13396 return -EIO;
13397 }
13398
13399 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13400 return 0;
13401
13402 if (state)
13403 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13404 else
13405 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13406
13407 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13408 DRM_ERROR("failed to write control word\n");
13409 return -EIO;
13410 }
13411
13412 return 0;
13413 }
13414
13415 struct intel_display_error_state {
13416
13417 u32 power_well_driver;
13418
13419 int num_transcoders;
13420
13421 struct intel_cursor_error_state {
13422 u32 control;
13423 u32 position;
13424 u32 base;
13425 u32 size;
13426 } cursor[I915_MAX_PIPES];
13427
13428 struct intel_pipe_error_state {
13429 bool power_domain_on;
13430 u32 source;
13431 u32 stat;
13432 } pipe[I915_MAX_PIPES];
13433
13434 struct intel_plane_error_state {
13435 u32 control;
13436 u32 stride;
13437 u32 size;
13438 u32 pos;
13439 u32 addr;
13440 u32 surface;
13441 u32 tile_offset;
13442 } plane[I915_MAX_PIPES];
13443
13444 struct intel_transcoder_error_state {
13445 bool power_domain_on;
13446 enum transcoder cpu_transcoder;
13447
13448 u32 conf;
13449
13450 u32 htotal;
13451 u32 hblank;
13452 u32 hsync;
13453 u32 vtotal;
13454 u32 vblank;
13455 u32 vsync;
13456 } transcoder[4];
13457 };
13458
13459 struct intel_display_error_state *
13460 intel_display_capture_error_state(struct drm_device *dev)
13461 {
13462 struct drm_i915_private *dev_priv = dev->dev_private;
13463 struct intel_display_error_state *error;
13464 int transcoders[] = {
13465 TRANSCODER_A,
13466 TRANSCODER_B,
13467 TRANSCODER_C,
13468 TRANSCODER_EDP,
13469 };
13470 int i;
13471
13472 if (INTEL_INFO(dev)->num_pipes == 0)
13473 return NULL;
13474
13475 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13476 if (error == NULL)
13477 return NULL;
13478
13479 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13480 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13481
13482 for_each_pipe(dev_priv, i) {
13483 error->pipe[i].power_domain_on =
13484 __intel_display_power_is_enabled(dev_priv,
13485 POWER_DOMAIN_PIPE(i));
13486 if (!error->pipe[i].power_domain_on)
13487 continue;
13488
13489 error->cursor[i].control = I915_READ(CURCNTR(i));
13490 error->cursor[i].position = I915_READ(CURPOS(i));
13491 error->cursor[i].base = I915_READ(CURBASE(i));
13492
13493 error->plane[i].control = I915_READ(DSPCNTR(i));
13494 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13495 if (INTEL_INFO(dev)->gen <= 3) {
13496 error->plane[i].size = I915_READ(DSPSIZE(i));
13497 error->plane[i].pos = I915_READ(DSPPOS(i));
13498 }
13499 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13500 error->plane[i].addr = I915_READ(DSPADDR(i));
13501 if (INTEL_INFO(dev)->gen >= 4) {
13502 error->plane[i].surface = I915_READ(DSPSURF(i));
13503 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13504 }
13505
13506 error->pipe[i].source = I915_READ(PIPESRC(i));
13507
13508 if (HAS_GMCH_DISPLAY(dev))
13509 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13510 }
13511
13512 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13513 if (HAS_DDI(dev_priv->dev))
13514 error->num_transcoders++; /* Account for eDP. */
13515
13516 for (i = 0; i < error->num_transcoders; i++) {
13517 enum transcoder cpu_transcoder = transcoders[i];
13518
13519 error->transcoder[i].power_domain_on =
13520 __intel_display_power_is_enabled(dev_priv,
13521 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13522 if (!error->transcoder[i].power_domain_on)
13523 continue;
13524
13525 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13526
13527 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13528 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13529 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13530 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13531 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13532 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13533 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13534 }
13535
13536 return error;
13537 }
13538
13539 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13540
13541 void
13542 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13543 struct drm_device *dev,
13544 struct intel_display_error_state *error)
13545 {
13546 struct drm_i915_private *dev_priv = dev->dev_private;
13547 int i;
13548
13549 if (!error)
13550 return;
13551
13552 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13553 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13554 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13555 error->power_well_driver);
13556 for_each_pipe(dev_priv, i) {
13557 err_printf(m, "Pipe [%d]:\n", i);
13558 err_printf(m, " Power: %s\n",
13559 error->pipe[i].power_domain_on ? "on" : "off");
13560 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13561 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13562
13563 err_printf(m, "Plane [%d]:\n", i);
13564 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13565 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13566 if (INTEL_INFO(dev)->gen <= 3) {
13567 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13568 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13569 }
13570 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13571 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13572 if (INTEL_INFO(dev)->gen >= 4) {
13573 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13574 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13575 }
13576
13577 err_printf(m, "Cursor [%d]:\n", i);
13578 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13579 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13580 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13581 }
13582
13583 for (i = 0; i < error->num_transcoders; i++) {
13584 err_printf(m, "CPU transcoder: %c\n",
13585 transcoder_name(error->transcoder[i].cpu_transcoder));
13586 err_printf(m, " Power: %s\n",
13587 error->transcoder[i].power_domain_on ? "on" : "off");
13588 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13589 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13590 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13591 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13592 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13593 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13594 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13595 }
13596 }
13597
13598 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13599 {
13600 struct intel_crtc *crtc;
13601
13602 for_each_intel_crtc(dev, crtc) {
13603 struct intel_unpin_work *work;
13604
13605 spin_lock_irq(&dev->event_lock);
13606
13607 work = crtc->unpin_work;
13608
13609 if (work && work->event &&
13610 work->event->base.file_priv == file) {
13611 kfree(work->event);
13612 work->event = NULL;
13613 }
13614
13615 spin_unlock_irq(&dev->event_lock);
13616 }
13617 }
Linux kernel - Deliverables
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