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drm/i915: Program PFI credits for VLV
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic_helper.h>
41 #include <drm/drm_dp_helper.h>
42 #include <drm/drm_crtc_helper.h>
43 #include <drm/drm_plane_helper.h>
44 #include <drm/drm_rect.h>
45 #include <linux/dma_remapping.h>
46
47 /* Primary plane formats supported by all gen */
48 #define COMMON_PRIMARY_FORMATS \
49 DRM_FORMAT_C8, \
50 DRM_FORMAT_RGB565, \
51 DRM_FORMAT_XRGB8888, \
52 DRM_FORMAT_ARGB8888
53
54 /* Primary plane formats for gen <= 3 */
55 static const uint32_t intel_primary_formats_gen2[] = {
56 COMMON_PRIMARY_FORMATS,
57 DRM_FORMAT_XRGB1555,
58 DRM_FORMAT_ARGB1555,
59 };
60
61 /* Primary plane formats for gen >= 4 */
62 static const uint32_t intel_primary_formats_gen4[] = {
63 COMMON_PRIMARY_FORMATS, \
64 DRM_FORMAT_XBGR8888,
65 DRM_FORMAT_ABGR8888,
66 DRM_FORMAT_XRGB2101010,
67 DRM_FORMAT_ARGB2101010,
68 DRM_FORMAT_XBGR2101010,
69 DRM_FORMAT_ABGR2101010,
70 };
71
72 /* Cursor formats */
73 static const uint32_t intel_cursor_formats[] = {
74 DRM_FORMAT_ARGB8888,
75 };
76
77 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
78
79 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
80 struct intel_crtc_state *pipe_config);
81 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
82 struct intel_crtc_state *pipe_config);
83
84 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
85 int x, int y, struct drm_framebuffer *old_fb);
86 static int intel_framebuffer_init(struct drm_device *dev,
87 struct intel_framebuffer *ifb,
88 struct drm_mode_fb_cmd2 *mode_cmd,
89 struct drm_i915_gem_object *obj);
90 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
91 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
92 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
93 struct intel_link_m_n *m_n,
94 struct intel_link_m_n *m2_n2);
95 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
96 static void haswell_set_pipeconf(struct drm_crtc *crtc);
97 static void intel_set_pipe_csc(struct drm_crtc *crtc);
98 static void vlv_prepare_pll(struct intel_crtc *crtc,
99 const struct intel_crtc_state *pipe_config);
100 static void chv_prepare_pll(struct intel_crtc *crtc,
101 const struct intel_crtc_state *pipe_config);
102 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
103 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
104
105 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
106 {
107 if (!connector->mst_port)
108 return connector->encoder;
109 else
110 return &connector->mst_port->mst_encoders[pipe]->base;
111 }
112
113 typedef struct {
114 int min, max;
115 } intel_range_t;
116
117 typedef struct {
118 int dot_limit;
119 int p2_slow, p2_fast;
120 } intel_p2_t;
121
122 typedef struct intel_limit intel_limit_t;
123 struct intel_limit {
124 intel_range_t dot, vco, n, m, m1, m2, p, p1;
125 intel_p2_t p2;
126 };
127
128 int
129 intel_pch_rawclk(struct drm_device *dev)
130 {
131 struct drm_i915_private *dev_priv = dev->dev_private;
132
133 WARN_ON(!HAS_PCH_SPLIT(dev));
134
135 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
136 }
137
138 static inline u32 /* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device *dev)
140 {
141 if (IS_GEN5(dev)) {
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
144 } else
145 return 27;
146 }
147
148 static const intel_limit_t intel_limits_i8xx_dac = {
149 .dot = { .min = 25000, .max = 350000 },
150 .vco = { .min = 908000, .max = 1512000 },
151 .n = { .min = 2, .max = 16 },
152 .m = { .min = 96, .max = 140 },
153 .m1 = { .min = 18, .max = 26 },
154 .m2 = { .min = 6, .max = 16 },
155 .p = { .min = 4, .max = 128 },
156 .p1 = { .min = 2, .max = 33 },
157 .p2 = { .dot_limit = 165000,
158 .p2_slow = 4, .p2_fast = 2 },
159 };
160
161 static const intel_limit_t intel_limits_i8xx_dvo = {
162 .dot = { .min = 25000, .max = 350000 },
163 .vco = { .min = 908000, .max = 1512000 },
164 .n = { .min = 2, .max = 16 },
165 .m = { .min = 96, .max = 140 },
166 .m1 = { .min = 18, .max = 26 },
167 .m2 = { .min = 6, .max = 16 },
168 .p = { .min = 4, .max = 128 },
169 .p1 = { .min = 2, .max = 33 },
170 .p2 = { .dot_limit = 165000,
171 .p2_slow = 4, .p2_fast = 4 },
172 };
173
174 static const intel_limit_t intel_limits_i8xx_lvds = {
175 .dot = { .min = 25000, .max = 350000 },
176 .vco = { .min = 908000, .max = 1512000 },
177 .n = { .min = 2, .max = 16 },
178 .m = { .min = 96, .max = 140 },
179 .m1 = { .min = 18, .max = 26 },
180 .m2 = { .min = 6, .max = 16 },
181 .p = { .min = 4, .max = 128 },
182 .p1 = { .min = 1, .max = 6 },
183 .p2 = { .dot_limit = 165000,
184 .p2_slow = 14, .p2_fast = 7 },
185 };
186
187 static const intel_limit_t intel_limits_i9xx_sdvo = {
188 .dot = { .min = 20000, .max = 400000 },
189 .vco = { .min = 1400000, .max = 2800000 },
190 .n = { .min = 1, .max = 6 },
191 .m = { .min = 70, .max = 120 },
192 .m1 = { .min = 8, .max = 18 },
193 .m2 = { .min = 3, .max = 7 },
194 .p = { .min = 5, .max = 80 },
195 .p1 = { .min = 1, .max = 8 },
196 .p2 = { .dot_limit = 200000,
197 .p2_slow = 10, .p2_fast = 5 },
198 };
199
200 static const intel_limit_t intel_limits_i9xx_lvds = {
201 .dot = { .min = 20000, .max = 400000 },
202 .vco = { .min = 1400000, .max = 2800000 },
203 .n = { .min = 1, .max = 6 },
204 .m = { .min = 70, .max = 120 },
205 .m1 = { .min = 8, .max = 18 },
206 .m2 = { .min = 3, .max = 7 },
207 .p = { .min = 7, .max = 98 },
208 .p1 = { .min = 1, .max = 8 },
209 .p2 = { .dot_limit = 112000,
210 .p2_slow = 14, .p2_fast = 7 },
211 };
212
213
214 static const intel_limit_t intel_limits_g4x_sdvo = {
215 .dot = { .min = 25000, .max = 270000 },
216 .vco = { .min = 1750000, .max = 3500000},
217 .n = { .min = 1, .max = 4 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 10, .max = 30 },
222 .p1 = { .min = 1, .max = 3},
223 .p2 = { .dot_limit = 270000,
224 .p2_slow = 10,
225 .p2_fast = 10
226 },
227 };
228
229 static const intel_limit_t intel_limits_g4x_hdmi = {
230 .dot = { .min = 22000, .max = 400000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 4 },
233 .m = { .min = 104, .max = 138 },
234 .m1 = { .min = 16, .max = 23 },
235 .m2 = { .min = 5, .max = 11 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8},
238 .p2 = { .dot_limit = 165000,
239 .p2_slow = 10, .p2_fast = 5 },
240 };
241
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
243 .dot = { .min = 20000, .max = 115000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 14, .p2_fast = 14
253 },
254 };
255
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
257 .dot = { .min = 80000, .max = 224000 },
258 .vco = { .min = 1750000, .max = 3500000 },
259 .n = { .min = 1, .max = 3 },
260 .m = { .min = 104, .max = 138 },
261 .m1 = { .min = 17, .max = 23 },
262 .m2 = { .min = 5, .max = 11 },
263 .p = { .min = 14, .max = 42 },
264 .p1 = { .min = 2, .max = 6 },
265 .p2 = { .dot_limit = 0,
266 .p2_slow = 7, .p2_fast = 7
267 },
268 };
269
270 static const intel_limit_t intel_limits_pineview_sdvo = {
271 .dot = { .min = 20000, .max = 400000},
272 .vco = { .min = 1700000, .max = 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1 = { .min = 0, .max = 0 },
278 .m2 = { .min = 0, .max = 254 },
279 .p = { .min = 5, .max = 80 },
280 .p1 = { .min = 1, .max = 8 },
281 .p2 = { .dot_limit = 200000,
282 .p2_slow = 10, .p2_fast = 5 },
283 };
284
285 static const intel_limit_t intel_limits_pineview_lvds = {
286 .dot = { .min = 20000, .max = 400000 },
287 .vco = { .min = 1700000, .max = 3500000 },
288 .n = { .min = 3, .max = 6 },
289 .m = { .min = 2, .max = 256 },
290 .m1 = { .min = 0, .max = 0 },
291 .m2 = { .min = 0, .max = 254 },
292 .p = { .min = 7, .max = 112 },
293 .p1 = { .min = 1, .max = 8 },
294 .p2 = { .dot_limit = 112000,
295 .p2_slow = 14, .p2_fast = 14 },
296 };
297
298 /* Ironlake / Sandybridge
299 *
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
302 */
303 static const intel_limit_t intel_limits_ironlake_dac = {
304 .dot = { .min = 25000, .max = 350000 },
305 .vco = { .min = 1760000, .max = 3510000 },
306 .n = { .min = 1, .max = 5 },
307 .m = { .min = 79, .max = 127 },
308 .m1 = { .min = 12, .max = 22 },
309 .m2 = { .min = 5, .max = 9 },
310 .p = { .min = 5, .max = 80 },
311 .p1 = { .min = 1, .max = 8 },
312 .p2 = { .dot_limit = 225000,
313 .p2_slow = 10, .p2_fast = 5 },
314 };
315
316 static const intel_limit_t intel_limits_ironlake_single_lvds = {
317 .dot = { .min = 25000, .max = 350000 },
318 .vco = { .min = 1760000, .max = 3510000 },
319 .n = { .min = 1, .max = 3 },
320 .m = { .min = 79, .max = 118 },
321 .m1 = { .min = 12, .max = 22 },
322 .m2 = { .min = 5, .max = 9 },
323 .p = { .min = 28, .max = 112 },
324 .p1 = { .min = 2, .max = 8 },
325 .p2 = { .dot_limit = 225000,
326 .p2_slow = 14, .p2_fast = 14 },
327 };
328
329 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
330 .dot = { .min = 25000, .max = 350000 },
331 .vco = { .min = 1760000, .max = 3510000 },
332 .n = { .min = 1, .max = 3 },
333 .m = { .min = 79, .max = 127 },
334 .m1 = { .min = 12, .max = 22 },
335 .m2 = { .min = 5, .max = 9 },
336 .p = { .min = 14, .max = 56 },
337 .p1 = { .min = 2, .max = 8 },
338 .p2 = { .dot_limit = 225000,
339 .p2_slow = 7, .p2_fast = 7 },
340 };
341
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
344 .dot = { .min = 25000, .max = 350000 },
345 .vco = { .min = 1760000, .max = 3510000 },
346 .n = { .min = 1, .max = 2 },
347 .m = { .min = 79, .max = 126 },
348 .m1 = { .min = 12, .max = 22 },
349 .m2 = { .min = 5, .max = 9 },
350 .p = { .min = 28, .max = 112 },
351 .p1 = { .min = 2, .max = 8 },
352 .p2 = { .dot_limit = 225000,
353 .p2_slow = 14, .p2_fast = 14 },
354 };
355
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
357 .dot = { .min = 25000, .max = 350000 },
358 .vco = { .min = 1760000, .max = 3510000 },
359 .n = { .min = 1, .max = 3 },
360 .m = { .min = 79, .max = 126 },
361 .m1 = { .min = 12, .max = 22 },
362 .m2 = { .min = 5, .max = 9 },
363 .p = { .min = 14, .max = 42 },
364 .p1 = { .min = 2, .max = 6 },
365 .p2 = { .dot_limit = 225000,
366 .p2_slow = 7, .p2_fast = 7 },
367 };
368
369 static const intel_limit_t intel_limits_vlv = {
370 /*
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
375 */
376 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m1 = { .min = 2, .max = 3 },
380 .m2 = { .min = 11, .max = 156 },
381 .p1 = { .min = 2, .max = 3 },
382 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
383 };
384
385 static const intel_limit_t intel_limits_chv = {
386 /*
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
391 */
392 .dot = { .min = 25000 * 5, .max = 540000 * 5},
393 .vco = { .min = 4800000, .max = 6480000 },
394 .n = { .min = 1, .max = 1 },
395 .m1 = { .min = 2, .max = 2 },
396 .m2 = { .min = 24 << 22, .max = 175 << 22 },
397 .p1 = { .min = 2, .max = 4 },
398 .p2 = { .p2_slow = 1, .p2_fast = 14 },
399 };
400
401 static void vlv_clock(int refclk, intel_clock_t *clock)
402 {
403 clock->m = clock->m1 * clock->m2;
404 clock->p = clock->p1 * clock->p2;
405 if (WARN_ON(clock->n == 0 || clock->p == 0))
406 return;
407 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
408 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
409 }
410
411 /**
412 * Returns whether any output on the specified pipe is of the specified type
413 */
414 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
415 {
416 struct drm_device *dev = crtc->base.dev;
417 struct intel_encoder *encoder;
418
419 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
420 if (encoder->type == type)
421 return true;
422
423 return false;
424 }
425
426 /**
427 * Returns whether any output on the specified pipe will have the specified
428 * type after a staged modeset is complete, i.e., the same as
429 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
430 * encoder->crtc.
431 */
432 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
433 {
434 struct drm_device *dev = crtc->base.dev;
435 struct intel_encoder *encoder;
436
437 for_each_intel_encoder(dev, encoder)
438 if (encoder->new_crtc == crtc && encoder->type == type)
439 return true;
440
441 return false;
442 }
443
444 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
445 int refclk)
446 {
447 struct drm_device *dev = crtc->base.dev;
448 const intel_limit_t *limit;
449
450 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
451 if (intel_is_dual_link_lvds(dev)) {
452 if (refclk == 100000)
453 limit = &intel_limits_ironlake_dual_lvds_100m;
454 else
455 limit = &intel_limits_ironlake_dual_lvds;
456 } else {
457 if (refclk == 100000)
458 limit = &intel_limits_ironlake_single_lvds_100m;
459 else
460 limit = &intel_limits_ironlake_single_lvds;
461 }
462 } else
463 limit = &intel_limits_ironlake_dac;
464
465 return limit;
466 }
467
468 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
469 {
470 struct drm_device *dev = crtc->base.dev;
471 const intel_limit_t *limit;
472
473 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
474 if (intel_is_dual_link_lvds(dev))
475 limit = &intel_limits_g4x_dual_channel_lvds;
476 else
477 limit = &intel_limits_g4x_single_channel_lvds;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
479 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
480 limit = &intel_limits_g4x_hdmi;
481 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
482 limit = &intel_limits_g4x_sdvo;
483 } else /* The option is for other outputs */
484 limit = &intel_limits_i9xx_sdvo;
485
486 return limit;
487 }
488
489 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
490 {
491 struct drm_device *dev = crtc->base.dev;
492 const intel_limit_t *limit;
493
494 if (HAS_PCH_SPLIT(dev))
495 limit = intel_ironlake_limit(crtc, refclk);
496 else if (IS_G4X(dev)) {
497 limit = intel_g4x_limit(crtc);
498 } else if (IS_PINEVIEW(dev)) {
499 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
500 limit = &intel_limits_pineview_lvds;
501 else
502 limit = &intel_limits_pineview_sdvo;
503 } else if (IS_CHERRYVIEW(dev)) {
504 limit = &intel_limits_chv;
505 } else if (IS_VALLEYVIEW(dev)) {
506 limit = &intel_limits_vlv;
507 } else if (!IS_GEN2(dev)) {
508 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
509 limit = &intel_limits_i9xx_lvds;
510 else
511 limit = &intel_limits_i9xx_sdvo;
512 } else {
513 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
514 limit = &intel_limits_i8xx_lvds;
515 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
516 limit = &intel_limits_i8xx_dvo;
517 else
518 limit = &intel_limits_i8xx_dac;
519 }
520 return limit;
521 }
522
523 /* m1 is reserved as 0 in Pineview, n is a ring counter */
524 static void pineview_clock(int refclk, intel_clock_t *clock)
525 {
526 clock->m = clock->m2 + 2;
527 clock->p = clock->p1 * clock->p2;
528 if (WARN_ON(clock->n == 0 || clock->p == 0))
529 return;
530 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
531 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
532 }
533
534 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
535 {
536 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
537 }
538
539 static void i9xx_clock(int refclk, intel_clock_t *clock)
540 {
541 clock->m = i9xx_dpll_compute_m(clock);
542 clock->p = clock->p1 * clock->p2;
543 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
544 return;
545 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
546 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
547 }
548
549 static void chv_clock(int refclk, intel_clock_t *clock)
550 {
551 clock->m = clock->m1 * clock->m2;
552 clock->p = clock->p1 * clock->p2;
553 if (WARN_ON(clock->n == 0 || clock->p == 0))
554 return;
555 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
556 clock->n << 22);
557 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
558 }
559
560 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
561 /**
562 * Returns whether the given set of divisors are valid for a given refclk with
563 * the given connectors.
564 */
565
566 static bool intel_PLL_is_valid(struct drm_device *dev,
567 const intel_limit_t *limit,
568 const intel_clock_t *clock)
569 {
570 if (clock->n < limit->n.min || limit->n.max < clock->n)
571 INTELPllInvalid("n out of range\n");
572 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
573 INTELPllInvalid("p1 out of range\n");
574 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
575 INTELPllInvalid("m2 out of range\n");
576 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
577 INTELPllInvalid("m1 out of range\n");
578
579 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
580 if (clock->m1 <= clock->m2)
581 INTELPllInvalid("m1 <= m2\n");
582
583 if (!IS_VALLEYVIEW(dev)) {
584 if (clock->p < limit->p.min || limit->p.max < clock->p)
585 INTELPllInvalid("p out of range\n");
586 if (clock->m < limit->m.min || limit->m.max < clock->m)
587 INTELPllInvalid("m out of range\n");
588 }
589
590 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
591 INTELPllInvalid("vco out of range\n");
592 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
593 * connector, etc., rather than just a single range.
594 */
595 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
596 INTELPllInvalid("dot out of range\n");
597
598 return true;
599 }
600
601 static bool
602 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
603 int target, int refclk, intel_clock_t *match_clock,
604 intel_clock_t *best_clock)
605 {
606 struct drm_device *dev = crtc->base.dev;
607 intel_clock_t clock;
608 int err = target;
609
610 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
611 /*
612 * For LVDS just rely on its current settings for dual-channel.
613 * We haven't figured out how to reliably set up different
614 * single/dual channel state, if we even can.
615 */
616 if (intel_is_dual_link_lvds(dev))
617 clock.p2 = limit->p2.p2_fast;
618 else
619 clock.p2 = limit->p2.p2_slow;
620 } else {
621 if (target < limit->p2.dot_limit)
622 clock.p2 = limit->p2.p2_slow;
623 else
624 clock.p2 = limit->p2.p2_fast;
625 }
626
627 memset(best_clock, 0, sizeof(*best_clock));
628
629 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
630 clock.m1++) {
631 for (clock.m2 = limit->m2.min;
632 clock.m2 <= limit->m2.max; clock.m2++) {
633 if (clock.m2 >= clock.m1)
634 break;
635 for (clock.n = limit->n.min;
636 clock.n <= limit->n.max; clock.n++) {
637 for (clock.p1 = limit->p1.min;
638 clock.p1 <= limit->p1.max; clock.p1++) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645 if (match_clock &&
646 clock.p != match_clock->p)
647 continue;
648
649 this_err = abs(clock.dot - target);
650 if (this_err < err) {
651 *best_clock = clock;
652 err = this_err;
653 }
654 }
655 }
656 }
657 }
658
659 return (err != target);
660 }
661
662 static bool
663 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
664 int target, int refclk, intel_clock_t *match_clock,
665 intel_clock_t *best_clock)
666 {
667 struct drm_device *dev = crtc->base.dev;
668 intel_clock_t clock;
669 int err = target;
670
671 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
672 /*
673 * For LVDS just rely on its current settings for dual-channel.
674 * We haven't figured out how to reliably set up different
675 * single/dual channel state, if we even can.
676 */
677 if (intel_is_dual_link_lvds(dev))
678 clock.p2 = limit->p2.p2_fast;
679 else
680 clock.p2 = limit->p2.p2_slow;
681 } else {
682 if (target < limit->p2.dot_limit)
683 clock.p2 = limit->p2.p2_slow;
684 else
685 clock.p2 = limit->p2.p2_fast;
686 }
687
688 memset(best_clock, 0, sizeof(*best_clock));
689
690 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
691 clock.m1++) {
692 for (clock.m2 = limit->m2.min;
693 clock.m2 <= limit->m2.max; clock.m2++) {
694 for (clock.n = limit->n.min;
695 clock.n <= limit->n.max; clock.n++) {
696 for (clock.p1 = limit->p1.min;
697 clock.p1 <= limit->p1.max; clock.p1++) {
698 int this_err;
699
700 pineview_clock(refclk, &clock);
701 if (!intel_PLL_is_valid(dev, limit,
702 &clock))
703 continue;
704 if (match_clock &&
705 clock.p != match_clock->p)
706 continue;
707
708 this_err = abs(clock.dot - target);
709 if (this_err < err) {
710 *best_clock = clock;
711 err = this_err;
712 }
713 }
714 }
715 }
716 }
717
718 return (err != target);
719 }
720
721 static bool
722 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
723 int target, int refclk, intel_clock_t *match_clock,
724 intel_clock_t *best_clock)
725 {
726 struct drm_device *dev = crtc->base.dev;
727 intel_clock_t clock;
728 int max_n;
729 bool found;
730 /* approximately equals target * 0.00585 */
731 int err_most = (target >> 8) + (target >> 9);
732 found = false;
733
734 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
735 if (intel_is_dual_link_lvds(dev))
736 clock.p2 = limit->p2.p2_fast;
737 else
738 clock.p2 = limit->p2.p2_slow;
739 } else {
740 if (target < limit->p2.dot_limit)
741 clock.p2 = limit->p2.p2_slow;
742 else
743 clock.p2 = limit->p2.p2_fast;
744 }
745
746 memset(best_clock, 0, sizeof(*best_clock));
747 max_n = limit->n.max;
748 /* based on hardware requirement, prefer smaller n to precision */
749 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
750 /* based on hardware requirement, prefere larger m1,m2 */
751 for (clock.m1 = limit->m1.max;
752 clock.m1 >= limit->m1.min; clock.m1--) {
753 for (clock.m2 = limit->m2.max;
754 clock.m2 >= limit->m2.min; clock.m2--) {
755 for (clock.p1 = limit->p1.max;
756 clock.p1 >= limit->p1.min; clock.p1--) {
757 int this_err;
758
759 i9xx_clock(refclk, &clock);
760 if (!intel_PLL_is_valid(dev, limit,
761 &clock))
762 continue;
763
764 this_err = abs(clock.dot - target);
765 if (this_err < err_most) {
766 *best_clock = clock;
767 err_most = this_err;
768 max_n = clock.n;
769 found = true;
770 }
771 }
772 }
773 }
774 }
775 return found;
776 }
777
778 static bool
779 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
780 int target, int refclk, intel_clock_t *match_clock,
781 intel_clock_t *best_clock)
782 {
783 struct drm_device *dev = crtc->base.dev;
784 intel_clock_t clock;
785 unsigned int bestppm = 1000000;
786 /* min update 19.2 MHz */
787 int max_n = min(limit->n.max, refclk / 19200);
788 bool found = false;
789
790 target *= 5; /* fast clock */
791
792 memset(best_clock, 0, sizeof(*best_clock));
793
794 /* based on hardware requirement, prefer smaller n to precision */
795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
796 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
797 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
798 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
799 clock.p = clock.p1 * clock.p2;
800 /* based on hardware requirement, prefer bigger m1,m2 values */
801 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
802 unsigned int ppm, diff;
803
804 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
805 refclk * clock.m1);
806
807 vlv_clock(refclk, &clock);
808
809 if (!intel_PLL_is_valid(dev, limit,
810 &clock))
811 continue;
812
813 diff = abs(clock.dot - target);
814 ppm = div_u64(1000000ULL * diff, target);
815
816 if (ppm < 100 && clock.p > best_clock->p) {
817 bestppm = 0;
818 *best_clock = clock;
819 found = true;
820 }
821
822 if (bestppm >= 10 && ppm < bestppm - 10) {
823 bestppm = ppm;
824 *best_clock = clock;
825 found = true;
826 }
827 }
828 }
829 }
830 }
831
832 return found;
833 }
834
835 static bool
836 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
839 {
840 struct drm_device *dev = crtc->base.dev;
841 intel_clock_t clock;
842 uint64_t m2;
843 int found = false;
844
845 memset(best_clock, 0, sizeof(*best_clock));
846
847 /*
848 * Based on hardware doc, the n always set to 1, and m1 always
849 * set to 2. If requires to support 200Mhz refclk, we need to
850 * revisit this because n may not 1 anymore.
851 */
852 clock.n = 1, clock.m1 = 2;
853 target *= 5; /* fast clock */
854
855 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
856 for (clock.p2 = limit->p2.p2_fast;
857 clock.p2 >= limit->p2.p2_slow;
858 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
859
860 clock.p = clock.p1 * clock.p2;
861
862 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
863 clock.n) << 22, refclk * clock.m1);
864
865 if (m2 > INT_MAX/clock.m1)
866 continue;
867
868 clock.m2 = m2;
869
870 chv_clock(refclk, &clock);
871
872 if (!intel_PLL_is_valid(dev, limit, &clock))
873 continue;
874
875 /* based on hardware requirement, prefer bigger p
876 */
877 if (clock.p > best_clock->p) {
878 *best_clock = clock;
879 found = true;
880 }
881 }
882 }
883
884 return found;
885 }
886
887 bool intel_crtc_active(struct drm_crtc *crtc)
888 {
889 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
890
891 /* Be paranoid as we can arrive here with only partial
892 * state retrieved from the hardware during setup.
893 *
894 * We can ditch the adjusted_mode.crtc_clock check as soon
895 * as Haswell has gained clock readout/fastboot support.
896 *
897 * We can ditch the crtc->primary->fb check as soon as we can
898 * properly reconstruct framebuffers.
899 *
900 * FIXME: The intel_crtc->active here should be switched to
901 * crtc->state->active once we have proper CRTC states wired up
902 * for atomic.
903 */
904 return intel_crtc->active && crtc->primary->state->fb &&
905 intel_crtc->config->base.adjusted_mode.crtc_clock;
906 }
907
908 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
909 enum pipe pipe)
910 {
911 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
913
914 return intel_crtc->config->cpu_transcoder;
915 }
916
917 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
918 {
919 struct drm_i915_private *dev_priv = dev->dev_private;
920 u32 reg = PIPEDSL(pipe);
921 u32 line1, line2;
922 u32 line_mask;
923
924 if (IS_GEN2(dev))
925 line_mask = DSL_LINEMASK_GEN2;
926 else
927 line_mask = DSL_LINEMASK_GEN3;
928
929 line1 = I915_READ(reg) & line_mask;
930 mdelay(5);
931 line2 = I915_READ(reg) & line_mask;
932
933 return line1 == line2;
934 }
935
936 /*
937 * intel_wait_for_pipe_off - wait for pipe to turn off
938 * @crtc: crtc whose pipe to wait for
939 *
940 * After disabling a pipe, we can't wait for vblank in the usual way,
941 * spinning on the vblank interrupt status bit, since we won't actually
942 * see an interrupt when the pipe is disabled.
943 *
944 * On Gen4 and above:
945 * wait for the pipe register state bit to turn off
946 *
947 * Otherwise:
948 * wait for the display line value to settle (it usually
949 * ends up stopping at the start of the next frame).
950 *
951 */
952 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
953 {
954 struct drm_device *dev = crtc->base.dev;
955 struct drm_i915_private *dev_priv = dev->dev_private;
956 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
957 enum pipe pipe = crtc->pipe;
958
959 if (INTEL_INFO(dev)->gen >= 4) {
960 int reg = PIPECONF(cpu_transcoder);
961
962 /* Wait for the Pipe State to go off */
963 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
964 100))
965 WARN(1, "pipe_off wait timed out\n");
966 } else {
967 /* Wait for the display line to settle */
968 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
969 WARN(1, "pipe_off wait timed out\n");
970 }
971 }
972
973 /*
974 * ibx_digital_port_connected - is the specified port connected?
975 * @dev_priv: i915 private structure
976 * @port: the port to test
977 *
978 * Returns true if @port is connected, false otherwise.
979 */
980 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
981 struct intel_digital_port *port)
982 {
983 u32 bit;
984
985 if (HAS_PCH_IBX(dev_priv->dev)) {
986 switch (port->port) {
987 case PORT_B:
988 bit = SDE_PORTB_HOTPLUG;
989 break;
990 case PORT_C:
991 bit = SDE_PORTC_HOTPLUG;
992 break;
993 case PORT_D:
994 bit = SDE_PORTD_HOTPLUG;
995 break;
996 default:
997 return true;
998 }
999 } else {
1000 switch (port->port) {
1001 case PORT_B:
1002 bit = SDE_PORTB_HOTPLUG_CPT;
1003 break;
1004 case PORT_C:
1005 bit = SDE_PORTC_HOTPLUG_CPT;
1006 break;
1007 case PORT_D:
1008 bit = SDE_PORTD_HOTPLUG_CPT;
1009 break;
1010 default:
1011 return true;
1012 }
1013 }
1014
1015 return I915_READ(SDEISR) & bit;
1016 }
1017
1018 static const char *state_string(bool enabled)
1019 {
1020 return enabled ? "on" : "off";
1021 }
1022
1023 /* Only for pre-ILK configs */
1024 void assert_pll(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026 {
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
1031 reg = DPLL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & DPLL_VCO_ENABLE);
1034 I915_STATE_WARN(cur_state != state,
1035 "PLL state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037 }
1038
1039 /* XXX: the dsi pll is shared between MIPI DSI ports */
1040 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1041 {
1042 u32 val;
1043 bool cur_state;
1044
1045 mutex_lock(&dev_priv->dpio_lock);
1046 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1047 mutex_unlock(&dev_priv->dpio_lock);
1048
1049 cur_state = val & DSI_PLL_VCO_EN;
1050 I915_STATE_WARN(cur_state != state,
1051 "DSI PLL state assertion failure (expected %s, current %s)\n",
1052 state_string(state), state_string(cur_state));
1053 }
1054 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1055 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1056
1057 struct intel_shared_dpll *
1058 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1059 {
1060 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1061
1062 if (crtc->config->shared_dpll < 0)
1063 return NULL;
1064
1065 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1066 }
1067
1068 /* For ILK+ */
1069 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1070 struct intel_shared_dpll *pll,
1071 bool state)
1072 {
1073 bool cur_state;
1074 struct intel_dpll_hw_state hw_state;
1075
1076 if (WARN (!pll,
1077 "asserting DPLL %s with no DPLL\n", state_string(state)))
1078 return;
1079
1080 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1081 I915_STATE_WARN(cur_state != state,
1082 "%s assertion failure (expected %s, current %s)\n",
1083 pll->name, state_string(state), state_string(cur_state));
1084 }
1085
1086 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1087 enum pipe pipe, bool state)
1088 {
1089 int reg;
1090 u32 val;
1091 bool cur_state;
1092 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1093 pipe);
1094
1095 if (HAS_DDI(dev_priv->dev)) {
1096 /* DDI does not have a specific FDI_TX register */
1097 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1098 val = I915_READ(reg);
1099 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1100 } else {
1101 reg = FDI_TX_CTL(pipe);
1102 val = I915_READ(reg);
1103 cur_state = !!(val & FDI_TX_ENABLE);
1104 }
1105 I915_STATE_WARN(cur_state != state,
1106 "FDI TX state assertion failure (expected %s, current %s)\n",
1107 state_string(state), state_string(cur_state));
1108 }
1109 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1110 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1111
1112 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118
1119 reg = FDI_RX_CTL(pipe);
1120 val = I915_READ(reg);
1121 cur_state = !!(val & FDI_RX_ENABLE);
1122 I915_STATE_WARN(cur_state != state,
1123 "FDI RX state assertion failure (expected %s, current %s)\n",
1124 state_string(state), state_string(cur_state));
1125 }
1126 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1127 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1128
1129 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1130 enum pipe pipe)
1131 {
1132 int reg;
1133 u32 val;
1134
1135 /* ILK FDI PLL is always enabled */
1136 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1137 return;
1138
1139 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1140 if (HAS_DDI(dev_priv->dev))
1141 return;
1142
1143 reg = FDI_TX_CTL(pipe);
1144 val = I915_READ(reg);
1145 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1146 }
1147
1148 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1149 enum pipe pipe, bool state)
1150 {
1151 int reg;
1152 u32 val;
1153 bool cur_state;
1154
1155 reg = FDI_RX_CTL(pipe);
1156 val = I915_READ(reg);
1157 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1158 I915_STATE_WARN(cur_state != state,
1159 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1160 state_string(state), state_string(cur_state));
1161 }
1162
1163 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1164 enum pipe pipe)
1165 {
1166 struct drm_device *dev = dev_priv->dev;
1167 int pp_reg;
1168 u32 val;
1169 enum pipe panel_pipe = PIPE_A;
1170 bool locked = true;
1171
1172 if (WARN_ON(HAS_DDI(dev)))
1173 return;
1174
1175 if (HAS_PCH_SPLIT(dev)) {
1176 u32 port_sel;
1177
1178 pp_reg = PCH_PP_CONTROL;
1179 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1180
1181 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1182 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1183 panel_pipe = PIPE_B;
1184 /* XXX: else fix for eDP */
1185 } else if (IS_VALLEYVIEW(dev)) {
1186 /* presumably write lock depends on pipe, not port select */
1187 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1188 panel_pipe = pipe;
1189 } else {
1190 pp_reg = PP_CONTROL;
1191 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1192 panel_pipe = PIPE_B;
1193 }
1194
1195 val = I915_READ(pp_reg);
1196 if (!(val & PANEL_POWER_ON) ||
1197 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1198 locked = false;
1199
1200 I915_STATE_WARN(panel_pipe == pipe && locked,
1201 "panel assertion failure, pipe %c regs locked\n",
1202 pipe_name(pipe));
1203 }
1204
1205 static void assert_cursor(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, bool state)
1207 {
1208 struct drm_device *dev = dev_priv->dev;
1209 bool cur_state;
1210
1211 if (IS_845G(dev) || IS_I865G(dev))
1212 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1213 else
1214 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1215
1216 I915_STATE_WARN(cur_state != state,
1217 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1218 pipe_name(pipe), state_string(state), state_string(cur_state));
1219 }
1220 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1221 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1222
1223 void assert_pipe(struct drm_i915_private *dev_priv,
1224 enum pipe pipe, bool state)
1225 {
1226 int reg;
1227 u32 val;
1228 bool cur_state;
1229 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1230 pipe);
1231
1232 /* if we need the pipe quirk it must be always on */
1233 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1234 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1235 state = true;
1236
1237 if (!intel_display_power_is_enabled(dev_priv,
1238 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1239 cur_state = false;
1240 } else {
1241 reg = PIPECONF(cpu_transcoder);
1242 val = I915_READ(reg);
1243 cur_state = !!(val & PIPECONF_ENABLE);
1244 }
1245
1246 I915_STATE_WARN(cur_state != state,
1247 "pipe %c assertion failure (expected %s, current %s)\n",
1248 pipe_name(pipe), state_string(state), state_string(cur_state));
1249 }
1250
1251 static void assert_plane(struct drm_i915_private *dev_priv,
1252 enum plane plane, bool state)
1253 {
1254 int reg;
1255 u32 val;
1256 bool cur_state;
1257
1258 reg = DSPCNTR(plane);
1259 val = I915_READ(reg);
1260 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1261 I915_STATE_WARN(cur_state != state,
1262 "plane %c assertion failure (expected %s, current %s)\n",
1263 plane_name(plane), state_string(state), state_string(cur_state));
1264 }
1265
1266 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1267 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1268
1269 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe)
1271 {
1272 struct drm_device *dev = dev_priv->dev;
1273 int reg, i;
1274 u32 val;
1275 int cur_pipe;
1276
1277 /* Primary planes are fixed to pipes on gen4+ */
1278 if (INTEL_INFO(dev)->gen >= 4) {
1279 reg = DSPCNTR(pipe);
1280 val = I915_READ(reg);
1281 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1282 "plane %c assertion failure, should be disabled but not\n",
1283 plane_name(pipe));
1284 return;
1285 }
1286
1287 /* Need to check both planes against the pipe */
1288 for_each_pipe(dev_priv, i) {
1289 reg = DSPCNTR(i);
1290 val = I915_READ(reg);
1291 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1292 DISPPLANE_SEL_PIPE_SHIFT;
1293 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1294 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1295 plane_name(i), pipe_name(pipe));
1296 }
1297 }
1298
1299 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1300 enum pipe pipe)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 int reg, sprite;
1304 u32 val;
1305
1306 if (INTEL_INFO(dev)->gen >= 9) {
1307 for_each_sprite(dev_priv, pipe, sprite) {
1308 val = I915_READ(PLANE_CTL(pipe, sprite));
1309 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1310 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1311 sprite, pipe_name(pipe));
1312 }
1313 } else if (IS_VALLEYVIEW(dev)) {
1314 for_each_sprite(dev_priv, pipe, sprite) {
1315 reg = SPCNTR(pipe, sprite);
1316 val = I915_READ(reg);
1317 I915_STATE_WARN(val & SP_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 sprite_name(pipe, sprite), pipe_name(pipe));
1320 }
1321 } else if (INTEL_INFO(dev)->gen >= 7) {
1322 reg = SPRCTL(pipe);
1323 val = I915_READ(reg);
1324 I915_STATE_WARN(val & SPRITE_ENABLE,
1325 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(pipe), pipe_name(pipe));
1327 } else if (INTEL_INFO(dev)->gen >= 5) {
1328 reg = DVSCNTR(pipe);
1329 val = I915_READ(reg);
1330 I915_STATE_WARN(val & DVS_ENABLE,
1331 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1332 plane_name(pipe), pipe_name(pipe));
1333 }
1334 }
1335
1336 static void assert_vblank_disabled(struct drm_crtc *crtc)
1337 {
1338 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1339 drm_crtc_vblank_put(crtc);
1340 }
1341
1342 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1343 {
1344 u32 val;
1345 bool enabled;
1346
1347 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1348
1349 val = I915_READ(PCH_DREF_CONTROL);
1350 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1351 DREF_SUPERSPREAD_SOURCE_MASK));
1352 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1353 }
1354
1355 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe)
1357 {
1358 int reg;
1359 u32 val;
1360 bool enabled;
1361
1362 reg = PCH_TRANSCONF(pipe);
1363 val = I915_READ(reg);
1364 enabled = !!(val & TRANS_ENABLE);
1365 I915_STATE_WARN(enabled,
1366 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1367 pipe_name(pipe));
1368 }
1369
1370 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1371 enum pipe pipe, u32 port_sel, u32 val)
1372 {
1373 if ((val & DP_PORT_EN) == 0)
1374 return false;
1375
1376 if (HAS_PCH_CPT(dev_priv->dev)) {
1377 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1378 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1379 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1380 return false;
1381 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1382 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1383 return false;
1384 } else {
1385 if ((val & DP_PIPE_MASK) != (pipe << 30))
1386 return false;
1387 }
1388 return true;
1389 }
1390
1391 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1392 enum pipe pipe, u32 val)
1393 {
1394 if ((val & SDVO_ENABLE) == 0)
1395 return false;
1396
1397 if (HAS_PCH_CPT(dev_priv->dev)) {
1398 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1399 return false;
1400 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1401 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1402 return false;
1403 } else {
1404 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1405 return false;
1406 }
1407 return true;
1408 }
1409
1410 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 val)
1412 {
1413 if ((val & LVDS_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1418 return false;
1419 } else {
1420 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1421 return false;
1422 }
1423 return true;
1424 }
1425
1426 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1427 enum pipe pipe, u32 val)
1428 {
1429 if ((val & ADPA_DAC_ENABLE) == 0)
1430 return false;
1431 if (HAS_PCH_CPT(dev_priv->dev)) {
1432 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1433 return false;
1434 } else {
1435 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1436 return false;
1437 }
1438 return true;
1439 }
1440
1441 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1442 enum pipe pipe, int reg, u32 port_sel)
1443 {
1444 u32 val = I915_READ(reg);
1445 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1446 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1447 reg, pipe_name(pipe));
1448
1449 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1450 && (val & DP_PIPEB_SELECT),
1451 "IBX PCH dp port still using transcoder B\n");
1452 }
1453
1454 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1455 enum pipe pipe, int reg)
1456 {
1457 u32 val = I915_READ(reg);
1458 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1459 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1460 reg, pipe_name(pipe));
1461
1462 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1463 && (val & SDVO_PIPE_B_SELECT),
1464 "IBX PCH hdmi port still using transcoder B\n");
1465 }
1466
1467 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe)
1469 {
1470 int reg;
1471 u32 val;
1472
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1474 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1475 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1476
1477 reg = PCH_ADPA;
1478 val = I915_READ(reg);
1479 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1480 "PCH VGA enabled on transcoder %c, should be disabled\n",
1481 pipe_name(pipe));
1482
1483 reg = PCH_LVDS;
1484 val = I915_READ(reg);
1485 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1486 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1487 pipe_name(pipe));
1488
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1490 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1491 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1492 }
1493
1494 static void intel_init_dpio(struct drm_device *dev)
1495 {
1496 struct drm_i915_private *dev_priv = dev->dev_private;
1497
1498 if (!IS_VALLEYVIEW(dev))
1499 return;
1500
1501 /*
1502 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1503 * CHV x1 PHY (DP/HDMI D)
1504 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1505 */
1506 if (IS_CHERRYVIEW(dev)) {
1507 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1508 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1509 } else {
1510 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1511 }
1512 }
1513
1514 static void vlv_enable_pll(struct intel_crtc *crtc,
1515 const struct intel_crtc_state *pipe_config)
1516 {
1517 struct drm_device *dev = crtc->base.dev;
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 int reg = DPLL(crtc->pipe);
1520 u32 dpll = pipe_config->dpll_hw_state.dpll;
1521
1522 assert_pipe_disabled(dev_priv, crtc->pipe);
1523
1524 /* No really, not for ILK+ */
1525 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1526
1527 /* PLL is protected by panel, make sure we can write it */
1528 if (IS_MOBILE(dev_priv->dev))
1529 assert_panel_unlocked(dev_priv, crtc->pipe);
1530
1531 I915_WRITE(reg, dpll);
1532 POSTING_READ(reg);
1533 udelay(150);
1534
1535 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1536 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1537
1538 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1539 POSTING_READ(DPLL_MD(crtc->pipe));
1540
1541 /* We do this three times for luck */
1542 I915_WRITE(reg, dpll);
1543 POSTING_READ(reg);
1544 udelay(150); /* wait for warmup */
1545 I915_WRITE(reg, dpll);
1546 POSTING_READ(reg);
1547 udelay(150); /* wait for warmup */
1548 I915_WRITE(reg, dpll);
1549 POSTING_READ(reg);
1550 udelay(150); /* wait for warmup */
1551 }
1552
1553 static void chv_enable_pll(struct intel_crtc *crtc,
1554 const struct intel_crtc_state *pipe_config)
1555 {
1556 struct drm_device *dev = crtc->base.dev;
1557 struct drm_i915_private *dev_priv = dev->dev_private;
1558 int pipe = crtc->pipe;
1559 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1560 u32 tmp;
1561
1562 assert_pipe_disabled(dev_priv, crtc->pipe);
1563
1564 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1565
1566 mutex_lock(&dev_priv->dpio_lock);
1567
1568 /* Enable back the 10bit clock to display controller */
1569 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1570 tmp |= DPIO_DCLKP_EN;
1571 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1572
1573 /*
1574 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1575 */
1576 udelay(1);
1577
1578 /* Enable PLL */
1579 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1580
1581 /* Check PLL is locked */
1582 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1583 DRM_ERROR("PLL %d failed to lock\n", pipe);
1584
1585 /* not sure when this should be written */
1586 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1587 POSTING_READ(DPLL_MD(pipe));
1588
1589 mutex_unlock(&dev_priv->dpio_lock);
1590 }
1591
1592 static int intel_num_dvo_pipes(struct drm_device *dev)
1593 {
1594 struct intel_crtc *crtc;
1595 int count = 0;
1596
1597 for_each_intel_crtc(dev, crtc)
1598 count += crtc->active &&
1599 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1600
1601 return count;
1602 }
1603
1604 static void i9xx_enable_pll(struct intel_crtc *crtc)
1605 {
1606 struct drm_device *dev = crtc->base.dev;
1607 struct drm_i915_private *dev_priv = dev->dev_private;
1608 int reg = DPLL(crtc->pipe);
1609 u32 dpll = crtc->config->dpll_hw_state.dpll;
1610
1611 assert_pipe_disabled(dev_priv, crtc->pipe);
1612
1613 /* No really, not for ILK+ */
1614 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1615
1616 /* PLL is protected by panel, make sure we can write it */
1617 if (IS_MOBILE(dev) && !IS_I830(dev))
1618 assert_panel_unlocked(dev_priv, crtc->pipe);
1619
1620 /* Enable DVO 2x clock on both PLLs if necessary */
1621 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1622 /*
1623 * It appears to be important that we don't enable this
1624 * for the current pipe before otherwise configuring the
1625 * PLL. No idea how this should be handled if multiple
1626 * DVO outputs are enabled simultaneosly.
1627 */
1628 dpll |= DPLL_DVO_2X_MODE;
1629 I915_WRITE(DPLL(!crtc->pipe),
1630 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1631 }
1632
1633 /* Wait for the clocks to stabilize. */
1634 POSTING_READ(reg);
1635 udelay(150);
1636
1637 if (INTEL_INFO(dev)->gen >= 4) {
1638 I915_WRITE(DPLL_MD(crtc->pipe),
1639 crtc->config->dpll_hw_state.dpll_md);
1640 } else {
1641 /* The pixel multiplier can only be updated once the
1642 * DPLL is enabled and the clocks are stable.
1643 *
1644 * So write it again.
1645 */
1646 I915_WRITE(reg, dpll);
1647 }
1648
1649 /* We do this three times for luck */
1650 I915_WRITE(reg, dpll);
1651 POSTING_READ(reg);
1652 udelay(150); /* wait for warmup */
1653 I915_WRITE(reg, dpll);
1654 POSTING_READ(reg);
1655 udelay(150); /* wait for warmup */
1656 I915_WRITE(reg, dpll);
1657 POSTING_READ(reg);
1658 udelay(150); /* wait for warmup */
1659 }
1660
1661 /**
1662 * i9xx_disable_pll - disable a PLL
1663 * @dev_priv: i915 private structure
1664 * @pipe: pipe PLL to disable
1665 *
1666 * Disable the PLL for @pipe, making sure the pipe is off first.
1667 *
1668 * Note! This is for pre-ILK only.
1669 */
1670 static void i9xx_disable_pll(struct intel_crtc *crtc)
1671 {
1672 struct drm_device *dev = crtc->base.dev;
1673 struct drm_i915_private *dev_priv = dev->dev_private;
1674 enum pipe pipe = crtc->pipe;
1675
1676 /* Disable DVO 2x clock on both PLLs if necessary */
1677 if (IS_I830(dev) &&
1678 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1679 intel_num_dvo_pipes(dev) == 1) {
1680 I915_WRITE(DPLL(PIPE_B),
1681 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1682 I915_WRITE(DPLL(PIPE_A),
1683 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1684 }
1685
1686 /* Don't disable pipe or pipe PLLs if needed */
1687 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1688 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1689 return;
1690
1691 /* Make sure the pipe isn't still relying on us */
1692 assert_pipe_disabled(dev_priv, pipe);
1693
1694 I915_WRITE(DPLL(pipe), 0);
1695 POSTING_READ(DPLL(pipe));
1696 }
1697
1698 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1699 {
1700 u32 val = 0;
1701
1702 /* Make sure the pipe isn't still relying on us */
1703 assert_pipe_disabled(dev_priv, pipe);
1704
1705 /*
1706 * Leave integrated clock source and reference clock enabled for pipe B.
1707 * The latter is needed for VGA hotplug / manual detection.
1708 */
1709 if (pipe == PIPE_B)
1710 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1711 I915_WRITE(DPLL(pipe), val);
1712 POSTING_READ(DPLL(pipe));
1713
1714 }
1715
1716 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1717 {
1718 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1719 u32 val;
1720
1721 /* Make sure the pipe isn't still relying on us */
1722 assert_pipe_disabled(dev_priv, pipe);
1723
1724 /* Set PLL en = 0 */
1725 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1726 if (pipe != PIPE_A)
1727 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1728 I915_WRITE(DPLL(pipe), val);
1729 POSTING_READ(DPLL(pipe));
1730
1731 mutex_lock(&dev_priv->dpio_lock);
1732
1733 /* Disable 10bit clock to display controller */
1734 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1735 val &= ~DPIO_DCLKP_EN;
1736 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1737
1738 /* disable left/right clock distribution */
1739 if (pipe != PIPE_B) {
1740 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1741 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1742 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1743 } else {
1744 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1745 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1746 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1747 }
1748
1749 mutex_unlock(&dev_priv->dpio_lock);
1750 }
1751
1752 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1753 struct intel_digital_port *dport)
1754 {
1755 u32 port_mask;
1756 int dpll_reg;
1757
1758 switch (dport->port) {
1759 case PORT_B:
1760 port_mask = DPLL_PORTB_READY_MASK;
1761 dpll_reg = DPLL(0);
1762 break;
1763 case PORT_C:
1764 port_mask = DPLL_PORTC_READY_MASK;
1765 dpll_reg = DPLL(0);
1766 break;
1767 case PORT_D:
1768 port_mask = DPLL_PORTD_READY_MASK;
1769 dpll_reg = DPIO_PHY_STATUS;
1770 break;
1771 default:
1772 BUG();
1773 }
1774
1775 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1776 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1777 port_name(dport->port), I915_READ(dpll_reg));
1778 }
1779
1780 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1781 {
1782 struct drm_device *dev = crtc->base.dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
1784 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1785
1786 if (WARN_ON(pll == NULL))
1787 return;
1788
1789 WARN_ON(!pll->config.crtc_mask);
1790 if (pll->active == 0) {
1791 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1792 WARN_ON(pll->on);
1793 assert_shared_dpll_disabled(dev_priv, pll);
1794
1795 pll->mode_set(dev_priv, pll);
1796 }
1797 }
1798
1799 /**
1800 * intel_enable_shared_dpll - enable PCH PLL
1801 * @dev_priv: i915 private structure
1802 * @pipe: pipe PLL to enable
1803 *
1804 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1805 * drives the transcoder clock.
1806 */
1807 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1808 {
1809 struct drm_device *dev = crtc->base.dev;
1810 struct drm_i915_private *dev_priv = dev->dev_private;
1811 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1812
1813 if (WARN_ON(pll == NULL))
1814 return;
1815
1816 if (WARN_ON(pll->config.crtc_mask == 0))
1817 return;
1818
1819 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1820 pll->name, pll->active, pll->on,
1821 crtc->base.base.id);
1822
1823 if (pll->active++) {
1824 WARN_ON(!pll->on);
1825 assert_shared_dpll_enabled(dev_priv, pll);
1826 return;
1827 }
1828 WARN_ON(pll->on);
1829
1830 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1831
1832 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1833 pll->enable(dev_priv, pll);
1834 pll->on = true;
1835 }
1836
1837 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1838 {
1839 struct drm_device *dev = crtc->base.dev;
1840 struct drm_i915_private *dev_priv = dev->dev_private;
1841 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1842
1843 /* PCH only available on ILK+ */
1844 BUG_ON(INTEL_INFO(dev)->gen < 5);
1845 if (WARN_ON(pll == NULL))
1846 return;
1847
1848 if (WARN_ON(pll->config.crtc_mask == 0))
1849 return;
1850
1851 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1852 pll->name, pll->active, pll->on,
1853 crtc->base.base.id);
1854
1855 if (WARN_ON(pll->active == 0)) {
1856 assert_shared_dpll_disabled(dev_priv, pll);
1857 return;
1858 }
1859
1860 assert_shared_dpll_enabled(dev_priv, pll);
1861 WARN_ON(!pll->on);
1862 if (--pll->active)
1863 return;
1864
1865 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1866 pll->disable(dev_priv, pll);
1867 pll->on = false;
1868
1869 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1870 }
1871
1872 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1873 enum pipe pipe)
1874 {
1875 struct drm_device *dev = dev_priv->dev;
1876 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1878 uint32_t reg, val, pipeconf_val;
1879
1880 /* PCH only available on ILK+ */
1881 BUG_ON(!HAS_PCH_SPLIT(dev));
1882
1883 /* Make sure PCH DPLL is enabled */
1884 assert_shared_dpll_enabled(dev_priv,
1885 intel_crtc_to_shared_dpll(intel_crtc));
1886
1887 /* FDI must be feeding us bits for PCH ports */
1888 assert_fdi_tx_enabled(dev_priv, pipe);
1889 assert_fdi_rx_enabled(dev_priv, pipe);
1890
1891 if (HAS_PCH_CPT(dev)) {
1892 /* Workaround: Set the timing override bit before enabling the
1893 * pch transcoder. */
1894 reg = TRANS_CHICKEN2(pipe);
1895 val = I915_READ(reg);
1896 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1897 I915_WRITE(reg, val);
1898 }
1899
1900 reg = PCH_TRANSCONF(pipe);
1901 val = I915_READ(reg);
1902 pipeconf_val = I915_READ(PIPECONF(pipe));
1903
1904 if (HAS_PCH_IBX(dev_priv->dev)) {
1905 /*
1906 * make the BPC in transcoder be consistent with
1907 * that in pipeconf reg.
1908 */
1909 val &= ~PIPECONF_BPC_MASK;
1910 val |= pipeconf_val & PIPECONF_BPC_MASK;
1911 }
1912
1913 val &= ~TRANS_INTERLACE_MASK;
1914 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1915 if (HAS_PCH_IBX(dev_priv->dev) &&
1916 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1917 val |= TRANS_LEGACY_INTERLACED_ILK;
1918 else
1919 val |= TRANS_INTERLACED;
1920 else
1921 val |= TRANS_PROGRESSIVE;
1922
1923 I915_WRITE(reg, val | TRANS_ENABLE);
1924 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1925 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1926 }
1927
1928 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1929 enum transcoder cpu_transcoder)
1930 {
1931 u32 val, pipeconf_val;
1932
1933 /* PCH only available on ILK+ */
1934 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1935
1936 /* FDI must be feeding us bits for PCH ports */
1937 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1938 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1939
1940 /* Workaround: set timing override bit. */
1941 val = I915_READ(_TRANSA_CHICKEN2);
1942 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1943 I915_WRITE(_TRANSA_CHICKEN2, val);
1944
1945 val = TRANS_ENABLE;
1946 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1947
1948 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1949 PIPECONF_INTERLACED_ILK)
1950 val |= TRANS_INTERLACED;
1951 else
1952 val |= TRANS_PROGRESSIVE;
1953
1954 I915_WRITE(LPT_TRANSCONF, val);
1955 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1956 DRM_ERROR("Failed to enable PCH transcoder\n");
1957 }
1958
1959 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1960 enum pipe pipe)
1961 {
1962 struct drm_device *dev = dev_priv->dev;
1963 uint32_t reg, val;
1964
1965 /* FDI relies on the transcoder */
1966 assert_fdi_tx_disabled(dev_priv, pipe);
1967 assert_fdi_rx_disabled(dev_priv, pipe);
1968
1969 /* Ports must be off as well */
1970 assert_pch_ports_disabled(dev_priv, pipe);
1971
1972 reg = PCH_TRANSCONF(pipe);
1973 val = I915_READ(reg);
1974 val &= ~TRANS_ENABLE;
1975 I915_WRITE(reg, val);
1976 /* wait for PCH transcoder off, transcoder state */
1977 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1978 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1979
1980 if (!HAS_PCH_IBX(dev)) {
1981 /* Workaround: Clear the timing override chicken bit again. */
1982 reg = TRANS_CHICKEN2(pipe);
1983 val = I915_READ(reg);
1984 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1985 I915_WRITE(reg, val);
1986 }
1987 }
1988
1989 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1990 {
1991 u32 val;
1992
1993 val = I915_READ(LPT_TRANSCONF);
1994 val &= ~TRANS_ENABLE;
1995 I915_WRITE(LPT_TRANSCONF, val);
1996 /* wait for PCH transcoder off, transcoder state */
1997 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1998 DRM_ERROR("Failed to disable PCH transcoder\n");
1999
2000 /* Workaround: clear timing override bit. */
2001 val = I915_READ(_TRANSA_CHICKEN2);
2002 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2003 I915_WRITE(_TRANSA_CHICKEN2, val);
2004 }
2005
2006 /**
2007 * intel_enable_pipe - enable a pipe, asserting requirements
2008 * @crtc: crtc responsible for the pipe
2009 *
2010 * Enable @crtc's pipe, making sure that various hardware specific requirements
2011 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2012 */
2013 static void intel_enable_pipe(struct intel_crtc *crtc)
2014 {
2015 struct drm_device *dev = crtc->base.dev;
2016 struct drm_i915_private *dev_priv = dev->dev_private;
2017 enum pipe pipe = crtc->pipe;
2018 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2019 pipe);
2020 enum pipe pch_transcoder;
2021 int reg;
2022 u32 val;
2023
2024 assert_planes_disabled(dev_priv, pipe);
2025 assert_cursor_disabled(dev_priv, pipe);
2026 assert_sprites_disabled(dev_priv, pipe);
2027
2028 if (HAS_PCH_LPT(dev_priv->dev))
2029 pch_transcoder = TRANSCODER_A;
2030 else
2031 pch_transcoder = pipe;
2032
2033 /*
2034 * A pipe without a PLL won't actually be able to drive bits from
2035 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2036 * need the check.
2037 */
2038 if (!HAS_PCH_SPLIT(dev_priv->dev))
2039 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2040 assert_dsi_pll_enabled(dev_priv);
2041 else
2042 assert_pll_enabled(dev_priv, pipe);
2043 else {
2044 if (crtc->config->has_pch_encoder) {
2045 /* if driving the PCH, we need FDI enabled */
2046 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2047 assert_fdi_tx_pll_enabled(dev_priv,
2048 (enum pipe) cpu_transcoder);
2049 }
2050 /* FIXME: assert CPU port conditions for SNB+ */
2051 }
2052
2053 reg = PIPECONF(cpu_transcoder);
2054 val = I915_READ(reg);
2055 if (val & PIPECONF_ENABLE) {
2056 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2057 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2058 return;
2059 }
2060
2061 I915_WRITE(reg, val | PIPECONF_ENABLE);
2062 POSTING_READ(reg);
2063 }
2064
2065 /**
2066 * intel_disable_pipe - disable a pipe, asserting requirements
2067 * @crtc: crtc whose pipes is to be disabled
2068 *
2069 * Disable the pipe of @crtc, making sure that various hardware
2070 * specific requirements are met, if applicable, e.g. plane
2071 * disabled, panel fitter off, etc.
2072 *
2073 * Will wait until the pipe has shut down before returning.
2074 */
2075 static void intel_disable_pipe(struct intel_crtc *crtc)
2076 {
2077 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2078 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2079 enum pipe pipe = crtc->pipe;
2080 int reg;
2081 u32 val;
2082
2083 /*
2084 * Make sure planes won't keep trying to pump pixels to us,
2085 * or we might hang the display.
2086 */
2087 assert_planes_disabled(dev_priv, pipe);
2088 assert_cursor_disabled(dev_priv, pipe);
2089 assert_sprites_disabled(dev_priv, pipe);
2090
2091 reg = PIPECONF(cpu_transcoder);
2092 val = I915_READ(reg);
2093 if ((val & PIPECONF_ENABLE) == 0)
2094 return;
2095
2096 /*
2097 * Double wide has implications for planes
2098 * so best keep it disabled when not needed.
2099 */
2100 if (crtc->config->double_wide)
2101 val &= ~PIPECONF_DOUBLE_WIDE;
2102
2103 /* Don't disable pipe or pipe PLLs if needed */
2104 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2105 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2106 val &= ~PIPECONF_ENABLE;
2107
2108 I915_WRITE(reg, val);
2109 if ((val & PIPECONF_ENABLE) == 0)
2110 intel_wait_for_pipe_off(crtc);
2111 }
2112
2113 /*
2114 * Plane regs are double buffered, going from enabled->disabled needs a
2115 * trigger in order to latch. The display address reg provides this.
2116 */
2117 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2118 enum plane plane)
2119 {
2120 struct drm_device *dev = dev_priv->dev;
2121 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2122
2123 I915_WRITE(reg, I915_READ(reg));
2124 POSTING_READ(reg);
2125 }
2126
2127 /**
2128 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2129 * @plane: plane to be enabled
2130 * @crtc: crtc for the plane
2131 *
2132 * Enable @plane on @crtc, making sure that the pipe is running first.
2133 */
2134 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2135 struct drm_crtc *crtc)
2136 {
2137 struct drm_device *dev = plane->dev;
2138 struct drm_i915_private *dev_priv = dev->dev_private;
2139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2140
2141 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2142 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2143
2144 if (intel_crtc->primary_enabled)
2145 return;
2146
2147 intel_crtc->primary_enabled = true;
2148
2149 dev_priv->display.update_primary_plane(crtc, plane->fb,
2150 crtc->x, crtc->y);
2151
2152 /*
2153 * BDW signals flip done immediately if the plane
2154 * is disabled, even if the plane enable is already
2155 * armed to occur at the next vblank :(
2156 */
2157 if (IS_BROADWELL(dev))
2158 intel_wait_for_vblank(dev, intel_crtc->pipe);
2159 }
2160
2161 /**
2162 * intel_disable_primary_hw_plane - disable the primary hardware plane
2163 * @plane: plane to be disabled
2164 * @crtc: crtc for the plane
2165 *
2166 * Disable @plane on @crtc, making sure that the pipe is running first.
2167 */
2168 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2169 struct drm_crtc *crtc)
2170 {
2171 struct drm_device *dev = plane->dev;
2172 struct drm_i915_private *dev_priv = dev->dev_private;
2173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2174
2175 if (WARN_ON(!intel_crtc->active))
2176 return;
2177
2178 if (!intel_crtc->primary_enabled)
2179 return;
2180
2181 intel_crtc->primary_enabled = false;
2182
2183 dev_priv->display.update_primary_plane(crtc, plane->fb,
2184 crtc->x, crtc->y);
2185 }
2186
2187 static bool need_vtd_wa(struct drm_device *dev)
2188 {
2189 #ifdef CONFIG_INTEL_IOMMU
2190 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2191 return true;
2192 #endif
2193 return false;
2194 }
2195
2196 int
2197 intel_fb_align_height(struct drm_device *dev, int height,
2198 uint32_t pixel_format,
2199 uint64_t fb_format_modifier)
2200 {
2201 int tile_height;
2202 uint32_t bits_per_pixel;
2203
2204 switch (fb_format_modifier) {
2205 case DRM_FORMAT_MOD_NONE:
2206 tile_height = 1;
2207 break;
2208 case I915_FORMAT_MOD_X_TILED:
2209 tile_height = IS_GEN2(dev) ? 16 : 8;
2210 break;
2211 case I915_FORMAT_MOD_Y_TILED:
2212 tile_height = 32;
2213 break;
2214 case I915_FORMAT_MOD_Yf_TILED:
2215 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2216 switch (bits_per_pixel) {
2217 default:
2218 case 8:
2219 tile_height = 64;
2220 break;
2221 case 16:
2222 case 32:
2223 tile_height = 32;
2224 break;
2225 case 64:
2226 tile_height = 16;
2227 break;
2228 case 128:
2229 WARN_ONCE(1,
2230 "128-bit pixels are not supported for display!");
2231 tile_height = 16;
2232 break;
2233 }
2234 break;
2235 default:
2236 MISSING_CASE(fb_format_modifier);
2237 tile_height = 1;
2238 break;
2239 }
2240
2241 return ALIGN(height, tile_height);
2242 }
2243
2244 int
2245 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2246 struct drm_framebuffer *fb,
2247 struct intel_engine_cs *pipelined)
2248 {
2249 struct drm_device *dev = fb->dev;
2250 struct drm_i915_private *dev_priv = dev->dev_private;
2251 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2252 u32 alignment;
2253 int ret;
2254
2255 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2256
2257 switch (fb->modifier[0]) {
2258 case DRM_FORMAT_MOD_NONE:
2259 if (INTEL_INFO(dev)->gen >= 9)
2260 alignment = 256 * 1024;
2261 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2262 alignment = 128 * 1024;
2263 else if (INTEL_INFO(dev)->gen >= 4)
2264 alignment = 4 * 1024;
2265 else
2266 alignment = 64 * 1024;
2267 break;
2268 case I915_FORMAT_MOD_X_TILED:
2269 if (INTEL_INFO(dev)->gen >= 9)
2270 alignment = 256 * 1024;
2271 else {
2272 /* pin() will align the object as required by fence */
2273 alignment = 0;
2274 }
2275 break;
2276 case I915_FORMAT_MOD_Y_TILED:
2277 case I915_FORMAT_MOD_Yf_TILED:
2278 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2279 "Y tiling bo slipped through, driver bug!\n"))
2280 return -EINVAL;
2281 alignment = 1 * 1024 * 1024;
2282 break;
2283 default:
2284 MISSING_CASE(fb->modifier[0]);
2285 return -EINVAL;
2286 }
2287
2288 /* Note that the w/a also requires 64 PTE of padding following the
2289 * bo. We currently fill all unused PTE with the shadow page and so
2290 * we should always have valid PTE following the scanout preventing
2291 * the VT-d warning.
2292 */
2293 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2294 alignment = 256 * 1024;
2295
2296 /*
2297 * Global gtt pte registers are special registers which actually forward
2298 * writes to a chunk of system memory. Which means that there is no risk
2299 * that the register values disappear as soon as we call
2300 * intel_runtime_pm_put(), so it is correct to wrap only the
2301 * pin/unpin/fence and not more.
2302 */
2303 intel_runtime_pm_get(dev_priv);
2304
2305 dev_priv->mm.interruptible = false;
2306 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2307 if (ret)
2308 goto err_interruptible;
2309
2310 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2311 * fence, whereas 965+ only requires a fence if using
2312 * framebuffer compression. For simplicity, we always install
2313 * a fence as the cost is not that onerous.
2314 */
2315 ret = i915_gem_object_get_fence(obj);
2316 if (ret)
2317 goto err_unpin;
2318
2319 i915_gem_object_pin_fence(obj);
2320
2321 dev_priv->mm.interruptible = true;
2322 intel_runtime_pm_put(dev_priv);
2323 return 0;
2324
2325 err_unpin:
2326 i915_gem_object_unpin_from_display_plane(obj);
2327 err_interruptible:
2328 dev_priv->mm.interruptible = true;
2329 intel_runtime_pm_put(dev_priv);
2330 return ret;
2331 }
2332
2333 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2334 {
2335 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2336
2337 i915_gem_object_unpin_fence(obj);
2338 i915_gem_object_unpin_from_display_plane(obj);
2339 }
2340
2341 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2342 * is assumed to be a power-of-two. */
2343 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2344 unsigned int tiling_mode,
2345 unsigned int cpp,
2346 unsigned int pitch)
2347 {
2348 if (tiling_mode != I915_TILING_NONE) {
2349 unsigned int tile_rows, tiles;
2350
2351 tile_rows = *y / 8;
2352 *y %= 8;
2353
2354 tiles = *x / (512/cpp);
2355 *x %= 512/cpp;
2356
2357 return tile_rows * pitch * 8 + tiles * 4096;
2358 } else {
2359 unsigned int offset;
2360
2361 offset = *y * pitch + *x * cpp;
2362 *y = 0;
2363 *x = (offset & 4095) / cpp;
2364 return offset & -4096;
2365 }
2366 }
2367
2368 static int i9xx_format_to_fourcc(int format)
2369 {
2370 switch (format) {
2371 case DISPPLANE_8BPP:
2372 return DRM_FORMAT_C8;
2373 case DISPPLANE_BGRX555:
2374 return DRM_FORMAT_XRGB1555;
2375 case DISPPLANE_BGRX565:
2376 return DRM_FORMAT_RGB565;
2377 default:
2378 case DISPPLANE_BGRX888:
2379 return DRM_FORMAT_XRGB8888;
2380 case DISPPLANE_RGBX888:
2381 return DRM_FORMAT_XBGR8888;
2382 case DISPPLANE_BGRX101010:
2383 return DRM_FORMAT_XRGB2101010;
2384 case DISPPLANE_RGBX101010:
2385 return DRM_FORMAT_XBGR2101010;
2386 }
2387 }
2388
2389 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2390 {
2391 switch (format) {
2392 case PLANE_CTL_FORMAT_RGB_565:
2393 return DRM_FORMAT_RGB565;
2394 default:
2395 case PLANE_CTL_FORMAT_XRGB_8888:
2396 if (rgb_order) {
2397 if (alpha)
2398 return DRM_FORMAT_ABGR8888;
2399 else
2400 return DRM_FORMAT_XBGR8888;
2401 } else {
2402 if (alpha)
2403 return DRM_FORMAT_ARGB8888;
2404 else
2405 return DRM_FORMAT_XRGB8888;
2406 }
2407 case PLANE_CTL_FORMAT_XRGB_2101010:
2408 if (rgb_order)
2409 return DRM_FORMAT_XBGR2101010;
2410 else
2411 return DRM_FORMAT_XRGB2101010;
2412 }
2413 }
2414
2415 static bool
2416 intel_alloc_plane_obj(struct intel_crtc *crtc,
2417 struct intel_initial_plane_config *plane_config)
2418 {
2419 struct drm_device *dev = crtc->base.dev;
2420 struct drm_i915_gem_object *obj = NULL;
2421 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2422 struct drm_framebuffer *fb = &plane_config->fb->base;
2423 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2424 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2425 PAGE_SIZE);
2426
2427 size_aligned -= base_aligned;
2428
2429 if (plane_config->size == 0)
2430 return false;
2431
2432 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2433 base_aligned,
2434 base_aligned,
2435 size_aligned);
2436 if (!obj)
2437 return false;
2438
2439 obj->tiling_mode = plane_config->tiling;
2440 if (obj->tiling_mode == I915_TILING_X)
2441 obj->stride = fb->pitches[0];
2442
2443 mode_cmd.pixel_format = fb->pixel_format;
2444 mode_cmd.width = fb->width;
2445 mode_cmd.height = fb->height;
2446 mode_cmd.pitches[0] = fb->pitches[0];
2447 mode_cmd.modifier[0] = fb->modifier[0];
2448 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2449
2450 mutex_lock(&dev->struct_mutex);
2451
2452 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2453 &mode_cmd, obj)) {
2454 DRM_DEBUG_KMS("intel fb init failed\n");
2455 goto out_unref_obj;
2456 }
2457
2458 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2459 mutex_unlock(&dev->struct_mutex);
2460
2461 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2462 return true;
2463
2464 out_unref_obj:
2465 drm_gem_object_unreference(&obj->base);
2466 mutex_unlock(&dev->struct_mutex);
2467 return false;
2468 }
2469
2470 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2471 static void
2472 update_state_fb(struct drm_plane *plane)
2473 {
2474 if (plane->fb == plane->state->fb)
2475 return;
2476
2477 if (plane->state->fb)
2478 drm_framebuffer_unreference(plane->state->fb);
2479 plane->state->fb = plane->fb;
2480 if (plane->state->fb)
2481 drm_framebuffer_reference(plane->state->fb);
2482 }
2483
2484 static void
2485 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2486 struct intel_initial_plane_config *plane_config)
2487 {
2488 struct drm_device *dev = intel_crtc->base.dev;
2489 struct drm_i915_private *dev_priv = dev->dev_private;
2490 struct drm_crtc *c;
2491 struct intel_crtc *i;
2492 struct drm_i915_gem_object *obj;
2493
2494 if (!plane_config->fb)
2495 return;
2496
2497 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2498 struct drm_plane *primary = intel_crtc->base.primary;
2499
2500 primary->fb = &plane_config->fb->base;
2501 primary->state->crtc = &intel_crtc->base;
2502 update_state_fb(primary);
2503
2504 return;
2505 }
2506
2507 kfree(plane_config->fb);
2508
2509 /*
2510 * Failed to alloc the obj, check to see if we should share
2511 * an fb with another CRTC instead
2512 */
2513 for_each_crtc(dev, c) {
2514 i = to_intel_crtc(c);
2515
2516 if (c == &intel_crtc->base)
2517 continue;
2518
2519 if (!i->active)
2520 continue;
2521
2522 obj = intel_fb_obj(c->primary->fb);
2523 if (obj == NULL)
2524 continue;
2525
2526 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2527 struct drm_plane *primary = intel_crtc->base.primary;
2528
2529 if (obj->tiling_mode != I915_TILING_NONE)
2530 dev_priv->preserve_bios_swizzle = true;
2531
2532 drm_framebuffer_reference(c->primary->fb);
2533 primary->fb = c->primary->fb;
2534 primary->state->crtc = &intel_crtc->base;
2535 update_state_fb(intel_crtc->base.primary);
2536 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2537 break;
2538 }
2539 }
2540
2541 }
2542
2543 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2544 struct drm_framebuffer *fb,
2545 int x, int y)
2546 {
2547 struct drm_device *dev = crtc->dev;
2548 struct drm_i915_private *dev_priv = dev->dev_private;
2549 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2550 struct drm_i915_gem_object *obj;
2551 int plane = intel_crtc->plane;
2552 unsigned long linear_offset;
2553 u32 dspcntr;
2554 u32 reg = DSPCNTR(plane);
2555 int pixel_size;
2556
2557 if (!intel_crtc->primary_enabled) {
2558 I915_WRITE(reg, 0);
2559 if (INTEL_INFO(dev)->gen >= 4)
2560 I915_WRITE(DSPSURF(plane), 0);
2561 else
2562 I915_WRITE(DSPADDR(plane), 0);
2563 POSTING_READ(reg);
2564 return;
2565 }
2566
2567 obj = intel_fb_obj(fb);
2568 if (WARN_ON(obj == NULL))
2569 return;
2570
2571 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2572
2573 dspcntr = DISPPLANE_GAMMA_ENABLE;
2574
2575 dspcntr |= DISPLAY_PLANE_ENABLE;
2576
2577 if (INTEL_INFO(dev)->gen < 4) {
2578 if (intel_crtc->pipe == PIPE_B)
2579 dspcntr |= DISPPLANE_SEL_PIPE_B;
2580
2581 /* pipesrc and dspsize control the size that is scaled from,
2582 * which should always be the user's requested size.
2583 */
2584 I915_WRITE(DSPSIZE(plane),
2585 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2586 (intel_crtc->config->pipe_src_w - 1));
2587 I915_WRITE(DSPPOS(plane), 0);
2588 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2589 I915_WRITE(PRIMSIZE(plane),
2590 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2591 (intel_crtc->config->pipe_src_w - 1));
2592 I915_WRITE(PRIMPOS(plane), 0);
2593 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2594 }
2595
2596 switch (fb->pixel_format) {
2597 case DRM_FORMAT_C8:
2598 dspcntr |= DISPPLANE_8BPP;
2599 break;
2600 case DRM_FORMAT_XRGB1555:
2601 case DRM_FORMAT_ARGB1555:
2602 dspcntr |= DISPPLANE_BGRX555;
2603 break;
2604 case DRM_FORMAT_RGB565:
2605 dspcntr |= DISPPLANE_BGRX565;
2606 break;
2607 case DRM_FORMAT_XRGB8888:
2608 case DRM_FORMAT_ARGB8888:
2609 dspcntr |= DISPPLANE_BGRX888;
2610 break;
2611 case DRM_FORMAT_XBGR8888:
2612 case DRM_FORMAT_ABGR8888:
2613 dspcntr |= DISPPLANE_RGBX888;
2614 break;
2615 case DRM_FORMAT_XRGB2101010:
2616 case DRM_FORMAT_ARGB2101010:
2617 dspcntr |= DISPPLANE_BGRX101010;
2618 break;
2619 case DRM_FORMAT_XBGR2101010:
2620 case DRM_FORMAT_ABGR2101010:
2621 dspcntr |= DISPPLANE_RGBX101010;
2622 break;
2623 default:
2624 BUG();
2625 }
2626
2627 if (INTEL_INFO(dev)->gen >= 4 &&
2628 obj->tiling_mode != I915_TILING_NONE)
2629 dspcntr |= DISPPLANE_TILED;
2630
2631 if (IS_G4X(dev))
2632 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2633
2634 linear_offset = y * fb->pitches[0] + x * pixel_size;
2635
2636 if (INTEL_INFO(dev)->gen >= 4) {
2637 intel_crtc->dspaddr_offset =
2638 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2639 pixel_size,
2640 fb->pitches[0]);
2641 linear_offset -= intel_crtc->dspaddr_offset;
2642 } else {
2643 intel_crtc->dspaddr_offset = linear_offset;
2644 }
2645
2646 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2647 dspcntr |= DISPPLANE_ROTATE_180;
2648
2649 x += (intel_crtc->config->pipe_src_w - 1);
2650 y += (intel_crtc->config->pipe_src_h - 1);
2651
2652 /* Finding the last pixel of the last line of the display
2653 data and adding to linear_offset*/
2654 linear_offset +=
2655 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2656 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2657 }
2658
2659 I915_WRITE(reg, dspcntr);
2660
2661 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2662 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2663 fb->pitches[0]);
2664 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2665 if (INTEL_INFO(dev)->gen >= 4) {
2666 I915_WRITE(DSPSURF(plane),
2667 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2668 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2669 I915_WRITE(DSPLINOFF(plane), linear_offset);
2670 } else
2671 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2672 POSTING_READ(reg);
2673 }
2674
2675 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2676 struct drm_framebuffer *fb,
2677 int x, int y)
2678 {
2679 struct drm_device *dev = crtc->dev;
2680 struct drm_i915_private *dev_priv = dev->dev_private;
2681 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2682 struct drm_i915_gem_object *obj;
2683 int plane = intel_crtc->plane;
2684 unsigned long linear_offset;
2685 u32 dspcntr;
2686 u32 reg = DSPCNTR(plane);
2687 int pixel_size;
2688
2689 if (!intel_crtc->primary_enabled) {
2690 I915_WRITE(reg, 0);
2691 I915_WRITE(DSPSURF(plane), 0);
2692 POSTING_READ(reg);
2693 return;
2694 }
2695
2696 obj = intel_fb_obj(fb);
2697 if (WARN_ON(obj == NULL))
2698 return;
2699
2700 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2701
2702 dspcntr = DISPPLANE_GAMMA_ENABLE;
2703
2704 dspcntr |= DISPLAY_PLANE_ENABLE;
2705
2706 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2707 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2708
2709 switch (fb->pixel_format) {
2710 case DRM_FORMAT_C8:
2711 dspcntr |= DISPPLANE_8BPP;
2712 break;
2713 case DRM_FORMAT_RGB565:
2714 dspcntr |= DISPPLANE_BGRX565;
2715 break;
2716 case DRM_FORMAT_XRGB8888:
2717 case DRM_FORMAT_ARGB8888:
2718 dspcntr |= DISPPLANE_BGRX888;
2719 break;
2720 case DRM_FORMAT_XBGR8888:
2721 case DRM_FORMAT_ABGR8888:
2722 dspcntr |= DISPPLANE_RGBX888;
2723 break;
2724 case DRM_FORMAT_XRGB2101010:
2725 case DRM_FORMAT_ARGB2101010:
2726 dspcntr |= DISPPLANE_BGRX101010;
2727 break;
2728 case DRM_FORMAT_XBGR2101010:
2729 case DRM_FORMAT_ABGR2101010:
2730 dspcntr |= DISPPLANE_RGBX101010;
2731 break;
2732 default:
2733 BUG();
2734 }
2735
2736 if (obj->tiling_mode != I915_TILING_NONE)
2737 dspcntr |= DISPPLANE_TILED;
2738
2739 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2740 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2741
2742 linear_offset = y * fb->pitches[0] + x * pixel_size;
2743 intel_crtc->dspaddr_offset =
2744 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2745 pixel_size,
2746 fb->pitches[0]);
2747 linear_offset -= intel_crtc->dspaddr_offset;
2748 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2749 dspcntr |= DISPPLANE_ROTATE_180;
2750
2751 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2760 }
2761 }
2762
2763 I915_WRITE(reg, dspcntr);
2764
2765 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2766 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2767 fb->pitches[0]);
2768 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2769 I915_WRITE(DSPSURF(plane),
2770 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2771 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2772 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2773 } else {
2774 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2775 I915_WRITE(DSPLINOFF(plane), linear_offset);
2776 }
2777 POSTING_READ(reg);
2778 }
2779
2780 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2781 uint32_t pixel_format)
2782 {
2783 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2784
2785 /*
2786 * The stride is either expressed as a multiple of 64 bytes
2787 * chunks for linear buffers or in number of tiles for tiled
2788 * buffers.
2789 */
2790 switch (fb_modifier) {
2791 case DRM_FORMAT_MOD_NONE:
2792 return 64;
2793 case I915_FORMAT_MOD_X_TILED:
2794 if (INTEL_INFO(dev)->gen == 2)
2795 return 128;
2796 return 512;
2797 case I915_FORMAT_MOD_Y_TILED:
2798 /* No need to check for old gens and Y tiling since this is
2799 * about the display engine and those will be blocked before
2800 * we get here.
2801 */
2802 return 128;
2803 case I915_FORMAT_MOD_Yf_TILED:
2804 if (bits_per_pixel == 8)
2805 return 64;
2806 else
2807 return 128;
2808 default:
2809 MISSING_CASE(fb_modifier);
2810 return 64;
2811 }
2812 }
2813
2814 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2815 struct drm_framebuffer *fb,
2816 int x, int y)
2817 {
2818 struct drm_device *dev = crtc->dev;
2819 struct drm_i915_private *dev_priv = dev->dev_private;
2820 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2821 struct drm_i915_gem_object *obj;
2822 int pipe = intel_crtc->pipe;
2823 u32 plane_ctl, stride_div;
2824
2825 if (!intel_crtc->primary_enabled) {
2826 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2827 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2828 POSTING_READ(PLANE_CTL(pipe, 0));
2829 return;
2830 }
2831
2832 plane_ctl = PLANE_CTL_ENABLE |
2833 PLANE_CTL_PIPE_GAMMA_ENABLE |
2834 PLANE_CTL_PIPE_CSC_ENABLE;
2835
2836 switch (fb->pixel_format) {
2837 case DRM_FORMAT_RGB565:
2838 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2839 break;
2840 case DRM_FORMAT_XRGB8888:
2841 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2842 break;
2843 case DRM_FORMAT_ARGB8888:
2844 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2845 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2846 break;
2847 case DRM_FORMAT_XBGR8888:
2848 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2849 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2850 break;
2851 case DRM_FORMAT_ABGR8888:
2852 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2853 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2854 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2855 break;
2856 case DRM_FORMAT_XRGB2101010:
2857 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2858 break;
2859 case DRM_FORMAT_XBGR2101010:
2860 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2861 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2862 break;
2863 default:
2864 BUG();
2865 }
2866
2867 switch (fb->modifier[0]) {
2868 case DRM_FORMAT_MOD_NONE:
2869 break;
2870 case I915_FORMAT_MOD_X_TILED:
2871 plane_ctl |= PLANE_CTL_TILED_X;
2872 break;
2873 case I915_FORMAT_MOD_Y_TILED:
2874 plane_ctl |= PLANE_CTL_TILED_Y;
2875 break;
2876 case I915_FORMAT_MOD_Yf_TILED:
2877 plane_ctl |= PLANE_CTL_TILED_YF;
2878 break;
2879 default:
2880 MISSING_CASE(fb->modifier[0]);
2881 }
2882
2883 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2884 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2885 plane_ctl |= PLANE_CTL_ROTATE_180;
2886
2887 obj = intel_fb_obj(fb);
2888 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2889 fb->pixel_format);
2890
2891 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2892
2893 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2894 i915_gem_obj_ggtt_offset(obj),
2895 x, y, fb->width, fb->height,
2896 fb->pitches[0]);
2897
2898 I915_WRITE(PLANE_POS(pipe, 0), 0);
2899 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2900 I915_WRITE(PLANE_SIZE(pipe, 0),
2901 (intel_crtc->config->pipe_src_h - 1) << 16 |
2902 (intel_crtc->config->pipe_src_w - 1));
2903 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2904 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2905
2906 POSTING_READ(PLANE_SURF(pipe, 0));
2907 }
2908
2909 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2910 static int
2911 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2912 int x, int y, enum mode_set_atomic state)
2913 {
2914 struct drm_device *dev = crtc->dev;
2915 struct drm_i915_private *dev_priv = dev->dev_private;
2916
2917 if (dev_priv->display.disable_fbc)
2918 dev_priv->display.disable_fbc(dev);
2919
2920 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2921
2922 return 0;
2923 }
2924
2925 static void intel_complete_page_flips(struct drm_device *dev)
2926 {
2927 struct drm_crtc *crtc;
2928
2929 for_each_crtc(dev, crtc) {
2930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2931 enum plane plane = intel_crtc->plane;
2932
2933 intel_prepare_page_flip(dev, plane);
2934 intel_finish_page_flip_plane(dev, plane);
2935 }
2936 }
2937
2938 static void intel_update_primary_planes(struct drm_device *dev)
2939 {
2940 struct drm_i915_private *dev_priv = dev->dev_private;
2941 struct drm_crtc *crtc;
2942
2943 for_each_crtc(dev, crtc) {
2944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2945
2946 drm_modeset_lock(&crtc->mutex, NULL);
2947 /*
2948 * FIXME: Once we have proper support for primary planes (and
2949 * disabling them without disabling the entire crtc) allow again
2950 * a NULL crtc->primary->fb.
2951 */
2952 if (intel_crtc->active && crtc->primary->fb)
2953 dev_priv->display.update_primary_plane(crtc,
2954 crtc->primary->fb,
2955 crtc->x,
2956 crtc->y);
2957 drm_modeset_unlock(&crtc->mutex);
2958 }
2959 }
2960
2961 void intel_prepare_reset(struct drm_device *dev)
2962 {
2963 struct drm_i915_private *dev_priv = to_i915(dev);
2964 struct intel_crtc *crtc;
2965
2966 /* no reset support for gen2 */
2967 if (IS_GEN2(dev))
2968 return;
2969
2970 /* reset doesn't touch the display */
2971 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2972 return;
2973
2974 drm_modeset_lock_all(dev);
2975
2976 /*
2977 * Disabling the crtcs gracefully seems nicer. Also the
2978 * g33 docs say we should at least disable all the planes.
2979 */
2980 for_each_intel_crtc(dev, crtc) {
2981 if (crtc->active)
2982 dev_priv->display.crtc_disable(&crtc->base);
2983 }
2984 }
2985
2986 void intel_finish_reset(struct drm_device *dev)
2987 {
2988 struct drm_i915_private *dev_priv = to_i915(dev);
2989
2990 /*
2991 * Flips in the rings will be nuked by the reset,
2992 * so complete all pending flips so that user space
2993 * will get its events and not get stuck.
2994 */
2995 intel_complete_page_flips(dev);
2996
2997 /* no reset support for gen2 */
2998 if (IS_GEN2(dev))
2999 return;
3000
3001 /* reset doesn't touch the display */
3002 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3003 /*
3004 * Flips in the rings have been nuked by the reset,
3005 * so update the base address of all primary
3006 * planes to the the last fb to make sure we're
3007 * showing the correct fb after a reset.
3008 */
3009 intel_update_primary_planes(dev);
3010 return;
3011 }
3012
3013 /*
3014 * The display has been reset as well,
3015 * so need a full re-initialization.
3016 */
3017 intel_runtime_pm_disable_interrupts(dev_priv);
3018 intel_runtime_pm_enable_interrupts(dev_priv);
3019
3020 intel_modeset_init_hw(dev);
3021
3022 spin_lock_irq(&dev_priv->irq_lock);
3023 if (dev_priv->display.hpd_irq_setup)
3024 dev_priv->display.hpd_irq_setup(dev);
3025 spin_unlock_irq(&dev_priv->irq_lock);
3026
3027 intel_modeset_setup_hw_state(dev, true);
3028
3029 intel_hpd_init(dev_priv);
3030
3031 drm_modeset_unlock_all(dev);
3032 }
3033
3034 static int
3035 intel_finish_fb(struct drm_framebuffer *old_fb)
3036 {
3037 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3038 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3039 bool was_interruptible = dev_priv->mm.interruptible;
3040 int ret;
3041
3042 /* Big Hammer, we also need to ensure that any pending
3043 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3044 * current scanout is retired before unpinning the old
3045 * framebuffer.
3046 *
3047 * This should only fail upon a hung GPU, in which case we
3048 * can safely continue.
3049 */
3050 dev_priv->mm.interruptible = false;
3051 ret = i915_gem_object_finish_gpu(obj);
3052 dev_priv->mm.interruptible = was_interruptible;
3053
3054 return ret;
3055 }
3056
3057 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3058 {
3059 struct drm_device *dev = crtc->dev;
3060 struct drm_i915_private *dev_priv = dev->dev_private;
3061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3062 bool pending;
3063
3064 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3065 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3066 return false;
3067
3068 spin_lock_irq(&dev->event_lock);
3069 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3070 spin_unlock_irq(&dev->event_lock);
3071
3072 return pending;
3073 }
3074
3075 static void intel_update_pipe_size(struct intel_crtc *crtc)
3076 {
3077 struct drm_device *dev = crtc->base.dev;
3078 struct drm_i915_private *dev_priv = dev->dev_private;
3079 const struct drm_display_mode *adjusted_mode;
3080
3081 if (!i915.fastboot)
3082 return;
3083
3084 /*
3085 * Update pipe size and adjust fitter if needed: the reason for this is
3086 * that in compute_mode_changes we check the native mode (not the pfit
3087 * mode) to see if we can flip rather than do a full mode set. In the
3088 * fastboot case, we'll flip, but if we don't update the pipesrc and
3089 * pfit state, we'll end up with a big fb scanned out into the wrong
3090 * sized surface.
3091 *
3092 * To fix this properly, we need to hoist the checks up into
3093 * compute_mode_changes (or above), check the actual pfit state and
3094 * whether the platform allows pfit disable with pipe active, and only
3095 * then update the pipesrc and pfit state, even on the flip path.
3096 */
3097
3098 adjusted_mode = &crtc->config->base.adjusted_mode;
3099
3100 I915_WRITE(PIPESRC(crtc->pipe),
3101 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3102 (adjusted_mode->crtc_vdisplay - 1));
3103 if (!crtc->config->pch_pfit.enabled &&
3104 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3105 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3106 I915_WRITE(PF_CTL(crtc->pipe), 0);
3107 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3108 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3109 }
3110 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3111 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3112 }
3113
3114 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3115 {
3116 struct drm_device *dev = crtc->dev;
3117 struct drm_i915_private *dev_priv = dev->dev_private;
3118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3119 int pipe = intel_crtc->pipe;
3120 u32 reg, temp;
3121
3122 /* enable normal train */
3123 reg = FDI_TX_CTL(pipe);
3124 temp = I915_READ(reg);
3125 if (IS_IVYBRIDGE(dev)) {
3126 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3127 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3128 } else {
3129 temp &= ~FDI_LINK_TRAIN_NONE;
3130 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3131 }
3132 I915_WRITE(reg, temp);
3133
3134 reg = FDI_RX_CTL(pipe);
3135 temp = I915_READ(reg);
3136 if (HAS_PCH_CPT(dev)) {
3137 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3138 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3139 } else {
3140 temp &= ~FDI_LINK_TRAIN_NONE;
3141 temp |= FDI_LINK_TRAIN_NONE;
3142 }
3143 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3144
3145 /* wait one idle pattern time */
3146 POSTING_READ(reg);
3147 udelay(1000);
3148
3149 /* IVB wants error correction enabled */
3150 if (IS_IVYBRIDGE(dev))
3151 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3152 FDI_FE_ERRC_ENABLE);
3153 }
3154
3155 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3156 {
3157 return crtc->base.state->enable && crtc->active &&
3158 crtc->config->has_pch_encoder;
3159 }
3160
3161 static void ivb_modeset_global_resources(struct drm_device *dev)
3162 {
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164 struct intel_crtc *pipe_B_crtc =
3165 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3166 struct intel_crtc *pipe_C_crtc =
3167 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3168 uint32_t temp;
3169
3170 /*
3171 * When everything is off disable fdi C so that we could enable fdi B
3172 * with all lanes. Note that we don't care about enabled pipes without
3173 * an enabled pch encoder.
3174 */
3175 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3176 !pipe_has_enabled_pch(pipe_C_crtc)) {
3177 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3178 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3179
3180 temp = I915_READ(SOUTH_CHICKEN1);
3181 temp &= ~FDI_BC_BIFURCATION_SELECT;
3182 DRM_DEBUG_KMS("disabling fdi C rx\n");
3183 I915_WRITE(SOUTH_CHICKEN1, temp);
3184 }
3185 }
3186
3187 /* The FDI link training functions for ILK/Ibexpeak. */
3188 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3189 {
3190 struct drm_device *dev = crtc->dev;
3191 struct drm_i915_private *dev_priv = dev->dev_private;
3192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193 int pipe = intel_crtc->pipe;
3194 u32 reg, temp, tries;
3195
3196 /* FDI needs bits from pipe first */
3197 assert_pipe_enabled(dev_priv, pipe);
3198
3199 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3200 for train result */
3201 reg = FDI_RX_IMR(pipe);
3202 temp = I915_READ(reg);
3203 temp &= ~FDI_RX_SYMBOL_LOCK;
3204 temp &= ~FDI_RX_BIT_LOCK;
3205 I915_WRITE(reg, temp);
3206 I915_READ(reg);
3207 udelay(150);
3208
3209 /* enable CPU FDI TX and PCH FDI RX */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3213 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3214 temp &= ~FDI_LINK_TRAIN_NONE;
3215 temp |= FDI_LINK_TRAIN_PATTERN_1;
3216 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3217
3218 reg = FDI_RX_CTL(pipe);
3219 temp = I915_READ(reg);
3220 temp &= ~FDI_LINK_TRAIN_NONE;
3221 temp |= FDI_LINK_TRAIN_PATTERN_1;
3222 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3223
3224 POSTING_READ(reg);
3225 udelay(150);
3226
3227 /* Ironlake workaround, enable clock pointer after FDI enable*/
3228 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3229 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3230 FDI_RX_PHASE_SYNC_POINTER_EN);
3231
3232 reg = FDI_RX_IIR(pipe);
3233 for (tries = 0; tries < 5; tries++) {
3234 temp = I915_READ(reg);
3235 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3236
3237 if ((temp & FDI_RX_BIT_LOCK)) {
3238 DRM_DEBUG_KMS("FDI train 1 done.\n");
3239 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3240 break;
3241 }
3242 }
3243 if (tries == 5)
3244 DRM_ERROR("FDI train 1 fail!\n");
3245
3246 /* Train 2 */
3247 reg = FDI_TX_CTL(pipe);
3248 temp = I915_READ(reg);
3249 temp &= ~FDI_LINK_TRAIN_NONE;
3250 temp |= FDI_LINK_TRAIN_PATTERN_2;
3251 I915_WRITE(reg, temp);
3252
3253 reg = FDI_RX_CTL(pipe);
3254 temp = I915_READ(reg);
3255 temp &= ~FDI_LINK_TRAIN_NONE;
3256 temp |= FDI_LINK_TRAIN_PATTERN_2;
3257 I915_WRITE(reg, temp);
3258
3259 POSTING_READ(reg);
3260 udelay(150);
3261
3262 reg = FDI_RX_IIR(pipe);
3263 for (tries = 0; tries < 5; tries++) {
3264 temp = I915_READ(reg);
3265 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3266
3267 if (temp & FDI_RX_SYMBOL_LOCK) {
3268 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3269 DRM_DEBUG_KMS("FDI train 2 done.\n");
3270 break;
3271 }
3272 }
3273 if (tries == 5)
3274 DRM_ERROR("FDI train 2 fail!\n");
3275
3276 DRM_DEBUG_KMS("FDI train done\n");
3277
3278 }
3279
3280 static const int snb_b_fdi_train_param[] = {
3281 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3282 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3283 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3284 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3285 };
3286
3287 /* The FDI link training functions for SNB/Cougarpoint. */
3288 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3289 {
3290 struct drm_device *dev = crtc->dev;
3291 struct drm_i915_private *dev_priv = dev->dev_private;
3292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293 int pipe = intel_crtc->pipe;
3294 u32 reg, temp, i, retry;
3295
3296 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3297 for train result */
3298 reg = FDI_RX_IMR(pipe);
3299 temp = I915_READ(reg);
3300 temp &= ~FDI_RX_SYMBOL_LOCK;
3301 temp &= ~FDI_RX_BIT_LOCK;
3302 I915_WRITE(reg, temp);
3303
3304 POSTING_READ(reg);
3305 udelay(150);
3306
3307 /* enable CPU FDI TX and PCH FDI RX */
3308 reg = FDI_TX_CTL(pipe);
3309 temp = I915_READ(reg);
3310 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3311 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3312 temp &= ~FDI_LINK_TRAIN_NONE;
3313 temp |= FDI_LINK_TRAIN_PATTERN_1;
3314 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3315 /* SNB-B */
3316 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3317 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3318
3319 I915_WRITE(FDI_RX_MISC(pipe),
3320 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3321
3322 reg = FDI_RX_CTL(pipe);
3323 temp = I915_READ(reg);
3324 if (HAS_PCH_CPT(dev)) {
3325 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3326 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3327 } else {
3328 temp &= ~FDI_LINK_TRAIN_NONE;
3329 temp |= FDI_LINK_TRAIN_PATTERN_1;
3330 }
3331 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3332
3333 POSTING_READ(reg);
3334 udelay(150);
3335
3336 for (i = 0; i < 4; i++) {
3337 reg = FDI_TX_CTL(pipe);
3338 temp = I915_READ(reg);
3339 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3340 temp |= snb_b_fdi_train_param[i];
3341 I915_WRITE(reg, temp);
3342
3343 POSTING_READ(reg);
3344 udelay(500);
3345
3346 for (retry = 0; retry < 5; retry++) {
3347 reg = FDI_RX_IIR(pipe);
3348 temp = I915_READ(reg);
3349 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3350 if (temp & FDI_RX_BIT_LOCK) {
3351 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3352 DRM_DEBUG_KMS("FDI train 1 done.\n");
3353 break;
3354 }
3355 udelay(50);
3356 }
3357 if (retry < 5)
3358 break;
3359 }
3360 if (i == 4)
3361 DRM_ERROR("FDI train 1 fail!\n");
3362
3363 /* Train 2 */
3364 reg = FDI_TX_CTL(pipe);
3365 temp = I915_READ(reg);
3366 temp &= ~FDI_LINK_TRAIN_NONE;
3367 temp |= FDI_LINK_TRAIN_PATTERN_2;
3368 if (IS_GEN6(dev)) {
3369 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3370 /* SNB-B */
3371 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3372 }
3373 I915_WRITE(reg, temp);
3374
3375 reg = FDI_RX_CTL(pipe);
3376 temp = I915_READ(reg);
3377 if (HAS_PCH_CPT(dev)) {
3378 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3379 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3380 } else {
3381 temp &= ~FDI_LINK_TRAIN_NONE;
3382 temp |= FDI_LINK_TRAIN_PATTERN_2;
3383 }
3384 I915_WRITE(reg, temp);
3385
3386 POSTING_READ(reg);
3387 udelay(150);
3388
3389 for (i = 0; i < 4; i++) {
3390 reg = FDI_TX_CTL(pipe);
3391 temp = I915_READ(reg);
3392 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3393 temp |= snb_b_fdi_train_param[i];
3394 I915_WRITE(reg, temp);
3395
3396 POSTING_READ(reg);
3397 udelay(500);
3398
3399 for (retry = 0; retry < 5; retry++) {
3400 reg = FDI_RX_IIR(pipe);
3401 temp = I915_READ(reg);
3402 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3403 if (temp & FDI_RX_SYMBOL_LOCK) {
3404 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3405 DRM_DEBUG_KMS("FDI train 2 done.\n");
3406 break;
3407 }
3408 udelay(50);
3409 }
3410 if (retry < 5)
3411 break;
3412 }
3413 if (i == 4)
3414 DRM_ERROR("FDI train 2 fail!\n");
3415
3416 DRM_DEBUG_KMS("FDI train done.\n");
3417 }
3418
3419 /* Manual link training for Ivy Bridge A0 parts */
3420 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3421 {
3422 struct drm_device *dev = crtc->dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3425 int pipe = intel_crtc->pipe;
3426 u32 reg, temp, i, j;
3427
3428 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3429 for train result */
3430 reg = FDI_RX_IMR(pipe);
3431 temp = I915_READ(reg);
3432 temp &= ~FDI_RX_SYMBOL_LOCK;
3433 temp &= ~FDI_RX_BIT_LOCK;
3434 I915_WRITE(reg, temp);
3435
3436 POSTING_READ(reg);
3437 udelay(150);
3438
3439 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3440 I915_READ(FDI_RX_IIR(pipe)));
3441
3442 /* Try each vswing and preemphasis setting twice before moving on */
3443 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3444 /* disable first in case we need to retry */
3445 reg = FDI_TX_CTL(pipe);
3446 temp = I915_READ(reg);
3447 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3448 temp &= ~FDI_TX_ENABLE;
3449 I915_WRITE(reg, temp);
3450
3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~FDI_LINK_TRAIN_AUTO;
3454 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3455 temp &= ~FDI_RX_ENABLE;
3456 I915_WRITE(reg, temp);
3457
3458 /* enable CPU FDI TX and PCH FDI RX */
3459 reg = FDI_TX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3462 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3463 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3464 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3465 temp |= snb_b_fdi_train_param[j/2];
3466 temp |= FDI_COMPOSITE_SYNC;
3467 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3468
3469 I915_WRITE(FDI_RX_MISC(pipe),
3470 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3471
3472 reg = FDI_RX_CTL(pipe);
3473 temp = I915_READ(reg);
3474 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3475 temp |= FDI_COMPOSITE_SYNC;
3476 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3477
3478 POSTING_READ(reg);
3479 udelay(1); /* should be 0.5us */
3480
3481 for (i = 0; i < 4; i++) {
3482 reg = FDI_RX_IIR(pipe);
3483 temp = I915_READ(reg);
3484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485
3486 if (temp & FDI_RX_BIT_LOCK ||
3487 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3488 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3489 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3490 i);
3491 break;
3492 }
3493 udelay(1); /* should be 0.5us */
3494 }
3495 if (i == 4) {
3496 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3497 continue;
3498 }
3499
3500 /* Train 2 */
3501 reg = FDI_TX_CTL(pipe);
3502 temp = I915_READ(reg);
3503 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3504 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3505 I915_WRITE(reg, temp);
3506
3507 reg = FDI_RX_CTL(pipe);
3508 temp = I915_READ(reg);
3509 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3510 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3511 I915_WRITE(reg, temp);
3512
3513 POSTING_READ(reg);
3514 udelay(2); /* should be 1.5us */
3515
3516 for (i = 0; i < 4; i++) {
3517 reg = FDI_RX_IIR(pipe);
3518 temp = I915_READ(reg);
3519 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3520
3521 if (temp & FDI_RX_SYMBOL_LOCK ||
3522 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3523 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3524 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3525 i);
3526 goto train_done;
3527 }
3528 udelay(2); /* should be 1.5us */
3529 }
3530 if (i == 4)
3531 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3532 }
3533
3534 train_done:
3535 DRM_DEBUG_KMS("FDI train done.\n");
3536 }
3537
3538 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3539 {
3540 struct drm_device *dev = intel_crtc->base.dev;
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542 int pipe = intel_crtc->pipe;
3543 u32 reg, temp;
3544
3545
3546 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3547 reg = FDI_RX_CTL(pipe);
3548 temp = I915_READ(reg);
3549 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3550 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3551 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3552 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3553
3554 POSTING_READ(reg);
3555 udelay(200);
3556
3557 /* Switch from Rawclk to PCDclk */
3558 temp = I915_READ(reg);
3559 I915_WRITE(reg, temp | FDI_PCDCLK);
3560
3561 POSTING_READ(reg);
3562 udelay(200);
3563
3564 /* Enable CPU FDI TX PLL, always on for Ironlake */
3565 reg = FDI_TX_CTL(pipe);
3566 temp = I915_READ(reg);
3567 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3568 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3569
3570 POSTING_READ(reg);
3571 udelay(100);
3572 }
3573 }
3574
3575 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3576 {
3577 struct drm_device *dev = intel_crtc->base.dev;
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579 int pipe = intel_crtc->pipe;
3580 u32 reg, temp;
3581
3582 /* Switch from PCDclk to Rawclk */
3583 reg = FDI_RX_CTL(pipe);
3584 temp = I915_READ(reg);
3585 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3586
3587 /* Disable CPU FDI TX PLL */
3588 reg = FDI_TX_CTL(pipe);
3589 temp = I915_READ(reg);
3590 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3591
3592 POSTING_READ(reg);
3593 udelay(100);
3594
3595 reg = FDI_RX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3598
3599 /* Wait for the clocks to turn off. */
3600 POSTING_READ(reg);
3601 udelay(100);
3602 }
3603
3604 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3605 {
3606 struct drm_device *dev = crtc->dev;
3607 struct drm_i915_private *dev_priv = dev->dev_private;
3608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609 int pipe = intel_crtc->pipe;
3610 u32 reg, temp;
3611
3612 /* disable CPU FDI tx and PCH FDI rx */
3613 reg = FDI_TX_CTL(pipe);
3614 temp = I915_READ(reg);
3615 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3616 POSTING_READ(reg);
3617
3618 reg = FDI_RX_CTL(pipe);
3619 temp = I915_READ(reg);
3620 temp &= ~(0x7 << 16);
3621 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3622 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3623
3624 POSTING_READ(reg);
3625 udelay(100);
3626
3627 /* Ironlake workaround, disable clock pointer after downing FDI */
3628 if (HAS_PCH_IBX(dev))
3629 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3630
3631 /* still set train pattern 1 */
3632 reg = FDI_TX_CTL(pipe);
3633 temp = I915_READ(reg);
3634 temp &= ~FDI_LINK_TRAIN_NONE;
3635 temp |= FDI_LINK_TRAIN_PATTERN_1;
3636 I915_WRITE(reg, temp);
3637
3638 reg = FDI_RX_CTL(pipe);
3639 temp = I915_READ(reg);
3640 if (HAS_PCH_CPT(dev)) {
3641 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3642 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3643 } else {
3644 temp &= ~FDI_LINK_TRAIN_NONE;
3645 temp |= FDI_LINK_TRAIN_PATTERN_1;
3646 }
3647 /* BPC in FDI rx is consistent with that in PIPECONF */
3648 temp &= ~(0x07 << 16);
3649 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3650 I915_WRITE(reg, temp);
3651
3652 POSTING_READ(reg);
3653 udelay(100);
3654 }
3655
3656 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3657 {
3658 struct intel_crtc *crtc;
3659
3660 /* Note that we don't need to be called with mode_config.lock here
3661 * as our list of CRTC objects is static for the lifetime of the
3662 * device and so cannot disappear as we iterate. Similarly, we can
3663 * happily treat the predicates as racy, atomic checks as userspace
3664 * cannot claim and pin a new fb without at least acquring the
3665 * struct_mutex and so serialising with us.
3666 */
3667 for_each_intel_crtc(dev, crtc) {
3668 if (atomic_read(&crtc->unpin_work_count) == 0)
3669 continue;
3670
3671 if (crtc->unpin_work)
3672 intel_wait_for_vblank(dev, crtc->pipe);
3673
3674 return true;
3675 }
3676
3677 return false;
3678 }
3679
3680 static void page_flip_completed(struct intel_crtc *intel_crtc)
3681 {
3682 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3683 struct intel_unpin_work *work = intel_crtc->unpin_work;
3684
3685 /* ensure that the unpin work is consistent wrt ->pending. */
3686 smp_rmb();
3687 intel_crtc->unpin_work = NULL;
3688
3689 if (work->event)
3690 drm_send_vblank_event(intel_crtc->base.dev,
3691 intel_crtc->pipe,
3692 work->event);
3693
3694 drm_crtc_vblank_put(&intel_crtc->base);
3695
3696 wake_up_all(&dev_priv->pending_flip_queue);
3697 queue_work(dev_priv->wq, &work->work);
3698
3699 trace_i915_flip_complete(intel_crtc->plane,
3700 work->pending_flip_obj);
3701 }
3702
3703 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3704 {
3705 struct drm_device *dev = crtc->dev;
3706 struct drm_i915_private *dev_priv = dev->dev_private;
3707
3708 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3709 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3710 !intel_crtc_has_pending_flip(crtc),
3711 60*HZ) == 0)) {
3712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3713
3714 spin_lock_irq(&dev->event_lock);
3715 if (intel_crtc->unpin_work) {
3716 WARN_ONCE(1, "Removing stuck page flip\n");
3717 page_flip_completed(intel_crtc);
3718 }
3719 spin_unlock_irq(&dev->event_lock);
3720 }
3721
3722 if (crtc->primary->fb) {
3723 mutex_lock(&dev->struct_mutex);
3724 intel_finish_fb(crtc->primary->fb);
3725 mutex_unlock(&dev->struct_mutex);
3726 }
3727 }
3728
3729 /* Program iCLKIP clock to the desired frequency */
3730 static void lpt_program_iclkip(struct drm_crtc *crtc)
3731 {
3732 struct drm_device *dev = crtc->dev;
3733 struct drm_i915_private *dev_priv = dev->dev_private;
3734 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3735 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3736 u32 temp;
3737
3738 mutex_lock(&dev_priv->dpio_lock);
3739
3740 /* It is necessary to ungate the pixclk gate prior to programming
3741 * the divisors, and gate it back when it is done.
3742 */
3743 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3744
3745 /* Disable SSCCTL */
3746 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3747 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3748 SBI_SSCCTL_DISABLE,
3749 SBI_ICLK);
3750
3751 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3752 if (clock == 20000) {
3753 auxdiv = 1;
3754 divsel = 0x41;
3755 phaseinc = 0x20;
3756 } else {
3757 /* The iCLK virtual clock root frequency is in MHz,
3758 * but the adjusted_mode->crtc_clock in in KHz. To get the
3759 * divisors, it is necessary to divide one by another, so we
3760 * convert the virtual clock precision to KHz here for higher
3761 * precision.
3762 */
3763 u32 iclk_virtual_root_freq = 172800 * 1000;
3764 u32 iclk_pi_range = 64;
3765 u32 desired_divisor, msb_divisor_value, pi_value;
3766
3767 desired_divisor = (iclk_virtual_root_freq / clock);
3768 msb_divisor_value = desired_divisor / iclk_pi_range;
3769 pi_value = desired_divisor % iclk_pi_range;
3770
3771 auxdiv = 0;
3772 divsel = msb_divisor_value - 2;
3773 phaseinc = pi_value;
3774 }
3775
3776 /* This should not happen with any sane values */
3777 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3778 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3779 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3780 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3781
3782 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3783 clock,
3784 auxdiv,
3785 divsel,
3786 phasedir,
3787 phaseinc);
3788
3789 /* Program SSCDIVINTPHASE6 */
3790 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3791 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3792 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3793 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3794 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3795 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3796 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3797 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3798
3799 /* Program SSCAUXDIV */
3800 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3801 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3802 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3803 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3804
3805 /* Enable modulator and associated divider */
3806 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3807 temp &= ~SBI_SSCCTL_DISABLE;
3808 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3809
3810 /* Wait for initialization time */
3811 udelay(24);
3812
3813 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3814
3815 mutex_unlock(&dev_priv->dpio_lock);
3816 }
3817
3818 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3819 enum pipe pch_transcoder)
3820 {
3821 struct drm_device *dev = crtc->base.dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3824
3825 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3826 I915_READ(HTOTAL(cpu_transcoder)));
3827 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3828 I915_READ(HBLANK(cpu_transcoder)));
3829 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3830 I915_READ(HSYNC(cpu_transcoder)));
3831
3832 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3833 I915_READ(VTOTAL(cpu_transcoder)));
3834 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3835 I915_READ(VBLANK(cpu_transcoder)));
3836 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3837 I915_READ(VSYNC(cpu_transcoder)));
3838 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3839 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3840 }
3841
3842 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3843 {
3844 struct drm_i915_private *dev_priv = dev->dev_private;
3845 uint32_t temp;
3846
3847 temp = I915_READ(SOUTH_CHICKEN1);
3848 if (temp & FDI_BC_BIFURCATION_SELECT)
3849 return;
3850
3851 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3852 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3853
3854 temp |= FDI_BC_BIFURCATION_SELECT;
3855 DRM_DEBUG_KMS("enabling fdi C rx\n");
3856 I915_WRITE(SOUTH_CHICKEN1, temp);
3857 POSTING_READ(SOUTH_CHICKEN1);
3858 }
3859
3860 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3861 {
3862 struct drm_device *dev = intel_crtc->base.dev;
3863 struct drm_i915_private *dev_priv = dev->dev_private;
3864
3865 switch (intel_crtc->pipe) {
3866 case PIPE_A:
3867 break;
3868 case PIPE_B:
3869 if (intel_crtc->config->fdi_lanes > 2)
3870 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3871 else
3872 cpt_enable_fdi_bc_bifurcation(dev);
3873
3874 break;
3875 case PIPE_C:
3876 cpt_enable_fdi_bc_bifurcation(dev);
3877
3878 break;
3879 default:
3880 BUG();
3881 }
3882 }
3883
3884 /*
3885 * Enable PCH resources required for PCH ports:
3886 * - PCH PLLs
3887 * - FDI training & RX/TX
3888 * - update transcoder timings
3889 * - DP transcoding bits
3890 * - transcoder
3891 */
3892 static void ironlake_pch_enable(struct drm_crtc *crtc)
3893 {
3894 struct drm_device *dev = crtc->dev;
3895 struct drm_i915_private *dev_priv = dev->dev_private;
3896 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3897 int pipe = intel_crtc->pipe;
3898 u32 reg, temp;
3899
3900 assert_pch_transcoder_disabled(dev_priv, pipe);
3901
3902 if (IS_IVYBRIDGE(dev))
3903 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3904
3905 /* Write the TU size bits before fdi link training, so that error
3906 * detection works. */
3907 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3908 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3909
3910 /* For PCH output, training FDI link */
3911 dev_priv->display.fdi_link_train(crtc);
3912
3913 /* We need to program the right clock selection before writing the pixel
3914 * mutliplier into the DPLL. */
3915 if (HAS_PCH_CPT(dev)) {
3916 u32 sel;
3917
3918 temp = I915_READ(PCH_DPLL_SEL);
3919 temp |= TRANS_DPLL_ENABLE(pipe);
3920 sel = TRANS_DPLLB_SEL(pipe);
3921 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3922 temp |= sel;
3923 else
3924 temp &= ~sel;
3925 I915_WRITE(PCH_DPLL_SEL, temp);
3926 }
3927
3928 /* XXX: pch pll's can be enabled any time before we enable the PCH
3929 * transcoder, and we actually should do this to not upset any PCH
3930 * transcoder that already use the clock when we share it.
3931 *
3932 * Note that enable_shared_dpll tries to do the right thing, but
3933 * get_shared_dpll unconditionally resets the pll - we need that to have
3934 * the right LVDS enable sequence. */
3935 intel_enable_shared_dpll(intel_crtc);
3936
3937 /* set transcoder timing, panel must allow it */
3938 assert_panel_unlocked(dev_priv, pipe);
3939 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3940
3941 intel_fdi_normal_train(crtc);
3942
3943 /* For PCH DP, enable TRANS_DP_CTL */
3944 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3945 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3946 reg = TRANS_DP_CTL(pipe);
3947 temp = I915_READ(reg);
3948 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3949 TRANS_DP_SYNC_MASK |
3950 TRANS_DP_BPC_MASK);
3951 temp |= (TRANS_DP_OUTPUT_ENABLE |
3952 TRANS_DP_ENH_FRAMING);
3953 temp |= bpc << 9; /* same format but at 11:9 */
3954
3955 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3956 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3957 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3958 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3959
3960 switch (intel_trans_dp_port_sel(crtc)) {
3961 case PCH_DP_B:
3962 temp |= TRANS_DP_PORT_SEL_B;
3963 break;
3964 case PCH_DP_C:
3965 temp |= TRANS_DP_PORT_SEL_C;
3966 break;
3967 case PCH_DP_D:
3968 temp |= TRANS_DP_PORT_SEL_D;
3969 break;
3970 default:
3971 BUG();
3972 }
3973
3974 I915_WRITE(reg, temp);
3975 }
3976
3977 ironlake_enable_pch_transcoder(dev_priv, pipe);
3978 }
3979
3980 static void lpt_pch_enable(struct drm_crtc *crtc)
3981 {
3982 struct drm_device *dev = crtc->dev;
3983 struct drm_i915_private *dev_priv = dev->dev_private;
3984 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3985 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3986
3987 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3988
3989 lpt_program_iclkip(crtc);
3990
3991 /* Set transcoder timing. */
3992 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3993
3994 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3995 }
3996
3997 void intel_put_shared_dpll(struct intel_crtc *crtc)
3998 {
3999 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4000
4001 if (pll == NULL)
4002 return;
4003
4004 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4005 WARN(1, "bad %s crtc mask\n", pll->name);
4006 return;
4007 }
4008
4009 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4010 if (pll->config.crtc_mask == 0) {
4011 WARN_ON(pll->on);
4012 WARN_ON(pll->active);
4013 }
4014
4015 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4016 }
4017
4018 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4019 struct intel_crtc_state *crtc_state)
4020 {
4021 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4022 struct intel_shared_dpll *pll;
4023 enum intel_dpll_id i;
4024
4025 if (HAS_PCH_IBX(dev_priv->dev)) {
4026 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4027 i = (enum intel_dpll_id) crtc->pipe;
4028 pll = &dev_priv->shared_dplls[i];
4029
4030 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4031 crtc->base.base.id, pll->name);
4032
4033 WARN_ON(pll->new_config->crtc_mask);
4034
4035 goto found;
4036 }
4037
4038 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4039 pll = &dev_priv->shared_dplls[i];
4040
4041 /* Only want to check enabled timings first */
4042 if (pll->new_config->crtc_mask == 0)
4043 continue;
4044
4045 if (memcmp(&crtc_state->dpll_hw_state,
4046 &pll->new_config->hw_state,
4047 sizeof(pll->new_config->hw_state)) == 0) {
4048 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4049 crtc->base.base.id, pll->name,
4050 pll->new_config->crtc_mask,
4051 pll->active);
4052 goto found;
4053 }
4054 }
4055
4056 /* Ok no matching timings, maybe there's a free one? */
4057 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4058 pll = &dev_priv->shared_dplls[i];
4059 if (pll->new_config->crtc_mask == 0) {
4060 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4061 crtc->base.base.id, pll->name);
4062 goto found;
4063 }
4064 }
4065
4066 return NULL;
4067
4068 found:
4069 if (pll->new_config->crtc_mask == 0)
4070 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4071
4072 crtc_state->shared_dpll = i;
4073 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4074 pipe_name(crtc->pipe));
4075
4076 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4077
4078 return pll;
4079 }
4080
4081 /**
4082 * intel_shared_dpll_start_config - start a new PLL staged config
4083 * @dev_priv: DRM device
4084 * @clear_pipes: mask of pipes that will have their PLLs freed
4085 *
4086 * Starts a new PLL staged config, copying the current config but
4087 * releasing the references of pipes specified in clear_pipes.
4088 */
4089 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4090 unsigned clear_pipes)
4091 {
4092 struct intel_shared_dpll *pll;
4093 enum intel_dpll_id i;
4094
4095 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4096 pll = &dev_priv->shared_dplls[i];
4097
4098 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4099 GFP_KERNEL);
4100 if (!pll->new_config)
4101 goto cleanup;
4102
4103 pll->new_config->crtc_mask &= ~clear_pipes;
4104 }
4105
4106 return 0;
4107
4108 cleanup:
4109 while (--i >= 0) {
4110 pll = &dev_priv->shared_dplls[i];
4111 kfree(pll->new_config);
4112 pll->new_config = NULL;
4113 }
4114
4115 return -ENOMEM;
4116 }
4117
4118 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4119 {
4120 struct intel_shared_dpll *pll;
4121 enum intel_dpll_id i;
4122
4123 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4124 pll = &dev_priv->shared_dplls[i];
4125
4126 WARN_ON(pll->new_config == &pll->config);
4127
4128 pll->config = *pll->new_config;
4129 kfree(pll->new_config);
4130 pll->new_config = NULL;
4131 }
4132 }
4133
4134 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4135 {
4136 struct intel_shared_dpll *pll;
4137 enum intel_dpll_id i;
4138
4139 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4140 pll = &dev_priv->shared_dplls[i];
4141
4142 WARN_ON(pll->new_config == &pll->config);
4143
4144 kfree(pll->new_config);
4145 pll->new_config = NULL;
4146 }
4147 }
4148
4149 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4150 {
4151 struct drm_i915_private *dev_priv = dev->dev_private;
4152 int dslreg = PIPEDSL(pipe);
4153 u32 temp;
4154
4155 temp = I915_READ(dslreg);
4156 udelay(500);
4157 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4158 if (wait_for(I915_READ(dslreg) != temp, 5))
4159 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4160 }
4161 }
4162
4163 static void skylake_pfit_enable(struct intel_crtc *crtc)
4164 {
4165 struct drm_device *dev = crtc->base.dev;
4166 struct drm_i915_private *dev_priv = dev->dev_private;
4167 int pipe = crtc->pipe;
4168
4169 if (crtc->config->pch_pfit.enabled) {
4170 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4171 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4172 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4173 }
4174 }
4175
4176 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4177 {
4178 struct drm_device *dev = crtc->base.dev;
4179 struct drm_i915_private *dev_priv = dev->dev_private;
4180 int pipe = crtc->pipe;
4181
4182 if (crtc->config->pch_pfit.enabled) {
4183 /* Force use of hard-coded filter coefficients
4184 * as some pre-programmed values are broken,
4185 * e.g. x201.
4186 */
4187 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4188 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4189 PF_PIPE_SEL_IVB(pipe));
4190 else
4191 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4192 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4193 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4194 }
4195 }
4196
4197 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4198 {
4199 struct drm_device *dev = crtc->dev;
4200 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4201 struct drm_plane *plane;
4202 struct intel_plane *intel_plane;
4203
4204 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4205 intel_plane = to_intel_plane(plane);
4206 if (intel_plane->pipe == pipe)
4207 intel_plane_restore(&intel_plane->base);
4208 }
4209 }
4210
4211 /*
4212 * Disable a plane internally without actually modifying the plane's state.
4213 * This will allow us to easily restore the plane later by just reprogramming
4214 * its state.
4215 */
4216 static void disable_plane_internal(struct drm_plane *plane)
4217 {
4218 struct intel_plane *intel_plane = to_intel_plane(plane);
4219 struct drm_plane_state *state =
4220 plane->funcs->atomic_duplicate_state(plane);
4221 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4222
4223 intel_state->visible = false;
4224 intel_plane->commit_plane(plane, intel_state);
4225
4226 intel_plane_destroy_state(plane, state);
4227 }
4228
4229 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4230 {
4231 struct drm_device *dev = crtc->dev;
4232 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4233 struct drm_plane *plane;
4234 struct intel_plane *intel_plane;
4235
4236 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4237 intel_plane = to_intel_plane(plane);
4238 if (plane->fb && intel_plane->pipe == pipe)
4239 disable_plane_internal(plane);
4240 }
4241 }
4242
4243 void hsw_enable_ips(struct intel_crtc *crtc)
4244 {
4245 struct drm_device *dev = crtc->base.dev;
4246 struct drm_i915_private *dev_priv = dev->dev_private;
4247
4248 if (!crtc->config->ips_enabled)
4249 return;
4250
4251 /* We can only enable IPS after we enable a plane and wait for a vblank */
4252 intel_wait_for_vblank(dev, crtc->pipe);
4253
4254 assert_plane_enabled(dev_priv, crtc->plane);
4255 if (IS_BROADWELL(dev)) {
4256 mutex_lock(&dev_priv->rps.hw_lock);
4257 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4258 mutex_unlock(&dev_priv->rps.hw_lock);
4259 /* Quoting Art Runyan: "its not safe to expect any particular
4260 * value in IPS_CTL bit 31 after enabling IPS through the
4261 * mailbox." Moreover, the mailbox may return a bogus state,
4262 * so we need to just enable it and continue on.
4263 */
4264 } else {
4265 I915_WRITE(IPS_CTL, IPS_ENABLE);
4266 /* The bit only becomes 1 in the next vblank, so this wait here
4267 * is essentially intel_wait_for_vblank. If we don't have this
4268 * and don't wait for vblanks until the end of crtc_enable, then
4269 * the HW state readout code will complain that the expected
4270 * IPS_CTL value is not the one we read. */
4271 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4272 DRM_ERROR("Timed out waiting for IPS enable\n");
4273 }
4274 }
4275
4276 void hsw_disable_ips(struct intel_crtc *crtc)
4277 {
4278 struct drm_device *dev = crtc->base.dev;
4279 struct drm_i915_private *dev_priv = dev->dev_private;
4280
4281 if (!crtc->config->ips_enabled)
4282 return;
4283
4284 assert_plane_enabled(dev_priv, crtc->plane);
4285 if (IS_BROADWELL(dev)) {
4286 mutex_lock(&dev_priv->rps.hw_lock);
4287 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4288 mutex_unlock(&dev_priv->rps.hw_lock);
4289 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4290 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4291 DRM_ERROR("Timed out waiting for IPS disable\n");
4292 } else {
4293 I915_WRITE(IPS_CTL, 0);
4294 POSTING_READ(IPS_CTL);
4295 }
4296
4297 /* We need to wait for a vblank before we can disable the plane. */
4298 intel_wait_for_vblank(dev, crtc->pipe);
4299 }
4300
4301 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4302 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4303 {
4304 struct drm_device *dev = crtc->dev;
4305 struct drm_i915_private *dev_priv = dev->dev_private;
4306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4307 enum pipe pipe = intel_crtc->pipe;
4308 int palreg = PALETTE(pipe);
4309 int i;
4310 bool reenable_ips = false;
4311
4312 /* The clocks have to be on to load the palette. */
4313 if (!crtc->state->enable || !intel_crtc->active)
4314 return;
4315
4316 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4317 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4318 assert_dsi_pll_enabled(dev_priv);
4319 else
4320 assert_pll_enabled(dev_priv, pipe);
4321 }
4322
4323 /* use legacy palette for Ironlake */
4324 if (!HAS_GMCH_DISPLAY(dev))
4325 palreg = LGC_PALETTE(pipe);
4326
4327 /* Workaround : Do not read or write the pipe palette/gamma data while
4328 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4329 */
4330 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4331 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4332 GAMMA_MODE_MODE_SPLIT)) {
4333 hsw_disable_ips(intel_crtc);
4334 reenable_ips = true;
4335 }
4336
4337 for (i = 0; i < 256; i++) {
4338 I915_WRITE(palreg + 4 * i,
4339 (intel_crtc->lut_r[i] << 16) |
4340 (intel_crtc->lut_g[i] << 8) |
4341 intel_crtc->lut_b[i]);
4342 }
4343
4344 if (reenable_ips)
4345 hsw_enable_ips(intel_crtc);
4346 }
4347
4348 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4349 {
4350 if (!enable && intel_crtc->overlay) {
4351 struct drm_device *dev = intel_crtc->base.dev;
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353
4354 mutex_lock(&dev->struct_mutex);
4355 dev_priv->mm.interruptible = false;
4356 (void) intel_overlay_switch_off(intel_crtc->overlay);
4357 dev_priv->mm.interruptible = true;
4358 mutex_unlock(&dev->struct_mutex);
4359 }
4360
4361 /* Let userspace switch the overlay on again. In most cases userspace
4362 * has to recompute where to put it anyway.
4363 */
4364 }
4365
4366 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4367 {
4368 struct drm_device *dev = crtc->dev;
4369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4370 int pipe = intel_crtc->pipe;
4371
4372 intel_enable_primary_hw_plane(crtc->primary, crtc);
4373 intel_enable_sprite_planes(crtc);
4374 intel_crtc_update_cursor(crtc, true);
4375 intel_crtc_dpms_overlay(intel_crtc, true);
4376
4377 hsw_enable_ips(intel_crtc);
4378
4379 mutex_lock(&dev->struct_mutex);
4380 intel_fbc_update(dev);
4381 mutex_unlock(&dev->struct_mutex);
4382
4383 /*
4384 * FIXME: Once we grow proper nuclear flip support out of this we need
4385 * to compute the mask of flip planes precisely. For the time being
4386 * consider this a flip from a NULL plane.
4387 */
4388 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4389 }
4390
4391 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4392 {
4393 struct drm_device *dev = crtc->dev;
4394 struct drm_i915_private *dev_priv = dev->dev_private;
4395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4396 int pipe = intel_crtc->pipe;
4397
4398 intel_crtc_wait_for_pending_flips(crtc);
4399
4400 if (dev_priv->fbc.crtc == intel_crtc)
4401 intel_fbc_disable(dev);
4402
4403 hsw_disable_ips(intel_crtc);
4404
4405 intel_crtc_dpms_overlay(intel_crtc, false);
4406 intel_crtc_update_cursor(crtc, false);
4407 intel_disable_sprite_planes(crtc);
4408 intel_disable_primary_hw_plane(crtc->primary, crtc);
4409
4410 /*
4411 * FIXME: Once we grow proper nuclear flip support out of this we need
4412 * to compute the mask of flip planes precisely. For the time being
4413 * consider this a flip to a NULL plane.
4414 */
4415 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4416 }
4417
4418 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4419 {
4420 struct drm_device *dev = crtc->dev;
4421 struct drm_i915_private *dev_priv = dev->dev_private;
4422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4423 struct intel_encoder *encoder;
4424 int pipe = intel_crtc->pipe;
4425
4426 WARN_ON(!crtc->state->enable);
4427
4428 if (intel_crtc->active)
4429 return;
4430
4431 if (intel_crtc->config->has_pch_encoder)
4432 intel_prepare_shared_dpll(intel_crtc);
4433
4434 if (intel_crtc->config->has_dp_encoder)
4435 intel_dp_set_m_n(intel_crtc, M1_N1);
4436
4437 intel_set_pipe_timings(intel_crtc);
4438
4439 if (intel_crtc->config->has_pch_encoder) {
4440 intel_cpu_transcoder_set_m_n(intel_crtc,
4441 &intel_crtc->config->fdi_m_n, NULL);
4442 }
4443
4444 ironlake_set_pipeconf(crtc);
4445
4446 intel_crtc->active = true;
4447
4448 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4449 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4450
4451 for_each_encoder_on_crtc(dev, crtc, encoder)
4452 if (encoder->pre_enable)
4453 encoder->pre_enable(encoder);
4454
4455 if (intel_crtc->config->has_pch_encoder) {
4456 /* Note: FDI PLL enabling _must_ be done before we enable the
4457 * cpu pipes, hence this is separate from all the other fdi/pch
4458 * enabling. */
4459 ironlake_fdi_pll_enable(intel_crtc);
4460 } else {
4461 assert_fdi_tx_disabled(dev_priv, pipe);
4462 assert_fdi_rx_disabled(dev_priv, pipe);
4463 }
4464
4465 ironlake_pfit_enable(intel_crtc);
4466
4467 /*
4468 * On ILK+ LUT must be loaded before the pipe is running but with
4469 * clocks enabled
4470 */
4471 intel_crtc_load_lut(crtc);
4472
4473 intel_update_watermarks(crtc);
4474 intel_enable_pipe(intel_crtc);
4475
4476 if (intel_crtc->config->has_pch_encoder)
4477 ironlake_pch_enable(crtc);
4478
4479 assert_vblank_disabled(crtc);
4480 drm_crtc_vblank_on(crtc);
4481
4482 for_each_encoder_on_crtc(dev, crtc, encoder)
4483 encoder->enable(encoder);
4484
4485 if (HAS_PCH_CPT(dev))
4486 cpt_verify_modeset(dev, intel_crtc->pipe);
4487
4488 intel_crtc_enable_planes(crtc);
4489 }
4490
4491 /* IPS only exists on ULT machines and is tied to pipe A. */
4492 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4493 {
4494 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4495 }
4496
4497 /*
4498 * This implements the workaround described in the "notes" section of the mode
4499 * set sequence documentation. When going from no pipes or single pipe to
4500 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4501 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4502 */
4503 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4504 {
4505 struct drm_device *dev = crtc->base.dev;
4506 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4507
4508 /* We want to get the other_active_crtc only if there's only 1 other
4509 * active crtc. */
4510 for_each_intel_crtc(dev, crtc_it) {
4511 if (!crtc_it->active || crtc_it == crtc)
4512 continue;
4513
4514 if (other_active_crtc)
4515 return;
4516
4517 other_active_crtc = crtc_it;
4518 }
4519 if (!other_active_crtc)
4520 return;
4521
4522 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4523 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4524 }
4525
4526 static void haswell_crtc_enable(struct drm_crtc *crtc)
4527 {
4528 struct drm_device *dev = crtc->dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4531 struct intel_encoder *encoder;
4532 int pipe = intel_crtc->pipe;
4533
4534 WARN_ON(!crtc->state->enable);
4535
4536 if (intel_crtc->active)
4537 return;
4538
4539 if (intel_crtc_to_shared_dpll(intel_crtc))
4540 intel_enable_shared_dpll(intel_crtc);
4541
4542 if (intel_crtc->config->has_dp_encoder)
4543 intel_dp_set_m_n(intel_crtc, M1_N1);
4544
4545 intel_set_pipe_timings(intel_crtc);
4546
4547 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4548 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4549 intel_crtc->config->pixel_multiplier - 1);
4550 }
4551
4552 if (intel_crtc->config->has_pch_encoder) {
4553 intel_cpu_transcoder_set_m_n(intel_crtc,
4554 &intel_crtc->config->fdi_m_n, NULL);
4555 }
4556
4557 haswell_set_pipeconf(crtc);
4558
4559 intel_set_pipe_csc(crtc);
4560
4561 intel_crtc->active = true;
4562
4563 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4564 for_each_encoder_on_crtc(dev, crtc, encoder)
4565 if (encoder->pre_enable)
4566 encoder->pre_enable(encoder);
4567
4568 if (intel_crtc->config->has_pch_encoder) {
4569 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4570 true);
4571 dev_priv->display.fdi_link_train(crtc);
4572 }
4573
4574 intel_ddi_enable_pipe_clock(intel_crtc);
4575
4576 if (IS_SKYLAKE(dev))
4577 skylake_pfit_enable(intel_crtc);
4578 else
4579 ironlake_pfit_enable(intel_crtc);
4580
4581 /*
4582 * On ILK+ LUT must be loaded before the pipe is running but with
4583 * clocks enabled
4584 */
4585 intel_crtc_load_lut(crtc);
4586
4587 intel_ddi_set_pipe_settings(crtc);
4588 intel_ddi_enable_transcoder_func(crtc);
4589
4590 intel_update_watermarks(crtc);
4591 intel_enable_pipe(intel_crtc);
4592
4593 if (intel_crtc->config->has_pch_encoder)
4594 lpt_pch_enable(crtc);
4595
4596 if (intel_crtc->config->dp_encoder_is_mst)
4597 intel_ddi_set_vc_payload_alloc(crtc, true);
4598
4599 assert_vblank_disabled(crtc);
4600 drm_crtc_vblank_on(crtc);
4601
4602 for_each_encoder_on_crtc(dev, crtc, encoder) {
4603 encoder->enable(encoder);
4604 intel_opregion_notify_encoder(encoder, true);
4605 }
4606
4607 /* If we change the relative order between pipe/planes enabling, we need
4608 * to change the workaround. */
4609 haswell_mode_set_planes_workaround(intel_crtc);
4610 intel_crtc_enable_planes(crtc);
4611 }
4612
4613 static void skylake_pfit_disable(struct intel_crtc *crtc)
4614 {
4615 struct drm_device *dev = crtc->base.dev;
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617 int pipe = crtc->pipe;
4618
4619 /* To avoid upsetting the power well on haswell only disable the pfit if
4620 * it's in use. The hw state code will make sure we get this right. */
4621 if (crtc->config->pch_pfit.enabled) {
4622 I915_WRITE(PS_CTL(pipe), 0);
4623 I915_WRITE(PS_WIN_POS(pipe), 0);
4624 I915_WRITE(PS_WIN_SZ(pipe), 0);
4625 }
4626 }
4627
4628 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4629 {
4630 struct drm_device *dev = crtc->base.dev;
4631 struct drm_i915_private *dev_priv = dev->dev_private;
4632 int pipe = crtc->pipe;
4633
4634 /* To avoid upsetting the power well on haswell only disable the pfit if
4635 * it's in use. The hw state code will make sure we get this right. */
4636 if (crtc->config->pch_pfit.enabled) {
4637 I915_WRITE(PF_CTL(pipe), 0);
4638 I915_WRITE(PF_WIN_POS(pipe), 0);
4639 I915_WRITE(PF_WIN_SZ(pipe), 0);
4640 }
4641 }
4642
4643 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4644 {
4645 struct drm_device *dev = crtc->dev;
4646 struct drm_i915_private *dev_priv = dev->dev_private;
4647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4648 struct intel_encoder *encoder;
4649 int pipe = intel_crtc->pipe;
4650 u32 reg, temp;
4651
4652 if (!intel_crtc->active)
4653 return;
4654
4655 intel_crtc_disable_planes(crtc);
4656
4657 for_each_encoder_on_crtc(dev, crtc, encoder)
4658 encoder->disable(encoder);
4659
4660 drm_crtc_vblank_off(crtc);
4661 assert_vblank_disabled(crtc);
4662
4663 if (intel_crtc->config->has_pch_encoder)
4664 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4665
4666 intel_disable_pipe(intel_crtc);
4667
4668 ironlake_pfit_disable(intel_crtc);
4669
4670 for_each_encoder_on_crtc(dev, crtc, encoder)
4671 if (encoder->post_disable)
4672 encoder->post_disable(encoder);
4673
4674 if (intel_crtc->config->has_pch_encoder) {
4675 ironlake_fdi_disable(crtc);
4676
4677 ironlake_disable_pch_transcoder(dev_priv, pipe);
4678
4679 if (HAS_PCH_CPT(dev)) {
4680 /* disable TRANS_DP_CTL */
4681 reg = TRANS_DP_CTL(pipe);
4682 temp = I915_READ(reg);
4683 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4684 TRANS_DP_PORT_SEL_MASK);
4685 temp |= TRANS_DP_PORT_SEL_NONE;
4686 I915_WRITE(reg, temp);
4687
4688 /* disable DPLL_SEL */
4689 temp = I915_READ(PCH_DPLL_SEL);
4690 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4691 I915_WRITE(PCH_DPLL_SEL, temp);
4692 }
4693
4694 /* disable PCH DPLL */
4695 intel_disable_shared_dpll(intel_crtc);
4696
4697 ironlake_fdi_pll_disable(intel_crtc);
4698 }
4699
4700 intel_crtc->active = false;
4701 intel_update_watermarks(crtc);
4702
4703 mutex_lock(&dev->struct_mutex);
4704 intel_fbc_update(dev);
4705 mutex_unlock(&dev->struct_mutex);
4706 }
4707
4708 static void haswell_crtc_disable(struct drm_crtc *crtc)
4709 {
4710 struct drm_device *dev = crtc->dev;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 struct intel_encoder *encoder;
4714 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4715
4716 if (!intel_crtc->active)
4717 return;
4718
4719 intel_crtc_disable_planes(crtc);
4720
4721 for_each_encoder_on_crtc(dev, crtc, encoder) {
4722 intel_opregion_notify_encoder(encoder, false);
4723 encoder->disable(encoder);
4724 }
4725
4726 drm_crtc_vblank_off(crtc);
4727 assert_vblank_disabled(crtc);
4728
4729 if (intel_crtc->config->has_pch_encoder)
4730 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4731 false);
4732 intel_disable_pipe(intel_crtc);
4733
4734 if (intel_crtc->config->dp_encoder_is_mst)
4735 intel_ddi_set_vc_payload_alloc(crtc, false);
4736
4737 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4738
4739 if (IS_SKYLAKE(dev))
4740 skylake_pfit_disable(intel_crtc);
4741 else
4742 ironlake_pfit_disable(intel_crtc);
4743
4744 intel_ddi_disable_pipe_clock(intel_crtc);
4745
4746 if (intel_crtc->config->has_pch_encoder) {
4747 lpt_disable_pch_transcoder(dev_priv);
4748 intel_ddi_fdi_disable(crtc);
4749 }
4750
4751 for_each_encoder_on_crtc(dev, crtc, encoder)
4752 if (encoder->post_disable)
4753 encoder->post_disable(encoder);
4754
4755 intel_crtc->active = false;
4756 intel_update_watermarks(crtc);
4757
4758 mutex_lock(&dev->struct_mutex);
4759 intel_fbc_update(dev);
4760 mutex_unlock(&dev->struct_mutex);
4761
4762 if (intel_crtc_to_shared_dpll(intel_crtc))
4763 intel_disable_shared_dpll(intel_crtc);
4764 }
4765
4766 static void ironlake_crtc_off(struct drm_crtc *crtc)
4767 {
4768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4769 intel_put_shared_dpll(intel_crtc);
4770 }
4771
4772
4773 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4774 {
4775 struct drm_device *dev = crtc->base.dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
4777 struct intel_crtc_state *pipe_config = crtc->config;
4778
4779 if (!pipe_config->gmch_pfit.control)
4780 return;
4781
4782 /*
4783 * The panel fitter should only be adjusted whilst the pipe is disabled,
4784 * according to register description and PRM.
4785 */
4786 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4787 assert_pipe_disabled(dev_priv, crtc->pipe);
4788
4789 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4790 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4791
4792 /* Border color in case we don't scale up to the full screen. Black by
4793 * default, change to something else for debugging. */
4794 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4795 }
4796
4797 static enum intel_display_power_domain port_to_power_domain(enum port port)
4798 {
4799 switch (port) {
4800 case PORT_A:
4801 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4802 case PORT_B:
4803 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4804 case PORT_C:
4805 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4806 case PORT_D:
4807 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4808 default:
4809 WARN_ON_ONCE(1);
4810 return POWER_DOMAIN_PORT_OTHER;
4811 }
4812 }
4813
4814 #define for_each_power_domain(domain, mask) \
4815 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4816 if ((1 << (domain)) & (mask))
4817
4818 enum intel_display_power_domain
4819 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4820 {
4821 struct drm_device *dev = intel_encoder->base.dev;
4822 struct intel_digital_port *intel_dig_port;
4823
4824 switch (intel_encoder->type) {
4825 case INTEL_OUTPUT_UNKNOWN:
4826 /* Only DDI platforms should ever use this output type */
4827 WARN_ON_ONCE(!HAS_DDI(dev));
4828 case INTEL_OUTPUT_DISPLAYPORT:
4829 case INTEL_OUTPUT_HDMI:
4830 case INTEL_OUTPUT_EDP:
4831 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4832 return port_to_power_domain(intel_dig_port->port);
4833 case INTEL_OUTPUT_DP_MST:
4834 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4835 return port_to_power_domain(intel_dig_port->port);
4836 case INTEL_OUTPUT_ANALOG:
4837 return POWER_DOMAIN_PORT_CRT;
4838 case INTEL_OUTPUT_DSI:
4839 return POWER_DOMAIN_PORT_DSI;
4840 default:
4841 return POWER_DOMAIN_PORT_OTHER;
4842 }
4843 }
4844
4845 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4846 {
4847 struct drm_device *dev = crtc->dev;
4848 struct intel_encoder *intel_encoder;
4849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4850 enum pipe pipe = intel_crtc->pipe;
4851 unsigned long mask;
4852 enum transcoder transcoder;
4853
4854 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4855
4856 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4857 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4858 if (intel_crtc->config->pch_pfit.enabled ||
4859 intel_crtc->config->pch_pfit.force_thru)
4860 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4861
4862 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4863 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4864
4865 return mask;
4866 }
4867
4868 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4869 {
4870 struct drm_i915_private *dev_priv = dev->dev_private;
4871 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4872 struct intel_crtc *crtc;
4873
4874 /*
4875 * First get all needed power domains, then put all unneeded, to avoid
4876 * any unnecessary toggling of the power wells.
4877 */
4878 for_each_intel_crtc(dev, crtc) {
4879 enum intel_display_power_domain domain;
4880
4881 if (!crtc->base.state->enable)
4882 continue;
4883
4884 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4885
4886 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4887 intel_display_power_get(dev_priv, domain);
4888 }
4889
4890 if (dev_priv->display.modeset_global_resources)
4891 dev_priv->display.modeset_global_resources(dev);
4892
4893 for_each_intel_crtc(dev, crtc) {
4894 enum intel_display_power_domain domain;
4895
4896 for_each_power_domain(domain, crtc->enabled_power_domains)
4897 intel_display_power_put(dev_priv, domain);
4898
4899 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4900 }
4901
4902 intel_display_set_init_power(dev_priv, false);
4903 }
4904
4905 /* returns HPLL frequency in kHz */
4906 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4907 {
4908 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4909
4910 /* Obtain SKU information */
4911 mutex_lock(&dev_priv->dpio_lock);
4912 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4913 CCK_FUSE_HPLL_FREQ_MASK;
4914 mutex_unlock(&dev_priv->dpio_lock);
4915
4916 return vco_freq[hpll_freq] * 1000;
4917 }
4918
4919 static void vlv_update_cdclk(struct drm_device *dev)
4920 {
4921 struct drm_i915_private *dev_priv = dev->dev_private;
4922
4923 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4924 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4925 dev_priv->vlv_cdclk_freq);
4926
4927 /*
4928 * Program the gmbus_freq based on the cdclk frequency.
4929 * BSpec erroneously claims we should aim for 4MHz, but
4930 * in fact 1MHz is the correct frequency.
4931 */
4932 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4933 }
4934
4935 /* Adjust CDclk dividers to allow high res or save power if possible */
4936 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4937 {
4938 struct drm_i915_private *dev_priv = dev->dev_private;
4939 u32 val, cmd;
4940
4941 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4942
4943 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4944 cmd = 2;
4945 else if (cdclk == 266667)
4946 cmd = 1;
4947 else
4948 cmd = 0;
4949
4950 mutex_lock(&dev_priv->rps.hw_lock);
4951 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4952 val &= ~DSPFREQGUAR_MASK;
4953 val |= (cmd << DSPFREQGUAR_SHIFT);
4954 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4955 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4956 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4957 50)) {
4958 DRM_ERROR("timed out waiting for CDclk change\n");
4959 }
4960 mutex_unlock(&dev_priv->rps.hw_lock);
4961
4962 if (cdclk == 400000) {
4963 u32 divider;
4964
4965 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4966
4967 mutex_lock(&dev_priv->dpio_lock);
4968 /* adjust cdclk divider */
4969 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4970 val &= ~DISPLAY_FREQUENCY_VALUES;
4971 val |= divider;
4972 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4973
4974 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4975 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4976 50))
4977 DRM_ERROR("timed out waiting for CDclk change\n");
4978 mutex_unlock(&dev_priv->dpio_lock);
4979 }
4980
4981 mutex_lock(&dev_priv->dpio_lock);
4982 /* adjust self-refresh exit latency value */
4983 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4984 val &= ~0x7f;
4985
4986 /*
4987 * For high bandwidth configs, we set a higher latency in the bunit
4988 * so that the core display fetch happens in time to avoid underruns.
4989 */
4990 if (cdclk == 400000)
4991 val |= 4500 / 250; /* 4.5 usec */
4992 else
4993 val |= 3000 / 250; /* 3.0 usec */
4994 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4995 mutex_unlock(&dev_priv->dpio_lock);
4996
4997 vlv_update_cdclk(dev);
4998 }
4999
5000 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5001 {
5002 struct drm_i915_private *dev_priv = dev->dev_private;
5003 u32 val, cmd;
5004
5005 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5006
5007 switch (cdclk) {
5008 case 333333:
5009 case 320000:
5010 case 266667:
5011 case 200000:
5012 break;
5013 default:
5014 MISSING_CASE(cdclk);
5015 return;
5016 }
5017
5018 /*
5019 * Specs are full of misinformation, but testing on actual
5020 * hardware has shown that we just need to write the desired
5021 * CCK divider into the Punit register.
5022 */
5023 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5024
5025 mutex_lock(&dev_priv->rps.hw_lock);
5026 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5027 val &= ~DSPFREQGUAR_MASK_CHV;
5028 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5029 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5030 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5031 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5032 50)) {
5033 DRM_ERROR("timed out waiting for CDclk change\n");
5034 }
5035 mutex_unlock(&dev_priv->rps.hw_lock);
5036
5037 vlv_update_cdclk(dev);
5038 }
5039
5040 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5041 int max_pixclk)
5042 {
5043 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5044 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5045
5046 /*
5047 * Really only a few cases to deal with, as only 4 CDclks are supported:
5048 * 200MHz
5049 * 267MHz
5050 * 320/333MHz (depends on HPLL freq)
5051 * 400MHz (VLV only)
5052 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5053 * of the lower bin and adjust if needed.
5054 *
5055 * We seem to get an unstable or solid color picture at 200MHz.
5056 * Not sure what's wrong. For now use 200MHz only when all pipes
5057 * are off.
5058 */
5059 if (!IS_CHERRYVIEW(dev_priv) &&
5060 max_pixclk > freq_320*limit/100)
5061 return 400000;
5062 else if (max_pixclk > 266667*limit/100)
5063 return freq_320;
5064 else if (max_pixclk > 0)
5065 return 266667;
5066 else
5067 return 200000;
5068 }
5069
5070 /* compute the max pixel clock for new configuration */
5071 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5072 {
5073 struct drm_device *dev = dev_priv->dev;
5074 struct intel_crtc *intel_crtc;
5075 int max_pixclk = 0;
5076
5077 for_each_intel_crtc(dev, intel_crtc) {
5078 if (intel_crtc->new_enabled)
5079 max_pixclk = max(max_pixclk,
5080 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5081 }
5082
5083 return max_pixclk;
5084 }
5085
5086 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5087 unsigned *prepare_pipes)
5088 {
5089 struct drm_i915_private *dev_priv = dev->dev_private;
5090 struct intel_crtc *intel_crtc;
5091 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5092
5093 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5094 dev_priv->vlv_cdclk_freq)
5095 return;
5096
5097 /* disable/enable all currently active pipes while we change cdclk */
5098 for_each_intel_crtc(dev, intel_crtc)
5099 if (intel_crtc->base.state->enable)
5100 *prepare_pipes |= (1 << intel_crtc->pipe);
5101 }
5102
5103 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5104 {
5105 unsigned int credits, default_credits;
5106
5107 if (IS_CHERRYVIEW(dev_priv))
5108 default_credits = PFI_CREDIT(12);
5109 else
5110 default_credits = PFI_CREDIT(8);
5111
5112 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5113 /* CHV suggested value is 31 or 63 */
5114 if (IS_CHERRYVIEW(dev_priv))
5115 credits = PFI_CREDIT_31;
5116 else
5117 credits = PFI_CREDIT(15);
5118 } else {
5119 credits = default_credits;
5120 }
5121
5122 /*
5123 * WA - write default credits before re-programming
5124 * FIXME: should we also set the resend bit here?
5125 */
5126 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5127 default_credits);
5128
5129 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5130 credits | PFI_CREDIT_RESEND);
5131
5132 /*
5133 * FIXME is this guaranteed to clear
5134 * immediately or should we poll for it?
5135 */
5136 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5137 }
5138
5139 static void valleyview_modeset_global_resources(struct drm_device *dev)
5140 {
5141 struct drm_i915_private *dev_priv = dev->dev_private;
5142 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5143 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5144
5145 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5146 /*
5147 * FIXME: We can end up here with all power domains off, yet
5148 * with a CDCLK frequency other than the minimum. To account
5149 * for this take the PIPE-A power domain, which covers the HW
5150 * blocks needed for the following programming. This can be
5151 * removed once it's guaranteed that we get here either with
5152 * the minimum CDCLK set, or the required power domains
5153 * enabled.
5154 */
5155 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5156
5157 if (IS_CHERRYVIEW(dev))
5158 cherryview_set_cdclk(dev, req_cdclk);
5159 else
5160 valleyview_set_cdclk(dev, req_cdclk);
5161
5162 vlv_program_pfi_credits(dev_priv);
5163
5164 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5165 }
5166 }
5167
5168 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5169 {
5170 struct drm_device *dev = crtc->dev;
5171 struct drm_i915_private *dev_priv = to_i915(dev);
5172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5173 struct intel_encoder *encoder;
5174 int pipe = intel_crtc->pipe;
5175 bool is_dsi;
5176
5177 WARN_ON(!crtc->state->enable);
5178
5179 if (intel_crtc->active)
5180 return;
5181
5182 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5183
5184 if (!is_dsi) {
5185 if (IS_CHERRYVIEW(dev))
5186 chv_prepare_pll(intel_crtc, intel_crtc->config);
5187 else
5188 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5189 }
5190
5191 if (intel_crtc->config->has_dp_encoder)
5192 intel_dp_set_m_n(intel_crtc, M1_N1);
5193
5194 intel_set_pipe_timings(intel_crtc);
5195
5196 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5197 struct drm_i915_private *dev_priv = dev->dev_private;
5198
5199 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5200 I915_WRITE(CHV_CANVAS(pipe), 0);
5201 }
5202
5203 i9xx_set_pipeconf(intel_crtc);
5204
5205 intel_crtc->active = true;
5206
5207 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5208
5209 for_each_encoder_on_crtc(dev, crtc, encoder)
5210 if (encoder->pre_pll_enable)
5211 encoder->pre_pll_enable(encoder);
5212
5213 if (!is_dsi) {
5214 if (IS_CHERRYVIEW(dev))
5215 chv_enable_pll(intel_crtc, intel_crtc->config);
5216 else
5217 vlv_enable_pll(intel_crtc, intel_crtc->config);
5218 }
5219
5220 for_each_encoder_on_crtc(dev, crtc, encoder)
5221 if (encoder->pre_enable)
5222 encoder->pre_enable(encoder);
5223
5224 i9xx_pfit_enable(intel_crtc);
5225
5226 intel_crtc_load_lut(crtc);
5227
5228 intel_update_watermarks(crtc);
5229 intel_enable_pipe(intel_crtc);
5230
5231 assert_vblank_disabled(crtc);
5232 drm_crtc_vblank_on(crtc);
5233
5234 for_each_encoder_on_crtc(dev, crtc, encoder)
5235 encoder->enable(encoder);
5236
5237 intel_crtc_enable_planes(crtc);
5238
5239 /* Underruns don't raise interrupts, so check manually. */
5240 i9xx_check_fifo_underruns(dev_priv);
5241 }
5242
5243 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5244 {
5245 struct drm_device *dev = crtc->base.dev;
5246 struct drm_i915_private *dev_priv = dev->dev_private;
5247
5248 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5249 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5250 }
5251
5252 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5253 {
5254 struct drm_device *dev = crtc->dev;
5255 struct drm_i915_private *dev_priv = to_i915(dev);
5256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5257 struct intel_encoder *encoder;
5258 int pipe = intel_crtc->pipe;
5259
5260 WARN_ON(!crtc->state->enable);
5261
5262 if (intel_crtc->active)
5263 return;
5264
5265 i9xx_set_pll_dividers(intel_crtc);
5266
5267 if (intel_crtc->config->has_dp_encoder)
5268 intel_dp_set_m_n(intel_crtc, M1_N1);
5269
5270 intel_set_pipe_timings(intel_crtc);
5271
5272 i9xx_set_pipeconf(intel_crtc);
5273
5274 intel_crtc->active = true;
5275
5276 if (!IS_GEN2(dev))
5277 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5278
5279 for_each_encoder_on_crtc(dev, crtc, encoder)
5280 if (encoder->pre_enable)
5281 encoder->pre_enable(encoder);
5282
5283 i9xx_enable_pll(intel_crtc);
5284
5285 i9xx_pfit_enable(intel_crtc);
5286
5287 intel_crtc_load_lut(crtc);
5288
5289 intel_update_watermarks(crtc);
5290 intel_enable_pipe(intel_crtc);
5291
5292 assert_vblank_disabled(crtc);
5293 drm_crtc_vblank_on(crtc);
5294
5295 for_each_encoder_on_crtc(dev, crtc, encoder)
5296 encoder->enable(encoder);
5297
5298 intel_crtc_enable_planes(crtc);
5299
5300 /*
5301 * Gen2 reports pipe underruns whenever all planes are disabled.
5302 * So don't enable underrun reporting before at least some planes
5303 * are enabled.
5304 * FIXME: Need to fix the logic to work when we turn off all planes
5305 * but leave the pipe running.
5306 */
5307 if (IS_GEN2(dev))
5308 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5309
5310 /* Underruns don't raise interrupts, so check manually. */
5311 i9xx_check_fifo_underruns(dev_priv);
5312 }
5313
5314 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5315 {
5316 struct drm_device *dev = crtc->base.dev;
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5318
5319 if (!crtc->config->gmch_pfit.control)
5320 return;
5321
5322 assert_pipe_disabled(dev_priv, crtc->pipe);
5323
5324 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5325 I915_READ(PFIT_CONTROL));
5326 I915_WRITE(PFIT_CONTROL, 0);
5327 }
5328
5329 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5330 {
5331 struct drm_device *dev = crtc->dev;
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5334 struct intel_encoder *encoder;
5335 int pipe = intel_crtc->pipe;
5336
5337 if (!intel_crtc->active)
5338 return;
5339
5340 /*
5341 * Gen2 reports pipe underruns whenever all planes are disabled.
5342 * So diasble underrun reporting before all the planes get disabled.
5343 * FIXME: Need to fix the logic to work when we turn off all planes
5344 * but leave the pipe running.
5345 */
5346 if (IS_GEN2(dev))
5347 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5348
5349 /*
5350 * Vblank time updates from the shadow to live plane control register
5351 * are blocked if the memory self-refresh mode is active at that
5352 * moment. So to make sure the plane gets truly disabled, disable
5353 * first the self-refresh mode. The self-refresh enable bit in turn
5354 * will be checked/applied by the HW only at the next frame start
5355 * event which is after the vblank start event, so we need to have a
5356 * wait-for-vblank between disabling the plane and the pipe.
5357 */
5358 intel_set_memory_cxsr(dev_priv, false);
5359 intel_crtc_disable_planes(crtc);
5360
5361 /*
5362 * On gen2 planes are double buffered but the pipe isn't, so we must
5363 * wait for planes to fully turn off before disabling the pipe.
5364 * We also need to wait on all gmch platforms because of the
5365 * self-refresh mode constraint explained above.
5366 */
5367 intel_wait_for_vblank(dev, pipe);
5368
5369 for_each_encoder_on_crtc(dev, crtc, encoder)
5370 encoder->disable(encoder);
5371
5372 drm_crtc_vblank_off(crtc);
5373 assert_vblank_disabled(crtc);
5374
5375 intel_disable_pipe(intel_crtc);
5376
5377 i9xx_pfit_disable(intel_crtc);
5378
5379 for_each_encoder_on_crtc(dev, crtc, encoder)
5380 if (encoder->post_disable)
5381 encoder->post_disable(encoder);
5382
5383 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5384 if (IS_CHERRYVIEW(dev))
5385 chv_disable_pll(dev_priv, pipe);
5386 else if (IS_VALLEYVIEW(dev))
5387 vlv_disable_pll(dev_priv, pipe);
5388 else
5389 i9xx_disable_pll(intel_crtc);
5390 }
5391
5392 if (!IS_GEN2(dev))
5393 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5394
5395 intel_crtc->active = false;
5396 intel_update_watermarks(crtc);
5397
5398 mutex_lock(&dev->struct_mutex);
5399 intel_fbc_update(dev);
5400 mutex_unlock(&dev->struct_mutex);
5401 }
5402
5403 static void i9xx_crtc_off(struct drm_crtc *crtc)
5404 {
5405 }
5406
5407 /* Master function to enable/disable CRTC and corresponding power wells */
5408 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5409 {
5410 struct drm_device *dev = crtc->dev;
5411 struct drm_i915_private *dev_priv = dev->dev_private;
5412 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5413 enum intel_display_power_domain domain;
5414 unsigned long domains;
5415
5416 if (enable) {
5417 if (!intel_crtc->active) {
5418 domains = get_crtc_power_domains(crtc);
5419 for_each_power_domain(domain, domains)
5420 intel_display_power_get(dev_priv, domain);
5421 intel_crtc->enabled_power_domains = domains;
5422
5423 dev_priv->display.crtc_enable(crtc);
5424 }
5425 } else {
5426 if (intel_crtc->active) {
5427 dev_priv->display.crtc_disable(crtc);
5428
5429 domains = intel_crtc->enabled_power_domains;
5430 for_each_power_domain(domain, domains)
5431 intel_display_power_put(dev_priv, domain);
5432 intel_crtc->enabled_power_domains = 0;
5433 }
5434 }
5435 }
5436
5437 /**
5438 * Sets the power management mode of the pipe and plane.
5439 */
5440 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5441 {
5442 struct drm_device *dev = crtc->dev;
5443 struct intel_encoder *intel_encoder;
5444 bool enable = false;
5445
5446 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5447 enable |= intel_encoder->connectors_active;
5448
5449 intel_crtc_control(crtc, enable);
5450 }
5451
5452 static void intel_crtc_disable(struct drm_crtc *crtc)
5453 {
5454 struct drm_device *dev = crtc->dev;
5455 struct drm_connector *connector;
5456 struct drm_i915_private *dev_priv = dev->dev_private;
5457
5458 /* crtc should still be enabled when we disable it. */
5459 WARN_ON(!crtc->state->enable);
5460
5461 dev_priv->display.crtc_disable(crtc);
5462 dev_priv->display.off(crtc);
5463
5464 crtc->primary->funcs->disable_plane(crtc->primary);
5465
5466 /* Update computed state. */
5467 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5468 if (!connector->encoder || !connector->encoder->crtc)
5469 continue;
5470
5471 if (connector->encoder->crtc != crtc)
5472 continue;
5473
5474 connector->dpms = DRM_MODE_DPMS_OFF;
5475 to_intel_encoder(connector->encoder)->connectors_active = false;
5476 }
5477 }
5478
5479 void intel_encoder_destroy(struct drm_encoder *encoder)
5480 {
5481 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5482
5483 drm_encoder_cleanup(encoder);
5484 kfree(intel_encoder);
5485 }
5486
5487 /* Simple dpms helper for encoders with just one connector, no cloning and only
5488 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5489 * state of the entire output pipe. */
5490 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5491 {
5492 if (mode == DRM_MODE_DPMS_ON) {
5493 encoder->connectors_active = true;
5494
5495 intel_crtc_update_dpms(encoder->base.crtc);
5496 } else {
5497 encoder->connectors_active = false;
5498
5499 intel_crtc_update_dpms(encoder->base.crtc);
5500 }
5501 }
5502
5503 /* Cross check the actual hw state with our own modeset state tracking (and it's
5504 * internal consistency). */
5505 static void intel_connector_check_state(struct intel_connector *connector)
5506 {
5507 if (connector->get_hw_state(connector)) {
5508 struct intel_encoder *encoder = connector->encoder;
5509 struct drm_crtc *crtc;
5510 bool encoder_enabled;
5511 enum pipe pipe;
5512
5513 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5514 connector->base.base.id,
5515 connector->base.name);
5516
5517 /* there is no real hw state for MST connectors */
5518 if (connector->mst_port)
5519 return;
5520
5521 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5522 "wrong connector dpms state\n");
5523 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5524 "active connector not linked to encoder\n");
5525
5526 if (encoder) {
5527 I915_STATE_WARN(!encoder->connectors_active,
5528 "encoder->connectors_active not set\n");
5529
5530 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5531 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5532 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5533 return;
5534
5535 crtc = encoder->base.crtc;
5536
5537 I915_STATE_WARN(!crtc->state->enable,
5538 "crtc not enabled\n");
5539 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5540 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5541 "encoder active on the wrong pipe\n");
5542 }
5543 }
5544 }
5545
5546 /* Even simpler default implementation, if there's really no special case to
5547 * consider. */
5548 void intel_connector_dpms(struct drm_connector *connector, int mode)
5549 {
5550 /* All the simple cases only support two dpms states. */
5551 if (mode != DRM_MODE_DPMS_ON)
5552 mode = DRM_MODE_DPMS_OFF;
5553
5554 if (mode == connector->dpms)
5555 return;
5556
5557 connector->dpms = mode;
5558
5559 /* Only need to change hw state when actually enabled */
5560 if (connector->encoder)
5561 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5562
5563 intel_modeset_check_state(connector->dev);
5564 }
5565
5566 /* Simple connector->get_hw_state implementation for encoders that support only
5567 * one connector and no cloning and hence the encoder state determines the state
5568 * of the connector. */
5569 bool intel_connector_get_hw_state(struct intel_connector *connector)
5570 {
5571 enum pipe pipe = 0;
5572 struct intel_encoder *encoder = connector->encoder;
5573
5574 return encoder->get_hw_state(encoder, &pipe);
5575 }
5576
5577 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5578 struct intel_crtc_state *pipe_config)
5579 {
5580 struct drm_i915_private *dev_priv = dev->dev_private;
5581 struct intel_crtc *pipe_B_crtc =
5582 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5583
5584 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5585 pipe_name(pipe), pipe_config->fdi_lanes);
5586 if (pipe_config->fdi_lanes > 4) {
5587 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5588 pipe_name(pipe), pipe_config->fdi_lanes);
5589 return false;
5590 }
5591
5592 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5593 if (pipe_config->fdi_lanes > 2) {
5594 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5595 pipe_config->fdi_lanes);
5596 return false;
5597 } else {
5598 return true;
5599 }
5600 }
5601
5602 if (INTEL_INFO(dev)->num_pipes == 2)
5603 return true;
5604
5605 /* Ivybridge 3 pipe is really complicated */
5606 switch (pipe) {
5607 case PIPE_A:
5608 return true;
5609 case PIPE_B:
5610 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5611 pipe_config->fdi_lanes > 2) {
5612 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5613 pipe_name(pipe), pipe_config->fdi_lanes);
5614 return false;
5615 }
5616 return true;
5617 case PIPE_C:
5618 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5619 pipe_B_crtc->config->fdi_lanes <= 2) {
5620 if (pipe_config->fdi_lanes > 2) {
5621 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5622 pipe_name(pipe), pipe_config->fdi_lanes);
5623 return false;
5624 }
5625 } else {
5626 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5627 return false;
5628 }
5629 return true;
5630 default:
5631 BUG();
5632 }
5633 }
5634
5635 #define RETRY 1
5636 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5637 struct intel_crtc_state *pipe_config)
5638 {
5639 struct drm_device *dev = intel_crtc->base.dev;
5640 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5641 int lane, link_bw, fdi_dotclock;
5642 bool setup_ok, needs_recompute = false;
5643
5644 retry:
5645 /* FDI is a binary signal running at ~2.7GHz, encoding
5646 * each output octet as 10 bits. The actual frequency
5647 * is stored as a divider into a 100MHz clock, and the
5648 * mode pixel clock is stored in units of 1KHz.
5649 * Hence the bw of each lane in terms of the mode signal
5650 * is:
5651 */
5652 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5653
5654 fdi_dotclock = adjusted_mode->crtc_clock;
5655
5656 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5657 pipe_config->pipe_bpp);
5658
5659 pipe_config->fdi_lanes = lane;
5660
5661 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5662 link_bw, &pipe_config->fdi_m_n);
5663
5664 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5665 intel_crtc->pipe, pipe_config);
5666 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5667 pipe_config->pipe_bpp -= 2*3;
5668 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5669 pipe_config->pipe_bpp);
5670 needs_recompute = true;
5671 pipe_config->bw_constrained = true;
5672
5673 goto retry;
5674 }
5675
5676 if (needs_recompute)
5677 return RETRY;
5678
5679 return setup_ok ? 0 : -EINVAL;
5680 }
5681
5682 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5683 struct intel_crtc_state *pipe_config)
5684 {
5685 pipe_config->ips_enabled = i915.enable_ips &&
5686 hsw_crtc_supports_ips(crtc) &&
5687 pipe_config->pipe_bpp <= 24;
5688 }
5689
5690 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5691 struct intel_crtc_state *pipe_config)
5692 {
5693 struct drm_device *dev = crtc->base.dev;
5694 struct drm_i915_private *dev_priv = dev->dev_private;
5695 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5696
5697 /* FIXME should check pixel clock limits on all platforms */
5698 if (INTEL_INFO(dev)->gen < 4) {
5699 int clock_limit =
5700 dev_priv->display.get_display_clock_speed(dev);
5701
5702 /*
5703 * Enable pixel doubling when the dot clock
5704 * is > 90% of the (display) core speed.
5705 *
5706 * GDG double wide on either pipe,
5707 * otherwise pipe A only.
5708 */
5709 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5710 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5711 clock_limit *= 2;
5712 pipe_config->double_wide = true;
5713 }
5714
5715 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5716 return -EINVAL;
5717 }
5718
5719 /*
5720 * Pipe horizontal size must be even in:
5721 * - DVO ganged mode
5722 * - LVDS dual channel mode
5723 * - Double wide pipe
5724 */
5725 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5726 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5727 pipe_config->pipe_src_w &= ~1;
5728
5729 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5730 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5731 */
5732 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5733 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5734 return -EINVAL;
5735
5736 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5737 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5738 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5739 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5740 * for lvds. */
5741 pipe_config->pipe_bpp = 8*3;
5742 }
5743
5744 if (HAS_IPS(dev))
5745 hsw_compute_ips_config(crtc, pipe_config);
5746
5747 if (pipe_config->has_pch_encoder)
5748 return ironlake_fdi_compute_config(crtc, pipe_config);
5749
5750 return 0;
5751 }
5752
5753 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5754 {
5755 struct drm_i915_private *dev_priv = dev->dev_private;
5756 u32 val;
5757 int divider;
5758
5759 if (dev_priv->hpll_freq == 0)
5760 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5761
5762 mutex_lock(&dev_priv->dpio_lock);
5763 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5764 mutex_unlock(&dev_priv->dpio_lock);
5765
5766 divider = val & DISPLAY_FREQUENCY_VALUES;
5767
5768 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5769 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5770 "cdclk change in progress\n");
5771
5772 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5773 }
5774
5775 static int i945_get_display_clock_speed(struct drm_device *dev)
5776 {
5777 return 400000;
5778 }
5779
5780 static int i915_get_display_clock_speed(struct drm_device *dev)
5781 {
5782 return 333000;
5783 }
5784
5785 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5786 {
5787 return 200000;
5788 }
5789
5790 static int pnv_get_display_clock_speed(struct drm_device *dev)
5791 {
5792 u16 gcfgc = 0;
5793
5794 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5795
5796 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5797 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5798 return 267000;
5799 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5800 return 333000;
5801 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5802 return 444000;
5803 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5804 return 200000;
5805 default:
5806 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5807 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5808 return 133000;
5809 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5810 return 167000;
5811 }
5812 }
5813
5814 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5815 {
5816 u16 gcfgc = 0;
5817
5818 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5819
5820 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5821 return 133000;
5822 else {
5823 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5824 case GC_DISPLAY_CLOCK_333_MHZ:
5825 return 333000;
5826 default:
5827 case GC_DISPLAY_CLOCK_190_200_MHZ:
5828 return 190000;
5829 }
5830 }
5831 }
5832
5833 static int i865_get_display_clock_speed(struct drm_device *dev)
5834 {
5835 return 266000;
5836 }
5837
5838 static int i855_get_display_clock_speed(struct drm_device *dev)
5839 {
5840 u16 hpllcc = 0;
5841 /* Assume that the hardware is in the high speed state. This
5842 * should be the default.
5843 */
5844 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5845 case GC_CLOCK_133_200:
5846 case GC_CLOCK_100_200:
5847 return 200000;
5848 case GC_CLOCK_166_250:
5849 return 250000;
5850 case GC_CLOCK_100_133:
5851 return 133000;
5852 }
5853
5854 /* Shouldn't happen */
5855 return 0;
5856 }
5857
5858 static int i830_get_display_clock_speed(struct drm_device *dev)
5859 {
5860 return 133000;
5861 }
5862
5863 static void
5864 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5865 {
5866 while (*num > DATA_LINK_M_N_MASK ||
5867 *den > DATA_LINK_M_N_MASK) {
5868 *num >>= 1;
5869 *den >>= 1;
5870 }
5871 }
5872
5873 static void compute_m_n(unsigned int m, unsigned int n,
5874 uint32_t *ret_m, uint32_t *ret_n)
5875 {
5876 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5877 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5878 intel_reduce_m_n_ratio(ret_m, ret_n);
5879 }
5880
5881 void
5882 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5883 int pixel_clock, int link_clock,
5884 struct intel_link_m_n *m_n)
5885 {
5886 m_n->tu = 64;
5887
5888 compute_m_n(bits_per_pixel * pixel_clock,
5889 link_clock * nlanes * 8,
5890 &m_n->gmch_m, &m_n->gmch_n);
5891
5892 compute_m_n(pixel_clock, link_clock,
5893 &m_n->link_m, &m_n->link_n);
5894 }
5895
5896 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5897 {
5898 if (i915.panel_use_ssc >= 0)
5899 return i915.panel_use_ssc != 0;
5900 return dev_priv->vbt.lvds_use_ssc
5901 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5902 }
5903
5904 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5905 {
5906 struct drm_device *dev = crtc->base.dev;
5907 struct drm_i915_private *dev_priv = dev->dev_private;
5908 int refclk;
5909
5910 if (IS_VALLEYVIEW(dev)) {
5911 refclk = 100000;
5912 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5913 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5914 refclk = dev_priv->vbt.lvds_ssc_freq;
5915 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5916 } else if (!IS_GEN2(dev)) {
5917 refclk = 96000;
5918 } else {
5919 refclk = 48000;
5920 }
5921
5922 return refclk;
5923 }
5924
5925 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5926 {
5927 return (1 << dpll->n) << 16 | dpll->m2;
5928 }
5929
5930 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5931 {
5932 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5933 }
5934
5935 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5936 struct intel_crtc_state *crtc_state,
5937 intel_clock_t *reduced_clock)
5938 {
5939 struct drm_device *dev = crtc->base.dev;
5940 u32 fp, fp2 = 0;
5941
5942 if (IS_PINEVIEW(dev)) {
5943 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5944 if (reduced_clock)
5945 fp2 = pnv_dpll_compute_fp(reduced_clock);
5946 } else {
5947 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5948 if (reduced_clock)
5949 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5950 }
5951
5952 crtc_state->dpll_hw_state.fp0 = fp;
5953
5954 crtc->lowfreq_avail = false;
5955 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5956 reduced_clock && i915.powersave) {
5957 crtc_state->dpll_hw_state.fp1 = fp2;
5958 crtc->lowfreq_avail = true;
5959 } else {
5960 crtc_state->dpll_hw_state.fp1 = fp;
5961 }
5962 }
5963
5964 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5965 pipe)
5966 {
5967 u32 reg_val;
5968
5969 /*
5970 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5971 * and set it to a reasonable value instead.
5972 */
5973 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5974 reg_val &= 0xffffff00;
5975 reg_val |= 0x00000030;
5976 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5977
5978 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5979 reg_val &= 0x8cffffff;
5980 reg_val = 0x8c000000;
5981 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5982
5983 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5984 reg_val &= 0xffffff00;
5985 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5986
5987 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5988 reg_val &= 0x00ffffff;
5989 reg_val |= 0xb0000000;
5990 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5991 }
5992
5993 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5994 struct intel_link_m_n *m_n)
5995 {
5996 struct drm_device *dev = crtc->base.dev;
5997 struct drm_i915_private *dev_priv = dev->dev_private;
5998 int pipe = crtc->pipe;
5999
6000 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6001 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6002 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6003 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6004 }
6005
6006 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6007 struct intel_link_m_n *m_n,
6008 struct intel_link_m_n *m2_n2)
6009 {
6010 struct drm_device *dev = crtc->base.dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 int pipe = crtc->pipe;
6013 enum transcoder transcoder = crtc->config->cpu_transcoder;
6014
6015 if (INTEL_INFO(dev)->gen >= 5) {
6016 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6017 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6018 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6019 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6020 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6021 * for gen < 8) and if DRRS is supported (to make sure the
6022 * registers are not unnecessarily accessed).
6023 */
6024 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6025 crtc->config->has_drrs) {
6026 I915_WRITE(PIPE_DATA_M2(transcoder),
6027 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6028 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6029 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6030 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6031 }
6032 } else {
6033 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6034 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6035 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6036 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6037 }
6038 }
6039
6040 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6041 {
6042 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6043
6044 if (m_n == M1_N1) {
6045 dp_m_n = &crtc->config->dp_m_n;
6046 dp_m2_n2 = &crtc->config->dp_m2_n2;
6047 } else if (m_n == M2_N2) {
6048
6049 /*
6050 * M2_N2 registers are not supported. Hence m2_n2 divider value
6051 * needs to be programmed into M1_N1.
6052 */
6053 dp_m_n = &crtc->config->dp_m2_n2;
6054 } else {
6055 DRM_ERROR("Unsupported divider value\n");
6056 return;
6057 }
6058
6059 if (crtc->config->has_pch_encoder)
6060 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6061 else
6062 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6063 }
6064
6065 static void vlv_update_pll(struct intel_crtc *crtc,
6066 struct intel_crtc_state *pipe_config)
6067 {
6068 u32 dpll, dpll_md;
6069
6070 /*
6071 * Enable DPIO clock input. We should never disable the reference
6072 * clock for pipe B, since VGA hotplug / manual detection depends
6073 * on it.
6074 */
6075 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6076 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6077 /* We should never disable this, set it here for state tracking */
6078 if (crtc->pipe == PIPE_B)
6079 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6080 dpll |= DPLL_VCO_ENABLE;
6081 pipe_config->dpll_hw_state.dpll = dpll;
6082
6083 dpll_md = (pipe_config->pixel_multiplier - 1)
6084 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6085 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6086 }
6087
6088 static void vlv_prepare_pll(struct intel_crtc *crtc,
6089 const struct intel_crtc_state *pipe_config)
6090 {
6091 struct drm_device *dev = crtc->base.dev;
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093 int pipe = crtc->pipe;
6094 u32 mdiv;
6095 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6096 u32 coreclk, reg_val;
6097
6098 mutex_lock(&dev_priv->dpio_lock);
6099
6100 bestn = pipe_config->dpll.n;
6101 bestm1 = pipe_config->dpll.m1;
6102 bestm2 = pipe_config->dpll.m2;
6103 bestp1 = pipe_config->dpll.p1;
6104 bestp2 = pipe_config->dpll.p2;
6105
6106 /* See eDP HDMI DPIO driver vbios notes doc */
6107
6108 /* PLL B needs special handling */
6109 if (pipe == PIPE_B)
6110 vlv_pllb_recal_opamp(dev_priv, pipe);
6111
6112 /* Set up Tx target for periodic Rcomp update */
6113 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6114
6115 /* Disable target IRef on PLL */
6116 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6117 reg_val &= 0x00ffffff;
6118 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6119
6120 /* Disable fast lock */
6121 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6122
6123 /* Set idtafcrecal before PLL is enabled */
6124 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6125 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6126 mdiv |= ((bestn << DPIO_N_SHIFT));
6127 mdiv |= (1 << DPIO_K_SHIFT);
6128
6129 /*
6130 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6131 * but we don't support that).
6132 * Note: don't use the DAC post divider as it seems unstable.
6133 */
6134 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6135 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6136
6137 mdiv |= DPIO_ENABLE_CALIBRATION;
6138 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6139
6140 /* Set HBR and RBR LPF coefficients */
6141 if (pipe_config->port_clock == 162000 ||
6142 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6143 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6144 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6145 0x009f0003);
6146 else
6147 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6148 0x00d0000f);
6149
6150 if (pipe_config->has_dp_encoder) {
6151 /* Use SSC source */
6152 if (pipe == PIPE_A)
6153 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6154 0x0df40000);
6155 else
6156 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6157 0x0df70000);
6158 } else { /* HDMI or VGA */
6159 /* Use bend source */
6160 if (pipe == PIPE_A)
6161 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6162 0x0df70000);
6163 else
6164 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6165 0x0df40000);
6166 }
6167
6168 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6169 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6170 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6171 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6172 coreclk |= 0x01000000;
6173 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6174
6175 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6176 mutex_unlock(&dev_priv->dpio_lock);
6177 }
6178
6179 static void chv_update_pll(struct intel_crtc *crtc,
6180 struct intel_crtc_state *pipe_config)
6181 {
6182 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6183 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6184 DPLL_VCO_ENABLE;
6185 if (crtc->pipe != PIPE_A)
6186 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6187
6188 pipe_config->dpll_hw_state.dpll_md =
6189 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6190 }
6191
6192 static void chv_prepare_pll(struct intel_crtc *crtc,
6193 const struct intel_crtc_state *pipe_config)
6194 {
6195 struct drm_device *dev = crtc->base.dev;
6196 struct drm_i915_private *dev_priv = dev->dev_private;
6197 int pipe = crtc->pipe;
6198 int dpll_reg = DPLL(crtc->pipe);
6199 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6200 u32 loopfilter, tribuf_calcntr;
6201 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6202 u32 dpio_val;
6203 int vco;
6204
6205 bestn = pipe_config->dpll.n;
6206 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6207 bestm1 = pipe_config->dpll.m1;
6208 bestm2 = pipe_config->dpll.m2 >> 22;
6209 bestp1 = pipe_config->dpll.p1;
6210 bestp2 = pipe_config->dpll.p2;
6211 vco = pipe_config->dpll.vco;
6212 dpio_val = 0;
6213 loopfilter = 0;
6214
6215 /*
6216 * Enable Refclk and SSC
6217 */
6218 I915_WRITE(dpll_reg,
6219 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6220
6221 mutex_lock(&dev_priv->dpio_lock);
6222
6223 /* p1 and p2 divider */
6224 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6225 5 << DPIO_CHV_S1_DIV_SHIFT |
6226 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6227 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6228 1 << DPIO_CHV_K_DIV_SHIFT);
6229
6230 /* Feedback post-divider - m2 */
6231 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6232
6233 /* Feedback refclk divider - n and m1 */
6234 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6235 DPIO_CHV_M1_DIV_BY_2 |
6236 1 << DPIO_CHV_N_DIV_SHIFT);
6237
6238 /* M2 fraction division */
6239 if (bestm2_frac)
6240 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6241
6242 /* M2 fraction division enable */
6243 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6244 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6245 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6246 if (bestm2_frac)
6247 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6248 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6249
6250 /* Program digital lock detect threshold */
6251 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6252 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6253 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6254 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6255 if (!bestm2_frac)
6256 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6257 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6258
6259 /* Loop filter */
6260 if (vco == 5400000) {
6261 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6262 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6263 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6264 tribuf_calcntr = 0x9;
6265 } else if (vco <= 6200000) {
6266 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6267 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6268 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6269 tribuf_calcntr = 0x9;
6270 } else if (vco <= 6480000) {
6271 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6272 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6273 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6274 tribuf_calcntr = 0x8;
6275 } else {
6276 /* Not supported. Apply the same limits as in the max case */
6277 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6278 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6279 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6280 tribuf_calcntr = 0;
6281 }
6282 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6283
6284 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(pipe));
6285 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6286 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6287 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6288
6289 /* AFC Recal */
6290 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6291 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6292 DPIO_AFC_RECAL);
6293
6294 mutex_unlock(&dev_priv->dpio_lock);
6295 }
6296
6297 /**
6298 * vlv_force_pll_on - forcibly enable just the PLL
6299 * @dev_priv: i915 private structure
6300 * @pipe: pipe PLL to enable
6301 * @dpll: PLL configuration
6302 *
6303 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6304 * in cases where we need the PLL enabled even when @pipe is not going to
6305 * be enabled.
6306 */
6307 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6308 const struct dpll *dpll)
6309 {
6310 struct intel_crtc *crtc =
6311 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6312 struct intel_crtc_state pipe_config = {
6313 .pixel_multiplier = 1,
6314 .dpll = *dpll,
6315 };
6316
6317 if (IS_CHERRYVIEW(dev)) {
6318 chv_update_pll(crtc, &pipe_config);
6319 chv_prepare_pll(crtc, &pipe_config);
6320 chv_enable_pll(crtc, &pipe_config);
6321 } else {
6322 vlv_update_pll(crtc, &pipe_config);
6323 vlv_prepare_pll(crtc, &pipe_config);
6324 vlv_enable_pll(crtc, &pipe_config);
6325 }
6326 }
6327
6328 /**
6329 * vlv_force_pll_off - forcibly disable just the PLL
6330 * @dev_priv: i915 private structure
6331 * @pipe: pipe PLL to disable
6332 *
6333 * Disable the PLL for @pipe. To be used in cases where we need
6334 * the PLL enabled even when @pipe is not going to be enabled.
6335 */
6336 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6337 {
6338 if (IS_CHERRYVIEW(dev))
6339 chv_disable_pll(to_i915(dev), pipe);
6340 else
6341 vlv_disable_pll(to_i915(dev), pipe);
6342 }
6343
6344 static void i9xx_update_pll(struct intel_crtc *crtc,
6345 struct intel_crtc_state *crtc_state,
6346 intel_clock_t *reduced_clock,
6347 int num_connectors)
6348 {
6349 struct drm_device *dev = crtc->base.dev;
6350 struct drm_i915_private *dev_priv = dev->dev_private;
6351 u32 dpll;
6352 bool is_sdvo;
6353 struct dpll *clock = &crtc_state->dpll;
6354
6355 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6356
6357 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6358 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6359
6360 dpll = DPLL_VGA_MODE_DIS;
6361
6362 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6363 dpll |= DPLLB_MODE_LVDS;
6364 else
6365 dpll |= DPLLB_MODE_DAC_SERIAL;
6366
6367 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6368 dpll |= (crtc_state->pixel_multiplier - 1)
6369 << SDVO_MULTIPLIER_SHIFT_HIRES;
6370 }
6371
6372 if (is_sdvo)
6373 dpll |= DPLL_SDVO_HIGH_SPEED;
6374
6375 if (crtc_state->has_dp_encoder)
6376 dpll |= DPLL_SDVO_HIGH_SPEED;
6377
6378 /* compute bitmask from p1 value */
6379 if (IS_PINEVIEW(dev))
6380 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6381 else {
6382 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6383 if (IS_G4X(dev) && reduced_clock)
6384 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6385 }
6386 switch (clock->p2) {
6387 case 5:
6388 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6389 break;
6390 case 7:
6391 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6392 break;
6393 case 10:
6394 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6395 break;
6396 case 14:
6397 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6398 break;
6399 }
6400 if (INTEL_INFO(dev)->gen >= 4)
6401 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6402
6403 if (crtc_state->sdvo_tv_clock)
6404 dpll |= PLL_REF_INPUT_TVCLKINBC;
6405 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6406 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6407 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6408 else
6409 dpll |= PLL_REF_INPUT_DREFCLK;
6410
6411 dpll |= DPLL_VCO_ENABLE;
6412 crtc_state->dpll_hw_state.dpll = dpll;
6413
6414 if (INTEL_INFO(dev)->gen >= 4) {
6415 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6416 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6417 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6418 }
6419 }
6420
6421 static void i8xx_update_pll(struct intel_crtc *crtc,
6422 struct intel_crtc_state *crtc_state,
6423 intel_clock_t *reduced_clock,
6424 int num_connectors)
6425 {
6426 struct drm_device *dev = crtc->base.dev;
6427 struct drm_i915_private *dev_priv = dev->dev_private;
6428 u32 dpll;
6429 struct dpll *clock = &crtc_state->dpll;
6430
6431 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6432
6433 dpll = DPLL_VGA_MODE_DIS;
6434
6435 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6436 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6437 } else {
6438 if (clock->p1 == 2)
6439 dpll |= PLL_P1_DIVIDE_BY_TWO;
6440 else
6441 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6442 if (clock->p2 == 4)
6443 dpll |= PLL_P2_DIVIDE_BY_4;
6444 }
6445
6446 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6447 dpll |= DPLL_DVO_2X_MODE;
6448
6449 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6450 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6451 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6452 else
6453 dpll |= PLL_REF_INPUT_DREFCLK;
6454
6455 dpll |= DPLL_VCO_ENABLE;
6456 crtc_state->dpll_hw_state.dpll = dpll;
6457 }
6458
6459 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6460 {
6461 struct drm_device *dev = intel_crtc->base.dev;
6462 struct drm_i915_private *dev_priv = dev->dev_private;
6463 enum pipe pipe = intel_crtc->pipe;
6464 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6465 struct drm_display_mode *adjusted_mode =
6466 &intel_crtc->config->base.adjusted_mode;
6467 uint32_t crtc_vtotal, crtc_vblank_end;
6468 int vsyncshift = 0;
6469
6470 /* We need to be careful not to changed the adjusted mode, for otherwise
6471 * the hw state checker will get angry at the mismatch. */
6472 crtc_vtotal = adjusted_mode->crtc_vtotal;
6473 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6474
6475 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6476 /* the chip adds 2 halflines automatically */
6477 crtc_vtotal -= 1;
6478 crtc_vblank_end -= 1;
6479
6480 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6481 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6482 else
6483 vsyncshift = adjusted_mode->crtc_hsync_start -
6484 adjusted_mode->crtc_htotal / 2;
6485 if (vsyncshift < 0)
6486 vsyncshift += adjusted_mode->crtc_htotal;
6487 }
6488
6489 if (INTEL_INFO(dev)->gen > 3)
6490 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6491
6492 I915_WRITE(HTOTAL(cpu_transcoder),
6493 (adjusted_mode->crtc_hdisplay - 1) |
6494 ((adjusted_mode->crtc_htotal - 1) << 16));
6495 I915_WRITE(HBLANK(cpu_transcoder),
6496 (adjusted_mode->crtc_hblank_start - 1) |
6497 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6498 I915_WRITE(HSYNC(cpu_transcoder),
6499 (adjusted_mode->crtc_hsync_start - 1) |
6500 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6501
6502 I915_WRITE(VTOTAL(cpu_transcoder),
6503 (adjusted_mode->crtc_vdisplay - 1) |
6504 ((crtc_vtotal - 1) << 16));
6505 I915_WRITE(VBLANK(cpu_transcoder),
6506 (adjusted_mode->crtc_vblank_start - 1) |
6507 ((crtc_vblank_end - 1) << 16));
6508 I915_WRITE(VSYNC(cpu_transcoder),
6509 (adjusted_mode->crtc_vsync_start - 1) |
6510 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6511
6512 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6513 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6514 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6515 * bits. */
6516 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6517 (pipe == PIPE_B || pipe == PIPE_C))
6518 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6519
6520 /* pipesrc controls the size that is scaled from, which should
6521 * always be the user's requested size.
6522 */
6523 I915_WRITE(PIPESRC(pipe),
6524 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6525 (intel_crtc->config->pipe_src_h - 1));
6526 }
6527
6528 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6529 struct intel_crtc_state *pipe_config)
6530 {
6531 struct drm_device *dev = crtc->base.dev;
6532 struct drm_i915_private *dev_priv = dev->dev_private;
6533 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6534 uint32_t tmp;
6535
6536 tmp = I915_READ(HTOTAL(cpu_transcoder));
6537 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6538 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6539 tmp = I915_READ(HBLANK(cpu_transcoder));
6540 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6541 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6542 tmp = I915_READ(HSYNC(cpu_transcoder));
6543 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6544 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6545
6546 tmp = I915_READ(VTOTAL(cpu_transcoder));
6547 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6548 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6549 tmp = I915_READ(VBLANK(cpu_transcoder));
6550 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6551 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6552 tmp = I915_READ(VSYNC(cpu_transcoder));
6553 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6554 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6555
6556 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6557 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6558 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6559 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6560 }
6561
6562 tmp = I915_READ(PIPESRC(crtc->pipe));
6563 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6564 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6565
6566 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6567 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6568 }
6569
6570 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6571 struct intel_crtc_state *pipe_config)
6572 {
6573 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6574 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6575 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6576 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6577
6578 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6579 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6580 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6581 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6582
6583 mode->flags = pipe_config->base.adjusted_mode.flags;
6584
6585 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6586 mode->flags |= pipe_config->base.adjusted_mode.flags;
6587 }
6588
6589 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6590 {
6591 struct drm_device *dev = intel_crtc->base.dev;
6592 struct drm_i915_private *dev_priv = dev->dev_private;
6593 uint32_t pipeconf;
6594
6595 pipeconf = 0;
6596
6597 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6598 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6599 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6600
6601 if (intel_crtc->config->double_wide)
6602 pipeconf |= PIPECONF_DOUBLE_WIDE;
6603
6604 /* only g4x and later have fancy bpc/dither controls */
6605 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6606 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6607 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6608 pipeconf |= PIPECONF_DITHER_EN |
6609 PIPECONF_DITHER_TYPE_SP;
6610
6611 switch (intel_crtc->config->pipe_bpp) {
6612 case 18:
6613 pipeconf |= PIPECONF_6BPC;
6614 break;
6615 case 24:
6616 pipeconf |= PIPECONF_8BPC;
6617 break;
6618 case 30:
6619 pipeconf |= PIPECONF_10BPC;
6620 break;
6621 default:
6622 /* Case prevented by intel_choose_pipe_bpp_dither. */
6623 BUG();
6624 }
6625 }
6626
6627 if (HAS_PIPE_CXSR(dev)) {
6628 if (intel_crtc->lowfreq_avail) {
6629 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6630 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6631 } else {
6632 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6633 }
6634 }
6635
6636 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6637 if (INTEL_INFO(dev)->gen < 4 ||
6638 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6639 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6640 else
6641 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6642 } else
6643 pipeconf |= PIPECONF_PROGRESSIVE;
6644
6645 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6646 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6647
6648 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6649 POSTING_READ(PIPECONF(intel_crtc->pipe));
6650 }
6651
6652 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6653 struct intel_crtc_state *crtc_state)
6654 {
6655 struct drm_device *dev = crtc->base.dev;
6656 struct drm_i915_private *dev_priv = dev->dev_private;
6657 int refclk, num_connectors = 0;
6658 intel_clock_t clock, reduced_clock;
6659 bool ok, has_reduced_clock = false;
6660 bool is_lvds = false, is_dsi = false;
6661 struct intel_encoder *encoder;
6662 const intel_limit_t *limit;
6663
6664 for_each_intel_encoder(dev, encoder) {
6665 if (encoder->new_crtc != crtc)
6666 continue;
6667
6668 switch (encoder->type) {
6669 case INTEL_OUTPUT_LVDS:
6670 is_lvds = true;
6671 break;
6672 case INTEL_OUTPUT_DSI:
6673 is_dsi = true;
6674 break;
6675 default:
6676 break;
6677 }
6678
6679 num_connectors++;
6680 }
6681
6682 if (is_dsi)
6683 return 0;
6684
6685 if (!crtc_state->clock_set) {
6686 refclk = i9xx_get_refclk(crtc, num_connectors);
6687
6688 /*
6689 * Returns a set of divisors for the desired target clock with
6690 * the given refclk, or FALSE. The returned values represent
6691 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6692 * 2) / p1 / p2.
6693 */
6694 limit = intel_limit(crtc, refclk);
6695 ok = dev_priv->display.find_dpll(limit, crtc,
6696 crtc_state->port_clock,
6697 refclk, NULL, &clock);
6698 if (!ok) {
6699 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6700 return -EINVAL;
6701 }
6702
6703 if (is_lvds && dev_priv->lvds_downclock_avail) {
6704 /*
6705 * Ensure we match the reduced clock's P to the target
6706 * clock. If the clocks don't match, we can't switch
6707 * the display clock by using the FP0/FP1. In such case
6708 * we will disable the LVDS downclock feature.
6709 */
6710 has_reduced_clock =
6711 dev_priv->display.find_dpll(limit, crtc,
6712 dev_priv->lvds_downclock,
6713 refclk, &clock,
6714 &reduced_clock);
6715 }
6716 /* Compat-code for transition, will disappear. */
6717 crtc_state->dpll.n = clock.n;
6718 crtc_state->dpll.m1 = clock.m1;
6719 crtc_state->dpll.m2 = clock.m2;
6720 crtc_state->dpll.p1 = clock.p1;
6721 crtc_state->dpll.p2 = clock.p2;
6722 }
6723
6724 if (IS_GEN2(dev)) {
6725 i8xx_update_pll(crtc, crtc_state,
6726 has_reduced_clock ? &reduced_clock : NULL,
6727 num_connectors);
6728 } else if (IS_CHERRYVIEW(dev)) {
6729 chv_update_pll(crtc, crtc_state);
6730 } else if (IS_VALLEYVIEW(dev)) {
6731 vlv_update_pll(crtc, crtc_state);
6732 } else {
6733 i9xx_update_pll(crtc, crtc_state,
6734 has_reduced_clock ? &reduced_clock : NULL,
6735 num_connectors);
6736 }
6737
6738 return 0;
6739 }
6740
6741 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6742 struct intel_crtc_state *pipe_config)
6743 {
6744 struct drm_device *dev = crtc->base.dev;
6745 struct drm_i915_private *dev_priv = dev->dev_private;
6746 uint32_t tmp;
6747
6748 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6749 return;
6750
6751 tmp = I915_READ(PFIT_CONTROL);
6752 if (!(tmp & PFIT_ENABLE))
6753 return;
6754
6755 /* Check whether the pfit is attached to our pipe. */
6756 if (INTEL_INFO(dev)->gen < 4) {
6757 if (crtc->pipe != PIPE_B)
6758 return;
6759 } else {
6760 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6761 return;
6762 }
6763
6764 pipe_config->gmch_pfit.control = tmp;
6765 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6766 if (INTEL_INFO(dev)->gen < 5)
6767 pipe_config->gmch_pfit.lvds_border_bits =
6768 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6769 }
6770
6771 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6772 struct intel_crtc_state *pipe_config)
6773 {
6774 struct drm_device *dev = crtc->base.dev;
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 int pipe = pipe_config->cpu_transcoder;
6777 intel_clock_t clock;
6778 u32 mdiv;
6779 int refclk = 100000;
6780
6781 /* In case of MIPI DPLL will not even be used */
6782 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6783 return;
6784
6785 mutex_lock(&dev_priv->dpio_lock);
6786 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6787 mutex_unlock(&dev_priv->dpio_lock);
6788
6789 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6790 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6791 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6792 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6793 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6794
6795 vlv_clock(refclk, &clock);
6796
6797 /* clock.dot is the fast clock */
6798 pipe_config->port_clock = clock.dot / 5;
6799 }
6800
6801 static void
6802 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6803 struct intel_initial_plane_config *plane_config)
6804 {
6805 struct drm_device *dev = crtc->base.dev;
6806 struct drm_i915_private *dev_priv = dev->dev_private;
6807 u32 val, base, offset;
6808 int pipe = crtc->pipe, plane = crtc->plane;
6809 int fourcc, pixel_format;
6810 int aligned_height;
6811 struct drm_framebuffer *fb;
6812 struct intel_framebuffer *intel_fb;
6813
6814 val = I915_READ(DSPCNTR(plane));
6815 if (!(val & DISPLAY_PLANE_ENABLE))
6816 return;
6817
6818 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6819 if (!intel_fb) {
6820 DRM_DEBUG_KMS("failed to alloc fb\n");
6821 return;
6822 }
6823
6824 fb = &intel_fb->base;
6825
6826 if (INTEL_INFO(dev)->gen >= 4) {
6827 if (val & DISPPLANE_TILED) {
6828 plane_config->tiling = I915_TILING_X;
6829 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6830 }
6831 }
6832
6833 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6834 fourcc = i9xx_format_to_fourcc(pixel_format);
6835 fb->pixel_format = fourcc;
6836 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6837
6838 if (INTEL_INFO(dev)->gen >= 4) {
6839 if (plane_config->tiling)
6840 offset = I915_READ(DSPTILEOFF(plane));
6841 else
6842 offset = I915_READ(DSPLINOFF(plane));
6843 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6844 } else {
6845 base = I915_READ(DSPADDR(plane));
6846 }
6847 plane_config->base = base;
6848
6849 val = I915_READ(PIPESRC(pipe));
6850 fb->width = ((val >> 16) & 0xfff) + 1;
6851 fb->height = ((val >> 0) & 0xfff) + 1;
6852
6853 val = I915_READ(DSPSTRIDE(pipe));
6854 fb->pitches[0] = val & 0xffffffc0;
6855
6856 aligned_height = intel_fb_align_height(dev, fb->height,
6857 fb->pixel_format,
6858 fb->modifier[0]);
6859
6860 plane_config->size = fb->pitches[0] * aligned_height;
6861
6862 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6863 pipe_name(pipe), plane, fb->width, fb->height,
6864 fb->bits_per_pixel, base, fb->pitches[0],
6865 plane_config->size);
6866
6867 plane_config->fb = intel_fb;
6868 }
6869
6870 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6871 struct intel_crtc_state *pipe_config)
6872 {
6873 struct drm_device *dev = crtc->base.dev;
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875 int pipe = pipe_config->cpu_transcoder;
6876 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6877 intel_clock_t clock;
6878 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6879 int refclk = 100000;
6880
6881 mutex_lock(&dev_priv->dpio_lock);
6882 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6883 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6884 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6885 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6886 mutex_unlock(&dev_priv->dpio_lock);
6887
6888 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6889 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6890 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6891 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6892 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6893
6894 chv_clock(refclk, &clock);
6895
6896 /* clock.dot is the fast clock */
6897 pipe_config->port_clock = clock.dot / 5;
6898 }
6899
6900 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6901 struct intel_crtc_state *pipe_config)
6902 {
6903 struct drm_device *dev = crtc->base.dev;
6904 struct drm_i915_private *dev_priv = dev->dev_private;
6905 uint32_t tmp;
6906
6907 if (!intel_display_power_is_enabled(dev_priv,
6908 POWER_DOMAIN_PIPE(crtc->pipe)))
6909 return false;
6910
6911 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6912 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6913
6914 tmp = I915_READ(PIPECONF(crtc->pipe));
6915 if (!(tmp & PIPECONF_ENABLE))
6916 return false;
6917
6918 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6919 switch (tmp & PIPECONF_BPC_MASK) {
6920 case PIPECONF_6BPC:
6921 pipe_config->pipe_bpp = 18;
6922 break;
6923 case PIPECONF_8BPC:
6924 pipe_config->pipe_bpp = 24;
6925 break;
6926 case PIPECONF_10BPC:
6927 pipe_config->pipe_bpp = 30;
6928 break;
6929 default:
6930 break;
6931 }
6932 }
6933
6934 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6935 pipe_config->limited_color_range = true;
6936
6937 if (INTEL_INFO(dev)->gen < 4)
6938 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6939
6940 intel_get_pipe_timings(crtc, pipe_config);
6941
6942 i9xx_get_pfit_config(crtc, pipe_config);
6943
6944 if (INTEL_INFO(dev)->gen >= 4) {
6945 tmp = I915_READ(DPLL_MD(crtc->pipe));
6946 pipe_config->pixel_multiplier =
6947 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6948 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6949 pipe_config->dpll_hw_state.dpll_md = tmp;
6950 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6951 tmp = I915_READ(DPLL(crtc->pipe));
6952 pipe_config->pixel_multiplier =
6953 ((tmp & SDVO_MULTIPLIER_MASK)
6954 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6955 } else {
6956 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6957 * port and will be fixed up in the encoder->get_config
6958 * function. */
6959 pipe_config->pixel_multiplier = 1;
6960 }
6961 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6962 if (!IS_VALLEYVIEW(dev)) {
6963 /*
6964 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6965 * on 830. Filter it out here so that we don't
6966 * report errors due to that.
6967 */
6968 if (IS_I830(dev))
6969 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6970
6971 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6972 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6973 } else {
6974 /* Mask out read-only status bits. */
6975 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6976 DPLL_PORTC_READY_MASK |
6977 DPLL_PORTB_READY_MASK);
6978 }
6979
6980 if (IS_CHERRYVIEW(dev))
6981 chv_crtc_clock_get(crtc, pipe_config);
6982 else if (IS_VALLEYVIEW(dev))
6983 vlv_crtc_clock_get(crtc, pipe_config);
6984 else
6985 i9xx_crtc_clock_get(crtc, pipe_config);
6986
6987 return true;
6988 }
6989
6990 static void ironlake_init_pch_refclk(struct drm_device *dev)
6991 {
6992 struct drm_i915_private *dev_priv = dev->dev_private;
6993 struct intel_encoder *encoder;
6994 u32 val, final;
6995 bool has_lvds = false;
6996 bool has_cpu_edp = false;
6997 bool has_panel = false;
6998 bool has_ck505 = false;
6999 bool can_ssc = false;
7000
7001 /* We need to take the global config into account */
7002 for_each_intel_encoder(dev, encoder) {
7003 switch (encoder->type) {
7004 case INTEL_OUTPUT_LVDS:
7005 has_panel = true;
7006 has_lvds = true;
7007 break;
7008 case INTEL_OUTPUT_EDP:
7009 has_panel = true;
7010 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7011 has_cpu_edp = true;
7012 break;
7013 default:
7014 break;
7015 }
7016 }
7017
7018 if (HAS_PCH_IBX(dev)) {
7019 has_ck505 = dev_priv->vbt.display_clock_mode;
7020 can_ssc = has_ck505;
7021 } else {
7022 has_ck505 = false;
7023 can_ssc = true;
7024 }
7025
7026 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7027 has_panel, has_lvds, has_ck505);
7028
7029 /* Ironlake: try to setup display ref clock before DPLL
7030 * enabling. This is only under driver's control after
7031 * PCH B stepping, previous chipset stepping should be
7032 * ignoring this setting.
7033 */
7034 val = I915_READ(PCH_DREF_CONTROL);
7035
7036 /* As we must carefully and slowly disable/enable each source in turn,
7037 * compute the final state we want first and check if we need to
7038 * make any changes at all.
7039 */
7040 final = val;
7041 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7042 if (has_ck505)
7043 final |= DREF_NONSPREAD_CK505_ENABLE;
7044 else
7045 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7046
7047 final &= ~DREF_SSC_SOURCE_MASK;
7048 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7049 final &= ~DREF_SSC1_ENABLE;
7050
7051 if (has_panel) {
7052 final |= DREF_SSC_SOURCE_ENABLE;
7053
7054 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7055 final |= DREF_SSC1_ENABLE;
7056
7057 if (has_cpu_edp) {
7058 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7059 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7060 else
7061 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7062 } else
7063 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7064 } else {
7065 final |= DREF_SSC_SOURCE_DISABLE;
7066 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7067 }
7068
7069 if (final == val)
7070 return;
7071
7072 /* Always enable nonspread source */
7073 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7074
7075 if (has_ck505)
7076 val |= DREF_NONSPREAD_CK505_ENABLE;
7077 else
7078 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7079
7080 if (has_panel) {
7081 val &= ~DREF_SSC_SOURCE_MASK;
7082 val |= DREF_SSC_SOURCE_ENABLE;
7083
7084 /* SSC must be turned on before enabling the CPU output */
7085 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7086 DRM_DEBUG_KMS("Using SSC on panel\n");
7087 val |= DREF_SSC1_ENABLE;
7088 } else
7089 val &= ~DREF_SSC1_ENABLE;
7090
7091 /* Get SSC going before enabling the outputs */
7092 I915_WRITE(PCH_DREF_CONTROL, val);
7093 POSTING_READ(PCH_DREF_CONTROL);
7094 udelay(200);
7095
7096 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7097
7098 /* Enable CPU source on CPU attached eDP */
7099 if (has_cpu_edp) {
7100 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7101 DRM_DEBUG_KMS("Using SSC on eDP\n");
7102 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7103 } else
7104 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7105 } else
7106 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7107
7108 I915_WRITE(PCH_DREF_CONTROL, val);
7109 POSTING_READ(PCH_DREF_CONTROL);
7110 udelay(200);
7111 } else {
7112 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7113
7114 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7115
7116 /* Turn off CPU output */
7117 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7118
7119 I915_WRITE(PCH_DREF_CONTROL, val);
7120 POSTING_READ(PCH_DREF_CONTROL);
7121 udelay(200);
7122
7123 /* Turn off the SSC source */
7124 val &= ~DREF_SSC_SOURCE_MASK;
7125 val |= DREF_SSC_SOURCE_DISABLE;
7126
7127 /* Turn off SSC1 */
7128 val &= ~DREF_SSC1_ENABLE;
7129
7130 I915_WRITE(PCH_DREF_CONTROL, val);
7131 POSTING_READ(PCH_DREF_CONTROL);
7132 udelay(200);
7133 }
7134
7135 BUG_ON(val != final);
7136 }
7137
7138 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7139 {
7140 uint32_t tmp;
7141
7142 tmp = I915_READ(SOUTH_CHICKEN2);
7143 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7144 I915_WRITE(SOUTH_CHICKEN2, tmp);
7145
7146 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7147 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7148 DRM_ERROR("FDI mPHY reset assert timeout\n");
7149
7150 tmp = I915_READ(SOUTH_CHICKEN2);
7151 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7152 I915_WRITE(SOUTH_CHICKEN2, tmp);
7153
7154 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7155 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7156 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7157 }
7158
7159 /* WaMPhyProgramming:hsw */
7160 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7161 {
7162 uint32_t tmp;
7163
7164 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7165 tmp &= ~(0xFF << 24);
7166 tmp |= (0x12 << 24);
7167 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7168
7169 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7170 tmp |= (1 << 11);
7171 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7172
7173 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7174 tmp |= (1 << 11);
7175 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7176
7177 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7178 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7179 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7180
7181 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7182 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7183 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7184
7185 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7186 tmp &= ~(7 << 13);
7187 tmp |= (5 << 13);
7188 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7189
7190 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7191 tmp &= ~(7 << 13);
7192 tmp |= (5 << 13);
7193 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7194
7195 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7196 tmp &= ~0xFF;
7197 tmp |= 0x1C;
7198 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7199
7200 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7201 tmp &= ~0xFF;
7202 tmp |= 0x1C;
7203 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7204
7205 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7206 tmp &= ~(0xFF << 16);
7207 tmp |= (0x1C << 16);
7208 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7209
7210 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7211 tmp &= ~(0xFF << 16);
7212 tmp |= (0x1C << 16);
7213 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7214
7215 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7216 tmp |= (1 << 27);
7217 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7218
7219 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7220 tmp |= (1 << 27);
7221 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7222
7223 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7224 tmp &= ~(0xF << 28);
7225 tmp |= (4 << 28);
7226 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7227
7228 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7229 tmp &= ~(0xF << 28);
7230 tmp |= (4 << 28);
7231 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7232 }
7233
7234 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7235 * Programming" based on the parameters passed:
7236 * - Sequence to enable CLKOUT_DP
7237 * - Sequence to enable CLKOUT_DP without spread
7238 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7239 */
7240 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7241 bool with_fdi)
7242 {
7243 struct drm_i915_private *dev_priv = dev->dev_private;
7244 uint32_t reg, tmp;
7245
7246 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7247 with_spread = true;
7248 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7249 with_fdi, "LP PCH doesn't have FDI\n"))
7250 with_fdi = false;
7251
7252 mutex_lock(&dev_priv->dpio_lock);
7253
7254 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7255 tmp &= ~SBI_SSCCTL_DISABLE;
7256 tmp |= SBI_SSCCTL_PATHALT;
7257 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7258
7259 udelay(24);
7260
7261 if (with_spread) {
7262 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7263 tmp &= ~SBI_SSCCTL_PATHALT;
7264 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7265
7266 if (with_fdi) {
7267 lpt_reset_fdi_mphy(dev_priv);
7268 lpt_program_fdi_mphy(dev_priv);
7269 }
7270 }
7271
7272 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7273 SBI_GEN0 : SBI_DBUFF0;
7274 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7275 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7276 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7277
7278 mutex_unlock(&dev_priv->dpio_lock);
7279 }
7280
7281 /* Sequence to disable CLKOUT_DP */
7282 static void lpt_disable_clkout_dp(struct drm_device *dev)
7283 {
7284 struct drm_i915_private *dev_priv = dev->dev_private;
7285 uint32_t reg, tmp;
7286
7287 mutex_lock(&dev_priv->dpio_lock);
7288
7289 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7290 SBI_GEN0 : SBI_DBUFF0;
7291 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7292 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7293 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7294
7295 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7296 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7297 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7298 tmp |= SBI_SSCCTL_PATHALT;
7299 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7300 udelay(32);
7301 }
7302 tmp |= SBI_SSCCTL_DISABLE;
7303 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7304 }
7305
7306 mutex_unlock(&dev_priv->dpio_lock);
7307 }
7308
7309 static void lpt_init_pch_refclk(struct drm_device *dev)
7310 {
7311 struct intel_encoder *encoder;
7312 bool has_vga = false;
7313
7314 for_each_intel_encoder(dev, encoder) {
7315 switch (encoder->type) {
7316 case INTEL_OUTPUT_ANALOG:
7317 has_vga = true;
7318 break;
7319 default:
7320 break;
7321 }
7322 }
7323
7324 if (has_vga)
7325 lpt_enable_clkout_dp(dev, true, true);
7326 else
7327 lpt_disable_clkout_dp(dev);
7328 }
7329
7330 /*
7331 * Initialize reference clocks when the driver loads
7332 */
7333 void intel_init_pch_refclk(struct drm_device *dev)
7334 {
7335 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7336 ironlake_init_pch_refclk(dev);
7337 else if (HAS_PCH_LPT(dev))
7338 lpt_init_pch_refclk(dev);
7339 }
7340
7341 static int ironlake_get_refclk(struct drm_crtc *crtc)
7342 {
7343 struct drm_device *dev = crtc->dev;
7344 struct drm_i915_private *dev_priv = dev->dev_private;
7345 struct intel_encoder *encoder;
7346 int num_connectors = 0;
7347 bool is_lvds = false;
7348
7349 for_each_intel_encoder(dev, encoder) {
7350 if (encoder->new_crtc != to_intel_crtc(crtc))
7351 continue;
7352
7353 switch (encoder->type) {
7354 case INTEL_OUTPUT_LVDS:
7355 is_lvds = true;
7356 break;
7357 default:
7358 break;
7359 }
7360 num_connectors++;
7361 }
7362
7363 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7364 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7365 dev_priv->vbt.lvds_ssc_freq);
7366 return dev_priv->vbt.lvds_ssc_freq;
7367 }
7368
7369 return 120000;
7370 }
7371
7372 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7373 {
7374 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7376 int pipe = intel_crtc->pipe;
7377 uint32_t val;
7378
7379 val = 0;
7380
7381 switch (intel_crtc->config->pipe_bpp) {
7382 case 18:
7383 val |= PIPECONF_6BPC;
7384 break;
7385 case 24:
7386 val |= PIPECONF_8BPC;
7387 break;
7388 case 30:
7389 val |= PIPECONF_10BPC;
7390 break;
7391 case 36:
7392 val |= PIPECONF_12BPC;
7393 break;
7394 default:
7395 /* Case prevented by intel_choose_pipe_bpp_dither. */
7396 BUG();
7397 }
7398
7399 if (intel_crtc->config->dither)
7400 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7401
7402 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7403 val |= PIPECONF_INTERLACED_ILK;
7404 else
7405 val |= PIPECONF_PROGRESSIVE;
7406
7407 if (intel_crtc->config->limited_color_range)
7408 val |= PIPECONF_COLOR_RANGE_SELECT;
7409
7410 I915_WRITE(PIPECONF(pipe), val);
7411 POSTING_READ(PIPECONF(pipe));
7412 }
7413
7414 /*
7415 * Set up the pipe CSC unit.
7416 *
7417 * Currently only full range RGB to limited range RGB conversion
7418 * is supported, but eventually this should handle various
7419 * RGB<->YCbCr scenarios as well.
7420 */
7421 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7422 {
7423 struct drm_device *dev = crtc->dev;
7424 struct drm_i915_private *dev_priv = dev->dev_private;
7425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7426 int pipe = intel_crtc->pipe;
7427 uint16_t coeff = 0x7800; /* 1.0 */
7428
7429 /*
7430 * TODO: Check what kind of values actually come out of the pipe
7431 * with these coeff/postoff values and adjust to get the best
7432 * accuracy. Perhaps we even need to take the bpc value into
7433 * consideration.
7434 */
7435
7436 if (intel_crtc->config->limited_color_range)
7437 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7438
7439 /*
7440 * GY/GU and RY/RU should be the other way around according
7441 * to BSpec, but reality doesn't agree. Just set them up in
7442 * a way that results in the correct picture.
7443 */
7444 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7445 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7446
7447 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7448 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7449
7450 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7451 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7452
7453 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7454 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7455 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7456
7457 if (INTEL_INFO(dev)->gen > 6) {
7458 uint16_t postoff = 0;
7459
7460 if (intel_crtc->config->limited_color_range)
7461 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7462
7463 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7464 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7465 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7466
7467 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7468 } else {
7469 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7470
7471 if (intel_crtc->config->limited_color_range)
7472 mode |= CSC_BLACK_SCREEN_OFFSET;
7473
7474 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7475 }
7476 }
7477
7478 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7479 {
7480 struct drm_device *dev = crtc->dev;
7481 struct drm_i915_private *dev_priv = dev->dev_private;
7482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7483 enum pipe pipe = intel_crtc->pipe;
7484 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7485 uint32_t val;
7486
7487 val = 0;
7488
7489 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7490 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7491
7492 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7493 val |= PIPECONF_INTERLACED_ILK;
7494 else
7495 val |= PIPECONF_PROGRESSIVE;
7496
7497 I915_WRITE(PIPECONF(cpu_transcoder), val);
7498 POSTING_READ(PIPECONF(cpu_transcoder));
7499
7500 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7501 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7502
7503 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7504 val = 0;
7505
7506 switch (intel_crtc->config->pipe_bpp) {
7507 case 18:
7508 val |= PIPEMISC_DITHER_6_BPC;
7509 break;
7510 case 24:
7511 val |= PIPEMISC_DITHER_8_BPC;
7512 break;
7513 case 30:
7514 val |= PIPEMISC_DITHER_10_BPC;
7515 break;
7516 case 36:
7517 val |= PIPEMISC_DITHER_12_BPC;
7518 break;
7519 default:
7520 /* Case prevented by pipe_config_set_bpp. */
7521 BUG();
7522 }
7523
7524 if (intel_crtc->config->dither)
7525 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7526
7527 I915_WRITE(PIPEMISC(pipe), val);
7528 }
7529 }
7530
7531 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7532 struct intel_crtc_state *crtc_state,
7533 intel_clock_t *clock,
7534 bool *has_reduced_clock,
7535 intel_clock_t *reduced_clock)
7536 {
7537 struct drm_device *dev = crtc->dev;
7538 struct drm_i915_private *dev_priv = dev->dev_private;
7539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7540 int refclk;
7541 const intel_limit_t *limit;
7542 bool ret, is_lvds = false;
7543
7544 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7545
7546 refclk = ironlake_get_refclk(crtc);
7547
7548 /*
7549 * Returns a set of divisors for the desired target clock with the given
7550 * refclk, or FALSE. The returned values represent the clock equation:
7551 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7552 */
7553 limit = intel_limit(intel_crtc, refclk);
7554 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7555 crtc_state->port_clock,
7556 refclk, NULL, clock);
7557 if (!ret)
7558 return false;
7559
7560 if (is_lvds && dev_priv->lvds_downclock_avail) {
7561 /*
7562 * Ensure we match the reduced clock's P to the target clock.
7563 * If the clocks don't match, we can't switch the display clock
7564 * by using the FP0/FP1. In such case we will disable the LVDS
7565 * downclock feature.
7566 */
7567 *has_reduced_clock =
7568 dev_priv->display.find_dpll(limit, intel_crtc,
7569 dev_priv->lvds_downclock,
7570 refclk, clock,
7571 reduced_clock);
7572 }
7573
7574 return true;
7575 }
7576
7577 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7578 {
7579 /*
7580 * Account for spread spectrum to avoid
7581 * oversubscribing the link. Max center spread
7582 * is 2.5%; use 5% for safety's sake.
7583 */
7584 u32 bps = target_clock * bpp * 21 / 20;
7585 return DIV_ROUND_UP(bps, link_bw * 8);
7586 }
7587
7588 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7589 {
7590 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7591 }
7592
7593 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7594 struct intel_crtc_state *crtc_state,
7595 u32 *fp,
7596 intel_clock_t *reduced_clock, u32 *fp2)
7597 {
7598 struct drm_crtc *crtc = &intel_crtc->base;
7599 struct drm_device *dev = crtc->dev;
7600 struct drm_i915_private *dev_priv = dev->dev_private;
7601 struct intel_encoder *intel_encoder;
7602 uint32_t dpll;
7603 int factor, num_connectors = 0;
7604 bool is_lvds = false, is_sdvo = false;
7605
7606 for_each_intel_encoder(dev, intel_encoder) {
7607 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7608 continue;
7609
7610 switch (intel_encoder->type) {
7611 case INTEL_OUTPUT_LVDS:
7612 is_lvds = true;
7613 break;
7614 case INTEL_OUTPUT_SDVO:
7615 case INTEL_OUTPUT_HDMI:
7616 is_sdvo = true;
7617 break;
7618 default:
7619 break;
7620 }
7621
7622 num_connectors++;
7623 }
7624
7625 /* Enable autotuning of the PLL clock (if permissible) */
7626 factor = 21;
7627 if (is_lvds) {
7628 if ((intel_panel_use_ssc(dev_priv) &&
7629 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7630 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7631 factor = 25;
7632 } else if (crtc_state->sdvo_tv_clock)
7633 factor = 20;
7634
7635 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7636 *fp |= FP_CB_TUNE;
7637
7638 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7639 *fp2 |= FP_CB_TUNE;
7640
7641 dpll = 0;
7642
7643 if (is_lvds)
7644 dpll |= DPLLB_MODE_LVDS;
7645 else
7646 dpll |= DPLLB_MODE_DAC_SERIAL;
7647
7648 dpll |= (crtc_state->pixel_multiplier - 1)
7649 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7650
7651 if (is_sdvo)
7652 dpll |= DPLL_SDVO_HIGH_SPEED;
7653 if (crtc_state->has_dp_encoder)
7654 dpll |= DPLL_SDVO_HIGH_SPEED;
7655
7656 /* compute bitmask from p1 value */
7657 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7658 /* also FPA1 */
7659 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7660
7661 switch (crtc_state->dpll.p2) {
7662 case 5:
7663 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7664 break;
7665 case 7:
7666 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7667 break;
7668 case 10:
7669 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7670 break;
7671 case 14:
7672 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7673 break;
7674 }
7675
7676 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7677 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7678 else
7679 dpll |= PLL_REF_INPUT_DREFCLK;
7680
7681 return dpll | DPLL_VCO_ENABLE;
7682 }
7683
7684 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7685 struct intel_crtc_state *crtc_state)
7686 {
7687 struct drm_device *dev = crtc->base.dev;
7688 intel_clock_t clock, reduced_clock;
7689 u32 dpll = 0, fp = 0, fp2 = 0;
7690 bool ok, has_reduced_clock = false;
7691 bool is_lvds = false;
7692 struct intel_shared_dpll *pll;
7693
7694 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7695
7696 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7697 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7698
7699 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7700 &has_reduced_clock, &reduced_clock);
7701 if (!ok && !crtc_state->clock_set) {
7702 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7703 return -EINVAL;
7704 }
7705 /* Compat-code for transition, will disappear. */
7706 if (!crtc_state->clock_set) {
7707 crtc_state->dpll.n = clock.n;
7708 crtc_state->dpll.m1 = clock.m1;
7709 crtc_state->dpll.m2 = clock.m2;
7710 crtc_state->dpll.p1 = clock.p1;
7711 crtc_state->dpll.p2 = clock.p2;
7712 }
7713
7714 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7715 if (crtc_state->has_pch_encoder) {
7716 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7717 if (has_reduced_clock)
7718 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7719
7720 dpll = ironlake_compute_dpll(crtc, crtc_state,
7721 &fp, &reduced_clock,
7722 has_reduced_clock ? &fp2 : NULL);
7723
7724 crtc_state->dpll_hw_state.dpll = dpll;
7725 crtc_state->dpll_hw_state.fp0 = fp;
7726 if (has_reduced_clock)
7727 crtc_state->dpll_hw_state.fp1 = fp2;
7728 else
7729 crtc_state->dpll_hw_state.fp1 = fp;
7730
7731 pll = intel_get_shared_dpll(crtc, crtc_state);
7732 if (pll == NULL) {
7733 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7734 pipe_name(crtc->pipe));
7735 return -EINVAL;
7736 }
7737 }
7738
7739 if (is_lvds && has_reduced_clock && i915.powersave)
7740 crtc->lowfreq_avail = true;
7741 else
7742 crtc->lowfreq_avail = false;
7743
7744 return 0;
7745 }
7746
7747 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7748 struct intel_link_m_n *m_n)
7749 {
7750 struct drm_device *dev = crtc->base.dev;
7751 struct drm_i915_private *dev_priv = dev->dev_private;
7752 enum pipe pipe = crtc->pipe;
7753
7754 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7755 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7756 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7757 & ~TU_SIZE_MASK;
7758 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7759 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7760 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7761 }
7762
7763 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7764 enum transcoder transcoder,
7765 struct intel_link_m_n *m_n,
7766 struct intel_link_m_n *m2_n2)
7767 {
7768 struct drm_device *dev = crtc->base.dev;
7769 struct drm_i915_private *dev_priv = dev->dev_private;
7770 enum pipe pipe = crtc->pipe;
7771
7772 if (INTEL_INFO(dev)->gen >= 5) {
7773 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7774 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7775 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7776 & ~TU_SIZE_MASK;
7777 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7778 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7779 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7780 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7781 * gen < 8) and if DRRS is supported (to make sure the
7782 * registers are not unnecessarily read).
7783 */
7784 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7785 crtc->config->has_drrs) {
7786 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7787 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7788 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7789 & ~TU_SIZE_MASK;
7790 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7791 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7792 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7793 }
7794 } else {
7795 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7796 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7797 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7798 & ~TU_SIZE_MASK;
7799 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7800 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7801 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7802 }
7803 }
7804
7805 void intel_dp_get_m_n(struct intel_crtc *crtc,
7806 struct intel_crtc_state *pipe_config)
7807 {
7808 if (pipe_config->has_pch_encoder)
7809 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7810 else
7811 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7812 &pipe_config->dp_m_n,
7813 &pipe_config->dp_m2_n2);
7814 }
7815
7816 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7817 struct intel_crtc_state *pipe_config)
7818 {
7819 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7820 &pipe_config->fdi_m_n, NULL);
7821 }
7822
7823 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7824 struct intel_crtc_state *pipe_config)
7825 {
7826 struct drm_device *dev = crtc->base.dev;
7827 struct drm_i915_private *dev_priv = dev->dev_private;
7828 uint32_t tmp;
7829
7830 tmp = I915_READ(PS_CTL(crtc->pipe));
7831
7832 if (tmp & PS_ENABLE) {
7833 pipe_config->pch_pfit.enabled = true;
7834 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7835 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7836 }
7837 }
7838
7839 static void
7840 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7841 struct intel_initial_plane_config *plane_config)
7842 {
7843 struct drm_device *dev = crtc->base.dev;
7844 struct drm_i915_private *dev_priv = dev->dev_private;
7845 u32 val, base, offset, stride_mult, tiling;
7846 int pipe = crtc->pipe;
7847 int fourcc, pixel_format;
7848 int aligned_height;
7849 struct drm_framebuffer *fb;
7850 struct intel_framebuffer *intel_fb;
7851
7852 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7853 if (!intel_fb) {
7854 DRM_DEBUG_KMS("failed to alloc fb\n");
7855 return;
7856 }
7857
7858 fb = &intel_fb->base;
7859
7860 val = I915_READ(PLANE_CTL(pipe, 0));
7861 if (!(val & PLANE_CTL_ENABLE))
7862 goto error;
7863
7864 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7865 fourcc = skl_format_to_fourcc(pixel_format,
7866 val & PLANE_CTL_ORDER_RGBX,
7867 val & PLANE_CTL_ALPHA_MASK);
7868 fb->pixel_format = fourcc;
7869 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7870
7871 tiling = val & PLANE_CTL_TILED_MASK;
7872 switch (tiling) {
7873 case PLANE_CTL_TILED_LINEAR:
7874 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7875 break;
7876 case PLANE_CTL_TILED_X:
7877 plane_config->tiling = I915_TILING_X;
7878 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7879 break;
7880 case PLANE_CTL_TILED_Y:
7881 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7882 break;
7883 case PLANE_CTL_TILED_YF:
7884 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7885 break;
7886 default:
7887 MISSING_CASE(tiling);
7888 goto error;
7889 }
7890
7891 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7892 plane_config->base = base;
7893
7894 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7895
7896 val = I915_READ(PLANE_SIZE(pipe, 0));
7897 fb->height = ((val >> 16) & 0xfff) + 1;
7898 fb->width = ((val >> 0) & 0x1fff) + 1;
7899
7900 val = I915_READ(PLANE_STRIDE(pipe, 0));
7901 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7902 fb->pixel_format);
7903 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7904
7905 aligned_height = intel_fb_align_height(dev, fb->height,
7906 fb->pixel_format,
7907 fb->modifier[0]);
7908
7909 plane_config->size = fb->pitches[0] * aligned_height;
7910
7911 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7912 pipe_name(pipe), fb->width, fb->height,
7913 fb->bits_per_pixel, base, fb->pitches[0],
7914 plane_config->size);
7915
7916 plane_config->fb = intel_fb;
7917 return;
7918
7919 error:
7920 kfree(fb);
7921 }
7922
7923 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7924 struct intel_crtc_state *pipe_config)
7925 {
7926 struct drm_device *dev = crtc->base.dev;
7927 struct drm_i915_private *dev_priv = dev->dev_private;
7928 uint32_t tmp;
7929
7930 tmp = I915_READ(PF_CTL(crtc->pipe));
7931
7932 if (tmp & PF_ENABLE) {
7933 pipe_config->pch_pfit.enabled = true;
7934 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7935 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7936
7937 /* We currently do not free assignements of panel fitters on
7938 * ivb/hsw (since we don't use the higher upscaling modes which
7939 * differentiates them) so just WARN about this case for now. */
7940 if (IS_GEN7(dev)) {
7941 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7942 PF_PIPE_SEL_IVB(crtc->pipe));
7943 }
7944 }
7945 }
7946
7947 static void
7948 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7949 struct intel_initial_plane_config *plane_config)
7950 {
7951 struct drm_device *dev = crtc->base.dev;
7952 struct drm_i915_private *dev_priv = dev->dev_private;
7953 u32 val, base, offset;
7954 int pipe = crtc->pipe;
7955 int fourcc, pixel_format;
7956 int aligned_height;
7957 struct drm_framebuffer *fb;
7958 struct intel_framebuffer *intel_fb;
7959
7960 val = I915_READ(DSPCNTR(pipe));
7961 if (!(val & DISPLAY_PLANE_ENABLE))
7962 return;
7963
7964 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7965 if (!intel_fb) {
7966 DRM_DEBUG_KMS("failed to alloc fb\n");
7967 return;
7968 }
7969
7970 fb = &intel_fb->base;
7971
7972 if (INTEL_INFO(dev)->gen >= 4) {
7973 if (val & DISPPLANE_TILED) {
7974 plane_config->tiling = I915_TILING_X;
7975 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7976 }
7977 }
7978
7979 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7980 fourcc = i9xx_format_to_fourcc(pixel_format);
7981 fb->pixel_format = fourcc;
7982 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7983
7984 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7985 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7986 offset = I915_READ(DSPOFFSET(pipe));
7987 } else {
7988 if (plane_config->tiling)
7989 offset = I915_READ(DSPTILEOFF(pipe));
7990 else
7991 offset = I915_READ(DSPLINOFF(pipe));
7992 }
7993 plane_config->base = base;
7994
7995 val = I915_READ(PIPESRC(pipe));
7996 fb->width = ((val >> 16) & 0xfff) + 1;
7997 fb->height = ((val >> 0) & 0xfff) + 1;
7998
7999 val = I915_READ(DSPSTRIDE(pipe));
8000 fb->pitches[0] = val & 0xffffffc0;
8001
8002 aligned_height = intel_fb_align_height(dev, fb->height,
8003 fb->pixel_format,
8004 fb->modifier[0]);
8005
8006 plane_config->size = fb->pitches[0] * aligned_height;
8007
8008 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8009 pipe_name(pipe), fb->width, fb->height,
8010 fb->bits_per_pixel, base, fb->pitches[0],
8011 plane_config->size);
8012
8013 plane_config->fb = intel_fb;
8014 }
8015
8016 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8017 struct intel_crtc_state *pipe_config)
8018 {
8019 struct drm_device *dev = crtc->base.dev;
8020 struct drm_i915_private *dev_priv = dev->dev_private;
8021 uint32_t tmp;
8022
8023 if (!intel_display_power_is_enabled(dev_priv,
8024 POWER_DOMAIN_PIPE(crtc->pipe)))
8025 return false;
8026
8027 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8028 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8029
8030 tmp = I915_READ(PIPECONF(crtc->pipe));
8031 if (!(tmp & PIPECONF_ENABLE))
8032 return false;
8033
8034 switch (tmp & PIPECONF_BPC_MASK) {
8035 case PIPECONF_6BPC:
8036 pipe_config->pipe_bpp = 18;
8037 break;
8038 case PIPECONF_8BPC:
8039 pipe_config->pipe_bpp = 24;
8040 break;
8041 case PIPECONF_10BPC:
8042 pipe_config->pipe_bpp = 30;
8043 break;
8044 case PIPECONF_12BPC:
8045 pipe_config->pipe_bpp = 36;
8046 break;
8047 default:
8048 break;
8049 }
8050
8051 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8052 pipe_config->limited_color_range = true;
8053
8054 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8055 struct intel_shared_dpll *pll;
8056
8057 pipe_config->has_pch_encoder = true;
8058
8059 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8060 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8061 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8062
8063 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8064
8065 if (HAS_PCH_IBX(dev_priv->dev)) {
8066 pipe_config->shared_dpll =
8067 (enum intel_dpll_id) crtc->pipe;
8068 } else {
8069 tmp = I915_READ(PCH_DPLL_SEL);
8070 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8071 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8072 else
8073 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8074 }
8075
8076 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8077
8078 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8079 &pipe_config->dpll_hw_state));
8080
8081 tmp = pipe_config->dpll_hw_state.dpll;
8082 pipe_config->pixel_multiplier =
8083 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8084 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8085
8086 ironlake_pch_clock_get(crtc, pipe_config);
8087 } else {
8088 pipe_config->pixel_multiplier = 1;
8089 }
8090
8091 intel_get_pipe_timings(crtc, pipe_config);
8092
8093 ironlake_get_pfit_config(crtc, pipe_config);
8094
8095 return true;
8096 }
8097
8098 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8099 {
8100 struct drm_device *dev = dev_priv->dev;
8101 struct intel_crtc *crtc;
8102
8103 for_each_intel_crtc(dev, crtc)
8104 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8105 pipe_name(crtc->pipe));
8106
8107 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8108 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8109 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8110 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8111 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8112 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8113 "CPU PWM1 enabled\n");
8114 if (IS_HASWELL(dev))
8115 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8116 "CPU PWM2 enabled\n");
8117 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8118 "PCH PWM1 enabled\n");
8119 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8120 "Utility pin enabled\n");
8121 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8122
8123 /*
8124 * In theory we can still leave IRQs enabled, as long as only the HPD
8125 * interrupts remain enabled. We used to check for that, but since it's
8126 * gen-specific and since we only disable LCPLL after we fully disable
8127 * the interrupts, the check below should be enough.
8128 */
8129 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8130 }
8131
8132 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8133 {
8134 struct drm_device *dev = dev_priv->dev;
8135
8136 if (IS_HASWELL(dev))
8137 return I915_READ(D_COMP_HSW);
8138 else
8139 return I915_READ(D_COMP_BDW);
8140 }
8141
8142 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8143 {
8144 struct drm_device *dev = dev_priv->dev;
8145
8146 if (IS_HASWELL(dev)) {
8147 mutex_lock(&dev_priv->rps.hw_lock);
8148 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8149 val))
8150 DRM_ERROR("Failed to write to D_COMP\n");
8151 mutex_unlock(&dev_priv->rps.hw_lock);
8152 } else {
8153 I915_WRITE(D_COMP_BDW, val);
8154 POSTING_READ(D_COMP_BDW);
8155 }
8156 }
8157
8158 /*
8159 * This function implements pieces of two sequences from BSpec:
8160 * - Sequence for display software to disable LCPLL
8161 * - Sequence for display software to allow package C8+
8162 * The steps implemented here are just the steps that actually touch the LCPLL
8163 * register. Callers should take care of disabling all the display engine
8164 * functions, doing the mode unset, fixing interrupts, etc.
8165 */
8166 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8167 bool switch_to_fclk, bool allow_power_down)
8168 {
8169 uint32_t val;
8170
8171 assert_can_disable_lcpll(dev_priv);
8172
8173 val = I915_READ(LCPLL_CTL);
8174
8175 if (switch_to_fclk) {
8176 val |= LCPLL_CD_SOURCE_FCLK;
8177 I915_WRITE(LCPLL_CTL, val);
8178
8179 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8180 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8181 DRM_ERROR("Switching to FCLK failed\n");
8182
8183 val = I915_READ(LCPLL_CTL);
8184 }
8185
8186 val |= LCPLL_PLL_DISABLE;
8187 I915_WRITE(LCPLL_CTL, val);
8188 POSTING_READ(LCPLL_CTL);
8189
8190 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8191 DRM_ERROR("LCPLL still locked\n");
8192
8193 val = hsw_read_dcomp(dev_priv);
8194 val |= D_COMP_COMP_DISABLE;
8195 hsw_write_dcomp(dev_priv, val);
8196 ndelay(100);
8197
8198 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8199 1))
8200 DRM_ERROR("D_COMP RCOMP still in progress\n");
8201
8202 if (allow_power_down) {
8203 val = I915_READ(LCPLL_CTL);
8204 val |= LCPLL_POWER_DOWN_ALLOW;
8205 I915_WRITE(LCPLL_CTL, val);
8206 POSTING_READ(LCPLL_CTL);
8207 }
8208 }
8209
8210 /*
8211 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8212 * source.
8213 */
8214 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8215 {
8216 uint32_t val;
8217
8218 val = I915_READ(LCPLL_CTL);
8219
8220 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8221 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8222 return;
8223
8224 /*
8225 * Make sure we're not on PC8 state before disabling PC8, otherwise
8226 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8227 */
8228 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8229
8230 if (val & LCPLL_POWER_DOWN_ALLOW) {
8231 val &= ~LCPLL_POWER_DOWN_ALLOW;
8232 I915_WRITE(LCPLL_CTL, val);
8233 POSTING_READ(LCPLL_CTL);
8234 }
8235
8236 val = hsw_read_dcomp(dev_priv);
8237 val |= D_COMP_COMP_FORCE;
8238 val &= ~D_COMP_COMP_DISABLE;
8239 hsw_write_dcomp(dev_priv, val);
8240
8241 val = I915_READ(LCPLL_CTL);
8242 val &= ~LCPLL_PLL_DISABLE;
8243 I915_WRITE(LCPLL_CTL, val);
8244
8245 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8246 DRM_ERROR("LCPLL not locked yet\n");
8247
8248 if (val & LCPLL_CD_SOURCE_FCLK) {
8249 val = I915_READ(LCPLL_CTL);
8250 val &= ~LCPLL_CD_SOURCE_FCLK;
8251 I915_WRITE(LCPLL_CTL, val);
8252
8253 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8254 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8255 DRM_ERROR("Switching back to LCPLL failed\n");
8256 }
8257
8258 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8259 }
8260
8261 /*
8262 * Package states C8 and deeper are really deep PC states that can only be
8263 * reached when all the devices on the system allow it, so even if the graphics
8264 * device allows PC8+, it doesn't mean the system will actually get to these
8265 * states. Our driver only allows PC8+ when going into runtime PM.
8266 *
8267 * The requirements for PC8+ are that all the outputs are disabled, the power
8268 * well is disabled and most interrupts are disabled, and these are also
8269 * requirements for runtime PM. When these conditions are met, we manually do
8270 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8271 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8272 * hang the machine.
8273 *
8274 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8275 * the state of some registers, so when we come back from PC8+ we need to
8276 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8277 * need to take care of the registers kept by RC6. Notice that this happens even
8278 * if we don't put the device in PCI D3 state (which is what currently happens
8279 * because of the runtime PM support).
8280 *
8281 * For more, read "Display Sequences for Package C8" on the hardware
8282 * documentation.
8283 */
8284 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8285 {
8286 struct drm_device *dev = dev_priv->dev;
8287 uint32_t val;
8288
8289 DRM_DEBUG_KMS("Enabling package C8+\n");
8290
8291 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8292 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8293 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8294 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8295 }
8296
8297 lpt_disable_clkout_dp(dev);
8298 hsw_disable_lcpll(dev_priv, true, true);
8299 }
8300
8301 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8302 {
8303 struct drm_device *dev = dev_priv->dev;
8304 uint32_t val;
8305
8306 DRM_DEBUG_KMS("Disabling package C8+\n");
8307
8308 hsw_restore_lcpll(dev_priv);
8309 lpt_init_pch_refclk(dev);
8310
8311 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8312 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8313 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8314 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8315 }
8316
8317 intel_prepare_ddi(dev);
8318 }
8319
8320 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8321 struct intel_crtc_state *crtc_state)
8322 {
8323 if (!intel_ddi_pll_select(crtc, crtc_state))
8324 return -EINVAL;
8325
8326 crtc->lowfreq_avail = false;
8327
8328 return 0;
8329 }
8330
8331 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8332 enum port port,
8333 struct intel_crtc_state *pipe_config)
8334 {
8335 u32 temp, dpll_ctl1;
8336
8337 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8338 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8339
8340 switch (pipe_config->ddi_pll_sel) {
8341 case SKL_DPLL0:
8342 /*
8343 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8344 * of the shared DPLL framework and thus needs to be read out
8345 * separately
8346 */
8347 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8348 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8349 break;
8350 case SKL_DPLL1:
8351 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8352 break;
8353 case SKL_DPLL2:
8354 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8355 break;
8356 case SKL_DPLL3:
8357 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8358 break;
8359 }
8360 }
8361
8362 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8363 enum port port,
8364 struct intel_crtc_state *pipe_config)
8365 {
8366 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8367
8368 switch (pipe_config->ddi_pll_sel) {
8369 case PORT_CLK_SEL_WRPLL1:
8370 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8371 break;
8372 case PORT_CLK_SEL_WRPLL2:
8373 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8374 break;
8375 }
8376 }
8377
8378 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8379 struct intel_crtc_state *pipe_config)
8380 {
8381 struct drm_device *dev = crtc->base.dev;
8382 struct drm_i915_private *dev_priv = dev->dev_private;
8383 struct intel_shared_dpll *pll;
8384 enum port port;
8385 uint32_t tmp;
8386
8387 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8388
8389 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8390
8391 if (IS_SKYLAKE(dev))
8392 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8393 else
8394 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8395
8396 if (pipe_config->shared_dpll >= 0) {
8397 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8398
8399 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8400 &pipe_config->dpll_hw_state));
8401 }
8402
8403 /*
8404 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8405 * DDI E. So just check whether this pipe is wired to DDI E and whether
8406 * the PCH transcoder is on.
8407 */
8408 if (INTEL_INFO(dev)->gen < 9 &&
8409 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8410 pipe_config->has_pch_encoder = true;
8411
8412 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8413 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8414 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8415
8416 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8417 }
8418 }
8419
8420 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8421 struct intel_crtc_state *pipe_config)
8422 {
8423 struct drm_device *dev = crtc->base.dev;
8424 struct drm_i915_private *dev_priv = dev->dev_private;
8425 enum intel_display_power_domain pfit_domain;
8426 uint32_t tmp;
8427
8428 if (!intel_display_power_is_enabled(dev_priv,
8429 POWER_DOMAIN_PIPE(crtc->pipe)))
8430 return false;
8431
8432 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8433 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8434
8435 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8436 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8437 enum pipe trans_edp_pipe;
8438 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8439 default:
8440 WARN(1, "unknown pipe linked to edp transcoder\n");
8441 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8442 case TRANS_DDI_EDP_INPUT_A_ON:
8443 trans_edp_pipe = PIPE_A;
8444 break;
8445 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8446 trans_edp_pipe = PIPE_B;
8447 break;
8448 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8449 trans_edp_pipe = PIPE_C;
8450 break;
8451 }
8452
8453 if (trans_edp_pipe == crtc->pipe)
8454 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8455 }
8456
8457 if (!intel_display_power_is_enabled(dev_priv,
8458 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8459 return false;
8460
8461 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8462 if (!(tmp & PIPECONF_ENABLE))
8463 return false;
8464
8465 haswell_get_ddi_port_state(crtc, pipe_config);
8466
8467 intel_get_pipe_timings(crtc, pipe_config);
8468
8469 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8470 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8471 if (IS_SKYLAKE(dev))
8472 skylake_get_pfit_config(crtc, pipe_config);
8473 else
8474 ironlake_get_pfit_config(crtc, pipe_config);
8475 }
8476
8477 if (IS_HASWELL(dev))
8478 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8479 (I915_READ(IPS_CTL) & IPS_ENABLE);
8480
8481 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8482 pipe_config->pixel_multiplier =
8483 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8484 } else {
8485 pipe_config->pixel_multiplier = 1;
8486 }
8487
8488 return true;
8489 }
8490
8491 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8492 {
8493 struct drm_device *dev = crtc->dev;
8494 struct drm_i915_private *dev_priv = dev->dev_private;
8495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8496 uint32_t cntl = 0, size = 0;
8497
8498 if (base) {
8499 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8500 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8501 unsigned int stride = roundup_pow_of_two(width) * 4;
8502
8503 switch (stride) {
8504 default:
8505 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8506 width, stride);
8507 stride = 256;
8508 /* fallthrough */
8509 case 256:
8510 case 512:
8511 case 1024:
8512 case 2048:
8513 break;
8514 }
8515
8516 cntl |= CURSOR_ENABLE |
8517 CURSOR_GAMMA_ENABLE |
8518 CURSOR_FORMAT_ARGB |
8519 CURSOR_STRIDE(stride);
8520
8521 size = (height << 12) | width;
8522 }
8523
8524 if (intel_crtc->cursor_cntl != 0 &&
8525 (intel_crtc->cursor_base != base ||
8526 intel_crtc->cursor_size != size ||
8527 intel_crtc->cursor_cntl != cntl)) {
8528 /* On these chipsets we can only modify the base/size/stride
8529 * whilst the cursor is disabled.
8530 */
8531 I915_WRITE(_CURACNTR, 0);
8532 POSTING_READ(_CURACNTR);
8533 intel_crtc->cursor_cntl = 0;
8534 }
8535
8536 if (intel_crtc->cursor_base != base) {
8537 I915_WRITE(_CURABASE, base);
8538 intel_crtc->cursor_base = base;
8539 }
8540
8541 if (intel_crtc->cursor_size != size) {
8542 I915_WRITE(CURSIZE, size);
8543 intel_crtc->cursor_size = size;
8544 }
8545
8546 if (intel_crtc->cursor_cntl != cntl) {
8547 I915_WRITE(_CURACNTR, cntl);
8548 POSTING_READ(_CURACNTR);
8549 intel_crtc->cursor_cntl = cntl;
8550 }
8551 }
8552
8553 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8554 {
8555 struct drm_device *dev = crtc->dev;
8556 struct drm_i915_private *dev_priv = dev->dev_private;
8557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8558 int pipe = intel_crtc->pipe;
8559 uint32_t cntl;
8560
8561 cntl = 0;
8562 if (base) {
8563 cntl = MCURSOR_GAMMA_ENABLE;
8564 switch (intel_crtc->base.cursor->state->crtc_w) {
8565 case 64:
8566 cntl |= CURSOR_MODE_64_ARGB_AX;
8567 break;
8568 case 128:
8569 cntl |= CURSOR_MODE_128_ARGB_AX;
8570 break;
8571 case 256:
8572 cntl |= CURSOR_MODE_256_ARGB_AX;
8573 break;
8574 default:
8575 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8576 return;
8577 }
8578 cntl |= pipe << 28; /* Connect to correct pipe */
8579
8580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8581 cntl |= CURSOR_PIPE_CSC_ENABLE;
8582 }
8583
8584 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8585 cntl |= CURSOR_ROTATE_180;
8586
8587 if (intel_crtc->cursor_cntl != cntl) {
8588 I915_WRITE(CURCNTR(pipe), cntl);
8589 POSTING_READ(CURCNTR(pipe));
8590 intel_crtc->cursor_cntl = cntl;
8591 }
8592
8593 /* and commit changes on next vblank */
8594 I915_WRITE(CURBASE(pipe), base);
8595 POSTING_READ(CURBASE(pipe));
8596
8597 intel_crtc->cursor_base = base;
8598 }
8599
8600 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8601 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8602 bool on)
8603 {
8604 struct drm_device *dev = crtc->dev;
8605 struct drm_i915_private *dev_priv = dev->dev_private;
8606 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8607 int pipe = intel_crtc->pipe;
8608 int x = crtc->cursor_x;
8609 int y = crtc->cursor_y;
8610 u32 base = 0, pos = 0;
8611
8612 if (on)
8613 base = intel_crtc->cursor_addr;
8614
8615 if (x >= intel_crtc->config->pipe_src_w)
8616 base = 0;
8617
8618 if (y >= intel_crtc->config->pipe_src_h)
8619 base = 0;
8620
8621 if (x < 0) {
8622 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8623 base = 0;
8624
8625 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8626 x = -x;
8627 }
8628 pos |= x << CURSOR_X_SHIFT;
8629
8630 if (y < 0) {
8631 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8632 base = 0;
8633
8634 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8635 y = -y;
8636 }
8637 pos |= y << CURSOR_Y_SHIFT;
8638
8639 if (base == 0 && intel_crtc->cursor_base == 0)
8640 return;
8641
8642 I915_WRITE(CURPOS(pipe), pos);
8643
8644 /* ILK+ do this automagically */
8645 if (HAS_GMCH_DISPLAY(dev) &&
8646 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8647 base += (intel_crtc->base.cursor->state->crtc_h *
8648 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8649 }
8650
8651 if (IS_845G(dev) || IS_I865G(dev))
8652 i845_update_cursor(crtc, base);
8653 else
8654 i9xx_update_cursor(crtc, base);
8655 }
8656
8657 static bool cursor_size_ok(struct drm_device *dev,
8658 uint32_t width, uint32_t height)
8659 {
8660 if (width == 0 || height == 0)
8661 return false;
8662
8663 /*
8664 * 845g/865g are special in that they are only limited by
8665 * the width of their cursors, the height is arbitrary up to
8666 * the precision of the register. Everything else requires
8667 * square cursors, limited to a few power-of-two sizes.
8668 */
8669 if (IS_845G(dev) || IS_I865G(dev)) {
8670 if ((width & 63) != 0)
8671 return false;
8672
8673 if (width > (IS_845G(dev) ? 64 : 512))
8674 return false;
8675
8676 if (height > 1023)
8677 return false;
8678 } else {
8679 switch (width | height) {
8680 case 256:
8681 case 128:
8682 if (IS_GEN2(dev))
8683 return false;
8684 case 64:
8685 break;
8686 default:
8687 return false;
8688 }
8689 }
8690
8691 return true;
8692 }
8693
8694 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8695 u16 *blue, uint32_t start, uint32_t size)
8696 {
8697 int end = (start + size > 256) ? 256 : start + size, i;
8698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8699
8700 for (i = start; i < end; i++) {
8701 intel_crtc->lut_r[i] = red[i] >> 8;
8702 intel_crtc->lut_g[i] = green[i] >> 8;
8703 intel_crtc->lut_b[i] = blue[i] >> 8;
8704 }
8705
8706 intel_crtc_load_lut(crtc);
8707 }
8708
8709 /* VESA 640x480x72Hz mode to set on the pipe */
8710 static struct drm_display_mode load_detect_mode = {
8711 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8712 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8713 };
8714
8715 struct drm_framebuffer *
8716 __intel_framebuffer_create(struct drm_device *dev,
8717 struct drm_mode_fb_cmd2 *mode_cmd,
8718 struct drm_i915_gem_object *obj)
8719 {
8720 struct intel_framebuffer *intel_fb;
8721 int ret;
8722
8723 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8724 if (!intel_fb) {
8725 drm_gem_object_unreference(&obj->base);
8726 return ERR_PTR(-ENOMEM);
8727 }
8728
8729 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8730 if (ret)
8731 goto err;
8732
8733 return &intel_fb->base;
8734 err:
8735 drm_gem_object_unreference(&obj->base);
8736 kfree(intel_fb);
8737
8738 return ERR_PTR(ret);
8739 }
8740
8741 static struct drm_framebuffer *
8742 intel_framebuffer_create(struct drm_device *dev,
8743 struct drm_mode_fb_cmd2 *mode_cmd,
8744 struct drm_i915_gem_object *obj)
8745 {
8746 struct drm_framebuffer *fb;
8747 int ret;
8748
8749 ret = i915_mutex_lock_interruptible(dev);
8750 if (ret)
8751 return ERR_PTR(ret);
8752 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8753 mutex_unlock(&dev->struct_mutex);
8754
8755 return fb;
8756 }
8757
8758 static u32
8759 intel_framebuffer_pitch_for_width(int width, int bpp)
8760 {
8761 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8762 return ALIGN(pitch, 64);
8763 }
8764
8765 static u32
8766 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8767 {
8768 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8769 return PAGE_ALIGN(pitch * mode->vdisplay);
8770 }
8771
8772 static struct drm_framebuffer *
8773 intel_framebuffer_create_for_mode(struct drm_device *dev,
8774 struct drm_display_mode *mode,
8775 int depth, int bpp)
8776 {
8777 struct drm_i915_gem_object *obj;
8778 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8779
8780 obj = i915_gem_alloc_object(dev,
8781 intel_framebuffer_size_for_mode(mode, bpp));
8782 if (obj == NULL)
8783 return ERR_PTR(-ENOMEM);
8784
8785 mode_cmd.width = mode->hdisplay;
8786 mode_cmd.height = mode->vdisplay;
8787 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8788 bpp);
8789 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8790
8791 return intel_framebuffer_create(dev, &mode_cmd, obj);
8792 }
8793
8794 static struct drm_framebuffer *
8795 mode_fits_in_fbdev(struct drm_device *dev,
8796 struct drm_display_mode *mode)
8797 {
8798 #ifdef CONFIG_DRM_I915_FBDEV
8799 struct drm_i915_private *dev_priv = dev->dev_private;
8800 struct drm_i915_gem_object *obj;
8801 struct drm_framebuffer *fb;
8802
8803 if (!dev_priv->fbdev)
8804 return NULL;
8805
8806 if (!dev_priv->fbdev->fb)
8807 return NULL;
8808
8809 obj = dev_priv->fbdev->fb->obj;
8810 BUG_ON(!obj);
8811
8812 fb = &dev_priv->fbdev->fb->base;
8813 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8814 fb->bits_per_pixel))
8815 return NULL;
8816
8817 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8818 return NULL;
8819
8820 return fb;
8821 #else
8822 return NULL;
8823 #endif
8824 }
8825
8826 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8827 struct drm_display_mode *mode,
8828 struct intel_load_detect_pipe *old,
8829 struct drm_modeset_acquire_ctx *ctx)
8830 {
8831 struct intel_crtc *intel_crtc;
8832 struct intel_encoder *intel_encoder =
8833 intel_attached_encoder(connector);
8834 struct drm_crtc *possible_crtc;
8835 struct drm_encoder *encoder = &intel_encoder->base;
8836 struct drm_crtc *crtc = NULL;
8837 struct drm_device *dev = encoder->dev;
8838 struct drm_framebuffer *fb;
8839 struct drm_mode_config *config = &dev->mode_config;
8840 int ret, i = -1;
8841
8842 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8843 connector->base.id, connector->name,
8844 encoder->base.id, encoder->name);
8845
8846 retry:
8847 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8848 if (ret)
8849 goto fail_unlock;
8850
8851 /*
8852 * Algorithm gets a little messy:
8853 *
8854 * - if the connector already has an assigned crtc, use it (but make
8855 * sure it's on first)
8856 *
8857 * - try to find the first unused crtc that can drive this connector,
8858 * and use that if we find one
8859 */
8860
8861 /* See if we already have a CRTC for this connector */
8862 if (encoder->crtc) {
8863 crtc = encoder->crtc;
8864
8865 ret = drm_modeset_lock(&crtc->mutex, ctx);
8866 if (ret)
8867 goto fail_unlock;
8868 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8869 if (ret)
8870 goto fail_unlock;
8871
8872 old->dpms_mode = connector->dpms;
8873 old->load_detect_temp = false;
8874
8875 /* Make sure the crtc and connector are running */
8876 if (connector->dpms != DRM_MODE_DPMS_ON)
8877 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8878
8879 return true;
8880 }
8881
8882 /* Find an unused one (if possible) */
8883 for_each_crtc(dev, possible_crtc) {
8884 i++;
8885 if (!(encoder->possible_crtcs & (1 << i)))
8886 continue;
8887 if (possible_crtc->state->enable)
8888 continue;
8889 /* This can occur when applying the pipe A quirk on resume. */
8890 if (to_intel_crtc(possible_crtc)->new_enabled)
8891 continue;
8892
8893 crtc = possible_crtc;
8894 break;
8895 }
8896
8897 /*
8898 * If we didn't find an unused CRTC, don't use any.
8899 */
8900 if (!crtc) {
8901 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8902 goto fail_unlock;
8903 }
8904
8905 ret = drm_modeset_lock(&crtc->mutex, ctx);
8906 if (ret)
8907 goto fail_unlock;
8908 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8909 if (ret)
8910 goto fail_unlock;
8911 intel_encoder->new_crtc = to_intel_crtc(crtc);
8912 to_intel_connector(connector)->new_encoder = intel_encoder;
8913
8914 intel_crtc = to_intel_crtc(crtc);
8915 intel_crtc->new_enabled = true;
8916 intel_crtc->new_config = intel_crtc->config;
8917 old->dpms_mode = connector->dpms;
8918 old->load_detect_temp = true;
8919 old->release_fb = NULL;
8920
8921 if (!mode)
8922 mode = &load_detect_mode;
8923
8924 /* We need a framebuffer large enough to accommodate all accesses
8925 * that the plane may generate whilst we perform load detection.
8926 * We can not rely on the fbcon either being present (we get called
8927 * during its initialisation to detect all boot displays, or it may
8928 * not even exist) or that it is large enough to satisfy the
8929 * requested mode.
8930 */
8931 fb = mode_fits_in_fbdev(dev, mode);
8932 if (fb == NULL) {
8933 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8934 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8935 old->release_fb = fb;
8936 } else
8937 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8938 if (IS_ERR(fb)) {
8939 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8940 goto fail;
8941 }
8942
8943 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8944 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8945 if (old->release_fb)
8946 old->release_fb->funcs->destroy(old->release_fb);
8947 goto fail;
8948 }
8949 crtc->primary->crtc = crtc;
8950
8951 /* let the connector get through one full cycle before testing */
8952 intel_wait_for_vblank(dev, intel_crtc->pipe);
8953 return true;
8954
8955 fail:
8956 intel_crtc->new_enabled = crtc->state->enable;
8957 if (intel_crtc->new_enabled)
8958 intel_crtc->new_config = intel_crtc->config;
8959 else
8960 intel_crtc->new_config = NULL;
8961 fail_unlock:
8962 if (ret == -EDEADLK) {
8963 drm_modeset_backoff(ctx);
8964 goto retry;
8965 }
8966
8967 return false;
8968 }
8969
8970 void intel_release_load_detect_pipe(struct drm_connector *connector,
8971 struct intel_load_detect_pipe *old)
8972 {
8973 struct intel_encoder *intel_encoder =
8974 intel_attached_encoder(connector);
8975 struct drm_encoder *encoder = &intel_encoder->base;
8976 struct drm_crtc *crtc = encoder->crtc;
8977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8978
8979 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8980 connector->base.id, connector->name,
8981 encoder->base.id, encoder->name);
8982
8983 if (old->load_detect_temp) {
8984 to_intel_connector(connector)->new_encoder = NULL;
8985 intel_encoder->new_crtc = NULL;
8986 intel_crtc->new_enabled = false;
8987 intel_crtc->new_config = NULL;
8988 intel_set_mode(crtc, NULL, 0, 0, NULL);
8989
8990 if (old->release_fb) {
8991 drm_framebuffer_unregister_private(old->release_fb);
8992 drm_framebuffer_unreference(old->release_fb);
8993 }
8994
8995 return;
8996 }
8997
8998 /* Switch crtc and encoder back off if necessary */
8999 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9000 connector->funcs->dpms(connector, old->dpms_mode);
9001 }
9002
9003 static int i9xx_pll_refclk(struct drm_device *dev,
9004 const struct intel_crtc_state *pipe_config)
9005 {
9006 struct drm_i915_private *dev_priv = dev->dev_private;
9007 u32 dpll = pipe_config->dpll_hw_state.dpll;
9008
9009 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9010 return dev_priv->vbt.lvds_ssc_freq;
9011 else if (HAS_PCH_SPLIT(dev))
9012 return 120000;
9013 else if (!IS_GEN2(dev))
9014 return 96000;
9015 else
9016 return 48000;
9017 }
9018
9019 /* Returns the clock of the currently programmed mode of the given pipe. */
9020 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9021 struct intel_crtc_state *pipe_config)
9022 {
9023 struct drm_device *dev = crtc->base.dev;
9024 struct drm_i915_private *dev_priv = dev->dev_private;
9025 int pipe = pipe_config->cpu_transcoder;
9026 u32 dpll = pipe_config->dpll_hw_state.dpll;
9027 u32 fp;
9028 intel_clock_t clock;
9029 int refclk = i9xx_pll_refclk(dev, pipe_config);
9030
9031 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9032 fp = pipe_config->dpll_hw_state.fp0;
9033 else
9034 fp = pipe_config->dpll_hw_state.fp1;
9035
9036 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9037 if (IS_PINEVIEW(dev)) {
9038 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9039 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9040 } else {
9041 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9042 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9043 }
9044
9045 if (!IS_GEN2(dev)) {
9046 if (IS_PINEVIEW(dev))
9047 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9048 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9049 else
9050 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9051 DPLL_FPA01_P1_POST_DIV_SHIFT);
9052
9053 switch (dpll & DPLL_MODE_MASK) {
9054 case DPLLB_MODE_DAC_SERIAL:
9055 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9056 5 : 10;
9057 break;
9058 case DPLLB_MODE_LVDS:
9059 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9060 7 : 14;
9061 break;
9062 default:
9063 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9064 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9065 return;
9066 }
9067
9068 if (IS_PINEVIEW(dev))
9069 pineview_clock(refclk, &clock);
9070 else
9071 i9xx_clock(refclk, &clock);
9072 } else {
9073 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9074 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9075
9076 if (is_lvds) {
9077 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9078 DPLL_FPA01_P1_POST_DIV_SHIFT);
9079
9080 if (lvds & LVDS_CLKB_POWER_UP)
9081 clock.p2 = 7;
9082 else
9083 clock.p2 = 14;
9084 } else {
9085 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9086 clock.p1 = 2;
9087 else {
9088 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9089 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9090 }
9091 if (dpll & PLL_P2_DIVIDE_BY_4)
9092 clock.p2 = 4;
9093 else
9094 clock.p2 = 2;
9095 }
9096
9097 i9xx_clock(refclk, &clock);
9098 }
9099
9100 /*
9101 * This value includes pixel_multiplier. We will use
9102 * port_clock to compute adjusted_mode.crtc_clock in the
9103 * encoder's get_config() function.
9104 */
9105 pipe_config->port_clock = clock.dot;
9106 }
9107
9108 int intel_dotclock_calculate(int link_freq,
9109 const struct intel_link_m_n *m_n)
9110 {
9111 /*
9112 * The calculation for the data clock is:
9113 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9114 * But we want to avoid losing precison if possible, so:
9115 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9116 *
9117 * and the link clock is simpler:
9118 * link_clock = (m * link_clock) / n
9119 */
9120
9121 if (!m_n->link_n)
9122 return 0;
9123
9124 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9125 }
9126
9127 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9128 struct intel_crtc_state *pipe_config)
9129 {
9130 struct drm_device *dev = crtc->base.dev;
9131
9132 /* read out port_clock from the DPLL */
9133 i9xx_crtc_clock_get(crtc, pipe_config);
9134
9135 /*
9136 * This value does not include pixel_multiplier.
9137 * We will check that port_clock and adjusted_mode.crtc_clock
9138 * agree once we know their relationship in the encoder's
9139 * get_config() function.
9140 */
9141 pipe_config->base.adjusted_mode.crtc_clock =
9142 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9143 &pipe_config->fdi_m_n);
9144 }
9145
9146 /** Returns the currently programmed mode of the given pipe. */
9147 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9148 struct drm_crtc *crtc)
9149 {
9150 struct drm_i915_private *dev_priv = dev->dev_private;
9151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9152 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9153 struct drm_display_mode *mode;
9154 struct intel_crtc_state pipe_config;
9155 int htot = I915_READ(HTOTAL(cpu_transcoder));
9156 int hsync = I915_READ(HSYNC(cpu_transcoder));
9157 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9158 int vsync = I915_READ(VSYNC(cpu_transcoder));
9159 enum pipe pipe = intel_crtc->pipe;
9160
9161 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9162 if (!mode)
9163 return NULL;
9164
9165 /*
9166 * Construct a pipe_config sufficient for getting the clock info
9167 * back out of crtc_clock_get.
9168 *
9169 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9170 * to use a real value here instead.
9171 */
9172 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9173 pipe_config.pixel_multiplier = 1;
9174 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9175 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9176 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9177 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9178
9179 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9180 mode->hdisplay = (htot & 0xffff) + 1;
9181 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9182 mode->hsync_start = (hsync & 0xffff) + 1;
9183 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9184 mode->vdisplay = (vtot & 0xffff) + 1;
9185 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9186 mode->vsync_start = (vsync & 0xffff) + 1;
9187 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9188
9189 drm_mode_set_name(mode);
9190
9191 return mode;
9192 }
9193
9194 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9195 {
9196 struct drm_device *dev = crtc->dev;
9197 struct drm_i915_private *dev_priv = dev->dev_private;
9198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9199
9200 if (!HAS_GMCH_DISPLAY(dev))
9201 return;
9202
9203 if (!dev_priv->lvds_downclock_avail)
9204 return;
9205
9206 /*
9207 * Since this is called by a timer, we should never get here in
9208 * the manual case.
9209 */
9210 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9211 int pipe = intel_crtc->pipe;
9212 int dpll_reg = DPLL(pipe);
9213 int dpll;
9214
9215 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9216
9217 assert_panel_unlocked(dev_priv, pipe);
9218
9219 dpll = I915_READ(dpll_reg);
9220 dpll |= DISPLAY_RATE_SELECT_FPA1;
9221 I915_WRITE(dpll_reg, dpll);
9222 intel_wait_for_vblank(dev, pipe);
9223 dpll = I915_READ(dpll_reg);
9224 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9225 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9226 }
9227
9228 }
9229
9230 void intel_mark_busy(struct drm_device *dev)
9231 {
9232 struct drm_i915_private *dev_priv = dev->dev_private;
9233
9234 if (dev_priv->mm.busy)
9235 return;
9236
9237 intel_runtime_pm_get(dev_priv);
9238 i915_update_gfx_val(dev_priv);
9239 dev_priv->mm.busy = true;
9240 }
9241
9242 void intel_mark_idle(struct drm_device *dev)
9243 {
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9245 struct drm_crtc *crtc;
9246
9247 if (!dev_priv->mm.busy)
9248 return;
9249
9250 dev_priv->mm.busy = false;
9251
9252 if (!i915.powersave)
9253 goto out;
9254
9255 for_each_crtc(dev, crtc) {
9256 if (!crtc->primary->fb)
9257 continue;
9258
9259 intel_decrease_pllclock(crtc);
9260 }
9261
9262 if (INTEL_INFO(dev)->gen >= 6)
9263 gen6_rps_idle(dev->dev_private);
9264
9265 out:
9266 intel_runtime_pm_put(dev_priv);
9267 }
9268
9269 static void intel_crtc_set_state(struct intel_crtc *crtc,
9270 struct intel_crtc_state *crtc_state)
9271 {
9272 kfree(crtc->config);
9273 crtc->config = crtc_state;
9274 crtc->base.state = &crtc_state->base;
9275 }
9276
9277 static void intel_crtc_destroy(struct drm_crtc *crtc)
9278 {
9279 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9280 struct drm_device *dev = crtc->dev;
9281 struct intel_unpin_work *work;
9282
9283 spin_lock_irq(&dev->event_lock);
9284 work = intel_crtc->unpin_work;
9285 intel_crtc->unpin_work = NULL;
9286 spin_unlock_irq(&dev->event_lock);
9287
9288 if (work) {
9289 cancel_work_sync(&work->work);
9290 kfree(work);
9291 }
9292
9293 intel_crtc_set_state(intel_crtc, NULL);
9294 drm_crtc_cleanup(crtc);
9295
9296 kfree(intel_crtc);
9297 }
9298
9299 static void intel_unpin_work_fn(struct work_struct *__work)
9300 {
9301 struct intel_unpin_work *work =
9302 container_of(__work, struct intel_unpin_work, work);
9303 struct drm_device *dev = work->crtc->dev;
9304 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9305
9306 mutex_lock(&dev->struct_mutex);
9307 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9308 drm_gem_object_unreference(&work->pending_flip_obj->base);
9309 drm_framebuffer_unreference(work->old_fb);
9310
9311 intel_fbc_update(dev);
9312
9313 if (work->flip_queued_req)
9314 i915_gem_request_assign(&work->flip_queued_req, NULL);
9315 mutex_unlock(&dev->struct_mutex);
9316
9317 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9318
9319 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9320 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9321
9322 kfree(work);
9323 }
9324
9325 static void do_intel_finish_page_flip(struct drm_device *dev,
9326 struct drm_crtc *crtc)
9327 {
9328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9329 struct intel_unpin_work *work;
9330 unsigned long flags;
9331
9332 /* Ignore early vblank irqs */
9333 if (intel_crtc == NULL)
9334 return;
9335
9336 /*
9337 * This is called both by irq handlers and the reset code (to complete
9338 * lost pageflips) so needs the full irqsave spinlocks.
9339 */
9340 spin_lock_irqsave(&dev->event_lock, flags);
9341 work = intel_crtc->unpin_work;
9342
9343 /* Ensure we don't miss a work->pending update ... */
9344 smp_rmb();
9345
9346 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9347 spin_unlock_irqrestore(&dev->event_lock, flags);
9348 return;
9349 }
9350
9351 page_flip_completed(intel_crtc);
9352
9353 spin_unlock_irqrestore(&dev->event_lock, flags);
9354 }
9355
9356 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9357 {
9358 struct drm_i915_private *dev_priv = dev->dev_private;
9359 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9360
9361 do_intel_finish_page_flip(dev, crtc);
9362 }
9363
9364 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9365 {
9366 struct drm_i915_private *dev_priv = dev->dev_private;
9367 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9368
9369 do_intel_finish_page_flip(dev, crtc);
9370 }
9371
9372 /* Is 'a' after or equal to 'b'? */
9373 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9374 {
9375 return !((a - b) & 0x80000000);
9376 }
9377
9378 static bool page_flip_finished(struct intel_crtc *crtc)
9379 {
9380 struct drm_device *dev = crtc->base.dev;
9381 struct drm_i915_private *dev_priv = dev->dev_private;
9382
9383 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9384 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9385 return true;
9386
9387 /*
9388 * The relevant registers doen't exist on pre-ctg.
9389 * As the flip done interrupt doesn't trigger for mmio
9390 * flips on gmch platforms, a flip count check isn't
9391 * really needed there. But since ctg has the registers,
9392 * include it in the check anyway.
9393 */
9394 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9395 return true;
9396
9397 /*
9398 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9399 * used the same base address. In that case the mmio flip might
9400 * have completed, but the CS hasn't even executed the flip yet.
9401 *
9402 * A flip count check isn't enough as the CS might have updated
9403 * the base address just after start of vblank, but before we
9404 * managed to process the interrupt. This means we'd complete the
9405 * CS flip too soon.
9406 *
9407 * Combining both checks should get us a good enough result. It may
9408 * still happen that the CS flip has been executed, but has not
9409 * yet actually completed. But in case the base address is the same
9410 * anyway, we don't really care.
9411 */
9412 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9413 crtc->unpin_work->gtt_offset &&
9414 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9415 crtc->unpin_work->flip_count);
9416 }
9417
9418 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9419 {
9420 struct drm_i915_private *dev_priv = dev->dev_private;
9421 struct intel_crtc *intel_crtc =
9422 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9423 unsigned long flags;
9424
9425
9426 /*
9427 * This is called both by irq handlers and the reset code (to complete
9428 * lost pageflips) so needs the full irqsave spinlocks.
9429 *
9430 * NB: An MMIO update of the plane base pointer will also
9431 * generate a page-flip completion irq, i.e. every modeset
9432 * is also accompanied by a spurious intel_prepare_page_flip().
9433 */
9434 spin_lock_irqsave(&dev->event_lock, flags);
9435 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9436 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9437 spin_unlock_irqrestore(&dev->event_lock, flags);
9438 }
9439
9440 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9441 {
9442 /* Ensure that the work item is consistent when activating it ... */
9443 smp_wmb();
9444 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9445 /* and that it is marked active as soon as the irq could fire. */
9446 smp_wmb();
9447 }
9448
9449 static int intel_gen2_queue_flip(struct drm_device *dev,
9450 struct drm_crtc *crtc,
9451 struct drm_framebuffer *fb,
9452 struct drm_i915_gem_object *obj,
9453 struct intel_engine_cs *ring,
9454 uint32_t flags)
9455 {
9456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9457 u32 flip_mask;
9458 int ret;
9459
9460 ret = intel_ring_begin(ring, 6);
9461 if (ret)
9462 return ret;
9463
9464 /* Can't queue multiple flips, so wait for the previous
9465 * one to finish before executing the next.
9466 */
9467 if (intel_crtc->plane)
9468 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9469 else
9470 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9471 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9472 intel_ring_emit(ring, MI_NOOP);
9473 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9474 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9475 intel_ring_emit(ring, fb->pitches[0]);
9476 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9477 intel_ring_emit(ring, 0); /* aux display base address, unused */
9478
9479 intel_mark_page_flip_active(intel_crtc);
9480 __intel_ring_advance(ring);
9481 return 0;
9482 }
9483
9484 static int intel_gen3_queue_flip(struct drm_device *dev,
9485 struct drm_crtc *crtc,
9486 struct drm_framebuffer *fb,
9487 struct drm_i915_gem_object *obj,
9488 struct intel_engine_cs *ring,
9489 uint32_t flags)
9490 {
9491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9492 u32 flip_mask;
9493 int ret;
9494
9495 ret = intel_ring_begin(ring, 6);
9496 if (ret)
9497 return ret;
9498
9499 if (intel_crtc->plane)
9500 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9501 else
9502 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9503 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9504 intel_ring_emit(ring, MI_NOOP);
9505 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9506 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9507 intel_ring_emit(ring, fb->pitches[0]);
9508 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9509 intel_ring_emit(ring, MI_NOOP);
9510
9511 intel_mark_page_flip_active(intel_crtc);
9512 __intel_ring_advance(ring);
9513 return 0;
9514 }
9515
9516 static int intel_gen4_queue_flip(struct drm_device *dev,
9517 struct drm_crtc *crtc,
9518 struct drm_framebuffer *fb,
9519 struct drm_i915_gem_object *obj,
9520 struct intel_engine_cs *ring,
9521 uint32_t flags)
9522 {
9523 struct drm_i915_private *dev_priv = dev->dev_private;
9524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9525 uint32_t pf, pipesrc;
9526 int ret;
9527
9528 ret = intel_ring_begin(ring, 4);
9529 if (ret)
9530 return ret;
9531
9532 /* i965+ uses the linear or tiled offsets from the
9533 * Display Registers (which do not change across a page-flip)
9534 * so we need only reprogram the base address.
9535 */
9536 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9537 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9538 intel_ring_emit(ring, fb->pitches[0]);
9539 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9540 obj->tiling_mode);
9541
9542 /* XXX Enabling the panel-fitter across page-flip is so far
9543 * untested on non-native modes, so ignore it for now.
9544 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9545 */
9546 pf = 0;
9547 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9548 intel_ring_emit(ring, pf | pipesrc);
9549
9550 intel_mark_page_flip_active(intel_crtc);
9551 __intel_ring_advance(ring);
9552 return 0;
9553 }
9554
9555 static int intel_gen6_queue_flip(struct drm_device *dev,
9556 struct drm_crtc *crtc,
9557 struct drm_framebuffer *fb,
9558 struct drm_i915_gem_object *obj,
9559 struct intel_engine_cs *ring,
9560 uint32_t flags)
9561 {
9562 struct drm_i915_private *dev_priv = dev->dev_private;
9563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9564 uint32_t pf, pipesrc;
9565 int ret;
9566
9567 ret = intel_ring_begin(ring, 4);
9568 if (ret)
9569 return ret;
9570
9571 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9572 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9573 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9574 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9575
9576 /* Contrary to the suggestions in the documentation,
9577 * "Enable Panel Fitter" does not seem to be required when page
9578 * flipping with a non-native mode, and worse causes a normal
9579 * modeset to fail.
9580 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9581 */
9582 pf = 0;
9583 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9584 intel_ring_emit(ring, pf | pipesrc);
9585
9586 intel_mark_page_flip_active(intel_crtc);
9587 __intel_ring_advance(ring);
9588 return 0;
9589 }
9590
9591 static int intel_gen7_queue_flip(struct drm_device *dev,
9592 struct drm_crtc *crtc,
9593 struct drm_framebuffer *fb,
9594 struct drm_i915_gem_object *obj,
9595 struct intel_engine_cs *ring,
9596 uint32_t flags)
9597 {
9598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9599 uint32_t plane_bit = 0;
9600 int len, ret;
9601
9602 switch (intel_crtc->plane) {
9603 case PLANE_A:
9604 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9605 break;
9606 case PLANE_B:
9607 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9608 break;
9609 case PLANE_C:
9610 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9611 break;
9612 default:
9613 WARN_ONCE(1, "unknown plane in flip command\n");
9614 return -ENODEV;
9615 }
9616
9617 len = 4;
9618 if (ring->id == RCS) {
9619 len += 6;
9620 /*
9621 * On Gen 8, SRM is now taking an extra dword to accommodate
9622 * 48bits addresses, and we need a NOOP for the batch size to
9623 * stay even.
9624 */
9625 if (IS_GEN8(dev))
9626 len += 2;
9627 }
9628
9629 /*
9630 * BSpec MI_DISPLAY_FLIP for IVB:
9631 * "The full packet must be contained within the same cache line."
9632 *
9633 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9634 * cacheline, if we ever start emitting more commands before
9635 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9636 * then do the cacheline alignment, and finally emit the
9637 * MI_DISPLAY_FLIP.
9638 */
9639 ret = intel_ring_cacheline_align(ring);
9640 if (ret)
9641 return ret;
9642
9643 ret = intel_ring_begin(ring, len);
9644 if (ret)
9645 return ret;
9646
9647 /* Unmask the flip-done completion message. Note that the bspec says that
9648 * we should do this for both the BCS and RCS, and that we must not unmask
9649 * more than one flip event at any time (or ensure that one flip message
9650 * can be sent by waiting for flip-done prior to queueing new flips).
9651 * Experimentation says that BCS works despite DERRMR masking all
9652 * flip-done completion events and that unmasking all planes at once
9653 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9654 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9655 */
9656 if (ring->id == RCS) {
9657 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9658 intel_ring_emit(ring, DERRMR);
9659 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9660 DERRMR_PIPEB_PRI_FLIP_DONE |
9661 DERRMR_PIPEC_PRI_FLIP_DONE));
9662 if (IS_GEN8(dev))
9663 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9664 MI_SRM_LRM_GLOBAL_GTT);
9665 else
9666 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9667 MI_SRM_LRM_GLOBAL_GTT);
9668 intel_ring_emit(ring, DERRMR);
9669 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9670 if (IS_GEN8(dev)) {
9671 intel_ring_emit(ring, 0);
9672 intel_ring_emit(ring, MI_NOOP);
9673 }
9674 }
9675
9676 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9677 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9678 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9679 intel_ring_emit(ring, (MI_NOOP));
9680
9681 intel_mark_page_flip_active(intel_crtc);
9682 __intel_ring_advance(ring);
9683 return 0;
9684 }
9685
9686 static bool use_mmio_flip(struct intel_engine_cs *ring,
9687 struct drm_i915_gem_object *obj)
9688 {
9689 /*
9690 * This is not being used for older platforms, because
9691 * non-availability of flip done interrupt forces us to use
9692 * CS flips. Older platforms derive flip done using some clever
9693 * tricks involving the flip_pending status bits and vblank irqs.
9694 * So using MMIO flips there would disrupt this mechanism.
9695 */
9696
9697 if (ring == NULL)
9698 return true;
9699
9700 if (INTEL_INFO(ring->dev)->gen < 5)
9701 return false;
9702
9703 if (i915.use_mmio_flip < 0)
9704 return false;
9705 else if (i915.use_mmio_flip > 0)
9706 return true;
9707 else if (i915.enable_execlists)
9708 return true;
9709 else
9710 return ring != i915_gem_request_get_ring(obj->last_read_req);
9711 }
9712
9713 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9714 {
9715 struct drm_device *dev = intel_crtc->base.dev;
9716 struct drm_i915_private *dev_priv = dev->dev_private;
9717 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9718 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9719 struct drm_i915_gem_object *obj = intel_fb->obj;
9720 const enum pipe pipe = intel_crtc->pipe;
9721 u32 ctl, stride;
9722
9723 ctl = I915_READ(PLANE_CTL(pipe, 0));
9724 ctl &= ~PLANE_CTL_TILED_MASK;
9725 if (obj->tiling_mode == I915_TILING_X)
9726 ctl |= PLANE_CTL_TILED_X;
9727
9728 /*
9729 * The stride is either expressed as a multiple of 64 bytes chunks for
9730 * linear buffers or in number of tiles for tiled buffers.
9731 */
9732 stride = fb->pitches[0] >> 6;
9733 if (obj->tiling_mode == I915_TILING_X)
9734 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9735
9736 /*
9737 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9738 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9739 */
9740 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9741 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9742
9743 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9744 POSTING_READ(PLANE_SURF(pipe, 0));
9745 }
9746
9747 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9748 {
9749 struct drm_device *dev = intel_crtc->base.dev;
9750 struct drm_i915_private *dev_priv = dev->dev_private;
9751 struct intel_framebuffer *intel_fb =
9752 to_intel_framebuffer(intel_crtc->base.primary->fb);
9753 struct drm_i915_gem_object *obj = intel_fb->obj;
9754 u32 dspcntr;
9755 u32 reg;
9756
9757 reg = DSPCNTR(intel_crtc->plane);
9758 dspcntr = I915_READ(reg);
9759
9760 if (obj->tiling_mode != I915_TILING_NONE)
9761 dspcntr |= DISPPLANE_TILED;
9762 else
9763 dspcntr &= ~DISPPLANE_TILED;
9764
9765 I915_WRITE(reg, dspcntr);
9766
9767 I915_WRITE(DSPSURF(intel_crtc->plane),
9768 intel_crtc->unpin_work->gtt_offset);
9769 POSTING_READ(DSPSURF(intel_crtc->plane));
9770
9771 }
9772
9773 /*
9774 * XXX: This is the temporary way to update the plane registers until we get
9775 * around to using the usual plane update functions for MMIO flips
9776 */
9777 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9778 {
9779 struct drm_device *dev = intel_crtc->base.dev;
9780 bool atomic_update;
9781 u32 start_vbl_count;
9782
9783 intel_mark_page_flip_active(intel_crtc);
9784
9785 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9786
9787 if (INTEL_INFO(dev)->gen >= 9)
9788 skl_do_mmio_flip(intel_crtc);
9789 else
9790 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9791 ilk_do_mmio_flip(intel_crtc);
9792
9793 if (atomic_update)
9794 intel_pipe_update_end(intel_crtc, start_vbl_count);
9795 }
9796
9797 static void intel_mmio_flip_work_func(struct work_struct *work)
9798 {
9799 struct intel_crtc *crtc =
9800 container_of(work, struct intel_crtc, mmio_flip.work);
9801 struct intel_mmio_flip *mmio_flip;
9802
9803 mmio_flip = &crtc->mmio_flip;
9804 if (mmio_flip->req)
9805 WARN_ON(__i915_wait_request(mmio_flip->req,
9806 crtc->reset_counter,
9807 false, NULL, NULL) != 0);
9808
9809 intel_do_mmio_flip(crtc);
9810 if (mmio_flip->req) {
9811 mutex_lock(&crtc->base.dev->struct_mutex);
9812 i915_gem_request_assign(&mmio_flip->req, NULL);
9813 mutex_unlock(&crtc->base.dev->struct_mutex);
9814 }
9815 }
9816
9817 static int intel_queue_mmio_flip(struct drm_device *dev,
9818 struct drm_crtc *crtc,
9819 struct drm_framebuffer *fb,
9820 struct drm_i915_gem_object *obj,
9821 struct intel_engine_cs *ring,
9822 uint32_t flags)
9823 {
9824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9825
9826 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9827 obj->last_write_req);
9828
9829 schedule_work(&intel_crtc->mmio_flip.work);
9830
9831 return 0;
9832 }
9833
9834 static int intel_default_queue_flip(struct drm_device *dev,
9835 struct drm_crtc *crtc,
9836 struct drm_framebuffer *fb,
9837 struct drm_i915_gem_object *obj,
9838 struct intel_engine_cs *ring,
9839 uint32_t flags)
9840 {
9841 return -ENODEV;
9842 }
9843
9844 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9845 struct drm_crtc *crtc)
9846 {
9847 struct drm_i915_private *dev_priv = dev->dev_private;
9848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9849 struct intel_unpin_work *work = intel_crtc->unpin_work;
9850 u32 addr;
9851
9852 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9853 return true;
9854
9855 if (!work->enable_stall_check)
9856 return false;
9857
9858 if (work->flip_ready_vblank == 0) {
9859 if (work->flip_queued_req &&
9860 !i915_gem_request_completed(work->flip_queued_req, true))
9861 return false;
9862
9863 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9864 }
9865
9866 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9867 return false;
9868
9869 /* Potential stall - if we see that the flip has happened,
9870 * assume a missed interrupt. */
9871 if (INTEL_INFO(dev)->gen >= 4)
9872 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9873 else
9874 addr = I915_READ(DSPADDR(intel_crtc->plane));
9875
9876 /* There is a potential issue here with a false positive after a flip
9877 * to the same address. We could address this by checking for a
9878 * non-incrementing frame counter.
9879 */
9880 return addr == work->gtt_offset;
9881 }
9882
9883 void intel_check_page_flip(struct drm_device *dev, int pipe)
9884 {
9885 struct drm_i915_private *dev_priv = dev->dev_private;
9886 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9888
9889 WARN_ON(!in_irq());
9890
9891 if (crtc == NULL)
9892 return;
9893
9894 spin_lock(&dev->event_lock);
9895 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9896 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9897 intel_crtc->unpin_work->flip_queued_vblank,
9898 drm_vblank_count(dev, pipe));
9899 page_flip_completed(intel_crtc);
9900 }
9901 spin_unlock(&dev->event_lock);
9902 }
9903
9904 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9905 struct drm_framebuffer *fb,
9906 struct drm_pending_vblank_event *event,
9907 uint32_t page_flip_flags)
9908 {
9909 struct drm_device *dev = crtc->dev;
9910 struct drm_i915_private *dev_priv = dev->dev_private;
9911 struct drm_framebuffer *old_fb = crtc->primary->fb;
9912 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9914 struct drm_plane *primary = crtc->primary;
9915 enum pipe pipe = intel_crtc->pipe;
9916 struct intel_unpin_work *work;
9917 struct intel_engine_cs *ring;
9918 int ret;
9919
9920 /*
9921 * drm_mode_page_flip_ioctl() should already catch this, but double
9922 * check to be safe. In the future we may enable pageflipping from
9923 * a disabled primary plane.
9924 */
9925 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9926 return -EBUSY;
9927
9928 /* Can't change pixel format via MI display flips. */
9929 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9930 return -EINVAL;
9931
9932 /*
9933 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9934 * Note that pitch changes could also affect these register.
9935 */
9936 if (INTEL_INFO(dev)->gen > 3 &&
9937 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9938 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9939 return -EINVAL;
9940
9941 if (i915_terminally_wedged(&dev_priv->gpu_error))
9942 goto out_hang;
9943
9944 work = kzalloc(sizeof(*work), GFP_KERNEL);
9945 if (work == NULL)
9946 return -ENOMEM;
9947
9948 work->event = event;
9949 work->crtc = crtc;
9950 work->old_fb = old_fb;
9951 INIT_WORK(&work->work, intel_unpin_work_fn);
9952
9953 ret = drm_crtc_vblank_get(crtc);
9954 if (ret)
9955 goto free_work;
9956
9957 /* We borrow the event spin lock for protecting unpin_work */
9958 spin_lock_irq(&dev->event_lock);
9959 if (intel_crtc->unpin_work) {
9960 /* Before declaring the flip queue wedged, check if
9961 * the hardware completed the operation behind our backs.
9962 */
9963 if (__intel_pageflip_stall_check(dev, crtc)) {
9964 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9965 page_flip_completed(intel_crtc);
9966 } else {
9967 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9968 spin_unlock_irq(&dev->event_lock);
9969
9970 drm_crtc_vblank_put(crtc);
9971 kfree(work);
9972 return -EBUSY;
9973 }
9974 }
9975 intel_crtc->unpin_work = work;
9976 spin_unlock_irq(&dev->event_lock);
9977
9978 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9979 flush_workqueue(dev_priv->wq);
9980
9981 ret = i915_mutex_lock_interruptible(dev);
9982 if (ret)
9983 goto cleanup;
9984
9985 /* Reference the objects for the scheduled work. */
9986 drm_framebuffer_reference(work->old_fb);
9987 drm_gem_object_reference(&obj->base);
9988
9989 crtc->primary->fb = fb;
9990 update_state_fb(crtc->primary);
9991
9992 work->pending_flip_obj = obj;
9993
9994 atomic_inc(&intel_crtc->unpin_work_count);
9995 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9996
9997 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9998 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9999
10000 if (IS_VALLEYVIEW(dev)) {
10001 ring = &dev_priv->ring[BCS];
10002 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
10003 /* vlv: DISPLAY_FLIP fails to change tiling */
10004 ring = NULL;
10005 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
10006 ring = &dev_priv->ring[BCS];
10007 } else if (INTEL_INFO(dev)->gen >= 7) {
10008 ring = i915_gem_request_get_ring(obj->last_read_req);
10009 if (ring == NULL || ring->id != RCS)
10010 ring = &dev_priv->ring[BCS];
10011 } else {
10012 ring = &dev_priv->ring[RCS];
10013 }
10014
10015 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
10016 if (ret)
10017 goto cleanup_pending;
10018
10019 work->gtt_offset =
10020 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10021
10022 if (use_mmio_flip(ring, obj)) {
10023 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10024 page_flip_flags);
10025 if (ret)
10026 goto cleanup_unpin;
10027
10028 i915_gem_request_assign(&work->flip_queued_req,
10029 obj->last_write_req);
10030 } else {
10031 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10032 page_flip_flags);
10033 if (ret)
10034 goto cleanup_unpin;
10035
10036 i915_gem_request_assign(&work->flip_queued_req,
10037 intel_ring_get_request(ring));
10038 }
10039
10040 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10041 work->enable_stall_check = true;
10042
10043 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10044 INTEL_FRONTBUFFER_PRIMARY(pipe));
10045
10046 intel_fbc_disable(dev);
10047 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10048 mutex_unlock(&dev->struct_mutex);
10049
10050 trace_i915_flip_request(intel_crtc->plane, obj);
10051
10052 return 0;
10053
10054 cleanup_unpin:
10055 intel_unpin_fb_obj(obj);
10056 cleanup_pending:
10057 atomic_dec(&intel_crtc->unpin_work_count);
10058 crtc->primary->fb = old_fb;
10059 update_state_fb(crtc->primary);
10060 drm_framebuffer_unreference(work->old_fb);
10061 drm_gem_object_unreference(&obj->base);
10062 mutex_unlock(&dev->struct_mutex);
10063
10064 cleanup:
10065 spin_lock_irq(&dev->event_lock);
10066 intel_crtc->unpin_work = NULL;
10067 spin_unlock_irq(&dev->event_lock);
10068
10069 drm_crtc_vblank_put(crtc);
10070 free_work:
10071 kfree(work);
10072
10073 if (ret == -EIO) {
10074 out_hang:
10075 ret = intel_plane_restore(primary);
10076 if (ret == 0 && event) {
10077 spin_lock_irq(&dev->event_lock);
10078 drm_send_vblank_event(dev, pipe, event);
10079 spin_unlock_irq(&dev->event_lock);
10080 }
10081 }
10082 return ret;
10083 }
10084
10085 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10086 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10087 .load_lut = intel_crtc_load_lut,
10088 .atomic_begin = intel_begin_crtc_commit,
10089 .atomic_flush = intel_finish_crtc_commit,
10090 };
10091
10092 /**
10093 * intel_modeset_update_staged_output_state
10094 *
10095 * Updates the staged output configuration state, e.g. after we've read out the
10096 * current hw state.
10097 */
10098 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10099 {
10100 struct intel_crtc *crtc;
10101 struct intel_encoder *encoder;
10102 struct intel_connector *connector;
10103
10104 for_each_intel_connector(dev, connector) {
10105 connector->new_encoder =
10106 to_intel_encoder(connector->base.encoder);
10107 }
10108
10109 for_each_intel_encoder(dev, encoder) {
10110 encoder->new_crtc =
10111 to_intel_crtc(encoder->base.crtc);
10112 }
10113
10114 for_each_intel_crtc(dev, crtc) {
10115 crtc->new_enabled = crtc->base.state->enable;
10116
10117 if (crtc->new_enabled)
10118 crtc->new_config = crtc->config;
10119 else
10120 crtc->new_config = NULL;
10121 }
10122 }
10123
10124 /**
10125 * intel_modeset_commit_output_state
10126 *
10127 * This function copies the stage display pipe configuration to the real one.
10128 */
10129 static void intel_modeset_commit_output_state(struct drm_device *dev)
10130 {
10131 struct intel_crtc *crtc;
10132 struct intel_encoder *encoder;
10133 struct intel_connector *connector;
10134
10135 for_each_intel_connector(dev, connector) {
10136 connector->base.encoder = &connector->new_encoder->base;
10137 }
10138
10139 for_each_intel_encoder(dev, encoder) {
10140 encoder->base.crtc = &encoder->new_crtc->base;
10141 }
10142
10143 for_each_intel_crtc(dev, crtc) {
10144 crtc->base.state->enable = crtc->new_enabled;
10145 crtc->base.enabled = crtc->new_enabled;
10146 }
10147 }
10148
10149 static void
10150 connected_sink_compute_bpp(struct intel_connector *connector,
10151 struct intel_crtc_state *pipe_config)
10152 {
10153 int bpp = pipe_config->pipe_bpp;
10154
10155 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10156 connector->base.base.id,
10157 connector->base.name);
10158
10159 /* Don't use an invalid EDID bpc value */
10160 if (connector->base.display_info.bpc &&
10161 connector->base.display_info.bpc * 3 < bpp) {
10162 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10163 bpp, connector->base.display_info.bpc*3);
10164 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10165 }
10166
10167 /* Clamp bpp to 8 on screens without EDID 1.4 */
10168 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10169 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10170 bpp);
10171 pipe_config->pipe_bpp = 24;
10172 }
10173 }
10174
10175 static int
10176 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10177 struct drm_framebuffer *fb,
10178 struct intel_crtc_state *pipe_config)
10179 {
10180 struct drm_device *dev = crtc->base.dev;
10181 struct intel_connector *connector;
10182 int bpp;
10183
10184 switch (fb->pixel_format) {
10185 case DRM_FORMAT_C8:
10186 bpp = 8*3; /* since we go through a colormap */
10187 break;
10188 case DRM_FORMAT_XRGB1555:
10189 case DRM_FORMAT_ARGB1555:
10190 /* checked in intel_framebuffer_init already */
10191 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10192 return -EINVAL;
10193 case DRM_FORMAT_RGB565:
10194 bpp = 6*3; /* min is 18bpp */
10195 break;
10196 case DRM_FORMAT_XBGR8888:
10197 case DRM_FORMAT_ABGR8888:
10198 /* checked in intel_framebuffer_init already */
10199 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10200 return -EINVAL;
10201 case DRM_FORMAT_XRGB8888:
10202 case DRM_FORMAT_ARGB8888:
10203 bpp = 8*3;
10204 break;
10205 case DRM_FORMAT_XRGB2101010:
10206 case DRM_FORMAT_ARGB2101010:
10207 case DRM_FORMAT_XBGR2101010:
10208 case DRM_FORMAT_ABGR2101010:
10209 /* checked in intel_framebuffer_init already */
10210 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10211 return -EINVAL;
10212 bpp = 10*3;
10213 break;
10214 /* TODO: gen4+ supports 16 bpc floating point, too. */
10215 default:
10216 DRM_DEBUG_KMS("unsupported depth\n");
10217 return -EINVAL;
10218 }
10219
10220 pipe_config->pipe_bpp = bpp;
10221
10222 /* Clamp display bpp to EDID value */
10223 for_each_intel_connector(dev, connector) {
10224 if (!connector->new_encoder ||
10225 connector->new_encoder->new_crtc != crtc)
10226 continue;
10227
10228 connected_sink_compute_bpp(connector, pipe_config);
10229 }
10230
10231 return bpp;
10232 }
10233
10234 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10235 {
10236 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10237 "type: 0x%x flags: 0x%x\n",
10238 mode->crtc_clock,
10239 mode->crtc_hdisplay, mode->crtc_hsync_start,
10240 mode->crtc_hsync_end, mode->crtc_htotal,
10241 mode->crtc_vdisplay, mode->crtc_vsync_start,
10242 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10243 }
10244
10245 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10246 struct intel_crtc_state *pipe_config,
10247 const char *context)
10248 {
10249 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10250 context, pipe_name(crtc->pipe));
10251
10252 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10253 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10254 pipe_config->pipe_bpp, pipe_config->dither);
10255 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10256 pipe_config->has_pch_encoder,
10257 pipe_config->fdi_lanes,
10258 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10259 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10260 pipe_config->fdi_m_n.tu);
10261 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10262 pipe_config->has_dp_encoder,
10263 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10264 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10265 pipe_config->dp_m_n.tu);
10266
10267 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10268 pipe_config->has_dp_encoder,
10269 pipe_config->dp_m2_n2.gmch_m,
10270 pipe_config->dp_m2_n2.gmch_n,
10271 pipe_config->dp_m2_n2.link_m,
10272 pipe_config->dp_m2_n2.link_n,
10273 pipe_config->dp_m2_n2.tu);
10274
10275 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10276 pipe_config->has_audio,
10277 pipe_config->has_infoframe);
10278
10279 DRM_DEBUG_KMS("requested mode:\n");
10280 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10281 DRM_DEBUG_KMS("adjusted mode:\n");
10282 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10283 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10284 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10285 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10286 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10287 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10288 pipe_config->gmch_pfit.control,
10289 pipe_config->gmch_pfit.pgm_ratios,
10290 pipe_config->gmch_pfit.lvds_border_bits);
10291 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10292 pipe_config->pch_pfit.pos,
10293 pipe_config->pch_pfit.size,
10294 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10295 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10296 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10297 }
10298
10299 static bool encoders_cloneable(const struct intel_encoder *a,
10300 const struct intel_encoder *b)
10301 {
10302 /* masks could be asymmetric, so check both ways */
10303 return a == b || (a->cloneable & (1 << b->type) &&
10304 b->cloneable & (1 << a->type));
10305 }
10306
10307 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10308 struct intel_encoder *encoder)
10309 {
10310 struct drm_device *dev = crtc->base.dev;
10311 struct intel_encoder *source_encoder;
10312
10313 for_each_intel_encoder(dev, source_encoder) {
10314 if (source_encoder->new_crtc != crtc)
10315 continue;
10316
10317 if (!encoders_cloneable(encoder, source_encoder))
10318 return false;
10319 }
10320
10321 return true;
10322 }
10323
10324 static bool check_encoder_cloning(struct intel_crtc *crtc)
10325 {
10326 struct drm_device *dev = crtc->base.dev;
10327 struct intel_encoder *encoder;
10328
10329 for_each_intel_encoder(dev, encoder) {
10330 if (encoder->new_crtc != crtc)
10331 continue;
10332
10333 if (!check_single_encoder_cloning(crtc, encoder))
10334 return false;
10335 }
10336
10337 return true;
10338 }
10339
10340 static bool check_digital_port_conflicts(struct drm_device *dev)
10341 {
10342 struct intel_connector *connector;
10343 unsigned int used_ports = 0;
10344
10345 /*
10346 * Walk the connector list instead of the encoder
10347 * list to detect the problem on ddi platforms
10348 * where there's just one encoder per digital port.
10349 */
10350 for_each_intel_connector(dev, connector) {
10351 struct intel_encoder *encoder = connector->new_encoder;
10352
10353 if (!encoder)
10354 continue;
10355
10356 WARN_ON(!encoder->new_crtc);
10357
10358 switch (encoder->type) {
10359 unsigned int port_mask;
10360 case INTEL_OUTPUT_UNKNOWN:
10361 if (WARN_ON(!HAS_DDI(dev)))
10362 break;
10363 case INTEL_OUTPUT_DISPLAYPORT:
10364 case INTEL_OUTPUT_HDMI:
10365 case INTEL_OUTPUT_EDP:
10366 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10367
10368 /* the same port mustn't appear more than once */
10369 if (used_ports & port_mask)
10370 return false;
10371
10372 used_ports |= port_mask;
10373 default:
10374 break;
10375 }
10376 }
10377
10378 return true;
10379 }
10380
10381 static struct intel_crtc_state *
10382 intel_modeset_pipe_config(struct drm_crtc *crtc,
10383 struct drm_framebuffer *fb,
10384 struct drm_display_mode *mode)
10385 {
10386 struct drm_device *dev = crtc->dev;
10387 struct intel_encoder *encoder;
10388 struct intel_crtc_state *pipe_config;
10389 int plane_bpp, ret = -EINVAL;
10390 bool retry = true;
10391
10392 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10393 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10394 return ERR_PTR(-EINVAL);
10395 }
10396
10397 if (!check_digital_port_conflicts(dev)) {
10398 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10399 return ERR_PTR(-EINVAL);
10400 }
10401
10402 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10403 if (!pipe_config)
10404 return ERR_PTR(-ENOMEM);
10405
10406 pipe_config->base.crtc = crtc;
10407 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10408 drm_mode_copy(&pipe_config->base.mode, mode);
10409
10410 pipe_config->cpu_transcoder =
10411 (enum transcoder) to_intel_crtc(crtc)->pipe;
10412 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10413
10414 /*
10415 * Sanitize sync polarity flags based on requested ones. If neither
10416 * positive or negative polarity is requested, treat this as meaning
10417 * negative polarity.
10418 */
10419 if (!(pipe_config->base.adjusted_mode.flags &
10420 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10421 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10422
10423 if (!(pipe_config->base.adjusted_mode.flags &
10424 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10425 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10426
10427 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10428 * plane pixel format and any sink constraints into account. Returns the
10429 * source plane bpp so that dithering can be selected on mismatches
10430 * after encoders and crtc also have had their say. */
10431 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10432 fb, pipe_config);
10433 if (plane_bpp < 0)
10434 goto fail;
10435
10436 /*
10437 * Determine the real pipe dimensions. Note that stereo modes can
10438 * increase the actual pipe size due to the frame doubling and
10439 * insertion of additional space for blanks between the frame. This
10440 * is stored in the crtc timings. We use the requested mode to do this
10441 * computation to clearly distinguish it from the adjusted mode, which
10442 * can be changed by the connectors in the below retry loop.
10443 */
10444 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10445 &pipe_config->pipe_src_w,
10446 &pipe_config->pipe_src_h);
10447
10448 encoder_retry:
10449 /* Ensure the port clock defaults are reset when retrying. */
10450 pipe_config->port_clock = 0;
10451 pipe_config->pixel_multiplier = 1;
10452
10453 /* Fill in default crtc timings, allow encoders to overwrite them. */
10454 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10455 CRTC_STEREO_DOUBLE);
10456
10457 /* Pass our mode to the connectors and the CRTC to give them a chance to
10458 * adjust it according to limitations or connector properties, and also
10459 * a chance to reject the mode entirely.
10460 */
10461 for_each_intel_encoder(dev, encoder) {
10462
10463 if (&encoder->new_crtc->base != crtc)
10464 continue;
10465
10466 if (!(encoder->compute_config(encoder, pipe_config))) {
10467 DRM_DEBUG_KMS("Encoder config failure\n");
10468 goto fail;
10469 }
10470 }
10471
10472 /* Set default port clock if not overwritten by the encoder. Needs to be
10473 * done afterwards in case the encoder adjusts the mode. */
10474 if (!pipe_config->port_clock)
10475 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10476 * pipe_config->pixel_multiplier;
10477
10478 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10479 if (ret < 0) {
10480 DRM_DEBUG_KMS("CRTC fixup failed\n");
10481 goto fail;
10482 }
10483
10484 if (ret == RETRY) {
10485 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10486 ret = -EINVAL;
10487 goto fail;
10488 }
10489
10490 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10491 retry = false;
10492 goto encoder_retry;
10493 }
10494
10495 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10496 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10497 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10498
10499 return pipe_config;
10500 fail:
10501 kfree(pipe_config);
10502 return ERR_PTR(ret);
10503 }
10504
10505 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10506 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10507 static void
10508 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10509 unsigned *prepare_pipes, unsigned *disable_pipes)
10510 {
10511 struct intel_crtc *intel_crtc;
10512 struct drm_device *dev = crtc->dev;
10513 struct intel_encoder *encoder;
10514 struct intel_connector *connector;
10515 struct drm_crtc *tmp_crtc;
10516
10517 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10518
10519 /* Check which crtcs have changed outputs connected to them, these need
10520 * to be part of the prepare_pipes mask. We don't (yet) support global
10521 * modeset across multiple crtcs, so modeset_pipes will only have one
10522 * bit set at most. */
10523 for_each_intel_connector(dev, connector) {
10524 if (connector->base.encoder == &connector->new_encoder->base)
10525 continue;
10526
10527 if (connector->base.encoder) {
10528 tmp_crtc = connector->base.encoder->crtc;
10529
10530 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10531 }
10532
10533 if (connector->new_encoder)
10534 *prepare_pipes |=
10535 1 << connector->new_encoder->new_crtc->pipe;
10536 }
10537
10538 for_each_intel_encoder(dev, encoder) {
10539 if (encoder->base.crtc == &encoder->new_crtc->base)
10540 continue;
10541
10542 if (encoder->base.crtc) {
10543 tmp_crtc = encoder->base.crtc;
10544
10545 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10546 }
10547
10548 if (encoder->new_crtc)
10549 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10550 }
10551
10552 /* Check for pipes that will be enabled/disabled ... */
10553 for_each_intel_crtc(dev, intel_crtc) {
10554 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10555 continue;
10556
10557 if (!intel_crtc->new_enabled)
10558 *disable_pipes |= 1 << intel_crtc->pipe;
10559 else
10560 *prepare_pipes |= 1 << intel_crtc->pipe;
10561 }
10562
10563
10564 /* set_mode is also used to update properties on life display pipes. */
10565 intel_crtc = to_intel_crtc(crtc);
10566 if (intel_crtc->new_enabled)
10567 *prepare_pipes |= 1 << intel_crtc->pipe;
10568
10569 /*
10570 * For simplicity do a full modeset on any pipe where the output routing
10571 * changed. We could be more clever, but that would require us to be
10572 * more careful with calling the relevant encoder->mode_set functions.
10573 */
10574 if (*prepare_pipes)
10575 *modeset_pipes = *prepare_pipes;
10576
10577 /* ... and mask these out. */
10578 *modeset_pipes &= ~(*disable_pipes);
10579 *prepare_pipes &= ~(*disable_pipes);
10580
10581 /*
10582 * HACK: We don't (yet) fully support global modesets. intel_set_config
10583 * obies this rule, but the modeset restore mode of
10584 * intel_modeset_setup_hw_state does not.
10585 */
10586 *modeset_pipes &= 1 << intel_crtc->pipe;
10587 *prepare_pipes &= 1 << intel_crtc->pipe;
10588
10589 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10590 *modeset_pipes, *prepare_pipes, *disable_pipes);
10591 }
10592
10593 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10594 {
10595 struct drm_encoder *encoder;
10596 struct drm_device *dev = crtc->dev;
10597
10598 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10599 if (encoder->crtc == crtc)
10600 return true;
10601
10602 return false;
10603 }
10604
10605 static void
10606 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10607 {
10608 struct drm_i915_private *dev_priv = dev->dev_private;
10609 struct intel_encoder *intel_encoder;
10610 struct intel_crtc *intel_crtc;
10611 struct drm_connector *connector;
10612
10613 intel_shared_dpll_commit(dev_priv);
10614
10615 for_each_intel_encoder(dev, intel_encoder) {
10616 if (!intel_encoder->base.crtc)
10617 continue;
10618
10619 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10620
10621 if (prepare_pipes & (1 << intel_crtc->pipe))
10622 intel_encoder->connectors_active = false;
10623 }
10624
10625 intel_modeset_commit_output_state(dev);
10626
10627 /* Double check state. */
10628 for_each_intel_crtc(dev, intel_crtc) {
10629 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10630 WARN_ON(intel_crtc->new_config &&
10631 intel_crtc->new_config != intel_crtc->config);
10632 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10633 }
10634
10635 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10636 if (!connector->encoder || !connector->encoder->crtc)
10637 continue;
10638
10639 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10640
10641 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10642 struct drm_property *dpms_property =
10643 dev->mode_config.dpms_property;
10644
10645 connector->dpms = DRM_MODE_DPMS_ON;
10646 drm_object_property_set_value(&connector->base,
10647 dpms_property,
10648 DRM_MODE_DPMS_ON);
10649
10650 intel_encoder = to_intel_encoder(connector->encoder);
10651 intel_encoder->connectors_active = true;
10652 }
10653 }
10654
10655 }
10656
10657 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10658 {
10659 int diff;
10660
10661 if (clock1 == clock2)
10662 return true;
10663
10664 if (!clock1 || !clock2)
10665 return false;
10666
10667 diff = abs(clock1 - clock2);
10668
10669 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10670 return true;
10671
10672 return false;
10673 }
10674
10675 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10676 list_for_each_entry((intel_crtc), \
10677 &(dev)->mode_config.crtc_list, \
10678 base.head) \
10679 if (mask & (1 <<(intel_crtc)->pipe))
10680
10681 static bool
10682 intel_pipe_config_compare(struct drm_device *dev,
10683 struct intel_crtc_state *current_config,
10684 struct intel_crtc_state *pipe_config)
10685 {
10686 #define PIPE_CONF_CHECK_X(name) \
10687 if (current_config->name != pipe_config->name) { \
10688 DRM_ERROR("mismatch in " #name " " \
10689 "(expected 0x%08x, found 0x%08x)\n", \
10690 current_config->name, \
10691 pipe_config->name); \
10692 return false; \
10693 }
10694
10695 #define PIPE_CONF_CHECK_I(name) \
10696 if (current_config->name != pipe_config->name) { \
10697 DRM_ERROR("mismatch in " #name " " \
10698 "(expected %i, found %i)\n", \
10699 current_config->name, \
10700 pipe_config->name); \
10701 return false; \
10702 }
10703
10704 /* This is required for BDW+ where there is only one set of registers for
10705 * switching between high and low RR.
10706 * This macro can be used whenever a comparison has to be made between one
10707 * hw state and multiple sw state variables.
10708 */
10709 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10710 if ((current_config->name != pipe_config->name) && \
10711 (current_config->alt_name != pipe_config->name)) { \
10712 DRM_ERROR("mismatch in " #name " " \
10713 "(expected %i or %i, found %i)\n", \
10714 current_config->name, \
10715 current_config->alt_name, \
10716 pipe_config->name); \
10717 return false; \
10718 }
10719
10720 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10721 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10722 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10723 "(expected %i, found %i)\n", \
10724 current_config->name & (mask), \
10725 pipe_config->name & (mask)); \
10726 return false; \
10727 }
10728
10729 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10730 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10731 DRM_ERROR("mismatch in " #name " " \
10732 "(expected %i, found %i)\n", \
10733 current_config->name, \
10734 pipe_config->name); \
10735 return false; \
10736 }
10737
10738 #define PIPE_CONF_QUIRK(quirk) \
10739 ((current_config->quirks | pipe_config->quirks) & (quirk))
10740
10741 PIPE_CONF_CHECK_I(cpu_transcoder);
10742
10743 PIPE_CONF_CHECK_I(has_pch_encoder);
10744 PIPE_CONF_CHECK_I(fdi_lanes);
10745 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10746 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10747 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10748 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10749 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10750
10751 PIPE_CONF_CHECK_I(has_dp_encoder);
10752
10753 if (INTEL_INFO(dev)->gen < 8) {
10754 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10755 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10756 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10757 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10758 PIPE_CONF_CHECK_I(dp_m_n.tu);
10759
10760 if (current_config->has_drrs) {
10761 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10762 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10763 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10764 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10765 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10766 }
10767 } else {
10768 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10769 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10770 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10771 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10772 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10773 }
10774
10775 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10776 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10777 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10778 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10779 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10780 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10781
10782 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10783 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10784 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10785 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10786 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10787 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10788
10789 PIPE_CONF_CHECK_I(pixel_multiplier);
10790 PIPE_CONF_CHECK_I(has_hdmi_sink);
10791 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10792 IS_VALLEYVIEW(dev))
10793 PIPE_CONF_CHECK_I(limited_color_range);
10794 PIPE_CONF_CHECK_I(has_infoframe);
10795
10796 PIPE_CONF_CHECK_I(has_audio);
10797
10798 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10799 DRM_MODE_FLAG_INTERLACE);
10800
10801 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10802 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10803 DRM_MODE_FLAG_PHSYNC);
10804 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10805 DRM_MODE_FLAG_NHSYNC);
10806 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10807 DRM_MODE_FLAG_PVSYNC);
10808 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10809 DRM_MODE_FLAG_NVSYNC);
10810 }
10811
10812 PIPE_CONF_CHECK_I(pipe_src_w);
10813 PIPE_CONF_CHECK_I(pipe_src_h);
10814
10815 /*
10816 * FIXME: BIOS likes to set up a cloned config with lvds+external
10817 * screen. Since we don't yet re-compute the pipe config when moving
10818 * just the lvds port away to another pipe the sw tracking won't match.
10819 *
10820 * Proper atomic modesets with recomputed global state will fix this.
10821 * Until then just don't check gmch state for inherited modes.
10822 */
10823 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10824 PIPE_CONF_CHECK_I(gmch_pfit.control);
10825 /* pfit ratios are autocomputed by the hw on gen4+ */
10826 if (INTEL_INFO(dev)->gen < 4)
10827 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10828 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10829 }
10830
10831 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10832 if (current_config->pch_pfit.enabled) {
10833 PIPE_CONF_CHECK_I(pch_pfit.pos);
10834 PIPE_CONF_CHECK_I(pch_pfit.size);
10835 }
10836
10837 /* BDW+ don't expose a synchronous way to read the state */
10838 if (IS_HASWELL(dev))
10839 PIPE_CONF_CHECK_I(ips_enabled);
10840
10841 PIPE_CONF_CHECK_I(double_wide);
10842
10843 PIPE_CONF_CHECK_X(ddi_pll_sel);
10844
10845 PIPE_CONF_CHECK_I(shared_dpll);
10846 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10847 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10848 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10849 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10850 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10851 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10852 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10853 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10854
10855 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10856 PIPE_CONF_CHECK_I(pipe_bpp);
10857
10858 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10859 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10860
10861 #undef PIPE_CONF_CHECK_X
10862 #undef PIPE_CONF_CHECK_I
10863 #undef PIPE_CONF_CHECK_I_ALT
10864 #undef PIPE_CONF_CHECK_FLAGS
10865 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10866 #undef PIPE_CONF_QUIRK
10867
10868 return true;
10869 }
10870
10871 static void check_wm_state(struct drm_device *dev)
10872 {
10873 struct drm_i915_private *dev_priv = dev->dev_private;
10874 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10875 struct intel_crtc *intel_crtc;
10876 int plane;
10877
10878 if (INTEL_INFO(dev)->gen < 9)
10879 return;
10880
10881 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10882 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10883
10884 for_each_intel_crtc(dev, intel_crtc) {
10885 struct skl_ddb_entry *hw_entry, *sw_entry;
10886 const enum pipe pipe = intel_crtc->pipe;
10887
10888 if (!intel_crtc->active)
10889 continue;
10890
10891 /* planes */
10892 for_each_plane(dev_priv, pipe, plane) {
10893 hw_entry = &hw_ddb.plane[pipe][plane];
10894 sw_entry = &sw_ddb->plane[pipe][plane];
10895
10896 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10897 continue;
10898
10899 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10900 "(expected (%u,%u), found (%u,%u))\n",
10901 pipe_name(pipe), plane + 1,
10902 sw_entry->start, sw_entry->end,
10903 hw_entry->start, hw_entry->end);
10904 }
10905
10906 /* cursor */
10907 hw_entry = &hw_ddb.cursor[pipe];
10908 sw_entry = &sw_ddb->cursor[pipe];
10909
10910 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10911 continue;
10912
10913 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10914 "(expected (%u,%u), found (%u,%u))\n",
10915 pipe_name(pipe),
10916 sw_entry->start, sw_entry->end,
10917 hw_entry->start, hw_entry->end);
10918 }
10919 }
10920
10921 static void
10922 check_connector_state(struct drm_device *dev)
10923 {
10924 struct intel_connector *connector;
10925
10926 for_each_intel_connector(dev, connector) {
10927 /* This also checks the encoder/connector hw state with the
10928 * ->get_hw_state callbacks. */
10929 intel_connector_check_state(connector);
10930
10931 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10932 "connector's staged encoder doesn't match current encoder\n");
10933 }
10934 }
10935
10936 static void
10937 check_encoder_state(struct drm_device *dev)
10938 {
10939 struct intel_encoder *encoder;
10940 struct intel_connector *connector;
10941
10942 for_each_intel_encoder(dev, encoder) {
10943 bool enabled = false;
10944 bool active = false;
10945 enum pipe pipe, tracked_pipe;
10946
10947 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10948 encoder->base.base.id,
10949 encoder->base.name);
10950
10951 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10952 "encoder's stage crtc doesn't match current crtc\n");
10953 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10954 "encoder's active_connectors set, but no crtc\n");
10955
10956 for_each_intel_connector(dev, connector) {
10957 if (connector->base.encoder != &encoder->base)
10958 continue;
10959 enabled = true;
10960 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10961 active = true;
10962 }
10963 /*
10964 * for MST connectors if we unplug the connector is gone
10965 * away but the encoder is still connected to a crtc
10966 * until a modeset happens in response to the hotplug.
10967 */
10968 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10969 continue;
10970
10971 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10972 "encoder's enabled state mismatch "
10973 "(expected %i, found %i)\n",
10974 !!encoder->base.crtc, enabled);
10975 I915_STATE_WARN(active && !encoder->base.crtc,
10976 "active encoder with no crtc\n");
10977
10978 I915_STATE_WARN(encoder->connectors_active != active,
10979 "encoder's computed active state doesn't match tracked active state "
10980 "(expected %i, found %i)\n", active, encoder->connectors_active);
10981
10982 active = encoder->get_hw_state(encoder, &pipe);
10983 I915_STATE_WARN(active != encoder->connectors_active,
10984 "encoder's hw state doesn't match sw tracking "
10985 "(expected %i, found %i)\n",
10986 encoder->connectors_active, active);
10987
10988 if (!encoder->base.crtc)
10989 continue;
10990
10991 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10992 I915_STATE_WARN(active && pipe != tracked_pipe,
10993 "active encoder's pipe doesn't match"
10994 "(expected %i, found %i)\n",
10995 tracked_pipe, pipe);
10996
10997 }
10998 }
10999
11000 static void
11001 check_crtc_state(struct drm_device *dev)
11002 {
11003 struct drm_i915_private *dev_priv = dev->dev_private;
11004 struct intel_crtc *crtc;
11005 struct intel_encoder *encoder;
11006 struct intel_crtc_state pipe_config;
11007
11008 for_each_intel_crtc(dev, crtc) {
11009 bool enabled = false;
11010 bool active = false;
11011
11012 memset(&pipe_config, 0, sizeof(pipe_config));
11013
11014 DRM_DEBUG_KMS("[CRTC:%d]\n",
11015 crtc->base.base.id);
11016
11017 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11018 "active crtc, but not enabled in sw tracking\n");
11019
11020 for_each_intel_encoder(dev, encoder) {
11021 if (encoder->base.crtc != &crtc->base)
11022 continue;
11023 enabled = true;
11024 if (encoder->connectors_active)
11025 active = true;
11026 }
11027
11028 I915_STATE_WARN(active != crtc->active,
11029 "crtc's computed active state doesn't match tracked active state "
11030 "(expected %i, found %i)\n", active, crtc->active);
11031 I915_STATE_WARN(enabled != crtc->base.state->enable,
11032 "crtc's computed enabled state doesn't match tracked enabled state "
11033 "(expected %i, found %i)\n", enabled,
11034 crtc->base.state->enable);
11035
11036 active = dev_priv->display.get_pipe_config(crtc,
11037 &pipe_config);
11038
11039 /* hw state is inconsistent with the pipe quirk */
11040 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11041 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11042 active = crtc->active;
11043
11044 for_each_intel_encoder(dev, encoder) {
11045 enum pipe pipe;
11046 if (encoder->base.crtc != &crtc->base)
11047 continue;
11048 if (encoder->get_hw_state(encoder, &pipe))
11049 encoder->get_config(encoder, &pipe_config);
11050 }
11051
11052 I915_STATE_WARN(crtc->active != active,
11053 "crtc active state doesn't match with hw state "
11054 "(expected %i, found %i)\n", crtc->active, active);
11055
11056 if (active &&
11057 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11058 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11059 intel_dump_pipe_config(crtc, &pipe_config,
11060 "[hw state]");
11061 intel_dump_pipe_config(crtc, crtc->config,
11062 "[sw state]");
11063 }
11064 }
11065 }
11066
11067 static void
11068 check_shared_dpll_state(struct drm_device *dev)
11069 {
11070 struct drm_i915_private *dev_priv = dev->dev_private;
11071 struct intel_crtc *crtc;
11072 struct intel_dpll_hw_state dpll_hw_state;
11073 int i;
11074
11075 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11076 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11077 int enabled_crtcs = 0, active_crtcs = 0;
11078 bool active;
11079
11080 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11081
11082 DRM_DEBUG_KMS("%s\n", pll->name);
11083
11084 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11085
11086 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11087 "more active pll users than references: %i vs %i\n",
11088 pll->active, hweight32(pll->config.crtc_mask));
11089 I915_STATE_WARN(pll->active && !pll->on,
11090 "pll in active use but not on in sw tracking\n");
11091 I915_STATE_WARN(pll->on && !pll->active,
11092 "pll in on but not on in use in sw tracking\n");
11093 I915_STATE_WARN(pll->on != active,
11094 "pll on state mismatch (expected %i, found %i)\n",
11095 pll->on, active);
11096
11097 for_each_intel_crtc(dev, crtc) {
11098 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11099 enabled_crtcs++;
11100 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11101 active_crtcs++;
11102 }
11103 I915_STATE_WARN(pll->active != active_crtcs,
11104 "pll active crtcs mismatch (expected %i, found %i)\n",
11105 pll->active, active_crtcs);
11106 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11107 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11108 hweight32(pll->config.crtc_mask), enabled_crtcs);
11109
11110 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11111 sizeof(dpll_hw_state)),
11112 "pll hw state mismatch\n");
11113 }
11114 }
11115
11116 void
11117 intel_modeset_check_state(struct drm_device *dev)
11118 {
11119 check_wm_state(dev);
11120 check_connector_state(dev);
11121 check_encoder_state(dev);
11122 check_crtc_state(dev);
11123 check_shared_dpll_state(dev);
11124 }
11125
11126 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11127 int dotclock)
11128 {
11129 /*
11130 * FDI already provided one idea for the dotclock.
11131 * Yell if the encoder disagrees.
11132 */
11133 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11134 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11135 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11136 }
11137
11138 static void update_scanline_offset(struct intel_crtc *crtc)
11139 {
11140 struct drm_device *dev = crtc->base.dev;
11141
11142 /*
11143 * The scanline counter increments at the leading edge of hsync.
11144 *
11145 * On most platforms it starts counting from vtotal-1 on the
11146 * first active line. That means the scanline counter value is
11147 * always one less than what we would expect. Ie. just after
11148 * start of vblank, which also occurs at start of hsync (on the
11149 * last active line), the scanline counter will read vblank_start-1.
11150 *
11151 * On gen2 the scanline counter starts counting from 1 instead
11152 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11153 * to keep the value positive), instead of adding one.
11154 *
11155 * On HSW+ the behaviour of the scanline counter depends on the output
11156 * type. For DP ports it behaves like most other platforms, but on HDMI
11157 * there's an extra 1 line difference. So we need to add two instead of
11158 * one to the value.
11159 */
11160 if (IS_GEN2(dev)) {
11161 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11162 int vtotal;
11163
11164 vtotal = mode->crtc_vtotal;
11165 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11166 vtotal /= 2;
11167
11168 crtc->scanline_offset = vtotal - 1;
11169 } else if (HAS_DDI(dev) &&
11170 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11171 crtc->scanline_offset = 2;
11172 } else
11173 crtc->scanline_offset = 1;
11174 }
11175
11176 static struct intel_crtc_state *
11177 intel_modeset_compute_config(struct drm_crtc *crtc,
11178 struct drm_display_mode *mode,
11179 struct drm_framebuffer *fb,
11180 unsigned *modeset_pipes,
11181 unsigned *prepare_pipes,
11182 unsigned *disable_pipes)
11183 {
11184 struct intel_crtc_state *pipe_config = NULL;
11185
11186 intel_modeset_affected_pipes(crtc, modeset_pipes,
11187 prepare_pipes, disable_pipes);
11188
11189 if ((*modeset_pipes) == 0)
11190 goto out;
11191
11192 /*
11193 * Note this needs changes when we start tracking multiple modes
11194 * and crtcs. At that point we'll need to compute the whole config
11195 * (i.e. one pipe_config for each crtc) rather than just the one
11196 * for this crtc.
11197 */
11198 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11199 if (IS_ERR(pipe_config)) {
11200 goto out;
11201 }
11202 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11203 "[modeset]");
11204
11205 out:
11206 return pipe_config;
11207 }
11208
11209 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11210 unsigned modeset_pipes,
11211 unsigned disable_pipes)
11212 {
11213 struct drm_i915_private *dev_priv = to_i915(dev);
11214 unsigned clear_pipes = modeset_pipes | disable_pipes;
11215 struct intel_crtc *intel_crtc;
11216 int ret = 0;
11217
11218 if (!dev_priv->display.crtc_compute_clock)
11219 return 0;
11220
11221 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11222 if (ret)
11223 goto done;
11224
11225 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11226 struct intel_crtc_state *state = intel_crtc->new_config;
11227 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11228 state);
11229 if (ret) {
11230 intel_shared_dpll_abort_config(dev_priv);
11231 goto done;
11232 }
11233 }
11234
11235 done:
11236 return ret;
11237 }
11238
11239 static int __intel_set_mode(struct drm_crtc *crtc,
11240 struct drm_display_mode *mode,
11241 int x, int y, struct drm_framebuffer *fb,
11242 struct intel_crtc_state *pipe_config,
11243 unsigned modeset_pipes,
11244 unsigned prepare_pipes,
11245 unsigned disable_pipes)
11246 {
11247 struct drm_device *dev = crtc->dev;
11248 struct drm_i915_private *dev_priv = dev->dev_private;
11249 struct drm_display_mode *saved_mode;
11250 struct intel_crtc *intel_crtc;
11251 int ret = 0;
11252
11253 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11254 if (!saved_mode)
11255 return -ENOMEM;
11256
11257 *saved_mode = crtc->mode;
11258
11259 if (modeset_pipes)
11260 to_intel_crtc(crtc)->new_config = pipe_config;
11261
11262 /*
11263 * See if the config requires any additional preparation, e.g.
11264 * to adjust global state with pipes off. We need to do this
11265 * here so we can get the modeset_pipe updated config for the new
11266 * mode set on this crtc. For other crtcs we need to use the
11267 * adjusted_mode bits in the crtc directly.
11268 */
11269 if (IS_VALLEYVIEW(dev)) {
11270 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11271
11272 /* may have added more to prepare_pipes than we should */
11273 prepare_pipes &= ~disable_pipes;
11274 }
11275
11276 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11277 if (ret)
11278 goto done;
11279
11280 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11281 intel_crtc_disable(&intel_crtc->base);
11282
11283 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11284 if (intel_crtc->base.state->enable)
11285 dev_priv->display.crtc_disable(&intel_crtc->base);
11286 }
11287
11288 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11289 * to set it here already despite that we pass it down the callchain.
11290 *
11291 * Note we'll need to fix this up when we start tracking multiple
11292 * pipes; here we assume a single modeset_pipe and only track the
11293 * single crtc and mode.
11294 */
11295 if (modeset_pipes) {
11296 crtc->mode = *mode;
11297 /* mode_set/enable/disable functions rely on a correct pipe
11298 * config. */
11299 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11300
11301 /*
11302 * Calculate and store various constants which
11303 * are later needed by vblank and swap-completion
11304 * timestamping. They are derived from true hwmode.
11305 */
11306 drm_calc_timestamping_constants(crtc,
11307 &pipe_config->base.adjusted_mode);
11308 }
11309
11310 /* Only after disabling all output pipelines that will be changed can we
11311 * update the the output configuration. */
11312 intel_modeset_update_state(dev, prepare_pipes);
11313
11314 modeset_update_crtc_power_domains(dev);
11315
11316 /* Set up the DPLL and any encoders state that needs to adjust or depend
11317 * on the DPLL.
11318 */
11319 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11320 struct drm_plane *primary = intel_crtc->base.primary;
11321 int vdisplay, hdisplay;
11322
11323 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11324 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11325 fb, 0, 0,
11326 hdisplay, vdisplay,
11327 x << 16, y << 16,
11328 hdisplay << 16, vdisplay << 16);
11329 }
11330
11331 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11332 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11333 update_scanline_offset(intel_crtc);
11334
11335 dev_priv->display.crtc_enable(&intel_crtc->base);
11336 }
11337
11338 /* FIXME: add subpixel order */
11339 done:
11340 if (ret && crtc->state->enable)
11341 crtc->mode = *saved_mode;
11342
11343 kfree(saved_mode);
11344 return ret;
11345 }
11346
11347 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11348 struct drm_display_mode *mode,
11349 int x, int y, struct drm_framebuffer *fb,
11350 struct intel_crtc_state *pipe_config,
11351 unsigned modeset_pipes,
11352 unsigned prepare_pipes,
11353 unsigned disable_pipes)
11354 {
11355 int ret;
11356
11357 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11358 prepare_pipes, disable_pipes);
11359
11360 if (ret == 0)
11361 intel_modeset_check_state(crtc->dev);
11362
11363 return ret;
11364 }
11365
11366 static int intel_set_mode(struct drm_crtc *crtc,
11367 struct drm_display_mode *mode,
11368 int x, int y, struct drm_framebuffer *fb)
11369 {
11370 struct intel_crtc_state *pipe_config;
11371 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11372
11373 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11374 &modeset_pipes,
11375 &prepare_pipes,
11376 &disable_pipes);
11377
11378 if (IS_ERR(pipe_config))
11379 return PTR_ERR(pipe_config);
11380
11381 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11382 modeset_pipes, prepare_pipes,
11383 disable_pipes);
11384 }
11385
11386 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11387 {
11388 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11389 }
11390
11391 #undef for_each_intel_crtc_masked
11392
11393 static void intel_set_config_free(struct intel_set_config *config)
11394 {
11395 if (!config)
11396 return;
11397
11398 kfree(config->save_connector_encoders);
11399 kfree(config->save_encoder_crtcs);
11400 kfree(config->save_crtc_enabled);
11401 kfree(config);
11402 }
11403
11404 static int intel_set_config_save_state(struct drm_device *dev,
11405 struct intel_set_config *config)
11406 {
11407 struct drm_crtc *crtc;
11408 struct drm_encoder *encoder;
11409 struct drm_connector *connector;
11410 int count;
11411
11412 config->save_crtc_enabled =
11413 kcalloc(dev->mode_config.num_crtc,
11414 sizeof(bool), GFP_KERNEL);
11415 if (!config->save_crtc_enabled)
11416 return -ENOMEM;
11417
11418 config->save_encoder_crtcs =
11419 kcalloc(dev->mode_config.num_encoder,
11420 sizeof(struct drm_crtc *), GFP_KERNEL);
11421 if (!config->save_encoder_crtcs)
11422 return -ENOMEM;
11423
11424 config->save_connector_encoders =
11425 kcalloc(dev->mode_config.num_connector,
11426 sizeof(struct drm_encoder *), GFP_KERNEL);
11427 if (!config->save_connector_encoders)
11428 return -ENOMEM;
11429
11430 /* Copy data. Note that driver private data is not affected.
11431 * Should anything bad happen only the expected state is
11432 * restored, not the drivers personal bookkeeping.
11433 */
11434 count = 0;
11435 for_each_crtc(dev, crtc) {
11436 config->save_crtc_enabled[count++] = crtc->state->enable;
11437 }
11438
11439 count = 0;
11440 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11441 config->save_encoder_crtcs[count++] = encoder->crtc;
11442 }
11443
11444 count = 0;
11445 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11446 config->save_connector_encoders[count++] = connector->encoder;
11447 }
11448
11449 return 0;
11450 }
11451
11452 static void intel_set_config_restore_state(struct drm_device *dev,
11453 struct intel_set_config *config)
11454 {
11455 struct intel_crtc *crtc;
11456 struct intel_encoder *encoder;
11457 struct intel_connector *connector;
11458 int count;
11459
11460 count = 0;
11461 for_each_intel_crtc(dev, crtc) {
11462 crtc->new_enabled = config->save_crtc_enabled[count++];
11463
11464 if (crtc->new_enabled)
11465 crtc->new_config = crtc->config;
11466 else
11467 crtc->new_config = NULL;
11468 }
11469
11470 count = 0;
11471 for_each_intel_encoder(dev, encoder) {
11472 encoder->new_crtc =
11473 to_intel_crtc(config->save_encoder_crtcs[count++]);
11474 }
11475
11476 count = 0;
11477 for_each_intel_connector(dev, connector) {
11478 connector->new_encoder =
11479 to_intel_encoder(config->save_connector_encoders[count++]);
11480 }
11481 }
11482
11483 static bool
11484 is_crtc_connector_off(struct drm_mode_set *set)
11485 {
11486 int i;
11487
11488 if (set->num_connectors == 0)
11489 return false;
11490
11491 if (WARN_ON(set->connectors == NULL))
11492 return false;
11493
11494 for (i = 0; i < set->num_connectors; i++)
11495 if (set->connectors[i]->encoder &&
11496 set->connectors[i]->encoder->crtc == set->crtc &&
11497 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11498 return true;
11499
11500 return false;
11501 }
11502
11503 static void
11504 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11505 struct intel_set_config *config)
11506 {
11507
11508 /* We should be able to check here if the fb has the same properties
11509 * and then just flip_or_move it */
11510 if (is_crtc_connector_off(set)) {
11511 config->mode_changed = true;
11512 } else if (set->crtc->primary->fb != set->fb) {
11513 /*
11514 * If we have no fb, we can only flip as long as the crtc is
11515 * active, otherwise we need a full mode set. The crtc may
11516 * be active if we've only disabled the primary plane, or
11517 * in fastboot situations.
11518 */
11519 if (set->crtc->primary->fb == NULL) {
11520 struct intel_crtc *intel_crtc =
11521 to_intel_crtc(set->crtc);
11522
11523 if (intel_crtc->active) {
11524 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11525 config->fb_changed = true;
11526 } else {
11527 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11528 config->mode_changed = true;
11529 }
11530 } else if (set->fb == NULL) {
11531 config->mode_changed = true;
11532 } else if (set->fb->pixel_format !=
11533 set->crtc->primary->fb->pixel_format) {
11534 config->mode_changed = true;
11535 } else {
11536 config->fb_changed = true;
11537 }
11538 }
11539
11540 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11541 config->fb_changed = true;
11542
11543 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11544 DRM_DEBUG_KMS("modes are different, full mode set\n");
11545 drm_mode_debug_printmodeline(&set->crtc->mode);
11546 drm_mode_debug_printmodeline(set->mode);
11547 config->mode_changed = true;
11548 }
11549
11550 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11551 set->crtc->base.id, config->mode_changed, config->fb_changed);
11552 }
11553
11554 static int
11555 intel_modeset_stage_output_state(struct drm_device *dev,
11556 struct drm_mode_set *set,
11557 struct intel_set_config *config)
11558 {
11559 struct intel_connector *connector;
11560 struct intel_encoder *encoder;
11561 struct intel_crtc *crtc;
11562 int ro;
11563
11564 /* The upper layers ensure that we either disable a crtc or have a list
11565 * of connectors. For paranoia, double-check this. */
11566 WARN_ON(!set->fb && (set->num_connectors != 0));
11567 WARN_ON(set->fb && (set->num_connectors == 0));
11568
11569 for_each_intel_connector(dev, connector) {
11570 /* Otherwise traverse passed in connector list and get encoders
11571 * for them. */
11572 for (ro = 0; ro < set->num_connectors; ro++) {
11573 if (set->connectors[ro] == &connector->base) {
11574 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11575 break;
11576 }
11577 }
11578
11579 /* If we disable the crtc, disable all its connectors. Also, if
11580 * the connector is on the changing crtc but not on the new
11581 * connector list, disable it. */
11582 if ((!set->fb || ro == set->num_connectors) &&
11583 connector->base.encoder &&
11584 connector->base.encoder->crtc == set->crtc) {
11585 connector->new_encoder = NULL;
11586
11587 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11588 connector->base.base.id,
11589 connector->base.name);
11590 }
11591
11592
11593 if (&connector->new_encoder->base != connector->base.encoder) {
11594 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11595 connector->base.base.id,
11596 connector->base.name);
11597 config->mode_changed = true;
11598 }
11599 }
11600 /* connector->new_encoder is now updated for all connectors. */
11601
11602 /* Update crtc of enabled connectors. */
11603 for_each_intel_connector(dev, connector) {
11604 struct drm_crtc *new_crtc;
11605
11606 if (!connector->new_encoder)
11607 continue;
11608
11609 new_crtc = connector->new_encoder->base.crtc;
11610
11611 for (ro = 0; ro < set->num_connectors; ro++) {
11612 if (set->connectors[ro] == &connector->base)
11613 new_crtc = set->crtc;
11614 }
11615
11616 /* Make sure the new CRTC will work with the encoder */
11617 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11618 new_crtc)) {
11619 return -EINVAL;
11620 }
11621 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11622
11623 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11624 connector->base.base.id,
11625 connector->base.name,
11626 new_crtc->base.id);
11627 }
11628
11629 /* Check for any encoders that needs to be disabled. */
11630 for_each_intel_encoder(dev, encoder) {
11631 int num_connectors = 0;
11632 for_each_intel_connector(dev, connector) {
11633 if (connector->new_encoder == encoder) {
11634 WARN_ON(!connector->new_encoder->new_crtc);
11635 num_connectors++;
11636 }
11637 }
11638
11639 if (num_connectors == 0)
11640 encoder->new_crtc = NULL;
11641 else if (num_connectors > 1)
11642 return -EINVAL;
11643
11644 /* Only now check for crtc changes so we don't miss encoders
11645 * that will be disabled. */
11646 if (&encoder->new_crtc->base != encoder->base.crtc) {
11647 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11648 encoder->base.base.id,
11649 encoder->base.name);
11650 config->mode_changed = true;
11651 }
11652 }
11653 /* Now we've also updated encoder->new_crtc for all encoders. */
11654 for_each_intel_connector(dev, connector) {
11655 if (connector->new_encoder)
11656 if (connector->new_encoder != connector->encoder)
11657 connector->encoder = connector->new_encoder;
11658 }
11659 for_each_intel_crtc(dev, crtc) {
11660 crtc->new_enabled = false;
11661
11662 for_each_intel_encoder(dev, encoder) {
11663 if (encoder->new_crtc == crtc) {
11664 crtc->new_enabled = true;
11665 break;
11666 }
11667 }
11668
11669 if (crtc->new_enabled != crtc->base.state->enable) {
11670 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11671 crtc->base.base.id,
11672 crtc->new_enabled ? "en" : "dis");
11673 config->mode_changed = true;
11674 }
11675
11676 if (crtc->new_enabled)
11677 crtc->new_config = crtc->config;
11678 else
11679 crtc->new_config = NULL;
11680 }
11681
11682 return 0;
11683 }
11684
11685 static void disable_crtc_nofb(struct intel_crtc *crtc)
11686 {
11687 struct drm_device *dev = crtc->base.dev;
11688 struct intel_encoder *encoder;
11689 struct intel_connector *connector;
11690
11691 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11692 pipe_name(crtc->pipe));
11693
11694 for_each_intel_connector(dev, connector) {
11695 if (connector->new_encoder &&
11696 connector->new_encoder->new_crtc == crtc)
11697 connector->new_encoder = NULL;
11698 }
11699
11700 for_each_intel_encoder(dev, encoder) {
11701 if (encoder->new_crtc == crtc)
11702 encoder->new_crtc = NULL;
11703 }
11704
11705 crtc->new_enabled = false;
11706 crtc->new_config = NULL;
11707 }
11708
11709 static int intel_crtc_set_config(struct drm_mode_set *set)
11710 {
11711 struct drm_device *dev;
11712 struct drm_mode_set save_set;
11713 struct intel_set_config *config;
11714 struct intel_crtc_state *pipe_config;
11715 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11716 int ret;
11717
11718 BUG_ON(!set);
11719 BUG_ON(!set->crtc);
11720 BUG_ON(!set->crtc->helper_private);
11721
11722 /* Enforce sane interface api - has been abused by the fb helper. */
11723 BUG_ON(!set->mode && set->fb);
11724 BUG_ON(set->fb && set->num_connectors == 0);
11725
11726 if (set->fb) {
11727 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11728 set->crtc->base.id, set->fb->base.id,
11729 (int)set->num_connectors, set->x, set->y);
11730 } else {
11731 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11732 }
11733
11734 dev = set->crtc->dev;
11735
11736 ret = -ENOMEM;
11737 config = kzalloc(sizeof(*config), GFP_KERNEL);
11738 if (!config)
11739 goto out_config;
11740
11741 ret = intel_set_config_save_state(dev, config);
11742 if (ret)
11743 goto out_config;
11744
11745 save_set.crtc = set->crtc;
11746 save_set.mode = &set->crtc->mode;
11747 save_set.x = set->crtc->x;
11748 save_set.y = set->crtc->y;
11749 save_set.fb = set->crtc->primary->fb;
11750
11751 /* Compute whether we need a full modeset, only an fb base update or no
11752 * change at all. In the future we might also check whether only the
11753 * mode changed, e.g. for LVDS where we only change the panel fitter in
11754 * such cases. */
11755 intel_set_config_compute_mode_changes(set, config);
11756
11757 ret = intel_modeset_stage_output_state(dev, set, config);
11758 if (ret)
11759 goto fail;
11760
11761 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11762 set->fb,
11763 &modeset_pipes,
11764 &prepare_pipes,
11765 &disable_pipes);
11766 if (IS_ERR(pipe_config)) {
11767 ret = PTR_ERR(pipe_config);
11768 goto fail;
11769 } else if (pipe_config) {
11770 if (pipe_config->has_audio !=
11771 to_intel_crtc(set->crtc)->config->has_audio)
11772 config->mode_changed = true;
11773
11774 /*
11775 * Note we have an issue here with infoframes: current code
11776 * only updates them on the full mode set path per hw
11777 * requirements. So here we should be checking for any
11778 * required changes and forcing a mode set.
11779 */
11780 }
11781
11782 /* set_mode will free it in the mode_changed case */
11783 if (!config->mode_changed)
11784 kfree(pipe_config);
11785
11786 intel_update_pipe_size(to_intel_crtc(set->crtc));
11787
11788 if (config->mode_changed) {
11789 ret = intel_set_mode_pipes(set->crtc, set->mode,
11790 set->x, set->y, set->fb, pipe_config,
11791 modeset_pipes, prepare_pipes,
11792 disable_pipes);
11793 } else if (config->fb_changed) {
11794 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11795 struct drm_plane *primary = set->crtc->primary;
11796 int vdisplay, hdisplay;
11797
11798 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11799 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11800 0, 0, hdisplay, vdisplay,
11801 set->x << 16, set->y << 16,
11802 hdisplay << 16, vdisplay << 16);
11803
11804 /*
11805 * We need to make sure the primary plane is re-enabled if it
11806 * has previously been turned off.
11807 */
11808 if (!intel_crtc->primary_enabled && ret == 0) {
11809 WARN_ON(!intel_crtc->active);
11810 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11811 }
11812
11813 /*
11814 * In the fastboot case this may be our only check of the
11815 * state after boot. It would be better to only do it on
11816 * the first update, but we don't have a nice way of doing that
11817 * (and really, set_config isn't used much for high freq page
11818 * flipping, so increasing its cost here shouldn't be a big
11819 * deal).
11820 */
11821 if (i915.fastboot && ret == 0)
11822 intel_modeset_check_state(set->crtc->dev);
11823 }
11824
11825 if (ret) {
11826 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11827 set->crtc->base.id, ret);
11828 fail:
11829 intel_set_config_restore_state(dev, config);
11830
11831 /*
11832 * HACK: if the pipe was on, but we didn't have a framebuffer,
11833 * force the pipe off to avoid oopsing in the modeset code
11834 * due to fb==NULL. This should only happen during boot since
11835 * we don't yet reconstruct the FB from the hardware state.
11836 */
11837 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11838 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11839
11840 /* Try to restore the config */
11841 if (config->mode_changed &&
11842 intel_set_mode(save_set.crtc, save_set.mode,
11843 save_set.x, save_set.y, save_set.fb))
11844 DRM_ERROR("failed to restore config after modeset failure\n");
11845 }
11846
11847 out_config:
11848 intel_set_config_free(config);
11849 return ret;
11850 }
11851
11852 static const struct drm_crtc_funcs intel_crtc_funcs = {
11853 .gamma_set = intel_crtc_gamma_set,
11854 .set_config = intel_crtc_set_config,
11855 .destroy = intel_crtc_destroy,
11856 .page_flip = intel_crtc_page_flip,
11857 .atomic_duplicate_state = intel_crtc_duplicate_state,
11858 .atomic_destroy_state = intel_crtc_destroy_state,
11859 };
11860
11861 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11862 struct intel_shared_dpll *pll,
11863 struct intel_dpll_hw_state *hw_state)
11864 {
11865 uint32_t val;
11866
11867 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11868 return false;
11869
11870 val = I915_READ(PCH_DPLL(pll->id));
11871 hw_state->dpll = val;
11872 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11873 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11874
11875 return val & DPLL_VCO_ENABLE;
11876 }
11877
11878 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11879 struct intel_shared_dpll *pll)
11880 {
11881 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11882 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11883 }
11884
11885 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11886 struct intel_shared_dpll *pll)
11887 {
11888 /* PCH refclock must be enabled first */
11889 ibx_assert_pch_refclk_enabled(dev_priv);
11890
11891 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11892
11893 /* Wait for the clocks to stabilize. */
11894 POSTING_READ(PCH_DPLL(pll->id));
11895 udelay(150);
11896
11897 /* The pixel multiplier can only be updated once the
11898 * DPLL is enabled and the clocks are stable.
11899 *
11900 * So write it again.
11901 */
11902 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11903 POSTING_READ(PCH_DPLL(pll->id));
11904 udelay(200);
11905 }
11906
11907 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11908 struct intel_shared_dpll *pll)
11909 {
11910 struct drm_device *dev = dev_priv->dev;
11911 struct intel_crtc *crtc;
11912
11913 /* Make sure no transcoder isn't still depending on us. */
11914 for_each_intel_crtc(dev, crtc) {
11915 if (intel_crtc_to_shared_dpll(crtc) == pll)
11916 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11917 }
11918
11919 I915_WRITE(PCH_DPLL(pll->id), 0);
11920 POSTING_READ(PCH_DPLL(pll->id));
11921 udelay(200);
11922 }
11923
11924 static char *ibx_pch_dpll_names[] = {
11925 "PCH DPLL A",
11926 "PCH DPLL B",
11927 };
11928
11929 static void ibx_pch_dpll_init(struct drm_device *dev)
11930 {
11931 struct drm_i915_private *dev_priv = dev->dev_private;
11932 int i;
11933
11934 dev_priv->num_shared_dpll = 2;
11935
11936 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11937 dev_priv->shared_dplls[i].id = i;
11938 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11939 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11940 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11941 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11942 dev_priv->shared_dplls[i].get_hw_state =
11943 ibx_pch_dpll_get_hw_state;
11944 }
11945 }
11946
11947 static void intel_shared_dpll_init(struct drm_device *dev)
11948 {
11949 struct drm_i915_private *dev_priv = dev->dev_private;
11950
11951 if (HAS_DDI(dev))
11952 intel_ddi_pll_init(dev);
11953 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11954 ibx_pch_dpll_init(dev);
11955 else
11956 dev_priv->num_shared_dpll = 0;
11957
11958 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11959 }
11960
11961 /**
11962 * intel_prepare_plane_fb - Prepare fb for usage on plane
11963 * @plane: drm plane to prepare for
11964 * @fb: framebuffer to prepare for presentation
11965 *
11966 * Prepares a framebuffer for usage on a display plane. Generally this
11967 * involves pinning the underlying object and updating the frontbuffer tracking
11968 * bits. Some older platforms need special physical address handling for
11969 * cursor planes.
11970 *
11971 * Returns 0 on success, negative error code on failure.
11972 */
11973 int
11974 intel_prepare_plane_fb(struct drm_plane *plane,
11975 struct drm_framebuffer *fb,
11976 const struct drm_plane_state *new_state)
11977 {
11978 struct drm_device *dev = plane->dev;
11979 struct intel_plane *intel_plane = to_intel_plane(plane);
11980 enum pipe pipe = intel_plane->pipe;
11981 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11982 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11983 unsigned frontbuffer_bits = 0;
11984 int ret = 0;
11985
11986 if (!obj)
11987 return 0;
11988
11989 switch (plane->type) {
11990 case DRM_PLANE_TYPE_PRIMARY:
11991 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11992 break;
11993 case DRM_PLANE_TYPE_CURSOR:
11994 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11995 break;
11996 case DRM_PLANE_TYPE_OVERLAY:
11997 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11998 break;
11999 }
12000
12001 mutex_lock(&dev->struct_mutex);
12002
12003 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12004 INTEL_INFO(dev)->cursor_needs_physical) {
12005 int align = IS_I830(dev) ? 16 * 1024 : 256;
12006 ret = i915_gem_object_attach_phys(obj, align);
12007 if (ret)
12008 DRM_DEBUG_KMS("failed to attach phys object\n");
12009 } else {
12010 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
12011 }
12012
12013 if (ret == 0)
12014 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12015
12016 mutex_unlock(&dev->struct_mutex);
12017
12018 return ret;
12019 }
12020
12021 /**
12022 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12023 * @plane: drm plane to clean up for
12024 * @fb: old framebuffer that was on plane
12025 *
12026 * Cleans up a framebuffer that has just been removed from a plane.
12027 */
12028 void
12029 intel_cleanup_plane_fb(struct drm_plane *plane,
12030 struct drm_framebuffer *fb,
12031 const struct drm_plane_state *old_state)
12032 {
12033 struct drm_device *dev = plane->dev;
12034 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12035
12036 if (WARN_ON(!obj))
12037 return;
12038
12039 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12040 !INTEL_INFO(dev)->cursor_needs_physical) {
12041 mutex_lock(&dev->struct_mutex);
12042 intel_unpin_fb_obj(obj);
12043 mutex_unlock(&dev->struct_mutex);
12044 }
12045 }
12046
12047 static int
12048 intel_check_primary_plane(struct drm_plane *plane,
12049 struct intel_plane_state *state)
12050 {
12051 struct drm_device *dev = plane->dev;
12052 struct drm_i915_private *dev_priv = dev->dev_private;
12053 struct drm_crtc *crtc = state->base.crtc;
12054 struct intel_crtc *intel_crtc;
12055 struct drm_framebuffer *fb = state->base.fb;
12056 struct drm_rect *dest = &state->dst;
12057 struct drm_rect *src = &state->src;
12058 const struct drm_rect *clip = &state->clip;
12059 int ret;
12060
12061 crtc = crtc ? crtc : plane->crtc;
12062 intel_crtc = to_intel_crtc(crtc);
12063
12064 ret = drm_plane_helper_check_update(plane, crtc, fb,
12065 src, dest, clip,
12066 DRM_PLANE_HELPER_NO_SCALING,
12067 DRM_PLANE_HELPER_NO_SCALING,
12068 false, true, &state->visible);
12069 if (ret)
12070 return ret;
12071
12072 if (intel_crtc->active) {
12073 intel_crtc->atomic.wait_for_flips = true;
12074
12075 /*
12076 * FBC does not work on some platforms for rotated
12077 * planes, so disable it when rotation is not 0 and
12078 * update it when rotation is set back to 0.
12079 *
12080 * FIXME: This is redundant with the fbc update done in
12081 * the primary plane enable function except that that
12082 * one is done too late. We eventually need to unify
12083 * this.
12084 */
12085 if (intel_crtc->primary_enabled &&
12086 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12087 dev_priv->fbc.crtc == intel_crtc &&
12088 state->base.rotation != BIT(DRM_ROTATE_0)) {
12089 intel_crtc->atomic.disable_fbc = true;
12090 }
12091
12092 if (state->visible) {
12093 /*
12094 * BDW signals flip done immediately if the plane
12095 * is disabled, even if the plane enable is already
12096 * armed to occur at the next vblank :(
12097 */
12098 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12099 intel_crtc->atomic.wait_vblank = true;
12100 }
12101
12102 intel_crtc->atomic.fb_bits |=
12103 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12104
12105 intel_crtc->atomic.update_fbc = true;
12106
12107 /* Update watermarks on tiling changes. */
12108 if (!plane->state->fb || !state->base.fb ||
12109 plane->state->fb->modifier[0] !=
12110 state->base.fb->modifier[0])
12111 intel_crtc->atomic.update_wm = true;
12112 }
12113
12114 return 0;
12115 }
12116
12117 static void
12118 intel_commit_primary_plane(struct drm_plane *plane,
12119 struct intel_plane_state *state)
12120 {
12121 struct drm_crtc *crtc = state->base.crtc;
12122 struct drm_framebuffer *fb = state->base.fb;
12123 struct drm_device *dev = plane->dev;
12124 struct drm_i915_private *dev_priv = dev->dev_private;
12125 struct intel_crtc *intel_crtc;
12126 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12127 struct intel_plane *intel_plane = to_intel_plane(plane);
12128 struct drm_rect *src = &state->src;
12129
12130 crtc = crtc ? crtc : plane->crtc;
12131 intel_crtc = to_intel_crtc(crtc);
12132
12133 plane->fb = fb;
12134 crtc->x = src->x1 >> 16;
12135 crtc->y = src->y1 >> 16;
12136
12137 intel_plane->obj = obj;
12138
12139 if (intel_crtc->active) {
12140 if (state->visible) {
12141 /* FIXME: kill this fastboot hack */
12142 intel_update_pipe_size(intel_crtc);
12143
12144 intel_crtc->primary_enabled = true;
12145
12146 dev_priv->display.update_primary_plane(crtc, plane->fb,
12147 crtc->x, crtc->y);
12148 } else {
12149 /*
12150 * If clipping results in a non-visible primary plane,
12151 * we'll disable the primary plane. Note that this is
12152 * a bit different than what happens if userspace
12153 * explicitly disables the plane by passing fb=0
12154 * because plane->fb still gets set and pinned.
12155 */
12156 intel_disable_primary_hw_plane(plane, crtc);
12157 }
12158 }
12159 }
12160
12161 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12162 {
12163 struct drm_device *dev = crtc->dev;
12164 struct drm_i915_private *dev_priv = dev->dev_private;
12165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12166 struct intel_plane *intel_plane;
12167 struct drm_plane *p;
12168 unsigned fb_bits = 0;
12169
12170 /* Track fb's for any planes being disabled */
12171 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12172 intel_plane = to_intel_plane(p);
12173
12174 if (intel_crtc->atomic.disabled_planes &
12175 (1 << drm_plane_index(p))) {
12176 switch (p->type) {
12177 case DRM_PLANE_TYPE_PRIMARY:
12178 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12179 break;
12180 case DRM_PLANE_TYPE_CURSOR:
12181 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12182 break;
12183 case DRM_PLANE_TYPE_OVERLAY:
12184 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12185 break;
12186 }
12187
12188 mutex_lock(&dev->struct_mutex);
12189 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12190 mutex_unlock(&dev->struct_mutex);
12191 }
12192 }
12193
12194 if (intel_crtc->atomic.wait_for_flips)
12195 intel_crtc_wait_for_pending_flips(crtc);
12196
12197 if (intel_crtc->atomic.disable_fbc)
12198 intel_fbc_disable(dev);
12199
12200 if (intel_crtc->atomic.pre_disable_primary)
12201 intel_pre_disable_primary(crtc);
12202
12203 if (intel_crtc->atomic.update_wm)
12204 intel_update_watermarks(crtc);
12205
12206 intel_runtime_pm_get(dev_priv);
12207
12208 /* Perform vblank evasion around commit operation */
12209 if (intel_crtc->active)
12210 intel_crtc->atomic.evade =
12211 intel_pipe_update_start(intel_crtc,
12212 &intel_crtc->atomic.start_vbl_count);
12213 }
12214
12215 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12216 {
12217 struct drm_device *dev = crtc->dev;
12218 struct drm_i915_private *dev_priv = dev->dev_private;
12219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12220 struct drm_plane *p;
12221
12222 if (intel_crtc->atomic.evade)
12223 intel_pipe_update_end(intel_crtc,
12224 intel_crtc->atomic.start_vbl_count);
12225
12226 intel_runtime_pm_put(dev_priv);
12227
12228 if (intel_crtc->atomic.wait_vblank)
12229 intel_wait_for_vblank(dev, intel_crtc->pipe);
12230
12231 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12232
12233 if (intel_crtc->atomic.update_fbc) {
12234 mutex_lock(&dev->struct_mutex);
12235 intel_fbc_update(dev);
12236 mutex_unlock(&dev->struct_mutex);
12237 }
12238
12239 if (intel_crtc->atomic.post_enable_primary)
12240 intel_post_enable_primary(crtc);
12241
12242 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12243 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12244 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12245 false, false);
12246
12247 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12248 }
12249
12250 /**
12251 * intel_plane_destroy - destroy a plane
12252 * @plane: plane to destroy
12253 *
12254 * Common destruction function for all types of planes (primary, cursor,
12255 * sprite).
12256 */
12257 void intel_plane_destroy(struct drm_plane *plane)
12258 {
12259 struct intel_plane *intel_plane = to_intel_plane(plane);
12260 drm_plane_cleanup(plane);
12261 kfree(intel_plane);
12262 }
12263
12264 const struct drm_plane_funcs intel_plane_funcs = {
12265 .update_plane = drm_plane_helper_update,
12266 .disable_plane = drm_plane_helper_disable,
12267 .destroy = intel_plane_destroy,
12268 .set_property = drm_atomic_helper_plane_set_property,
12269 .atomic_get_property = intel_plane_atomic_get_property,
12270 .atomic_set_property = intel_plane_atomic_set_property,
12271 .atomic_duplicate_state = intel_plane_duplicate_state,
12272 .atomic_destroy_state = intel_plane_destroy_state,
12273
12274 };
12275
12276 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12277 int pipe)
12278 {
12279 struct intel_plane *primary;
12280 struct intel_plane_state *state;
12281 const uint32_t *intel_primary_formats;
12282 int num_formats;
12283
12284 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12285 if (primary == NULL)
12286 return NULL;
12287
12288 state = intel_create_plane_state(&primary->base);
12289 if (!state) {
12290 kfree(primary);
12291 return NULL;
12292 }
12293 primary->base.state = &state->base;
12294
12295 primary->can_scale = false;
12296 primary->max_downscale = 1;
12297 primary->pipe = pipe;
12298 primary->plane = pipe;
12299 primary->check_plane = intel_check_primary_plane;
12300 primary->commit_plane = intel_commit_primary_plane;
12301 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12302 primary->plane = !pipe;
12303
12304 if (INTEL_INFO(dev)->gen <= 3) {
12305 intel_primary_formats = intel_primary_formats_gen2;
12306 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12307 } else {
12308 intel_primary_formats = intel_primary_formats_gen4;
12309 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12310 }
12311
12312 drm_universal_plane_init(dev, &primary->base, 0,
12313 &intel_plane_funcs,
12314 intel_primary_formats, num_formats,
12315 DRM_PLANE_TYPE_PRIMARY);
12316
12317 if (INTEL_INFO(dev)->gen >= 4) {
12318 if (!dev->mode_config.rotation_property)
12319 dev->mode_config.rotation_property =
12320 drm_mode_create_rotation_property(dev,
12321 BIT(DRM_ROTATE_0) |
12322 BIT(DRM_ROTATE_180));
12323 if (dev->mode_config.rotation_property)
12324 drm_object_attach_property(&primary->base.base,
12325 dev->mode_config.rotation_property,
12326 state->base.rotation);
12327 }
12328
12329 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12330
12331 return &primary->base;
12332 }
12333
12334 static int
12335 intel_check_cursor_plane(struct drm_plane *plane,
12336 struct intel_plane_state *state)
12337 {
12338 struct drm_crtc *crtc = state->base.crtc;
12339 struct drm_device *dev = plane->dev;
12340 struct drm_framebuffer *fb = state->base.fb;
12341 struct drm_rect *dest = &state->dst;
12342 struct drm_rect *src = &state->src;
12343 const struct drm_rect *clip = &state->clip;
12344 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12345 struct intel_crtc *intel_crtc;
12346 unsigned stride;
12347 int ret;
12348
12349 crtc = crtc ? crtc : plane->crtc;
12350 intel_crtc = to_intel_crtc(crtc);
12351
12352 ret = drm_plane_helper_check_update(plane, crtc, fb,
12353 src, dest, clip,
12354 DRM_PLANE_HELPER_NO_SCALING,
12355 DRM_PLANE_HELPER_NO_SCALING,
12356 true, true, &state->visible);
12357 if (ret)
12358 return ret;
12359
12360
12361 /* if we want to turn off the cursor ignore width and height */
12362 if (!obj)
12363 goto finish;
12364
12365 /* Check for which cursor types we support */
12366 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12367 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12368 state->base.crtc_w, state->base.crtc_h);
12369 return -EINVAL;
12370 }
12371
12372 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12373 if (obj->base.size < stride * state->base.crtc_h) {
12374 DRM_DEBUG_KMS("buffer is too small\n");
12375 return -ENOMEM;
12376 }
12377
12378 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12379 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12380 ret = -EINVAL;
12381 }
12382
12383 finish:
12384 if (intel_crtc->active) {
12385 if (intel_crtc->base.cursor->state->crtc_w != state->base.crtc_w)
12386 intel_crtc->atomic.update_wm = true;
12387
12388 intel_crtc->atomic.fb_bits |=
12389 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12390 }
12391
12392 return ret;
12393 }
12394
12395 static void
12396 intel_commit_cursor_plane(struct drm_plane *plane,
12397 struct intel_plane_state *state)
12398 {
12399 struct drm_crtc *crtc = state->base.crtc;
12400 struct drm_device *dev = plane->dev;
12401 struct intel_crtc *intel_crtc;
12402 struct intel_plane *intel_plane = to_intel_plane(plane);
12403 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12404 uint32_t addr;
12405
12406 crtc = crtc ? crtc : plane->crtc;
12407 intel_crtc = to_intel_crtc(crtc);
12408
12409 plane->fb = state->base.fb;
12410 crtc->cursor_x = state->base.crtc_x;
12411 crtc->cursor_y = state->base.crtc_y;
12412
12413 intel_plane->obj = obj;
12414
12415 if (intel_crtc->cursor_bo == obj)
12416 goto update;
12417
12418 if (!obj)
12419 addr = 0;
12420 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12421 addr = i915_gem_obj_ggtt_offset(obj);
12422 else
12423 addr = obj->phys_handle->busaddr;
12424
12425 intel_crtc->cursor_addr = addr;
12426 intel_crtc->cursor_bo = obj;
12427 update:
12428
12429 if (intel_crtc->active)
12430 intel_crtc_update_cursor(crtc, state->visible);
12431 }
12432
12433 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12434 int pipe)
12435 {
12436 struct intel_plane *cursor;
12437 struct intel_plane_state *state;
12438
12439 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12440 if (cursor == NULL)
12441 return NULL;
12442
12443 state = intel_create_plane_state(&cursor->base);
12444 if (!state) {
12445 kfree(cursor);
12446 return NULL;
12447 }
12448 cursor->base.state = &state->base;
12449
12450 cursor->can_scale = false;
12451 cursor->max_downscale = 1;
12452 cursor->pipe = pipe;
12453 cursor->plane = pipe;
12454 cursor->check_plane = intel_check_cursor_plane;
12455 cursor->commit_plane = intel_commit_cursor_plane;
12456
12457 drm_universal_plane_init(dev, &cursor->base, 0,
12458 &intel_plane_funcs,
12459 intel_cursor_formats,
12460 ARRAY_SIZE(intel_cursor_formats),
12461 DRM_PLANE_TYPE_CURSOR);
12462
12463 if (INTEL_INFO(dev)->gen >= 4) {
12464 if (!dev->mode_config.rotation_property)
12465 dev->mode_config.rotation_property =
12466 drm_mode_create_rotation_property(dev,
12467 BIT(DRM_ROTATE_0) |
12468 BIT(DRM_ROTATE_180));
12469 if (dev->mode_config.rotation_property)
12470 drm_object_attach_property(&cursor->base.base,
12471 dev->mode_config.rotation_property,
12472 state->base.rotation);
12473 }
12474
12475 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12476
12477 return &cursor->base;
12478 }
12479
12480 static void intel_crtc_init(struct drm_device *dev, int pipe)
12481 {
12482 struct drm_i915_private *dev_priv = dev->dev_private;
12483 struct intel_crtc *intel_crtc;
12484 struct intel_crtc_state *crtc_state = NULL;
12485 struct drm_plane *primary = NULL;
12486 struct drm_plane *cursor = NULL;
12487 int i, ret;
12488
12489 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12490 if (intel_crtc == NULL)
12491 return;
12492
12493 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12494 if (!crtc_state)
12495 goto fail;
12496 intel_crtc_set_state(intel_crtc, crtc_state);
12497 crtc_state->base.crtc = &intel_crtc->base;
12498
12499 primary = intel_primary_plane_create(dev, pipe);
12500 if (!primary)
12501 goto fail;
12502
12503 cursor = intel_cursor_plane_create(dev, pipe);
12504 if (!cursor)
12505 goto fail;
12506
12507 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12508 cursor, &intel_crtc_funcs);
12509 if (ret)
12510 goto fail;
12511
12512 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12513 for (i = 0; i < 256; i++) {
12514 intel_crtc->lut_r[i] = i;
12515 intel_crtc->lut_g[i] = i;
12516 intel_crtc->lut_b[i] = i;
12517 }
12518
12519 /*
12520 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12521 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12522 */
12523 intel_crtc->pipe = pipe;
12524 intel_crtc->plane = pipe;
12525 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12526 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12527 intel_crtc->plane = !pipe;
12528 }
12529
12530 intel_crtc->cursor_base = ~0;
12531 intel_crtc->cursor_cntl = ~0;
12532 intel_crtc->cursor_size = ~0;
12533
12534 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12535 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12536 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12537 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12538
12539 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12540
12541 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12542
12543 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12544 return;
12545
12546 fail:
12547 if (primary)
12548 drm_plane_cleanup(primary);
12549 if (cursor)
12550 drm_plane_cleanup(cursor);
12551 kfree(crtc_state);
12552 kfree(intel_crtc);
12553 }
12554
12555 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12556 {
12557 struct drm_encoder *encoder = connector->base.encoder;
12558 struct drm_device *dev = connector->base.dev;
12559
12560 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12561
12562 if (!encoder || WARN_ON(!encoder->crtc))
12563 return INVALID_PIPE;
12564
12565 return to_intel_crtc(encoder->crtc)->pipe;
12566 }
12567
12568 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12569 struct drm_file *file)
12570 {
12571 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12572 struct drm_crtc *drmmode_crtc;
12573 struct intel_crtc *crtc;
12574
12575 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12576
12577 if (!drmmode_crtc) {
12578 DRM_ERROR("no such CRTC id\n");
12579 return -ENOENT;
12580 }
12581
12582 crtc = to_intel_crtc(drmmode_crtc);
12583 pipe_from_crtc_id->pipe = crtc->pipe;
12584
12585 return 0;
12586 }
12587
12588 static int intel_encoder_clones(struct intel_encoder *encoder)
12589 {
12590 struct drm_device *dev = encoder->base.dev;
12591 struct intel_encoder *source_encoder;
12592 int index_mask = 0;
12593 int entry = 0;
12594
12595 for_each_intel_encoder(dev, source_encoder) {
12596 if (encoders_cloneable(encoder, source_encoder))
12597 index_mask |= (1 << entry);
12598
12599 entry++;
12600 }
12601
12602 return index_mask;
12603 }
12604
12605 static bool has_edp_a(struct drm_device *dev)
12606 {
12607 struct drm_i915_private *dev_priv = dev->dev_private;
12608
12609 if (!IS_MOBILE(dev))
12610 return false;
12611
12612 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12613 return false;
12614
12615 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12616 return false;
12617
12618 return true;
12619 }
12620
12621 static bool intel_crt_present(struct drm_device *dev)
12622 {
12623 struct drm_i915_private *dev_priv = dev->dev_private;
12624
12625 if (INTEL_INFO(dev)->gen >= 9)
12626 return false;
12627
12628 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12629 return false;
12630
12631 if (IS_CHERRYVIEW(dev))
12632 return false;
12633
12634 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12635 return false;
12636
12637 return true;
12638 }
12639
12640 static void intel_setup_outputs(struct drm_device *dev)
12641 {
12642 struct drm_i915_private *dev_priv = dev->dev_private;
12643 struct intel_encoder *encoder;
12644 struct drm_connector *connector;
12645 bool dpd_is_edp = false;
12646
12647 intel_lvds_init(dev);
12648
12649 if (intel_crt_present(dev))
12650 intel_crt_init(dev);
12651
12652 if (HAS_DDI(dev)) {
12653 int found;
12654
12655 /*
12656 * Haswell uses DDI functions to detect digital outputs.
12657 * On SKL pre-D0 the strap isn't connected, so we assume
12658 * it's there.
12659 */
12660 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12661 /* WaIgnoreDDIAStrap: skl */
12662 if (found ||
12663 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12664 intel_ddi_init(dev, PORT_A);
12665
12666 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12667 * register */
12668 found = I915_READ(SFUSE_STRAP);
12669
12670 if (found & SFUSE_STRAP_DDIB_DETECTED)
12671 intel_ddi_init(dev, PORT_B);
12672 if (found & SFUSE_STRAP_DDIC_DETECTED)
12673 intel_ddi_init(dev, PORT_C);
12674 if (found & SFUSE_STRAP_DDID_DETECTED)
12675 intel_ddi_init(dev, PORT_D);
12676 } else if (HAS_PCH_SPLIT(dev)) {
12677 int found;
12678 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12679
12680 if (has_edp_a(dev))
12681 intel_dp_init(dev, DP_A, PORT_A);
12682
12683 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12684 /* PCH SDVOB multiplex with HDMIB */
12685 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12686 if (!found)
12687 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12688 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12689 intel_dp_init(dev, PCH_DP_B, PORT_B);
12690 }
12691
12692 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12693 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12694
12695 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12696 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12697
12698 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12699 intel_dp_init(dev, PCH_DP_C, PORT_C);
12700
12701 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12702 intel_dp_init(dev, PCH_DP_D, PORT_D);
12703 } else if (IS_VALLEYVIEW(dev)) {
12704 /*
12705 * The DP_DETECTED bit is the latched state of the DDC
12706 * SDA pin at boot. However since eDP doesn't require DDC
12707 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12708 * eDP ports may have been muxed to an alternate function.
12709 * Thus we can't rely on the DP_DETECTED bit alone to detect
12710 * eDP ports. Consult the VBT as well as DP_DETECTED to
12711 * detect eDP ports.
12712 */
12713 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12714 !intel_dp_is_edp(dev, PORT_B))
12715 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12716 PORT_B);
12717 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12718 intel_dp_is_edp(dev, PORT_B))
12719 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12720
12721 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12722 !intel_dp_is_edp(dev, PORT_C))
12723 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12724 PORT_C);
12725 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12726 intel_dp_is_edp(dev, PORT_C))
12727 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12728
12729 if (IS_CHERRYVIEW(dev)) {
12730 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12731 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12732 PORT_D);
12733 /* eDP not supported on port D, so don't check VBT */
12734 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12735 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12736 }
12737
12738 intel_dsi_init(dev);
12739 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12740 bool found = false;
12741
12742 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12743 DRM_DEBUG_KMS("probing SDVOB\n");
12744 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12745 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12746 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12747 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12748 }
12749
12750 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12751 intel_dp_init(dev, DP_B, PORT_B);
12752 }
12753
12754 /* Before G4X SDVOC doesn't have its own detect register */
12755
12756 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12757 DRM_DEBUG_KMS("probing SDVOC\n");
12758 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12759 }
12760
12761 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12762
12763 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12764 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12765 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12766 }
12767 if (SUPPORTS_INTEGRATED_DP(dev))
12768 intel_dp_init(dev, DP_C, PORT_C);
12769 }
12770
12771 if (SUPPORTS_INTEGRATED_DP(dev) &&
12772 (I915_READ(DP_D) & DP_DETECTED))
12773 intel_dp_init(dev, DP_D, PORT_D);
12774 } else if (IS_GEN2(dev))
12775 intel_dvo_init(dev);
12776
12777 if (SUPPORTS_TV(dev))
12778 intel_tv_init(dev);
12779
12780 /*
12781 * FIXME: We don't have full atomic support yet, but we want to be
12782 * able to enable/test plane updates via the atomic interface in the
12783 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12784 * will take some atomic codepaths to lookup properties during
12785 * drmModeGetConnector() that unconditionally dereference
12786 * connector->state.
12787 *
12788 * We create a dummy connector state here for each connector to ensure
12789 * the DRM core doesn't try to dereference a NULL connector->state.
12790 * The actual connector properties will never be updated or contain
12791 * useful information, but since we're doing this specifically for
12792 * testing/debug of the plane operations (and only when a specific
12793 * kernel module option is given), that shouldn't really matter.
12794 *
12795 * Once atomic support for crtc's + connectors lands, this loop should
12796 * be removed since we'll be setting up real connector state, which
12797 * will contain Intel-specific properties.
12798 */
12799 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12800 list_for_each_entry(connector,
12801 &dev->mode_config.connector_list,
12802 head) {
12803 if (!WARN_ON(connector->state)) {
12804 connector->state =
12805 kzalloc(sizeof(*connector->state),
12806 GFP_KERNEL);
12807 }
12808 }
12809 }
12810
12811 intel_psr_init(dev);
12812
12813 for_each_intel_encoder(dev, encoder) {
12814 encoder->base.possible_crtcs = encoder->crtc_mask;
12815 encoder->base.possible_clones =
12816 intel_encoder_clones(encoder);
12817 }
12818
12819 intel_init_pch_refclk(dev);
12820
12821 drm_helper_move_panel_connectors_to_head(dev);
12822 }
12823
12824 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12825 {
12826 struct drm_device *dev = fb->dev;
12827 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12828
12829 drm_framebuffer_cleanup(fb);
12830 mutex_lock(&dev->struct_mutex);
12831 WARN_ON(!intel_fb->obj->framebuffer_references--);
12832 drm_gem_object_unreference(&intel_fb->obj->base);
12833 mutex_unlock(&dev->struct_mutex);
12834 kfree(intel_fb);
12835 }
12836
12837 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12838 struct drm_file *file,
12839 unsigned int *handle)
12840 {
12841 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12842 struct drm_i915_gem_object *obj = intel_fb->obj;
12843
12844 return drm_gem_handle_create(file, &obj->base, handle);
12845 }
12846
12847 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12848 .destroy = intel_user_framebuffer_destroy,
12849 .create_handle = intel_user_framebuffer_create_handle,
12850 };
12851
12852 static
12853 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12854 uint32_t pixel_format)
12855 {
12856 u32 gen = INTEL_INFO(dev)->gen;
12857
12858 if (gen >= 9) {
12859 /* "The stride in bytes must not exceed the of the size of 8K
12860 * pixels and 32K bytes."
12861 */
12862 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12863 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12864 return 32*1024;
12865 } else if (gen >= 4) {
12866 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12867 return 16*1024;
12868 else
12869 return 32*1024;
12870 } else if (gen >= 3) {
12871 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12872 return 8*1024;
12873 else
12874 return 16*1024;
12875 } else {
12876 /* XXX DSPC is limited to 4k tiled */
12877 return 8*1024;
12878 }
12879 }
12880
12881 static int intel_framebuffer_init(struct drm_device *dev,
12882 struct intel_framebuffer *intel_fb,
12883 struct drm_mode_fb_cmd2 *mode_cmd,
12884 struct drm_i915_gem_object *obj)
12885 {
12886 int aligned_height;
12887 int ret;
12888 u32 pitch_limit, stride_alignment;
12889
12890 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12891
12892 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12893 /* Enforce that fb modifier and tiling mode match, but only for
12894 * X-tiled. This is needed for FBC. */
12895 if (!!(obj->tiling_mode == I915_TILING_X) !=
12896 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12897 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12898 return -EINVAL;
12899 }
12900 } else {
12901 if (obj->tiling_mode == I915_TILING_X)
12902 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12903 else if (obj->tiling_mode == I915_TILING_Y) {
12904 DRM_DEBUG("No Y tiling for legacy addfb\n");
12905 return -EINVAL;
12906 }
12907 }
12908
12909 /* Passed in modifier sanity checking. */
12910 switch (mode_cmd->modifier[0]) {
12911 case I915_FORMAT_MOD_Y_TILED:
12912 case I915_FORMAT_MOD_Yf_TILED:
12913 if (INTEL_INFO(dev)->gen < 9) {
12914 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12915 mode_cmd->modifier[0]);
12916 return -EINVAL;
12917 }
12918 case DRM_FORMAT_MOD_NONE:
12919 case I915_FORMAT_MOD_X_TILED:
12920 break;
12921 default:
12922 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12923 mode_cmd->modifier[0]);
12924 return -EINVAL;
12925 }
12926
12927 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12928 mode_cmd->pixel_format);
12929 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12930 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12931 mode_cmd->pitches[0], stride_alignment);
12932 return -EINVAL;
12933 }
12934
12935 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12936 mode_cmd->pixel_format);
12937 if (mode_cmd->pitches[0] > pitch_limit) {
12938 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12939 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12940 "tiled" : "linear",
12941 mode_cmd->pitches[0], pitch_limit);
12942 return -EINVAL;
12943 }
12944
12945 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12946 mode_cmd->pitches[0] != obj->stride) {
12947 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12948 mode_cmd->pitches[0], obj->stride);
12949 return -EINVAL;
12950 }
12951
12952 /* Reject formats not supported by any plane early. */
12953 switch (mode_cmd->pixel_format) {
12954 case DRM_FORMAT_C8:
12955 case DRM_FORMAT_RGB565:
12956 case DRM_FORMAT_XRGB8888:
12957 case DRM_FORMAT_ARGB8888:
12958 break;
12959 case DRM_FORMAT_XRGB1555:
12960 case DRM_FORMAT_ARGB1555:
12961 if (INTEL_INFO(dev)->gen > 3) {
12962 DRM_DEBUG("unsupported pixel format: %s\n",
12963 drm_get_format_name(mode_cmd->pixel_format));
12964 return -EINVAL;
12965 }
12966 break;
12967 case DRM_FORMAT_XBGR8888:
12968 case DRM_FORMAT_ABGR8888:
12969 case DRM_FORMAT_XRGB2101010:
12970 case DRM_FORMAT_ARGB2101010:
12971 case DRM_FORMAT_XBGR2101010:
12972 case DRM_FORMAT_ABGR2101010:
12973 if (INTEL_INFO(dev)->gen < 4) {
12974 DRM_DEBUG("unsupported pixel format: %s\n",
12975 drm_get_format_name(mode_cmd->pixel_format));
12976 return -EINVAL;
12977 }
12978 break;
12979 case DRM_FORMAT_YUYV:
12980 case DRM_FORMAT_UYVY:
12981 case DRM_FORMAT_YVYU:
12982 case DRM_FORMAT_VYUY:
12983 if (INTEL_INFO(dev)->gen < 5) {
12984 DRM_DEBUG("unsupported pixel format: %s\n",
12985 drm_get_format_name(mode_cmd->pixel_format));
12986 return -EINVAL;
12987 }
12988 break;
12989 default:
12990 DRM_DEBUG("unsupported pixel format: %s\n",
12991 drm_get_format_name(mode_cmd->pixel_format));
12992 return -EINVAL;
12993 }
12994
12995 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12996 if (mode_cmd->offsets[0] != 0)
12997 return -EINVAL;
12998
12999 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13000 mode_cmd->pixel_format,
13001 mode_cmd->modifier[0]);
13002 /* FIXME drm helper for size checks (especially planar formats)? */
13003 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13004 return -EINVAL;
13005
13006 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13007 intel_fb->obj = obj;
13008 intel_fb->obj->framebuffer_references++;
13009
13010 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13011 if (ret) {
13012 DRM_ERROR("framebuffer init failed %d\n", ret);
13013 return ret;
13014 }
13015
13016 return 0;
13017 }
13018
13019 static struct drm_framebuffer *
13020 intel_user_framebuffer_create(struct drm_device *dev,
13021 struct drm_file *filp,
13022 struct drm_mode_fb_cmd2 *mode_cmd)
13023 {
13024 struct drm_i915_gem_object *obj;
13025
13026 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13027 mode_cmd->handles[0]));
13028 if (&obj->base == NULL)
13029 return ERR_PTR(-ENOENT);
13030
13031 return intel_framebuffer_create(dev, mode_cmd, obj);
13032 }
13033
13034 #ifndef CONFIG_DRM_I915_FBDEV
13035 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13036 {
13037 }
13038 #endif
13039
13040 static const struct drm_mode_config_funcs intel_mode_funcs = {
13041 .fb_create = intel_user_framebuffer_create,
13042 .output_poll_changed = intel_fbdev_output_poll_changed,
13043 .atomic_check = intel_atomic_check,
13044 .atomic_commit = intel_atomic_commit,
13045 };
13046
13047 /* Set up chip specific display functions */
13048 static void intel_init_display(struct drm_device *dev)
13049 {
13050 struct drm_i915_private *dev_priv = dev->dev_private;
13051
13052 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13053 dev_priv->display.find_dpll = g4x_find_best_dpll;
13054 else if (IS_CHERRYVIEW(dev))
13055 dev_priv->display.find_dpll = chv_find_best_dpll;
13056 else if (IS_VALLEYVIEW(dev))
13057 dev_priv->display.find_dpll = vlv_find_best_dpll;
13058 else if (IS_PINEVIEW(dev))
13059 dev_priv->display.find_dpll = pnv_find_best_dpll;
13060 else
13061 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13062
13063 if (INTEL_INFO(dev)->gen >= 9) {
13064 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13065 dev_priv->display.get_initial_plane_config =
13066 skylake_get_initial_plane_config;
13067 dev_priv->display.crtc_compute_clock =
13068 haswell_crtc_compute_clock;
13069 dev_priv->display.crtc_enable = haswell_crtc_enable;
13070 dev_priv->display.crtc_disable = haswell_crtc_disable;
13071 dev_priv->display.off = ironlake_crtc_off;
13072 dev_priv->display.update_primary_plane =
13073 skylake_update_primary_plane;
13074 } else if (HAS_DDI(dev)) {
13075 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13076 dev_priv->display.get_initial_plane_config =
13077 ironlake_get_initial_plane_config;
13078 dev_priv->display.crtc_compute_clock =
13079 haswell_crtc_compute_clock;
13080 dev_priv->display.crtc_enable = haswell_crtc_enable;
13081 dev_priv->display.crtc_disable = haswell_crtc_disable;
13082 dev_priv->display.off = ironlake_crtc_off;
13083 dev_priv->display.update_primary_plane =
13084 ironlake_update_primary_plane;
13085 } else if (HAS_PCH_SPLIT(dev)) {
13086 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13087 dev_priv->display.get_initial_plane_config =
13088 ironlake_get_initial_plane_config;
13089 dev_priv->display.crtc_compute_clock =
13090 ironlake_crtc_compute_clock;
13091 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13092 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13093 dev_priv->display.off = ironlake_crtc_off;
13094 dev_priv->display.update_primary_plane =
13095 ironlake_update_primary_plane;
13096 } else if (IS_VALLEYVIEW(dev)) {
13097 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13098 dev_priv->display.get_initial_plane_config =
13099 i9xx_get_initial_plane_config;
13100 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13101 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13102 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13103 dev_priv->display.off = i9xx_crtc_off;
13104 dev_priv->display.update_primary_plane =
13105 i9xx_update_primary_plane;
13106 } else {
13107 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13108 dev_priv->display.get_initial_plane_config =
13109 i9xx_get_initial_plane_config;
13110 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13111 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13112 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13113 dev_priv->display.off = i9xx_crtc_off;
13114 dev_priv->display.update_primary_plane =
13115 i9xx_update_primary_plane;
13116 }
13117
13118 /* Returns the core display clock speed */
13119 if (IS_VALLEYVIEW(dev))
13120 dev_priv->display.get_display_clock_speed =
13121 valleyview_get_display_clock_speed;
13122 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13123 dev_priv->display.get_display_clock_speed =
13124 i945_get_display_clock_speed;
13125 else if (IS_I915G(dev))
13126 dev_priv->display.get_display_clock_speed =
13127 i915_get_display_clock_speed;
13128 else if (IS_I945GM(dev) || IS_845G(dev))
13129 dev_priv->display.get_display_clock_speed =
13130 i9xx_misc_get_display_clock_speed;
13131 else if (IS_PINEVIEW(dev))
13132 dev_priv->display.get_display_clock_speed =
13133 pnv_get_display_clock_speed;
13134 else if (IS_I915GM(dev))
13135 dev_priv->display.get_display_clock_speed =
13136 i915gm_get_display_clock_speed;
13137 else if (IS_I865G(dev))
13138 dev_priv->display.get_display_clock_speed =
13139 i865_get_display_clock_speed;
13140 else if (IS_I85X(dev))
13141 dev_priv->display.get_display_clock_speed =
13142 i855_get_display_clock_speed;
13143 else /* 852, 830 */
13144 dev_priv->display.get_display_clock_speed =
13145 i830_get_display_clock_speed;
13146
13147 if (IS_GEN5(dev)) {
13148 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13149 } else if (IS_GEN6(dev)) {
13150 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13151 } else if (IS_IVYBRIDGE(dev)) {
13152 /* FIXME: detect B0+ stepping and use auto training */
13153 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13154 dev_priv->display.modeset_global_resources =
13155 ivb_modeset_global_resources;
13156 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13157 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13158 } else if (IS_VALLEYVIEW(dev)) {
13159 dev_priv->display.modeset_global_resources =
13160 valleyview_modeset_global_resources;
13161 }
13162
13163 switch (INTEL_INFO(dev)->gen) {
13164 case 2:
13165 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13166 break;
13167
13168 case 3:
13169 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13170 break;
13171
13172 case 4:
13173 case 5:
13174 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13175 break;
13176
13177 case 6:
13178 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13179 break;
13180 case 7:
13181 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13182 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13183 break;
13184 case 9:
13185 /* Drop through - unsupported since execlist only. */
13186 default:
13187 /* Default just returns -ENODEV to indicate unsupported */
13188 dev_priv->display.queue_flip = intel_default_queue_flip;
13189 }
13190
13191 intel_panel_init_backlight_funcs(dev);
13192
13193 mutex_init(&dev_priv->pps_mutex);
13194 }
13195
13196 /*
13197 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13198 * resume, or other times. This quirk makes sure that's the case for
13199 * affected systems.
13200 */
13201 static void quirk_pipea_force(struct drm_device *dev)
13202 {
13203 struct drm_i915_private *dev_priv = dev->dev_private;
13204
13205 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13206 DRM_INFO("applying pipe a force quirk\n");
13207 }
13208
13209 static void quirk_pipeb_force(struct drm_device *dev)
13210 {
13211 struct drm_i915_private *dev_priv = dev->dev_private;
13212
13213 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13214 DRM_INFO("applying pipe b force quirk\n");
13215 }
13216
13217 /*
13218 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13219 */
13220 static void quirk_ssc_force_disable(struct drm_device *dev)
13221 {
13222 struct drm_i915_private *dev_priv = dev->dev_private;
13223 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13224 DRM_INFO("applying lvds SSC disable quirk\n");
13225 }
13226
13227 /*
13228 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13229 * brightness value
13230 */
13231 static void quirk_invert_brightness(struct drm_device *dev)
13232 {
13233 struct drm_i915_private *dev_priv = dev->dev_private;
13234 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13235 DRM_INFO("applying inverted panel brightness quirk\n");
13236 }
13237
13238 /* Some VBT's incorrectly indicate no backlight is present */
13239 static void quirk_backlight_present(struct drm_device *dev)
13240 {
13241 struct drm_i915_private *dev_priv = dev->dev_private;
13242 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13243 DRM_INFO("applying backlight present quirk\n");
13244 }
13245
13246 struct intel_quirk {
13247 int device;
13248 int subsystem_vendor;
13249 int subsystem_device;
13250 void (*hook)(struct drm_device *dev);
13251 };
13252
13253 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13254 struct intel_dmi_quirk {
13255 void (*hook)(struct drm_device *dev);
13256 const struct dmi_system_id (*dmi_id_list)[];
13257 };
13258
13259 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13260 {
13261 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13262 return 1;
13263 }
13264
13265 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13266 {
13267 .dmi_id_list = &(const struct dmi_system_id[]) {
13268 {
13269 .callback = intel_dmi_reverse_brightness,
13270 .ident = "NCR Corporation",
13271 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13272 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13273 },
13274 },
13275 { } /* terminating entry */
13276 },
13277 .hook = quirk_invert_brightness,
13278 },
13279 };
13280
13281 static struct intel_quirk intel_quirks[] = {
13282 /* HP Mini needs pipe A force quirk (LP: #322104) */
13283 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13284
13285 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13286 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13287
13288 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13289 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13290
13291 /* 830 needs to leave pipe A & dpll A up */
13292 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13293
13294 /* 830 needs to leave pipe B & dpll B up */
13295 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13296
13297 /* Lenovo U160 cannot use SSC on LVDS */
13298 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13299
13300 /* Sony Vaio Y cannot use SSC on LVDS */
13301 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13302
13303 /* Acer Aspire 5734Z must invert backlight brightness */
13304 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13305
13306 /* Acer/eMachines G725 */
13307 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13308
13309 /* Acer/eMachines e725 */
13310 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13311
13312 /* Acer/Packard Bell NCL20 */
13313 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13314
13315 /* Acer Aspire 4736Z */
13316 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13317
13318 /* Acer Aspire 5336 */
13319 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13320
13321 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13322 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13323
13324 /* Acer C720 Chromebook (Core i3 4005U) */
13325 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13326
13327 /* Apple Macbook 2,1 (Core 2 T7400) */
13328 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13329
13330 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13331 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13332
13333 /* HP Chromebook 14 (Celeron 2955U) */
13334 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13335
13336 /* Dell Chromebook 11 */
13337 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13338 };
13339
13340 static void intel_init_quirks(struct drm_device *dev)
13341 {
13342 struct pci_dev *d = dev->pdev;
13343 int i;
13344
13345 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13346 struct intel_quirk *q = &intel_quirks[i];
13347
13348 if (d->device == q->device &&
13349 (d->subsystem_vendor == q->subsystem_vendor ||
13350 q->subsystem_vendor == PCI_ANY_ID) &&
13351 (d->subsystem_device == q->subsystem_device ||
13352 q->subsystem_device == PCI_ANY_ID))
13353 q->hook(dev);
13354 }
13355 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13356 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13357 intel_dmi_quirks[i].hook(dev);
13358 }
13359 }
13360
13361 /* Disable the VGA plane that we never use */
13362 static void i915_disable_vga(struct drm_device *dev)
13363 {
13364 struct drm_i915_private *dev_priv = dev->dev_private;
13365 u8 sr1;
13366 u32 vga_reg = i915_vgacntrl_reg(dev);
13367
13368 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13369 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13370 outb(SR01, VGA_SR_INDEX);
13371 sr1 = inb(VGA_SR_DATA);
13372 outb(sr1 | 1<<5, VGA_SR_DATA);
13373 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13374 udelay(300);
13375
13376 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13377 POSTING_READ(vga_reg);
13378 }
13379
13380 void intel_modeset_init_hw(struct drm_device *dev)
13381 {
13382 intel_prepare_ddi(dev);
13383
13384 if (IS_VALLEYVIEW(dev))
13385 vlv_update_cdclk(dev);
13386
13387 intel_init_clock_gating(dev);
13388
13389 intel_enable_gt_powersave(dev);
13390 }
13391
13392 void intel_modeset_init(struct drm_device *dev)
13393 {
13394 struct drm_i915_private *dev_priv = dev->dev_private;
13395 int sprite, ret;
13396 enum pipe pipe;
13397 struct intel_crtc *crtc;
13398
13399 drm_mode_config_init(dev);
13400
13401 dev->mode_config.min_width = 0;
13402 dev->mode_config.min_height = 0;
13403
13404 dev->mode_config.preferred_depth = 24;
13405 dev->mode_config.prefer_shadow = 1;
13406
13407 dev->mode_config.allow_fb_modifiers = true;
13408
13409 dev->mode_config.funcs = &intel_mode_funcs;
13410
13411 intel_init_quirks(dev);
13412
13413 intel_init_pm(dev);
13414
13415 if (INTEL_INFO(dev)->num_pipes == 0)
13416 return;
13417
13418 intel_init_display(dev);
13419 intel_init_audio(dev);
13420
13421 if (IS_GEN2(dev)) {
13422 dev->mode_config.max_width = 2048;
13423 dev->mode_config.max_height = 2048;
13424 } else if (IS_GEN3(dev)) {
13425 dev->mode_config.max_width = 4096;
13426 dev->mode_config.max_height = 4096;
13427 } else {
13428 dev->mode_config.max_width = 8192;
13429 dev->mode_config.max_height = 8192;
13430 }
13431
13432 if (IS_845G(dev) || IS_I865G(dev)) {
13433 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13434 dev->mode_config.cursor_height = 1023;
13435 } else if (IS_GEN2(dev)) {
13436 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13437 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13438 } else {
13439 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13440 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13441 }
13442
13443 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13444
13445 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13446 INTEL_INFO(dev)->num_pipes,
13447 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13448
13449 for_each_pipe(dev_priv, pipe) {
13450 intel_crtc_init(dev, pipe);
13451 for_each_sprite(dev_priv, pipe, sprite) {
13452 ret = intel_plane_init(dev, pipe, sprite);
13453 if (ret)
13454 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13455 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13456 }
13457 }
13458
13459 intel_init_dpio(dev);
13460
13461 intel_shared_dpll_init(dev);
13462
13463 /* Just disable it once at startup */
13464 i915_disable_vga(dev);
13465 intel_setup_outputs(dev);
13466
13467 /* Just in case the BIOS is doing something questionable. */
13468 intel_fbc_disable(dev);
13469
13470 drm_modeset_lock_all(dev);
13471 intel_modeset_setup_hw_state(dev, false);
13472 drm_modeset_unlock_all(dev);
13473
13474 for_each_intel_crtc(dev, crtc) {
13475 if (!crtc->active)
13476 continue;
13477
13478 /*
13479 * Note that reserving the BIOS fb up front prevents us
13480 * from stuffing other stolen allocations like the ring
13481 * on top. This prevents some ugliness at boot time, and
13482 * can even allow for smooth boot transitions if the BIOS
13483 * fb is large enough for the active pipe configuration.
13484 */
13485 if (dev_priv->display.get_initial_plane_config) {
13486 dev_priv->display.get_initial_plane_config(crtc,
13487 &crtc->plane_config);
13488 /*
13489 * If the fb is shared between multiple heads, we'll
13490 * just get the first one.
13491 */
13492 intel_find_plane_obj(crtc, &crtc->plane_config);
13493 }
13494 }
13495 }
13496
13497 static void intel_enable_pipe_a(struct drm_device *dev)
13498 {
13499 struct intel_connector *connector;
13500 struct drm_connector *crt = NULL;
13501 struct intel_load_detect_pipe load_detect_temp;
13502 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13503
13504 /* We can't just switch on the pipe A, we need to set things up with a
13505 * proper mode and output configuration. As a gross hack, enable pipe A
13506 * by enabling the load detect pipe once. */
13507 for_each_intel_connector(dev, connector) {
13508 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13509 crt = &connector->base;
13510 break;
13511 }
13512 }
13513
13514 if (!crt)
13515 return;
13516
13517 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13518 intel_release_load_detect_pipe(crt, &load_detect_temp);
13519 }
13520
13521 static bool
13522 intel_check_plane_mapping(struct intel_crtc *crtc)
13523 {
13524 struct drm_device *dev = crtc->base.dev;
13525 struct drm_i915_private *dev_priv = dev->dev_private;
13526 u32 reg, val;
13527
13528 if (INTEL_INFO(dev)->num_pipes == 1)
13529 return true;
13530
13531 reg = DSPCNTR(!crtc->plane);
13532 val = I915_READ(reg);
13533
13534 if ((val & DISPLAY_PLANE_ENABLE) &&
13535 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13536 return false;
13537
13538 return true;
13539 }
13540
13541 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13542 {
13543 struct drm_device *dev = crtc->base.dev;
13544 struct drm_i915_private *dev_priv = dev->dev_private;
13545 u32 reg;
13546
13547 /* Clear any frame start delays used for debugging left by the BIOS */
13548 reg = PIPECONF(crtc->config->cpu_transcoder);
13549 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13550
13551 /* restore vblank interrupts to correct state */
13552 drm_crtc_vblank_reset(&crtc->base);
13553 if (crtc->active) {
13554 update_scanline_offset(crtc);
13555 drm_crtc_vblank_on(&crtc->base);
13556 }
13557
13558 /* We need to sanitize the plane -> pipe mapping first because this will
13559 * disable the crtc (and hence change the state) if it is wrong. Note
13560 * that gen4+ has a fixed plane -> pipe mapping. */
13561 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13562 struct intel_connector *connector;
13563 bool plane;
13564
13565 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13566 crtc->base.base.id);
13567
13568 /* Pipe has the wrong plane attached and the plane is active.
13569 * Temporarily change the plane mapping and disable everything
13570 * ... */
13571 plane = crtc->plane;
13572 crtc->plane = !plane;
13573 crtc->primary_enabled = true;
13574 dev_priv->display.crtc_disable(&crtc->base);
13575 crtc->plane = plane;
13576
13577 /* ... and break all links. */
13578 for_each_intel_connector(dev, connector) {
13579 if (connector->encoder->base.crtc != &crtc->base)
13580 continue;
13581
13582 connector->base.dpms = DRM_MODE_DPMS_OFF;
13583 connector->base.encoder = NULL;
13584 }
13585 /* multiple connectors may have the same encoder:
13586 * handle them and break crtc link separately */
13587 for_each_intel_connector(dev, connector)
13588 if (connector->encoder->base.crtc == &crtc->base) {
13589 connector->encoder->base.crtc = NULL;
13590 connector->encoder->connectors_active = false;
13591 }
13592
13593 WARN_ON(crtc->active);
13594 crtc->base.state->enable = false;
13595 crtc->base.enabled = false;
13596 }
13597
13598 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13599 crtc->pipe == PIPE_A && !crtc->active) {
13600 /* BIOS forgot to enable pipe A, this mostly happens after
13601 * resume. Force-enable the pipe to fix this, the update_dpms
13602 * call below we restore the pipe to the right state, but leave
13603 * the required bits on. */
13604 intel_enable_pipe_a(dev);
13605 }
13606
13607 /* Adjust the state of the output pipe according to whether we
13608 * have active connectors/encoders. */
13609 intel_crtc_update_dpms(&crtc->base);
13610
13611 if (crtc->active != crtc->base.state->enable) {
13612 struct intel_encoder *encoder;
13613
13614 /* This can happen either due to bugs in the get_hw_state
13615 * functions or because the pipe is force-enabled due to the
13616 * pipe A quirk. */
13617 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13618 crtc->base.base.id,
13619 crtc->base.state->enable ? "enabled" : "disabled",
13620 crtc->active ? "enabled" : "disabled");
13621
13622 crtc->base.state->enable = crtc->active;
13623 crtc->base.enabled = crtc->active;
13624
13625 /* Because we only establish the connector -> encoder ->
13626 * crtc links if something is active, this means the
13627 * crtc is now deactivated. Break the links. connector
13628 * -> encoder links are only establish when things are
13629 * actually up, hence no need to break them. */
13630 WARN_ON(crtc->active);
13631
13632 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13633 WARN_ON(encoder->connectors_active);
13634 encoder->base.crtc = NULL;
13635 }
13636 }
13637
13638 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13639 /*
13640 * We start out with underrun reporting disabled to avoid races.
13641 * For correct bookkeeping mark this on active crtcs.
13642 *
13643 * Also on gmch platforms we dont have any hardware bits to
13644 * disable the underrun reporting. Which means we need to start
13645 * out with underrun reporting disabled also on inactive pipes,
13646 * since otherwise we'll complain about the garbage we read when
13647 * e.g. coming up after runtime pm.
13648 *
13649 * No protection against concurrent access is required - at
13650 * worst a fifo underrun happens which also sets this to false.
13651 */
13652 crtc->cpu_fifo_underrun_disabled = true;
13653 crtc->pch_fifo_underrun_disabled = true;
13654 }
13655 }
13656
13657 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13658 {
13659 struct intel_connector *connector;
13660 struct drm_device *dev = encoder->base.dev;
13661
13662 /* We need to check both for a crtc link (meaning that the
13663 * encoder is active and trying to read from a pipe) and the
13664 * pipe itself being active. */
13665 bool has_active_crtc = encoder->base.crtc &&
13666 to_intel_crtc(encoder->base.crtc)->active;
13667
13668 if (encoder->connectors_active && !has_active_crtc) {
13669 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13670 encoder->base.base.id,
13671 encoder->base.name);
13672
13673 /* Connector is active, but has no active pipe. This is
13674 * fallout from our resume register restoring. Disable
13675 * the encoder manually again. */
13676 if (encoder->base.crtc) {
13677 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13678 encoder->base.base.id,
13679 encoder->base.name);
13680 encoder->disable(encoder);
13681 if (encoder->post_disable)
13682 encoder->post_disable(encoder);
13683 }
13684 encoder->base.crtc = NULL;
13685 encoder->connectors_active = false;
13686
13687 /* Inconsistent output/port/pipe state happens presumably due to
13688 * a bug in one of the get_hw_state functions. Or someplace else
13689 * in our code, like the register restore mess on resume. Clamp
13690 * things to off as a safer default. */
13691 for_each_intel_connector(dev, connector) {
13692 if (connector->encoder != encoder)
13693 continue;
13694 connector->base.dpms = DRM_MODE_DPMS_OFF;
13695 connector->base.encoder = NULL;
13696 }
13697 }
13698 /* Enabled encoders without active connectors will be fixed in
13699 * the crtc fixup. */
13700 }
13701
13702 void i915_redisable_vga_power_on(struct drm_device *dev)
13703 {
13704 struct drm_i915_private *dev_priv = dev->dev_private;
13705 u32 vga_reg = i915_vgacntrl_reg(dev);
13706
13707 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13708 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13709 i915_disable_vga(dev);
13710 }
13711 }
13712
13713 void i915_redisable_vga(struct drm_device *dev)
13714 {
13715 struct drm_i915_private *dev_priv = dev->dev_private;
13716
13717 /* This function can be called both from intel_modeset_setup_hw_state or
13718 * at a very early point in our resume sequence, where the power well
13719 * structures are not yet restored. Since this function is at a very
13720 * paranoid "someone might have enabled VGA while we were not looking"
13721 * level, just check if the power well is enabled instead of trying to
13722 * follow the "don't touch the power well if we don't need it" policy
13723 * the rest of the driver uses. */
13724 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13725 return;
13726
13727 i915_redisable_vga_power_on(dev);
13728 }
13729
13730 static bool primary_get_hw_state(struct intel_crtc *crtc)
13731 {
13732 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13733
13734 if (!crtc->active)
13735 return false;
13736
13737 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13738 }
13739
13740 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13741 {
13742 struct drm_i915_private *dev_priv = dev->dev_private;
13743 enum pipe pipe;
13744 struct intel_crtc *crtc;
13745 struct intel_encoder *encoder;
13746 struct intel_connector *connector;
13747 int i;
13748
13749 for_each_intel_crtc(dev, crtc) {
13750 memset(crtc->config, 0, sizeof(*crtc->config));
13751
13752 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13753
13754 crtc->active = dev_priv->display.get_pipe_config(crtc,
13755 crtc->config);
13756
13757 crtc->base.state->enable = crtc->active;
13758 crtc->base.enabled = crtc->active;
13759 crtc->primary_enabled = primary_get_hw_state(crtc);
13760
13761 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13762 crtc->base.base.id,
13763 crtc->active ? "enabled" : "disabled");
13764 }
13765
13766 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13767 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13768
13769 pll->on = pll->get_hw_state(dev_priv, pll,
13770 &pll->config.hw_state);
13771 pll->active = 0;
13772 pll->config.crtc_mask = 0;
13773 for_each_intel_crtc(dev, crtc) {
13774 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13775 pll->active++;
13776 pll->config.crtc_mask |= 1 << crtc->pipe;
13777 }
13778 }
13779
13780 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13781 pll->name, pll->config.crtc_mask, pll->on);
13782
13783 if (pll->config.crtc_mask)
13784 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13785 }
13786
13787 for_each_intel_encoder(dev, encoder) {
13788 pipe = 0;
13789
13790 if (encoder->get_hw_state(encoder, &pipe)) {
13791 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13792 encoder->base.crtc = &crtc->base;
13793 encoder->get_config(encoder, crtc->config);
13794 } else {
13795 encoder->base.crtc = NULL;
13796 }
13797
13798 encoder->connectors_active = false;
13799 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13800 encoder->base.base.id,
13801 encoder->base.name,
13802 encoder->base.crtc ? "enabled" : "disabled",
13803 pipe_name(pipe));
13804 }
13805
13806 for_each_intel_connector(dev, connector) {
13807 if (connector->get_hw_state(connector)) {
13808 connector->base.dpms = DRM_MODE_DPMS_ON;
13809 connector->encoder->connectors_active = true;
13810 connector->base.encoder = &connector->encoder->base;
13811 } else {
13812 connector->base.dpms = DRM_MODE_DPMS_OFF;
13813 connector->base.encoder = NULL;
13814 }
13815 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13816 connector->base.base.id,
13817 connector->base.name,
13818 connector->base.encoder ? "enabled" : "disabled");
13819 }
13820 }
13821
13822 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13823 * and i915 state tracking structures. */
13824 void intel_modeset_setup_hw_state(struct drm_device *dev,
13825 bool force_restore)
13826 {
13827 struct drm_i915_private *dev_priv = dev->dev_private;
13828 enum pipe pipe;
13829 struct intel_crtc *crtc;
13830 struct intel_encoder *encoder;
13831 int i;
13832
13833 intel_modeset_readout_hw_state(dev);
13834
13835 /*
13836 * Now that we have the config, copy it to each CRTC struct
13837 * Note that this could go away if we move to using crtc_config
13838 * checking everywhere.
13839 */
13840 for_each_intel_crtc(dev, crtc) {
13841 if (crtc->active && i915.fastboot) {
13842 intel_mode_from_pipe_config(&crtc->base.mode,
13843 crtc->config);
13844 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13845 crtc->base.base.id);
13846 drm_mode_debug_printmodeline(&crtc->base.mode);
13847 }
13848 }
13849
13850 /* HW state is read out, now we need to sanitize this mess. */
13851 for_each_intel_encoder(dev, encoder) {
13852 intel_sanitize_encoder(encoder);
13853 }
13854
13855 for_each_pipe(dev_priv, pipe) {
13856 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13857 intel_sanitize_crtc(crtc);
13858 intel_dump_pipe_config(crtc, crtc->config,
13859 "[setup_hw_state]");
13860 }
13861
13862 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13863 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13864
13865 if (!pll->on || pll->active)
13866 continue;
13867
13868 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13869
13870 pll->disable(dev_priv, pll);
13871 pll->on = false;
13872 }
13873
13874 if (IS_GEN9(dev))
13875 skl_wm_get_hw_state(dev);
13876 else if (HAS_PCH_SPLIT(dev))
13877 ilk_wm_get_hw_state(dev);
13878
13879 if (force_restore) {
13880 i915_redisable_vga(dev);
13881
13882 /*
13883 * We need to use raw interfaces for restoring state to avoid
13884 * checking (bogus) intermediate states.
13885 */
13886 for_each_pipe(dev_priv, pipe) {
13887 struct drm_crtc *crtc =
13888 dev_priv->pipe_to_crtc_mapping[pipe];
13889
13890 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13891 crtc->primary->fb);
13892 }
13893 } else {
13894 intel_modeset_update_staged_output_state(dev);
13895 }
13896
13897 intel_modeset_check_state(dev);
13898 }
13899
13900 void intel_modeset_gem_init(struct drm_device *dev)
13901 {
13902 struct drm_i915_private *dev_priv = dev->dev_private;
13903 struct drm_crtc *c;
13904 struct drm_i915_gem_object *obj;
13905
13906 mutex_lock(&dev->struct_mutex);
13907 intel_init_gt_powersave(dev);
13908 mutex_unlock(&dev->struct_mutex);
13909
13910 /*
13911 * There may be no VBT; and if the BIOS enabled SSC we can
13912 * just keep using it to avoid unnecessary flicker. Whereas if the
13913 * BIOS isn't using it, don't assume it will work even if the VBT
13914 * indicates as much.
13915 */
13916 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13917 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13918 DREF_SSC1_ENABLE);
13919
13920 intel_modeset_init_hw(dev);
13921
13922 intel_setup_overlay(dev);
13923
13924 /*
13925 * Make sure any fbs we allocated at startup are properly
13926 * pinned & fenced. When we do the allocation it's too early
13927 * for this.
13928 */
13929 mutex_lock(&dev->struct_mutex);
13930 for_each_crtc(dev, c) {
13931 obj = intel_fb_obj(c->primary->fb);
13932 if (obj == NULL)
13933 continue;
13934
13935 if (intel_pin_and_fence_fb_obj(c->primary,
13936 c->primary->fb,
13937 NULL)) {
13938 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13939 to_intel_crtc(c)->pipe);
13940 drm_framebuffer_unreference(c->primary->fb);
13941 c->primary->fb = NULL;
13942 update_state_fb(c->primary);
13943 }
13944 }
13945 mutex_unlock(&dev->struct_mutex);
13946
13947 intel_backlight_register(dev);
13948 }
13949
13950 void intel_connector_unregister(struct intel_connector *intel_connector)
13951 {
13952 struct drm_connector *connector = &intel_connector->base;
13953
13954 intel_panel_destroy_backlight(connector);
13955 drm_connector_unregister(connector);
13956 }
13957
13958 void intel_modeset_cleanup(struct drm_device *dev)
13959 {
13960 struct drm_i915_private *dev_priv = dev->dev_private;
13961 struct drm_connector *connector;
13962
13963 intel_disable_gt_powersave(dev);
13964
13965 intel_backlight_unregister(dev);
13966
13967 /*
13968 * Interrupts and polling as the first thing to avoid creating havoc.
13969 * Too much stuff here (turning of connectors, ...) would
13970 * experience fancy races otherwise.
13971 */
13972 intel_irq_uninstall(dev_priv);
13973
13974 /*
13975 * Due to the hpd irq storm handling the hotplug work can re-arm the
13976 * poll handlers. Hence disable polling after hpd handling is shut down.
13977 */
13978 drm_kms_helper_poll_fini(dev);
13979
13980 mutex_lock(&dev->struct_mutex);
13981
13982 intel_unregister_dsm_handler();
13983
13984 intel_fbc_disable(dev);
13985
13986 mutex_unlock(&dev->struct_mutex);
13987
13988 /* flush any delayed tasks or pending work */
13989 flush_scheduled_work();
13990
13991 /* destroy the backlight and sysfs files before encoders/connectors */
13992 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13993 struct intel_connector *intel_connector;
13994
13995 intel_connector = to_intel_connector(connector);
13996 intel_connector->unregister(intel_connector);
13997 }
13998
13999 drm_mode_config_cleanup(dev);
14000
14001 intel_cleanup_overlay(dev);
14002
14003 mutex_lock(&dev->struct_mutex);
14004 intel_cleanup_gt_powersave(dev);
14005 mutex_unlock(&dev->struct_mutex);
14006 }
14007
14008 /*
14009 * Return which encoder is currently attached for connector.
14010 */
14011 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
14012 {
14013 return &intel_attached_encoder(connector)->base;
14014 }
14015
14016 void intel_connector_attach_encoder(struct intel_connector *connector,
14017 struct intel_encoder *encoder)
14018 {
14019 connector->encoder = encoder;
14020 drm_mode_connector_attach_encoder(&connector->base,
14021 &encoder->base);
14022 }
14023
14024 /*
14025 * set vga decode state - true == enable VGA decode
14026 */
14027 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14028 {
14029 struct drm_i915_private *dev_priv = dev->dev_private;
14030 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14031 u16 gmch_ctrl;
14032
14033 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14034 DRM_ERROR("failed to read control word\n");
14035 return -EIO;
14036 }
14037
14038 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14039 return 0;
14040
14041 if (state)
14042 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14043 else
14044 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14045
14046 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14047 DRM_ERROR("failed to write control word\n");
14048 return -EIO;
14049 }
14050
14051 return 0;
14052 }
14053
14054 struct intel_display_error_state {
14055
14056 u32 power_well_driver;
14057
14058 int num_transcoders;
14059
14060 struct intel_cursor_error_state {
14061 u32 control;
14062 u32 position;
14063 u32 base;
14064 u32 size;
14065 } cursor[I915_MAX_PIPES];
14066
14067 struct intel_pipe_error_state {
14068 bool power_domain_on;
14069 u32 source;
14070 u32 stat;
14071 } pipe[I915_MAX_PIPES];
14072
14073 struct intel_plane_error_state {
14074 u32 control;
14075 u32 stride;
14076 u32 size;
14077 u32 pos;
14078 u32 addr;
14079 u32 surface;
14080 u32 tile_offset;
14081 } plane[I915_MAX_PIPES];
14082
14083 struct intel_transcoder_error_state {
14084 bool power_domain_on;
14085 enum transcoder cpu_transcoder;
14086
14087 u32 conf;
14088
14089 u32 htotal;
14090 u32 hblank;
14091 u32 hsync;
14092 u32 vtotal;
14093 u32 vblank;
14094 u32 vsync;
14095 } transcoder[4];
14096 };
14097
14098 struct intel_display_error_state *
14099 intel_display_capture_error_state(struct drm_device *dev)
14100 {
14101 struct drm_i915_private *dev_priv = dev->dev_private;
14102 struct intel_display_error_state *error;
14103 int transcoders[] = {
14104 TRANSCODER_A,
14105 TRANSCODER_B,
14106 TRANSCODER_C,
14107 TRANSCODER_EDP,
14108 };
14109 int i;
14110
14111 if (INTEL_INFO(dev)->num_pipes == 0)
14112 return NULL;
14113
14114 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14115 if (error == NULL)
14116 return NULL;
14117
14118 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14119 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14120
14121 for_each_pipe(dev_priv, i) {
14122 error->pipe[i].power_domain_on =
14123 __intel_display_power_is_enabled(dev_priv,
14124 POWER_DOMAIN_PIPE(i));
14125 if (!error->pipe[i].power_domain_on)
14126 continue;
14127
14128 error->cursor[i].control = I915_READ(CURCNTR(i));
14129 error->cursor[i].position = I915_READ(CURPOS(i));
14130 error->cursor[i].base = I915_READ(CURBASE(i));
14131
14132 error->plane[i].control = I915_READ(DSPCNTR(i));
14133 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14134 if (INTEL_INFO(dev)->gen <= 3) {
14135 error->plane[i].size = I915_READ(DSPSIZE(i));
14136 error->plane[i].pos = I915_READ(DSPPOS(i));
14137 }
14138 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14139 error->plane[i].addr = I915_READ(DSPADDR(i));
14140 if (INTEL_INFO(dev)->gen >= 4) {
14141 error->plane[i].surface = I915_READ(DSPSURF(i));
14142 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14143 }
14144
14145 error->pipe[i].source = I915_READ(PIPESRC(i));
14146
14147 if (HAS_GMCH_DISPLAY(dev))
14148 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14149 }
14150
14151 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14152 if (HAS_DDI(dev_priv->dev))
14153 error->num_transcoders++; /* Account for eDP. */
14154
14155 for (i = 0; i < error->num_transcoders; i++) {
14156 enum transcoder cpu_transcoder = transcoders[i];
14157
14158 error->transcoder[i].power_domain_on =
14159 __intel_display_power_is_enabled(dev_priv,
14160 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14161 if (!error->transcoder[i].power_domain_on)
14162 continue;
14163
14164 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14165
14166 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14167 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14168 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14169 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14170 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14171 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14172 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14173 }
14174
14175 return error;
14176 }
14177
14178 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14179
14180 void
14181 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14182 struct drm_device *dev,
14183 struct intel_display_error_state *error)
14184 {
14185 struct drm_i915_private *dev_priv = dev->dev_private;
14186 int i;
14187
14188 if (!error)
14189 return;
14190
14191 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14192 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14193 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14194 error->power_well_driver);
14195 for_each_pipe(dev_priv, i) {
14196 err_printf(m, "Pipe [%d]:\n", i);
14197 err_printf(m, " Power: %s\n",
14198 error->pipe[i].power_domain_on ? "on" : "off");
14199 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14200 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14201
14202 err_printf(m, "Plane [%d]:\n", i);
14203 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14204 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14205 if (INTEL_INFO(dev)->gen <= 3) {
14206 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14207 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14208 }
14209 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14210 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14211 if (INTEL_INFO(dev)->gen >= 4) {
14212 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14213 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14214 }
14215
14216 err_printf(m, "Cursor [%d]:\n", i);
14217 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14218 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14219 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14220 }
14221
14222 for (i = 0; i < error->num_transcoders; i++) {
14223 err_printf(m, "CPU transcoder: %c\n",
14224 transcoder_name(error->transcoder[i].cpu_transcoder));
14225 err_printf(m, " Power: %s\n",
14226 error->transcoder[i].power_domain_on ? "on" : "off");
14227 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14228 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14229 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14230 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14231 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14232 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14233 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14234 }
14235 }
14236
14237 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14238 {
14239 struct intel_crtc *crtc;
14240
14241 for_each_intel_crtc(dev, crtc) {
14242 struct intel_unpin_work *work;
14243
14244 spin_lock_irq(&dev->event_lock);
14245
14246 work = crtc->unpin_work;
14247
14248 if (work && work->event &&
14249 work->event->base.file_priv == file) {
14250 kfree(work->event);
14251 work->event = NULL;
14252 }
14253
14254 spin_unlock_irq(&dev->event_lock);
14255 }
14256 }
Linux kernel - Deliverables
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