2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_XRGB8888, \
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2
[] = {
55 COMMON_PRIMARY_FORMATS
,
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4
[] = {
62 COMMON_PRIMARY_FORMATS
, \
65 DRM_FORMAT_XRGB2101010
,
66 DRM_FORMAT_ARGB2101010
,
67 DRM_FORMAT_XBGR2101010
,
68 DRM_FORMAT_ABGR2101010
,
72 static const uint32_t intel_cursor_formats
[] = {
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
79 static void intel_increase_pllclock(struct drm_device
*dev
,
81 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
83 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
84 struct intel_crtc_config
*pipe_config
);
85 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
86 struct intel_crtc_config
*pipe_config
);
88 static int intel_set_mode(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
89 int x
, int y
, struct drm_framebuffer
*old_fb
);
90 static int intel_framebuffer_init(struct drm_device
*dev
,
91 struct intel_framebuffer
*ifb
,
92 struct drm_mode_fb_cmd2
*mode_cmd
,
93 struct drm_i915_gem_object
*obj
);
94 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
95 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
97 struct intel_link_m_n
*m_n
,
98 struct intel_link_m_n
*m2_n2
);
99 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
100 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
101 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
102 static void vlv_prepare_pll(struct intel_crtc
*crtc
);
103 static void chv_prepare_pll(struct intel_crtc
*crtc
);
105 static struct intel_encoder
*intel_find_encoder(struct intel_connector
*connector
, int pipe
)
107 if (!connector
->mst_port
)
108 return connector
->encoder
;
110 return &connector
->mst_port
->mst_encoders
[pipe
]->base
;
119 int p2_slow
, p2_fast
;
122 typedef struct intel_limit intel_limit_t
;
124 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
129 intel_pch_rawclk(struct drm_device
*dev
)
131 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
133 WARN_ON(!HAS_PCH_SPLIT(dev
));
135 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
138 static inline u32
/* units of 100MHz */
139 intel_fdi_link_freq(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
143 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
148 static const intel_limit_t intel_limits_i8xx_dac
= {
149 .dot
= { .min
= 25000, .max
= 350000 },
150 .vco
= { .min
= 908000, .max
= 1512000 },
151 .n
= { .min
= 2, .max
= 16 },
152 .m
= { .min
= 96, .max
= 140 },
153 .m1
= { .min
= 18, .max
= 26 },
154 .m2
= { .min
= 6, .max
= 16 },
155 .p
= { .min
= 4, .max
= 128 },
156 .p1
= { .min
= 2, .max
= 33 },
157 .p2
= { .dot_limit
= 165000,
158 .p2_slow
= 4, .p2_fast
= 2 },
161 static const intel_limit_t intel_limits_i8xx_dvo
= {
162 .dot
= { .min
= 25000, .max
= 350000 },
163 .vco
= { .min
= 908000, .max
= 1512000 },
164 .n
= { .min
= 2, .max
= 16 },
165 .m
= { .min
= 96, .max
= 140 },
166 .m1
= { .min
= 18, .max
= 26 },
167 .m2
= { .min
= 6, .max
= 16 },
168 .p
= { .min
= 4, .max
= 128 },
169 .p1
= { .min
= 2, .max
= 33 },
170 .p2
= { .dot_limit
= 165000,
171 .p2_slow
= 4, .p2_fast
= 4 },
174 static const intel_limit_t intel_limits_i8xx_lvds
= {
175 .dot
= { .min
= 25000, .max
= 350000 },
176 .vco
= { .min
= 908000, .max
= 1512000 },
177 .n
= { .min
= 2, .max
= 16 },
178 .m
= { .min
= 96, .max
= 140 },
179 .m1
= { .min
= 18, .max
= 26 },
180 .m2
= { .min
= 6, .max
= 16 },
181 .p
= { .min
= 4, .max
= 128 },
182 .p1
= { .min
= 1, .max
= 6 },
183 .p2
= { .dot_limit
= 165000,
184 .p2_slow
= 14, .p2_fast
= 7 },
187 static const intel_limit_t intel_limits_i9xx_sdvo
= {
188 .dot
= { .min
= 20000, .max
= 400000 },
189 .vco
= { .min
= 1400000, .max
= 2800000 },
190 .n
= { .min
= 1, .max
= 6 },
191 .m
= { .min
= 70, .max
= 120 },
192 .m1
= { .min
= 8, .max
= 18 },
193 .m2
= { .min
= 3, .max
= 7 },
194 .p
= { .min
= 5, .max
= 80 },
195 .p1
= { .min
= 1, .max
= 8 },
196 .p2
= { .dot_limit
= 200000,
197 .p2_slow
= 10, .p2_fast
= 5 },
200 static const intel_limit_t intel_limits_i9xx_lvds
= {
201 .dot
= { .min
= 20000, .max
= 400000 },
202 .vco
= { .min
= 1400000, .max
= 2800000 },
203 .n
= { .min
= 1, .max
= 6 },
204 .m
= { .min
= 70, .max
= 120 },
205 .m1
= { .min
= 8, .max
= 18 },
206 .m2
= { .min
= 3, .max
= 7 },
207 .p
= { .min
= 7, .max
= 98 },
208 .p1
= { .min
= 1, .max
= 8 },
209 .p2
= { .dot_limit
= 112000,
210 .p2_slow
= 14, .p2_fast
= 7 },
214 static const intel_limit_t intel_limits_g4x_sdvo
= {
215 .dot
= { .min
= 25000, .max
= 270000 },
216 .vco
= { .min
= 1750000, .max
= 3500000},
217 .n
= { .min
= 1, .max
= 4 },
218 .m
= { .min
= 104, .max
= 138 },
219 .m1
= { .min
= 17, .max
= 23 },
220 .m2
= { .min
= 5, .max
= 11 },
221 .p
= { .min
= 10, .max
= 30 },
222 .p1
= { .min
= 1, .max
= 3},
223 .p2
= { .dot_limit
= 270000,
229 static const intel_limit_t intel_limits_g4x_hdmi
= {
230 .dot
= { .min
= 22000, .max
= 400000 },
231 .vco
= { .min
= 1750000, .max
= 3500000},
232 .n
= { .min
= 1, .max
= 4 },
233 .m
= { .min
= 104, .max
= 138 },
234 .m1
= { .min
= 16, .max
= 23 },
235 .m2
= { .min
= 5, .max
= 11 },
236 .p
= { .min
= 5, .max
= 80 },
237 .p1
= { .min
= 1, .max
= 8},
238 .p2
= { .dot_limit
= 165000,
239 .p2_slow
= 10, .p2_fast
= 5 },
242 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
243 .dot
= { .min
= 20000, .max
= 115000 },
244 .vco
= { .min
= 1750000, .max
= 3500000 },
245 .n
= { .min
= 1, .max
= 3 },
246 .m
= { .min
= 104, .max
= 138 },
247 .m1
= { .min
= 17, .max
= 23 },
248 .m2
= { .min
= 5, .max
= 11 },
249 .p
= { .min
= 28, .max
= 112 },
250 .p1
= { .min
= 2, .max
= 8 },
251 .p2
= { .dot_limit
= 0,
252 .p2_slow
= 14, .p2_fast
= 14
256 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
257 .dot
= { .min
= 80000, .max
= 224000 },
258 .vco
= { .min
= 1750000, .max
= 3500000 },
259 .n
= { .min
= 1, .max
= 3 },
260 .m
= { .min
= 104, .max
= 138 },
261 .m1
= { .min
= 17, .max
= 23 },
262 .m2
= { .min
= 5, .max
= 11 },
263 .p
= { .min
= 14, .max
= 42 },
264 .p1
= { .min
= 2, .max
= 6 },
265 .p2
= { .dot_limit
= 0,
266 .p2_slow
= 7, .p2_fast
= 7
270 static const intel_limit_t intel_limits_pineview_sdvo
= {
271 .dot
= { .min
= 20000, .max
= 400000},
272 .vco
= { .min
= 1700000, .max
= 3500000 },
273 /* Pineview's Ncounter is a ring counter */
274 .n
= { .min
= 3, .max
= 6 },
275 .m
= { .min
= 2, .max
= 256 },
276 /* Pineview only has one combined m divider, which we treat as m2. */
277 .m1
= { .min
= 0, .max
= 0 },
278 .m2
= { .min
= 0, .max
= 254 },
279 .p
= { .min
= 5, .max
= 80 },
280 .p1
= { .min
= 1, .max
= 8 },
281 .p2
= { .dot_limit
= 200000,
282 .p2_slow
= 10, .p2_fast
= 5 },
285 static const intel_limit_t intel_limits_pineview_lvds
= {
286 .dot
= { .min
= 20000, .max
= 400000 },
287 .vco
= { .min
= 1700000, .max
= 3500000 },
288 .n
= { .min
= 3, .max
= 6 },
289 .m
= { .min
= 2, .max
= 256 },
290 .m1
= { .min
= 0, .max
= 0 },
291 .m2
= { .min
= 0, .max
= 254 },
292 .p
= { .min
= 7, .max
= 112 },
293 .p1
= { .min
= 1, .max
= 8 },
294 .p2
= { .dot_limit
= 112000,
295 .p2_slow
= 14, .p2_fast
= 14 },
298 /* Ironlake / Sandybridge
300 * We calculate clock using (register_value + 2) for N/M1/M2, so here
301 * the range value for them is (actual_value - 2).
303 static const intel_limit_t intel_limits_ironlake_dac
= {
304 .dot
= { .min
= 25000, .max
= 350000 },
305 .vco
= { .min
= 1760000, .max
= 3510000 },
306 .n
= { .min
= 1, .max
= 5 },
307 .m
= { .min
= 79, .max
= 127 },
308 .m1
= { .min
= 12, .max
= 22 },
309 .m2
= { .min
= 5, .max
= 9 },
310 .p
= { .min
= 5, .max
= 80 },
311 .p1
= { .min
= 1, .max
= 8 },
312 .p2
= { .dot_limit
= 225000,
313 .p2_slow
= 10, .p2_fast
= 5 },
316 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
317 .dot
= { .min
= 25000, .max
= 350000 },
318 .vco
= { .min
= 1760000, .max
= 3510000 },
319 .n
= { .min
= 1, .max
= 3 },
320 .m
= { .min
= 79, .max
= 118 },
321 .m1
= { .min
= 12, .max
= 22 },
322 .m2
= { .min
= 5, .max
= 9 },
323 .p
= { .min
= 28, .max
= 112 },
324 .p1
= { .min
= 2, .max
= 8 },
325 .p2
= { .dot_limit
= 225000,
326 .p2_slow
= 14, .p2_fast
= 14 },
329 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
330 .dot
= { .min
= 25000, .max
= 350000 },
331 .vco
= { .min
= 1760000, .max
= 3510000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 79, .max
= 127 },
334 .m1
= { .min
= 12, .max
= 22 },
335 .m2
= { .min
= 5, .max
= 9 },
336 .p
= { .min
= 14, .max
= 56 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 225000,
339 .p2_slow
= 7, .p2_fast
= 7 },
342 /* LVDS 100mhz refclk limits. */
343 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
344 .dot
= { .min
= 25000, .max
= 350000 },
345 .vco
= { .min
= 1760000, .max
= 3510000 },
346 .n
= { .min
= 1, .max
= 2 },
347 .m
= { .min
= 79, .max
= 126 },
348 .m1
= { .min
= 12, .max
= 22 },
349 .m2
= { .min
= 5, .max
= 9 },
350 .p
= { .min
= 28, .max
= 112 },
351 .p1
= { .min
= 2, .max
= 8 },
352 .p2
= { .dot_limit
= 225000,
353 .p2_slow
= 14, .p2_fast
= 14 },
356 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
357 .dot
= { .min
= 25000, .max
= 350000 },
358 .vco
= { .min
= 1760000, .max
= 3510000 },
359 .n
= { .min
= 1, .max
= 3 },
360 .m
= { .min
= 79, .max
= 126 },
361 .m1
= { .min
= 12, .max
= 22 },
362 .m2
= { .min
= 5, .max
= 9 },
363 .p
= { .min
= 14, .max
= 42 },
364 .p1
= { .min
= 2, .max
= 6 },
365 .p2
= { .dot_limit
= 225000,
366 .p2_slow
= 7, .p2_fast
= 7 },
369 static const intel_limit_t intel_limits_vlv
= {
371 * These are the data rate limits (measured in fast clocks)
372 * since those are the strictest limits we have. The fast
373 * clock and actual rate limits are more relaxed, so checking
374 * them would make no difference.
376 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
377 .vco
= { .min
= 4000000, .max
= 6000000 },
378 .n
= { .min
= 1, .max
= 7 },
379 .m1
= { .min
= 2, .max
= 3 },
380 .m2
= { .min
= 11, .max
= 156 },
381 .p1
= { .min
= 2, .max
= 3 },
382 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
385 static const intel_limit_t intel_limits_chv
= {
387 * These are the data rate limits (measured in fast clocks)
388 * since those are the strictest limits we have. The fast
389 * clock and actual rate limits are more relaxed, so checking
390 * them would make no difference.
392 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
393 .vco
= { .min
= 4860000, .max
= 6700000 },
394 .n
= { .min
= 1, .max
= 1 },
395 .m1
= { .min
= 2, .max
= 2 },
396 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
397 .p1
= { .min
= 2, .max
= 4 },
398 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
401 static void vlv_clock(int refclk
, intel_clock_t
*clock
)
403 clock
->m
= clock
->m1
* clock
->m2
;
404 clock
->p
= clock
->p1
* clock
->p2
;
405 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
407 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
408 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
412 * Returns whether any output on the specified pipe is of the specified type
414 static bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
416 struct drm_device
*dev
= crtc
->dev
;
417 struct intel_encoder
*encoder
;
419 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
420 if (encoder
->type
== type
)
426 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
429 struct drm_device
*dev
= crtc
->dev
;
430 const intel_limit_t
*limit
;
432 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
433 if (intel_is_dual_link_lvds(dev
)) {
434 if (refclk
== 100000)
435 limit
= &intel_limits_ironlake_dual_lvds_100m
;
437 limit
= &intel_limits_ironlake_dual_lvds
;
439 if (refclk
== 100000)
440 limit
= &intel_limits_ironlake_single_lvds_100m
;
442 limit
= &intel_limits_ironlake_single_lvds
;
445 limit
= &intel_limits_ironlake_dac
;
450 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
452 struct drm_device
*dev
= crtc
->dev
;
453 const intel_limit_t
*limit
;
455 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
456 if (intel_is_dual_link_lvds(dev
))
457 limit
= &intel_limits_g4x_dual_channel_lvds
;
459 limit
= &intel_limits_g4x_single_channel_lvds
;
460 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
461 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
462 limit
= &intel_limits_g4x_hdmi
;
463 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
464 limit
= &intel_limits_g4x_sdvo
;
465 } else /* The option is for other outputs */
466 limit
= &intel_limits_i9xx_sdvo
;
471 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
473 struct drm_device
*dev
= crtc
->dev
;
474 const intel_limit_t
*limit
;
476 if (HAS_PCH_SPLIT(dev
))
477 limit
= intel_ironlake_limit(crtc
, refclk
);
478 else if (IS_G4X(dev
)) {
479 limit
= intel_g4x_limit(crtc
);
480 } else if (IS_PINEVIEW(dev
)) {
481 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
482 limit
= &intel_limits_pineview_lvds
;
484 limit
= &intel_limits_pineview_sdvo
;
485 } else if (IS_CHERRYVIEW(dev
)) {
486 limit
= &intel_limits_chv
;
487 } else if (IS_VALLEYVIEW(dev
)) {
488 limit
= &intel_limits_vlv
;
489 } else if (!IS_GEN2(dev
)) {
490 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
491 limit
= &intel_limits_i9xx_lvds
;
493 limit
= &intel_limits_i9xx_sdvo
;
495 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
496 limit
= &intel_limits_i8xx_lvds
;
497 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
))
498 limit
= &intel_limits_i8xx_dvo
;
500 limit
= &intel_limits_i8xx_dac
;
505 /* m1 is reserved as 0 in Pineview, n is a ring counter */
506 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
508 clock
->m
= clock
->m2
+ 2;
509 clock
->p
= clock
->p1
* clock
->p2
;
510 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
512 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
513 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
516 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
518 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
521 static void i9xx_clock(int refclk
, intel_clock_t
*clock
)
523 clock
->m
= i9xx_dpll_compute_m(clock
);
524 clock
->p
= clock
->p1
* clock
->p2
;
525 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
527 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
528 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
531 static void chv_clock(int refclk
, intel_clock_t
*clock
)
533 clock
->m
= clock
->m1
* clock
->m2
;
534 clock
->p
= clock
->p1
* clock
->p2
;
535 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
537 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
539 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
542 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
548 static bool intel_PLL_is_valid(struct drm_device
*dev
,
549 const intel_limit_t
*limit
,
550 const intel_clock_t
*clock
)
552 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
553 INTELPllInvalid("n out of range\n");
554 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
555 INTELPllInvalid("p1 out of range\n");
556 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
557 INTELPllInvalid("m2 out of range\n");
558 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
559 INTELPllInvalid("m1 out of range\n");
561 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
))
562 if (clock
->m1
<= clock
->m2
)
563 INTELPllInvalid("m1 <= m2\n");
565 if (!IS_VALLEYVIEW(dev
)) {
566 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
567 INTELPllInvalid("p out of range\n");
568 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
569 INTELPllInvalid("m out of range\n");
572 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
573 INTELPllInvalid("vco out of range\n");
574 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
575 * connector, etc., rather than just a single range.
577 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
578 INTELPllInvalid("dot out of range\n");
584 i9xx_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
585 int target
, int refclk
, intel_clock_t
*match_clock
,
586 intel_clock_t
*best_clock
)
588 struct drm_device
*dev
= crtc
->dev
;
592 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
594 * For LVDS just rely on its current settings for dual-channel.
595 * We haven't figured out how to reliably set up different
596 * single/dual channel state, if we even can.
598 if (intel_is_dual_link_lvds(dev
))
599 clock
.p2
= limit
->p2
.p2_fast
;
601 clock
.p2
= limit
->p2
.p2_slow
;
603 if (target
< limit
->p2
.dot_limit
)
604 clock
.p2
= limit
->p2
.p2_slow
;
606 clock
.p2
= limit
->p2
.p2_fast
;
609 memset(best_clock
, 0, sizeof(*best_clock
));
611 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
613 for (clock
.m2
= limit
->m2
.min
;
614 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
615 if (clock
.m2
>= clock
.m1
)
617 for (clock
.n
= limit
->n
.min
;
618 clock
.n
<= limit
->n
.max
; clock
.n
++) {
619 for (clock
.p1
= limit
->p1
.min
;
620 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
623 i9xx_clock(refclk
, &clock
);
624 if (!intel_PLL_is_valid(dev
, limit
,
628 clock
.p
!= match_clock
->p
)
631 this_err
= abs(clock
.dot
- target
);
632 if (this_err
< err
) {
641 return (err
!= target
);
645 pnv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
646 int target
, int refclk
, intel_clock_t
*match_clock
,
647 intel_clock_t
*best_clock
)
649 struct drm_device
*dev
= crtc
->dev
;
653 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
655 * For LVDS just rely on its current settings for dual-channel.
656 * We haven't figured out how to reliably set up different
657 * single/dual channel state, if we even can.
659 if (intel_is_dual_link_lvds(dev
))
660 clock
.p2
= limit
->p2
.p2_fast
;
662 clock
.p2
= limit
->p2
.p2_slow
;
664 if (target
< limit
->p2
.dot_limit
)
665 clock
.p2
= limit
->p2
.p2_slow
;
667 clock
.p2
= limit
->p2
.p2_fast
;
670 memset(best_clock
, 0, sizeof(*best_clock
));
672 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
674 for (clock
.m2
= limit
->m2
.min
;
675 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
676 for (clock
.n
= limit
->n
.min
;
677 clock
.n
<= limit
->n
.max
; clock
.n
++) {
678 for (clock
.p1
= limit
->p1
.min
;
679 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
682 pineview_clock(refclk
, &clock
);
683 if (!intel_PLL_is_valid(dev
, limit
,
687 clock
.p
!= match_clock
->p
)
690 this_err
= abs(clock
.dot
- target
);
691 if (this_err
< err
) {
700 return (err
!= target
);
704 g4x_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
705 int target
, int refclk
, intel_clock_t
*match_clock
,
706 intel_clock_t
*best_clock
)
708 struct drm_device
*dev
= crtc
->dev
;
712 /* approximately equals target * 0.00585 */
713 int err_most
= (target
>> 8) + (target
>> 9);
716 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
717 if (intel_is_dual_link_lvds(dev
))
718 clock
.p2
= limit
->p2
.p2_fast
;
720 clock
.p2
= limit
->p2
.p2_slow
;
722 if (target
< limit
->p2
.dot_limit
)
723 clock
.p2
= limit
->p2
.p2_slow
;
725 clock
.p2
= limit
->p2
.p2_fast
;
728 memset(best_clock
, 0, sizeof(*best_clock
));
729 max_n
= limit
->n
.max
;
730 /* based on hardware requirement, prefer smaller n to precision */
731 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
732 /* based on hardware requirement, prefere larger m1,m2 */
733 for (clock
.m1
= limit
->m1
.max
;
734 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
735 for (clock
.m2
= limit
->m2
.max
;
736 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
737 for (clock
.p1
= limit
->p1
.max
;
738 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
741 i9xx_clock(refclk
, &clock
);
742 if (!intel_PLL_is_valid(dev
, limit
,
746 this_err
= abs(clock
.dot
- target
);
747 if (this_err
< err_most
) {
761 vlv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
762 int target
, int refclk
, intel_clock_t
*match_clock
,
763 intel_clock_t
*best_clock
)
765 struct drm_device
*dev
= crtc
->dev
;
767 unsigned int bestppm
= 1000000;
768 /* min update 19.2 MHz */
769 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
772 target
*= 5; /* fast clock */
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
778 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
779 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
780 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
781 clock
.p
= clock
.p1
* clock
.p2
;
782 /* based on hardware requirement, prefer bigger m1,m2 values */
783 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
784 unsigned int ppm
, diff
;
786 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
789 vlv_clock(refclk
, &clock
);
791 if (!intel_PLL_is_valid(dev
, limit
,
795 diff
= abs(clock
.dot
- target
);
796 ppm
= div_u64(1000000ULL * diff
, target
);
798 if (ppm
< 100 && clock
.p
> best_clock
->p
) {
804 if (bestppm
>= 10 && ppm
< bestppm
- 10) {
818 chv_find_best_dpll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
819 int target
, int refclk
, intel_clock_t
*match_clock
,
820 intel_clock_t
*best_clock
)
822 struct drm_device
*dev
= crtc
->dev
;
827 memset(best_clock
, 0, sizeof(*best_clock
));
830 * Based on hardware doc, the n always set to 1, and m1 always
831 * set to 2. If requires to support 200Mhz refclk, we need to
832 * revisit this because n may not 1 anymore.
834 clock
.n
= 1, clock
.m1
= 2;
835 target
*= 5; /* fast clock */
837 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
838 for (clock
.p2
= limit
->p2
.p2_fast
;
839 clock
.p2
>= limit
->p2
.p2_slow
;
840 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
842 clock
.p
= clock
.p1
* clock
.p2
;
844 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
845 clock
.n
) << 22, refclk
* clock
.m1
);
847 if (m2
> INT_MAX
/clock
.m1
)
852 chv_clock(refclk
, &clock
);
854 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
857 /* based on hardware requirement, prefer bigger p
859 if (clock
.p
> best_clock
->p
) {
869 bool intel_crtc_active(struct drm_crtc
*crtc
)
871 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
873 /* Be paranoid as we can arrive here with only partial
874 * state retrieved from the hardware during setup.
876 * We can ditch the adjusted_mode.crtc_clock check as soon
877 * as Haswell has gained clock readout/fastboot support.
879 * We can ditch the crtc->primary->fb check as soon as we can
880 * properly reconstruct framebuffers.
882 return intel_crtc
->active
&& crtc
->primary
->fb
&&
883 intel_crtc
->config
.adjusted_mode
.crtc_clock
;
886 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
889 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
892 return intel_crtc
->config
.cpu_transcoder
;
895 static void g4x_wait_for_vblank(struct drm_device
*dev
, int pipe
)
897 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
898 u32 frame
, frame_reg
= PIPE_FRMCOUNT_GM45(pipe
);
900 frame
= I915_READ(frame_reg
);
902 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
903 WARN(1, "vblank wait on pipe %c timed out\n",
908 * intel_wait_for_vblank - wait for vblank on a given pipe
910 * @pipe: pipe to wait for
912 * Wait for vblank to occur on a given pipe. Needed for various bits of
915 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
917 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
918 int pipestat_reg
= PIPESTAT(pipe
);
920 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
921 g4x_wait_for_vblank(dev
, pipe
);
925 /* Clear existing vblank status. Note this will clear any other
926 * sticky status fields as well.
928 * This races with i915_driver_irq_handler() with the result
929 * that either function could miss a vblank event. Here it is not
930 * fatal, as we will either wait upon the next vblank interrupt or
931 * timeout. Generally speaking intel_wait_for_vblank() is only
932 * called during modeset at which time the GPU should be idle and
933 * should *not* be performing page flips and thus not waiting on
935 * Currently, the result of us stealing a vblank from the irq
936 * handler is that a single frame will be skipped during swapbuffers.
938 I915_WRITE(pipestat_reg
,
939 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
941 /* Wait for vblank interrupt bit to set */
942 if (wait_for(I915_READ(pipestat_reg
) &
943 PIPE_VBLANK_INTERRUPT_STATUS
,
945 DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n",
949 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 u32 reg
= PIPEDSL(pipe
);
957 line_mask
= DSL_LINEMASK_GEN2
;
959 line_mask
= DSL_LINEMASK_GEN3
;
961 line1
= I915_READ(reg
) & line_mask
;
963 line2
= I915_READ(reg
) & line_mask
;
965 return line1
== line2
;
969 * intel_wait_for_pipe_off - wait for pipe to turn off
971 * @pipe: pipe to wait for
973 * After disabling a pipe, we can't wait for vblank in the usual way,
974 * spinning on the vblank interrupt status bit, since we won't actually
975 * see an interrupt when the pipe is disabled.
978 * wait for the pipe register state bit to turn off
981 * wait for the display line value to settle (it usually
982 * ends up stopping at the start of the next frame).
985 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
987 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
988 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
991 if (INTEL_INFO(dev
)->gen
>= 4) {
992 int reg
= PIPECONF(cpu_transcoder
);
994 /* Wait for the Pipe State to go off */
995 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
997 WARN(1, "pipe_off wait timed out\n");
999 /* Wait for the display line to settle */
1000 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1001 WARN(1, "pipe_off wait timed out\n");
1006 * ibx_digital_port_connected - is the specified port connected?
1007 * @dev_priv: i915 private structure
1008 * @port: the port to test
1010 * Returns true if @port is connected, false otherwise.
1012 bool ibx_digital_port_connected(struct drm_i915_private
*dev_priv
,
1013 struct intel_digital_port
*port
)
1017 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1018 switch (port
->port
) {
1020 bit
= SDE_PORTB_HOTPLUG
;
1023 bit
= SDE_PORTC_HOTPLUG
;
1026 bit
= SDE_PORTD_HOTPLUG
;
1032 switch (port
->port
) {
1034 bit
= SDE_PORTB_HOTPLUG_CPT
;
1037 bit
= SDE_PORTC_HOTPLUG_CPT
;
1040 bit
= SDE_PORTD_HOTPLUG_CPT
;
1047 return I915_READ(SDEISR
) & bit
;
1050 static const char *state_string(bool enabled
)
1052 return enabled
? "on" : "off";
1055 /* Only for pre-ILK configs */
1056 void assert_pll(struct drm_i915_private
*dev_priv
,
1057 enum pipe pipe
, bool state
)
1064 val
= I915_READ(reg
);
1065 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1066 WARN(cur_state
!= state
,
1067 "PLL state assertion failure (expected %s, current %s)\n",
1068 state_string(state
), state_string(cur_state
));
1071 /* XXX: the dsi pll is shared between MIPI DSI ports */
1072 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1077 mutex_lock(&dev_priv
->dpio_lock
);
1078 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1079 mutex_unlock(&dev_priv
->dpio_lock
);
1081 cur_state
= val
& DSI_PLL_VCO_EN
;
1082 WARN(cur_state
!= state
,
1083 "DSI PLL state assertion failure (expected %s, current %s)\n",
1084 state_string(state
), state_string(cur_state
));
1086 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1087 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1089 struct intel_shared_dpll
*
1090 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1092 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1094 if (crtc
->config
.shared_dpll
< 0)
1097 return &dev_priv
->shared_dplls
[crtc
->config
.shared_dpll
];
1101 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1102 struct intel_shared_dpll
*pll
,
1106 struct intel_dpll_hw_state hw_state
;
1109 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1112 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1113 WARN(cur_state
!= state
,
1114 "%s assertion failure (expected %s, current %s)\n",
1115 pll
->name
, state_string(state
), state_string(cur_state
));
1118 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1119 enum pipe pipe
, bool state
)
1124 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1127 if (HAS_DDI(dev_priv
->dev
)) {
1128 /* DDI does not have a specific FDI_TX register */
1129 reg
= TRANS_DDI_FUNC_CTL(cpu_transcoder
);
1130 val
= I915_READ(reg
);
1131 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1133 reg
= FDI_TX_CTL(pipe
);
1134 val
= I915_READ(reg
);
1135 cur_state
= !!(val
& FDI_TX_ENABLE
);
1137 WARN(cur_state
!= state
,
1138 "FDI TX state assertion failure (expected %s, current %s)\n",
1139 state_string(state
), state_string(cur_state
));
1141 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1142 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1144 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1145 enum pipe pipe
, bool state
)
1151 reg
= FDI_RX_CTL(pipe
);
1152 val
= I915_READ(reg
);
1153 cur_state
= !!(val
& FDI_RX_ENABLE
);
1154 WARN(cur_state
!= state
,
1155 "FDI RX state assertion failure (expected %s, current %s)\n",
1156 state_string(state
), state_string(cur_state
));
1158 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1159 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1161 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1167 /* ILK FDI PLL is always enabled */
1168 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1171 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1172 if (HAS_DDI(dev_priv
->dev
))
1175 reg
= FDI_TX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1180 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1181 enum pipe pipe
, bool state
)
1187 reg
= FDI_RX_CTL(pipe
);
1188 val
= I915_READ(reg
);
1189 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1190 WARN(cur_state
!= state
,
1191 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1192 state_string(state
), state_string(cur_state
));
1195 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1198 struct drm_device
*dev
= dev_priv
->dev
;
1201 enum pipe panel_pipe
= PIPE_A
;
1204 if (WARN_ON(HAS_DDI(dev
)))
1207 if (HAS_PCH_SPLIT(dev
)) {
1210 pp_reg
= PCH_PP_CONTROL
;
1211 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1213 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1214 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1215 panel_pipe
= PIPE_B
;
1216 /* XXX: else fix for eDP */
1217 } else if (IS_VALLEYVIEW(dev
)) {
1218 /* presumably write lock depends on pipe, not port select */
1219 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1222 pp_reg
= PP_CONTROL
;
1223 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1224 panel_pipe
= PIPE_B
;
1227 val
= I915_READ(pp_reg
);
1228 if (!(val
& PANEL_POWER_ON
) ||
1229 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1232 WARN(panel_pipe
== pipe
&& locked
,
1233 "panel assertion failure, pipe %c regs locked\n",
1237 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1238 enum pipe pipe
, bool state
)
1240 struct drm_device
*dev
= dev_priv
->dev
;
1243 if (IS_845G(dev
) || IS_I865G(dev
))
1244 cur_state
= I915_READ(_CURACNTR
) & CURSOR_ENABLE
;
1246 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1248 WARN(cur_state
!= state
,
1249 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1252 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1253 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1255 void assert_pipe(struct drm_i915_private
*dev_priv
,
1256 enum pipe pipe
, bool state
)
1261 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1264 /* if we need the pipe A quirk it must be always on */
1265 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1268 if (!intel_display_power_enabled(dev_priv
,
1269 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1272 reg
= PIPECONF(cpu_transcoder
);
1273 val
= I915_READ(reg
);
1274 cur_state
= !!(val
& PIPECONF_ENABLE
);
1277 WARN(cur_state
!= state
,
1278 "pipe %c assertion failure (expected %s, current %s)\n",
1279 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1282 static void assert_plane(struct drm_i915_private
*dev_priv
,
1283 enum plane plane
, bool state
)
1289 reg
= DSPCNTR(plane
);
1290 val
= I915_READ(reg
);
1291 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1292 WARN(cur_state
!= state
,
1293 "plane %c assertion failure (expected %s, current %s)\n",
1294 plane_name(plane
), state_string(state
), state_string(cur_state
));
1297 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1298 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1300 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1303 struct drm_device
*dev
= dev_priv
->dev
;
1308 /* Primary planes are fixed to pipes on gen4+ */
1309 if (INTEL_INFO(dev
)->gen
>= 4) {
1310 reg
= DSPCNTR(pipe
);
1311 val
= I915_READ(reg
);
1312 WARN(val
& DISPLAY_PLANE_ENABLE
,
1313 "plane %c assertion failure, should be disabled but not\n",
1318 /* Need to check both planes against the pipe */
1319 for_each_pipe(dev_priv
, i
) {
1321 val
= I915_READ(reg
);
1322 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1323 DISPPLANE_SEL_PIPE_SHIFT
;
1324 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1325 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1326 plane_name(i
), pipe_name(pipe
));
1330 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1333 struct drm_device
*dev
= dev_priv
->dev
;
1337 if (IS_VALLEYVIEW(dev
)) {
1338 for_each_sprite(pipe
, sprite
) {
1339 reg
= SPCNTR(pipe
, sprite
);
1340 val
= I915_READ(reg
);
1341 WARN(val
& SP_ENABLE
,
1342 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1343 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1345 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1347 val
= I915_READ(reg
);
1348 WARN(val
& SPRITE_ENABLE
,
1349 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1350 plane_name(pipe
), pipe_name(pipe
));
1351 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1352 reg
= DVSCNTR(pipe
);
1353 val
= I915_READ(reg
);
1354 WARN(val
& DVS_ENABLE
,
1355 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1356 plane_name(pipe
), pipe_name(pipe
));
1360 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1365 WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1367 val
= I915_READ(PCH_DREF_CONTROL
);
1368 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1369 DREF_SUPERSPREAD_SOURCE_MASK
));
1370 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1373 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1380 reg
= PCH_TRANSCONF(pipe
);
1381 val
= I915_READ(reg
);
1382 enabled
= !!(val
& TRANS_ENABLE
);
1384 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1388 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1389 enum pipe pipe
, u32 port_sel
, u32 val
)
1391 if ((val
& DP_PORT_EN
) == 0)
1394 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1395 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1396 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1397 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1399 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1400 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1403 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1409 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1410 enum pipe pipe
, u32 val
)
1412 if ((val
& SDVO_ENABLE
) == 0)
1415 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1416 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1418 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1419 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1422 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1428 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1429 enum pipe pipe
, u32 val
)
1431 if ((val
& LVDS_PORT_EN
) == 0)
1434 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1435 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1438 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1444 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1445 enum pipe pipe
, u32 val
)
1447 if ((val
& ADPA_DAC_ENABLE
) == 0)
1449 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1450 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1453 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1459 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1460 enum pipe pipe
, int reg
, u32 port_sel
)
1462 u32 val
= I915_READ(reg
);
1463 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1464 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1465 reg
, pipe_name(pipe
));
1467 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1468 && (val
& DP_PIPEB_SELECT
),
1469 "IBX PCH dp port still using transcoder B\n");
1472 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1473 enum pipe pipe
, int reg
)
1475 u32 val
= I915_READ(reg
);
1476 WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1477 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1478 reg
, pipe_name(pipe
));
1480 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1481 && (val
& SDVO_PIPE_B_SELECT
),
1482 "IBX PCH hdmi port still using transcoder B\n");
1485 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1491 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1492 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1493 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1496 val
= I915_READ(reg
);
1497 WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1498 "PCH VGA enabled on transcoder %c, should be disabled\n",
1502 val
= I915_READ(reg
);
1503 WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1504 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1507 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1508 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1509 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1512 static void intel_init_dpio(struct drm_device
*dev
)
1514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1516 if (!IS_VALLEYVIEW(dev
))
1520 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1521 * CHV x1 PHY (DP/HDMI D)
1522 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1524 if (IS_CHERRYVIEW(dev
)) {
1525 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO_2
;
1526 DPIO_PHY_IOSF_PORT(DPIO_PHY1
) = IOSF_PORT_DPIO
;
1528 DPIO_PHY_IOSF_PORT(DPIO_PHY0
) = IOSF_PORT_DPIO
;
1532 static void vlv_enable_pll(struct intel_crtc
*crtc
)
1534 struct drm_device
*dev
= crtc
->base
.dev
;
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1536 int reg
= DPLL(crtc
->pipe
);
1537 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1539 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1541 /* No really, not for ILK+ */
1542 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1544 /* PLL is protected by panel, make sure we can write it */
1545 if (IS_MOBILE(dev_priv
->dev
))
1546 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1548 I915_WRITE(reg
, dpll
);
1552 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1553 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1555 I915_WRITE(DPLL_MD(crtc
->pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1556 POSTING_READ(DPLL_MD(crtc
->pipe
));
1558 /* We do this three times for luck */
1559 I915_WRITE(reg
, dpll
);
1561 udelay(150); /* wait for warmup */
1562 I915_WRITE(reg
, dpll
);
1564 udelay(150); /* wait for warmup */
1565 I915_WRITE(reg
, dpll
);
1567 udelay(150); /* wait for warmup */
1570 static void chv_enable_pll(struct intel_crtc
*crtc
)
1572 struct drm_device
*dev
= crtc
->base
.dev
;
1573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1574 int pipe
= crtc
->pipe
;
1575 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1578 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1580 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1582 mutex_lock(&dev_priv
->dpio_lock
);
1584 /* Enable back the 10bit clock to display controller */
1585 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1586 tmp
|= DPIO_DCLKP_EN
;
1587 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1590 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1595 I915_WRITE(DPLL(pipe
), crtc
->config
.dpll_hw_state
.dpll
);
1597 /* Check PLL is locked */
1598 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1599 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1601 /* not sure when this should be written */
1602 I915_WRITE(DPLL_MD(pipe
), crtc
->config
.dpll_hw_state
.dpll_md
);
1603 POSTING_READ(DPLL_MD(pipe
));
1605 mutex_unlock(&dev_priv
->dpio_lock
);
1608 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1610 struct drm_device
*dev
= crtc
->base
.dev
;
1611 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1612 int reg
= DPLL(crtc
->pipe
);
1613 u32 dpll
= crtc
->config
.dpll_hw_state
.dpll
;
1615 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1617 /* No really, not for ILK+ */
1618 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1620 /* PLL is protected by panel, make sure we can write it */
1621 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1622 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1624 I915_WRITE(reg
, dpll
);
1626 /* Wait for the clocks to stabilize. */
1630 if (INTEL_INFO(dev
)->gen
>= 4) {
1631 I915_WRITE(DPLL_MD(crtc
->pipe
),
1632 crtc
->config
.dpll_hw_state
.dpll_md
);
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1637 * So write it again.
1639 I915_WRITE(reg
, dpll
);
1642 /* We do this three times for luck */
1643 I915_WRITE(reg
, dpll
);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg
, dpll
);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg
, dpll
);
1651 udelay(150); /* wait for warmup */
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1661 * Note! This is for pre-ILK only.
1663 static void i9xx_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1665 /* Don't disable pipe A or pipe A PLLs if needed */
1666 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1669 /* Make sure the pipe isn't still relying on us */
1670 assert_pipe_disabled(dev_priv
, pipe
);
1672 I915_WRITE(DPLL(pipe
), 0);
1673 POSTING_READ(DPLL(pipe
));
1676 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1680 /* Make sure the pipe isn't still relying on us */
1681 assert_pipe_disabled(dev_priv
, pipe
);
1684 * Leave integrated clock source and reference clock enabled for pipe B.
1685 * The latter is needed for VGA hotplug / manual detection.
1688 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REFA_CLK_ENABLE_VLV
;
1689 I915_WRITE(DPLL(pipe
), val
);
1690 POSTING_READ(DPLL(pipe
));
1694 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1696 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1699 /* Make sure the pipe isn't still relying on us */
1700 assert_pipe_disabled(dev_priv
, pipe
);
1702 /* Set PLL en = 0 */
1703 val
= DPLL_SSC_REF_CLOCK_CHV
| DPLL_REFA_CLK_ENABLE_VLV
;
1705 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1706 I915_WRITE(DPLL(pipe
), val
);
1707 POSTING_READ(DPLL(pipe
));
1709 mutex_lock(&dev_priv
->dpio_lock
);
1711 /* Disable 10bit clock to display controller */
1712 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1713 val
&= ~DPIO_DCLKP_EN
;
1714 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1716 /* disable left/right clock distribution */
1717 if (pipe
!= PIPE_B
) {
1718 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
);
1719 val
&= ~(CHV_BUFLEFTENA1_MASK
| CHV_BUFRIGHTENA1_MASK
);
1720 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW5_CH0
, val
);
1722 val
= vlv_dpio_read(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
);
1723 val
&= ~(CHV_BUFLEFTENA2_MASK
| CHV_BUFRIGHTENA2_MASK
);
1724 vlv_dpio_write(dev_priv
, pipe
, _CHV_CMN_DW1_CH1
, val
);
1727 mutex_unlock(&dev_priv
->dpio_lock
);
1730 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1731 struct intel_digital_port
*dport
)
1736 switch (dport
->port
) {
1738 port_mask
= DPLL_PORTB_READY_MASK
;
1742 port_mask
= DPLL_PORTC_READY_MASK
;
1746 port_mask
= DPLL_PORTD_READY_MASK
;
1747 dpll_reg
= DPIO_PHY_STATUS
;
1753 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == 0, 1000))
1754 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1755 port_name(dport
->port
), I915_READ(dpll_reg
));
1758 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1760 struct drm_device
*dev
= crtc
->base
.dev
;
1761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1762 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1764 if (WARN_ON(pll
== NULL
))
1767 WARN_ON(!pll
->refcount
);
1768 if (pll
->active
== 0) {
1769 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1771 assert_shared_dpll_disabled(dev_priv
, pll
);
1773 pll
->mode_set(dev_priv
, pll
);
1778 * intel_enable_shared_dpll - enable PCH PLL
1779 * @dev_priv: i915 private structure
1780 * @pipe: pipe PLL to enable
1782 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1783 * drives the transcoder clock.
1785 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1787 struct drm_device
*dev
= crtc
->base
.dev
;
1788 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1789 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1791 if (WARN_ON(pll
== NULL
))
1794 if (WARN_ON(pll
->refcount
== 0))
1797 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1798 pll
->name
, pll
->active
, pll
->on
,
1799 crtc
->base
.base
.id
);
1801 if (pll
->active
++) {
1803 assert_shared_dpll_enabled(dev_priv
, pll
);
1808 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1810 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1811 pll
->enable(dev_priv
, pll
);
1815 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1817 struct drm_device
*dev
= crtc
->base
.dev
;
1818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1819 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1821 /* PCH only available on ILK+ */
1822 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1823 if (WARN_ON(pll
== NULL
))
1826 if (WARN_ON(pll
->refcount
== 0))
1829 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1830 pll
->name
, pll
->active
, pll
->on
,
1831 crtc
->base
.base
.id
);
1833 if (WARN_ON(pll
->active
== 0)) {
1834 assert_shared_dpll_disabled(dev_priv
, pll
);
1838 assert_shared_dpll_enabled(dev_priv
, pll
);
1843 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1844 pll
->disable(dev_priv
, pll
);
1847 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1850 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1853 struct drm_device
*dev
= dev_priv
->dev
;
1854 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1856 uint32_t reg
, val
, pipeconf_val
;
1858 /* PCH only available on ILK+ */
1859 BUG_ON(INTEL_INFO(dev
)->gen
< 5);
1861 /* Make sure PCH DPLL is enabled */
1862 assert_shared_dpll_enabled(dev_priv
,
1863 intel_crtc_to_shared_dpll(intel_crtc
));
1865 /* FDI must be feeding us bits for PCH ports */
1866 assert_fdi_tx_enabled(dev_priv
, pipe
);
1867 assert_fdi_rx_enabled(dev_priv
, pipe
);
1869 if (HAS_PCH_CPT(dev
)) {
1870 /* Workaround: Set the timing override bit before enabling the
1871 * pch transcoder. */
1872 reg
= TRANS_CHICKEN2(pipe
);
1873 val
= I915_READ(reg
);
1874 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1875 I915_WRITE(reg
, val
);
1878 reg
= PCH_TRANSCONF(pipe
);
1879 val
= I915_READ(reg
);
1880 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1882 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1884 * make the BPC in transcoder be consistent with
1885 * that in pipeconf reg.
1887 val
&= ~PIPECONF_BPC_MASK
;
1888 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
1891 val
&= ~TRANS_INTERLACE_MASK
;
1892 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1893 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1894 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1895 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1897 val
|= TRANS_INTERLACED
;
1899 val
|= TRANS_PROGRESSIVE
;
1901 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1902 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1903 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
1906 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1907 enum transcoder cpu_transcoder
)
1909 u32 val
, pipeconf_val
;
1911 /* PCH only available on ILK+ */
1912 BUG_ON(INTEL_INFO(dev_priv
->dev
)->gen
< 5);
1914 /* FDI must be feeding us bits for PCH ports */
1915 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
1916 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
1918 /* Workaround: set timing override bit. */
1919 val
= I915_READ(_TRANSA_CHICKEN2
);
1920 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1921 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1924 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
1926 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
1927 PIPECONF_INTERLACED_ILK
)
1928 val
|= TRANS_INTERLACED
;
1930 val
|= TRANS_PROGRESSIVE
;
1932 I915_WRITE(LPT_TRANSCONF
, val
);
1933 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
1934 DRM_ERROR("Failed to enable PCH transcoder\n");
1937 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1940 struct drm_device
*dev
= dev_priv
->dev
;
1943 /* FDI relies on the transcoder */
1944 assert_fdi_tx_disabled(dev_priv
, pipe
);
1945 assert_fdi_rx_disabled(dev_priv
, pipe
);
1947 /* Ports must be off as well */
1948 assert_pch_ports_disabled(dev_priv
, pipe
);
1950 reg
= PCH_TRANSCONF(pipe
);
1951 val
= I915_READ(reg
);
1952 val
&= ~TRANS_ENABLE
;
1953 I915_WRITE(reg
, val
);
1954 /* wait for PCH transcoder off, transcoder state */
1955 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1956 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
1958 if (!HAS_PCH_IBX(dev
)) {
1959 /* Workaround: Clear the timing override chicken bit again. */
1960 reg
= TRANS_CHICKEN2(pipe
);
1961 val
= I915_READ(reg
);
1962 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1963 I915_WRITE(reg
, val
);
1967 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
1971 val
= I915_READ(LPT_TRANSCONF
);
1972 val
&= ~TRANS_ENABLE
;
1973 I915_WRITE(LPT_TRANSCONF
, val
);
1974 /* wait for PCH transcoder off, transcoder state */
1975 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
1976 DRM_ERROR("Failed to disable PCH transcoder\n");
1978 /* Workaround: clear timing override bit. */
1979 val
= I915_READ(_TRANSA_CHICKEN2
);
1980 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
1981 I915_WRITE(_TRANSA_CHICKEN2
, val
);
1985 * intel_enable_pipe - enable a pipe, asserting requirements
1986 * @crtc: crtc responsible for the pipe
1988 * Enable @crtc's pipe, making sure that various hardware specific requirements
1989 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1991 static void intel_enable_pipe(struct intel_crtc
*crtc
)
1993 struct drm_device
*dev
= crtc
->base
.dev
;
1994 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1995 enum pipe pipe
= crtc
->pipe
;
1996 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1998 enum pipe pch_transcoder
;
2002 assert_planes_disabled(dev_priv
, pipe
);
2003 assert_cursor_disabled(dev_priv
, pipe
);
2004 assert_sprites_disabled(dev_priv
, pipe
);
2006 if (HAS_PCH_LPT(dev_priv
->dev
))
2007 pch_transcoder
= TRANSCODER_A
;
2009 pch_transcoder
= pipe
;
2012 * A pipe without a PLL won't actually be able to drive bits from
2013 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2016 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
2017 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DSI
))
2018 assert_dsi_pll_enabled(dev_priv
);
2020 assert_pll_enabled(dev_priv
, pipe
);
2022 if (crtc
->config
.has_pch_encoder
) {
2023 /* if driving the PCH, we need FDI enabled */
2024 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2025 assert_fdi_tx_pll_enabled(dev_priv
,
2026 (enum pipe
) cpu_transcoder
);
2028 /* FIXME: assert CPU port conditions for SNB+ */
2031 reg
= PIPECONF(cpu_transcoder
);
2032 val
= I915_READ(reg
);
2033 if (val
& PIPECONF_ENABLE
) {
2034 WARN_ON(!(pipe
== PIPE_A
&&
2035 dev_priv
->quirks
& QUIRK_PIPEA_FORCE
));
2039 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2044 * intel_disable_pipe - disable a pipe, asserting requirements
2045 * @dev_priv: i915 private structure
2046 * @pipe: pipe to disable
2048 * Disable @pipe, making sure that various hardware specific requirements
2049 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2051 * @pipe should be %PIPE_A or %PIPE_B.
2053 * Will wait until the pipe has shut down before returning.
2055 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
2058 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2064 * Make sure planes won't keep trying to pump pixels to us,
2065 * or we might hang the display.
2067 assert_planes_disabled(dev_priv
, pipe
);
2068 assert_cursor_disabled(dev_priv
, pipe
);
2069 assert_sprites_disabled(dev_priv
, pipe
);
2071 /* Don't disable pipe A or pipe A PLLs if needed */
2072 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
2075 reg
= PIPECONF(cpu_transcoder
);
2076 val
= I915_READ(reg
);
2077 if ((val
& PIPECONF_ENABLE
) == 0)
2080 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
2081 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
2085 * Plane regs are double buffered, going from enabled->disabled needs a
2086 * trigger in order to latch. The display address reg provides this.
2088 void intel_flush_primary_plane(struct drm_i915_private
*dev_priv
,
2091 struct drm_device
*dev
= dev_priv
->dev
;
2092 u32 reg
= INTEL_INFO(dev
)->gen
>= 4 ? DSPSURF(plane
) : DSPADDR(plane
);
2094 I915_WRITE(reg
, I915_READ(reg
));
2099 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2100 * @plane: plane to be enabled
2101 * @crtc: crtc for the plane
2103 * Enable @plane on @crtc, making sure that the pipe is running first.
2105 static void intel_enable_primary_hw_plane(struct drm_plane
*plane
,
2106 struct drm_crtc
*crtc
)
2108 struct drm_device
*dev
= plane
->dev
;
2109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2110 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2112 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2113 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2115 if (intel_crtc
->primary_enabled
)
2118 intel_crtc
->primary_enabled
= true;
2120 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2124 * BDW signals flip done immediately if the plane
2125 * is disabled, even if the plane enable is already
2126 * armed to occur at the next vblank :(
2128 if (IS_BROADWELL(dev
))
2129 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2133 * intel_disable_primary_hw_plane - disable the primary hardware plane
2134 * @plane: plane to be disabled
2135 * @crtc: crtc for the plane
2137 * Disable @plane on @crtc, making sure that the pipe is running first.
2139 static void intel_disable_primary_hw_plane(struct drm_plane
*plane
,
2140 struct drm_crtc
*crtc
)
2142 struct drm_device
*dev
= plane
->dev
;
2143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2144 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2146 assert_pipe_enabled(dev_priv
, intel_crtc
->pipe
);
2148 if (!intel_crtc
->primary_enabled
)
2151 intel_crtc
->primary_enabled
= false;
2153 dev_priv
->display
.update_primary_plane(crtc
, plane
->fb
,
2157 static bool need_vtd_wa(struct drm_device
*dev
)
2159 #ifdef CONFIG_INTEL_IOMMU
2160 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2166 static int intel_align_height(struct drm_device
*dev
, int height
, bool tiled
)
2170 tile_height
= tiled
? (IS_GEN2(dev
) ? 16 : 8) : 1;
2171 return ALIGN(height
, tile_height
);
2175 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
2176 struct drm_i915_gem_object
*obj
,
2177 struct intel_engine_cs
*pipelined
)
2179 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2183 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2185 switch (obj
->tiling_mode
) {
2186 case I915_TILING_NONE
:
2187 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
2188 alignment
= 128 * 1024;
2189 else if (INTEL_INFO(dev
)->gen
>= 4)
2190 alignment
= 4 * 1024;
2192 alignment
= 64 * 1024;
2195 /* pin() will align the object as required by fence */
2199 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2205 /* Note that the w/a also requires 64 PTE of padding following the
2206 * bo. We currently fill all unused PTE with the shadow page and so
2207 * we should always have valid PTE following the scanout preventing
2210 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2211 alignment
= 256 * 1024;
2213 dev_priv
->mm
.interruptible
= false;
2214 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
2216 goto err_interruptible
;
2218 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2219 * fence, whereas 965+ only requires a fence if using
2220 * framebuffer compression. For simplicity, we always install
2221 * a fence as the cost is not that onerous.
2223 ret
= i915_gem_object_get_fence(obj
);
2227 i915_gem_object_pin_fence(obj
);
2229 dev_priv
->mm
.interruptible
= true;
2233 i915_gem_object_unpin_from_display_plane(obj
);
2235 dev_priv
->mm
.interruptible
= true;
2239 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
2241 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2243 i915_gem_object_unpin_fence(obj
);
2244 i915_gem_object_unpin_from_display_plane(obj
);
2247 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2248 * is assumed to be a power-of-two. */
2249 unsigned long intel_gen4_compute_page_offset(int *x
, int *y
,
2250 unsigned int tiling_mode
,
2254 if (tiling_mode
!= I915_TILING_NONE
) {
2255 unsigned int tile_rows
, tiles
;
2260 tiles
= *x
/ (512/cpp
);
2263 return tile_rows
* pitch
* 8 + tiles
* 4096;
2265 unsigned int offset
;
2267 offset
= *y
* pitch
+ *x
* cpp
;
2269 *x
= (offset
& 4095) / cpp
;
2270 return offset
& -4096;
2274 int intel_format_to_fourcc(int format
)
2277 case DISPPLANE_8BPP
:
2278 return DRM_FORMAT_C8
;
2279 case DISPPLANE_BGRX555
:
2280 return DRM_FORMAT_XRGB1555
;
2281 case DISPPLANE_BGRX565
:
2282 return DRM_FORMAT_RGB565
;
2284 case DISPPLANE_BGRX888
:
2285 return DRM_FORMAT_XRGB8888
;
2286 case DISPPLANE_RGBX888
:
2287 return DRM_FORMAT_XBGR8888
;
2288 case DISPPLANE_BGRX101010
:
2289 return DRM_FORMAT_XRGB2101010
;
2290 case DISPPLANE_RGBX101010
:
2291 return DRM_FORMAT_XBGR2101010
;
2295 static bool intel_alloc_plane_obj(struct intel_crtc
*crtc
,
2296 struct intel_plane_config
*plane_config
)
2298 struct drm_device
*dev
= crtc
->base
.dev
;
2299 struct drm_i915_gem_object
*obj
= NULL
;
2300 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2301 u32 base
= plane_config
->base
;
2303 if (plane_config
->size
== 0)
2306 obj
= i915_gem_object_create_stolen_for_preallocated(dev
, base
, base
,
2307 plane_config
->size
);
2311 if (plane_config
->tiled
) {
2312 obj
->tiling_mode
= I915_TILING_X
;
2313 obj
->stride
= crtc
->base
.primary
->fb
->pitches
[0];
2316 mode_cmd
.pixel_format
= crtc
->base
.primary
->fb
->pixel_format
;
2317 mode_cmd
.width
= crtc
->base
.primary
->fb
->width
;
2318 mode_cmd
.height
= crtc
->base
.primary
->fb
->height
;
2319 mode_cmd
.pitches
[0] = crtc
->base
.primary
->fb
->pitches
[0];
2321 mutex_lock(&dev
->struct_mutex
);
2323 if (intel_framebuffer_init(dev
, to_intel_framebuffer(crtc
->base
.primary
->fb
),
2325 DRM_DEBUG_KMS("intel fb init failed\n");
2329 obj
->frontbuffer_bits
= INTEL_FRONTBUFFER_PRIMARY(crtc
->pipe
);
2330 mutex_unlock(&dev
->struct_mutex
);
2332 DRM_DEBUG_KMS("plane fb obj %p\n", obj
);
2336 drm_gem_object_unreference(&obj
->base
);
2337 mutex_unlock(&dev
->struct_mutex
);
2341 static void intel_find_plane_obj(struct intel_crtc
*intel_crtc
,
2342 struct intel_plane_config
*plane_config
)
2344 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2346 struct intel_crtc
*i
;
2347 struct drm_i915_gem_object
*obj
;
2349 if (!intel_crtc
->base
.primary
->fb
)
2352 if (intel_alloc_plane_obj(intel_crtc
, plane_config
))
2355 kfree(intel_crtc
->base
.primary
->fb
);
2356 intel_crtc
->base
.primary
->fb
= NULL
;
2359 * Failed to alloc the obj, check to see if we should share
2360 * an fb with another CRTC instead
2362 for_each_crtc(dev
, c
) {
2363 i
= to_intel_crtc(c
);
2365 if (c
== &intel_crtc
->base
)
2371 obj
= intel_fb_obj(c
->primary
->fb
);
2375 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2376 drm_framebuffer_reference(c
->primary
->fb
);
2377 intel_crtc
->base
.primary
->fb
= c
->primary
->fb
;
2378 obj
->frontbuffer_bits
|= INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
);
2384 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2385 struct drm_framebuffer
*fb
,
2388 struct drm_device
*dev
= crtc
->dev
;
2389 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2390 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2391 struct drm_i915_gem_object
*obj
;
2392 int plane
= intel_crtc
->plane
;
2393 unsigned long linear_offset
;
2395 u32 reg
= DSPCNTR(plane
);
2398 if (!intel_crtc
->primary_enabled
) {
2400 if (INTEL_INFO(dev
)->gen
>= 4)
2401 I915_WRITE(DSPSURF(plane
), 0);
2403 I915_WRITE(DSPADDR(plane
), 0);
2408 obj
= intel_fb_obj(fb
);
2409 if (WARN_ON(obj
== NULL
))
2412 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2414 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2416 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2418 if (INTEL_INFO(dev
)->gen
< 4) {
2419 if (intel_crtc
->pipe
== PIPE_B
)
2420 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2422 /* pipesrc and dspsize control the size that is scaled from,
2423 * which should always be the user's requested size.
2425 I915_WRITE(DSPSIZE(plane
),
2426 ((intel_crtc
->config
.pipe_src_h
- 1) << 16) |
2427 (intel_crtc
->config
.pipe_src_w
- 1));
2428 I915_WRITE(DSPPOS(plane
), 0);
2431 switch (fb
->pixel_format
) {
2433 dspcntr
|= DISPPLANE_8BPP
;
2435 case DRM_FORMAT_XRGB1555
:
2436 case DRM_FORMAT_ARGB1555
:
2437 dspcntr
|= DISPPLANE_BGRX555
;
2439 case DRM_FORMAT_RGB565
:
2440 dspcntr
|= DISPPLANE_BGRX565
;
2442 case DRM_FORMAT_XRGB8888
:
2443 case DRM_FORMAT_ARGB8888
:
2444 dspcntr
|= DISPPLANE_BGRX888
;
2446 case DRM_FORMAT_XBGR8888
:
2447 case DRM_FORMAT_ABGR8888
:
2448 dspcntr
|= DISPPLANE_RGBX888
;
2450 case DRM_FORMAT_XRGB2101010
:
2451 case DRM_FORMAT_ARGB2101010
:
2452 dspcntr
|= DISPPLANE_BGRX101010
;
2454 case DRM_FORMAT_XBGR2101010
:
2455 case DRM_FORMAT_ABGR2101010
:
2456 dspcntr
|= DISPPLANE_RGBX101010
;
2462 if (INTEL_INFO(dev
)->gen
>= 4 &&
2463 obj
->tiling_mode
!= I915_TILING_NONE
)
2464 dspcntr
|= DISPPLANE_TILED
;
2467 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2469 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2471 if (INTEL_INFO(dev
)->gen
>= 4) {
2472 intel_crtc
->dspaddr_offset
=
2473 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2476 linear_offset
-= intel_crtc
->dspaddr_offset
;
2478 intel_crtc
->dspaddr_offset
= linear_offset
;
2481 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2482 dspcntr
|= DISPPLANE_ROTATE_180
;
2484 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2485 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2487 /* Finding the last pixel of the last line of the display
2488 data and adding to linear_offset*/
2490 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2491 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2494 I915_WRITE(reg
, dspcntr
);
2496 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2497 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2499 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2500 if (INTEL_INFO(dev
)->gen
>= 4) {
2501 I915_WRITE(DSPSURF(plane
),
2502 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2503 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2504 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2506 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2510 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2511 struct drm_framebuffer
*fb
,
2514 struct drm_device
*dev
= crtc
->dev
;
2515 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2516 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2517 struct drm_i915_gem_object
*obj
;
2518 int plane
= intel_crtc
->plane
;
2519 unsigned long linear_offset
;
2521 u32 reg
= DSPCNTR(plane
);
2524 if (!intel_crtc
->primary_enabled
) {
2526 I915_WRITE(DSPSURF(plane
), 0);
2531 obj
= intel_fb_obj(fb
);
2532 if (WARN_ON(obj
== NULL
))
2535 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2537 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2539 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2541 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2542 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2544 switch (fb
->pixel_format
) {
2546 dspcntr
|= DISPPLANE_8BPP
;
2548 case DRM_FORMAT_RGB565
:
2549 dspcntr
|= DISPPLANE_BGRX565
;
2551 case DRM_FORMAT_XRGB8888
:
2552 case DRM_FORMAT_ARGB8888
:
2553 dspcntr
|= DISPPLANE_BGRX888
;
2555 case DRM_FORMAT_XBGR8888
:
2556 case DRM_FORMAT_ABGR8888
:
2557 dspcntr
|= DISPPLANE_RGBX888
;
2559 case DRM_FORMAT_XRGB2101010
:
2560 case DRM_FORMAT_ARGB2101010
:
2561 dspcntr
|= DISPPLANE_BGRX101010
;
2563 case DRM_FORMAT_XBGR2101010
:
2564 case DRM_FORMAT_ABGR2101010
:
2565 dspcntr
|= DISPPLANE_RGBX101010
;
2571 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2572 dspcntr
|= DISPPLANE_TILED
;
2574 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2575 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2577 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2578 intel_crtc
->dspaddr_offset
=
2579 intel_gen4_compute_page_offset(&x
, &y
, obj
->tiling_mode
,
2582 linear_offset
-= intel_crtc
->dspaddr_offset
;
2583 if (to_intel_plane(crtc
->primary
)->rotation
== BIT(DRM_ROTATE_180
)) {
2584 dspcntr
|= DISPPLANE_ROTATE_180
;
2586 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2587 x
+= (intel_crtc
->config
.pipe_src_w
- 1);
2588 y
+= (intel_crtc
->config
.pipe_src_h
- 1);
2590 /* Finding the last pixel of the last line of the display
2591 data and adding to linear_offset*/
2593 (intel_crtc
->config
.pipe_src_h
- 1) * fb
->pitches
[0] +
2594 (intel_crtc
->config
.pipe_src_w
- 1) * pixel_size
;
2598 I915_WRITE(reg
, dspcntr
);
2600 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2601 i915_gem_obj_ggtt_offset(obj
), linear_offset
, x
, y
,
2603 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2604 I915_WRITE(DSPSURF(plane
),
2605 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2606 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2607 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2609 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2610 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2615 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2617 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2618 int x
, int y
, enum mode_set_atomic state
)
2620 struct drm_device
*dev
= crtc
->dev
;
2621 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2623 if (dev_priv
->display
.disable_fbc
)
2624 dev_priv
->display
.disable_fbc(dev
);
2625 intel_increase_pllclock(dev
, to_intel_crtc(crtc
)->pipe
);
2627 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2632 void intel_display_handle_reset(struct drm_device
*dev
)
2634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2635 struct drm_crtc
*crtc
;
2638 * Flips in the rings have been nuked by the reset,
2639 * so complete all pending flips so that user space
2640 * will get its events and not get stuck.
2642 * Also update the base address of all primary
2643 * planes to the the last fb to make sure we're
2644 * showing the correct fb after a reset.
2646 * Need to make two loops over the crtcs so that we
2647 * don't try to grab a crtc mutex before the
2648 * pending_flip_queue really got woken up.
2651 for_each_crtc(dev
, crtc
) {
2652 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2653 enum plane plane
= intel_crtc
->plane
;
2655 intel_prepare_page_flip(dev
, plane
);
2656 intel_finish_page_flip_plane(dev
, plane
);
2659 for_each_crtc(dev
, crtc
) {
2660 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2662 drm_modeset_lock(&crtc
->mutex
, NULL
);
2664 * FIXME: Once we have proper support for primary planes (and
2665 * disabling them without disabling the entire crtc) allow again
2666 * a NULL crtc->primary->fb.
2668 if (intel_crtc
->active
&& crtc
->primary
->fb
)
2669 dev_priv
->display
.update_primary_plane(crtc
,
2673 drm_modeset_unlock(&crtc
->mutex
);
2678 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2680 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
2681 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2682 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2685 /* Big Hammer, we also need to ensure that any pending
2686 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2687 * current scanout is retired before unpinning the old
2690 * This should only fail upon a hung GPU, in which case we
2691 * can safely continue.
2693 dev_priv
->mm
.interruptible
= false;
2694 ret
= i915_gem_object_finish_gpu(obj
);
2695 dev_priv
->mm
.interruptible
= was_interruptible
;
2700 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
2702 struct drm_device
*dev
= crtc
->dev
;
2703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2704 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2705 unsigned long flags
;
2708 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
2709 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
2712 spin_lock_irqsave(&dev
->event_lock
, flags
);
2713 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
2714 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
2720 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2721 struct drm_framebuffer
*fb
)
2723 struct drm_device
*dev
= crtc
->dev
;
2724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2725 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2726 enum pipe pipe
= intel_crtc
->pipe
;
2727 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
2728 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2729 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
2732 if (intel_crtc_has_pending_flip(crtc
)) {
2733 DRM_ERROR("pipe is still busy with an old pageflip\n");
2739 DRM_ERROR("No FB bound\n");
2743 if (intel_crtc
->plane
> INTEL_INFO(dev
)->num_pipes
) {
2744 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2745 plane_name(intel_crtc
->plane
),
2746 INTEL_INFO(dev
)->num_pipes
);
2750 mutex_lock(&dev
->struct_mutex
);
2751 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
2753 i915_gem_track_fb(old_obj
, obj
,
2754 INTEL_FRONTBUFFER_PRIMARY(pipe
));
2755 mutex_unlock(&dev
->struct_mutex
);
2757 DRM_ERROR("pin & fence failed\n");
2762 * Update pipe size and adjust fitter if needed: the reason for this is
2763 * that in compute_mode_changes we check the native mode (not the pfit
2764 * mode) to see if we can flip rather than do a full mode set. In the
2765 * fastboot case, we'll flip, but if we don't update the pipesrc and
2766 * pfit state, we'll end up with a big fb scanned out into the wrong
2769 * To fix this properly, we need to hoist the checks up into
2770 * compute_mode_changes (or above), check the actual pfit state and
2771 * whether the platform allows pfit disable with pipe active, and only
2772 * then update the pipesrc and pfit state, even on the flip path.
2774 if (i915
.fastboot
) {
2775 const struct drm_display_mode
*adjusted_mode
=
2776 &intel_crtc
->config
.adjusted_mode
;
2778 I915_WRITE(PIPESRC(intel_crtc
->pipe
),
2779 ((adjusted_mode
->crtc_hdisplay
- 1) << 16) |
2780 (adjusted_mode
->crtc_vdisplay
- 1));
2781 if (!intel_crtc
->config
.pch_pfit
.enabled
&&
2782 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) ||
2783 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
2784 I915_WRITE(PF_CTL(intel_crtc
->pipe
), 0);
2785 I915_WRITE(PF_WIN_POS(intel_crtc
->pipe
), 0);
2786 I915_WRITE(PF_WIN_SZ(intel_crtc
->pipe
), 0);
2788 intel_crtc
->config
.pipe_src_w
= adjusted_mode
->crtc_hdisplay
;
2789 intel_crtc
->config
.pipe_src_h
= adjusted_mode
->crtc_vdisplay
;
2792 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
2794 if (intel_crtc
->active
)
2795 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
2797 crtc
->primary
->fb
= fb
;
2802 if (intel_crtc
->active
&& old_fb
!= fb
)
2803 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2804 mutex_lock(&dev
->struct_mutex
);
2805 intel_unpin_fb_obj(old_obj
);
2806 mutex_unlock(&dev
->struct_mutex
);
2809 mutex_lock(&dev
->struct_mutex
);
2810 intel_update_fbc(dev
);
2811 mutex_unlock(&dev
->struct_mutex
);
2816 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2818 struct drm_device
*dev
= crtc
->dev
;
2819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2820 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2821 int pipe
= intel_crtc
->pipe
;
2824 /* enable normal train */
2825 reg
= FDI_TX_CTL(pipe
);
2826 temp
= I915_READ(reg
);
2827 if (IS_IVYBRIDGE(dev
)) {
2828 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2829 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2831 temp
&= ~FDI_LINK_TRAIN_NONE
;
2832 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2834 I915_WRITE(reg
, temp
);
2836 reg
= FDI_RX_CTL(pipe
);
2837 temp
= I915_READ(reg
);
2838 if (HAS_PCH_CPT(dev
)) {
2839 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2840 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2842 temp
&= ~FDI_LINK_TRAIN_NONE
;
2843 temp
|= FDI_LINK_TRAIN_NONE
;
2845 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2847 /* wait one idle pattern time */
2851 /* IVB wants error correction enabled */
2852 if (IS_IVYBRIDGE(dev
))
2853 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2854 FDI_FE_ERRC_ENABLE
);
2857 static bool pipe_has_enabled_pch(struct intel_crtc
*crtc
)
2859 return crtc
->base
.enabled
&& crtc
->active
&&
2860 crtc
->config
.has_pch_encoder
;
2863 static void ivb_modeset_global_resources(struct drm_device
*dev
)
2865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2866 struct intel_crtc
*pipe_B_crtc
=
2867 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
2868 struct intel_crtc
*pipe_C_crtc
=
2869 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]);
2873 * When everything is off disable fdi C so that we could enable fdi B
2874 * with all lanes. Note that we don't care about enabled pipes without
2875 * an enabled pch encoder.
2877 if (!pipe_has_enabled_pch(pipe_B_crtc
) &&
2878 !pipe_has_enabled_pch(pipe_C_crtc
)) {
2879 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
2880 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
2882 temp
= I915_READ(SOUTH_CHICKEN1
);
2883 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
2884 DRM_DEBUG_KMS("disabling fdi C rx\n");
2885 I915_WRITE(SOUTH_CHICKEN1
, temp
);
2889 /* The FDI link training functions for ILK/Ibexpeak. */
2890 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2892 struct drm_device
*dev
= crtc
->dev
;
2893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2894 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2895 int pipe
= intel_crtc
->pipe
;
2896 u32 reg
, temp
, tries
;
2898 /* FDI needs bits from pipe first */
2899 assert_pipe_enabled(dev_priv
, pipe
);
2901 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2903 reg
= FDI_RX_IMR(pipe
);
2904 temp
= I915_READ(reg
);
2905 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2906 temp
&= ~FDI_RX_BIT_LOCK
;
2907 I915_WRITE(reg
, temp
);
2911 /* enable CPU FDI TX and PCH FDI RX */
2912 reg
= FDI_TX_CTL(pipe
);
2913 temp
= I915_READ(reg
);
2914 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
2915 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
2916 temp
&= ~FDI_LINK_TRAIN_NONE
;
2917 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2918 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2920 reg
= FDI_RX_CTL(pipe
);
2921 temp
= I915_READ(reg
);
2922 temp
&= ~FDI_LINK_TRAIN_NONE
;
2923 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2924 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2929 /* Ironlake workaround, enable clock pointer after FDI enable*/
2930 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2931 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2932 FDI_RX_PHASE_SYNC_POINTER_EN
);
2934 reg
= FDI_RX_IIR(pipe
);
2935 for (tries
= 0; tries
< 5; tries
++) {
2936 temp
= I915_READ(reg
);
2937 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2939 if ((temp
& FDI_RX_BIT_LOCK
)) {
2940 DRM_DEBUG_KMS("FDI train 1 done.\n");
2941 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2946 DRM_ERROR("FDI train 1 fail!\n");
2949 reg
= FDI_TX_CTL(pipe
);
2950 temp
= I915_READ(reg
);
2951 temp
&= ~FDI_LINK_TRAIN_NONE
;
2952 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2953 I915_WRITE(reg
, temp
);
2955 reg
= FDI_RX_CTL(pipe
);
2956 temp
= I915_READ(reg
);
2957 temp
&= ~FDI_LINK_TRAIN_NONE
;
2958 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2959 I915_WRITE(reg
, temp
);
2964 reg
= FDI_RX_IIR(pipe
);
2965 for (tries
= 0; tries
< 5; tries
++) {
2966 temp
= I915_READ(reg
);
2967 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2969 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2970 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2971 DRM_DEBUG_KMS("FDI train 2 done.\n");
2976 DRM_ERROR("FDI train 2 fail!\n");
2978 DRM_DEBUG_KMS("FDI train done\n");
2982 static const int snb_b_fdi_train_param
[] = {
2983 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2984 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2985 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2986 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2989 /* The FDI link training functions for SNB/Cougarpoint. */
2990 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2992 struct drm_device
*dev
= crtc
->dev
;
2993 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2994 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2995 int pipe
= intel_crtc
->pipe
;
2996 u32 reg
, temp
, i
, retry
;
2998 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3000 reg
= FDI_RX_IMR(pipe
);
3001 temp
= I915_READ(reg
);
3002 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3003 temp
&= ~FDI_RX_BIT_LOCK
;
3004 I915_WRITE(reg
, temp
);
3009 /* enable CPU FDI TX and PCH FDI RX */
3010 reg
= FDI_TX_CTL(pipe
);
3011 temp
= I915_READ(reg
);
3012 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3013 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3014 temp
&= ~FDI_LINK_TRAIN_NONE
;
3015 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3016 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3018 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3019 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3021 I915_WRITE(FDI_RX_MISC(pipe
),
3022 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3024 reg
= FDI_RX_CTL(pipe
);
3025 temp
= I915_READ(reg
);
3026 if (HAS_PCH_CPT(dev
)) {
3027 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3028 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3030 temp
&= ~FDI_LINK_TRAIN_NONE
;
3031 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3033 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3038 for (i
= 0; i
< 4; i
++) {
3039 reg
= FDI_TX_CTL(pipe
);
3040 temp
= I915_READ(reg
);
3041 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3042 temp
|= snb_b_fdi_train_param
[i
];
3043 I915_WRITE(reg
, temp
);
3048 for (retry
= 0; retry
< 5; retry
++) {
3049 reg
= FDI_RX_IIR(pipe
);
3050 temp
= I915_READ(reg
);
3051 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3052 if (temp
& FDI_RX_BIT_LOCK
) {
3053 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3054 DRM_DEBUG_KMS("FDI train 1 done.\n");
3063 DRM_ERROR("FDI train 1 fail!\n");
3066 reg
= FDI_TX_CTL(pipe
);
3067 temp
= I915_READ(reg
);
3068 temp
&= ~FDI_LINK_TRAIN_NONE
;
3069 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3071 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3073 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3075 I915_WRITE(reg
, temp
);
3077 reg
= FDI_RX_CTL(pipe
);
3078 temp
= I915_READ(reg
);
3079 if (HAS_PCH_CPT(dev
)) {
3080 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3081 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3083 temp
&= ~FDI_LINK_TRAIN_NONE
;
3084 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3086 I915_WRITE(reg
, temp
);
3091 for (i
= 0; i
< 4; i
++) {
3092 reg
= FDI_TX_CTL(pipe
);
3093 temp
= I915_READ(reg
);
3094 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3095 temp
|= snb_b_fdi_train_param
[i
];
3096 I915_WRITE(reg
, temp
);
3101 for (retry
= 0; retry
< 5; retry
++) {
3102 reg
= FDI_RX_IIR(pipe
);
3103 temp
= I915_READ(reg
);
3104 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3105 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3106 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3107 DRM_DEBUG_KMS("FDI train 2 done.\n");
3116 DRM_ERROR("FDI train 2 fail!\n");
3118 DRM_DEBUG_KMS("FDI train done.\n");
3121 /* Manual link training for Ivy Bridge A0 parts */
3122 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3124 struct drm_device
*dev
= crtc
->dev
;
3125 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3126 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3127 int pipe
= intel_crtc
->pipe
;
3128 u32 reg
, temp
, i
, j
;
3130 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3132 reg
= FDI_RX_IMR(pipe
);
3133 temp
= I915_READ(reg
);
3134 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3135 temp
&= ~FDI_RX_BIT_LOCK
;
3136 I915_WRITE(reg
, temp
);
3141 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3142 I915_READ(FDI_RX_IIR(pipe
)));
3144 /* Try each vswing and preemphasis setting twice before moving on */
3145 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3146 /* disable first in case we need to retry */
3147 reg
= FDI_TX_CTL(pipe
);
3148 temp
= I915_READ(reg
);
3149 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3150 temp
&= ~FDI_TX_ENABLE
;
3151 I915_WRITE(reg
, temp
);
3153 reg
= FDI_RX_CTL(pipe
);
3154 temp
= I915_READ(reg
);
3155 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3156 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3157 temp
&= ~FDI_RX_ENABLE
;
3158 I915_WRITE(reg
, temp
);
3160 /* enable CPU FDI TX and PCH FDI RX */
3161 reg
= FDI_TX_CTL(pipe
);
3162 temp
= I915_READ(reg
);
3163 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3164 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3165 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3166 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3167 temp
|= snb_b_fdi_train_param
[j
/2];
3168 temp
|= FDI_COMPOSITE_SYNC
;
3169 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3171 I915_WRITE(FDI_RX_MISC(pipe
),
3172 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3174 reg
= FDI_RX_CTL(pipe
);
3175 temp
= I915_READ(reg
);
3176 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3177 temp
|= FDI_COMPOSITE_SYNC
;
3178 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3181 udelay(1); /* should be 0.5us */
3183 for (i
= 0; i
< 4; i
++) {
3184 reg
= FDI_RX_IIR(pipe
);
3185 temp
= I915_READ(reg
);
3186 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3188 if (temp
& FDI_RX_BIT_LOCK
||
3189 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3190 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3191 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3195 udelay(1); /* should be 0.5us */
3198 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3203 reg
= FDI_TX_CTL(pipe
);
3204 temp
= I915_READ(reg
);
3205 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3206 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3207 I915_WRITE(reg
, temp
);
3209 reg
= FDI_RX_CTL(pipe
);
3210 temp
= I915_READ(reg
);
3211 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3212 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3213 I915_WRITE(reg
, temp
);
3216 udelay(2); /* should be 1.5us */
3218 for (i
= 0; i
< 4; i
++) {
3219 reg
= FDI_RX_IIR(pipe
);
3220 temp
= I915_READ(reg
);
3221 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3223 if (temp
& FDI_RX_SYMBOL_LOCK
||
3224 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3225 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3226 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3230 udelay(2); /* should be 1.5us */
3233 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3237 DRM_DEBUG_KMS("FDI train done.\n");
3240 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3242 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3243 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3244 int pipe
= intel_crtc
->pipe
;
3248 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3249 reg
= FDI_RX_CTL(pipe
);
3250 temp
= I915_READ(reg
);
3251 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3252 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
.fdi_lanes
);
3253 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3254 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3259 /* Switch from Rawclk to PCDclk */
3260 temp
= I915_READ(reg
);
3261 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3266 /* Enable CPU FDI TX PLL, always on for Ironlake */
3267 reg
= FDI_TX_CTL(pipe
);
3268 temp
= I915_READ(reg
);
3269 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3270 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3277 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3279 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3281 int pipe
= intel_crtc
->pipe
;
3284 /* Switch from PCDclk to Rawclk */
3285 reg
= FDI_RX_CTL(pipe
);
3286 temp
= I915_READ(reg
);
3287 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3289 /* Disable CPU FDI TX PLL */
3290 reg
= FDI_TX_CTL(pipe
);
3291 temp
= I915_READ(reg
);
3292 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3297 reg
= FDI_RX_CTL(pipe
);
3298 temp
= I915_READ(reg
);
3299 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3301 /* Wait for the clocks to turn off. */
3306 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3308 struct drm_device
*dev
= crtc
->dev
;
3309 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3310 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3311 int pipe
= intel_crtc
->pipe
;
3314 /* disable CPU FDI tx and PCH FDI rx */
3315 reg
= FDI_TX_CTL(pipe
);
3316 temp
= I915_READ(reg
);
3317 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3320 reg
= FDI_RX_CTL(pipe
);
3321 temp
= I915_READ(reg
);
3322 temp
&= ~(0x7 << 16);
3323 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3324 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3329 /* Ironlake workaround, disable clock pointer after downing FDI */
3330 if (HAS_PCH_IBX(dev
))
3331 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3333 /* still set train pattern 1 */
3334 reg
= FDI_TX_CTL(pipe
);
3335 temp
= I915_READ(reg
);
3336 temp
&= ~FDI_LINK_TRAIN_NONE
;
3337 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3338 I915_WRITE(reg
, temp
);
3340 reg
= FDI_RX_CTL(pipe
);
3341 temp
= I915_READ(reg
);
3342 if (HAS_PCH_CPT(dev
)) {
3343 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3344 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3346 temp
&= ~FDI_LINK_TRAIN_NONE
;
3347 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3349 /* BPC in FDI rx is consistent with that in PIPECONF */
3350 temp
&= ~(0x07 << 16);
3351 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3352 I915_WRITE(reg
, temp
);
3358 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3360 struct intel_crtc
*crtc
;
3362 /* Note that we don't need to be called with mode_config.lock here
3363 * as our list of CRTC objects is static for the lifetime of the
3364 * device and so cannot disappear as we iterate. Similarly, we can
3365 * happily treat the predicates as racy, atomic checks as userspace
3366 * cannot claim and pin a new fb without at least acquring the
3367 * struct_mutex and so serialising with us.
3369 for_each_intel_crtc(dev
, crtc
) {
3370 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3373 if (crtc
->unpin_work
)
3374 intel_wait_for_vblank(dev
, crtc
->pipe
);
3382 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3384 struct drm_device
*dev
= crtc
->dev
;
3385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3387 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3388 WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3389 !intel_crtc_has_pending_flip(crtc
),
3392 if (crtc
->primary
->fb
) {
3393 mutex_lock(&dev
->struct_mutex
);
3394 intel_finish_fb(crtc
->primary
->fb
);
3395 mutex_unlock(&dev
->struct_mutex
);
3399 /* Program iCLKIP clock to the desired frequency */
3400 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3402 struct drm_device
*dev
= crtc
->dev
;
3403 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3404 int clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
3405 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3408 mutex_lock(&dev_priv
->dpio_lock
);
3410 /* It is necessary to ungate the pixclk gate prior to programming
3411 * the divisors, and gate it back when it is done.
3413 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3415 /* Disable SSCCTL */
3416 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3417 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3421 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3422 if (clock
== 20000) {
3427 /* The iCLK virtual clock root frequency is in MHz,
3428 * but the adjusted_mode->crtc_clock in in KHz. To get the
3429 * divisors, it is necessary to divide one by another, so we
3430 * convert the virtual clock precision to KHz here for higher
3433 u32 iclk_virtual_root_freq
= 172800 * 1000;
3434 u32 iclk_pi_range
= 64;
3435 u32 desired_divisor
, msb_divisor_value
, pi_value
;
3437 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
3438 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
3439 pi_value
= desired_divisor
% iclk_pi_range
;
3442 divsel
= msb_divisor_value
- 2;
3443 phaseinc
= pi_value
;
3446 /* This should not happen with any sane values */
3447 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
3448 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
3449 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
3450 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
3452 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3459 /* Program SSCDIVINTPHASE6 */
3460 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
3461 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
3462 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
3463 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
3464 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
3465 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
3466 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
3467 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
3469 /* Program SSCAUXDIV */
3470 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
3471 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3472 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
3473 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
3475 /* Enable modulator and associated divider */
3476 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
3477 temp
&= ~SBI_SSCCTL_DISABLE
;
3478 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
3480 /* Wait for initialization time */
3483 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
3485 mutex_unlock(&dev_priv
->dpio_lock
);
3488 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
3489 enum pipe pch_transcoder
)
3491 struct drm_device
*dev
= crtc
->base
.dev
;
3492 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3493 enum transcoder cpu_transcoder
= crtc
->config
.cpu_transcoder
;
3495 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
3496 I915_READ(HTOTAL(cpu_transcoder
)));
3497 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
3498 I915_READ(HBLANK(cpu_transcoder
)));
3499 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
3500 I915_READ(HSYNC(cpu_transcoder
)));
3502 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
3503 I915_READ(VTOTAL(cpu_transcoder
)));
3504 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
3505 I915_READ(VBLANK(cpu_transcoder
)));
3506 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
3507 I915_READ(VSYNC(cpu_transcoder
)));
3508 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
3509 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
3512 static void cpt_enable_fdi_bc_bifurcation(struct drm_device
*dev
)
3514 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3517 temp
= I915_READ(SOUTH_CHICKEN1
);
3518 if (temp
& FDI_BC_BIFURCATION_SELECT
)
3521 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
3522 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
3524 temp
|= FDI_BC_BIFURCATION_SELECT
;
3525 DRM_DEBUG_KMS("enabling fdi C rx\n");
3526 I915_WRITE(SOUTH_CHICKEN1
, temp
);
3527 POSTING_READ(SOUTH_CHICKEN1
);
3530 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
3532 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3533 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3535 switch (intel_crtc
->pipe
) {
3539 if (intel_crtc
->config
.fdi_lanes
> 2)
3540 WARN_ON(I915_READ(SOUTH_CHICKEN1
) & FDI_BC_BIFURCATION_SELECT
);
3542 cpt_enable_fdi_bc_bifurcation(dev
);
3546 cpt_enable_fdi_bc_bifurcation(dev
);
3555 * Enable PCH resources required for PCH ports:
3557 * - FDI training & RX/TX
3558 * - update transcoder timings
3559 * - DP transcoding bits
3562 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
3564 struct drm_device
*dev
= crtc
->dev
;
3565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3566 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3567 int pipe
= intel_crtc
->pipe
;
3570 assert_pch_transcoder_disabled(dev_priv
, pipe
);
3572 if (IS_IVYBRIDGE(dev
))
3573 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
3575 /* Write the TU size bits before fdi link training, so that error
3576 * detection works. */
3577 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
3578 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
3580 /* For PCH output, training FDI link */
3581 dev_priv
->display
.fdi_link_train(crtc
);
3583 /* We need to program the right clock selection before writing the pixel
3584 * mutliplier into the DPLL. */
3585 if (HAS_PCH_CPT(dev
)) {
3588 temp
= I915_READ(PCH_DPLL_SEL
);
3589 temp
|= TRANS_DPLL_ENABLE(pipe
);
3590 sel
= TRANS_DPLLB_SEL(pipe
);
3591 if (intel_crtc
->config
.shared_dpll
== DPLL_ID_PCH_PLL_B
)
3595 I915_WRITE(PCH_DPLL_SEL
, temp
);
3598 /* XXX: pch pll's can be enabled any time before we enable the PCH
3599 * transcoder, and we actually should do this to not upset any PCH
3600 * transcoder that already use the clock when we share it.
3602 * Note that enable_shared_dpll tries to do the right thing, but
3603 * get_shared_dpll unconditionally resets the pll - we need that to have
3604 * the right LVDS enable sequence. */
3605 intel_enable_shared_dpll(intel_crtc
);
3607 /* set transcoder timing, panel must allow it */
3608 assert_panel_unlocked(dev_priv
, pipe
);
3609 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
3611 intel_fdi_normal_train(crtc
);
3613 /* For PCH DP, enable TRANS_DP_CTL */
3614 if (HAS_PCH_CPT(dev
) &&
3615 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3616 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3617 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
3618 reg
= TRANS_DP_CTL(pipe
);
3619 temp
= I915_READ(reg
);
3620 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3621 TRANS_DP_SYNC_MASK
|
3623 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3624 TRANS_DP_ENH_FRAMING
);
3625 temp
|= bpc
<< 9; /* same format but at 11:9 */
3627 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3628 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3629 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3630 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3632 switch (intel_trans_dp_port_sel(crtc
)) {
3634 temp
|= TRANS_DP_PORT_SEL_B
;
3637 temp
|= TRANS_DP_PORT_SEL_C
;
3640 temp
|= TRANS_DP_PORT_SEL_D
;
3646 I915_WRITE(reg
, temp
);
3649 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
3652 static void lpt_pch_enable(struct drm_crtc
*crtc
)
3654 struct drm_device
*dev
= crtc
->dev
;
3655 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3656 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3657 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
3659 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
3661 lpt_program_iclkip(crtc
);
3663 /* Set transcoder timing. */
3664 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
3666 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
3669 void intel_put_shared_dpll(struct intel_crtc
*crtc
)
3671 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3676 if (pll
->refcount
== 0) {
3677 WARN(1, "bad %s refcount\n", pll
->name
);
3681 if (--pll
->refcount
== 0) {
3683 WARN_ON(pll
->active
);
3686 crtc
->config
.shared_dpll
= DPLL_ID_PRIVATE
;
3689 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
)
3691 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
3692 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
3693 enum intel_dpll_id i
;
3696 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3697 crtc
->base
.base
.id
, pll
->name
);
3698 intel_put_shared_dpll(crtc
);
3701 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3702 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3703 i
= (enum intel_dpll_id
) crtc
->pipe
;
3704 pll
= &dev_priv
->shared_dplls
[i
];
3706 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3707 crtc
->base
.base
.id
, pll
->name
);
3709 WARN_ON(pll
->refcount
);
3714 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3715 pll
= &dev_priv
->shared_dplls
[i
];
3717 /* Only want to check enabled timings first */
3718 if (pll
->refcount
== 0)
3721 if (memcmp(&crtc
->config
.dpll_hw_state
, &pll
->hw_state
,
3722 sizeof(pll
->hw_state
)) == 0) {
3723 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3725 pll
->name
, pll
->refcount
, pll
->active
);
3731 /* Ok no matching timings, maybe there's a free one? */
3732 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
3733 pll
= &dev_priv
->shared_dplls
[i
];
3734 if (pll
->refcount
== 0) {
3735 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3736 crtc
->base
.base
.id
, pll
->name
);
3744 if (pll
->refcount
== 0)
3745 pll
->hw_state
= crtc
->config
.dpll_hw_state
;
3747 crtc
->config
.shared_dpll
= i
;
3748 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
3749 pipe_name(crtc
->pipe
));
3756 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3758 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3759 int dslreg
= PIPEDSL(pipe
);
3762 temp
= I915_READ(dslreg
);
3764 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3765 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3766 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
3770 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
3772 struct drm_device
*dev
= crtc
->base
.dev
;
3773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3774 int pipe
= crtc
->pipe
;
3776 if (crtc
->config
.pch_pfit
.enabled
) {
3777 /* Force use of hard-coded filter coefficients
3778 * as some pre-programmed values are broken,
3781 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
3782 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
3783 PF_PIPE_SEL_IVB(pipe
));
3785 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3786 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
.pch_pfit
.pos
);
3787 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
.pch_pfit
.size
);
3791 static void intel_enable_planes(struct drm_crtc
*crtc
)
3793 struct drm_device
*dev
= crtc
->dev
;
3794 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3795 struct drm_plane
*plane
;
3796 struct intel_plane
*intel_plane
;
3798 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3799 intel_plane
= to_intel_plane(plane
);
3800 if (intel_plane
->pipe
== pipe
)
3801 intel_plane_restore(&intel_plane
->base
);
3805 static void intel_disable_planes(struct drm_crtc
*crtc
)
3807 struct drm_device
*dev
= crtc
->dev
;
3808 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
3809 struct drm_plane
*plane
;
3810 struct intel_plane
*intel_plane
;
3812 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
3813 intel_plane
= to_intel_plane(plane
);
3814 if (intel_plane
->pipe
== pipe
)
3815 intel_plane_disable(&intel_plane
->base
);
3819 void hsw_enable_ips(struct intel_crtc
*crtc
)
3821 struct drm_device
*dev
= crtc
->base
.dev
;
3822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3824 if (!crtc
->config
.ips_enabled
)
3827 /* We can only enable IPS after we enable a plane and wait for a vblank */
3828 intel_wait_for_vblank(dev
, crtc
->pipe
);
3830 assert_plane_enabled(dev_priv
, crtc
->plane
);
3831 if (IS_BROADWELL(dev
)) {
3832 mutex_lock(&dev_priv
->rps
.hw_lock
);
3833 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
3834 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3835 /* Quoting Art Runyan: "its not safe to expect any particular
3836 * value in IPS_CTL bit 31 after enabling IPS through the
3837 * mailbox." Moreover, the mailbox may return a bogus state,
3838 * so we need to just enable it and continue on.
3841 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
3842 /* The bit only becomes 1 in the next vblank, so this wait here
3843 * is essentially intel_wait_for_vblank. If we don't have this
3844 * and don't wait for vblanks until the end of crtc_enable, then
3845 * the HW state readout code will complain that the expected
3846 * IPS_CTL value is not the one we read. */
3847 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
3848 DRM_ERROR("Timed out waiting for IPS enable\n");
3852 void hsw_disable_ips(struct intel_crtc
*crtc
)
3854 struct drm_device
*dev
= crtc
->base
.dev
;
3855 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3857 if (!crtc
->config
.ips_enabled
)
3860 assert_plane_enabled(dev_priv
, crtc
->plane
);
3861 if (IS_BROADWELL(dev
)) {
3862 mutex_lock(&dev_priv
->rps
.hw_lock
);
3863 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
3864 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3865 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3866 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
3867 DRM_ERROR("Timed out waiting for IPS disable\n");
3869 I915_WRITE(IPS_CTL
, 0);
3870 POSTING_READ(IPS_CTL
);
3873 /* We need to wait for a vblank before we can disable the plane. */
3874 intel_wait_for_vblank(dev
, crtc
->pipe
);
3877 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3878 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
3880 struct drm_device
*dev
= crtc
->dev
;
3881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3882 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3883 enum pipe pipe
= intel_crtc
->pipe
;
3884 int palreg
= PALETTE(pipe
);
3886 bool reenable_ips
= false;
3888 /* The clocks have to be on to load the palette. */
3889 if (!crtc
->enabled
|| !intel_crtc
->active
)
3892 if (!HAS_PCH_SPLIT(dev_priv
->dev
)) {
3893 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
3894 assert_dsi_pll_enabled(dev_priv
);
3896 assert_pll_enabled(dev_priv
, pipe
);
3899 /* use legacy palette for Ironlake */
3900 if (!HAS_GMCH_DISPLAY(dev
))
3901 palreg
= LGC_PALETTE(pipe
);
3903 /* Workaround : Do not read or write the pipe palette/gamma data while
3904 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3906 if (IS_HASWELL(dev
) && intel_crtc
->config
.ips_enabled
&&
3907 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
3908 GAMMA_MODE_MODE_SPLIT
)) {
3909 hsw_disable_ips(intel_crtc
);
3910 reenable_ips
= true;
3913 for (i
= 0; i
< 256; i
++) {
3914 I915_WRITE(palreg
+ 4 * i
,
3915 (intel_crtc
->lut_r
[i
] << 16) |
3916 (intel_crtc
->lut_g
[i
] << 8) |
3917 intel_crtc
->lut_b
[i
]);
3921 hsw_enable_ips(intel_crtc
);
3924 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3926 if (!enable
&& intel_crtc
->overlay
) {
3927 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3928 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3930 mutex_lock(&dev
->struct_mutex
);
3931 dev_priv
->mm
.interruptible
= false;
3932 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3933 dev_priv
->mm
.interruptible
= true;
3934 mutex_unlock(&dev
->struct_mutex
);
3937 /* Let userspace switch the overlay on again. In most cases userspace
3938 * has to recompute where to put it anyway.
3942 static void intel_crtc_enable_planes(struct drm_crtc
*crtc
)
3944 struct drm_device
*dev
= crtc
->dev
;
3945 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3946 int pipe
= intel_crtc
->pipe
;
3948 drm_vblank_on(dev
, pipe
);
3950 intel_enable_primary_hw_plane(crtc
->primary
, crtc
);
3951 intel_enable_planes(crtc
);
3952 intel_crtc_update_cursor(crtc
, true);
3953 intel_crtc_dpms_overlay(intel_crtc
, true);
3955 hsw_enable_ips(intel_crtc
);
3957 mutex_lock(&dev
->struct_mutex
);
3958 intel_update_fbc(dev
);
3959 mutex_unlock(&dev
->struct_mutex
);
3962 * FIXME: Once we grow proper nuclear flip support out of this we need
3963 * to compute the mask of flip planes precisely. For the time being
3964 * consider this a flip from a NULL plane.
3966 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
3969 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
)
3971 struct drm_device
*dev
= crtc
->dev
;
3972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3973 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3974 int pipe
= intel_crtc
->pipe
;
3975 int plane
= intel_crtc
->plane
;
3977 intel_crtc_wait_for_pending_flips(crtc
);
3979 if (dev_priv
->fbc
.plane
== plane
)
3980 intel_disable_fbc(dev
);
3982 hsw_disable_ips(intel_crtc
);
3984 intel_crtc_dpms_overlay(intel_crtc
, false);
3985 intel_crtc_update_cursor(crtc
, false);
3986 intel_disable_planes(crtc
);
3987 intel_disable_primary_hw_plane(crtc
->primary
, crtc
);
3990 * FIXME: Once we grow proper nuclear flip support out of this we need
3991 * to compute the mask of flip planes precisely. For the time being
3992 * consider this a flip to a NULL plane.
3994 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
3996 drm_vblank_off(dev
, pipe
);
3999 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4001 struct drm_device
*dev
= crtc
->dev
;
4002 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4003 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4004 struct intel_encoder
*encoder
;
4005 int pipe
= intel_crtc
->pipe
;
4007 WARN_ON(!crtc
->enabled
);
4009 if (intel_crtc
->active
)
4012 if (intel_crtc
->config
.has_pch_encoder
)
4013 intel_prepare_shared_dpll(intel_crtc
);
4015 if (intel_crtc
->config
.has_dp_encoder
)
4016 intel_dp_set_m_n(intel_crtc
);
4018 intel_set_pipe_timings(intel_crtc
);
4020 if (intel_crtc
->config
.has_pch_encoder
) {
4021 intel_cpu_transcoder_set_m_n(intel_crtc
,
4022 &intel_crtc
->config
.fdi_m_n
, NULL
);
4025 ironlake_set_pipeconf(crtc
);
4027 intel_crtc
->active
= true;
4029 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4030 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4032 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4033 if (encoder
->pre_enable
)
4034 encoder
->pre_enable(encoder
);
4036 if (intel_crtc
->config
.has_pch_encoder
) {
4037 /* Note: FDI PLL enabling _must_ be done before we enable the
4038 * cpu pipes, hence this is separate from all the other fdi/pch
4040 ironlake_fdi_pll_enable(intel_crtc
);
4042 assert_fdi_tx_disabled(dev_priv
, pipe
);
4043 assert_fdi_rx_disabled(dev_priv
, pipe
);
4046 ironlake_pfit_enable(intel_crtc
);
4049 * On ILK+ LUT must be loaded before the pipe is running but with
4052 intel_crtc_load_lut(crtc
);
4054 intel_update_watermarks(crtc
);
4055 intel_enable_pipe(intel_crtc
);
4057 if (intel_crtc
->config
.has_pch_encoder
)
4058 ironlake_pch_enable(crtc
);
4060 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4061 encoder
->enable(encoder
);
4063 if (HAS_PCH_CPT(dev
))
4064 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4066 intel_crtc_enable_planes(crtc
);
4069 /* IPS only exists on ULT machines and is tied to pipe A. */
4070 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4072 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4076 * This implements the workaround described in the "notes" section of the mode
4077 * set sequence documentation. When going from no pipes or single pipe to
4078 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4079 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4081 static void haswell_mode_set_planes_workaround(struct intel_crtc
*crtc
)
4083 struct drm_device
*dev
= crtc
->base
.dev
;
4084 struct intel_crtc
*crtc_it
, *other_active_crtc
= NULL
;
4086 /* We want to get the other_active_crtc only if there's only 1 other
4088 for_each_intel_crtc(dev
, crtc_it
) {
4089 if (!crtc_it
->active
|| crtc_it
== crtc
)
4092 if (other_active_crtc
)
4095 other_active_crtc
= crtc_it
;
4097 if (!other_active_crtc
)
4100 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4101 intel_wait_for_vblank(dev
, other_active_crtc
->pipe
);
4104 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4106 struct drm_device
*dev
= crtc
->dev
;
4107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4108 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4109 struct intel_encoder
*encoder
;
4110 int pipe
= intel_crtc
->pipe
;
4112 WARN_ON(!crtc
->enabled
);
4114 if (intel_crtc
->active
)
4117 if (intel_crtc_to_shared_dpll(intel_crtc
))
4118 intel_enable_shared_dpll(intel_crtc
);
4120 if (intel_crtc
->config
.has_dp_encoder
)
4121 intel_dp_set_m_n(intel_crtc
);
4123 intel_set_pipe_timings(intel_crtc
);
4125 if (intel_crtc
->config
.has_pch_encoder
) {
4126 intel_cpu_transcoder_set_m_n(intel_crtc
,
4127 &intel_crtc
->config
.fdi_m_n
, NULL
);
4130 haswell_set_pipeconf(crtc
);
4132 intel_set_pipe_csc(crtc
);
4134 intel_crtc
->active
= true;
4136 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4137 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4138 if (encoder
->pre_enable
)
4139 encoder
->pre_enable(encoder
);
4141 if (intel_crtc
->config
.has_pch_encoder
) {
4142 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4143 dev_priv
->display
.fdi_link_train(crtc
);
4146 intel_ddi_enable_pipe_clock(intel_crtc
);
4148 ironlake_pfit_enable(intel_crtc
);
4151 * On ILK+ LUT must be loaded before the pipe is running but with
4154 intel_crtc_load_lut(crtc
);
4156 intel_ddi_set_pipe_settings(crtc
);
4157 intel_ddi_enable_transcoder_func(crtc
);
4159 intel_update_watermarks(crtc
);
4160 intel_enable_pipe(intel_crtc
);
4162 if (intel_crtc
->config
.has_pch_encoder
)
4163 lpt_pch_enable(crtc
);
4165 if (intel_crtc
->config
.dp_encoder_is_mst
)
4166 intel_ddi_set_vc_payload_alloc(crtc
, true);
4168 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4169 encoder
->enable(encoder
);
4170 intel_opregion_notify_encoder(encoder
, true);
4173 /* If we change the relative order between pipe/planes enabling, we need
4174 * to change the workaround. */
4175 haswell_mode_set_planes_workaround(intel_crtc
);
4176 intel_crtc_enable_planes(crtc
);
4179 static void ironlake_pfit_disable(struct intel_crtc
*crtc
)
4181 struct drm_device
*dev
= crtc
->base
.dev
;
4182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4183 int pipe
= crtc
->pipe
;
4185 /* To avoid upsetting the power well on haswell only disable the pfit if
4186 * it's in use. The hw state code will make sure we get this right. */
4187 if (crtc
->config
.pch_pfit
.enabled
) {
4188 I915_WRITE(PF_CTL(pipe
), 0);
4189 I915_WRITE(PF_WIN_POS(pipe
), 0);
4190 I915_WRITE(PF_WIN_SZ(pipe
), 0);
4194 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
4196 struct drm_device
*dev
= crtc
->dev
;
4197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4199 struct intel_encoder
*encoder
;
4200 int pipe
= intel_crtc
->pipe
;
4203 if (!intel_crtc
->active
)
4206 intel_crtc_disable_planes(crtc
);
4208 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4209 encoder
->disable(encoder
);
4211 if (intel_crtc
->config
.has_pch_encoder
)
4212 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, false);
4214 intel_disable_pipe(dev_priv
, pipe
);
4216 if (intel_crtc
->config
.dp_encoder_is_mst
)
4217 intel_ddi_set_vc_payload_alloc(crtc
, false);
4219 ironlake_pfit_disable(intel_crtc
);
4221 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4222 if (encoder
->post_disable
)
4223 encoder
->post_disable(encoder
);
4225 if (intel_crtc
->config
.has_pch_encoder
) {
4226 ironlake_fdi_disable(crtc
);
4228 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
4229 intel_set_pch_fifo_underrun_reporting(dev
, pipe
, true);
4231 if (HAS_PCH_CPT(dev
)) {
4232 /* disable TRANS_DP_CTL */
4233 reg
= TRANS_DP_CTL(pipe
);
4234 temp
= I915_READ(reg
);
4235 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
4236 TRANS_DP_PORT_SEL_MASK
);
4237 temp
|= TRANS_DP_PORT_SEL_NONE
;
4238 I915_WRITE(reg
, temp
);
4240 /* disable DPLL_SEL */
4241 temp
= I915_READ(PCH_DPLL_SEL
);
4242 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
4243 I915_WRITE(PCH_DPLL_SEL
, temp
);
4246 /* disable PCH DPLL */
4247 intel_disable_shared_dpll(intel_crtc
);
4249 ironlake_fdi_pll_disable(intel_crtc
);
4252 intel_crtc
->active
= false;
4253 intel_update_watermarks(crtc
);
4255 mutex_lock(&dev
->struct_mutex
);
4256 intel_update_fbc(dev
);
4257 mutex_unlock(&dev
->struct_mutex
);
4260 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
4262 struct drm_device
*dev
= crtc
->dev
;
4263 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4264 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4265 struct intel_encoder
*encoder
;
4266 int pipe
= intel_crtc
->pipe
;
4267 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
4269 if (!intel_crtc
->active
)
4272 intel_crtc_disable_planes(crtc
);
4274 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4275 intel_opregion_notify_encoder(encoder
, false);
4276 encoder
->disable(encoder
);
4279 if (intel_crtc
->config
.has_pch_encoder
)
4280 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, false);
4281 intel_disable_pipe(dev_priv
, pipe
);
4283 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
4285 ironlake_pfit_disable(intel_crtc
);
4287 intel_ddi_disable_pipe_clock(intel_crtc
);
4289 if (intel_crtc
->config
.has_pch_encoder
) {
4290 lpt_disable_pch_transcoder(dev_priv
);
4291 intel_set_pch_fifo_underrun_reporting(dev
, TRANSCODER_A
, true);
4292 intel_ddi_fdi_disable(crtc
);
4295 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4296 if (encoder
->post_disable
)
4297 encoder
->post_disable(encoder
);
4299 intel_crtc
->active
= false;
4300 intel_update_watermarks(crtc
);
4302 mutex_lock(&dev
->struct_mutex
);
4303 intel_update_fbc(dev
);
4304 mutex_unlock(&dev
->struct_mutex
);
4306 if (intel_crtc_to_shared_dpll(intel_crtc
))
4307 intel_disable_shared_dpll(intel_crtc
);
4310 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
4312 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4313 intel_put_shared_dpll(intel_crtc
);
4317 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
4319 struct drm_device
*dev
= crtc
->base
.dev
;
4320 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4321 struct intel_crtc_config
*pipe_config
= &crtc
->config
;
4323 if (!crtc
->config
.gmch_pfit
.control
)
4327 * The panel fitter should only be adjusted whilst the pipe is disabled,
4328 * according to register description and PRM.
4330 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
4331 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4333 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
4334 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
4336 /* Border color in case we don't scale up to the full screen. Black by
4337 * default, change to something else for debugging. */
4338 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
4341 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
4345 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
4347 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
4349 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
4351 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
4354 return POWER_DOMAIN_PORT_OTHER
;
4358 #define for_each_power_domain(domain, mask) \
4359 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4360 if ((1 << (domain)) & (mask))
4362 enum intel_display_power_domain
4363 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
4365 struct drm_device
*dev
= intel_encoder
->base
.dev
;
4366 struct intel_digital_port
*intel_dig_port
;
4368 switch (intel_encoder
->type
) {
4369 case INTEL_OUTPUT_UNKNOWN
:
4370 /* Only DDI platforms should ever use this output type */
4371 WARN_ON_ONCE(!HAS_DDI(dev
));
4372 case INTEL_OUTPUT_DISPLAYPORT
:
4373 case INTEL_OUTPUT_HDMI
:
4374 case INTEL_OUTPUT_EDP
:
4375 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
4376 return port_to_power_domain(intel_dig_port
->port
);
4377 case INTEL_OUTPUT_DP_MST
:
4378 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
4379 return port_to_power_domain(intel_dig_port
->port
);
4380 case INTEL_OUTPUT_ANALOG
:
4381 return POWER_DOMAIN_PORT_CRT
;
4382 case INTEL_OUTPUT_DSI
:
4383 return POWER_DOMAIN_PORT_DSI
;
4385 return POWER_DOMAIN_PORT_OTHER
;
4389 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
4391 struct drm_device
*dev
= crtc
->dev
;
4392 struct intel_encoder
*intel_encoder
;
4393 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4394 enum pipe pipe
= intel_crtc
->pipe
;
4396 enum transcoder transcoder
;
4398 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
4400 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
4401 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
4402 if (intel_crtc
->config
.pch_pfit
.enabled
||
4403 intel_crtc
->config
.pch_pfit
.force_thru
)
4404 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
4406 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4407 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
4412 void intel_display_set_init_power(struct drm_i915_private
*dev_priv
,
4415 if (dev_priv
->power_domains
.init_power_on
== enable
)
4419 intel_display_power_get(dev_priv
, POWER_DOMAIN_INIT
);
4421 intel_display_power_put(dev_priv
, POWER_DOMAIN_INIT
);
4423 dev_priv
->power_domains
.init_power_on
= enable
;
4426 static void modeset_update_crtc_power_domains(struct drm_device
*dev
)
4428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4429 unsigned long pipe_domains
[I915_MAX_PIPES
] = { 0, };
4430 struct intel_crtc
*crtc
;
4433 * First get all needed power domains, then put all unneeded, to avoid
4434 * any unnecessary toggling of the power wells.
4436 for_each_intel_crtc(dev
, crtc
) {
4437 enum intel_display_power_domain domain
;
4439 if (!crtc
->base
.enabled
)
4442 pipe_domains
[crtc
->pipe
] = get_crtc_power_domains(&crtc
->base
);
4444 for_each_power_domain(domain
, pipe_domains
[crtc
->pipe
])
4445 intel_display_power_get(dev_priv
, domain
);
4448 for_each_intel_crtc(dev
, crtc
) {
4449 enum intel_display_power_domain domain
;
4451 for_each_power_domain(domain
, crtc
->enabled_power_domains
)
4452 intel_display_power_put(dev_priv
, domain
);
4454 crtc
->enabled_power_domains
= pipe_domains
[crtc
->pipe
];
4457 intel_display_set_init_power(dev_priv
, false);
4460 /* returns HPLL frequency in kHz */
4461 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
4463 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
4465 /* Obtain SKU information */
4466 mutex_lock(&dev_priv
->dpio_lock
);
4467 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
4468 CCK_FUSE_HPLL_FREQ_MASK
;
4469 mutex_unlock(&dev_priv
->dpio_lock
);
4471 return vco_freq
[hpll_freq
] * 1000;
4474 static void vlv_update_cdclk(struct drm_device
*dev
)
4476 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4478 dev_priv
->vlv_cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
4479 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz",
4480 dev_priv
->vlv_cdclk_freq
);
4483 * Program the gmbus_freq based on the cdclk frequency.
4484 * BSpec erroneously claims we should aim for 4MHz, but
4485 * in fact 1MHz is the correct frequency.
4487 I915_WRITE(GMBUSFREQ_VLV
, dev_priv
->vlv_cdclk_freq
);
4490 /* Adjust CDclk dividers to allow high res or save power if possible */
4491 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4493 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4496 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4498 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
4500 else if (cdclk
== 266667)
4505 mutex_lock(&dev_priv
->rps
.hw_lock
);
4506 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4507 val
&= ~DSPFREQGUAR_MASK
;
4508 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
4509 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4510 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4511 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
4513 DRM_ERROR("timed out waiting for CDclk change\n");
4515 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4517 if (cdclk
== 400000) {
4520 vco
= valleyview_get_vco(dev_priv
);
4521 divider
= DIV_ROUND_CLOSEST(vco
<< 1, cdclk
) - 1;
4523 mutex_lock(&dev_priv
->dpio_lock
);
4524 /* adjust cdclk divider */
4525 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
4526 val
&= ~DISPLAY_FREQUENCY_VALUES
;
4528 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
4530 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
4531 DISPLAY_FREQUENCY_STATUS
) == (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
4533 DRM_ERROR("timed out waiting for CDclk change\n");
4534 mutex_unlock(&dev_priv
->dpio_lock
);
4537 mutex_lock(&dev_priv
->dpio_lock
);
4538 /* adjust self-refresh exit latency value */
4539 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
4543 * For high bandwidth configs, we set a higher latency in the bunit
4544 * so that the core display fetch happens in time to avoid underruns.
4546 if (cdclk
== 400000)
4547 val
|= 4500 / 250; /* 4.5 usec */
4549 val
|= 3000 / 250; /* 3.0 usec */
4550 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
4551 mutex_unlock(&dev_priv
->dpio_lock
);
4553 vlv_update_cdclk(dev
);
4556 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
4558 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4561 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
) != dev_priv
->vlv_cdclk_freq
);
4582 mutex_lock(&dev_priv
->rps
.hw_lock
);
4583 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
4584 val
&= ~DSPFREQGUAR_MASK_CHV
;
4585 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
4586 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
4587 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
4588 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
4590 DRM_ERROR("timed out waiting for CDclk change\n");
4592 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4594 vlv_update_cdclk(dev
);
4597 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
4600 int vco
= valleyview_get_vco(dev_priv
);
4601 int freq_320
= (vco
<< 1) % 320000 != 0 ? 333333 : 320000;
4603 /* FIXME: Punit isn't quite ready yet */
4604 if (IS_CHERRYVIEW(dev_priv
->dev
))
4608 * Really only a few cases to deal with, as only 4 CDclks are supported:
4611 * 320/333MHz (depends on HPLL freq)
4613 * So we check to see whether we're above 90% of the lower bin and
4616 * We seem to get an unstable or solid color picture at 200MHz.
4617 * Not sure what's wrong. For now use 200MHz only when all pipes
4620 if (max_pixclk
> freq_320
*9/10)
4622 else if (max_pixclk
> 266667*9/10)
4624 else if (max_pixclk
> 0)
4630 /* compute the max pixel clock for new configuration */
4631 static int intel_mode_max_pixclk(struct drm_i915_private
*dev_priv
)
4633 struct drm_device
*dev
= dev_priv
->dev
;
4634 struct intel_crtc
*intel_crtc
;
4637 for_each_intel_crtc(dev
, intel_crtc
) {
4638 if (intel_crtc
->new_enabled
)
4639 max_pixclk
= max(max_pixclk
,
4640 intel_crtc
->new_config
->adjusted_mode
.crtc_clock
);
4646 static void valleyview_modeset_global_pipes(struct drm_device
*dev
,
4647 unsigned *prepare_pipes
)
4649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4650 struct intel_crtc
*intel_crtc
;
4651 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4653 if (valleyview_calc_cdclk(dev_priv
, max_pixclk
) ==
4654 dev_priv
->vlv_cdclk_freq
)
4657 /* disable/enable all currently active pipes while we change cdclk */
4658 for_each_intel_crtc(dev
, intel_crtc
)
4659 if (intel_crtc
->base
.enabled
)
4660 *prepare_pipes
|= (1 << intel_crtc
->pipe
);
4663 static void valleyview_modeset_global_resources(struct drm_device
*dev
)
4665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4666 int max_pixclk
= intel_mode_max_pixclk(dev_priv
);
4667 int req_cdclk
= valleyview_calc_cdclk(dev_priv
, max_pixclk
);
4669 if (req_cdclk
!= dev_priv
->vlv_cdclk_freq
) {
4670 if (IS_CHERRYVIEW(dev
))
4671 cherryview_set_cdclk(dev
, req_cdclk
);
4673 valleyview_set_cdclk(dev
, req_cdclk
);
4676 modeset_update_crtc_power_domains(dev
);
4679 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
4681 struct drm_device
*dev
= crtc
->dev
;
4682 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4683 struct intel_encoder
*encoder
;
4684 int pipe
= intel_crtc
->pipe
;
4687 WARN_ON(!crtc
->enabled
);
4689 if (intel_crtc
->active
)
4692 is_dsi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
);
4695 if (IS_CHERRYVIEW(dev
))
4696 chv_prepare_pll(intel_crtc
);
4698 vlv_prepare_pll(intel_crtc
);
4701 if (intel_crtc
->config
.has_dp_encoder
)
4702 intel_dp_set_m_n(intel_crtc
);
4704 intel_set_pipe_timings(intel_crtc
);
4706 i9xx_set_pipeconf(intel_crtc
);
4708 intel_crtc
->active
= true;
4710 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4712 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4713 if (encoder
->pre_pll_enable
)
4714 encoder
->pre_pll_enable(encoder
);
4717 if (IS_CHERRYVIEW(dev
))
4718 chv_enable_pll(intel_crtc
);
4720 vlv_enable_pll(intel_crtc
);
4723 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4724 if (encoder
->pre_enable
)
4725 encoder
->pre_enable(encoder
);
4727 i9xx_pfit_enable(intel_crtc
);
4729 intel_crtc_load_lut(crtc
);
4731 intel_update_watermarks(crtc
);
4732 intel_enable_pipe(intel_crtc
);
4734 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4735 encoder
->enable(encoder
);
4737 intel_crtc_enable_planes(crtc
);
4739 /* Underruns don't raise interrupts, so check manually. */
4740 i9xx_check_fifo_underruns(dev
);
4743 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
4745 struct drm_device
*dev
= crtc
->base
.dev
;
4746 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4748 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp0
);
4749 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
.dpll_hw_state
.fp1
);
4752 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
4754 struct drm_device
*dev
= crtc
->dev
;
4755 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4756 struct intel_encoder
*encoder
;
4757 int pipe
= intel_crtc
->pipe
;
4759 WARN_ON(!crtc
->enabled
);
4761 if (intel_crtc
->active
)
4764 i9xx_set_pll_dividers(intel_crtc
);
4766 if (intel_crtc
->config
.has_dp_encoder
)
4767 intel_dp_set_m_n(intel_crtc
);
4769 intel_set_pipe_timings(intel_crtc
);
4771 i9xx_set_pipeconf(intel_crtc
);
4773 intel_crtc
->active
= true;
4776 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4778 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4779 if (encoder
->pre_enable
)
4780 encoder
->pre_enable(encoder
);
4782 i9xx_enable_pll(intel_crtc
);
4784 i9xx_pfit_enable(intel_crtc
);
4786 intel_crtc_load_lut(crtc
);
4788 intel_update_watermarks(crtc
);
4789 intel_enable_pipe(intel_crtc
);
4791 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4792 encoder
->enable(encoder
);
4794 intel_crtc_enable_planes(crtc
);
4797 * Gen2 reports pipe underruns whenever all planes are disabled.
4798 * So don't enable underrun reporting before at least some planes
4800 * FIXME: Need to fix the logic to work when we turn off all planes
4801 * but leave the pipe running.
4804 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, true);
4806 /* Underruns don't raise interrupts, so check manually. */
4807 i9xx_check_fifo_underruns(dev
);
4810 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
4812 struct drm_device
*dev
= crtc
->base
.dev
;
4813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4815 if (!crtc
->config
.gmch_pfit
.control
)
4818 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
4820 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4821 I915_READ(PFIT_CONTROL
));
4822 I915_WRITE(PFIT_CONTROL
, 0);
4825 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
4827 struct drm_device
*dev
= crtc
->dev
;
4828 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4829 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4830 struct intel_encoder
*encoder
;
4831 int pipe
= intel_crtc
->pipe
;
4833 if (!intel_crtc
->active
)
4837 * Gen2 reports pipe underruns whenever all planes are disabled.
4838 * So diasble underrun reporting before all the planes get disabled.
4839 * FIXME: Need to fix the logic to work when we turn off all planes
4840 * but leave the pipe running.
4843 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4846 * Vblank time updates from the shadow to live plane control register
4847 * are blocked if the memory self-refresh mode is active at that
4848 * moment. So to make sure the plane gets truly disabled, disable
4849 * first the self-refresh mode. The self-refresh enable bit in turn
4850 * will be checked/applied by the HW only at the next frame start
4851 * event which is after the vblank start event, so we need to have a
4852 * wait-for-vblank between disabling the plane and the pipe.
4854 intel_set_memory_cxsr(dev_priv
, false);
4855 intel_crtc_disable_planes(crtc
);
4857 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4858 encoder
->disable(encoder
);
4861 * On gen2 planes are double buffered but the pipe isn't, so we must
4862 * wait for planes to fully turn off before disabling the pipe.
4863 * We also need to wait on all gmch platforms because of the
4864 * self-refresh mode constraint explained above.
4866 intel_wait_for_vblank(dev
, pipe
);
4868 intel_disable_pipe(dev_priv
, pipe
);
4870 i9xx_pfit_disable(intel_crtc
);
4872 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4873 if (encoder
->post_disable
)
4874 encoder
->post_disable(encoder
);
4876 if (!intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
)) {
4877 if (IS_CHERRYVIEW(dev
))
4878 chv_disable_pll(dev_priv
, pipe
);
4879 else if (IS_VALLEYVIEW(dev
))
4880 vlv_disable_pll(dev_priv
, pipe
);
4882 i9xx_disable_pll(dev_priv
, pipe
);
4886 intel_set_cpu_fifo_underrun_reporting(dev
, pipe
, false);
4888 intel_crtc
->active
= false;
4889 intel_update_watermarks(crtc
);
4891 mutex_lock(&dev
->struct_mutex
);
4892 intel_update_fbc(dev
);
4893 mutex_unlock(&dev
->struct_mutex
);
4896 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
4900 static void intel_crtc_update_sarea(struct drm_crtc
*crtc
,
4903 struct drm_device
*dev
= crtc
->dev
;
4904 struct drm_i915_master_private
*master_priv
;
4905 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4906 int pipe
= intel_crtc
->pipe
;
4908 if (!dev
->primary
->master
)
4911 master_priv
= dev
->primary
->master
->driver_priv
;
4912 if (!master_priv
->sarea_priv
)
4917 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4918 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4921 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
4922 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
4925 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
4930 /* Master function to enable/disable CRTC and corresponding power wells */
4931 void intel_crtc_control(struct drm_crtc
*crtc
, bool enable
)
4933 struct drm_device
*dev
= crtc
->dev
;
4934 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4935 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4936 enum intel_display_power_domain domain
;
4937 unsigned long domains
;
4940 if (!intel_crtc
->active
) {
4941 domains
= get_crtc_power_domains(crtc
);
4942 for_each_power_domain(domain
, domains
)
4943 intel_display_power_get(dev_priv
, domain
);
4944 intel_crtc
->enabled_power_domains
= domains
;
4946 dev_priv
->display
.crtc_enable(crtc
);
4949 if (intel_crtc
->active
) {
4950 dev_priv
->display
.crtc_disable(crtc
);
4952 domains
= intel_crtc
->enabled_power_domains
;
4953 for_each_power_domain(domain
, domains
)
4954 intel_display_power_put(dev_priv
, domain
);
4955 intel_crtc
->enabled_power_domains
= 0;
4961 * Sets the power management mode of the pipe and plane.
4963 void intel_crtc_update_dpms(struct drm_crtc
*crtc
)
4965 struct drm_device
*dev
= crtc
->dev
;
4966 struct intel_encoder
*intel_encoder
;
4967 bool enable
= false;
4969 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
4970 enable
|= intel_encoder
->connectors_active
;
4972 intel_crtc_control(crtc
, enable
);
4974 intel_crtc_update_sarea(crtc
, enable
);
4977 static void intel_crtc_disable(struct drm_crtc
*crtc
)
4979 struct drm_device
*dev
= crtc
->dev
;
4980 struct drm_connector
*connector
;
4981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4982 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(crtc
->primary
->fb
);
4983 enum pipe pipe
= to_intel_crtc(crtc
)->pipe
;
4985 /* crtc should still be enabled when we disable it. */
4986 WARN_ON(!crtc
->enabled
);
4988 dev_priv
->display
.crtc_disable(crtc
);
4989 intel_crtc_update_sarea(crtc
, false);
4990 dev_priv
->display
.off(crtc
);
4992 if (crtc
->primary
->fb
) {
4993 mutex_lock(&dev
->struct_mutex
);
4994 intel_unpin_fb_obj(old_obj
);
4995 i915_gem_track_fb(old_obj
, NULL
,
4996 INTEL_FRONTBUFFER_PRIMARY(pipe
));
4997 mutex_unlock(&dev
->struct_mutex
);
4998 crtc
->primary
->fb
= NULL
;
5001 /* Update computed state. */
5002 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
5003 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
5006 if (connector
->encoder
->crtc
!= crtc
)
5009 connector
->dpms
= DRM_MODE_DPMS_OFF
;
5010 to_intel_encoder(connector
->encoder
)->connectors_active
= false;
5014 void intel_encoder_destroy(struct drm_encoder
*encoder
)
5016 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
5018 drm_encoder_cleanup(encoder
);
5019 kfree(intel_encoder
);
5022 /* Simple dpms helper for encoders with just one connector, no cloning and only
5023 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5024 * state of the entire output pipe. */
5025 static void intel_encoder_dpms(struct intel_encoder
*encoder
, int mode
)
5027 if (mode
== DRM_MODE_DPMS_ON
) {
5028 encoder
->connectors_active
= true;
5030 intel_crtc_update_dpms(encoder
->base
.crtc
);
5032 encoder
->connectors_active
= false;
5034 intel_crtc_update_dpms(encoder
->base
.crtc
);
5038 /* Cross check the actual hw state with our own modeset state tracking (and it's
5039 * internal consistency). */
5040 static void intel_connector_check_state(struct intel_connector
*connector
)
5042 if (connector
->get_hw_state(connector
)) {
5043 struct intel_encoder
*encoder
= connector
->encoder
;
5044 struct drm_crtc
*crtc
;
5045 bool encoder_enabled
;
5048 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5049 connector
->base
.base
.id
,
5050 connector
->base
.name
);
5052 /* there is no real hw state for MST connectors */
5053 if (connector
->mst_port
)
5056 WARN(connector
->base
.dpms
== DRM_MODE_DPMS_OFF
,
5057 "wrong connector dpms state\n");
5058 WARN(connector
->base
.encoder
!= &encoder
->base
,
5059 "active connector not linked to encoder\n");
5062 WARN(!encoder
->connectors_active
,
5063 "encoder->connectors_active not set\n");
5065 encoder_enabled
= encoder
->get_hw_state(encoder
, &pipe
);
5066 WARN(!encoder_enabled
, "encoder not enabled\n");
5067 if (WARN_ON(!encoder
->base
.crtc
))
5070 crtc
= encoder
->base
.crtc
;
5072 WARN(!crtc
->enabled
, "crtc not enabled\n");
5073 WARN(!to_intel_crtc(crtc
)->active
, "crtc not active\n");
5074 WARN(pipe
!= to_intel_crtc(crtc
)->pipe
,
5075 "encoder active on the wrong pipe\n");
5080 /* Even simpler default implementation, if there's really no special case to
5082 void intel_connector_dpms(struct drm_connector
*connector
, int mode
)
5084 /* All the simple cases only support two dpms states. */
5085 if (mode
!= DRM_MODE_DPMS_ON
)
5086 mode
= DRM_MODE_DPMS_OFF
;
5088 if (mode
== connector
->dpms
)
5091 connector
->dpms
= mode
;
5093 /* Only need to change hw state when actually enabled */
5094 if (connector
->encoder
)
5095 intel_encoder_dpms(to_intel_encoder(connector
->encoder
), mode
);
5097 intel_modeset_check_state(connector
->dev
);
5100 /* Simple connector->get_hw_state implementation for encoders that support only
5101 * one connector and no cloning and hence the encoder state determines the state
5102 * of the connector. */
5103 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
5106 struct intel_encoder
*encoder
= connector
->encoder
;
5108 return encoder
->get_hw_state(encoder
, &pipe
);
5111 static bool ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
5112 struct intel_crtc_config
*pipe_config
)
5114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5115 struct intel_crtc
*pipe_B_crtc
=
5116 to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[PIPE_B
]);
5118 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5119 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5120 if (pipe_config
->fdi_lanes
> 4) {
5121 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5122 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5126 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
5127 if (pipe_config
->fdi_lanes
> 2) {
5128 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5129 pipe_config
->fdi_lanes
);
5136 if (INTEL_INFO(dev
)->num_pipes
== 2)
5139 /* Ivybridge 3 pipe is really complicated */
5144 if (dev_priv
->pipe_to_crtc_mapping
[PIPE_C
]->enabled
&&
5145 pipe_config
->fdi_lanes
> 2) {
5146 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5147 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5152 if (!pipe_has_enabled_pch(pipe_B_crtc
) ||
5153 pipe_B_crtc
->config
.fdi_lanes
<= 2) {
5154 if (pipe_config
->fdi_lanes
> 2) {
5155 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5156 pipe_name(pipe
), pipe_config
->fdi_lanes
);
5160 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5170 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
5171 struct intel_crtc_config
*pipe_config
)
5173 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5174 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5175 int lane
, link_bw
, fdi_dotclock
;
5176 bool setup_ok
, needs_recompute
= false;
5179 /* FDI is a binary signal running at ~2.7GHz, encoding
5180 * each output octet as 10 bits. The actual frequency
5181 * is stored as a divider into a 100MHz clock, and the
5182 * mode pixel clock is stored in units of 1KHz.
5183 * Hence the bw of each lane in terms of the mode signal
5186 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
5188 fdi_dotclock
= adjusted_mode
->crtc_clock
;
5190 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
5191 pipe_config
->pipe_bpp
);
5193 pipe_config
->fdi_lanes
= lane
;
5195 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
5196 link_bw
, &pipe_config
->fdi_m_n
);
5198 setup_ok
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
5199 intel_crtc
->pipe
, pipe_config
);
5200 if (!setup_ok
&& pipe_config
->pipe_bpp
> 6*3) {
5201 pipe_config
->pipe_bpp
-= 2*3;
5202 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5203 pipe_config
->pipe_bpp
);
5204 needs_recompute
= true;
5205 pipe_config
->bw_constrained
= true;
5210 if (needs_recompute
)
5213 return setup_ok
? 0 : -EINVAL
;
5216 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
5217 struct intel_crtc_config
*pipe_config
)
5219 pipe_config
->ips_enabled
= i915
.enable_ips
&&
5220 hsw_crtc_supports_ips(crtc
) &&
5221 pipe_config
->pipe_bpp
<= 24;
5224 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
5225 struct intel_crtc_config
*pipe_config
)
5227 struct drm_device
*dev
= crtc
->base
.dev
;
5228 struct drm_display_mode
*adjusted_mode
= &pipe_config
->adjusted_mode
;
5230 /* FIXME should check pixel clock limits on all platforms */
5231 if (INTEL_INFO(dev
)->gen
< 4) {
5232 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5234 dev_priv
->display
.get_display_clock_speed(dev
);
5237 * Enable pixel doubling when the dot clock
5238 * is > 90% of the (display) core speed.
5240 * GDG double wide on either pipe,
5241 * otherwise pipe A only.
5243 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
5244 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
5246 pipe_config
->double_wide
= true;
5249 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
5254 * Pipe horizontal size must be even in:
5256 * - LVDS dual channel mode
5257 * - Double wide pipe
5259 if ((intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5260 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
5261 pipe_config
->pipe_src_w
&= ~1;
5263 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5264 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5266 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
5267 adjusted_mode
->hsync_start
== adjusted_mode
->hdisplay
)
5270 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) && pipe_config
->pipe_bpp
> 10*3) {
5271 pipe_config
->pipe_bpp
= 10*3; /* 12bpc is gen5+ */
5272 } else if (INTEL_INFO(dev
)->gen
<= 4 && pipe_config
->pipe_bpp
> 8*3) {
5273 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5275 pipe_config
->pipe_bpp
= 8*3;
5279 hsw_compute_ips_config(crtc
, pipe_config
);
5282 * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the
5283 * old clock survives for now.
5285 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
) || HAS_DDI(dev
))
5286 pipe_config
->shared_dpll
= crtc
->config
.shared_dpll
;
5288 if (pipe_config
->has_pch_encoder
)
5289 return ironlake_fdi_compute_config(crtc
, pipe_config
);
5294 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
5296 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5297 int vco
= valleyview_get_vco(dev_priv
);
5301 /* FIXME: Punit isn't quite ready yet */
5302 if (IS_CHERRYVIEW(dev
))
5305 mutex_lock(&dev_priv
->dpio_lock
);
5306 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5307 mutex_unlock(&dev_priv
->dpio_lock
);
5309 divider
= val
& DISPLAY_FREQUENCY_VALUES
;
5311 WARN((val
& DISPLAY_FREQUENCY_STATUS
) !=
5312 (divider
<< DISPLAY_FREQUENCY_STATUS_SHIFT
),
5313 "cdclk change in progress\n");
5315 return DIV_ROUND_CLOSEST(vco
<< 1, divider
+ 1);
5318 static int i945_get_display_clock_speed(struct drm_device
*dev
)
5323 static int i915_get_display_clock_speed(struct drm_device
*dev
)
5328 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
5333 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
5337 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5339 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5340 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
5342 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
5344 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
5346 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
5349 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
5350 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
5352 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
5357 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
5361 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
5363 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
5366 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
5367 case GC_DISPLAY_CLOCK_333_MHZ
:
5370 case GC_DISPLAY_CLOCK_190_200_MHZ
:
5376 static int i865_get_display_clock_speed(struct drm_device
*dev
)
5381 static int i855_get_display_clock_speed(struct drm_device
*dev
)
5384 /* Assume that the hardware is in the high speed state. This
5385 * should be the default.
5387 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
5388 case GC_CLOCK_133_200
:
5389 case GC_CLOCK_100_200
:
5391 case GC_CLOCK_166_250
:
5393 case GC_CLOCK_100_133
:
5397 /* Shouldn't happen */
5401 static int i830_get_display_clock_speed(struct drm_device
*dev
)
5407 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
5409 while (*num
> DATA_LINK_M_N_MASK
||
5410 *den
> DATA_LINK_M_N_MASK
) {
5416 static void compute_m_n(unsigned int m
, unsigned int n
,
5417 uint32_t *ret_m
, uint32_t *ret_n
)
5419 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
5420 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
5421 intel_reduce_m_n_ratio(ret_m
, ret_n
);
5425 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
5426 int pixel_clock
, int link_clock
,
5427 struct intel_link_m_n
*m_n
)
5431 compute_m_n(bits_per_pixel
* pixel_clock
,
5432 link_clock
* nlanes
* 8,
5433 &m_n
->gmch_m
, &m_n
->gmch_n
);
5435 compute_m_n(pixel_clock
, link_clock
,
5436 &m_n
->link_m
, &m_n
->link_n
);
5439 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
5441 if (i915
.panel_use_ssc
>= 0)
5442 return i915
.panel_use_ssc
!= 0;
5443 return dev_priv
->vbt
.lvds_use_ssc
5444 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
5447 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
5449 struct drm_device
*dev
= crtc
->dev
;
5450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5453 if (IS_VALLEYVIEW(dev
)) {
5455 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
5456 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
5457 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
5458 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
5459 } else if (!IS_GEN2(dev
)) {
5468 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
5470 return (1 << dpll
->n
) << 16 | dpll
->m2
;
5473 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
5475 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
5478 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
5479 intel_clock_t
*reduced_clock
)
5481 struct drm_device
*dev
= crtc
->base
.dev
;
5484 if (IS_PINEVIEW(dev
)) {
5485 fp
= pnv_dpll_compute_fp(&crtc
->config
.dpll
);
5487 fp2
= pnv_dpll_compute_fp(reduced_clock
);
5489 fp
= i9xx_dpll_compute_fp(&crtc
->config
.dpll
);
5491 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
5494 crtc
->config
.dpll_hw_state
.fp0
= fp
;
5496 crtc
->lowfreq_avail
= false;
5497 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5498 reduced_clock
&& i915
.powersave
) {
5499 crtc
->config
.dpll_hw_state
.fp1
= fp2
;
5500 crtc
->lowfreq_avail
= true;
5502 crtc
->config
.dpll_hw_state
.fp1
= fp
;
5506 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
5512 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5513 * and set it to a reasonable value instead.
5515 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5516 reg_val
&= 0xffffff00;
5517 reg_val
|= 0x00000030;
5518 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5520 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5521 reg_val
&= 0x8cffffff;
5522 reg_val
= 0x8c000000;
5523 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5525 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
5526 reg_val
&= 0xffffff00;
5527 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
5529 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
5530 reg_val
&= 0x00ffffff;
5531 reg_val
|= 0xb0000000;
5532 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
5535 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
5536 struct intel_link_m_n
*m_n
)
5538 struct drm_device
*dev
= crtc
->base
.dev
;
5539 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5540 int pipe
= crtc
->pipe
;
5542 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5543 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
5544 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
5545 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
5548 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
5549 struct intel_link_m_n
*m_n
,
5550 struct intel_link_m_n
*m2_n2
)
5552 struct drm_device
*dev
= crtc
->base
.dev
;
5553 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5554 int pipe
= crtc
->pipe
;
5555 enum transcoder transcoder
= crtc
->config
.cpu_transcoder
;
5557 if (INTEL_INFO(dev
)->gen
>= 5) {
5558 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5559 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
5560 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
5561 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
5562 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5563 * for gen < 8) and if DRRS is supported (to make sure the
5564 * registers are not unnecessarily accessed).
5566 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
5567 crtc
->config
.has_drrs
) {
5568 I915_WRITE(PIPE_DATA_M2(transcoder
),
5569 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
5570 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
5571 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
5572 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
5575 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
5576 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
5577 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
5578 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
5582 void intel_dp_set_m_n(struct intel_crtc
*crtc
)
5584 if (crtc
->config
.has_pch_encoder
)
5585 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
);
5587 intel_cpu_transcoder_set_m_n(crtc
, &crtc
->config
.dp_m_n
,
5588 &crtc
->config
.dp_m2_n2
);
5591 static void vlv_update_pll(struct intel_crtc
*crtc
)
5596 * Enable DPIO clock input. We should never disable the reference
5597 * clock for pipe B, since VGA hotplug / manual detection depends
5600 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
5601 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
5602 /* We should never disable this, set it here for state tracking */
5603 if (crtc
->pipe
== PIPE_B
)
5604 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5605 dpll
|= DPLL_VCO_ENABLE
;
5606 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5608 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5609 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5610 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5613 static void vlv_prepare_pll(struct intel_crtc
*crtc
)
5615 struct drm_device
*dev
= crtc
->base
.dev
;
5616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5617 int pipe
= crtc
->pipe
;
5619 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
5620 u32 coreclk
, reg_val
;
5622 mutex_lock(&dev_priv
->dpio_lock
);
5624 bestn
= crtc
->config
.dpll
.n
;
5625 bestm1
= crtc
->config
.dpll
.m1
;
5626 bestm2
= crtc
->config
.dpll
.m2
;
5627 bestp1
= crtc
->config
.dpll
.p1
;
5628 bestp2
= crtc
->config
.dpll
.p2
;
5630 /* See eDP HDMI DPIO driver vbios notes doc */
5632 /* PLL B needs special handling */
5634 vlv_pllb_recal_opamp(dev_priv
, pipe
);
5636 /* Set up Tx target for periodic Rcomp update */
5637 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
5639 /* Disable target IRef on PLL */
5640 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
5641 reg_val
&= 0x00ffffff;
5642 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
5644 /* Disable fast lock */
5645 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
5647 /* Set idtafcrecal before PLL is enabled */
5648 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
5649 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
5650 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
5651 mdiv
|= (1 << DPIO_K_SHIFT
);
5654 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5655 * but we don't support that).
5656 * Note: don't use the DAC post divider as it seems unstable.
5658 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
5659 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5661 mdiv
|= DPIO_ENABLE_CALIBRATION
;
5662 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
5664 /* Set HBR and RBR LPF coefficients */
5665 if (crtc
->config
.port_clock
== 162000 ||
5666 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_ANALOG
) ||
5667 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
))
5668 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5671 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
5674 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
) ||
5675 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
)) {
5676 /* Use SSC source */
5678 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5681 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5683 } else { /* HDMI or VGA */
5684 /* Use bend source */
5686 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5689 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
5693 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
5694 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
5695 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
) ||
5696 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_EDP
))
5697 coreclk
|= 0x01000000;
5698 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
5700 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
5701 mutex_unlock(&dev_priv
->dpio_lock
);
5704 static void chv_update_pll(struct intel_crtc
*crtc
)
5706 crtc
->config
.dpll_hw_state
.dpll
= DPLL_SSC_REF_CLOCK_CHV
|
5707 DPLL_REFA_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
5709 if (crtc
->pipe
!= PIPE_A
)
5710 crtc
->config
.dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
5712 crtc
->config
.dpll_hw_state
.dpll_md
=
5713 (crtc
->config
.pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5716 static void chv_prepare_pll(struct intel_crtc
*crtc
)
5718 struct drm_device
*dev
= crtc
->base
.dev
;
5719 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5720 int pipe
= crtc
->pipe
;
5721 int dpll_reg
= DPLL(crtc
->pipe
);
5722 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
5723 u32 loopfilter
, intcoeff
;
5724 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
5727 bestn
= crtc
->config
.dpll
.n
;
5728 bestm2_frac
= crtc
->config
.dpll
.m2
& 0x3fffff;
5729 bestm1
= crtc
->config
.dpll
.m1
;
5730 bestm2
= crtc
->config
.dpll
.m2
>> 22;
5731 bestp1
= crtc
->config
.dpll
.p1
;
5732 bestp2
= crtc
->config
.dpll
.p2
;
5735 * Enable Refclk and SSC
5737 I915_WRITE(dpll_reg
,
5738 crtc
->config
.dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
5740 mutex_lock(&dev_priv
->dpio_lock
);
5742 /* p1 and p2 divider */
5743 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
5744 5 << DPIO_CHV_S1_DIV_SHIFT
|
5745 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
5746 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
5747 1 << DPIO_CHV_K_DIV_SHIFT
);
5749 /* Feedback post-divider - m2 */
5750 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
5752 /* Feedback refclk divider - n and m1 */
5753 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
5754 DPIO_CHV_M1_DIV_BY_2
|
5755 1 << DPIO_CHV_N_DIV_SHIFT
);
5757 /* M2 fraction division */
5758 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
5760 /* M2 fraction division enable */
5761 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
),
5762 DPIO_CHV_FRAC_DIV_EN
|
5763 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
));
5766 refclk
= i9xx_get_refclk(&crtc
->base
, 0);
5767 loopfilter
= 5 << DPIO_CHV_PROP_COEFF_SHIFT
|
5768 2 << DPIO_CHV_GAIN_CTRL_SHIFT
;
5769 if (refclk
== 100000)
5771 else if (refclk
== 38400)
5775 loopfilter
|= intcoeff
<< DPIO_CHV_INT_COEFF_SHIFT
;
5776 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
5779 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
5780 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
5783 mutex_unlock(&dev_priv
->dpio_lock
);
5786 static void i9xx_update_pll(struct intel_crtc
*crtc
,
5787 intel_clock_t
*reduced_clock
,
5790 struct drm_device
*dev
= crtc
->base
.dev
;
5791 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5794 struct dpll
*clock
= &crtc
->config
.dpll
;
5796 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5798 is_sdvo
= intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_SDVO
) ||
5799 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
);
5801 dpll
= DPLL_VGA_MODE_DIS
;
5803 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
))
5804 dpll
|= DPLLB_MODE_LVDS
;
5806 dpll
|= DPLLB_MODE_DAC_SERIAL
;
5808 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
5809 dpll
|= (crtc
->config
.pixel_multiplier
- 1)
5810 << SDVO_MULTIPLIER_SHIFT_HIRES
;
5814 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5816 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DISPLAYPORT
))
5817 dpll
|= DPLL_SDVO_HIGH_SPEED
;
5819 /* compute bitmask from p1 value */
5820 if (IS_PINEVIEW(dev
))
5821 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
5823 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5824 if (IS_G4X(dev
) && reduced_clock
)
5825 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
5827 switch (clock
->p2
) {
5829 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
5832 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
5835 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
5838 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
5841 if (INTEL_INFO(dev
)->gen
>= 4)
5842 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
5844 if (crtc
->config
.sdvo_tv_clock
)
5845 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
5846 else if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5847 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5848 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5850 dpll
|= PLL_REF_INPUT_DREFCLK
;
5852 dpll
|= DPLL_VCO_ENABLE
;
5853 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5855 if (INTEL_INFO(dev
)->gen
>= 4) {
5856 u32 dpll_md
= (crtc
->config
.pixel_multiplier
- 1)
5857 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
5858 crtc
->config
.dpll_hw_state
.dpll_md
= dpll_md
;
5862 static void i8xx_update_pll(struct intel_crtc
*crtc
,
5863 intel_clock_t
*reduced_clock
,
5866 struct drm_device
*dev
= crtc
->base
.dev
;
5867 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5869 struct dpll
*clock
= &crtc
->config
.dpll
;
5871 i9xx_update_pll_dividers(crtc
, reduced_clock
);
5873 dpll
= DPLL_VGA_MODE_DIS
;
5875 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
)) {
5876 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5879 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
5881 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
5883 dpll
|= PLL_P2_DIVIDE_BY_4
;
5886 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_DVO
))
5887 dpll
|= DPLL_DVO_2X_MODE
;
5889 if (intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_LVDS
) &&
5890 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
5891 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
5893 dpll
|= PLL_REF_INPUT_DREFCLK
;
5895 dpll
|= DPLL_VCO_ENABLE
;
5896 crtc
->config
.dpll_hw_state
.dpll
= dpll
;
5899 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
5901 struct drm_device
*dev
= intel_crtc
->base
.dev
;
5902 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5903 enum pipe pipe
= intel_crtc
->pipe
;
5904 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
5905 struct drm_display_mode
*adjusted_mode
=
5906 &intel_crtc
->config
.adjusted_mode
;
5907 uint32_t crtc_vtotal
, crtc_vblank_end
;
5910 /* We need to be careful not to changed the adjusted mode, for otherwise
5911 * the hw state checker will get angry at the mismatch. */
5912 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
5913 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
5915 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
5916 /* the chip adds 2 halflines automatically */
5918 crtc_vblank_end
-= 1;
5920 if (intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
5921 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
5923 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
5924 adjusted_mode
->crtc_htotal
/ 2;
5926 vsyncshift
+= adjusted_mode
->crtc_htotal
;
5929 if (INTEL_INFO(dev
)->gen
> 3)
5930 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
5932 I915_WRITE(HTOTAL(cpu_transcoder
),
5933 (adjusted_mode
->crtc_hdisplay
- 1) |
5934 ((adjusted_mode
->crtc_htotal
- 1) << 16));
5935 I915_WRITE(HBLANK(cpu_transcoder
),
5936 (adjusted_mode
->crtc_hblank_start
- 1) |
5937 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
5938 I915_WRITE(HSYNC(cpu_transcoder
),
5939 (adjusted_mode
->crtc_hsync_start
- 1) |
5940 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
5942 I915_WRITE(VTOTAL(cpu_transcoder
),
5943 (adjusted_mode
->crtc_vdisplay
- 1) |
5944 ((crtc_vtotal
- 1) << 16));
5945 I915_WRITE(VBLANK(cpu_transcoder
),
5946 (adjusted_mode
->crtc_vblank_start
- 1) |
5947 ((crtc_vblank_end
- 1) << 16));
5948 I915_WRITE(VSYNC(cpu_transcoder
),
5949 (adjusted_mode
->crtc_vsync_start
- 1) |
5950 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
5952 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5953 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5954 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5956 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
5957 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
5958 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
5960 /* pipesrc controls the size that is scaled from, which should
5961 * always be the user's requested size.
5963 I915_WRITE(PIPESRC(pipe
),
5964 ((intel_crtc
->config
.pipe_src_w
- 1) << 16) |
5965 (intel_crtc
->config
.pipe_src_h
- 1));
5968 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
5969 struct intel_crtc_config
*pipe_config
)
5971 struct drm_device
*dev
= crtc
->base
.dev
;
5972 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5973 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
5976 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
5977 pipe_config
->adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
5978 pipe_config
->adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
5979 tmp
= I915_READ(HBLANK(cpu_transcoder
));
5980 pipe_config
->adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
5981 pipe_config
->adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5982 tmp
= I915_READ(HSYNC(cpu_transcoder
));
5983 pipe_config
->adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
5984 pipe_config
->adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5986 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
5987 pipe_config
->adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
5988 pipe_config
->adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
5989 tmp
= I915_READ(VBLANK(cpu_transcoder
));
5990 pipe_config
->adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
5991 pipe_config
->adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
5992 tmp
= I915_READ(VSYNC(cpu_transcoder
));
5993 pipe_config
->adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
5994 pipe_config
->adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
5996 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
5997 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
5998 pipe_config
->adjusted_mode
.crtc_vtotal
+= 1;
5999 pipe_config
->adjusted_mode
.crtc_vblank_end
+= 1;
6002 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
6003 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
6004 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
6006 pipe_config
->requested_mode
.vdisplay
= pipe_config
->pipe_src_h
;
6007 pipe_config
->requested_mode
.hdisplay
= pipe_config
->pipe_src_w
;
6010 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
6011 struct intel_crtc_config
*pipe_config
)
6013 mode
->hdisplay
= pipe_config
->adjusted_mode
.crtc_hdisplay
;
6014 mode
->htotal
= pipe_config
->adjusted_mode
.crtc_htotal
;
6015 mode
->hsync_start
= pipe_config
->adjusted_mode
.crtc_hsync_start
;
6016 mode
->hsync_end
= pipe_config
->adjusted_mode
.crtc_hsync_end
;
6018 mode
->vdisplay
= pipe_config
->adjusted_mode
.crtc_vdisplay
;
6019 mode
->vtotal
= pipe_config
->adjusted_mode
.crtc_vtotal
;
6020 mode
->vsync_start
= pipe_config
->adjusted_mode
.crtc_vsync_start
;
6021 mode
->vsync_end
= pipe_config
->adjusted_mode
.crtc_vsync_end
;
6023 mode
->flags
= pipe_config
->adjusted_mode
.flags
;
6025 mode
->clock
= pipe_config
->adjusted_mode
.crtc_clock
;
6026 mode
->flags
|= pipe_config
->adjusted_mode
.flags
;
6029 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
6031 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6032 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6037 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
6038 I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
)
6039 pipeconf
|= PIPECONF_ENABLE
;
6041 if (intel_crtc
->config
.double_wide
)
6042 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
6044 /* only g4x and later have fancy bpc/dither controls */
6045 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6046 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6047 if (intel_crtc
->config
.dither
&& intel_crtc
->config
.pipe_bpp
!= 30)
6048 pipeconf
|= PIPECONF_DITHER_EN
|
6049 PIPECONF_DITHER_TYPE_SP
;
6051 switch (intel_crtc
->config
.pipe_bpp
) {
6053 pipeconf
|= PIPECONF_6BPC
;
6056 pipeconf
|= PIPECONF_8BPC
;
6059 pipeconf
|= PIPECONF_10BPC
;
6062 /* Case prevented by intel_choose_pipe_bpp_dither. */
6067 if (HAS_PIPE_CXSR(dev
)) {
6068 if (intel_crtc
->lowfreq_avail
) {
6069 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6070 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
6072 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6076 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
6077 if (INTEL_INFO(dev
)->gen
< 4 ||
6078 intel_pipe_has_type(&intel_crtc
->base
, INTEL_OUTPUT_SDVO
))
6079 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
6081 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
6083 pipeconf
|= PIPECONF_PROGRESSIVE
;
6085 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
.limited_color_range
)
6086 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
6088 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
6089 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
6092 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
6094 struct drm_framebuffer
*fb
)
6096 struct drm_device
*dev
= crtc
->dev
;
6097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6098 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6099 int refclk
, num_connectors
= 0;
6100 intel_clock_t clock
, reduced_clock
;
6101 bool ok
, has_reduced_clock
= false;
6102 bool is_lvds
= false, is_dsi
= false;
6103 struct intel_encoder
*encoder
;
6104 const intel_limit_t
*limit
;
6106 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6107 switch (encoder
->type
) {
6108 case INTEL_OUTPUT_LVDS
:
6111 case INTEL_OUTPUT_DSI
:
6122 if (!intel_crtc
->config
.clock_set
) {
6123 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
6126 * Returns a set of divisors for the desired target clock with
6127 * the given refclk, or FALSE. The returned values represent
6128 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6131 limit
= intel_limit(crtc
, refclk
);
6132 ok
= dev_priv
->display
.find_dpll(limit
, crtc
,
6133 intel_crtc
->config
.port_clock
,
6134 refclk
, NULL
, &clock
);
6136 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6140 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6142 * Ensure we match the reduced clock's P to the target
6143 * clock. If the clocks don't match, we can't switch
6144 * the display clock by using the FP0/FP1. In such case
6145 * we will disable the LVDS downclock feature.
6148 dev_priv
->display
.find_dpll(limit
, crtc
,
6149 dev_priv
->lvds_downclock
,
6153 /* Compat-code for transition, will disappear. */
6154 intel_crtc
->config
.dpll
.n
= clock
.n
;
6155 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
6156 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
6157 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
6158 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
6162 i8xx_update_pll(intel_crtc
,
6163 has_reduced_clock
? &reduced_clock
: NULL
,
6165 } else if (IS_CHERRYVIEW(dev
)) {
6166 chv_update_pll(intel_crtc
);
6167 } else if (IS_VALLEYVIEW(dev
)) {
6168 vlv_update_pll(intel_crtc
);
6170 i9xx_update_pll(intel_crtc
,
6171 has_reduced_clock
? &reduced_clock
: NULL
,
6178 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
6179 struct intel_crtc_config
*pipe_config
)
6181 struct drm_device
*dev
= crtc
->base
.dev
;
6182 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6185 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
6188 tmp
= I915_READ(PFIT_CONTROL
);
6189 if (!(tmp
& PFIT_ENABLE
))
6192 /* Check whether the pfit is attached to our pipe. */
6193 if (INTEL_INFO(dev
)->gen
< 4) {
6194 if (crtc
->pipe
!= PIPE_B
)
6197 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
6201 pipe_config
->gmch_pfit
.control
= tmp
;
6202 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
6203 if (INTEL_INFO(dev
)->gen
< 5)
6204 pipe_config
->gmch_pfit
.lvds_border_bits
=
6205 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
6208 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
6209 struct intel_crtc_config
*pipe_config
)
6211 struct drm_device
*dev
= crtc
->base
.dev
;
6212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6213 int pipe
= pipe_config
->cpu_transcoder
;
6214 intel_clock_t clock
;
6216 int refclk
= 100000;
6218 /* In case of MIPI DPLL will not even be used */
6219 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
6222 mutex_lock(&dev_priv
->dpio_lock
);
6223 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
6224 mutex_unlock(&dev_priv
->dpio_lock
);
6226 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
6227 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
6228 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
6229 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
6230 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
6232 vlv_clock(refclk
, &clock
);
6234 /* clock.dot is the fast clock */
6235 pipe_config
->port_clock
= clock
.dot
/ 5;
6238 static void i9xx_get_plane_config(struct intel_crtc
*crtc
,
6239 struct intel_plane_config
*plane_config
)
6241 struct drm_device
*dev
= crtc
->base
.dev
;
6242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6243 u32 val
, base
, offset
;
6244 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
6245 int fourcc
, pixel_format
;
6248 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
6249 if (!crtc
->base
.primary
->fb
) {
6250 DRM_DEBUG_KMS("failed to alloc fb\n");
6254 val
= I915_READ(DSPCNTR(plane
));
6256 if (INTEL_INFO(dev
)->gen
>= 4)
6257 if (val
& DISPPLANE_TILED
)
6258 plane_config
->tiled
= true;
6260 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
6261 fourcc
= intel_format_to_fourcc(pixel_format
);
6262 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
6263 crtc
->base
.primary
->fb
->bits_per_pixel
=
6264 drm_format_plane_cpp(fourcc
, 0) * 8;
6266 if (INTEL_INFO(dev
)->gen
>= 4) {
6267 if (plane_config
->tiled
)
6268 offset
= I915_READ(DSPTILEOFF(plane
));
6270 offset
= I915_READ(DSPLINOFF(plane
));
6271 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
6273 base
= I915_READ(DSPADDR(plane
));
6275 plane_config
->base
= base
;
6277 val
= I915_READ(PIPESRC(pipe
));
6278 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
6279 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
6281 val
= I915_READ(DSPSTRIDE(pipe
));
6282 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
6284 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
6285 plane_config
->tiled
);
6287 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
6290 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6291 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
6292 crtc
->base
.primary
->fb
->height
,
6293 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
6294 crtc
->base
.primary
->fb
->pitches
[0],
6295 plane_config
->size
);
6299 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
6300 struct intel_crtc_config
*pipe_config
)
6302 struct drm_device
*dev
= crtc
->base
.dev
;
6303 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6304 int pipe
= pipe_config
->cpu_transcoder
;
6305 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
6306 intel_clock_t clock
;
6307 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
;
6308 int refclk
= 100000;
6310 mutex_lock(&dev_priv
->dpio_lock
);
6311 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
6312 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
6313 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
6314 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
6315 mutex_unlock(&dev_priv
->dpio_lock
);
6317 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
6318 clock
.m2
= ((pll_dw0
& 0xff) << 22) | (pll_dw2
& 0x3fffff);
6319 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
6320 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
6321 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
6323 chv_clock(refclk
, &clock
);
6325 /* clock.dot is the fast clock */
6326 pipe_config
->port_clock
= clock
.dot
/ 5;
6329 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
6330 struct intel_crtc_config
*pipe_config
)
6332 struct drm_device
*dev
= crtc
->base
.dev
;
6333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6336 if (!intel_display_power_enabled(dev_priv
,
6337 POWER_DOMAIN_PIPE(crtc
->pipe
)))
6340 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
6341 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
6343 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
6344 if (!(tmp
& PIPECONF_ENABLE
))
6347 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
6348 switch (tmp
& PIPECONF_BPC_MASK
) {
6350 pipe_config
->pipe_bpp
= 18;
6353 pipe_config
->pipe_bpp
= 24;
6355 case PIPECONF_10BPC
:
6356 pipe_config
->pipe_bpp
= 30;
6363 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
6364 pipe_config
->limited_color_range
= true;
6366 if (INTEL_INFO(dev
)->gen
< 4)
6367 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
6369 intel_get_pipe_timings(crtc
, pipe_config
);
6371 i9xx_get_pfit_config(crtc
, pipe_config
);
6373 if (INTEL_INFO(dev
)->gen
>= 4) {
6374 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
6375 pipe_config
->pixel_multiplier
=
6376 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
6377 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
6378 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
6379 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
6380 tmp
= I915_READ(DPLL(crtc
->pipe
));
6381 pipe_config
->pixel_multiplier
=
6382 ((tmp
& SDVO_MULTIPLIER_MASK
)
6383 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
6385 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6386 * port and will be fixed up in the encoder->get_config
6388 pipe_config
->pixel_multiplier
= 1;
6390 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
6391 if (!IS_VALLEYVIEW(dev
)) {
6392 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
6393 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
6395 /* Mask out read-only status bits. */
6396 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
6397 DPLL_PORTC_READY_MASK
|
6398 DPLL_PORTB_READY_MASK
);
6401 if (IS_CHERRYVIEW(dev
))
6402 chv_crtc_clock_get(crtc
, pipe_config
);
6403 else if (IS_VALLEYVIEW(dev
))
6404 vlv_crtc_clock_get(crtc
, pipe_config
);
6406 i9xx_crtc_clock_get(crtc
, pipe_config
);
6411 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
6413 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6414 struct intel_encoder
*encoder
;
6416 bool has_lvds
= false;
6417 bool has_cpu_edp
= false;
6418 bool has_panel
= false;
6419 bool has_ck505
= false;
6420 bool can_ssc
= false;
6422 /* We need to take the global config into account */
6423 for_each_intel_encoder(dev
, encoder
) {
6424 switch (encoder
->type
) {
6425 case INTEL_OUTPUT_LVDS
:
6429 case INTEL_OUTPUT_EDP
:
6431 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
6437 if (HAS_PCH_IBX(dev
)) {
6438 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
6439 can_ssc
= has_ck505
;
6445 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6446 has_panel
, has_lvds
, has_ck505
);
6448 /* Ironlake: try to setup display ref clock before DPLL
6449 * enabling. This is only under driver's control after
6450 * PCH B stepping, previous chipset stepping should be
6451 * ignoring this setting.
6453 val
= I915_READ(PCH_DREF_CONTROL
);
6455 /* As we must carefully and slowly disable/enable each source in turn,
6456 * compute the final state we want first and check if we need to
6457 * make any changes at all.
6460 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6462 final
|= DREF_NONSPREAD_CK505_ENABLE
;
6464 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6466 final
&= ~DREF_SSC_SOURCE_MASK
;
6467 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6468 final
&= ~DREF_SSC1_ENABLE
;
6471 final
|= DREF_SSC_SOURCE_ENABLE
;
6473 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6474 final
|= DREF_SSC1_ENABLE
;
6477 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
6478 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6480 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6482 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6484 final
|= DREF_SSC_SOURCE_DISABLE
;
6485 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6491 /* Always enable nonspread source */
6492 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
6495 val
|= DREF_NONSPREAD_CK505_ENABLE
;
6497 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
6500 val
&= ~DREF_SSC_SOURCE_MASK
;
6501 val
|= DREF_SSC_SOURCE_ENABLE
;
6503 /* SSC must be turned on before enabling the CPU output */
6504 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6505 DRM_DEBUG_KMS("Using SSC on panel\n");
6506 val
|= DREF_SSC1_ENABLE
;
6508 val
&= ~DREF_SSC1_ENABLE
;
6510 /* Get SSC going before enabling the outputs */
6511 I915_WRITE(PCH_DREF_CONTROL
, val
);
6512 POSTING_READ(PCH_DREF_CONTROL
);
6515 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6517 /* Enable CPU source on CPU attached eDP */
6519 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
6520 DRM_DEBUG_KMS("Using SSC on eDP\n");
6521 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
6523 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
6525 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6527 I915_WRITE(PCH_DREF_CONTROL
, val
);
6528 POSTING_READ(PCH_DREF_CONTROL
);
6531 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6533 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
6535 /* Turn off CPU output */
6536 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
6538 I915_WRITE(PCH_DREF_CONTROL
, val
);
6539 POSTING_READ(PCH_DREF_CONTROL
);
6542 /* Turn off the SSC source */
6543 val
&= ~DREF_SSC_SOURCE_MASK
;
6544 val
|= DREF_SSC_SOURCE_DISABLE
;
6547 val
&= ~DREF_SSC1_ENABLE
;
6549 I915_WRITE(PCH_DREF_CONTROL
, val
);
6550 POSTING_READ(PCH_DREF_CONTROL
);
6554 BUG_ON(val
!= final
);
6557 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
6561 tmp
= I915_READ(SOUTH_CHICKEN2
);
6562 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
6563 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6565 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
6566 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
6567 DRM_ERROR("FDI mPHY reset assert timeout\n");
6569 tmp
= I915_READ(SOUTH_CHICKEN2
);
6570 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
6571 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
6573 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
6574 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
6575 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6578 /* WaMPhyProgramming:hsw */
6579 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
6583 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
6584 tmp
&= ~(0xFF << 24);
6585 tmp
|= (0x12 << 24);
6586 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
6588 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
6590 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
6592 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
6594 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
6596 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
6597 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6598 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
6600 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
6601 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
6602 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
6604 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
6607 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
6609 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
6612 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
6614 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
6617 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
6619 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
6622 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
6624 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
6625 tmp
&= ~(0xFF << 16);
6626 tmp
|= (0x1C << 16);
6627 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
6629 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
6630 tmp
&= ~(0xFF << 16);
6631 tmp
|= (0x1C << 16);
6632 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
6634 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
6636 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
6638 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
6640 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
6642 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
6643 tmp
&= ~(0xF << 28);
6645 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
6647 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
6648 tmp
&= ~(0xF << 28);
6650 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
6653 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6654 * Programming" based on the parameters passed:
6655 * - Sequence to enable CLKOUT_DP
6656 * - Sequence to enable CLKOUT_DP without spread
6657 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6659 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
6662 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6665 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
6667 if (WARN(dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
&&
6668 with_fdi
, "LP PCH doesn't have FDI\n"))
6671 mutex_lock(&dev_priv
->dpio_lock
);
6673 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6674 tmp
&= ~SBI_SSCCTL_DISABLE
;
6675 tmp
|= SBI_SSCCTL_PATHALT
;
6676 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6681 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6682 tmp
&= ~SBI_SSCCTL_PATHALT
;
6683 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6686 lpt_reset_fdi_mphy(dev_priv
);
6687 lpt_program_fdi_mphy(dev_priv
);
6691 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6692 SBI_GEN0
: SBI_DBUFF0
;
6693 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6694 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6695 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6697 mutex_unlock(&dev_priv
->dpio_lock
);
6700 /* Sequence to disable CLKOUT_DP */
6701 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
6703 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6706 mutex_lock(&dev_priv
->dpio_lock
);
6708 reg
= (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) ?
6709 SBI_GEN0
: SBI_DBUFF0
;
6710 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
6711 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
6712 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
6714 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
6715 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
6716 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
6717 tmp
|= SBI_SSCCTL_PATHALT
;
6718 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6721 tmp
|= SBI_SSCCTL_DISABLE
;
6722 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
6725 mutex_unlock(&dev_priv
->dpio_lock
);
6728 static void lpt_init_pch_refclk(struct drm_device
*dev
)
6730 struct intel_encoder
*encoder
;
6731 bool has_vga
= false;
6733 for_each_intel_encoder(dev
, encoder
) {
6734 switch (encoder
->type
) {
6735 case INTEL_OUTPUT_ANALOG
:
6742 lpt_enable_clkout_dp(dev
, true, true);
6744 lpt_disable_clkout_dp(dev
);
6748 * Initialize reference clocks when the driver loads
6750 void intel_init_pch_refclk(struct drm_device
*dev
)
6752 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
6753 ironlake_init_pch_refclk(dev
);
6754 else if (HAS_PCH_LPT(dev
))
6755 lpt_init_pch_refclk(dev
);
6758 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
6760 struct drm_device
*dev
= crtc
->dev
;
6761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6762 struct intel_encoder
*encoder
;
6763 int num_connectors
= 0;
6764 bool is_lvds
= false;
6766 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
6767 switch (encoder
->type
) {
6768 case INTEL_OUTPUT_LVDS
:
6775 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
6776 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6777 dev_priv
->vbt
.lvds_ssc_freq
);
6778 return dev_priv
->vbt
.lvds_ssc_freq
;
6784 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
6786 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
6787 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6788 int pipe
= intel_crtc
->pipe
;
6793 switch (intel_crtc
->config
.pipe_bpp
) {
6795 val
|= PIPECONF_6BPC
;
6798 val
|= PIPECONF_8BPC
;
6801 val
|= PIPECONF_10BPC
;
6804 val
|= PIPECONF_12BPC
;
6807 /* Case prevented by intel_choose_pipe_bpp_dither. */
6811 if (intel_crtc
->config
.dither
)
6812 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6814 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6815 val
|= PIPECONF_INTERLACED_ILK
;
6817 val
|= PIPECONF_PROGRESSIVE
;
6819 if (intel_crtc
->config
.limited_color_range
)
6820 val
|= PIPECONF_COLOR_RANGE_SELECT
;
6822 I915_WRITE(PIPECONF(pipe
), val
);
6823 POSTING_READ(PIPECONF(pipe
));
6827 * Set up the pipe CSC unit.
6829 * Currently only full range RGB to limited range RGB conversion
6830 * is supported, but eventually this should handle various
6831 * RGB<->YCbCr scenarios as well.
6833 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
6835 struct drm_device
*dev
= crtc
->dev
;
6836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6837 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6838 int pipe
= intel_crtc
->pipe
;
6839 uint16_t coeff
= 0x7800; /* 1.0 */
6842 * TODO: Check what kind of values actually come out of the pipe
6843 * with these coeff/postoff values and adjust to get the best
6844 * accuracy. Perhaps we even need to take the bpc value into
6848 if (intel_crtc
->config
.limited_color_range
)
6849 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6852 * GY/GU and RY/RU should be the other way around according
6853 * to BSpec, but reality doesn't agree. Just set them up in
6854 * a way that results in the correct picture.
6856 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
6857 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
6859 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
6860 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
6862 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
6863 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
6865 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
6866 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
6867 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
6869 if (INTEL_INFO(dev
)->gen
> 6) {
6870 uint16_t postoff
= 0;
6872 if (intel_crtc
->config
.limited_color_range
)
6873 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
6875 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
6876 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
6877 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
6879 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
6881 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
6883 if (intel_crtc
->config
.limited_color_range
)
6884 mode
|= CSC_BLACK_SCREEN_OFFSET
;
6886 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
6890 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
6892 struct drm_device
*dev
= crtc
->dev
;
6893 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6894 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6895 enum pipe pipe
= intel_crtc
->pipe
;
6896 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
6901 if (IS_HASWELL(dev
) && intel_crtc
->config
.dither
)
6902 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
6904 if (intel_crtc
->config
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
6905 val
|= PIPECONF_INTERLACED_ILK
;
6907 val
|= PIPECONF_PROGRESSIVE
;
6909 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
6910 POSTING_READ(PIPECONF(cpu_transcoder
));
6912 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
6913 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
6915 if (IS_BROADWELL(dev
)) {
6918 switch (intel_crtc
->config
.pipe_bpp
) {
6920 val
|= PIPEMISC_DITHER_6_BPC
;
6923 val
|= PIPEMISC_DITHER_8_BPC
;
6926 val
|= PIPEMISC_DITHER_10_BPC
;
6929 val
|= PIPEMISC_DITHER_12_BPC
;
6932 /* Case prevented by pipe_config_set_bpp. */
6936 if (intel_crtc
->config
.dither
)
6937 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
6939 I915_WRITE(PIPEMISC(pipe
), val
);
6943 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
6944 intel_clock_t
*clock
,
6945 bool *has_reduced_clock
,
6946 intel_clock_t
*reduced_clock
)
6948 struct drm_device
*dev
= crtc
->dev
;
6949 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6950 struct intel_encoder
*intel_encoder
;
6952 const intel_limit_t
*limit
;
6953 bool ret
, is_lvds
= false;
6955 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
6956 switch (intel_encoder
->type
) {
6957 case INTEL_OUTPUT_LVDS
:
6963 refclk
= ironlake_get_refclk(crtc
);
6966 * Returns a set of divisors for the desired target clock with the given
6967 * refclk, or FALSE. The returned values represent the clock equation:
6968 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6970 limit
= intel_limit(crtc
, refclk
);
6971 ret
= dev_priv
->display
.find_dpll(limit
, crtc
,
6972 to_intel_crtc(crtc
)->config
.port_clock
,
6973 refclk
, NULL
, clock
);
6977 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
6979 * Ensure we match the reduced clock's P to the target clock.
6980 * If the clocks don't match, we can't switch the display clock
6981 * by using the FP0/FP1. In such case we will disable the LVDS
6982 * downclock feature.
6984 *has_reduced_clock
=
6985 dev_priv
->display
.find_dpll(limit
, crtc
,
6986 dev_priv
->lvds_downclock
,
6994 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
6997 * Account for spread spectrum to avoid
6998 * oversubscribing the link. Max center spread
6999 * is 2.5%; use 5% for safety's sake.
7001 u32 bps
= target_clock
* bpp
* 21 / 20;
7002 return DIV_ROUND_UP(bps
, link_bw
* 8);
7005 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
7007 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
7010 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
7012 intel_clock_t
*reduced_clock
, u32
*fp2
)
7014 struct drm_crtc
*crtc
= &intel_crtc
->base
;
7015 struct drm_device
*dev
= crtc
->dev
;
7016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7017 struct intel_encoder
*intel_encoder
;
7019 int factor
, num_connectors
= 0;
7020 bool is_lvds
= false, is_sdvo
= false;
7022 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
) {
7023 switch (intel_encoder
->type
) {
7024 case INTEL_OUTPUT_LVDS
:
7027 case INTEL_OUTPUT_SDVO
:
7028 case INTEL_OUTPUT_HDMI
:
7036 /* Enable autotuning of the PLL clock (if permissible) */
7039 if ((intel_panel_use_ssc(dev_priv
) &&
7040 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
7041 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
7043 } else if (intel_crtc
->config
.sdvo_tv_clock
)
7046 if (ironlake_needs_fb_cb_tune(&intel_crtc
->config
.dpll
, factor
))
7049 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
7055 dpll
|= DPLLB_MODE_LVDS
;
7057 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7059 dpll
|= (intel_crtc
->config
.pixel_multiplier
- 1)
7060 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
7063 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7064 if (intel_crtc
->config
.has_dp_encoder
)
7065 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7067 /* compute bitmask from p1 value */
7068 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7070 dpll
|= (1 << (intel_crtc
->config
.dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7072 switch (intel_crtc
->config
.dpll
.p2
) {
7074 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7077 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7080 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7083 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7087 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7088 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7090 dpll
|= PLL_REF_INPUT_DREFCLK
;
7092 return dpll
| DPLL_VCO_ENABLE
;
7095 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
7097 struct drm_framebuffer
*fb
)
7099 struct drm_device
*dev
= crtc
->dev
;
7100 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7101 int num_connectors
= 0;
7102 intel_clock_t clock
, reduced_clock
;
7103 u32 dpll
= 0, fp
= 0, fp2
= 0;
7104 bool ok
, has_reduced_clock
= false;
7105 bool is_lvds
= false;
7106 struct intel_encoder
*encoder
;
7107 struct intel_shared_dpll
*pll
;
7109 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
7110 switch (encoder
->type
) {
7111 case INTEL_OUTPUT_LVDS
:
7119 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
7120 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
7122 ok
= ironlake_compute_clocks(crtc
, &clock
,
7123 &has_reduced_clock
, &reduced_clock
);
7124 if (!ok
&& !intel_crtc
->config
.clock_set
) {
7125 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7128 /* Compat-code for transition, will disappear. */
7129 if (!intel_crtc
->config
.clock_set
) {
7130 intel_crtc
->config
.dpll
.n
= clock
.n
;
7131 intel_crtc
->config
.dpll
.m1
= clock
.m1
;
7132 intel_crtc
->config
.dpll
.m2
= clock
.m2
;
7133 intel_crtc
->config
.dpll
.p1
= clock
.p1
;
7134 intel_crtc
->config
.dpll
.p2
= clock
.p2
;
7137 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7138 if (intel_crtc
->config
.has_pch_encoder
) {
7139 fp
= i9xx_dpll_compute_fp(&intel_crtc
->config
.dpll
);
7140 if (has_reduced_clock
)
7141 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
7143 dpll
= ironlake_compute_dpll(intel_crtc
,
7144 &fp
, &reduced_clock
,
7145 has_reduced_clock
? &fp2
: NULL
);
7147 intel_crtc
->config
.dpll_hw_state
.dpll
= dpll
;
7148 intel_crtc
->config
.dpll_hw_state
.fp0
= fp
;
7149 if (has_reduced_clock
)
7150 intel_crtc
->config
.dpll_hw_state
.fp1
= fp2
;
7152 intel_crtc
->config
.dpll_hw_state
.fp1
= fp
;
7154 pll
= intel_get_shared_dpll(intel_crtc
);
7156 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7157 pipe_name(intel_crtc
->pipe
));
7161 intel_put_shared_dpll(intel_crtc
);
7163 if (is_lvds
&& has_reduced_clock
&& i915
.powersave
)
7164 intel_crtc
->lowfreq_avail
= true;
7166 intel_crtc
->lowfreq_avail
= false;
7171 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
7172 struct intel_link_m_n
*m_n
)
7174 struct drm_device
*dev
= crtc
->base
.dev
;
7175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7176 enum pipe pipe
= crtc
->pipe
;
7178 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
7179 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
7180 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
7182 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
7183 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
7184 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7187 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
7188 enum transcoder transcoder
,
7189 struct intel_link_m_n
*m_n
,
7190 struct intel_link_m_n
*m2_n2
)
7192 struct drm_device
*dev
= crtc
->base
.dev
;
7193 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7194 enum pipe pipe
= crtc
->pipe
;
7196 if (INTEL_INFO(dev
)->gen
>= 5) {
7197 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
7198 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
7199 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
7201 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
7202 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
7203 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7204 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7205 * gen < 8) and if DRRS is supported (to make sure the
7206 * registers are not unnecessarily read).
7208 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
7209 crtc
->config
.has_drrs
) {
7210 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
7211 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
7212 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
7214 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
7215 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
7216 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7219 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
7220 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
7221 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
7223 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
7224 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
7225 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
7229 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
7230 struct intel_crtc_config
*pipe_config
)
7232 if (crtc
->config
.has_pch_encoder
)
7233 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
7235 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7236 &pipe_config
->dp_m_n
,
7237 &pipe_config
->dp_m2_n2
);
7240 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
7241 struct intel_crtc_config
*pipe_config
)
7243 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
7244 &pipe_config
->fdi_m_n
, NULL
);
7247 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
7248 struct intel_crtc_config
*pipe_config
)
7250 struct drm_device
*dev
= crtc
->base
.dev
;
7251 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7254 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
7256 if (tmp
& PF_ENABLE
) {
7257 pipe_config
->pch_pfit
.enabled
= true;
7258 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
7259 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
7261 /* We currently do not free assignements of panel fitters on
7262 * ivb/hsw (since we don't use the higher upscaling modes which
7263 * differentiates them) so just WARN about this case for now. */
7265 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
7266 PF_PIPE_SEL_IVB(crtc
->pipe
));
7271 static void ironlake_get_plane_config(struct intel_crtc
*crtc
,
7272 struct intel_plane_config
*plane_config
)
7274 struct drm_device
*dev
= crtc
->base
.dev
;
7275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7276 u32 val
, base
, offset
;
7277 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
7278 int fourcc
, pixel_format
;
7281 crtc
->base
.primary
->fb
= kzalloc(sizeof(struct intel_framebuffer
), GFP_KERNEL
);
7282 if (!crtc
->base
.primary
->fb
) {
7283 DRM_DEBUG_KMS("failed to alloc fb\n");
7287 val
= I915_READ(DSPCNTR(plane
));
7289 if (INTEL_INFO(dev
)->gen
>= 4)
7290 if (val
& DISPPLANE_TILED
)
7291 plane_config
->tiled
= true;
7293 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
7294 fourcc
= intel_format_to_fourcc(pixel_format
);
7295 crtc
->base
.primary
->fb
->pixel_format
= fourcc
;
7296 crtc
->base
.primary
->fb
->bits_per_pixel
=
7297 drm_format_plane_cpp(fourcc
, 0) * 8;
7299 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
7300 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
7301 offset
= I915_READ(DSPOFFSET(plane
));
7303 if (plane_config
->tiled
)
7304 offset
= I915_READ(DSPTILEOFF(plane
));
7306 offset
= I915_READ(DSPLINOFF(plane
));
7308 plane_config
->base
= base
;
7310 val
= I915_READ(PIPESRC(pipe
));
7311 crtc
->base
.primary
->fb
->width
= ((val
>> 16) & 0xfff) + 1;
7312 crtc
->base
.primary
->fb
->height
= ((val
>> 0) & 0xfff) + 1;
7314 val
= I915_READ(DSPSTRIDE(pipe
));
7315 crtc
->base
.primary
->fb
->pitches
[0] = val
& 0xffffffc0;
7317 aligned_height
= intel_align_height(dev
, crtc
->base
.primary
->fb
->height
,
7318 plane_config
->tiled
);
7320 plane_config
->size
= PAGE_ALIGN(crtc
->base
.primary
->fb
->pitches
[0] *
7323 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7324 pipe
, plane
, crtc
->base
.primary
->fb
->width
,
7325 crtc
->base
.primary
->fb
->height
,
7326 crtc
->base
.primary
->fb
->bits_per_pixel
, base
,
7327 crtc
->base
.primary
->fb
->pitches
[0],
7328 plane_config
->size
);
7331 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
7332 struct intel_crtc_config
*pipe_config
)
7334 struct drm_device
*dev
= crtc
->base
.dev
;
7335 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7338 if (!intel_display_power_enabled(dev_priv
,
7339 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7342 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7343 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7345 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
7346 if (!(tmp
& PIPECONF_ENABLE
))
7349 switch (tmp
& PIPECONF_BPC_MASK
) {
7351 pipe_config
->pipe_bpp
= 18;
7354 pipe_config
->pipe_bpp
= 24;
7356 case PIPECONF_10BPC
:
7357 pipe_config
->pipe_bpp
= 30;
7359 case PIPECONF_12BPC
:
7360 pipe_config
->pipe_bpp
= 36;
7366 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
7367 pipe_config
->limited_color_range
= true;
7369 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
7370 struct intel_shared_dpll
*pll
;
7372 pipe_config
->has_pch_encoder
= true;
7374 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
7375 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7376 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7378 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7380 if (HAS_PCH_IBX(dev_priv
->dev
)) {
7381 pipe_config
->shared_dpll
=
7382 (enum intel_dpll_id
) crtc
->pipe
;
7384 tmp
= I915_READ(PCH_DPLL_SEL
);
7385 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
7386 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
7388 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
7391 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7393 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7394 &pipe_config
->dpll_hw_state
));
7396 tmp
= pipe_config
->dpll_hw_state
.dpll
;
7397 pipe_config
->pixel_multiplier
=
7398 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
7399 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
7401 ironlake_pch_clock_get(crtc
, pipe_config
);
7403 pipe_config
->pixel_multiplier
= 1;
7406 intel_get_pipe_timings(crtc
, pipe_config
);
7408 ironlake_get_pfit_config(crtc
, pipe_config
);
7413 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
7415 struct drm_device
*dev
= dev_priv
->dev
;
7416 struct intel_crtc
*crtc
;
7418 for_each_intel_crtc(dev
, crtc
)
7419 WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
7420 pipe_name(crtc
->pipe
));
7422 WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
7423 WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
7424 WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
7425 WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
7426 WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
7427 WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
7428 "CPU PWM1 enabled\n");
7429 if (IS_HASWELL(dev
))
7430 WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
7431 "CPU PWM2 enabled\n");
7432 WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
7433 "PCH PWM1 enabled\n");
7434 WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
7435 "Utility pin enabled\n");
7436 WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
7439 * In theory we can still leave IRQs enabled, as long as only the HPD
7440 * interrupts remain enabled. We used to check for that, but since it's
7441 * gen-specific and since we only disable LCPLL after we fully disable
7442 * the interrupts, the check below should be enough.
7444 WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
7447 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
7449 struct drm_device
*dev
= dev_priv
->dev
;
7451 if (IS_HASWELL(dev
))
7452 return I915_READ(D_COMP_HSW
);
7454 return I915_READ(D_COMP_BDW
);
7457 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
7459 struct drm_device
*dev
= dev_priv
->dev
;
7461 if (IS_HASWELL(dev
)) {
7462 mutex_lock(&dev_priv
->rps
.hw_lock
);
7463 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
7465 DRM_ERROR("Failed to write to D_COMP\n");
7466 mutex_unlock(&dev_priv
->rps
.hw_lock
);
7468 I915_WRITE(D_COMP_BDW
, val
);
7469 POSTING_READ(D_COMP_BDW
);
7474 * This function implements pieces of two sequences from BSpec:
7475 * - Sequence for display software to disable LCPLL
7476 * - Sequence for display software to allow package C8+
7477 * The steps implemented here are just the steps that actually touch the LCPLL
7478 * register. Callers should take care of disabling all the display engine
7479 * functions, doing the mode unset, fixing interrupts, etc.
7481 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
7482 bool switch_to_fclk
, bool allow_power_down
)
7486 assert_can_disable_lcpll(dev_priv
);
7488 val
= I915_READ(LCPLL_CTL
);
7490 if (switch_to_fclk
) {
7491 val
|= LCPLL_CD_SOURCE_FCLK
;
7492 I915_WRITE(LCPLL_CTL
, val
);
7494 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
7495 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
7496 DRM_ERROR("Switching to FCLK failed\n");
7498 val
= I915_READ(LCPLL_CTL
);
7501 val
|= LCPLL_PLL_DISABLE
;
7502 I915_WRITE(LCPLL_CTL
, val
);
7503 POSTING_READ(LCPLL_CTL
);
7505 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
7506 DRM_ERROR("LCPLL still locked\n");
7508 val
= hsw_read_dcomp(dev_priv
);
7509 val
|= D_COMP_COMP_DISABLE
;
7510 hsw_write_dcomp(dev_priv
, val
);
7513 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
7515 DRM_ERROR("D_COMP RCOMP still in progress\n");
7517 if (allow_power_down
) {
7518 val
= I915_READ(LCPLL_CTL
);
7519 val
|= LCPLL_POWER_DOWN_ALLOW
;
7520 I915_WRITE(LCPLL_CTL
, val
);
7521 POSTING_READ(LCPLL_CTL
);
7526 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7529 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
7532 unsigned long irqflags
;
7534 val
= I915_READ(LCPLL_CTL
);
7536 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
7537 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
7541 * Make sure we're not on PC8 state before disabling PC8, otherwise
7542 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7544 * The other problem is that hsw_restore_lcpll() is called as part of
7545 * the runtime PM resume sequence, so we can't just call
7546 * gen6_gt_force_wake_get() because that function calls
7547 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7548 * while we are on the resume sequence. So to solve this problem we have
7549 * to call special forcewake code that doesn't touch runtime PM and
7550 * doesn't enable the forcewake delayed work.
7552 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7553 if (dev_priv
->uncore
.forcewake_count
++ == 0)
7554 dev_priv
->uncore
.funcs
.force_wake_get(dev_priv
, FORCEWAKE_ALL
);
7555 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7557 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
7558 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
7559 I915_WRITE(LCPLL_CTL
, val
);
7560 POSTING_READ(LCPLL_CTL
);
7563 val
= hsw_read_dcomp(dev_priv
);
7564 val
|= D_COMP_COMP_FORCE
;
7565 val
&= ~D_COMP_COMP_DISABLE
;
7566 hsw_write_dcomp(dev_priv
, val
);
7568 val
= I915_READ(LCPLL_CTL
);
7569 val
&= ~LCPLL_PLL_DISABLE
;
7570 I915_WRITE(LCPLL_CTL
, val
);
7572 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
7573 DRM_ERROR("LCPLL not locked yet\n");
7575 if (val
& LCPLL_CD_SOURCE_FCLK
) {
7576 val
= I915_READ(LCPLL_CTL
);
7577 val
&= ~LCPLL_CD_SOURCE_FCLK
;
7578 I915_WRITE(LCPLL_CTL
, val
);
7580 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
7581 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
7582 DRM_ERROR("Switching back to LCPLL failed\n");
7585 /* See the big comment above. */
7586 spin_lock_irqsave(&dev_priv
->uncore
.lock
, irqflags
);
7587 if (--dev_priv
->uncore
.forcewake_count
== 0)
7588 dev_priv
->uncore
.funcs
.force_wake_put(dev_priv
, FORCEWAKE_ALL
);
7589 spin_unlock_irqrestore(&dev_priv
->uncore
.lock
, irqflags
);
7593 * Package states C8 and deeper are really deep PC states that can only be
7594 * reached when all the devices on the system allow it, so even if the graphics
7595 * device allows PC8+, it doesn't mean the system will actually get to these
7596 * states. Our driver only allows PC8+ when going into runtime PM.
7598 * The requirements for PC8+ are that all the outputs are disabled, the power
7599 * well is disabled and most interrupts are disabled, and these are also
7600 * requirements for runtime PM. When these conditions are met, we manually do
7601 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7602 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7605 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7606 * the state of some registers, so when we come back from PC8+ we need to
7607 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7608 * need to take care of the registers kept by RC6. Notice that this happens even
7609 * if we don't put the device in PCI D3 state (which is what currently happens
7610 * because of the runtime PM support).
7612 * For more, read "Display Sequences for Package C8" on the hardware
7615 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
7617 struct drm_device
*dev
= dev_priv
->dev
;
7620 DRM_DEBUG_KMS("Enabling package C8+\n");
7622 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7623 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7624 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
7625 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7628 lpt_disable_clkout_dp(dev
);
7629 hsw_disable_lcpll(dev_priv
, true, true);
7632 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
7634 struct drm_device
*dev
= dev_priv
->dev
;
7637 DRM_DEBUG_KMS("Disabling package C8+\n");
7639 hsw_restore_lcpll(dev_priv
);
7640 lpt_init_pch_refclk(dev
);
7642 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
7643 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
7644 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
7645 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
7648 intel_prepare_ddi(dev
);
7651 static void snb_modeset_global_resources(struct drm_device
*dev
)
7653 modeset_update_crtc_power_domains(dev
);
7656 static void haswell_modeset_global_resources(struct drm_device
*dev
)
7658 modeset_update_crtc_power_domains(dev
);
7661 static int haswell_crtc_mode_set(struct drm_crtc
*crtc
,
7663 struct drm_framebuffer
*fb
)
7665 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
7667 if (!intel_ddi_pll_select(intel_crtc
))
7670 intel_crtc
->lowfreq_avail
= false;
7675 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
7677 struct intel_crtc_config
*pipe_config
)
7679 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
7681 switch (pipe_config
->ddi_pll_sel
) {
7682 case PORT_CLK_SEL_WRPLL1
:
7683 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
7685 case PORT_CLK_SEL_WRPLL2
:
7686 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
7691 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
7692 struct intel_crtc_config
*pipe_config
)
7694 struct drm_device
*dev
= crtc
->base
.dev
;
7695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7696 struct intel_shared_dpll
*pll
;
7700 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
7702 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
7704 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
7706 if (pipe_config
->shared_dpll
>= 0) {
7707 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
7709 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
7710 &pipe_config
->dpll_hw_state
));
7714 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7715 * DDI E. So just check whether this pipe is wired to DDI E and whether
7716 * the PCH transcoder is on.
7718 if ((port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
7719 pipe_config
->has_pch_encoder
= true;
7721 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
7722 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
7723 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
7725 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
7729 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
7730 struct intel_crtc_config
*pipe_config
)
7732 struct drm_device
*dev
= crtc
->base
.dev
;
7733 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7734 enum intel_display_power_domain pfit_domain
;
7737 if (!intel_display_power_enabled(dev_priv
,
7738 POWER_DOMAIN_PIPE(crtc
->pipe
)))
7741 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
7742 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
7744 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
7745 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
7746 enum pipe trans_edp_pipe
;
7747 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
7749 WARN(1, "unknown pipe linked to edp transcoder\n");
7750 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
7751 case TRANS_DDI_EDP_INPUT_A_ON
:
7752 trans_edp_pipe
= PIPE_A
;
7754 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
7755 trans_edp_pipe
= PIPE_B
;
7757 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
7758 trans_edp_pipe
= PIPE_C
;
7762 if (trans_edp_pipe
== crtc
->pipe
)
7763 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
7766 if (!intel_display_power_enabled(dev_priv
,
7767 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
7770 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
7771 if (!(tmp
& PIPECONF_ENABLE
))
7774 haswell_get_ddi_port_state(crtc
, pipe_config
);
7776 intel_get_pipe_timings(crtc
, pipe_config
);
7778 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
7779 if (intel_display_power_enabled(dev_priv
, pfit_domain
))
7780 ironlake_get_pfit_config(crtc
, pipe_config
);
7782 if (IS_HASWELL(dev
))
7783 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
7784 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
7786 pipe_config
->pixel_multiplier
= 1;
7794 } hdmi_audio_clock
[] = {
7795 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175
},
7796 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200
}, /* default per bspec */
7797 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000
},
7798 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027
},
7799 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000
},
7800 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054
},
7801 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176
},
7802 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250
},
7803 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352
},
7804 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500
},
7807 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7808 static u32
audio_config_hdmi_pixel_clock(struct drm_display_mode
*mode
)
7812 for (i
= 0; i
< ARRAY_SIZE(hdmi_audio_clock
); i
++) {
7813 if (mode
->clock
== hdmi_audio_clock
[i
].clock
)
7817 if (i
== ARRAY_SIZE(hdmi_audio_clock
)) {
7818 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode
->clock
);
7822 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7823 hdmi_audio_clock
[i
].clock
,
7824 hdmi_audio_clock
[i
].config
);
7826 return hdmi_audio_clock
[i
].config
;
7829 static bool intel_eld_uptodate(struct drm_connector
*connector
,
7830 int reg_eldv
, uint32_t bits_eldv
,
7831 int reg_elda
, uint32_t bits_elda
,
7834 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7835 uint8_t *eld
= connector
->eld
;
7838 i
= I915_READ(reg_eldv
);
7847 i
= I915_READ(reg_elda
);
7849 I915_WRITE(reg_elda
, i
);
7851 for (i
= 0; i
< eld
[2]; i
++)
7852 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
7858 static void g4x_write_eld(struct drm_connector
*connector
,
7859 struct drm_crtc
*crtc
,
7860 struct drm_display_mode
*mode
)
7862 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7863 uint8_t *eld
= connector
->eld
;
7868 i
= I915_READ(G4X_AUD_VID_DID
);
7870 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
7871 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
7873 eldv
= G4X_ELDV_DEVCTG
;
7875 if (intel_eld_uptodate(connector
,
7876 G4X_AUD_CNTL_ST
, eldv
,
7877 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
7878 G4X_HDMIW_HDMIEDID
))
7881 i
= I915_READ(G4X_AUD_CNTL_ST
);
7882 i
&= ~(eldv
| G4X_ELD_ADDR
);
7883 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
7884 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7889 len
= min_t(uint8_t, eld
[2], len
);
7890 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7891 for (i
= 0; i
< len
; i
++)
7892 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
7894 i
= I915_READ(G4X_AUD_CNTL_ST
);
7896 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
7899 static void haswell_write_eld(struct drm_connector
*connector
,
7900 struct drm_crtc
*crtc
,
7901 struct drm_display_mode
*mode
)
7903 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7904 uint8_t *eld
= connector
->eld
;
7908 int pipe
= to_intel_crtc(crtc
)->pipe
;
7911 int hdmiw_hdmiedid
= HSW_AUD_EDID_DATA(pipe
);
7912 int aud_cntl_st
= HSW_AUD_DIP_ELD_CTRL(pipe
);
7913 int aud_config
= HSW_AUD_CFG(pipe
);
7914 int aud_cntrl_st2
= HSW_AUD_PIN_ELD_CP_VLD
;
7916 /* Audio output enable */
7917 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7918 tmp
= I915_READ(aud_cntrl_st2
);
7919 tmp
|= (AUDIO_OUTPUT_ENABLE_A
<< (pipe
* 4));
7920 I915_WRITE(aud_cntrl_st2
, tmp
);
7921 POSTING_READ(aud_cntrl_st2
);
7923 assert_pipe_disabled(dev_priv
, to_intel_crtc(crtc
)->pipe
);
7925 /* Set ELD valid state */
7926 tmp
= I915_READ(aud_cntrl_st2
);
7927 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp
);
7928 tmp
|= (AUDIO_ELD_VALID_A
<< (pipe
* 4));
7929 I915_WRITE(aud_cntrl_st2
, tmp
);
7930 tmp
= I915_READ(aud_cntrl_st2
);
7931 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp
);
7933 /* Enable HDMI mode */
7934 tmp
= I915_READ(aud_config
);
7935 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp
);
7936 /* clear N_programing_enable and N_value_index */
7937 tmp
&= ~(AUD_CONFIG_N_VALUE_INDEX
| AUD_CONFIG_N_PROG_ENABLE
);
7938 I915_WRITE(aud_config
, tmp
);
7940 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
7942 eldv
= AUDIO_ELD_VALID_A
<< (pipe
* 4);
7944 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
7945 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7946 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7947 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
7949 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
7952 if (intel_eld_uptodate(connector
,
7953 aud_cntrl_st2
, eldv
,
7954 aud_cntl_st
, IBX_ELD_ADDRESS
,
7958 i
= I915_READ(aud_cntrl_st2
);
7960 I915_WRITE(aud_cntrl_st2
, i
);
7965 i
= I915_READ(aud_cntl_st
);
7966 i
&= ~IBX_ELD_ADDRESS
;
7967 I915_WRITE(aud_cntl_st
, i
);
7968 i
= (i
>> 29) & DIP_PORT_SEL_MASK
; /* DIP_Port_Select, 0x1 = PortB */
7969 DRM_DEBUG_DRIVER("port num:%d\n", i
);
7971 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
7972 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
7973 for (i
= 0; i
< len
; i
++)
7974 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
7976 i
= I915_READ(aud_cntrl_st2
);
7978 I915_WRITE(aud_cntrl_st2
, i
);
7982 static void ironlake_write_eld(struct drm_connector
*connector
,
7983 struct drm_crtc
*crtc
,
7984 struct drm_display_mode
*mode
)
7986 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
7987 uint8_t *eld
= connector
->eld
;
7995 int pipe
= to_intel_crtc(crtc
)->pipe
;
7997 if (HAS_PCH_IBX(connector
->dev
)) {
7998 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID(pipe
);
7999 aud_config
= IBX_AUD_CFG(pipe
);
8000 aud_cntl_st
= IBX_AUD_CNTL_ST(pipe
);
8001 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
8002 } else if (IS_VALLEYVIEW(connector
->dev
)) {
8003 hdmiw_hdmiedid
= VLV_HDMIW_HDMIEDID(pipe
);
8004 aud_config
= VLV_AUD_CFG(pipe
);
8005 aud_cntl_st
= VLV_AUD_CNTL_ST(pipe
);
8006 aud_cntrl_st2
= VLV_AUD_CNTL_ST2
;
8008 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID(pipe
);
8009 aud_config
= CPT_AUD_CFG(pipe
);
8010 aud_cntl_st
= CPT_AUD_CNTL_ST(pipe
);
8011 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
8014 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe
));
8016 if (IS_VALLEYVIEW(connector
->dev
)) {
8017 struct intel_encoder
*intel_encoder
;
8018 struct intel_digital_port
*intel_dig_port
;
8020 intel_encoder
= intel_attached_encoder(connector
);
8021 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
8022 i
= intel_dig_port
->port
;
8024 i
= I915_READ(aud_cntl_st
);
8025 i
= (i
>> 29) & DIP_PORT_SEL_MASK
;
8026 /* DIP_Port_Select, 0x1 = PortB */
8030 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
8031 /* operate blindly on all ports */
8032 eldv
= IBX_ELD_VALIDB
;
8033 eldv
|= IBX_ELD_VALIDB
<< 4;
8034 eldv
|= IBX_ELD_VALIDB
<< 8;
8036 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i
));
8037 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
8040 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
8041 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
8042 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
8043 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
8045 I915_WRITE(aud_config
, audio_config_hdmi_pixel_clock(mode
));
8048 if (intel_eld_uptodate(connector
,
8049 aud_cntrl_st2
, eldv
,
8050 aud_cntl_st
, IBX_ELD_ADDRESS
,
8054 i
= I915_READ(aud_cntrl_st2
);
8056 I915_WRITE(aud_cntrl_st2
, i
);
8061 i
= I915_READ(aud_cntl_st
);
8062 i
&= ~IBX_ELD_ADDRESS
;
8063 I915_WRITE(aud_cntl_st
, i
);
8065 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
8066 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
8067 for (i
= 0; i
< len
; i
++)
8068 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
8070 i
= I915_READ(aud_cntrl_st2
);
8072 I915_WRITE(aud_cntrl_st2
, i
);
8075 void intel_write_eld(struct drm_encoder
*encoder
,
8076 struct drm_display_mode
*mode
)
8078 struct drm_crtc
*crtc
= encoder
->crtc
;
8079 struct drm_connector
*connector
;
8080 struct drm_device
*dev
= encoder
->dev
;
8081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8083 connector
= drm_select_eld(encoder
, mode
);
8087 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8090 connector
->encoder
->base
.id
,
8091 connector
->encoder
->name
);
8093 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
8095 if (dev_priv
->display
.write_eld
)
8096 dev_priv
->display
.write_eld(connector
, crtc
, mode
);
8099 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8101 struct drm_device
*dev
= crtc
->dev
;
8102 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8103 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8104 uint32_t cntl
= 0, size
= 0;
8107 unsigned int width
= intel_crtc
->cursor_width
;
8108 unsigned int height
= intel_crtc
->cursor_height
;
8109 unsigned int stride
= roundup_pow_of_two(width
) * 4;
8113 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8124 cntl
|= CURSOR_ENABLE
|
8125 CURSOR_GAMMA_ENABLE
|
8126 CURSOR_FORMAT_ARGB
|
8127 CURSOR_STRIDE(stride
);
8129 size
= (height
<< 12) | width
;
8132 if (intel_crtc
->cursor_cntl
!= 0 &&
8133 (intel_crtc
->cursor_base
!= base
||
8134 intel_crtc
->cursor_size
!= size
||
8135 intel_crtc
->cursor_cntl
!= cntl
)) {
8136 /* On these chipsets we can only modify the base/size/stride
8137 * whilst the cursor is disabled.
8139 I915_WRITE(_CURACNTR
, 0);
8140 POSTING_READ(_CURACNTR
);
8141 intel_crtc
->cursor_cntl
= 0;
8144 if (intel_crtc
->cursor_base
!= base
)
8145 I915_WRITE(_CURABASE
, base
);
8147 if (intel_crtc
->cursor_size
!= size
) {
8148 I915_WRITE(CURSIZE
, size
);
8149 intel_crtc
->cursor_size
= size
;
8152 if (intel_crtc
->cursor_cntl
!= cntl
) {
8153 I915_WRITE(_CURACNTR
, cntl
);
8154 POSTING_READ(_CURACNTR
);
8155 intel_crtc
->cursor_cntl
= cntl
;
8159 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
8161 struct drm_device
*dev
= crtc
->dev
;
8162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8163 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8164 int pipe
= intel_crtc
->pipe
;
8169 cntl
= MCURSOR_GAMMA_ENABLE
;
8170 switch (intel_crtc
->cursor_width
) {
8172 cntl
|= CURSOR_MODE_64_ARGB_AX
;
8175 cntl
|= CURSOR_MODE_128_ARGB_AX
;
8178 cntl
|= CURSOR_MODE_256_ARGB_AX
;
8184 cntl
|= pipe
<< 28; /* Connect to correct pipe */
8186 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
8187 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
8189 if (intel_crtc
->cursor_cntl
!= cntl
) {
8190 I915_WRITE(CURCNTR(pipe
), cntl
);
8191 POSTING_READ(CURCNTR(pipe
));
8192 intel_crtc
->cursor_cntl
= cntl
;
8195 /* and commit changes on next vblank */
8196 I915_WRITE(CURBASE(pipe
), base
);
8197 POSTING_READ(CURBASE(pipe
));
8200 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8201 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
8204 struct drm_device
*dev
= crtc
->dev
;
8205 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8206 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8207 int pipe
= intel_crtc
->pipe
;
8208 int x
= crtc
->cursor_x
;
8209 int y
= crtc
->cursor_y
;
8210 u32 base
= 0, pos
= 0;
8213 base
= intel_crtc
->cursor_addr
;
8215 if (x
>= intel_crtc
->config
.pipe_src_w
)
8218 if (y
>= intel_crtc
->config
.pipe_src_h
)
8222 if (x
+ intel_crtc
->cursor_width
<= 0)
8225 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
8228 pos
|= x
<< CURSOR_X_SHIFT
;
8231 if (y
+ intel_crtc
->cursor_height
<= 0)
8234 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
8237 pos
|= y
<< CURSOR_Y_SHIFT
;
8239 if (base
== 0 && intel_crtc
->cursor_base
== 0)
8242 I915_WRITE(CURPOS(pipe
), pos
);
8244 if (IS_845G(dev
) || IS_I865G(dev
))
8245 i845_update_cursor(crtc
, base
);
8247 i9xx_update_cursor(crtc
, base
);
8248 intel_crtc
->cursor_base
= base
;
8251 static bool cursor_size_ok(struct drm_device
*dev
,
8252 uint32_t width
, uint32_t height
)
8254 if (width
== 0 || height
== 0)
8258 * 845g/865g are special in that they are only limited by
8259 * the width of their cursors, the height is arbitrary up to
8260 * the precision of the register. Everything else requires
8261 * square cursors, limited to a few power-of-two sizes.
8263 if (IS_845G(dev
) || IS_I865G(dev
)) {
8264 if ((width
& 63) != 0)
8267 if (width
> (IS_845G(dev
) ? 64 : 512))
8273 switch (width
| height
) {
8289 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8291 * Note that the object's reference will be consumed if the update fails. If
8292 * the update succeeds, the reference of the old object (if any) will be
8295 static int intel_crtc_cursor_set_obj(struct drm_crtc
*crtc
,
8296 struct drm_i915_gem_object
*obj
,
8297 uint32_t width
, uint32_t height
)
8299 struct drm_device
*dev
= crtc
->dev
;
8300 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8301 enum pipe pipe
= intel_crtc
->pipe
;
8302 unsigned old_width
, stride
;
8306 /* if we want to turn off the cursor ignore width and height */
8308 DRM_DEBUG_KMS("cursor off\n");
8310 mutex_lock(&dev
->struct_mutex
);
8314 /* Check for which cursor types we support */
8315 if (!cursor_size_ok(dev
, width
, height
)) {
8316 DRM_DEBUG("Cursor dimension not supported\n");
8320 stride
= roundup_pow_of_two(width
) * 4;
8321 if (obj
->base
.size
< stride
* height
) {
8322 DRM_DEBUG_KMS("buffer is too small\n");
8327 /* we only need to pin inside GTT if cursor is non-phy */
8328 mutex_lock(&dev
->struct_mutex
);
8329 if (!INTEL_INFO(dev
)->cursor_needs_physical
) {
8332 if (obj
->tiling_mode
) {
8333 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8338 /* Note that the w/a also requires 2 PTE of padding following
8339 * the bo. We currently fill all unused PTE with the shadow
8340 * page and so we should always have valid PTE following the
8341 * cursor preventing the VT-d warning.
8344 if (need_vtd_wa(dev
))
8345 alignment
= 64*1024;
8347 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, NULL
);
8349 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8353 ret
= i915_gem_object_put_fence(obj
);
8355 DRM_DEBUG_KMS("failed to release fence for cursor");
8359 addr
= i915_gem_obj_ggtt_offset(obj
);
8361 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
8362 ret
= i915_gem_object_attach_phys(obj
, align
);
8364 DRM_DEBUG_KMS("failed to attach phys object\n");
8367 addr
= obj
->phys_handle
->busaddr
;
8371 if (intel_crtc
->cursor_bo
) {
8372 if (!INTEL_INFO(dev
)->cursor_needs_physical
)
8373 i915_gem_object_unpin_from_display_plane(intel_crtc
->cursor_bo
);
8376 i915_gem_track_fb(intel_crtc
->cursor_bo
, obj
,
8377 INTEL_FRONTBUFFER_CURSOR(pipe
));
8378 mutex_unlock(&dev
->struct_mutex
);
8380 old_width
= intel_crtc
->cursor_width
;
8382 intel_crtc
->cursor_addr
= addr
;
8383 intel_crtc
->cursor_bo
= obj
;
8384 intel_crtc
->cursor_width
= width
;
8385 intel_crtc
->cursor_height
= height
;
8387 if (intel_crtc
->active
) {
8388 if (old_width
!= width
)
8389 intel_update_watermarks(crtc
);
8390 intel_crtc_update_cursor(crtc
, intel_crtc
->cursor_bo
!= NULL
);
8393 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_CURSOR(pipe
));
8397 i915_gem_object_unpin_from_display_plane(obj
);
8399 mutex_unlock(&dev
->struct_mutex
);
8401 drm_gem_object_unreference_unlocked(&obj
->base
);
8405 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
8406 u16
*blue
, uint32_t start
, uint32_t size
)
8408 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
8409 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8411 for (i
= start
; i
< end
; i
++) {
8412 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
8413 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
8414 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
8417 intel_crtc_load_lut(crtc
);
8420 /* VESA 640x480x72Hz mode to set on the pipe */
8421 static struct drm_display_mode load_detect_mode
= {
8422 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
8423 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
8426 struct drm_framebuffer
*
8427 __intel_framebuffer_create(struct drm_device
*dev
,
8428 struct drm_mode_fb_cmd2
*mode_cmd
,
8429 struct drm_i915_gem_object
*obj
)
8431 struct intel_framebuffer
*intel_fb
;
8434 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8436 drm_gem_object_unreference_unlocked(&obj
->base
);
8437 return ERR_PTR(-ENOMEM
);
8440 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
8444 return &intel_fb
->base
;
8446 drm_gem_object_unreference_unlocked(&obj
->base
);
8449 return ERR_PTR(ret
);
8452 static struct drm_framebuffer
*
8453 intel_framebuffer_create(struct drm_device
*dev
,
8454 struct drm_mode_fb_cmd2
*mode_cmd
,
8455 struct drm_i915_gem_object
*obj
)
8457 struct drm_framebuffer
*fb
;
8460 ret
= i915_mutex_lock_interruptible(dev
);
8462 return ERR_PTR(ret
);
8463 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
8464 mutex_unlock(&dev
->struct_mutex
);
8470 intel_framebuffer_pitch_for_width(int width
, int bpp
)
8472 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
8473 return ALIGN(pitch
, 64);
8477 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
8479 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
8480 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
8483 static struct drm_framebuffer
*
8484 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
8485 struct drm_display_mode
*mode
,
8488 struct drm_i915_gem_object
*obj
;
8489 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
8491 obj
= i915_gem_alloc_object(dev
,
8492 intel_framebuffer_size_for_mode(mode
, bpp
));
8494 return ERR_PTR(-ENOMEM
);
8496 mode_cmd
.width
= mode
->hdisplay
;
8497 mode_cmd
.height
= mode
->vdisplay
;
8498 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
8500 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
8502 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
8505 static struct drm_framebuffer
*
8506 mode_fits_in_fbdev(struct drm_device
*dev
,
8507 struct drm_display_mode
*mode
)
8509 #ifdef CONFIG_DRM_I915_FBDEV
8510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8511 struct drm_i915_gem_object
*obj
;
8512 struct drm_framebuffer
*fb
;
8514 if (!dev_priv
->fbdev
)
8517 if (!dev_priv
->fbdev
->fb
)
8520 obj
= dev_priv
->fbdev
->fb
->obj
;
8523 fb
= &dev_priv
->fbdev
->fb
->base
;
8524 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
8525 fb
->bits_per_pixel
))
8528 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
8537 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
8538 struct drm_display_mode
*mode
,
8539 struct intel_load_detect_pipe
*old
,
8540 struct drm_modeset_acquire_ctx
*ctx
)
8542 struct intel_crtc
*intel_crtc
;
8543 struct intel_encoder
*intel_encoder
=
8544 intel_attached_encoder(connector
);
8545 struct drm_crtc
*possible_crtc
;
8546 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8547 struct drm_crtc
*crtc
= NULL
;
8548 struct drm_device
*dev
= encoder
->dev
;
8549 struct drm_framebuffer
*fb
;
8550 struct drm_mode_config
*config
= &dev
->mode_config
;
8553 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8554 connector
->base
.id
, connector
->name
,
8555 encoder
->base
.id
, encoder
->name
);
8558 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
8563 * Algorithm gets a little messy:
8565 * - if the connector already has an assigned crtc, use it (but make
8566 * sure it's on first)
8568 * - try to find the first unused crtc that can drive this connector,
8569 * and use that if we find one
8572 /* See if we already have a CRTC for this connector */
8573 if (encoder
->crtc
) {
8574 crtc
= encoder
->crtc
;
8576 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8580 old
->dpms_mode
= connector
->dpms
;
8581 old
->load_detect_temp
= false;
8583 /* Make sure the crtc and connector are running */
8584 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
8585 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
8590 /* Find an unused one (if possible) */
8591 for_each_crtc(dev
, possible_crtc
) {
8593 if (!(encoder
->possible_crtcs
& (1 << i
)))
8595 if (possible_crtc
->enabled
)
8597 /* This can occur when applying the pipe A quirk on resume. */
8598 if (to_intel_crtc(possible_crtc
)->new_enabled
)
8601 crtc
= possible_crtc
;
8606 * If we didn't find an unused CRTC, don't use any.
8609 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8613 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
8616 intel_encoder
->new_crtc
= to_intel_crtc(crtc
);
8617 to_intel_connector(connector
)->new_encoder
= intel_encoder
;
8619 intel_crtc
= to_intel_crtc(crtc
);
8620 intel_crtc
->new_enabled
= true;
8621 intel_crtc
->new_config
= &intel_crtc
->config
;
8622 old
->dpms_mode
= connector
->dpms
;
8623 old
->load_detect_temp
= true;
8624 old
->release_fb
= NULL
;
8627 mode
= &load_detect_mode
;
8629 /* We need a framebuffer large enough to accommodate all accesses
8630 * that the plane may generate whilst we perform load detection.
8631 * We can not rely on the fbcon either being present (we get called
8632 * during its initialisation to detect all boot displays, or it may
8633 * not even exist) or that it is large enough to satisfy the
8636 fb
= mode_fits_in_fbdev(dev
, mode
);
8638 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8639 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
8640 old
->release_fb
= fb
;
8642 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8644 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8648 if (intel_set_mode(crtc
, mode
, 0, 0, fb
)) {
8649 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8650 if (old
->release_fb
)
8651 old
->release_fb
->funcs
->destroy(old
->release_fb
);
8655 /* let the connector get through one full cycle before testing */
8656 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
8660 intel_crtc
->new_enabled
= crtc
->enabled
;
8661 if (intel_crtc
->new_enabled
)
8662 intel_crtc
->new_config
= &intel_crtc
->config
;
8664 intel_crtc
->new_config
= NULL
;
8666 if (ret
== -EDEADLK
) {
8667 drm_modeset_backoff(ctx
);
8674 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
8675 struct intel_load_detect_pipe
*old
)
8677 struct intel_encoder
*intel_encoder
=
8678 intel_attached_encoder(connector
);
8679 struct drm_encoder
*encoder
= &intel_encoder
->base
;
8680 struct drm_crtc
*crtc
= encoder
->crtc
;
8681 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8683 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8684 connector
->base
.id
, connector
->name
,
8685 encoder
->base
.id
, encoder
->name
);
8687 if (old
->load_detect_temp
) {
8688 to_intel_connector(connector
)->new_encoder
= NULL
;
8689 intel_encoder
->new_crtc
= NULL
;
8690 intel_crtc
->new_enabled
= false;
8691 intel_crtc
->new_config
= NULL
;
8692 intel_set_mode(crtc
, NULL
, 0, 0, NULL
);
8694 if (old
->release_fb
) {
8695 drm_framebuffer_unregister_private(old
->release_fb
);
8696 drm_framebuffer_unreference(old
->release_fb
);
8702 /* Switch crtc and encoder back off if necessary */
8703 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
8704 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
8707 static int i9xx_pll_refclk(struct drm_device
*dev
,
8708 const struct intel_crtc_config
*pipe_config
)
8710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8711 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8713 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
8714 return dev_priv
->vbt
.lvds_ssc_freq
;
8715 else if (HAS_PCH_SPLIT(dev
))
8717 else if (!IS_GEN2(dev
))
8723 /* Returns the clock of the currently programmed mode of the given pipe. */
8724 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
8725 struct intel_crtc_config
*pipe_config
)
8727 struct drm_device
*dev
= crtc
->base
.dev
;
8728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8729 int pipe
= pipe_config
->cpu_transcoder
;
8730 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
8732 intel_clock_t clock
;
8733 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
8735 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
8736 fp
= pipe_config
->dpll_hw_state
.fp0
;
8738 fp
= pipe_config
->dpll_hw_state
.fp1
;
8740 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
8741 if (IS_PINEVIEW(dev
)) {
8742 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
8743 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8745 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
8746 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
8749 if (!IS_GEN2(dev
)) {
8750 if (IS_PINEVIEW(dev
))
8751 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
8752 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
8754 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
8755 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8757 switch (dpll
& DPLL_MODE_MASK
) {
8758 case DPLLB_MODE_DAC_SERIAL
:
8759 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
8762 case DPLLB_MODE_LVDS
:
8763 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
8767 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8768 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
8772 if (IS_PINEVIEW(dev
))
8773 pineview_clock(refclk
, &clock
);
8775 i9xx_clock(refclk
, &clock
);
8777 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
8778 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
8781 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
8782 DPLL_FPA01_P1_POST_DIV_SHIFT
);
8784 if (lvds
& LVDS_CLKB_POWER_UP
)
8789 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
8792 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
8793 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
8795 if (dpll
& PLL_P2_DIVIDE_BY_4
)
8801 i9xx_clock(refclk
, &clock
);
8805 * This value includes pixel_multiplier. We will use
8806 * port_clock to compute adjusted_mode.crtc_clock in the
8807 * encoder's get_config() function.
8809 pipe_config
->port_clock
= clock
.dot
;
8812 int intel_dotclock_calculate(int link_freq
,
8813 const struct intel_link_m_n
*m_n
)
8816 * The calculation for the data clock is:
8817 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8818 * But we want to avoid losing precison if possible, so:
8819 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8821 * and the link clock is simpler:
8822 * link_clock = (m * link_clock) / n
8828 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
8831 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
8832 struct intel_crtc_config
*pipe_config
)
8834 struct drm_device
*dev
= crtc
->base
.dev
;
8836 /* read out port_clock from the DPLL */
8837 i9xx_crtc_clock_get(crtc
, pipe_config
);
8840 * This value does not include pixel_multiplier.
8841 * We will check that port_clock and adjusted_mode.crtc_clock
8842 * agree once we know their relationship in the encoder's
8843 * get_config() function.
8845 pipe_config
->adjusted_mode
.crtc_clock
=
8846 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
8847 &pipe_config
->fdi_m_n
);
8850 /** Returns the currently programmed mode of the given pipe. */
8851 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
8852 struct drm_crtc
*crtc
)
8854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8855 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8856 enum transcoder cpu_transcoder
= intel_crtc
->config
.cpu_transcoder
;
8857 struct drm_display_mode
*mode
;
8858 struct intel_crtc_config pipe_config
;
8859 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
8860 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
8861 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
8862 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
8863 enum pipe pipe
= intel_crtc
->pipe
;
8865 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
8870 * Construct a pipe_config sufficient for getting the clock info
8871 * back out of crtc_clock_get.
8873 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8874 * to use a real value here instead.
8876 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
8877 pipe_config
.pixel_multiplier
= 1;
8878 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
8879 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
8880 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
8881 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
8883 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
8884 mode
->hdisplay
= (htot
& 0xffff) + 1;
8885 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
8886 mode
->hsync_start
= (hsync
& 0xffff) + 1;
8887 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
8888 mode
->vdisplay
= (vtot
& 0xffff) + 1;
8889 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
8890 mode
->vsync_start
= (vsync
& 0xffff) + 1;
8891 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
8893 drm_mode_set_name(mode
);
8898 static void intel_increase_pllclock(struct drm_device
*dev
,
8901 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8902 int dpll_reg
= DPLL(pipe
);
8905 if (!HAS_GMCH_DISPLAY(dev
))
8908 if (!dev_priv
->lvds_downclock_avail
)
8911 dpll
= I915_READ(dpll_reg
);
8912 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
8913 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8915 assert_panel_unlocked(dev_priv
, pipe
);
8917 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
8918 I915_WRITE(dpll_reg
, dpll
);
8919 intel_wait_for_vblank(dev
, pipe
);
8921 dpll
= I915_READ(dpll_reg
);
8922 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
8923 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8927 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
8929 struct drm_device
*dev
= crtc
->dev
;
8930 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8931 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8933 if (!HAS_GMCH_DISPLAY(dev
))
8936 if (!dev_priv
->lvds_downclock_avail
)
8940 * Since this is called by a timer, we should never get here in
8943 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
8944 int pipe
= intel_crtc
->pipe
;
8945 int dpll_reg
= DPLL(pipe
);
8948 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8950 assert_panel_unlocked(dev_priv
, pipe
);
8952 dpll
= I915_READ(dpll_reg
);
8953 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
8954 I915_WRITE(dpll_reg
, dpll
);
8955 intel_wait_for_vblank(dev
, pipe
);
8956 dpll
= I915_READ(dpll_reg
);
8957 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
8958 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8963 void intel_mark_busy(struct drm_device
*dev
)
8965 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8967 if (dev_priv
->mm
.busy
)
8970 intel_runtime_pm_get(dev_priv
);
8971 i915_update_gfx_val(dev_priv
);
8972 dev_priv
->mm
.busy
= true;
8975 void intel_mark_idle(struct drm_device
*dev
)
8977 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8978 struct drm_crtc
*crtc
;
8980 if (!dev_priv
->mm
.busy
)
8983 dev_priv
->mm
.busy
= false;
8985 if (!i915
.powersave
)
8988 for_each_crtc(dev
, crtc
) {
8989 if (!crtc
->primary
->fb
)
8992 intel_decrease_pllclock(crtc
);
8995 if (INTEL_INFO(dev
)->gen
>= 6)
8996 gen6_rps_idle(dev
->dev_private
);
8999 intel_runtime_pm_put(dev_priv
);
9004 * intel_mark_fb_busy - mark given planes as busy
9006 * @frontbuffer_bits: bits for the affected planes
9007 * @ring: optional ring for asynchronous commands
9009 * This function gets called every time the screen contents change. It can be
9010 * used to keep e.g. the update rate at the nominal refresh rate with DRRS.
9012 static void intel_mark_fb_busy(struct drm_device
*dev
,
9013 unsigned frontbuffer_bits
,
9014 struct intel_engine_cs
*ring
)
9016 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9019 if (!i915
.powersave
)
9022 for_each_pipe(dev_priv
, pipe
) {
9023 if (!(frontbuffer_bits
& INTEL_FRONTBUFFER_ALL_MASK(pipe
)))
9026 intel_increase_pllclock(dev
, pipe
);
9027 if (ring
&& intel_fbc_enabled(dev
))
9028 ring
->fbc_dirty
= true;
9033 * intel_fb_obj_invalidate - invalidate frontbuffer object
9034 * @obj: GEM object to invalidate
9035 * @ring: set for asynchronous rendering
9037 * This function gets called every time rendering on the given object starts and
9038 * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must
9039 * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed
9040 * until the rendering completes or a flip on this frontbuffer plane is
9043 void intel_fb_obj_invalidate(struct drm_i915_gem_object
*obj
,
9044 struct intel_engine_cs
*ring
)
9046 struct drm_device
*dev
= obj
->base
.dev
;
9047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9049 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9051 if (!obj
->frontbuffer_bits
)
9055 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9056 dev_priv
->fb_tracking
.busy_bits
9057 |= obj
->frontbuffer_bits
;
9058 dev_priv
->fb_tracking
.flip_bits
9059 &= ~obj
->frontbuffer_bits
;
9060 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9063 intel_mark_fb_busy(dev
, obj
->frontbuffer_bits
, ring
);
9065 intel_edp_psr_invalidate(dev
, obj
->frontbuffer_bits
);
9069 * intel_frontbuffer_flush - flush frontbuffer
9071 * @frontbuffer_bits: frontbuffer plane tracking bits
9073 * This function gets called every time rendering on the given planes has
9074 * completed and frontbuffer caching can be started again. Flushes will get
9075 * delayed if they're blocked by some oustanding asynchronous rendering.
9077 * Can be called without any locks held.
9079 void intel_frontbuffer_flush(struct drm_device
*dev
,
9080 unsigned frontbuffer_bits
)
9082 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9084 /* Delay flushing when rings are still busy.*/
9085 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9086 frontbuffer_bits
&= ~dev_priv
->fb_tracking
.busy_bits
;
9087 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9089 intel_mark_fb_busy(dev
, frontbuffer_bits
, NULL
);
9091 intel_edp_psr_flush(dev
, frontbuffer_bits
);
9094 gen8_fbc_sw_flush(dev
, FBC_REND_CACHE_CLEAN
);
9098 * intel_fb_obj_flush - flush frontbuffer object
9099 * @obj: GEM object to flush
9100 * @retire: set when retiring asynchronous rendering
9102 * This function gets called every time rendering on the given object has
9103 * completed and frontbuffer caching can be started again. If @retire is true
9104 * then any delayed flushes will be unblocked.
9106 void intel_fb_obj_flush(struct drm_i915_gem_object
*obj
,
9109 struct drm_device
*dev
= obj
->base
.dev
;
9110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9111 unsigned frontbuffer_bits
;
9113 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
9115 if (!obj
->frontbuffer_bits
)
9118 frontbuffer_bits
= obj
->frontbuffer_bits
;
9121 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9122 /* Filter out new bits since rendering started. */
9123 frontbuffer_bits
&= dev_priv
->fb_tracking
.busy_bits
;
9125 dev_priv
->fb_tracking
.busy_bits
&= ~frontbuffer_bits
;
9126 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9129 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9133 * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip
9135 * @frontbuffer_bits: frontbuffer plane tracking bits
9137 * This function gets called after scheduling a flip on @obj. The actual
9138 * frontbuffer flushing will be delayed until completion is signalled with
9139 * intel_frontbuffer_flip_complete. If an invalidate happens in between this
9140 * flush will be cancelled.
9142 * Can be called without any locks held.
9144 void intel_frontbuffer_flip_prepare(struct drm_device
*dev
,
9145 unsigned frontbuffer_bits
)
9147 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9149 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9150 dev_priv
->fb_tracking
.flip_bits
9151 |= frontbuffer_bits
;
9152 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9156 * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush
9158 * @frontbuffer_bits: frontbuffer plane tracking bits
9160 * This function gets called after the flip has been latched and will complete
9161 * on the next vblank. It will execute the fush if it hasn't been cancalled yet.
9163 * Can be called without any locks held.
9165 void intel_frontbuffer_flip_complete(struct drm_device
*dev
,
9166 unsigned frontbuffer_bits
)
9168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9170 mutex_lock(&dev_priv
->fb_tracking
.lock
);
9171 /* Mask any cancelled flips. */
9172 frontbuffer_bits
&= dev_priv
->fb_tracking
.flip_bits
;
9173 dev_priv
->fb_tracking
.flip_bits
&= ~frontbuffer_bits
;
9174 mutex_unlock(&dev_priv
->fb_tracking
.lock
);
9176 intel_frontbuffer_flush(dev
, frontbuffer_bits
);
9179 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
9181 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9182 struct drm_device
*dev
= crtc
->dev
;
9183 struct intel_unpin_work
*work
;
9184 unsigned long flags
;
9186 spin_lock_irqsave(&dev
->event_lock
, flags
);
9187 work
= intel_crtc
->unpin_work
;
9188 intel_crtc
->unpin_work
= NULL
;
9189 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9192 cancel_work_sync(&work
->work
);
9196 drm_crtc_cleanup(crtc
);
9201 static void intel_unpin_work_fn(struct work_struct
*__work
)
9203 struct intel_unpin_work
*work
=
9204 container_of(__work
, struct intel_unpin_work
, work
);
9205 struct drm_device
*dev
= work
->crtc
->dev
;
9206 enum pipe pipe
= to_intel_crtc(work
->crtc
)->pipe
;
9208 mutex_lock(&dev
->struct_mutex
);
9209 intel_unpin_fb_obj(work
->old_fb_obj
);
9210 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
9211 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9213 intel_update_fbc(dev
);
9214 mutex_unlock(&dev
->struct_mutex
);
9216 intel_frontbuffer_flip_complete(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9218 BUG_ON(atomic_read(&to_intel_crtc(work
->crtc
)->unpin_work_count
) == 0);
9219 atomic_dec(&to_intel_crtc(work
->crtc
)->unpin_work_count
);
9224 static void do_intel_finish_page_flip(struct drm_device
*dev
,
9225 struct drm_crtc
*crtc
)
9227 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9228 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9229 struct intel_unpin_work
*work
;
9230 unsigned long flags
;
9232 /* Ignore early vblank irqs */
9233 if (intel_crtc
== NULL
)
9236 spin_lock_irqsave(&dev
->event_lock
, flags
);
9237 work
= intel_crtc
->unpin_work
;
9239 /* Ensure we don't miss a work->pending update ... */
9242 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
9243 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9247 /* and that the unpin work is consistent wrt ->pending. */
9250 intel_crtc
->unpin_work
= NULL
;
9253 drm_send_vblank_event(dev
, intel_crtc
->pipe
, work
->event
);
9255 drm_crtc_vblank_put(crtc
);
9257 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9259 wake_up_all(&dev_priv
->pending_flip_queue
);
9261 queue_work(dev_priv
->wq
, &work
->work
);
9263 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
9266 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
9268 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9269 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
9271 do_intel_finish_page_flip(dev
, crtc
);
9274 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
9276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9277 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
9279 do_intel_finish_page_flip(dev
, crtc
);
9282 /* Is 'a' after or equal to 'b'? */
9283 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
9285 return !((a
- b
) & 0x80000000);
9288 static bool page_flip_finished(struct intel_crtc
*crtc
)
9290 struct drm_device
*dev
= crtc
->base
.dev
;
9291 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9294 * The relevant registers doen't exist on pre-ctg.
9295 * As the flip done interrupt doesn't trigger for mmio
9296 * flips on gmch platforms, a flip count check isn't
9297 * really needed there. But since ctg has the registers,
9298 * include it in the check anyway.
9300 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
9304 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9305 * used the same base address. In that case the mmio flip might
9306 * have completed, but the CS hasn't even executed the flip yet.
9308 * A flip count check isn't enough as the CS might have updated
9309 * the base address just after start of vblank, but before we
9310 * managed to process the interrupt. This means we'd complete the
9313 * Combining both checks should get us a good enough result. It may
9314 * still happen that the CS flip has been executed, but has not
9315 * yet actually completed. But in case the base address is the same
9316 * anyway, we don't really care.
9318 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
9319 crtc
->unpin_work
->gtt_offset
&&
9320 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc
->pipe
)),
9321 crtc
->unpin_work
->flip_count
);
9324 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
9326 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9327 struct intel_crtc
*intel_crtc
=
9328 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
9329 unsigned long flags
;
9331 /* NB: An MMIO update of the plane base pointer will also
9332 * generate a page-flip completion irq, i.e. every modeset
9333 * is also accompanied by a spurious intel_prepare_page_flip().
9335 spin_lock_irqsave(&dev
->event_lock
, flags
);
9336 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
9337 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
9338 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9341 static inline void intel_mark_page_flip_active(struct intel_crtc
*intel_crtc
)
9343 /* Ensure that the work item is consistent when activating it ... */
9345 atomic_set(&intel_crtc
->unpin_work
->pending
, INTEL_FLIP_PENDING
);
9346 /* and that it is marked active as soon as the irq could fire. */
9350 static int intel_gen2_queue_flip(struct drm_device
*dev
,
9351 struct drm_crtc
*crtc
,
9352 struct drm_framebuffer
*fb
,
9353 struct drm_i915_gem_object
*obj
,
9354 struct intel_engine_cs
*ring
,
9357 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9361 ret
= intel_ring_begin(ring
, 6);
9365 /* Can't queue multiple flips, so wait for the previous
9366 * one to finish before executing the next.
9368 if (intel_crtc
->plane
)
9369 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9371 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9372 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9373 intel_ring_emit(ring
, MI_NOOP
);
9374 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9375 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9376 intel_ring_emit(ring
, fb
->pitches
[0]);
9377 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9378 intel_ring_emit(ring
, 0); /* aux display base address, unused */
9380 intel_mark_page_flip_active(intel_crtc
);
9381 __intel_ring_advance(ring
);
9385 static int intel_gen3_queue_flip(struct drm_device
*dev
,
9386 struct drm_crtc
*crtc
,
9387 struct drm_framebuffer
*fb
,
9388 struct drm_i915_gem_object
*obj
,
9389 struct intel_engine_cs
*ring
,
9392 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9396 ret
= intel_ring_begin(ring
, 6);
9400 if (intel_crtc
->plane
)
9401 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
9403 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
9404 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
9405 intel_ring_emit(ring
, MI_NOOP
);
9406 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
9407 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9408 intel_ring_emit(ring
, fb
->pitches
[0]);
9409 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9410 intel_ring_emit(ring
, MI_NOOP
);
9412 intel_mark_page_flip_active(intel_crtc
);
9413 __intel_ring_advance(ring
);
9417 static int intel_gen4_queue_flip(struct drm_device
*dev
,
9418 struct drm_crtc
*crtc
,
9419 struct drm_framebuffer
*fb
,
9420 struct drm_i915_gem_object
*obj
,
9421 struct intel_engine_cs
*ring
,
9424 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9425 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9426 uint32_t pf
, pipesrc
;
9429 ret
= intel_ring_begin(ring
, 4);
9433 /* i965+ uses the linear or tiled offsets from the
9434 * Display Registers (which do not change across a page-flip)
9435 * so we need only reprogram the base address.
9437 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9438 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9439 intel_ring_emit(ring
, fb
->pitches
[0]);
9440 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
9443 /* XXX Enabling the panel-fitter across page-flip is so far
9444 * untested on non-native modes, so ignore it for now.
9445 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9448 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9449 intel_ring_emit(ring
, pf
| pipesrc
);
9451 intel_mark_page_flip_active(intel_crtc
);
9452 __intel_ring_advance(ring
);
9456 static int intel_gen6_queue_flip(struct drm_device
*dev
,
9457 struct drm_crtc
*crtc
,
9458 struct drm_framebuffer
*fb
,
9459 struct drm_i915_gem_object
*obj
,
9460 struct intel_engine_cs
*ring
,
9463 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9464 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9465 uint32_t pf
, pipesrc
;
9468 ret
= intel_ring_begin(ring
, 4);
9472 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
9473 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
9474 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
9475 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9477 /* Contrary to the suggestions in the documentation,
9478 * "Enable Panel Fitter" does not seem to be required when page
9479 * flipping with a non-native mode, and worse causes a normal
9481 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9484 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
9485 intel_ring_emit(ring
, pf
| pipesrc
);
9487 intel_mark_page_flip_active(intel_crtc
);
9488 __intel_ring_advance(ring
);
9492 static int intel_gen7_queue_flip(struct drm_device
*dev
,
9493 struct drm_crtc
*crtc
,
9494 struct drm_framebuffer
*fb
,
9495 struct drm_i915_gem_object
*obj
,
9496 struct intel_engine_cs
*ring
,
9499 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9500 uint32_t plane_bit
= 0;
9503 switch (intel_crtc
->plane
) {
9505 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
9508 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
9511 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
9514 WARN_ONCE(1, "unknown plane in flip command\n");
9519 if (ring
->id
== RCS
) {
9522 * On Gen 8, SRM is now taking an extra dword to accommodate
9523 * 48bits addresses, and we need a NOOP for the batch size to
9531 * BSpec MI_DISPLAY_FLIP for IVB:
9532 * "The full packet must be contained within the same cache line."
9534 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9535 * cacheline, if we ever start emitting more commands before
9536 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9537 * then do the cacheline alignment, and finally emit the
9540 ret
= intel_ring_cacheline_align(ring
);
9544 ret
= intel_ring_begin(ring
, len
);
9548 /* Unmask the flip-done completion message. Note that the bspec says that
9549 * we should do this for both the BCS and RCS, and that we must not unmask
9550 * more than one flip event at any time (or ensure that one flip message
9551 * can be sent by waiting for flip-done prior to queueing new flips).
9552 * Experimentation says that BCS works despite DERRMR masking all
9553 * flip-done completion events and that unmasking all planes at once
9554 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9555 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9557 if (ring
->id
== RCS
) {
9558 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
9559 intel_ring_emit(ring
, DERRMR
);
9560 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
9561 DERRMR_PIPEB_PRI_FLIP_DONE
|
9562 DERRMR_PIPEC_PRI_FLIP_DONE
));
9564 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8(1) |
9565 MI_SRM_LRM_GLOBAL_GTT
);
9567 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM(1) |
9568 MI_SRM_LRM_GLOBAL_GTT
);
9569 intel_ring_emit(ring
, DERRMR
);
9570 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
9572 intel_ring_emit(ring
, 0);
9573 intel_ring_emit(ring
, MI_NOOP
);
9577 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
9578 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
9579 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
9580 intel_ring_emit(ring
, (MI_NOOP
));
9582 intel_mark_page_flip_active(intel_crtc
);
9583 __intel_ring_advance(ring
);
9587 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
9588 struct drm_i915_gem_object
*obj
)
9591 * This is not being used for older platforms, because
9592 * non-availability of flip done interrupt forces us to use
9593 * CS flips. Older platforms derive flip done using some clever
9594 * tricks involving the flip_pending status bits and vblank irqs.
9595 * So using MMIO flips there would disrupt this mechanism.
9601 if (INTEL_INFO(ring
->dev
)->gen
< 5)
9604 if (i915
.use_mmio_flip
< 0)
9606 else if (i915
.use_mmio_flip
> 0)
9608 else if (i915
.enable_execlists
)
9611 return ring
!= obj
->ring
;
9614 static void intel_do_mmio_flip(struct intel_crtc
*intel_crtc
)
9616 struct drm_device
*dev
= intel_crtc
->base
.dev
;
9617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9618 struct intel_framebuffer
*intel_fb
=
9619 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
9620 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
9624 intel_mark_page_flip_active(intel_crtc
);
9626 reg
= DSPCNTR(intel_crtc
->plane
);
9627 dspcntr
= I915_READ(reg
);
9629 if (INTEL_INFO(dev
)->gen
>= 4) {
9630 if (obj
->tiling_mode
!= I915_TILING_NONE
)
9631 dspcntr
|= DISPPLANE_TILED
;
9633 dspcntr
&= ~DISPPLANE_TILED
;
9635 I915_WRITE(reg
, dspcntr
);
9637 I915_WRITE(DSPSURF(intel_crtc
->plane
),
9638 intel_crtc
->unpin_work
->gtt_offset
);
9639 POSTING_READ(DSPSURF(intel_crtc
->plane
));
9642 static int intel_postpone_flip(struct drm_i915_gem_object
*obj
)
9644 struct intel_engine_cs
*ring
;
9647 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
9649 if (!obj
->last_write_seqno
)
9654 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
9655 obj
->last_write_seqno
))
9658 ret
= i915_gem_check_olr(ring
, obj
->last_write_seqno
);
9662 if (WARN_ON(!ring
->irq_get(ring
)))
9668 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
)
9670 struct drm_i915_private
*dev_priv
= to_i915(ring
->dev
);
9671 struct intel_crtc
*intel_crtc
;
9672 unsigned long irq_flags
;
9675 seqno
= ring
->get_seqno(ring
, false);
9677 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9678 for_each_intel_crtc(ring
->dev
, intel_crtc
) {
9679 struct intel_mmio_flip
*mmio_flip
;
9681 mmio_flip
= &intel_crtc
->mmio_flip
;
9682 if (mmio_flip
->seqno
== 0)
9685 if (ring
->id
!= mmio_flip
->ring_id
)
9688 if (i915_seqno_passed(seqno
, mmio_flip
->seqno
)) {
9689 intel_do_mmio_flip(intel_crtc
);
9690 mmio_flip
->seqno
= 0;
9691 ring
->irq_put(ring
);
9694 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9697 static int intel_queue_mmio_flip(struct drm_device
*dev
,
9698 struct drm_crtc
*crtc
,
9699 struct drm_framebuffer
*fb
,
9700 struct drm_i915_gem_object
*obj
,
9701 struct intel_engine_cs
*ring
,
9704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9705 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9706 unsigned long irq_flags
;
9709 if (WARN_ON(intel_crtc
->mmio_flip
.seqno
))
9712 ret
= intel_postpone_flip(obj
);
9716 intel_do_mmio_flip(intel_crtc
);
9720 spin_lock_irqsave(&dev_priv
->mmio_flip_lock
, irq_flags
);
9721 intel_crtc
->mmio_flip
.seqno
= obj
->last_write_seqno
;
9722 intel_crtc
->mmio_flip
.ring_id
= obj
->ring
->id
;
9723 spin_unlock_irqrestore(&dev_priv
->mmio_flip_lock
, irq_flags
);
9726 * Double check to catch cases where irq fired before
9727 * mmio flip data was ready
9729 intel_notify_mmio_flip(obj
->ring
);
9733 static int intel_default_queue_flip(struct drm_device
*dev
,
9734 struct drm_crtc
*crtc
,
9735 struct drm_framebuffer
*fb
,
9736 struct drm_i915_gem_object
*obj
,
9737 struct intel_engine_cs
*ring
,
9743 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
9744 struct drm_framebuffer
*fb
,
9745 struct drm_pending_vblank_event
*event
,
9746 uint32_t page_flip_flags
)
9748 struct drm_device
*dev
= crtc
->dev
;
9749 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9750 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
9751 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
9752 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9753 enum pipe pipe
= intel_crtc
->pipe
;
9754 struct intel_unpin_work
*work
;
9755 struct intel_engine_cs
*ring
;
9756 unsigned long flags
;
9759 //trigger software GT busyness calculation
9760 gen8_flip_interrupt(dev
);
9763 * drm_mode_page_flip_ioctl() should already catch this, but double
9764 * check to be safe. In the future we may enable pageflipping from
9765 * a disabled primary plane.
9767 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
9770 /* Can't change pixel format via MI display flips. */
9771 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
9775 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9776 * Note that pitch changes could also affect these register.
9778 if (INTEL_INFO(dev
)->gen
> 3 &&
9779 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
9780 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
9783 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
9786 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
9790 work
->event
= event
;
9792 work
->old_fb_obj
= intel_fb_obj(old_fb
);
9793 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
9795 ret
= drm_crtc_vblank_get(crtc
);
9799 /* We borrow the event spin lock for protecting unpin_work */
9800 spin_lock_irqsave(&dev
->event_lock
, flags
);
9801 if (intel_crtc
->unpin_work
) {
9802 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9804 drm_crtc_vblank_put(crtc
);
9806 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9809 intel_crtc
->unpin_work
= work
;
9810 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9812 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
9813 flush_workqueue(dev_priv
->wq
);
9815 ret
= i915_mutex_lock_interruptible(dev
);
9819 /* Reference the objects for the scheduled work. */
9820 drm_gem_object_reference(&work
->old_fb_obj
->base
);
9821 drm_gem_object_reference(&obj
->base
);
9823 crtc
->primary
->fb
= fb
;
9825 work
->pending_flip_obj
= obj
;
9827 work
->enable_stall_check
= true;
9829 atomic_inc(&intel_crtc
->unpin_work_count
);
9830 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
9832 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
9833 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_GM45(pipe
)) + 1;
9835 if (IS_VALLEYVIEW(dev
)) {
9836 ring
= &dev_priv
->ring
[BCS
];
9837 if (obj
->tiling_mode
!= work
->old_fb_obj
->tiling_mode
)
9838 /* vlv: DISPLAY_FLIP fails to change tiling */
9840 } else if (IS_IVYBRIDGE(dev
)) {
9841 ring
= &dev_priv
->ring
[BCS
];
9842 } else if (INTEL_INFO(dev
)->gen
>= 7) {
9844 if (ring
== NULL
|| ring
->id
!= RCS
)
9845 ring
= &dev_priv
->ring
[BCS
];
9847 ring
= &dev_priv
->ring
[RCS
];
9850 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
9852 goto cleanup_pending
;
9855 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
;
9857 if (use_mmio_flip(ring
, obj
))
9858 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
9861 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, ring
,
9866 i915_gem_track_fb(work
->old_fb_obj
, obj
,
9867 INTEL_FRONTBUFFER_PRIMARY(pipe
));
9869 intel_disable_fbc(dev
);
9870 intel_frontbuffer_flip_prepare(dev
, INTEL_FRONTBUFFER_PRIMARY(pipe
));
9871 mutex_unlock(&dev
->struct_mutex
);
9873 trace_i915_flip_request(intel_crtc
->plane
, obj
);
9878 intel_unpin_fb_obj(obj
);
9880 atomic_dec(&intel_crtc
->unpin_work_count
);
9881 crtc
->primary
->fb
= old_fb
;
9882 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
9883 drm_gem_object_unreference(&obj
->base
);
9884 mutex_unlock(&dev
->struct_mutex
);
9887 spin_lock_irqsave(&dev
->event_lock
, flags
);
9888 intel_crtc
->unpin_work
= NULL
;
9889 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
9891 drm_crtc_vblank_put(crtc
);
9897 intel_crtc_wait_for_pending_flips(crtc
);
9898 ret
= intel_pipe_set_base(crtc
, crtc
->x
, crtc
->y
, fb
);
9899 if (ret
== 0 && event
)
9900 drm_send_vblank_event(dev
, pipe
, event
);
9905 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
9906 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
9907 .load_lut
= intel_crtc_load_lut
,
9911 * intel_modeset_update_staged_output_state
9913 * Updates the staged output configuration state, e.g. after we've read out the
9916 static void intel_modeset_update_staged_output_state(struct drm_device
*dev
)
9918 struct intel_crtc
*crtc
;
9919 struct intel_encoder
*encoder
;
9920 struct intel_connector
*connector
;
9922 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9924 connector
->new_encoder
=
9925 to_intel_encoder(connector
->base
.encoder
);
9928 for_each_intel_encoder(dev
, encoder
) {
9930 to_intel_crtc(encoder
->base
.crtc
);
9933 for_each_intel_crtc(dev
, crtc
) {
9934 crtc
->new_enabled
= crtc
->base
.enabled
;
9936 if (crtc
->new_enabled
)
9937 crtc
->new_config
= &crtc
->config
;
9939 crtc
->new_config
= NULL
;
9944 * intel_modeset_commit_output_state
9946 * This function copies the stage display pipe configuration to the real one.
9948 static void intel_modeset_commit_output_state(struct drm_device
*dev
)
9950 struct intel_crtc
*crtc
;
9951 struct intel_encoder
*encoder
;
9952 struct intel_connector
*connector
;
9954 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
9956 connector
->base
.encoder
= &connector
->new_encoder
->base
;
9959 for_each_intel_encoder(dev
, encoder
) {
9960 encoder
->base
.crtc
= &encoder
->new_crtc
->base
;
9963 for_each_intel_crtc(dev
, crtc
) {
9964 crtc
->base
.enabled
= crtc
->new_enabled
;
9969 connected_sink_compute_bpp(struct intel_connector
*connector
,
9970 struct intel_crtc_config
*pipe_config
)
9972 int bpp
= pipe_config
->pipe_bpp
;
9974 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9975 connector
->base
.base
.id
,
9976 connector
->base
.name
);
9978 /* Don't use an invalid EDID bpc value */
9979 if (connector
->base
.display_info
.bpc
&&
9980 connector
->base
.display_info
.bpc
* 3 < bpp
) {
9981 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9982 bpp
, connector
->base
.display_info
.bpc
*3);
9983 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
9986 /* Clamp bpp to 8 on screens without EDID 1.4 */
9987 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
9988 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9990 pipe_config
->pipe_bpp
= 24;
9995 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
9996 struct drm_framebuffer
*fb
,
9997 struct intel_crtc_config
*pipe_config
)
9999 struct drm_device
*dev
= crtc
->base
.dev
;
10000 struct intel_connector
*connector
;
10003 switch (fb
->pixel_format
) {
10004 case DRM_FORMAT_C8
:
10005 bpp
= 8*3; /* since we go through a colormap */
10007 case DRM_FORMAT_XRGB1555
:
10008 case DRM_FORMAT_ARGB1555
:
10009 /* checked in intel_framebuffer_init already */
10010 if (WARN_ON(INTEL_INFO(dev
)->gen
> 3))
10012 case DRM_FORMAT_RGB565
:
10013 bpp
= 6*3; /* min is 18bpp */
10015 case DRM_FORMAT_XBGR8888
:
10016 case DRM_FORMAT_ABGR8888
:
10017 /* checked in intel_framebuffer_init already */
10018 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10020 case DRM_FORMAT_XRGB8888
:
10021 case DRM_FORMAT_ARGB8888
:
10024 case DRM_FORMAT_XRGB2101010
:
10025 case DRM_FORMAT_ARGB2101010
:
10026 case DRM_FORMAT_XBGR2101010
:
10027 case DRM_FORMAT_ABGR2101010
:
10028 /* checked in intel_framebuffer_init already */
10029 if (WARN_ON(INTEL_INFO(dev
)->gen
< 4))
10033 /* TODO: gen4+ supports 16 bpc floating point, too. */
10035 DRM_DEBUG_KMS("unsupported depth\n");
10039 pipe_config
->pipe_bpp
= bpp
;
10041 /* Clamp display bpp to EDID value */
10042 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10044 if (!connector
->new_encoder
||
10045 connector
->new_encoder
->new_crtc
!= crtc
)
10048 connected_sink_compute_bpp(connector
, pipe_config
);
10054 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
10056 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10057 "type: 0x%x flags: 0x%x\n",
10059 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
10060 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
10061 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
10062 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
10065 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
10066 struct intel_crtc_config
*pipe_config
,
10067 const char *context
)
10069 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc
->base
.base
.id
,
10070 context
, pipe_name(crtc
->pipe
));
10072 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
10073 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10074 pipe_config
->pipe_bpp
, pipe_config
->dither
);
10075 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10076 pipe_config
->has_pch_encoder
,
10077 pipe_config
->fdi_lanes
,
10078 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
10079 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
10080 pipe_config
->fdi_m_n
.tu
);
10081 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10082 pipe_config
->has_dp_encoder
,
10083 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
10084 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
10085 pipe_config
->dp_m_n
.tu
);
10087 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10088 pipe_config
->has_dp_encoder
,
10089 pipe_config
->dp_m2_n2
.gmch_m
,
10090 pipe_config
->dp_m2_n2
.gmch_n
,
10091 pipe_config
->dp_m2_n2
.link_m
,
10092 pipe_config
->dp_m2_n2
.link_n
,
10093 pipe_config
->dp_m2_n2
.tu
);
10095 DRM_DEBUG_KMS("requested mode:\n");
10096 drm_mode_debug_printmodeline(&pipe_config
->requested_mode
);
10097 DRM_DEBUG_KMS("adjusted mode:\n");
10098 drm_mode_debug_printmodeline(&pipe_config
->adjusted_mode
);
10099 intel_dump_crtc_timings(&pipe_config
->adjusted_mode
);
10100 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
10101 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10102 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
10103 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10104 pipe_config
->gmch_pfit
.control
,
10105 pipe_config
->gmch_pfit
.pgm_ratios
,
10106 pipe_config
->gmch_pfit
.lvds_border_bits
);
10107 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10108 pipe_config
->pch_pfit
.pos
,
10109 pipe_config
->pch_pfit
.size
,
10110 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
10111 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
10112 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
10115 static bool encoders_cloneable(const struct intel_encoder
*a
,
10116 const struct intel_encoder
*b
)
10118 /* masks could be asymmetric, so check both ways */
10119 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
10120 b
->cloneable
& (1 << a
->type
));
10123 static bool check_single_encoder_cloning(struct intel_crtc
*crtc
,
10124 struct intel_encoder
*encoder
)
10126 struct drm_device
*dev
= crtc
->base
.dev
;
10127 struct intel_encoder
*source_encoder
;
10129 for_each_intel_encoder(dev
, source_encoder
) {
10130 if (source_encoder
->new_crtc
!= crtc
)
10133 if (!encoders_cloneable(encoder
, source_encoder
))
10140 static bool check_encoder_cloning(struct intel_crtc
*crtc
)
10142 struct drm_device
*dev
= crtc
->base
.dev
;
10143 struct intel_encoder
*encoder
;
10145 for_each_intel_encoder(dev
, encoder
) {
10146 if (encoder
->new_crtc
!= crtc
)
10149 if (!check_single_encoder_cloning(crtc
, encoder
))
10156 static struct intel_crtc_config
*
10157 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
10158 struct drm_framebuffer
*fb
,
10159 struct drm_display_mode
*mode
)
10161 struct drm_device
*dev
= crtc
->dev
;
10162 struct intel_encoder
*encoder
;
10163 struct intel_crtc_config
*pipe_config
;
10164 int plane_bpp
, ret
= -EINVAL
;
10167 if (!check_encoder_cloning(to_intel_crtc(crtc
))) {
10168 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10169 return ERR_PTR(-EINVAL
);
10172 pipe_config
= kzalloc(sizeof(*pipe_config
), GFP_KERNEL
);
10174 return ERR_PTR(-ENOMEM
);
10176 drm_mode_copy(&pipe_config
->adjusted_mode
, mode
);
10177 drm_mode_copy(&pipe_config
->requested_mode
, mode
);
10179 pipe_config
->cpu_transcoder
=
10180 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
10181 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
10184 * Sanitize sync polarity flags based on requested ones. If neither
10185 * positive or negative polarity is requested, treat this as meaning
10186 * negative polarity.
10188 if (!(pipe_config
->adjusted_mode
.flags
&
10189 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
10190 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
10192 if (!(pipe_config
->adjusted_mode
.flags
&
10193 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
10194 pipe_config
->adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
10196 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10197 * plane pixel format and any sink constraints into account. Returns the
10198 * source plane bpp so that dithering can be selected on mismatches
10199 * after encoders and crtc also have had their say. */
10200 plane_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
10206 * Determine the real pipe dimensions. Note that stereo modes can
10207 * increase the actual pipe size due to the frame doubling and
10208 * insertion of additional space for blanks between the frame. This
10209 * is stored in the crtc timings. We use the requested mode to do this
10210 * computation to clearly distinguish it from the adjusted mode, which
10211 * can be changed by the connectors in the below retry loop.
10213 drm_mode_set_crtcinfo(&pipe_config
->requested_mode
, CRTC_STEREO_DOUBLE
);
10214 pipe_config
->pipe_src_w
= pipe_config
->requested_mode
.crtc_hdisplay
;
10215 pipe_config
->pipe_src_h
= pipe_config
->requested_mode
.crtc_vdisplay
;
10218 /* Ensure the port clock defaults are reset when retrying. */
10219 pipe_config
->port_clock
= 0;
10220 pipe_config
->pixel_multiplier
= 1;
10222 /* Fill in default crtc timings, allow encoders to overwrite them. */
10223 drm_mode_set_crtcinfo(&pipe_config
->adjusted_mode
, CRTC_STEREO_DOUBLE
);
10225 /* Pass our mode to the connectors and the CRTC to give them a chance to
10226 * adjust it according to limitations or connector properties, and also
10227 * a chance to reject the mode entirely.
10229 for_each_intel_encoder(dev
, encoder
) {
10231 if (&encoder
->new_crtc
->base
!= crtc
)
10234 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
10235 DRM_DEBUG_KMS("Encoder config failure\n");
10240 /* Set default port clock if not overwritten by the encoder. Needs to be
10241 * done afterwards in case the encoder adjusts the mode. */
10242 if (!pipe_config
->port_clock
)
10243 pipe_config
->port_clock
= pipe_config
->adjusted_mode
.crtc_clock
10244 * pipe_config
->pixel_multiplier
;
10246 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
10248 DRM_DEBUG_KMS("CRTC fixup failed\n");
10252 if (ret
== RETRY
) {
10253 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
10258 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10260 goto encoder_retry
;
10263 pipe_config
->dither
= pipe_config
->pipe_bpp
!= plane_bpp
;
10264 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10265 plane_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
10267 return pipe_config
;
10269 kfree(pipe_config
);
10270 return ERR_PTR(ret
);
10273 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10274 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10276 intel_modeset_affected_pipes(struct drm_crtc
*crtc
, unsigned *modeset_pipes
,
10277 unsigned *prepare_pipes
, unsigned *disable_pipes
)
10279 struct intel_crtc
*intel_crtc
;
10280 struct drm_device
*dev
= crtc
->dev
;
10281 struct intel_encoder
*encoder
;
10282 struct intel_connector
*connector
;
10283 struct drm_crtc
*tmp_crtc
;
10285 *disable_pipes
= *modeset_pipes
= *prepare_pipes
= 0;
10287 /* Check which crtcs have changed outputs connected to them, these need
10288 * to be part of the prepare_pipes mask. We don't (yet) support global
10289 * modeset across multiple crtcs, so modeset_pipes will only have one
10290 * bit set at most. */
10291 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10293 if (connector
->base
.encoder
== &connector
->new_encoder
->base
)
10296 if (connector
->base
.encoder
) {
10297 tmp_crtc
= connector
->base
.encoder
->crtc
;
10299 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10302 if (connector
->new_encoder
)
10304 1 << connector
->new_encoder
->new_crtc
->pipe
;
10307 for_each_intel_encoder(dev
, encoder
) {
10308 if (encoder
->base
.crtc
== &encoder
->new_crtc
->base
)
10311 if (encoder
->base
.crtc
) {
10312 tmp_crtc
= encoder
->base
.crtc
;
10314 *prepare_pipes
|= 1 << to_intel_crtc(tmp_crtc
)->pipe
;
10317 if (encoder
->new_crtc
)
10318 *prepare_pipes
|= 1 << encoder
->new_crtc
->pipe
;
10321 /* Check for pipes that will be enabled/disabled ... */
10322 for_each_intel_crtc(dev
, intel_crtc
) {
10323 if (intel_crtc
->base
.enabled
== intel_crtc
->new_enabled
)
10326 if (!intel_crtc
->new_enabled
)
10327 *disable_pipes
|= 1 << intel_crtc
->pipe
;
10329 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10333 /* set_mode is also used to update properties on life display pipes. */
10334 intel_crtc
= to_intel_crtc(crtc
);
10335 if (intel_crtc
->new_enabled
)
10336 *prepare_pipes
|= 1 << intel_crtc
->pipe
;
10339 * For simplicity do a full modeset on any pipe where the output routing
10340 * changed. We could be more clever, but that would require us to be
10341 * more careful with calling the relevant encoder->mode_set functions.
10343 if (*prepare_pipes
)
10344 *modeset_pipes
= *prepare_pipes
;
10346 /* ... and mask these out. */
10347 *modeset_pipes
&= ~(*disable_pipes
);
10348 *prepare_pipes
&= ~(*disable_pipes
);
10351 * HACK: We don't (yet) fully support global modesets. intel_set_config
10352 * obies this rule, but the modeset restore mode of
10353 * intel_modeset_setup_hw_state does not.
10355 *modeset_pipes
&= 1 << intel_crtc
->pipe
;
10356 *prepare_pipes
&= 1 << intel_crtc
->pipe
;
10358 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10359 *modeset_pipes
, *prepare_pipes
, *disable_pipes
);
10362 static bool intel_crtc_in_use(struct drm_crtc
*crtc
)
10364 struct drm_encoder
*encoder
;
10365 struct drm_device
*dev
= crtc
->dev
;
10367 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
)
10368 if (encoder
->crtc
== crtc
)
10375 intel_modeset_update_state(struct drm_device
*dev
, unsigned prepare_pipes
)
10377 struct intel_encoder
*intel_encoder
;
10378 struct intel_crtc
*intel_crtc
;
10379 struct drm_connector
*connector
;
10381 for_each_intel_encoder(dev
, intel_encoder
) {
10382 if (!intel_encoder
->base
.crtc
)
10385 intel_crtc
= to_intel_crtc(intel_encoder
->base
.crtc
);
10387 if (prepare_pipes
& (1 << intel_crtc
->pipe
))
10388 intel_encoder
->connectors_active
= false;
10391 intel_modeset_commit_output_state(dev
);
10393 /* Double check state. */
10394 for_each_intel_crtc(dev
, intel_crtc
) {
10395 WARN_ON(intel_crtc
->base
.enabled
!= intel_crtc_in_use(&intel_crtc
->base
));
10396 WARN_ON(intel_crtc
->new_config
&&
10397 intel_crtc
->new_config
!= &intel_crtc
->config
);
10398 WARN_ON(intel_crtc
->base
.enabled
!= !!intel_crtc
->new_config
);
10401 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
10402 if (!connector
->encoder
|| !connector
->encoder
->crtc
)
10405 intel_crtc
= to_intel_crtc(connector
->encoder
->crtc
);
10407 if (prepare_pipes
& (1 << intel_crtc
->pipe
)) {
10408 struct drm_property
*dpms_property
=
10409 dev
->mode_config
.dpms_property
;
10411 connector
->dpms
= DRM_MODE_DPMS_ON
;
10412 drm_object_property_set_value(&connector
->base
,
10416 intel_encoder
= to_intel_encoder(connector
->encoder
);
10417 intel_encoder
->connectors_active
= true;
10423 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
10427 if (clock1
== clock2
)
10430 if (!clock1
|| !clock2
)
10433 diff
= abs(clock1
- clock2
);
10435 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
10441 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10442 list_for_each_entry((intel_crtc), \
10443 &(dev)->mode_config.crtc_list, \
10445 if (mask & (1 <<(intel_crtc)->pipe))
10448 intel_pipe_config_compare(struct drm_device
*dev
,
10449 struct intel_crtc_config
*current_config
,
10450 struct intel_crtc_config
*pipe_config
)
10452 #define PIPE_CONF_CHECK_X(name) \
10453 if (current_config->name != pipe_config->name) { \
10454 DRM_ERROR("mismatch in " #name " " \
10455 "(expected 0x%08x, found 0x%08x)\n", \
10456 current_config->name, \
10457 pipe_config->name); \
10461 #define PIPE_CONF_CHECK_I(name) \
10462 if (current_config->name != pipe_config->name) { \
10463 DRM_ERROR("mismatch in " #name " " \
10464 "(expected %i, found %i)\n", \
10465 current_config->name, \
10466 pipe_config->name); \
10470 /* This is required for BDW+ where there is only one set of registers for
10471 * switching between high and low RR.
10472 * This macro can be used whenever a comparison has to be made between one
10473 * hw state and multiple sw state variables.
10475 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10476 if ((current_config->name != pipe_config->name) && \
10477 (current_config->alt_name != pipe_config->name)) { \
10478 DRM_ERROR("mismatch in " #name " " \
10479 "(expected %i or %i, found %i)\n", \
10480 current_config->name, \
10481 current_config->alt_name, \
10482 pipe_config->name); \
10486 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10487 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10488 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10489 "(expected %i, found %i)\n", \
10490 current_config->name & (mask), \
10491 pipe_config->name & (mask)); \
10495 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10496 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10497 DRM_ERROR("mismatch in " #name " " \
10498 "(expected %i, found %i)\n", \
10499 current_config->name, \
10500 pipe_config->name); \
10504 #define PIPE_CONF_QUIRK(quirk) \
10505 ((current_config->quirks | pipe_config->quirks) & (quirk))
10507 PIPE_CONF_CHECK_I(cpu_transcoder
);
10509 PIPE_CONF_CHECK_I(has_pch_encoder
);
10510 PIPE_CONF_CHECK_I(fdi_lanes
);
10511 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_m
);
10512 PIPE_CONF_CHECK_I(fdi_m_n
.gmch_n
);
10513 PIPE_CONF_CHECK_I(fdi_m_n
.link_m
);
10514 PIPE_CONF_CHECK_I(fdi_m_n
.link_n
);
10515 PIPE_CONF_CHECK_I(fdi_m_n
.tu
);
10517 PIPE_CONF_CHECK_I(has_dp_encoder
);
10519 if (INTEL_INFO(dev
)->gen
< 8) {
10520 PIPE_CONF_CHECK_I(dp_m_n
.gmch_m
);
10521 PIPE_CONF_CHECK_I(dp_m_n
.gmch_n
);
10522 PIPE_CONF_CHECK_I(dp_m_n
.link_m
);
10523 PIPE_CONF_CHECK_I(dp_m_n
.link_n
);
10524 PIPE_CONF_CHECK_I(dp_m_n
.tu
);
10526 if (current_config
->has_drrs
) {
10527 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_m
);
10528 PIPE_CONF_CHECK_I(dp_m2_n2
.gmch_n
);
10529 PIPE_CONF_CHECK_I(dp_m2_n2
.link_m
);
10530 PIPE_CONF_CHECK_I(dp_m2_n2
.link_n
);
10531 PIPE_CONF_CHECK_I(dp_m2_n2
.tu
);
10534 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_m
, dp_m2_n2
.gmch_m
);
10535 PIPE_CONF_CHECK_I_ALT(dp_m_n
.gmch_n
, dp_m2_n2
.gmch_n
);
10536 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_m
, dp_m2_n2
.link_m
);
10537 PIPE_CONF_CHECK_I_ALT(dp_m_n
.link_n
, dp_m2_n2
.link_n
);
10538 PIPE_CONF_CHECK_I_ALT(dp_m_n
.tu
, dp_m2_n2
.tu
);
10541 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hdisplay
);
10542 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_htotal
);
10543 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_start
);
10544 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hblank_end
);
10545 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_start
);
10546 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_hsync_end
);
10548 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vdisplay
);
10549 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vtotal
);
10550 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_start
);
10551 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vblank_end
);
10552 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_start
);
10553 PIPE_CONF_CHECK_I(adjusted_mode
.crtc_vsync_end
);
10555 PIPE_CONF_CHECK_I(pixel_multiplier
);
10556 PIPE_CONF_CHECK_I(has_hdmi_sink
);
10557 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
10558 IS_VALLEYVIEW(dev
))
10559 PIPE_CONF_CHECK_I(limited_color_range
);
10561 PIPE_CONF_CHECK_I(has_audio
);
10563 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10564 DRM_MODE_FLAG_INTERLACE
);
10566 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
10567 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10568 DRM_MODE_FLAG_PHSYNC
);
10569 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10570 DRM_MODE_FLAG_NHSYNC
);
10571 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10572 DRM_MODE_FLAG_PVSYNC
);
10573 PIPE_CONF_CHECK_FLAGS(adjusted_mode
.flags
,
10574 DRM_MODE_FLAG_NVSYNC
);
10577 PIPE_CONF_CHECK_I(pipe_src_w
);
10578 PIPE_CONF_CHECK_I(pipe_src_h
);
10581 * FIXME: BIOS likes to set up a cloned config with lvds+external
10582 * screen. Since we don't yet re-compute the pipe config when moving
10583 * just the lvds port away to another pipe the sw tracking won't match.
10585 * Proper atomic modesets with recomputed global state will fix this.
10586 * Until then just don't check gmch state for inherited modes.
10588 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE
)) {
10589 PIPE_CONF_CHECK_I(gmch_pfit
.control
);
10590 /* pfit ratios are autocomputed by the hw on gen4+ */
10591 if (INTEL_INFO(dev
)->gen
< 4)
10592 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
10593 PIPE_CONF_CHECK_I(gmch_pfit
.lvds_border_bits
);
10596 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
10597 if (current_config
->pch_pfit
.enabled
) {
10598 PIPE_CONF_CHECK_I(pch_pfit
.pos
);
10599 PIPE_CONF_CHECK_I(pch_pfit
.size
);
10602 /* BDW+ don't expose a synchronous way to read the state */
10603 if (IS_HASWELL(dev
))
10604 PIPE_CONF_CHECK_I(ips_enabled
);
10606 PIPE_CONF_CHECK_I(double_wide
);
10608 PIPE_CONF_CHECK_X(ddi_pll_sel
);
10610 PIPE_CONF_CHECK_I(shared_dpll
);
10611 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
10612 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
10613 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
10614 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
10615 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
10617 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
10618 PIPE_CONF_CHECK_I(pipe_bpp
);
10620 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode
.crtc_clock
);
10621 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
10623 #undef PIPE_CONF_CHECK_X
10624 #undef PIPE_CONF_CHECK_I
10625 #undef PIPE_CONF_CHECK_I_ALT
10626 #undef PIPE_CONF_CHECK_FLAGS
10627 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10628 #undef PIPE_CONF_QUIRK
10634 check_connector_state(struct drm_device
*dev
)
10636 struct intel_connector
*connector
;
10638 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10640 /* This also checks the encoder/connector hw state with the
10641 * ->get_hw_state callbacks. */
10642 intel_connector_check_state(connector
);
10644 WARN(&connector
->new_encoder
->base
!= connector
->base
.encoder
,
10645 "connector's staged encoder doesn't match current encoder\n");
10650 check_encoder_state(struct drm_device
*dev
)
10652 struct intel_encoder
*encoder
;
10653 struct intel_connector
*connector
;
10655 for_each_intel_encoder(dev
, encoder
) {
10656 bool enabled
= false;
10657 bool active
= false;
10658 enum pipe pipe
, tracked_pipe
;
10660 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10661 encoder
->base
.base
.id
,
10662 encoder
->base
.name
);
10664 WARN(&encoder
->new_crtc
->base
!= encoder
->base
.crtc
,
10665 "encoder's stage crtc doesn't match current crtc\n");
10666 WARN(encoder
->connectors_active
&& !encoder
->base
.crtc
,
10667 "encoder's active_connectors set, but no crtc\n");
10669 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
10671 if (connector
->base
.encoder
!= &encoder
->base
)
10674 if (connector
->base
.dpms
!= DRM_MODE_DPMS_OFF
)
10678 * for MST connectors if we unplug the connector is gone
10679 * away but the encoder is still connected to a crtc
10680 * until a modeset happens in response to the hotplug.
10682 if (!enabled
&& encoder
->base
.encoder_type
== DRM_MODE_ENCODER_DPMST
)
10685 WARN(!!encoder
->base
.crtc
!= enabled
,
10686 "encoder's enabled state mismatch "
10687 "(expected %i, found %i)\n",
10688 !!encoder
->base
.crtc
, enabled
);
10689 WARN(active
&& !encoder
->base
.crtc
,
10690 "active encoder with no crtc\n");
10692 WARN(encoder
->connectors_active
!= active
,
10693 "encoder's computed active state doesn't match tracked active state "
10694 "(expected %i, found %i)\n", active
, encoder
->connectors_active
);
10696 active
= encoder
->get_hw_state(encoder
, &pipe
);
10697 WARN(active
!= encoder
->connectors_active
,
10698 "encoder's hw state doesn't match sw tracking "
10699 "(expected %i, found %i)\n",
10700 encoder
->connectors_active
, active
);
10702 if (!encoder
->base
.crtc
)
10705 tracked_pipe
= to_intel_crtc(encoder
->base
.crtc
)->pipe
;
10706 WARN(active
&& pipe
!= tracked_pipe
,
10707 "active encoder's pipe doesn't match"
10708 "(expected %i, found %i)\n",
10709 tracked_pipe
, pipe
);
10715 check_crtc_state(struct drm_device
*dev
)
10717 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10718 struct intel_crtc
*crtc
;
10719 struct intel_encoder
*encoder
;
10720 struct intel_crtc_config pipe_config
;
10722 for_each_intel_crtc(dev
, crtc
) {
10723 bool enabled
= false;
10724 bool active
= false;
10726 memset(&pipe_config
, 0, sizeof(pipe_config
));
10728 DRM_DEBUG_KMS("[CRTC:%d]\n",
10729 crtc
->base
.base
.id
);
10731 WARN(crtc
->active
&& !crtc
->base
.enabled
,
10732 "active crtc, but not enabled in sw tracking\n");
10734 for_each_intel_encoder(dev
, encoder
) {
10735 if (encoder
->base
.crtc
!= &crtc
->base
)
10738 if (encoder
->connectors_active
)
10742 WARN(active
!= crtc
->active
,
10743 "crtc's computed active state doesn't match tracked active state "
10744 "(expected %i, found %i)\n", active
, crtc
->active
);
10745 WARN(enabled
!= crtc
->base
.enabled
,
10746 "crtc's computed enabled state doesn't match tracked enabled state "
10747 "(expected %i, found %i)\n", enabled
, crtc
->base
.enabled
);
10749 active
= dev_priv
->display
.get_pipe_config(crtc
,
10752 /* hw state is inconsistent with the pipe A quirk */
10753 if (crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
10754 active
= crtc
->active
;
10756 for_each_intel_encoder(dev
, encoder
) {
10758 if (encoder
->base
.crtc
!= &crtc
->base
)
10760 if (encoder
->get_hw_state(encoder
, &pipe
))
10761 encoder
->get_config(encoder
, &pipe_config
);
10764 WARN(crtc
->active
!= active
,
10765 "crtc active state doesn't match with hw state "
10766 "(expected %i, found %i)\n", crtc
->active
, active
);
10769 !intel_pipe_config_compare(dev
, &crtc
->config
, &pipe_config
)) {
10770 WARN(1, "pipe state doesn't match!\n");
10771 intel_dump_pipe_config(crtc
, &pipe_config
,
10773 intel_dump_pipe_config(crtc
, &crtc
->config
,
10780 check_shared_dpll_state(struct drm_device
*dev
)
10782 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10783 struct intel_crtc
*crtc
;
10784 struct intel_dpll_hw_state dpll_hw_state
;
10787 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
10788 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
10789 int enabled_crtcs
= 0, active_crtcs
= 0;
10792 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
10794 DRM_DEBUG_KMS("%s\n", pll
->name
);
10796 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
10798 WARN(pll
->active
> pll
->refcount
,
10799 "more active pll users than references: %i vs %i\n",
10800 pll
->active
, pll
->refcount
);
10801 WARN(pll
->active
&& !pll
->on
,
10802 "pll in active use but not on in sw tracking\n");
10803 WARN(pll
->on
&& !pll
->active
,
10804 "pll in on but not on in use in sw tracking\n");
10805 WARN(pll
->on
!= active
,
10806 "pll on state mismatch (expected %i, found %i)\n",
10809 for_each_intel_crtc(dev
, crtc
) {
10810 if (crtc
->base
.enabled
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10812 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
10815 WARN(pll
->active
!= active_crtcs
,
10816 "pll active crtcs mismatch (expected %i, found %i)\n",
10817 pll
->active
, active_crtcs
);
10818 WARN(pll
->refcount
!= enabled_crtcs
,
10819 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10820 pll
->refcount
, enabled_crtcs
);
10822 WARN(pll
->on
&& memcmp(&pll
->hw_state
, &dpll_hw_state
,
10823 sizeof(dpll_hw_state
)),
10824 "pll hw state mismatch\n");
10829 intel_modeset_check_state(struct drm_device
*dev
)
10831 check_connector_state(dev
);
10832 check_encoder_state(dev
);
10833 check_crtc_state(dev
);
10834 check_shared_dpll_state(dev
);
10837 void ironlake_check_encoder_dotclock(const struct intel_crtc_config
*pipe_config
,
10841 * FDI already provided one idea for the dotclock.
10842 * Yell if the encoder disagrees.
10844 WARN(!intel_fuzzy_clock_check(pipe_config
->adjusted_mode
.crtc_clock
, dotclock
),
10845 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10846 pipe_config
->adjusted_mode
.crtc_clock
, dotclock
);
10849 static void update_scanline_offset(struct intel_crtc
*crtc
)
10851 struct drm_device
*dev
= crtc
->base
.dev
;
10854 * The scanline counter increments at the leading edge of hsync.
10856 * On most platforms it starts counting from vtotal-1 on the
10857 * first active line. That means the scanline counter value is
10858 * always one less than what we would expect. Ie. just after
10859 * start of vblank, which also occurs at start of hsync (on the
10860 * last active line), the scanline counter will read vblank_start-1.
10862 * On gen2 the scanline counter starts counting from 1 instead
10863 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10864 * to keep the value positive), instead of adding one.
10866 * On HSW+ the behaviour of the scanline counter depends on the output
10867 * type. For DP ports it behaves like most other platforms, but on HDMI
10868 * there's an extra 1 line difference. So we need to add two instead of
10869 * one to the value.
10871 if (IS_GEN2(dev
)) {
10872 const struct drm_display_mode
*mode
= &crtc
->config
.adjusted_mode
;
10875 vtotal
= mode
->crtc_vtotal
;
10876 if (mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
10879 crtc
->scanline_offset
= vtotal
- 1;
10880 } else if (HAS_DDI(dev
) &&
10881 intel_pipe_has_type(&crtc
->base
, INTEL_OUTPUT_HDMI
)) {
10882 crtc
->scanline_offset
= 2;
10884 crtc
->scanline_offset
= 1;
10887 static int __intel_set_mode(struct drm_crtc
*crtc
,
10888 struct drm_display_mode
*mode
,
10889 int x
, int y
, struct drm_framebuffer
*fb
)
10891 struct drm_device
*dev
= crtc
->dev
;
10892 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10893 struct drm_display_mode
*saved_mode
;
10894 struct intel_crtc_config
*pipe_config
= NULL
;
10895 struct intel_crtc
*intel_crtc
;
10896 unsigned disable_pipes
, prepare_pipes
, modeset_pipes
;
10899 saved_mode
= kmalloc(sizeof(*saved_mode
), GFP_KERNEL
);
10903 intel_modeset_affected_pipes(crtc
, &modeset_pipes
,
10904 &prepare_pipes
, &disable_pipes
);
10906 *saved_mode
= crtc
->mode
;
10908 /* Hack: Because we don't (yet) support global modeset on multiple
10909 * crtcs, we don't keep track of the new mode for more than one crtc.
10910 * Hence simply check whether any bit is set in modeset_pipes in all the
10911 * pieces of code that are not yet converted to deal with mutliple crtcs
10912 * changing their mode at the same time. */
10913 if (modeset_pipes
) {
10914 pipe_config
= intel_modeset_pipe_config(crtc
, fb
, mode
);
10915 if (IS_ERR(pipe_config
)) {
10916 ret
= PTR_ERR(pipe_config
);
10917 pipe_config
= NULL
;
10921 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
10923 to_intel_crtc(crtc
)->new_config
= pipe_config
;
10927 * See if the config requires any additional preparation, e.g.
10928 * to adjust global state with pipes off. We need to do this
10929 * here so we can get the modeset_pipe updated config for the new
10930 * mode set on this crtc. For other crtcs we need to use the
10931 * adjusted_mode bits in the crtc directly.
10933 if (IS_VALLEYVIEW(dev
)) {
10934 valleyview_modeset_global_pipes(dev
, &prepare_pipes
);
10936 /* may have added more to prepare_pipes than we should */
10937 prepare_pipes
&= ~disable_pipes
;
10940 for_each_intel_crtc_masked(dev
, disable_pipes
, intel_crtc
)
10941 intel_crtc_disable(&intel_crtc
->base
);
10943 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
10944 if (intel_crtc
->base
.enabled
)
10945 dev_priv
->display
.crtc_disable(&intel_crtc
->base
);
10948 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10949 * to set it here already despite that we pass it down the callchain.
10951 if (modeset_pipes
) {
10952 crtc
->mode
= *mode
;
10953 /* mode_set/enable/disable functions rely on a correct pipe
10955 to_intel_crtc(crtc
)->config
= *pipe_config
;
10956 to_intel_crtc(crtc
)->new_config
= &to_intel_crtc(crtc
)->config
;
10959 * Calculate and store various constants which
10960 * are later needed by vblank and swap-completion
10961 * timestamping. They are derived from true hwmode.
10963 drm_calc_timestamping_constants(crtc
,
10964 &pipe_config
->adjusted_mode
);
10967 /* Only after disabling all output pipelines that will be changed can we
10968 * update the the output configuration. */
10969 intel_modeset_update_state(dev
, prepare_pipes
);
10971 if (dev_priv
->display
.modeset_global_resources
)
10972 dev_priv
->display
.modeset_global_resources(dev
);
10974 /* Set up the DPLL and any encoders state that needs to adjust or depend
10977 for_each_intel_crtc_masked(dev
, modeset_pipes
, intel_crtc
) {
10978 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
10979 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(old_fb
);
10980 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
10982 mutex_lock(&dev
->struct_mutex
);
10983 ret
= intel_pin_and_fence_fb_obj(dev
,
10987 DRM_ERROR("pin & fence failed\n");
10988 mutex_unlock(&dev
->struct_mutex
);
10992 intel_unpin_fb_obj(old_obj
);
10993 i915_gem_track_fb(old_obj
, obj
,
10994 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
10995 mutex_unlock(&dev
->struct_mutex
);
10997 crtc
->primary
->fb
= fb
;
11001 ret
= dev_priv
->display
.crtc_mode_set(&intel_crtc
->base
,
11007 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11008 for_each_intel_crtc_masked(dev
, prepare_pipes
, intel_crtc
) {
11009 update_scanline_offset(intel_crtc
);
11011 dev_priv
->display
.crtc_enable(&intel_crtc
->base
);
11014 /* FIXME: add subpixel order */
11016 if (ret
&& crtc
->enabled
)
11017 crtc
->mode
= *saved_mode
;
11020 kfree(pipe_config
);
11025 static int intel_set_mode(struct drm_crtc
*crtc
,
11026 struct drm_display_mode
*mode
,
11027 int x
, int y
, struct drm_framebuffer
*fb
)
11031 ret
= __intel_set_mode(crtc
, mode
, x
, y
, fb
);
11034 intel_modeset_check_state(crtc
->dev
);
11039 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
11041 intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
, crtc
->primary
->fb
);
11044 #undef for_each_intel_crtc_masked
11046 static void intel_set_config_free(struct intel_set_config
*config
)
11051 kfree(config
->save_connector_encoders
);
11052 kfree(config
->save_encoder_crtcs
);
11053 kfree(config
->save_crtc_enabled
);
11057 static int intel_set_config_save_state(struct drm_device
*dev
,
11058 struct intel_set_config
*config
)
11060 struct drm_crtc
*crtc
;
11061 struct drm_encoder
*encoder
;
11062 struct drm_connector
*connector
;
11065 config
->save_crtc_enabled
=
11066 kcalloc(dev
->mode_config
.num_crtc
,
11067 sizeof(bool), GFP_KERNEL
);
11068 if (!config
->save_crtc_enabled
)
11071 config
->save_encoder_crtcs
=
11072 kcalloc(dev
->mode_config
.num_encoder
,
11073 sizeof(struct drm_crtc
*), GFP_KERNEL
);
11074 if (!config
->save_encoder_crtcs
)
11077 config
->save_connector_encoders
=
11078 kcalloc(dev
->mode_config
.num_connector
,
11079 sizeof(struct drm_encoder
*), GFP_KERNEL
);
11080 if (!config
->save_connector_encoders
)
11083 /* Copy data. Note that driver private data is not affected.
11084 * Should anything bad happen only the expected state is
11085 * restored, not the drivers personal bookkeeping.
11088 for_each_crtc(dev
, crtc
) {
11089 config
->save_crtc_enabled
[count
++] = crtc
->enabled
;
11093 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
11094 config
->save_encoder_crtcs
[count
++] = encoder
->crtc
;
11098 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
11099 config
->save_connector_encoders
[count
++] = connector
->encoder
;
11105 static void intel_set_config_restore_state(struct drm_device
*dev
,
11106 struct intel_set_config
*config
)
11108 struct intel_crtc
*crtc
;
11109 struct intel_encoder
*encoder
;
11110 struct intel_connector
*connector
;
11114 for_each_intel_crtc(dev
, crtc
) {
11115 crtc
->new_enabled
= config
->save_crtc_enabled
[count
++];
11117 if (crtc
->new_enabled
)
11118 crtc
->new_config
= &crtc
->config
;
11120 crtc
->new_config
= NULL
;
11124 for_each_intel_encoder(dev
, encoder
) {
11125 encoder
->new_crtc
=
11126 to_intel_crtc(config
->save_encoder_crtcs
[count
++]);
11130 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11131 connector
->new_encoder
=
11132 to_intel_encoder(config
->save_connector_encoders
[count
++]);
11137 is_crtc_connector_off(struct drm_mode_set
*set
)
11141 if (set
->num_connectors
== 0)
11144 if (WARN_ON(set
->connectors
== NULL
))
11147 for (i
= 0; i
< set
->num_connectors
; i
++)
11148 if (set
->connectors
[i
]->encoder
&&
11149 set
->connectors
[i
]->encoder
->crtc
== set
->crtc
&&
11150 set
->connectors
[i
]->dpms
!= DRM_MODE_DPMS_ON
)
11157 intel_set_config_compute_mode_changes(struct drm_mode_set
*set
,
11158 struct intel_set_config
*config
)
11161 /* We should be able to check here if the fb has the same properties
11162 * and then just flip_or_move it */
11163 if (is_crtc_connector_off(set
)) {
11164 config
->mode_changed
= true;
11165 } else if (set
->crtc
->primary
->fb
!= set
->fb
) {
11167 * If we have no fb, we can only flip as long as the crtc is
11168 * active, otherwise we need a full mode set. The crtc may
11169 * be active if we've only disabled the primary plane, or
11170 * in fastboot situations.
11172 if (set
->crtc
->primary
->fb
== NULL
) {
11173 struct intel_crtc
*intel_crtc
=
11174 to_intel_crtc(set
->crtc
);
11176 if (intel_crtc
->active
) {
11177 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11178 config
->fb_changed
= true;
11180 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11181 config
->mode_changed
= true;
11183 } else if (set
->fb
== NULL
) {
11184 config
->mode_changed
= true;
11185 } else if (set
->fb
->pixel_format
!=
11186 set
->crtc
->primary
->fb
->pixel_format
) {
11187 config
->mode_changed
= true;
11189 config
->fb_changed
= true;
11193 if (set
->fb
&& (set
->x
!= set
->crtc
->x
|| set
->y
!= set
->crtc
->y
))
11194 config
->fb_changed
= true;
11196 if (set
->mode
&& !drm_mode_equal(set
->mode
, &set
->crtc
->mode
)) {
11197 DRM_DEBUG_KMS("modes are different, full mode set\n");
11198 drm_mode_debug_printmodeline(&set
->crtc
->mode
);
11199 drm_mode_debug_printmodeline(set
->mode
);
11200 config
->mode_changed
= true;
11203 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11204 set
->crtc
->base
.id
, config
->mode_changed
, config
->fb_changed
);
11208 intel_modeset_stage_output_state(struct drm_device
*dev
,
11209 struct drm_mode_set
*set
,
11210 struct intel_set_config
*config
)
11212 struct intel_connector
*connector
;
11213 struct intel_encoder
*encoder
;
11214 struct intel_crtc
*crtc
;
11217 /* The upper layers ensure that we either disable a crtc or have a list
11218 * of connectors. For paranoia, double-check this. */
11219 WARN_ON(!set
->fb
&& (set
->num_connectors
!= 0));
11220 WARN_ON(set
->fb
&& (set
->num_connectors
== 0));
11222 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11224 /* Otherwise traverse passed in connector list and get encoders
11226 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11227 if (set
->connectors
[ro
] == &connector
->base
) {
11228 connector
->new_encoder
= intel_find_encoder(connector
, to_intel_crtc(set
->crtc
)->pipe
);
11233 /* If we disable the crtc, disable all its connectors. Also, if
11234 * the connector is on the changing crtc but not on the new
11235 * connector list, disable it. */
11236 if ((!set
->fb
|| ro
== set
->num_connectors
) &&
11237 connector
->base
.encoder
&&
11238 connector
->base
.encoder
->crtc
== set
->crtc
) {
11239 connector
->new_encoder
= NULL
;
11241 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11242 connector
->base
.base
.id
,
11243 connector
->base
.name
);
11247 if (&connector
->new_encoder
->base
!= connector
->base
.encoder
) {
11248 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11249 config
->mode_changed
= true;
11252 /* connector->new_encoder is now updated for all connectors. */
11254 /* Update crtc of enabled connectors. */
11255 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11257 struct drm_crtc
*new_crtc
;
11259 if (!connector
->new_encoder
)
11262 new_crtc
= connector
->new_encoder
->base
.crtc
;
11264 for (ro
= 0; ro
< set
->num_connectors
; ro
++) {
11265 if (set
->connectors
[ro
] == &connector
->base
)
11266 new_crtc
= set
->crtc
;
11269 /* Make sure the new CRTC will work with the encoder */
11270 if (!drm_encoder_crtc_ok(&connector
->new_encoder
->base
,
11274 connector
->new_encoder
->new_crtc
= to_intel_crtc(new_crtc
);
11276 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11277 connector
->base
.base
.id
,
11278 connector
->base
.name
,
11279 new_crtc
->base
.id
);
11282 /* Check for any encoders that needs to be disabled. */
11283 for_each_intel_encoder(dev
, encoder
) {
11284 int num_connectors
= 0;
11285 list_for_each_entry(connector
,
11286 &dev
->mode_config
.connector_list
,
11288 if (connector
->new_encoder
== encoder
) {
11289 WARN_ON(!connector
->new_encoder
->new_crtc
);
11294 if (num_connectors
== 0)
11295 encoder
->new_crtc
= NULL
;
11296 else if (num_connectors
> 1)
11299 /* Only now check for crtc changes so we don't miss encoders
11300 * that will be disabled. */
11301 if (&encoder
->new_crtc
->base
!= encoder
->base
.crtc
) {
11302 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11303 config
->mode_changed
= true;
11306 /* Now we've also updated encoder->new_crtc for all encoders. */
11307 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
11309 if (connector
->new_encoder
)
11310 if (connector
->new_encoder
!= connector
->encoder
)
11311 connector
->encoder
= connector
->new_encoder
;
11313 for_each_intel_crtc(dev
, crtc
) {
11314 crtc
->new_enabled
= false;
11316 for_each_intel_encoder(dev
, encoder
) {
11317 if (encoder
->new_crtc
== crtc
) {
11318 crtc
->new_enabled
= true;
11323 if (crtc
->new_enabled
!= crtc
->base
.enabled
) {
11324 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11325 crtc
->new_enabled
? "en" : "dis");
11326 config
->mode_changed
= true;
11329 if (crtc
->new_enabled
)
11330 crtc
->new_config
= &crtc
->config
;
11332 crtc
->new_config
= NULL
;
11338 static void disable_crtc_nofb(struct intel_crtc
*crtc
)
11340 struct drm_device
*dev
= crtc
->base
.dev
;
11341 struct intel_encoder
*encoder
;
11342 struct intel_connector
*connector
;
11344 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11345 pipe_name(crtc
->pipe
));
11347 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, base
.head
) {
11348 if (connector
->new_encoder
&&
11349 connector
->new_encoder
->new_crtc
== crtc
)
11350 connector
->new_encoder
= NULL
;
11353 for_each_intel_encoder(dev
, encoder
) {
11354 if (encoder
->new_crtc
== crtc
)
11355 encoder
->new_crtc
= NULL
;
11358 crtc
->new_enabled
= false;
11359 crtc
->new_config
= NULL
;
11362 static int intel_crtc_set_config(struct drm_mode_set
*set
)
11364 struct drm_device
*dev
;
11365 struct drm_mode_set save_set
;
11366 struct intel_set_config
*config
;
11370 BUG_ON(!set
->crtc
);
11371 BUG_ON(!set
->crtc
->helper_private
);
11373 /* Enforce sane interface api - has been abused by the fb helper. */
11374 BUG_ON(!set
->mode
&& set
->fb
);
11375 BUG_ON(set
->fb
&& set
->num_connectors
== 0);
11378 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11379 set
->crtc
->base
.id
, set
->fb
->base
.id
,
11380 (int)set
->num_connectors
, set
->x
, set
->y
);
11382 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set
->crtc
->base
.id
);
11385 dev
= set
->crtc
->dev
;
11388 config
= kzalloc(sizeof(*config
), GFP_KERNEL
);
11392 ret
= intel_set_config_save_state(dev
, config
);
11396 save_set
.crtc
= set
->crtc
;
11397 save_set
.mode
= &set
->crtc
->mode
;
11398 save_set
.x
= set
->crtc
->x
;
11399 save_set
.y
= set
->crtc
->y
;
11400 save_set
.fb
= set
->crtc
->primary
->fb
;
11402 /* Compute whether we need a full modeset, only an fb base update or no
11403 * change at all. In the future we might also check whether only the
11404 * mode changed, e.g. for LVDS where we only change the panel fitter in
11406 intel_set_config_compute_mode_changes(set
, config
);
11408 ret
= intel_modeset_stage_output_state(dev
, set
, config
);
11412 if (config
->mode_changed
) {
11413 ret
= intel_set_mode(set
->crtc
, set
->mode
,
11414 set
->x
, set
->y
, set
->fb
);
11415 } else if (config
->fb_changed
) {
11416 struct intel_crtc
*intel_crtc
= to_intel_crtc(set
->crtc
);
11418 intel_crtc_wait_for_pending_flips(set
->crtc
);
11420 ret
= intel_pipe_set_base(set
->crtc
,
11421 set
->x
, set
->y
, set
->fb
);
11424 * We need to make sure the primary plane is re-enabled if it
11425 * has previously been turned off.
11427 if (!intel_crtc
->primary_enabled
&& ret
== 0) {
11428 WARN_ON(!intel_crtc
->active
);
11429 intel_enable_primary_hw_plane(set
->crtc
->primary
, set
->crtc
);
11433 * In the fastboot case this may be our only check of the
11434 * state after boot. It would be better to only do it on
11435 * the first update, but we don't have a nice way of doing that
11436 * (and really, set_config isn't used much for high freq page
11437 * flipping, so increasing its cost here shouldn't be a big
11440 if (i915
.fastboot
&& ret
== 0)
11441 intel_modeset_check_state(set
->crtc
->dev
);
11445 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11446 set
->crtc
->base
.id
, ret
);
11448 intel_set_config_restore_state(dev
, config
);
11451 * HACK: if the pipe was on, but we didn't have a framebuffer,
11452 * force the pipe off to avoid oopsing in the modeset code
11453 * due to fb==NULL. This should only happen during boot since
11454 * we don't yet reconstruct the FB from the hardware state.
11456 if (to_intel_crtc(save_set
.crtc
)->new_enabled
&& !save_set
.fb
)
11457 disable_crtc_nofb(to_intel_crtc(save_set
.crtc
));
11459 /* Try to restore the config */
11460 if (config
->mode_changed
&&
11461 intel_set_mode(save_set
.crtc
, save_set
.mode
,
11462 save_set
.x
, save_set
.y
, save_set
.fb
))
11463 DRM_ERROR("failed to restore config after modeset failure\n");
11467 intel_set_config_free(config
);
11471 static const struct drm_crtc_funcs intel_crtc_funcs
= {
11472 .gamma_set
= intel_crtc_gamma_set
,
11473 .set_config
= intel_crtc_set_config
,
11474 .destroy
= intel_crtc_destroy
,
11475 .page_flip
= intel_crtc_page_flip
,
11478 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
11479 struct intel_shared_dpll
*pll
,
11480 struct intel_dpll_hw_state
*hw_state
)
11484 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
11487 val
= I915_READ(PCH_DPLL(pll
->id
));
11488 hw_state
->dpll
= val
;
11489 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
11490 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
11492 return val
& DPLL_VCO_ENABLE
;
11495 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
11496 struct intel_shared_dpll
*pll
)
11498 I915_WRITE(PCH_FP0(pll
->id
), pll
->hw_state
.fp0
);
11499 I915_WRITE(PCH_FP1(pll
->id
), pll
->hw_state
.fp1
);
11502 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
11503 struct intel_shared_dpll
*pll
)
11505 /* PCH refclock must be enabled first */
11506 ibx_assert_pch_refclk_enabled(dev_priv
);
11508 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11510 /* Wait for the clocks to stabilize. */
11511 POSTING_READ(PCH_DPLL(pll
->id
));
11514 /* The pixel multiplier can only be updated once the
11515 * DPLL is enabled and the clocks are stable.
11517 * So write it again.
11519 I915_WRITE(PCH_DPLL(pll
->id
), pll
->hw_state
.dpll
);
11520 POSTING_READ(PCH_DPLL(pll
->id
));
11524 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
11525 struct intel_shared_dpll
*pll
)
11527 struct drm_device
*dev
= dev_priv
->dev
;
11528 struct intel_crtc
*crtc
;
11530 /* Make sure no transcoder isn't still depending on us. */
11531 for_each_intel_crtc(dev
, crtc
) {
11532 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
11533 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
11536 I915_WRITE(PCH_DPLL(pll
->id
), 0);
11537 POSTING_READ(PCH_DPLL(pll
->id
));
11541 static char *ibx_pch_dpll_names
[] = {
11546 static void ibx_pch_dpll_init(struct drm_device
*dev
)
11548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11551 dev_priv
->num_shared_dpll
= 2;
11553 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
11554 dev_priv
->shared_dplls
[i
].id
= i
;
11555 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
11556 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
11557 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
11558 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
11559 dev_priv
->shared_dplls
[i
].get_hw_state
=
11560 ibx_pch_dpll_get_hw_state
;
11564 static void intel_shared_dpll_init(struct drm_device
*dev
)
11566 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11569 intel_ddi_pll_init(dev
);
11570 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
11571 ibx_pch_dpll_init(dev
);
11573 dev_priv
->num_shared_dpll
= 0;
11575 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
11579 intel_primary_plane_disable(struct drm_plane
*plane
)
11581 struct drm_device
*dev
= plane
->dev
;
11582 struct intel_crtc
*intel_crtc
;
11587 BUG_ON(!plane
->crtc
);
11589 intel_crtc
= to_intel_crtc(plane
->crtc
);
11592 * Even though we checked plane->fb above, it's still possible that
11593 * the primary plane has been implicitly disabled because the crtc
11594 * coordinates given weren't visible, or because we detected
11595 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11596 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11597 * In either case, we need to unpin the FB and let the fb pointer get
11598 * updated, but otherwise we don't need to touch the hardware.
11600 if (!intel_crtc
->primary_enabled
)
11601 goto disable_unpin
;
11603 intel_crtc_wait_for_pending_flips(plane
->crtc
);
11604 intel_disable_primary_hw_plane(plane
, plane
->crtc
);
11607 mutex_lock(&dev
->struct_mutex
);
11608 i915_gem_track_fb(intel_fb_obj(plane
->fb
), NULL
,
11609 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11610 intel_unpin_fb_obj(intel_fb_obj(plane
->fb
));
11611 mutex_unlock(&dev
->struct_mutex
);
11618 intel_primary_plane_setplane(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11619 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11620 unsigned int crtc_w
, unsigned int crtc_h
,
11621 uint32_t src_x
, uint32_t src_y
,
11622 uint32_t src_w
, uint32_t src_h
)
11624 struct drm_device
*dev
= crtc
->dev
;
11625 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11626 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11627 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11628 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
11629 struct drm_rect dest
= {
11630 /* integer pixels */
11633 .x2
= crtc_x
+ crtc_w
,
11634 .y2
= crtc_y
+ crtc_h
,
11636 struct drm_rect src
= {
11637 /* 16.16 fixed point */
11640 .x2
= src_x
+ src_w
,
11641 .y2
= src_y
+ src_h
,
11643 const struct drm_rect clip
= {
11644 /* integer pixels */
11645 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11646 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11649 int crtc_x
, crtc_y
;
11650 unsigned int crtc_w
, crtc_h
;
11651 uint32_t src_x
, src_y
, src_w
, src_h
;
11662 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11666 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11667 &src
, &dest
, &clip
,
11668 DRM_PLANE_HELPER_NO_SCALING
,
11669 DRM_PLANE_HELPER_NO_SCALING
,
11670 false, true, &visible
);
11676 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11677 * updating the fb pointer, and returning without touching the
11678 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11679 * turn on the display with all planes setup as desired.
11681 if (!crtc
->enabled
) {
11682 mutex_lock(&dev
->struct_mutex
);
11685 * If we already called setplane while the crtc was disabled,
11686 * we may have an fb pinned; unpin it.
11689 intel_unpin_fb_obj(old_obj
);
11691 i915_gem_track_fb(old_obj
, obj
,
11692 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11694 /* Pin and return without programming hardware */
11695 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11696 mutex_unlock(&dev
->struct_mutex
);
11701 intel_crtc_wait_for_pending_flips(crtc
);
11704 * If clipping results in a non-visible primary plane, we'll disable
11705 * the primary plane. Note that this is a bit different than what
11706 * happens if userspace explicitly disables the plane by passing fb=0
11707 * because plane->fb still gets set and pinned.
11710 mutex_lock(&dev
->struct_mutex
);
11713 * Try to pin the new fb first so that we can bail out if we
11716 if (plane
->fb
!= fb
) {
11717 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, NULL
);
11719 mutex_unlock(&dev
->struct_mutex
);
11724 i915_gem_track_fb(old_obj
, obj
,
11725 INTEL_FRONTBUFFER_PRIMARY(intel_crtc
->pipe
));
11727 if (intel_crtc
->primary_enabled
)
11728 intel_disable_primary_hw_plane(plane
, crtc
);
11731 if (plane
->fb
!= fb
)
11733 intel_unpin_fb_obj(old_obj
);
11735 mutex_unlock(&dev
->struct_mutex
);
11738 if (intel_crtc
&& intel_crtc
->active
&&
11739 intel_crtc
->primary_enabled
) {
11741 * FBC does not work on some platforms for rotated
11742 * planes, so disable it when rotation is not 0 and
11743 * update it when rotation is set back to 0.
11745 * FIXME: This is redundant with the fbc update done in
11746 * the primary plane enable function except that that
11747 * one is done too late. We eventually need to unify
11750 if (INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11751 dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
11752 intel_plane
->rotation
!= BIT(DRM_ROTATE_0
)) {
11753 intel_disable_fbc(dev
);
11756 ret
= intel_pipe_set_base(crtc
, src
.x1
, src
.y1
, fb
);
11760 if (!intel_crtc
->primary_enabled
)
11761 intel_enable_primary_hw_plane(plane
, crtc
);
11764 intel_plane
->crtc_x
= orig
.crtc_x
;
11765 intel_plane
->crtc_y
= orig
.crtc_y
;
11766 intel_plane
->crtc_w
= orig
.crtc_w
;
11767 intel_plane
->crtc_h
= orig
.crtc_h
;
11768 intel_plane
->src_x
= orig
.src_x
;
11769 intel_plane
->src_y
= orig
.src_y
;
11770 intel_plane
->src_w
= orig
.src_w
;
11771 intel_plane
->src_h
= orig
.src_h
;
11772 intel_plane
->obj
= obj
;
11777 /* Common destruction function for both primary and cursor planes */
11778 static void intel_plane_destroy(struct drm_plane
*plane
)
11780 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
11781 drm_plane_cleanup(plane
);
11782 kfree(intel_plane
);
11785 static const struct drm_plane_funcs intel_primary_plane_funcs
= {
11786 .update_plane
= intel_primary_plane_setplane
,
11787 .disable_plane
= intel_primary_plane_disable
,
11788 .destroy
= intel_plane_destroy
,
11789 .set_property
= intel_plane_set_property
11792 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
11795 struct intel_plane
*primary
;
11796 const uint32_t *intel_primary_formats
;
11799 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
11800 if (primary
== NULL
)
11803 primary
->can_scale
= false;
11804 primary
->max_downscale
= 1;
11805 primary
->pipe
= pipe
;
11806 primary
->plane
= pipe
;
11807 primary
->rotation
= BIT(DRM_ROTATE_0
);
11808 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
11809 primary
->plane
= !pipe
;
11811 if (INTEL_INFO(dev
)->gen
<= 3) {
11812 intel_primary_formats
= intel_primary_formats_gen2
;
11813 num_formats
= ARRAY_SIZE(intel_primary_formats_gen2
);
11815 intel_primary_formats
= intel_primary_formats_gen4
;
11816 num_formats
= ARRAY_SIZE(intel_primary_formats_gen4
);
11819 drm_universal_plane_init(dev
, &primary
->base
, 0,
11820 &intel_primary_plane_funcs
,
11821 intel_primary_formats
, num_formats
,
11822 DRM_PLANE_TYPE_PRIMARY
);
11824 if (INTEL_INFO(dev
)->gen
>= 4) {
11825 if (!dev
->mode_config
.rotation_property
)
11826 dev
->mode_config
.rotation_property
=
11827 drm_mode_create_rotation_property(dev
,
11828 BIT(DRM_ROTATE_0
) |
11829 BIT(DRM_ROTATE_180
));
11830 if (dev
->mode_config
.rotation_property
)
11831 drm_object_attach_property(&primary
->base
.base
,
11832 dev
->mode_config
.rotation_property
,
11833 primary
->rotation
);
11836 return &primary
->base
;
11840 intel_cursor_plane_disable(struct drm_plane
*plane
)
11845 BUG_ON(!plane
->crtc
);
11847 return intel_crtc_cursor_set_obj(plane
->crtc
, NULL
, 0, 0);
11851 intel_cursor_plane_update(struct drm_plane
*plane
, struct drm_crtc
*crtc
,
11852 struct drm_framebuffer
*fb
, int crtc_x
, int crtc_y
,
11853 unsigned int crtc_w
, unsigned int crtc_h
,
11854 uint32_t src_x
, uint32_t src_y
,
11855 uint32_t src_w
, uint32_t src_h
)
11857 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11858 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
11859 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11860 struct drm_rect dest
= {
11861 /* integer pixels */
11864 .x2
= crtc_x
+ crtc_w
,
11865 .y2
= crtc_y
+ crtc_h
,
11867 struct drm_rect src
= {
11868 /* 16.16 fixed point */
11871 .x2
= src_x
+ src_w
,
11872 .y2
= src_y
+ src_h
,
11874 const struct drm_rect clip
= {
11875 /* integer pixels */
11876 .x2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_w
: 0,
11877 .y2
= intel_crtc
->active
? intel_crtc
->config
.pipe_src_h
: 0,
11882 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
,
11883 &src
, &dest
, &clip
,
11884 DRM_PLANE_HELPER_NO_SCALING
,
11885 DRM_PLANE_HELPER_NO_SCALING
,
11886 true, true, &visible
);
11890 crtc
->cursor_x
= crtc_x
;
11891 crtc
->cursor_y
= crtc_y
;
11892 if (fb
!= crtc
->cursor
->fb
) {
11893 return intel_crtc_cursor_set_obj(crtc
, obj
, crtc_w
, crtc_h
);
11895 intel_crtc_update_cursor(crtc
, visible
);
11897 intel_frontbuffer_flip(crtc
->dev
,
11898 INTEL_FRONTBUFFER_CURSOR(intel_crtc
->pipe
));
11903 static const struct drm_plane_funcs intel_cursor_plane_funcs
= {
11904 .update_plane
= intel_cursor_plane_update
,
11905 .disable_plane
= intel_cursor_plane_disable
,
11906 .destroy
= intel_plane_destroy
,
11909 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
11912 struct intel_plane
*cursor
;
11914 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
11915 if (cursor
== NULL
)
11918 cursor
->can_scale
= false;
11919 cursor
->max_downscale
= 1;
11920 cursor
->pipe
= pipe
;
11921 cursor
->plane
= pipe
;
11923 drm_universal_plane_init(dev
, &cursor
->base
, 0,
11924 &intel_cursor_plane_funcs
,
11925 intel_cursor_formats
,
11926 ARRAY_SIZE(intel_cursor_formats
),
11927 DRM_PLANE_TYPE_CURSOR
);
11928 return &cursor
->base
;
11931 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
11933 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11934 struct intel_crtc
*intel_crtc
;
11935 struct drm_plane
*primary
= NULL
;
11936 struct drm_plane
*cursor
= NULL
;
11939 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
11940 if (intel_crtc
== NULL
)
11943 primary
= intel_primary_plane_create(dev
, pipe
);
11947 cursor
= intel_cursor_plane_create(dev
, pipe
);
11951 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
11952 cursor
, &intel_crtc_funcs
);
11956 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
11957 for (i
= 0; i
< 256; i
++) {
11958 intel_crtc
->lut_r
[i
] = i
;
11959 intel_crtc
->lut_g
[i
] = i
;
11960 intel_crtc
->lut_b
[i
] = i
;
11964 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11965 * is hooked to pipe B. Hence we want plane A feeding pipe B.
11967 intel_crtc
->pipe
= pipe
;
11968 intel_crtc
->plane
= pipe
;
11969 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
11970 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11971 intel_crtc
->plane
= !pipe
;
11974 intel_crtc
->cursor_base
= ~0;
11975 intel_crtc
->cursor_cntl
= ~0;
11976 intel_crtc
->cursor_size
= ~0;
11978 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
11979 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
11980 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
11981 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
11983 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
11985 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
11990 drm_plane_cleanup(primary
);
11992 drm_plane_cleanup(cursor
);
11996 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
11998 struct drm_encoder
*encoder
= connector
->base
.encoder
;
11999 struct drm_device
*dev
= connector
->base
.dev
;
12001 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
12004 return INVALID_PIPE
;
12006 return to_intel_crtc(encoder
->crtc
)->pipe
;
12009 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
12010 struct drm_file
*file
)
12012 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
12013 struct drm_crtc
*drmmode_crtc
;
12014 struct intel_crtc
*crtc
;
12016 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
12019 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
12021 if (!drmmode_crtc
) {
12022 DRM_ERROR("no such CRTC id\n");
12026 crtc
= to_intel_crtc(drmmode_crtc
);
12027 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
12032 static int intel_encoder_clones(struct intel_encoder
*encoder
)
12034 struct drm_device
*dev
= encoder
->base
.dev
;
12035 struct intel_encoder
*source_encoder
;
12036 int index_mask
= 0;
12039 for_each_intel_encoder(dev
, source_encoder
) {
12040 if (encoders_cloneable(encoder
, source_encoder
))
12041 index_mask
|= (1 << entry
);
12049 static bool has_edp_a(struct drm_device
*dev
)
12051 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12053 if (!IS_MOBILE(dev
))
12056 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
12059 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
12065 const char *intel_output_name(int output
)
12067 static const char *names
[] = {
12068 [INTEL_OUTPUT_UNUSED
] = "Unused",
12069 [INTEL_OUTPUT_ANALOG
] = "Analog",
12070 [INTEL_OUTPUT_DVO
] = "DVO",
12071 [INTEL_OUTPUT_SDVO
] = "SDVO",
12072 [INTEL_OUTPUT_LVDS
] = "LVDS",
12073 [INTEL_OUTPUT_TVOUT
] = "TV",
12074 [INTEL_OUTPUT_HDMI
] = "HDMI",
12075 [INTEL_OUTPUT_DISPLAYPORT
] = "DisplayPort",
12076 [INTEL_OUTPUT_EDP
] = "eDP",
12077 [INTEL_OUTPUT_DSI
] = "DSI",
12078 [INTEL_OUTPUT_UNKNOWN
] = "Unknown",
12081 if (output
< 0 || output
>= ARRAY_SIZE(names
) || !names
[output
])
12084 return names
[output
];
12087 static bool intel_crt_present(struct drm_device
*dev
)
12089 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12094 if (IS_CHERRYVIEW(dev
))
12097 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
12103 static void intel_setup_outputs(struct drm_device
*dev
)
12105 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12106 struct intel_encoder
*encoder
;
12107 bool dpd_is_edp
= false;
12109 intel_lvds_init(dev
);
12111 if (intel_crt_present(dev
))
12112 intel_crt_init(dev
);
12114 if (HAS_DDI(dev
)) {
12117 /* Haswell uses DDI functions to detect digital outputs */
12118 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
12119 /* DDI A only supports eDP */
12121 intel_ddi_init(dev
, PORT_A
);
12123 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12125 found
= I915_READ(SFUSE_STRAP
);
12127 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
12128 intel_ddi_init(dev
, PORT_B
);
12129 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
12130 intel_ddi_init(dev
, PORT_C
);
12131 if (found
& SFUSE_STRAP_DDID_DETECTED
)
12132 intel_ddi_init(dev
, PORT_D
);
12133 } else if (HAS_PCH_SPLIT(dev
)) {
12135 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
12137 if (has_edp_a(dev
))
12138 intel_dp_init(dev
, DP_A
, PORT_A
);
12140 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
12141 /* PCH SDVOB multiplex with HDMIB */
12142 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
12144 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
12145 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
12146 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
12149 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
12150 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
12152 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
12153 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
12155 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
12156 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
12158 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
12159 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
12160 } else if (IS_VALLEYVIEW(dev
)) {
12161 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIB
) & SDVO_DETECTED
) {
12162 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIB
,
12164 if (I915_READ(VLV_DISPLAY_BASE
+ DP_B
) & DP_DETECTED
)
12165 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_B
, PORT_B
);
12168 if (I915_READ(VLV_DISPLAY_BASE
+ GEN4_HDMIC
) & SDVO_DETECTED
) {
12169 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ GEN4_HDMIC
,
12171 if (I915_READ(VLV_DISPLAY_BASE
+ DP_C
) & DP_DETECTED
)
12172 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_C
, PORT_C
);
12175 if (IS_CHERRYVIEW(dev
)) {
12176 if (I915_READ(VLV_DISPLAY_BASE
+ CHV_HDMID
) & SDVO_DETECTED
) {
12177 intel_hdmi_init(dev
, VLV_DISPLAY_BASE
+ CHV_HDMID
,
12179 if (I915_READ(VLV_DISPLAY_BASE
+ DP_D
) & DP_DETECTED
)
12180 intel_dp_init(dev
, VLV_DISPLAY_BASE
+ DP_D
, PORT_D
);
12184 intel_dsi_init(dev
);
12185 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
12186 bool found
= false;
12188 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12189 DRM_DEBUG_KMS("probing SDVOB\n");
12190 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
12191 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
12192 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12193 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
12196 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
))
12197 intel_dp_init(dev
, DP_B
, PORT_B
);
12200 /* Before G4X SDVOC doesn't have its own detect register */
12202 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
12203 DRM_DEBUG_KMS("probing SDVOC\n");
12204 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
12207 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
12209 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
12210 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12211 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
12213 if (SUPPORTS_INTEGRATED_DP(dev
))
12214 intel_dp_init(dev
, DP_C
, PORT_C
);
12217 if (SUPPORTS_INTEGRATED_DP(dev
) &&
12218 (I915_READ(DP_D
) & DP_DETECTED
))
12219 intel_dp_init(dev
, DP_D
, PORT_D
);
12220 } else if (IS_GEN2(dev
))
12221 intel_dvo_init(dev
);
12223 if (SUPPORTS_TV(dev
))
12224 intel_tv_init(dev
);
12226 intel_edp_psr_init(dev
);
12228 for_each_intel_encoder(dev
, encoder
) {
12229 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
12230 encoder
->base
.possible_clones
=
12231 intel_encoder_clones(encoder
);
12234 intel_init_pch_refclk(dev
);
12236 drm_helper_move_panel_connectors_to_head(dev
);
12239 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
12241 struct drm_device
*dev
= fb
->dev
;
12242 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12244 drm_framebuffer_cleanup(fb
);
12245 mutex_lock(&dev
->struct_mutex
);
12246 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
12247 drm_gem_object_unreference(&intel_fb
->obj
->base
);
12248 mutex_unlock(&dev
->struct_mutex
);
12252 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
12253 struct drm_file
*file
,
12254 unsigned int *handle
)
12256 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
12257 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
12259 return drm_gem_handle_create(file
, &obj
->base
, handle
);
12262 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
12263 .destroy
= intel_user_framebuffer_destroy
,
12264 .create_handle
= intel_user_framebuffer_create_handle
,
12267 static int intel_framebuffer_init(struct drm_device
*dev
,
12268 struct intel_framebuffer
*intel_fb
,
12269 struct drm_mode_fb_cmd2
*mode_cmd
,
12270 struct drm_i915_gem_object
*obj
)
12272 int aligned_height
;
12276 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
12278 if (obj
->tiling_mode
== I915_TILING_Y
) {
12279 DRM_DEBUG("hardware does not support tiling Y\n");
12283 if (mode_cmd
->pitches
[0] & 63) {
12284 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12285 mode_cmd
->pitches
[0]);
12289 if (INTEL_INFO(dev
)->gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
12290 pitch_limit
= 32*1024;
12291 } else if (INTEL_INFO(dev
)->gen
>= 4) {
12292 if (obj
->tiling_mode
)
12293 pitch_limit
= 16*1024;
12295 pitch_limit
= 32*1024;
12296 } else if (INTEL_INFO(dev
)->gen
>= 3) {
12297 if (obj
->tiling_mode
)
12298 pitch_limit
= 8*1024;
12300 pitch_limit
= 16*1024;
12302 /* XXX DSPC is limited to 4k tiled */
12303 pitch_limit
= 8*1024;
12305 if (mode_cmd
->pitches
[0] > pitch_limit
) {
12306 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12307 obj
->tiling_mode
? "tiled" : "linear",
12308 mode_cmd
->pitches
[0], pitch_limit
);
12312 if (obj
->tiling_mode
!= I915_TILING_NONE
&&
12313 mode_cmd
->pitches
[0] != obj
->stride
) {
12314 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12315 mode_cmd
->pitches
[0], obj
->stride
);
12319 /* Reject formats not supported by any plane early. */
12320 switch (mode_cmd
->pixel_format
) {
12321 case DRM_FORMAT_C8
:
12322 case DRM_FORMAT_RGB565
:
12323 case DRM_FORMAT_XRGB8888
:
12324 case DRM_FORMAT_ARGB8888
:
12326 case DRM_FORMAT_XRGB1555
:
12327 case DRM_FORMAT_ARGB1555
:
12328 if (INTEL_INFO(dev
)->gen
> 3) {
12329 DRM_DEBUG("unsupported pixel format: %s\n",
12330 drm_get_format_name(mode_cmd
->pixel_format
));
12334 case DRM_FORMAT_XBGR8888
:
12335 case DRM_FORMAT_ABGR8888
:
12336 case DRM_FORMAT_XRGB2101010
:
12337 case DRM_FORMAT_ARGB2101010
:
12338 case DRM_FORMAT_XBGR2101010
:
12339 case DRM_FORMAT_ABGR2101010
:
12340 if (INTEL_INFO(dev
)->gen
< 4) {
12341 DRM_DEBUG("unsupported pixel format: %s\n",
12342 drm_get_format_name(mode_cmd
->pixel_format
));
12346 case DRM_FORMAT_YUYV
:
12347 case DRM_FORMAT_UYVY
:
12348 case DRM_FORMAT_YVYU
:
12349 case DRM_FORMAT_VYUY
:
12350 if (INTEL_INFO(dev
)->gen
< 5) {
12351 DRM_DEBUG("unsupported pixel format: %s\n",
12352 drm_get_format_name(mode_cmd
->pixel_format
));
12357 DRM_DEBUG("unsupported pixel format: %s\n",
12358 drm_get_format_name(mode_cmd
->pixel_format
));
12362 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12363 if (mode_cmd
->offsets
[0] != 0)
12366 aligned_height
= intel_align_height(dev
, mode_cmd
->height
,
12368 /* FIXME drm helper for size checks (especially planar formats)? */
12369 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
12372 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
12373 intel_fb
->obj
= obj
;
12374 intel_fb
->obj
->framebuffer_references
++;
12376 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
12378 DRM_ERROR("framebuffer init failed %d\n", ret
);
12385 static struct drm_framebuffer
*
12386 intel_user_framebuffer_create(struct drm_device
*dev
,
12387 struct drm_file
*filp
,
12388 struct drm_mode_fb_cmd2
*mode_cmd
)
12390 struct drm_i915_gem_object
*obj
;
12392 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
12393 mode_cmd
->handles
[0]));
12394 if (&obj
->base
== NULL
)
12395 return ERR_PTR(-ENOENT
);
12397 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
12400 #ifndef CONFIG_DRM_I915_FBDEV
12401 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
12406 static const struct drm_mode_config_funcs intel_mode_funcs
= {
12407 .fb_create
= intel_user_framebuffer_create
,
12408 .output_poll_changed
= intel_fbdev_output_poll_changed
,
12411 /* Set up chip specific display functions */
12412 static void intel_init_display(struct drm_device
*dev
)
12414 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12416 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
12417 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
12418 else if (IS_CHERRYVIEW(dev
))
12419 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
12420 else if (IS_VALLEYVIEW(dev
))
12421 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
12422 else if (IS_PINEVIEW(dev
))
12423 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
12425 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
12427 if (HAS_DDI(dev
)) {
12428 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
12429 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12430 dev_priv
->display
.crtc_mode_set
= haswell_crtc_mode_set
;
12431 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
12432 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
12433 dev_priv
->display
.off
= ironlake_crtc_off
;
12434 dev_priv
->display
.update_primary_plane
=
12435 ironlake_update_primary_plane
;
12436 } else if (HAS_PCH_SPLIT(dev
)) {
12437 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
12438 dev_priv
->display
.get_plane_config
= ironlake_get_plane_config
;
12439 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
12440 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
12441 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
12442 dev_priv
->display
.off
= ironlake_crtc_off
;
12443 dev_priv
->display
.update_primary_plane
=
12444 ironlake_update_primary_plane
;
12445 } else if (IS_VALLEYVIEW(dev
)) {
12446 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12447 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12448 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12449 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
12450 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12451 dev_priv
->display
.off
= i9xx_crtc_off
;
12452 dev_priv
->display
.update_primary_plane
=
12453 i9xx_update_primary_plane
;
12455 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
12456 dev_priv
->display
.get_plane_config
= i9xx_get_plane_config
;
12457 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
12458 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
12459 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
12460 dev_priv
->display
.off
= i9xx_crtc_off
;
12461 dev_priv
->display
.update_primary_plane
=
12462 i9xx_update_primary_plane
;
12465 /* Returns the core display clock speed */
12466 if (IS_VALLEYVIEW(dev
))
12467 dev_priv
->display
.get_display_clock_speed
=
12468 valleyview_get_display_clock_speed
;
12469 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
12470 dev_priv
->display
.get_display_clock_speed
=
12471 i945_get_display_clock_speed
;
12472 else if (IS_I915G(dev
))
12473 dev_priv
->display
.get_display_clock_speed
=
12474 i915_get_display_clock_speed
;
12475 else if (IS_I945GM(dev
) || IS_845G(dev
))
12476 dev_priv
->display
.get_display_clock_speed
=
12477 i9xx_misc_get_display_clock_speed
;
12478 else if (IS_PINEVIEW(dev
))
12479 dev_priv
->display
.get_display_clock_speed
=
12480 pnv_get_display_clock_speed
;
12481 else if (IS_I915GM(dev
))
12482 dev_priv
->display
.get_display_clock_speed
=
12483 i915gm_get_display_clock_speed
;
12484 else if (IS_I865G(dev
))
12485 dev_priv
->display
.get_display_clock_speed
=
12486 i865_get_display_clock_speed
;
12487 else if (IS_I85X(dev
))
12488 dev_priv
->display
.get_display_clock_speed
=
12489 i855_get_display_clock_speed
;
12490 else /* 852, 830 */
12491 dev_priv
->display
.get_display_clock_speed
=
12492 i830_get_display_clock_speed
;
12495 dev_priv
->display
.write_eld
= g4x_write_eld
;
12496 } else if (IS_GEN5(dev
)) {
12497 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
12498 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12499 } else if (IS_GEN6(dev
)) {
12500 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
12501 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12502 dev_priv
->display
.modeset_global_resources
=
12503 snb_modeset_global_resources
;
12504 } else if (IS_IVYBRIDGE(dev
)) {
12505 /* FIXME: detect B0+ stepping and use auto training */
12506 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
12507 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12508 dev_priv
->display
.modeset_global_resources
=
12509 ivb_modeset_global_resources
;
12510 } else if (IS_HASWELL(dev
) || IS_GEN8(dev
)) {
12511 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
12512 dev_priv
->display
.write_eld
= haswell_write_eld
;
12513 dev_priv
->display
.modeset_global_resources
=
12514 haswell_modeset_global_resources
;
12515 } else if (IS_VALLEYVIEW(dev
)) {
12516 dev_priv
->display
.modeset_global_resources
=
12517 valleyview_modeset_global_resources
;
12518 dev_priv
->display
.write_eld
= ironlake_write_eld
;
12521 /* Default just returns -ENODEV to indicate unsupported */
12522 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
12524 switch (INTEL_INFO(dev
)->gen
) {
12526 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
12530 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
12535 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
12539 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
12542 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12543 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
12547 intel_panel_init_backlight_funcs(dev
);
12551 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12552 * resume, or other times. This quirk makes sure that's the case for
12553 * affected systems.
12555 static void quirk_pipea_force(struct drm_device
*dev
)
12557 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12559 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
12560 DRM_INFO("applying pipe a force quirk\n");
12564 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12566 static void quirk_ssc_force_disable(struct drm_device
*dev
)
12568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12569 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
12570 DRM_INFO("applying lvds SSC disable quirk\n");
12574 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12577 static void quirk_invert_brightness(struct drm_device
*dev
)
12579 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12580 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
12581 DRM_INFO("applying inverted panel brightness quirk\n");
12584 /* Some VBT's incorrectly indicate no backlight is present */
12585 static void quirk_backlight_present(struct drm_device
*dev
)
12587 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12588 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
12589 DRM_INFO("applying backlight present quirk\n");
12592 struct intel_quirk
{
12594 int subsystem_vendor
;
12595 int subsystem_device
;
12596 void (*hook
)(struct drm_device
*dev
);
12599 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12600 struct intel_dmi_quirk
{
12601 void (*hook
)(struct drm_device
*dev
);
12602 const struct dmi_system_id (*dmi_id_list
)[];
12605 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
12607 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
12611 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
12613 .dmi_id_list
= &(const struct dmi_system_id
[]) {
12615 .callback
= intel_dmi_reverse_brightness
,
12616 .ident
= "NCR Corporation",
12617 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
12618 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
12621 { } /* terminating entry */
12623 .hook
= quirk_invert_brightness
,
12627 static struct intel_quirk intel_quirks
[] = {
12628 /* HP Mini needs pipe A force quirk (LP: #322104) */
12629 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
12631 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12632 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
12634 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12635 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
12637 /* Lenovo U160 cannot use SSC on LVDS */
12638 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
12640 /* Sony Vaio Y cannot use SSC on LVDS */
12641 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
12643 /* Acer Aspire 5734Z must invert backlight brightness */
12644 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
12646 /* Acer/eMachines G725 */
12647 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
12649 /* Acer/eMachines e725 */
12650 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
12652 /* Acer/Packard Bell NCL20 */
12653 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
12655 /* Acer Aspire 4736Z */
12656 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
12658 /* Acer Aspire 5336 */
12659 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
12661 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12662 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
12664 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12665 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
12667 /* HP Chromebook 14 (Celeron 2955U) */
12668 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
12671 static void intel_init_quirks(struct drm_device
*dev
)
12673 struct pci_dev
*d
= dev
->pdev
;
12676 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
12677 struct intel_quirk
*q
= &intel_quirks
[i
];
12679 if (d
->device
== q
->device
&&
12680 (d
->subsystem_vendor
== q
->subsystem_vendor
||
12681 q
->subsystem_vendor
== PCI_ANY_ID
) &&
12682 (d
->subsystem_device
== q
->subsystem_device
||
12683 q
->subsystem_device
== PCI_ANY_ID
))
12686 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
12687 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
12688 intel_dmi_quirks
[i
].hook(dev
);
12692 /* Disable the VGA plane that we never use */
12693 static void i915_disable_vga(struct drm_device
*dev
)
12695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12697 u32 vga_reg
= i915_vgacntrl_reg(dev
);
12699 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12700 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12701 outb(SR01
, VGA_SR_INDEX
);
12702 sr1
= inb(VGA_SR_DATA
);
12703 outb(sr1
| 1<<5, VGA_SR_DATA
);
12704 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
12707 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
12708 POSTING_READ(vga_reg
);
12711 void intel_modeset_init_hw(struct drm_device
*dev
)
12713 intel_prepare_ddi(dev
);
12715 if (IS_VALLEYVIEW(dev
))
12716 vlv_update_cdclk(dev
);
12718 intel_init_clock_gating(dev
);
12720 intel_enable_gt_powersave(dev
);
12723 void intel_modeset_suspend_hw(struct drm_device
*dev
)
12725 intel_suspend_hw(dev
);
12728 void intel_modeset_init(struct drm_device
*dev
)
12730 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12733 struct intel_crtc
*crtc
;
12735 drm_mode_config_init(dev
);
12737 dev
->mode_config
.min_width
= 0;
12738 dev
->mode_config
.min_height
= 0;
12740 dev
->mode_config
.preferred_depth
= 24;
12741 dev
->mode_config
.prefer_shadow
= 1;
12743 dev
->mode_config
.funcs
= &intel_mode_funcs
;
12745 intel_init_quirks(dev
);
12747 intel_init_pm(dev
);
12749 if (INTEL_INFO(dev
)->num_pipes
== 0)
12752 intel_init_display(dev
);
12754 if (IS_GEN2(dev
)) {
12755 dev
->mode_config
.max_width
= 2048;
12756 dev
->mode_config
.max_height
= 2048;
12757 } else if (IS_GEN3(dev
)) {
12758 dev
->mode_config
.max_width
= 4096;
12759 dev
->mode_config
.max_height
= 4096;
12761 dev
->mode_config
.max_width
= 8192;
12762 dev
->mode_config
.max_height
= 8192;
12765 if (IS_845G(dev
) || IS_I865G(dev
)) {
12766 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
12767 dev
->mode_config
.cursor_height
= 1023;
12768 } else if (IS_GEN2(dev
)) {
12769 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
12770 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
12772 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
12773 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
12776 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
12778 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12779 INTEL_INFO(dev
)->num_pipes
,
12780 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
12782 for_each_pipe(dev_priv
, pipe
) {
12783 intel_crtc_init(dev
, pipe
);
12784 for_each_sprite(pipe
, sprite
) {
12785 ret
= intel_plane_init(dev
, pipe
, sprite
);
12787 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12788 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
12792 intel_init_dpio(dev
);
12794 intel_shared_dpll_init(dev
);
12796 /* Just disable it once at startup */
12797 i915_disable_vga(dev
);
12798 intel_setup_outputs(dev
);
12800 /* Just in case the BIOS is doing something questionable. */
12801 intel_disable_fbc(dev
);
12803 drm_modeset_lock_all(dev
);
12804 intel_modeset_setup_hw_state(dev
, false);
12805 drm_modeset_unlock_all(dev
);
12807 for_each_intel_crtc(dev
, crtc
) {
12812 * Note that reserving the BIOS fb up front prevents us
12813 * from stuffing other stolen allocations like the ring
12814 * on top. This prevents some ugliness at boot time, and
12815 * can even allow for smooth boot transitions if the BIOS
12816 * fb is large enough for the active pipe configuration.
12818 if (dev_priv
->display
.get_plane_config
) {
12819 dev_priv
->display
.get_plane_config(crtc
,
12820 &crtc
->plane_config
);
12822 * If the fb is shared between multiple heads, we'll
12823 * just get the first one.
12825 intel_find_plane_obj(crtc
, &crtc
->plane_config
);
12830 static void intel_enable_pipe_a(struct drm_device
*dev
)
12832 struct intel_connector
*connector
;
12833 struct drm_connector
*crt
= NULL
;
12834 struct intel_load_detect_pipe load_detect_temp
;
12835 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
12837 /* We can't just switch on the pipe A, we need to set things up with a
12838 * proper mode and output configuration. As a gross hack, enable pipe A
12839 * by enabling the load detect pipe once. */
12840 list_for_each_entry(connector
,
12841 &dev
->mode_config
.connector_list
,
12843 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
12844 crt
= &connector
->base
;
12852 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
12853 intel_release_load_detect_pipe(crt
, &load_detect_temp
);
12857 intel_check_plane_mapping(struct intel_crtc
*crtc
)
12859 struct drm_device
*dev
= crtc
->base
.dev
;
12860 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12863 if (INTEL_INFO(dev
)->num_pipes
== 1)
12866 reg
= DSPCNTR(!crtc
->plane
);
12867 val
= I915_READ(reg
);
12869 if ((val
& DISPLAY_PLANE_ENABLE
) &&
12870 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
12876 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
12878 struct drm_device
*dev
= crtc
->base
.dev
;
12879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12882 /* Clear any frame start delays used for debugging left by the BIOS */
12883 reg
= PIPECONF(crtc
->config
.cpu_transcoder
);
12884 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
12886 /* restore vblank interrupts to correct state */
12888 drm_vblank_on(dev
, crtc
->pipe
);
12890 drm_vblank_off(dev
, crtc
->pipe
);
12892 /* We need to sanitize the plane -> pipe mapping first because this will
12893 * disable the crtc (and hence change the state) if it is wrong. Note
12894 * that gen4+ has a fixed plane -> pipe mapping. */
12895 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
12896 struct intel_connector
*connector
;
12899 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12900 crtc
->base
.base
.id
);
12902 /* Pipe has the wrong plane attached and the plane is active.
12903 * Temporarily change the plane mapping and disable everything
12905 plane
= crtc
->plane
;
12906 crtc
->plane
= !plane
;
12907 crtc
->primary_enabled
= true;
12908 dev_priv
->display
.crtc_disable(&crtc
->base
);
12909 crtc
->plane
= plane
;
12911 /* ... and break all links. */
12912 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12914 if (connector
->encoder
->base
.crtc
!= &crtc
->base
)
12917 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
12918 connector
->base
.encoder
= NULL
;
12920 /* multiple connectors may have the same encoder:
12921 * handle them and break crtc link separately */
12922 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
12924 if (connector
->encoder
->base
.crtc
== &crtc
->base
) {
12925 connector
->encoder
->base
.crtc
= NULL
;
12926 connector
->encoder
->connectors_active
= false;
12929 WARN_ON(crtc
->active
);
12930 crtc
->base
.enabled
= false;
12933 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
12934 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
12935 /* BIOS forgot to enable pipe A, this mostly happens after
12936 * resume. Force-enable the pipe to fix this, the update_dpms
12937 * call below we restore the pipe to the right state, but leave
12938 * the required bits on. */
12939 intel_enable_pipe_a(dev
);
12942 /* Adjust the state of the output pipe according to whether we
12943 * have active connectors/encoders. */
12944 intel_crtc_update_dpms(&crtc
->base
);
12946 if (crtc
->active
!= crtc
->base
.enabled
) {
12947 struct intel_encoder
*encoder
;
12949 /* This can happen either due to bugs in the get_hw_state
12950 * functions or because the pipe is force-enabled due to the
12952 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12953 crtc
->base
.base
.id
,
12954 crtc
->base
.enabled
? "enabled" : "disabled",
12955 crtc
->active
? "enabled" : "disabled");
12957 crtc
->base
.enabled
= crtc
->active
;
12959 /* Because we only establish the connector -> encoder ->
12960 * crtc links if something is active, this means the
12961 * crtc is now deactivated. Break the links. connector
12962 * -> encoder links are only establish when things are
12963 * actually up, hence no need to break them. */
12964 WARN_ON(crtc
->active
);
12966 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
) {
12967 WARN_ON(encoder
->connectors_active
);
12968 encoder
->base
.crtc
= NULL
;
12972 if (crtc
->active
|| IS_VALLEYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 5) {
12974 * We start out with underrun reporting disabled to avoid races.
12975 * For correct bookkeeping mark this on active crtcs.
12977 * Also on gmch platforms we dont have any hardware bits to
12978 * disable the underrun reporting. Which means we need to start
12979 * out with underrun reporting disabled also on inactive pipes,
12980 * since otherwise we'll complain about the garbage we read when
12981 * e.g. coming up after runtime pm.
12983 * No protection against concurrent access is required - at
12984 * worst a fifo underrun happens which also sets this to false.
12986 crtc
->cpu_fifo_underrun_disabled
= true;
12987 crtc
->pch_fifo_underrun_disabled
= true;
12989 update_scanline_offset(crtc
);
12993 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
12995 struct intel_connector
*connector
;
12996 struct drm_device
*dev
= encoder
->base
.dev
;
12998 /* We need to check both for a crtc link (meaning that the
12999 * encoder is active and trying to read from a pipe) and the
13000 * pipe itself being active. */
13001 bool has_active_crtc
= encoder
->base
.crtc
&&
13002 to_intel_crtc(encoder
->base
.crtc
)->active
;
13004 if (encoder
->connectors_active
&& !has_active_crtc
) {
13005 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13006 encoder
->base
.base
.id
,
13007 encoder
->base
.name
);
13009 /* Connector is active, but has no active pipe. This is
13010 * fallout from our resume register restoring. Disable
13011 * the encoder manually again. */
13012 if (encoder
->base
.crtc
) {
13013 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13014 encoder
->base
.base
.id
,
13015 encoder
->base
.name
);
13016 encoder
->disable(encoder
);
13017 if (encoder
->post_disable
)
13018 encoder
->post_disable(encoder
);
13020 encoder
->base
.crtc
= NULL
;
13021 encoder
->connectors_active
= false;
13023 /* Inconsistent output/port/pipe state happens presumably due to
13024 * a bug in one of the get_hw_state functions. Or someplace else
13025 * in our code, like the register restore mess on resume. Clamp
13026 * things to off as a safer default. */
13027 list_for_each_entry(connector
,
13028 &dev
->mode_config
.connector_list
,
13030 if (connector
->encoder
!= encoder
)
13032 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13033 connector
->base
.encoder
= NULL
;
13036 /* Enabled encoders without active connectors will be fixed in
13037 * the crtc fixup. */
13040 void i915_redisable_vga_power_on(struct drm_device
*dev
)
13042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13043 u32 vga_reg
= i915_vgacntrl_reg(dev
);
13045 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
13046 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13047 i915_disable_vga(dev
);
13051 void i915_redisable_vga(struct drm_device
*dev
)
13053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13055 /* This function can be called both from intel_modeset_setup_hw_state or
13056 * at a very early point in our resume sequence, where the power well
13057 * structures are not yet restored. Since this function is at a very
13058 * paranoid "someone might have enabled VGA while we were not looking"
13059 * level, just check if the power well is enabled instead of trying to
13060 * follow the "don't touch the power well if we don't need it" policy
13061 * the rest of the driver uses. */
13062 if (!intel_display_power_enabled(dev_priv
, POWER_DOMAIN_VGA
))
13065 i915_redisable_vga_power_on(dev
);
13068 static bool primary_get_hw_state(struct intel_crtc
*crtc
)
13070 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
13075 return I915_READ(DSPCNTR(crtc
->plane
)) & DISPLAY_PLANE_ENABLE
;
13078 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
13080 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13082 struct intel_crtc
*crtc
;
13083 struct intel_encoder
*encoder
;
13084 struct intel_connector
*connector
;
13087 for_each_intel_crtc(dev
, crtc
) {
13088 memset(&crtc
->config
, 0, sizeof(crtc
->config
));
13090 crtc
->config
.quirks
|= PIPE_CONFIG_QUIRK_INHERITED_MODE
;
13092 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
13095 crtc
->base
.enabled
= crtc
->active
;
13096 crtc
->primary_enabled
= primary_get_hw_state(crtc
);
13098 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13099 crtc
->base
.base
.id
,
13100 crtc
->active
? "enabled" : "disabled");
13103 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13104 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13106 pll
->on
= pll
->get_hw_state(dev_priv
, pll
, &pll
->hw_state
);
13108 for_each_intel_crtc(dev
, crtc
) {
13109 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
13112 pll
->refcount
= pll
->active
;
13114 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
13115 pll
->name
, pll
->refcount
, pll
->on
);
13118 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
13121 for_each_intel_encoder(dev
, encoder
) {
13124 if (encoder
->get_hw_state(encoder
, &pipe
)) {
13125 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13126 encoder
->base
.crtc
= &crtc
->base
;
13127 encoder
->get_config(encoder
, &crtc
->config
);
13129 encoder
->base
.crtc
= NULL
;
13132 encoder
->connectors_active
= false;
13133 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13134 encoder
->base
.base
.id
,
13135 encoder
->base
.name
,
13136 encoder
->base
.crtc
? "enabled" : "disabled",
13140 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
13142 if (connector
->get_hw_state(connector
)) {
13143 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
13144 connector
->encoder
->connectors_active
= true;
13145 connector
->base
.encoder
= &connector
->encoder
->base
;
13147 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
13148 connector
->base
.encoder
= NULL
;
13150 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13151 connector
->base
.base
.id
,
13152 connector
->base
.name
,
13153 connector
->base
.encoder
? "enabled" : "disabled");
13157 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13158 * and i915 state tracking structures. */
13159 void intel_modeset_setup_hw_state(struct drm_device
*dev
,
13160 bool force_restore
)
13162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13164 struct intel_crtc
*crtc
;
13165 struct intel_encoder
*encoder
;
13168 intel_modeset_readout_hw_state(dev
);
13171 * Now that we have the config, copy it to each CRTC struct
13172 * Note that this could go away if we move to using crtc_config
13173 * checking everywhere.
13175 for_each_intel_crtc(dev
, crtc
) {
13176 if (crtc
->active
&& i915
.fastboot
) {
13177 intel_mode_from_pipe_config(&crtc
->base
.mode
, &crtc
->config
);
13178 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13179 crtc
->base
.base
.id
);
13180 drm_mode_debug_printmodeline(&crtc
->base
.mode
);
13184 /* HW state is read out, now we need to sanitize this mess. */
13185 for_each_intel_encoder(dev
, encoder
) {
13186 intel_sanitize_encoder(encoder
);
13189 for_each_pipe(dev_priv
, pipe
) {
13190 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
13191 intel_sanitize_crtc(crtc
);
13192 intel_dump_pipe_config(crtc
, &crtc
->config
, "[setup_hw_state]");
13195 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13196 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
13198 if (!pll
->on
|| pll
->active
)
13201 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
13203 pll
->disable(dev_priv
, pll
);
13207 if (HAS_PCH_SPLIT(dev
))
13208 ilk_wm_get_hw_state(dev
);
13210 if (force_restore
) {
13211 i915_redisable_vga(dev
);
13214 * We need to use raw interfaces for restoring state to avoid
13215 * checking (bogus) intermediate states.
13217 for_each_pipe(dev_priv
, pipe
) {
13218 struct drm_crtc
*crtc
=
13219 dev_priv
->pipe_to_crtc_mapping
[pipe
];
13221 __intel_set_mode(crtc
, &crtc
->mode
, crtc
->x
, crtc
->y
,
13222 crtc
->primary
->fb
);
13225 intel_modeset_update_staged_output_state(dev
);
13228 intel_modeset_check_state(dev
);
13231 void intel_modeset_gem_init(struct drm_device
*dev
)
13233 struct drm_crtc
*c
;
13234 struct drm_i915_gem_object
*obj
;
13236 mutex_lock(&dev
->struct_mutex
);
13237 intel_init_gt_powersave(dev
);
13238 mutex_unlock(&dev
->struct_mutex
);
13240 intel_modeset_init_hw(dev
);
13242 intel_setup_overlay(dev
);
13245 * Make sure any fbs we allocated at startup are properly
13246 * pinned & fenced. When we do the allocation it's too early
13249 mutex_lock(&dev
->struct_mutex
);
13250 for_each_crtc(dev
, c
) {
13251 obj
= intel_fb_obj(c
->primary
->fb
);
13255 if (intel_pin_and_fence_fb_obj(dev
, obj
, NULL
)) {
13256 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13257 to_intel_crtc(c
)->pipe
);
13258 drm_framebuffer_unreference(c
->primary
->fb
);
13259 c
->primary
->fb
= NULL
;
13262 mutex_unlock(&dev
->struct_mutex
);
13265 void intel_connector_unregister(struct intel_connector
*intel_connector
)
13267 struct drm_connector
*connector
= &intel_connector
->base
;
13269 intel_panel_destroy_backlight(connector
);
13270 drm_connector_unregister(connector
);
13273 void intel_modeset_cleanup(struct drm_device
*dev
)
13275 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13276 struct drm_connector
*connector
;
13279 * Interrupts and polling as the first thing to avoid creating havoc.
13280 * Too much stuff here (turning of rps, connectors, ...) would
13281 * experience fancy races otherwise.
13283 drm_irq_uninstall(dev
);
13284 intel_hpd_cancel_work(dev_priv
);
13285 dev_priv
->pm
._irqs_disabled
= true;
13288 * Due to the hpd irq storm handling the hotplug work can re-arm the
13289 * poll handlers. Hence disable polling after hpd handling is shut down.
13291 drm_kms_helper_poll_fini(dev
);
13293 mutex_lock(&dev
->struct_mutex
);
13295 intel_unregister_dsm_handler();
13297 intel_disable_fbc(dev
);
13299 intel_disable_gt_powersave(dev
);
13301 ironlake_teardown_rc6(dev
);
13303 mutex_unlock(&dev
->struct_mutex
);
13305 /* flush any delayed tasks or pending work */
13306 flush_scheduled_work();
13308 /* destroy the backlight and sysfs files before encoders/connectors */
13309 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
13310 struct intel_connector
*intel_connector
;
13312 intel_connector
= to_intel_connector(connector
);
13313 intel_connector
->unregister(intel_connector
);
13316 drm_mode_config_cleanup(dev
);
13318 intel_cleanup_overlay(dev
);
13320 mutex_lock(&dev
->struct_mutex
);
13321 intel_cleanup_gt_powersave(dev
);
13322 mutex_unlock(&dev
->struct_mutex
);
13326 * Return which encoder is currently attached for connector.
13328 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
13330 return &intel_attached_encoder(connector
)->base
;
13333 void intel_connector_attach_encoder(struct intel_connector
*connector
,
13334 struct intel_encoder
*encoder
)
13336 connector
->encoder
= encoder
;
13337 drm_mode_connector_attach_encoder(&connector
->base
,
13342 * set vga decode state - true == enable VGA decode
13344 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
13346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13347 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
13350 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
13351 DRM_ERROR("failed to read control word\n");
13355 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
13359 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
13361 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
13363 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
13364 DRM_ERROR("failed to write control word\n");
13371 struct intel_display_error_state
{
13373 u32 power_well_driver
;
13375 int num_transcoders
;
13377 struct intel_cursor_error_state
{
13382 } cursor
[I915_MAX_PIPES
];
13384 struct intel_pipe_error_state
{
13385 bool power_domain_on
;
13388 } pipe
[I915_MAX_PIPES
];
13390 struct intel_plane_error_state
{
13398 } plane
[I915_MAX_PIPES
];
13400 struct intel_transcoder_error_state
{
13401 bool power_domain_on
;
13402 enum transcoder cpu_transcoder
;
13415 struct intel_display_error_state
*
13416 intel_display_capture_error_state(struct drm_device
*dev
)
13418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13419 struct intel_display_error_state
*error
;
13420 int transcoders
[] = {
13428 if (INTEL_INFO(dev
)->num_pipes
== 0)
13431 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
13435 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13436 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
13438 for_each_pipe(dev_priv
, i
) {
13439 error
->pipe
[i
].power_domain_on
=
13440 intel_display_power_enabled_unlocked(dev_priv
,
13441 POWER_DOMAIN_PIPE(i
));
13442 if (!error
->pipe
[i
].power_domain_on
)
13445 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
13446 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
13447 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
13449 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
13450 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
13451 if (INTEL_INFO(dev
)->gen
<= 3) {
13452 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
13453 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
13455 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13456 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
13457 if (INTEL_INFO(dev
)->gen
>= 4) {
13458 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
13459 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
13462 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
13464 if (HAS_GMCH_DISPLAY(dev
))
13465 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
13468 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
13469 if (HAS_DDI(dev_priv
->dev
))
13470 error
->num_transcoders
++; /* Account for eDP. */
13472 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13473 enum transcoder cpu_transcoder
= transcoders
[i
];
13475 error
->transcoder
[i
].power_domain_on
=
13476 intel_display_power_enabled_unlocked(dev_priv
,
13477 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
13478 if (!error
->transcoder
[i
].power_domain_on
)
13481 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
13483 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
13484 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
13485 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
13486 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
13487 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
13488 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
13489 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
13495 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13498 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
13499 struct drm_device
*dev
,
13500 struct intel_display_error_state
*error
)
13502 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13508 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
13509 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
13510 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
13511 error
->power_well_driver
);
13512 for_each_pipe(dev_priv
, i
) {
13513 err_printf(m
, "Pipe [%d]:\n", i
);
13514 err_printf(m
, " Power: %s\n",
13515 error
->pipe
[i
].power_domain_on
? "on" : "off");
13516 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
13517 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
13519 err_printf(m
, "Plane [%d]:\n", i
);
13520 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
13521 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
13522 if (INTEL_INFO(dev
)->gen
<= 3) {
13523 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
13524 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
13526 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
13527 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
13528 if (INTEL_INFO(dev
)->gen
>= 4) {
13529 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
13530 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
13533 err_printf(m
, "Cursor [%d]:\n", i
);
13534 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
13535 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
13536 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
13539 for (i
= 0; i
< error
->num_transcoders
; i
++) {
13540 err_printf(m
, "CPU transcoder: %c\n",
13541 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
13542 err_printf(m
, " Power: %s\n",
13543 error
->transcoder
[i
].power_domain_on
? "on" : "off");
13544 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
13545 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
13546 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
13547 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
13548 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
13549 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
13550 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
13554 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
13556 struct intel_crtc
*crtc
;
13558 for_each_intel_crtc(dev
, crtc
) {
13559 struct intel_unpin_work
*work
;
13560 unsigned long irqflags
;
13562 spin_lock_irqsave(&dev
->event_lock
, irqflags
);
13564 work
= crtc
->unpin_work
;
13566 if (work
&& work
->event
&&
13567 work
->event
->base
.file_priv
== file
) {
13568 kfree(work
->event
);
13569 work
->event
= NULL
;
13572 spin_unlock_irqrestore(&dev
->event_lock
, irqflags
);