2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
48 /* Primary plane formats for gen <= 3 */
49 static const uint32_t i8xx_primary_formats
[] = {
56 /* Primary plane formats for gen >= 4 */
57 static const uint32_t i965_primary_formats
[] = {
62 DRM_FORMAT_XRGB2101010
,
63 DRM_FORMAT_XBGR2101010
,
66 static const uint32_t skl_primary_formats
[] = {
73 DRM_FORMAT_XRGB2101010
,
74 DRM_FORMAT_XBGR2101010
,
82 static const uint32_t intel_cursor_formats
[] = {
86 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
88 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
89 struct intel_crtc_state
*pipe_config
);
90 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
91 struct intel_crtc_state
*pipe_config
);
93 static int intel_framebuffer_init(struct drm_device
*dev
,
94 struct intel_framebuffer
*ifb
,
95 struct drm_mode_fb_cmd2
*mode_cmd
,
96 struct drm_i915_gem_object
*obj
);
97 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
);
98 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
100 struct intel_link_m_n
*m_n
,
101 struct intel_link_m_n
*m2_n2
);
102 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
);
103 static void haswell_set_pipeconf(struct drm_crtc
*crtc
);
104 static void intel_set_pipe_csc(struct drm_crtc
*crtc
);
105 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
106 const struct intel_crtc_state
*pipe_config
);
107 static void chv_prepare_pll(struct intel_crtc
*crtc
,
108 const struct intel_crtc_state
*pipe_config
);
109 static void intel_begin_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
110 static void intel_finish_crtc_commit(struct drm_crtc
*, struct drm_crtc_state
*);
111 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
112 struct intel_crtc_state
*crtc_state
);
113 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
115 static void skylake_pfit_enable(struct intel_crtc
*crtc
);
116 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
);
117 static void ironlake_pfit_enable(struct intel_crtc
*crtc
);
118 static void intel_modeset_setup_hw_state(struct drm_device
*dev
);
126 int p2_slow
, p2_fast
;
129 typedef struct intel_limit intel_limit_t
;
131 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
135 /* returns HPLL frequency in kHz */
136 static int valleyview_get_vco(struct drm_i915_private
*dev_priv
)
138 int hpll_freq
, vco_freq
[] = { 800, 1600, 2000, 2400 };
140 /* Obtain SKU information */
141 mutex_lock(&dev_priv
->sb_lock
);
142 hpll_freq
= vlv_cck_read(dev_priv
, CCK_FUSE_REG
) &
143 CCK_FUSE_HPLL_FREQ_MASK
;
144 mutex_unlock(&dev_priv
->sb_lock
);
146 return vco_freq
[hpll_freq
] * 1000;
149 static int vlv_get_cck_clock_hpll(struct drm_i915_private
*dev_priv
,
150 const char *name
, u32 reg
)
155 if (dev_priv
->hpll_freq
== 0)
156 dev_priv
->hpll_freq
= valleyview_get_vco(dev_priv
);
158 mutex_lock(&dev_priv
->sb_lock
);
159 val
= vlv_cck_read(dev_priv
, reg
);
160 mutex_unlock(&dev_priv
->sb_lock
);
162 divider
= val
& CCK_FREQUENCY_VALUES
;
164 WARN((val
& CCK_FREQUENCY_STATUS
) !=
165 (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
166 "%s change in progress\n", name
);
168 return DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, divider
+ 1);
172 intel_pch_rawclk(struct drm_device
*dev
)
174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
176 WARN_ON(!HAS_PCH_SPLIT(dev
));
178 return I915_READ(PCH_RAWCLK_FREQ
) & RAWCLK_FREQ_MASK
;
181 /* hrawclock is 1/4 the FSB frequency */
182 int intel_hrawclk(struct drm_device
*dev
)
184 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
187 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
188 if (IS_VALLEYVIEW(dev
))
191 clkcfg
= I915_READ(CLKCFG
);
192 switch (clkcfg
& CLKCFG_FSB_MASK
) {
201 case CLKCFG_FSB_1067
:
203 case CLKCFG_FSB_1333
:
205 /* these two are just a guess; one of them might be right */
206 case CLKCFG_FSB_1600
:
207 case CLKCFG_FSB_1600_ALT
:
214 static void intel_update_czclk(struct drm_i915_private
*dev_priv
)
216 if (!IS_VALLEYVIEW(dev_priv
))
219 dev_priv
->czclk_freq
= vlv_get_cck_clock_hpll(dev_priv
, "czclk",
220 CCK_CZ_CLOCK_CONTROL
);
222 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv
->czclk_freq
);
225 static inline u32
/* units of 100MHz */
226 intel_fdi_link_freq(struct drm_device
*dev
)
229 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
230 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
235 static const intel_limit_t intel_limits_i8xx_dac
= {
236 .dot
= { .min
= 25000, .max
= 350000 },
237 .vco
= { .min
= 908000, .max
= 1512000 },
238 .n
= { .min
= 2, .max
= 16 },
239 .m
= { .min
= 96, .max
= 140 },
240 .m1
= { .min
= 18, .max
= 26 },
241 .m2
= { .min
= 6, .max
= 16 },
242 .p
= { .min
= 4, .max
= 128 },
243 .p1
= { .min
= 2, .max
= 33 },
244 .p2
= { .dot_limit
= 165000,
245 .p2_slow
= 4, .p2_fast
= 2 },
248 static const intel_limit_t intel_limits_i8xx_dvo
= {
249 .dot
= { .min
= 25000, .max
= 350000 },
250 .vco
= { .min
= 908000, .max
= 1512000 },
251 .n
= { .min
= 2, .max
= 16 },
252 .m
= { .min
= 96, .max
= 140 },
253 .m1
= { .min
= 18, .max
= 26 },
254 .m2
= { .min
= 6, .max
= 16 },
255 .p
= { .min
= 4, .max
= 128 },
256 .p1
= { .min
= 2, .max
= 33 },
257 .p2
= { .dot_limit
= 165000,
258 .p2_slow
= 4, .p2_fast
= 4 },
261 static const intel_limit_t intel_limits_i8xx_lvds
= {
262 .dot
= { .min
= 25000, .max
= 350000 },
263 .vco
= { .min
= 908000, .max
= 1512000 },
264 .n
= { .min
= 2, .max
= 16 },
265 .m
= { .min
= 96, .max
= 140 },
266 .m1
= { .min
= 18, .max
= 26 },
267 .m2
= { .min
= 6, .max
= 16 },
268 .p
= { .min
= 4, .max
= 128 },
269 .p1
= { .min
= 1, .max
= 6 },
270 .p2
= { .dot_limit
= 165000,
271 .p2_slow
= 14, .p2_fast
= 7 },
274 static const intel_limit_t intel_limits_i9xx_sdvo
= {
275 .dot
= { .min
= 20000, .max
= 400000 },
276 .vco
= { .min
= 1400000, .max
= 2800000 },
277 .n
= { .min
= 1, .max
= 6 },
278 .m
= { .min
= 70, .max
= 120 },
279 .m1
= { .min
= 8, .max
= 18 },
280 .m2
= { .min
= 3, .max
= 7 },
281 .p
= { .min
= 5, .max
= 80 },
282 .p1
= { .min
= 1, .max
= 8 },
283 .p2
= { .dot_limit
= 200000,
284 .p2_slow
= 10, .p2_fast
= 5 },
287 static const intel_limit_t intel_limits_i9xx_lvds
= {
288 .dot
= { .min
= 20000, .max
= 400000 },
289 .vco
= { .min
= 1400000, .max
= 2800000 },
290 .n
= { .min
= 1, .max
= 6 },
291 .m
= { .min
= 70, .max
= 120 },
292 .m1
= { .min
= 8, .max
= 18 },
293 .m2
= { .min
= 3, .max
= 7 },
294 .p
= { .min
= 7, .max
= 98 },
295 .p1
= { .min
= 1, .max
= 8 },
296 .p2
= { .dot_limit
= 112000,
297 .p2_slow
= 14, .p2_fast
= 7 },
301 static const intel_limit_t intel_limits_g4x_sdvo
= {
302 .dot
= { .min
= 25000, .max
= 270000 },
303 .vco
= { .min
= 1750000, .max
= 3500000},
304 .n
= { .min
= 1, .max
= 4 },
305 .m
= { .min
= 104, .max
= 138 },
306 .m1
= { .min
= 17, .max
= 23 },
307 .m2
= { .min
= 5, .max
= 11 },
308 .p
= { .min
= 10, .max
= 30 },
309 .p1
= { .min
= 1, .max
= 3},
310 .p2
= { .dot_limit
= 270000,
316 static const intel_limit_t intel_limits_g4x_hdmi
= {
317 .dot
= { .min
= 22000, .max
= 400000 },
318 .vco
= { .min
= 1750000, .max
= 3500000},
319 .n
= { .min
= 1, .max
= 4 },
320 .m
= { .min
= 104, .max
= 138 },
321 .m1
= { .min
= 16, .max
= 23 },
322 .m2
= { .min
= 5, .max
= 11 },
323 .p
= { .min
= 5, .max
= 80 },
324 .p1
= { .min
= 1, .max
= 8},
325 .p2
= { .dot_limit
= 165000,
326 .p2_slow
= 10, .p2_fast
= 5 },
329 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
330 .dot
= { .min
= 20000, .max
= 115000 },
331 .vco
= { .min
= 1750000, .max
= 3500000 },
332 .n
= { .min
= 1, .max
= 3 },
333 .m
= { .min
= 104, .max
= 138 },
334 .m1
= { .min
= 17, .max
= 23 },
335 .m2
= { .min
= 5, .max
= 11 },
336 .p
= { .min
= 28, .max
= 112 },
337 .p1
= { .min
= 2, .max
= 8 },
338 .p2
= { .dot_limit
= 0,
339 .p2_slow
= 14, .p2_fast
= 14
343 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
344 .dot
= { .min
= 80000, .max
= 224000 },
345 .vco
= { .min
= 1750000, .max
= 3500000 },
346 .n
= { .min
= 1, .max
= 3 },
347 .m
= { .min
= 104, .max
= 138 },
348 .m1
= { .min
= 17, .max
= 23 },
349 .m2
= { .min
= 5, .max
= 11 },
350 .p
= { .min
= 14, .max
= 42 },
351 .p1
= { .min
= 2, .max
= 6 },
352 .p2
= { .dot_limit
= 0,
353 .p2_slow
= 7, .p2_fast
= 7
357 static const intel_limit_t intel_limits_pineview_sdvo
= {
358 .dot
= { .min
= 20000, .max
= 400000},
359 .vco
= { .min
= 1700000, .max
= 3500000 },
360 /* Pineview's Ncounter is a ring counter */
361 .n
= { .min
= 3, .max
= 6 },
362 .m
= { .min
= 2, .max
= 256 },
363 /* Pineview only has one combined m divider, which we treat as m2. */
364 .m1
= { .min
= 0, .max
= 0 },
365 .m2
= { .min
= 0, .max
= 254 },
366 .p
= { .min
= 5, .max
= 80 },
367 .p1
= { .min
= 1, .max
= 8 },
368 .p2
= { .dot_limit
= 200000,
369 .p2_slow
= 10, .p2_fast
= 5 },
372 static const intel_limit_t intel_limits_pineview_lvds
= {
373 .dot
= { .min
= 20000, .max
= 400000 },
374 .vco
= { .min
= 1700000, .max
= 3500000 },
375 .n
= { .min
= 3, .max
= 6 },
376 .m
= { .min
= 2, .max
= 256 },
377 .m1
= { .min
= 0, .max
= 0 },
378 .m2
= { .min
= 0, .max
= 254 },
379 .p
= { .min
= 7, .max
= 112 },
380 .p1
= { .min
= 1, .max
= 8 },
381 .p2
= { .dot_limit
= 112000,
382 .p2_slow
= 14, .p2_fast
= 14 },
385 /* Ironlake / Sandybridge
387 * We calculate clock using (register_value + 2) for N/M1/M2, so here
388 * the range value for them is (actual_value - 2).
390 static const intel_limit_t intel_limits_ironlake_dac
= {
391 .dot
= { .min
= 25000, .max
= 350000 },
392 .vco
= { .min
= 1760000, .max
= 3510000 },
393 .n
= { .min
= 1, .max
= 5 },
394 .m
= { .min
= 79, .max
= 127 },
395 .m1
= { .min
= 12, .max
= 22 },
396 .m2
= { .min
= 5, .max
= 9 },
397 .p
= { .min
= 5, .max
= 80 },
398 .p1
= { .min
= 1, .max
= 8 },
399 .p2
= { .dot_limit
= 225000,
400 .p2_slow
= 10, .p2_fast
= 5 },
403 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
404 .dot
= { .min
= 25000, .max
= 350000 },
405 .vco
= { .min
= 1760000, .max
= 3510000 },
406 .n
= { .min
= 1, .max
= 3 },
407 .m
= { .min
= 79, .max
= 118 },
408 .m1
= { .min
= 12, .max
= 22 },
409 .m2
= { .min
= 5, .max
= 9 },
410 .p
= { .min
= 28, .max
= 112 },
411 .p1
= { .min
= 2, .max
= 8 },
412 .p2
= { .dot_limit
= 225000,
413 .p2_slow
= 14, .p2_fast
= 14 },
416 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
417 .dot
= { .min
= 25000, .max
= 350000 },
418 .vco
= { .min
= 1760000, .max
= 3510000 },
419 .n
= { .min
= 1, .max
= 3 },
420 .m
= { .min
= 79, .max
= 127 },
421 .m1
= { .min
= 12, .max
= 22 },
422 .m2
= { .min
= 5, .max
= 9 },
423 .p
= { .min
= 14, .max
= 56 },
424 .p1
= { .min
= 2, .max
= 8 },
425 .p2
= { .dot_limit
= 225000,
426 .p2_slow
= 7, .p2_fast
= 7 },
429 /* LVDS 100mhz refclk limits. */
430 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
431 .dot
= { .min
= 25000, .max
= 350000 },
432 .vco
= { .min
= 1760000, .max
= 3510000 },
433 .n
= { .min
= 1, .max
= 2 },
434 .m
= { .min
= 79, .max
= 126 },
435 .m1
= { .min
= 12, .max
= 22 },
436 .m2
= { .min
= 5, .max
= 9 },
437 .p
= { .min
= 28, .max
= 112 },
438 .p1
= { .min
= 2, .max
= 8 },
439 .p2
= { .dot_limit
= 225000,
440 .p2_slow
= 14, .p2_fast
= 14 },
443 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
444 .dot
= { .min
= 25000, .max
= 350000 },
445 .vco
= { .min
= 1760000, .max
= 3510000 },
446 .n
= { .min
= 1, .max
= 3 },
447 .m
= { .min
= 79, .max
= 126 },
448 .m1
= { .min
= 12, .max
= 22 },
449 .m2
= { .min
= 5, .max
= 9 },
450 .p
= { .min
= 14, .max
= 42 },
451 .p1
= { .min
= 2, .max
= 6 },
452 .p2
= { .dot_limit
= 225000,
453 .p2_slow
= 7, .p2_fast
= 7 },
456 static const intel_limit_t intel_limits_vlv
= {
458 * These are the data rate limits (measured in fast clocks)
459 * since those are the strictest limits we have. The fast
460 * clock and actual rate limits are more relaxed, so checking
461 * them would make no difference.
463 .dot
= { .min
= 25000 * 5, .max
= 270000 * 5 },
464 .vco
= { .min
= 4000000, .max
= 6000000 },
465 .n
= { .min
= 1, .max
= 7 },
466 .m1
= { .min
= 2, .max
= 3 },
467 .m2
= { .min
= 11, .max
= 156 },
468 .p1
= { .min
= 2, .max
= 3 },
469 .p2
= { .p2_slow
= 2, .p2_fast
= 20 }, /* slow=min, fast=max */
472 static const intel_limit_t intel_limits_chv
= {
474 * These are the data rate limits (measured in fast clocks)
475 * since those are the strictest limits we have. The fast
476 * clock and actual rate limits are more relaxed, so checking
477 * them would make no difference.
479 .dot
= { .min
= 25000 * 5, .max
= 540000 * 5},
480 .vco
= { .min
= 4800000, .max
= 6480000 },
481 .n
= { .min
= 1, .max
= 1 },
482 .m1
= { .min
= 2, .max
= 2 },
483 .m2
= { .min
= 24 << 22, .max
= 175 << 22 },
484 .p1
= { .min
= 2, .max
= 4 },
485 .p2
= { .p2_slow
= 1, .p2_fast
= 14 },
488 static const intel_limit_t intel_limits_bxt
= {
489 /* FIXME: find real dot limits */
490 .dot
= { .min
= 0, .max
= INT_MAX
},
491 .vco
= { .min
= 4800000, .max
= 6700000 },
492 .n
= { .min
= 1, .max
= 1 },
493 .m1
= { .min
= 2, .max
= 2 },
494 /* FIXME: find real m2 limits */
495 .m2
= { .min
= 2 << 22, .max
= 255 << 22 },
496 .p1
= { .min
= 2, .max
= 4 },
497 .p2
= { .p2_slow
= 1, .p2_fast
= 20 },
501 needs_modeset(struct drm_crtc_state
*state
)
503 return drm_atomic_crtc_needs_modeset(state
);
507 * Returns whether any output on the specified pipe is of the specified type
509 bool intel_pipe_has_type(struct intel_crtc
*crtc
, enum intel_output_type type
)
511 struct drm_device
*dev
= crtc
->base
.dev
;
512 struct intel_encoder
*encoder
;
514 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
515 if (encoder
->type
== type
)
522 * Returns whether any output on the specified pipe will have the specified
523 * type after a staged modeset is complete, i.e., the same as
524 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
527 static bool intel_pipe_will_have_type(const struct intel_crtc_state
*crtc_state
,
530 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
531 struct drm_connector
*connector
;
532 struct drm_connector_state
*connector_state
;
533 struct intel_encoder
*encoder
;
534 int i
, num_connectors
= 0;
536 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
537 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
542 encoder
= to_intel_encoder(connector_state
->best_encoder
);
543 if (encoder
->type
== type
)
547 WARN_ON(num_connectors
== 0);
552 static const intel_limit_t
*
553 intel_ironlake_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
555 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
556 const intel_limit_t
*limit
;
558 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
559 if (intel_is_dual_link_lvds(dev
)) {
560 if (refclk
== 100000)
561 limit
= &intel_limits_ironlake_dual_lvds_100m
;
563 limit
= &intel_limits_ironlake_dual_lvds
;
565 if (refclk
== 100000)
566 limit
= &intel_limits_ironlake_single_lvds_100m
;
568 limit
= &intel_limits_ironlake_single_lvds
;
571 limit
= &intel_limits_ironlake_dac
;
576 static const intel_limit_t
*
577 intel_g4x_limit(struct intel_crtc_state
*crtc_state
)
579 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
580 const intel_limit_t
*limit
;
582 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
583 if (intel_is_dual_link_lvds(dev
))
584 limit
= &intel_limits_g4x_dual_channel_lvds
;
586 limit
= &intel_limits_g4x_single_channel_lvds
;
587 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
) ||
588 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_ANALOG
)) {
589 limit
= &intel_limits_g4x_hdmi
;
590 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
)) {
591 limit
= &intel_limits_g4x_sdvo
;
592 } else /* The option is for other outputs */
593 limit
= &intel_limits_i9xx_sdvo
;
598 static const intel_limit_t
*
599 intel_limit(struct intel_crtc_state
*crtc_state
, int refclk
)
601 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
602 const intel_limit_t
*limit
;
605 limit
= &intel_limits_bxt
;
606 else if (HAS_PCH_SPLIT(dev
))
607 limit
= intel_ironlake_limit(crtc_state
, refclk
);
608 else if (IS_G4X(dev
)) {
609 limit
= intel_g4x_limit(crtc_state
);
610 } else if (IS_PINEVIEW(dev
)) {
611 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
612 limit
= &intel_limits_pineview_lvds
;
614 limit
= &intel_limits_pineview_sdvo
;
615 } else if (IS_CHERRYVIEW(dev
)) {
616 limit
= &intel_limits_chv
;
617 } else if (IS_VALLEYVIEW(dev
)) {
618 limit
= &intel_limits_vlv
;
619 } else if (!IS_GEN2(dev
)) {
620 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
621 limit
= &intel_limits_i9xx_lvds
;
623 limit
= &intel_limits_i9xx_sdvo
;
625 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
626 limit
= &intel_limits_i8xx_lvds
;
627 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
628 limit
= &intel_limits_i8xx_dvo
;
630 limit
= &intel_limits_i8xx_dac
;
636 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
637 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
638 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
639 * The helpers' return value is the rate of the clock that is fed to the
640 * display engine's pipe which can be the above fast dot clock rate or a
641 * divided-down version of it.
643 /* m1 is reserved as 0 in Pineview, n is a ring counter */
644 static int pnv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
646 clock
->m
= clock
->m2
+ 2;
647 clock
->p
= clock
->p1
* clock
->p2
;
648 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
650 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
651 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
656 static uint32_t i9xx_dpll_compute_m(struct dpll
*dpll
)
658 return 5 * (dpll
->m1
+ 2) + (dpll
->m2
+ 2);
661 static int i9xx_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
663 clock
->m
= i9xx_dpll_compute_m(clock
);
664 clock
->p
= clock
->p1
* clock
->p2
;
665 if (WARN_ON(clock
->n
+ 2 == 0 || clock
->p
== 0))
667 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
+ 2);
668 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
673 static int vlv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
675 clock
->m
= clock
->m1
* clock
->m2
;
676 clock
->p
= clock
->p1
* clock
->p2
;
677 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
679 clock
->vco
= DIV_ROUND_CLOSEST(refclk
* clock
->m
, clock
->n
);
680 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
682 return clock
->dot
/ 5;
685 int chv_calc_dpll_params(int refclk
, intel_clock_t
*clock
)
687 clock
->m
= clock
->m1
* clock
->m2
;
688 clock
->p
= clock
->p1
* clock
->p2
;
689 if (WARN_ON(clock
->n
== 0 || clock
->p
== 0))
691 clock
->vco
= DIV_ROUND_CLOSEST_ULL((uint64_t)refclk
* clock
->m
,
693 clock
->dot
= DIV_ROUND_CLOSEST(clock
->vco
, clock
->p
);
695 return clock
->dot
/ 5;
698 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
700 * Returns whether the given set of divisors are valid for a given refclk with
701 * the given connectors.
704 static bool intel_PLL_is_valid(struct drm_device
*dev
,
705 const intel_limit_t
*limit
,
706 const intel_clock_t
*clock
)
708 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
709 INTELPllInvalid("n out of range\n");
710 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
711 INTELPllInvalid("p1 out of range\n");
712 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
713 INTELPllInvalid("m2 out of range\n");
714 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
715 INTELPllInvalid("m1 out of range\n");
717 if (!IS_PINEVIEW(dev
) && !IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
))
718 if (clock
->m1
<= clock
->m2
)
719 INTELPllInvalid("m1 <= m2\n");
721 if (!IS_VALLEYVIEW(dev
) && !IS_BROXTON(dev
)) {
722 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
723 INTELPllInvalid("p out of range\n");
724 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
725 INTELPllInvalid("m out of range\n");
728 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
729 INTELPllInvalid("vco out of range\n");
730 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
731 * connector, etc., rather than just a single range.
733 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
734 INTELPllInvalid("dot out of range\n");
740 i9xx_select_p2_div(const intel_limit_t
*limit
,
741 const struct intel_crtc_state
*crtc_state
,
744 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
746 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
748 * For LVDS just rely on its current settings for dual-channel.
749 * We haven't figured out how to reliably set up different
750 * single/dual channel state, if we even can.
752 if (intel_is_dual_link_lvds(dev
))
753 return limit
->p2
.p2_fast
;
755 return limit
->p2
.p2_slow
;
757 if (target
< limit
->p2
.dot_limit
)
758 return limit
->p2
.p2_slow
;
760 return limit
->p2
.p2_fast
;
765 i9xx_find_best_dpll(const intel_limit_t
*limit
,
766 struct intel_crtc_state
*crtc_state
,
767 int target
, int refclk
, intel_clock_t
*match_clock
,
768 intel_clock_t
*best_clock
)
770 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
774 memset(best_clock
, 0, sizeof(*best_clock
));
776 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
778 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
780 for (clock
.m2
= limit
->m2
.min
;
781 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
782 if (clock
.m2
>= clock
.m1
)
784 for (clock
.n
= limit
->n
.min
;
785 clock
.n
<= limit
->n
.max
; clock
.n
++) {
786 for (clock
.p1
= limit
->p1
.min
;
787 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
790 i9xx_calc_dpll_params(refclk
, &clock
);
791 if (!intel_PLL_is_valid(dev
, limit
,
795 clock
.p
!= match_clock
->p
)
798 this_err
= abs(clock
.dot
- target
);
799 if (this_err
< err
) {
808 return (err
!= target
);
812 pnv_find_best_dpll(const intel_limit_t
*limit
,
813 struct intel_crtc_state
*crtc_state
,
814 int target
, int refclk
, intel_clock_t
*match_clock
,
815 intel_clock_t
*best_clock
)
817 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
821 memset(best_clock
, 0, sizeof(*best_clock
));
823 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
825 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
827 for (clock
.m2
= limit
->m2
.min
;
828 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
829 for (clock
.n
= limit
->n
.min
;
830 clock
.n
<= limit
->n
.max
; clock
.n
++) {
831 for (clock
.p1
= limit
->p1
.min
;
832 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
835 pnv_calc_dpll_params(refclk
, &clock
);
836 if (!intel_PLL_is_valid(dev
, limit
,
840 clock
.p
!= match_clock
->p
)
843 this_err
= abs(clock
.dot
- target
);
844 if (this_err
< err
) {
853 return (err
!= target
);
857 g4x_find_best_dpll(const intel_limit_t
*limit
,
858 struct intel_crtc_state
*crtc_state
,
859 int target
, int refclk
, intel_clock_t
*match_clock
,
860 intel_clock_t
*best_clock
)
862 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
866 /* approximately equals target * 0.00585 */
867 int err_most
= (target
>> 8) + (target
>> 9);
869 memset(best_clock
, 0, sizeof(*best_clock
));
871 clock
.p2
= i9xx_select_p2_div(limit
, crtc_state
, target
);
873 max_n
= limit
->n
.max
;
874 /* based on hardware requirement, prefer smaller n to precision */
875 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
876 /* based on hardware requirement, prefere larger m1,m2 */
877 for (clock
.m1
= limit
->m1
.max
;
878 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
879 for (clock
.m2
= limit
->m2
.max
;
880 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
881 for (clock
.p1
= limit
->p1
.max
;
882 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
885 i9xx_calc_dpll_params(refclk
, &clock
);
886 if (!intel_PLL_is_valid(dev
, limit
,
890 this_err
= abs(clock
.dot
- target
);
891 if (this_err
< err_most
) {
905 * Check if the calculated PLL configuration is more optimal compared to the
906 * best configuration and error found so far. Return the calculated error.
908 static bool vlv_PLL_is_optimal(struct drm_device
*dev
, int target_freq
,
909 const intel_clock_t
*calculated_clock
,
910 const intel_clock_t
*best_clock
,
911 unsigned int best_error_ppm
,
912 unsigned int *error_ppm
)
915 * For CHV ignore the error and consider only the P value.
916 * Prefer a bigger P value based on HW requirements.
918 if (IS_CHERRYVIEW(dev
)) {
921 return calculated_clock
->p
> best_clock
->p
;
924 if (WARN_ON_ONCE(!target_freq
))
927 *error_ppm
= div_u64(1000000ULL *
928 abs(target_freq
- calculated_clock
->dot
),
931 * Prefer a better P value over a better (smaller) error if the error
932 * is small. Ensure this preference for future configurations too by
933 * setting the error to 0.
935 if (*error_ppm
< 100 && calculated_clock
->p
> best_clock
->p
) {
941 return *error_ppm
+ 10 < best_error_ppm
;
945 vlv_find_best_dpll(const intel_limit_t
*limit
,
946 struct intel_crtc_state
*crtc_state
,
947 int target
, int refclk
, intel_clock_t
*match_clock
,
948 intel_clock_t
*best_clock
)
950 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
951 struct drm_device
*dev
= crtc
->base
.dev
;
953 unsigned int bestppm
= 1000000;
954 /* min update 19.2 MHz */
955 int max_n
= min(limit
->n
.max
, refclk
/ 19200);
958 target
*= 5; /* fast clock */
960 memset(best_clock
, 0, sizeof(*best_clock
));
962 /* based on hardware requirement, prefer smaller n to precision */
963 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
964 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
965 for (clock
.p2
= limit
->p2
.p2_fast
; clock
.p2
>= limit
->p2
.p2_slow
;
966 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
967 clock
.p
= clock
.p1
* clock
.p2
;
968 /* based on hardware requirement, prefer bigger m1,m2 values */
969 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
; clock
.m1
++) {
972 clock
.m2
= DIV_ROUND_CLOSEST(target
* clock
.p
* clock
.n
,
975 vlv_calc_dpll_params(refclk
, &clock
);
977 if (!intel_PLL_is_valid(dev
, limit
,
981 if (!vlv_PLL_is_optimal(dev
, target
,
999 chv_find_best_dpll(const intel_limit_t
*limit
,
1000 struct intel_crtc_state
*crtc_state
,
1001 int target
, int refclk
, intel_clock_t
*match_clock
,
1002 intel_clock_t
*best_clock
)
1004 struct intel_crtc
*crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
1005 struct drm_device
*dev
= crtc
->base
.dev
;
1006 unsigned int best_error_ppm
;
1007 intel_clock_t clock
;
1011 memset(best_clock
, 0, sizeof(*best_clock
));
1012 best_error_ppm
= 1000000;
1015 * Based on hardware doc, the n always set to 1, and m1 always
1016 * set to 2. If requires to support 200Mhz refclk, we need to
1017 * revisit this because n may not 1 anymore.
1019 clock
.n
= 1, clock
.m1
= 2;
1020 target
*= 5; /* fast clock */
1022 for (clock
.p1
= limit
->p1
.max
; clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
1023 for (clock
.p2
= limit
->p2
.p2_fast
;
1024 clock
.p2
>= limit
->p2
.p2_slow
;
1025 clock
.p2
-= clock
.p2
> 10 ? 2 : 1) {
1026 unsigned int error_ppm
;
1028 clock
.p
= clock
.p1
* clock
.p2
;
1030 m2
= DIV_ROUND_CLOSEST_ULL(((uint64_t)target
* clock
.p
*
1031 clock
.n
) << 22, refclk
* clock
.m1
);
1033 if (m2
> INT_MAX
/clock
.m1
)
1038 chv_calc_dpll_params(refclk
, &clock
);
1040 if (!intel_PLL_is_valid(dev
, limit
, &clock
))
1043 if (!vlv_PLL_is_optimal(dev
, target
, &clock
, best_clock
,
1044 best_error_ppm
, &error_ppm
))
1047 *best_clock
= clock
;
1048 best_error_ppm
= error_ppm
;
1056 bool bxt_find_best_dpll(struct intel_crtc_state
*crtc_state
, int target_clock
,
1057 intel_clock_t
*best_clock
)
1059 int refclk
= i9xx_get_refclk(crtc_state
, 0);
1061 return chv_find_best_dpll(intel_limit(crtc_state
, refclk
), crtc_state
,
1062 target_clock
, refclk
, NULL
, best_clock
);
1065 bool intel_crtc_active(struct drm_crtc
*crtc
)
1067 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1069 /* Be paranoid as we can arrive here with only partial
1070 * state retrieved from the hardware during setup.
1072 * We can ditch the adjusted_mode.crtc_clock check as soon
1073 * as Haswell has gained clock readout/fastboot support.
1075 * We can ditch the crtc->primary->fb check as soon as we can
1076 * properly reconstruct framebuffers.
1078 * FIXME: The intel_crtc->active here should be switched to
1079 * crtc->state->active once we have proper CRTC states wired up
1082 return intel_crtc
->active
&& crtc
->primary
->state
->fb
&&
1083 intel_crtc
->config
->base
.adjusted_mode
.crtc_clock
;
1086 enum transcoder
intel_pipe_to_cpu_transcoder(struct drm_i915_private
*dev_priv
,
1089 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1090 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1092 return intel_crtc
->config
->cpu_transcoder
;
1095 static bool pipe_dsl_stopped(struct drm_device
*dev
, enum pipe pipe
)
1097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1098 u32 reg
= PIPEDSL(pipe
);
1103 line_mask
= DSL_LINEMASK_GEN2
;
1105 line_mask
= DSL_LINEMASK_GEN3
;
1107 line1
= I915_READ(reg
) & line_mask
;
1109 line2
= I915_READ(reg
) & line_mask
;
1111 return line1
== line2
;
1115 * intel_wait_for_pipe_off - wait for pipe to turn off
1116 * @crtc: crtc whose pipe to wait for
1118 * After disabling a pipe, we can't wait for vblank in the usual way,
1119 * spinning on the vblank interrupt status bit, since we won't actually
1120 * see an interrupt when the pipe is disabled.
1122 * On Gen4 and above:
1123 * wait for the pipe register state bit to turn off
1126 * wait for the display line value to settle (it usually
1127 * ends up stopping at the start of the next frame).
1130 static void intel_wait_for_pipe_off(struct intel_crtc
*crtc
)
1132 struct drm_device
*dev
= crtc
->base
.dev
;
1133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1134 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
1135 enum pipe pipe
= crtc
->pipe
;
1137 if (INTEL_INFO(dev
)->gen
>= 4) {
1138 int reg
= PIPECONF(cpu_transcoder
);
1140 /* Wait for the Pipe State to go off */
1141 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1143 WARN(1, "pipe_off wait timed out\n");
1145 /* Wait for the display line to settle */
1146 if (wait_for(pipe_dsl_stopped(dev
, pipe
), 100))
1147 WARN(1, "pipe_off wait timed out\n");
1151 static const char *state_string(bool enabled
)
1153 return enabled
? "on" : "off";
1156 /* Only for pre-ILK configs */
1157 void assert_pll(struct drm_i915_private
*dev_priv
,
1158 enum pipe pipe
, bool state
)
1163 val
= I915_READ(DPLL(pipe
));
1164 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1165 I915_STATE_WARN(cur_state
!= state
,
1166 "PLL state assertion failure (expected %s, current %s)\n",
1167 state_string(state
), state_string(cur_state
));
1170 /* XXX: the dsi pll is shared between MIPI DSI ports */
1171 static void assert_dsi_pll(struct drm_i915_private
*dev_priv
, bool state
)
1176 mutex_lock(&dev_priv
->sb_lock
);
1177 val
= vlv_cck_read(dev_priv
, CCK_REG_DSI_PLL_CONTROL
);
1178 mutex_unlock(&dev_priv
->sb_lock
);
1180 cur_state
= val
& DSI_PLL_VCO_EN
;
1181 I915_STATE_WARN(cur_state
!= state
,
1182 "DSI PLL state assertion failure (expected %s, current %s)\n",
1183 state_string(state
), state_string(cur_state
));
1185 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1186 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1188 struct intel_shared_dpll
*
1189 intel_crtc_to_shared_dpll(struct intel_crtc
*crtc
)
1191 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
1193 if (crtc
->config
->shared_dpll
< 0)
1196 return &dev_priv
->shared_dplls
[crtc
->config
->shared_dpll
];
1200 void assert_shared_dpll(struct drm_i915_private
*dev_priv
,
1201 struct intel_shared_dpll
*pll
,
1205 struct intel_dpll_hw_state hw_state
;
1208 "asserting DPLL %s with no DPLL\n", state_string(state
)))
1211 cur_state
= pll
->get_hw_state(dev_priv
, pll
, &hw_state
);
1212 I915_STATE_WARN(cur_state
!= state
,
1213 "%s assertion failure (expected %s, current %s)\n",
1214 pll
->name
, state_string(state
), state_string(cur_state
));
1217 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1218 enum pipe pipe
, bool state
)
1221 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1224 if (HAS_DDI(dev_priv
->dev
)) {
1225 /* DDI does not have a specific FDI_TX register */
1226 u32 val
= I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder
));
1227 cur_state
= !!(val
& TRANS_DDI_FUNC_ENABLE
);
1229 u32 val
= I915_READ(FDI_TX_CTL(pipe
));
1230 cur_state
= !!(val
& FDI_TX_ENABLE
);
1232 I915_STATE_WARN(cur_state
!= state
,
1233 "FDI TX state assertion failure (expected %s, current %s)\n",
1234 state_string(state
), state_string(cur_state
));
1236 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1237 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1239 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1240 enum pipe pipe
, bool state
)
1245 val
= I915_READ(FDI_RX_CTL(pipe
));
1246 cur_state
= !!(val
& FDI_RX_ENABLE
);
1247 I915_STATE_WARN(cur_state
!= state
,
1248 "FDI RX state assertion failure (expected %s, current %s)\n",
1249 state_string(state
), state_string(cur_state
));
1251 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1252 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1254 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1259 /* ILK FDI PLL is always enabled */
1260 if (INTEL_INFO(dev_priv
->dev
)->gen
== 5)
1263 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1264 if (HAS_DDI(dev_priv
->dev
))
1267 val
= I915_READ(FDI_TX_CTL(pipe
));
1268 I915_STATE_WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1271 void assert_fdi_rx_pll(struct drm_i915_private
*dev_priv
,
1272 enum pipe pipe
, bool state
)
1277 val
= I915_READ(FDI_RX_CTL(pipe
));
1278 cur_state
= !!(val
& FDI_RX_PLL_ENABLE
);
1279 I915_STATE_WARN(cur_state
!= state
,
1280 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1281 state_string(state
), state_string(cur_state
));
1284 void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1287 struct drm_device
*dev
= dev_priv
->dev
;
1290 enum pipe panel_pipe
= PIPE_A
;
1293 if (WARN_ON(HAS_DDI(dev
)))
1296 if (HAS_PCH_SPLIT(dev
)) {
1299 pp_reg
= PCH_PP_CONTROL
;
1300 port_sel
= I915_READ(PCH_PP_ON_DELAYS
) & PANEL_PORT_SELECT_MASK
;
1302 if (port_sel
== PANEL_PORT_SELECT_LVDS
&&
1303 I915_READ(PCH_LVDS
) & LVDS_PIPEB_SELECT
)
1304 panel_pipe
= PIPE_B
;
1305 /* XXX: else fix for eDP */
1306 } else if (IS_VALLEYVIEW(dev
)) {
1307 /* presumably write lock depends on pipe, not port select */
1308 pp_reg
= VLV_PIPE_PP_CONTROL(pipe
);
1311 pp_reg
= PP_CONTROL
;
1312 if (I915_READ(LVDS
) & LVDS_PIPEB_SELECT
)
1313 panel_pipe
= PIPE_B
;
1316 val
= I915_READ(pp_reg
);
1317 if (!(val
& PANEL_POWER_ON
) ||
1318 ((val
& PANEL_UNLOCK_MASK
) == PANEL_UNLOCK_REGS
))
1321 I915_STATE_WARN(panel_pipe
== pipe
&& locked
,
1322 "panel assertion failure, pipe %c regs locked\n",
1326 static void assert_cursor(struct drm_i915_private
*dev_priv
,
1327 enum pipe pipe
, bool state
)
1329 struct drm_device
*dev
= dev_priv
->dev
;
1332 if (IS_845G(dev
) || IS_I865G(dev
))
1333 cur_state
= I915_READ(CURCNTR(PIPE_A
)) & CURSOR_ENABLE
;
1335 cur_state
= I915_READ(CURCNTR(pipe
)) & CURSOR_MODE
;
1337 I915_STATE_WARN(cur_state
!= state
,
1338 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1339 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1341 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1342 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1344 void assert_pipe(struct drm_i915_private
*dev_priv
,
1345 enum pipe pipe
, bool state
)
1348 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
1351 /* if we need the pipe quirk it must be always on */
1352 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1353 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1356 if (!intel_display_power_is_enabled(dev_priv
,
1357 POWER_DOMAIN_TRANSCODER(cpu_transcoder
))) {
1360 u32 val
= I915_READ(PIPECONF(cpu_transcoder
));
1361 cur_state
= !!(val
& PIPECONF_ENABLE
);
1364 I915_STATE_WARN(cur_state
!= state
,
1365 "pipe %c assertion failure (expected %s, current %s)\n",
1366 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1369 static void assert_plane(struct drm_i915_private
*dev_priv
,
1370 enum plane plane
, bool state
)
1375 val
= I915_READ(DSPCNTR(plane
));
1376 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1377 I915_STATE_WARN(cur_state
!= state
,
1378 "plane %c assertion failure (expected %s, current %s)\n",
1379 plane_name(plane
), state_string(state
), state_string(cur_state
));
1382 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1383 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1385 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1388 struct drm_device
*dev
= dev_priv
->dev
;
1391 /* Primary planes are fixed to pipes on gen4+ */
1392 if (INTEL_INFO(dev
)->gen
>= 4) {
1393 u32 val
= I915_READ(DSPCNTR(pipe
));
1394 I915_STATE_WARN(val
& DISPLAY_PLANE_ENABLE
,
1395 "plane %c assertion failure, should be disabled but not\n",
1400 /* Need to check both planes against the pipe */
1401 for_each_pipe(dev_priv
, i
) {
1402 u32 val
= I915_READ(DSPCNTR(i
));
1403 enum pipe cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1404 DISPPLANE_SEL_PIPE_SHIFT
;
1405 I915_STATE_WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1406 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1407 plane_name(i
), pipe_name(pipe
));
1411 static void assert_sprites_disabled(struct drm_i915_private
*dev_priv
,
1414 struct drm_device
*dev
= dev_priv
->dev
;
1417 if (INTEL_INFO(dev
)->gen
>= 9) {
1418 for_each_sprite(dev_priv
, pipe
, sprite
) {
1419 u32 val
= I915_READ(PLANE_CTL(pipe
, sprite
));
1420 I915_STATE_WARN(val
& PLANE_CTL_ENABLE
,
1421 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1422 sprite
, pipe_name(pipe
));
1424 } else if (IS_VALLEYVIEW(dev
)) {
1425 for_each_sprite(dev_priv
, pipe
, sprite
) {
1426 u32 val
= I915_READ(SPCNTR(pipe
, sprite
));
1427 I915_STATE_WARN(val
& SP_ENABLE
,
1428 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1429 sprite_name(pipe
, sprite
), pipe_name(pipe
));
1431 } else if (INTEL_INFO(dev
)->gen
>= 7) {
1432 u32 val
= I915_READ(SPRCTL(pipe
));
1433 I915_STATE_WARN(val
& SPRITE_ENABLE
,
1434 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1435 plane_name(pipe
), pipe_name(pipe
));
1436 } else if (INTEL_INFO(dev
)->gen
>= 5) {
1437 u32 val
= I915_READ(DVSCNTR(pipe
));
1438 I915_STATE_WARN(val
& DVS_ENABLE
,
1439 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1440 plane_name(pipe
), pipe_name(pipe
));
1444 static void assert_vblank_disabled(struct drm_crtc
*crtc
)
1446 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc
) == 0))
1447 drm_crtc_vblank_put(crtc
);
1450 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1455 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv
->dev
) || HAS_PCH_CPT(dev_priv
->dev
)));
1457 val
= I915_READ(PCH_DREF_CONTROL
);
1458 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1459 DREF_SUPERSPREAD_SOURCE_MASK
));
1460 I915_STATE_WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1463 static void assert_pch_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1469 val
= I915_READ(PCH_TRANSCONF(pipe
));
1470 enabled
= !!(val
& TRANS_ENABLE
);
1471 I915_STATE_WARN(enabled
,
1472 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1476 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1477 enum pipe pipe
, u32 port_sel
, u32 val
)
1479 if ((val
& DP_PORT_EN
) == 0)
1482 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1483 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1484 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1485 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1487 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1488 if ((val
& DP_PIPE_MASK_CHV
) != DP_PIPE_SELECT_CHV(pipe
))
1491 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1497 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1498 enum pipe pipe
, u32 val
)
1500 if ((val
& SDVO_ENABLE
) == 0)
1503 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1504 if ((val
& SDVO_PIPE_SEL_MASK_CPT
) != SDVO_PIPE_SEL_CPT(pipe
))
1506 } else if (IS_CHERRYVIEW(dev_priv
->dev
)) {
1507 if ((val
& SDVO_PIPE_SEL_MASK_CHV
) != SDVO_PIPE_SEL_CHV(pipe
))
1510 if ((val
& SDVO_PIPE_SEL_MASK
) != SDVO_PIPE_SEL(pipe
))
1516 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1517 enum pipe pipe
, u32 val
)
1519 if ((val
& LVDS_PORT_EN
) == 0)
1522 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1523 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1526 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1532 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1533 enum pipe pipe
, u32 val
)
1535 if ((val
& ADPA_DAC_ENABLE
) == 0)
1537 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1538 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1541 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1547 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1548 enum pipe pipe
, int reg
, u32 port_sel
)
1550 u32 val
= I915_READ(reg
);
1551 I915_STATE_WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1552 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1553 reg
, pipe_name(pipe
));
1555 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& DP_PORT_EN
) == 0
1556 && (val
& DP_PIPEB_SELECT
),
1557 "IBX PCH dp port still using transcoder B\n");
1560 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1561 enum pipe pipe
, int reg
)
1563 u32 val
= I915_READ(reg
);
1564 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv
, pipe
, val
),
1565 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1566 reg
, pipe_name(pipe
));
1568 I915_STATE_WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_ENABLE
) == 0
1569 && (val
& SDVO_PIPE_B_SELECT
),
1570 "IBX PCH hdmi port still using transcoder B\n");
1573 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1578 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1579 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1580 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1582 val
= I915_READ(PCH_ADPA
);
1583 I915_STATE_WARN(adpa_pipe_enabled(dev_priv
, pipe
, val
),
1584 "PCH VGA enabled on transcoder %c, should be disabled\n",
1587 val
= I915_READ(PCH_LVDS
);
1588 I915_STATE_WARN(lvds_pipe_enabled(dev_priv
, pipe
, val
),
1589 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIB
);
1593 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMIC
);
1594 assert_pch_hdmi_disabled(dev_priv
, pipe
, PCH_HDMID
);
1597 static void vlv_enable_pll(struct intel_crtc
*crtc
,
1598 const struct intel_crtc_state
*pipe_config
)
1600 struct drm_device
*dev
= crtc
->base
.dev
;
1601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1602 int reg
= DPLL(crtc
->pipe
);
1603 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
1605 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1607 /* No really, not for ILK+ */
1608 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
));
1610 /* PLL is protected by panel, make sure we can write it */
1611 if (IS_MOBILE(dev_priv
->dev
))
1612 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1614 I915_WRITE(reg
, dpll
);
1618 if (wait_for(((I915_READ(reg
) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1619 DRM_ERROR("DPLL %d failed to lock\n", crtc
->pipe
);
1621 I915_WRITE(DPLL_MD(crtc
->pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1622 POSTING_READ(DPLL_MD(crtc
->pipe
));
1624 /* We do this three times for luck */
1625 I915_WRITE(reg
, dpll
);
1627 udelay(150); /* wait for warmup */
1628 I915_WRITE(reg
, dpll
);
1630 udelay(150); /* wait for warmup */
1631 I915_WRITE(reg
, dpll
);
1633 udelay(150); /* wait for warmup */
1636 static void chv_enable_pll(struct intel_crtc
*crtc
,
1637 const struct intel_crtc_state
*pipe_config
)
1639 struct drm_device
*dev
= crtc
->base
.dev
;
1640 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1641 int pipe
= crtc
->pipe
;
1642 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1645 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1647 BUG_ON(!IS_CHERRYVIEW(dev_priv
->dev
));
1649 mutex_lock(&dev_priv
->sb_lock
);
1651 /* Enable back the 10bit clock to display controller */
1652 tmp
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1653 tmp
|= DPIO_DCLKP_EN
;
1654 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), tmp
);
1656 mutex_unlock(&dev_priv
->sb_lock
);
1659 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1664 I915_WRITE(DPLL(pipe
), pipe_config
->dpll_hw_state
.dpll
);
1666 /* Check PLL is locked */
1667 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
1668 DRM_ERROR("PLL %d failed to lock\n", pipe
);
1670 /* not sure when this should be written */
1671 I915_WRITE(DPLL_MD(pipe
), pipe_config
->dpll_hw_state
.dpll_md
);
1672 POSTING_READ(DPLL_MD(pipe
));
1675 static int intel_num_dvo_pipes(struct drm_device
*dev
)
1677 struct intel_crtc
*crtc
;
1680 for_each_intel_crtc(dev
, crtc
)
1681 count
+= crtc
->base
.state
->active
&&
1682 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
);
1687 static void i9xx_enable_pll(struct intel_crtc
*crtc
)
1689 struct drm_device
*dev
= crtc
->base
.dev
;
1690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1691 int reg
= DPLL(crtc
->pipe
);
1692 u32 dpll
= crtc
->config
->dpll_hw_state
.dpll
;
1694 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
1696 /* No really, not for ILK+ */
1697 BUG_ON(INTEL_INFO(dev
)->gen
>= 5);
1699 /* PLL is protected by panel, make sure we can write it */
1700 if (IS_MOBILE(dev
) && !IS_I830(dev
))
1701 assert_panel_unlocked(dev_priv
, crtc
->pipe
);
1703 /* Enable DVO 2x clock on both PLLs if necessary */
1704 if (IS_I830(dev
) && intel_num_dvo_pipes(dev
) > 0) {
1706 * It appears to be important that we don't enable this
1707 * for the current pipe before otherwise configuring the
1708 * PLL. No idea how this should be handled if multiple
1709 * DVO outputs are enabled simultaneosly.
1711 dpll
|= DPLL_DVO_2X_MODE
;
1712 I915_WRITE(DPLL(!crtc
->pipe
),
1713 I915_READ(DPLL(!crtc
->pipe
)) | DPLL_DVO_2X_MODE
);
1717 * Apparently we need to have VGA mode enabled prior to changing
1718 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1719 * dividers, even though the register value does change.
1723 I915_WRITE(reg
, dpll
);
1725 /* Wait for the clocks to stabilize. */
1729 if (INTEL_INFO(dev
)->gen
>= 4) {
1730 I915_WRITE(DPLL_MD(crtc
->pipe
),
1731 crtc
->config
->dpll_hw_state
.dpll_md
);
1733 /* The pixel multiplier can only be updated once the
1734 * DPLL is enabled and the clocks are stable.
1736 * So write it again.
1738 I915_WRITE(reg
, dpll
);
1741 /* We do this three times for luck */
1742 I915_WRITE(reg
, dpll
);
1744 udelay(150); /* wait for warmup */
1745 I915_WRITE(reg
, dpll
);
1747 udelay(150); /* wait for warmup */
1748 I915_WRITE(reg
, dpll
);
1750 udelay(150); /* wait for warmup */
1754 * i9xx_disable_pll - disable a PLL
1755 * @dev_priv: i915 private structure
1756 * @pipe: pipe PLL to disable
1758 * Disable the PLL for @pipe, making sure the pipe is off first.
1760 * Note! This is for pre-ILK only.
1762 static void i9xx_disable_pll(struct intel_crtc
*crtc
)
1764 struct drm_device
*dev
= crtc
->base
.dev
;
1765 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1766 enum pipe pipe
= crtc
->pipe
;
1768 /* Disable DVO 2x clock on both PLLs if necessary */
1770 intel_pipe_has_type(crtc
, INTEL_OUTPUT_DVO
) &&
1771 !intel_num_dvo_pipes(dev
)) {
1772 I915_WRITE(DPLL(PIPE_B
),
1773 I915_READ(DPLL(PIPE_B
)) & ~DPLL_DVO_2X_MODE
);
1774 I915_WRITE(DPLL(PIPE_A
),
1775 I915_READ(DPLL(PIPE_A
)) & ~DPLL_DVO_2X_MODE
);
1778 /* Don't disable pipe or pipe PLLs if needed */
1779 if ((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
1780 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
1783 /* Make sure the pipe isn't still relying on us */
1784 assert_pipe_disabled(dev_priv
, pipe
);
1786 I915_WRITE(DPLL(pipe
), DPLL_VGA_MODE_DIS
);
1787 POSTING_READ(DPLL(pipe
));
1790 static void vlv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1794 /* Make sure the pipe isn't still relying on us */
1795 assert_pipe_disabled(dev_priv
, pipe
);
1798 * Leave integrated clock source and reference clock enabled for pipe B.
1799 * The latter is needed for VGA hotplug / manual detection.
1801 val
= DPLL_VGA_MODE_DIS
;
1803 val
= DPLL_INTEGRATED_CRI_CLK_VLV
| DPLL_REF_CLK_ENABLE_VLV
;
1804 I915_WRITE(DPLL(pipe
), val
);
1805 POSTING_READ(DPLL(pipe
));
1809 static void chv_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1811 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
1814 /* Make sure the pipe isn't still relying on us */
1815 assert_pipe_disabled(dev_priv
, pipe
);
1817 /* Set PLL en = 0 */
1818 val
= DPLL_SSC_REF_CLK_CHV
|
1819 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
;
1821 val
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
1822 I915_WRITE(DPLL(pipe
), val
);
1823 POSTING_READ(DPLL(pipe
));
1825 mutex_lock(&dev_priv
->sb_lock
);
1827 /* Disable 10bit clock to display controller */
1828 val
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
));
1829 val
&= ~DPIO_DCLKP_EN
;
1830 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
), val
);
1832 mutex_unlock(&dev_priv
->sb_lock
);
1835 void vlv_wait_port_ready(struct drm_i915_private
*dev_priv
,
1836 struct intel_digital_port
*dport
,
1837 unsigned int expected_mask
)
1842 switch (dport
->port
) {
1844 port_mask
= DPLL_PORTB_READY_MASK
;
1848 port_mask
= DPLL_PORTC_READY_MASK
;
1850 expected_mask
<<= 4;
1853 port_mask
= DPLL_PORTD_READY_MASK
;
1854 dpll_reg
= DPIO_PHY_STATUS
;
1860 if (wait_for((I915_READ(dpll_reg
) & port_mask
) == expected_mask
, 1000))
1861 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1862 port_name(dport
->port
), I915_READ(dpll_reg
) & port_mask
, expected_mask
);
1865 static void intel_prepare_shared_dpll(struct intel_crtc
*crtc
)
1867 struct drm_device
*dev
= crtc
->base
.dev
;
1868 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1869 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1871 if (WARN_ON(pll
== NULL
))
1874 WARN_ON(!pll
->config
.crtc_mask
);
1875 if (pll
->active
== 0) {
1876 DRM_DEBUG_DRIVER("setting up %s\n", pll
->name
);
1878 assert_shared_dpll_disabled(dev_priv
, pll
);
1880 pll
->mode_set(dev_priv
, pll
);
1885 * intel_enable_shared_dpll - enable PCH PLL
1886 * @dev_priv: i915 private structure
1887 * @pipe: pipe PLL to enable
1889 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1890 * drives the transcoder clock.
1892 static void intel_enable_shared_dpll(struct intel_crtc
*crtc
)
1894 struct drm_device
*dev
= crtc
->base
.dev
;
1895 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1896 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1898 if (WARN_ON(pll
== NULL
))
1901 if (WARN_ON(pll
->config
.crtc_mask
== 0))
1904 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1905 pll
->name
, pll
->active
, pll
->on
,
1906 crtc
->base
.base
.id
);
1908 if (pll
->active
++) {
1910 assert_shared_dpll_enabled(dev_priv
, pll
);
1915 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
1917 DRM_DEBUG_KMS("enabling %s\n", pll
->name
);
1918 pll
->enable(dev_priv
, pll
);
1922 static void intel_disable_shared_dpll(struct intel_crtc
*crtc
)
1924 struct drm_device
*dev
= crtc
->base
.dev
;
1925 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1926 struct intel_shared_dpll
*pll
= intel_crtc_to_shared_dpll(crtc
);
1928 /* PCH only available on ILK+ */
1929 if (INTEL_INFO(dev
)->gen
< 5)
1935 if (WARN_ON(!(pll
->config
.crtc_mask
& (1 << drm_crtc_index(&crtc
->base
)))))
1938 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1939 pll
->name
, pll
->active
, pll
->on
,
1940 crtc
->base
.base
.id
);
1942 if (WARN_ON(pll
->active
== 0)) {
1943 assert_shared_dpll_disabled(dev_priv
, pll
);
1947 assert_shared_dpll_enabled(dev_priv
, pll
);
1952 DRM_DEBUG_KMS("disabling %s\n", pll
->name
);
1953 pll
->disable(dev_priv
, pll
);
1956 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
1959 static void ironlake_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
1962 struct drm_device
*dev
= dev_priv
->dev
;
1963 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1964 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1965 uint32_t reg
, val
, pipeconf_val
;
1967 /* PCH only available on ILK+ */
1968 BUG_ON(!HAS_PCH_SPLIT(dev
));
1970 /* Make sure PCH DPLL is enabled */
1971 assert_shared_dpll_enabled(dev_priv
,
1972 intel_crtc_to_shared_dpll(intel_crtc
));
1974 /* FDI must be feeding us bits for PCH ports */
1975 assert_fdi_tx_enabled(dev_priv
, pipe
);
1976 assert_fdi_rx_enabled(dev_priv
, pipe
);
1978 if (HAS_PCH_CPT(dev
)) {
1979 /* Workaround: Set the timing override bit before enabling the
1980 * pch transcoder. */
1981 reg
= TRANS_CHICKEN2(pipe
);
1982 val
= I915_READ(reg
);
1983 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
1984 I915_WRITE(reg
, val
);
1987 reg
= PCH_TRANSCONF(pipe
);
1988 val
= I915_READ(reg
);
1989 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1991 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1993 * Make the BPC in transcoder be consistent with
1994 * that in pipeconf reg. For HDMI we must use 8bpc
1995 * here for both 8bpc and 12bpc.
1997 val
&= ~PIPECONF_BPC_MASK
;
1998 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_HDMI
))
1999 val
|= PIPECONF_8BPC
;
2001 val
|= pipeconf_val
& PIPECONF_BPC_MASK
;
2004 val
&= ~TRANS_INTERLACE_MASK
;
2005 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
2006 if (HAS_PCH_IBX(dev_priv
->dev
) &&
2007 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
2008 val
|= TRANS_LEGACY_INTERLACED_ILK
;
2010 val
|= TRANS_INTERLACED
;
2012 val
|= TRANS_PROGRESSIVE
;
2014 I915_WRITE(reg
, val
| TRANS_ENABLE
);
2015 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
2016 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe
));
2019 static void lpt_enable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2020 enum transcoder cpu_transcoder
)
2022 u32 val
, pipeconf_val
;
2024 /* PCH only available on ILK+ */
2025 BUG_ON(!HAS_PCH_SPLIT(dev_priv
->dev
));
2027 /* FDI must be feeding us bits for PCH ports */
2028 assert_fdi_tx_enabled(dev_priv
, (enum pipe
) cpu_transcoder
);
2029 assert_fdi_rx_enabled(dev_priv
, TRANSCODER_A
);
2031 /* Workaround: set timing override bit. */
2032 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
2033 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
2034 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
2037 pipeconf_val
= I915_READ(PIPECONF(cpu_transcoder
));
2039 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK_HSW
) ==
2040 PIPECONF_INTERLACED_ILK
)
2041 val
|= TRANS_INTERLACED
;
2043 val
|= TRANS_PROGRESSIVE
;
2045 I915_WRITE(LPT_TRANSCONF
, val
);
2046 if (wait_for(I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
, 100))
2047 DRM_ERROR("Failed to enable PCH transcoder\n");
2050 static void ironlake_disable_pch_transcoder(struct drm_i915_private
*dev_priv
,
2053 struct drm_device
*dev
= dev_priv
->dev
;
2056 /* FDI relies on the transcoder */
2057 assert_fdi_tx_disabled(dev_priv
, pipe
);
2058 assert_fdi_rx_disabled(dev_priv
, pipe
);
2060 /* Ports must be off as well */
2061 assert_pch_ports_disabled(dev_priv
, pipe
);
2063 reg
= PCH_TRANSCONF(pipe
);
2064 val
= I915_READ(reg
);
2065 val
&= ~TRANS_ENABLE
;
2066 I915_WRITE(reg
, val
);
2067 /* wait for PCH transcoder off, transcoder state */
2068 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
2069 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe
));
2071 if (!HAS_PCH_IBX(dev
)) {
2072 /* Workaround: Clear the timing override chicken bit again. */
2073 reg
= TRANS_CHICKEN2(pipe
);
2074 val
= I915_READ(reg
);
2075 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2076 I915_WRITE(reg
, val
);
2080 static void lpt_disable_pch_transcoder(struct drm_i915_private
*dev_priv
)
2084 val
= I915_READ(LPT_TRANSCONF
);
2085 val
&= ~TRANS_ENABLE
;
2086 I915_WRITE(LPT_TRANSCONF
, val
);
2087 /* wait for PCH transcoder off, transcoder state */
2088 if (wait_for((I915_READ(LPT_TRANSCONF
) & TRANS_STATE_ENABLE
) == 0, 50))
2089 DRM_ERROR("Failed to disable PCH transcoder\n");
2091 /* Workaround: clear timing override bit. */
2092 val
= I915_READ(TRANS_CHICKEN2(PIPE_A
));
2093 val
&= ~TRANS_CHICKEN2_TIMING_OVERRIDE
;
2094 I915_WRITE(TRANS_CHICKEN2(PIPE_A
), val
);
2098 * intel_enable_pipe - enable a pipe, asserting requirements
2099 * @crtc: crtc responsible for the pipe
2101 * Enable @crtc's pipe, making sure that various hardware specific requirements
2102 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2104 static void intel_enable_pipe(struct intel_crtc
*crtc
)
2106 struct drm_device
*dev
= crtc
->base
.dev
;
2107 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2108 enum pipe pipe
= crtc
->pipe
;
2109 enum transcoder cpu_transcoder
= intel_pipe_to_cpu_transcoder(dev_priv
,
2111 enum pipe pch_transcoder
;
2115 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe
));
2117 assert_planes_disabled(dev_priv
, pipe
);
2118 assert_cursor_disabled(dev_priv
, pipe
);
2119 assert_sprites_disabled(dev_priv
, pipe
);
2121 if (HAS_PCH_LPT(dev_priv
->dev
))
2122 pch_transcoder
= TRANSCODER_A
;
2124 pch_transcoder
= pipe
;
2127 * A pipe without a PLL won't actually be able to drive bits from
2128 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2131 if (HAS_GMCH_DISPLAY(dev_priv
->dev
))
2132 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DSI
))
2133 assert_dsi_pll_enabled(dev_priv
);
2135 assert_pll_enabled(dev_priv
, pipe
);
2137 if (crtc
->config
->has_pch_encoder
) {
2138 /* if driving the PCH, we need FDI enabled */
2139 assert_fdi_rx_pll_enabled(dev_priv
, pch_transcoder
);
2140 assert_fdi_tx_pll_enabled(dev_priv
,
2141 (enum pipe
) cpu_transcoder
);
2143 /* FIXME: assert CPU port conditions for SNB+ */
2146 reg
= PIPECONF(cpu_transcoder
);
2147 val
= I915_READ(reg
);
2148 if (val
& PIPECONF_ENABLE
) {
2149 WARN_ON(!((pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
2150 (pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
)));
2154 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
2159 * intel_disable_pipe - disable a pipe, asserting requirements
2160 * @crtc: crtc whose pipes is to be disabled
2162 * Disable the pipe of @crtc, making sure that various hardware
2163 * specific requirements are met, if applicable, e.g. plane
2164 * disabled, panel fitter off, etc.
2166 * Will wait until the pipe has shut down before returning.
2168 static void intel_disable_pipe(struct intel_crtc
*crtc
)
2170 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
2171 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
2172 enum pipe pipe
= crtc
->pipe
;
2176 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe
));
2179 * Make sure planes won't keep trying to pump pixels to us,
2180 * or we might hang the display.
2182 assert_planes_disabled(dev_priv
, pipe
);
2183 assert_cursor_disabled(dev_priv
, pipe
);
2184 assert_sprites_disabled(dev_priv
, pipe
);
2186 reg
= PIPECONF(cpu_transcoder
);
2187 val
= I915_READ(reg
);
2188 if ((val
& PIPECONF_ENABLE
) == 0)
2192 * Double wide has implications for planes
2193 * so best keep it disabled when not needed.
2195 if (crtc
->config
->double_wide
)
2196 val
&= ~PIPECONF_DOUBLE_WIDE
;
2198 /* Don't disable pipe or pipe PLLs if needed */
2199 if (!(pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) &&
2200 !(pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
2201 val
&= ~PIPECONF_ENABLE
;
2203 I915_WRITE(reg
, val
);
2204 if ((val
& PIPECONF_ENABLE
) == 0)
2205 intel_wait_for_pipe_off(crtc
);
2208 static bool need_vtd_wa(struct drm_device
*dev
)
2210 #ifdef CONFIG_INTEL_IOMMU
2211 if (INTEL_INFO(dev
)->gen
>= 6 && intel_iommu_gfx_mapped
)
2218 intel_tile_height(struct drm_device
*dev
, uint32_t pixel_format
,
2219 uint64_t fb_format_modifier
, unsigned int plane
)
2221 unsigned int tile_height
;
2222 uint32_t pixel_bytes
;
2224 switch (fb_format_modifier
) {
2225 case DRM_FORMAT_MOD_NONE
:
2228 case I915_FORMAT_MOD_X_TILED
:
2229 tile_height
= IS_GEN2(dev
) ? 16 : 8;
2231 case I915_FORMAT_MOD_Y_TILED
:
2234 case I915_FORMAT_MOD_Yf_TILED
:
2235 pixel_bytes
= drm_format_plane_cpp(pixel_format
, plane
);
2236 switch (pixel_bytes
) {
2250 "128-bit pixels are not supported for display!");
2256 MISSING_CASE(fb_format_modifier
);
2265 intel_fb_align_height(struct drm_device
*dev
, unsigned int height
,
2266 uint32_t pixel_format
, uint64_t fb_format_modifier
)
2268 return ALIGN(height
, intel_tile_height(dev
, pixel_format
,
2269 fb_format_modifier
, 0));
2273 intel_fill_fb_ggtt_view(struct i915_ggtt_view
*view
, struct drm_framebuffer
*fb
,
2274 const struct drm_plane_state
*plane_state
)
2276 struct intel_rotation_info
*info
= &view
->rotation_info
;
2277 unsigned int tile_height
, tile_pitch
;
2279 *view
= i915_ggtt_view_normal
;
2284 if (!intel_rotation_90_or_270(plane_state
->rotation
))
2287 *view
= i915_ggtt_view_rotated
;
2289 info
->height
= fb
->height
;
2290 info
->pixel_format
= fb
->pixel_format
;
2291 info
->pitch
= fb
->pitches
[0];
2292 info
->uv_offset
= fb
->offsets
[1];
2293 info
->fb_modifier
= fb
->modifier
[0];
2295 tile_height
= intel_tile_height(fb
->dev
, fb
->pixel_format
,
2296 fb
->modifier
[0], 0);
2297 tile_pitch
= PAGE_SIZE
/ tile_height
;
2298 info
->width_pages
= DIV_ROUND_UP(fb
->pitches
[0], tile_pitch
);
2299 info
->height_pages
= DIV_ROUND_UP(fb
->height
, tile_height
);
2300 info
->size
= info
->width_pages
* info
->height_pages
* PAGE_SIZE
;
2302 if (info
->pixel_format
== DRM_FORMAT_NV12
) {
2303 tile_height
= intel_tile_height(fb
->dev
, fb
->pixel_format
,
2304 fb
->modifier
[0], 1);
2305 tile_pitch
= PAGE_SIZE
/ tile_height
;
2306 info
->width_pages_uv
= DIV_ROUND_UP(fb
->pitches
[0], tile_pitch
);
2307 info
->height_pages_uv
= DIV_ROUND_UP(fb
->height
/ 2,
2309 info
->size_uv
= info
->width_pages_uv
* info
->height_pages_uv
*
2316 static unsigned int intel_linear_alignment(struct drm_i915_private
*dev_priv
)
2318 if (INTEL_INFO(dev_priv
)->gen
>= 9)
2320 else if (IS_BROADWATER(dev_priv
) || IS_CRESTLINE(dev_priv
) ||
2321 IS_VALLEYVIEW(dev_priv
))
2323 else if (INTEL_INFO(dev_priv
)->gen
>= 4)
2330 intel_pin_and_fence_fb_obj(struct drm_plane
*plane
,
2331 struct drm_framebuffer
*fb
,
2332 const struct drm_plane_state
*plane_state
,
2333 struct intel_engine_cs
*pipelined
,
2334 struct drm_i915_gem_request
**pipelined_request
)
2336 struct drm_device
*dev
= fb
->dev
;
2337 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2338 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2339 struct i915_ggtt_view view
;
2343 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2345 switch (fb
->modifier
[0]) {
2346 case DRM_FORMAT_MOD_NONE
:
2347 alignment
= intel_linear_alignment(dev_priv
);
2349 case I915_FORMAT_MOD_X_TILED
:
2350 if (INTEL_INFO(dev
)->gen
>= 9)
2351 alignment
= 256 * 1024;
2353 /* pin() will align the object as required by fence */
2357 case I915_FORMAT_MOD_Y_TILED
:
2358 case I915_FORMAT_MOD_Yf_TILED
:
2359 if (WARN_ONCE(INTEL_INFO(dev
)->gen
< 9,
2360 "Y tiling bo slipped through, driver bug!\n"))
2362 alignment
= 1 * 1024 * 1024;
2365 MISSING_CASE(fb
->modifier
[0]);
2369 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2373 /* Note that the w/a also requires 64 PTE of padding following the
2374 * bo. We currently fill all unused PTE with the shadow page and so
2375 * we should always have valid PTE following the scanout preventing
2378 if (need_vtd_wa(dev
) && alignment
< 256 * 1024)
2379 alignment
= 256 * 1024;
2382 * Global gtt pte registers are special registers which actually forward
2383 * writes to a chunk of system memory. Which means that there is no risk
2384 * that the register values disappear as soon as we call
2385 * intel_runtime_pm_put(), so it is correct to wrap only the
2386 * pin/unpin/fence and not more.
2388 intel_runtime_pm_get(dev_priv
);
2390 dev_priv
->mm
.interruptible
= false;
2391 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
,
2392 pipelined_request
, &view
);
2394 goto err_interruptible
;
2396 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2397 * fence, whereas 965+ only requires a fence if using
2398 * framebuffer compression. For simplicity, we always install
2399 * a fence as the cost is not that onerous.
2401 if (view
.type
== I915_GGTT_VIEW_NORMAL
) {
2402 ret
= i915_gem_object_get_fence(obj
);
2403 if (ret
== -EDEADLK
) {
2405 * -EDEADLK means there are no free fences
2408 * This is propagated to atomic, but it uses
2409 * -EDEADLK to force a locking recovery, so
2410 * change the returned error to -EBUSY.
2417 i915_gem_object_pin_fence(obj
);
2420 dev_priv
->mm
.interruptible
= true;
2421 intel_runtime_pm_put(dev_priv
);
2425 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2427 dev_priv
->mm
.interruptible
= true;
2428 intel_runtime_pm_put(dev_priv
);
2432 static void intel_unpin_fb_obj(struct drm_framebuffer
*fb
,
2433 const struct drm_plane_state
*plane_state
)
2435 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
2436 struct i915_ggtt_view view
;
2439 WARN_ON(!mutex_is_locked(&obj
->base
.dev
->struct_mutex
));
2441 ret
= intel_fill_fb_ggtt_view(&view
, fb
, plane_state
);
2442 WARN_ONCE(ret
, "Couldn't get view from plane state!");
2444 if (view
.type
== I915_GGTT_VIEW_NORMAL
)
2445 i915_gem_object_unpin_fence(obj
);
2447 i915_gem_object_unpin_from_display_plane(obj
, &view
);
2450 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2451 * is assumed to be a power-of-two. */
2452 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private
*dev_priv
,
2454 unsigned int tiling_mode
,
2458 if (tiling_mode
!= I915_TILING_NONE
) {
2459 unsigned int tile_rows
, tiles
;
2464 tiles
= *x
/ (512/cpp
);
2467 return tile_rows
* pitch
* 8 + tiles
* 4096;
2469 unsigned int alignment
= intel_linear_alignment(dev_priv
) - 1;
2470 unsigned int offset
;
2472 offset
= *y
* pitch
+ *x
* cpp
;
2473 *y
= (offset
& alignment
) / pitch
;
2474 *x
= ((offset
& alignment
) - *y
* pitch
) / cpp
;
2475 return offset
& ~alignment
;
2479 static int i9xx_format_to_fourcc(int format
)
2482 case DISPPLANE_8BPP
:
2483 return DRM_FORMAT_C8
;
2484 case DISPPLANE_BGRX555
:
2485 return DRM_FORMAT_XRGB1555
;
2486 case DISPPLANE_BGRX565
:
2487 return DRM_FORMAT_RGB565
;
2489 case DISPPLANE_BGRX888
:
2490 return DRM_FORMAT_XRGB8888
;
2491 case DISPPLANE_RGBX888
:
2492 return DRM_FORMAT_XBGR8888
;
2493 case DISPPLANE_BGRX101010
:
2494 return DRM_FORMAT_XRGB2101010
;
2495 case DISPPLANE_RGBX101010
:
2496 return DRM_FORMAT_XBGR2101010
;
2500 static int skl_format_to_fourcc(int format
, bool rgb_order
, bool alpha
)
2503 case PLANE_CTL_FORMAT_RGB_565
:
2504 return DRM_FORMAT_RGB565
;
2506 case PLANE_CTL_FORMAT_XRGB_8888
:
2509 return DRM_FORMAT_ABGR8888
;
2511 return DRM_FORMAT_XBGR8888
;
2514 return DRM_FORMAT_ARGB8888
;
2516 return DRM_FORMAT_XRGB8888
;
2518 case PLANE_CTL_FORMAT_XRGB_2101010
:
2520 return DRM_FORMAT_XBGR2101010
;
2522 return DRM_FORMAT_XRGB2101010
;
2527 intel_alloc_initial_plane_obj(struct intel_crtc
*crtc
,
2528 struct intel_initial_plane_config
*plane_config
)
2530 struct drm_device
*dev
= crtc
->base
.dev
;
2531 struct drm_i915_private
*dev_priv
= to_i915(dev
);
2532 struct drm_i915_gem_object
*obj
= NULL
;
2533 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
2534 struct drm_framebuffer
*fb
= &plane_config
->fb
->base
;
2535 u32 base_aligned
= round_down(plane_config
->base
, PAGE_SIZE
);
2536 u32 size_aligned
= round_up(plane_config
->base
+ plane_config
->size
,
2539 size_aligned
-= base_aligned
;
2541 if (plane_config
->size
== 0)
2544 /* If the FB is too big, just don't use it since fbdev is not very
2545 * important and we should probably use that space with FBC or other
2547 if (size_aligned
* 2 > dev_priv
->gtt
.stolen_usable_size
)
2550 obj
= i915_gem_object_create_stolen_for_preallocated(dev
,
2557 obj
->tiling_mode
= plane_config
->tiling
;
2558 if (obj
->tiling_mode
== I915_TILING_X
)
2559 obj
->stride
= fb
->pitches
[0];
2561 mode_cmd
.pixel_format
= fb
->pixel_format
;
2562 mode_cmd
.width
= fb
->width
;
2563 mode_cmd
.height
= fb
->height
;
2564 mode_cmd
.pitches
[0] = fb
->pitches
[0];
2565 mode_cmd
.modifier
[0] = fb
->modifier
[0];
2566 mode_cmd
.flags
= DRM_MODE_FB_MODIFIERS
;
2568 mutex_lock(&dev
->struct_mutex
);
2569 if (intel_framebuffer_init(dev
, to_intel_framebuffer(fb
),
2571 DRM_DEBUG_KMS("intel fb init failed\n");
2574 mutex_unlock(&dev
->struct_mutex
);
2576 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj
);
2580 drm_gem_object_unreference(&obj
->base
);
2581 mutex_unlock(&dev
->struct_mutex
);
2585 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2587 update_state_fb(struct drm_plane
*plane
)
2589 if (plane
->fb
== plane
->state
->fb
)
2592 if (plane
->state
->fb
)
2593 drm_framebuffer_unreference(plane
->state
->fb
);
2594 plane
->state
->fb
= plane
->fb
;
2595 if (plane
->state
->fb
)
2596 drm_framebuffer_reference(plane
->state
->fb
);
2600 intel_find_initial_plane_obj(struct intel_crtc
*intel_crtc
,
2601 struct intel_initial_plane_config
*plane_config
)
2603 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2604 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2606 struct intel_crtc
*i
;
2607 struct drm_i915_gem_object
*obj
;
2608 struct drm_plane
*primary
= intel_crtc
->base
.primary
;
2609 struct drm_plane_state
*plane_state
= primary
->state
;
2610 struct drm_framebuffer
*fb
;
2612 if (!plane_config
->fb
)
2615 if (intel_alloc_initial_plane_obj(intel_crtc
, plane_config
)) {
2616 fb
= &plane_config
->fb
->base
;
2620 kfree(plane_config
->fb
);
2623 * Failed to alloc the obj, check to see if we should share
2624 * an fb with another CRTC instead
2626 for_each_crtc(dev
, c
) {
2627 i
= to_intel_crtc(c
);
2629 if (c
== &intel_crtc
->base
)
2635 fb
= c
->primary
->fb
;
2639 obj
= intel_fb_obj(fb
);
2640 if (i915_gem_obj_ggtt_offset(obj
) == plane_config
->base
) {
2641 drm_framebuffer_reference(fb
);
2649 plane_state
->src_x
= 0;
2650 plane_state
->src_y
= 0;
2651 plane_state
->src_w
= fb
->width
<< 16;
2652 plane_state
->src_h
= fb
->height
<< 16;
2654 plane_state
->crtc_x
= 0;
2655 plane_state
->crtc_y
= 0;
2656 plane_state
->crtc_w
= fb
->width
;
2657 plane_state
->crtc_h
= fb
->height
;
2659 obj
= intel_fb_obj(fb
);
2660 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2661 dev_priv
->preserve_bios_swizzle
= true;
2663 drm_framebuffer_reference(fb
);
2664 primary
->fb
= primary
->state
->fb
= fb
;
2665 primary
->crtc
= primary
->state
->crtc
= &intel_crtc
->base
;
2666 intel_crtc
->base
.state
->plane_mask
|= (1 << drm_plane_index(primary
));
2667 obj
->frontbuffer_bits
|= to_intel_plane(primary
)->frontbuffer_bit
;
2670 static void i9xx_update_primary_plane(struct drm_crtc
*crtc
,
2671 struct drm_framebuffer
*fb
,
2674 struct drm_device
*dev
= crtc
->dev
;
2675 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2676 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2677 struct drm_plane
*primary
= crtc
->primary
;
2678 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2679 struct drm_i915_gem_object
*obj
;
2680 int plane
= intel_crtc
->plane
;
2681 unsigned long linear_offset
;
2683 u32 reg
= DSPCNTR(plane
);
2686 if (!visible
|| !fb
) {
2688 if (INTEL_INFO(dev
)->gen
>= 4)
2689 I915_WRITE(DSPSURF(plane
), 0);
2691 I915_WRITE(DSPADDR(plane
), 0);
2696 obj
= intel_fb_obj(fb
);
2697 if (WARN_ON(obj
== NULL
))
2700 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2702 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2704 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2706 if (INTEL_INFO(dev
)->gen
< 4) {
2707 if (intel_crtc
->pipe
== PIPE_B
)
2708 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
2710 /* pipesrc and dspsize control the size that is scaled from,
2711 * which should always be the user's requested size.
2713 I915_WRITE(DSPSIZE(plane
),
2714 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2715 (intel_crtc
->config
->pipe_src_w
- 1));
2716 I915_WRITE(DSPPOS(plane
), 0);
2717 } else if (IS_CHERRYVIEW(dev
) && plane
== PLANE_B
) {
2718 I915_WRITE(PRIMSIZE(plane
),
2719 ((intel_crtc
->config
->pipe_src_h
- 1) << 16) |
2720 (intel_crtc
->config
->pipe_src_w
- 1));
2721 I915_WRITE(PRIMPOS(plane
), 0);
2722 I915_WRITE(PRIMCNSTALPHA(plane
), 0);
2725 switch (fb
->pixel_format
) {
2727 dspcntr
|= DISPPLANE_8BPP
;
2729 case DRM_FORMAT_XRGB1555
:
2730 dspcntr
|= DISPPLANE_BGRX555
;
2732 case DRM_FORMAT_RGB565
:
2733 dspcntr
|= DISPPLANE_BGRX565
;
2735 case DRM_FORMAT_XRGB8888
:
2736 dspcntr
|= DISPPLANE_BGRX888
;
2738 case DRM_FORMAT_XBGR8888
:
2739 dspcntr
|= DISPPLANE_RGBX888
;
2741 case DRM_FORMAT_XRGB2101010
:
2742 dspcntr
|= DISPPLANE_BGRX101010
;
2744 case DRM_FORMAT_XBGR2101010
:
2745 dspcntr
|= DISPPLANE_RGBX101010
;
2751 if (INTEL_INFO(dev
)->gen
>= 4 &&
2752 obj
->tiling_mode
!= I915_TILING_NONE
)
2753 dspcntr
|= DISPPLANE_TILED
;
2756 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2758 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2760 if (INTEL_INFO(dev
)->gen
>= 4) {
2761 intel_crtc
->dspaddr_offset
=
2762 intel_gen4_compute_page_offset(dev_priv
,
2763 &x
, &y
, obj
->tiling_mode
,
2766 linear_offset
-= intel_crtc
->dspaddr_offset
;
2768 intel_crtc
->dspaddr_offset
= linear_offset
;
2771 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2772 dspcntr
|= DISPPLANE_ROTATE_180
;
2774 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2775 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2777 /* Finding the last pixel of the last line of the display
2778 data and adding to linear_offset*/
2780 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2781 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2784 intel_crtc
->adjusted_x
= x
;
2785 intel_crtc
->adjusted_y
= y
;
2787 I915_WRITE(reg
, dspcntr
);
2789 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2790 if (INTEL_INFO(dev
)->gen
>= 4) {
2791 I915_WRITE(DSPSURF(plane
),
2792 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2793 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2794 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2796 I915_WRITE(DSPADDR(plane
), i915_gem_obj_ggtt_offset(obj
) + linear_offset
);
2800 static void ironlake_update_primary_plane(struct drm_crtc
*crtc
,
2801 struct drm_framebuffer
*fb
,
2804 struct drm_device
*dev
= crtc
->dev
;
2805 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2806 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2807 struct drm_plane
*primary
= crtc
->primary
;
2808 bool visible
= to_intel_plane_state(primary
->state
)->visible
;
2809 struct drm_i915_gem_object
*obj
;
2810 int plane
= intel_crtc
->plane
;
2811 unsigned long linear_offset
;
2813 u32 reg
= DSPCNTR(plane
);
2816 if (!visible
|| !fb
) {
2818 I915_WRITE(DSPSURF(plane
), 0);
2823 obj
= intel_fb_obj(fb
);
2824 if (WARN_ON(obj
== NULL
))
2827 pixel_size
= drm_format_plane_cpp(fb
->pixel_format
, 0);
2829 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
2831 dspcntr
|= DISPLAY_PLANE_ENABLE
;
2833 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2834 dspcntr
|= DISPPLANE_PIPE_CSC_ENABLE
;
2836 switch (fb
->pixel_format
) {
2838 dspcntr
|= DISPPLANE_8BPP
;
2840 case DRM_FORMAT_RGB565
:
2841 dspcntr
|= DISPPLANE_BGRX565
;
2843 case DRM_FORMAT_XRGB8888
:
2844 dspcntr
|= DISPPLANE_BGRX888
;
2846 case DRM_FORMAT_XBGR8888
:
2847 dspcntr
|= DISPPLANE_RGBX888
;
2849 case DRM_FORMAT_XRGB2101010
:
2850 dspcntr
|= DISPPLANE_BGRX101010
;
2852 case DRM_FORMAT_XBGR2101010
:
2853 dspcntr
|= DISPPLANE_RGBX101010
;
2859 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2860 dspcntr
|= DISPPLANE_TILED
;
2862 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
))
2863 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2865 linear_offset
= y
* fb
->pitches
[0] + x
* pixel_size
;
2866 intel_crtc
->dspaddr_offset
=
2867 intel_gen4_compute_page_offset(dev_priv
,
2868 &x
, &y
, obj
->tiling_mode
,
2871 linear_offset
-= intel_crtc
->dspaddr_offset
;
2872 if (crtc
->primary
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
2873 dspcntr
|= DISPPLANE_ROTATE_180
;
2875 if (!IS_HASWELL(dev
) && !IS_BROADWELL(dev
)) {
2876 x
+= (intel_crtc
->config
->pipe_src_w
- 1);
2877 y
+= (intel_crtc
->config
->pipe_src_h
- 1);
2879 /* Finding the last pixel of the last line of the display
2880 data and adding to linear_offset*/
2882 (intel_crtc
->config
->pipe_src_h
- 1) * fb
->pitches
[0] +
2883 (intel_crtc
->config
->pipe_src_w
- 1) * pixel_size
;
2887 intel_crtc
->adjusted_x
= x
;
2888 intel_crtc
->adjusted_y
= y
;
2890 I915_WRITE(reg
, dspcntr
);
2892 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2893 I915_WRITE(DSPSURF(plane
),
2894 i915_gem_obj_ggtt_offset(obj
) + intel_crtc
->dspaddr_offset
);
2895 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2896 I915_WRITE(DSPOFFSET(plane
), (y
<< 16) | x
);
2898 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2899 I915_WRITE(DSPLINOFF(plane
), linear_offset
);
2904 u32
intel_fb_stride_alignment(struct drm_device
*dev
, uint64_t fb_modifier
,
2905 uint32_t pixel_format
)
2907 u32 bits_per_pixel
= drm_format_plane_cpp(pixel_format
, 0) * 8;
2910 * The stride is either expressed as a multiple of 64 bytes
2911 * chunks for linear buffers or in number of tiles for tiled
2914 switch (fb_modifier
) {
2915 case DRM_FORMAT_MOD_NONE
:
2917 case I915_FORMAT_MOD_X_TILED
:
2918 if (INTEL_INFO(dev
)->gen
== 2)
2921 case I915_FORMAT_MOD_Y_TILED
:
2922 /* No need to check for old gens and Y tiling since this is
2923 * about the display engine and those will be blocked before
2927 case I915_FORMAT_MOD_Yf_TILED
:
2928 if (bits_per_pixel
== 8)
2933 MISSING_CASE(fb_modifier
);
2938 unsigned long intel_plane_obj_offset(struct intel_plane
*intel_plane
,
2939 struct drm_i915_gem_object
*obj
,
2942 const struct i915_ggtt_view
*view
= &i915_ggtt_view_normal
;
2943 struct i915_vma
*vma
;
2944 unsigned char *offset
;
2946 if (intel_rotation_90_or_270(intel_plane
->base
.state
->rotation
))
2947 view
= &i915_ggtt_view_rotated
;
2949 vma
= i915_gem_obj_to_ggtt_view(obj
, view
);
2950 if (WARN(!vma
, "ggtt vma for display object not found! (view=%u)\n",
2954 offset
= (unsigned char *)vma
->node
.start
;
2957 offset
+= vma
->ggtt_view
.rotation_info
.uv_start_page
*
2961 return (unsigned long)offset
;
2964 static void skl_detach_scaler(struct intel_crtc
*intel_crtc
, int id
)
2966 struct drm_device
*dev
= intel_crtc
->base
.dev
;
2967 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2969 I915_WRITE(SKL_PS_CTRL(intel_crtc
->pipe
, id
), 0);
2970 I915_WRITE(SKL_PS_WIN_POS(intel_crtc
->pipe
, id
), 0);
2971 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc
->pipe
, id
), 0);
2975 * This function detaches (aka. unbinds) unused scalers in hardware
2977 static void skl_detach_scalers(struct intel_crtc
*intel_crtc
)
2979 struct intel_crtc_scaler_state
*scaler_state
;
2982 scaler_state
= &intel_crtc
->config
->scaler_state
;
2984 /* loop through and disable scalers that aren't in use */
2985 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
2986 if (!scaler_state
->scalers
[i
].in_use
)
2987 skl_detach_scaler(intel_crtc
, i
);
2991 u32
skl_plane_ctl_format(uint32_t pixel_format
)
2993 switch (pixel_format
) {
2995 return PLANE_CTL_FORMAT_INDEXED
;
2996 case DRM_FORMAT_RGB565
:
2997 return PLANE_CTL_FORMAT_RGB_565
;
2998 case DRM_FORMAT_XBGR8888
:
2999 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
;
3000 case DRM_FORMAT_XRGB8888
:
3001 return PLANE_CTL_FORMAT_XRGB_8888
;
3003 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3004 * to be already pre-multiplied. We need to add a knob (or a different
3005 * DRM_FORMAT) for user-space to configure that.
3007 case DRM_FORMAT_ABGR8888
:
3008 return PLANE_CTL_FORMAT_XRGB_8888
| PLANE_CTL_ORDER_RGBX
|
3009 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3010 case DRM_FORMAT_ARGB8888
:
3011 return PLANE_CTL_FORMAT_XRGB_8888
|
3012 PLANE_CTL_ALPHA_SW_PREMULTIPLY
;
3013 case DRM_FORMAT_XRGB2101010
:
3014 return PLANE_CTL_FORMAT_XRGB_2101010
;
3015 case DRM_FORMAT_XBGR2101010
:
3016 return PLANE_CTL_ORDER_RGBX
| PLANE_CTL_FORMAT_XRGB_2101010
;
3017 case DRM_FORMAT_YUYV
:
3018 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YUYV
;
3019 case DRM_FORMAT_YVYU
:
3020 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_YVYU
;
3021 case DRM_FORMAT_UYVY
:
3022 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_UYVY
;
3023 case DRM_FORMAT_VYUY
:
3024 return PLANE_CTL_FORMAT_YUV422
| PLANE_CTL_YUV422_VYUY
;
3026 MISSING_CASE(pixel_format
);
3032 u32
skl_plane_ctl_tiling(uint64_t fb_modifier
)
3034 switch (fb_modifier
) {
3035 case DRM_FORMAT_MOD_NONE
:
3037 case I915_FORMAT_MOD_X_TILED
:
3038 return PLANE_CTL_TILED_X
;
3039 case I915_FORMAT_MOD_Y_TILED
:
3040 return PLANE_CTL_TILED_Y
;
3041 case I915_FORMAT_MOD_Yf_TILED
:
3042 return PLANE_CTL_TILED_YF
;
3044 MISSING_CASE(fb_modifier
);
3050 u32
skl_plane_ctl_rotation(unsigned int rotation
)
3053 case BIT(DRM_ROTATE_0
):
3056 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3057 * while i915 HW rotation is clockwise, thats why this swapping.
3059 case BIT(DRM_ROTATE_90
):
3060 return PLANE_CTL_ROTATE_270
;
3061 case BIT(DRM_ROTATE_180
):
3062 return PLANE_CTL_ROTATE_180
;
3063 case BIT(DRM_ROTATE_270
):
3064 return PLANE_CTL_ROTATE_90
;
3066 MISSING_CASE(rotation
);
3072 static void skylake_update_primary_plane(struct drm_crtc
*crtc
,
3073 struct drm_framebuffer
*fb
,
3076 struct drm_device
*dev
= crtc
->dev
;
3077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3078 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3079 struct drm_plane
*plane
= crtc
->primary
;
3080 bool visible
= to_intel_plane_state(plane
->state
)->visible
;
3081 struct drm_i915_gem_object
*obj
;
3082 int pipe
= intel_crtc
->pipe
;
3083 u32 plane_ctl
, stride_div
, stride
;
3084 u32 tile_height
, plane_offset
, plane_size
;
3085 unsigned int rotation
;
3086 int x_offset
, y_offset
;
3087 unsigned long surf_addr
;
3088 struct intel_crtc_state
*crtc_state
= intel_crtc
->config
;
3089 struct intel_plane_state
*plane_state
;
3090 int src_x
= 0, src_y
= 0, src_w
= 0, src_h
= 0;
3091 int dst_x
= 0, dst_y
= 0, dst_w
= 0, dst_h
= 0;
3094 plane_state
= to_intel_plane_state(plane
->state
);
3096 if (!visible
|| !fb
) {
3097 I915_WRITE(PLANE_CTL(pipe
, 0), 0);
3098 I915_WRITE(PLANE_SURF(pipe
, 0), 0);
3099 POSTING_READ(PLANE_CTL(pipe
, 0));
3103 plane_ctl
= PLANE_CTL_ENABLE
|
3104 PLANE_CTL_PIPE_GAMMA_ENABLE
|
3105 PLANE_CTL_PIPE_CSC_ENABLE
;
3107 plane_ctl
|= skl_plane_ctl_format(fb
->pixel_format
);
3108 plane_ctl
|= skl_plane_ctl_tiling(fb
->modifier
[0]);
3109 plane_ctl
|= PLANE_CTL_PLANE_GAMMA_DISABLE
;
3111 rotation
= plane
->state
->rotation
;
3112 plane_ctl
|= skl_plane_ctl_rotation(rotation
);
3114 obj
= intel_fb_obj(fb
);
3115 stride_div
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
3117 surf_addr
= intel_plane_obj_offset(to_intel_plane(plane
), obj
, 0);
3119 WARN_ON(drm_rect_width(&plane_state
->src
) == 0);
3121 scaler_id
= plane_state
->scaler_id
;
3122 src_x
= plane_state
->src
.x1
>> 16;
3123 src_y
= plane_state
->src
.y1
>> 16;
3124 src_w
= drm_rect_width(&plane_state
->src
) >> 16;
3125 src_h
= drm_rect_height(&plane_state
->src
) >> 16;
3126 dst_x
= plane_state
->dst
.x1
;
3127 dst_y
= plane_state
->dst
.y1
;
3128 dst_w
= drm_rect_width(&plane_state
->dst
);
3129 dst_h
= drm_rect_height(&plane_state
->dst
);
3131 WARN_ON(x
!= src_x
|| y
!= src_y
);
3133 if (intel_rotation_90_or_270(rotation
)) {
3134 /* stride = Surface height in tiles */
3135 tile_height
= intel_tile_height(dev
, fb
->pixel_format
,
3136 fb
->modifier
[0], 0);
3137 stride
= DIV_ROUND_UP(fb
->height
, tile_height
);
3138 x_offset
= stride
* tile_height
- y
- src_h
;
3140 plane_size
= (src_w
- 1) << 16 | (src_h
- 1);
3142 stride
= fb
->pitches
[0] / stride_div
;
3145 plane_size
= (src_h
- 1) << 16 | (src_w
- 1);
3147 plane_offset
= y_offset
<< 16 | x_offset
;
3149 intel_crtc
->adjusted_x
= x_offset
;
3150 intel_crtc
->adjusted_y
= y_offset
;
3152 I915_WRITE(PLANE_CTL(pipe
, 0), plane_ctl
);
3153 I915_WRITE(PLANE_OFFSET(pipe
, 0), plane_offset
);
3154 I915_WRITE(PLANE_SIZE(pipe
, 0), plane_size
);
3155 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
3157 if (scaler_id
>= 0) {
3158 uint32_t ps_ctrl
= 0;
3160 WARN_ON(!dst_w
|| !dst_h
);
3161 ps_ctrl
= PS_SCALER_EN
| PS_PLANE_SEL(0) |
3162 crtc_state
->scaler_state
.scalers
[scaler_id
].mode
;
3163 I915_WRITE(SKL_PS_CTRL(pipe
, scaler_id
), ps_ctrl
);
3164 I915_WRITE(SKL_PS_PWR_GATE(pipe
, scaler_id
), 0);
3165 I915_WRITE(SKL_PS_WIN_POS(pipe
, scaler_id
), (dst_x
<< 16) | dst_y
);
3166 I915_WRITE(SKL_PS_WIN_SZ(pipe
, scaler_id
), (dst_w
<< 16) | dst_h
);
3167 I915_WRITE(PLANE_POS(pipe
, 0), 0);
3169 I915_WRITE(PLANE_POS(pipe
, 0), (dst_y
<< 16) | dst_x
);
3172 I915_WRITE(PLANE_SURF(pipe
, 0), surf_addr
);
3174 POSTING_READ(PLANE_SURF(pipe
, 0));
3177 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3179 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
3180 int x
, int y
, enum mode_set_atomic state
)
3182 struct drm_device
*dev
= crtc
->dev
;
3183 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3185 if (dev_priv
->fbc
.disable_fbc
)
3186 dev_priv
->fbc
.disable_fbc(dev_priv
);
3188 dev_priv
->display
.update_primary_plane(crtc
, fb
, x
, y
);
3193 static void intel_complete_page_flips(struct drm_device
*dev
)
3195 struct drm_crtc
*crtc
;
3197 for_each_crtc(dev
, crtc
) {
3198 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3199 enum plane plane
= intel_crtc
->plane
;
3201 intel_prepare_page_flip(dev
, plane
);
3202 intel_finish_page_flip_plane(dev
, plane
);
3206 static void intel_update_primary_planes(struct drm_device
*dev
)
3208 struct drm_crtc
*crtc
;
3210 for_each_crtc(dev
, crtc
) {
3211 struct intel_plane
*plane
= to_intel_plane(crtc
->primary
);
3212 struct intel_plane_state
*plane_state
;
3214 drm_modeset_lock_crtc(crtc
, &plane
->base
);
3216 plane_state
= to_intel_plane_state(plane
->base
.state
);
3218 if (plane_state
->base
.fb
)
3219 plane
->commit_plane(&plane
->base
, plane_state
);
3221 drm_modeset_unlock_crtc(crtc
);
3225 void intel_prepare_reset(struct drm_device
*dev
)
3227 /* no reset support for gen2 */
3231 /* reset doesn't touch the display */
3232 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
3235 drm_modeset_lock_all(dev
);
3237 * Disabling the crtcs gracefully seems nicer. Also the
3238 * g33 docs say we should at least disable all the planes.
3240 intel_display_suspend(dev
);
3243 void intel_finish_reset(struct drm_device
*dev
)
3245 struct drm_i915_private
*dev_priv
= to_i915(dev
);
3248 * Flips in the rings will be nuked by the reset,
3249 * so complete all pending flips so that user space
3250 * will get its events and not get stuck.
3252 intel_complete_page_flips(dev
);
3254 /* no reset support for gen2 */
3258 /* reset doesn't touch the display */
3259 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
)) {
3261 * Flips in the rings have been nuked by the reset,
3262 * so update the base address of all primary
3263 * planes to the the last fb to make sure we're
3264 * showing the correct fb after a reset.
3266 * FIXME: Atomic will make this obsolete since we won't schedule
3267 * CS-based flips (which might get lost in gpu resets) any more.
3269 intel_update_primary_planes(dev
);
3274 * The display has been reset as well,
3275 * so need a full re-initialization.
3277 intel_runtime_pm_disable_interrupts(dev_priv
);
3278 intel_runtime_pm_enable_interrupts(dev_priv
);
3280 intel_modeset_init_hw(dev
);
3282 spin_lock_irq(&dev_priv
->irq_lock
);
3283 if (dev_priv
->display
.hpd_irq_setup
)
3284 dev_priv
->display
.hpd_irq_setup(dev
);
3285 spin_unlock_irq(&dev_priv
->irq_lock
);
3287 intel_display_resume(dev
);
3289 intel_hpd_init(dev_priv
);
3291 drm_modeset_unlock_all(dev
);
3295 intel_finish_fb(struct drm_framebuffer
*old_fb
)
3297 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_fb
);
3298 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3299 bool was_interruptible
= dev_priv
->mm
.interruptible
;
3302 /* Big Hammer, we also need to ensure that any pending
3303 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3304 * current scanout is retired before unpinning the old
3305 * framebuffer. Note that we rely on userspace rendering
3306 * into the buffer attached to the pipe they are waiting
3307 * on. If not, userspace generates a GPU hang with IPEHR
3308 * point to the MI_WAIT_FOR_EVENT.
3310 * This should only fail upon a hung GPU, in which case we
3311 * can safely continue.
3313 dev_priv
->mm
.interruptible
= false;
3314 ret
= i915_gem_object_wait_rendering(obj
, true);
3315 dev_priv
->mm
.interruptible
= was_interruptible
;
3320 static bool intel_crtc_has_pending_flip(struct drm_crtc
*crtc
)
3322 struct drm_device
*dev
= crtc
->dev
;
3323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3324 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3327 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
3328 intel_crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
3331 spin_lock_irq(&dev
->event_lock
);
3332 pending
= to_intel_crtc(crtc
)->unpin_work
!= NULL
;
3333 spin_unlock_irq(&dev
->event_lock
);
3338 static void intel_update_pipe_config(struct intel_crtc
*crtc
,
3339 struct intel_crtc_state
*old_crtc_state
)
3341 struct drm_device
*dev
= crtc
->base
.dev
;
3342 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3343 struct intel_crtc_state
*pipe_config
=
3344 to_intel_crtc_state(crtc
->base
.state
);
3346 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3347 crtc
->base
.mode
= crtc
->base
.state
->mode
;
3349 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3350 old_crtc_state
->pipe_src_w
, old_crtc_state
->pipe_src_h
,
3351 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
3354 intel_set_pipe_csc(&crtc
->base
);
3357 * Update pipe size and adjust fitter if needed: the reason for this is
3358 * that in compute_mode_changes we check the native mode (not the pfit
3359 * mode) to see if we can flip rather than do a full mode set. In the
3360 * fastboot case, we'll flip, but if we don't update the pipesrc and
3361 * pfit state, we'll end up with a big fb scanned out into the wrong
3365 I915_WRITE(PIPESRC(crtc
->pipe
),
3366 ((pipe_config
->pipe_src_w
- 1) << 16) |
3367 (pipe_config
->pipe_src_h
- 1));
3369 /* on skylake this is done by detaching scalers */
3370 if (INTEL_INFO(dev
)->gen
>= 9) {
3371 skl_detach_scalers(crtc
);
3373 if (pipe_config
->pch_pfit
.enabled
)
3374 skylake_pfit_enable(crtc
);
3375 } else if (HAS_PCH_SPLIT(dev
)) {
3376 if (pipe_config
->pch_pfit
.enabled
)
3377 ironlake_pfit_enable(crtc
);
3378 else if (old_crtc_state
->pch_pfit
.enabled
)
3379 ironlake_pfit_disable(crtc
, true);
3383 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
3385 struct drm_device
*dev
= crtc
->dev
;
3386 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3387 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3388 int pipe
= intel_crtc
->pipe
;
3391 /* enable normal train */
3392 reg
= FDI_TX_CTL(pipe
);
3393 temp
= I915_READ(reg
);
3394 if (IS_IVYBRIDGE(dev
)) {
3395 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3396 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3398 temp
&= ~FDI_LINK_TRAIN_NONE
;
3399 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
3401 I915_WRITE(reg
, temp
);
3403 reg
= FDI_RX_CTL(pipe
);
3404 temp
= I915_READ(reg
);
3405 if (HAS_PCH_CPT(dev
)) {
3406 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3407 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
3409 temp
&= ~FDI_LINK_TRAIN_NONE
;
3410 temp
|= FDI_LINK_TRAIN_NONE
;
3412 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
3414 /* wait one idle pattern time */
3418 /* IVB wants error correction enabled */
3419 if (IS_IVYBRIDGE(dev
))
3420 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
3421 FDI_FE_ERRC_ENABLE
);
3424 /* The FDI link training functions for ILK/Ibexpeak. */
3425 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
3427 struct drm_device
*dev
= crtc
->dev
;
3428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3429 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3430 int pipe
= intel_crtc
->pipe
;
3431 u32 reg
, temp
, tries
;
3433 /* FDI needs bits from pipe first */
3434 assert_pipe_enabled(dev_priv
, pipe
);
3436 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3438 reg
= FDI_RX_IMR(pipe
);
3439 temp
= I915_READ(reg
);
3440 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3441 temp
&= ~FDI_RX_BIT_LOCK
;
3442 I915_WRITE(reg
, temp
);
3446 /* enable CPU FDI TX and PCH FDI RX */
3447 reg
= FDI_TX_CTL(pipe
);
3448 temp
= I915_READ(reg
);
3449 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3450 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3451 temp
&= ~FDI_LINK_TRAIN_NONE
;
3452 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3453 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3455 reg
= FDI_RX_CTL(pipe
);
3456 temp
= I915_READ(reg
);
3457 temp
&= ~FDI_LINK_TRAIN_NONE
;
3458 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3459 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3464 /* Ironlake workaround, enable clock pointer after FDI enable*/
3465 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3466 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
3467 FDI_RX_PHASE_SYNC_POINTER_EN
);
3469 reg
= FDI_RX_IIR(pipe
);
3470 for (tries
= 0; tries
< 5; tries
++) {
3471 temp
= I915_READ(reg
);
3472 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3474 if ((temp
& FDI_RX_BIT_LOCK
)) {
3475 DRM_DEBUG_KMS("FDI train 1 done.\n");
3476 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3481 DRM_ERROR("FDI train 1 fail!\n");
3484 reg
= FDI_TX_CTL(pipe
);
3485 temp
= I915_READ(reg
);
3486 temp
&= ~FDI_LINK_TRAIN_NONE
;
3487 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3488 I915_WRITE(reg
, temp
);
3490 reg
= FDI_RX_CTL(pipe
);
3491 temp
= I915_READ(reg
);
3492 temp
&= ~FDI_LINK_TRAIN_NONE
;
3493 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3494 I915_WRITE(reg
, temp
);
3499 reg
= FDI_RX_IIR(pipe
);
3500 for (tries
= 0; tries
< 5; tries
++) {
3501 temp
= I915_READ(reg
);
3502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3504 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3505 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3506 DRM_DEBUG_KMS("FDI train 2 done.\n");
3511 DRM_ERROR("FDI train 2 fail!\n");
3513 DRM_DEBUG_KMS("FDI train done\n");
3517 static const int snb_b_fdi_train_param
[] = {
3518 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
3519 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
3520 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
3521 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
3524 /* The FDI link training functions for SNB/Cougarpoint. */
3525 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
3527 struct drm_device
*dev
= crtc
->dev
;
3528 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3529 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3530 int pipe
= intel_crtc
->pipe
;
3531 u32 reg
, temp
, i
, retry
;
3533 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3535 reg
= FDI_RX_IMR(pipe
);
3536 temp
= I915_READ(reg
);
3537 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3538 temp
&= ~FDI_RX_BIT_LOCK
;
3539 I915_WRITE(reg
, temp
);
3544 /* enable CPU FDI TX and PCH FDI RX */
3545 reg
= FDI_TX_CTL(pipe
);
3546 temp
= I915_READ(reg
);
3547 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3548 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3549 temp
&= ~FDI_LINK_TRAIN_NONE
;
3550 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3551 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3553 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3554 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3556 I915_WRITE(FDI_RX_MISC(pipe
),
3557 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3559 reg
= FDI_RX_CTL(pipe
);
3560 temp
= I915_READ(reg
);
3561 if (HAS_PCH_CPT(dev
)) {
3562 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3563 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3565 temp
&= ~FDI_LINK_TRAIN_NONE
;
3566 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3568 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3573 for (i
= 0; i
< 4; i
++) {
3574 reg
= FDI_TX_CTL(pipe
);
3575 temp
= I915_READ(reg
);
3576 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3577 temp
|= snb_b_fdi_train_param
[i
];
3578 I915_WRITE(reg
, temp
);
3583 for (retry
= 0; retry
< 5; retry
++) {
3584 reg
= FDI_RX_IIR(pipe
);
3585 temp
= I915_READ(reg
);
3586 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3587 if (temp
& FDI_RX_BIT_LOCK
) {
3588 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3589 DRM_DEBUG_KMS("FDI train 1 done.\n");
3598 DRM_ERROR("FDI train 1 fail!\n");
3601 reg
= FDI_TX_CTL(pipe
);
3602 temp
= I915_READ(reg
);
3603 temp
&= ~FDI_LINK_TRAIN_NONE
;
3604 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3606 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3608 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
3610 I915_WRITE(reg
, temp
);
3612 reg
= FDI_RX_CTL(pipe
);
3613 temp
= I915_READ(reg
);
3614 if (HAS_PCH_CPT(dev
)) {
3615 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3616 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3618 temp
&= ~FDI_LINK_TRAIN_NONE
;
3619 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
3621 I915_WRITE(reg
, temp
);
3626 for (i
= 0; i
< 4; i
++) {
3627 reg
= FDI_TX_CTL(pipe
);
3628 temp
= I915_READ(reg
);
3629 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3630 temp
|= snb_b_fdi_train_param
[i
];
3631 I915_WRITE(reg
, temp
);
3636 for (retry
= 0; retry
< 5; retry
++) {
3637 reg
= FDI_RX_IIR(pipe
);
3638 temp
= I915_READ(reg
);
3639 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3640 if (temp
& FDI_RX_SYMBOL_LOCK
) {
3641 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3642 DRM_DEBUG_KMS("FDI train 2 done.\n");
3651 DRM_ERROR("FDI train 2 fail!\n");
3653 DRM_DEBUG_KMS("FDI train done.\n");
3656 /* Manual link training for Ivy Bridge A0 parts */
3657 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
3659 struct drm_device
*dev
= crtc
->dev
;
3660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3661 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3662 int pipe
= intel_crtc
->pipe
;
3663 u32 reg
, temp
, i
, j
;
3665 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3667 reg
= FDI_RX_IMR(pipe
);
3668 temp
= I915_READ(reg
);
3669 temp
&= ~FDI_RX_SYMBOL_LOCK
;
3670 temp
&= ~FDI_RX_BIT_LOCK
;
3671 I915_WRITE(reg
, temp
);
3676 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3677 I915_READ(FDI_RX_IIR(pipe
)));
3679 /* Try each vswing and preemphasis setting twice before moving on */
3680 for (j
= 0; j
< ARRAY_SIZE(snb_b_fdi_train_param
) * 2; j
++) {
3681 /* disable first in case we need to retry */
3682 reg
= FDI_TX_CTL(pipe
);
3683 temp
= I915_READ(reg
);
3684 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
3685 temp
&= ~FDI_TX_ENABLE
;
3686 I915_WRITE(reg
, temp
);
3688 reg
= FDI_RX_CTL(pipe
);
3689 temp
= I915_READ(reg
);
3690 temp
&= ~FDI_LINK_TRAIN_AUTO
;
3691 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3692 temp
&= ~FDI_RX_ENABLE
;
3693 I915_WRITE(reg
, temp
);
3695 /* enable CPU FDI TX and PCH FDI RX */
3696 reg
= FDI_TX_CTL(pipe
);
3697 temp
= I915_READ(reg
);
3698 temp
&= ~FDI_DP_PORT_WIDTH_MASK
;
3699 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3700 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
3701 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
3702 temp
|= snb_b_fdi_train_param
[j
/2];
3703 temp
|= FDI_COMPOSITE_SYNC
;
3704 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
3706 I915_WRITE(FDI_RX_MISC(pipe
),
3707 FDI_RX_TP1_TO_TP2_48
| FDI_RX_FDI_DELAY_90
);
3709 reg
= FDI_RX_CTL(pipe
);
3710 temp
= I915_READ(reg
);
3711 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3712 temp
|= FDI_COMPOSITE_SYNC
;
3713 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
3716 udelay(1); /* should be 0.5us */
3718 for (i
= 0; i
< 4; i
++) {
3719 reg
= FDI_RX_IIR(pipe
);
3720 temp
= I915_READ(reg
);
3721 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3723 if (temp
& FDI_RX_BIT_LOCK
||
3724 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
3725 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
3726 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3730 udelay(1); /* should be 0.5us */
3733 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j
/ 2);
3738 reg
= FDI_TX_CTL(pipe
);
3739 temp
= I915_READ(reg
);
3740 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
3741 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
3742 I915_WRITE(reg
, temp
);
3744 reg
= FDI_RX_CTL(pipe
);
3745 temp
= I915_READ(reg
);
3746 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3747 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
3748 I915_WRITE(reg
, temp
);
3751 udelay(2); /* should be 1.5us */
3753 for (i
= 0; i
< 4; i
++) {
3754 reg
= FDI_RX_IIR(pipe
);
3755 temp
= I915_READ(reg
);
3756 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
3758 if (temp
& FDI_RX_SYMBOL_LOCK
||
3759 (I915_READ(reg
) & FDI_RX_SYMBOL_LOCK
)) {
3760 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
3761 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3765 udelay(2); /* should be 1.5us */
3768 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j
/ 2);
3772 DRM_DEBUG_KMS("FDI train done.\n");
3775 static void ironlake_fdi_pll_enable(struct intel_crtc
*intel_crtc
)
3777 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3778 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3779 int pipe
= intel_crtc
->pipe
;
3783 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3784 reg
= FDI_RX_CTL(pipe
);
3785 temp
= I915_READ(reg
);
3786 temp
&= ~(FDI_DP_PORT_WIDTH_MASK
| (0x7 << 16));
3787 temp
|= FDI_DP_PORT_WIDTH(intel_crtc
->config
->fdi_lanes
);
3788 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3789 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
3794 /* Switch from Rawclk to PCDclk */
3795 temp
= I915_READ(reg
);
3796 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
3801 /* Enable CPU FDI TX PLL, always on for Ironlake */
3802 reg
= FDI_TX_CTL(pipe
);
3803 temp
= I915_READ(reg
);
3804 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
3805 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
3812 static void ironlake_fdi_pll_disable(struct intel_crtc
*intel_crtc
)
3814 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3815 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3816 int pipe
= intel_crtc
->pipe
;
3819 /* Switch from PCDclk to Rawclk */
3820 reg
= FDI_RX_CTL(pipe
);
3821 temp
= I915_READ(reg
);
3822 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3824 /* Disable CPU FDI TX PLL */
3825 reg
= FDI_TX_CTL(pipe
);
3826 temp
= I915_READ(reg
);
3827 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3832 reg
= FDI_RX_CTL(pipe
);
3833 temp
= I915_READ(reg
);
3834 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3836 /* Wait for the clocks to turn off. */
3841 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
3843 struct drm_device
*dev
= crtc
->dev
;
3844 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3845 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3846 int pipe
= intel_crtc
->pipe
;
3849 /* disable CPU FDI tx and PCH FDI rx */
3850 reg
= FDI_TX_CTL(pipe
);
3851 temp
= I915_READ(reg
);
3852 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
3855 reg
= FDI_RX_CTL(pipe
);
3856 temp
= I915_READ(reg
);
3857 temp
&= ~(0x7 << 16);
3858 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3859 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
3864 /* Ironlake workaround, disable clock pointer after downing FDI */
3865 if (HAS_PCH_IBX(dev
))
3866 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
3868 /* still set train pattern 1 */
3869 reg
= FDI_TX_CTL(pipe
);
3870 temp
= I915_READ(reg
);
3871 temp
&= ~FDI_LINK_TRAIN_NONE
;
3872 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3873 I915_WRITE(reg
, temp
);
3875 reg
= FDI_RX_CTL(pipe
);
3876 temp
= I915_READ(reg
);
3877 if (HAS_PCH_CPT(dev
)) {
3878 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
3879 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
3881 temp
&= ~FDI_LINK_TRAIN_NONE
;
3882 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
3884 /* BPC in FDI rx is consistent with that in PIPECONF */
3885 temp
&= ~(0x07 << 16);
3886 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) << 11;
3887 I915_WRITE(reg
, temp
);
3893 bool intel_has_pending_fb_unpin(struct drm_device
*dev
)
3895 struct intel_crtc
*crtc
;
3897 /* Note that we don't need to be called with mode_config.lock here
3898 * as our list of CRTC objects is static for the lifetime of the
3899 * device and so cannot disappear as we iterate. Similarly, we can
3900 * happily treat the predicates as racy, atomic checks as userspace
3901 * cannot claim and pin a new fb without at least acquring the
3902 * struct_mutex and so serialising with us.
3904 for_each_intel_crtc(dev
, crtc
) {
3905 if (atomic_read(&crtc
->unpin_work_count
) == 0)
3908 if (crtc
->unpin_work
)
3909 intel_wait_for_vblank(dev
, crtc
->pipe
);
3917 static void page_flip_completed(struct intel_crtc
*intel_crtc
)
3919 struct drm_i915_private
*dev_priv
= to_i915(intel_crtc
->base
.dev
);
3920 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
3922 /* ensure that the unpin work is consistent wrt ->pending. */
3924 intel_crtc
->unpin_work
= NULL
;
3927 drm_send_vblank_event(intel_crtc
->base
.dev
,
3931 drm_crtc_vblank_put(&intel_crtc
->base
);
3933 wake_up_all(&dev_priv
->pending_flip_queue
);
3934 queue_work(dev_priv
->wq
, &work
->work
);
3936 trace_i915_flip_complete(intel_crtc
->plane
,
3937 work
->pending_flip_obj
);
3940 void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
3942 struct drm_device
*dev
= crtc
->dev
;
3943 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3945 WARN_ON(waitqueue_active(&dev_priv
->pending_flip_queue
));
3946 if (WARN_ON(wait_event_timeout(dev_priv
->pending_flip_queue
,
3947 !intel_crtc_has_pending_flip(crtc
),
3949 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3951 spin_lock_irq(&dev
->event_lock
);
3952 if (intel_crtc
->unpin_work
) {
3953 WARN_ONCE(1, "Removing stuck page flip\n");
3954 page_flip_completed(intel_crtc
);
3956 spin_unlock_irq(&dev
->event_lock
);
3959 if (crtc
->primary
->fb
) {
3960 mutex_lock(&dev
->struct_mutex
);
3961 intel_finish_fb(crtc
->primary
->fb
);
3962 mutex_unlock(&dev
->struct_mutex
);
3966 /* Program iCLKIP clock to the desired frequency */
3967 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
3969 struct drm_device
*dev
= crtc
->dev
;
3970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3971 int clock
= to_intel_crtc(crtc
)->config
->base
.adjusted_mode
.crtc_clock
;
3972 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
3975 mutex_lock(&dev_priv
->sb_lock
);
3977 /* It is necessary to ungate the pixclk gate prior to programming
3978 * the divisors, and gate it back when it is done.
3980 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
3982 /* Disable SSCCTL */
3983 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
3984 intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
) |
3988 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3989 if (clock
== 20000) {
3994 /* The iCLK virtual clock root frequency is in MHz,
3995 * but the adjusted_mode->crtc_clock in in KHz. To get the
3996 * divisors, it is necessary to divide one by another, so we
3997 * convert the virtual clock precision to KHz here for higher
4000 u32 iclk_virtual_root_freq
= 172800 * 1000;
4001 u32 iclk_pi_range
= 64;
4002 u32 desired_divisor
, msb_divisor_value
, pi_value
;
4004 desired_divisor
= (iclk_virtual_root_freq
/ clock
);
4005 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
4006 pi_value
= desired_divisor
% iclk_pi_range
;
4009 divsel
= msb_divisor_value
- 2;
4010 phaseinc
= pi_value
;
4013 /* This should not happen with any sane values */
4014 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
4015 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
4016 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
4017 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
4019 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4026 /* Program SSCDIVINTPHASE6 */
4027 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
, SBI_ICLK
);
4028 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
4029 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
4030 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
4031 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
4032 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
4033 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
4034 intel_sbi_write(dev_priv
, SBI_SSCDIVINTPHASE6
, temp
, SBI_ICLK
);
4036 /* Program SSCAUXDIV */
4037 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
, SBI_ICLK
);
4038 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4039 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
4040 intel_sbi_write(dev_priv
, SBI_SSCAUXDIV6
, temp
, SBI_ICLK
);
4042 /* Enable modulator and associated divider */
4043 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
, SBI_ICLK
);
4044 temp
&= ~SBI_SSCCTL_DISABLE
;
4045 intel_sbi_write(dev_priv
, SBI_SSCCTL6
, temp
, SBI_ICLK
);
4047 /* Wait for initialization time */
4050 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
4052 mutex_unlock(&dev_priv
->sb_lock
);
4055 static void ironlake_pch_transcoder_set_timings(struct intel_crtc
*crtc
,
4056 enum pipe pch_transcoder
)
4058 struct drm_device
*dev
= crtc
->base
.dev
;
4059 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4060 enum transcoder cpu_transcoder
= crtc
->config
->cpu_transcoder
;
4062 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder
),
4063 I915_READ(HTOTAL(cpu_transcoder
)));
4064 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder
),
4065 I915_READ(HBLANK(cpu_transcoder
)));
4066 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder
),
4067 I915_READ(HSYNC(cpu_transcoder
)));
4069 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder
),
4070 I915_READ(VTOTAL(cpu_transcoder
)));
4071 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder
),
4072 I915_READ(VBLANK(cpu_transcoder
)));
4073 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder
),
4074 I915_READ(VSYNC(cpu_transcoder
)));
4075 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder
),
4076 I915_READ(VSYNCSHIFT(cpu_transcoder
)));
4079 static void cpt_set_fdi_bc_bifurcation(struct drm_device
*dev
, bool enable
)
4081 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4084 temp
= I915_READ(SOUTH_CHICKEN1
);
4085 if (!!(temp
& FDI_BC_BIFURCATION_SELECT
) == enable
)
4088 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B
)) & FDI_RX_ENABLE
);
4089 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C
)) & FDI_RX_ENABLE
);
4091 temp
&= ~FDI_BC_BIFURCATION_SELECT
;
4093 temp
|= FDI_BC_BIFURCATION_SELECT
;
4095 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable
? "en" : "dis");
4096 I915_WRITE(SOUTH_CHICKEN1
, temp
);
4097 POSTING_READ(SOUTH_CHICKEN1
);
4100 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc
*intel_crtc
)
4102 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4104 switch (intel_crtc
->pipe
) {
4108 if (intel_crtc
->config
->fdi_lanes
> 2)
4109 cpt_set_fdi_bc_bifurcation(dev
, false);
4111 cpt_set_fdi_bc_bifurcation(dev
, true);
4115 cpt_set_fdi_bc_bifurcation(dev
, true);
4124 * Enable PCH resources required for PCH ports:
4126 * - FDI training & RX/TX
4127 * - update transcoder timings
4128 * - DP transcoding bits
4131 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
4133 struct drm_device
*dev
= crtc
->dev
;
4134 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4135 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4136 int pipe
= intel_crtc
->pipe
;
4139 assert_pch_transcoder_disabled(dev_priv
, pipe
);
4141 if (IS_IVYBRIDGE(dev
))
4142 ivybridge_update_fdi_bc_bifurcation(intel_crtc
);
4144 /* Write the TU size bits before fdi link training, so that error
4145 * detection works. */
4146 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
4147 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
4149 /* For PCH output, training FDI link */
4150 dev_priv
->display
.fdi_link_train(crtc
);
4152 /* We need to program the right clock selection before writing the pixel
4153 * mutliplier into the DPLL. */
4154 if (HAS_PCH_CPT(dev
)) {
4157 temp
= I915_READ(PCH_DPLL_SEL
);
4158 temp
|= TRANS_DPLL_ENABLE(pipe
);
4159 sel
= TRANS_DPLLB_SEL(pipe
);
4160 if (intel_crtc
->config
->shared_dpll
== DPLL_ID_PCH_PLL_B
)
4164 I915_WRITE(PCH_DPLL_SEL
, temp
);
4167 /* XXX: pch pll's can be enabled any time before we enable the PCH
4168 * transcoder, and we actually should do this to not upset any PCH
4169 * transcoder that already use the clock when we share it.
4171 * Note that enable_shared_dpll tries to do the right thing, but
4172 * get_shared_dpll unconditionally resets the pll - we need that to have
4173 * the right LVDS enable sequence. */
4174 intel_enable_shared_dpll(intel_crtc
);
4176 /* set transcoder timing, panel must allow it */
4177 assert_panel_unlocked(dev_priv
, pipe
);
4178 ironlake_pch_transcoder_set_timings(intel_crtc
, pipe
);
4180 intel_fdi_normal_train(crtc
);
4182 /* For PCH DP, enable TRANS_DP_CTL */
4183 if (HAS_PCH_CPT(dev
) && intel_crtc
->config
->has_dp_encoder
) {
4184 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPECONF_BPC_MASK
) >> 5;
4185 reg
= TRANS_DP_CTL(pipe
);
4186 temp
= I915_READ(reg
);
4187 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
4188 TRANS_DP_SYNC_MASK
|
4190 temp
|= TRANS_DP_OUTPUT_ENABLE
;
4191 temp
|= bpc
<< 9; /* same format but at 11:9 */
4193 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
4194 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
4195 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
4196 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
4198 switch (intel_trans_dp_port_sel(crtc
)) {
4200 temp
|= TRANS_DP_PORT_SEL_B
;
4203 temp
|= TRANS_DP_PORT_SEL_C
;
4206 temp
|= TRANS_DP_PORT_SEL_D
;
4212 I915_WRITE(reg
, temp
);
4215 ironlake_enable_pch_transcoder(dev_priv
, pipe
);
4218 static void lpt_pch_enable(struct drm_crtc
*crtc
)
4220 struct drm_device
*dev
= crtc
->dev
;
4221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4222 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4223 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
4225 assert_pch_transcoder_disabled(dev_priv
, TRANSCODER_A
);
4227 lpt_program_iclkip(crtc
);
4229 /* Set transcoder timing. */
4230 ironlake_pch_transcoder_set_timings(intel_crtc
, PIPE_A
);
4232 lpt_enable_pch_transcoder(dev_priv
, cpu_transcoder
);
4235 struct intel_shared_dpll
*intel_get_shared_dpll(struct intel_crtc
*crtc
,
4236 struct intel_crtc_state
*crtc_state
)
4238 struct drm_i915_private
*dev_priv
= crtc
->base
.dev
->dev_private
;
4239 struct intel_shared_dpll
*pll
;
4240 struct intel_shared_dpll_config
*shared_dpll
;
4241 enum intel_dpll_id i
;
4242 int max
= dev_priv
->num_shared_dpll
;
4244 shared_dpll
= intel_atomic_get_shared_dpll_state(crtc_state
->base
.state
);
4246 if (HAS_PCH_IBX(dev_priv
->dev
)) {
4247 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4248 i
= (enum intel_dpll_id
) crtc
->pipe
;
4249 pll
= &dev_priv
->shared_dplls
[i
];
4251 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4252 crtc
->base
.base
.id
, pll
->name
);
4254 WARN_ON(shared_dpll
[i
].crtc_mask
);
4259 if (IS_BROXTON(dev_priv
->dev
)) {
4260 /* PLL is attached to port in bxt */
4261 struct intel_encoder
*encoder
;
4262 struct intel_digital_port
*intel_dig_port
;
4264 encoder
= intel_ddi_get_crtc_new_encoder(crtc_state
);
4265 if (WARN_ON(!encoder
))
4268 intel_dig_port
= enc_to_dig_port(&encoder
->base
);
4269 /* 1:1 mapping between ports and PLLs */
4270 i
= (enum intel_dpll_id
)intel_dig_port
->port
;
4271 pll
= &dev_priv
->shared_dplls
[i
];
4272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4273 crtc
->base
.base
.id
, pll
->name
);
4274 WARN_ON(shared_dpll
[i
].crtc_mask
);
4277 } else if (INTEL_INFO(dev_priv
)->gen
< 9 && HAS_DDI(dev_priv
))
4278 /* Do not consider SPLL */
4281 for (i
= 0; i
< max
; i
++) {
4282 pll
= &dev_priv
->shared_dplls
[i
];
4284 /* Only want to check enabled timings first */
4285 if (shared_dpll
[i
].crtc_mask
== 0)
4288 if (memcmp(&crtc_state
->dpll_hw_state
,
4289 &shared_dpll
[i
].hw_state
,
4290 sizeof(crtc_state
->dpll_hw_state
)) == 0) {
4291 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4292 crtc
->base
.base
.id
, pll
->name
,
4293 shared_dpll
[i
].crtc_mask
,
4299 /* Ok no matching timings, maybe there's a free one? */
4300 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4301 pll
= &dev_priv
->shared_dplls
[i
];
4302 if (shared_dpll
[i
].crtc_mask
== 0) {
4303 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4304 crtc
->base
.base
.id
, pll
->name
);
4312 if (shared_dpll
[i
].crtc_mask
== 0)
4313 shared_dpll
[i
].hw_state
=
4314 crtc_state
->dpll_hw_state
;
4316 crtc_state
->shared_dpll
= i
;
4317 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll
->name
,
4318 pipe_name(crtc
->pipe
));
4320 shared_dpll
[i
].crtc_mask
|= 1 << crtc
->pipe
;
4325 static void intel_shared_dpll_commit(struct drm_atomic_state
*state
)
4327 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
4328 struct intel_shared_dpll_config
*shared_dpll
;
4329 struct intel_shared_dpll
*pll
;
4330 enum intel_dpll_id i
;
4332 if (!to_intel_atomic_state(state
)->dpll_set
)
4335 shared_dpll
= to_intel_atomic_state(state
)->shared_dpll
;
4336 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
4337 pll
= &dev_priv
->shared_dplls
[i
];
4338 pll
->config
= shared_dpll
[i
];
4342 static void cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
4344 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4345 int dslreg
= PIPEDSL(pipe
);
4348 temp
= I915_READ(dslreg
);
4350 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
4351 if (wait_for(I915_READ(dslreg
) != temp
, 5))
4352 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe
));
4357 skl_update_scaler(struct intel_crtc_state
*crtc_state
, bool force_detach
,
4358 unsigned scaler_user
, int *scaler_id
, unsigned int rotation
,
4359 int src_w
, int src_h
, int dst_w
, int dst_h
)
4361 struct intel_crtc_scaler_state
*scaler_state
=
4362 &crtc_state
->scaler_state
;
4363 struct intel_crtc
*intel_crtc
=
4364 to_intel_crtc(crtc_state
->base
.crtc
);
4367 need_scaling
= intel_rotation_90_or_270(rotation
) ?
4368 (src_h
!= dst_w
|| src_w
!= dst_h
):
4369 (src_w
!= dst_w
|| src_h
!= dst_h
);
4372 * if plane is being disabled or scaler is no more required or force detach
4373 * - free scaler binded to this plane/crtc
4374 * - in order to do this, update crtc->scaler_usage
4376 * Here scaler state in crtc_state is set free so that
4377 * scaler can be assigned to other user. Actual register
4378 * update to free the scaler is done in plane/panel-fit programming.
4379 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4381 if (force_detach
|| !need_scaling
) {
4382 if (*scaler_id
>= 0) {
4383 scaler_state
->scaler_users
&= ~(1 << scaler_user
);
4384 scaler_state
->scalers
[*scaler_id
].in_use
= 0;
4386 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4387 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4388 intel_crtc
->pipe
, scaler_user
, *scaler_id
,
4389 scaler_state
->scaler_users
);
4396 if (src_w
< SKL_MIN_SRC_W
|| src_h
< SKL_MIN_SRC_H
||
4397 dst_w
< SKL_MIN_DST_W
|| dst_h
< SKL_MIN_DST_H
||
4399 src_w
> SKL_MAX_SRC_W
|| src_h
> SKL_MAX_SRC_H
||
4400 dst_w
> SKL_MAX_DST_W
|| dst_h
> SKL_MAX_DST_H
) {
4401 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4402 "size is out of scaler range\n",
4403 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
);
4407 /* mark this plane as a scaler user in crtc_state */
4408 scaler_state
->scaler_users
|= (1 << scaler_user
);
4409 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4410 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4411 intel_crtc
->pipe
, scaler_user
, src_w
, src_h
, dst_w
, dst_h
,
4412 scaler_state
->scaler_users
);
4418 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4420 * @state: crtc's scaler state
4423 * 0 - scaler_usage updated successfully
4424 * error - requested scaling cannot be supported or other error condition
4426 int skl_update_scaler_crtc(struct intel_crtc_state
*state
)
4428 struct intel_crtc
*intel_crtc
= to_intel_crtc(state
->base
.crtc
);
4429 const struct drm_display_mode
*adjusted_mode
= &state
->base
.adjusted_mode
;
4431 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4432 intel_crtc
->base
.base
.id
, intel_crtc
->pipe
, SKL_CRTC_INDEX
);
4434 return skl_update_scaler(state
, !state
->base
.active
, SKL_CRTC_INDEX
,
4435 &state
->scaler_state
.scaler_id
, DRM_ROTATE_0
,
4436 state
->pipe_src_w
, state
->pipe_src_h
,
4437 adjusted_mode
->crtc_hdisplay
, adjusted_mode
->crtc_vdisplay
);
4441 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4443 * @state: crtc's scaler state
4444 * @plane_state: atomic plane state to update
4447 * 0 - scaler_usage updated successfully
4448 * error - requested scaling cannot be supported or other error condition
4450 static int skl_update_scaler_plane(struct intel_crtc_state
*crtc_state
,
4451 struct intel_plane_state
*plane_state
)
4454 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc_state
->base
.crtc
);
4455 struct intel_plane
*intel_plane
=
4456 to_intel_plane(plane_state
->base
.plane
);
4457 struct drm_framebuffer
*fb
= plane_state
->base
.fb
;
4460 bool force_detach
= !fb
|| !plane_state
->visible
;
4462 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4463 intel_plane
->base
.base
.id
, intel_crtc
->pipe
,
4464 drm_plane_index(&intel_plane
->base
));
4466 ret
= skl_update_scaler(crtc_state
, force_detach
,
4467 drm_plane_index(&intel_plane
->base
),
4468 &plane_state
->scaler_id
,
4469 plane_state
->base
.rotation
,
4470 drm_rect_width(&plane_state
->src
) >> 16,
4471 drm_rect_height(&plane_state
->src
) >> 16,
4472 drm_rect_width(&plane_state
->dst
),
4473 drm_rect_height(&plane_state
->dst
));
4475 if (ret
|| plane_state
->scaler_id
< 0)
4478 /* check colorkey */
4479 if (plane_state
->ckey
.flags
!= I915_SET_COLORKEY_NONE
) {
4480 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4481 intel_plane
->base
.base
.id
);
4485 /* Check src format */
4486 switch (fb
->pixel_format
) {
4487 case DRM_FORMAT_RGB565
:
4488 case DRM_FORMAT_XBGR8888
:
4489 case DRM_FORMAT_XRGB8888
:
4490 case DRM_FORMAT_ABGR8888
:
4491 case DRM_FORMAT_ARGB8888
:
4492 case DRM_FORMAT_XRGB2101010
:
4493 case DRM_FORMAT_XBGR2101010
:
4494 case DRM_FORMAT_YUYV
:
4495 case DRM_FORMAT_YVYU
:
4496 case DRM_FORMAT_UYVY
:
4497 case DRM_FORMAT_VYUY
:
4500 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4501 intel_plane
->base
.base
.id
, fb
->base
.id
, fb
->pixel_format
);
4508 static void skylake_scaler_disable(struct intel_crtc
*crtc
)
4512 for (i
= 0; i
< crtc
->num_scalers
; i
++)
4513 skl_detach_scaler(crtc
, i
);
4516 static void skylake_pfit_enable(struct intel_crtc
*crtc
)
4518 struct drm_device
*dev
= crtc
->base
.dev
;
4519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4520 int pipe
= crtc
->pipe
;
4521 struct intel_crtc_scaler_state
*scaler_state
=
4522 &crtc
->config
->scaler_state
;
4524 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc
->config
);
4526 if (crtc
->config
->pch_pfit
.enabled
) {
4529 if (WARN_ON(crtc
->config
->scaler_state
.scaler_id
< 0)) {
4530 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4534 id
= scaler_state
->scaler_id
;
4535 I915_WRITE(SKL_PS_CTRL(pipe
, id
), PS_SCALER_EN
|
4536 PS_FILTER_MEDIUM
| scaler_state
->scalers
[id
].mode
);
4537 I915_WRITE(SKL_PS_WIN_POS(pipe
, id
), crtc
->config
->pch_pfit
.pos
);
4538 I915_WRITE(SKL_PS_WIN_SZ(pipe
, id
), crtc
->config
->pch_pfit
.size
);
4540 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc
->config
, id
);
4544 static void ironlake_pfit_enable(struct intel_crtc
*crtc
)
4546 struct drm_device
*dev
= crtc
->base
.dev
;
4547 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4548 int pipe
= crtc
->pipe
;
4550 if (crtc
->config
->pch_pfit
.enabled
) {
4551 /* Force use of hard-coded filter coefficients
4552 * as some pre-programmed values are broken,
4555 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
))
4556 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
|
4557 PF_PIPE_SEL_IVB(pipe
));
4559 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
4560 I915_WRITE(PF_WIN_POS(pipe
), crtc
->config
->pch_pfit
.pos
);
4561 I915_WRITE(PF_WIN_SZ(pipe
), crtc
->config
->pch_pfit
.size
);
4565 void hsw_enable_ips(struct intel_crtc
*crtc
)
4567 struct drm_device
*dev
= crtc
->base
.dev
;
4568 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4570 if (!crtc
->config
->ips_enabled
)
4573 /* We can only enable IPS after we enable a plane and wait for a vblank */
4574 intel_wait_for_vblank(dev
, crtc
->pipe
);
4576 assert_plane_enabled(dev_priv
, crtc
->plane
);
4577 if (IS_BROADWELL(dev
)) {
4578 mutex_lock(&dev_priv
->rps
.hw_lock
);
4579 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0xc0000000));
4580 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4581 /* Quoting Art Runyan: "its not safe to expect any particular
4582 * value in IPS_CTL bit 31 after enabling IPS through the
4583 * mailbox." Moreover, the mailbox may return a bogus state,
4584 * so we need to just enable it and continue on.
4587 I915_WRITE(IPS_CTL
, IPS_ENABLE
);
4588 /* The bit only becomes 1 in the next vblank, so this wait here
4589 * is essentially intel_wait_for_vblank. If we don't have this
4590 * and don't wait for vblanks until the end of crtc_enable, then
4591 * the HW state readout code will complain that the expected
4592 * IPS_CTL value is not the one we read. */
4593 if (wait_for(I915_READ_NOTRACE(IPS_CTL
) & IPS_ENABLE
, 50))
4594 DRM_ERROR("Timed out waiting for IPS enable\n");
4598 void hsw_disable_ips(struct intel_crtc
*crtc
)
4600 struct drm_device
*dev
= crtc
->base
.dev
;
4601 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4603 if (!crtc
->config
->ips_enabled
)
4606 assert_plane_enabled(dev_priv
, crtc
->plane
);
4607 if (IS_BROADWELL(dev
)) {
4608 mutex_lock(&dev_priv
->rps
.hw_lock
);
4609 WARN_ON(sandybridge_pcode_write(dev_priv
, DISPLAY_IPS_CONTROL
, 0));
4610 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4611 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4612 if (wait_for((I915_READ(IPS_CTL
) & IPS_ENABLE
) == 0, 42))
4613 DRM_ERROR("Timed out waiting for IPS disable\n");
4615 I915_WRITE(IPS_CTL
, 0);
4616 POSTING_READ(IPS_CTL
);
4619 /* We need to wait for a vblank before we can disable the plane. */
4620 intel_wait_for_vblank(dev
, crtc
->pipe
);
4623 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4624 static void intel_crtc_load_lut(struct drm_crtc
*crtc
)
4626 struct drm_device
*dev
= crtc
->dev
;
4627 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4628 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4629 enum pipe pipe
= intel_crtc
->pipe
;
4631 bool reenable_ips
= false;
4633 /* The clocks have to be on to load the palette. */
4634 if (!crtc
->state
->active
)
4637 if (HAS_GMCH_DISPLAY(dev_priv
->dev
)) {
4638 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
))
4639 assert_dsi_pll_enabled(dev_priv
);
4641 assert_pll_enabled(dev_priv
, pipe
);
4644 /* Workaround : Do not read or write the pipe palette/gamma data while
4645 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4647 if (IS_HASWELL(dev
) && intel_crtc
->config
->ips_enabled
&&
4648 ((I915_READ(GAMMA_MODE(pipe
)) & GAMMA_MODE_MODE_MASK
) ==
4649 GAMMA_MODE_MODE_SPLIT
)) {
4650 hsw_disable_ips(intel_crtc
);
4651 reenable_ips
= true;
4654 for (i
= 0; i
< 256; i
++) {
4657 if (HAS_GMCH_DISPLAY(dev
))
4658 palreg
= PALETTE(pipe
, i
);
4660 palreg
= LGC_PALETTE(pipe
, i
);
4663 (intel_crtc
->lut_r
[i
] << 16) |
4664 (intel_crtc
->lut_g
[i
] << 8) |
4665 intel_crtc
->lut_b
[i
]);
4669 hsw_enable_ips(intel_crtc
);
4672 static void intel_crtc_dpms_overlay_disable(struct intel_crtc
*intel_crtc
)
4674 if (intel_crtc
->overlay
) {
4675 struct drm_device
*dev
= intel_crtc
->base
.dev
;
4676 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4678 mutex_lock(&dev
->struct_mutex
);
4679 dev_priv
->mm
.interruptible
= false;
4680 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
4681 dev_priv
->mm
.interruptible
= true;
4682 mutex_unlock(&dev
->struct_mutex
);
4685 /* Let userspace switch the overlay on again. In most cases userspace
4686 * has to recompute where to put it anyway.
4691 * intel_post_enable_primary - Perform operations after enabling primary plane
4692 * @crtc: the CRTC whose primary plane was just enabled
4694 * Performs potentially sleeping operations that must be done after the primary
4695 * plane is enabled, such as updating FBC and IPS. Note that this may be
4696 * called due to an explicit primary plane update, or due to an implicit
4697 * re-enable that is caused when a sprite plane is updated to no longer
4698 * completely hide the primary plane.
4701 intel_post_enable_primary(struct drm_crtc
*crtc
)
4703 struct drm_device
*dev
= crtc
->dev
;
4704 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4705 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4706 int pipe
= intel_crtc
->pipe
;
4709 * BDW signals flip done immediately if the plane
4710 * is disabled, even if the plane enable is already
4711 * armed to occur at the next vblank :(
4713 if (IS_BROADWELL(dev
))
4714 intel_wait_for_vblank(dev
, pipe
);
4717 * FIXME IPS should be fine as long as one plane is
4718 * enabled, but in practice it seems to have problems
4719 * when going from primary only to sprite only and vice
4722 hsw_enable_ips(intel_crtc
);
4725 * Gen2 reports pipe underruns whenever all planes are disabled.
4726 * So don't enable underrun reporting before at least some planes
4728 * FIXME: Need to fix the logic to work when we turn off all planes
4729 * but leave the pipe running.
4732 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4734 /* Underruns don't raise interrupts, so check manually. */
4735 if (HAS_GMCH_DISPLAY(dev
))
4736 i9xx_check_fifo_underruns(dev_priv
);
4740 * intel_pre_disable_primary - Perform operations before disabling primary plane
4741 * @crtc: the CRTC whose primary plane is to be disabled
4743 * Performs potentially sleeping operations that must be done before the
4744 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4745 * be called due to an explicit primary plane update, or due to an implicit
4746 * disable that is caused when a sprite plane completely hides the primary
4750 intel_pre_disable_primary(struct drm_crtc
*crtc
)
4752 struct drm_device
*dev
= crtc
->dev
;
4753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4754 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4755 int pipe
= intel_crtc
->pipe
;
4758 * Gen2 reports pipe underruns whenever all planes are disabled.
4759 * So diasble underrun reporting before all the planes get disabled.
4760 * FIXME: Need to fix the logic to work when we turn off all planes
4761 * but leave the pipe running.
4764 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
4767 * Vblank time updates from the shadow to live plane control register
4768 * are blocked if the memory self-refresh mode is active at that
4769 * moment. So to make sure the plane gets truly disabled, disable
4770 * first the self-refresh mode. The self-refresh enable bit in turn
4771 * will be checked/applied by the HW only at the next frame start
4772 * event which is after the vblank start event, so we need to have a
4773 * wait-for-vblank between disabling the plane and the pipe.
4775 if (HAS_GMCH_DISPLAY(dev
)) {
4776 intel_set_memory_cxsr(dev_priv
, false);
4777 dev_priv
->wm
.vlv
.cxsr
= false;
4778 intel_wait_for_vblank(dev
, pipe
);
4782 * FIXME IPS should be fine as long as one plane is
4783 * enabled, but in practice it seems to have problems
4784 * when going from primary only to sprite only and vice
4787 hsw_disable_ips(intel_crtc
);
4790 static void intel_post_plane_update(struct intel_crtc
*crtc
)
4792 struct intel_crtc_atomic_commit
*atomic
= &crtc
->atomic
;
4793 struct drm_device
*dev
= crtc
->base
.dev
;
4794 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4795 struct drm_plane
*plane
;
4797 if (atomic
->wait_vblank
)
4798 intel_wait_for_vblank(dev
, crtc
->pipe
);
4800 intel_frontbuffer_flip(dev
, atomic
->fb_bits
);
4802 if (atomic
->disable_cxsr
)
4803 crtc
->wm
.cxsr_allowed
= true;
4805 if (crtc
->atomic
.update_wm_post
)
4806 intel_update_watermarks(&crtc
->base
);
4808 if (atomic
->update_fbc
)
4809 intel_fbc_update(dev_priv
);
4811 if (atomic
->post_enable_primary
)
4812 intel_post_enable_primary(&crtc
->base
);
4814 drm_for_each_plane_mask(plane
, dev
, atomic
->update_sprite_watermarks
)
4815 intel_update_sprite_watermarks(plane
, &crtc
->base
,
4816 0, 0, 0, false, false);
4818 memset(atomic
, 0, sizeof(*atomic
));
4821 static void intel_pre_plane_update(struct intel_crtc
*crtc
)
4823 struct drm_device
*dev
= crtc
->base
.dev
;
4824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4825 struct intel_crtc_atomic_commit
*atomic
= &crtc
->atomic
;
4826 struct drm_plane
*p
;
4828 /* Track fb's for any planes being disabled */
4829 drm_for_each_plane_mask(p
, dev
, atomic
->disabled_planes
) {
4830 struct intel_plane
*plane
= to_intel_plane(p
);
4832 mutex_lock(&dev
->struct_mutex
);
4833 i915_gem_track_fb(intel_fb_obj(plane
->base
.fb
), NULL
,
4834 plane
->frontbuffer_bit
);
4835 mutex_unlock(&dev
->struct_mutex
);
4838 if (atomic
->wait_for_flips
)
4839 intel_crtc_wait_for_pending_flips(&crtc
->base
);
4841 if (atomic
->disable_fbc
)
4842 intel_fbc_disable_crtc(crtc
);
4844 if (crtc
->atomic
.disable_ips
)
4845 hsw_disable_ips(crtc
);
4847 if (atomic
->pre_disable_primary
)
4848 intel_pre_disable_primary(&crtc
->base
);
4850 if (atomic
->disable_cxsr
) {
4851 crtc
->wm
.cxsr_allowed
= false;
4852 intel_set_memory_cxsr(dev_priv
, false);
4856 static void intel_crtc_disable_planes(struct drm_crtc
*crtc
, unsigned plane_mask
)
4858 struct drm_device
*dev
= crtc
->dev
;
4859 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4860 struct drm_plane
*p
;
4861 int pipe
= intel_crtc
->pipe
;
4863 intel_crtc_dpms_overlay_disable(intel_crtc
);
4865 drm_for_each_plane_mask(p
, dev
, plane_mask
)
4866 to_intel_plane(p
)->disable_plane(p
, crtc
);
4869 * FIXME: Once we grow proper nuclear flip support out of this we need
4870 * to compute the mask of flip planes precisely. For the time being
4871 * consider this a flip to a NULL plane.
4873 intel_frontbuffer_flip(dev
, INTEL_FRONTBUFFER_ALL_MASK(pipe
));
4876 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
4878 struct drm_device
*dev
= crtc
->dev
;
4879 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4880 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4881 struct intel_encoder
*encoder
;
4882 int pipe
= intel_crtc
->pipe
;
4884 if (WARN_ON(intel_crtc
->active
))
4887 if (intel_crtc
->config
->has_pch_encoder
)
4888 intel_prepare_shared_dpll(intel_crtc
);
4890 if (intel_crtc
->config
->has_dp_encoder
)
4891 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4893 intel_set_pipe_timings(intel_crtc
);
4895 if (intel_crtc
->config
->has_pch_encoder
) {
4896 intel_cpu_transcoder_set_m_n(intel_crtc
,
4897 &intel_crtc
->config
->fdi_m_n
, NULL
);
4900 ironlake_set_pipeconf(crtc
);
4902 intel_crtc
->active
= true;
4904 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4905 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, true);
4907 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4908 if (encoder
->pre_enable
)
4909 encoder
->pre_enable(encoder
);
4911 if (intel_crtc
->config
->has_pch_encoder
) {
4912 /* Note: FDI PLL enabling _must_ be done before we enable the
4913 * cpu pipes, hence this is separate from all the other fdi/pch
4915 ironlake_fdi_pll_enable(intel_crtc
);
4917 assert_fdi_tx_disabled(dev_priv
, pipe
);
4918 assert_fdi_rx_disabled(dev_priv
, pipe
);
4921 ironlake_pfit_enable(intel_crtc
);
4924 * On ILK+ LUT must be loaded before the pipe is running but with
4927 intel_crtc_load_lut(crtc
);
4929 intel_update_watermarks(crtc
);
4930 intel_enable_pipe(intel_crtc
);
4932 if (intel_crtc
->config
->has_pch_encoder
)
4933 ironlake_pch_enable(crtc
);
4935 assert_vblank_disabled(crtc
);
4936 drm_crtc_vblank_on(crtc
);
4938 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
4939 encoder
->enable(encoder
);
4941 if (HAS_PCH_CPT(dev
))
4942 cpt_verify_modeset(dev
, intel_crtc
->pipe
);
4945 /* IPS only exists on ULT machines and is tied to pipe A. */
4946 static bool hsw_crtc_supports_ips(struct intel_crtc
*crtc
)
4948 return HAS_IPS(crtc
->base
.dev
) && crtc
->pipe
== PIPE_A
;
4951 static void haswell_crtc_enable(struct drm_crtc
*crtc
)
4953 struct drm_device
*dev
= crtc
->dev
;
4954 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4955 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4956 struct intel_encoder
*encoder
;
4957 int pipe
= intel_crtc
->pipe
, hsw_workaround_pipe
;
4958 struct intel_crtc_state
*pipe_config
=
4959 to_intel_crtc_state(crtc
->state
);
4960 bool is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
4962 if (WARN_ON(intel_crtc
->active
))
4965 if (intel_crtc_to_shared_dpll(intel_crtc
))
4966 intel_enable_shared_dpll(intel_crtc
);
4968 if (intel_crtc
->config
->has_dp_encoder
)
4969 intel_dp_set_m_n(intel_crtc
, M1_N1
);
4971 intel_set_pipe_timings(intel_crtc
);
4973 if (intel_crtc
->config
->cpu_transcoder
!= TRANSCODER_EDP
) {
4974 I915_WRITE(PIPE_MULT(intel_crtc
->config
->cpu_transcoder
),
4975 intel_crtc
->config
->pixel_multiplier
- 1);
4978 if (intel_crtc
->config
->has_pch_encoder
) {
4979 intel_cpu_transcoder_set_m_n(intel_crtc
,
4980 &intel_crtc
->config
->fdi_m_n
, NULL
);
4983 haswell_set_pipeconf(crtc
);
4985 intel_set_pipe_csc(crtc
);
4987 intel_crtc
->active
= true;
4989 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
4990 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
4991 if (encoder
->pre_pll_enable
)
4992 encoder
->pre_pll_enable(encoder
);
4993 if (encoder
->pre_enable
)
4994 encoder
->pre_enable(encoder
);
4997 if (intel_crtc
->config
->has_pch_encoder
) {
4998 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5000 dev_priv
->display
.fdi_link_train(crtc
);
5004 intel_ddi_enable_pipe_clock(intel_crtc
);
5006 if (INTEL_INFO(dev
)->gen
>= 9)
5007 skylake_pfit_enable(intel_crtc
);
5009 ironlake_pfit_enable(intel_crtc
);
5012 * On ILK+ LUT must be loaded before the pipe is running but with
5015 intel_crtc_load_lut(crtc
);
5017 intel_ddi_set_pipe_settings(crtc
);
5019 intel_ddi_enable_transcoder_func(crtc
);
5021 intel_update_watermarks(crtc
);
5022 intel_enable_pipe(intel_crtc
);
5024 if (intel_crtc
->config
->has_pch_encoder
)
5025 lpt_pch_enable(crtc
);
5027 if (intel_crtc
->config
->dp_encoder_is_mst
&& !is_dsi
)
5028 intel_ddi_set_vc_payload_alloc(crtc
, true);
5030 assert_vblank_disabled(crtc
);
5031 drm_crtc_vblank_on(crtc
);
5033 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5034 encoder
->enable(encoder
);
5035 intel_opregion_notify_encoder(encoder
, true);
5038 /* If we change the relative order between pipe/planes enabling, we need
5039 * to change the workaround. */
5040 hsw_workaround_pipe
= pipe_config
->hsw_workaround_pipe
;
5041 if (IS_HASWELL(dev
) && hsw_workaround_pipe
!= INVALID_PIPE
) {
5042 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
5043 intel_wait_for_vblank(dev
, hsw_workaround_pipe
);
5047 static void ironlake_pfit_disable(struct intel_crtc
*crtc
, bool force
)
5049 struct drm_device
*dev
= crtc
->base
.dev
;
5050 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5051 int pipe
= crtc
->pipe
;
5053 /* To avoid upsetting the power well on haswell only disable the pfit if
5054 * it's in use. The hw state code will make sure we get this right. */
5055 if (force
|| crtc
->config
->pch_pfit
.enabled
) {
5056 I915_WRITE(PF_CTL(pipe
), 0);
5057 I915_WRITE(PF_WIN_POS(pipe
), 0);
5058 I915_WRITE(PF_WIN_SZ(pipe
), 0);
5062 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
5064 struct drm_device
*dev
= crtc
->dev
;
5065 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5066 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5067 struct intel_encoder
*encoder
;
5068 int pipe
= intel_crtc
->pipe
;
5071 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5072 encoder
->disable(encoder
);
5074 drm_crtc_vblank_off(crtc
);
5075 assert_vblank_disabled(crtc
);
5077 if (intel_crtc
->config
->has_pch_encoder
)
5078 intel_set_pch_fifo_underrun_reporting(dev_priv
, pipe
, false);
5080 intel_disable_pipe(intel_crtc
);
5082 ironlake_pfit_disable(intel_crtc
, false);
5084 if (intel_crtc
->config
->has_pch_encoder
)
5085 ironlake_fdi_disable(crtc
);
5087 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5088 if (encoder
->post_disable
)
5089 encoder
->post_disable(encoder
);
5091 if (intel_crtc
->config
->has_pch_encoder
) {
5092 ironlake_disable_pch_transcoder(dev_priv
, pipe
);
5094 if (HAS_PCH_CPT(dev
)) {
5095 /* disable TRANS_DP_CTL */
5096 reg
= TRANS_DP_CTL(pipe
);
5097 temp
= I915_READ(reg
);
5098 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
|
5099 TRANS_DP_PORT_SEL_MASK
);
5100 temp
|= TRANS_DP_PORT_SEL_NONE
;
5101 I915_WRITE(reg
, temp
);
5103 /* disable DPLL_SEL */
5104 temp
= I915_READ(PCH_DPLL_SEL
);
5105 temp
&= ~(TRANS_DPLL_ENABLE(pipe
) | TRANS_DPLLB_SEL(pipe
));
5106 I915_WRITE(PCH_DPLL_SEL
, temp
);
5109 ironlake_fdi_pll_disable(intel_crtc
);
5113 static void haswell_crtc_disable(struct drm_crtc
*crtc
)
5115 struct drm_device
*dev
= crtc
->dev
;
5116 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5117 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5118 struct intel_encoder
*encoder
;
5119 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
5120 bool is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
5122 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
5123 intel_opregion_notify_encoder(encoder
, false);
5124 encoder
->disable(encoder
);
5127 drm_crtc_vblank_off(crtc
);
5128 assert_vblank_disabled(crtc
);
5130 if (intel_crtc
->config
->has_pch_encoder
)
5131 intel_set_pch_fifo_underrun_reporting(dev_priv
, TRANSCODER_A
,
5133 intel_disable_pipe(intel_crtc
);
5135 if (intel_crtc
->config
->dp_encoder_is_mst
)
5136 intel_ddi_set_vc_payload_alloc(crtc
, false);
5139 intel_ddi_disable_transcoder_func(dev_priv
, cpu_transcoder
);
5141 if (INTEL_INFO(dev
)->gen
>= 9)
5142 skylake_scaler_disable(intel_crtc
);
5144 ironlake_pfit_disable(intel_crtc
, false);
5147 intel_ddi_disable_pipe_clock(intel_crtc
);
5149 if (intel_crtc
->config
->has_pch_encoder
) {
5150 lpt_disable_pch_transcoder(dev_priv
);
5151 intel_ddi_fdi_disable(crtc
);
5154 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
5155 if (encoder
->post_disable
)
5156 encoder
->post_disable(encoder
);
5159 static void i9xx_pfit_enable(struct intel_crtc
*crtc
)
5161 struct drm_device
*dev
= crtc
->base
.dev
;
5162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5163 struct intel_crtc_state
*pipe_config
= crtc
->config
;
5165 if (!pipe_config
->gmch_pfit
.control
)
5169 * The panel fitter should only be adjusted whilst the pipe is disabled,
5170 * according to register description and PRM.
5172 WARN_ON(I915_READ(PFIT_CONTROL
) & PFIT_ENABLE
);
5173 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
5175 I915_WRITE(PFIT_PGM_RATIOS
, pipe_config
->gmch_pfit
.pgm_ratios
);
5176 I915_WRITE(PFIT_CONTROL
, pipe_config
->gmch_pfit
.control
);
5178 /* Border color in case we don't scale up to the full screen. Black by
5179 * default, change to something else for debugging. */
5180 I915_WRITE(BCLRPAT(crtc
->pipe
), 0);
5183 static enum intel_display_power_domain
port_to_power_domain(enum port port
)
5187 return POWER_DOMAIN_PORT_DDI_A_4_LANES
;
5189 return POWER_DOMAIN_PORT_DDI_B_4_LANES
;
5191 return POWER_DOMAIN_PORT_DDI_C_4_LANES
;
5193 return POWER_DOMAIN_PORT_DDI_D_4_LANES
;
5195 return POWER_DOMAIN_PORT_DDI_E_2_LANES
;
5198 return POWER_DOMAIN_PORT_OTHER
;
5202 static enum intel_display_power_domain
port_to_aux_power_domain(enum port port
)
5206 return POWER_DOMAIN_AUX_A
;
5208 return POWER_DOMAIN_AUX_B
;
5210 return POWER_DOMAIN_AUX_C
;
5212 return POWER_DOMAIN_AUX_D
;
5214 /* FIXME: Check VBT for actual wiring of PORT E */
5215 return POWER_DOMAIN_AUX_D
;
5218 return POWER_DOMAIN_AUX_A
;
5222 #define for_each_power_domain(domain, mask) \
5223 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5224 if ((1 << (domain)) & (mask))
5226 enum intel_display_power_domain
5227 intel_display_port_power_domain(struct intel_encoder
*intel_encoder
)
5229 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5230 struct intel_digital_port
*intel_dig_port
;
5232 switch (intel_encoder
->type
) {
5233 case INTEL_OUTPUT_UNKNOWN
:
5234 /* Only DDI platforms should ever use this output type */
5235 WARN_ON_ONCE(!HAS_DDI(dev
));
5236 case INTEL_OUTPUT_DISPLAYPORT
:
5237 case INTEL_OUTPUT_HDMI
:
5238 case INTEL_OUTPUT_EDP
:
5239 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5240 return port_to_power_domain(intel_dig_port
->port
);
5241 case INTEL_OUTPUT_DP_MST
:
5242 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5243 return port_to_power_domain(intel_dig_port
->port
);
5244 case INTEL_OUTPUT_ANALOG
:
5245 return POWER_DOMAIN_PORT_CRT
;
5246 case INTEL_OUTPUT_DSI
:
5247 return POWER_DOMAIN_PORT_DSI
;
5249 return POWER_DOMAIN_PORT_OTHER
;
5253 enum intel_display_power_domain
5254 intel_display_port_aux_power_domain(struct intel_encoder
*intel_encoder
)
5256 struct drm_device
*dev
= intel_encoder
->base
.dev
;
5257 struct intel_digital_port
*intel_dig_port
;
5259 switch (intel_encoder
->type
) {
5260 case INTEL_OUTPUT_UNKNOWN
:
5261 case INTEL_OUTPUT_HDMI
:
5263 * Only DDI platforms should ever use these output types.
5264 * We can get here after the HDMI detect code has already set
5265 * the type of the shared encoder. Since we can't be sure
5266 * what's the status of the given connectors, play safe and
5267 * run the DP detection too.
5269 WARN_ON_ONCE(!HAS_DDI(dev
));
5270 case INTEL_OUTPUT_DISPLAYPORT
:
5271 case INTEL_OUTPUT_EDP
:
5272 intel_dig_port
= enc_to_dig_port(&intel_encoder
->base
);
5273 return port_to_aux_power_domain(intel_dig_port
->port
);
5274 case INTEL_OUTPUT_DP_MST
:
5275 intel_dig_port
= enc_to_mst(&intel_encoder
->base
)->primary
;
5276 return port_to_aux_power_domain(intel_dig_port
->port
);
5278 MISSING_CASE(intel_encoder
->type
);
5279 return POWER_DOMAIN_AUX_A
;
5283 static unsigned long get_crtc_power_domains(struct drm_crtc
*crtc
)
5285 struct drm_device
*dev
= crtc
->dev
;
5286 struct intel_encoder
*intel_encoder
;
5287 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5288 enum pipe pipe
= intel_crtc
->pipe
;
5290 enum transcoder transcoder
;
5292 if (!crtc
->state
->active
)
5295 transcoder
= intel_pipe_to_cpu_transcoder(dev
->dev_private
, pipe
);
5297 mask
= BIT(POWER_DOMAIN_PIPE(pipe
));
5298 mask
|= BIT(POWER_DOMAIN_TRANSCODER(transcoder
));
5299 if (intel_crtc
->config
->pch_pfit
.enabled
||
5300 intel_crtc
->config
->pch_pfit
.force_thru
)
5301 mask
|= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe
));
5303 for_each_encoder_on_crtc(dev
, crtc
, intel_encoder
)
5304 mask
|= BIT(intel_display_port_power_domain(intel_encoder
));
5309 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc
*crtc
)
5311 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
5312 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5313 enum intel_display_power_domain domain
;
5314 unsigned long domains
, new_domains
, old_domains
;
5316 old_domains
= intel_crtc
->enabled_power_domains
;
5317 intel_crtc
->enabled_power_domains
= new_domains
= get_crtc_power_domains(crtc
);
5319 domains
= new_domains
& ~old_domains
;
5321 for_each_power_domain(domain
, domains
)
5322 intel_display_power_get(dev_priv
, domain
);
5324 return old_domains
& ~new_domains
;
5327 static void modeset_put_power_domains(struct drm_i915_private
*dev_priv
,
5328 unsigned long domains
)
5330 enum intel_display_power_domain domain
;
5332 for_each_power_domain(domain
, domains
)
5333 intel_display_power_put(dev_priv
, domain
);
5336 static void modeset_update_crtc_power_domains(struct drm_atomic_state
*state
)
5338 struct drm_device
*dev
= state
->dev
;
5339 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5340 unsigned long put_domains
[I915_MAX_PIPES
] = {};
5341 struct drm_crtc_state
*crtc_state
;
5342 struct drm_crtc
*crtc
;
5345 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
5346 if (needs_modeset(crtc
->state
))
5347 put_domains
[to_intel_crtc(crtc
)->pipe
] =
5348 modeset_get_crtc_power_domains(crtc
);
5351 if (dev_priv
->display
.modeset_commit_cdclk
) {
5352 unsigned int cdclk
= to_intel_atomic_state(state
)->cdclk
;
5354 if (cdclk
!= dev_priv
->cdclk_freq
&&
5355 !WARN_ON(!state
->allow_modeset
))
5356 dev_priv
->display
.modeset_commit_cdclk(state
);
5359 for (i
= 0; i
< I915_MAX_PIPES
; i
++)
5361 modeset_put_power_domains(dev_priv
, put_domains
[i
]);
5364 static int intel_compute_max_dotclk(struct drm_i915_private
*dev_priv
)
5366 int max_cdclk_freq
= dev_priv
->max_cdclk_freq
;
5368 if (INTEL_INFO(dev_priv
)->gen
>= 9 ||
5369 IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
5370 return max_cdclk_freq
;
5371 else if (IS_CHERRYVIEW(dev_priv
))
5372 return max_cdclk_freq
*95/100;
5373 else if (INTEL_INFO(dev_priv
)->gen
< 4)
5374 return 2*max_cdclk_freq
*90/100;
5376 return max_cdclk_freq
*90/100;
5379 static void intel_update_max_cdclk(struct drm_device
*dev
)
5381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5383 if (IS_SKYLAKE(dev
)) {
5384 u32 limit
= I915_READ(SKL_DFSM
) & SKL_DFSM_CDCLK_LIMIT_MASK
;
5386 if (limit
== SKL_DFSM_CDCLK_LIMIT_675
)
5387 dev_priv
->max_cdclk_freq
= 675000;
5388 else if (limit
== SKL_DFSM_CDCLK_LIMIT_540
)
5389 dev_priv
->max_cdclk_freq
= 540000;
5390 else if (limit
== SKL_DFSM_CDCLK_LIMIT_450
)
5391 dev_priv
->max_cdclk_freq
= 450000;
5393 dev_priv
->max_cdclk_freq
= 337500;
5394 } else if (IS_BROADWELL(dev
)) {
5396 * FIXME with extra cooling we can allow
5397 * 540 MHz for ULX and 675 Mhz for ULT.
5398 * How can we know if extra cooling is
5399 * available? PCI ID, VTB, something else?
5401 if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
5402 dev_priv
->max_cdclk_freq
= 450000;
5403 else if (IS_BDW_ULX(dev
))
5404 dev_priv
->max_cdclk_freq
= 450000;
5405 else if (IS_BDW_ULT(dev
))
5406 dev_priv
->max_cdclk_freq
= 540000;
5408 dev_priv
->max_cdclk_freq
= 675000;
5409 } else if (IS_CHERRYVIEW(dev
)) {
5410 dev_priv
->max_cdclk_freq
= 320000;
5411 } else if (IS_VALLEYVIEW(dev
)) {
5412 dev_priv
->max_cdclk_freq
= 400000;
5414 /* otherwise assume cdclk is fixed */
5415 dev_priv
->max_cdclk_freq
= dev_priv
->cdclk_freq
;
5418 dev_priv
->max_dotclk_freq
= intel_compute_max_dotclk(dev_priv
);
5420 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5421 dev_priv
->max_cdclk_freq
);
5423 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5424 dev_priv
->max_dotclk_freq
);
5427 static void intel_update_cdclk(struct drm_device
*dev
)
5429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5431 dev_priv
->cdclk_freq
= dev_priv
->display
.get_display_clock_speed(dev
);
5432 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5433 dev_priv
->cdclk_freq
);
5436 * Program the gmbus_freq based on the cdclk frequency.
5437 * BSpec erroneously claims we should aim for 4MHz, but
5438 * in fact 1MHz is the correct frequency.
5440 if (IS_VALLEYVIEW(dev
)) {
5442 * Program the gmbus_freq based on the cdclk frequency.
5443 * BSpec erroneously claims we should aim for 4MHz, but
5444 * in fact 1MHz is the correct frequency.
5446 I915_WRITE(GMBUSFREQ_VLV
, DIV_ROUND_UP(dev_priv
->cdclk_freq
, 1000));
5449 if (dev_priv
->max_cdclk_freq
== 0)
5450 intel_update_max_cdclk(dev
);
5453 static void broxton_set_cdclk(struct drm_device
*dev
, int frequency
)
5455 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5458 uint32_t current_freq
;
5461 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5462 switch (frequency
) {
5464 divider
= BXT_CDCLK_CD2X_DIV_SEL_4
;
5465 ratio
= BXT_DE_PLL_RATIO(60);
5468 divider
= BXT_CDCLK_CD2X_DIV_SEL_2
;
5469 ratio
= BXT_DE_PLL_RATIO(60);
5472 divider
= BXT_CDCLK_CD2X_DIV_SEL_1_5
;
5473 ratio
= BXT_DE_PLL_RATIO(60);
5476 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5477 ratio
= BXT_DE_PLL_RATIO(60);
5480 divider
= BXT_CDCLK_CD2X_DIV_SEL_1
;
5481 ratio
= BXT_DE_PLL_RATIO(65);
5485 * Bypass frequency with DE PLL disabled. Init ratio, divider
5486 * to suppress GCC warning.
5492 DRM_ERROR("unsupported CDCLK freq %d", frequency
);
5497 mutex_lock(&dev_priv
->rps
.hw_lock
);
5498 /* Inform power controller of upcoming frequency change */
5499 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5501 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5504 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5509 current_freq
= I915_READ(CDCLK_CTL
) & CDCLK_FREQ_DECIMAL_MASK
;
5510 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5511 current_freq
= current_freq
* 500 + 1000;
5514 * DE PLL has to be disabled when
5515 * - setting to 19.2MHz (bypass, PLL isn't used)
5516 * - before setting to 624MHz (PLL needs toggling)
5517 * - before setting to any frequency from 624MHz (PLL needs toggling)
5519 if (frequency
== 19200 || frequency
== 624000 ||
5520 current_freq
== 624000) {
5521 I915_WRITE(BXT_DE_PLL_ENABLE
, ~BXT_DE_PLL_PLL_ENABLE
);
5523 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
),
5525 DRM_ERROR("timout waiting for DE PLL unlock\n");
5528 if (frequency
!= 19200) {
5531 val
= I915_READ(BXT_DE_PLL_CTL
);
5532 val
&= ~BXT_DE_PLL_RATIO_MASK
;
5534 I915_WRITE(BXT_DE_PLL_CTL
, val
);
5536 I915_WRITE(BXT_DE_PLL_ENABLE
, BXT_DE_PLL_PLL_ENABLE
);
5538 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_LOCK
, 1))
5539 DRM_ERROR("timeout waiting for DE PLL lock\n");
5541 val
= I915_READ(CDCLK_CTL
);
5542 val
&= ~BXT_CDCLK_CD2X_DIV_SEL_MASK
;
5545 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5548 val
&= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5549 if (frequency
>= 500000)
5550 val
|= BXT_CDCLK_SSA_PRECHARGE_ENABLE
;
5552 val
&= ~CDCLK_FREQ_DECIMAL_MASK
;
5553 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5554 val
|= (frequency
- 1000) / 500;
5555 I915_WRITE(CDCLK_CTL
, val
);
5558 mutex_lock(&dev_priv
->rps
.hw_lock
);
5559 ret
= sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
,
5560 DIV_ROUND_UP(frequency
, 25000));
5561 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5564 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5569 intel_update_cdclk(dev
);
5572 void broxton_init_cdclk(struct drm_device
*dev
)
5574 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5578 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5579 * or else the reset will hang because there is no PCH to respond.
5580 * Move the handshake programming to initialization sequence.
5581 * Previously was left up to BIOS.
5583 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5584 val
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
5585 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
);
5587 /* Enable PG1 for cdclk */
5588 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5590 /* check if cd clock is enabled */
5591 if (I915_READ(BXT_DE_PLL_ENABLE
) & BXT_DE_PLL_PLL_ENABLE
) {
5592 DRM_DEBUG_KMS("Display already initialized\n");
5598 * - The initial CDCLK needs to be read from VBT.
5599 * Need to make this change after VBT has changes for BXT.
5600 * - check if setting the max (or any) cdclk freq is really necessary
5601 * here, it belongs to modeset time
5603 broxton_set_cdclk(dev
, 624000);
5605 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5606 POSTING_READ(DBUF_CTL
);
5610 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5611 DRM_ERROR("DBuf power enable timeout!\n");
5614 void broxton_uninit_cdclk(struct drm_device
*dev
)
5616 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5618 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5619 POSTING_READ(DBUF_CTL
);
5623 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5624 DRM_ERROR("DBuf power disable timeout!\n");
5626 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5627 broxton_set_cdclk(dev
, 19200);
5629 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5632 static const struct skl_cdclk_entry
{
5635 } skl_cdclk_frequencies
[] = {
5636 { .freq
= 308570, .vco
= 8640 },
5637 { .freq
= 337500, .vco
= 8100 },
5638 { .freq
= 432000, .vco
= 8640 },
5639 { .freq
= 450000, .vco
= 8100 },
5640 { .freq
= 540000, .vco
= 8100 },
5641 { .freq
= 617140, .vco
= 8640 },
5642 { .freq
= 675000, .vco
= 8100 },
5645 static unsigned int skl_cdclk_decimal(unsigned int freq
)
5647 return (freq
- 1000) / 500;
5650 static unsigned int skl_cdclk_get_vco(unsigned int freq
)
5654 for (i
= 0; i
< ARRAY_SIZE(skl_cdclk_frequencies
); i
++) {
5655 const struct skl_cdclk_entry
*e
= &skl_cdclk_frequencies
[i
];
5657 if (e
->freq
== freq
)
5665 skl_dpll0_enable(struct drm_i915_private
*dev_priv
, unsigned int required_vco
)
5667 unsigned int min_freq
;
5670 /* select the minimum CDCLK before enabling DPLL 0 */
5671 val
= I915_READ(CDCLK_CTL
);
5672 val
&= ~CDCLK_FREQ_SEL_MASK
| ~CDCLK_FREQ_DECIMAL_MASK
;
5673 val
|= CDCLK_FREQ_337_308
;
5675 if (required_vco
== 8640)
5680 val
= CDCLK_FREQ_337_308
| skl_cdclk_decimal(min_freq
);
5682 I915_WRITE(CDCLK_CTL
, val
);
5683 POSTING_READ(CDCLK_CTL
);
5686 * We always enable DPLL0 with the lowest link rate possible, but still
5687 * taking into account the VCO required to operate the eDP panel at the
5688 * desired frequency. The usual DP link rates operate with a VCO of
5689 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5690 * The modeset code is responsible for the selection of the exact link
5691 * rate later on, with the constraint of choosing a frequency that
5692 * works with required_vco.
5694 val
= I915_READ(DPLL_CTRL1
);
5696 val
&= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0
) | DPLL_CTRL1_SSC(SKL_DPLL0
) |
5697 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
));
5698 val
|= DPLL_CTRL1_OVERRIDE(SKL_DPLL0
);
5699 if (required_vco
== 8640)
5700 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080
,
5703 val
|= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810
,
5706 I915_WRITE(DPLL_CTRL1
, val
);
5707 POSTING_READ(DPLL_CTRL1
);
5709 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) | LCPLL_PLL_ENABLE
);
5711 if (wait_for(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
, 5))
5712 DRM_ERROR("DPLL0 not locked\n");
5715 static bool skl_cdclk_pcu_ready(struct drm_i915_private
*dev_priv
)
5720 /* inform PCU we want to change CDCLK */
5721 val
= SKL_CDCLK_PREPARE_FOR_CHANGE
;
5722 mutex_lock(&dev_priv
->rps
.hw_lock
);
5723 ret
= sandybridge_pcode_read(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, &val
);
5724 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5726 return ret
== 0 && (val
& SKL_CDCLK_READY_FOR_CHANGE
);
5729 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private
*dev_priv
)
5733 for (i
= 0; i
< 15; i
++) {
5734 if (skl_cdclk_pcu_ready(dev_priv
))
5742 static void skl_set_cdclk(struct drm_i915_private
*dev_priv
, unsigned int freq
)
5744 struct drm_device
*dev
= dev_priv
->dev
;
5745 u32 freq_select
, pcu_ack
;
5747 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq
);
5749 if (!skl_cdclk_wait_for_pcu_ready(dev_priv
)) {
5750 DRM_ERROR("failed to inform PCU about cdclk change\n");
5758 freq_select
= CDCLK_FREQ_450_432
;
5762 freq_select
= CDCLK_FREQ_540
;
5768 freq_select
= CDCLK_FREQ_337_308
;
5773 freq_select
= CDCLK_FREQ_675_617
;
5778 I915_WRITE(CDCLK_CTL
, freq_select
| skl_cdclk_decimal(freq
));
5779 POSTING_READ(CDCLK_CTL
);
5781 /* inform PCU of the change */
5782 mutex_lock(&dev_priv
->rps
.hw_lock
);
5783 sandybridge_pcode_write(dev_priv
, SKL_PCODE_CDCLK_CONTROL
, pcu_ack
);
5784 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5786 intel_update_cdclk(dev
);
5789 void skl_uninit_cdclk(struct drm_i915_private
*dev_priv
)
5791 /* disable DBUF power */
5792 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) & ~DBUF_POWER_REQUEST
);
5793 POSTING_READ(DBUF_CTL
);
5797 if (I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
)
5798 DRM_ERROR("DBuf power disable timeout\n");
5801 * DMC assumes ownership of LCPLL and will get confused if we touch it.
5803 if (dev_priv
->csr
.dmc_payload
) {
5805 I915_WRITE(LCPLL1_CTL
, I915_READ(LCPLL1_CTL
) &
5807 if (wait_for(!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_LOCK
), 1))
5808 DRM_ERROR("Couldn't disable DPLL0\n");
5811 intel_display_power_put(dev_priv
, POWER_DOMAIN_PLLS
);
5814 void skl_init_cdclk(struct drm_i915_private
*dev_priv
)
5817 unsigned int required_vco
;
5819 /* enable PCH reset handshake */
5820 val
= I915_READ(HSW_NDE_RSTWRN_OPT
);
5821 I915_WRITE(HSW_NDE_RSTWRN_OPT
, val
| RESET_PCH_HANDSHAKE_ENABLE
);
5823 /* enable PG1 and Misc I/O */
5824 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
5826 /* DPLL0 not enabled (happens on early BIOS versions) */
5827 if (!(I915_READ(LCPLL1_CTL
) & LCPLL_PLL_ENABLE
)) {
5829 required_vco
= skl_cdclk_get_vco(dev_priv
->skl_boot_cdclk
);
5830 skl_dpll0_enable(dev_priv
, required_vco
);
5833 /* set CDCLK to the frequency the BIOS chose */
5834 skl_set_cdclk(dev_priv
, dev_priv
->skl_boot_cdclk
);
5836 /* enable DBUF power */
5837 I915_WRITE(DBUF_CTL
, I915_READ(DBUF_CTL
) | DBUF_POWER_REQUEST
);
5838 POSTING_READ(DBUF_CTL
);
5842 if (!(I915_READ(DBUF_CTL
) & DBUF_POWER_STATE
))
5843 DRM_ERROR("DBuf power enable timeout\n");
5846 /* Adjust CDclk dividers to allow high res or save power if possible */
5847 static void valleyview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5849 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5852 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5853 != dev_priv
->cdclk_freq
);
5855 if (cdclk
>= 320000) /* jump to highest voltage for 400MHz too */
5857 else if (cdclk
== 266667)
5862 mutex_lock(&dev_priv
->rps
.hw_lock
);
5863 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5864 val
&= ~DSPFREQGUAR_MASK
;
5865 val
|= (cmd
<< DSPFREQGUAR_SHIFT
);
5866 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5867 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5868 DSPFREQSTAT_MASK
) == (cmd
<< DSPFREQSTAT_SHIFT
),
5870 DRM_ERROR("timed out waiting for CDclk change\n");
5872 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5874 mutex_lock(&dev_priv
->sb_lock
);
5876 if (cdclk
== 400000) {
5879 divider
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5881 /* adjust cdclk divider */
5882 val
= vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
);
5883 val
&= ~CCK_FREQUENCY_VALUES
;
5885 vlv_cck_write(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
, val
);
5887 if (wait_for((vlv_cck_read(dev_priv
, CCK_DISPLAY_CLOCK_CONTROL
) &
5888 CCK_FREQUENCY_STATUS
) == (divider
<< CCK_FREQUENCY_STATUS_SHIFT
),
5890 DRM_ERROR("timed out waiting for CDclk change\n");
5893 /* adjust self-refresh exit latency value */
5894 val
= vlv_bunit_read(dev_priv
, BUNIT_REG_BISOC
);
5898 * For high bandwidth configs, we set a higher latency in the bunit
5899 * so that the core display fetch happens in time to avoid underruns.
5901 if (cdclk
== 400000)
5902 val
|= 4500 / 250; /* 4.5 usec */
5904 val
|= 3000 / 250; /* 3.0 usec */
5905 vlv_bunit_write(dev_priv
, BUNIT_REG_BISOC
, val
);
5907 mutex_unlock(&dev_priv
->sb_lock
);
5909 intel_update_cdclk(dev
);
5912 static void cherryview_set_cdclk(struct drm_device
*dev
, int cdclk
)
5914 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5917 WARN_ON(dev_priv
->display
.get_display_clock_speed(dev
)
5918 != dev_priv
->cdclk_freq
);
5927 MISSING_CASE(cdclk
);
5932 * Specs are full of misinformation, but testing on actual
5933 * hardware has shown that we just need to write the desired
5934 * CCK divider into the Punit register.
5936 cmd
= DIV_ROUND_CLOSEST(dev_priv
->hpll_freq
<< 1, cdclk
) - 1;
5938 mutex_lock(&dev_priv
->rps
.hw_lock
);
5939 val
= vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
);
5940 val
&= ~DSPFREQGUAR_MASK_CHV
;
5941 val
|= (cmd
<< DSPFREQGUAR_SHIFT_CHV
);
5942 vlv_punit_write(dev_priv
, PUNIT_REG_DSPFREQ
, val
);
5943 if (wait_for((vlv_punit_read(dev_priv
, PUNIT_REG_DSPFREQ
) &
5944 DSPFREQSTAT_MASK_CHV
) == (cmd
<< DSPFREQSTAT_SHIFT_CHV
),
5946 DRM_ERROR("timed out waiting for CDclk change\n");
5948 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5950 intel_update_cdclk(dev
);
5953 static int valleyview_calc_cdclk(struct drm_i915_private
*dev_priv
,
5956 int freq_320
= (dev_priv
->hpll_freq
<< 1) % 320000 != 0 ? 333333 : 320000;
5957 int limit
= IS_CHERRYVIEW(dev_priv
) ? 95 : 90;
5960 * Really only a few cases to deal with, as only 4 CDclks are supported:
5963 * 320/333MHz (depends on HPLL freq)
5965 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5966 * of the lower bin and adjust if needed.
5968 * We seem to get an unstable or solid color picture at 200MHz.
5969 * Not sure what's wrong. For now use 200MHz only when all pipes
5972 if (!IS_CHERRYVIEW(dev_priv
) &&
5973 max_pixclk
> freq_320
*limit
/100)
5975 else if (max_pixclk
> 266667*limit
/100)
5977 else if (max_pixclk
> 0)
5983 static int broxton_calc_cdclk(struct drm_i915_private
*dev_priv
,
5988 * - remove the guardband, it's not needed on BXT
5989 * - set 19.2MHz bypass frequency if there are no active pipes
5991 if (max_pixclk
> 576000*9/10)
5993 else if (max_pixclk
> 384000*9/10)
5995 else if (max_pixclk
> 288000*9/10)
5997 else if (max_pixclk
> 144000*9/10)
6003 /* Compute the max pixel clock for new configuration. Uses atomic state if
6004 * that's non-NULL, look at current state otherwise. */
6005 static int intel_mode_max_pixclk(struct drm_device
*dev
,
6006 struct drm_atomic_state
*state
)
6008 struct intel_crtc
*intel_crtc
;
6009 struct intel_crtc_state
*crtc_state
;
6012 for_each_intel_crtc(dev
, intel_crtc
) {
6013 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
6014 if (IS_ERR(crtc_state
))
6015 return PTR_ERR(crtc_state
);
6017 if (!crtc_state
->base
.enable
)
6020 max_pixclk
= max(max_pixclk
,
6021 crtc_state
->base
.adjusted_mode
.crtc_clock
);
6027 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6029 struct drm_device
*dev
= state
->dev
;
6030 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6031 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
6036 to_intel_atomic_state(state
)->cdclk
=
6037 valleyview_calc_cdclk(dev_priv
, max_pixclk
);
6042 static int broxton_modeset_calc_cdclk(struct drm_atomic_state
*state
)
6044 struct drm_device
*dev
= state
->dev
;
6045 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6046 int max_pixclk
= intel_mode_max_pixclk(dev
, state
);
6051 to_intel_atomic_state(state
)->cdclk
=
6052 broxton_calc_cdclk(dev_priv
, max_pixclk
);
6057 static void vlv_program_pfi_credits(struct drm_i915_private
*dev_priv
)
6059 unsigned int credits
, default_credits
;
6061 if (IS_CHERRYVIEW(dev_priv
))
6062 default_credits
= PFI_CREDIT(12);
6064 default_credits
= PFI_CREDIT(8);
6066 if (dev_priv
->cdclk_freq
>= dev_priv
->czclk_freq
) {
6067 /* CHV suggested value is 31 or 63 */
6068 if (IS_CHERRYVIEW(dev_priv
))
6069 credits
= PFI_CREDIT_63
;
6071 credits
= PFI_CREDIT(15);
6073 credits
= default_credits
;
6077 * WA - write default credits before re-programming
6078 * FIXME: should we also set the resend bit here?
6080 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6083 I915_WRITE(GCI_CONTROL
, VGA_FAST_MODE_DISABLE
|
6084 credits
| PFI_CREDIT_RESEND
);
6087 * FIXME is this guaranteed to clear
6088 * immediately or should we poll for it?
6090 WARN_ON(I915_READ(GCI_CONTROL
) & PFI_CREDIT_RESEND
);
6093 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
6095 struct drm_device
*dev
= old_state
->dev
;
6096 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
6097 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6100 * FIXME: We can end up here with all power domains off, yet
6101 * with a CDCLK frequency other than the minimum. To account
6102 * for this take the PIPE-A power domain, which covers the HW
6103 * blocks needed for the following programming. This can be
6104 * removed once it's guaranteed that we get here either with
6105 * the minimum CDCLK set, or the required power domains
6108 intel_display_power_get(dev_priv
, POWER_DOMAIN_PIPE_A
);
6110 if (IS_CHERRYVIEW(dev
))
6111 cherryview_set_cdclk(dev
, req_cdclk
);
6113 valleyview_set_cdclk(dev
, req_cdclk
);
6115 vlv_program_pfi_credits(dev_priv
);
6117 intel_display_power_put(dev_priv
, POWER_DOMAIN_PIPE_A
);
6120 static void valleyview_crtc_enable(struct drm_crtc
*crtc
)
6122 struct drm_device
*dev
= crtc
->dev
;
6123 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6124 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6125 struct intel_encoder
*encoder
;
6126 int pipe
= intel_crtc
->pipe
;
6129 if (WARN_ON(intel_crtc
->active
))
6132 is_dsi
= intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
);
6134 if (intel_crtc
->config
->has_dp_encoder
)
6135 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6137 intel_set_pipe_timings(intel_crtc
);
6139 if (IS_CHERRYVIEW(dev
) && pipe
== PIPE_B
) {
6140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6142 I915_WRITE(CHV_BLEND(pipe
), CHV_BLEND_LEGACY
);
6143 I915_WRITE(CHV_CANVAS(pipe
), 0);
6146 i9xx_set_pipeconf(intel_crtc
);
6148 intel_crtc
->active
= true;
6150 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6152 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6153 if (encoder
->pre_pll_enable
)
6154 encoder
->pre_pll_enable(encoder
);
6157 if (IS_CHERRYVIEW(dev
)) {
6158 chv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6159 chv_enable_pll(intel_crtc
, intel_crtc
->config
);
6161 vlv_prepare_pll(intel_crtc
, intel_crtc
->config
);
6162 vlv_enable_pll(intel_crtc
, intel_crtc
->config
);
6166 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6167 if (encoder
->pre_enable
)
6168 encoder
->pre_enable(encoder
);
6170 i9xx_pfit_enable(intel_crtc
);
6172 intel_crtc_load_lut(crtc
);
6174 intel_enable_pipe(intel_crtc
);
6176 assert_vblank_disabled(crtc
);
6177 drm_crtc_vblank_on(crtc
);
6179 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6180 encoder
->enable(encoder
);
6183 static void i9xx_set_pll_dividers(struct intel_crtc
*crtc
)
6185 struct drm_device
*dev
= crtc
->base
.dev
;
6186 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6188 I915_WRITE(FP0(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp0
);
6189 I915_WRITE(FP1(crtc
->pipe
), crtc
->config
->dpll_hw_state
.fp1
);
6192 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
6194 struct drm_device
*dev
= crtc
->dev
;
6195 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6197 struct intel_encoder
*encoder
;
6198 int pipe
= intel_crtc
->pipe
;
6200 if (WARN_ON(intel_crtc
->active
))
6203 i9xx_set_pll_dividers(intel_crtc
);
6205 if (intel_crtc
->config
->has_dp_encoder
)
6206 intel_dp_set_m_n(intel_crtc
, M1_N1
);
6208 intel_set_pipe_timings(intel_crtc
);
6210 i9xx_set_pipeconf(intel_crtc
);
6212 intel_crtc
->active
= true;
6215 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, true);
6217 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6218 if (encoder
->pre_enable
)
6219 encoder
->pre_enable(encoder
);
6221 i9xx_enable_pll(intel_crtc
);
6223 i9xx_pfit_enable(intel_crtc
);
6225 intel_crtc_load_lut(crtc
);
6227 intel_update_watermarks(crtc
);
6228 intel_enable_pipe(intel_crtc
);
6230 assert_vblank_disabled(crtc
);
6231 drm_crtc_vblank_on(crtc
);
6233 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6234 encoder
->enable(encoder
);
6237 static void i9xx_pfit_disable(struct intel_crtc
*crtc
)
6239 struct drm_device
*dev
= crtc
->base
.dev
;
6240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6242 if (!crtc
->config
->gmch_pfit
.control
)
6245 assert_pipe_disabled(dev_priv
, crtc
->pipe
);
6247 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6248 I915_READ(PFIT_CONTROL
));
6249 I915_WRITE(PFIT_CONTROL
, 0);
6252 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
6254 struct drm_device
*dev
= crtc
->dev
;
6255 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6256 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6257 struct intel_encoder
*encoder
;
6258 int pipe
= intel_crtc
->pipe
;
6261 * On gen2 planes are double buffered but the pipe isn't, so we must
6262 * wait for planes to fully turn off before disabling the pipe.
6263 * We also need to wait on all gmch platforms because of the
6264 * self-refresh mode constraint explained above.
6266 intel_wait_for_vblank(dev
, pipe
);
6268 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6269 encoder
->disable(encoder
);
6271 drm_crtc_vblank_off(crtc
);
6272 assert_vblank_disabled(crtc
);
6274 intel_disable_pipe(intel_crtc
);
6276 i9xx_pfit_disable(intel_crtc
);
6278 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6279 if (encoder
->post_disable
)
6280 encoder
->post_disable(encoder
);
6282 if (!intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_DSI
)) {
6283 if (IS_CHERRYVIEW(dev
))
6284 chv_disable_pll(dev_priv
, pipe
);
6285 else if (IS_VALLEYVIEW(dev
))
6286 vlv_disable_pll(dev_priv
, pipe
);
6288 i9xx_disable_pll(intel_crtc
);
6291 for_each_encoder_on_crtc(dev
, crtc
, encoder
)
6292 if (encoder
->post_pll_disable
)
6293 encoder
->post_pll_disable(encoder
);
6296 intel_set_cpu_fifo_underrun_reporting(dev_priv
, pipe
, false);
6299 static void intel_crtc_disable_noatomic(struct drm_crtc
*crtc
)
6301 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6302 struct drm_i915_private
*dev_priv
= to_i915(crtc
->dev
);
6303 enum intel_display_power_domain domain
;
6304 unsigned long domains
;
6306 if (!intel_crtc
->active
)
6309 if (to_intel_plane_state(crtc
->primary
->state
)->visible
) {
6310 intel_crtc_wait_for_pending_flips(crtc
);
6311 intel_pre_disable_primary(crtc
);
6313 intel_crtc_disable_planes(crtc
, 1 << drm_plane_index(crtc
->primary
));
6314 to_intel_plane_state(crtc
->primary
->state
)->visible
= false;
6317 dev_priv
->display
.crtc_disable(crtc
);
6318 intel_crtc
->active
= false;
6319 intel_update_watermarks(crtc
);
6320 intel_disable_shared_dpll(intel_crtc
);
6322 domains
= intel_crtc
->enabled_power_domains
;
6323 for_each_power_domain(domain
, domains
)
6324 intel_display_power_put(dev_priv
, domain
);
6325 intel_crtc
->enabled_power_domains
= 0;
6329 * turn all crtc's off, but do not adjust state
6330 * This has to be paired with a call to intel_modeset_setup_hw_state.
6332 int intel_display_suspend(struct drm_device
*dev
)
6334 struct drm_mode_config
*config
= &dev
->mode_config
;
6335 struct drm_modeset_acquire_ctx
*ctx
= config
->acquire_ctx
;
6336 struct drm_atomic_state
*state
;
6337 struct drm_crtc
*crtc
;
6338 unsigned crtc_mask
= 0;
6344 lockdep_assert_held(&ctx
->ww_ctx
);
6345 state
= drm_atomic_state_alloc(dev
);
6346 if (WARN_ON(!state
))
6349 state
->acquire_ctx
= ctx
;
6350 state
->allow_modeset
= true;
6352 for_each_crtc(dev
, crtc
) {
6353 struct drm_crtc_state
*crtc_state
=
6354 drm_atomic_get_crtc_state(state
, crtc
);
6356 ret
= PTR_ERR_OR_ZERO(crtc_state
);
6360 if (!crtc_state
->active
)
6363 crtc_state
->active
= false;
6364 crtc_mask
|= 1 << drm_crtc_index(crtc
);
6368 ret
= drm_atomic_commit(state
);
6371 for_each_crtc(dev
, crtc
)
6372 if (crtc_mask
& (1 << drm_crtc_index(crtc
)))
6373 crtc
->state
->active
= true;
6381 DRM_ERROR("Suspending crtc's failed with %i\n", ret
);
6382 drm_atomic_state_free(state
);
6386 void intel_encoder_destroy(struct drm_encoder
*encoder
)
6388 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
6390 drm_encoder_cleanup(encoder
);
6391 kfree(intel_encoder
);
6394 /* Cross check the actual hw state with our own modeset state tracking (and it's
6395 * internal consistency). */
6396 static void intel_connector_check_state(struct intel_connector
*connector
)
6398 struct drm_crtc
*crtc
= connector
->base
.state
->crtc
;
6400 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6401 connector
->base
.base
.id
,
6402 connector
->base
.name
);
6404 if (connector
->get_hw_state(connector
)) {
6405 struct intel_encoder
*encoder
= connector
->encoder
;
6406 struct drm_connector_state
*conn_state
= connector
->base
.state
;
6408 I915_STATE_WARN(!crtc
,
6409 "connector enabled without attached crtc\n");
6414 I915_STATE_WARN(!crtc
->state
->active
,
6415 "connector is active, but attached crtc isn't\n");
6417 if (!encoder
|| encoder
->type
== INTEL_OUTPUT_DP_MST
)
6420 I915_STATE_WARN(conn_state
->best_encoder
!= &encoder
->base
,
6421 "atomic encoder doesn't match attached encoder\n");
6423 I915_STATE_WARN(conn_state
->crtc
!= encoder
->base
.crtc
,
6424 "attached encoder crtc differs from connector crtc\n");
6426 I915_STATE_WARN(crtc
&& crtc
->state
->active
,
6427 "attached crtc is active, but connector isn't\n");
6428 I915_STATE_WARN(!crtc
&& connector
->base
.state
->best_encoder
,
6429 "best encoder set without crtc!\n");
6433 int intel_connector_init(struct intel_connector
*connector
)
6435 struct drm_connector_state
*connector_state
;
6437 connector_state
= kzalloc(sizeof *connector_state
, GFP_KERNEL
);
6438 if (!connector_state
)
6441 connector
->base
.state
= connector_state
;
6445 struct intel_connector
*intel_connector_alloc(void)
6447 struct intel_connector
*connector
;
6449 connector
= kzalloc(sizeof *connector
, GFP_KERNEL
);
6453 if (intel_connector_init(connector
) < 0) {
6461 /* Simple connector->get_hw_state implementation for encoders that support only
6462 * one connector and no cloning and hence the encoder state determines the state
6463 * of the connector. */
6464 bool intel_connector_get_hw_state(struct intel_connector
*connector
)
6467 struct intel_encoder
*encoder
= connector
->encoder
;
6469 return encoder
->get_hw_state(encoder
, &pipe
);
6472 static int pipe_required_fdi_lanes(struct intel_crtc_state
*crtc_state
)
6474 if (crtc_state
->base
.enable
&& crtc_state
->has_pch_encoder
)
6475 return crtc_state
->fdi_lanes
;
6480 static int ironlake_check_fdi_lanes(struct drm_device
*dev
, enum pipe pipe
,
6481 struct intel_crtc_state
*pipe_config
)
6483 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
6484 struct intel_crtc
*other_crtc
;
6485 struct intel_crtc_state
*other_crtc_state
;
6487 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6488 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6489 if (pipe_config
->fdi_lanes
> 4) {
6490 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6491 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6495 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
6496 if (pipe_config
->fdi_lanes
> 2) {
6497 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6498 pipe_config
->fdi_lanes
);
6505 if (INTEL_INFO(dev
)->num_pipes
== 2)
6508 /* Ivybridge 3 pipe is really complicated */
6513 if (pipe_config
->fdi_lanes
<= 2)
6516 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_C
));
6518 intel_atomic_get_crtc_state(state
, other_crtc
);
6519 if (IS_ERR(other_crtc_state
))
6520 return PTR_ERR(other_crtc_state
);
6522 if (pipe_required_fdi_lanes(other_crtc_state
) > 0) {
6523 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6524 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6529 if (pipe_config
->fdi_lanes
> 2) {
6530 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6531 pipe_name(pipe
), pipe_config
->fdi_lanes
);
6535 other_crtc
= to_intel_crtc(intel_get_crtc_for_pipe(dev
, PIPE_B
));
6537 intel_atomic_get_crtc_state(state
, other_crtc
);
6538 if (IS_ERR(other_crtc_state
))
6539 return PTR_ERR(other_crtc_state
);
6541 if (pipe_required_fdi_lanes(other_crtc_state
) > 2) {
6542 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6552 static int ironlake_fdi_compute_config(struct intel_crtc
*intel_crtc
,
6553 struct intel_crtc_state
*pipe_config
)
6555 struct drm_device
*dev
= intel_crtc
->base
.dev
;
6556 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6557 int lane
, link_bw
, fdi_dotclock
, ret
;
6558 bool needs_recompute
= false;
6561 /* FDI is a binary signal running at ~2.7GHz, encoding
6562 * each output octet as 10 bits. The actual frequency
6563 * is stored as a divider into a 100MHz clock, and the
6564 * mode pixel clock is stored in units of 1KHz.
6565 * Hence the bw of each lane in terms of the mode signal
6568 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
6570 fdi_dotclock
= adjusted_mode
->crtc_clock
;
6572 lane
= ironlake_get_lanes_required(fdi_dotclock
, link_bw
,
6573 pipe_config
->pipe_bpp
);
6575 pipe_config
->fdi_lanes
= lane
;
6577 intel_link_compute_m_n(pipe_config
->pipe_bpp
, lane
, fdi_dotclock
,
6578 link_bw
, &pipe_config
->fdi_m_n
);
6580 ret
= ironlake_check_fdi_lanes(intel_crtc
->base
.dev
,
6581 intel_crtc
->pipe
, pipe_config
);
6582 if (ret
== -EINVAL
&& pipe_config
->pipe_bpp
> 6*3) {
6583 pipe_config
->pipe_bpp
-= 2*3;
6584 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6585 pipe_config
->pipe_bpp
);
6586 needs_recompute
= true;
6587 pipe_config
->bw_constrained
= true;
6592 if (needs_recompute
)
6598 static bool pipe_config_supports_ips(struct drm_i915_private
*dev_priv
,
6599 struct intel_crtc_state
*pipe_config
)
6601 if (pipe_config
->pipe_bpp
> 24)
6604 /* HSW can handle pixel rate up to cdclk? */
6605 if (IS_HASWELL(dev_priv
->dev
))
6609 * We compare against max which means we must take
6610 * the increased cdclk requirement into account when
6611 * calculating the new cdclk.
6613 * Should measure whether using a lower cdclk w/o IPS
6615 return ilk_pipe_pixel_rate(pipe_config
) <=
6616 dev_priv
->max_cdclk_freq
* 95 / 100;
6619 static void hsw_compute_ips_config(struct intel_crtc
*crtc
,
6620 struct intel_crtc_state
*pipe_config
)
6622 struct drm_device
*dev
= crtc
->base
.dev
;
6623 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6625 pipe_config
->ips_enabled
= i915
.enable_ips
&&
6626 hsw_crtc_supports_ips(crtc
) &&
6627 pipe_config_supports_ips(dev_priv
, pipe_config
);
6630 static int intel_crtc_compute_config(struct intel_crtc
*crtc
,
6631 struct intel_crtc_state
*pipe_config
)
6633 struct drm_device
*dev
= crtc
->base
.dev
;
6634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6635 const struct drm_display_mode
*adjusted_mode
= &pipe_config
->base
.adjusted_mode
;
6637 /* FIXME should check pixel clock limits on all platforms */
6638 if (INTEL_INFO(dev
)->gen
< 4) {
6639 int clock_limit
= dev_priv
->max_cdclk_freq
;
6642 * Enable pixel doubling when the dot clock
6643 * is > 90% of the (display) core speed.
6645 * GDG double wide on either pipe,
6646 * otherwise pipe A only.
6648 if ((crtc
->pipe
== PIPE_A
|| IS_I915G(dev
)) &&
6649 adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10) {
6651 pipe_config
->double_wide
= true;
6654 if (adjusted_mode
->crtc_clock
> clock_limit
* 9 / 10)
6659 * Pipe horizontal size must be even in:
6661 * - LVDS dual channel mode
6662 * - Double wide pipe
6664 if ((intel_pipe_will_have_type(pipe_config
, INTEL_OUTPUT_LVDS
) &&
6665 intel_is_dual_link_lvds(dev
)) || pipe_config
->double_wide
)
6666 pipe_config
->pipe_src_w
&= ~1;
6668 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6669 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6671 if ((INTEL_INFO(dev
)->gen
> 4 || IS_G4X(dev
)) &&
6672 adjusted_mode
->crtc_hsync_start
== adjusted_mode
->crtc_hdisplay
)
6676 hsw_compute_ips_config(crtc
, pipe_config
);
6678 if (pipe_config
->has_pch_encoder
)
6679 return ironlake_fdi_compute_config(crtc
, pipe_config
);
6684 static int skylake_get_display_clock_speed(struct drm_device
*dev
)
6686 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6687 uint32_t lcpll1
= I915_READ(LCPLL1_CTL
);
6688 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6691 if (!(lcpll1
& LCPLL_PLL_ENABLE
))
6692 return 24000; /* 24MHz is the cd freq with NSSC ref */
6694 if ((cdctl
& CDCLK_FREQ_SEL_MASK
) == CDCLK_FREQ_540
)
6697 linkrate
= (I915_READ(DPLL_CTRL1
) &
6698 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0
)) >> 1;
6700 if (linkrate
== DPLL_CTRL1_LINK_RATE_2160
||
6701 linkrate
== DPLL_CTRL1_LINK_RATE_1080
) {
6703 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6704 case CDCLK_FREQ_450_432
:
6706 case CDCLK_FREQ_337_308
:
6708 case CDCLK_FREQ_675_617
:
6711 WARN(1, "Unknown cd freq selection\n");
6715 switch (cdctl
& CDCLK_FREQ_SEL_MASK
) {
6716 case CDCLK_FREQ_450_432
:
6718 case CDCLK_FREQ_337_308
:
6720 case CDCLK_FREQ_675_617
:
6723 WARN(1, "Unknown cd freq selection\n");
6727 /* error case, do as if DPLL0 isn't enabled */
6731 static int broxton_get_display_clock_speed(struct drm_device
*dev
)
6733 struct drm_i915_private
*dev_priv
= to_i915(dev
);
6734 uint32_t cdctl
= I915_READ(CDCLK_CTL
);
6735 uint32_t pll_ratio
= I915_READ(BXT_DE_PLL_CTL
) & BXT_DE_PLL_RATIO_MASK
;
6736 uint32_t pll_enab
= I915_READ(BXT_DE_PLL_ENABLE
);
6739 if (!(pll_enab
& BXT_DE_PLL_PLL_ENABLE
))
6742 cdclk
= 19200 * pll_ratio
/ 2;
6744 switch (cdctl
& BXT_CDCLK_CD2X_DIV_SEL_MASK
) {
6745 case BXT_CDCLK_CD2X_DIV_SEL_1
:
6746 return cdclk
; /* 576MHz or 624MHz */
6747 case BXT_CDCLK_CD2X_DIV_SEL_1_5
:
6748 return cdclk
* 2 / 3; /* 384MHz */
6749 case BXT_CDCLK_CD2X_DIV_SEL_2
:
6750 return cdclk
/ 2; /* 288MHz */
6751 case BXT_CDCLK_CD2X_DIV_SEL_4
:
6752 return cdclk
/ 4; /* 144MHz */
6755 /* error case, do as if DE PLL isn't enabled */
6759 static int broadwell_get_display_clock_speed(struct drm_device
*dev
)
6761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6762 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6763 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6765 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6767 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6769 else if (freq
== LCPLL_CLK_FREQ_450
)
6771 else if (freq
== LCPLL_CLK_FREQ_54O_BDW
)
6773 else if (freq
== LCPLL_CLK_FREQ_337_5_BDW
)
6779 static int haswell_get_display_clock_speed(struct drm_device
*dev
)
6781 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6782 uint32_t lcpll
= I915_READ(LCPLL_CTL
);
6783 uint32_t freq
= lcpll
& LCPLL_CLK_FREQ_MASK
;
6785 if (lcpll
& LCPLL_CD_SOURCE_FCLK
)
6787 else if (I915_READ(FUSE_STRAP
) & HSW_CDCLK_LIMIT
)
6789 else if (freq
== LCPLL_CLK_FREQ_450
)
6791 else if (IS_HSW_ULT(dev
))
6797 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
6799 return vlv_get_cck_clock_hpll(to_i915(dev
), "cdclk",
6800 CCK_DISPLAY_CLOCK_CONTROL
);
6803 static int ilk_get_display_clock_speed(struct drm_device
*dev
)
6808 static int i945_get_display_clock_speed(struct drm_device
*dev
)
6813 static int i915_get_display_clock_speed(struct drm_device
*dev
)
6818 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
6823 static int pnv_get_display_clock_speed(struct drm_device
*dev
)
6827 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6829 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6830 case GC_DISPLAY_CLOCK_267_MHZ_PNV
:
6832 case GC_DISPLAY_CLOCK_333_MHZ_PNV
:
6834 case GC_DISPLAY_CLOCK_444_MHZ_PNV
:
6836 case GC_DISPLAY_CLOCK_200_MHZ_PNV
:
6839 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc
);
6840 case GC_DISPLAY_CLOCK_133_MHZ_PNV
:
6842 case GC_DISPLAY_CLOCK_167_MHZ_PNV
:
6847 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
6851 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
6853 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
6856 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
6857 case GC_DISPLAY_CLOCK_333_MHZ
:
6860 case GC_DISPLAY_CLOCK_190_200_MHZ
:
6866 static int i865_get_display_clock_speed(struct drm_device
*dev
)
6871 static int i85x_get_display_clock_speed(struct drm_device
*dev
)
6876 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6877 * encoding is different :(
6878 * FIXME is this the right way to detect 852GM/852GMV?
6880 if (dev
->pdev
->revision
== 0x1)
6883 pci_bus_read_config_word(dev
->pdev
->bus
,
6884 PCI_DEVFN(0, 3), HPLLCC
, &hpllcc
);
6886 /* Assume that the hardware is in the high speed state. This
6887 * should be the default.
6889 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
6890 case GC_CLOCK_133_200
:
6891 case GC_CLOCK_133_200_2
:
6892 case GC_CLOCK_100_200
:
6894 case GC_CLOCK_166_250
:
6896 case GC_CLOCK_100_133
:
6898 case GC_CLOCK_133_266
:
6899 case GC_CLOCK_133_266_2
:
6900 case GC_CLOCK_166_266
:
6904 /* Shouldn't happen */
6908 static int i830_get_display_clock_speed(struct drm_device
*dev
)
6913 static unsigned int intel_hpll_vco(struct drm_device
*dev
)
6915 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6916 static const unsigned int blb_vco
[8] = {
6923 static const unsigned int pnv_vco
[8] = {
6930 static const unsigned int cl_vco
[8] = {
6939 static const unsigned int elk_vco
[8] = {
6945 static const unsigned int ctg_vco
[8] = {
6953 const unsigned int *vco_table
;
6957 /* FIXME other chipsets? */
6959 vco_table
= ctg_vco
;
6960 else if (IS_G4X(dev
))
6961 vco_table
= elk_vco
;
6962 else if (IS_CRESTLINE(dev
))
6964 else if (IS_PINEVIEW(dev
))
6965 vco_table
= pnv_vco
;
6966 else if (IS_G33(dev
))
6967 vco_table
= blb_vco
;
6971 tmp
= I915_READ(IS_MOBILE(dev
) ? HPLLVCO_MOBILE
: HPLLVCO
);
6973 vco
= vco_table
[tmp
& 0x7];
6975 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp
);
6977 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco
);
6982 static int gm45_get_display_clock_speed(struct drm_device
*dev
)
6984 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
6987 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
6989 cdclk_sel
= (tmp
>> 12) & 0x1;
6995 return cdclk_sel
? 333333 : 222222;
6997 return cdclk_sel
? 320000 : 228571;
6999 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco
, tmp
);
7004 static int i965gm_get_display_clock_speed(struct drm_device
*dev
)
7006 static const uint8_t div_3200
[] = { 16, 10, 8 };
7007 static const uint8_t div_4000
[] = { 20, 12, 10 };
7008 static const uint8_t div_5333
[] = { 24, 16, 14 };
7009 const uint8_t *div_table
;
7010 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7013 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7015 cdclk_sel
= ((tmp
>> 8) & 0x1f) - 1;
7017 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7022 div_table
= div_3200
;
7025 div_table
= div_4000
;
7028 div_table
= div_5333
;
7034 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7037 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco
, tmp
);
7041 static int g33_get_display_clock_speed(struct drm_device
*dev
)
7043 static const uint8_t div_3200
[] = { 12, 10, 8, 7, 5, 16 };
7044 static const uint8_t div_4000
[] = { 14, 12, 10, 8, 6, 20 };
7045 static const uint8_t div_4800
[] = { 20, 14, 12, 10, 8, 24 };
7046 static const uint8_t div_5333
[] = { 20, 16, 12, 12, 8, 28 };
7047 const uint8_t *div_table
;
7048 unsigned int cdclk_sel
, vco
= intel_hpll_vco(dev
);
7051 pci_read_config_word(dev
->pdev
, GCFGC
, &tmp
);
7053 cdclk_sel
= (tmp
>> 4) & 0x7;
7055 if (cdclk_sel
>= ARRAY_SIZE(div_3200
))
7060 div_table
= div_3200
;
7063 div_table
= div_4000
;
7066 div_table
= div_4800
;
7069 div_table
= div_5333
;
7075 return DIV_ROUND_CLOSEST(vco
, div_table
[cdclk_sel
]);
7078 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco
, tmp
);
7083 intel_reduce_m_n_ratio(uint32_t *num
, uint32_t *den
)
7085 while (*num
> DATA_LINK_M_N_MASK
||
7086 *den
> DATA_LINK_M_N_MASK
) {
7092 static void compute_m_n(unsigned int m
, unsigned int n
,
7093 uint32_t *ret_m
, uint32_t *ret_n
)
7095 *ret_n
= min_t(unsigned int, roundup_pow_of_two(n
), DATA_LINK_N_MAX
);
7096 *ret_m
= div_u64((uint64_t) m
* *ret_n
, n
);
7097 intel_reduce_m_n_ratio(ret_m
, ret_n
);
7101 intel_link_compute_m_n(int bits_per_pixel
, int nlanes
,
7102 int pixel_clock
, int link_clock
,
7103 struct intel_link_m_n
*m_n
)
7107 compute_m_n(bits_per_pixel
* pixel_clock
,
7108 link_clock
* nlanes
* 8,
7109 &m_n
->gmch_m
, &m_n
->gmch_n
);
7111 compute_m_n(pixel_clock
, link_clock
,
7112 &m_n
->link_m
, &m_n
->link_n
);
7115 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
7117 if (i915
.panel_use_ssc
>= 0)
7118 return i915
.panel_use_ssc
!= 0;
7119 return dev_priv
->vbt
.lvds_use_ssc
7120 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
7123 static int i9xx_get_refclk(const struct intel_crtc_state
*crtc_state
,
7126 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
7127 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7130 WARN_ON(!crtc_state
->base
.state
);
7132 if (IS_VALLEYVIEW(dev
) || IS_BROXTON(dev
)) {
7134 } else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7135 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
7136 refclk
= dev_priv
->vbt
.lvds_ssc_freq
;
7137 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk
);
7138 } else if (!IS_GEN2(dev
)) {
7147 static uint32_t pnv_dpll_compute_fp(struct dpll
*dpll
)
7149 return (1 << dpll
->n
) << 16 | dpll
->m2
;
7152 static uint32_t i9xx_dpll_compute_fp(struct dpll
*dpll
)
7154 return dpll
->n
<< 16 | dpll
->m1
<< 8 | dpll
->m2
;
7157 static void i9xx_update_pll_dividers(struct intel_crtc
*crtc
,
7158 struct intel_crtc_state
*crtc_state
,
7159 intel_clock_t
*reduced_clock
)
7161 struct drm_device
*dev
= crtc
->base
.dev
;
7164 if (IS_PINEVIEW(dev
)) {
7165 fp
= pnv_dpll_compute_fp(&crtc_state
->dpll
);
7167 fp2
= pnv_dpll_compute_fp(reduced_clock
);
7169 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
7171 fp2
= i9xx_dpll_compute_fp(reduced_clock
);
7174 crtc_state
->dpll_hw_state
.fp0
= fp
;
7176 crtc
->lowfreq_avail
= false;
7177 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7179 crtc_state
->dpll_hw_state
.fp1
= fp2
;
7180 crtc
->lowfreq_avail
= true;
7182 crtc_state
->dpll_hw_state
.fp1
= fp
;
7186 static void vlv_pllb_recal_opamp(struct drm_i915_private
*dev_priv
, enum pipe
7192 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7193 * and set it to a reasonable value instead.
7195 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7196 reg_val
&= 0xffffff00;
7197 reg_val
|= 0x00000030;
7198 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7200 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7201 reg_val
&= 0x8cffffff;
7202 reg_val
= 0x8c000000;
7203 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7205 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW9(1));
7206 reg_val
&= 0xffffff00;
7207 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9(1), reg_val
);
7209 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_REF_DW13
);
7210 reg_val
&= 0x00ffffff;
7211 reg_val
|= 0xb0000000;
7212 vlv_dpio_write(dev_priv
, pipe
, VLV_REF_DW13
, reg_val
);
7215 static void intel_pch_transcoder_set_m_n(struct intel_crtc
*crtc
,
7216 struct intel_link_m_n
*m_n
)
7218 struct drm_device
*dev
= crtc
->base
.dev
;
7219 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7220 int pipe
= crtc
->pipe
;
7222 I915_WRITE(PCH_TRANS_DATA_M1(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7223 I915_WRITE(PCH_TRANS_DATA_N1(pipe
), m_n
->gmch_n
);
7224 I915_WRITE(PCH_TRANS_LINK_M1(pipe
), m_n
->link_m
);
7225 I915_WRITE(PCH_TRANS_LINK_N1(pipe
), m_n
->link_n
);
7228 static void intel_cpu_transcoder_set_m_n(struct intel_crtc
*crtc
,
7229 struct intel_link_m_n
*m_n
,
7230 struct intel_link_m_n
*m2_n2
)
7232 struct drm_device
*dev
= crtc
->base
.dev
;
7233 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7234 int pipe
= crtc
->pipe
;
7235 enum transcoder transcoder
= crtc
->config
->cpu_transcoder
;
7237 if (INTEL_INFO(dev
)->gen
>= 5) {
7238 I915_WRITE(PIPE_DATA_M1(transcoder
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7239 I915_WRITE(PIPE_DATA_N1(transcoder
), m_n
->gmch_n
);
7240 I915_WRITE(PIPE_LINK_M1(transcoder
), m_n
->link_m
);
7241 I915_WRITE(PIPE_LINK_N1(transcoder
), m_n
->link_n
);
7242 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7243 * for gen < 8) and if DRRS is supported (to make sure the
7244 * registers are not unnecessarily accessed).
7246 if (m2_n2
&& (IS_CHERRYVIEW(dev
) || INTEL_INFO(dev
)->gen
< 8) &&
7247 crtc
->config
->has_drrs
) {
7248 I915_WRITE(PIPE_DATA_M2(transcoder
),
7249 TU_SIZE(m2_n2
->tu
) | m2_n2
->gmch_m
);
7250 I915_WRITE(PIPE_DATA_N2(transcoder
), m2_n2
->gmch_n
);
7251 I915_WRITE(PIPE_LINK_M2(transcoder
), m2_n2
->link_m
);
7252 I915_WRITE(PIPE_LINK_N2(transcoder
), m2_n2
->link_n
);
7255 I915_WRITE(PIPE_DATA_M_G4X(pipe
), TU_SIZE(m_n
->tu
) | m_n
->gmch_m
);
7256 I915_WRITE(PIPE_DATA_N_G4X(pipe
), m_n
->gmch_n
);
7257 I915_WRITE(PIPE_LINK_M_G4X(pipe
), m_n
->link_m
);
7258 I915_WRITE(PIPE_LINK_N_G4X(pipe
), m_n
->link_n
);
7262 void intel_dp_set_m_n(struct intel_crtc
*crtc
, enum link_m_n_set m_n
)
7264 struct intel_link_m_n
*dp_m_n
, *dp_m2_n2
= NULL
;
7267 dp_m_n
= &crtc
->config
->dp_m_n
;
7268 dp_m2_n2
= &crtc
->config
->dp_m2_n2
;
7269 } else if (m_n
== M2_N2
) {
7272 * M2_N2 registers are not supported. Hence m2_n2 divider value
7273 * needs to be programmed into M1_N1.
7275 dp_m_n
= &crtc
->config
->dp_m2_n2
;
7277 DRM_ERROR("Unsupported divider value\n");
7281 if (crtc
->config
->has_pch_encoder
)
7282 intel_pch_transcoder_set_m_n(crtc
, &crtc
->config
->dp_m_n
);
7284 intel_cpu_transcoder_set_m_n(crtc
, dp_m_n
, dp_m2_n2
);
7287 static void vlv_compute_dpll(struct intel_crtc
*crtc
,
7288 struct intel_crtc_state
*pipe_config
)
7293 * Enable DPIO clock input. We should never disable the reference
7294 * clock for pipe B, since VGA hotplug / manual detection depends
7297 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REF_CLK_ENABLE_VLV
|
7298 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_REF_CLK_VLV
;
7299 /* We should never disable this, set it here for state tracking */
7300 if (crtc
->pipe
== PIPE_B
)
7301 dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7302 dpll
|= DPLL_VCO_ENABLE
;
7303 pipe_config
->dpll_hw_state
.dpll
= dpll
;
7305 dpll_md
= (pipe_config
->pixel_multiplier
- 1)
7306 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7307 pipe_config
->dpll_hw_state
.dpll_md
= dpll_md
;
7310 static void vlv_prepare_pll(struct intel_crtc
*crtc
,
7311 const struct intel_crtc_state
*pipe_config
)
7313 struct drm_device
*dev
= crtc
->base
.dev
;
7314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7315 int pipe
= crtc
->pipe
;
7317 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
7318 u32 coreclk
, reg_val
;
7320 mutex_lock(&dev_priv
->sb_lock
);
7322 bestn
= pipe_config
->dpll
.n
;
7323 bestm1
= pipe_config
->dpll
.m1
;
7324 bestm2
= pipe_config
->dpll
.m2
;
7325 bestp1
= pipe_config
->dpll
.p1
;
7326 bestp2
= pipe_config
->dpll
.p2
;
7328 /* See eDP HDMI DPIO driver vbios notes doc */
7330 /* PLL B needs special handling */
7332 vlv_pllb_recal_opamp(dev_priv
, pipe
);
7334 /* Set up Tx target for periodic Rcomp update */
7335 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW9_BCAST
, 0x0100000f);
7337 /* Disable target IRef on PLL */
7338 reg_val
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW8(pipe
));
7339 reg_val
&= 0x00ffffff;
7340 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW8(pipe
), reg_val
);
7342 /* Disable fast lock */
7343 vlv_dpio_write(dev_priv
, pipe
, VLV_CMN_DW0
, 0x610);
7345 /* Set idtafcrecal before PLL is enabled */
7346 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
7347 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
7348 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
7349 mdiv
|= (1 << DPIO_K_SHIFT
);
7352 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7353 * but we don't support that).
7354 * Note: don't use the DAC post divider as it seems unstable.
7356 mdiv
|= (DPIO_POST_DIV_HDMIDP
<< DPIO_POST_DIV_SHIFT
);
7357 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7359 mdiv
|= DPIO_ENABLE_CALIBRATION
;
7360 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW3(pipe
), mdiv
);
7362 /* Set HBR and RBR LPF coefficients */
7363 if (pipe_config
->port_clock
== 162000 ||
7364 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
) ||
7365 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
7366 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7369 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW10(pipe
),
7372 if (pipe_config
->has_dp_encoder
) {
7373 /* Use SSC source */
7375 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7378 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7380 } else { /* HDMI or VGA */
7381 /* Use bend source */
7383 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7386 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW5(pipe
),
7390 coreclk
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW7(pipe
));
7391 coreclk
= (coreclk
& 0x0000ff00) | 0x01c00000;
7392 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
7393 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))
7394 coreclk
|= 0x01000000;
7395 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW7(pipe
), coreclk
);
7397 vlv_dpio_write(dev_priv
, pipe
, VLV_PLL_DW11(pipe
), 0x87871000);
7398 mutex_unlock(&dev_priv
->sb_lock
);
7401 static void chv_compute_dpll(struct intel_crtc
*crtc
,
7402 struct intel_crtc_state
*pipe_config
)
7404 pipe_config
->dpll_hw_state
.dpll
= DPLL_SSC_REF_CLK_CHV
|
7405 DPLL_REF_CLK_ENABLE_VLV
| DPLL_VGA_MODE_DIS
|
7407 if (crtc
->pipe
!= PIPE_A
)
7408 pipe_config
->dpll_hw_state
.dpll
|= DPLL_INTEGRATED_CRI_CLK_VLV
;
7410 pipe_config
->dpll_hw_state
.dpll_md
=
7411 (pipe_config
->pixel_multiplier
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7414 static void chv_prepare_pll(struct intel_crtc
*crtc
,
7415 const struct intel_crtc_state
*pipe_config
)
7417 struct drm_device
*dev
= crtc
->base
.dev
;
7418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7419 int pipe
= crtc
->pipe
;
7420 int dpll_reg
= DPLL(crtc
->pipe
);
7421 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
7422 u32 loopfilter
, tribuf_calcntr
;
7423 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
, bestm2_frac
;
7427 bestn
= pipe_config
->dpll
.n
;
7428 bestm2_frac
= pipe_config
->dpll
.m2
& 0x3fffff;
7429 bestm1
= pipe_config
->dpll
.m1
;
7430 bestm2
= pipe_config
->dpll
.m2
>> 22;
7431 bestp1
= pipe_config
->dpll
.p1
;
7432 bestp2
= pipe_config
->dpll
.p2
;
7433 vco
= pipe_config
->dpll
.vco
;
7438 * Enable Refclk and SSC
7440 I915_WRITE(dpll_reg
,
7441 pipe_config
->dpll_hw_state
.dpll
& ~DPLL_VCO_ENABLE
);
7443 mutex_lock(&dev_priv
->sb_lock
);
7445 /* p1 and p2 divider */
7446 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW13(port
),
7447 5 << DPIO_CHV_S1_DIV_SHIFT
|
7448 bestp1
<< DPIO_CHV_P1_DIV_SHIFT
|
7449 bestp2
<< DPIO_CHV_P2_DIV_SHIFT
|
7450 1 << DPIO_CHV_K_DIV_SHIFT
);
7452 /* Feedback post-divider - m2 */
7453 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW0(port
), bestm2
);
7455 /* Feedback refclk divider - n and m1 */
7456 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW1(port
),
7457 DPIO_CHV_M1_DIV_BY_2
|
7458 1 << DPIO_CHV_N_DIV_SHIFT
);
7460 /* M2 fraction division */
7461 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW2(port
), bestm2_frac
);
7463 /* M2 fraction division enable */
7464 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
7465 dpio_val
&= ~(DPIO_CHV_FEEDFWD_GAIN_MASK
| DPIO_CHV_FRAC_DIV_EN
);
7466 dpio_val
|= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT
);
7468 dpio_val
|= DPIO_CHV_FRAC_DIV_EN
;
7469 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW3(port
), dpio_val
);
7471 /* Program digital lock detect threshold */
7472 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW9(port
));
7473 dpio_val
&= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK
|
7474 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
);
7475 dpio_val
|= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT
);
7477 dpio_val
|= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE
;
7478 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW9(port
), dpio_val
);
7481 if (vco
== 5400000) {
7482 loopfilter
|= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT
);
7483 loopfilter
|= (0x8 << DPIO_CHV_INT_COEFF_SHIFT
);
7484 loopfilter
|= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7485 tribuf_calcntr
= 0x9;
7486 } else if (vco
<= 6200000) {
7487 loopfilter
|= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT
);
7488 loopfilter
|= (0xB << DPIO_CHV_INT_COEFF_SHIFT
);
7489 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7490 tribuf_calcntr
= 0x9;
7491 } else if (vco
<= 6480000) {
7492 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7493 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7494 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7495 tribuf_calcntr
= 0x8;
7497 /* Not supported. Apply the same limits as in the max case */
7498 loopfilter
|= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT
);
7499 loopfilter
|= (0x9 << DPIO_CHV_INT_COEFF_SHIFT
);
7500 loopfilter
|= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT
);
7503 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW6(port
), loopfilter
);
7505 dpio_val
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW8(port
));
7506 dpio_val
&= ~DPIO_CHV_TDC_TARGET_CNT_MASK
;
7507 dpio_val
|= (tribuf_calcntr
<< DPIO_CHV_TDC_TARGET_CNT_SHIFT
);
7508 vlv_dpio_write(dev_priv
, pipe
, CHV_PLL_DW8(port
), dpio_val
);
7511 vlv_dpio_write(dev_priv
, pipe
, CHV_CMN_DW14(port
),
7512 vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW14(port
)) |
7515 mutex_unlock(&dev_priv
->sb_lock
);
7519 * vlv_force_pll_on - forcibly enable just the PLL
7520 * @dev_priv: i915 private structure
7521 * @pipe: pipe PLL to enable
7522 * @dpll: PLL configuration
7524 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7525 * in cases where we need the PLL enabled even when @pipe is not going to
7528 void vlv_force_pll_on(struct drm_device
*dev
, enum pipe pipe
,
7529 const struct dpll
*dpll
)
7531 struct intel_crtc
*crtc
=
7532 to_intel_crtc(intel_get_crtc_for_pipe(dev
, pipe
));
7533 struct intel_crtc_state pipe_config
= {
7534 .base
.crtc
= &crtc
->base
,
7535 .pixel_multiplier
= 1,
7539 if (IS_CHERRYVIEW(dev
)) {
7540 chv_compute_dpll(crtc
, &pipe_config
);
7541 chv_prepare_pll(crtc
, &pipe_config
);
7542 chv_enable_pll(crtc
, &pipe_config
);
7544 vlv_compute_dpll(crtc
, &pipe_config
);
7545 vlv_prepare_pll(crtc
, &pipe_config
);
7546 vlv_enable_pll(crtc
, &pipe_config
);
7551 * vlv_force_pll_off - forcibly disable just the PLL
7552 * @dev_priv: i915 private structure
7553 * @pipe: pipe PLL to disable
7555 * Disable the PLL for @pipe. To be used in cases where we need
7556 * the PLL enabled even when @pipe is not going to be enabled.
7558 void vlv_force_pll_off(struct drm_device
*dev
, enum pipe pipe
)
7560 if (IS_CHERRYVIEW(dev
))
7561 chv_disable_pll(to_i915(dev
), pipe
);
7563 vlv_disable_pll(to_i915(dev
), pipe
);
7566 static void i9xx_compute_dpll(struct intel_crtc
*crtc
,
7567 struct intel_crtc_state
*crtc_state
,
7568 intel_clock_t
*reduced_clock
,
7571 struct drm_device
*dev
= crtc
->base
.dev
;
7572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7575 struct dpll
*clock
= &crtc_state
->dpll
;
7577 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7579 is_sdvo
= intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_SDVO
) ||
7580 intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_HDMI
);
7582 dpll
= DPLL_VGA_MODE_DIS
;
7584 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
))
7585 dpll
|= DPLLB_MODE_LVDS
;
7587 dpll
|= DPLLB_MODE_DAC_SERIAL
;
7589 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
7590 dpll
|= (crtc_state
->pixel_multiplier
- 1)
7591 << SDVO_MULTIPLIER_SHIFT_HIRES
;
7595 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7597 if (crtc_state
->has_dp_encoder
)
7598 dpll
|= DPLL_SDVO_HIGH_SPEED
;
7600 /* compute bitmask from p1 value */
7601 if (IS_PINEVIEW(dev
))
7602 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
7604 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7605 if (IS_G4X(dev
) && reduced_clock
)
7606 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
7608 switch (clock
->p2
) {
7610 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
7613 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
7616 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
7619 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
7622 if (INTEL_INFO(dev
)->gen
>= 4)
7623 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
7625 if (crtc_state
->sdvo_tv_clock
)
7626 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
7627 else if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7628 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7629 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7631 dpll
|= PLL_REF_INPUT_DREFCLK
;
7633 dpll
|= DPLL_VCO_ENABLE
;
7634 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7636 if (INTEL_INFO(dev
)->gen
>= 4) {
7637 u32 dpll_md
= (crtc_state
->pixel_multiplier
- 1)
7638 << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
7639 crtc_state
->dpll_hw_state
.dpll_md
= dpll_md
;
7643 static void i8xx_compute_dpll(struct intel_crtc
*crtc
,
7644 struct intel_crtc_state
*crtc_state
,
7645 intel_clock_t
*reduced_clock
,
7648 struct drm_device
*dev
= crtc
->base
.dev
;
7649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7651 struct dpll
*clock
= &crtc_state
->dpll
;
7653 i9xx_update_pll_dividers(crtc
, crtc_state
, reduced_clock
);
7655 dpll
= DPLL_VGA_MODE_DIS
;
7657 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
)) {
7658 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7661 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
7663 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
7665 dpll
|= PLL_P2_DIVIDE_BY_4
;
7668 if (!IS_I830(dev
) && intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_DVO
))
7669 dpll
|= DPLL_DVO_2X_MODE
;
7671 if (intel_pipe_will_have_type(crtc_state
, INTEL_OUTPUT_LVDS
) &&
7672 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
7673 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
7675 dpll
|= PLL_REF_INPUT_DREFCLK
;
7677 dpll
|= DPLL_VCO_ENABLE
;
7678 crtc_state
->dpll_hw_state
.dpll
= dpll
;
7681 static void intel_set_pipe_timings(struct intel_crtc
*intel_crtc
)
7683 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7684 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7685 enum pipe pipe
= intel_crtc
->pipe
;
7686 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
7687 const struct drm_display_mode
*adjusted_mode
= &intel_crtc
->config
->base
.adjusted_mode
;
7688 uint32_t crtc_vtotal
, crtc_vblank_end
;
7691 /* We need to be careful not to changed the adjusted mode, for otherwise
7692 * the hw state checker will get angry at the mismatch. */
7693 crtc_vtotal
= adjusted_mode
->crtc_vtotal
;
7694 crtc_vblank_end
= adjusted_mode
->crtc_vblank_end
;
7696 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
7697 /* the chip adds 2 halflines automatically */
7699 crtc_vblank_end
-= 1;
7701 if (intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7702 vsyncshift
= (adjusted_mode
->crtc_htotal
- 1) / 2;
7704 vsyncshift
= adjusted_mode
->crtc_hsync_start
-
7705 adjusted_mode
->crtc_htotal
/ 2;
7707 vsyncshift
+= adjusted_mode
->crtc_htotal
;
7710 if (INTEL_INFO(dev
)->gen
> 3)
7711 I915_WRITE(VSYNCSHIFT(cpu_transcoder
), vsyncshift
);
7713 I915_WRITE(HTOTAL(cpu_transcoder
),
7714 (adjusted_mode
->crtc_hdisplay
- 1) |
7715 ((adjusted_mode
->crtc_htotal
- 1) << 16));
7716 I915_WRITE(HBLANK(cpu_transcoder
),
7717 (adjusted_mode
->crtc_hblank_start
- 1) |
7718 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
7719 I915_WRITE(HSYNC(cpu_transcoder
),
7720 (adjusted_mode
->crtc_hsync_start
- 1) |
7721 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
7723 I915_WRITE(VTOTAL(cpu_transcoder
),
7724 (adjusted_mode
->crtc_vdisplay
- 1) |
7725 ((crtc_vtotal
- 1) << 16));
7726 I915_WRITE(VBLANK(cpu_transcoder
),
7727 (adjusted_mode
->crtc_vblank_start
- 1) |
7728 ((crtc_vblank_end
- 1) << 16));
7729 I915_WRITE(VSYNC(cpu_transcoder
),
7730 (adjusted_mode
->crtc_vsync_start
- 1) |
7731 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
7733 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7734 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7735 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7737 if (IS_HASWELL(dev
) && cpu_transcoder
== TRANSCODER_EDP
&&
7738 (pipe
== PIPE_B
|| pipe
== PIPE_C
))
7739 I915_WRITE(VTOTAL(pipe
), I915_READ(VTOTAL(cpu_transcoder
)));
7741 /* pipesrc controls the size that is scaled from, which should
7742 * always be the user's requested size.
7744 I915_WRITE(PIPESRC(pipe
),
7745 ((intel_crtc
->config
->pipe_src_w
- 1) << 16) |
7746 (intel_crtc
->config
->pipe_src_h
- 1));
7749 static void intel_get_pipe_timings(struct intel_crtc
*crtc
,
7750 struct intel_crtc_state
*pipe_config
)
7752 struct drm_device
*dev
= crtc
->base
.dev
;
7753 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7754 enum transcoder cpu_transcoder
= pipe_config
->cpu_transcoder
;
7757 tmp
= I915_READ(HTOTAL(cpu_transcoder
));
7758 pipe_config
->base
.adjusted_mode
.crtc_hdisplay
= (tmp
& 0xffff) + 1;
7759 pipe_config
->base
.adjusted_mode
.crtc_htotal
= ((tmp
>> 16) & 0xffff) + 1;
7760 tmp
= I915_READ(HBLANK(cpu_transcoder
));
7761 pipe_config
->base
.adjusted_mode
.crtc_hblank_start
= (tmp
& 0xffff) + 1;
7762 pipe_config
->base
.adjusted_mode
.crtc_hblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7763 tmp
= I915_READ(HSYNC(cpu_transcoder
));
7764 pipe_config
->base
.adjusted_mode
.crtc_hsync_start
= (tmp
& 0xffff) + 1;
7765 pipe_config
->base
.adjusted_mode
.crtc_hsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7767 tmp
= I915_READ(VTOTAL(cpu_transcoder
));
7768 pipe_config
->base
.adjusted_mode
.crtc_vdisplay
= (tmp
& 0xffff) + 1;
7769 pipe_config
->base
.adjusted_mode
.crtc_vtotal
= ((tmp
>> 16) & 0xffff) + 1;
7770 tmp
= I915_READ(VBLANK(cpu_transcoder
));
7771 pipe_config
->base
.adjusted_mode
.crtc_vblank_start
= (tmp
& 0xffff) + 1;
7772 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
= ((tmp
>> 16) & 0xffff) + 1;
7773 tmp
= I915_READ(VSYNC(cpu_transcoder
));
7774 pipe_config
->base
.adjusted_mode
.crtc_vsync_start
= (tmp
& 0xffff) + 1;
7775 pipe_config
->base
.adjusted_mode
.crtc_vsync_end
= ((tmp
>> 16) & 0xffff) + 1;
7777 if (I915_READ(PIPECONF(cpu_transcoder
)) & PIPECONF_INTERLACE_MASK
) {
7778 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_INTERLACE
;
7779 pipe_config
->base
.adjusted_mode
.crtc_vtotal
+= 1;
7780 pipe_config
->base
.adjusted_mode
.crtc_vblank_end
+= 1;
7783 tmp
= I915_READ(PIPESRC(crtc
->pipe
));
7784 pipe_config
->pipe_src_h
= (tmp
& 0xffff) + 1;
7785 pipe_config
->pipe_src_w
= ((tmp
>> 16) & 0xffff) + 1;
7787 pipe_config
->base
.mode
.vdisplay
= pipe_config
->pipe_src_h
;
7788 pipe_config
->base
.mode
.hdisplay
= pipe_config
->pipe_src_w
;
7791 void intel_mode_from_pipe_config(struct drm_display_mode
*mode
,
7792 struct intel_crtc_state
*pipe_config
)
7794 mode
->hdisplay
= pipe_config
->base
.adjusted_mode
.crtc_hdisplay
;
7795 mode
->htotal
= pipe_config
->base
.adjusted_mode
.crtc_htotal
;
7796 mode
->hsync_start
= pipe_config
->base
.adjusted_mode
.crtc_hsync_start
;
7797 mode
->hsync_end
= pipe_config
->base
.adjusted_mode
.crtc_hsync_end
;
7799 mode
->vdisplay
= pipe_config
->base
.adjusted_mode
.crtc_vdisplay
;
7800 mode
->vtotal
= pipe_config
->base
.adjusted_mode
.crtc_vtotal
;
7801 mode
->vsync_start
= pipe_config
->base
.adjusted_mode
.crtc_vsync_start
;
7802 mode
->vsync_end
= pipe_config
->base
.adjusted_mode
.crtc_vsync_end
;
7804 mode
->flags
= pipe_config
->base
.adjusted_mode
.flags
;
7805 mode
->type
= DRM_MODE_TYPE_DRIVER
;
7807 mode
->clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
;
7808 mode
->flags
|= pipe_config
->base
.adjusted_mode
.flags
;
7810 mode
->hsync
= drm_mode_hsync(mode
);
7811 mode
->vrefresh
= drm_mode_vrefresh(mode
);
7812 drm_mode_set_name(mode
);
7815 static void i9xx_set_pipeconf(struct intel_crtc
*intel_crtc
)
7817 struct drm_device
*dev
= intel_crtc
->base
.dev
;
7818 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7823 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
7824 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
7825 pipeconf
|= I915_READ(PIPECONF(intel_crtc
->pipe
)) & PIPECONF_ENABLE
;
7827 if (intel_crtc
->config
->double_wide
)
7828 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
7830 /* only g4x and later have fancy bpc/dither controls */
7831 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
7832 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7833 if (intel_crtc
->config
->dither
&& intel_crtc
->config
->pipe_bpp
!= 30)
7834 pipeconf
|= PIPECONF_DITHER_EN
|
7835 PIPECONF_DITHER_TYPE_SP
;
7837 switch (intel_crtc
->config
->pipe_bpp
) {
7839 pipeconf
|= PIPECONF_6BPC
;
7842 pipeconf
|= PIPECONF_8BPC
;
7845 pipeconf
|= PIPECONF_10BPC
;
7848 /* Case prevented by intel_choose_pipe_bpp_dither. */
7853 if (HAS_PIPE_CXSR(dev
)) {
7854 if (intel_crtc
->lowfreq_avail
) {
7855 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7856 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
7858 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7862 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
) {
7863 if (INTEL_INFO(dev
)->gen
< 4 ||
7864 intel_pipe_has_type(intel_crtc
, INTEL_OUTPUT_SDVO
))
7865 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
7867 pipeconf
|= PIPECONF_INTERLACE_W_SYNC_SHIFT
;
7869 pipeconf
|= PIPECONF_PROGRESSIVE
;
7871 if (IS_VALLEYVIEW(dev
) && intel_crtc
->config
->limited_color_range
)
7872 pipeconf
|= PIPECONF_COLOR_RANGE_SELECT
;
7874 I915_WRITE(PIPECONF(intel_crtc
->pipe
), pipeconf
);
7875 POSTING_READ(PIPECONF(intel_crtc
->pipe
));
7878 static int i9xx_crtc_compute_clock(struct intel_crtc
*crtc
,
7879 struct intel_crtc_state
*crtc_state
)
7881 struct drm_device
*dev
= crtc
->base
.dev
;
7882 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7883 int refclk
, num_connectors
= 0;
7884 intel_clock_t clock
;
7886 bool is_dsi
= false;
7887 struct intel_encoder
*encoder
;
7888 const intel_limit_t
*limit
;
7889 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
7890 struct drm_connector
*connector
;
7891 struct drm_connector_state
*connector_state
;
7894 memset(&crtc_state
->dpll_hw_state
, 0,
7895 sizeof(crtc_state
->dpll_hw_state
));
7897 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
7898 if (connector_state
->crtc
!= &crtc
->base
)
7901 encoder
= to_intel_encoder(connector_state
->best_encoder
);
7903 switch (encoder
->type
) {
7904 case INTEL_OUTPUT_DSI
:
7917 if (!crtc_state
->clock_set
) {
7918 refclk
= i9xx_get_refclk(crtc_state
, num_connectors
);
7921 * Returns a set of divisors for the desired target clock with
7922 * the given refclk, or FALSE. The returned values represent
7923 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7926 limit
= intel_limit(crtc_state
, refclk
);
7927 ok
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
7928 crtc_state
->port_clock
,
7929 refclk
, NULL
, &clock
);
7931 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7935 /* Compat-code for transition, will disappear. */
7936 crtc_state
->dpll
.n
= clock
.n
;
7937 crtc_state
->dpll
.m1
= clock
.m1
;
7938 crtc_state
->dpll
.m2
= clock
.m2
;
7939 crtc_state
->dpll
.p1
= clock
.p1
;
7940 crtc_state
->dpll
.p2
= clock
.p2
;
7944 i8xx_compute_dpll(crtc
, crtc_state
, NULL
,
7946 } else if (IS_CHERRYVIEW(dev
)) {
7947 chv_compute_dpll(crtc
, crtc_state
);
7948 } else if (IS_VALLEYVIEW(dev
)) {
7949 vlv_compute_dpll(crtc
, crtc_state
);
7951 i9xx_compute_dpll(crtc
, crtc_state
, NULL
,
7958 static void i9xx_get_pfit_config(struct intel_crtc
*crtc
,
7959 struct intel_crtc_state
*pipe_config
)
7961 struct drm_device
*dev
= crtc
->base
.dev
;
7962 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7965 if (INTEL_INFO(dev
)->gen
<= 3 && (IS_I830(dev
) || !IS_MOBILE(dev
)))
7968 tmp
= I915_READ(PFIT_CONTROL
);
7969 if (!(tmp
& PFIT_ENABLE
))
7972 /* Check whether the pfit is attached to our pipe. */
7973 if (INTEL_INFO(dev
)->gen
< 4) {
7974 if (crtc
->pipe
!= PIPE_B
)
7977 if ((tmp
& PFIT_PIPE_MASK
) != (crtc
->pipe
<< PFIT_PIPE_SHIFT
))
7981 pipe_config
->gmch_pfit
.control
= tmp
;
7982 pipe_config
->gmch_pfit
.pgm_ratios
= I915_READ(PFIT_PGM_RATIOS
);
7983 if (INTEL_INFO(dev
)->gen
< 5)
7984 pipe_config
->gmch_pfit
.lvds_border_bits
=
7985 I915_READ(LVDS
) & LVDS_BORDER_ENABLE
;
7988 static void vlv_crtc_clock_get(struct intel_crtc
*crtc
,
7989 struct intel_crtc_state
*pipe_config
)
7991 struct drm_device
*dev
= crtc
->base
.dev
;
7992 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7993 int pipe
= pipe_config
->cpu_transcoder
;
7994 intel_clock_t clock
;
7996 int refclk
= 100000;
7998 /* In case of MIPI DPLL will not even be used */
7999 if (!(pipe_config
->dpll_hw_state
.dpll
& DPLL_VCO_ENABLE
))
8002 mutex_lock(&dev_priv
->sb_lock
);
8003 mdiv
= vlv_dpio_read(dev_priv
, pipe
, VLV_PLL_DW3(pipe
));
8004 mutex_unlock(&dev_priv
->sb_lock
);
8006 clock
.m1
= (mdiv
>> DPIO_M1DIV_SHIFT
) & 7;
8007 clock
.m2
= mdiv
& DPIO_M2DIV_MASK
;
8008 clock
.n
= (mdiv
>> DPIO_N_SHIFT
) & 0xf;
8009 clock
.p1
= (mdiv
>> DPIO_P1_SHIFT
) & 7;
8010 clock
.p2
= (mdiv
>> DPIO_P2_SHIFT
) & 0x1f;
8012 pipe_config
->port_clock
= vlv_calc_dpll_params(refclk
, &clock
);
8016 i9xx_get_initial_plane_config(struct intel_crtc
*crtc
,
8017 struct intel_initial_plane_config
*plane_config
)
8019 struct drm_device
*dev
= crtc
->base
.dev
;
8020 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8021 u32 val
, base
, offset
;
8022 int pipe
= crtc
->pipe
, plane
= crtc
->plane
;
8023 int fourcc
, pixel_format
;
8024 unsigned int aligned_height
;
8025 struct drm_framebuffer
*fb
;
8026 struct intel_framebuffer
*intel_fb
;
8028 val
= I915_READ(DSPCNTR(plane
));
8029 if (!(val
& DISPLAY_PLANE_ENABLE
))
8032 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
8034 DRM_DEBUG_KMS("failed to alloc fb\n");
8038 fb
= &intel_fb
->base
;
8040 if (INTEL_INFO(dev
)->gen
>= 4) {
8041 if (val
& DISPPLANE_TILED
) {
8042 plane_config
->tiling
= I915_TILING_X
;
8043 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
8047 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
8048 fourcc
= i9xx_format_to_fourcc(pixel_format
);
8049 fb
->pixel_format
= fourcc
;
8050 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
8052 if (INTEL_INFO(dev
)->gen
>= 4) {
8053 if (plane_config
->tiling
)
8054 offset
= I915_READ(DSPTILEOFF(plane
));
8056 offset
= I915_READ(DSPLINOFF(plane
));
8057 base
= I915_READ(DSPSURF(plane
)) & 0xfffff000;
8059 base
= I915_READ(DSPADDR(plane
));
8061 plane_config
->base
= base
;
8063 val
= I915_READ(PIPESRC(pipe
));
8064 fb
->width
= ((val
>> 16) & 0xfff) + 1;
8065 fb
->height
= ((val
>> 0) & 0xfff) + 1;
8067 val
= I915_READ(DSPSTRIDE(pipe
));
8068 fb
->pitches
[0] = val
& 0xffffffc0;
8070 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
8074 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
8076 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8077 pipe_name(pipe
), plane
, fb
->width
, fb
->height
,
8078 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
8079 plane_config
->size
);
8081 plane_config
->fb
= intel_fb
;
8084 static void chv_crtc_clock_get(struct intel_crtc
*crtc
,
8085 struct intel_crtc_state
*pipe_config
)
8087 struct drm_device
*dev
= crtc
->base
.dev
;
8088 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8089 int pipe
= pipe_config
->cpu_transcoder
;
8090 enum dpio_channel port
= vlv_pipe_to_channel(pipe
);
8091 intel_clock_t clock
;
8092 u32 cmn_dw13
, pll_dw0
, pll_dw1
, pll_dw2
, pll_dw3
;
8093 int refclk
= 100000;
8095 mutex_lock(&dev_priv
->sb_lock
);
8096 cmn_dw13
= vlv_dpio_read(dev_priv
, pipe
, CHV_CMN_DW13(port
));
8097 pll_dw0
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW0(port
));
8098 pll_dw1
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW1(port
));
8099 pll_dw2
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW2(port
));
8100 pll_dw3
= vlv_dpio_read(dev_priv
, pipe
, CHV_PLL_DW3(port
));
8101 mutex_unlock(&dev_priv
->sb_lock
);
8103 clock
.m1
= (pll_dw1
& 0x7) == DPIO_CHV_M1_DIV_BY_2
? 2 : 0;
8104 clock
.m2
= (pll_dw0
& 0xff) << 22;
8105 if (pll_dw3
& DPIO_CHV_FRAC_DIV_EN
)
8106 clock
.m2
|= pll_dw2
& 0x3fffff;
8107 clock
.n
= (pll_dw1
>> DPIO_CHV_N_DIV_SHIFT
) & 0xf;
8108 clock
.p1
= (cmn_dw13
>> DPIO_CHV_P1_DIV_SHIFT
) & 0x7;
8109 clock
.p2
= (cmn_dw13
>> DPIO_CHV_P2_DIV_SHIFT
) & 0x1f;
8111 pipe_config
->port_clock
= chv_calc_dpll_params(refclk
, &clock
);
8114 static bool i9xx_get_pipe_config(struct intel_crtc
*crtc
,
8115 struct intel_crtc_state
*pipe_config
)
8117 struct drm_device
*dev
= crtc
->base
.dev
;
8118 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8121 if (!intel_display_power_is_enabled(dev_priv
,
8122 POWER_DOMAIN_PIPE(crtc
->pipe
)))
8125 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
8126 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
8128 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
8129 if (!(tmp
& PIPECONF_ENABLE
))
8132 if (IS_G4X(dev
) || IS_VALLEYVIEW(dev
)) {
8133 switch (tmp
& PIPECONF_BPC_MASK
) {
8135 pipe_config
->pipe_bpp
= 18;
8138 pipe_config
->pipe_bpp
= 24;
8140 case PIPECONF_10BPC
:
8141 pipe_config
->pipe_bpp
= 30;
8148 if (IS_VALLEYVIEW(dev
) && (tmp
& PIPECONF_COLOR_RANGE_SELECT
))
8149 pipe_config
->limited_color_range
= true;
8151 if (INTEL_INFO(dev
)->gen
< 4)
8152 pipe_config
->double_wide
= tmp
& PIPECONF_DOUBLE_WIDE
;
8154 intel_get_pipe_timings(crtc
, pipe_config
);
8156 i9xx_get_pfit_config(crtc
, pipe_config
);
8158 if (INTEL_INFO(dev
)->gen
>= 4) {
8159 tmp
= I915_READ(DPLL_MD(crtc
->pipe
));
8160 pipe_config
->pixel_multiplier
=
8161 ((tmp
& DPLL_MD_UDI_MULTIPLIER_MASK
)
8162 >> DPLL_MD_UDI_MULTIPLIER_SHIFT
) + 1;
8163 pipe_config
->dpll_hw_state
.dpll_md
= tmp
;
8164 } else if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
)) {
8165 tmp
= I915_READ(DPLL(crtc
->pipe
));
8166 pipe_config
->pixel_multiplier
=
8167 ((tmp
& SDVO_MULTIPLIER_MASK
)
8168 >> SDVO_MULTIPLIER_SHIFT_HIRES
) + 1;
8170 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8171 * port and will be fixed up in the encoder->get_config
8173 pipe_config
->pixel_multiplier
= 1;
8175 pipe_config
->dpll_hw_state
.dpll
= I915_READ(DPLL(crtc
->pipe
));
8176 if (!IS_VALLEYVIEW(dev
)) {
8178 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8179 * on 830. Filter it out here so that we don't
8180 * report errors due to that.
8183 pipe_config
->dpll_hw_state
.dpll
&= ~DPLL_DVO_2X_MODE
;
8185 pipe_config
->dpll_hw_state
.fp0
= I915_READ(FP0(crtc
->pipe
));
8186 pipe_config
->dpll_hw_state
.fp1
= I915_READ(FP1(crtc
->pipe
));
8188 /* Mask out read-only status bits. */
8189 pipe_config
->dpll_hw_state
.dpll
&= ~(DPLL_LOCK_VLV
|
8190 DPLL_PORTC_READY_MASK
|
8191 DPLL_PORTB_READY_MASK
);
8194 if (IS_CHERRYVIEW(dev
))
8195 chv_crtc_clock_get(crtc
, pipe_config
);
8196 else if (IS_VALLEYVIEW(dev
))
8197 vlv_crtc_clock_get(crtc
, pipe_config
);
8199 i9xx_crtc_clock_get(crtc
, pipe_config
);
8202 * Normally the dotclock is filled in by the encoder .get_config()
8203 * but in case the pipe is enabled w/o any ports we need a sane
8206 pipe_config
->base
.adjusted_mode
.crtc_clock
=
8207 pipe_config
->port_clock
/ pipe_config
->pixel_multiplier
;
8212 static void ironlake_init_pch_refclk(struct drm_device
*dev
)
8214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8215 struct intel_encoder
*encoder
;
8217 bool has_lvds
= false;
8218 bool has_cpu_edp
= false;
8219 bool has_panel
= false;
8220 bool has_ck505
= false;
8221 bool can_ssc
= false;
8223 /* We need to take the global config into account */
8224 for_each_intel_encoder(dev
, encoder
) {
8225 switch (encoder
->type
) {
8226 case INTEL_OUTPUT_LVDS
:
8230 case INTEL_OUTPUT_EDP
:
8232 if (enc_to_dig_port(&encoder
->base
)->port
== PORT_A
)
8240 if (HAS_PCH_IBX(dev
)) {
8241 has_ck505
= dev_priv
->vbt
.display_clock_mode
;
8242 can_ssc
= has_ck505
;
8248 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8249 has_panel
, has_lvds
, has_ck505
);
8251 /* Ironlake: try to setup display ref clock before DPLL
8252 * enabling. This is only under driver's control after
8253 * PCH B stepping, previous chipset stepping should be
8254 * ignoring this setting.
8256 val
= I915_READ(PCH_DREF_CONTROL
);
8258 /* As we must carefully and slowly disable/enable each source in turn,
8259 * compute the final state we want first and check if we need to
8260 * make any changes at all.
8263 final
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8265 final
|= DREF_NONSPREAD_CK505_ENABLE
;
8267 final
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8269 final
&= ~DREF_SSC_SOURCE_MASK
;
8270 final
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8271 final
&= ~DREF_SSC1_ENABLE
;
8274 final
|= DREF_SSC_SOURCE_ENABLE
;
8276 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8277 final
|= DREF_SSC1_ENABLE
;
8280 if (intel_panel_use_ssc(dev_priv
) && can_ssc
)
8281 final
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8283 final
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8285 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8287 final
|= DREF_SSC_SOURCE_DISABLE
;
8288 final
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8294 /* Always enable nonspread source */
8295 val
&= ~DREF_NONSPREAD_SOURCE_MASK
;
8298 val
|= DREF_NONSPREAD_CK505_ENABLE
;
8300 val
|= DREF_NONSPREAD_SOURCE_ENABLE
;
8303 val
&= ~DREF_SSC_SOURCE_MASK
;
8304 val
|= DREF_SSC_SOURCE_ENABLE
;
8306 /* SSC must be turned on before enabling the CPU output */
8307 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8308 DRM_DEBUG_KMS("Using SSC on panel\n");
8309 val
|= DREF_SSC1_ENABLE
;
8311 val
&= ~DREF_SSC1_ENABLE
;
8313 /* Get SSC going before enabling the outputs */
8314 I915_WRITE(PCH_DREF_CONTROL
, val
);
8315 POSTING_READ(PCH_DREF_CONTROL
);
8318 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8320 /* Enable CPU source on CPU attached eDP */
8322 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
8323 DRM_DEBUG_KMS("Using SSC on eDP\n");
8324 val
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
8326 val
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
8328 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8330 I915_WRITE(PCH_DREF_CONTROL
, val
);
8331 POSTING_READ(PCH_DREF_CONTROL
);
8334 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8336 val
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
8338 /* Turn off CPU output */
8339 val
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
8341 I915_WRITE(PCH_DREF_CONTROL
, val
);
8342 POSTING_READ(PCH_DREF_CONTROL
);
8345 /* Turn off the SSC source */
8346 val
&= ~DREF_SSC_SOURCE_MASK
;
8347 val
|= DREF_SSC_SOURCE_DISABLE
;
8350 val
&= ~DREF_SSC1_ENABLE
;
8352 I915_WRITE(PCH_DREF_CONTROL
, val
);
8353 POSTING_READ(PCH_DREF_CONTROL
);
8357 BUG_ON(val
!= final
);
8360 static void lpt_reset_fdi_mphy(struct drm_i915_private
*dev_priv
)
8364 tmp
= I915_READ(SOUTH_CHICKEN2
);
8365 tmp
|= FDI_MPHY_IOSFSB_RESET_CTL
;
8366 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8368 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2
) &
8369 FDI_MPHY_IOSFSB_RESET_STATUS
, 100))
8370 DRM_ERROR("FDI mPHY reset assert timeout\n");
8372 tmp
= I915_READ(SOUTH_CHICKEN2
);
8373 tmp
&= ~FDI_MPHY_IOSFSB_RESET_CTL
;
8374 I915_WRITE(SOUTH_CHICKEN2
, tmp
);
8376 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2
) &
8377 FDI_MPHY_IOSFSB_RESET_STATUS
) == 0, 100))
8378 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8381 /* WaMPhyProgramming:hsw */
8382 static void lpt_program_fdi_mphy(struct drm_i915_private
*dev_priv
)
8386 tmp
= intel_sbi_read(dev_priv
, 0x8008, SBI_MPHY
);
8387 tmp
&= ~(0xFF << 24);
8388 tmp
|= (0x12 << 24);
8389 intel_sbi_write(dev_priv
, 0x8008, tmp
, SBI_MPHY
);
8391 tmp
= intel_sbi_read(dev_priv
, 0x2008, SBI_MPHY
);
8393 intel_sbi_write(dev_priv
, 0x2008, tmp
, SBI_MPHY
);
8395 tmp
= intel_sbi_read(dev_priv
, 0x2108, SBI_MPHY
);
8397 intel_sbi_write(dev_priv
, 0x2108, tmp
, SBI_MPHY
);
8399 tmp
= intel_sbi_read(dev_priv
, 0x206C, SBI_MPHY
);
8400 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8401 intel_sbi_write(dev_priv
, 0x206C, tmp
, SBI_MPHY
);
8403 tmp
= intel_sbi_read(dev_priv
, 0x216C, SBI_MPHY
);
8404 tmp
|= (1 << 24) | (1 << 21) | (1 << 18);
8405 intel_sbi_write(dev_priv
, 0x216C, tmp
, SBI_MPHY
);
8407 tmp
= intel_sbi_read(dev_priv
, 0x2080, SBI_MPHY
);
8410 intel_sbi_write(dev_priv
, 0x2080, tmp
, SBI_MPHY
);
8412 tmp
= intel_sbi_read(dev_priv
, 0x2180, SBI_MPHY
);
8415 intel_sbi_write(dev_priv
, 0x2180, tmp
, SBI_MPHY
);
8417 tmp
= intel_sbi_read(dev_priv
, 0x208C, SBI_MPHY
);
8420 intel_sbi_write(dev_priv
, 0x208C, tmp
, SBI_MPHY
);
8422 tmp
= intel_sbi_read(dev_priv
, 0x218C, SBI_MPHY
);
8425 intel_sbi_write(dev_priv
, 0x218C, tmp
, SBI_MPHY
);
8427 tmp
= intel_sbi_read(dev_priv
, 0x2098, SBI_MPHY
);
8428 tmp
&= ~(0xFF << 16);
8429 tmp
|= (0x1C << 16);
8430 intel_sbi_write(dev_priv
, 0x2098, tmp
, SBI_MPHY
);
8432 tmp
= intel_sbi_read(dev_priv
, 0x2198, SBI_MPHY
);
8433 tmp
&= ~(0xFF << 16);
8434 tmp
|= (0x1C << 16);
8435 intel_sbi_write(dev_priv
, 0x2198, tmp
, SBI_MPHY
);
8437 tmp
= intel_sbi_read(dev_priv
, 0x20C4, SBI_MPHY
);
8439 intel_sbi_write(dev_priv
, 0x20C4, tmp
, SBI_MPHY
);
8441 tmp
= intel_sbi_read(dev_priv
, 0x21C4, SBI_MPHY
);
8443 intel_sbi_write(dev_priv
, 0x21C4, tmp
, SBI_MPHY
);
8445 tmp
= intel_sbi_read(dev_priv
, 0x20EC, SBI_MPHY
);
8446 tmp
&= ~(0xF << 28);
8448 intel_sbi_write(dev_priv
, 0x20EC, tmp
, SBI_MPHY
);
8450 tmp
= intel_sbi_read(dev_priv
, 0x21EC, SBI_MPHY
);
8451 tmp
&= ~(0xF << 28);
8453 intel_sbi_write(dev_priv
, 0x21EC, tmp
, SBI_MPHY
);
8456 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8457 * Programming" based on the parameters passed:
8458 * - Sequence to enable CLKOUT_DP
8459 * - Sequence to enable CLKOUT_DP without spread
8460 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8462 static void lpt_enable_clkout_dp(struct drm_device
*dev
, bool with_spread
,
8465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8468 if (WARN(with_fdi
&& !with_spread
, "FDI requires downspread\n"))
8470 if (WARN(HAS_PCH_LPT_LP(dev
) && with_fdi
, "LP PCH doesn't have FDI\n"))
8473 mutex_lock(&dev_priv
->sb_lock
);
8475 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8476 tmp
&= ~SBI_SSCCTL_DISABLE
;
8477 tmp
|= SBI_SSCCTL_PATHALT
;
8478 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8483 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8484 tmp
&= ~SBI_SSCCTL_PATHALT
;
8485 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8488 lpt_reset_fdi_mphy(dev_priv
);
8489 lpt_program_fdi_mphy(dev_priv
);
8493 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8494 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8495 tmp
|= SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8496 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8498 mutex_unlock(&dev_priv
->sb_lock
);
8501 /* Sequence to disable CLKOUT_DP */
8502 static void lpt_disable_clkout_dp(struct drm_device
*dev
)
8504 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8507 mutex_lock(&dev_priv
->sb_lock
);
8509 reg
= HAS_PCH_LPT_LP(dev
) ? SBI_GEN0
: SBI_DBUFF0
;
8510 tmp
= intel_sbi_read(dev_priv
, reg
, SBI_ICLK
);
8511 tmp
&= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE
;
8512 intel_sbi_write(dev_priv
, reg
, tmp
, SBI_ICLK
);
8514 tmp
= intel_sbi_read(dev_priv
, SBI_SSCCTL
, SBI_ICLK
);
8515 if (!(tmp
& SBI_SSCCTL_DISABLE
)) {
8516 if (!(tmp
& SBI_SSCCTL_PATHALT
)) {
8517 tmp
|= SBI_SSCCTL_PATHALT
;
8518 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8521 tmp
|= SBI_SSCCTL_DISABLE
;
8522 intel_sbi_write(dev_priv
, SBI_SSCCTL
, tmp
, SBI_ICLK
);
8525 mutex_unlock(&dev_priv
->sb_lock
);
8528 static void lpt_init_pch_refclk(struct drm_device
*dev
)
8530 struct intel_encoder
*encoder
;
8531 bool has_vga
= false;
8533 for_each_intel_encoder(dev
, encoder
) {
8534 switch (encoder
->type
) {
8535 case INTEL_OUTPUT_ANALOG
:
8544 lpt_enable_clkout_dp(dev
, true, true);
8546 lpt_disable_clkout_dp(dev
);
8550 * Initialize reference clocks when the driver loads
8552 void intel_init_pch_refclk(struct drm_device
*dev
)
8554 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
8555 ironlake_init_pch_refclk(dev
);
8556 else if (HAS_PCH_LPT(dev
))
8557 lpt_init_pch_refclk(dev
);
8560 static int ironlake_get_refclk(struct intel_crtc_state
*crtc_state
)
8562 struct drm_device
*dev
= crtc_state
->base
.crtc
->dev
;
8563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8564 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8565 struct drm_connector
*connector
;
8566 struct drm_connector_state
*connector_state
;
8567 struct intel_encoder
*encoder
;
8568 int num_connectors
= 0, i
;
8569 bool is_lvds
= false;
8571 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8572 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8575 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8577 switch (encoder
->type
) {
8578 case INTEL_OUTPUT_LVDS
:
8587 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
8588 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8589 dev_priv
->vbt
.lvds_ssc_freq
);
8590 return dev_priv
->vbt
.lvds_ssc_freq
;
8596 static void ironlake_set_pipeconf(struct drm_crtc
*crtc
)
8598 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
8599 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8600 int pipe
= intel_crtc
->pipe
;
8605 switch (intel_crtc
->config
->pipe_bpp
) {
8607 val
|= PIPECONF_6BPC
;
8610 val
|= PIPECONF_8BPC
;
8613 val
|= PIPECONF_10BPC
;
8616 val
|= PIPECONF_12BPC
;
8619 /* Case prevented by intel_choose_pipe_bpp_dither. */
8623 if (intel_crtc
->config
->dither
)
8624 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8626 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8627 val
|= PIPECONF_INTERLACED_ILK
;
8629 val
|= PIPECONF_PROGRESSIVE
;
8631 if (intel_crtc
->config
->limited_color_range
)
8632 val
|= PIPECONF_COLOR_RANGE_SELECT
;
8634 I915_WRITE(PIPECONF(pipe
), val
);
8635 POSTING_READ(PIPECONF(pipe
));
8639 * Set up the pipe CSC unit.
8641 * Currently only full range RGB to limited range RGB conversion
8642 * is supported, but eventually this should handle various
8643 * RGB<->YCbCr scenarios as well.
8645 static void intel_set_pipe_csc(struct drm_crtc
*crtc
)
8647 struct drm_device
*dev
= crtc
->dev
;
8648 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8649 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8650 int pipe
= intel_crtc
->pipe
;
8651 uint16_t coeff
= 0x7800; /* 1.0 */
8654 * TODO: Check what kind of values actually come out of the pipe
8655 * with these coeff/postoff values and adjust to get the best
8656 * accuracy. Perhaps we even need to take the bpc value into
8660 if (intel_crtc
->config
->limited_color_range
)
8661 coeff
= ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8664 * GY/GU and RY/RU should be the other way around according
8665 * to BSpec, but reality doesn't agree. Just set them up in
8666 * a way that results in the correct picture.
8668 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe
), coeff
<< 16);
8669 I915_WRITE(PIPE_CSC_COEFF_BY(pipe
), 0);
8671 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe
), coeff
);
8672 I915_WRITE(PIPE_CSC_COEFF_BU(pipe
), 0);
8674 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe
), 0);
8675 I915_WRITE(PIPE_CSC_COEFF_BV(pipe
), coeff
<< 16);
8677 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe
), 0);
8678 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe
), 0);
8679 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe
), 0);
8681 if (INTEL_INFO(dev
)->gen
> 6) {
8682 uint16_t postoff
= 0;
8684 if (intel_crtc
->config
->limited_color_range
)
8685 postoff
= (16 * (1 << 12) / 255) & 0x1fff;
8687 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe
), postoff
);
8688 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe
), postoff
);
8689 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe
), postoff
);
8691 I915_WRITE(PIPE_CSC_MODE(pipe
), 0);
8693 uint32_t mode
= CSC_MODE_YUV_TO_RGB
;
8695 if (intel_crtc
->config
->limited_color_range
)
8696 mode
|= CSC_BLACK_SCREEN_OFFSET
;
8698 I915_WRITE(PIPE_CSC_MODE(pipe
), mode
);
8702 static void haswell_set_pipeconf(struct drm_crtc
*crtc
)
8704 struct drm_device
*dev
= crtc
->dev
;
8705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8706 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
8707 enum pipe pipe
= intel_crtc
->pipe
;
8708 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
8713 if (IS_HASWELL(dev
) && intel_crtc
->config
->dither
)
8714 val
|= (PIPECONF_DITHER_EN
| PIPECONF_DITHER_TYPE_SP
);
8716 if (intel_crtc
->config
->base
.adjusted_mode
.flags
& DRM_MODE_FLAG_INTERLACE
)
8717 val
|= PIPECONF_INTERLACED_ILK
;
8719 val
|= PIPECONF_PROGRESSIVE
;
8721 I915_WRITE(PIPECONF(cpu_transcoder
), val
);
8722 POSTING_READ(PIPECONF(cpu_transcoder
));
8724 I915_WRITE(GAMMA_MODE(intel_crtc
->pipe
), GAMMA_MODE_MODE_8BIT
);
8725 POSTING_READ(GAMMA_MODE(intel_crtc
->pipe
));
8727 if (IS_BROADWELL(dev
) || INTEL_INFO(dev
)->gen
>= 9) {
8730 switch (intel_crtc
->config
->pipe_bpp
) {
8732 val
|= PIPEMISC_DITHER_6_BPC
;
8735 val
|= PIPEMISC_DITHER_8_BPC
;
8738 val
|= PIPEMISC_DITHER_10_BPC
;
8741 val
|= PIPEMISC_DITHER_12_BPC
;
8744 /* Case prevented by pipe_config_set_bpp. */
8748 if (intel_crtc
->config
->dither
)
8749 val
|= PIPEMISC_DITHER_ENABLE
| PIPEMISC_DITHER_TYPE_SP
;
8751 I915_WRITE(PIPEMISC(pipe
), val
);
8755 static bool ironlake_compute_clocks(struct drm_crtc
*crtc
,
8756 struct intel_crtc_state
*crtc_state
,
8757 intel_clock_t
*clock
,
8758 bool *has_reduced_clock
,
8759 intel_clock_t
*reduced_clock
)
8761 struct drm_device
*dev
= crtc
->dev
;
8762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8764 const intel_limit_t
*limit
;
8767 refclk
= ironlake_get_refclk(crtc_state
);
8770 * Returns a set of divisors for the desired target clock with the given
8771 * refclk, or FALSE. The returned values represent the clock equation:
8772 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8774 limit
= intel_limit(crtc_state
, refclk
);
8775 ret
= dev_priv
->display
.find_dpll(limit
, crtc_state
,
8776 crtc_state
->port_clock
,
8777 refclk
, NULL
, clock
);
8784 int ironlake_get_lanes_required(int target_clock
, int link_bw
, int bpp
)
8787 * Account for spread spectrum to avoid
8788 * oversubscribing the link. Max center spread
8789 * is 2.5%; use 5% for safety's sake.
8791 u32 bps
= target_clock
* bpp
* 21 / 20;
8792 return DIV_ROUND_UP(bps
, link_bw
* 8);
8795 static bool ironlake_needs_fb_cb_tune(struct dpll
*dpll
, int factor
)
8797 return i9xx_dpll_compute_m(dpll
) < factor
* dpll
->n
;
8800 static uint32_t ironlake_compute_dpll(struct intel_crtc
*intel_crtc
,
8801 struct intel_crtc_state
*crtc_state
,
8803 intel_clock_t
*reduced_clock
, u32
*fp2
)
8805 struct drm_crtc
*crtc
= &intel_crtc
->base
;
8806 struct drm_device
*dev
= crtc
->dev
;
8807 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8808 struct drm_atomic_state
*state
= crtc_state
->base
.state
;
8809 struct drm_connector
*connector
;
8810 struct drm_connector_state
*connector_state
;
8811 struct intel_encoder
*encoder
;
8813 int factor
, num_connectors
= 0, i
;
8814 bool is_lvds
= false, is_sdvo
= false;
8816 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
8817 if (connector_state
->crtc
!= crtc_state
->base
.crtc
)
8820 encoder
= to_intel_encoder(connector_state
->best_encoder
);
8822 switch (encoder
->type
) {
8823 case INTEL_OUTPUT_LVDS
:
8826 case INTEL_OUTPUT_SDVO
:
8827 case INTEL_OUTPUT_HDMI
:
8837 /* Enable autotuning of the PLL clock (if permissible) */
8840 if ((intel_panel_use_ssc(dev_priv
) &&
8841 dev_priv
->vbt
.lvds_ssc_freq
== 100000) ||
8842 (HAS_PCH_IBX(dev
) && intel_is_dual_link_lvds(dev
)))
8844 } else if (crtc_state
->sdvo_tv_clock
)
8847 if (ironlake_needs_fb_cb_tune(&crtc_state
->dpll
, factor
))
8850 if (fp2
&& (reduced_clock
->m
< factor
* reduced_clock
->n
))
8856 dpll
|= DPLLB_MODE_LVDS
;
8858 dpll
|= DPLLB_MODE_DAC_SERIAL
;
8860 dpll
|= (crtc_state
->pixel_multiplier
- 1)
8861 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
8864 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8865 if (crtc_state
->has_dp_encoder
)
8866 dpll
|= DPLL_SDVO_HIGH_SPEED
;
8868 /* compute bitmask from p1 value */
8869 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
8871 dpll
|= (1 << (crtc_state
->dpll
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
8873 switch (crtc_state
->dpll
.p2
) {
8875 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
8878 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
8881 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
8884 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
8888 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
8889 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
8891 dpll
|= PLL_REF_INPUT_DREFCLK
;
8893 return dpll
| DPLL_VCO_ENABLE
;
8896 static int ironlake_crtc_compute_clock(struct intel_crtc
*crtc
,
8897 struct intel_crtc_state
*crtc_state
)
8899 struct drm_device
*dev
= crtc
->base
.dev
;
8900 intel_clock_t clock
, reduced_clock
;
8901 u32 dpll
= 0, fp
= 0, fp2
= 0;
8902 bool ok
, has_reduced_clock
= false;
8903 bool is_lvds
= false;
8904 struct intel_shared_dpll
*pll
;
8906 memset(&crtc_state
->dpll_hw_state
, 0,
8907 sizeof(crtc_state
->dpll_hw_state
));
8909 is_lvds
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
);
8911 WARN(!(HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)),
8912 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev
));
8914 ok
= ironlake_compute_clocks(&crtc
->base
, crtc_state
, &clock
,
8915 &has_reduced_clock
, &reduced_clock
);
8916 if (!ok
&& !crtc_state
->clock_set
) {
8917 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8920 /* Compat-code for transition, will disappear. */
8921 if (!crtc_state
->clock_set
) {
8922 crtc_state
->dpll
.n
= clock
.n
;
8923 crtc_state
->dpll
.m1
= clock
.m1
;
8924 crtc_state
->dpll
.m2
= clock
.m2
;
8925 crtc_state
->dpll
.p1
= clock
.p1
;
8926 crtc_state
->dpll
.p2
= clock
.p2
;
8929 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8930 if (crtc_state
->has_pch_encoder
) {
8931 fp
= i9xx_dpll_compute_fp(&crtc_state
->dpll
);
8932 if (has_reduced_clock
)
8933 fp2
= i9xx_dpll_compute_fp(&reduced_clock
);
8935 dpll
= ironlake_compute_dpll(crtc
, crtc_state
,
8936 &fp
, &reduced_clock
,
8937 has_reduced_clock
? &fp2
: NULL
);
8939 crtc_state
->dpll_hw_state
.dpll
= dpll
;
8940 crtc_state
->dpll_hw_state
.fp0
= fp
;
8941 if (has_reduced_clock
)
8942 crtc_state
->dpll_hw_state
.fp1
= fp2
;
8944 crtc_state
->dpll_hw_state
.fp1
= fp
;
8946 pll
= intel_get_shared_dpll(crtc
, crtc_state
);
8948 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8949 pipe_name(crtc
->pipe
));
8954 if (is_lvds
&& has_reduced_clock
)
8955 crtc
->lowfreq_avail
= true;
8957 crtc
->lowfreq_avail
= false;
8962 static void intel_pch_transcoder_get_m_n(struct intel_crtc
*crtc
,
8963 struct intel_link_m_n
*m_n
)
8965 struct drm_device
*dev
= crtc
->base
.dev
;
8966 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8967 enum pipe pipe
= crtc
->pipe
;
8969 m_n
->link_m
= I915_READ(PCH_TRANS_LINK_M1(pipe
));
8970 m_n
->link_n
= I915_READ(PCH_TRANS_LINK_N1(pipe
));
8971 m_n
->gmch_m
= I915_READ(PCH_TRANS_DATA_M1(pipe
))
8973 m_n
->gmch_n
= I915_READ(PCH_TRANS_DATA_N1(pipe
));
8974 m_n
->tu
= ((I915_READ(PCH_TRANS_DATA_M1(pipe
))
8975 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8978 static void intel_cpu_transcoder_get_m_n(struct intel_crtc
*crtc
,
8979 enum transcoder transcoder
,
8980 struct intel_link_m_n
*m_n
,
8981 struct intel_link_m_n
*m2_n2
)
8983 struct drm_device
*dev
= crtc
->base
.dev
;
8984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
8985 enum pipe pipe
= crtc
->pipe
;
8987 if (INTEL_INFO(dev
)->gen
>= 5) {
8988 m_n
->link_m
= I915_READ(PIPE_LINK_M1(transcoder
));
8989 m_n
->link_n
= I915_READ(PIPE_LINK_N1(transcoder
));
8990 m_n
->gmch_m
= I915_READ(PIPE_DATA_M1(transcoder
))
8992 m_n
->gmch_n
= I915_READ(PIPE_DATA_N1(transcoder
));
8993 m_n
->tu
= ((I915_READ(PIPE_DATA_M1(transcoder
))
8994 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
8995 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8996 * gen < 8) and if DRRS is supported (to make sure the
8997 * registers are not unnecessarily read).
8999 if (m2_n2
&& INTEL_INFO(dev
)->gen
< 8 &&
9000 crtc
->config
->has_drrs
) {
9001 m2_n2
->link_m
= I915_READ(PIPE_LINK_M2(transcoder
));
9002 m2_n2
->link_n
= I915_READ(PIPE_LINK_N2(transcoder
));
9003 m2_n2
->gmch_m
= I915_READ(PIPE_DATA_M2(transcoder
))
9005 m2_n2
->gmch_n
= I915_READ(PIPE_DATA_N2(transcoder
));
9006 m2_n2
->tu
= ((I915_READ(PIPE_DATA_M2(transcoder
))
9007 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9010 m_n
->link_m
= I915_READ(PIPE_LINK_M_G4X(pipe
));
9011 m_n
->link_n
= I915_READ(PIPE_LINK_N_G4X(pipe
));
9012 m_n
->gmch_m
= I915_READ(PIPE_DATA_M_G4X(pipe
))
9014 m_n
->gmch_n
= I915_READ(PIPE_DATA_N_G4X(pipe
));
9015 m_n
->tu
= ((I915_READ(PIPE_DATA_M_G4X(pipe
))
9016 & TU_SIZE_MASK
) >> TU_SIZE_SHIFT
) + 1;
9020 void intel_dp_get_m_n(struct intel_crtc
*crtc
,
9021 struct intel_crtc_state
*pipe_config
)
9023 if (pipe_config
->has_pch_encoder
)
9024 intel_pch_transcoder_get_m_n(crtc
, &pipe_config
->dp_m_n
);
9026 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9027 &pipe_config
->dp_m_n
,
9028 &pipe_config
->dp_m2_n2
);
9031 static void ironlake_get_fdi_m_n_config(struct intel_crtc
*crtc
,
9032 struct intel_crtc_state
*pipe_config
)
9034 intel_cpu_transcoder_get_m_n(crtc
, pipe_config
->cpu_transcoder
,
9035 &pipe_config
->fdi_m_n
, NULL
);
9038 static void skylake_get_pfit_config(struct intel_crtc
*crtc
,
9039 struct intel_crtc_state
*pipe_config
)
9041 struct drm_device
*dev
= crtc
->base
.dev
;
9042 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9043 struct intel_crtc_scaler_state
*scaler_state
= &pipe_config
->scaler_state
;
9044 uint32_t ps_ctrl
= 0;
9048 /* find scaler attached to this pipe */
9049 for (i
= 0; i
< crtc
->num_scalers
; i
++) {
9050 ps_ctrl
= I915_READ(SKL_PS_CTRL(crtc
->pipe
, i
));
9051 if (ps_ctrl
& PS_SCALER_EN
&& !(ps_ctrl
& PS_PLANE_SEL_MASK
)) {
9053 pipe_config
->pch_pfit
.enabled
= true;
9054 pipe_config
->pch_pfit
.pos
= I915_READ(SKL_PS_WIN_POS(crtc
->pipe
, i
));
9055 pipe_config
->pch_pfit
.size
= I915_READ(SKL_PS_WIN_SZ(crtc
->pipe
, i
));
9060 scaler_state
->scaler_id
= id
;
9062 scaler_state
->scaler_users
|= (1 << SKL_CRTC_INDEX
);
9064 scaler_state
->scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9069 skylake_get_initial_plane_config(struct intel_crtc
*crtc
,
9070 struct intel_initial_plane_config
*plane_config
)
9072 struct drm_device
*dev
= crtc
->base
.dev
;
9073 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9074 u32 val
, base
, offset
, stride_mult
, tiling
;
9075 int pipe
= crtc
->pipe
;
9076 int fourcc
, pixel_format
;
9077 unsigned int aligned_height
;
9078 struct drm_framebuffer
*fb
;
9079 struct intel_framebuffer
*intel_fb
;
9081 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9083 DRM_DEBUG_KMS("failed to alloc fb\n");
9087 fb
= &intel_fb
->base
;
9089 val
= I915_READ(PLANE_CTL(pipe
, 0));
9090 if (!(val
& PLANE_CTL_ENABLE
))
9093 pixel_format
= val
& PLANE_CTL_FORMAT_MASK
;
9094 fourcc
= skl_format_to_fourcc(pixel_format
,
9095 val
& PLANE_CTL_ORDER_RGBX
,
9096 val
& PLANE_CTL_ALPHA_MASK
);
9097 fb
->pixel_format
= fourcc
;
9098 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9100 tiling
= val
& PLANE_CTL_TILED_MASK
;
9102 case PLANE_CTL_TILED_LINEAR
:
9103 fb
->modifier
[0] = DRM_FORMAT_MOD_NONE
;
9105 case PLANE_CTL_TILED_X
:
9106 plane_config
->tiling
= I915_TILING_X
;
9107 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9109 case PLANE_CTL_TILED_Y
:
9110 fb
->modifier
[0] = I915_FORMAT_MOD_Y_TILED
;
9112 case PLANE_CTL_TILED_YF
:
9113 fb
->modifier
[0] = I915_FORMAT_MOD_Yf_TILED
;
9116 MISSING_CASE(tiling
);
9120 base
= I915_READ(PLANE_SURF(pipe
, 0)) & 0xfffff000;
9121 plane_config
->base
= base
;
9123 offset
= I915_READ(PLANE_OFFSET(pipe
, 0));
9125 val
= I915_READ(PLANE_SIZE(pipe
, 0));
9126 fb
->height
= ((val
>> 16) & 0xfff) + 1;
9127 fb
->width
= ((val
>> 0) & 0x1fff) + 1;
9129 val
= I915_READ(PLANE_STRIDE(pipe
, 0));
9130 stride_mult
= intel_fb_stride_alignment(dev
, fb
->modifier
[0],
9132 fb
->pitches
[0] = (val
& 0x3ff) * stride_mult
;
9134 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9138 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9140 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9141 pipe_name(pipe
), fb
->width
, fb
->height
,
9142 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9143 plane_config
->size
);
9145 plane_config
->fb
= intel_fb
;
9152 static void ironlake_get_pfit_config(struct intel_crtc
*crtc
,
9153 struct intel_crtc_state
*pipe_config
)
9155 struct drm_device
*dev
= crtc
->base
.dev
;
9156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9159 tmp
= I915_READ(PF_CTL(crtc
->pipe
));
9161 if (tmp
& PF_ENABLE
) {
9162 pipe_config
->pch_pfit
.enabled
= true;
9163 pipe_config
->pch_pfit
.pos
= I915_READ(PF_WIN_POS(crtc
->pipe
));
9164 pipe_config
->pch_pfit
.size
= I915_READ(PF_WIN_SZ(crtc
->pipe
));
9166 /* We currently do not free assignements of panel fitters on
9167 * ivb/hsw (since we don't use the higher upscaling modes which
9168 * differentiates them) so just WARN about this case for now. */
9170 WARN_ON((tmp
& PF_PIPE_SEL_MASK_IVB
) !=
9171 PF_PIPE_SEL_IVB(crtc
->pipe
));
9177 ironlake_get_initial_plane_config(struct intel_crtc
*crtc
,
9178 struct intel_initial_plane_config
*plane_config
)
9180 struct drm_device
*dev
= crtc
->base
.dev
;
9181 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9182 u32 val
, base
, offset
;
9183 int pipe
= crtc
->pipe
;
9184 int fourcc
, pixel_format
;
9185 unsigned int aligned_height
;
9186 struct drm_framebuffer
*fb
;
9187 struct intel_framebuffer
*intel_fb
;
9189 val
= I915_READ(DSPCNTR(pipe
));
9190 if (!(val
& DISPLAY_PLANE_ENABLE
))
9193 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
9195 DRM_DEBUG_KMS("failed to alloc fb\n");
9199 fb
= &intel_fb
->base
;
9201 if (INTEL_INFO(dev
)->gen
>= 4) {
9202 if (val
& DISPPLANE_TILED
) {
9203 plane_config
->tiling
= I915_TILING_X
;
9204 fb
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
9208 pixel_format
= val
& DISPPLANE_PIXFORMAT_MASK
;
9209 fourcc
= i9xx_format_to_fourcc(pixel_format
);
9210 fb
->pixel_format
= fourcc
;
9211 fb
->bits_per_pixel
= drm_format_plane_cpp(fourcc
, 0) * 8;
9213 base
= I915_READ(DSPSURF(pipe
)) & 0xfffff000;
9214 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
9215 offset
= I915_READ(DSPOFFSET(pipe
));
9217 if (plane_config
->tiling
)
9218 offset
= I915_READ(DSPTILEOFF(pipe
));
9220 offset
= I915_READ(DSPLINOFF(pipe
));
9222 plane_config
->base
= base
;
9224 val
= I915_READ(PIPESRC(pipe
));
9225 fb
->width
= ((val
>> 16) & 0xfff) + 1;
9226 fb
->height
= ((val
>> 0) & 0xfff) + 1;
9228 val
= I915_READ(DSPSTRIDE(pipe
));
9229 fb
->pitches
[0] = val
& 0xffffffc0;
9231 aligned_height
= intel_fb_align_height(dev
, fb
->height
,
9235 plane_config
->size
= fb
->pitches
[0] * aligned_height
;
9237 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9238 pipe_name(pipe
), fb
->width
, fb
->height
,
9239 fb
->bits_per_pixel
, base
, fb
->pitches
[0],
9240 plane_config
->size
);
9242 plane_config
->fb
= intel_fb
;
9245 static bool ironlake_get_pipe_config(struct intel_crtc
*crtc
,
9246 struct intel_crtc_state
*pipe_config
)
9248 struct drm_device
*dev
= crtc
->base
.dev
;
9249 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9252 if (!intel_display_power_is_enabled(dev_priv
,
9253 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9256 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9257 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9259 tmp
= I915_READ(PIPECONF(crtc
->pipe
));
9260 if (!(tmp
& PIPECONF_ENABLE
))
9263 switch (tmp
& PIPECONF_BPC_MASK
) {
9265 pipe_config
->pipe_bpp
= 18;
9268 pipe_config
->pipe_bpp
= 24;
9270 case PIPECONF_10BPC
:
9271 pipe_config
->pipe_bpp
= 30;
9273 case PIPECONF_12BPC
:
9274 pipe_config
->pipe_bpp
= 36;
9280 if (tmp
& PIPECONF_COLOR_RANGE_SELECT
)
9281 pipe_config
->limited_color_range
= true;
9283 if (I915_READ(PCH_TRANSCONF(crtc
->pipe
)) & TRANS_ENABLE
) {
9284 struct intel_shared_dpll
*pll
;
9286 pipe_config
->has_pch_encoder
= true;
9288 tmp
= I915_READ(FDI_RX_CTL(crtc
->pipe
));
9289 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9290 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9292 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9294 if (HAS_PCH_IBX(dev_priv
->dev
)) {
9295 pipe_config
->shared_dpll
=
9296 (enum intel_dpll_id
) crtc
->pipe
;
9298 tmp
= I915_READ(PCH_DPLL_SEL
);
9299 if (tmp
& TRANS_DPLLB_SEL(crtc
->pipe
))
9300 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_B
;
9302 pipe_config
->shared_dpll
= DPLL_ID_PCH_PLL_A
;
9305 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9307 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9308 &pipe_config
->dpll_hw_state
));
9310 tmp
= pipe_config
->dpll_hw_state
.dpll
;
9311 pipe_config
->pixel_multiplier
=
9312 ((tmp
& PLL_REF_SDVO_HDMI_MULTIPLIER_MASK
)
9313 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
) + 1;
9315 ironlake_pch_clock_get(crtc
, pipe_config
);
9317 pipe_config
->pixel_multiplier
= 1;
9320 intel_get_pipe_timings(crtc
, pipe_config
);
9322 ironlake_get_pfit_config(crtc
, pipe_config
);
9327 static void assert_can_disable_lcpll(struct drm_i915_private
*dev_priv
)
9329 struct drm_device
*dev
= dev_priv
->dev
;
9330 struct intel_crtc
*crtc
;
9332 for_each_intel_crtc(dev
, crtc
)
9333 I915_STATE_WARN(crtc
->active
, "CRTC for pipe %c enabled\n",
9334 pipe_name(crtc
->pipe
));
9336 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER
), "Power well on\n");
9337 I915_STATE_WARN(I915_READ(SPLL_CTL
) & SPLL_PLL_ENABLE
, "SPLL enabled\n");
9338 I915_STATE_WARN(I915_READ(WRPLL_CTL1
) & WRPLL_PLL_ENABLE
, "WRPLL1 enabled\n");
9339 I915_STATE_WARN(I915_READ(WRPLL_CTL2
) & WRPLL_PLL_ENABLE
, "WRPLL2 enabled\n");
9340 I915_STATE_WARN(I915_READ(PCH_PP_STATUS
) & PP_ON
, "Panel power on\n");
9341 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2
) & BLM_PWM_ENABLE
,
9342 "CPU PWM1 enabled\n");
9343 if (IS_HASWELL(dev
))
9344 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL
) & BLM_PWM_ENABLE
,
9345 "CPU PWM2 enabled\n");
9346 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1
) & BLM_PCH_PWM_ENABLE
,
9347 "PCH PWM1 enabled\n");
9348 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL
) & UTIL_PIN_ENABLE
,
9349 "Utility pin enabled\n");
9350 I915_STATE_WARN(I915_READ(PCH_GTC_CTL
) & PCH_GTC_ENABLE
, "PCH GTC enabled\n");
9353 * In theory we can still leave IRQs enabled, as long as only the HPD
9354 * interrupts remain enabled. We used to check for that, but since it's
9355 * gen-specific and since we only disable LCPLL after we fully disable
9356 * the interrupts, the check below should be enough.
9358 I915_STATE_WARN(intel_irqs_enabled(dev_priv
), "IRQs enabled\n");
9361 static uint32_t hsw_read_dcomp(struct drm_i915_private
*dev_priv
)
9363 struct drm_device
*dev
= dev_priv
->dev
;
9365 if (IS_HASWELL(dev
))
9366 return I915_READ(D_COMP_HSW
);
9368 return I915_READ(D_COMP_BDW
);
9371 static void hsw_write_dcomp(struct drm_i915_private
*dev_priv
, uint32_t val
)
9373 struct drm_device
*dev
= dev_priv
->dev
;
9375 if (IS_HASWELL(dev
)) {
9376 mutex_lock(&dev_priv
->rps
.hw_lock
);
9377 if (sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_D_COMP
,
9379 DRM_ERROR("Failed to write to D_COMP\n");
9380 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9382 I915_WRITE(D_COMP_BDW
, val
);
9383 POSTING_READ(D_COMP_BDW
);
9388 * This function implements pieces of two sequences from BSpec:
9389 * - Sequence for display software to disable LCPLL
9390 * - Sequence for display software to allow package C8+
9391 * The steps implemented here are just the steps that actually touch the LCPLL
9392 * register. Callers should take care of disabling all the display engine
9393 * functions, doing the mode unset, fixing interrupts, etc.
9395 static void hsw_disable_lcpll(struct drm_i915_private
*dev_priv
,
9396 bool switch_to_fclk
, bool allow_power_down
)
9400 assert_can_disable_lcpll(dev_priv
);
9402 val
= I915_READ(LCPLL_CTL
);
9404 if (switch_to_fclk
) {
9405 val
|= LCPLL_CD_SOURCE_FCLK
;
9406 I915_WRITE(LCPLL_CTL
, val
);
9408 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9409 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9410 DRM_ERROR("Switching to FCLK failed\n");
9412 val
= I915_READ(LCPLL_CTL
);
9415 val
|= LCPLL_PLL_DISABLE
;
9416 I915_WRITE(LCPLL_CTL
, val
);
9417 POSTING_READ(LCPLL_CTL
);
9419 if (wait_for((I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
) == 0, 1))
9420 DRM_ERROR("LCPLL still locked\n");
9422 val
= hsw_read_dcomp(dev_priv
);
9423 val
|= D_COMP_COMP_DISABLE
;
9424 hsw_write_dcomp(dev_priv
, val
);
9427 if (wait_for((hsw_read_dcomp(dev_priv
) & D_COMP_RCOMP_IN_PROGRESS
) == 0,
9429 DRM_ERROR("D_COMP RCOMP still in progress\n");
9431 if (allow_power_down
) {
9432 val
= I915_READ(LCPLL_CTL
);
9433 val
|= LCPLL_POWER_DOWN_ALLOW
;
9434 I915_WRITE(LCPLL_CTL
, val
);
9435 POSTING_READ(LCPLL_CTL
);
9440 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9443 static void hsw_restore_lcpll(struct drm_i915_private
*dev_priv
)
9447 val
= I915_READ(LCPLL_CTL
);
9449 if ((val
& (LCPLL_PLL_LOCK
| LCPLL_PLL_DISABLE
| LCPLL_CD_SOURCE_FCLK
|
9450 LCPLL_POWER_DOWN_ALLOW
)) == LCPLL_PLL_LOCK
)
9454 * Make sure we're not on PC8 state before disabling PC8, otherwise
9455 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9457 intel_uncore_forcewake_get(dev_priv
, FORCEWAKE_ALL
);
9459 if (val
& LCPLL_POWER_DOWN_ALLOW
) {
9460 val
&= ~LCPLL_POWER_DOWN_ALLOW
;
9461 I915_WRITE(LCPLL_CTL
, val
);
9462 POSTING_READ(LCPLL_CTL
);
9465 val
= hsw_read_dcomp(dev_priv
);
9466 val
|= D_COMP_COMP_FORCE
;
9467 val
&= ~D_COMP_COMP_DISABLE
;
9468 hsw_write_dcomp(dev_priv
, val
);
9470 val
= I915_READ(LCPLL_CTL
);
9471 val
&= ~LCPLL_PLL_DISABLE
;
9472 I915_WRITE(LCPLL_CTL
, val
);
9474 if (wait_for(I915_READ(LCPLL_CTL
) & LCPLL_PLL_LOCK
, 5))
9475 DRM_ERROR("LCPLL not locked yet\n");
9477 if (val
& LCPLL_CD_SOURCE_FCLK
) {
9478 val
= I915_READ(LCPLL_CTL
);
9479 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9480 I915_WRITE(LCPLL_CTL
, val
);
9482 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9483 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9484 DRM_ERROR("Switching back to LCPLL failed\n");
9487 intel_uncore_forcewake_put(dev_priv
, FORCEWAKE_ALL
);
9488 intel_update_cdclk(dev_priv
->dev
);
9492 * Package states C8 and deeper are really deep PC states that can only be
9493 * reached when all the devices on the system allow it, so even if the graphics
9494 * device allows PC8+, it doesn't mean the system will actually get to these
9495 * states. Our driver only allows PC8+ when going into runtime PM.
9497 * The requirements for PC8+ are that all the outputs are disabled, the power
9498 * well is disabled and most interrupts are disabled, and these are also
9499 * requirements for runtime PM. When these conditions are met, we manually do
9500 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9501 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9504 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9505 * the state of some registers, so when we come back from PC8+ we need to
9506 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9507 * need to take care of the registers kept by RC6. Notice that this happens even
9508 * if we don't put the device in PCI D3 state (which is what currently happens
9509 * because of the runtime PM support).
9511 * For more, read "Display Sequences for Package C8" on the hardware
9514 void hsw_enable_pc8(struct drm_i915_private
*dev_priv
)
9516 struct drm_device
*dev
= dev_priv
->dev
;
9519 DRM_DEBUG_KMS("Enabling package C8+\n");
9521 if (HAS_PCH_LPT_LP(dev
)) {
9522 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9523 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
9524 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9527 lpt_disable_clkout_dp(dev
);
9528 hsw_disable_lcpll(dev_priv
, true, true);
9531 void hsw_disable_pc8(struct drm_i915_private
*dev_priv
)
9533 struct drm_device
*dev
= dev_priv
->dev
;
9536 DRM_DEBUG_KMS("Disabling package C8+\n");
9538 hsw_restore_lcpll(dev_priv
);
9539 lpt_init_pch_refclk(dev
);
9541 if (HAS_PCH_LPT_LP(dev
)) {
9542 val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
9543 val
|= PCH_LP_PARTITION_LEVEL_DISABLE
;
9544 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
9547 intel_prepare_ddi(dev
);
9550 static void broxton_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9552 struct drm_device
*dev
= old_state
->dev
;
9553 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
9555 broxton_set_cdclk(dev
, req_cdclk
);
9558 /* compute the max rate for new configuration */
9559 static int ilk_max_pixel_rate(struct drm_atomic_state
*state
)
9561 struct intel_crtc
*intel_crtc
;
9562 struct intel_crtc_state
*crtc_state
;
9563 int max_pixel_rate
= 0;
9565 for_each_intel_crtc(state
->dev
, intel_crtc
) {
9568 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
9569 if (IS_ERR(crtc_state
))
9570 return PTR_ERR(crtc_state
);
9572 if (!crtc_state
->base
.enable
)
9575 pixel_rate
= ilk_pipe_pixel_rate(crtc_state
);
9577 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9578 if (IS_BROADWELL(state
->dev
) && crtc_state
->ips_enabled
)
9579 pixel_rate
= DIV_ROUND_UP(pixel_rate
* 100, 95);
9581 max_pixel_rate
= max(max_pixel_rate
, pixel_rate
);
9584 return max_pixel_rate
;
9587 static void broadwell_set_cdclk(struct drm_device
*dev
, int cdclk
)
9589 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9593 if (WARN((I915_READ(LCPLL_CTL
) &
9594 (LCPLL_PLL_DISABLE
| LCPLL_PLL_LOCK
|
9595 LCPLL_CD_CLOCK_DISABLE
| LCPLL_ROOT_CD_CLOCK_DISABLE
|
9596 LCPLL_CD2X_CLOCK_DISABLE
| LCPLL_POWER_DOWN_ALLOW
|
9597 LCPLL_CD_SOURCE_FCLK
)) != LCPLL_PLL_LOCK
,
9598 "trying to change cdclk frequency with cdclk not enabled\n"))
9601 mutex_lock(&dev_priv
->rps
.hw_lock
);
9602 ret
= sandybridge_pcode_write(dev_priv
,
9603 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ
, 0x0);
9604 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9606 DRM_ERROR("failed to inform pcode about cdclk change\n");
9610 val
= I915_READ(LCPLL_CTL
);
9611 val
|= LCPLL_CD_SOURCE_FCLK
;
9612 I915_WRITE(LCPLL_CTL
, val
);
9614 if (wait_for_atomic_us(I915_READ(LCPLL_CTL
) &
9615 LCPLL_CD_SOURCE_FCLK_DONE
, 1))
9616 DRM_ERROR("Switching to FCLK failed\n");
9618 val
= I915_READ(LCPLL_CTL
);
9619 val
&= ~LCPLL_CLK_FREQ_MASK
;
9623 val
|= LCPLL_CLK_FREQ_450
;
9627 val
|= LCPLL_CLK_FREQ_54O_BDW
;
9631 val
|= LCPLL_CLK_FREQ_337_5_BDW
;
9635 val
|= LCPLL_CLK_FREQ_675_BDW
;
9639 WARN(1, "invalid cdclk frequency\n");
9643 I915_WRITE(LCPLL_CTL
, val
);
9645 val
= I915_READ(LCPLL_CTL
);
9646 val
&= ~LCPLL_CD_SOURCE_FCLK
;
9647 I915_WRITE(LCPLL_CTL
, val
);
9649 if (wait_for_atomic_us((I915_READ(LCPLL_CTL
) &
9650 LCPLL_CD_SOURCE_FCLK_DONE
) == 0, 1))
9651 DRM_ERROR("Switching back to LCPLL failed\n");
9653 mutex_lock(&dev_priv
->rps
.hw_lock
);
9654 sandybridge_pcode_write(dev_priv
, HSW_PCODE_DE_WRITE_FREQ_REQ
, data
);
9655 mutex_unlock(&dev_priv
->rps
.hw_lock
);
9657 intel_update_cdclk(dev
);
9659 WARN(cdclk
!= dev_priv
->cdclk_freq
,
9660 "cdclk requested %d kHz but got %d kHz\n",
9661 cdclk
, dev_priv
->cdclk_freq
);
9664 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state
*state
)
9666 struct drm_i915_private
*dev_priv
= to_i915(state
->dev
);
9667 int max_pixclk
= ilk_max_pixel_rate(state
);
9671 * FIXME should also account for plane ratio
9672 * once 64bpp pixel formats are supported.
9674 if (max_pixclk
> 540000)
9676 else if (max_pixclk
> 450000)
9678 else if (max_pixclk
> 337500)
9684 * FIXME move the cdclk caclulation to
9685 * compute_config() so we can fail gracegully.
9687 if (cdclk
> dev_priv
->max_cdclk_freq
) {
9688 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9689 cdclk
, dev_priv
->max_cdclk_freq
);
9690 cdclk
= dev_priv
->max_cdclk_freq
;
9693 to_intel_atomic_state(state
)->cdclk
= cdclk
;
9698 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state
*old_state
)
9700 struct drm_device
*dev
= old_state
->dev
;
9701 unsigned int req_cdclk
= to_intel_atomic_state(old_state
)->cdclk
;
9703 broadwell_set_cdclk(dev
, req_cdclk
);
9706 static int haswell_crtc_compute_clock(struct intel_crtc
*crtc
,
9707 struct intel_crtc_state
*crtc_state
)
9709 if (!intel_ddi_pll_select(crtc
, crtc_state
))
9712 crtc
->lowfreq_avail
= false;
9717 static void bxt_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9719 struct intel_crtc_state
*pipe_config
)
9723 pipe_config
->ddi_pll_sel
= SKL_DPLL0
;
9724 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9727 pipe_config
->ddi_pll_sel
= SKL_DPLL1
;
9728 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9731 pipe_config
->ddi_pll_sel
= SKL_DPLL2
;
9732 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9735 DRM_ERROR("Incorrect port type\n");
9739 static void skylake_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9741 struct intel_crtc_state
*pipe_config
)
9743 u32 temp
, dpll_ctl1
;
9745 temp
= I915_READ(DPLL_CTRL2
) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port
);
9746 pipe_config
->ddi_pll_sel
= temp
>> (port
* 3 + 1);
9748 switch (pipe_config
->ddi_pll_sel
) {
9751 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9752 * of the shared DPLL framework and thus needs to be read out
9755 dpll_ctl1
= I915_READ(DPLL_CTRL1
);
9756 pipe_config
->dpll_hw_state
.ctrl1
= dpll_ctl1
& 0x3f;
9759 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL1
;
9762 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL2
;
9765 pipe_config
->shared_dpll
= DPLL_ID_SKL_DPLL3
;
9770 static void haswell_get_ddi_pll(struct drm_i915_private
*dev_priv
,
9772 struct intel_crtc_state
*pipe_config
)
9774 pipe_config
->ddi_pll_sel
= I915_READ(PORT_CLK_SEL(port
));
9776 switch (pipe_config
->ddi_pll_sel
) {
9777 case PORT_CLK_SEL_WRPLL1
:
9778 pipe_config
->shared_dpll
= DPLL_ID_WRPLL1
;
9780 case PORT_CLK_SEL_WRPLL2
:
9781 pipe_config
->shared_dpll
= DPLL_ID_WRPLL2
;
9783 case PORT_CLK_SEL_SPLL
:
9784 pipe_config
->shared_dpll
= DPLL_ID_SPLL
;
9788 static void haswell_get_ddi_port_state(struct intel_crtc
*crtc
,
9789 struct intel_crtc_state
*pipe_config
)
9791 struct drm_device
*dev
= crtc
->base
.dev
;
9792 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9793 struct intel_shared_dpll
*pll
;
9797 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(pipe_config
->cpu_transcoder
));
9799 port
= (tmp
& TRANS_DDI_PORT_MASK
) >> TRANS_DDI_PORT_SHIFT
;
9801 if (IS_SKYLAKE(dev
))
9802 skylake_get_ddi_pll(dev_priv
, port
, pipe_config
);
9803 else if (IS_BROXTON(dev
))
9804 bxt_get_ddi_pll(dev_priv
, port
, pipe_config
);
9806 haswell_get_ddi_pll(dev_priv
, port
, pipe_config
);
9808 if (pipe_config
->shared_dpll
>= 0) {
9809 pll
= &dev_priv
->shared_dplls
[pipe_config
->shared_dpll
];
9811 WARN_ON(!pll
->get_hw_state(dev_priv
, pll
,
9812 &pipe_config
->dpll_hw_state
));
9816 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9817 * DDI E. So just check whether this pipe is wired to DDI E and whether
9818 * the PCH transcoder is on.
9820 if (INTEL_INFO(dev
)->gen
< 9 &&
9821 (port
== PORT_E
) && I915_READ(LPT_TRANSCONF
) & TRANS_ENABLE
) {
9822 pipe_config
->has_pch_encoder
= true;
9824 tmp
= I915_READ(FDI_RX_CTL(PIPE_A
));
9825 pipe_config
->fdi_lanes
= ((FDI_DP_PORT_WIDTH_MASK
& tmp
) >>
9826 FDI_DP_PORT_WIDTH_SHIFT
) + 1;
9828 ironlake_get_fdi_m_n_config(crtc
, pipe_config
);
9832 static bool haswell_get_pipe_config(struct intel_crtc
*crtc
,
9833 struct intel_crtc_state
*pipe_config
)
9835 struct drm_device
*dev
= crtc
->base
.dev
;
9836 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9837 enum intel_display_power_domain pfit_domain
;
9840 if (!intel_display_power_is_enabled(dev_priv
,
9841 POWER_DOMAIN_PIPE(crtc
->pipe
)))
9844 pipe_config
->cpu_transcoder
= (enum transcoder
) crtc
->pipe
;
9845 pipe_config
->shared_dpll
= DPLL_ID_PRIVATE
;
9847 tmp
= I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP
));
9848 if (tmp
& TRANS_DDI_FUNC_ENABLE
) {
9849 enum pipe trans_edp_pipe
;
9850 switch (tmp
& TRANS_DDI_EDP_INPUT_MASK
) {
9852 WARN(1, "unknown pipe linked to edp transcoder\n");
9853 case TRANS_DDI_EDP_INPUT_A_ONOFF
:
9854 case TRANS_DDI_EDP_INPUT_A_ON
:
9855 trans_edp_pipe
= PIPE_A
;
9857 case TRANS_DDI_EDP_INPUT_B_ONOFF
:
9858 trans_edp_pipe
= PIPE_B
;
9860 case TRANS_DDI_EDP_INPUT_C_ONOFF
:
9861 trans_edp_pipe
= PIPE_C
;
9865 if (trans_edp_pipe
== crtc
->pipe
)
9866 pipe_config
->cpu_transcoder
= TRANSCODER_EDP
;
9869 if (!intel_display_power_is_enabled(dev_priv
,
9870 POWER_DOMAIN_TRANSCODER(pipe_config
->cpu_transcoder
)))
9873 tmp
= I915_READ(PIPECONF(pipe_config
->cpu_transcoder
));
9874 if (!(tmp
& PIPECONF_ENABLE
))
9877 haswell_get_ddi_port_state(crtc
, pipe_config
);
9879 intel_get_pipe_timings(crtc
, pipe_config
);
9881 if (INTEL_INFO(dev
)->gen
>= 9) {
9882 skl_init_scalers(dev
, crtc
, pipe_config
);
9885 pfit_domain
= POWER_DOMAIN_PIPE_PANEL_FITTER(crtc
->pipe
);
9887 if (INTEL_INFO(dev
)->gen
>= 9) {
9888 pipe_config
->scaler_state
.scaler_id
= -1;
9889 pipe_config
->scaler_state
.scaler_users
&= ~(1 << SKL_CRTC_INDEX
);
9892 if (intel_display_power_is_enabled(dev_priv
, pfit_domain
)) {
9893 if (INTEL_INFO(dev
)->gen
>= 9)
9894 skylake_get_pfit_config(crtc
, pipe_config
);
9896 ironlake_get_pfit_config(crtc
, pipe_config
);
9899 if (IS_HASWELL(dev
))
9900 pipe_config
->ips_enabled
= hsw_crtc_supports_ips(crtc
) &&
9901 (I915_READ(IPS_CTL
) & IPS_ENABLE
);
9903 if (pipe_config
->cpu_transcoder
!= TRANSCODER_EDP
) {
9904 pipe_config
->pixel_multiplier
=
9905 I915_READ(PIPE_MULT(pipe_config
->cpu_transcoder
)) + 1;
9907 pipe_config
->pixel_multiplier
= 1;
9913 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9915 struct drm_device
*dev
= crtc
->dev
;
9916 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9917 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9918 uint32_t cntl
= 0, size
= 0;
9921 unsigned int width
= intel_crtc
->base
.cursor
->state
->crtc_w
;
9922 unsigned int height
= intel_crtc
->base
.cursor
->state
->crtc_h
;
9923 unsigned int stride
= roundup_pow_of_two(width
) * 4;
9927 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9938 cntl
|= CURSOR_ENABLE
|
9939 CURSOR_GAMMA_ENABLE
|
9940 CURSOR_FORMAT_ARGB
|
9941 CURSOR_STRIDE(stride
);
9943 size
= (height
<< 12) | width
;
9946 if (intel_crtc
->cursor_cntl
!= 0 &&
9947 (intel_crtc
->cursor_base
!= base
||
9948 intel_crtc
->cursor_size
!= size
||
9949 intel_crtc
->cursor_cntl
!= cntl
)) {
9950 /* On these chipsets we can only modify the base/size/stride
9951 * whilst the cursor is disabled.
9953 I915_WRITE(CURCNTR(PIPE_A
), 0);
9954 POSTING_READ(CURCNTR(PIPE_A
));
9955 intel_crtc
->cursor_cntl
= 0;
9958 if (intel_crtc
->cursor_base
!= base
) {
9959 I915_WRITE(CURBASE(PIPE_A
), base
);
9960 intel_crtc
->cursor_base
= base
;
9963 if (intel_crtc
->cursor_size
!= size
) {
9964 I915_WRITE(CURSIZE
, size
);
9965 intel_crtc
->cursor_size
= size
;
9968 if (intel_crtc
->cursor_cntl
!= cntl
) {
9969 I915_WRITE(CURCNTR(PIPE_A
), cntl
);
9970 POSTING_READ(CURCNTR(PIPE_A
));
9971 intel_crtc
->cursor_cntl
= cntl
;
9975 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
9977 struct drm_device
*dev
= crtc
->dev
;
9978 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
9979 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
9980 int pipe
= intel_crtc
->pipe
;
9985 cntl
= MCURSOR_GAMMA_ENABLE
;
9986 switch (intel_crtc
->base
.cursor
->state
->crtc_w
) {
9988 cntl
|= CURSOR_MODE_64_ARGB_AX
;
9991 cntl
|= CURSOR_MODE_128_ARGB_AX
;
9994 cntl
|= CURSOR_MODE_256_ARGB_AX
;
9997 MISSING_CASE(intel_crtc
->base
.cursor
->state
->crtc_w
);
10000 cntl
|= pipe
<< 28; /* Connect to correct pipe */
10003 cntl
|= CURSOR_PIPE_CSC_ENABLE
;
10006 if (crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
))
10007 cntl
|= CURSOR_ROTATE_180
;
10009 if (intel_crtc
->cursor_cntl
!= cntl
) {
10010 I915_WRITE(CURCNTR(pipe
), cntl
);
10011 POSTING_READ(CURCNTR(pipe
));
10012 intel_crtc
->cursor_cntl
= cntl
;
10015 /* and commit changes on next vblank */
10016 I915_WRITE(CURBASE(pipe
), base
);
10017 POSTING_READ(CURBASE(pipe
));
10019 intel_crtc
->cursor_base
= base
;
10022 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10023 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
10026 struct drm_device
*dev
= crtc
->dev
;
10027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10028 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10029 int pipe
= intel_crtc
->pipe
;
10030 struct drm_plane_state
*cursor_state
= crtc
->cursor
->state
;
10031 int x
= cursor_state
->crtc_x
;
10032 int y
= cursor_state
->crtc_y
;
10033 u32 base
= 0, pos
= 0;
10036 base
= intel_crtc
->cursor_addr
;
10038 if (x
>= intel_crtc
->config
->pipe_src_w
)
10041 if (y
>= intel_crtc
->config
->pipe_src_h
)
10045 if (x
+ cursor_state
->crtc_w
<= 0)
10048 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
10051 pos
|= x
<< CURSOR_X_SHIFT
;
10054 if (y
+ cursor_state
->crtc_h
<= 0)
10057 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
10060 pos
|= y
<< CURSOR_Y_SHIFT
;
10062 if (base
== 0 && intel_crtc
->cursor_base
== 0)
10065 I915_WRITE(CURPOS(pipe
), pos
);
10067 /* ILK+ do this automagically */
10068 if (HAS_GMCH_DISPLAY(dev
) &&
10069 crtc
->cursor
->state
->rotation
== BIT(DRM_ROTATE_180
)) {
10070 base
+= (cursor_state
->crtc_h
*
10071 cursor_state
->crtc_w
- 1) * 4;
10074 if (IS_845G(dev
) || IS_I865G(dev
))
10075 i845_update_cursor(crtc
, base
);
10077 i9xx_update_cursor(crtc
, base
);
10080 static bool cursor_size_ok(struct drm_device
*dev
,
10081 uint32_t width
, uint32_t height
)
10083 if (width
== 0 || height
== 0)
10087 * 845g/865g are special in that they are only limited by
10088 * the width of their cursors, the height is arbitrary up to
10089 * the precision of the register. Everything else requires
10090 * square cursors, limited to a few power-of-two sizes.
10092 if (IS_845G(dev
) || IS_I865G(dev
)) {
10093 if ((width
& 63) != 0)
10096 if (width
> (IS_845G(dev
) ? 64 : 512))
10102 switch (width
| height
) {
10117 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
10118 u16
*blue
, uint32_t start
, uint32_t size
)
10120 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
10121 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10123 for (i
= start
; i
< end
; i
++) {
10124 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
10125 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
10126 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
10129 intel_crtc_load_lut(crtc
);
10132 /* VESA 640x480x72Hz mode to set on the pipe */
10133 static struct drm_display_mode load_detect_mode
= {
10134 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
10135 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
10138 struct drm_framebuffer
*
10139 __intel_framebuffer_create(struct drm_device
*dev
,
10140 struct drm_mode_fb_cmd2
*mode_cmd
,
10141 struct drm_i915_gem_object
*obj
)
10143 struct intel_framebuffer
*intel_fb
;
10146 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
10148 drm_gem_object_unreference(&obj
->base
);
10149 return ERR_PTR(-ENOMEM
);
10152 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
10156 return &intel_fb
->base
;
10158 drm_gem_object_unreference(&obj
->base
);
10161 return ERR_PTR(ret
);
10164 static struct drm_framebuffer
*
10165 intel_framebuffer_create(struct drm_device
*dev
,
10166 struct drm_mode_fb_cmd2
*mode_cmd
,
10167 struct drm_i915_gem_object
*obj
)
10169 struct drm_framebuffer
*fb
;
10172 ret
= i915_mutex_lock_interruptible(dev
);
10174 return ERR_PTR(ret
);
10175 fb
= __intel_framebuffer_create(dev
, mode_cmd
, obj
);
10176 mutex_unlock(&dev
->struct_mutex
);
10182 intel_framebuffer_pitch_for_width(int width
, int bpp
)
10184 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
10185 return ALIGN(pitch
, 64);
10189 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
10191 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
10192 return PAGE_ALIGN(pitch
* mode
->vdisplay
);
10195 static struct drm_framebuffer
*
10196 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
10197 struct drm_display_mode
*mode
,
10198 int depth
, int bpp
)
10200 struct drm_i915_gem_object
*obj
;
10201 struct drm_mode_fb_cmd2 mode_cmd
= { 0 };
10203 obj
= i915_gem_alloc_object(dev
,
10204 intel_framebuffer_size_for_mode(mode
, bpp
));
10206 return ERR_PTR(-ENOMEM
);
10208 mode_cmd
.width
= mode
->hdisplay
;
10209 mode_cmd
.height
= mode
->vdisplay
;
10210 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
10212 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
10214 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
10217 static struct drm_framebuffer
*
10218 mode_fits_in_fbdev(struct drm_device
*dev
,
10219 struct drm_display_mode
*mode
)
10221 #ifdef CONFIG_DRM_FBDEV_EMULATION
10222 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10223 struct drm_i915_gem_object
*obj
;
10224 struct drm_framebuffer
*fb
;
10226 if (!dev_priv
->fbdev
)
10229 if (!dev_priv
->fbdev
->fb
)
10232 obj
= dev_priv
->fbdev
->fb
->obj
;
10235 fb
= &dev_priv
->fbdev
->fb
->base
;
10236 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
10237 fb
->bits_per_pixel
))
10240 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
10249 static int intel_modeset_setup_plane_state(struct drm_atomic_state
*state
,
10250 struct drm_crtc
*crtc
,
10251 struct drm_display_mode
*mode
,
10252 struct drm_framebuffer
*fb
,
10255 struct drm_plane_state
*plane_state
;
10256 int hdisplay
, vdisplay
;
10259 plane_state
= drm_atomic_get_plane_state(state
, crtc
->primary
);
10260 if (IS_ERR(plane_state
))
10261 return PTR_ERR(plane_state
);
10264 drm_crtc_get_hv_timing(mode
, &hdisplay
, &vdisplay
);
10266 hdisplay
= vdisplay
= 0;
10268 ret
= drm_atomic_set_crtc_for_plane(plane_state
, fb
? crtc
: NULL
);
10271 drm_atomic_set_fb_for_plane(plane_state
, fb
);
10272 plane_state
->crtc_x
= 0;
10273 plane_state
->crtc_y
= 0;
10274 plane_state
->crtc_w
= hdisplay
;
10275 plane_state
->crtc_h
= vdisplay
;
10276 plane_state
->src_x
= x
<< 16;
10277 plane_state
->src_y
= y
<< 16;
10278 plane_state
->src_w
= hdisplay
<< 16;
10279 plane_state
->src_h
= vdisplay
<< 16;
10284 bool intel_get_load_detect_pipe(struct drm_connector
*connector
,
10285 struct drm_display_mode
*mode
,
10286 struct intel_load_detect_pipe
*old
,
10287 struct drm_modeset_acquire_ctx
*ctx
)
10289 struct intel_crtc
*intel_crtc
;
10290 struct intel_encoder
*intel_encoder
=
10291 intel_attached_encoder(connector
);
10292 struct drm_crtc
*possible_crtc
;
10293 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10294 struct drm_crtc
*crtc
= NULL
;
10295 struct drm_device
*dev
= encoder
->dev
;
10296 struct drm_framebuffer
*fb
;
10297 struct drm_mode_config
*config
= &dev
->mode_config
;
10298 struct drm_atomic_state
*state
= NULL
;
10299 struct drm_connector_state
*connector_state
;
10300 struct intel_crtc_state
*crtc_state
;
10303 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10304 connector
->base
.id
, connector
->name
,
10305 encoder
->base
.id
, encoder
->name
);
10308 ret
= drm_modeset_lock(&config
->connection_mutex
, ctx
);
10313 * Algorithm gets a little messy:
10315 * - if the connector already has an assigned crtc, use it (but make
10316 * sure it's on first)
10318 * - try to find the first unused crtc that can drive this connector,
10319 * and use that if we find one
10322 /* See if we already have a CRTC for this connector */
10323 if (encoder
->crtc
) {
10324 crtc
= encoder
->crtc
;
10326 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10329 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10333 old
->dpms_mode
= connector
->dpms
;
10334 old
->load_detect_temp
= false;
10336 /* Make sure the crtc and connector are running */
10337 if (connector
->dpms
!= DRM_MODE_DPMS_ON
)
10338 connector
->funcs
->dpms(connector
, DRM_MODE_DPMS_ON
);
10343 /* Find an unused one (if possible) */
10344 for_each_crtc(dev
, possible_crtc
) {
10346 if (!(encoder
->possible_crtcs
& (1 << i
)))
10348 if (possible_crtc
->state
->enable
)
10351 crtc
= possible_crtc
;
10356 * If we didn't find an unused CRTC, don't use any.
10359 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10363 ret
= drm_modeset_lock(&crtc
->mutex
, ctx
);
10366 ret
= drm_modeset_lock(&crtc
->primary
->mutex
, ctx
);
10370 intel_crtc
= to_intel_crtc(crtc
);
10371 old
->dpms_mode
= connector
->dpms
;
10372 old
->load_detect_temp
= true;
10373 old
->release_fb
= NULL
;
10375 state
= drm_atomic_state_alloc(dev
);
10379 state
->acquire_ctx
= ctx
;
10381 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10382 if (IS_ERR(connector_state
)) {
10383 ret
= PTR_ERR(connector_state
);
10387 connector_state
->crtc
= crtc
;
10388 connector_state
->best_encoder
= &intel_encoder
->base
;
10390 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10391 if (IS_ERR(crtc_state
)) {
10392 ret
= PTR_ERR(crtc_state
);
10396 crtc_state
->base
.active
= crtc_state
->base
.enable
= true;
10399 mode
= &load_detect_mode
;
10401 /* We need a framebuffer large enough to accommodate all accesses
10402 * that the plane may generate whilst we perform load detection.
10403 * We can not rely on the fbcon either being present (we get called
10404 * during its initialisation to detect all boot displays, or it may
10405 * not even exist) or that it is large enough to satisfy the
10408 fb
= mode_fits_in_fbdev(dev
, mode
);
10410 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10411 fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
10412 old
->release_fb
= fb
;
10414 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10416 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10420 ret
= intel_modeset_setup_plane_state(state
, crtc
, mode
, fb
, 0, 0);
10424 drm_mode_copy(&crtc_state
->base
.mode
, mode
);
10426 if (drm_atomic_commit(state
)) {
10427 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10428 if (old
->release_fb
)
10429 old
->release_fb
->funcs
->destroy(old
->release_fb
);
10432 crtc
->primary
->crtc
= crtc
;
10434 /* let the connector get through one full cycle before testing */
10435 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
10439 drm_atomic_state_free(state
);
10442 if (ret
== -EDEADLK
) {
10443 drm_modeset_backoff(ctx
);
10450 void intel_release_load_detect_pipe(struct drm_connector
*connector
,
10451 struct intel_load_detect_pipe
*old
,
10452 struct drm_modeset_acquire_ctx
*ctx
)
10454 struct drm_device
*dev
= connector
->dev
;
10455 struct intel_encoder
*intel_encoder
=
10456 intel_attached_encoder(connector
);
10457 struct drm_encoder
*encoder
= &intel_encoder
->base
;
10458 struct drm_crtc
*crtc
= encoder
->crtc
;
10459 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10460 struct drm_atomic_state
*state
;
10461 struct drm_connector_state
*connector_state
;
10462 struct intel_crtc_state
*crtc_state
;
10465 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10466 connector
->base
.id
, connector
->name
,
10467 encoder
->base
.id
, encoder
->name
);
10469 if (old
->load_detect_temp
) {
10470 state
= drm_atomic_state_alloc(dev
);
10474 state
->acquire_ctx
= ctx
;
10476 connector_state
= drm_atomic_get_connector_state(state
, connector
);
10477 if (IS_ERR(connector_state
))
10480 crtc_state
= intel_atomic_get_crtc_state(state
, intel_crtc
);
10481 if (IS_ERR(crtc_state
))
10484 connector_state
->best_encoder
= NULL
;
10485 connector_state
->crtc
= NULL
;
10487 crtc_state
->base
.enable
= crtc_state
->base
.active
= false;
10489 ret
= intel_modeset_setup_plane_state(state
, crtc
, NULL
, NULL
,
10494 ret
= drm_atomic_commit(state
);
10498 if (old
->release_fb
) {
10499 drm_framebuffer_unregister_private(old
->release_fb
);
10500 drm_framebuffer_unreference(old
->release_fb
);
10506 /* Switch crtc and encoder back off if necessary */
10507 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
)
10508 connector
->funcs
->dpms(connector
, old
->dpms_mode
);
10512 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10513 drm_atomic_state_free(state
);
10516 static int i9xx_pll_refclk(struct drm_device
*dev
,
10517 const struct intel_crtc_state
*pipe_config
)
10519 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10520 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10522 if ((dpll
& PLL_REF_INPUT_MASK
) == PLLB_REF_INPUT_SPREADSPECTRUMIN
)
10523 return dev_priv
->vbt
.lvds_ssc_freq
;
10524 else if (HAS_PCH_SPLIT(dev
))
10526 else if (!IS_GEN2(dev
))
10532 /* Returns the clock of the currently programmed mode of the given pipe. */
10533 static void i9xx_crtc_clock_get(struct intel_crtc
*crtc
,
10534 struct intel_crtc_state
*pipe_config
)
10536 struct drm_device
*dev
= crtc
->base
.dev
;
10537 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10538 int pipe
= pipe_config
->cpu_transcoder
;
10539 u32 dpll
= pipe_config
->dpll_hw_state
.dpll
;
10541 intel_clock_t clock
;
10543 int refclk
= i9xx_pll_refclk(dev
, pipe_config
);
10545 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
10546 fp
= pipe_config
->dpll_hw_state
.fp0
;
10548 fp
= pipe_config
->dpll_hw_state
.fp1
;
10550 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
10551 if (IS_PINEVIEW(dev
)) {
10552 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
10553 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10555 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
10556 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
10559 if (!IS_GEN2(dev
)) {
10560 if (IS_PINEVIEW(dev
))
10561 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
10562 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
10564 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
10565 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10567 switch (dpll
& DPLL_MODE_MASK
) {
10568 case DPLLB_MODE_DAC_SERIAL
:
10569 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
10572 case DPLLB_MODE_LVDS
:
10573 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
10577 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10578 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
10582 if (IS_PINEVIEW(dev
))
10583 port_clock
= pnv_calc_dpll_params(refclk
, &clock
);
10585 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10587 u32 lvds
= IS_I830(dev
) ? 0 : I915_READ(LVDS
);
10588 bool is_lvds
= (pipe
== 1) && (lvds
& LVDS_PORT_EN
);
10591 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
10592 DPLL_FPA01_P1_POST_DIV_SHIFT
);
10594 if (lvds
& LVDS_CLKB_POWER_UP
)
10599 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
10602 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
10603 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
10605 if (dpll
& PLL_P2_DIVIDE_BY_4
)
10611 port_clock
= i9xx_calc_dpll_params(refclk
, &clock
);
10615 * This value includes pixel_multiplier. We will use
10616 * port_clock to compute adjusted_mode.crtc_clock in the
10617 * encoder's get_config() function.
10619 pipe_config
->port_clock
= port_clock
;
10622 int intel_dotclock_calculate(int link_freq
,
10623 const struct intel_link_m_n
*m_n
)
10626 * The calculation for the data clock is:
10627 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10628 * But we want to avoid losing precison if possible, so:
10629 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10631 * and the link clock is simpler:
10632 * link_clock = (m * link_clock) / n
10638 return div_u64((u64
)m_n
->link_m
* link_freq
, m_n
->link_n
);
10641 static void ironlake_pch_clock_get(struct intel_crtc
*crtc
,
10642 struct intel_crtc_state
*pipe_config
)
10644 struct drm_device
*dev
= crtc
->base
.dev
;
10646 /* read out port_clock from the DPLL */
10647 i9xx_crtc_clock_get(crtc
, pipe_config
);
10650 * This value does not include pixel_multiplier.
10651 * We will check that port_clock and adjusted_mode.crtc_clock
10652 * agree once we know their relationship in the encoder's
10653 * get_config() function.
10655 pipe_config
->base
.adjusted_mode
.crtc_clock
=
10656 intel_dotclock_calculate(intel_fdi_link_freq(dev
) * 10000,
10657 &pipe_config
->fdi_m_n
);
10660 /** Returns the currently programmed mode of the given pipe. */
10661 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
10662 struct drm_crtc
*crtc
)
10664 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10665 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10666 enum transcoder cpu_transcoder
= intel_crtc
->config
->cpu_transcoder
;
10667 struct drm_display_mode
*mode
;
10668 struct intel_crtc_state pipe_config
;
10669 int htot
= I915_READ(HTOTAL(cpu_transcoder
));
10670 int hsync
= I915_READ(HSYNC(cpu_transcoder
));
10671 int vtot
= I915_READ(VTOTAL(cpu_transcoder
));
10672 int vsync
= I915_READ(VSYNC(cpu_transcoder
));
10673 enum pipe pipe
= intel_crtc
->pipe
;
10675 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
10680 * Construct a pipe_config sufficient for getting the clock info
10681 * back out of crtc_clock_get.
10683 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10684 * to use a real value here instead.
10686 pipe_config
.cpu_transcoder
= (enum transcoder
) pipe
;
10687 pipe_config
.pixel_multiplier
= 1;
10688 pipe_config
.dpll_hw_state
.dpll
= I915_READ(DPLL(pipe
));
10689 pipe_config
.dpll_hw_state
.fp0
= I915_READ(FP0(pipe
));
10690 pipe_config
.dpll_hw_state
.fp1
= I915_READ(FP1(pipe
));
10691 i9xx_crtc_clock_get(intel_crtc
, &pipe_config
);
10693 mode
->clock
= pipe_config
.port_clock
/ pipe_config
.pixel_multiplier
;
10694 mode
->hdisplay
= (htot
& 0xffff) + 1;
10695 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
10696 mode
->hsync_start
= (hsync
& 0xffff) + 1;
10697 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
10698 mode
->vdisplay
= (vtot
& 0xffff) + 1;
10699 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
10700 mode
->vsync_start
= (vsync
& 0xffff) + 1;
10701 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
10703 drm_mode_set_name(mode
);
10708 void intel_mark_busy(struct drm_device
*dev
)
10710 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10712 if (dev_priv
->mm
.busy
)
10715 intel_runtime_pm_get(dev_priv
);
10716 i915_update_gfx_val(dev_priv
);
10717 if (INTEL_INFO(dev
)->gen
>= 6)
10718 gen6_rps_busy(dev_priv
);
10719 dev_priv
->mm
.busy
= true;
10722 void intel_mark_idle(struct drm_device
*dev
)
10724 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10726 if (!dev_priv
->mm
.busy
)
10729 dev_priv
->mm
.busy
= false;
10731 if (INTEL_INFO(dev
)->gen
>= 6)
10732 gen6_rps_idle(dev
->dev_private
);
10734 intel_runtime_pm_put(dev_priv
);
10737 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
10739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10740 struct drm_device
*dev
= crtc
->dev
;
10741 struct intel_unpin_work
*work
;
10743 spin_lock_irq(&dev
->event_lock
);
10744 work
= intel_crtc
->unpin_work
;
10745 intel_crtc
->unpin_work
= NULL
;
10746 spin_unlock_irq(&dev
->event_lock
);
10749 cancel_work_sync(&work
->work
);
10753 drm_crtc_cleanup(crtc
);
10758 static void intel_unpin_work_fn(struct work_struct
*__work
)
10760 struct intel_unpin_work
*work
=
10761 container_of(__work
, struct intel_unpin_work
, work
);
10762 struct intel_crtc
*crtc
= to_intel_crtc(work
->crtc
);
10763 struct drm_device
*dev
= crtc
->base
.dev
;
10764 struct drm_plane
*primary
= crtc
->base
.primary
;
10766 mutex_lock(&dev
->struct_mutex
);
10767 intel_unpin_fb_obj(work
->old_fb
, primary
->state
);
10768 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
10770 if (work
->flip_queued_req
)
10771 i915_gem_request_assign(&work
->flip_queued_req
, NULL
);
10772 mutex_unlock(&dev
->struct_mutex
);
10774 intel_frontbuffer_flip_complete(dev
, to_intel_plane(primary
)->frontbuffer_bit
);
10775 drm_framebuffer_unreference(work
->old_fb
);
10777 BUG_ON(atomic_read(&crtc
->unpin_work_count
) == 0);
10778 atomic_dec(&crtc
->unpin_work_count
);
10783 static void do_intel_finish_page_flip(struct drm_device
*dev
,
10784 struct drm_crtc
*crtc
)
10786 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10787 struct intel_unpin_work
*work
;
10788 unsigned long flags
;
10790 /* Ignore early vblank irqs */
10791 if (intel_crtc
== NULL
)
10795 * This is called both by irq handlers and the reset code (to complete
10796 * lost pageflips) so needs the full irqsave spinlocks.
10798 spin_lock_irqsave(&dev
->event_lock
, flags
);
10799 work
= intel_crtc
->unpin_work
;
10801 /* Ensure we don't miss a work->pending update ... */
10804 if (work
== NULL
|| atomic_read(&work
->pending
) < INTEL_FLIP_COMPLETE
) {
10805 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10809 page_flip_completed(intel_crtc
);
10811 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10814 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
10816 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10817 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
10819 do_intel_finish_page_flip(dev
, crtc
);
10822 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
10824 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10825 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
10827 do_intel_finish_page_flip(dev
, crtc
);
10830 /* Is 'a' after or equal to 'b'? */
10831 static bool g4x_flip_count_after_eq(u32 a
, u32 b
)
10833 return !((a
- b
) & 0x80000000);
10836 static bool page_flip_finished(struct intel_crtc
*crtc
)
10838 struct drm_device
*dev
= crtc
->base
.dev
;
10839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10841 if (i915_reset_in_progress(&dev_priv
->gpu_error
) ||
10842 crtc
->reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
))
10846 * The relevant registers doen't exist on pre-ctg.
10847 * As the flip done interrupt doesn't trigger for mmio
10848 * flips on gmch platforms, a flip count check isn't
10849 * really needed there. But since ctg has the registers,
10850 * include it in the check anyway.
10852 if (INTEL_INFO(dev
)->gen
< 5 && !IS_G4X(dev
))
10856 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10857 * used the same base address. In that case the mmio flip might
10858 * have completed, but the CS hasn't even executed the flip yet.
10860 * A flip count check isn't enough as the CS might have updated
10861 * the base address just after start of vblank, but before we
10862 * managed to process the interrupt. This means we'd complete the
10863 * CS flip too soon.
10865 * Combining both checks should get us a good enough result. It may
10866 * still happen that the CS flip has been executed, but has not
10867 * yet actually completed. But in case the base address is the same
10868 * anyway, we don't really care.
10870 return (I915_READ(DSPSURFLIVE(crtc
->plane
)) & ~0xfff) ==
10871 crtc
->unpin_work
->gtt_offset
&&
10872 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc
->pipe
)),
10873 crtc
->unpin_work
->flip_count
);
10876 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
10878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10879 struct intel_crtc
*intel_crtc
=
10880 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
10881 unsigned long flags
;
10885 * This is called both by irq handlers and the reset code (to complete
10886 * lost pageflips) so needs the full irqsave spinlocks.
10888 * NB: An MMIO update of the plane base pointer will also
10889 * generate a page-flip completion irq, i.e. every modeset
10890 * is also accompanied by a spurious intel_prepare_page_flip().
10892 spin_lock_irqsave(&dev
->event_lock
, flags
);
10893 if (intel_crtc
->unpin_work
&& page_flip_finished(intel_crtc
))
10894 atomic_inc_not_zero(&intel_crtc
->unpin_work
->pending
);
10895 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
10898 static inline void intel_mark_page_flip_active(struct intel_unpin_work
*work
)
10900 /* Ensure that the work item is consistent when activating it ... */
10902 atomic_set(&work
->pending
, INTEL_FLIP_PENDING
);
10903 /* and that it is marked active as soon as the irq could fire. */
10907 static int intel_gen2_queue_flip(struct drm_device
*dev
,
10908 struct drm_crtc
*crtc
,
10909 struct drm_framebuffer
*fb
,
10910 struct drm_i915_gem_object
*obj
,
10911 struct drm_i915_gem_request
*req
,
10914 struct intel_engine_cs
*ring
= req
->ring
;
10915 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10919 ret
= intel_ring_begin(req
, 6);
10923 /* Can't queue multiple flips, so wait for the previous
10924 * one to finish before executing the next.
10926 if (intel_crtc
->plane
)
10927 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10929 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10930 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10931 intel_ring_emit(ring
, MI_NOOP
);
10932 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10933 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10934 intel_ring_emit(ring
, fb
->pitches
[0]);
10935 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10936 intel_ring_emit(ring
, 0); /* aux display base address, unused */
10938 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
10942 static int intel_gen3_queue_flip(struct drm_device
*dev
,
10943 struct drm_crtc
*crtc
,
10944 struct drm_framebuffer
*fb
,
10945 struct drm_i915_gem_object
*obj
,
10946 struct drm_i915_gem_request
*req
,
10949 struct intel_engine_cs
*ring
= req
->ring
;
10950 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10954 ret
= intel_ring_begin(req
, 6);
10958 if (intel_crtc
->plane
)
10959 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
10961 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
10962 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
10963 intel_ring_emit(ring
, MI_NOOP
);
10964 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
10965 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10966 intel_ring_emit(ring
, fb
->pitches
[0]);
10967 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
10968 intel_ring_emit(ring
, MI_NOOP
);
10970 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
10974 static int intel_gen4_queue_flip(struct drm_device
*dev
,
10975 struct drm_crtc
*crtc
,
10976 struct drm_framebuffer
*fb
,
10977 struct drm_i915_gem_object
*obj
,
10978 struct drm_i915_gem_request
*req
,
10981 struct intel_engine_cs
*ring
= req
->ring
;
10982 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
10983 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
10984 uint32_t pf
, pipesrc
;
10987 ret
= intel_ring_begin(req
, 4);
10991 /* i965+ uses the linear or tiled offsets from the
10992 * Display Registers (which do not change across a page-flip)
10993 * so we need only reprogram the base address.
10995 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
10996 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
10997 intel_ring_emit(ring
, fb
->pitches
[0]);
10998 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
|
11001 /* XXX Enabling the panel-fitter across page-flip is so far
11002 * untested on non-native modes, so ignore it for now.
11003 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11006 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11007 intel_ring_emit(ring
, pf
| pipesrc
);
11009 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11013 static int intel_gen6_queue_flip(struct drm_device
*dev
,
11014 struct drm_crtc
*crtc
,
11015 struct drm_framebuffer
*fb
,
11016 struct drm_i915_gem_object
*obj
,
11017 struct drm_i915_gem_request
*req
,
11020 struct intel_engine_cs
*ring
= req
->ring
;
11021 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11022 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11023 uint32_t pf
, pipesrc
;
11026 ret
= intel_ring_begin(req
, 4);
11030 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
11031 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
11032 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
11033 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11035 /* Contrary to the suggestions in the documentation,
11036 * "Enable Panel Fitter" does not seem to be required when page
11037 * flipping with a non-native mode, and worse causes a normal
11039 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11042 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
11043 intel_ring_emit(ring
, pf
| pipesrc
);
11045 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11049 static int intel_gen7_queue_flip(struct drm_device
*dev
,
11050 struct drm_crtc
*crtc
,
11051 struct drm_framebuffer
*fb
,
11052 struct drm_i915_gem_object
*obj
,
11053 struct drm_i915_gem_request
*req
,
11056 struct intel_engine_cs
*ring
= req
->ring
;
11057 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11058 uint32_t plane_bit
= 0;
11061 switch (intel_crtc
->plane
) {
11063 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
11066 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
11069 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
11072 WARN_ONCE(1, "unknown plane in flip command\n");
11077 if (ring
->id
== RCS
) {
11080 * On Gen 8, SRM is now taking an extra dword to accommodate
11081 * 48bits addresses, and we need a NOOP for the batch size to
11089 * BSpec MI_DISPLAY_FLIP for IVB:
11090 * "The full packet must be contained within the same cache line."
11092 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11093 * cacheline, if we ever start emitting more commands before
11094 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11095 * then do the cacheline alignment, and finally emit the
11098 ret
= intel_ring_cacheline_align(req
);
11102 ret
= intel_ring_begin(req
, len
);
11106 /* Unmask the flip-done completion message. Note that the bspec says that
11107 * we should do this for both the BCS and RCS, and that we must not unmask
11108 * more than one flip event at any time (or ensure that one flip message
11109 * can be sent by waiting for flip-done prior to queueing new flips).
11110 * Experimentation says that BCS works despite DERRMR masking all
11111 * flip-done completion events and that unmasking all planes at once
11112 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11113 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11115 if (ring
->id
== RCS
) {
11116 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
11117 intel_ring_emit(ring
, DERRMR
);
11118 intel_ring_emit(ring
, ~(DERRMR_PIPEA_PRI_FLIP_DONE
|
11119 DERRMR_PIPEB_PRI_FLIP_DONE
|
11120 DERRMR_PIPEC_PRI_FLIP_DONE
));
11122 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM_GEN8
|
11123 MI_SRM_LRM_GLOBAL_GTT
);
11125 intel_ring_emit(ring
, MI_STORE_REGISTER_MEM
|
11126 MI_SRM_LRM_GLOBAL_GTT
);
11127 intel_ring_emit(ring
, DERRMR
);
11128 intel_ring_emit(ring
, ring
->scratch
.gtt_offset
+ 256);
11129 if (IS_GEN8(dev
)) {
11130 intel_ring_emit(ring
, 0);
11131 intel_ring_emit(ring
, MI_NOOP
);
11135 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
11136 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
11137 intel_ring_emit(ring
, intel_crtc
->unpin_work
->gtt_offset
);
11138 intel_ring_emit(ring
, (MI_NOOP
));
11140 intel_mark_page_flip_active(intel_crtc
->unpin_work
);
11144 static bool use_mmio_flip(struct intel_engine_cs
*ring
,
11145 struct drm_i915_gem_object
*obj
)
11148 * This is not being used for older platforms, because
11149 * non-availability of flip done interrupt forces us to use
11150 * CS flips. Older platforms derive flip done using some clever
11151 * tricks involving the flip_pending status bits and vblank irqs.
11152 * So using MMIO flips there would disrupt this mechanism.
11158 if (INTEL_INFO(ring
->dev
)->gen
< 5)
11161 if (i915
.use_mmio_flip
< 0)
11163 else if (i915
.use_mmio_flip
> 0)
11165 else if (i915
.enable_execlists
)
11168 return ring
!= i915_gem_request_get_ring(obj
->last_write_req
);
11171 static void skl_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11172 struct intel_unpin_work
*work
)
11174 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11176 struct drm_framebuffer
*fb
= intel_crtc
->base
.primary
->fb
;
11177 const enum pipe pipe
= intel_crtc
->pipe
;
11180 ctl
= I915_READ(PLANE_CTL(pipe
, 0));
11181 ctl
&= ~PLANE_CTL_TILED_MASK
;
11182 switch (fb
->modifier
[0]) {
11183 case DRM_FORMAT_MOD_NONE
:
11185 case I915_FORMAT_MOD_X_TILED
:
11186 ctl
|= PLANE_CTL_TILED_X
;
11188 case I915_FORMAT_MOD_Y_TILED
:
11189 ctl
|= PLANE_CTL_TILED_Y
;
11191 case I915_FORMAT_MOD_Yf_TILED
:
11192 ctl
|= PLANE_CTL_TILED_YF
;
11195 MISSING_CASE(fb
->modifier
[0]);
11199 * The stride is either expressed as a multiple of 64 bytes chunks for
11200 * linear buffers or in number of tiles for tiled buffers.
11202 stride
= fb
->pitches
[0] /
11203 intel_fb_stride_alignment(dev
, fb
->modifier
[0],
11207 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11208 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11210 I915_WRITE(PLANE_CTL(pipe
, 0), ctl
);
11211 I915_WRITE(PLANE_STRIDE(pipe
, 0), stride
);
11213 I915_WRITE(PLANE_SURF(pipe
, 0), work
->gtt_offset
);
11214 POSTING_READ(PLANE_SURF(pipe
, 0));
11217 static void ilk_do_mmio_flip(struct intel_crtc
*intel_crtc
,
11218 struct intel_unpin_work
*work
)
11220 struct drm_device
*dev
= intel_crtc
->base
.dev
;
11221 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11222 struct intel_framebuffer
*intel_fb
=
11223 to_intel_framebuffer(intel_crtc
->base
.primary
->fb
);
11224 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
11228 reg
= DSPCNTR(intel_crtc
->plane
);
11229 dspcntr
= I915_READ(reg
);
11231 if (obj
->tiling_mode
!= I915_TILING_NONE
)
11232 dspcntr
|= DISPPLANE_TILED
;
11234 dspcntr
&= ~DISPPLANE_TILED
;
11236 I915_WRITE(reg
, dspcntr
);
11238 I915_WRITE(DSPSURF(intel_crtc
->plane
), work
->gtt_offset
);
11239 POSTING_READ(DSPSURF(intel_crtc
->plane
));
11243 * XXX: This is the temporary way to update the plane registers until we get
11244 * around to using the usual plane update functions for MMIO flips
11246 static void intel_do_mmio_flip(struct intel_mmio_flip
*mmio_flip
)
11248 struct intel_crtc
*crtc
= mmio_flip
->crtc
;
11249 struct intel_unpin_work
*work
;
11251 spin_lock_irq(&crtc
->base
.dev
->event_lock
);
11252 work
= crtc
->unpin_work
;
11253 spin_unlock_irq(&crtc
->base
.dev
->event_lock
);
11257 intel_mark_page_flip_active(work
);
11259 intel_pipe_update_start(crtc
);
11261 if (INTEL_INFO(mmio_flip
->i915
)->gen
>= 9)
11262 skl_do_mmio_flip(crtc
, work
);
11264 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11265 ilk_do_mmio_flip(crtc
, work
);
11267 intel_pipe_update_end(crtc
);
11270 static void intel_mmio_flip_work_func(struct work_struct
*work
)
11272 struct intel_mmio_flip
*mmio_flip
=
11273 container_of(work
, struct intel_mmio_flip
, work
);
11275 if (mmio_flip
->req
) {
11276 WARN_ON(__i915_wait_request(mmio_flip
->req
,
11277 mmio_flip
->crtc
->reset_counter
,
11279 &mmio_flip
->i915
->rps
.mmioflips
));
11280 i915_gem_request_unreference__unlocked(mmio_flip
->req
);
11283 intel_do_mmio_flip(mmio_flip
);
11287 static int intel_queue_mmio_flip(struct drm_device
*dev
,
11288 struct drm_crtc
*crtc
,
11289 struct drm_framebuffer
*fb
,
11290 struct drm_i915_gem_object
*obj
,
11291 struct intel_engine_cs
*ring
,
11294 struct intel_mmio_flip
*mmio_flip
;
11296 mmio_flip
= kmalloc(sizeof(*mmio_flip
), GFP_KERNEL
);
11297 if (mmio_flip
== NULL
)
11300 mmio_flip
->i915
= to_i915(dev
);
11301 mmio_flip
->req
= i915_gem_request_reference(obj
->last_write_req
);
11302 mmio_flip
->crtc
= to_intel_crtc(crtc
);
11304 INIT_WORK(&mmio_flip
->work
, intel_mmio_flip_work_func
);
11305 schedule_work(&mmio_flip
->work
);
11310 static int intel_default_queue_flip(struct drm_device
*dev
,
11311 struct drm_crtc
*crtc
,
11312 struct drm_framebuffer
*fb
,
11313 struct drm_i915_gem_object
*obj
,
11314 struct drm_i915_gem_request
*req
,
11320 static bool __intel_pageflip_stall_check(struct drm_device
*dev
,
11321 struct drm_crtc
*crtc
)
11323 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11324 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11325 struct intel_unpin_work
*work
= intel_crtc
->unpin_work
;
11328 if (atomic_read(&work
->pending
) >= INTEL_FLIP_COMPLETE
)
11331 if (atomic_read(&work
->pending
) < INTEL_FLIP_PENDING
)
11334 if (!work
->enable_stall_check
)
11337 if (work
->flip_ready_vblank
== 0) {
11338 if (work
->flip_queued_req
&&
11339 !i915_gem_request_completed(work
->flip_queued_req
, true))
11342 work
->flip_ready_vblank
= drm_crtc_vblank_count(crtc
);
11345 if (drm_crtc_vblank_count(crtc
) - work
->flip_ready_vblank
< 3)
11348 /* Potential stall - if we see that the flip has happened,
11349 * assume a missed interrupt. */
11350 if (INTEL_INFO(dev
)->gen
>= 4)
11351 addr
= I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc
->plane
)));
11353 addr
= I915_READ(DSPADDR(intel_crtc
->plane
));
11355 /* There is a potential issue here with a false positive after a flip
11356 * to the same address. We could address this by checking for a
11357 * non-incrementing frame counter.
11359 return addr
== work
->gtt_offset
;
11362 void intel_check_page_flip(struct drm_device
*dev
, int pipe
)
11364 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11365 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
11366 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11367 struct intel_unpin_work
*work
;
11369 WARN_ON(!in_interrupt());
11374 spin_lock(&dev
->event_lock
);
11375 work
= intel_crtc
->unpin_work
;
11376 if (work
!= NULL
&& __intel_pageflip_stall_check(dev
, crtc
)) {
11377 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11378 work
->flip_queued_vblank
, drm_vblank_count(dev
, pipe
));
11379 page_flip_completed(intel_crtc
);
11382 if (work
!= NULL
&&
11383 drm_vblank_count(dev
, pipe
) - work
->flip_queued_vblank
> 1)
11384 intel_queue_rps_boost_for_request(dev
, work
->flip_queued_req
);
11385 spin_unlock(&dev
->event_lock
);
11388 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
11389 struct drm_framebuffer
*fb
,
11390 struct drm_pending_vblank_event
*event
,
11391 uint32_t page_flip_flags
)
11393 struct drm_device
*dev
= crtc
->dev
;
11394 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11395 struct drm_framebuffer
*old_fb
= crtc
->primary
->fb
;
11396 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
11397 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11398 struct drm_plane
*primary
= crtc
->primary
;
11399 enum pipe pipe
= intel_crtc
->pipe
;
11400 struct intel_unpin_work
*work
;
11401 struct intel_engine_cs
*ring
;
11403 struct drm_i915_gem_request
*request
= NULL
;
11407 * drm_mode_page_flip_ioctl() should already catch this, but double
11408 * check to be safe. In the future we may enable pageflipping from
11409 * a disabled primary plane.
11411 if (WARN_ON(intel_fb_obj(old_fb
) == NULL
))
11414 /* Can't change pixel format via MI display flips. */
11415 if (fb
->pixel_format
!= crtc
->primary
->fb
->pixel_format
)
11419 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11420 * Note that pitch changes could also affect these register.
11422 if (INTEL_INFO(dev
)->gen
> 3 &&
11423 (fb
->offsets
[0] != crtc
->primary
->fb
->offsets
[0] ||
11424 fb
->pitches
[0] != crtc
->primary
->fb
->pitches
[0]))
11427 if (i915_terminally_wedged(&dev_priv
->gpu_error
))
11430 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
11434 work
->event
= event
;
11436 work
->old_fb
= old_fb
;
11437 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
11439 ret
= drm_crtc_vblank_get(crtc
);
11443 /* We borrow the event spin lock for protecting unpin_work */
11444 spin_lock_irq(&dev
->event_lock
);
11445 if (intel_crtc
->unpin_work
) {
11446 /* Before declaring the flip queue wedged, check if
11447 * the hardware completed the operation behind our backs.
11449 if (__intel_pageflip_stall_check(dev
, crtc
)) {
11450 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11451 page_flip_completed(intel_crtc
);
11453 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11454 spin_unlock_irq(&dev
->event_lock
);
11456 drm_crtc_vblank_put(crtc
);
11461 intel_crtc
->unpin_work
= work
;
11462 spin_unlock_irq(&dev
->event_lock
);
11464 if (atomic_read(&intel_crtc
->unpin_work_count
) >= 2)
11465 flush_workqueue(dev_priv
->wq
);
11467 /* Reference the objects for the scheduled work. */
11468 drm_framebuffer_reference(work
->old_fb
);
11469 drm_gem_object_reference(&obj
->base
);
11471 crtc
->primary
->fb
= fb
;
11472 update_state_fb(crtc
->primary
);
11474 work
->pending_flip_obj
= obj
;
11476 ret
= i915_mutex_lock_interruptible(dev
);
11480 atomic_inc(&intel_crtc
->unpin_work_count
);
11481 intel_crtc
->reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
11483 if (INTEL_INFO(dev
)->gen
>= 5 || IS_G4X(dev
))
11484 work
->flip_count
= I915_READ(PIPE_FLIPCOUNT_G4X(pipe
)) + 1;
11486 if (IS_VALLEYVIEW(dev
)) {
11487 ring
= &dev_priv
->ring
[BCS
];
11488 if (obj
->tiling_mode
!= intel_fb_obj(work
->old_fb
)->tiling_mode
)
11489 /* vlv: DISPLAY_FLIP fails to change tiling */
11491 } else if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
11492 ring
= &dev_priv
->ring
[BCS
];
11493 } else if (INTEL_INFO(dev
)->gen
>= 7) {
11494 ring
= i915_gem_request_get_ring(obj
->last_write_req
);
11495 if (ring
== NULL
|| ring
->id
!= RCS
)
11496 ring
= &dev_priv
->ring
[BCS
];
11498 ring
= &dev_priv
->ring
[RCS
];
11501 mmio_flip
= use_mmio_flip(ring
, obj
);
11503 /* When using CS flips, we want to emit semaphores between rings.
11504 * However, when using mmio flips we will create a task to do the
11505 * synchronisation, so all we want here is to pin the framebuffer
11506 * into the display plane and skip any waits.
11508 ret
= intel_pin_and_fence_fb_obj(crtc
->primary
, fb
,
11509 crtc
->primary
->state
,
11510 mmio_flip
? i915_gem_request_get_ring(obj
->last_write_req
) : ring
, &request
);
11512 goto cleanup_pending
;
11514 work
->gtt_offset
= intel_plane_obj_offset(to_intel_plane(primary
),
11516 work
->gtt_offset
+= intel_crtc
->dspaddr_offset
;
11519 ret
= intel_queue_mmio_flip(dev
, crtc
, fb
, obj
, ring
,
11522 goto cleanup_unpin
;
11524 i915_gem_request_assign(&work
->flip_queued_req
,
11525 obj
->last_write_req
);
11528 ret
= i915_gem_request_alloc(ring
, ring
->default_context
, &request
);
11530 goto cleanup_unpin
;
11533 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
, request
,
11536 goto cleanup_unpin
;
11538 i915_gem_request_assign(&work
->flip_queued_req
, request
);
11542 i915_add_request_no_flush(request
);
11544 work
->flip_queued_vblank
= drm_crtc_vblank_count(crtc
);
11545 work
->enable_stall_check
= true;
11547 i915_gem_track_fb(intel_fb_obj(work
->old_fb
), obj
,
11548 to_intel_plane(primary
)->frontbuffer_bit
);
11549 mutex_unlock(&dev
->struct_mutex
);
11551 intel_fbc_disable_crtc(intel_crtc
);
11552 intel_frontbuffer_flip_prepare(dev
,
11553 to_intel_plane(primary
)->frontbuffer_bit
);
11555 trace_i915_flip_request(intel_crtc
->plane
, obj
);
11560 intel_unpin_fb_obj(fb
, crtc
->primary
->state
);
11563 i915_gem_request_cancel(request
);
11564 atomic_dec(&intel_crtc
->unpin_work_count
);
11565 mutex_unlock(&dev
->struct_mutex
);
11567 crtc
->primary
->fb
= old_fb
;
11568 update_state_fb(crtc
->primary
);
11570 drm_gem_object_unreference_unlocked(&obj
->base
);
11571 drm_framebuffer_unreference(work
->old_fb
);
11573 spin_lock_irq(&dev
->event_lock
);
11574 intel_crtc
->unpin_work
= NULL
;
11575 spin_unlock_irq(&dev
->event_lock
);
11577 drm_crtc_vblank_put(crtc
);
11582 struct drm_atomic_state
*state
;
11583 struct drm_plane_state
*plane_state
;
11586 state
= drm_atomic_state_alloc(dev
);
11589 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
11592 plane_state
= drm_atomic_get_plane_state(state
, primary
);
11593 ret
= PTR_ERR_OR_ZERO(plane_state
);
11595 drm_atomic_set_fb_for_plane(plane_state
, fb
);
11597 ret
= drm_atomic_set_crtc_for_plane(plane_state
, crtc
);
11599 ret
= drm_atomic_commit(state
);
11602 if (ret
== -EDEADLK
) {
11603 drm_modeset_backoff(state
->acquire_ctx
);
11604 drm_atomic_state_clear(state
);
11609 drm_atomic_state_free(state
);
11611 if (ret
== 0 && event
) {
11612 spin_lock_irq(&dev
->event_lock
);
11613 drm_send_vblank_event(dev
, pipe
, event
);
11614 spin_unlock_irq(&dev
->event_lock
);
11622 * intel_wm_need_update - Check whether watermarks need updating
11623 * @plane: drm plane
11624 * @state: new plane state
11626 * Check current plane state versus the new one to determine whether
11627 * watermarks need to be recalculated.
11629 * Returns true or false.
11631 static bool intel_wm_need_update(struct drm_plane
*plane
,
11632 struct drm_plane_state
*state
)
11634 /* Update watermarks on tiling changes. */
11635 if (!plane
->state
->fb
|| !state
->fb
||
11636 plane
->state
->fb
->modifier
[0] != state
->fb
->modifier
[0] ||
11637 plane
->state
->rotation
!= state
->rotation
)
11640 if (plane
->state
->crtc_w
!= state
->crtc_w
)
11646 int intel_plane_atomic_calc_changes(struct drm_crtc_state
*crtc_state
,
11647 struct drm_plane_state
*plane_state
)
11649 struct drm_crtc
*crtc
= crtc_state
->crtc
;
11650 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11651 struct drm_plane
*plane
= plane_state
->plane
;
11652 struct drm_device
*dev
= crtc
->dev
;
11653 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11654 struct intel_plane_state
*old_plane_state
=
11655 to_intel_plane_state(plane
->state
);
11656 int idx
= intel_crtc
->base
.base
.id
, ret
;
11657 int i
= drm_plane_index(plane
);
11658 bool mode_changed
= needs_modeset(crtc_state
);
11659 bool was_crtc_enabled
= crtc
->state
->active
;
11660 bool is_crtc_enabled
= crtc_state
->active
;
11662 bool turn_off
, turn_on
, visible
, was_visible
;
11663 struct drm_framebuffer
*fb
= plane_state
->fb
;
11665 if (crtc_state
&& INTEL_INFO(dev
)->gen
>= 9 &&
11666 plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11667 ret
= skl_update_scaler_plane(
11668 to_intel_crtc_state(crtc_state
),
11669 to_intel_plane_state(plane_state
));
11675 * Disabling a plane is always okay; we just need to update
11676 * fb tracking in a special way since cleanup_fb() won't
11677 * get called by the plane helpers.
11679 if (old_plane_state
->base
.fb
&& !fb
)
11680 intel_crtc
->atomic
.disabled_planes
|= 1 << i
;
11682 was_visible
= old_plane_state
->visible
;
11683 visible
= to_intel_plane_state(plane_state
)->visible
;
11685 if (!was_crtc_enabled
&& WARN_ON(was_visible
))
11686 was_visible
= false;
11688 if (!is_crtc_enabled
&& WARN_ON(visible
))
11691 if (!was_visible
&& !visible
)
11694 turn_off
= was_visible
&& (!visible
|| mode_changed
);
11695 turn_on
= visible
&& (!was_visible
|| mode_changed
);
11697 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx
,
11698 plane
->base
.id
, fb
? fb
->base
.id
: -1);
11700 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11701 plane
->base
.id
, was_visible
, visible
,
11702 turn_off
, turn_on
, mode_changed
);
11705 intel_crtc
->atomic
.update_wm_pre
= true;
11706 /* must disable cxsr around plane enable/disable */
11707 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11708 intel_crtc
->atomic
.disable_cxsr
= true;
11709 /* to potentially re-enable cxsr */
11710 intel_crtc
->atomic
.wait_vblank
= true;
11711 intel_crtc
->atomic
.update_wm_post
= true;
11713 } else if (turn_off
) {
11714 intel_crtc
->atomic
.update_wm_post
= true;
11715 /* must disable cxsr around plane enable/disable */
11716 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
) {
11717 if (is_crtc_enabled
)
11718 intel_crtc
->atomic
.wait_vblank
= true;
11719 intel_crtc
->atomic
.disable_cxsr
= true;
11721 } else if (intel_wm_need_update(plane
, plane_state
)) {
11722 intel_crtc
->atomic
.update_wm_pre
= true;
11725 if (visible
|| was_visible
)
11726 intel_crtc
->atomic
.fb_bits
|=
11727 to_intel_plane(plane
)->frontbuffer_bit
;
11729 switch (plane
->type
) {
11730 case DRM_PLANE_TYPE_PRIMARY
:
11731 intel_crtc
->atomic
.wait_for_flips
= true;
11732 intel_crtc
->atomic
.pre_disable_primary
= turn_off
;
11733 intel_crtc
->atomic
.post_enable_primary
= turn_on
;
11737 * FIXME: Actually if we will still have any other
11738 * plane enabled on the pipe we could let IPS enabled
11739 * still, but for now lets consider that when we make
11740 * primary invisible by setting DSPCNTR to 0 on
11741 * update_primary_plane function IPS needs to be
11744 intel_crtc
->atomic
.disable_ips
= true;
11746 intel_crtc
->atomic
.disable_fbc
= true;
11750 * FBC does not work on some platforms for rotated
11751 * planes, so disable it when rotation is not 0 and
11752 * update it when rotation is set back to 0.
11754 * FIXME: This is redundant with the fbc update done in
11755 * the primary plane enable function except that that
11756 * one is done too late. We eventually need to unify
11761 INTEL_INFO(dev
)->gen
<= 4 && !IS_G4X(dev
) &&
11762 dev_priv
->fbc
.crtc
== intel_crtc
&&
11763 plane_state
->rotation
!= BIT(DRM_ROTATE_0
))
11764 intel_crtc
->atomic
.disable_fbc
= true;
11767 * BDW signals flip done immediately if the plane
11768 * is disabled, even if the plane enable is already
11769 * armed to occur at the next vblank :(
11771 if (turn_on
&& IS_BROADWELL(dev
))
11772 intel_crtc
->atomic
.wait_vblank
= true;
11774 intel_crtc
->atomic
.update_fbc
|= visible
|| mode_changed
;
11776 case DRM_PLANE_TYPE_CURSOR
:
11778 case DRM_PLANE_TYPE_OVERLAY
:
11779 if (turn_off
&& !mode_changed
) {
11780 intel_crtc
->atomic
.wait_vblank
= true;
11781 intel_crtc
->atomic
.update_sprite_watermarks
|=
11788 static bool encoders_cloneable(const struct intel_encoder
*a
,
11789 const struct intel_encoder
*b
)
11791 /* masks could be asymmetric, so check both ways */
11792 return a
== b
|| (a
->cloneable
& (1 << b
->type
) &&
11793 b
->cloneable
& (1 << a
->type
));
11796 static bool check_single_encoder_cloning(struct drm_atomic_state
*state
,
11797 struct intel_crtc
*crtc
,
11798 struct intel_encoder
*encoder
)
11800 struct intel_encoder
*source_encoder
;
11801 struct drm_connector
*connector
;
11802 struct drm_connector_state
*connector_state
;
11805 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11806 if (connector_state
->crtc
!= &crtc
->base
)
11810 to_intel_encoder(connector_state
->best_encoder
);
11811 if (!encoders_cloneable(encoder
, source_encoder
))
11818 static bool check_encoder_cloning(struct drm_atomic_state
*state
,
11819 struct intel_crtc
*crtc
)
11821 struct intel_encoder
*encoder
;
11822 struct drm_connector
*connector
;
11823 struct drm_connector_state
*connector_state
;
11826 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11827 if (connector_state
->crtc
!= &crtc
->base
)
11830 encoder
= to_intel_encoder(connector_state
->best_encoder
);
11831 if (!check_single_encoder_cloning(state
, crtc
, encoder
))
11838 static int intel_crtc_atomic_check(struct drm_crtc
*crtc
,
11839 struct drm_crtc_state
*crtc_state
)
11841 struct drm_device
*dev
= crtc
->dev
;
11842 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
11843 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
11844 struct intel_crtc_state
*pipe_config
=
11845 to_intel_crtc_state(crtc_state
);
11846 struct drm_atomic_state
*state
= crtc_state
->state
;
11848 bool mode_changed
= needs_modeset(crtc_state
);
11850 if (mode_changed
&& !check_encoder_cloning(state
, intel_crtc
)) {
11851 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11855 if (mode_changed
&& !crtc_state
->active
)
11856 intel_crtc
->atomic
.update_wm_post
= true;
11858 if (mode_changed
&& crtc_state
->enable
&&
11859 dev_priv
->display
.crtc_compute_clock
&&
11860 !WARN_ON(pipe_config
->shared_dpll
!= DPLL_ID_PRIVATE
)) {
11861 ret
= dev_priv
->display
.crtc_compute_clock(intel_crtc
,
11868 if (INTEL_INFO(dev
)->gen
>= 9) {
11870 ret
= skl_update_scaler_crtc(pipe_config
);
11873 ret
= intel_atomic_setup_scalers(dev
, intel_crtc
,
11880 static const struct drm_crtc_helper_funcs intel_helper_funcs
= {
11881 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
11882 .load_lut
= intel_crtc_load_lut
,
11883 .atomic_begin
= intel_begin_crtc_commit
,
11884 .atomic_flush
= intel_finish_crtc_commit
,
11885 .atomic_check
= intel_crtc_atomic_check
,
11888 static void intel_modeset_update_connector_atomic_state(struct drm_device
*dev
)
11890 struct intel_connector
*connector
;
11892 for_each_intel_connector(dev
, connector
) {
11893 if (connector
->base
.encoder
) {
11894 connector
->base
.state
->best_encoder
=
11895 connector
->base
.encoder
;
11896 connector
->base
.state
->crtc
=
11897 connector
->base
.encoder
->crtc
;
11899 connector
->base
.state
->best_encoder
= NULL
;
11900 connector
->base
.state
->crtc
= NULL
;
11906 connected_sink_compute_bpp(struct intel_connector
*connector
,
11907 struct intel_crtc_state
*pipe_config
)
11909 int bpp
= pipe_config
->pipe_bpp
;
11911 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11912 connector
->base
.base
.id
,
11913 connector
->base
.name
);
11915 /* Don't use an invalid EDID bpc value */
11916 if (connector
->base
.display_info
.bpc
&&
11917 connector
->base
.display_info
.bpc
* 3 < bpp
) {
11918 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11919 bpp
, connector
->base
.display_info
.bpc
*3);
11920 pipe_config
->pipe_bpp
= connector
->base
.display_info
.bpc
*3;
11923 /* Clamp bpp to 8 on screens without EDID 1.4 */
11924 if (connector
->base
.display_info
.bpc
== 0 && bpp
> 24) {
11925 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11927 pipe_config
->pipe_bpp
= 24;
11932 compute_baseline_pipe_bpp(struct intel_crtc
*crtc
,
11933 struct intel_crtc_state
*pipe_config
)
11935 struct drm_device
*dev
= crtc
->base
.dev
;
11936 struct drm_atomic_state
*state
;
11937 struct drm_connector
*connector
;
11938 struct drm_connector_state
*connector_state
;
11941 if ((IS_G4X(dev
) || IS_VALLEYVIEW(dev
)))
11943 else if (INTEL_INFO(dev
)->gen
>= 5)
11949 pipe_config
->pipe_bpp
= bpp
;
11951 state
= pipe_config
->base
.state
;
11953 /* Clamp display bpp to EDID value */
11954 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
11955 if (connector_state
->crtc
!= &crtc
->base
)
11958 connected_sink_compute_bpp(to_intel_connector(connector
),
11965 static void intel_dump_crtc_timings(const struct drm_display_mode
*mode
)
11967 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11968 "type: 0x%x flags: 0x%x\n",
11970 mode
->crtc_hdisplay
, mode
->crtc_hsync_start
,
11971 mode
->crtc_hsync_end
, mode
->crtc_htotal
,
11972 mode
->crtc_vdisplay
, mode
->crtc_vsync_start
,
11973 mode
->crtc_vsync_end
, mode
->crtc_vtotal
, mode
->type
, mode
->flags
);
11976 static void intel_dump_pipe_config(struct intel_crtc
*crtc
,
11977 struct intel_crtc_state
*pipe_config
,
11978 const char *context
)
11980 struct drm_device
*dev
= crtc
->base
.dev
;
11981 struct drm_plane
*plane
;
11982 struct intel_plane
*intel_plane
;
11983 struct intel_plane_state
*state
;
11984 struct drm_framebuffer
*fb
;
11986 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc
->base
.base
.id
,
11987 context
, pipe_config
, pipe_name(crtc
->pipe
));
11989 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config
->cpu_transcoder
));
11990 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11991 pipe_config
->pipe_bpp
, pipe_config
->dither
);
11992 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11993 pipe_config
->has_pch_encoder
,
11994 pipe_config
->fdi_lanes
,
11995 pipe_config
->fdi_m_n
.gmch_m
, pipe_config
->fdi_m_n
.gmch_n
,
11996 pipe_config
->fdi_m_n
.link_m
, pipe_config
->fdi_m_n
.link_n
,
11997 pipe_config
->fdi_m_n
.tu
);
11998 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11999 pipe_config
->has_dp_encoder
,
12000 pipe_config
->lane_count
,
12001 pipe_config
->dp_m_n
.gmch_m
, pipe_config
->dp_m_n
.gmch_n
,
12002 pipe_config
->dp_m_n
.link_m
, pipe_config
->dp_m_n
.link_n
,
12003 pipe_config
->dp_m_n
.tu
);
12005 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12006 pipe_config
->has_dp_encoder
,
12007 pipe_config
->lane_count
,
12008 pipe_config
->dp_m2_n2
.gmch_m
,
12009 pipe_config
->dp_m2_n2
.gmch_n
,
12010 pipe_config
->dp_m2_n2
.link_m
,
12011 pipe_config
->dp_m2_n2
.link_n
,
12012 pipe_config
->dp_m2_n2
.tu
);
12014 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12015 pipe_config
->has_audio
,
12016 pipe_config
->has_infoframe
);
12018 DRM_DEBUG_KMS("requested mode:\n");
12019 drm_mode_debug_printmodeline(&pipe_config
->base
.mode
);
12020 DRM_DEBUG_KMS("adjusted mode:\n");
12021 drm_mode_debug_printmodeline(&pipe_config
->base
.adjusted_mode
);
12022 intel_dump_crtc_timings(&pipe_config
->base
.adjusted_mode
);
12023 DRM_DEBUG_KMS("port clock: %d\n", pipe_config
->port_clock
);
12024 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12025 pipe_config
->pipe_src_w
, pipe_config
->pipe_src_h
);
12026 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12028 pipe_config
->scaler_state
.scaler_users
,
12029 pipe_config
->scaler_state
.scaler_id
);
12030 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12031 pipe_config
->gmch_pfit
.control
,
12032 pipe_config
->gmch_pfit
.pgm_ratios
,
12033 pipe_config
->gmch_pfit
.lvds_border_bits
);
12034 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12035 pipe_config
->pch_pfit
.pos
,
12036 pipe_config
->pch_pfit
.size
,
12037 pipe_config
->pch_pfit
.enabled
? "enabled" : "disabled");
12038 DRM_DEBUG_KMS("ips: %i\n", pipe_config
->ips_enabled
);
12039 DRM_DEBUG_KMS("double wide: %i\n", pipe_config
->double_wide
);
12041 if (IS_BROXTON(dev
)) {
12042 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12043 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12044 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12045 pipe_config
->ddi_pll_sel
,
12046 pipe_config
->dpll_hw_state
.ebb0
,
12047 pipe_config
->dpll_hw_state
.ebb4
,
12048 pipe_config
->dpll_hw_state
.pll0
,
12049 pipe_config
->dpll_hw_state
.pll1
,
12050 pipe_config
->dpll_hw_state
.pll2
,
12051 pipe_config
->dpll_hw_state
.pll3
,
12052 pipe_config
->dpll_hw_state
.pll6
,
12053 pipe_config
->dpll_hw_state
.pll8
,
12054 pipe_config
->dpll_hw_state
.pll9
,
12055 pipe_config
->dpll_hw_state
.pll10
,
12056 pipe_config
->dpll_hw_state
.pcsdw12
);
12057 } else if (IS_SKYLAKE(dev
)) {
12058 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12059 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12060 pipe_config
->ddi_pll_sel
,
12061 pipe_config
->dpll_hw_state
.ctrl1
,
12062 pipe_config
->dpll_hw_state
.cfgcr1
,
12063 pipe_config
->dpll_hw_state
.cfgcr2
);
12064 } else if (HAS_DDI(dev
)) {
12065 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12066 pipe_config
->ddi_pll_sel
,
12067 pipe_config
->dpll_hw_state
.wrpll
,
12068 pipe_config
->dpll_hw_state
.spll
);
12070 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12071 "fp0: 0x%x, fp1: 0x%x\n",
12072 pipe_config
->dpll_hw_state
.dpll
,
12073 pipe_config
->dpll_hw_state
.dpll_md
,
12074 pipe_config
->dpll_hw_state
.fp0
,
12075 pipe_config
->dpll_hw_state
.fp1
);
12078 DRM_DEBUG_KMS("planes on this crtc\n");
12079 list_for_each_entry(plane
, &dev
->mode_config
.plane_list
, head
) {
12080 intel_plane
= to_intel_plane(plane
);
12081 if (intel_plane
->pipe
!= crtc
->pipe
)
12084 state
= to_intel_plane_state(plane
->state
);
12085 fb
= state
->base
.fb
;
12087 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12088 "disabled, scaler_id = %d\n",
12089 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12090 plane
->base
.id
, intel_plane
->pipe
,
12091 (crtc
->base
.primary
== plane
) ? 0 : intel_plane
->plane
+ 1,
12092 drm_plane_index(plane
), state
->scaler_id
);
12096 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12097 plane
->type
== DRM_PLANE_TYPE_CURSOR
? "CURSOR" : "STANDARD",
12098 plane
->base
.id
, intel_plane
->pipe
,
12099 crtc
->base
.primary
== plane
? 0 : intel_plane
->plane
+ 1,
12100 drm_plane_index(plane
));
12101 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12102 fb
->base
.id
, fb
->width
, fb
->height
, fb
->pixel_format
);
12103 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12105 state
->src
.x1
>> 16, state
->src
.y1
>> 16,
12106 drm_rect_width(&state
->src
) >> 16,
12107 drm_rect_height(&state
->src
) >> 16,
12108 state
->dst
.x1
, state
->dst
.y1
,
12109 drm_rect_width(&state
->dst
), drm_rect_height(&state
->dst
));
12113 static bool check_digital_port_conflicts(struct drm_atomic_state
*state
)
12115 struct drm_device
*dev
= state
->dev
;
12116 struct intel_encoder
*encoder
;
12117 struct drm_connector
*connector
;
12118 struct drm_connector_state
*connector_state
;
12119 unsigned int used_ports
= 0;
12123 * Walk the connector list instead of the encoder
12124 * list to detect the problem on ddi platforms
12125 * where there's just one encoder per digital port.
12127 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12128 if (!connector_state
->best_encoder
)
12131 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12133 WARN_ON(!connector_state
->crtc
);
12135 switch (encoder
->type
) {
12136 unsigned int port_mask
;
12137 case INTEL_OUTPUT_UNKNOWN
:
12138 if (WARN_ON(!HAS_DDI(dev
)))
12140 case INTEL_OUTPUT_DISPLAYPORT
:
12141 case INTEL_OUTPUT_HDMI
:
12142 case INTEL_OUTPUT_EDP
:
12143 port_mask
= 1 << enc_to_dig_port(&encoder
->base
)->port
;
12145 /* the same port mustn't appear more than once */
12146 if (used_ports
& port_mask
)
12149 used_ports
|= port_mask
;
12159 clear_intel_crtc_state(struct intel_crtc_state
*crtc_state
)
12161 struct drm_crtc_state tmp_state
;
12162 struct intel_crtc_scaler_state scaler_state
;
12163 struct intel_dpll_hw_state dpll_hw_state
;
12164 enum intel_dpll_id shared_dpll
;
12165 uint32_t ddi_pll_sel
;
12168 /* FIXME: before the switch to atomic started, a new pipe_config was
12169 * kzalloc'd. Code that depends on any field being zero should be
12170 * fixed, so that the crtc_state can be safely duplicated. For now,
12171 * only fields that are know to not cause problems are preserved. */
12173 tmp_state
= crtc_state
->base
;
12174 scaler_state
= crtc_state
->scaler_state
;
12175 shared_dpll
= crtc_state
->shared_dpll
;
12176 dpll_hw_state
= crtc_state
->dpll_hw_state
;
12177 ddi_pll_sel
= crtc_state
->ddi_pll_sel
;
12178 force_thru
= crtc_state
->pch_pfit
.force_thru
;
12180 memset(crtc_state
, 0, sizeof *crtc_state
);
12182 crtc_state
->base
= tmp_state
;
12183 crtc_state
->scaler_state
= scaler_state
;
12184 crtc_state
->shared_dpll
= shared_dpll
;
12185 crtc_state
->dpll_hw_state
= dpll_hw_state
;
12186 crtc_state
->ddi_pll_sel
= ddi_pll_sel
;
12187 crtc_state
->pch_pfit
.force_thru
= force_thru
;
12191 intel_modeset_pipe_config(struct drm_crtc
*crtc
,
12192 struct intel_crtc_state
*pipe_config
)
12194 struct drm_atomic_state
*state
= pipe_config
->base
.state
;
12195 struct intel_encoder
*encoder
;
12196 struct drm_connector
*connector
;
12197 struct drm_connector_state
*connector_state
;
12198 int base_bpp
, ret
= -EINVAL
;
12202 clear_intel_crtc_state(pipe_config
);
12204 pipe_config
->cpu_transcoder
=
12205 (enum transcoder
) to_intel_crtc(crtc
)->pipe
;
12208 * Sanitize sync polarity flags based on requested ones. If neither
12209 * positive or negative polarity is requested, treat this as meaning
12210 * negative polarity.
12212 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12213 (DRM_MODE_FLAG_PHSYNC
| DRM_MODE_FLAG_NHSYNC
)))
12214 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NHSYNC
;
12216 if (!(pipe_config
->base
.adjusted_mode
.flags
&
12217 (DRM_MODE_FLAG_PVSYNC
| DRM_MODE_FLAG_NVSYNC
)))
12218 pipe_config
->base
.adjusted_mode
.flags
|= DRM_MODE_FLAG_NVSYNC
;
12220 base_bpp
= compute_baseline_pipe_bpp(to_intel_crtc(crtc
),
12226 * Determine the real pipe dimensions. Note that stereo modes can
12227 * increase the actual pipe size due to the frame doubling and
12228 * insertion of additional space for blanks between the frame. This
12229 * is stored in the crtc timings. We use the requested mode to do this
12230 * computation to clearly distinguish it from the adjusted mode, which
12231 * can be changed by the connectors in the below retry loop.
12233 drm_crtc_get_hv_timing(&pipe_config
->base
.mode
,
12234 &pipe_config
->pipe_src_w
,
12235 &pipe_config
->pipe_src_h
);
12238 /* Ensure the port clock defaults are reset when retrying. */
12239 pipe_config
->port_clock
= 0;
12240 pipe_config
->pixel_multiplier
= 1;
12242 /* Fill in default crtc timings, allow encoders to overwrite them. */
12243 drm_mode_set_crtcinfo(&pipe_config
->base
.adjusted_mode
,
12244 CRTC_STEREO_DOUBLE
);
12246 /* Pass our mode to the connectors and the CRTC to give them a chance to
12247 * adjust it according to limitations or connector properties, and also
12248 * a chance to reject the mode entirely.
12250 for_each_connector_in_state(state
, connector
, connector_state
, i
) {
12251 if (connector_state
->crtc
!= crtc
)
12254 encoder
= to_intel_encoder(connector_state
->best_encoder
);
12256 if (!(encoder
->compute_config(encoder
, pipe_config
))) {
12257 DRM_DEBUG_KMS("Encoder config failure\n");
12262 /* Set default port clock if not overwritten by the encoder. Needs to be
12263 * done afterwards in case the encoder adjusts the mode. */
12264 if (!pipe_config
->port_clock
)
12265 pipe_config
->port_clock
= pipe_config
->base
.adjusted_mode
.crtc_clock
12266 * pipe_config
->pixel_multiplier
;
12268 ret
= intel_crtc_compute_config(to_intel_crtc(crtc
), pipe_config
);
12270 DRM_DEBUG_KMS("CRTC fixup failed\n");
12274 if (ret
== RETRY
) {
12275 if (WARN(!retry
, "loop in pipe configuration computation\n")) {
12280 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12282 goto encoder_retry
;
12285 /* Dithering seems to not pass-through bits correctly when it should, so
12286 * only enable it on 6bpc panels. */
12287 pipe_config
->dither
= pipe_config
->pipe_bpp
== 6*3;
12288 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12289 base_bpp
, pipe_config
->pipe_bpp
, pipe_config
->dither
);
12296 intel_modeset_update_crtc_state(struct drm_atomic_state
*state
)
12298 struct drm_crtc
*crtc
;
12299 struct drm_crtc_state
*crtc_state
;
12302 /* Double check state. */
12303 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12304 to_intel_crtc(crtc
)->config
= to_intel_crtc_state(crtc
->state
);
12306 /* Update hwmode for vblank functions */
12307 if (crtc
->state
->active
)
12308 crtc
->hwmode
= crtc
->state
->adjusted_mode
;
12310 crtc
->hwmode
.crtc_clock
= 0;
12314 static bool intel_fuzzy_clock_check(int clock1
, int clock2
)
12318 if (clock1
== clock2
)
12321 if (!clock1
|| !clock2
)
12324 diff
= abs(clock1
- clock2
);
12326 if (((((diff
+ clock1
+ clock2
) * 100)) / (clock1
+ clock2
)) < 105)
12332 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12333 list_for_each_entry((intel_crtc), \
12334 &(dev)->mode_config.crtc_list, \
12336 if (mask & (1 <<(intel_crtc)->pipe))
12339 intel_compare_m_n(unsigned int m
, unsigned int n
,
12340 unsigned int m2
, unsigned int n2
,
12343 if (m
== m2
&& n
== n2
)
12346 if (exact
|| !m
|| !n
|| !m2
|| !n2
)
12349 BUILD_BUG_ON(DATA_LINK_M_N_MASK
> INT_MAX
);
12356 } else if (m
< m2
) {
12363 return m
== m2
&& n
== n2
;
12367 intel_compare_link_m_n(const struct intel_link_m_n
*m_n
,
12368 struct intel_link_m_n
*m2_n2
,
12371 if (m_n
->tu
== m2_n2
->tu
&&
12372 intel_compare_m_n(m_n
->gmch_m
, m_n
->gmch_n
,
12373 m2_n2
->gmch_m
, m2_n2
->gmch_n
, !adjust
) &&
12374 intel_compare_m_n(m_n
->link_m
, m_n
->link_n
,
12375 m2_n2
->link_m
, m2_n2
->link_n
, !adjust
)) {
12386 intel_pipe_config_compare(struct drm_device
*dev
,
12387 struct intel_crtc_state
*current_config
,
12388 struct intel_crtc_state
*pipe_config
,
12393 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12396 DRM_ERROR(fmt, ##__VA_ARGS__); \
12398 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12401 #define PIPE_CONF_CHECK_X(name) \
12402 if (current_config->name != pipe_config->name) { \
12403 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12404 "(expected 0x%08x, found 0x%08x)\n", \
12405 current_config->name, \
12406 pipe_config->name); \
12410 #define PIPE_CONF_CHECK_I(name) \
12411 if (current_config->name != pipe_config->name) { \
12412 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12413 "(expected %i, found %i)\n", \
12414 current_config->name, \
12415 pipe_config->name); \
12419 #define PIPE_CONF_CHECK_M_N(name) \
12420 if (!intel_compare_link_m_n(¤t_config->name, \
12421 &pipe_config->name,\
12423 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12424 "(expected tu %i gmch %i/%i link %i/%i, " \
12425 "found tu %i, gmch %i/%i link %i/%i)\n", \
12426 current_config->name.tu, \
12427 current_config->name.gmch_m, \
12428 current_config->name.gmch_n, \
12429 current_config->name.link_m, \
12430 current_config->name.link_n, \
12431 pipe_config->name.tu, \
12432 pipe_config->name.gmch_m, \
12433 pipe_config->name.gmch_n, \
12434 pipe_config->name.link_m, \
12435 pipe_config->name.link_n); \
12439 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12440 if (!intel_compare_link_m_n(¤t_config->name, \
12441 &pipe_config->name, adjust) && \
12442 !intel_compare_link_m_n(¤t_config->alt_name, \
12443 &pipe_config->name, adjust)) { \
12444 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12445 "(expected tu %i gmch %i/%i link %i/%i, " \
12446 "or tu %i gmch %i/%i link %i/%i, " \
12447 "found tu %i, gmch %i/%i link %i/%i)\n", \
12448 current_config->name.tu, \
12449 current_config->name.gmch_m, \
12450 current_config->name.gmch_n, \
12451 current_config->name.link_m, \
12452 current_config->name.link_n, \
12453 current_config->alt_name.tu, \
12454 current_config->alt_name.gmch_m, \
12455 current_config->alt_name.gmch_n, \
12456 current_config->alt_name.link_m, \
12457 current_config->alt_name.link_n, \
12458 pipe_config->name.tu, \
12459 pipe_config->name.gmch_m, \
12460 pipe_config->name.gmch_n, \
12461 pipe_config->name.link_m, \
12462 pipe_config->name.link_n); \
12466 /* This is required for BDW+ where there is only one set of registers for
12467 * switching between high and low RR.
12468 * This macro can be used whenever a comparison has to be made between one
12469 * hw state and multiple sw state variables.
12471 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12472 if ((current_config->name != pipe_config->name) && \
12473 (current_config->alt_name != pipe_config->name)) { \
12474 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12475 "(expected %i or %i, found %i)\n", \
12476 current_config->name, \
12477 current_config->alt_name, \
12478 pipe_config->name); \
12482 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12483 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12484 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12485 "(expected %i, found %i)\n", \
12486 current_config->name & (mask), \
12487 pipe_config->name & (mask)); \
12491 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12492 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12493 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12494 "(expected %i, found %i)\n", \
12495 current_config->name, \
12496 pipe_config->name); \
12500 #define PIPE_CONF_QUIRK(quirk) \
12501 ((current_config->quirks | pipe_config->quirks) & (quirk))
12503 PIPE_CONF_CHECK_I(cpu_transcoder
);
12505 PIPE_CONF_CHECK_I(has_pch_encoder
);
12506 PIPE_CONF_CHECK_I(fdi_lanes
);
12507 PIPE_CONF_CHECK_M_N(fdi_m_n
);
12509 PIPE_CONF_CHECK_I(has_dp_encoder
);
12510 PIPE_CONF_CHECK_I(lane_count
);
12512 if (INTEL_INFO(dev
)->gen
< 8) {
12513 PIPE_CONF_CHECK_M_N(dp_m_n
);
12515 if (current_config
->has_drrs
)
12516 PIPE_CONF_CHECK_M_N(dp_m2_n2
);
12518 PIPE_CONF_CHECK_M_N_ALT(dp_m_n
, dp_m2_n2
);
12520 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hdisplay
);
12521 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_htotal
);
12522 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_start
);
12523 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hblank_end
);
12524 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_start
);
12525 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_hsync_end
);
12527 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vdisplay
);
12528 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vtotal
);
12529 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_start
);
12530 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vblank_end
);
12531 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_start
);
12532 PIPE_CONF_CHECK_I(base
.adjusted_mode
.crtc_vsync_end
);
12534 PIPE_CONF_CHECK_I(pixel_multiplier
);
12535 PIPE_CONF_CHECK_I(has_hdmi_sink
);
12536 if ((INTEL_INFO(dev
)->gen
< 8 && !IS_HASWELL(dev
)) ||
12537 IS_VALLEYVIEW(dev
))
12538 PIPE_CONF_CHECK_I(limited_color_range
);
12539 PIPE_CONF_CHECK_I(has_infoframe
);
12541 PIPE_CONF_CHECK_I(has_audio
);
12543 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12544 DRM_MODE_FLAG_INTERLACE
);
12546 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS
)) {
12547 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12548 DRM_MODE_FLAG_PHSYNC
);
12549 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12550 DRM_MODE_FLAG_NHSYNC
);
12551 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12552 DRM_MODE_FLAG_PVSYNC
);
12553 PIPE_CONF_CHECK_FLAGS(base
.adjusted_mode
.flags
,
12554 DRM_MODE_FLAG_NVSYNC
);
12557 PIPE_CONF_CHECK_X(gmch_pfit
.control
);
12558 /* pfit ratios are autocomputed by the hw on gen4+ */
12559 if (INTEL_INFO(dev
)->gen
< 4)
12560 PIPE_CONF_CHECK_I(gmch_pfit
.pgm_ratios
);
12561 PIPE_CONF_CHECK_X(gmch_pfit
.lvds_border_bits
);
12564 PIPE_CONF_CHECK_I(pipe_src_w
);
12565 PIPE_CONF_CHECK_I(pipe_src_h
);
12567 PIPE_CONF_CHECK_I(pch_pfit
.enabled
);
12568 if (current_config
->pch_pfit
.enabled
) {
12569 PIPE_CONF_CHECK_X(pch_pfit
.pos
);
12570 PIPE_CONF_CHECK_X(pch_pfit
.size
);
12573 PIPE_CONF_CHECK_I(scaler_state
.scaler_id
);
12576 /* BDW+ don't expose a synchronous way to read the state */
12577 if (IS_HASWELL(dev
))
12578 PIPE_CONF_CHECK_I(ips_enabled
);
12580 PIPE_CONF_CHECK_I(double_wide
);
12582 PIPE_CONF_CHECK_X(ddi_pll_sel
);
12584 PIPE_CONF_CHECK_I(shared_dpll
);
12585 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll
);
12586 PIPE_CONF_CHECK_X(dpll_hw_state
.dpll_md
);
12587 PIPE_CONF_CHECK_X(dpll_hw_state
.fp0
);
12588 PIPE_CONF_CHECK_X(dpll_hw_state
.fp1
);
12589 PIPE_CONF_CHECK_X(dpll_hw_state
.wrpll
);
12590 PIPE_CONF_CHECK_X(dpll_hw_state
.spll
);
12591 PIPE_CONF_CHECK_X(dpll_hw_state
.ctrl1
);
12592 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr1
);
12593 PIPE_CONF_CHECK_X(dpll_hw_state
.cfgcr2
);
12595 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5)
12596 PIPE_CONF_CHECK_I(pipe_bpp
);
12598 PIPE_CONF_CHECK_CLOCK_FUZZY(base
.adjusted_mode
.crtc_clock
);
12599 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock
);
12601 #undef PIPE_CONF_CHECK_X
12602 #undef PIPE_CONF_CHECK_I
12603 #undef PIPE_CONF_CHECK_I_ALT
12604 #undef PIPE_CONF_CHECK_FLAGS
12605 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12606 #undef PIPE_CONF_QUIRK
12607 #undef INTEL_ERR_OR_DBG_KMS
12612 static void check_wm_state(struct drm_device
*dev
)
12614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12615 struct skl_ddb_allocation hw_ddb
, *sw_ddb
;
12616 struct intel_crtc
*intel_crtc
;
12619 if (INTEL_INFO(dev
)->gen
< 9)
12622 skl_ddb_get_hw_state(dev_priv
, &hw_ddb
);
12623 sw_ddb
= &dev_priv
->wm
.skl_hw
.ddb
;
12625 for_each_intel_crtc(dev
, intel_crtc
) {
12626 struct skl_ddb_entry
*hw_entry
, *sw_entry
;
12627 const enum pipe pipe
= intel_crtc
->pipe
;
12629 if (!intel_crtc
->active
)
12633 for_each_plane(dev_priv
, pipe
, plane
) {
12634 hw_entry
= &hw_ddb
.plane
[pipe
][plane
];
12635 sw_entry
= &sw_ddb
->plane
[pipe
][plane
];
12637 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12640 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12641 "(expected (%u,%u), found (%u,%u))\n",
12642 pipe_name(pipe
), plane
+ 1,
12643 sw_entry
->start
, sw_entry
->end
,
12644 hw_entry
->start
, hw_entry
->end
);
12648 hw_entry
= &hw_ddb
.plane
[pipe
][PLANE_CURSOR
];
12649 sw_entry
= &sw_ddb
->plane
[pipe
][PLANE_CURSOR
];
12651 if (skl_ddb_entry_equal(hw_entry
, sw_entry
))
12654 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12655 "(expected (%u,%u), found (%u,%u))\n",
12657 sw_entry
->start
, sw_entry
->end
,
12658 hw_entry
->start
, hw_entry
->end
);
12663 check_connector_state(struct drm_device
*dev
,
12664 struct drm_atomic_state
*old_state
)
12666 struct drm_connector_state
*old_conn_state
;
12667 struct drm_connector
*connector
;
12670 for_each_connector_in_state(old_state
, connector
, old_conn_state
, i
) {
12671 struct drm_encoder
*encoder
= connector
->encoder
;
12672 struct drm_connector_state
*state
= connector
->state
;
12674 /* This also checks the encoder/connector hw state with the
12675 * ->get_hw_state callbacks. */
12676 intel_connector_check_state(to_intel_connector(connector
));
12678 I915_STATE_WARN(state
->best_encoder
!= encoder
,
12679 "connector's atomic encoder doesn't match legacy encoder\n");
12684 check_encoder_state(struct drm_device
*dev
)
12686 struct intel_encoder
*encoder
;
12687 struct intel_connector
*connector
;
12689 for_each_intel_encoder(dev
, encoder
) {
12690 bool enabled
= false;
12693 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12694 encoder
->base
.base
.id
,
12695 encoder
->base
.name
);
12697 for_each_intel_connector(dev
, connector
) {
12698 if (connector
->base
.state
->best_encoder
!= &encoder
->base
)
12702 I915_STATE_WARN(connector
->base
.state
->crtc
!=
12703 encoder
->base
.crtc
,
12704 "connector's crtc doesn't match encoder crtc\n");
12707 I915_STATE_WARN(!!encoder
->base
.crtc
!= enabled
,
12708 "encoder's enabled state mismatch "
12709 "(expected %i, found %i)\n",
12710 !!encoder
->base
.crtc
, enabled
);
12712 if (!encoder
->base
.crtc
) {
12715 active
= encoder
->get_hw_state(encoder
, &pipe
);
12716 I915_STATE_WARN(active
,
12717 "encoder detached but still enabled on pipe %c.\n",
12724 check_crtc_state(struct drm_device
*dev
, struct drm_atomic_state
*old_state
)
12726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12727 struct intel_encoder
*encoder
;
12728 struct drm_crtc_state
*old_crtc_state
;
12729 struct drm_crtc
*crtc
;
12732 for_each_crtc_in_state(old_state
, crtc
, old_crtc_state
, i
) {
12733 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
12734 struct intel_crtc_state
*pipe_config
, *sw_config
;
12737 if (!needs_modeset(crtc
->state
) &&
12738 !to_intel_crtc_state(crtc
->state
)->update_pipe
)
12741 __drm_atomic_helper_crtc_destroy_state(crtc
, old_crtc_state
);
12742 pipe_config
= to_intel_crtc_state(old_crtc_state
);
12743 memset(pipe_config
, 0, sizeof(*pipe_config
));
12744 pipe_config
->base
.crtc
= crtc
;
12745 pipe_config
->base
.state
= old_state
;
12747 DRM_DEBUG_KMS("[CRTC:%d]\n",
12750 active
= dev_priv
->display
.get_pipe_config(intel_crtc
,
12753 /* hw state is inconsistent with the pipe quirk */
12754 if ((intel_crtc
->pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
) ||
12755 (intel_crtc
->pipe
== PIPE_B
&& dev_priv
->quirks
& QUIRK_PIPEB_FORCE
))
12756 active
= crtc
->state
->active
;
12758 I915_STATE_WARN(crtc
->state
->active
!= active
,
12759 "crtc active state doesn't match with hw state "
12760 "(expected %i, found %i)\n", crtc
->state
->active
, active
);
12762 I915_STATE_WARN(intel_crtc
->active
!= crtc
->state
->active
,
12763 "transitional active state does not match atomic hw state "
12764 "(expected %i, found %i)\n", crtc
->state
->active
, intel_crtc
->active
);
12766 for_each_encoder_on_crtc(dev
, crtc
, encoder
) {
12769 active
= encoder
->get_hw_state(encoder
, &pipe
);
12770 I915_STATE_WARN(active
!= crtc
->state
->active
,
12771 "[ENCODER:%i] active %i with crtc active %i\n",
12772 encoder
->base
.base
.id
, active
, crtc
->state
->active
);
12774 I915_STATE_WARN(active
&& intel_crtc
->pipe
!= pipe
,
12775 "Encoder connected to wrong pipe %c\n",
12779 encoder
->get_config(encoder
, pipe_config
);
12782 if (!crtc
->state
->active
)
12785 sw_config
= to_intel_crtc_state(crtc
->state
);
12786 if (!intel_pipe_config_compare(dev
, sw_config
,
12787 pipe_config
, false)) {
12788 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12789 intel_dump_pipe_config(intel_crtc
, pipe_config
,
12791 intel_dump_pipe_config(intel_crtc
, sw_config
,
12798 check_shared_dpll_state(struct drm_device
*dev
)
12800 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
12801 struct intel_crtc
*crtc
;
12802 struct intel_dpll_hw_state dpll_hw_state
;
12805 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
12806 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
12807 int enabled_crtcs
= 0, active_crtcs
= 0;
12810 memset(&dpll_hw_state
, 0, sizeof(dpll_hw_state
));
12812 DRM_DEBUG_KMS("%s\n", pll
->name
);
12814 active
= pll
->get_hw_state(dev_priv
, pll
, &dpll_hw_state
);
12816 I915_STATE_WARN(pll
->active
> hweight32(pll
->config
.crtc_mask
),
12817 "more active pll users than references: %i vs %i\n",
12818 pll
->active
, hweight32(pll
->config
.crtc_mask
));
12819 I915_STATE_WARN(pll
->active
&& !pll
->on
,
12820 "pll in active use but not on in sw tracking\n");
12821 I915_STATE_WARN(pll
->on
&& !pll
->active
,
12822 "pll in on but not on in use in sw tracking\n");
12823 I915_STATE_WARN(pll
->on
!= active
,
12824 "pll on state mismatch (expected %i, found %i)\n",
12827 for_each_intel_crtc(dev
, crtc
) {
12828 if (crtc
->base
.state
->enable
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12830 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
)
12833 I915_STATE_WARN(pll
->active
!= active_crtcs
,
12834 "pll active crtcs mismatch (expected %i, found %i)\n",
12835 pll
->active
, active_crtcs
);
12836 I915_STATE_WARN(hweight32(pll
->config
.crtc_mask
) != enabled_crtcs
,
12837 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12838 hweight32(pll
->config
.crtc_mask
), enabled_crtcs
);
12840 I915_STATE_WARN(pll
->on
&& memcmp(&pll
->config
.hw_state
, &dpll_hw_state
,
12841 sizeof(dpll_hw_state
)),
12842 "pll hw state mismatch\n");
12847 intel_modeset_check_state(struct drm_device
*dev
,
12848 struct drm_atomic_state
*old_state
)
12850 check_wm_state(dev
);
12851 check_connector_state(dev
, old_state
);
12852 check_encoder_state(dev
);
12853 check_crtc_state(dev
, old_state
);
12854 check_shared_dpll_state(dev
);
12857 void ironlake_check_encoder_dotclock(const struct intel_crtc_state
*pipe_config
,
12861 * FDI already provided one idea for the dotclock.
12862 * Yell if the encoder disagrees.
12864 WARN(!intel_fuzzy_clock_check(pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
),
12865 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12866 pipe_config
->base
.adjusted_mode
.crtc_clock
, dotclock
);
12869 static void update_scanline_offset(struct intel_crtc
*crtc
)
12871 struct drm_device
*dev
= crtc
->base
.dev
;
12874 * The scanline counter increments at the leading edge of hsync.
12876 * On most platforms it starts counting from vtotal-1 on the
12877 * first active line. That means the scanline counter value is
12878 * always one less than what we would expect. Ie. just after
12879 * start of vblank, which also occurs at start of hsync (on the
12880 * last active line), the scanline counter will read vblank_start-1.
12882 * On gen2 the scanline counter starts counting from 1 instead
12883 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12884 * to keep the value positive), instead of adding one.
12886 * On HSW+ the behaviour of the scanline counter depends on the output
12887 * type. For DP ports it behaves like most other platforms, but on HDMI
12888 * there's an extra 1 line difference. So we need to add two instead of
12889 * one to the value.
12891 if (IS_GEN2(dev
)) {
12892 const struct drm_display_mode
*adjusted_mode
= &crtc
->config
->base
.adjusted_mode
;
12895 vtotal
= adjusted_mode
->crtc_vtotal
;
12896 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
)
12899 crtc
->scanline_offset
= vtotal
- 1;
12900 } else if (HAS_DDI(dev
) &&
12901 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
)) {
12902 crtc
->scanline_offset
= 2;
12904 crtc
->scanline_offset
= 1;
12907 static void intel_modeset_clear_plls(struct drm_atomic_state
*state
)
12909 struct drm_device
*dev
= state
->dev
;
12910 struct drm_i915_private
*dev_priv
= to_i915(dev
);
12911 struct intel_shared_dpll_config
*shared_dpll
= NULL
;
12912 struct intel_crtc
*intel_crtc
;
12913 struct intel_crtc_state
*intel_crtc_state
;
12914 struct drm_crtc
*crtc
;
12915 struct drm_crtc_state
*crtc_state
;
12918 if (!dev_priv
->display
.crtc_compute_clock
)
12921 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12924 intel_crtc
= to_intel_crtc(crtc
);
12925 intel_crtc_state
= to_intel_crtc_state(crtc_state
);
12926 dpll
= intel_crtc_state
->shared_dpll
;
12928 if (!needs_modeset(crtc_state
) || dpll
== DPLL_ID_PRIVATE
)
12931 intel_crtc_state
->shared_dpll
= DPLL_ID_PRIVATE
;
12934 shared_dpll
= intel_atomic_get_shared_dpll_state(state
);
12936 shared_dpll
[dpll
].crtc_mask
&= ~(1 << intel_crtc
->pipe
);
12941 * This implements the workaround described in the "notes" section of the mode
12942 * set sequence documentation. When going from no pipes or single pipe to
12943 * multiple pipes, and planes are enabled after the pipe, we need to wait at
12944 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
12946 static int haswell_mode_set_planes_workaround(struct drm_atomic_state
*state
)
12948 struct drm_crtc_state
*crtc_state
;
12949 struct intel_crtc
*intel_crtc
;
12950 struct drm_crtc
*crtc
;
12951 struct intel_crtc_state
*first_crtc_state
= NULL
;
12952 struct intel_crtc_state
*other_crtc_state
= NULL
;
12953 enum pipe first_pipe
= INVALID_PIPE
, enabled_pipe
= INVALID_PIPE
;
12956 /* look at all crtc's that are going to be enabled in during modeset */
12957 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
12958 intel_crtc
= to_intel_crtc(crtc
);
12960 if (!crtc_state
->active
|| !needs_modeset(crtc_state
))
12963 if (first_crtc_state
) {
12964 other_crtc_state
= to_intel_crtc_state(crtc_state
);
12967 first_crtc_state
= to_intel_crtc_state(crtc_state
);
12968 first_pipe
= intel_crtc
->pipe
;
12972 /* No workaround needed? */
12973 if (!first_crtc_state
)
12976 /* w/a possibly needed, check how many crtc's are already enabled. */
12977 for_each_intel_crtc(state
->dev
, intel_crtc
) {
12978 struct intel_crtc_state
*pipe_config
;
12980 pipe_config
= intel_atomic_get_crtc_state(state
, intel_crtc
);
12981 if (IS_ERR(pipe_config
))
12982 return PTR_ERR(pipe_config
);
12984 pipe_config
->hsw_workaround_pipe
= INVALID_PIPE
;
12986 if (!pipe_config
->base
.active
||
12987 needs_modeset(&pipe_config
->base
))
12990 /* 2 or more enabled crtcs means no need for w/a */
12991 if (enabled_pipe
!= INVALID_PIPE
)
12994 enabled_pipe
= intel_crtc
->pipe
;
12997 if (enabled_pipe
!= INVALID_PIPE
)
12998 first_crtc_state
->hsw_workaround_pipe
= enabled_pipe
;
12999 else if (other_crtc_state
)
13000 other_crtc_state
->hsw_workaround_pipe
= first_pipe
;
13005 static int intel_modeset_all_pipes(struct drm_atomic_state
*state
)
13007 struct drm_crtc
*crtc
;
13008 struct drm_crtc_state
*crtc_state
;
13011 /* add all active pipes to the state */
13012 for_each_crtc(state
->dev
, crtc
) {
13013 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13014 if (IS_ERR(crtc_state
))
13015 return PTR_ERR(crtc_state
);
13017 if (!crtc_state
->active
|| needs_modeset(crtc_state
))
13020 crtc_state
->mode_changed
= true;
13022 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13026 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13034 static int intel_modeset_checks(struct drm_atomic_state
*state
)
13036 struct drm_device
*dev
= state
->dev
;
13037 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13040 if (!check_digital_port_conflicts(state
)) {
13041 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13046 * See if the config requires any additional preparation, e.g.
13047 * to adjust global state with pipes off. We need to do this
13048 * here so we can get the modeset_pipe updated config for the new
13049 * mode set on this crtc. For other crtcs we need to use the
13050 * adjusted_mode bits in the crtc directly.
13052 if (dev_priv
->display
.modeset_calc_cdclk
) {
13053 unsigned int cdclk
;
13055 ret
= dev_priv
->display
.modeset_calc_cdclk(state
);
13057 cdclk
= to_intel_atomic_state(state
)->cdclk
;
13058 if (!ret
&& cdclk
!= dev_priv
->cdclk_freq
)
13059 ret
= intel_modeset_all_pipes(state
);
13064 to_intel_atomic_state(state
)->cdclk
= dev_priv
->cdclk_freq
;
13066 intel_modeset_clear_plls(state
);
13068 if (IS_HASWELL(dev
))
13069 return haswell_mode_set_planes_workaround(state
);
13075 * intel_atomic_check - validate state object
13077 * @state: state to validate
13079 static int intel_atomic_check(struct drm_device
*dev
,
13080 struct drm_atomic_state
*state
)
13082 struct drm_crtc
*crtc
;
13083 struct drm_crtc_state
*crtc_state
;
13085 bool any_ms
= false;
13087 ret
= drm_atomic_helper_check_modeset(dev
, state
);
13091 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13092 struct intel_crtc_state
*pipe_config
=
13093 to_intel_crtc_state(crtc_state
);
13095 memset(&to_intel_crtc(crtc
)->atomic
, 0,
13096 sizeof(struct intel_crtc_atomic_commit
));
13098 /* Catch I915_MODE_FLAG_INHERITED */
13099 if (crtc_state
->mode
.private_flags
!= crtc
->state
->mode
.private_flags
)
13100 crtc_state
->mode_changed
= true;
13102 if (!crtc_state
->enable
) {
13103 if (needs_modeset(crtc_state
))
13108 if (!needs_modeset(crtc_state
))
13111 /* FIXME: For only active_changed we shouldn't need to do any
13112 * state recomputation at all. */
13114 ret
= drm_atomic_add_affected_connectors(state
, crtc
);
13118 ret
= intel_modeset_pipe_config(crtc
, pipe_config
);
13122 if (i915
.fastboot
&&
13123 intel_pipe_config_compare(state
->dev
,
13124 to_intel_crtc_state(crtc
->state
),
13125 pipe_config
, true)) {
13126 crtc_state
->mode_changed
= false;
13127 to_intel_crtc_state(crtc_state
)->update_pipe
= true;
13130 if (needs_modeset(crtc_state
)) {
13133 ret
= drm_atomic_add_affected_planes(state
, crtc
);
13138 intel_dump_pipe_config(to_intel_crtc(crtc
), pipe_config
,
13139 needs_modeset(crtc_state
) ?
13140 "[modeset]" : "[fastset]");
13144 ret
= intel_modeset_checks(state
);
13149 to_intel_atomic_state(state
)->cdclk
=
13150 to_i915(state
->dev
)->cdclk_freq
;
13152 return drm_atomic_helper_check_planes(state
->dev
, state
);
13156 * intel_atomic_commit - commit validated state object
13158 * @state: the top-level driver state object
13159 * @async: asynchronous commit
13161 * This function commits a top-level state object that has been validated
13162 * with drm_atomic_helper_check().
13164 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13165 * we can only handle plane-related operations and do not yet support
13166 * asynchronous commit.
13169 * Zero for success or -errno.
13171 static int intel_atomic_commit(struct drm_device
*dev
,
13172 struct drm_atomic_state
*state
,
13175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13176 struct drm_crtc
*crtc
;
13177 struct drm_crtc_state
*crtc_state
;
13180 bool any_ms
= false;
13183 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13187 ret
= drm_atomic_helper_prepare_planes(dev
, state
);
13191 drm_atomic_helper_swap_state(dev
, state
);
13193 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13194 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13196 if (!needs_modeset(crtc
->state
))
13200 intel_pre_plane_update(intel_crtc
);
13202 if (crtc_state
->active
) {
13203 intel_crtc_disable_planes(crtc
, crtc_state
->plane_mask
);
13204 dev_priv
->display
.crtc_disable(crtc
);
13205 intel_crtc
->active
= false;
13206 intel_disable_shared_dpll(intel_crtc
);
13210 /* Only after disabling all output pipelines that will be changed can we
13211 * update the the output configuration. */
13212 intel_modeset_update_crtc_state(state
);
13215 intel_shared_dpll_commit(state
);
13217 drm_atomic_helper_update_legacy_modeset_state(state
->dev
, state
);
13218 modeset_update_crtc_power_domains(state
);
13221 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13222 for_each_crtc_in_state(state
, crtc
, crtc_state
, i
) {
13223 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13224 bool modeset
= needs_modeset(crtc
->state
);
13225 bool update_pipe
= !modeset
&&
13226 to_intel_crtc_state(crtc
->state
)->update_pipe
;
13227 unsigned long put_domains
= 0;
13229 if (modeset
&& crtc
->state
->active
) {
13230 update_scanline_offset(to_intel_crtc(crtc
));
13231 dev_priv
->display
.crtc_enable(crtc
);
13235 put_domains
= modeset_get_crtc_power_domains(crtc
);
13237 /* make sure intel_modeset_check_state runs */
13242 intel_pre_plane_update(intel_crtc
);
13244 drm_atomic_helper_commit_planes_on_crtc(crtc_state
);
13247 modeset_put_power_domains(dev_priv
, put_domains
);
13249 intel_post_plane_update(intel_crtc
);
13252 /* FIXME: add subpixel order */
13254 drm_atomic_helper_wait_for_vblanks(dev
, state
);
13255 drm_atomic_helper_cleanup_planes(dev
, state
);
13258 intel_modeset_check_state(dev
, state
);
13260 drm_atomic_state_free(state
);
13265 void intel_crtc_restore_mode(struct drm_crtc
*crtc
)
13267 struct drm_device
*dev
= crtc
->dev
;
13268 struct drm_atomic_state
*state
;
13269 struct drm_crtc_state
*crtc_state
;
13272 state
= drm_atomic_state_alloc(dev
);
13274 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13279 state
->acquire_ctx
= drm_modeset_legacy_acquire_ctx(crtc
);
13282 crtc_state
= drm_atomic_get_crtc_state(state
, crtc
);
13283 ret
= PTR_ERR_OR_ZERO(crtc_state
);
13285 if (!crtc_state
->active
)
13288 crtc_state
->mode_changed
= true;
13289 ret
= drm_atomic_commit(state
);
13292 if (ret
== -EDEADLK
) {
13293 drm_atomic_state_clear(state
);
13294 drm_modeset_backoff(state
->acquire_ctx
);
13300 drm_atomic_state_free(state
);
13303 #undef for_each_intel_crtc_masked
13305 static const struct drm_crtc_funcs intel_crtc_funcs
= {
13306 .gamma_set
= intel_crtc_gamma_set
,
13307 .set_config
= drm_atomic_helper_set_config
,
13308 .destroy
= intel_crtc_destroy
,
13309 .page_flip
= intel_crtc_page_flip
,
13310 .atomic_duplicate_state
= intel_crtc_duplicate_state
,
13311 .atomic_destroy_state
= intel_crtc_destroy_state
,
13314 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private
*dev_priv
,
13315 struct intel_shared_dpll
*pll
,
13316 struct intel_dpll_hw_state
*hw_state
)
13320 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_PLLS
))
13323 val
= I915_READ(PCH_DPLL(pll
->id
));
13324 hw_state
->dpll
= val
;
13325 hw_state
->fp0
= I915_READ(PCH_FP0(pll
->id
));
13326 hw_state
->fp1
= I915_READ(PCH_FP1(pll
->id
));
13328 return val
& DPLL_VCO_ENABLE
;
13331 static void ibx_pch_dpll_mode_set(struct drm_i915_private
*dev_priv
,
13332 struct intel_shared_dpll
*pll
)
13334 I915_WRITE(PCH_FP0(pll
->id
), pll
->config
.hw_state
.fp0
);
13335 I915_WRITE(PCH_FP1(pll
->id
), pll
->config
.hw_state
.fp1
);
13338 static void ibx_pch_dpll_enable(struct drm_i915_private
*dev_priv
,
13339 struct intel_shared_dpll
*pll
)
13341 /* PCH refclock must be enabled first */
13342 ibx_assert_pch_refclk_enabled(dev_priv
);
13344 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13346 /* Wait for the clocks to stabilize. */
13347 POSTING_READ(PCH_DPLL(pll
->id
));
13350 /* The pixel multiplier can only be updated once the
13351 * DPLL is enabled and the clocks are stable.
13353 * So write it again.
13355 I915_WRITE(PCH_DPLL(pll
->id
), pll
->config
.hw_state
.dpll
);
13356 POSTING_READ(PCH_DPLL(pll
->id
));
13360 static void ibx_pch_dpll_disable(struct drm_i915_private
*dev_priv
,
13361 struct intel_shared_dpll
*pll
)
13363 struct drm_device
*dev
= dev_priv
->dev
;
13364 struct intel_crtc
*crtc
;
13366 /* Make sure no transcoder isn't still depending on us. */
13367 for_each_intel_crtc(dev
, crtc
) {
13368 if (intel_crtc_to_shared_dpll(crtc
) == pll
)
13369 assert_pch_transcoder_disabled(dev_priv
, crtc
->pipe
);
13372 I915_WRITE(PCH_DPLL(pll
->id
), 0);
13373 POSTING_READ(PCH_DPLL(pll
->id
));
13377 static char *ibx_pch_dpll_names
[] = {
13382 static void ibx_pch_dpll_init(struct drm_device
*dev
)
13384 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13387 dev_priv
->num_shared_dpll
= 2;
13389 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
13390 dev_priv
->shared_dplls
[i
].id
= i
;
13391 dev_priv
->shared_dplls
[i
].name
= ibx_pch_dpll_names
[i
];
13392 dev_priv
->shared_dplls
[i
].mode_set
= ibx_pch_dpll_mode_set
;
13393 dev_priv
->shared_dplls
[i
].enable
= ibx_pch_dpll_enable
;
13394 dev_priv
->shared_dplls
[i
].disable
= ibx_pch_dpll_disable
;
13395 dev_priv
->shared_dplls
[i
].get_hw_state
=
13396 ibx_pch_dpll_get_hw_state
;
13400 static void intel_shared_dpll_init(struct drm_device
*dev
)
13402 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13405 intel_ddi_pll_init(dev
);
13406 else if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
))
13407 ibx_pch_dpll_init(dev
);
13409 dev_priv
->num_shared_dpll
= 0;
13411 BUG_ON(dev_priv
->num_shared_dpll
> I915_NUM_PLLS
);
13415 * intel_prepare_plane_fb - Prepare fb for usage on plane
13416 * @plane: drm plane to prepare for
13417 * @fb: framebuffer to prepare for presentation
13419 * Prepares a framebuffer for usage on a display plane. Generally this
13420 * involves pinning the underlying object and updating the frontbuffer tracking
13421 * bits. Some older platforms need special physical address handling for
13424 * Returns 0 on success, negative error code on failure.
13427 intel_prepare_plane_fb(struct drm_plane
*plane
,
13428 const struct drm_plane_state
*new_state
)
13430 struct drm_device
*dev
= plane
->dev
;
13431 struct drm_framebuffer
*fb
= new_state
->fb
;
13432 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13433 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13434 struct drm_i915_gem_object
*old_obj
= intel_fb_obj(plane
->fb
);
13440 mutex_lock(&dev
->struct_mutex
);
13442 if (plane
->type
== DRM_PLANE_TYPE_CURSOR
&&
13443 INTEL_INFO(dev
)->cursor_needs_physical
) {
13444 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
13445 ret
= i915_gem_object_attach_phys(obj
, align
);
13447 DRM_DEBUG_KMS("failed to attach phys object\n");
13449 ret
= intel_pin_and_fence_fb_obj(plane
, fb
, new_state
, NULL
, NULL
);
13453 i915_gem_track_fb(old_obj
, obj
, intel_plane
->frontbuffer_bit
);
13455 mutex_unlock(&dev
->struct_mutex
);
13461 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13462 * @plane: drm plane to clean up for
13463 * @fb: old framebuffer that was on plane
13465 * Cleans up a framebuffer that has just been removed from a plane.
13468 intel_cleanup_plane_fb(struct drm_plane
*plane
,
13469 const struct drm_plane_state
*old_state
)
13471 struct drm_device
*dev
= plane
->dev
;
13472 struct drm_i915_gem_object
*obj
= intel_fb_obj(old_state
->fb
);
13477 if (plane
->type
!= DRM_PLANE_TYPE_CURSOR
||
13478 !INTEL_INFO(dev
)->cursor_needs_physical
) {
13479 mutex_lock(&dev
->struct_mutex
);
13480 intel_unpin_fb_obj(old_state
->fb
, old_state
);
13481 mutex_unlock(&dev
->struct_mutex
);
13486 skl_max_scale(struct intel_crtc
*intel_crtc
, struct intel_crtc_state
*crtc_state
)
13489 struct drm_device
*dev
;
13490 struct drm_i915_private
*dev_priv
;
13491 int crtc_clock
, cdclk
;
13493 if (!intel_crtc
|| !crtc_state
)
13494 return DRM_PLANE_HELPER_NO_SCALING
;
13496 dev
= intel_crtc
->base
.dev
;
13497 dev_priv
= dev
->dev_private
;
13498 crtc_clock
= crtc_state
->base
.adjusted_mode
.crtc_clock
;
13499 cdclk
= to_intel_atomic_state(crtc_state
->base
.state
)->cdclk
;
13501 if (!crtc_clock
|| !cdclk
)
13502 return DRM_PLANE_HELPER_NO_SCALING
;
13505 * skl max scale is lower of:
13506 * close to 3 but not 3, -1 is for that purpose
13510 max_scale
= min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk
<< 8) / crtc_clock
));
13516 intel_check_primary_plane(struct drm_plane
*plane
,
13517 struct intel_crtc_state
*crtc_state
,
13518 struct intel_plane_state
*state
)
13520 struct drm_crtc
*crtc
= state
->base
.crtc
;
13521 struct drm_framebuffer
*fb
= state
->base
.fb
;
13522 int min_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13523 int max_scale
= DRM_PLANE_HELPER_NO_SCALING
;
13524 bool can_position
= false;
13526 /* use scaler when colorkey is not required */
13527 if (INTEL_INFO(plane
->dev
)->gen
>= 9 &&
13528 state
->ckey
.flags
== I915_SET_COLORKEY_NONE
) {
13530 max_scale
= skl_max_scale(to_intel_crtc(crtc
), crtc_state
);
13531 can_position
= true;
13534 return drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13535 &state
->dst
, &state
->clip
,
13536 min_scale
, max_scale
,
13537 can_position
, true,
13542 intel_commit_primary_plane(struct drm_plane
*plane
,
13543 struct intel_plane_state
*state
)
13545 struct drm_crtc
*crtc
= state
->base
.crtc
;
13546 struct drm_framebuffer
*fb
= state
->base
.fb
;
13547 struct drm_device
*dev
= plane
->dev
;
13548 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13549 struct intel_crtc
*intel_crtc
;
13550 struct drm_rect
*src
= &state
->src
;
13552 crtc
= crtc
? crtc
: plane
->crtc
;
13553 intel_crtc
= to_intel_crtc(crtc
);
13556 crtc
->x
= src
->x1
>> 16;
13557 crtc
->y
= src
->y1
>> 16;
13559 if (!crtc
->state
->active
)
13562 dev_priv
->display
.update_primary_plane(crtc
, fb
,
13563 state
->src
.x1
>> 16,
13564 state
->src
.y1
>> 16);
13568 intel_disable_primary_plane(struct drm_plane
*plane
,
13569 struct drm_crtc
*crtc
)
13571 struct drm_device
*dev
= plane
->dev
;
13572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13574 dev_priv
->display
.update_primary_plane(crtc
, NULL
, 0, 0);
13577 static void intel_begin_crtc_commit(struct drm_crtc
*crtc
,
13578 struct drm_crtc_state
*old_crtc_state
)
13580 struct drm_device
*dev
= crtc
->dev
;
13581 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13582 struct intel_crtc_state
*old_intel_state
=
13583 to_intel_crtc_state(old_crtc_state
);
13584 bool modeset
= needs_modeset(crtc
->state
);
13586 if (intel_crtc
->atomic
.update_wm_pre
)
13587 intel_update_watermarks(crtc
);
13589 /* Perform vblank evasion around commit operation */
13590 if (crtc
->state
->active
)
13591 intel_pipe_update_start(intel_crtc
);
13596 if (to_intel_crtc_state(crtc
->state
)->update_pipe
)
13597 intel_update_pipe_config(intel_crtc
, old_intel_state
);
13598 else if (INTEL_INFO(dev
)->gen
>= 9)
13599 skl_detach_scalers(intel_crtc
);
13602 static void intel_finish_crtc_commit(struct drm_crtc
*crtc
,
13603 struct drm_crtc_state
*old_crtc_state
)
13605 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
13607 if (crtc
->state
->active
)
13608 intel_pipe_update_end(intel_crtc
);
13612 * intel_plane_destroy - destroy a plane
13613 * @plane: plane to destroy
13615 * Common destruction function for all types of planes (primary, cursor,
13618 void intel_plane_destroy(struct drm_plane
*plane
)
13620 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
13621 drm_plane_cleanup(plane
);
13622 kfree(intel_plane
);
13625 const struct drm_plane_funcs intel_plane_funcs
= {
13626 .update_plane
= drm_atomic_helper_update_plane
,
13627 .disable_plane
= drm_atomic_helper_disable_plane
,
13628 .destroy
= intel_plane_destroy
,
13629 .set_property
= drm_atomic_helper_plane_set_property
,
13630 .atomic_get_property
= intel_plane_atomic_get_property
,
13631 .atomic_set_property
= intel_plane_atomic_set_property
,
13632 .atomic_duplicate_state
= intel_plane_duplicate_state
,
13633 .atomic_destroy_state
= intel_plane_destroy_state
,
13637 static struct drm_plane
*intel_primary_plane_create(struct drm_device
*dev
,
13640 struct intel_plane
*primary
;
13641 struct intel_plane_state
*state
;
13642 const uint32_t *intel_primary_formats
;
13643 unsigned int num_formats
;
13645 primary
= kzalloc(sizeof(*primary
), GFP_KERNEL
);
13646 if (primary
== NULL
)
13649 state
= intel_create_plane_state(&primary
->base
);
13654 primary
->base
.state
= &state
->base
;
13656 primary
->can_scale
= false;
13657 primary
->max_downscale
= 1;
13658 if (INTEL_INFO(dev
)->gen
>= 9) {
13659 primary
->can_scale
= true;
13660 state
->scaler_id
= -1;
13662 primary
->pipe
= pipe
;
13663 primary
->plane
= pipe
;
13664 primary
->frontbuffer_bit
= INTEL_FRONTBUFFER_PRIMARY(pipe
);
13665 primary
->check_plane
= intel_check_primary_plane
;
13666 primary
->commit_plane
= intel_commit_primary_plane
;
13667 primary
->disable_plane
= intel_disable_primary_plane
;
13668 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4)
13669 primary
->plane
= !pipe
;
13671 if (INTEL_INFO(dev
)->gen
>= 9) {
13672 intel_primary_formats
= skl_primary_formats
;
13673 num_formats
= ARRAY_SIZE(skl_primary_formats
);
13674 } else if (INTEL_INFO(dev
)->gen
>= 4) {
13675 intel_primary_formats
= i965_primary_formats
;
13676 num_formats
= ARRAY_SIZE(i965_primary_formats
);
13678 intel_primary_formats
= i8xx_primary_formats
;
13679 num_formats
= ARRAY_SIZE(i8xx_primary_formats
);
13682 drm_universal_plane_init(dev
, &primary
->base
, 0,
13683 &intel_plane_funcs
,
13684 intel_primary_formats
, num_formats
,
13685 DRM_PLANE_TYPE_PRIMARY
);
13687 if (INTEL_INFO(dev
)->gen
>= 4)
13688 intel_create_rotation_property(dev
, primary
);
13690 drm_plane_helper_add(&primary
->base
, &intel_plane_helper_funcs
);
13692 return &primary
->base
;
13695 void intel_create_rotation_property(struct drm_device
*dev
, struct intel_plane
*plane
)
13697 if (!dev
->mode_config
.rotation_property
) {
13698 unsigned long flags
= BIT(DRM_ROTATE_0
) |
13699 BIT(DRM_ROTATE_180
);
13701 if (INTEL_INFO(dev
)->gen
>= 9)
13702 flags
|= BIT(DRM_ROTATE_90
) | BIT(DRM_ROTATE_270
);
13704 dev
->mode_config
.rotation_property
=
13705 drm_mode_create_rotation_property(dev
, flags
);
13707 if (dev
->mode_config
.rotation_property
)
13708 drm_object_attach_property(&plane
->base
.base
,
13709 dev
->mode_config
.rotation_property
,
13710 plane
->base
.state
->rotation
);
13714 intel_check_cursor_plane(struct drm_plane
*plane
,
13715 struct intel_crtc_state
*crtc_state
,
13716 struct intel_plane_state
*state
)
13718 struct drm_crtc
*crtc
= crtc_state
->base
.crtc
;
13719 struct drm_framebuffer
*fb
= state
->base
.fb
;
13720 struct drm_i915_gem_object
*obj
= intel_fb_obj(fb
);
13724 ret
= drm_plane_helper_check_update(plane
, crtc
, fb
, &state
->src
,
13725 &state
->dst
, &state
->clip
,
13726 DRM_PLANE_HELPER_NO_SCALING
,
13727 DRM_PLANE_HELPER_NO_SCALING
,
13728 true, true, &state
->visible
);
13732 /* if we want to turn off the cursor ignore width and height */
13736 /* Check for which cursor types we support */
13737 if (!cursor_size_ok(plane
->dev
, state
->base
.crtc_w
, state
->base
.crtc_h
)) {
13738 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13739 state
->base
.crtc_w
, state
->base
.crtc_h
);
13743 stride
= roundup_pow_of_two(state
->base
.crtc_w
) * 4;
13744 if (obj
->base
.size
< stride
* state
->base
.crtc_h
) {
13745 DRM_DEBUG_KMS("buffer is too small\n");
13749 if (fb
->modifier
[0] != DRM_FORMAT_MOD_NONE
) {
13750 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13758 intel_disable_cursor_plane(struct drm_plane
*plane
,
13759 struct drm_crtc
*crtc
)
13761 intel_crtc_update_cursor(crtc
, false);
13765 intel_commit_cursor_plane(struct drm_plane
*plane
,
13766 struct intel_plane_state
*state
)
13768 struct drm_crtc
*crtc
= state
->base
.crtc
;
13769 struct drm_device
*dev
= plane
->dev
;
13770 struct intel_crtc
*intel_crtc
;
13771 struct drm_i915_gem_object
*obj
= intel_fb_obj(state
->base
.fb
);
13774 crtc
= crtc
? crtc
: plane
->crtc
;
13775 intel_crtc
= to_intel_crtc(crtc
);
13777 if (intel_crtc
->cursor_bo
== obj
)
13782 else if (!INTEL_INFO(dev
)->cursor_needs_physical
)
13783 addr
= i915_gem_obj_ggtt_offset(obj
);
13785 addr
= obj
->phys_handle
->busaddr
;
13787 intel_crtc
->cursor_addr
= addr
;
13788 intel_crtc
->cursor_bo
= obj
;
13791 if (crtc
->state
->active
)
13792 intel_crtc_update_cursor(crtc
, state
->visible
);
13795 static struct drm_plane
*intel_cursor_plane_create(struct drm_device
*dev
,
13798 struct intel_plane
*cursor
;
13799 struct intel_plane_state
*state
;
13801 cursor
= kzalloc(sizeof(*cursor
), GFP_KERNEL
);
13802 if (cursor
== NULL
)
13805 state
= intel_create_plane_state(&cursor
->base
);
13810 cursor
->base
.state
= &state
->base
;
13812 cursor
->can_scale
= false;
13813 cursor
->max_downscale
= 1;
13814 cursor
->pipe
= pipe
;
13815 cursor
->plane
= pipe
;
13816 cursor
->frontbuffer_bit
= INTEL_FRONTBUFFER_CURSOR(pipe
);
13817 cursor
->check_plane
= intel_check_cursor_plane
;
13818 cursor
->commit_plane
= intel_commit_cursor_plane
;
13819 cursor
->disable_plane
= intel_disable_cursor_plane
;
13821 drm_universal_plane_init(dev
, &cursor
->base
, 0,
13822 &intel_plane_funcs
,
13823 intel_cursor_formats
,
13824 ARRAY_SIZE(intel_cursor_formats
),
13825 DRM_PLANE_TYPE_CURSOR
);
13827 if (INTEL_INFO(dev
)->gen
>= 4) {
13828 if (!dev
->mode_config
.rotation_property
)
13829 dev
->mode_config
.rotation_property
=
13830 drm_mode_create_rotation_property(dev
,
13831 BIT(DRM_ROTATE_0
) |
13832 BIT(DRM_ROTATE_180
));
13833 if (dev
->mode_config
.rotation_property
)
13834 drm_object_attach_property(&cursor
->base
.base
,
13835 dev
->mode_config
.rotation_property
,
13836 state
->base
.rotation
);
13839 if (INTEL_INFO(dev
)->gen
>=9)
13840 state
->scaler_id
= -1;
13842 drm_plane_helper_add(&cursor
->base
, &intel_plane_helper_funcs
);
13844 return &cursor
->base
;
13847 static void skl_init_scalers(struct drm_device
*dev
, struct intel_crtc
*intel_crtc
,
13848 struct intel_crtc_state
*crtc_state
)
13851 struct intel_scaler
*intel_scaler
;
13852 struct intel_crtc_scaler_state
*scaler_state
= &crtc_state
->scaler_state
;
13854 for (i
= 0; i
< intel_crtc
->num_scalers
; i
++) {
13855 intel_scaler
= &scaler_state
->scalers
[i
];
13856 intel_scaler
->in_use
= 0;
13857 intel_scaler
->mode
= PS_SCALER_MODE_DYN
;
13860 scaler_state
->scaler_id
= -1;
13863 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
13865 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
13866 struct intel_crtc
*intel_crtc
;
13867 struct intel_crtc_state
*crtc_state
= NULL
;
13868 struct drm_plane
*primary
= NULL
;
13869 struct drm_plane
*cursor
= NULL
;
13872 intel_crtc
= kzalloc(sizeof(*intel_crtc
), GFP_KERNEL
);
13873 if (intel_crtc
== NULL
)
13876 crtc_state
= kzalloc(sizeof(*crtc_state
), GFP_KERNEL
);
13879 intel_crtc
->config
= crtc_state
;
13880 intel_crtc
->base
.state
= &crtc_state
->base
;
13881 crtc_state
->base
.crtc
= &intel_crtc
->base
;
13883 /* initialize shared scalers */
13884 if (INTEL_INFO(dev
)->gen
>= 9) {
13885 if (pipe
== PIPE_C
)
13886 intel_crtc
->num_scalers
= 1;
13888 intel_crtc
->num_scalers
= SKL_NUM_SCALERS
;
13890 skl_init_scalers(dev
, intel_crtc
, crtc_state
);
13893 primary
= intel_primary_plane_create(dev
, pipe
);
13897 cursor
= intel_cursor_plane_create(dev
, pipe
);
13901 ret
= drm_crtc_init_with_planes(dev
, &intel_crtc
->base
, primary
,
13902 cursor
, &intel_crtc_funcs
);
13906 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
13907 for (i
= 0; i
< 256; i
++) {
13908 intel_crtc
->lut_r
[i
] = i
;
13909 intel_crtc
->lut_g
[i
] = i
;
13910 intel_crtc
->lut_b
[i
] = i
;
13914 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13915 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13917 intel_crtc
->pipe
= pipe
;
13918 intel_crtc
->plane
= pipe
;
13919 if (HAS_FBC(dev
) && INTEL_INFO(dev
)->gen
< 4) {
13920 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13921 intel_crtc
->plane
= !pipe
;
13924 intel_crtc
->cursor_base
= ~0;
13925 intel_crtc
->cursor_cntl
= ~0;
13926 intel_crtc
->cursor_size
= ~0;
13928 intel_crtc
->wm
.cxsr_allowed
= true;
13930 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
13931 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
13932 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
13933 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
13935 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
13937 WARN_ON(drm_crtc_index(&intel_crtc
->base
) != intel_crtc
->pipe
);
13942 drm_plane_cleanup(primary
);
13944 drm_plane_cleanup(cursor
);
13949 enum pipe
intel_get_pipe_from_connector(struct intel_connector
*connector
)
13951 struct drm_encoder
*encoder
= connector
->base
.encoder
;
13952 struct drm_device
*dev
= connector
->base
.dev
;
13954 WARN_ON(!drm_modeset_is_locked(&dev
->mode_config
.connection_mutex
));
13956 if (!encoder
|| WARN_ON(!encoder
->crtc
))
13957 return INVALID_PIPE
;
13959 return to_intel_crtc(encoder
->crtc
)->pipe
;
13962 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
13963 struct drm_file
*file
)
13965 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
13966 struct drm_crtc
*drmmode_crtc
;
13967 struct intel_crtc
*crtc
;
13969 drmmode_crtc
= drm_crtc_find(dev
, pipe_from_crtc_id
->crtc_id
);
13971 if (!drmmode_crtc
) {
13972 DRM_ERROR("no such CRTC id\n");
13976 crtc
= to_intel_crtc(drmmode_crtc
);
13977 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
13982 static int intel_encoder_clones(struct intel_encoder
*encoder
)
13984 struct drm_device
*dev
= encoder
->base
.dev
;
13985 struct intel_encoder
*source_encoder
;
13986 int index_mask
= 0;
13989 for_each_intel_encoder(dev
, source_encoder
) {
13990 if (encoders_cloneable(encoder
, source_encoder
))
13991 index_mask
|= (1 << entry
);
13999 static bool has_edp_a(struct drm_device
*dev
)
14001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14003 if (!IS_MOBILE(dev
))
14006 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
14009 if (IS_GEN5(dev
) && (I915_READ(FUSE_STRAP
) & ILK_eDP_A_DISABLE
))
14015 static bool intel_crt_present(struct drm_device
*dev
)
14017 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14019 if (INTEL_INFO(dev
)->gen
>= 9)
14022 if (IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
))
14025 if (IS_CHERRYVIEW(dev
))
14028 if (IS_VALLEYVIEW(dev
) && !dev_priv
->vbt
.int_crt_support
)
14034 static void intel_setup_outputs(struct drm_device
*dev
)
14036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14037 struct intel_encoder
*encoder
;
14038 bool dpd_is_edp
= false;
14040 intel_lvds_init(dev
);
14042 if (intel_crt_present(dev
))
14043 intel_crt_init(dev
);
14045 if (IS_BROXTON(dev
)) {
14047 * FIXME: Broxton doesn't support port detection via the
14048 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14049 * detect the ports.
14051 intel_ddi_init(dev
, PORT_A
);
14052 intel_ddi_init(dev
, PORT_B
);
14053 intel_ddi_init(dev
, PORT_C
);
14054 } else if (HAS_DDI(dev
)) {
14058 * Haswell uses DDI functions to detect digital outputs.
14059 * On SKL pre-D0 the strap isn't connected, so we assume
14062 found
= I915_READ(DDI_BUF_CTL(PORT_A
)) & DDI_INIT_DISPLAY_DETECTED
;
14063 /* WaIgnoreDDIAStrap: skl */
14064 if (found
|| IS_SKYLAKE(dev
))
14065 intel_ddi_init(dev
, PORT_A
);
14067 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14069 found
= I915_READ(SFUSE_STRAP
);
14071 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
14072 intel_ddi_init(dev
, PORT_B
);
14073 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
14074 intel_ddi_init(dev
, PORT_C
);
14075 if (found
& SFUSE_STRAP_DDID_DETECTED
)
14076 intel_ddi_init(dev
, PORT_D
);
14078 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14080 if (IS_SKYLAKE(dev
) &&
14081 (dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dp
||
14082 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_dvi
||
14083 dev_priv
->vbt
.ddi_port_info
[PORT_E
].supports_hdmi
))
14084 intel_ddi_init(dev
, PORT_E
);
14086 } else if (HAS_PCH_SPLIT(dev
)) {
14088 dpd_is_edp
= intel_dp_is_edp(dev
, PORT_D
);
14090 if (has_edp_a(dev
))
14091 intel_dp_init(dev
, DP_A
, PORT_A
);
14093 if (I915_READ(PCH_HDMIB
) & SDVO_DETECTED
) {
14094 /* PCH SDVOB multiplex with HDMIB */
14095 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
14097 intel_hdmi_init(dev
, PCH_HDMIB
, PORT_B
);
14098 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
14099 intel_dp_init(dev
, PCH_DP_B
, PORT_B
);
14102 if (I915_READ(PCH_HDMIC
) & SDVO_DETECTED
)
14103 intel_hdmi_init(dev
, PCH_HDMIC
, PORT_C
);
14105 if (!dpd_is_edp
&& I915_READ(PCH_HDMID
) & SDVO_DETECTED
)
14106 intel_hdmi_init(dev
, PCH_HDMID
, PORT_D
);
14108 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
14109 intel_dp_init(dev
, PCH_DP_C
, PORT_C
);
14111 if (I915_READ(PCH_DP_D
) & DP_DETECTED
)
14112 intel_dp_init(dev
, PCH_DP_D
, PORT_D
);
14113 } else if (IS_VALLEYVIEW(dev
)) {
14115 * The DP_DETECTED bit is the latched state of the DDC
14116 * SDA pin at boot. However since eDP doesn't require DDC
14117 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14118 * eDP ports may have been muxed to an alternate function.
14119 * Thus we can't rely on the DP_DETECTED bit alone to detect
14120 * eDP ports. Consult the VBT as well as DP_DETECTED to
14121 * detect eDP ports.
14123 if (I915_READ(VLV_HDMIB
) & SDVO_DETECTED
&&
14124 !intel_dp_is_edp(dev
, PORT_B
))
14125 intel_hdmi_init(dev
, VLV_HDMIB
, PORT_B
);
14126 if (I915_READ(VLV_DP_B
) & DP_DETECTED
||
14127 intel_dp_is_edp(dev
, PORT_B
))
14128 intel_dp_init(dev
, VLV_DP_B
, PORT_B
);
14130 if (I915_READ(VLV_HDMIC
) & SDVO_DETECTED
&&
14131 !intel_dp_is_edp(dev
, PORT_C
))
14132 intel_hdmi_init(dev
, VLV_HDMIC
, PORT_C
);
14133 if (I915_READ(VLV_DP_C
) & DP_DETECTED
||
14134 intel_dp_is_edp(dev
, PORT_C
))
14135 intel_dp_init(dev
, VLV_DP_C
, PORT_C
);
14137 if (IS_CHERRYVIEW(dev
)) {
14138 /* eDP not supported on port D, so don't check VBT */
14139 if (I915_READ(CHV_HDMID
) & SDVO_DETECTED
)
14140 intel_hdmi_init(dev
, CHV_HDMID
, PORT_D
);
14141 if (I915_READ(CHV_DP_D
) & DP_DETECTED
)
14142 intel_dp_init(dev
, CHV_DP_D
, PORT_D
);
14145 intel_dsi_init(dev
);
14146 } else if (!IS_GEN2(dev
) && !IS_PINEVIEW(dev
)) {
14147 bool found
= false;
14149 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14150 DRM_DEBUG_KMS("probing SDVOB\n");
14151 found
= intel_sdvo_init(dev
, GEN3_SDVOB
, true);
14152 if (!found
&& IS_G4X(dev
)) {
14153 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14154 intel_hdmi_init(dev
, GEN4_HDMIB
, PORT_B
);
14157 if (!found
&& IS_G4X(dev
))
14158 intel_dp_init(dev
, DP_B
, PORT_B
);
14161 /* Before G4X SDVOC doesn't have its own detect register */
14163 if (I915_READ(GEN3_SDVOB
) & SDVO_DETECTED
) {
14164 DRM_DEBUG_KMS("probing SDVOC\n");
14165 found
= intel_sdvo_init(dev
, GEN3_SDVOC
, false);
14168 if (!found
&& (I915_READ(GEN3_SDVOC
) & SDVO_DETECTED
)) {
14171 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14172 intel_hdmi_init(dev
, GEN4_HDMIC
, PORT_C
);
14175 intel_dp_init(dev
, DP_C
, PORT_C
);
14179 (I915_READ(DP_D
) & DP_DETECTED
))
14180 intel_dp_init(dev
, DP_D
, PORT_D
);
14181 } else if (IS_GEN2(dev
))
14182 intel_dvo_init(dev
);
14184 if (SUPPORTS_TV(dev
))
14185 intel_tv_init(dev
);
14187 intel_psr_init(dev
);
14189 for_each_intel_encoder(dev
, encoder
) {
14190 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
14191 encoder
->base
.possible_clones
=
14192 intel_encoder_clones(encoder
);
14195 intel_init_pch_refclk(dev
);
14197 drm_helper_move_panel_connectors_to_head(dev
);
14200 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
14202 struct drm_device
*dev
= fb
->dev
;
14203 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14205 drm_framebuffer_cleanup(fb
);
14206 mutex_lock(&dev
->struct_mutex
);
14207 WARN_ON(!intel_fb
->obj
->framebuffer_references
--);
14208 drm_gem_object_unreference(&intel_fb
->obj
->base
);
14209 mutex_unlock(&dev
->struct_mutex
);
14213 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
14214 struct drm_file
*file
,
14215 unsigned int *handle
)
14217 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14218 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14220 if (obj
->userptr
.mm
) {
14221 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14225 return drm_gem_handle_create(file
, &obj
->base
, handle
);
14228 static int intel_user_framebuffer_dirty(struct drm_framebuffer
*fb
,
14229 struct drm_file
*file
,
14230 unsigned flags
, unsigned color
,
14231 struct drm_clip_rect
*clips
,
14232 unsigned num_clips
)
14234 struct drm_device
*dev
= fb
->dev
;
14235 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
14236 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
14238 mutex_lock(&dev
->struct_mutex
);
14239 intel_fb_obj_flush(obj
, false, ORIGIN_DIRTYFB
);
14240 mutex_unlock(&dev
->struct_mutex
);
14245 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
14246 .destroy
= intel_user_framebuffer_destroy
,
14247 .create_handle
= intel_user_framebuffer_create_handle
,
14248 .dirty
= intel_user_framebuffer_dirty
,
14252 u32
intel_fb_pitch_limit(struct drm_device
*dev
, uint64_t fb_modifier
,
14253 uint32_t pixel_format
)
14255 u32 gen
= INTEL_INFO(dev
)->gen
;
14258 /* "The stride in bytes must not exceed the of the size of 8K
14259 * pixels and 32K bytes."
14261 return min(8192*drm_format_plane_cpp(pixel_format
, 0), 32768);
14262 } else if (gen
>= 5 && !IS_VALLEYVIEW(dev
)) {
14264 } else if (gen
>= 4) {
14265 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14269 } else if (gen
>= 3) {
14270 if (fb_modifier
== I915_FORMAT_MOD_X_TILED
)
14275 /* XXX DSPC is limited to 4k tiled */
14280 static int intel_framebuffer_init(struct drm_device
*dev
,
14281 struct intel_framebuffer
*intel_fb
,
14282 struct drm_mode_fb_cmd2
*mode_cmd
,
14283 struct drm_i915_gem_object
*obj
)
14285 unsigned int aligned_height
;
14287 u32 pitch_limit
, stride_alignment
;
14289 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
14291 if (mode_cmd
->flags
& DRM_MODE_FB_MODIFIERS
) {
14292 /* Enforce that fb modifier and tiling mode match, but only for
14293 * X-tiled. This is needed for FBC. */
14294 if (!!(obj
->tiling_mode
== I915_TILING_X
) !=
14295 !!(mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
)) {
14296 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14300 if (obj
->tiling_mode
== I915_TILING_X
)
14301 mode_cmd
->modifier
[0] = I915_FORMAT_MOD_X_TILED
;
14302 else if (obj
->tiling_mode
== I915_TILING_Y
) {
14303 DRM_DEBUG("No Y tiling for legacy addfb\n");
14308 /* Passed in modifier sanity checking. */
14309 switch (mode_cmd
->modifier
[0]) {
14310 case I915_FORMAT_MOD_Y_TILED
:
14311 case I915_FORMAT_MOD_Yf_TILED
:
14312 if (INTEL_INFO(dev
)->gen
< 9) {
14313 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14314 mode_cmd
->modifier
[0]);
14317 case DRM_FORMAT_MOD_NONE
:
14318 case I915_FORMAT_MOD_X_TILED
:
14321 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14322 mode_cmd
->modifier
[0]);
14326 stride_alignment
= intel_fb_stride_alignment(dev
, mode_cmd
->modifier
[0],
14327 mode_cmd
->pixel_format
);
14328 if (mode_cmd
->pitches
[0] & (stride_alignment
- 1)) {
14329 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14330 mode_cmd
->pitches
[0], stride_alignment
);
14334 pitch_limit
= intel_fb_pitch_limit(dev
, mode_cmd
->modifier
[0],
14335 mode_cmd
->pixel_format
);
14336 if (mode_cmd
->pitches
[0] > pitch_limit
) {
14337 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14338 mode_cmd
->modifier
[0] != DRM_FORMAT_MOD_NONE
?
14339 "tiled" : "linear",
14340 mode_cmd
->pitches
[0], pitch_limit
);
14344 if (mode_cmd
->modifier
[0] == I915_FORMAT_MOD_X_TILED
&&
14345 mode_cmd
->pitches
[0] != obj
->stride
) {
14346 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14347 mode_cmd
->pitches
[0], obj
->stride
);
14351 /* Reject formats not supported by any plane early. */
14352 switch (mode_cmd
->pixel_format
) {
14353 case DRM_FORMAT_C8
:
14354 case DRM_FORMAT_RGB565
:
14355 case DRM_FORMAT_XRGB8888
:
14356 case DRM_FORMAT_ARGB8888
:
14358 case DRM_FORMAT_XRGB1555
:
14359 if (INTEL_INFO(dev
)->gen
> 3) {
14360 DRM_DEBUG("unsupported pixel format: %s\n",
14361 drm_get_format_name(mode_cmd
->pixel_format
));
14365 case DRM_FORMAT_ABGR8888
:
14366 if (!IS_VALLEYVIEW(dev
) && INTEL_INFO(dev
)->gen
< 9) {
14367 DRM_DEBUG("unsupported pixel format: %s\n",
14368 drm_get_format_name(mode_cmd
->pixel_format
));
14372 case DRM_FORMAT_XBGR8888
:
14373 case DRM_FORMAT_XRGB2101010
:
14374 case DRM_FORMAT_XBGR2101010
:
14375 if (INTEL_INFO(dev
)->gen
< 4) {
14376 DRM_DEBUG("unsupported pixel format: %s\n",
14377 drm_get_format_name(mode_cmd
->pixel_format
));
14381 case DRM_FORMAT_ABGR2101010
:
14382 if (!IS_VALLEYVIEW(dev
)) {
14383 DRM_DEBUG("unsupported pixel format: %s\n",
14384 drm_get_format_name(mode_cmd
->pixel_format
));
14388 case DRM_FORMAT_YUYV
:
14389 case DRM_FORMAT_UYVY
:
14390 case DRM_FORMAT_YVYU
:
14391 case DRM_FORMAT_VYUY
:
14392 if (INTEL_INFO(dev
)->gen
< 5) {
14393 DRM_DEBUG("unsupported pixel format: %s\n",
14394 drm_get_format_name(mode_cmd
->pixel_format
));
14399 DRM_DEBUG("unsupported pixel format: %s\n",
14400 drm_get_format_name(mode_cmd
->pixel_format
));
14404 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14405 if (mode_cmd
->offsets
[0] != 0)
14408 aligned_height
= intel_fb_align_height(dev
, mode_cmd
->height
,
14409 mode_cmd
->pixel_format
,
14410 mode_cmd
->modifier
[0]);
14411 /* FIXME drm helper for size checks (especially planar formats)? */
14412 if (obj
->base
.size
< aligned_height
* mode_cmd
->pitches
[0])
14415 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
14416 intel_fb
->obj
= obj
;
14417 intel_fb
->obj
->framebuffer_references
++;
14419 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
14421 DRM_ERROR("framebuffer init failed %d\n", ret
);
14428 static struct drm_framebuffer
*
14429 intel_user_framebuffer_create(struct drm_device
*dev
,
14430 struct drm_file
*filp
,
14431 struct drm_mode_fb_cmd2
*user_mode_cmd
)
14433 struct drm_i915_gem_object
*obj
;
14434 struct drm_mode_fb_cmd2 mode_cmd
= *user_mode_cmd
;
14436 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
14437 mode_cmd
.handles
[0]));
14438 if (&obj
->base
== NULL
)
14439 return ERR_PTR(-ENOENT
);
14441 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
14444 #ifndef CONFIG_DRM_FBDEV_EMULATION
14445 static inline void intel_fbdev_output_poll_changed(struct drm_device
*dev
)
14450 static const struct drm_mode_config_funcs intel_mode_funcs
= {
14451 .fb_create
= intel_user_framebuffer_create
,
14452 .output_poll_changed
= intel_fbdev_output_poll_changed
,
14453 .atomic_check
= intel_atomic_check
,
14454 .atomic_commit
= intel_atomic_commit
,
14455 .atomic_state_alloc
= intel_atomic_state_alloc
,
14456 .atomic_state_clear
= intel_atomic_state_clear
,
14459 /* Set up chip specific display functions */
14460 static void intel_init_display(struct drm_device
*dev
)
14462 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14464 if (HAS_PCH_SPLIT(dev
) || IS_G4X(dev
))
14465 dev_priv
->display
.find_dpll
= g4x_find_best_dpll
;
14466 else if (IS_CHERRYVIEW(dev
))
14467 dev_priv
->display
.find_dpll
= chv_find_best_dpll
;
14468 else if (IS_VALLEYVIEW(dev
))
14469 dev_priv
->display
.find_dpll
= vlv_find_best_dpll
;
14470 else if (IS_PINEVIEW(dev
))
14471 dev_priv
->display
.find_dpll
= pnv_find_best_dpll
;
14473 dev_priv
->display
.find_dpll
= i9xx_find_best_dpll
;
14475 if (INTEL_INFO(dev
)->gen
>= 9) {
14476 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14477 dev_priv
->display
.get_initial_plane_config
=
14478 skylake_get_initial_plane_config
;
14479 dev_priv
->display
.crtc_compute_clock
=
14480 haswell_crtc_compute_clock
;
14481 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14482 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14483 dev_priv
->display
.update_primary_plane
=
14484 skylake_update_primary_plane
;
14485 } else if (HAS_DDI(dev
)) {
14486 dev_priv
->display
.get_pipe_config
= haswell_get_pipe_config
;
14487 dev_priv
->display
.get_initial_plane_config
=
14488 ironlake_get_initial_plane_config
;
14489 dev_priv
->display
.crtc_compute_clock
=
14490 haswell_crtc_compute_clock
;
14491 dev_priv
->display
.crtc_enable
= haswell_crtc_enable
;
14492 dev_priv
->display
.crtc_disable
= haswell_crtc_disable
;
14493 dev_priv
->display
.update_primary_plane
=
14494 ironlake_update_primary_plane
;
14495 } else if (HAS_PCH_SPLIT(dev
)) {
14496 dev_priv
->display
.get_pipe_config
= ironlake_get_pipe_config
;
14497 dev_priv
->display
.get_initial_plane_config
=
14498 ironlake_get_initial_plane_config
;
14499 dev_priv
->display
.crtc_compute_clock
=
14500 ironlake_crtc_compute_clock
;
14501 dev_priv
->display
.crtc_enable
= ironlake_crtc_enable
;
14502 dev_priv
->display
.crtc_disable
= ironlake_crtc_disable
;
14503 dev_priv
->display
.update_primary_plane
=
14504 ironlake_update_primary_plane
;
14505 } else if (IS_VALLEYVIEW(dev
)) {
14506 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14507 dev_priv
->display
.get_initial_plane_config
=
14508 i9xx_get_initial_plane_config
;
14509 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14510 dev_priv
->display
.crtc_enable
= valleyview_crtc_enable
;
14511 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14512 dev_priv
->display
.update_primary_plane
=
14513 i9xx_update_primary_plane
;
14515 dev_priv
->display
.get_pipe_config
= i9xx_get_pipe_config
;
14516 dev_priv
->display
.get_initial_plane_config
=
14517 i9xx_get_initial_plane_config
;
14518 dev_priv
->display
.crtc_compute_clock
= i9xx_crtc_compute_clock
;
14519 dev_priv
->display
.crtc_enable
= i9xx_crtc_enable
;
14520 dev_priv
->display
.crtc_disable
= i9xx_crtc_disable
;
14521 dev_priv
->display
.update_primary_plane
=
14522 i9xx_update_primary_plane
;
14525 /* Returns the core display clock speed */
14526 if (IS_SKYLAKE(dev
))
14527 dev_priv
->display
.get_display_clock_speed
=
14528 skylake_get_display_clock_speed
;
14529 else if (IS_BROXTON(dev
))
14530 dev_priv
->display
.get_display_clock_speed
=
14531 broxton_get_display_clock_speed
;
14532 else if (IS_BROADWELL(dev
))
14533 dev_priv
->display
.get_display_clock_speed
=
14534 broadwell_get_display_clock_speed
;
14535 else if (IS_HASWELL(dev
))
14536 dev_priv
->display
.get_display_clock_speed
=
14537 haswell_get_display_clock_speed
;
14538 else if (IS_VALLEYVIEW(dev
))
14539 dev_priv
->display
.get_display_clock_speed
=
14540 valleyview_get_display_clock_speed
;
14541 else if (IS_GEN5(dev
))
14542 dev_priv
->display
.get_display_clock_speed
=
14543 ilk_get_display_clock_speed
;
14544 else if (IS_I945G(dev
) || IS_BROADWATER(dev
) ||
14545 IS_GEN6(dev
) || IS_IVYBRIDGE(dev
))
14546 dev_priv
->display
.get_display_clock_speed
=
14547 i945_get_display_clock_speed
;
14548 else if (IS_GM45(dev
))
14549 dev_priv
->display
.get_display_clock_speed
=
14550 gm45_get_display_clock_speed
;
14551 else if (IS_CRESTLINE(dev
))
14552 dev_priv
->display
.get_display_clock_speed
=
14553 i965gm_get_display_clock_speed
;
14554 else if (IS_PINEVIEW(dev
))
14555 dev_priv
->display
.get_display_clock_speed
=
14556 pnv_get_display_clock_speed
;
14557 else if (IS_G33(dev
) || IS_G4X(dev
))
14558 dev_priv
->display
.get_display_clock_speed
=
14559 g33_get_display_clock_speed
;
14560 else if (IS_I915G(dev
))
14561 dev_priv
->display
.get_display_clock_speed
=
14562 i915_get_display_clock_speed
;
14563 else if (IS_I945GM(dev
) || IS_845G(dev
))
14564 dev_priv
->display
.get_display_clock_speed
=
14565 i9xx_misc_get_display_clock_speed
;
14566 else if (IS_PINEVIEW(dev
))
14567 dev_priv
->display
.get_display_clock_speed
=
14568 pnv_get_display_clock_speed
;
14569 else if (IS_I915GM(dev
))
14570 dev_priv
->display
.get_display_clock_speed
=
14571 i915gm_get_display_clock_speed
;
14572 else if (IS_I865G(dev
))
14573 dev_priv
->display
.get_display_clock_speed
=
14574 i865_get_display_clock_speed
;
14575 else if (IS_I85X(dev
))
14576 dev_priv
->display
.get_display_clock_speed
=
14577 i85x_get_display_clock_speed
;
14579 WARN(!IS_I830(dev
), "Unknown platform. Assuming 133 MHz CDCLK\n");
14580 dev_priv
->display
.get_display_clock_speed
=
14581 i830_get_display_clock_speed
;
14584 if (IS_GEN5(dev
)) {
14585 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
14586 } else if (IS_GEN6(dev
)) {
14587 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
14588 } else if (IS_IVYBRIDGE(dev
)) {
14589 /* FIXME: detect B0+ stepping and use auto training */
14590 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
14591 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
14592 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
14593 if (IS_BROADWELL(dev
)) {
14594 dev_priv
->display
.modeset_commit_cdclk
=
14595 broadwell_modeset_commit_cdclk
;
14596 dev_priv
->display
.modeset_calc_cdclk
=
14597 broadwell_modeset_calc_cdclk
;
14599 } else if (IS_VALLEYVIEW(dev
)) {
14600 dev_priv
->display
.modeset_commit_cdclk
=
14601 valleyview_modeset_commit_cdclk
;
14602 dev_priv
->display
.modeset_calc_cdclk
=
14603 valleyview_modeset_calc_cdclk
;
14604 } else if (IS_BROXTON(dev
)) {
14605 dev_priv
->display
.modeset_commit_cdclk
=
14606 broxton_modeset_commit_cdclk
;
14607 dev_priv
->display
.modeset_calc_cdclk
=
14608 broxton_modeset_calc_cdclk
;
14611 switch (INTEL_INFO(dev
)->gen
) {
14613 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
14617 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
14622 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
14626 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
14629 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14630 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
14633 /* Drop through - unsupported since execlist only. */
14635 /* Default just returns -ENODEV to indicate unsupported */
14636 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
14639 mutex_init(&dev_priv
->pps_mutex
);
14643 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14644 * resume, or other times. This quirk makes sure that's the case for
14645 * affected systems.
14647 static void quirk_pipea_force(struct drm_device
*dev
)
14649 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14651 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
14652 DRM_INFO("applying pipe a force quirk\n");
14655 static void quirk_pipeb_force(struct drm_device
*dev
)
14657 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14659 dev_priv
->quirks
|= QUIRK_PIPEB_FORCE
;
14660 DRM_INFO("applying pipe b force quirk\n");
14664 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14666 static void quirk_ssc_force_disable(struct drm_device
*dev
)
14668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14669 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
14670 DRM_INFO("applying lvds SSC disable quirk\n");
14674 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14677 static void quirk_invert_brightness(struct drm_device
*dev
)
14679 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14680 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
14681 DRM_INFO("applying inverted panel brightness quirk\n");
14684 /* Some VBT's incorrectly indicate no backlight is present */
14685 static void quirk_backlight_present(struct drm_device
*dev
)
14687 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14688 dev_priv
->quirks
|= QUIRK_BACKLIGHT_PRESENT
;
14689 DRM_INFO("applying backlight present quirk\n");
14692 struct intel_quirk
{
14694 int subsystem_vendor
;
14695 int subsystem_device
;
14696 void (*hook
)(struct drm_device
*dev
);
14699 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14700 struct intel_dmi_quirk
{
14701 void (*hook
)(struct drm_device
*dev
);
14702 const struct dmi_system_id (*dmi_id_list
)[];
14705 static int intel_dmi_reverse_brightness(const struct dmi_system_id
*id
)
14707 DRM_INFO("Backlight polarity reversed on %s\n", id
->ident
);
14711 static const struct intel_dmi_quirk intel_dmi_quirks
[] = {
14713 .dmi_id_list
= &(const struct dmi_system_id
[]) {
14715 .callback
= intel_dmi_reverse_brightness
,
14716 .ident
= "NCR Corporation",
14717 .matches
= {DMI_MATCH(DMI_SYS_VENDOR
, "NCR Corporation"),
14718 DMI_MATCH(DMI_PRODUCT_NAME
, ""),
14721 { } /* terminating entry */
14723 .hook
= quirk_invert_brightness
,
14727 static struct intel_quirk intel_quirks
[] = {
14728 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14729 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
14731 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14732 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
14734 /* 830 needs to leave pipe A & dpll A up */
14735 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
14737 /* 830 needs to leave pipe B & dpll B up */
14738 { 0x3577, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipeb_force
},
14740 /* Lenovo U160 cannot use SSC on LVDS */
14741 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
14743 /* Sony Vaio Y cannot use SSC on LVDS */
14744 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
14746 /* Acer Aspire 5734Z must invert backlight brightness */
14747 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
14749 /* Acer/eMachines G725 */
14750 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness
},
14752 /* Acer/eMachines e725 */
14753 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness
},
14755 /* Acer/Packard Bell NCL20 */
14756 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness
},
14758 /* Acer Aspire 4736Z */
14759 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness
},
14761 /* Acer Aspire 5336 */
14762 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness
},
14764 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14765 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present
},
14767 /* Acer C720 Chromebook (Core i3 4005U) */
14768 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present
},
14770 /* Apple Macbook 2,1 (Core 2 T7400) */
14771 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present
},
14773 /* Apple Macbook 4,1 */
14774 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present
},
14776 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14777 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present
},
14779 /* HP Chromebook 14 (Celeron 2955U) */
14780 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present
},
14782 /* Dell Chromebook 11 */
14783 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present
},
14785 /* Dell Chromebook 11 (2015 version) */
14786 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present
},
14789 static void intel_init_quirks(struct drm_device
*dev
)
14791 struct pci_dev
*d
= dev
->pdev
;
14794 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
14795 struct intel_quirk
*q
= &intel_quirks
[i
];
14797 if (d
->device
== q
->device
&&
14798 (d
->subsystem_vendor
== q
->subsystem_vendor
||
14799 q
->subsystem_vendor
== PCI_ANY_ID
) &&
14800 (d
->subsystem_device
== q
->subsystem_device
||
14801 q
->subsystem_device
== PCI_ANY_ID
))
14804 for (i
= 0; i
< ARRAY_SIZE(intel_dmi_quirks
); i
++) {
14805 if (dmi_check_system(*intel_dmi_quirks
[i
].dmi_id_list
) != 0)
14806 intel_dmi_quirks
[i
].hook(dev
);
14810 /* Disable the VGA plane that we never use */
14811 static void i915_disable_vga(struct drm_device
*dev
)
14813 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14815 u32 vga_reg
= i915_vgacntrl_reg(dev
);
14817 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14818 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14819 outb(SR01
, VGA_SR_INDEX
);
14820 sr1
= inb(VGA_SR_DATA
);
14821 outb(sr1
| 1<<5, VGA_SR_DATA
);
14822 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
14825 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
14826 POSTING_READ(vga_reg
);
14829 void intel_modeset_init_hw(struct drm_device
*dev
)
14831 intel_update_cdclk(dev
);
14832 intel_prepare_ddi(dev
);
14833 intel_init_clock_gating(dev
);
14834 intel_enable_gt_powersave(dev
);
14837 void intel_modeset_init(struct drm_device
*dev
)
14839 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14842 struct intel_crtc
*crtc
;
14844 drm_mode_config_init(dev
);
14846 dev
->mode_config
.min_width
= 0;
14847 dev
->mode_config
.min_height
= 0;
14849 dev
->mode_config
.preferred_depth
= 24;
14850 dev
->mode_config
.prefer_shadow
= 1;
14852 dev
->mode_config
.allow_fb_modifiers
= true;
14854 dev
->mode_config
.funcs
= &intel_mode_funcs
;
14856 intel_init_quirks(dev
);
14858 intel_init_pm(dev
);
14860 if (INTEL_INFO(dev
)->num_pipes
== 0)
14864 * There may be no VBT; and if the BIOS enabled SSC we can
14865 * just keep using it to avoid unnecessary flicker. Whereas if the
14866 * BIOS isn't using it, don't assume it will work even if the VBT
14867 * indicates as much.
14869 if (HAS_PCH_IBX(dev
) || HAS_PCH_CPT(dev
)) {
14870 bool bios_lvds_use_ssc
= !!(I915_READ(PCH_DREF_CONTROL
) &
14873 if (dev_priv
->vbt
.lvds_use_ssc
!= bios_lvds_use_ssc
) {
14874 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
14875 bios_lvds_use_ssc
? "en" : "dis",
14876 dev_priv
->vbt
.lvds_use_ssc
? "en" : "dis");
14877 dev_priv
->vbt
.lvds_use_ssc
= bios_lvds_use_ssc
;
14881 intel_init_display(dev
);
14882 intel_init_audio(dev
);
14884 if (IS_GEN2(dev
)) {
14885 dev
->mode_config
.max_width
= 2048;
14886 dev
->mode_config
.max_height
= 2048;
14887 } else if (IS_GEN3(dev
)) {
14888 dev
->mode_config
.max_width
= 4096;
14889 dev
->mode_config
.max_height
= 4096;
14891 dev
->mode_config
.max_width
= 8192;
14892 dev
->mode_config
.max_height
= 8192;
14895 if (IS_845G(dev
) || IS_I865G(dev
)) {
14896 dev
->mode_config
.cursor_width
= IS_845G(dev
) ? 64 : 512;
14897 dev
->mode_config
.cursor_height
= 1023;
14898 } else if (IS_GEN2(dev
)) {
14899 dev
->mode_config
.cursor_width
= GEN2_CURSOR_WIDTH
;
14900 dev
->mode_config
.cursor_height
= GEN2_CURSOR_HEIGHT
;
14902 dev
->mode_config
.cursor_width
= MAX_CURSOR_WIDTH
;
14903 dev
->mode_config
.cursor_height
= MAX_CURSOR_HEIGHT
;
14906 dev
->mode_config
.fb_base
= dev_priv
->gtt
.mappable_base
;
14908 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14909 INTEL_INFO(dev
)->num_pipes
,
14910 INTEL_INFO(dev
)->num_pipes
> 1 ? "s" : "");
14912 for_each_pipe(dev_priv
, pipe
) {
14913 intel_crtc_init(dev
, pipe
);
14914 for_each_sprite(dev_priv
, pipe
, sprite
) {
14915 ret
= intel_plane_init(dev
, pipe
, sprite
);
14917 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14918 pipe_name(pipe
), sprite_name(pipe
, sprite
), ret
);
14922 intel_update_czclk(dev_priv
);
14923 intel_update_cdclk(dev
);
14925 intel_shared_dpll_init(dev
);
14927 /* Just disable it once at startup */
14928 i915_disable_vga(dev
);
14929 intel_setup_outputs(dev
);
14931 /* Just in case the BIOS is doing something questionable. */
14932 intel_fbc_disable(dev_priv
);
14934 drm_modeset_lock_all(dev
);
14935 intel_modeset_setup_hw_state(dev
);
14936 drm_modeset_unlock_all(dev
);
14938 for_each_intel_crtc(dev
, crtc
) {
14939 struct intel_initial_plane_config plane_config
= {};
14945 * Note that reserving the BIOS fb up front prevents us
14946 * from stuffing other stolen allocations like the ring
14947 * on top. This prevents some ugliness at boot time, and
14948 * can even allow for smooth boot transitions if the BIOS
14949 * fb is large enough for the active pipe configuration.
14951 dev_priv
->display
.get_initial_plane_config(crtc
,
14955 * If the fb is shared between multiple heads, we'll
14956 * just get the first one.
14958 intel_find_initial_plane_obj(crtc
, &plane_config
);
14962 static void intel_enable_pipe_a(struct drm_device
*dev
)
14964 struct intel_connector
*connector
;
14965 struct drm_connector
*crt
= NULL
;
14966 struct intel_load_detect_pipe load_detect_temp
;
14967 struct drm_modeset_acquire_ctx
*ctx
= dev
->mode_config
.acquire_ctx
;
14969 /* We can't just switch on the pipe A, we need to set things up with a
14970 * proper mode and output configuration. As a gross hack, enable pipe A
14971 * by enabling the load detect pipe once. */
14972 for_each_intel_connector(dev
, connector
) {
14973 if (connector
->encoder
->type
== INTEL_OUTPUT_ANALOG
) {
14974 crt
= &connector
->base
;
14982 if (intel_get_load_detect_pipe(crt
, NULL
, &load_detect_temp
, ctx
))
14983 intel_release_load_detect_pipe(crt
, &load_detect_temp
, ctx
);
14987 intel_check_plane_mapping(struct intel_crtc
*crtc
)
14989 struct drm_device
*dev
= crtc
->base
.dev
;
14990 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
14993 if (INTEL_INFO(dev
)->num_pipes
== 1)
14996 val
= I915_READ(DSPCNTR(!crtc
->plane
));
14998 if ((val
& DISPLAY_PLANE_ENABLE
) &&
14999 (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == crtc
->pipe
))
15005 static bool intel_crtc_has_encoders(struct intel_crtc
*crtc
)
15007 struct drm_device
*dev
= crtc
->base
.dev
;
15008 struct intel_encoder
*encoder
;
15010 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15016 static void intel_sanitize_crtc(struct intel_crtc
*crtc
)
15018 struct drm_device
*dev
= crtc
->base
.dev
;
15019 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15022 /* Clear any frame start delays used for debugging left by the BIOS */
15023 reg
= PIPECONF(crtc
->config
->cpu_transcoder
);
15024 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
15026 /* restore vblank interrupts to correct state */
15027 drm_crtc_vblank_reset(&crtc
->base
);
15028 if (crtc
->active
) {
15029 struct intel_plane
*plane
;
15031 drm_crtc_vblank_on(&crtc
->base
);
15033 /* Disable everything but the primary plane */
15034 for_each_intel_plane_on_crtc(dev
, crtc
, plane
) {
15035 if (plane
->base
.type
== DRM_PLANE_TYPE_PRIMARY
)
15038 plane
->disable_plane(&plane
->base
, &crtc
->base
);
15042 /* We need to sanitize the plane -> pipe mapping first because this will
15043 * disable the crtc (and hence change the state) if it is wrong. Note
15044 * that gen4+ has a fixed plane -> pipe mapping. */
15045 if (INTEL_INFO(dev
)->gen
< 4 && !intel_check_plane_mapping(crtc
)) {
15048 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15049 crtc
->base
.base
.id
);
15051 /* Pipe has the wrong plane attached and the plane is active.
15052 * Temporarily change the plane mapping and disable everything
15054 plane
= crtc
->plane
;
15055 to_intel_plane_state(crtc
->base
.primary
->state
)->visible
= true;
15056 crtc
->plane
= !plane
;
15057 intel_crtc_disable_noatomic(&crtc
->base
);
15058 crtc
->plane
= plane
;
15061 if (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
&&
15062 crtc
->pipe
== PIPE_A
&& !crtc
->active
) {
15063 /* BIOS forgot to enable pipe A, this mostly happens after
15064 * resume. Force-enable the pipe to fix this, the update_dpms
15065 * call below we restore the pipe to the right state, but leave
15066 * the required bits on. */
15067 intel_enable_pipe_a(dev
);
15070 /* Adjust the state of the output pipe according to whether we
15071 * have active connectors/encoders. */
15072 if (!intel_crtc_has_encoders(crtc
))
15073 intel_crtc_disable_noatomic(&crtc
->base
);
15075 if (crtc
->active
!= crtc
->base
.state
->active
) {
15076 struct intel_encoder
*encoder
;
15078 /* This can happen either due to bugs in the get_hw_state
15079 * functions or because of calls to intel_crtc_disable_noatomic,
15080 * or because the pipe is force-enabled due to the
15082 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15083 crtc
->base
.base
.id
,
15084 crtc
->base
.state
->enable
? "enabled" : "disabled",
15085 crtc
->active
? "enabled" : "disabled");
15087 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, NULL
) < 0);
15088 crtc
->base
.state
->active
= crtc
->active
;
15089 crtc
->base
.enabled
= crtc
->active
;
15091 /* Because we only establish the connector -> encoder ->
15092 * crtc links if something is active, this means the
15093 * crtc is now deactivated. Break the links. connector
15094 * -> encoder links are only establish when things are
15095 * actually up, hence no need to break them. */
15096 WARN_ON(crtc
->active
);
15098 for_each_encoder_on_crtc(dev
, &crtc
->base
, encoder
)
15099 encoder
->base
.crtc
= NULL
;
15102 if (crtc
->active
|| HAS_GMCH_DISPLAY(dev
)) {
15104 * We start out with underrun reporting disabled to avoid races.
15105 * For correct bookkeeping mark this on active crtcs.
15107 * Also on gmch platforms we dont have any hardware bits to
15108 * disable the underrun reporting. Which means we need to start
15109 * out with underrun reporting disabled also on inactive pipes,
15110 * since otherwise we'll complain about the garbage we read when
15111 * e.g. coming up after runtime pm.
15113 * No protection against concurrent access is required - at
15114 * worst a fifo underrun happens which also sets this to false.
15116 crtc
->cpu_fifo_underrun_disabled
= true;
15117 crtc
->pch_fifo_underrun_disabled
= true;
15121 static void intel_sanitize_encoder(struct intel_encoder
*encoder
)
15123 struct intel_connector
*connector
;
15124 struct drm_device
*dev
= encoder
->base
.dev
;
15125 bool active
= false;
15127 /* We need to check both for a crtc link (meaning that the
15128 * encoder is active and trying to read from a pipe) and the
15129 * pipe itself being active. */
15130 bool has_active_crtc
= encoder
->base
.crtc
&&
15131 to_intel_crtc(encoder
->base
.crtc
)->active
;
15133 for_each_intel_connector(dev
, connector
) {
15134 if (connector
->base
.encoder
!= &encoder
->base
)
15141 if (active
&& !has_active_crtc
) {
15142 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15143 encoder
->base
.base
.id
,
15144 encoder
->base
.name
);
15146 /* Connector is active, but has no active pipe. This is
15147 * fallout from our resume register restoring. Disable
15148 * the encoder manually again. */
15149 if (encoder
->base
.crtc
) {
15150 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15151 encoder
->base
.base
.id
,
15152 encoder
->base
.name
);
15153 encoder
->disable(encoder
);
15154 if (encoder
->post_disable
)
15155 encoder
->post_disable(encoder
);
15157 encoder
->base
.crtc
= NULL
;
15159 /* Inconsistent output/port/pipe state happens presumably due to
15160 * a bug in one of the get_hw_state functions. Or someplace else
15161 * in our code, like the register restore mess on resume. Clamp
15162 * things to off as a safer default. */
15163 for_each_intel_connector(dev
, connector
) {
15164 if (connector
->encoder
!= encoder
)
15166 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15167 connector
->base
.encoder
= NULL
;
15170 /* Enabled encoders without active connectors will be fixed in
15171 * the crtc fixup. */
15174 void i915_redisable_vga_power_on(struct drm_device
*dev
)
15176 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15177 u32 vga_reg
= i915_vgacntrl_reg(dev
);
15179 if (!(I915_READ(vga_reg
) & VGA_DISP_DISABLE
)) {
15180 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15181 i915_disable_vga(dev
);
15185 void i915_redisable_vga(struct drm_device
*dev
)
15187 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15189 /* This function can be called both from intel_modeset_setup_hw_state or
15190 * at a very early point in our resume sequence, where the power well
15191 * structures are not yet restored. Since this function is at a very
15192 * paranoid "someone might have enabled VGA while we were not looking"
15193 * level, just check if the power well is enabled instead of trying to
15194 * follow the "don't touch the power well if we don't need it" policy
15195 * the rest of the driver uses. */
15196 if (!intel_display_power_is_enabled(dev_priv
, POWER_DOMAIN_VGA
))
15199 i915_redisable_vga_power_on(dev
);
15202 static bool primary_get_hw_state(struct intel_plane
*plane
)
15204 struct drm_i915_private
*dev_priv
= to_i915(plane
->base
.dev
);
15206 return I915_READ(DSPCNTR(plane
->plane
)) & DISPLAY_PLANE_ENABLE
;
15209 /* FIXME read out full plane state for all planes */
15210 static void readout_plane_state(struct intel_crtc
*crtc
)
15212 struct drm_plane
*primary
= crtc
->base
.primary
;
15213 struct intel_plane_state
*plane_state
=
15214 to_intel_plane_state(primary
->state
);
15216 plane_state
->visible
=
15217 primary_get_hw_state(to_intel_plane(primary
));
15219 if (plane_state
->visible
)
15220 crtc
->base
.state
->plane_mask
|= 1 << drm_plane_index(primary
);
15223 static void intel_modeset_readout_hw_state(struct drm_device
*dev
)
15225 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15227 struct intel_crtc
*crtc
;
15228 struct intel_encoder
*encoder
;
15229 struct intel_connector
*connector
;
15232 for_each_intel_crtc(dev
, crtc
) {
15233 __drm_atomic_helper_crtc_destroy_state(&crtc
->base
, crtc
->base
.state
);
15234 memset(crtc
->config
, 0, sizeof(*crtc
->config
));
15235 crtc
->config
->base
.crtc
= &crtc
->base
;
15237 crtc
->active
= dev_priv
->display
.get_pipe_config(crtc
,
15240 crtc
->base
.state
->active
= crtc
->active
;
15241 crtc
->base
.enabled
= crtc
->active
;
15243 readout_plane_state(crtc
);
15245 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15246 crtc
->base
.base
.id
,
15247 crtc
->active
? "enabled" : "disabled");
15250 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15251 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15253 pll
->on
= pll
->get_hw_state(dev_priv
, pll
,
15254 &pll
->config
.hw_state
);
15256 pll
->config
.crtc_mask
= 0;
15257 for_each_intel_crtc(dev
, crtc
) {
15258 if (crtc
->active
&& intel_crtc_to_shared_dpll(crtc
) == pll
) {
15260 pll
->config
.crtc_mask
|= 1 << crtc
->pipe
;
15264 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15265 pll
->name
, pll
->config
.crtc_mask
, pll
->on
);
15267 if (pll
->config
.crtc_mask
)
15268 intel_display_power_get(dev_priv
, POWER_DOMAIN_PLLS
);
15271 for_each_intel_encoder(dev
, encoder
) {
15274 if (encoder
->get_hw_state(encoder
, &pipe
)) {
15275 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15276 encoder
->base
.crtc
= &crtc
->base
;
15277 encoder
->get_config(encoder
, crtc
->config
);
15279 encoder
->base
.crtc
= NULL
;
15282 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15283 encoder
->base
.base
.id
,
15284 encoder
->base
.name
,
15285 encoder
->base
.crtc
? "enabled" : "disabled",
15289 for_each_intel_connector(dev
, connector
) {
15290 if (connector
->get_hw_state(connector
)) {
15291 connector
->base
.dpms
= DRM_MODE_DPMS_ON
;
15292 connector
->base
.encoder
= &connector
->encoder
->base
;
15294 connector
->base
.dpms
= DRM_MODE_DPMS_OFF
;
15295 connector
->base
.encoder
= NULL
;
15297 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15298 connector
->base
.base
.id
,
15299 connector
->base
.name
,
15300 connector
->base
.encoder
? "enabled" : "disabled");
15303 for_each_intel_crtc(dev
, crtc
) {
15304 crtc
->base
.hwmode
= crtc
->config
->base
.adjusted_mode
;
15306 memset(&crtc
->base
.mode
, 0, sizeof(crtc
->base
.mode
));
15307 if (crtc
->base
.state
->active
) {
15308 intel_mode_from_pipe_config(&crtc
->base
.mode
, crtc
->config
);
15309 intel_mode_from_pipe_config(&crtc
->base
.state
->adjusted_mode
, crtc
->config
);
15310 WARN_ON(drm_atomic_set_mode_for_crtc(crtc
->base
.state
, &crtc
->base
.mode
));
15313 * The initial mode needs to be set in order to keep
15314 * the atomic core happy. It wants a valid mode if the
15315 * crtc's enabled, so we do the above call.
15317 * At this point some state updated by the connectors
15318 * in their ->detect() callback has not run yet, so
15319 * no recalculation can be done yet.
15321 * Even if we could do a recalculation and modeset
15322 * right now it would cause a double modeset if
15323 * fbdev or userspace chooses a different initial mode.
15325 * If that happens, someone indicated they wanted a
15326 * mode change, which means it's safe to do a full
15329 crtc
->base
.state
->mode
.private_flags
= I915_MODE_FLAG_INHERITED
;
15331 drm_calc_timestamping_constants(&crtc
->base
, &crtc
->base
.hwmode
);
15332 update_scanline_offset(crtc
);
15337 /* Scan out the current hw modeset state,
15338 * and sanitizes it to the current state
15341 intel_modeset_setup_hw_state(struct drm_device
*dev
)
15343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15345 struct intel_crtc
*crtc
;
15346 struct intel_encoder
*encoder
;
15349 intel_modeset_readout_hw_state(dev
);
15351 /* HW state is read out, now we need to sanitize this mess. */
15352 for_each_intel_encoder(dev
, encoder
) {
15353 intel_sanitize_encoder(encoder
);
15356 for_each_pipe(dev_priv
, pipe
) {
15357 crtc
= to_intel_crtc(dev_priv
->pipe_to_crtc_mapping
[pipe
]);
15358 intel_sanitize_crtc(crtc
);
15359 intel_dump_pipe_config(crtc
, crtc
->config
,
15360 "[setup_hw_state]");
15363 intel_modeset_update_connector_atomic_state(dev
);
15365 for (i
= 0; i
< dev_priv
->num_shared_dpll
; i
++) {
15366 struct intel_shared_dpll
*pll
= &dev_priv
->shared_dplls
[i
];
15368 if (!pll
->on
|| pll
->active
)
15371 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll
->name
);
15373 pll
->disable(dev_priv
, pll
);
15377 if (IS_VALLEYVIEW(dev
))
15378 vlv_wm_get_hw_state(dev
);
15379 else if (IS_GEN9(dev
))
15380 skl_wm_get_hw_state(dev
);
15381 else if (HAS_PCH_SPLIT(dev
))
15382 ilk_wm_get_hw_state(dev
);
15384 for_each_intel_crtc(dev
, crtc
) {
15385 unsigned long put_domains
;
15387 put_domains
= modeset_get_crtc_power_domains(&crtc
->base
);
15388 if (WARN_ON(put_domains
))
15389 modeset_put_power_domains(dev_priv
, put_domains
);
15391 intel_display_set_init_power(dev_priv
, false);
15394 void intel_display_resume(struct drm_device
*dev
)
15396 struct drm_atomic_state
*state
= drm_atomic_state_alloc(dev
);
15397 struct intel_connector
*conn
;
15398 struct intel_plane
*plane
;
15399 struct drm_crtc
*crtc
;
15405 state
->acquire_ctx
= dev
->mode_config
.acquire_ctx
;
15407 /* preserve complete old state, including dpll */
15408 intel_atomic_get_shared_dpll_state(state
);
15410 for_each_crtc(dev
, crtc
) {
15411 struct drm_crtc_state
*crtc_state
=
15412 drm_atomic_get_crtc_state(state
, crtc
);
15414 ret
= PTR_ERR_OR_ZERO(crtc_state
);
15418 /* force a restore */
15419 crtc_state
->mode_changed
= true;
15422 for_each_intel_plane(dev
, plane
) {
15423 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state
, &plane
->base
));
15428 for_each_intel_connector(dev
, conn
) {
15429 ret
= PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state
, &conn
->base
));
15434 intel_modeset_setup_hw_state(dev
);
15436 i915_redisable_vga(dev
);
15437 ret
= drm_atomic_commit(state
);
15442 DRM_ERROR("Restoring old state failed with %i\n", ret
);
15443 drm_atomic_state_free(state
);
15446 void intel_modeset_gem_init(struct drm_device
*dev
)
15448 struct drm_crtc
*c
;
15449 struct drm_i915_gem_object
*obj
;
15452 mutex_lock(&dev
->struct_mutex
);
15453 intel_init_gt_powersave(dev
);
15454 mutex_unlock(&dev
->struct_mutex
);
15456 intel_modeset_init_hw(dev
);
15458 intel_setup_overlay(dev
);
15461 * Make sure any fbs we allocated at startup are properly
15462 * pinned & fenced. When we do the allocation it's too early
15465 for_each_crtc(dev
, c
) {
15466 obj
= intel_fb_obj(c
->primary
->fb
);
15470 mutex_lock(&dev
->struct_mutex
);
15471 ret
= intel_pin_and_fence_fb_obj(c
->primary
,
15475 mutex_unlock(&dev
->struct_mutex
);
15477 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15478 to_intel_crtc(c
)->pipe
);
15479 drm_framebuffer_unreference(c
->primary
->fb
);
15480 c
->primary
->fb
= NULL
;
15481 c
->primary
->crtc
= c
->primary
->state
->crtc
= NULL
;
15482 update_state_fb(c
->primary
);
15483 c
->state
->plane_mask
&= ~(1 << drm_plane_index(c
->primary
));
15487 intel_backlight_register(dev
);
15490 void intel_connector_unregister(struct intel_connector
*intel_connector
)
15492 struct drm_connector
*connector
= &intel_connector
->base
;
15494 intel_panel_destroy_backlight(connector
);
15495 drm_connector_unregister(connector
);
15498 void intel_modeset_cleanup(struct drm_device
*dev
)
15500 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15501 struct drm_connector
*connector
;
15503 intel_disable_gt_powersave(dev
);
15505 intel_backlight_unregister(dev
);
15508 * Interrupts and polling as the first thing to avoid creating havoc.
15509 * Too much stuff here (turning of connectors, ...) would
15510 * experience fancy races otherwise.
15512 intel_irq_uninstall(dev_priv
);
15515 * Due to the hpd irq storm handling the hotplug work can re-arm the
15516 * poll handlers. Hence disable polling after hpd handling is shut down.
15518 drm_kms_helper_poll_fini(dev
);
15520 intel_unregister_dsm_handler();
15522 intel_fbc_disable(dev_priv
);
15524 /* flush any delayed tasks or pending work */
15525 flush_scheduled_work();
15527 /* destroy the backlight and sysfs files before encoders/connectors */
15528 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
, head
) {
15529 struct intel_connector
*intel_connector
;
15531 intel_connector
= to_intel_connector(connector
);
15532 intel_connector
->unregister(intel_connector
);
15535 drm_mode_config_cleanup(dev
);
15537 intel_cleanup_overlay(dev
);
15539 mutex_lock(&dev
->struct_mutex
);
15540 intel_cleanup_gt_powersave(dev
);
15541 mutex_unlock(&dev
->struct_mutex
);
15545 * Return which encoder is currently attached for connector.
15547 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
15549 return &intel_attached_encoder(connector
)->base
;
15552 void intel_connector_attach_encoder(struct intel_connector
*connector
,
15553 struct intel_encoder
*encoder
)
15555 connector
->encoder
= encoder
;
15556 drm_mode_connector_attach_encoder(&connector
->base
,
15561 * set vga decode state - true == enable VGA decode
15563 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
15565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15566 unsigned reg
= INTEL_INFO(dev
)->gen
>= 6 ? SNB_GMCH_CTRL
: INTEL_GMCH_CTRL
;
15569 if (pci_read_config_word(dev_priv
->bridge_dev
, reg
, &gmch_ctrl
)) {
15570 DRM_ERROR("failed to read control word\n");
15574 if (!!(gmch_ctrl
& INTEL_GMCH_VGA_DISABLE
) == !state
)
15578 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
15580 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
15582 if (pci_write_config_word(dev_priv
->bridge_dev
, reg
, gmch_ctrl
)) {
15583 DRM_ERROR("failed to write control word\n");
15590 struct intel_display_error_state
{
15592 u32 power_well_driver
;
15594 int num_transcoders
;
15596 struct intel_cursor_error_state
{
15601 } cursor
[I915_MAX_PIPES
];
15603 struct intel_pipe_error_state
{
15604 bool power_domain_on
;
15607 } pipe
[I915_MAX_PIPES
];
15609 struct intel_plane_error_state
{
15617 } plane
[I915_MAX_PIPES
];
15619 struct intel_transcoder_error_state
{
15620 bool power_domain_on
;
15621 enum transcoder cpu_transcoder
;
15634 struct intel_display_error_state
*
15635 intel_display_capture_error_state(struct drm_device
*dev
)
15637 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15638 struct intel_display_error_state
*error
;
15639 int transcoders
[] = {
15647 if (INTEL_INFO(dev
)->num_pipes
== 0)
15650 error
= kzalloc(sizeof(*error
), GFP_ATOMIC
);
15654 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15655 error
->power_well_driver
= I915_READ(HSW_PWR_WELL_DRIVER
);
15657 for_each_pipe(dev_priv
, i
) {
15658 error
->pipe
[i
].power_domain_on
=
15659 __intel_display_power_is_enabled(dev_priv
,
15660 POWER_DOMAIN_PIPE(i
));
15661 if (!error
->pipe
[i
].power_domain_on
)
15664 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
15665 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
15666 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
15668 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
15669 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
15670 if (INTEL_INFO(dev
)->gen
<= 3) {
15671 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
15672 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
15674 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15675 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
15676 if (INTEL_INFO(dev
)->gen
>= 4) {
15677 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
15678 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
15681 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
15683 if (HAS_GMCH_DISPLAY(dev
))
15684 error
->pipe
[i
].stat
= I915_READ(PIPESTAT(i
));
15687 error
->num_transcoders
= INTEL_INFO(dev
)->num_pipes
;
15688 if (HAS_DDI(dev_priv
->dev
))
15689 error
->num_transcoders
++; /* Account for eDP. */
15691 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15692 enum transcoder cpu_transcoder
= transcoders
[i
];
15694 error
->transcoder
[i
].power_domain_on
=
15695 __intel_display_power_is_enabled(dev_priv
,
15696 POWER_DOMAIN_TRANSCODER(cpu_transcoder
));
15697 if (!error
->transcoder
[i
].power_domain_on
)
15700 error
->transcoder
[i
].cpu_transcoder
= cpu_transcoder
;
15702 error
->transcoder
[i
].conf
= I915_READ(PIPECONF(cpu_transcoder
));
15703 error
->transcoder
[i
].htotal
= I915_READ(HTOTAL(cpu_transcoder
));
15704 error
->transcoder
[i
].hblank
= I915_READ(HBLANK(cpu_transcoder
));
15705 error
->transcoder
[i
].hsync
= I915_READ(HSYNC(cpu_transcoder
));
15706 error
->transcoder
[i
].vtotal
= I915_READ(VTOTAL(cpu_transcoder
));
15707 error
->transcoder
[i
].vblank
= I915_READ(VBLANK(cpu_transcoder
));
15708 error
->transcoder
[i
].vsync
= I915_READ(VSYNC(cpu_transcoder
));
15714 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15717 intel_display_print_error_state(struct drm_i915_error_state_buf
*m
,
15718 struct drm_device
*dev
,
15719 struct intel_display_error_state
*error
)
15721 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
15727 err_printf(m
, "Num Pipes: %d\n", INTEL_INFO(dev
)->num_pipes
);
15728 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
15729 err_printf(m
, "PWR_WELL_CTL2: %08x\n",
15730 error
->power_well_driver
);
15731 for_each_pipe(dev_priv
, i
) {
15732 err_printf(m
, "Pipe [%d]:\n", i
);
15733 err_printf(m
, " Power: %s\n",
15734 error
->pipe
[i
].power_domain_on
? "on" : "off");
15735 err_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
15736 err_printf(m
, " STAT: %08x\n", error
->pipe
[i
].stat
);
15738 err_printf(m
, "Plane [%d]:\n", i
);
15739 err_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
15740 err_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
15741 if (INTEL_INFO(dev
)->gen
<= 3) {
15742 err_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
15743 err_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
15745 if (INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
))
15746 err_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
15747 if (INTEL_INFO(dev
)->gen
>= 4) {
15748 err_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
15749 err_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
15752 err_printf(m
, "Cursor [%d]:\n", i
);
15753 err_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
15754 err_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
15755 err_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);
15758 for (i
= 0; i
< error
->num_transcoders
; i
++) {
15759 err_printf(m
, "CPU transcoder: %c\n",
15760 transcoder_name(error
->transcoder
[i
].cpu_transcoder
));
15761 err_printf(m
, " Power: %s\n",
15762 error
->transcoder
[i
].power_domain_on
? "on" : "off");
15763 err_printf(m
, " CONF: %08x\n", error
->transcoder
[i
].conf
);
15764 err_printf(m
, " HTOTAL: %08x\n", error
->transcoder
[i
].htotal
);
15765 err_printf(m
, " HBLANK: %08x\n", error
->transcoder
[i
].hblank
);
15766 err_printf(m
, " HSYNC: %08x\n", error
->transcoder
[i
].hsync
);
15767 err_printf(m
, " VTOTAL: %08x\n", error
->transcoder
[i
].vtotal
);
15768 err_printf(m
, " VBLANK: %08x\n", error
->transcoder
[i
].vblank
);
15769 err_printf(m
, " VSYNC: %08x\n", error
->transcoder
[i
].vsync
);
15773 void intel_modeset_preclose(struct drm_device
*dev
, struct drm_file
*file
)
15775 struct intel_crtc
*crtc
;
15777 for_each_intel_crtc(dev
, crtc
) {
15778 struct intel_unpin_work
*work
;
15780 spin_lock_irq(&dev
->event_lock
);
15782 work
= crtc
->unpin_work
;
15784 if (work
&& work
->event
&&
15785 work
->event
->base
.file_priv
== file
) {
15786 kfree(work
->event
);
15787 work
->event
= NULL
;
15790 spin_unlock_irq(&dev
->event_lock
);