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drm/i915: CPT+ pch transcoder workaround
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
43
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
46 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
47 static void intel_increase_pllclock(struct drm_crtc *crtc);
48 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
49
50 typedef struct {
51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
60 } intel_clock_t;
61
62 typedef struct {
63 int min, max;
64 } intel_range_t;
65
66 typedef struct {
67 int dot_limit;
68 int p2_slow, p2_fast;
69 } intel_p2_t;
70
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t;
73 struct intel_limit {
74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
77 int, int, intel_clock_t *, intel_clock_t *);
78 };
79
80 /* FDI */
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
83 int
84 intel_pch_rawclk(struct drm_device *dev)
85 {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87
88 WARN_ON(!HAS_PCH_SPLIT(dev));
89
90 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
91 }
92
93 static bool
94 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
97 static bool
98 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
101
102 static bool
103 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
104 int target, int refclk, intel_clock_t *match_clock,
105 intel_clock_t *best_clock);
106 static bool
107 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
108 int target, int refclk, intel_clock_t *match_clock,
109 intel_clock_t *best_clock);
110
111 static bool
112 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
115
116 static inline u32 /* units of 100MHz */
117 intel_fdi_link_freq(struct drm_device *dev)
118 {
119 if (IS_GEN5(dev)) {
120 struct drm_i915_private *dev_priv = dev->dev_private;
121 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
122 } else
123 return 27;
124 }
125
126 static const intel_limit_t intel_limits_i8xx_dvo = {
127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 2, .max = 33 },
135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 4, .p2_fast = 2 },
137 .find_pll = intel_find_best_PLL,
138 };
139
140 static const intel_limit_t intel_limits_i8xx_lvds = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 1, .max = 6 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 14, .p2_fast = 7 },
151 .find_pll = intel_find_best_PLL,
152 };
153
154 static const intel_limit_t intel_limits_i9xx_sdvo = {
155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 5, .max = 80 },
162 .p1 = { .min = 1, .max = 8 },
163 .p2 = { .dot_limit = 200000,
164 .p2_slow = 10, .p2_fast = 5 },
165 .find_pll = intel_find_best_PLL,
166 };
167
168 static const intel_limit_t intel_limits_i9xx_lvds = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 10, .max = 22 },
174 .m2 = { .min = 5, .max = 9 },
175 .p = { .min = 7, .max = 98 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 112000,
178 .p2_slow = 14, .p2_fast = 7 },
179 .find_pll = intel_find_best_PLL,
180 };
181
182
183 static const intel_limit_t intel_limits_g4x_sdvo = {
184 .dot = { .min = 25000, .max = 270000 },
185 .vco = { .min = 1750000, .max = 3500000},
186 .n = { .min = 1, .max = 4 },
187 .m = { .min = 104, .max = 138 },
188 .m1 = { .min = 17, .max = 23 },
189 .m2 = { .min = 5, .max = 11 },
190 .p = { .min = 10, .max = 30 },
191 .p1 = { .min = 1, .max = 3},
192 .p2 = { .dot_limit = 270000,
193 .p2_slow = 10,
194 .p2_fast = 10
195 },
196 .find_pll = intel_g4x_find_best_PLL,
197 };
198
199 static const intel_limit_t intel_limits_g4x_hdmi = {
200 .dot = { .min = 22000, .max = 400000 },
201 .vco = { .min = 1750000, .max = 3500000},
202 .n = { .min = 1, .max = 4 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 16, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 5, .max = 80 },
207 .p1 = { .min = 1, .max = 8},
208 .p2 = { .dot_limit = 165000,
209 .p2_slow = 10, .p2_fast = 5 },
210 .find_pll = intel_g4x_find_best_PLL,
211 };
212
213 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
214 .dot = { .min = 20000, .max = 115000 },
215 .vco = { .min = 1750000, .max = 3500000 },
216 .n = { .min = 1, .max = 3 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 17, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 28, .max = 112 },
221 .p1 = { .min = 2, .max = 8 },
222 .p2 = { .dot_limit = 0,
223 .p2_slow = 14, .p2_fast = 14
224 },
225 .find_pll = intel_g4x_find_best_PLL,
226 };
227
228 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
229 .dot = { .min = 80000, .max = 224000 },
230 .vco = { .min = 1750000, .max = 3500000 },
231 .n = { .min = 1, .max = 3 },
232 .m = { .min = 104, .max = 138 },
233 .m1 = { .min = 17, .max = 23 },
234 .m2 = { .min = 5, .max = 11 },
235 .p = { .min = 14, .max = 42 },
236 .p1 = { .min = 2, .max = 6 },
237 .p2 = { .dot_limit = 0,
238 .p2_slow = 7, .p2_fast = 7
239 },
240 .find_pll = intel_g4x_find_best_PLL,
241 };
242
243 static const intel_limit_t intel_limits_g4x_display_port = {
244 .dot = { .min = 161670, .max = 227000 },
245 .vco = { .min = 1750000, .max = 3500000},
246 .n = { .min = 1, .max = 2 },
247 .m = { .min = 97, .max = 108 },
248 .m1 = { .min = 0x10, .max = 0x12 },
249 .m2 = { .min = 0x05, .max = 0x06 },
250 .p = { .min = 10, .max = 20 },
251 .p1 = { .min = 1, .max = 2},
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 10, .p2_fast = 10 },
254 .find_pll = intel_find_pll_g4x_dp,
255 };
256
257 static const intel_limit_t intel_limits_pineview_sdvo = {
258 .dot = { .min = 20000, .max = 400000},
259 .vco = { .min = 1700000, .max = 3500000 },
260 /* Pineview's Ncounter is a ring counter */
261 .n = { .min = 3, .max = 6 },
262 .m = { .min = 2, .max = 256 },
263 /* Pineview only has one combined m divider, which we treat as m2. */
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 5, .max = 80 },
267 .p1 = { .min = 1, .max = 8 },
268 .p2 = { .dot_limit = 200000,
269 .p2_slow = 10, .p2_fast = 5 },
270 .find_pll = intel_find_best_PLL,
271 };
272
273 static const intel_limit_t intel_limits_pineview_lvds = {
274 .dot = { .min = 20000, .max = 400000 },
275 .vco = { .min = 1700000, .max = 3500000 },
276 .n = { .min = 3, .max = 6 },
277 .m = { .min = 2, .max = 256 },
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 7, .max = 112 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 112000,
283 .p2_slow = 14, .p2_fast = 14 },
284 .find_pll = intel_find_best_PLL,
285 };
286
287 /* Ironlake / Sandybridge
288 *
289 * We calculate clock using (register_value + 2) for N/M1/M2, so here
290 * the range value for them is (actual_value - 2).
291 */
292 static const intel_limit_t intel_limits_ironlake_dac = {
293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 5 },
296 .m = { .min = 79, .max = 127 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 5, .max = 80 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 10, .p2_fast = 5 },
303 .find_pll = intel_g4x_find_best_PLL,
304 };
305
306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
317 .find_pll = intel_g4x_find_best_PLL,
318 };
319
320 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 127 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 14, .max = 56 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 7, .p2_fast = 7 },
331 .find_pll = intel_g4x_find_best_PLL,
332 };
333
334 /* LVDS 100mhz refclk limits. */
335 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 2 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 28, .max = 112 },
343 .p1 = { .min = 2, .max = 8 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 14, .p2_fast = 14 },
346 .find_pll = intel_g4x_find_best_PLL,
347 };
348
349 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 3 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 14, .max = 42 },
357 .p1 = { .min = 2, .max = 6 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 7, .p2_fast = 7 },
360 .find_pll = intel_g4x_find_best_PLL,
361 };
362
363 static const intel_limit_t intel_limits_ironlake_display_port = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000},
366 .n = { .min = 1, .max = 2 },
367 .m = { .min = 81, .max = 90 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 10, .max = 20 },
371 .p1 = { .min = 1, .max = 2},
372 .p2 = { .dot_limit = 0,
373 .p2_slow = 10, .p2_fast = 10 },
374 .find_pll = intel_find_pll_ironlake_dp,
375 };
376
377 static const intel_limit_t intel_limits_vlv_dac = {
378 .dot = { .min = 25000, .max = 270000 },
379 .vco = { .min = 4000000, .max = 6000000 },
380 .n = { .min = 1, .max = 7 },
381 .m = { .min = 22, .max = 450 }, /* guess */
382 .m1 = { .min = 2, .max = 3 },
383 .m2 = { .min = 11, .max = 156 },
384 .p = { .min = 10, .max = 30 },
385 .p1 = { .min = 2, .max = 3 },
386 .p2 = { .dot_limit = 270000,
387 .p2_slow = 2, .p2_fast = 20 },
388 .find_pll = intel_vlv_find_best_pll,
389 };
390
391 static const intel_limit_t intel_limits_vlv_hdmi = {
392 .dot = { .min = 20000, .max = 165000 },
393 .vco = { .min = 4000000, .max = 5994000},
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 60, .max = 300 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 2, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
403 };
404
405 static const intel_limit_t intel_limits_vlv_dp = {
406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 22, .max = 450 },
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
417 };
418
419 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
420 {
421 unsigned long flags;
422 u32 val = 0;
423
424 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
425 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
426 DRM_ERROR("DPIO idle wait timed out\n");
427 goto out_unlock;
428 }
429
430 I915_WRITE(DPIO_REG, reg);
431 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
432 DPIO_BYTE);
433 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
434 DRM_ERROR("DPIO read wait timed out\n");
435 goto out_unlock;
436 }
437 val = I915_READ(DPIO_DATA);
438
439 out_unlock:
440 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
441 return val;
442 }
443
444 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
445 u32 val)
446 {
447 unsigned long flags;
448
449 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
450 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
451 DRM_ERROR("DPIO idle wait timed out\n");
452 goto out_unlock;
453 }
454
455 I915_WRITE(DPIO_DATA, val);
456 I915_WRITE(DPIO_REG, reg);
457 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
458 DPIO_BYTE);
459 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
460 DRM_ERROR("DPIO write wait timed out\n");
461
462 out_unlock:
463 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
464 }
465
466 static void vlv_init_dpio(struct drm_device *dev)
467 {
468 struct drm_i915_private *dev_priv = dev->dev_private;
469
470 /* Reset the DPIO config */
471 I915_WRITE(DPIO_CTL, 0);
472 POSTING_READ(DPIO_CTL);
473 I915_WRITE(DPIO_CTL, 1);
474 POSTING_READ(DPIO_CTL);
475 }
476
477 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
478 {
479 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
480 return 1;
481 }
482
483 static const struct dmi_system_id intel_dual_link_lvds[] = {
484 {
485 .callback = intel_dual_link_lvds_callback,
486 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
487 .matches = {
488 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
489 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
490 },
491 },
492 { } /* terminating entry */
493 };
494
495 static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
496 unsigned int reg)
497 {
498 unsigned int val;
499
500 /* use the module option value if specified */
501 if (i915_lvds_channel_mode > 0)
502 return i915_lvds_channel_mode == 2;
503
504 if (dmi_check_system(intel_dual_link_lvds))
505 return true;
506
507 if (dev_priv->lvds_val)
508 val = dev_priv->lvds_val;
509 else {
510 /* BIOS should set the proper LVDS register value at boot, but
511 * in reality, it doesn't set the value when the lid is closed;
512 * we need to check "the value to be set" in VBT when LVDS
513 * register is uninitialized.
514 */
515 val = I915_READ(reg);
516 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
517 val = dev_priv->bios_lvds_val;
518 dev_priv->lvds_val = val;
519 }
520 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
521 }
522
523 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
524 int refclk)
525 {
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 const intel_limit_t *limit;
529
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
531 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
532 /* LVDS dual channel */
533 if (refclk == 100000)
534 limit = &intel_limits_ironlake_dual_lvds_100m;
535 else
536 limit = &intel_limits_ironlake_dual_lvds;
537 } else {
538 if (refclk == 100000)
539 limit = &intel_limits_ironlake_single_lvds_100m;
540 else
541 limit = &intel_limits_ironlake_single_lvds;
542 }
543 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
544 HAS_eDP)
545 limit = &intel_limits_ironlake_display_port;
546 else
547 limit = &intel_limits_ironlake_dac;
548
549 return limit;
550 }
551
552 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
553 {
554 struct drm_device *dev = crtc->dev;
555 struct drm_i915_private *dev_priv = dev->dev_private;
556 const intel_limit_t *limit;
557
558 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
559 if (is_dual_link_lvds(dev_priv, LVDS))
560 /* LVDS with dual channel */
561 limit = &intel_limits_g4x_dual_channel_lvds;
562 else
563 /* LVDS with dual channel */
564 limit = &intel_limits_g4x_single_channel_lvds;
565 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
566 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
567 limit = &intel_limits_g4x_hdmi;
568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
569 limit = &intel_limits_g4x_sdvo;
570 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
571 limit = &intel_limits_g4x_display_port;
572 } else /* The option is for other outputs */
573 limit = &intel_limits_i9xx_sdvo;
574
575 return limit;
576 }
577
578 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
579 {
580 struct drm_device *dev = crtc->dev;
581 const intel_limit_t *limit;
582
583 if (HAS_PCH_SPLIT(dev))
584 limit = intel_ironlake_limit(crtc, refclk);
585 else if (IS_G4X(dev)) {
586 limit = intel_g4x_limit(crtc);
587 } else if (IS_PINEVIEW(dev)) {
588 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
589 limit = &intel_limits_pineview_lvds;
590 else
591 limit = &intel_limits_pineview_sdvo;
592 } else if (IS_VALLEYVIEW(dev)) {
593 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
594 limit = &intel_limits_vlv_dac;
595 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
596 limit = &intel_limits_vlv_hdmi;
597 else
598 limit = &intel_limits_vlv_dp;
599 } else if (!IS_GEN2(dev)) {
600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
601 limit = &intel_limits_i9xx_lvds;
602 else
603 limit = &intel_limits_i9xx_sdvo;
604 } else {
605 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
606 limit = &intel_limits_i8xx_lvds;
607 else
608 limit = &intel_limits_i8xx_dvo;
609 }
610 return limit;
611 }
612
613 /* m1 is reserved as 0 in Pineview, n is a ring counter */
614 static void pineview_clock(int refclk, intel_clock_t *clock)
615 {
616 clock->m = clock->m2 + 2;
617 clock->p = clock->p1 * clock->p2;
618 clock->vco = refclk * clock->m / clock->n;
619 clock->dot = clock->vco / clock->p;
620 }
621
622 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
623 {
624 if (IS_PINEVIEW(dev)) {
625 pineview_clock(refclk, clock);
626 return;
627 }
628 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
629 clock->p = clock->p1 * clock->p2;
630 clock->vco = refclk * clock->m / (clock->n + 2);
631 clock->dot = clock->vco / clock->p;
632 }
633
634 /**
635 * Returns whether any output on the specified pipe is of the specified type
636 */
637 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
638 {
639 struct drm_device *dev = crtc->dev;
640 struct intel_encoder *encoder;
641
642 for_each_encoder_on_crtc(dev, crtc, encoder)
643 if (encoder->type == type)
644 return true;
645
646 return false;
647 }
648
649 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
650 /**
651 * Returns whether the given set of divisors are valid for a given refclk with
652 * the given connectors.
653 */
654
655 static bool intel_PLL_is_valid(struct drm_device *dev,
656 const intel_limit_t *limit,
657 const intel_clock_t *clock)
658 {
659 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
660 INTELPllInvalid("p1 out of range\n");
661 if (clock->p < limit->p.min || limit->p.max < clock->p)
662 INTELPllInvalid("p out of range\n");
663 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
664 INTELPllInvalid("m2 out of range\n");
665 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
666 INTELPllInvalid("m1 out of range\n");
667 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
668 INTELPllInvalid("m1 <= m2\n");
669 if (clock->m < limit->m.min || limit->m.max < clock->m)
670 INTELPllInvalid("m out of range\n");
671 if (clock->n < limit->n.min || limit->n.max < clock->n)
672 INTELPllInvalid("n out of range\n");
673 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
674 INTELPllInvalid("vco out of range\n");
675 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
676 * connector, etc., rather than just a single range.
677 */
678 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
679 INTELPllInvalid("dot out of range\n");
680
681 return true;
682 }
683
684 static bool
685 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
686 int target, int refclk, intel_clock_t *match_clock,
687 intel_clock_t *best_clock)
688
689 {
690 struct drm_device *dev = crtc->dev;
691 struct drm_i915_private *dev_priv = dev->dev_private;
692 intel_clock_t clock;
693 int err = target;
694
695 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
696 (I915_READ(LVDS)) != 0) {
697 /*
698 * For LVDS, if the panel is on, just rely on its current
699 * settings for dual-channel. We haven't figured out how to
700 * reliably set up different single/dual channel state, if we
701 * even can.
702 */
703 if (is_dual_link_lvds(dev_priv, LVDS))
704 clock.p2 = limit->p2.p2_fast;
705 else
706 clock.p2 = limit->p2.p2_slow;
707 } else {
708 if (target < limit->p2.dot_limit)
709 clock.p2 = limit->p2.p2_slow;
710 else
711 clock.p2 = limit->p2.p2_fast;
712 }
713
714 memset(best_clock, 0, sizeof(*best_clock));
715
716 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
717 clock.m1++) {
718 for (clock.m2 = limit->m2.min;
719 clock.m2 <= limit->m2.max; clock.m2++) {
720 /* m1 is always 0 in Pineview */
721 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
722 break;
723 for (clock.n = limit->n.min;
724 clock.n <= limit->n.max; clock.n++) {
725 for (clock.p1 = limit->p1.min;
726 clock.p1 <= limit->p1.max; clock.p1++) {
727 int this_err;
728
729 intel_clock(dev, refclk, &clock);
730 if (!intel_PLL_is_valid(dev, limit,
731 &clock))
732 continue;
733 if (match_clock &&
734 clock.p != match_clock->p)
735 continue;
736
737 this_err = abs(clock.dot - target);
738 if (this_err < err) {
739 *best_clock = clock;
740 err = this_err;
741 }
742 }
743 }
744 }
745 }
746
747 return (err != target);
748 }
749
750 static bool
751 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
754 {
755 struct drm_device *dev = crtc->dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 intel_clock_t clock;
758 int max_n;
759 bool found;
760 /* approximately equals target * 0.00585 */
761 int err_most = (target >> 8) + (target >> 9);
762 found = false;
763
764 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
765 int lvds_reg;
766
767 if (HAS_PCH_SPLIT(dev))
768 lvds_reg = PCH_LVDS;
769 else
770 lvds_reg = LVDS;
771 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
772 LVDS_CLKB_POWER_UP)
773 clock.p2 = limit->p2.p2_fast;
774 else
775 clock.p2 = limit->p2.p2_slow;
776 } else {
777 if (target < limit->p2.dot_limit)
778 clock.p2 = limit->p2.p2_slow;
779 else
780 clock.p2 = limit->p2.p2_fast;
781 }
782
783 memset(best_clock, 0, sizeof(*best_clock));
784 max_n = limit->n.max;
785 /* based on hardware requirement, prefer smaller n to precision */
786 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
787 /* based on hardware requirement, prefere larger m1,m2 */
788 for (clock.m1 = limit->m1.max;
789 clock.m1 >= limit->m1.min; clock.m1--) {
790 for (clock.m2 = limit->m2.max;
791 clock.m2 >= limit->m2.min; clock.m2--) {
792 for (clock.p1 = limit->p1.max;
793 clock.p1 >= limit->p1.min; clock.p1--) {
794 int this_err;
795
796 intel_clock(dev, refclk, &clock);
797 if (!intel_PLL_is_valid(dev, limit,
798 &clock))
799 continue;
800 if (match_clock &&
801 clock.p != match_clock->p)
802 continue;
803
804 this_err = abs(clock.dot - target);
805 if (this_err < err_most) {
806 *best_clock = clock;
807 err_most = this_err;
808 max_n = clock.n;
809 found = true;
810 }
811 }
812 }
813 }
814 }
815 return found;
816 }
817
818 static bool
819 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
820 int target, int refclk, intel_clock_t *match_clock,
821 intel_clock_t *best_clock)
822 {
823 struct drm_device *dev = crtc->dev;
824 intel_clock_t clock;
825
826 if (target < 200000) {
827 clock.n = 1;
828 clock.p1 = 2;
829 clock.p2 = 10;
830 clock.m1 = 12;
831 clock.m2 = 9;
832 } else {
833 clock.n = 2;
834 clock.p1 = 1;
835 clock.p2 = 10;
836 clock.m1 = 14;
837 clock.m2 = 8;
838 }
839 intel_clock(dev, refclk, &clock);
840 memcpy(best_clock, &clock, sizeof(intel_clock_t));
841 return true;
842 }
843
844 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
845 static bool
846 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
847 int target, int refclk, intel_clock_t *match_clock,
848 intel_clock_t *best_clock)
849 {
850 intel_clock_t clock;
851 if (target < 200000) {
852 clock.p1 = 2;
853 clock.p2 = 10;
854 clock.n = 2;
855 clock.m1 = 23;
856 clock.m2 = 8;
857 } else {
858 clock.p1 = 1;
859 clock.p2 = 10;
860 clock.n = 1;
861 clock.m1 = 14;
862 clock.m2 = 2;
863 }
864 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
865 clock.p = (clock.p1 * clock.p2);
866 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
867 clock.vco = 0;
868 memcpy(best_clock, &clock, sizeof(intel_clock_t));
869 return true;
870 }
871 static bool
872 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875 {
876 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
877 u32 m, n, fastclk;
878 u32 updrate, minupdate, fracbits, p;
879 unsigned long bestppm, ppm, absppm;
880 int dotclk, flag;
881
882 flag = 0;
883 dotclk = target * 1000;
884 bestppm = 1000000;
885 ppm = absppm = 0;
886 fastclk = dotclk / (2*100);
887 updrate = 0;
888 minupdate = 19200;
889 fracbits = 1;
890 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
891 bestm1 = bestm2 = bestp1 = bestp2 = 0;
892
893 /* based on hardware requirement, prefer smaller n to precision */
894 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
895 updrate = refclk / n;
896 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
897 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
898 if (p2 > 10)
899 p2 = p2 - 1;
900 p = p1 * p2;
901 /* based on hardware requirement, prefer bigger m1,m2 values */
902 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
903 m2 = (((2*(fastclk * p * n / m1 )) +
904 refclk) / (2*refclk));
905 m = m1 * m2;
906 vco = updrate * m;
907 if (vco >= limit->vco.min && vco < limit->vco.max) {
908 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
909 absppm = (ppm > 0) ? ppm : (-ppm);
910 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
911 bestppm = 0;
912 flag = 1;
913 }
914 if (absppm < bestppm - 10) {
915 bestppm = absppm;
916 flag = 1;
917 }
918 if (flag) {
919 bestn = n;
920 bestm1 = m1;
921 bestm2 = m2;
922 bestp1 = p1;
923 bestp2 = p2;
924 flag = 0;
925 }
926 }
927 }
928 }
929 }
930 }
931 best_clock->n = bestn;
932 best_clock->m1 = bestm1;
933 best_clock->m2 = bestm2;
934 best_clock->p1 = bestp1;
935 best_clock->p2 = bestp2;
936
937 return true;
938 }
939
940 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
941 enum pipe pipe)
942 {
943 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
945
946 return intel_crtc->cpu_transcoder;
947 }
948
949 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
950 {
951 struct drm_i915_private *dev_priv = dev->dev_private;
952 u32 frame, frame_reg = PIPEFRAME(pipe);
953
954 frame = I915_READ(frame_reg);
955
956 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
957 DRM_DEBUG_KMS("vblank wait timed out\n");
958 }
959
960 /**
961 * intel_wait_for_vblank - wait for vblank on a given pipe
962 * @dev: drm device
963 * @pipe: pipe to wait for
964 *
965 * Wait for vblank to occur on a given pipe. Needed for various bits of
966 * mode setting code.
967 */
968 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
969 {
970 struct drm_i915_private *dev_priv = dev->dev_private;
971 int pipestat_reg = PIPESTAT(pipe);
972
973 if (INTEL_INFO(dev)->gen >= 5) {
974 ironlake_wait_for_vblank(dev, pipe);
975 return;
976 }
977
978 /* Clear existing vblank status. Note this will clear any other
979 * sticky status fields as well.
980 *
981 * This races with i915_driver_irq_handler() with the result
982 * that either function could miss a vblank event. Here it is not
983 * fatal, as we will either wait upon the next vblank interrupt or
984 * timeout. Generally speaking intel_wait_for_vblank() is only
985 * called during modeset at which time the GPU should be idle and
986 * should *not* be performing page flips and thus not waiting on
987 * vblanks...
988 * Currently, the result of us stealing a vblank from the irq
989 * handler is that a single frame will be skipped during swapbuffers.
990 */
991 I915_WRITE(pipestat_reg,
992 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
993
994 /* Wait for vblank interrupt bit to set */
995 if (wait_for(I915_READ(pipestat_reg) &
996 PIPE_VBLANK_INTERRUPT_STATUS,
997 50))
998 DRM_DEBUG_KMS("vblank wait timed out\n");
999 }
1000
1001 /*
1002 * intel_wait_for_pipe_off - wait for pipe to turn off
1003 * @dev: drm device
1004 * @pipe: pipe to wait for
1005 *
1006 * After disabling a pipe, we can't wait for vblank in the usual way,
1007 * spinning on the vblank interrupt status bit, since we won't actually
1008 * see an interrupt when the pipe is disabled.
1009 *
1010 * On Gen4 and above:
1011 * wait for the pipe register state bit to turn off
1012 *
1013 * Otherwise:
1014 * wait for the display line value to settle (it usually
1015 * ends up stopping at the start of the next frame).
1016 *
1017 */
1018 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
1019 {
1020 struct drm_i915_private *dev_priv = dev->dev_private;
1021 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1022 pipe);
1023
1024 if (INTEL_INFO(dev)->gen >= 4) {
1025 int reg = PIPECONF(cpu_transcoder);
1026
1027 /* Wait for the Pipe State to go off */
1028 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1029 100))
1030 WARN(1, "pipe_off wait timed out\n");
1031 } else {
1032 u32 last_line, line_mask;
1033 int reg = PIPEDSL(pipe);
1034 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1035
1036 if (IS_GEN2(dev))
1037 line_mask = DSL_LINEMASK_GEN2;
1038 else
1039 line_mask = DSL_LINEMASK_GEN3;
1040
1041 /* Wait for the display line to settle */
1042 do {
1043 last_line = I915_READ(reg) & line_mask;
1044 mdelay(5);
1045 } while (((I915_READ(reg) & line_mask) != last_line) &&
1046 time_after(timeout, jiffies));
1047 if (time_after(jiffies, timeout))
1048 WARN(1, "pipe_off wait timed out\n");
1049 }
1050 }
1051
1052 static const char *state_string(bool enabled)
1053 {
1054 return enabled ? "on" : "off";
1055 }
1056
1057 /* Only for pre-ILK configs */
1058 static void assert_pll(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, bool state)
1060 {
1061 int reg;
1062 u32 val;
1063 bool cur_state;
1064
1065 reg = DPLL(pipe);
1066 val = I915_READ(reg);
1067 cur_state = !!(val & DPLL_VCO_ENABLE);
1068 WARN(cur_state != state,
1069 "PLL state assertion failure (expected %s, current %s)\n",
1070 state_string(state), state_string(cur_state));
1071 }
1072 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1073 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1074
1075 /* For ILK+ */
1076 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1077 struct intel_pch_pll *pll,
1078 struct intel_crtc *crtc,
1079 bool state)
1080 {
1081 u32 val;
1082 bool cur_state;
1083
1084 if (HAS_PCH_LPT(dev_priv->dev)) {
1085 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1086 return;
1087 }
1088
1089 if (WARN (!pll,
1090 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1091 return;
1092
1093 val = I915_READ(pll->pll_reg);
1094 cur_state = !!(val & DPLL_VCO_ENABLE);
1095 WARN(cur_state != state,
1096 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1097 pll->pll_reg, state_string(state), state_string(cur_state), val);
1098
1099 /* Make sure the selected PLL is correctly attached to the transcoder */
1100 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1101 u32 pch_dpll;
1102
1103 pch_dpll = I915_READ(PCH_DPLL_SEL);
1104 cur_state = pll->pll_reg == _PCH_DPLL_B;
1105 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1106 "PLL[%d] not attached to this transcoder %d: %08x\n",
1107 cur_state, crtc->pipe, pch_dpll)) {
1108 cur_state = !!(val >> (4*crtc->pipe + 3));
1109 WARN(cur_state != state,
1110 "PLL[%d] not %s on this transcoder %d: %08x\n",
1111 pll->pll_reg == _PCH_DPLL_B,
1112 state_string(state),
1113 crtc->pipe,
1114 val);
1115 }
1116 }
1117 }
1118 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1119 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1120
1121 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1122 enum pipe pipe, bool state)
1123 {
1124 int reg;
1125 u32 val;
1126 bool cur_state;
1127 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1128 pipe);
1129
1130 if (IS_HASWELL(dev_priv->dev)) {
1131 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1132 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1133 val = I915_READ(reg);
1134 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1135 } else {
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_TX_ENABLE);
1139 }
1140 WARN(cur_state != state,
1141 "FDI TX state assertion failure (expected %s, current %s)\n",
1142 state_string(state), state_string(cur_state));
1143 }
1144 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1145 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1146
1147 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1148 enum pipe pipe, bool state)
1149 {
1150 int reg;
1151 u32 val;
1152 bool cur_state;
1153
1154 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1155 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1156 return;
1157 } else {
1158 reg = FDI_RX_CTL(pipe);
1159 val = I915_READ(reg);
1160 cur_state = !!(val & FDI_RX_ENABLE);
1161 }
1162 WARN(cur_state != state,
1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165 }
1166 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171 {
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
1176 if (dev_priv->info->gen == 5)
1177 return;
1178
1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1180 if (IS_HASWELL(dev_priv->dev))
1181 return;
1182
1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
1185 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1186 }
1187
1188 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int reg;
1192 u32 val;
1193
1194 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1195 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1196 return;
1197 }
1198 reg = FDI_RX_CTL(pipe);
1199 val = I915_READ(reg);
1200 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1201 }
1202
1203 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205 {
1206 int pp_reg, lvds_reg;
1207 u32 val;
1208 enum pipe panel_pipe = PIPE_A;
1209 bool locked = true;
1210
1211 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1212 pp_reg = PCH_PP_CONTROL;
1213 lvds_reg = PCH_LVDS;
1214 } else {
1215 pp_reg = PP_CONTROL;
1216 lvds_reg = LVDS;
1217 }
1218
1219 val = I915_READ(pp_reg);
1220 if (!(val & PANEL_POWER_ON) ||
1221 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1222 locked = false;
1223
1224 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1225 panel_pipe = PIPE_B;
1226
1227 WARN(panel_pipe == pipe && locked,
1228 "panel assertion failure, pipe %c regs locked\n",
1229 pipe_name(pipe));
1230 }
1231
1232 void assert_pipe(struct drm_i915_private *dev_priv,
1233 enum pipe pipe, bool state)
1234 {
1235 int reg;
1236 u32 val;
1237 bool cur_state;
1238 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1239 pipe);
1240
1241 /* if we need the pipe A quirk it must be always on */
1242 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1243 state = true;
1244
1245 reg = PIPECONF(cpu_transcoder);
1246 val = I915_READ(reg);
1247 cur_state = !!(val & PIPECONF_ENABLE);
1248 WARN(cur_state != state,
1249 "pipe %c assertion failure (expected %s, current %s)\n",
1250 pipe_name(pipe), state_string(state), state_string(cur_state));
1251 }
1252
1253 static void assert_plane(struct drm_i915_private *dev_priv,
1254 enum plane plane, bool state)
1255 {
1256 int reg;
1257 u32 val;
1258 bool cur_state;
1259
1260 reg = DSPCNTR(plane);
1261 val = I915_READ(reg);
1262 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1263 WARN(cur_state != state,
1264 "plane %c assertion failure (expected %s, current %s)\n",
1265 plane_name(plane), state_string(state), state_string(cur_state));
1266 }
1267
1268 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1269 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1270
1271 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1272 enum pipe pipe)
1273 {
1274 int reg, i;
1275 u32 val;
1276 int cur_pipe;
1277
1278 /* Planes are fixed to pipes on ILK+ */
1279 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1280 reg = DSPCNTR(pipe);
1281 val = I915_READ(reg);
1282 WARN((val & DISPLAY_PLANE_ENABLE),
1283 "plane %c assertion failure, should be disabled but not\n",
1284 plane_name(pipe));
1285 return;
1286 }
1287
1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < 2; i++) {
1290 reg = DSPCNTR(i);
1291 val = I915_READ(reg);
1292 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1293 DISPPLANE_SEL_PIPE_SHIFT;
1294 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1295 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1296 plane_name(i), pipe_name(pipe));
1297 }
1298 }
1299
1300 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1301 {
1302 u32 val;
1303 bool enabled;
1304
1305 if (HAS_PCH_LPT(dev_priv->dev)) {
1306 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1307 return;
1308 }
1309
1310 val = I915_READ(PCH_DREF_CONTROL);
1311 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1312 DREF_SUPERSPREAD_SOURCE_MASK));
1313 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 }
1315
1316 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1317 enum pipe pipe)
1318 {
1319 int reg;
1320 u32 val;
1321 bool enabled;
1322
1323 reg = TRANSCONF(pipe);
1324 val = I915_READ(reg);
1325 enabled = !!(val & TRANS_ENABLE);
1326 WARN(enabled,
1327 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1328 pipe_name(pipe));
1329 }
1330
1331 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1332 enum pipe pipe, u32 port_sel, u32 val)
1333 {
1334 if ((val & DP_PORT_EN) == 0)
1335 return false;
1336
1337 if (HAS_PCH_CPT(dev_priv->dev)) {
1338 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1339 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1340 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 return false;
1342 } else {
1343 if ((val & DP_PIPE_MASK) != (pipe << 30))
1344 return false;
1345 }
1346 return true;
1347 }
1348
1349 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1350 enum pipe pipe, u32 val)
1351 {
1352 if ((val & PORT_ENABLE) == 0)
1353 return false;
1354
1355 if (HAS_PCH_CPT(dev_priv->dev)) {
1356 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1357 return false;
1358 } else {
1359 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1360 return false;
1361 }
1362 return true;
1363 }
1364
1365 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe, u32 val)
1367 {
1368 if ((val & LVDS_PORT_EN) == 0)
1369 return false;
1370
1371 if (HAS_PCH_CPT(dev_priv->dev)) {
1372 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 return false;
1374 } else {
1375 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1376 return false;
1377 }
1378 return true;
1379 }
1380
1381 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe, u32 val)
1383 {
1384 if ((val & ADPA_DAC_ENABLE) == 0)
1385 return false;
1386 if (HAS_PCH_CPT(dev_priv->dev)) {
1387 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 return false;
1389 } else {
1390 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1391 return false;
1392 }
1393 return true;
1394 }
1395
1396 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1397 enum pipe pipe, int reg, u32 port_sel)
1398 {
1399 u32 val = I915_READ(reg);
1400 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1401 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1402 reg, pipe_name(pipe));
1403
1404 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1405 && (val & DP_PIPEB_SELECT),
1406 "IBX PCH dp port still using transcoder B\n");
1407 }
1408
1409 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1410 enum pipe pipe, int reg)
1411 {
1412 u32 val = I915_READ(reg);
1413 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1414 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1415 reg, pipe_name(pipe));
1416
1417 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1418 && (val & SDVO_PIPE_B_SELECT),
1419 "IBX PCH hdmi port still using transcoder B\n");
1420 }
1421
1422 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1423 enum pipe pipe)
1424 {
1425 int reg;
1426 u32 val;
1427
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1429 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1430 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431
1432 reg = PCH_ADPA;
1433 val = I915_READ(reg);
1434 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1435 "PCH VGA enabled on transcoder %c, should be disabled\n",
1436 pipe_name(pipe));
1437
1438 reg = PCH_LVDS;
1439 val = I915_READ(reg);
1440 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1441 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442 pipe_name(pipe));
1443
1444 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1445 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1446 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1447 }
1448
1449 /**
1450 * intel_enable_pll - enable a PLL
1451 * @dev_priv: i915 private structure
1452 * @pipe: pipe PLL to enable
1453 *
1454 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1455 * make sure the PLL reg is writable first though, since the panel write
1456 * protect mechanism may be enabled.
1457 *
1458 * Note! This is for pre-ILK only.
1459 *
1460 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1461 */
1462 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1463 {
1464 int reg;
1465 u32 val;
1466
1467 /* No really, not for ILK+ */
1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1469
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1473
1474 reg = DPLL(pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1477
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1480 POSTING_READ(reg);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1483 POSTING_READ(reg);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487 udelay(150); /* wait for warmup */
1488 }
1489
1490 /**
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1494 *
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1496 *
1497 * Note! This is for pre-ILK only.
1498 */
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1500 {
1501 int reg;
1502 u32 val;
1503
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1506 return;
1507
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1510
1511 reg = DPLL(pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1515 POSTING_READ(reg);
1516 }
1517
1518 /* SBI access */
1519 static void
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1521 {
1522 unsigned long flags;
1523
1524 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1525 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to become ready\n");
1528 goto out_unlock;
1529 }
1530
1531 I915_WRITE(SBI_ADDR,
1532 (reg << 16));
1533 I915_WRITE(SBI_DATA,
1534 value);
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRWR);
1538
1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1542 goto out_unlock;
1543 }
1544
1545 out_unlock:
1546 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1547 }
1548
1549 static u32
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1551 {
1552 unsigned long flags;
1553 u32 value = 0;
1554
1555 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1557 100)) {
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1559 goto out_unlock;
1560 }
1561
1562 I915_WRITE(SBI_ADDR,
1563 (reg << 16));
1564 I915_WRITE(SBI_CTL_STAT,
1565 SBI_BUSY |
1566 SBI_CTL_OP_CRRD);
1567
1568 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1569 100)) {
1570 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1571 goto out_unlock;
1572 }
1573
1574 value = I915_READ(SBI_DATA);
1575
1576 out_unlock:
1577 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1578 return value;
1579 }
1580
1581 /**
1582 * ironlake_enable_pch_pll - enable PCH PLL
1583 * @dev_priv: i915 private structure
1584 * @pipe: pipe PLL to enable
1585 *
1586 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1587 * drives the transcoder clock.
1588 */
1589 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1590 {
1591 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1592 struct intel_pch_pll *pll;
1593 int reg;
1594 u32 val;
1595
1596 /* PCH PLLs only available on ILK, SNB and IVB */
1597 BUG_ON(dev_priv->info->gen < 5);
1598 pll = intel_crtc->pch_pll;
1599 if (pll == NULL)
1600 return;
1601
1602 if (WARN_ON(pll->refcount == 0))
1603 return;
1604
1605 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1606 pll->pll_reg, pll->active, pll->on,
1607 intel_crtc->base.base.id);
1608
1609 /* PCH refclock must be enabled first */
1610 assert_pch_refclk_enabled(dev_priv);
1611
1612 if (pll->active++ && pll->on) {
1613 assert_pch_pll_enabled(dev_priv, pll, NULL);
1614 return;
1615 }
1616
1617 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1618
1619 reg = pll->pll_reg;
1620 val = I915_READ(reg);
1621 val |= DPLL_VCO_ENABLE;
1622 I915_WRITE(reg, val);
1623 POSTING_READ(reg);
1624 udelay(200);
1625
1626 pll->on = true;
1627 }
1628
1629 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1630 {
1631 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1632 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1633 int reg;
1634 u32 val;
1635
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
1638 if (pll == NULL)
1639 return;
1640
1641 if (WARN_ON(pll->refcount == 0))
1642 return;
1643
1644 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1645 pll->pll_reg, pll->active, pll->on,
1646 intel_crtc->base.base.id);
1647
1648 if (WARN_ON(pll->active == 0)) {
1649 assert_pch_pll_disabled(dev_priv, pll, NULL);
1650 return;
1651 }
1652
1653 if (--pll->active) {
1654 assert_pch_pll_enabled(dev_priv, pll, NULL);
1655 return;
1656 }
1657
1658 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1659
1660 /* Make sure transcoder isn't still depending on us */
1661 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1662
1663 reg = pll->pll_reg;
1664 val = I915_READ(reg);
1665 val &= ~DPLL_VCO_ENABLE;
1666 I915_WRITE(reg, val);
1667 POSTING_READ(reg);
1668 udelay(200);
1669
1670 pll->on = false;
1671 }
1672
1673 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
1675 {
1676 struct drm_device *dev = dev_priv->dev;
1677 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1678 uint32_t reg, val, pipeconf_val;
1679
1680 /* PCH only available on ILK+ */
1681 BUG_ON(dev_priv->info->gen < 5);
1682
1683 /* Make sure PCH DPLL is enabled */
1684 assert_pch_pll_enabled(dev_priv,
1685 to_intel_crtc(crtc)->pch_pll,
1686 to_intel_crtc(crtc));
1687
1688 /* FDI must be feeding us bits for PCH ports */
1689 assert_fdi_tx_enabled(dev_priv, pipe);
1690 assert_fdi_rx_enabled(dev_priv, pipe);
1691
1692 if (HAS_PCH_CPT(dev)) {
1693 /* Workaround: Set the timing override bit before enabling the
1694 * pch transcoder. */
1695 reg = TRANS_CHICKEN2(pipe);
1696 val = I915_READ(reg);
1697 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1698 I915_WRITE(reg, val);
1699 }
1700
1701 reg = TRANSCONF(pipe);
1702 val = I915_READ(reg);
1703 pipeconf_val = I915_READ(PIPECONF(pipe));
1704
1705 if (HAS_PCH_IBX(dev_priv->dev)) {
1706 /*
1707 * make the BPC in transcoder be consistent with
1708 * that in pipeconf reg.
1709 */
1710 val &= ~PIPE_BPC_MASK;
1711 val |= pipeconf_val & PIPE_BPC_MASK;
1712 }
1713
1714 val &= ~TRANS_INTERLACE_MASK;
1715 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1716 if (HAS_PCH_IBX(dev_priv->dev) &&
1717 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1718 val |= TRANS_LEGACY_INTERLACED_ILK;
1719 else
1720 val |= TRANS_INTERLACED;
1721 else
1722 val |= TRANS_PROGRESSIVE;
1723
1724 I915_WRITE(reg, val | TRANS_ENABLE);
1725 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1726 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1727 }
1728
1729 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1730 enum transcoder cpu_transcoder)
1731 {
1732 u32 val, pipeconf_val;
1733
1734 /* PCH only available on ILK+ */
1735 BUG_ON(dev_priv->info->gen < 5);
1736
1737 /* FDI must be feeding us bits for PCH ports */
1738 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1739 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1740
1741 /* Workaround: set timing override bit. */
1742 val = I915_READ(_TRANSA_CHICKEN2);
1743 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1744 I915_WRITE(_TRANSA_CHICKEN2, val);
1745
1746 val = TRANS_ENABLE;
1747 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1748
1749 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1750 PIPECONF_INTERLACED_ILK)
1751 val |= TRANS_INTERLACED;
1752 else
1753 val |= TRANS_PROGRESSIVE;
1754
1755 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1756 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1757 DRM_ERROR("Failed to enable PCH transcoder\n");
1758 }
1759
1760 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1761 enum pipe pipe)
1762 {
1763 struct drm_device *dev = dev_priv->dev;
1764 uint32_t reg, val;
1765
1766 /* FDI relies on the transcoder */
1767 assert_fdi_tx_disabled(dev_priv, pipe);
1768 assert_fdi_rx_disabled(dev_priv, pipe);
1769
1770 /* Ports must be off as well */
1771 assert_pch_ports_disabled(dev_priv, pipe);
1772
1773 reg = TRANSCONF(pipe);
1774 val = I915_READ(reg);
1775 val &= ~TRANS_ENABLE;
1776 I915_WRITE(reg, val);
1777 /* wait for PCH transcoder off, transcoder state */
1778 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1779 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1780
1781 if (!HAS_PCH_IBX(dev)) {
1782 /* Workaround: Clear the timing override chicken bit again. */
1783 reg = TRANS_CHICKEN2(pipe);
1784 val = I915_READ(reg);
1785 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1786 I915_WRITE(reg, val);
1787 }
1788 }
1789
1790 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1791 {
1792 u32 val;
1793
1794 val = I915_READ(_TRANSACONF);
1795 val &= ~TRANS_ENABLE;
1796 I915_WRITE(_TRANSACONF, val);
1797 /* wait for PCH transcoder off, transcoder state */
1798 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1799 DRM_ERROR("Failed to disable PCH transcoder\n");
1800
1801 /* Workaround: clear timing override bit. */
1802 val = I915_READ(_TRANSA_CHICKEN2);
1803 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1804 I915_WRITE(_TRANSA_CHICKEN2, val);
1805 }
1806
1807 /**
1808 * intel_enable_pipe - enable a pipe, asserting requirements
1809 * @dev_priv: i915 private structure
1810 * @pipe: pipe to enable
1811 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1812 *
1813 * Enable @pipe, making sure that various hardware specific requirements
1814 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1815 *
1816 * @pipe should be %PIPE_A or %PIPE_B.
1817 *
1818 * Will wait until the pipe is actually running (i.e. first vblank) before
1819 * returning.
1820 */
1821 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1822 bool pch_port)
1823 {
1824 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1825 pipe);
1826 int reg;
1827 u32 val;
1828
1829 /*
1830 * A pipe without a PLL won't actually be able to drive bits from
1831 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1832 * need the check.
1833 */
1834 if (!HAS_PCH_SPLIT(dev_priv->dev))
1835 assert_pll_enabled(dev_priv, pipe);
1836 else {
1837 if (pch_port) {
1838 /* if driving the PCH, we need FDI enabled */
1839 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1840 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1841 }
1842 /* FIXME: assert CPU port conditions for SNB+ */
1843 }
1844
1845 reg = PIPECONF(cpu_transcoder);
1846 val = I915_READ(reg);
1847 if (val & PIPECONF_ENABLE)
1848 return;
1849
1850 I915_WRITE(reg, val | PIPECONF_ENABLE);
1851 intel_wait_for_vblank(dev_priv->dev, pipe);
1852 }
1853
1854 /**
1855 * intel_disable_pipe - disable a pipe, asserting requirements
1856 * @dev_priv: i915 private structure
1857 * @pipe: pipe to disable
1858 *
1859 * Disable @pipe, making sure that various hardware specific requirements
1860 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1861 *
1862 * @pipe should be %PIPE_A or %PIPE_B.
1863 *
1864 * Will wait until the pipe has shut down before returning.
1865 */
1866 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1867 enum pipe pipe)
1868 {
1869 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1870 pipe);
1871 int reg;
1872 u32 val;
1873
1874 /*
1875 * Make sure planes won't keep trying to pump pixels to us,
1876 * or we might hang the display.
1877 */
1878 assert_planes_disabled(dev_priv, pipe);
1879
1880 /* Don't disable pipe A or pipe A PLLs if needed */
1881 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1882 return;
1883
1884 reg = PIPECONF(cpu_transcoder);
1885 val = I915_READ(reg);
1886 if ((val & PIPECONF_ENABLE) == 0)
1887 return;
1888
1889 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1890 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1891 }
1892
1893 /*
1894 * Plane regs are double buffered, going from enabled->disabled needs a
1895 * trigger in order to latch. The display address reg provides this.
1896 */
1897 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane)
1899 {
1900 if (dev_priv->info->gen >= 4)
1901 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1902 else
1903 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1904 }
1905
1906 /**
1907 * intel_enable_plane - enable a display plane on a given pipe
1908 * @dev_priv: i915 private structure
1909 * @plane: plane to enable
1910 * @pipe: pipe being fed
1911 *
1912 * Enable @plane on @pipe, making sure that @pipe is running first.
1913 */
1914 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1915 enum plane plane, enum pipe pipe)
1916 {
1917 int reg;
1918 u32 val;
1919
1920 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1921 assert_pipe_enabled(dev_priv, pipe);
1922
1923 reg = DSPCNTR(plane);
1924 val = I915_READ(reg);
1925 if (val & DISPLAY_PLANE_ENABLE)
1926 return;
1927
1928 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1929 intel_flush_display_plane(dev_priv, plane);
1930 intel_wait_for_vblank(dev_priv->dev, pipe);
1931 }
1932
1933 /**
1934 * intel_disable_plane - disable a display plane
1935 * @dev_priv: i915 private structure
1936 * @plane: plane to disable
1937 * @pipe: pipe consuming the data
1938 *
1939 * Disable @plane; should be an independent operation.
1940 */
1941 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1942 enum plane plane, enum pipe pipe)
1943 {
1944 int reg;
1945 u32 val;
1946
1947 reg = DSPCNTR(plane);
1948 val = I915_READ(reg);
1949 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1950 return;
1951
1952 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1953 intel_flush_display_plane(dev_priv, plane);
1954 intel_wait_for_vblank(dev_priv->dev, pipe);
1955 }
1956
1957 int
1958 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1959 struct drm_i915_gem_object *obj,
1960 struct intel_ring_buffer *pipelined)
1961 {
1962 struct drm_i915_private *dev_priv = dev->dev_private;
1963 u32 alignment;
1964 int ret;
1965
1966 switch (obj->tiling_mode) {
1967 case I915_TILING_NONE:
1968 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1969 alignment = 128 * 1024;
1970 else if (INTEL_INFO(dev)->gen >= 4)
1971 alignment = 4 * 1024;
1972 else
1973 alignment = 64 * 1024;
1974 break;
1975 case I915_TILING_X:
1976 /* pin() will align the object as required by fence */
1977 alignment = 0;
1978 break;
1979 case I915_TILING_Y:
1980 /* FIXME: Is this true? */
1981 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1982 return -EINVAL;
1983 default:
1984 BUG();
1985 }
1986
1987 dev_priv->mm.interruptible = false;
1988 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1989 if (ret)
1990 goto err_interruptible;
1991
1992 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1993 * fence, whereas 965+ only requires a fence if using
1994 * framebuffer compression. For simplicity, we always install
1995 * a fence as the cost is not that onerous.
1996 */
1997 ret = i915_gem_object_get_fence(obj);
1998 if (ret)
1999 goto err_unpin;
2000
2001 i915_gem_object_pin_fence(obj);
2002
2003 dev_priv->mm.interruptible = true;
2004 return 0;
2005
2006 err_unpin:
2007 i915_gem_object_unpin(obj);
2008 err_interruptible:
2009 dev_priv->mm.interruptible = true;
2010 return ret;
2011 }
2012
2013 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2014 {
2015 i915_gem_object_unpin_fence(obj);
2016 i915_gem_object_unpin(obj);
2017 }
2018
2019 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2020 * is assumed to be a power-of-two. */
2021 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2022 unsigned int bpp,
2023 unsigned int pitch)
2024 {
2025 int tile_rows, tiles;
2026
2027 tile_rows = *y / 8;
2028 *y %= 8;
2029 tiles = *x / (512/bpp);
2030 *x %= 512/bpp;
2031
2032 return tile_rows * pitch * 8 + tiles * 4096;
2033 }
2034
2035 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2036 int x, int y)
2037 {
2038 struct drm_device *dev = crtc->dev;
2039 struct drm_i915_private *dev_priv = dev->dev_private;
2040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2041 struct intel_framebuffer *intel_fb;
2042 struct drm_i915_gem_object *obj;
2043 int plane = intel_crtc->plane;
2044 unsigned long linear_offset;
2045 u32 dspcntr;
2046 u32 reg;
2047
2048 switch (plane) {
2049 case 0:
2050 case 1:
2051 break;
2052 default:
2053 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2054 return -EINVAL;
2055 }
2056
2057 intel_fb = to_intel_framebuffer(fb);
2058 obj = intel_fb->obj;
2059
2060 reg = DSPCNTR(plane);
2061 dspcntr = I915_READ(reg);
2062 /* Mask out pixel format bits in case we change it */
2063 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2064 switch (fb->pixel_format) {
2065 case DRM_FORMAT_C8:
2066 dspcntr |= DISPPLANE_8BPP;
2067 break;
2068 case DRM_FORMAT_XRGB1555:
2069 case DRM_FORMAT_ARGB1555:
2070 dspcntr |= DISPPLANE_BGRX555;
2071 break;
2072 case DRM_FORMAT_RGB565:
2073 dspcntr |= DISPPLANE_BGRX565;
2074 break;
2075 case DRM_FORMAT_XRGB8888:
2076 case DRM_FORMAT_ARGB8888:
2077 dspcntr |= DISPPLANE_BGRX888;
2078 break;
2079 case DRM_FORMAT_XBGR8888:
2080 case DRM_FORMAT_ABGR8888:
2081 dspcntr |= DISPPLANE_RGBX888;
2082 break;
2083 case DRM_FORMAT_XRGB2101010:
2084 case DRM_FORMAT_ARGB2101010:
2085 dspcntr |= DISPPLANE_BGRX101010;
2086 break;
2087 case DRM_FORMAT_XBGR2101010:
2088 case DRM_FORMAT_ABGR2101010:
2089 dspcntr |= DISPPLANE_RGBX101010;
2090 break;
2091 default:
2092 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2093 return -EINVAL;
2094 }
2095
2096 if (INTEL_INFO(dev)->gen >= 4) {
2097 if (obj->tiling_mode != I915_TILING_NONE)
2098 dspcntr |= DISPPLANE_TILED;
2099 else
2100 dspcntr &= ~DISPPLANE_TILED;
2101 }
2102
2103 I915_WRITE(reg, dspcntr);
2104
2105 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2106
2107 if (INTEL_INFO(dev)->gen >= 4) {
2108 intel_crtc->dspaddr_offset =
2109 intel_gen4_compute_offset_xtiled(&x, &y,
2110 fb->bits_per_pixel / 8,
2111 fb->pitches[0]);
2112 linear_offset -= intel_crtc->dspaddr_offset;
2113 } else {
2114 intel_crtc->dspaddr_offset = linear_offset;
2115 }
2116
2117 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2118 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2119 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2120 if (INTEL_INFO(dev)->gen >= 4) {
2121 I915_MODIFY_DISPBASE(DSPSURF(plane),
2122 obj->gtt_offset + intel_crtc->dspaddr_offset);
2123 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2124 I915_WRITE(DSPLINOFF(plane), linear_offset);
2125 } else
2126 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2127 POSTING_READ(reg);
2128
2129 return 0;
2130 }
2131
2132 static int ironlake_update_plane(struct drm_crtc *crtc,
2133 struct drm_framebuffer *fb, int x, int y)
2134 {
2135 struct drm_device *dev = crtc->dev;
2136 struct drm_i915_private *dev_priv = dev->dev_private;
2137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2138 struct intel_framebuffer *intel_fb;
2139 struct drm_i915_gem_object *obj;
2140 int plane = intel_crtc->plane;
2141 unsigned long linear_offset;
2142 u32 dspcntr;
2143 u32 reg;
2144
2145 switch (plane) {
2146 case 0:
2147 case 1:
2148 case 2:
2149 break;
2150 default:
2151 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2152 return -EINVAL;
2153 }
2154
2155 intel_fb = to_intel_framebuffer(fb);
2156 obj = intel_fb->obj;
2157
2158 reg = DSPCNTR(plane);
2159 dspcntr = I915_READ(reg);
2160 /* Mask out pixel format bits in case we change it */
2161 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2162 switch (fb->pixel_format) {
2163 case DRM_FORMAT_C8:
2164 dspcntr |= DISPPLANE_8BPP;
2165 break;
2166 case DRM_FORMAT_RGB565:
2167 dspcntr |= DISPPLANE_BGRX565;
2168 break;
2169 case DRM_FORMAT_XRGB8888:
2170 case DRM_FORMAT_ARGB8888:
2171 dspcntr |= DISPPLANE_BGRX888;
2172 break;
2173 case DRM_FORMAT_XBGR8888:
2174 case DRM_FORMAT_ABGR8888:
2175 dspcntr |= DISPPLANE_RGBX888;
2176 break;
2177 case DRM_FORMAT_XRGB2101010:
2178 case DRM_FORMAT_ARGB2101010:
2179 dspcntr |= DISPPLANE_BGRX101010;
2180 break;
2181 case DRM_FORMAT_XBGR2101010:
2182 case DRM_FORMAT_ABGR2101010:
2183 dspcntr |= DISPPLANE_RGBX101010;
2184 break;
2185 default:
2186 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2187 return -EINVAL;
2188 }
2189
2190 if (obj->tiling_mode != I915_TILING_NONE)
2191 dspcntr |= DISPPLANE_TILED;
2192 else
2193 dspcntr &= ~DISPPLANE_TILED;
2194
2195 /* must disable */
2196 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2197
2198 I915_WRITE(reg, dspcntr);
2199
2200 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2201 intel_crtc->dspaddr_offset =
2202 intel_gen4_compute_offset_xtiled(&x, &y,
2203 fb->bits_per_pixel / 8,
2204 fb->pitches[0]);
2205 linear_offset -= intel_crtc->dspaddr_offset;
2206
2207 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2208 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2209 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2210 I915_MODIFY_DISPBASE(DSPSURF(plane),
2211 obj->gtt_offset + intel_crtc->dspaddr_offset);
2212 if (IS_HASWELL(dev)) {
2213 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2214 } else {
2215 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2216 I915_WRITE(DSPLINOFF(plane), linear_offset);
2217 }
2218 POSTING_READ(reg);
2219
2220 return 0;
2221 }
2222
2223 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2224 static int
2225 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2226 int x, int y, enum mode_set_atomic state)
2227 {
2228 struct drm_device *dev = crtc->dev;
2229 struct drm_i915_private *dev_priv = dev->dev_private;
2230
2231 if (dev_priv->display.disable_fbc)
2232 dev_priv->display.disable_fbc(dev);
2233 intel_increase_pllclock(crtc);
2234
2235 return dev_priv->display.update_plane(crtc, fb, x, y);
2236 }
2237
2238 static int
2239 intel_finish_fb(struct drm_framebuffer *old_fb)
2240 {
2241 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2242 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2243 bool was_interruptible = dev_priv->mm.interruptible;
2244 int ret;
2245
2246 wait_event(dev_priv->pending_flip_queue,
2247 atomic_read(&dev_priv->mm.wedged) ||
2248 atomic_read(&obj->pending_flip) == 0);
2249
2250 /* Big Hammer, we also need to ensure that any pending
2251 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2252 * current scanout is retired before unpinning the old
2253 * framebuffer.
2254 *
2255 * This should only fail upon a hung GPU, in which case we
2256 * can safely continue.
2257 */
2258 dev_priv->mm.interruptible = false;
2259 ret = i915_gem_object_finish_gpu(obj);
2260 dev_priv->mm.interruptible = was_interruptible;
2261
2262 return ret;
2263 }
2264
2265 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2266 {
2267 struct drm_device *dev = crtc->dev;
2268 struct drm_i915_master_private *master_priv;
2269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2270
2271 if (!dev->primary->master)
2272 return;
2273
2274 master_priv = dev->primary->master->driver_priv;
2275 if (!master_priv->sarea_priv)
2276 return;
2277
2278 switch (intel_crtc->pipe) {
2279 case 0:
2280 master_priv->sarea_priv->pipeA_x = x;
2281 master_priv->sarea_priv->pipeA_y = y;
2282 break;
2283 case 1:
2284 master_priv->sarea_priv->pipeB_x = x;
2285 master_priv->sarea_priv->pipeB_y = y;
2286 break;
2287 default:
2288 break;
2289 }
2290 }
2291
2292 static int
2293 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2294 struct drm_framebuffer *fb)
2295 {
2296 struct drm_device *dev = crtc->dev;
2297 struct drm_i915_private *dev_priv = dev->dev_private;
2298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2299 struct drm_framebuffer *old_fb;
2300 int ret;
2301
2302 /* no fb bound */
2303 if (!fb) {
2304 DRM_ERROR("No FB bound\n");
2305 return 0;
2306 }
2307
2308 if(intel_crtc->plane > dev_priv->num_pipe) {
2309 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2310 intel_crtc->plane,
2311 dev_priv->num_pipe);
2312 return -EINVAL;
2313 }
2314
2315 mutex_lock(&dev->struct_mutex);
2316 ret = intel_pin_and_fence_fb_obj(dev,
2317 to_intel_framebuffer(fb)->obj,
2318 NULL);
2319 if (ret != 0) {
2320 mutex_unlock(&dev->struct_mutex);
2321 DRM_ERROR("pin & fence failed\n");
2322 return ret;
2323 }
2324
2325 if (crtc->fb)
2326 intel_finish_fb(crtc->fb);
2327
2328 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2329 if (ret) {
2330 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2331 mutex_unlock(&dev->struct_mutex);
2332 DRM_ERROR("failed to update base address\n");
2333 return ret;
2334 }
2335
2336 old_fb = crtc->fb;
2337 crtc->fb = fb;
2338 crtc->x = x;
2339 crtc->y = y;
2340
2341 if (old_fb) {
2342 intel_wait_for_vblank(dev, intel_crtc->pipe);
2343 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2344 }
2345
2346 intel_update_fbc(dev);
2347 mutex_unlock(&dev->struct_mutex);
2348
2349 intel_crtc_update_sarea_pos(crtc, x, y);
2350
2351 return 0;
2352 }
2353
2354 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2355 {
2356 struct drm_device *dev = crtc->dev;
2357 struct drm_i915_private *dev_priv = dev->dev_private;
2358 u32 dpa_ctl;
2359
2360 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2361 dpa_ctl = I915_READ(DP_A);
2362 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2363
2364 if (clock < 200000) {
2365 u32 temp;
2366 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2367 /* workaround for 160Mhz:
2368 1) program 0x4600c bits 15:0 = 0x8124
2369 2) program 0x46010 bit 0 = 1
2370 3) program 0x46034 bit 24 = 1
2371 4) program 0x64000 bit 14 = 1
2372 */
2373 temp = I915_READ(0x4600c);
2374 temp &= 0xffff0000;
2375 I915_WRITE(0x4600c, temp | 0x8124);
2376
2377 temp = I915_READ(0x46010);
2378 I915_WRITE(0x46010, temp | 1);
2379
2380 temp = I915_READ(0x46034);
2381 I915_WRITE(0x46034, temp | (1 << 24));
2382 } else {
2383 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2384 }
2385 I915_WRITE(DP_A, dpa_ctl);
2386
2387 POSTING_READ(DP_A);
2388 udelay(500);
2389 }
2390
2391 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2392 {
2393 struct drm_device *dev = crtc->dev;
2394 struct drm_i915_private *dev_priv = dev->dev_private;
2395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2396 int pipe = intel_crtc->pipe;
2397 u32 reg, temp;
2398
2399 /* enable normal train */
2400 reg = FDI_TX_CTL(pipe);
2401 temp = I915_READ(reg);
2402 if (IS_IVYBRIDGE(dev)) {
2403 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2404 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2405 } else {
2406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2408 }
2409 I915_WRITE(reg, temp);
2410
2411 reg = FDI_RX_CTL(pipe);
2412 temp = I915_READ(reg);
2413 if (HAS_PCH_CPT(dev)) {
2414 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2415 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2416 } else {
2417 temp &= ~FDI_LINK_TRAIN_NONE;
2418 temp |= FDI_LINK_TRAIN_NONE;
2419 }
2420 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2421
2422 /* wait one idle pattern time */
2423 POSTING_READ(reg);
2424 udelay(1000);
2425
2426 /* IVB wants error correction enabled */
2427 if (IS_IVYBRIDGE(dev))
2428 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2429 FDI_FE_ERRC_ENABLE);
2430 }
2431
2432 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2433 {
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 u32 flags = I915_READ(SOUTH_CHICKEN1);
2436
2437 flags |= FDI_PHASE_SYNC_OVR(pipe);
2438 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2439 flags |= FDI_PHASE_SYNC_EN(pipe);
2440 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2441 POSTING_READ(SOUTH_CHICKEN1);
2442 }
2443
2444 static void ivb_modeset_global_resources(struct drm_device *dev)
2445 {
2446 struct drm_i915_private *dev_priv = dev->dev_private;
2447 struct intel_crtc *pipe_B_crtc =
2448 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2449 struct intel_crtc *pipe_C_crtc =
2450 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2451 uint32_t temp;
2452
2453 /* When everything is off disable fdi C so that we could enable fdi B
2454 * with all lanes. XXX: This misses the case where a pipe is not using
2455 * any pch resources and so doesn't need any fdi lanes. */
2456 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2457 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2458 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2459
2460 temp = I915_READ(SOUTH_CHICKEN1);
2461 temp &= ~FDI_BC_BIFURCATION_SELECT;
2462 DRM_DEBUG_KMS("disabling fdi C rx\n");
2463 I915_WRITE(SOUTH_CHICKEN1, temp);
2464 }
2465 }
2466
2467 /* The FDI link training functions for ILK/Ibexpeak. */
2468 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2469 {
2470 struct drm_device *dev = crtc->dev;
2471 struct drm_i915_private *dev_priv = dev->dev_private;
2472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2473 int pipe = intel_crtc->pipe;
2474 int plane = intel_crtc->plane;
2475 u32 reg, temp, tries;
2476
2477 /* FDI needs bits from pipe & plane first */
2478 assert_pipe_enabled(dev_priv, pipe);
2479 assert_plane_enabled(dev_priv, plane);
2480
2481 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2482 for train result */
2483 reg = FDI_RX_IMR(pipe);
2484 temp = I915_READ(reg);
2485 temp &= ~FDI_RX_SYMBOL_LOCK;
2486 temp &= ~FDI_RX_BIT_LOCK;
2487 I915_WRITE(reg, temp);
2488 I915_READ(reg);
2489 udelay(150);
2490
2491 /* enable CPU FDI TX and PCH FDI RX */
2492 reg = FDI_TX_CTL(pipe);
2493 temp = I915_READ(reg);
2494 temp &= ~(7 << 19);
2495 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_1;
2498 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2499
2500 reg = FDI_RX_CTL(pipe);
2501 temp = I915_READ(reg);
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2505
2506 POSTING_READ(reg);
2507 udelay(150);
2508
2509 /* Ironlake workaround, enable clock pointer after FDI enable*/
2510 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2511 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2512 FDI_RX_PHASE_SYNC_POINTER_EN);
2513
2514 reg = FDI_RX_IIR(pipe);
2515 for (tries = 0; tries < 5; tries++) {
2516 temp = I915_READ(reg);
2517 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2518
2519 if ((temp & FDI_RX_BIT_LOCK)) {
2520 DRM_DEBUG_KMS("FDI train 1 done.\n");
2521 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2522 break;
2523 }
2524 }
2525 if (tries == 5)
2526 DRM_ERROR("FDI train 1 fail!\n");
2527
2528 /* Train 2 */
2529 reg = FDI_TX_CTL(pipe);
2530 temp = I915_READ(reg);
2531 temp &= ~FDI_LINK_TRAIN_NONE;
2532 temp |= FDI_LINK_TRAIN_PATTERN_2;
2533 I915_WRITE(reg, temp);
2534
2535 reg = FDI_RX_CTL(pipe);
2536 temp = I915_READ(reg);
2537 temp &= ~FDI_LINK_TRAIN_NONE;
2538 temp |= FDI_LINK_TRAIN_PATTERN_2;
2539 I915_WRITE(reg, temp);
2540
2541 POSTING_READ(reg);
2542 udelay(150);
2543
2544 reg = FDI_RX_IIR(pipe);
2545 for (tries = 0; tries < 5; tries++) {
2546 temp = I915_READ(reg);
2547 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2548
2549 if (temp & FDI_RX_SYMBOL_LOCK) {
2550 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2551 DRM_DEBUG_KMS("FDI train 2 done.\n");
2552 break;
2553 }
2554 }
2555 if (tries == 5)
2556 DRM_ERROR("FDI train 2 fail!\n");
2557
2558 DRM_DEBUG_KMS("FDI train done\n");
2559
2560 }
2561
2562 static const int snb_b_fdi_train_param[] = {
2563 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2564 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2565 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2566 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2567 };
2568
2569 /* The FDI link training functions for SNB/Cougarpoint. */
2570 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2571 {
2572 struct drm_device *dev = crtc->dev;
2573 struct drm_i915_private *dev_priv = dev->dev_private;
2574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2575 int pipe = intel_crtc->pipe;
2576 u32 reg, temp, i, retry;
2577
2578 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2579 for train result */
2580 reg = FDI_RX_IMR(pipe);
2581 temp = I915_READ(reg);
2582 temp &= ~FDI_RX_SYMBOL_LOCK;
2583 temp &= ~FDI_RX_BIT_LOCK;
2584 I915_WRITE(reg, temp);
2585
2586 POSTING_READ(reg);
2587 udelay(150);
2588
2589 /* enable CPU FDI TX and PCH FDI RX */
2590 reg = FDI_TX_CTL(pipe);
2591 temp = I915_READ(reg);
2592 temp &= ~(7 << 19);
2593 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2594 temp &= ~FDI_LINK_TRAIN_NONE;
2595 temp |= FDI_LINK_TRAIN_PATTERN_1;
2596 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2597 /* SNB-B */
2598 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2599 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2600
2601 I915_WRITE(FDI_RX_MISC(pipe),
2602 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2603
2604 reg = FDI_RX_CTL(pipe);
2605 temp = I915_READ(reg);
2606 if (HAS_PCH_CPT(dev)) {
2607 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2609 } else {
2610 temp &= ~FDI_LINK_TRAIN_NONE;
2611 temp |= FDI_LINK_TRAIN_PATTERN_1;
2612 }
2613 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2614
2615 POSTING_READ(reg);
2616 udelay(150);
2617
2618 cpt_phase_pointer_enable(dev, pipe);
2619
2620 for (i = 0; i < 4; i++) {
2621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= snb_b_fdi_train_param[i];
2625 I915_WRITE(reg, temp);
2626
2627 POSTING_READ(reg);
2628 udelay(500);
2629
2630 for (retry = 0; retry < 5; retry++) {
2631 reg = FDI_RX_IIR(pipe);
2632 temp = I915_READ(reg);
2633 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2634 if (temp & FDI_RX_BIT_LOCK) {
2635 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2636 DRM_DEBUG_KMS("FDI train 1 done.\n");
2637 break;
2638 }
2639 udelay(50);
2640 }
2641 if (retry < 5)
2642 break;
2643 }
2644 if (i == 4)
2645 DRM_ERROR("FDI train 1 fail!\n");
2646
2647 /* Train 2 */
2648 reg = FDI_TX_CTL(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_LINK_TRAIN_NONE;
2651 temp |= FDI_LINK_TRAIN_PATTERN_2;
2652 if (IS_GEN6(dev)) {
2653 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2654 /* SNB-B */
2655 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2656 }
2657 I915_WRITE(reg, temp);
2658
2659 reg = FDI_RX_CTL(pipe);
2660 temp = I915_READ(reg);
2661 if (HAS_PCH_CPT(dev)) {
2662 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2663 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2664 } else {
2665 temp &= ~FDI_LINK_TRAIN_NONE;
2666 temp |= FDI_LINK_TRAIN_PATTERN_2;
2667 }
2668 I915_WRITE(reg, temp);
2669
2670 POSTING_READ(reg);
2671 udelay(150);
2672
2673 for (i = 0; i < 4; i++) {
2674 reg = FDI_TX_CTL(pipe);
2675 temp = I915_READ(reg);
2676 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2677 temp |= snb_b_fdi_train_param[i];
2678 I915_WRITE(reg, temp);
2679
2680 POSTING_READ(reg);
2681 udelay(500);
2682
2683 for (retry = 0; retry < 5; retry++) {
2684 reg = FDI_RX_IIR(pipe);
2685 temp = I915_READ(reg);
2686 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2687 if (temp & FDI_RX_SYMBOL_LOCK) {
2688 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2689 DRM_DEBUG_KMS("FDI train 2 done.\n");
2690 break;
2691 }
2692 udelay(50);
2693 }
2694 if (retry < 5)
2695 break;
2696 }
2697 if (i == 4)
2698 DRM_ERROR("FDI train 2 fail!\n");
2699
2700 DRM_DEBUG_KMS("FDI train done.\n");
2701 }
2702
2703 /* Manual link training for Ivy Bridge A0 parts */
2704 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2705 {
2706 struct drm_device *dev = crtc->dev;
2707 struct drm_i915_private *dev_priv = dev->dev_private;
2708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2709 int pipe = intel_crtc->pipe;
2710 u32 reg, temp, i;
2711
2712 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2713 for train result */
2714 reg = FDI_RX_IMR(pipe);
2715 temp = I915_READ(reg);
2716 temp &= ~FDI_RX_SYMBOL_LOCK;
2717 temp &= ~FDI_RX_BIT_LOCK;
2718 I915_WRITE(reg, temp);
2719
2720 POSTING_READ(reg);
2721 udelay(150);
2722
2723 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2724 I915_READ(FDI_RX_IIR(pipe)));
2725
2726 /* enable CPU FDI TX and PCH FDI RX */
2727 reg = FDI_TX_CTL(pipe);
2728 temp = I915_READ(reg);
2729 temp &= ~(7 << 19);
2730 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2731 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2732 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2733 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2734 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2735 temp |= FDI_COMPOSITE_SYNC;
2736 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2737
2738 I915_WRITE(FDI_RX_MISC(pipe),
2739 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2740
2741 reg = FDI_RX_CTL(pipe);
2742 temp = I915_READ(reg);
2743 temp &= ~FDI_LINK_TRAIN_AUTO;
2744 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2745 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2746 temp |= FDI_COMPOSITE_SYNC;
2747 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2748
2749 POSTING_READ(reg);
2750 udelay(150);
2751
2752 cpt_phase_pointer_enable(dev, pipe);
2753
2754 for (i = 0; i < 4; i++) {
2755 reg = FDI_TX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2758 temp |= snb_b_fdi_train_param[i];
2759 I915_WRITE(reg, temp);
2760
2761 POSTING_READ(reg);
2762 udelay(500);
2763
2764 reg = FDI_RX_IIR(pipe);
2765 temp = I915_READ(reg);
2766 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2767
2768 if (temp & FDI_RX_BIT_LOCK ||
2769 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2770 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2771 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2772 break;
2773 }
2774 }
2775 if (i == 4)
2776 DRM_ERROR("FDI train 1 fail!\n");
2777
2778 /* Train 2 */
2779 reg = FDI_TX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2782 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2783 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2784 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2785 I915_WRITE(reg, temp);
2786
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2790 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2791 I915_WRITE(reg, temp);
2792
2793 POSTING_READ(reg);
2794 udelay(150);
2795
2796 for (i = 0; i < 4; i++) {
2797 reg = FDI_TX_CTL(pipe);
2798 temp = I915_READ(reg);
2799 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2800 temp |= snb_b_fdi_train_param[i];
2801 I915_WRITE(reg, temp);
2802
2803 POSTING_READ(reg);
2804 udelay(500);
2805
2806 reg = FDI_RX_IIR(pipe);
2807 temp = I915_READ(reg);
2808 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2809
2810 if (temp & FDI_RX_SYMBOL_LOCK) {
2811 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2812 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2813 break;
2814 }
2815 }
2816 if (i == 4)
2817 DRM_ERROR("FDI train 2 fail!\n");
2818
2819 DRM_DEBUG_KMS("FDI train done.\n");
2820 }
2821
2822 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2823 {
2824 struct drm_device *dev = intel_crtc->base.dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 int pipe = intel_crtc->pipe;
2827 u32 reg, temp;
2828
2829
2830 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2831 reg = FDI_RX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 temp &= ~((0x7 << 19) | (0x7 << 16));
2834 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2835 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2836 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2837
2838 POSTING_READ(reg);
2839 udelay(200);
2840
2841 /* Switch from Rawclk to PCDclk */
2842 temp = I915_READ(reg);
2843 I915_WRITE(reg, temp | FDI_PCDCLK);
2844
2845 POSTING_READ(reg);
2846 udelay(200);
2847
2848 /* On Haswell, the PLL configuration for ports and pipes is handled
2849 * separately, as part of DDI setup */
2850 if (!IS_HASWELL(dev)) {
2851 /* Enable CPU FDI TX PLL, always on for Ironlake */
2852 reg = FDI_TX_CTL(pipe);
2853 temp = I915_READ(reg);
2854 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2855 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2856
2857 POSTING_READ(reg);
2858 udelay(100);
2859 }
2860 }
2861 }
2862
2863 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2864 {
2865 struct drm_device *dev = intel_crtc->base.dev;
2866 struct drm_i915_private *dev_priv = dev->dev_private;
2867 int pipe = intel_crtc->pipe;
2868 u32 reg, temp;
2869
2870 /* Switch from PCDclk to Rawclk */
2871 reg = FDI_RX_CTL(pipe);
2872 temp = I915_READ(reg);
2873 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2874
2875 /* Disable CPU FDI TX PLL */
2876 reg = FDI_TX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2879
2880 POSTING_READ(reg);
2881 udelay(100);
2882
2883 reg = FDI_RX_CTL(pipe);
2884 temp = I915_READ(reg);
2885 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2886
2887 /* Wait for the clocks to turn off. */
2888 POSTING_READ(reg);
2889 udelay(100);
2890 }
2891
2892 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2893 {
2894 struct drm_i915_private *dev_priv = dev->dev_private;
2895 u32 flags = I915_READ(SOUTH_CHICKEN1);
2896
2897 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2898 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2899 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2900 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2901 POSTING_READ(SOUTH_CHICKEN1);
2902 }
2903 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2904 {
2905 struct drm_device *dev = crtc->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2908 int pipe = intel_crtc->pipe;
2909 u32 reg, temp;
2910
2911 /* disable CPU FDI tx and PCH FDI rx */
2912 reg = FDI_TX_CTL(pipe);
2913 temp = I915_READ(reg);
2914 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2915 POSTING_READ(reg);
2916
2917 reg = FDI_RX_CTL(pipe);
2918 temp = I915_READ(reg);
2919 temp &= ~(0x7 << 16);
2920 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2921 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2922
2923 POSTING_READ(reg);
2924 udelay(100);
2925
2926 /* Ironlake workaround, disable clock pointer after downing FDI */
2927 if (HAS_PCH_IBX(dev)) {
2928 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2929 I915_WRITE(FDI_RX_CHICKEN(pipe),
2930 I915_READ(FDI_RX_CHICKEN(pipe) &
2931 ~FDI_RX_PHASE_SYNC_POINTER_EN));
2932 } else if (HAS_PCH_CPT(dev)) {
2933 cpt_phase_pointer_disable(dev, pipe);
2934 }
2935
2936 /* still set train pattern 1 */
2937 reg = FDI_TX_CTL(pipe);
2938 temp = I915_READ(reg);
2939 temp &= ~FDI_LINK_TRAIN_NONE;
2940 temp |= FDI_LINK_TRAIN_PATTERN_1;
2941 I915_WRITE(reg, temp);
2942
2943 reg = FDI_RX_CTL(pipe);
2944 temp = I915_READ(reg);
2945 if (HAS_PCH_CPT(dev)) {
2946 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2947 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2948 } else {
2949 temp &= ~FDI_LINK_TRAIN_NONE;
2950 temp |= FDI_LINK_TRAIN_PATTERN_1;
2951 }
2952 /* BPC in FDI rx is consistent with that in PIPECONF */
2953 temp &= ~(0x07 << 16);
2954 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2955 I915_WRITE(reg, temp);
2956
2957 POSTING_READ(reg);
2958 udelay(100);
2959 }
2960
2961 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2962 {
2963 struct drm_device *dev = crtc->dev;
2964 struct drm_i915_private *dev_priv = dev->dev_private;
2965 unsigned long flags;
2966 bool pending;
2967
2968 if (atomic_read(&dev_priv->mm.wedged))
2969 return false;
2970
2971 spin_lock_irqsave(&dev->event_lock, flags);
2972 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2973 spin_unlock_irqrestore(&dev->event_lock, flags);
2974
2975 return pending;
2976 }
2977
2978 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2979 {
2980 struct drm_device *dev = crtc->dev;
2981 struct drm_i915_private *dev_priv = dev->dev_private;
2982
2983 if (crtc->fb == NULL)
2984 return;
2985
2986 wait_event(dev_priv->pending_flip_queue,
2987 !intel_crtc_has_pending_flip(crtc));
2988
2989 mutex_lock(&dev->struct_mutex);
2990 intel_finish_fb(crtc->fb);
2991 mutex_unlock(&dev->struct_mutex);
2992 }
2993
2994 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2995 {
2996 struct drm_device *dev = crtc->dev;
2997 struct intel_encoder *intel_encoder;
2998
2999 /*
3000 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
3001 * must be driven by its own crtc; no sharing is possible.
3002 */
3003 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
3004 switch (intel_encoder->type) {
3005 case INTEL_OUTPUT_EDP:
3006 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
3007 return false;
3008 continue;
3009 }
3010 }
3011
3012 return true;
3013 }
3014
3015 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3016 {
3017 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3018 }
3019
3020 /* Program iCLKIP clock to the desired frequency */
3021 static void lpt_program_iclkip(struct drm_crtc *crtc)
3022 {
3023 struct drm_device *dev = crtc->dev;
3024 struct drm_i915_private *dev_priv = dev->dev_private;
3025 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3026 u32 temp;
3027
3028 /* It is necessary to ungate the pixclk gate prior to programming
3029 * the divisors, and gate it back when it is done.
3030 */
3031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3032
3033 /* Disable SSCCTL */
3034 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3035 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3036 SBI_SSCCTL_DISABLE);
3037
3038 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3039 if (crtc->mode.clock == 20000) {
3040 auxdiv = 1;
3041 divsel = 0x41;
3042 phaseinc = 0x20;
3043 } else {
3044 /* The iCLK virtual clock root frequency is in MHz,
3045 * but the crtc->mode.clock in in KHz. To get the divisors,
3046 * it is necessary to divide one by another, so we
3047 * convert the virtual clock precision to KHz here for higher
3048 * precision.
3049 */
3050 u32 iclk_virtual_root_freq = 172800 * 1000;
3051 u32 iclk_pi_range = 64;
3052 u32 desired_divisor, msb_divisor_value, pi_value;
3053
3054 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3055 msb_divisor_value = desired_divisor / iclk_pi_range;
3056 pi_value = desired_divisor % iclk_pi_range;
3057
3058 auxdiv = 0;
3059 divsel = msb_divisor_value - 2;
3060 phaseinc = pi_value;
3061 }
3062
3063 /* This should not happen with any sane values */
3064 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3065 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3066 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3067 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3068
3069 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3070 crtc->mode.clock,
3071 auxdiv,
3072 divsel,
3073 phasedir,
3074 phaseinc);
3075
3076 /* Program SSCDIVINTPHASE6 */
3077 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3078 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3079 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3080 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3081 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3082 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3083 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3084
3085 intel_sbi_write(dev_priv,
3086 SBI_SSCDIVINTPHASE6,
3087 temp);
3088
3089 /* Program SSCAUXDIV */
3090 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3091 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3092 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3093 intel_sbi_write(dev_priv,
3094 SBI_SSCAUXDIV6,
3095 temp);
3096
3097
3098 /* Enable modulator and associated divider */
3099 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3100 temp &= ~SBI_SSCCTL_DISABLE;
3101 intel_sbi_write(dev_priv,
3102 SBI_SSCCTL6,
3103 temp);
3104
3105 /* Wait for initialization time */
3106 udelay(24);
3107
3108 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3109 }
3110
3111 /*
3112 * Enable PCH resources required for PCH ports:
3113 * - PCH PLLs
3114 * - FDI training & RX/TX
3115 * - update transcoder timings
3116 * - DP transcoding bits
3117 * - transcoder
3118 */
3119 static void ironlake_pch_enable(struct drm_crtc *crtc)
3120 {
3121 struct drm_device *dev = crtc->dev;
3122 struct drm_i915_private *dev_priv = dev->dev_private;
3123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3124 int pipe = intel_crtc->pipe;
3125 u32 reg, temp;
3126
3127 assert_transcoder_disabled(dev_priv, pipe);
3128
3129 /* Write the TU size bits before fdi link training, so that error
3130 * detection works. */
3131 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3132 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3133
3134 /* For PCH output, training FDI link */
3135 dev_priv->display.fdi_link_train(crtc);
3136
3137 /* XXX: pch pll's can be enabled any time before we enable the PCH
3138 * transcoder, and we actually should do this to not upset any PCH
3139 * transcoder that already use the clock when we share it.
3140 *
3141 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3142 * unconditionally resets the pll - we need that to have the right LVDS
3143 * enable sequence. */
3144 ironlake_enable_pch_pll(intel_crtc);
3145
3146 if (HAS_PCH_CPT(dev)) {
3147 u32 sel;
3148
3149 temp = I915_READ(PCH_DPLL_SEL);
3150 switch (pipe) {
3151 default:
3152 case 0:
3153 temp |= TRANSA_DPLL_ENABLE;
3154 sel = TRANSA_DPLLB_SEL;
3155 break;
3156 case 1:
3157 temp |= TRANSB_DPLL_ENABLE;
3158 sel = TRANSB_DPLLB_SEL;
3159 break;
3160 case 2:
3161 temp |= TRANSC_DPLL_ENABLE;
3162 sel = TRANSC_DPLLB_SEL;
3163 break;
3164 }
3165 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3166 temp |= sel;
3167 else
3168 temp &= ~sel;
3169 I915_WRITE(PCH_DPLL_SEL, temp);
3170 }
3171
3172 /* set transcoder timing, panel must allow it */
3173 assert_panel_unlocked(dev_priv, pipe);
3174 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3175 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3176 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3177
3178 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3179 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3180 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3181 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3182
3183 intel_fdi_normal_train(crtc);
3184
3185 /* For PCH DP, enable TRANS_DP_CTL */
3186 if (HAS_PCH_CPT(dev) &&
3187 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3188 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3189 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3190 reg = TRANS_DP_CTL(pipe);
3191 temp = I915_READ(reg);
3192 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3193 TRANS_DP_SYNC_MASK |
3194 TRANS_DP_BPC_MASK);
3195 temp |= (TRANS_DP_OUTPUT_ENABLE |
3196 TRANS_DP_ENH_FRAMING);
3197 temp |= bpc << 9; /* same format but at 11:9 */
3198
3199 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3200 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3201 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3202 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3203
3204 switch (intel_trans_dp_port_sel(crtc)) {
3205 case PCH_DP_B:
3206 temp |= TRANS_DP_PORT_SEL_B;
3207 break;
3208 case PCH_DP_C:
3209 temp |= TRANS_DP_PORT_SEL_C;
3210 break;
3211 case PCH_DP_D:
3212 temp |= TRANS_DP_PORT_SEL_D;
3213 break;
3214 default:
3215 BUG();
3216 }
3217
3218 I915_WRITE(reg, temp);
3219 }
3220
3221 ironlake_enable_pch_transcoder(dev_priv, pipe);
3222 }
3223
3224 static void lpt_pch_enable(struct drm_crtc *crtc)
3225 {
3226 struct drm_device *dev = crtc->dev;
3227 struct drm_i915_private *dev_priv = dev->dev_private;
3228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3229 int pipe = intel_crtc->pipe;
3230 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3231
3232 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3233
3234 /* Write the TU size bits before fdi link training, so that error
3235 * detection works. */
3236 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3237 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3238
3239 /* For PCH output, training FDI link */
3240 dev_priv->display.fdi_link_train(crtc);
3241
3242 lpt_program_iclkip(crtc);
3243
3244 /* Set transcoder timing. */
3245 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3246 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3247 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3248
3249 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3250 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3251 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3252 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3253
3254 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3255 }
3256
3257 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3258 {
3259 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3260
3261 if (pll == NULL)
3262 return;
3263
3264 if (pll->refcount == 0) {
3265 WARN(1, "bad PCH PLL refcount\n");
3266 return;
3267 }
3268
3269 --pll->refcount;
3270 intel_crtc->pch_pll = NULL;
3271 }
3272
3273 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3274 {
3275 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3276 struct intel_pch_pll *pll;
3277 int i;
3278
3279 pll = intel_crtc->pch_pll;
3280 if (pll) {
3281 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3282 intel_crtc->base.base.id, pll->pll_reg);
3283 goto prepare;
3284 }
3285
3286 if (HAS_PCH_IBX(dev_priv->dev)) {
3287 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3288 i = intel_crtc->pipe;
3289 pll = &dev_priv->pch_plls[i];
3290
3291 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3292 intel_crtc->base.base.id, pll->pll_reg);
3293
3294 goto found;
3295 }
3296
3297 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3298 pll = &dev_priv->pch_plls[i];
3299
3300 /* Only want to check enabled timings first */
3301 if (pll->refcount == 0)
3302 continue;
3303
3304 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3305 fp == I915_READ(pll->fp0_reg)) {
3306 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3307 intel_crtc->base.base.id,
3308 pll->pll_reg, pll->refcount, pll->active);
3309
3310 goto found;
3311 }
3312 }
3313
3314 /* Ok no matching timings, maybe there's a free one? */
3315 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3316 pll = &dev_priv->pch_plls[i];
3317 if (pll->refcount == 0) {
3318 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3319 intel_crtc->base.base.id, pll->pll_reg);
3320 goto found;
3321 }
3322 }
3323
3324 return NULL;
3325
3326 found:
3327 intel_crtc->pch_pll = pll;
3328 pll->refcount++;
3329 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3330 prepare: /* separate function? */
3331 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3332
3333 /* Wait for the clocks to stabilize before rewriting the regs */
3334 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3335 POSTING_READ(pll->pll_reg);
3336 udelay(150);
3337
3338 I915_WRITE(pll->fp0_reg, fp);
3339 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3340 pll->on = false;
3341 return pll;
3342 }
3343
3344 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3345 {
3346 struct drm_i915_private *dev_priv = dev->dev_private;
3347 int dslreg = PIPEDSL(pipe);
3348 u32 temp;
3349
3350 temp = I915_READ(dslreg);
3351 udelay(500);
3352 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3353 if (wait_for(I915_READ(dslreg) != temp, 5))
3354 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3355 }
3356 }
3357
3358 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3359 {
3360 struct drm_device *dev = crtc->dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3363 struct intel_encoder *encoder;
3364 int pipe = intel_crtc->pipe;
3365 int plane = intel_crtc->plane;
3366 u32 temp;
3367 bool is_pch_port;
3368
3369 WARN_ON(!crtc->enabled);
3370
3371 if (intel_crtc->active)
3372 return;
3373
3374 intel_crtc->active = true;
3375 intel_update_watermarks(dev);
3376
3377 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3378 temp = I915_READ(PCH_LVDS);
3379 if ((temp & LVDS_PORT_EN) == 0)
3380 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3381 }
3382
3383 is_pch_port = ironlake_crtc_driving_pch(crtc);
3384
3385 if (is_pch_port) {
3386 /* Note: FDI PLL enabling _must_ be done before we enable the
3387 * cpu pipes, hence this is separate from all the other fdi/pch
3388 * enabling. */
3389 ironlake_fdi_pll_enable(intel_crtc);
3390 } else {
3391 assert_fdi_tx_disabled(dev_priv, pipe);
3392 assert_fdi_rx_disabled(dev_priv, pipe);
3393 }
3394
3395 for_each_encoder_on_crtc(dev, crtc, encoder)
3396 if (encoder->pre_enable)
3397 encoder->pre_enable(encoder);
3398
3399 /* Enable panel fitting for LVDS */
3400 if (dev_priv->pch_pf_size &&
3401 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3402 /* Force use of hard-coded filter coefficients
3403 * as some pre-programmed values are broken,
3404 * e.g. x201.
3405 */
3406 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3407 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3408 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3409 }
3410
3411 /*
3412 * On ILK+ LUT must be loaded before the pipe is running but with
3413 * clocks enabled
3414 */
3415 intel_crtc_load_lut(crtc);
3416
3417 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3418 intel_enable_plane(dev_priv, plane, pipe);
3419
3420 if (is_pch_port)
3421 ironlake_pch_enable(crtc);
3422
3423 mutex_lock(&dev->struct_mutex);
3424 intel_update_fbc(dev);
3425 mutex_unlock(&dev->struct_mutex);
3426
3427 intel_crtc_update_cursor(crtc, true);
3428
3429 for_each_encoder_on_crtc(dev, crtc, encoder)
3430 encoder->enable(encoder);
3431
3432 if (HAS_PCH_CPT(dev))
3433 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3434
3435 /*
3436 * There seems to be a race in PCH platform hw (at least on some
3437 * outputs) where an enabled pipe still completes any pageflip right
3438 * away (as if the pipe is off) instead of waiting for vblank. As soon
3439 * as the first vblank happend, everything works as expected. Hence just
3440 * wait for one vblank before returning to avoid strange things
3441 * happening.
3442 */
3443 intel_wait_for_vblank(dev, intel_crtc->pipe);
3444 }
3445
3446 static void haswell_crtc_enable(struct drm_crtc *crtc)
3447 {
3448 struct drm_device *dev = crtc->dev;
3449 struct drm_i915_private *dev_priv = dev->dev_private;
3450 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3451 struct intel_encoder *encoder;
3452 int pipe = intel_crtc->pipe;
3453 int plane = intel_crtc->plane;
3454 bool is_pch_port;
3455
3456 WARN_ON(!crtc->enabled);
3457
3458 if (intel_crtc->active)
3459 return;
3460
3461 intel_crtc->active = true;
3462 intel_update_watermarks(dev);
3463
3464 is_pch_port = haswell_crtc_driving_pch(crtc);
3465
3466 if (is_pch_port)
3467 ironlake_fdi_pll_enable(intel_crtc);
3468
3469 for_each_encoder_on_crtc(dev, crtc, encoder)
3470 if (encoder->pre_enable)
3471 encoder->pre_enable(encoder);
3472
3473 intel_ddi_enable_pipe_clock(intel_crtc);
3474
3475 /* Enable panel fitting for eDP */
3476 if (dev_priv->pch_pf_size && HAS_eDP) {
3477 /* Force use of hard-coded filter coefficients
3478 * as some pre-programmed values are broken,
3479 * e.g. x201.
3480 */
3481 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3482 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3483 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3484 }
3485
3486 /*
3487 * On ILK+ LUT must be loaded before the pipe is running but with
3488 * clocks enabled
3489 */
3490 intel_crtc_load_lut(crtc);
3491
3492 intel_ddi_set_pipe_settings(crtc);
3493 intel_ddi_enable_pipe_func(crtc);
3494
3495 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3496 intel_enable_plane(dev_priv, plane, pipe);
3497
3498 if (is_pch_port)
3499 lpt_pch_enable(crtc);
3500
3501 mutex_lock(&dev->struct_mutex);
3502 intel_update_fbc(dev);
3503 mutex_unlock(&dev->struct_mutex);
3504
3505 intel_crtc_update_cursor(crtc, true);
3506
3507 for_each_encoder_on_crtc(dev, crtc, encoder)
3508 encoder->enable(encoder);
3509
3510 /*
3511 * There seems to be a race in PCH platform hw (at least on some
3512 * outputs) where an enabled pipe still completes any pageflip right
3513 * away (as if the pipe is off) instead of waiting for vblank. As soon
3514 * as the first vblank happend, everything works as expected. Hence just
3515 * wait for one vblank before returning to avoid strange things
3516 * happening.
3517 */
3518 intel_wait_for_vblank(dev, intel_crtc->pipe);
3519 }
3520
3521 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3522 {
3523 struct drm_device *dev = crtc->dev;
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526 struct intel_encoder *encoder;
3527 int pipe = intel_crtc->pipe;
3528 int plane = intel_crtc->plane;
3529 u32 reg, temp;
3530
3531
3532 if (!intel_crtc->active)
3533 return;
3534
3535 for_each_encoder_on_crtc(dev, crtc, encoder)
3536 encoder->disable(encoder);
3537
3538 intel_crtc_wait_for_pending_flips(crtc);
3539 drm_vblank_off(dev, pipe);
3540 intel_crtc_update_cursor(crtc, false);
3541
3542 intel_disable_plane(dev_priv, plane, pipe);
3543
3544 if (dev_priv->cfb_plane == plane)
3545 intel_disable_fbc(dev);
3546
3547 intel_disable_pipe(dev_priv, pipe);
3548
3549 /* Disable PF */
3550 I915_WRITE(PF_CTL(pipe), 0);
3551 I915_WRITE(PF_WIN_SZ(pipe), 0);
3552
3553 for_each_encoder_on_crtc(dev, crtc, encoder)
3554 if (encoder->post_disable)
3555 encoder->post_disable(encoder);
3556
3557 ironlake_fdi_disable(crtc);
3558
3559 ironlake_disable_pch_transcoder(dev_priv, pipe);
3560
3561 if (HAS_PCH_CPT(dev)) {
3562 /* disable TRANS_DP_CTL */
3563 reg = TRANS_DP_CTL(pipe);
3564 temp = I915_READ(reg);
3565 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3566 temp |= TRANS_DP_PORT_SEL_NONE;
3567 I915_WRITE(reg, temp);
3568
3569 /* disable DPLL_SEL */
3570 temp = I915_READ(PCH_DPLL_SEL);
3571 switch (pipe) {
3572 case 0:
3573 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3574 break;
3575 case 1:
3576 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3577 break;
3578 case 2:
3579 /* C shares PLL A or B */
3580 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3581 break;
3582 default:
3583 BUG(); /* wtf */
3584 }
3585 I915_WRITE(PCH_DPLL_SEL, temp);
3586 }
3587
3588 /* disable PCH DPLL */
3589 intel_disable_pch_pll(intel_crtc);
3590
3591 ironlake_fdi_pll_disable(intel_crtc);
3592
3593 intel_crtc->active = false;
3594 intel_update_watermarks(dev);
3595
3596 mutex_lock(&dev->struct_mutex);
3597 intel_update_fbc(dev);
3598 mutex_unlock(&dev->struct_mutex);
3599 }
3600
3601 static void haswell_crtc_disable(struct drm_crtc *crtc)
3602 {
3603 struct drm_device *dev = crtc->dev;
3604 struct drm_i915_private *dev_priv = dev->dev_private;
3605 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3606 struct intel_encoder *encoder;
3607 int pipe = intel_crtc->pipe;
3608 int plane = intel_crtc->plane;
3609 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3610 bool is_pch_port;
3611
3612 if (!intel_crtc->active)
3613 return;
3614
3615 is_pch_port = haswell_crtc_driving_pch(crtc);
3616
3617 for_each_encoder_on_crtc(dev, crtc, encoder)
3618 encoder->disable(encoder);
3619
3620 intel_crtc_wait_for_pending_flips(crtc);
3621 drm_vblank_off(dev, pipe);
3622 intel_crtc_update_cursor(crtc, false);
3623
3624 intel_disable_plane(dev_priv, plane, pipe);
3625
3626 if (dev_priv->cfb_plane == plane)
3627 intel_disable_fbc(dev);
3628
3629 intel_disable_pipe(dev_priv, pipe);
3630
3631 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3632
3633 /* Disable PF */
3634 I915_WRITE(PF_CTL(pipe), 0);
3635 I915_WRITE(PF_WIN_SZ(pipe), 0);
3636
3637 intel_ddi_disable_pipe_clock(intel_crtc);
3638
3639 for_each_encoder_on_crtc(dev, crtc, encoder)
3640 if (encoder->post_disable)
3641 encoder->post_disable(encoder);
3642
3643 if (is_pch_port) {
3644 ironlake_fdi_disable(crtc);
3645 lpt_disable_pch_transcoder(dev_priv);
3646 ironlake_fdi_pll_disable(intel_crtc);
3647 }
3648
3649 intel_crtc->active = false;
3650 intel_update_watermarks(dev);
3651
3652 mutex_lock(&dev->struct_mutex);
3653 intel_update_fbc(dev);
3654 mutex_unlock(&dev->struct_mutex);
3655 }
3656
3657 static void ironlake_crtc_off(struct drm_crtc *crtc)
3658 {
3659 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660 intel_put_pch_pll(intel_crtc);
3661 }
3662
3663 static void haswell_crtc_off(struct drm_crtc *crtc)
3664 {
3665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3666
3667 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3668 * start using it. */
3669 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3670
3671 intel_ddi_put_crtc_pll(crtc);
3672 }
3673
3674 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3675 {
3676 if (!enable && intel_crtc->overlay) {
3677 struct drm_device *dev = intel_crtc->base.dev;
3678 struct drm_i915_private *dev_priv = dev->dev_private;
3679
3680 mutex_lock(&dev->struct_mutex);
3681 dev_priv->mm.interruptible = false;
3682 (void) intel_overlay_switch_off(intel_crtc->overlay);
3683 dev_priv->mm.interruptible = true;
3684 mutex_unlock(&dev->struct_mutex);
3685 }
3686
3687 /* Let userspace switch the overlay on again. In most cases userspace
3688 * has to recompute where to put it anyway.
3689 */
3690 }
3691
3692 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3693 {
3694 struct drm_device *dev = crtc->dev;
3695 struct drm_i915_private *dev_priv = dev->dev_private;
3696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3697 struct intel_encoder *encoder;
3698 int pipe = intel_crtc->pipe;
3699 int plane = intel_crtc->plane;
3700
3701 WARN_ON(!crtc->enabled);
3702
3703 if (intel_crtc->active)
3704 return;
3705
3706 intel_crtc->active = true;
3707 intel_update_watermarks(dev);
3708
3709 intel_enable_pll(dev_priv, pipe);
3710 intel_enable_pipe(dev_priv, pipe, false);
3711 intel_enable_plane(dev_priv, plane, pipe);
3712
3713 intel_crtc_load_lut(crtc);
3714 intel_update_fbc(dev);
3715
3716 /* Give the overlay scaler a chance to enable if it's on this pipe */
3717 intel_crtc_dpms_overlay(intel_crtc, true);
3718 intel_crtc_update_cursor(crtc, true);
3719
3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 encoder->enable(encoder);
3722 }
3723
3724 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3725 {
3726 struct drm_device *dev = crtc->dev;
3727 struct drm_i915_private *dev_priv = dev->dev_private;
3728 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3729 struct intel_encoder *encoder;
3730 int pipe = intel_crtc->pipe;
3731 int plane = intel_crtc->plane;
3732
3733
3734 if (!intel_crtc->active)
3735 return;
3736
3737 for_each_encoder_on_crtc(dev, crtc, encoder)
3738 encoder->disable(encoder);
3739
3740 /* Give the overlay scaler a chance to disable if it's on this pipe */
3741 intel_crtc_wait_for_pending_flips(crtc);
3742 drm_vblank_off(dev, pipe);
3743 intel_crtc_dpms_overlay(intel_crtc, false);
3744 intel_crtc_update_cursor(crtc, false);
3745
3746 if (dev_priv->cfb_plane == plane)
3747 intel_disable_fbc(dev);
3748
3749 intel_disable_plane(dev_priv, plane, pipe);
3750 intel_disable_pipe(dev_priv, pipe);
3751 intel_disable_pll(dev_priv, pipe);
3752
3753 intel_crtc->active = false;
3754 intel_update_fbc(dev);
3755 intel_update_watermarks(dev);
3756 }
3757
3758 static void i9xx_crtc_off(struct drm_crtc *crtc)
3759 {
3760 }
3761
3762 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3763 bool enabled)
3764 {
3765 struct drm_device *dev = crtc->dev;
3766 struct drm_i915_master_private *master_priv;
3767 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3768 int pipe = intel_crtc->pipe;
3769
3770 if (!dev->primary->master)
3771 return;
3772
3773 master_priv = dev->primary->master->driver_priv;
3774 if (!master_priv->sarea_priv)
3775 return;
3776
3777 switch (pipe) {
3778 case 0:
3779 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3780 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3781 break;
3782 case 1:
3783 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3784 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3785 break;
3786 default:
3787 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3788 break;
3789 }
3790 }
3791
3792 /**
3793 * Sets the power management mode of the pipe and plane.
3794 */
3795 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3796 {
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_encoder *intel_encoder;
3800 bool enable = false;
3801
3802 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3803 enable |= intel_encoder->connectors_active;
3804
3805 if (enable)
3806 dev_priv->display.crtc_enable(crtc);
3807 else
3808 dev_priv->display.crtc_disable(crtc);
3809
3810 intel_crtc_update_sarea(crtc, enable);
3811 }
3812
3813 static void intel_crtc_noop(struct drm_crtc *crtc)
3814 {
3815 }
3816
3817 static void intel_crtc_disable(struct drm_crtc *crtc)
3818 {
3819 struct drm_device *dev = crtc->dev;
3820 struct drm_connector *connector;
3821 struct drm_i915_private *dev_priv = dev->dev_private;
3822
3823 /* crtc should still be enabled when we disable it. */
3824 WARN_ON(!crtc->enabled);
3825
3826 dev_priv->display.crtc_disable(crtc);
3827 intel_crtc_update_sarea(crtc, false);
3828 dev_priv->display.off(crtc);
3829
3830 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3831 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3832
3833 if (crtc->fb) {
3834 mutex_lock(&dev->struct_mutex);
3835 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3836 mutex_unlock(&dev->struct_mutex);
3837 crtc->fb = NULL;
3838 }
3839
3840 /* Update computed state. */
3841 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3842 if (!connector->encoder || !connector->encoder->crtc)
3843 continue;
3844
3845 if (connector->encoder->crtc != crtc)
3846 continue;
3847
3848 connector->dpms = DRM_MODE_DPMS_OFF;
3849 to_intel_encoder(connector->encoder)->connectors_active = false;
3850 }
3851 }
3852
3853 void intel_modeset_disable(struct drm_device *dev)
3854 {
3855 struct drm_crtc *crtc;
3856
3857 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3858 if (crtc->enabled)
3859 intel_crtc_disable(crtc);
3860 }
3861 }
3862
3863 void intel_encoder_noop(struct drm_encoder *encoder)
3864 {
3865 }
3866
3867 void intel_encoder_destroy(struct drm_encoder *encoder)
3868 {
3869 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3870
3871 drm_encoder_cleanup(encoder);
3872 kfree(intel_encoder);
3873 }
3874
3875 /* Simple dpms helper for encodres with just one connector, no cloning and only
3876 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3877 * state of the entire output pipe. */
3878 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3879 {
3880 if (mode == DRM_MODE_DPMS_ON) {
3881 encoder->connectors_active = true;
3882
3883 intel_crtc_update_dpms(encoder->base.crtc);
3884 } else {
3885 encoder->connectors_active = false;
3886
3887 intel_crtc_update_dpms(encoder->base.crtc);
3888 }
3889 }
3890
3891 /* Cross check the actual hw state with our own modeset state tracking (and it's
3892 * internal consistency). */
3893 static void intel_connector_check_state(struct intel_connector *connector)
3894 {
3895 if (connector->get_hw_state(connector)) {
3896 struct intel_encoder *encoder = connector->encoder;
3897 struct drm_crtc *crtc;
3898 bool encoder_enabled;
3899 enum pipe pipe;
3900
3901 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3902 connector->base.base.id,
3903 drm_get_connector_name(&connector->base));
3904
3905 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3906 "wrong connector dpms state\n");
3907 WARN(connector->base.encoder != &encoder->base,
3908 "active connector not linked to encoder\n");
3909 WARN(!encoder->connectors_active,
3910 "encoder->connectors_active not set\n");
3911
3912 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3913 WARN(!encoder_enabled, "encoder not enabled\n");
3914 if (WARN_ON(!encoder->base.crtc))
3915 return;
3916
3917 crtc = encoder->base.crtc;
3918
3919 WARN(!crtc->enabled, "crtc not enabled\n");
3920 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3921 WARN(pipe != to_intel_crtc(crtc)->pipe,
3922 "encoder active on the wrong pipe\n");
3923 }
3924 }
3925
3926 /* Even simpler default implementation, if there's really no special case to
3927 * consider. */
3928 void intel_connector_dpms(struct drm_connector *connector, int mode)
3929 {
3930 struct intel_encoder *encoder = intel_attached_encoder(connector);
3931
3932 /* All the simple cases only support two dpms states. */
3933 if (mode != DRM_MODE_DPMS_ON)
3934 mode = DRM_MODE_DPMS_OFF;
3935
3936 if (mode == connector->dpms)
3937 return;
3938
3939 connector->dpms = mode;
3940
3941 /* Only need to change hw state when actually enabled */
3942 if (encoder->base.crtc)
3943 intel_encoder_dpms(encoder, mode);
3944 else
3945 WARN_ON(encoder->connectors_active != false);
3946
3947 intel_modeset_check_state(connector->dev);
3948 }
3949
3950 /* Simple connector->get_hw_state implementation for encoders that support only
3951 * one connector and no cloning and hence the encoder state determines the state
3952 * of the connector. */
3953 bool intel_connector_get_hw_state(struct intel_connector *connector)
3954 {
3955 enum pipe pipe = 0;
3956 struct intel_encoder *encoder = connector->encoder;
3957
3958 return encoder->get_hw_state(encoder, &pipe);
3959 }
3960
3961 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3962 const struct drm_display_mode *mode,
3963 struct drm_display_mode *adjusted_mode)
3964 {
3965 struct drm_device *dev = crtc->dev;
3966
3967 if (HAS_PCH_SPLIT(dev)) {
3968 /* FDI link clock is fixed at 2.7G */
3969 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3970 return false;
3971 }
3972
3973 /* All interlaced capable intel hw wants timings in frames. Note though
3974 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3975 * timings, so we need to be careful not to clobber these.*/
3976 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3977 drm_mode_set_crtcinfo(adjusted_mode, 0);
3978
3979 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3980 * with a hsync front porch of 0.
3981 */
3982 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3983 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3984 return false;
3985
3986 return true;
3987 }
3988
3989 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3990 {
3991 return 400000; /* FIXME */
3992 }
3993
3994 static int i945_get_display_clock_speed(struct drm_device *dev)
3995 {
3996 return 400000;
3997 }
3998
3999 static int i915_get_display_clock_speed(struct drm_device *dev)
4000 {
4001 return 333000;
4002 }
4003
4004 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4005 {
4006 return 200000;
4007 }
4008
4009 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4010 {
4011 u16 gcfgc = 0;
4012
4013 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4014
4015 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4016 return 133000;
4017 else {
4018 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4019 case GC_DISPLAY_CLOCK_333_MHZ:
4020 return 333000;
4021 default:
4022 case GC_DISPLAY_CLOCK_190_200_MHZ:
4023 return 190000;
4024 }
4025 }
4026 }
4027
4028 static int i865_get_display_clock_speed(struct drm_device *dev)
4029 {
4030 return 266000;
4031 }
4032
4033 static int i855_get_display_clock_speed(struct drm_device *dev)
4034 {
4035 u16 hpllcc = 0;
4036 /* Assume that the hardware is in the high speed state. This
4037 * should be the default.
4038 */
4039 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4040 case GC_CLOCK_133_200:
4041 case GC_CLOCK_100_200:
4042 return 200000;
4043 case GC_CLOCK_166_250:
4044 return 250000;
4045 case GC_CLOCK_100_133:
4046 return 133000;
4047 }
4048
4049 /* Shouldn't happen */
4050 return 0;
4051 }
4052
4053 static int i830_get_display_clock_speed(struct drm_device *dev)
4054 {
4055 return 133000;
4056 }
4057
4058 struct fdi_m_n {
4059 u32 tu;
4060 u32 gmch_m;
4061 u32 gmch_n;
4062 u32 link_m;
4063 u32 link_n;
4064 };
4065
4066 static void
4067 fdi_reduce_ratio(u32 *num, u32 *den)
4068 {
4069 while (*num > 0xffffff || *den > 0xffffff) {
4070 *num >>= 1;
4071 *den >>= 1;
4072 }
4073 }
4074
4075 static void
4076 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4077 int link_clock, struct fdi_m_n *m_n)
4078 {
4079 m_n->tu = 64; /* default size */
4080
4081 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4082 m_n->gmch_m = bits_per_pixel * pixel_clock;
4083 m_n->gmch_n = link_clock * nlanes * 8;
4084 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4085
4086 m_n->link_m = pixel_clock;
4087 m_n->link_n = link_clock;
4088 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4089 }
4090
4091 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4092 {
4093 if (i915_panel_use_ssc >= 0)
4094 return i915_panel_use_ssc != 0;
4095 return dev_priv->lvds_use_ssc
4096 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4097 }
4098
4099 /**
4100 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4101 * @crtc: CRTC structure
4102 * @mode: requested mode
4103 *
4104 * A pipe may be connected to one or more outputs. Based on the depth of the
4105 * attached framebuffer, choose a good color depth to use on the pipe.
4106 *
4107 * If possible, match the pipe depth to the fb depth. In some cases, this
4108 * isn't ideal, because the connected output supports a lesser or restricted
4109 * set of depths. Resolve that here:
4110 * LVDS typically supports only 6bpc, so clamp down in that case
4111 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4112 * Displays may support a restricted set as well, check EDID and clamp as
4113 * appropriate.
4114 * DP may want to dither down to 6bpc to fit larger modes
4115 *
4116 * RETURNS:
4117 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4118 * true if they don't match).
4119 */
4120 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4121 struct drm_framebuffer *fb,
4122 unsigned int *pipe_bpp,
4123 struct drm_display_mode *mode)
4124 {
4125 struct drm_device *dev = crtc->dev;
4126 struct drm_i915_private *dev_priv = dev->dev_private;
4127 struct drm_connector *connector;
4128 struct intel_encoder *intel_encoder;
4129 unsigned int display_bpc = UINT_MAX, bpc;
4130
4131 /* Walk the encoders & connectors on this crtc, get min bpc */
4132 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4133
4134 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4135 unsigned int lvds_bpc;
4136
4137 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4138 LVDS_A3_POWER_UP)
4139 lvds_bpc = 8;
4140 else
4141 lvds_bpc = 6;
4142
4143 if (lvds_bpc < display_bpc) {
4144 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4145 display_bpc = lvds_bpc;
4146 }
4147 continue;
4148 }
4149
4150 /* Not one of the known troublemakers, check the EDID */
4151 list_for_each_entry(connector, &dev->mode_config.connector_list,
4152 head) {
4153 if (connector->encoder != &intel_encoder->base)
4154 continue;
4155
4156 /* Don't use an invalid EDID bpc value */
4157 if (connector->display_info.bpc &&
4158 connector->display_info.bpc < display_bpc) {
4159 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4160 display_bpc = connector->display_info.bpc;
4161 }
4162 }
4163
4164 /*
4165 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4166 * through, clamp it down. (Note: >12bpc will be caught below.)
4167 */
4168 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4169 if (display_bpc > 8 && display_bpc < 12) {
4170 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4171 display_bpc = 12;
4172 } else {
4173 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4174 display_bpc = 8;
4175 }
4176 }
4177 }
4178
4179 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4180 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4181 display_bpc = 6;
4182 }
4183
4184 /*
4185 * We could just drive the pipe at the highest bpc all the time and
4186 * enable dithering as needed, but that costs bandwidth. So choose
4187 * the minimum value that expresses the full color range of the fb but
4188 * also stays within the max display bpc discovered above.
4189 */
4190
4191 switch (fb->depth) {
4192 case 8:
4193 bpc = 8; /* since we go through a colormap */
4194 break;
4195 case 15:
4196 case 16:
4197 bpc = 6; /* min is 18bpp */
4198 break;
4199 case 24:
4200 bpc = 8;
4201 break;
4202 case 30:
4203 bpc = 10;
4204 break;
4205 case 48:
4206 bpc = 12;
4207 break;
4208 default:
4209 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4210 bpc = min((unsigned int)8, display_bpc);
4211 break;
4212 }
4213
4214 display_bpc = min(display_bpc, bpc);
4215
4216 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4217 bpc, display_bpc);
4218
4219 *pipe_bpp = display_bpc * 3;
4220
4221 return display_bpc != bpc;
4222 }
4223
4224 static int vlv_get_refclk(struct drm_crtc *crtc)
4225 {
4226 struct drm_device *dev = crtc->dev;
4227 struct drm_i915_private *dev_priv = dev->dev_private;
4228 int refclk = 27000; /* for DP & HDMI */
4229
4230 return 100000; /* only one validated so far */
4231
4232 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4233 refclk = 96000;
4234 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4235 if (intel_panel_use_ssc(dev_priv))
4236 refclk = 100000;
4237 else
4238 refclk = 96000;
4239 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4240 refclk = 100000;
4241 }
4242
4243 return refclk;
4244 }
4245
4246 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4247 {
4248 struct drm_device *dev = crtc->dev;
4249 struct drm_i915_private *dev_priv = dev->dev_private;
4250 int refclk;
4251
4252 if (IS_VALLEYVIEW(dev)) {
4253 refclk = vlv_get_refclk(crtc);
4254 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4255 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4256 refclk = dev_priv->lvds_ssc_freq * 1000;
4257 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4258 refclk / 1000);
4259 } else if (!IS_GEN2(dev)) {
4260 refclk = 96000;
4261 } else {
4262 refclk = 48000;
4263 }
4264
4265 return refclk;
4266 }
4267
4268 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4269 intel_clock_t *clock)
4270 {
4271 /* SDVO TV has fixed PLL values depend on its clock range,
4272 this mirrors vbios setting. */
4273 if (adjusted_mode->clock >= 100000
4274 && adjusted_mode->clock < 140500) {
4275 clock->p1 = 2;
4276 clock->p2 = 10;
4277 clock->n = 3;
4278 clock->m1 = 16;
4279 clock->m2 = 8;
4280 } else if (adjusted_mode->clock >= 140500
4281 && adjusted_mode->clock <= 200000) {
4282 clock->p1 = 1;
4283 clock->p2 = 10;
4284 clock->n = 6;
4285 clock->m1 = 12;
4286 clock->m2 = 8;
4287 }
4288 }
4289
4290 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4291 intel_clock_t *clock,
4292 intel_clock_t *reduced_clock)
4293 {
4294 struct drm_device *dev = crtc->dev;
4295 struct drm_i915_private *dev_priv = dev->dev_private;
4296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4297 int pipe = intel_crtc->pipe;
4298 u32 fp, fp2 = 0;
4299
4300 if (IS_PINEVIEW(dev)) {
4301 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4302 if (reduced_clock)
4303 fp2 = (1 << reduced_clock->n) << 16 |
4304 reduced_clock->m1 << 8 | reduced_clock->m2;
4305 } else {
4306 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4307 if (reduced_clock)
4308 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4309 reduced_clock->m2;
4310 }
4311
4312 I915_WRITE(FP0(pipe), fp);
4313
4314 intel_crtc->lowfreq_avail = false;
4315 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4316 reduced_clock && i915_powersave) {
4317 I915_WRITE(FP1(pipe), fp2);
4318 intel_crtc->lowfreq_avail = true;
4319 } else {
4320 I915_WRITE(FP1(pipe), fp);
4321 }
4322 }
4323
4324 static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4325 struct drm_display_mode *adjusted_mode)
4326 {
4327 struct drm_device *dev = crtc->dev;
4328 struct drm_i915_private *dev_priv = dev->dev_private;
4329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4330 int pipe = intel_crtc->pipe;
4331 u32 temp;
4332
4333 temp = I915_READ(LVDS);
4334 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4335 if (pipe == 1) {
4336 temp |= LVDS_PIPEB_SELECT;
4337 } else {
4338 temp &= ~LVDS_PIPEB_SELECT;
4339 }
4340 /* set the corresponsding LVDS_BORDER bit */
4341 temp |= dev_priv->lvds_border_bits;
4342 /* Set the B0-B3 data pairs corresponding to whether we're going to
4343 * set the DPLLs for dual-channel mode or not.
4344 */
4345 if (clock->p2 == 7)
4346 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4347 else
4348 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4349
4350 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4351 * appropriately here, but we need to look more thoroughly into how
4352 * panels behave in the two modes.
4353 */
4354 /* set the dithering flag on LVDS as needed */
4355 if (INTEL_INFO(dev)->gen >= 4) {
4356 if (dev_priv->lvds_dither)
4357 temp |= LVDS_ENABLE_DITHER;
4358 else
4359 temp &= ~LVDS_ENABLE_DITHER;
4360 }
4361 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4362 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
4363 temp |= LVDS_HSYNC_POLARITY;
4364 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
4365 temp |= LVDS_VSYNC_POLARITY;
4366 I915_WRITE(LVDS, temp);
4367 }
4368
4369 static void vlv_update_pll(struct drm_crtc *crtc,
4370 struct drm_display_mode *mode,
4371 struct drm_display_mode *adjusted_mode,
4372 intel_clock_t *clock, intel_clock_t *reduced_clock,
4373 int num_connectors)
4374 {
4375 struct drm_device *dev = crtc->dev;
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4378 int pipe = intel_crtc->pipe;
4379 u32 dpll, mdiv, pdiv;
4380 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4381 bool is_sdvo;
4382 u32 temp;
4383
4384 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4385 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4386
4387 dpll = DPLL_VGA_MODE_DIS;
4388 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4389 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4390 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4391
4392 I915_WRITE(DPLL(pipe), dpll);
4393 POSTING_READ(DPLL(pipe));
4394
4395 bestn = clock->n;
4396 bestm1 = clock->m1;
4397 bestm2 = clock->m2;
4398 bestp1 = clock->p1;
4399 bestp2 = clock->p2;
4400
4401 /*
4402 * In Valleyview PLL and program lane counter registers are exposed
4403 * through DPIO interface
4404 */
4405 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4406 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4407 mdiv |= ((bestn << DPIO_N_SHIFT));
4408 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4409 mdiv |= (1 << DPIO_K_SHIFT);
4410 mdiv |= DPIO_ENABLE_CALIBRATION;
4411 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4412
4413 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4414
4415 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4416 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4417 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4418 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4419 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4420
4421 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4422
4423 dpll |= DPLL_VCO_ENABLE;
4424 I915_WRITE(DPLL(pipe), dpll);
4425 POSTING_READ(DPLL(pipe));
4426 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4427 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4428
4429 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4430
4431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4432 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4433
4434 I915_WRITE(DPLL(pipe), dpll);
4435
4436 /* Wait for the clocks to stabilize. */
4437 POSTING_READ(DPLL(pipe));
4438 udelay(150);
4439
4440 temp = 0;
4441 if (is_sdvo) {
4442 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4443 if (temp > 1)
4444 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4445 else
4446 temp = 0;
4447 }
4448 I915_WRITE(DPLL_MD(pipe), temp);
4449 POSTING_READ(DPLL_MD(pipe));
4450
4451 /* Now program lane control registers */
4452 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4453 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4454 {
4455 temp = 0x1000C4;
4456 if(pipe == 1)
4457 temp |= (1 << 21);
4458 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4459 }
4460 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4461 {
4462 temp = 0x1000C4;
4463 if(pipe == 1)
4464 temp |= (1 << 21);
4465 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4466 }
4467 }
4468
4469 static void i9xx_update_pll(struct drm_crtc *crtc,
4470 struct drm_display_mode *mode,
4471 struct drm_display_mode *adjusted_mode,
4472 intel_clock_t *clock, intel_clock_t *reduced_clock,
4473 int num_connectors)
4474 {
4475 struct drm_device *dev = crtc->dev;
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4478 int pipe = intel_crtc->pipe;
4479 u32 dpll;
4480 bool is_sdvo;
4481
4482 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4483
4484 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4485 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4486
4487 dpll = DPLL_VGA_MODE_DIS;
4488
4489 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4490 dpll |= DPLLB_MODE_LVDS;
4491 else
4492 dpll |= DPLLB_MODE_DAC_SERIAL;
4493 if (is_sdvo) {
4494 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4495 if (pixel_multiplier > 1) {
4496 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4497 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4498 }
4499 dpll |= DPLL_DVO_HIGH_SPEED;
4500 }
4501 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4502 dpll |= DPLL_DVO_HIGH_SPEED;
4503
4504 /* compute bitmask from p1 value */
4505 if (IS_PINEVIEW(dev))
4506 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4507 else {
4508 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4509 if (IS_G4X(dev) && reduced_clock)
4510 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4511 }
4512 switch (clock->p2) {
4513 case 5:
4514 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4515 break;
4516 case 7:
4517 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4518 break;
4519 case 10:
4520 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4521 break;
4522 case 14:
4523 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4524 break;
4525 }
4526 if (INTEL_INFO(dev)->gen >= 4)
4527 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4528
4529 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4530 dpll |= PLL_REF_INPUT_TVCLKINBC;
4531 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4532 /* XXX: just matching BIOS for now */
4533 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4534 dpll |= 3;
4535 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4536 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4537 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4538 else
4539 dpll |= PLL_REF_INPUT_DREFCLK;
4540
4541 dpll |= DPLL_VCO_ENABLE;
4542 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4543 POSTING_READ(DPLL(pipe));
4544 udelay(150);
4545
4546 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4547 * This is an exception to the general rule that mode_set doesn't turn
4548 * things on.
4549 */
4550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4551 intel_update_lvds(crtc, clock, adjusted_mode);
4552
4553 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4554 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4555
4556 I915_WRITE(DPLL(pipe), dpll);
4557
4558 /* Wait for the clocks to stabilize. */
4559 POSTING_READ(DPLL(pipe));
4560 udelay(150);
4561
4562 if (INTEL_INFO(dev)->gen >= 4) {
4563 u32 temp = 0;
4564 if (is_sdvo) {
4565 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4566 if (temp > 1)
4567 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4568 else
4569 temp = 0;
4570 }
4571 I915_WRITE(DPLL_MD(pipe), temp);
4572 } else {
4573 /* The pixel multiplier can only be updated once the
4574 * DPLL is enabled and the clocks are stable.
4575 *
4576 * So write it again.
4577 */
4578 I915_WRITE(DPLL(pipe), dpll);
4579 }
4580 }
4581
4582 static void i8xx_update_pll(struct drm_crtc *crtc,
4583 struct drm_display_mode *adjusted_mode,
4584 intel_clock_t *clock, intel_clock_t *reduced_clock,
4585 int num_connectors)
4586 {
4587 struct drm_device *dev = crtc->dev;
4588 struct drm_i915_private *dev_priv = dev->dev_private;
4589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4590 int pipe = intel_crtc->pipe;
4591 u32 dpll;
4592
4593 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4594
4595 dpll = DPLL_VGA_MODE_DIS;
4596
4597 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4598 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4599 } else {
4600 if (clock->p1 == 2)
4601 dpll |= PLL_P1_DIVIDE_BY_TWO;
4602 else
4603 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4604 if (clock->p2 == 4)
4605 dpll |= PLL_P2_DIVIDE_BY_4;
4606 }
4607
4608 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4609 /* XXX: just matching BIOS for now */
4610 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4611 dpll |= 3;
4612 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4613 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4614 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4615 else
4616 dpll |= PLL_REF_INPUT_DREFCLK;
4617
4618 dpll |= DPLL_VCO_ENABLE;
4619 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4620 POSTING_READ(DPLL(pipe));
4621 udelay(150);
4622
4623 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4624 * This is an exception to the general rule that mode_set doesn't turn
4625 * things on.
4626 */
4627 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4628 intel_update_lvds(crtc, clock, adjusted_mode);
4629
4630 I915_WRITE(DPLL(pipe), dpll);
4631
4632 /* Wait for the clocks to stabilize. */
4633 POSTING_READ(DPLL(pipe));
4634 udelay(150);
4635
4636 /* The pixel multiplier can only be updated once the
4637 * DPLL is enabled and the clocks are stable.
4638 *
4639 * So write it again.
4640 */
4641 I915_WRITE(DPLL(pipe), dpll);
4642 }
4643
4644 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4645 struct drm_display_mode *mode,
4646 struct drm_display_mode *adjusted_mode)
4647 {
4648 struct drm_device *dev = intel_crtc->base.dev;
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 enum pipe pipe = intel_crtc->pipe;
4651 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4652 uint32_t vsyncshift;
4653
4654 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4655 /* the chip adds 2 halflines automatically */
4656 adjusted_mode->crtc_vtotal -= 1;
4657 adjusted_mode->crtc_vblank_end -= 1;
4658 vsyncshift = adjusted_mode->crtc_hsync_start
4659 - adjusted_mode->crtc_htotal / 2;
4660 } else {
4661 vsyncshift = 0;
4662 }
4663
4664 if (INTEL_INFO(dev)->gen > 3)
4665 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4666
4667 I915_WRITE(HTOTAL(cpu_transcoder),
4668 (adjusted_mode->crtc_hdisplay - 1) |
4669 ((adjusted_mode->crtc_htotal - 1) << 16));
4670 I915_WRITE(HBLANK(cpu_transcoder),
4671 (adjusted_mode->crtc_hblank_start - 1) |
4672 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4673 I915_WRITE(HSYNC(cpu_transcoder),
4674 (adjusted_mode->crtc_hsync_start - 1) |
4675 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4676
4677 I915_WRITE(VTOTAL(cpu_transcoder),
4678 (adjusted_mode->crtc_vdisplay - 1) |
4679 ((adjusted_mode->crtc_vtotal - 1) << 16));
4680 I915_WRITE(VBLANK(cpu_transcoder),
4681 (adjusted_mode->crtc_vblank_start - 1) |
4682 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4683 I915_WRITE(VSYNC(cpu_transcoder),
4684 (adjusted_mode->crtc_vsync_start - 1) |
4685 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4686
4687 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4688 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4689 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4690 * bits. */
4691 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4692 (pipe == PIPE_B || pipe == PIPE_C))
4693 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4694
4695 /* pipesrc controls the size that is scaled from, which should
4696 * always be the user's requested size.
4697 */
4698 I915_WRITE(PIPESRC(pipe),
4699 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4700 }
4701
4702 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4703 struct drm_display_mode *mode,
4704 struct drm_display_mode *adjusted_mode,
4705 int x, int y,
4706 struct drm_framebuffer *fb)
4707 {
4708 struct drm_device *dev = crtc->dev;
4709 struct drm_i915_private *dev_priv = dev->dev_private;
4710 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4711 int pipe = intel_crtc->pipe;
4712 int plane = intel_crtc->plane;
4713 int refclk, num_connectors = 0;
4714 intel_clock_t clock, reduced_clock;
4715 u32 dspcntr, pipeconf;
4716 bool ok, has_reduced_clock = false, is_sdvo = false;
4717 bool is_lvds = false, is_tv = false, is_dp = false;
4718 struct intel_encoder *encoder;
4719 const intel_limit_t *limit;
4720 int ret;
4721
4722 for_each_encoder_on_crtc(dev, crtc, encoder) {
4723 switch (encoder->type) {
4724 case INTEL_OUTPUT_LVDS:
4725 is_lvds = true;
4726 break;
4727 case INTEL_OUTPUT_SDVO:
4728 case INTEL_OUTPUT_HDMI:
4729 is_sdvo = true;
4730 if (encoder->needs_tv_clock)
4731 is_tv = true;
4732 break;
4733 case INTEL_OUTPUT_TVOUT:
4734 is_tv = true;
4735 break;
4736 case INTEL_OUTPUT_DISPLAYPORT:
4737 is_dp = true;
4738 break;
4739 }
4740
4741 num_connectors++;
4742 }
4743
4744 refclk = i9xx_get_refclk(crtc, num_connectors);
4745
4746 /*
4747 * Returns a set of divisors for the desired target clock with the given
4748 * refclk, or FALSE. The returned values represent the clock equation:
4749 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4750 */
4751 limit = intel_limit(crtc, refclk);
4752 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4753 &clock);
4754 if (!ok) {
4755 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4756 return -EINVAL;
4757 }
4758
4759 /* Ensure that the cursor is valid for the new mode before changing... */
4760 intel_crtc_update_cursor(crtc, true);
4761
4762 if (is_lvds && dev_priv->lvds_downclock_avail) {
4763 /*
4764 * Ensure we match the reduced clock's P to the target clock.
4765 * If the clocks don't match, we can't switch the display clock
4766 * by using the FP0/FP1. In such case we will disable the LVDS
4767 * downclock feature.
4768 */
4769 has_reduced_clock = limit->find_pll(limit, crtc,
4770 dev_priv->lvds_downclock,
4771 refclk,
4772 &clock,
4773 &reduced_clock);
4774 }
4775
4776 if (is_sdvo && is_tv)
4777 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4778
4779 if (IS_GEN2(dev))
4780 i8xx_update_pll(crtc, adjusted_mode, &clock,
4781 has_reduced_clock ? &reduced_clock : NULL,
4782 num_connectors);
4783 else if (IS_VALLEYVIEW(dev))
4784 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4785 has_reduced_clock ? &reduced_clock : NULL,
4786 num_connectors);
4787 else
4788 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4789 has_reduced_clock ? &reduced_clock : NULL,
4790 num_connectors);
4791
4792 /* setup pipeconf */
4793 pipeconf = I915_READ(PIPECONF(pipe));
4794
4795 /* Set up the display plane register */
4796 dspcntr = DISPPLANE_GAMMA_ENABLE;
4797
4798 if (pipe == 0)
4799 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4800 else
4801 dspcntr |= DISPPLANE_SEL_PIPE_B;
4802
4803 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4804 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4805 * core speed.
4806 *
4807 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4808 * pipe == 0 check?
4809 */
4810 if (mode->clock >
4811 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4812 pipeconf |= PIPECONF_DOUBLE_WIDE;
4813 else
4814 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4815 }
4816
4817 /* default to 8bpc */
4818 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4819 if (is_dp) {
4820 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4821 pipeconf |= PIPECONF_BPP_6 |
4822 PIPECONF_DITHER_EN |
4823 PIPECONF_DITHER_TYPE_SP;
4824 }
4825 }
4826
4827 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4828 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4829 pipeconf |= PIPECONF_BPP_6 |
4830 PIPECONF_ENABLE |
4831 I965_PIPECONF_ACTIVE;
4832 }
4833 }
4834
4835 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4836 drm_mode_debug_printmodeline(mode);
4837
4838 if (HAS_PIPE_CXSR(dev)) {
4839 if (intel_crtc->lowfreq_avail) {
4840 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4841 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4842 } else {
4843 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4844 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4845 }
4846 }
4847
4848 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4849 if (!IS_GEN2(dev) &&
4850 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4851 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4852 else
4853 pipeconf |= PIPECONF_PROGRESSIVE;
4854
4855 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4856
4857 /* pipesrc and dspsize control the size that is scaled from,
4858 * which should always be the user's requested size.
4859 */
4860 I915_WRITE(DSPSIZE(plane),
4861 ((mode->vdisplay - 1) << 16) |
4862 (mode->hdisplay - 1));
4863 I915_WRITE(DSPPOS(plane), 0);
4864
4865 I915_WRITE(PIPECONF(pipe), pipeconf);
4866 POSTING_READ(PIPECONF(pipe));
4867 intel_enable_pipe(dev_priv, pipe, false);
4868
4869 intel_wait_for_vblank(dev, pipe);
4870
4871 I915_WRITE(DSPCNTR(plane), dspcntr);
4872 POSTING_READ(DSPCNTR(plane));
4873
4874 ret = intel_pipe_set_base(crtc, x, y, fb);
4875
4876 intel_update_watermarks(dev);
4877
4878 return ret;
4879 }
4880
4881 /*
4882 * Initialize reference clocks when the driver loads
4883 */
4884 void ironlake_init_pch_refclk(struct drm_device *dev)
4885 {
4886 struct drm_i915_private *dev_priv = dev->dev_private;
4887 struct drm_mode_config *mode_config = &dev->mode_config;
4888 struct intel_encoder *encoder;
4889 u32 temp;
4890 bool has_lvds = false;
4891 bool has_cpu_edp = false;
4892 bool has_pch_edp = false;
4893 bool has_panel = false;
4894 bool has_ck505 = false;
4895 bool can_ssc = false;
4896
4897 /* We need to take the global config into account */
4898 list_for_each_entry(encoder, &mode_config->encoder_list,
4899 base.head) {
4900 switch (encoder->type) {
4901 case INTEL_OUTPUT_LVDS:
4902 has_panel = true;
4903 has_lvds = true;
4904 break;
4905 case INTEL_OUTPUT_EDP:
4906 has_panel = true;
4907 if (intel_encoder_is_pch_edp(&encoder->base))
4908 has_pch_edp = true;
4909 else
4910 has_cpu_edp = true;
4911 break;
4912 }
4913 }
4914
4915 if (HAS_PCH_IBX(dev)) {
4916 has_ck505 = dev_priv->display_clock_mode;
4917 can_ssc = has_ck505;
4918 } else {
4919 has_ck505 = false;
4920 can_ssc = true;
4921 }
4922
4923 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4924 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4925 has_ck505);
4926
4927 /* Ironlake: try to setup display ref clock before DPLL
4928 * enabling. This is only under driver's control after
4929 * PCH B stepping, previous chipset stepping should be
4930 * ignoring this setting.
4931 */
4932 temp = I915_READ(PCH_DREF_CONTROL);
4933 /* Always enable nonspread source */
4934 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4935
4936 if (has_ck505)
4937 temp |= DREF_NONSPREAD_CK505_ENABLE;
4938 else
4939 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4940
4941 if (has_panel) {
4942 temp &= ~DREF_SSC_SOURCE_MASK;
4943 temp |= DREF_SSC_SOURCE_ENABLE;
4944
4945 /* SSC must be turned on before enabling the CPU output */
4946 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4947 DRM_DEBUG_KMS("Using SSC on panel\n");
4948 temp |= DREF_SSC1_ENABLE;
4949 } else
4950 temp &= ~DREF_SSC1_ENABLE;
4951
4952 /* Get SSC going before enabling the outputs */
4953 I915_WRITE(PCH_DREF_CONTROL, temp);
4954 POSTING_READ(PCH_DREF_CONTROL);
4955 udelay(200);
4956
4957 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4958
4959 /* Enable CPU source on CPU attached eDP */
4960 if (has_cpu_edp) {
4961 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4962 DRM_DEBUG_KMS("Using SSC on eDP\n");
4963 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4964 }
4965 else
4966 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4967 } else
4968 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4969
4970 I915_WRITE(PCH_DREF_CONTROL, temp);
4971 POSTING_READ(PCH_DREF_CONTROL);
4972 udelay(200);
4973 } else {
4974 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4975
4976 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4977
4978 /* Turn off CPU output */
4979 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4980
4981 I915_WRITE(PCH_DREF_CONTROL, temp);
4982 POSTING_READ(PCH_DREF_CONTROL);
4983 udelay(200);
4984
4985 /* Turn off the SSC source */
4986 temp &= ~DREF_SSC_SOURCE_MASK;
4987 temp |= DREF_SSC_SOURCE_DISABLE;
4988
4989 /* Turn off SSC1 */
4990 temp &= ~ DREF_SSC1_ENABLE;
4991
4992 I915_WRITE(PCH_DREF_CONTROL, temp);
4993 POSTING_READ(PCH_DREF_CONTROL);
4994 udelay(200);
4995 }
4996 }
4997
4998 static int ironlake_get_refclk(struct drm_crtc *crtc)
4999 {
5000 struct drm_device *dev = crtc->dev;
5001 struct drm_i915_private *dev_priv = dev->dev_private;
5002 struct intel_encoder *encoder;
5003 struct intel_encoder *edp_encoder = NULL;
5004 int num_connectors = 0;
5005 bool is_lvds = false;
5006
5007 for_each_encoder_on_crtc(dev, crtc, encoder) {
5008 switch (encoder->type) {
5009 case INTEL_OUTPUT_LVDS:
5010 is_lvds = true;
5011 break;
5012 case INTEL_OUTPUT_EDP:
5013 edp_encoder = encoder;
5014 break;
5015 }
5016 num_connectors++;
5017 }
5018
5019 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5020 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5021 dev_priv->lvds_ssc_freq);
5022 return dev_priv->lvds_ssc_freq * 1000;
5023 }
5024
5025 return 120000;
5026 }
5027
5028 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5029 struct drm_display_mode *adjusted_mode,
5030 bool dither)
5031 {
5032 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5033 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5034 int pipe = intel_crtc->pipe;
5035 uint32_t val;
5036
5037 val = I915_READ(PIPECONF(pipe));
5038
5039 val &= ~PIPE_BPC_MASK;
5040 switch (intel_crtc->bpp) {
5041 case 18:
5042 val |= PIPE_6BPC;
5043 break;
5044 case 24:
5045 val |= PIPE_8BPC;
5046 break;
5047 case 30:
5048 val |= PIPE_10BPC;
5049 break;
5050 case 36:
5051 val |= PIPE_12BPC;
5052 break;
5053 default:
5054 /* Case prevented by intel_choose_pipe_bpp_dither. */
5055 BUG();
5056 }
5057
5058 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5059 if (dither)
5060 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5061
5062 val &= ~PIPECONF_INTERLACE_MASK;
5063 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5064 val |= PIPECONF_INTERLACED_ILK;
5065 else
5066 val |= PIPECONF_PROGRESSIVE;
5067
5068 I915_WRITE(PIPECONF(pipe), val);
5069 POSTING_READ(PIPECONF(pipe));
5070 }
5071
5072 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5073 struct drm_display_mode *adjusted_mode,
5074 bool dither)
5075 {
5076 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5077 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5078 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5079 uint32_t val;
5080
5081 val = I915_READ(PIPECONF(cpu_transcoder));
5082
5083 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5084 if (dither)
5085 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5086
5087 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5088 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5089 val |= PIPECONF_INTERLACED_ILK;
5090 else
5091 val |= PIPECONF_PROGRESSIVE;
5092
5093 I915_WRITE(PIPECONF(cpu_transcoder), val);
5094 POSTING_READ(PIPECONF(cpu_transcoder));
5095 }
5096
5097 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5098 struct drm_display_mode *adjusted_mode,
5099 intel_clock_t *clock,
5100 bool *has_reduced_clock,
5101 intel_clock_t *reduced_clock)
5102 {
5103 struct drm_device *dev = crtc->dev;
5104 struct drm_i915_private *dev_priv = dev->dev_private;
5105 struct intel_encoder *intel_encoder;
5106 int refclk;
5107 const intel_limit_t *limit;
5108 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5109
5110 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5111 switch (intel_encoder->type) {
5112 case INTEL_OUTPUT_LVDS:
5113 is_lvds = true;
5114 break;
5115 case INTEL_OUTPUT_SDVO:
5116 case INTEL_OUTPUT_HDMI:
5117 is_sdvo = true;
5118 if (intel_encoder->needs_tv_clock)
5119 is_tv = true;
5120 break;
5121 case INTEL_OUTPUT_TVOUT:
5122 is_tv = true;
5123 break;
5124 }
5125 }
5126
5127 refclk = ironlake_get_refclk(crtc);
5128
5129 /*
5130 * Returns a set of divisors for the desired target clock with the given
5131 * refclk, or FALSE. The returned values represent the clock equation:
5132 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5133 */
5134 limit = intel_limit(crtc, refclk);
5135 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5136 clock);
5137 if (!ret)
5138 return false;
5139
5140 if (is_lvds && dev_priv->lvds_downclock_avail) {
5141 /*
5142 * Ensure we match the reduced clock's P to the target clock.
5143 * If the clocks don't match, we can't switch the display clock
5144 * by using the FP0/FP1. In such case we will disable the LVDS
5145 * downclock feature.
5146 */
5147 *has_reduced_clock = limit->find_pll(limit, crtc,
5148 dev_priv->lvds_downclock,
5149 refclk,
5150 clock,
5151 reduced_clock);
5152 }
5153
5154 if (is_sdvo && is_tv)
5155 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5156
5157 return true;
5158 }
5159
5160 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5161 {
5162 struct drm_i915_private *dev_priv = dev->dev_private;
5163 uint32_t temp;
5164
5165 temp = I915_READ(SOUTH_CHICKEN1);
5166 if (temp & FDI_BC_BIFURCATION_SELECT)
5167 return;
5168
5169 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5170 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5171
5172 temp |= FDI_BC_BIFURCATION_SELECT;
5173 DRM_DEBUG_KMS("enabling fdi C rx\n");
5174 I915_WRITE(SOUTH_CHICKEN1, temp);
5175 POSTING_READ(SOUTH_CHICKEN1);
5176 }
5177
5178 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5179 {
5180 struct drm_device *dev = intel_crtc->base.dev;
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182 struct intel_crtc *pipe_B_crtc =
5183 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5184
5185 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5186 intel_crtc->pipe, intel_crtc->fdi_lanes);
5187 if (intel_crtc->fdi_lanes > 4) {
5188 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5189 intel_crtc->pipe, intel_crtc->fdi_lanes);
5190 /* Clamp lanes to avoid programming the hw with bogus values. */
5191 intel_crtc->fdi_lanes = 4;
5192
5193 return false;
5194 }
5195
5196 if (dev_priv->num_pipe == 2)
5197 return true;
5198
5199 switch (intel_crtc->pipe) {
5200 case PIPE_A:
5201 return true;
5202 case PIPE_B:
5203 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5204 intel_crtc->fdi_lanes > 2) {
5205 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5206 intel_crtc->pipe, intel_crtc->fdi_lanes);
5207 /* Clamp lanes to avoid programming the hw with bogus values. */
5208 intel_crtc->fdi_lanes = 2;
5209
5210 return false;
5211 }
5212
5213 if (intel_crtc->fdi_lanes > 2)
5214 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5215 else
5216 cpt_enable_fdi_bc_bifurcation(dev);
5217
5218 return true;
5219 case PIPE_C:
5220 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5221 if (intel_crtc->fdi_lanes > 2) {
5222 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5223 intel_crtc->pipe, intel_crtc->fdi_lanes);
5224 /* Clamp lanes to avoid programming the hw with bogus values. */
5225 intel_crtc->fdi_lanes = 2;
5226
5227 return false;
5228 }
5229 } else {
5230 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5231 return false;
5232 }
5233
5234 cpt_enable_fdi_bc_bifurcation(dev);
5235
5236 return true;
5237 default:
5238 BUG();
5239 }
5240 }
5241
5242 static void ironlake_set_m_n(struct drm_crtc *crtc,
5243 struct drm_display_mode *mode,
5244 struct drm_display_mode *adjusted_mode)
5245 {
5246 struct drm_device *dev = crtc->dev;
5247 struct drm_i915_private *dev_priv = dev->dev_private;
5248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5250 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5251 struct fdi_m_n m_n = {0};
5252 int target_clock, pixel_multiplier, lane, link_bw;
5253 bool is_dp = false, is_cpu_edp = false;
5254
5255 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5256 switch (intel_encoder->type) {
5257 case INTEL_OUTPUT_DISPLAYPORT:
5258 is_dp = true;
5259 break;
5260 case INTEL_OUTPUT_EDP:
5261 is_dp = true;
5262 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5263 is_cpu_edp = true;
5264 edp_encoder = intel_encoder;
5265 break;
5266 }
5267 }
5268
5269 /* FDI link */
5270 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5271 lane = 0;
5272 /* CPU eDP doesn't require FDI link, so just set DP M/N
5273 according to current link config */
5274 if (is_cpu_edp) {
5275 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5276 } else {
5277 /* FDI is a binary signal running at ~2.7GHz, encoding
5278 * each output octet as 10 bits. The actual frequency
5279 * is stored as a divider into a 100MHz clock, and the
5280 * mode pixel clock is stored in units of 1KHz.
5281 * Hence the bw of each lane in terms of the mode signal
5282 * is:
5283 */
5284 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5285 }
5286
5287 /* [e]DP over FDI requires target mode clock instead of link clock. */
5288 if (edp_encoder)
5289 target_clock = intel_edp_target_clock(edp_encoder, mode);
5290 else if (is_dp)
5291 target_clock = mode->clock;
5292 else
5293 target_clock = adjusted_mode->clock;
5294
5295 if (!lane) {
5296 /*
5297 * Account for spread spectrum to avoid
5298 * oversubscribing the link. Max center spread
5299 * is 2.5%; use 5% for safety's sake.
5300 */
5301 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5302 lane = bps / (link_bw * 8) + 1;
5303 }
5304
5305 intel_crtc->fdi_lanes = lane;
5306
5307 if (pixel_multiplier > 1)
5308 link_bw *= pixel_multiplier;
5309 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5310 &m_n);
5311
5312 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5313 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5314 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5315 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5316 }
5317
5318 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5319 struct drm_display_mode *adjusted_mode,
5320 intel_clock_t *clock, u32 fp)
5321 {
5322 struct drm_crtc *crtc = &intel_crtc->base;
5323 struct drm_device *dev = crtc->dev;
5324 struct drm_i915_private *dev_priv = dev->dev_private;
5325 struct intel_encoder *intel_encoder;
5326 uint32_t dpll;
5327 int factor, pixel_multiplier, num_connectors = 0;
5328 bool is_lvds = false, is_sdvo = false, is_tv = false;
5329 bool is_dp = false, is_cpu_edp = false;
5330
5331 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5332 switch (intel_encoder->type) {
5333 case INTEL_OUTPUT_LVDS:
5334 is_lvds = true;
5335 break;
5336 case INTEL_OUTPUT_SDVO:
5337 case INTEL_OUTPUT_HDMI:
5338 is_sdvo = true;
5339 if (intel_encoder->needs_tv_clock)
5340 is_tv = true;
5341 break;
5342 case INTEL_OUTPUT_TVOUT:
5343 is_tv = true;
5344 break;
5345 case INTEL_OUTPUT_DISPLAYPORT:
5346 is_dp = true;
5347 break;
5348 case INTEL_OUTPUT_EDP:
5349 is_dp = true;
5350 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5351 is_cpu_edp = true;
5352 break;
5353 }
5354
5355 num_connectors++;
5356 }
5357
5358 /* Enable autotuning of the PLL clock (if permissible) */
5359 factor = 21;
5360 if (is_lvds) {
5361 if ((intel_panel_use_ssc(dev_priv) &&
5362 dev_priv->lvds_ssc_freq == 100) ||
5363 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5364 factor = 25;
5365 } else if (is_sdvo && is_tv)
5366 factor = 20;
5367
5368 if (clock->m < factor * clock->n)
5369 fp |= FP_CB_TUNE;
5370
5371 dpll = 0;
5372
5373 if (is_lvds)
5374 dpll |= DPLLB_MODE_LVDS;
5375 else
5376 dpll |= DPLLB_MODE_DAC_SERIAL;
5377 if (is_sdvo) {
5378 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5379 if (pixel_multiplier > 1) {
5380 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5381 }
5382 dpll |= DPLL_DVO_HIGH_SPEED;
5383 }
5384 if (is_dp && !is_cpu_edp)
5385 dpll |= DPLL_DVO_HIGH_SPEED;
5386
5387 /* compute bitmask from p1 value */
5388 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5389 /* also FPA1 */
5390 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5391
5392 switch (clock->p2) {
5393 case 5:
5394 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5395 break;
5396 case 7:
5397 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5398 break;
5399 case 10:
5400 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5401 break;
5402 case 14:
5403 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5404 break;
5405 }
5406
5407 if (is_sdvo && is_tv)
5408 dpll |= PLL_REF_INPUT_TVCLKINBC;
5409 else if (is_tv)
5410 /* XXX: just matching BIOS for now */
5411 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5412 dpll |= 3;
5413 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5414 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5415 else
5416 dpll |= PLL_REF_INPUT_DREFCLK;
5417
5418 return dpll;
5419 }
5420
5421 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5422 struct drm_display_mode *mode,
5423 struct drm_display_mode *adjusted_mode,
5424 int x, int y,
5425 struct drm_framebuffer *fb)
5426 {
5427 struct drm_device *dev = crtc->dev;
5428 struct drm_i915_private *dev_priv = dev->dev_private;
5429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5430 int pipe = intel_crtc->pipe;
5431 int plane = intel_crtc->plane;
5432 int num_connectors = 0;
5433 intel_clock_t clock, reduced_clock;
5434 u32 dpll, fp = 0, fp2 = 0;
5435 bool ok, has_reduced_clock = false;
5436 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5437 struct intel_encoder *encoder;
5438 u32 temp;
5439 int ret;
5440 bool dither, fdi_config_ok;
5441
5442 for_each_encoder_on_crtc(dev, crtc, encoder) {
5443 switch (encoder->type) {
5444 case INTEL_OUTPUT_LVDS:
5445 is_lvds = true;
5446 break;
5447 case INTEL_OUTPUT_DISPLAYPORT:
5448 is_dp = true;
5449 break;
5450 case INTEL_OUTPUT_EDP:
5451 is_dp = true;
5452 if (!intel_encoder_is_pch_edp(&encoder->base))
5453 is_cpu_edp = true;
5454 break;
5455 }
5456
5457 num_connectors++;
5458 }
5459
5460 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5461 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5462
5463 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5464 &has_reduced_clock, &reduced_clock);
5465 if (!ok) {
5466 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5467 return -EINVAL;
5468 }
5469
5470 /* Ensure that the cursor is valid for the new mode before changing... */
5471 intel_crtc_update_cursor(crtc, true);
5472
5473 /* determine panel color depth */
5474 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5475 adjusted_mode);
5476 if (is_lvds && dev_priv->lvds_dither)
5477 dither = true;
5478
5479 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5480 if (has_reduced_clock)
5481 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5482 reduced_clock.m2;
5483
5484 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5485
5486 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5487 drm_mode_debug_printmodeline(mode);
5488
5489 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5490 if (!is_cpu_edp) {
5491 struct intel_pch_pll *pll;
5492
5493 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5494 if (pll == NULL) {
5495 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5496 pipe);
5497 return -EINVAL;
5498 }
5499 } else
5500 intel_put_pch_pll(intel_crtc);
5501
5502 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5503 * This is an exception to the general rule that mode_set doesn't turn
5504 * things on.
5505 */
5506 if (is_lvds) {
5507 temp = I915_READ(PCH_LVDS);
5508 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5509 if (HAS_PCH_CPT(dev)) {
5510 temp &= ~PORT_TRANS_SEL_MASK;
5511 temp |= PORT_TRANS_SEL_CPT(pipe);
5512 } else {
5513 if (pipe == 1)
5514 temp |= LVDS_PIPEB_SELECT;
5515 else
5516 temp &= ~LVDS_PIPEB_SELECT;
5517 }
5518
5519 /* set the corresponsding LVDS_BORDER bit */
5520 temp |= dev_priv->lvds_border_bits;
5521 /* Set the B0-B3 data pairs corresponding to whether we're going to
5522 * set the DPLLs for dual-channel mode or not.
5523 */
5524 if (clock.p2 == 7)
5525 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5526 else
5527 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
5528
5529 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5530 * appropriately here, but we need to look more thoroughly into how
5531 * panels behave in the two modes.
5532 */
5533 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5534 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5535 temp |= LVDS_HSYNC_POLARITY;
5536 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5537 temp |= LVDS_VSYNC_POLARITY;
5538 I915_WRITE(PCH_LVDS, temp);
5539 }
5540
5541 if (is_dp && !is_cpu_edp) {
5542 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5543 } else {
5544 /* For non-DP output, clear any trans DP clock recovery setting.*/
5545 I915_WRITE(TRANSDATA_M1(pipe), 0);
5546 I915_WRITE(TRANSDATA_N1(pipe), 0);
5547 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5548 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5549 }
5550
5551 if (intel_crtc->pch_pll) {
5552 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5553
5554 /* Wait for the clocks to stabilize. */
5555 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5556 udelay(150);
5557
5558 /* The pixel multiplier can only be updated once the
5559 * DPLL is enabled and the clocks are stable.
5560 *
5561 * So write it again.
5562 */
5563 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5564 }
5565
5566 intel_crtc->lowfreq_avail = false;
5567 if (intel_crtc->pch_pll) {
5568 if (is_lvds && has_reduced_clock && i915_powersave) {
5569 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5570 intel_crtc->lowfreq_avail = true;
5571 } else {
5572 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5573 }
5574 }
5575
5576 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5577
5578 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5579 * ironlake_check_fdi_lanes. */
5580 ironlake_set_m_n(crtc, mode, adjusted_mode);
5581
5582 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5583
5584 if (is_cpu_edp)
5585 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5586
5587 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5588
5589 intel_wait_for_vblank(dev, pipe);
5590
5591 /* Set up the display plane register */
5592 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5593 POSTING_READ(DSPCNTR(plane));
5594
5595 ret = intel_pipe_set_base(crtc, x, y, fb);
5596
5597 intel_update_watermarks(dev);
5598
5599 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5600
5601 return fdi_config_ok ? ret : -EINVAL;
5602 }
5603
5604 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5605 struct drm_display_mode *mode,
5606 struct drm_display_mode *adjusted_mode,
5607 int x, int y,
5608 struct drm_framebuffer *fb)
5609 {
5610 struct drm_device *dev = crtc->dev;
5611 struct drm_i915_private *dev_priv = dev->dev_private;
5612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5613 int pipe = intel_crtc->pipe;
5614 int plane = intel_crtc->plane;
5615 int num_connectors = 0;
5616 intel_clock_t clock, reduced_clock;
5617 u32 dpll = 0, fp = 0, fp2 = 0;
5618 bool ok, has_reduced_clock = false;
5619 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5620 struct intel_encoder *encoder;
5621 u32 temp;
5622 int ret;
5623 bool dither;
5624
5625 for_each_encoder_on_crtc(dev, crtc, encoder) {
5626 switch (encoder->type) {
5627 case INTEL_OUTPUT_LVDS:
5628 is_lvds = true;
5629 break;
5630 case INTEL_OUTPUT_DISPLAYPORT:
5631 is_dp = true;
5632 break;
5633 case INTEL_OUTPUT_EDP:
5634 is_dp = true;
5635 if (!intel_encoder_is_pch_edp(&encoder->base))
5636 is_cpu_edp = true;
5637 break;
5638 }
5639
5640 num_connectors++;
5641 }
5642
5643 if (is_cpu_edp)
5644 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5645 else
5646 intel_crtc->cpu_transcoder = pipe;
5647
5648 /* We are not sure yet this won't happen. */
5649 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5650 INTEL_PCH_TYPE(dev));
5651
5652 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5653 num_connectors, pipe_name(pipe));
5654
5655 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5656 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5657
5658 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5659
5660 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5661 return -EINVAL;
5662
5663 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5664 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5665 &has_reduced_clock,
5666 &reduced_clock);
5667 if (!ok) {
5668 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5669 return -EINVAL;
5670 }
5671 }
5672
5673 /* Ensure that the cursor is valid for the new mode before changing... */
5674 intel_crtc_update_cursor(crtc, true);
5675
5676 /* determine panel color depth */
5677 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5678 adjusted_mode);
5679 if (is_lvds && dev_priv->lvds_dither)
5680 dither = true;
5681
5682 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5683 drm_mode_debug_printmodeline(mode);
5684
5685 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5686 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5687 if (has_reduced_clock)
5688 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5689 reduced_clock.m2;
5690
5691 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5692 fp);
5693
5694 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5695 * own on pre-Haswell/LPT generation */
5696 if (!is_cpu_edp) {
5697 struct intel_pch_pll *pll;
5698
5699 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5700 if (pll == NULL) {
5701 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5702 pipe);
5703 return -EINVAL;
5704 }
5705 } else
5706 intel_put_pch_pll(intel_crtc);
5707
5708 /* The LVDS pin pair needs to be on before the DPLLs are
5709 * enabled. This is an exception to the general rule that
5710 * mode_set doesn't turn things on.
5711 */
5712 if (is_lvds) {
5713 temp = I915_READ(PCH_LVDS);
5714 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5715 if (HAS_PCH_CPT(dev)) {
5716 temp &= ~PORT_TRANS_SEL_MASK;
5717 temp |= PORT_TRANS_SEL_CPT(pipe);
5718 } else {
5719 if (pipe == 1)
5720 temp |= LVDS_PIPEB_SELECT;
5721 else
5722 temp &= ~LVDS_PIPEB_SELECT;
5723 }
5724
5725 /* set the corresponsding LVDS_BORDER bit */
5726 temp |= dev_priv->lvds_border_bits;
5727 /* Set the B0-B3 data pairs corresponding to whether
5728 * we're going to set the DPLLs for dual-channel mode or
5729 * not.
5730 */
5731 if (clock.p2 == 7)
5732 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5733 else
5734 temp &= ~(LVDS_B0B3_POWER_UP |
5735 LVDS_CLKB_POWER_UP);
5736
5737 /* It would be nice to set 24 vs 18-bit mode
5738 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5739 * look more thoroughly into how panels behave in the
5740 * two modes.
5741 */
5742 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5743 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5744 temp |= LVDS_HSYNC_POLARITY;
5745 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5746 temp |= LVDS_VSYNC_POLARITY;
5747 I915_WRITE(PCH_LVDS, temp);
5748 }
5749 }
5750
5751 if (is_dp && !is_cpu_edp) {
5752 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5753 } else {
5754 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5755 /* For non-DP output, clear any trans DP clock recovery
5756 * setting.*/
5757 I915_WRITE(TRANSDATA_M1(pipe), 0);
5758 I915_WRITE(TRANSDATA_N1(pipe), 0);
5759 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5760 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5761 }
5762 }
5763
5764 intel_crtc->lowfreq_avail = false;
5765 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5766 if (intel_crtc->pch_pll) {
5767 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5768
5769 /* Wait for the clocks to stabilize. */
5770 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5771 udelay(150);
5772
5773 /* The pixel multiplier can only be updated once the
5774 * DPLL is enabled and the clocks are stable.
5775 *
5776 * So write it again.
5777 */
5778 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5779 }
5780
5781 if (intel_crtc->pch_pll) {
5782 if (is_lvds && has_reduced_clock && i915_powersave) {
5783 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5784 intel_crtc->lowfreq_avail = true;
5785 } else {
5786 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5787 }
5788 }
5789 }
5790
5791 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5792
5793 if (!is_dp || is_cpu_edp)
5794 ironlake_set_m_n(crtc, mode, adjusted_mode);
5795
5796 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5797 if (is_cpu_edp)
5798 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5799
5800 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5801
5802 /* Set up the display plane register */
5803 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5804 POSTING_READ(DSPCNTR(plane));
5805
5806 ret = intel_pipe_set_base(crtc, x, y, fb);
5807
5808 intel_update_watermarks(dev);
5809
5810 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5811
5812 return ret;
5813 }
5814
5815 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5816 struct drm_display_mode *mode,
5817 struct drm_display_mode *adjusted_mode,
5818 int x, int y,
5819 struct drm_framebuffer *fb)
5820 {
5821 struct drm_device *dev = crtc->dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 struct drm_encoder_helper_funcs *encoder_funcs;
5824 struct intel_encoder *encoder;
5825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5826 int pipe = intel_crtc->pipe;
5827 int ret;
5828
5829 drm_vblank_pre_modeset(dev, pipe);
5830
5831 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5832 x, y, fb);
5833 drm_vblank_post_modeset(dev, pipe);
5834
5835 if (ret != 0)
5836 return ret;
5837
5838 for_each_encoder_on_crtc(dev, crtc, encoder) {
5839 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5840 encoder->base.base.id,
5841 drm_get_encoder_name(&encoder->base),
5842 mode->base.id, mode->name);
5843 encoder_funcs = encoder->base.helper_private;
5844 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5845 }
5846
5847 return 0;
5848 }
5849
5850 static bool intel_eld_uptodate(struct drm_connector *connector,
5851 int reg_eldv, uint32_t bits_eldv,
5852 int reg_elda, uint32_t bits_elda,
5853 int reg_edid)
5854 {
5855 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5856 uint8_t *eld = connector->eld;
5857 uint32_t i;
5858
5859 i = I915_READ(reg_eldv);
5860 i &= bits_eldv;
5861
5862 if (!eld[0])
5863 return !i;
5864
5865 if (!i)
5866 return false;
5867
5868 i = I915_READ(reg_elda);
5869 i &= ~bits_elda;
5870 I915_WRITE(reg_elda, i);
5871
5872 for (i = 0; i < eld[2]; i++)
5873 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5874 return false;
5875
5876 return true;
5877 }
5878
5879 static void g4x_write_eld(struct drm_connector *connector,
5880 struct drm_crtc *crtc)
5881 {
5882 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5883 uint8_t *eld = connector->eld;
5884 uint32_t eldv;
5885 uint32_t len;
5886 uint32_t i;
5887
5888 i = I915_READ(G4X_AUD_VID_DID);
5889
5890 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5891 eldv = G4X_ELDV_DEVCL_DEVBLC;
5892 else
5893 eldv = G4X_ELDV_DEVCTG;
5894
5895 if (intel_eld_uptodate(connector,
5896 G4X_AUD_CNTL_ST, eldv,
5897 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5898 G4X_HDMIW_HDMIEDID))
5899 return;
5900
5901 i = I915_READ(G4X_AUD_CNTL_ST);
5902 i &= ~(eldv | G4X_ELD_ADDR);
5903 len = (i >> 9) & 0x1f; /* ELD buffer size */
5904 I915_WRITE(G4X_AUD_CNTL_ST, i);
5905
5906 if (!eld[0])
5907 return;
5908
5909 len = min_t(uint8_t, eld[2], len);
5910 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5911 for (i = 0; i < len; i++)
5912 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5913
5914 i = I915_READ(G4X_AUD_CNTL_ST);
5915 i |= eldv;
5916 I915_WRITE(G4X_AUD_CNTL_ST, i);
5917 }
5918
5919 static void haswell_write_eld(struct drm_connector *connector,
5920 struct drm_crtc *crtc)
5921 {
5922 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5923 uint8_t *eld = connector->eld;
5924 struct drm_device *dev = crtc->dev;
5925 uint32_t eldv;
5926 uint32_t i;
5927 int len;
5928 int pipe = to_intel_crtc(crtc)->pipe;
5929 int tmp;
5930
5931 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5932 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5933 int aud_config = HSW_AUD_CFG(pipe);
5934 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5935
5936
5937 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5938
5939 /* Audio output enable */
5940 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5941 tmp = I915_READ(aud_cntrl_st2);
5942 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5943 I915_WRITE(aud_cntrl_st2, tmp);
5944
5945 /* Wait for 1 vertical blank */
5946 intel_wait_for_vblank(dev, pipe);
5947
5948 /* Set ELD valid state */
5949 tmp = I915_READ(aud_cntrl_st2);
5950 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5951 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5952 I915_WRITE(aud_cntrl_st2, tmp);
5953 tmp = I915_READ(aud_cntrl_st2);
5954 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5955
5956 /* Enable HDMI mode */
5957 tmp = I915_READ(aud_config);
5958 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5959 /* clear N_programing_enable and N_value_index */
5960 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5961 I915_WRITE(aud_config, tmp);
5962
5963 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5964
5965 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5966
5967 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5968 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5969 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5970 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5971 } else
5972 I915_WRITE(aud_config, 0);
5973
5974 if (intel_eld_uptodate(connector,
5975 aud_cntrl_st2, eldv,
5976 aud_cntl_st, IBX_ELD_ADDRESS,
5977 hdmiw_hdmiedid))
5978 return;
5979
5980 i = I915_READ(aud_cntrl_st2);
5981 i &= ~eldv;
5982 I915_WRITE(aud_cntrl_st2, i);
5983
5984 if (!eld[0])
5985 return;
5986
5987 i = I915_READ(aud_cntl_st);
5988 i &= ~IBX_ELD_ADDRESS;
5989 I915_WRITE(aud_cntl_st, i);
5990 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5991 DRM_DEBUG_DRIVER("port num:%d\n", i);
5992
5993 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5994 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5995 for (i = 0; i < len; i++)
5996 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5997
5998 i = I915_READ(aud_cntrl_st2);
5999 i |= eldv;
6000 I915_WRITE(aud_cntrl_st2, i);
6001
6002 }
6003
6004 static void ironlake_write_eld(struct drm_connector *connector,
6005 struct drm_crtc *crtc)
6006 {
6007 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6008 uint8_t *eld = connector->eld;
6009 uint32_t eldv;
6010 uint32_t i;
6011 int len;
6012 int hdmiw_hdmiedid;
6013 int aud_config;
6014 int aud_cntl_st;
6015 int aud_cntrl_st2;
6016 int pipe = to_intel_crtc(crtc)->pipe;
6017
6018 if (HAS_PCH_IBX(connector->dev)) {
6019 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6020 aud_config = IBX_AUD_CFG(pipe);
6021 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6022 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6023 } else {
6024 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6025 aud_config = CPT_AUD_CFG(pipe);
6026 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6027 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6028 }
6029
6030 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6031
6032 i = I915_READ(aud_cntl_st);
6033 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6034 if (!i) {
6035 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6036 /* operate blindly on all ports */
6037 eldv = IBX_ELD_VALIDB;
6038 eldv |= IBX_ELD_VALIDB << 4;
6039 eldv |= IBX_ELD_VALIDB << 8;
6040 } else {
6041 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
6042 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6043 }
6044
6045 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6046 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6047 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6048 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6049 } else
6050 I915_WRITE(aud_config, 0);
6051
6052 if (intel_eld_uptodate(connector,
6053 aud_cntrl_st2, eldv,
6054 aud_cntl_st, IBX_ELD_ADDRESS,
6055 hdmiw_hdmiedid))
6056 return;
6057
6058 i = I915_READ(aud_cntrl_st2);
6059 i &= ~eldv;
6060 I915_WRITE(aud_cntrl_st2, i);
6061
6062 if (!eld[0])
6063 return;
6064
6065 i = I915_READ(aud_cntl_st);
6066 i &= ~IBX_ELD_ADDRESS;
6067 I915_WRITE(aud_cntl_st, i);
6068
6069 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6070 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6071 for (i = 0; i < len; i++)
6072 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6073
6074 i = I915_READ(aud_cntrl_st2);
6075 i |= eldv;
6076 I915_WRITE(aud_cntrl_st2, i);
6077 }
6078
6079 void intel_write_eld(struct drm_encoder *encoder,
6080 struct drm_display_mode *mode)
6081 {
6082 struct drm_crtc *crtc = encoder->crtc;
6083 struct drm_connector *connector;
6084 struct drm_device *dev = encoder->dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086
6087 connector = drm_select_eld(encoder, mode);
6088 if (!connector)
6089 return;
6090
6091 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6092 connector->base.id,
6093 drm_get_connector_name(connector),
6094 connector->encoder->base.id,
6095 drm_get_encoder_name(connector->encoder));
6096
6097 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6098
6099 if (dev_priv->display.write_eld)
6100 dev_priv->display.write_eld(connector, crtc);
6101 }
6102
6103 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6104 void intel_crtc_load_lut(struct drm_crtc *crtc)
6105 {
6106 struct drm_device *dev = crtc->dev;
6107 struct drm_i915_private *dev_priv = dev->dev_private;
6108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6109 int palreg = PALETTE(intel_crtc->pipe);
6110 int i;
6111
6112 /* The clocks have to be on to load the palette. */
6113 if (!crtc->enabled || !intel_crtc->active)
6114 return;
6115
6116 /* use legacy palette for Ironlake */
6117 if (HAS_PCH_SPLIT(dev))
6118 palreg = LGC_PALETTE(intel_crtc->pipe);
6119
6120 for (i = 0; i < 256; i++) {
6121 I915_WRITE(palreg + 4 * i,
6122 (intel_crtc->lut_r[i] << 16) |
6123 (intel_crtc->lut_g[i] << 8) |
6124 intel_crtc->lut_b[i]);
6125 }
6126 }
6127
6128 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6129 {
6130 struct drm_device *dev = crtc->dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6133 bool visible = base != 0;
6134 u32 cntl;
6135
6136 if (intel_crtc->cursor_visible == visible)
6137 return;
6138
6139 cntl = I915_READ(_CURACNTR);
6140 if (visible) {
6141 /* On these chipsets we can only modify the base whilst
6142 * the cursor is disabled.
6143 */
6144 I915_WRITE(_CURABASE, base);
6145
6146 cntl &= ~(CURSOR_FORMAT_MASK);
6147 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6148 cntl |= CURSOR_ENABLE |
6149 CURSOR_GAMMA_ENABLE |
6150 CURSOR_FORMAT_ARGB;
6151 } else
6152 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6153 I915_WRITE(_CURACNTR, cntl);
6154
6155 intel_crtc->cursor_visible = visible;
6156 }
6157
6158 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6159 {
6160 struct drm_device *dev = crtc->dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163 int pipe = intel_crtc->pipe;
6164 bool visible = base != 0;
6165
6166 if (intel_crtc->cursor_visible != visible) {
6167 uint32_t cntl = I915_READ(CURCNTR(pipe));
6168 if (base) {
6169 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6170 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6171 cntl |= pipe << 28; /* Connect to correct pipe */
6172 } else {
6173 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6174 cntl |= CURSOR_MODE_DISABLE;
6175 }
6176 I915_WRITE(CURCNTR(pipe), cntl);
6177
6178 intel_crtc->cursor_visible = visible;
6179 }
6180 /* and commit changes on next vblank */
6181 I915_WRITE(CURBASE(pipe), base);
6182 }
6183
6184 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6185 {
6186 struct drm_device *dev = crtc->dev;
6187 struct drm_i915_private *dev_priv = dev->dev_private;
6188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6189 int pipe = intel_crtc->pipe;
6190 bool visible = base != 0;
6191
6192 if (intel_crtc->cursor_visible != visible) {
6193 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6194 if (base) {
6195 cntl &= ~CURSOR_MODE;
6196 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6197 } else {
6198 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6199 cntl |= CURSOR_MODE_DISABLE;
6200 }
6201 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6202
6203 intel_crtc->cursor_visible = visible;
6204 }
6205 /* and commit changes on next vblank */
6206 I915_WRITE(CURBASE_IVB(pipe), base);
6207 }
6208
6209 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6210 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6211 bool on)
6212 {
6213 struct drm_device *dev = crtc->dev;
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6216 int pipe = intel_crtc->pipe;
6217 int x = intel_crtc->cursor_x;
6218 int y = intel_crtc->cursor_y;
6219 u32 base, pos;
6220 bool visible;
6221
6222 pos = 0;
6223
6224 if (on && crtc->enabled && crtc->fb) {
6225 base = intel_crtc->cursor_addr;
6226 if (x > (int) crtc->fb->width)
6227 base = 0;
6228
6229 if (y > (int) crtc->fb->height)
6230 base = 0;
6231 } else
6232 base = 0;
6233
6234 if (x < 0) {
6235 if (x + intel_crtc->cursor_width < 0)
6236 base = 0;
6237
6238 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6239 x = -x;
6240 }
6241 pos |= x << CURSOR_X_SHIFT;
6242
6243 if (y < 0) {
6244 if (y + intel_crtc->cursor_height < 0)
6245 base = 0;
6246
6247 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6248 y = -y;
6249 }
6250 pos |= y << CURSOR_Y_SHIFT;
6251
6252 visible = base != 0;
6253 if (!visible && !intel_crtc->cursor_visible)
6254 return;
6255
6256 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6257 I915_WRITE(CURPOS_IVB(pipe), pos);
6258 ivb_update_cursor(crtc, base);
6259 } else {
6260 I915_WRITE(CURPOS(pipe), pos);
6261 if (IS_845G(dev) || IS_I865G(dev))
6262 i845_update_cursor(crtc, base);
6263 else
6264 i9xx_update_cursor(crtc, base);
6265 }
6266 }
6267
6268 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6269 struct drm_file *file,
6270 uint32_t handle,
6271 uint32_t width, uint32_t height)
6272 {
6273 struct drm_device *dev = crtc->dev;
6274 struct drm_i915_private *dev_priv = dev->dev_private;
6275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6276 struct drm_i915_gem_object *obj;
6277 uint32_t addr;
6278 int ret;
6279
6280 /* if we want to turn off the cursor ignore width and height */
6281 if (!handle) {
6282 DRM_DEBUG_KMS("cursor off\n");
6283 addr = 0;
6284 obj = NULL;
6285 mutex_lock(&dev->struct_mutex);
6286 goto finish;
6287 }
6288
6289 /* Currently we only support 64x64 cursors */
6290 if (width != 64 || height != 64) {
6291 DRM_ERROR("we currently only support 64x64 cursors\n");
6292 return -EINVAL;
6293 }
6294
6295 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6296 if (&obj->base == NULL)
6297 return -ENOENT;
6298
6299 if (obj->base.size < width * height * 4) {
6300 DRM_ERROR("buffer is to small\n");
6301 ret = -ENOMEM;
6302 goto fail;
6303 }
6304
6305 /* we only need to pin inside GTT if cursor is non-phy */
6306 mutex_lock(&dev->struct_mutex);
6307 if (!dev_priv->info->cursor_needs_physical) {
6308 if (obj->tiling_mode) {
6309 DRM_ERROR("cursor cannot be tiled\n");
6310 ret = -EINVAL;
6311 goto fail_locked;
6312 }
6313
6314 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6315 if (ret) {
6316 DRM_ERROR("failed to move cursor bo into the GTT\n");
6317 goto fail_locked;
6318 }
6319
6320 ret = i915_gem_object_put_fence(obj);
6321 if (ret) {
6322 DRM_ERROR("failed to release fence for cursor");
6323 goto fail_unpin;
6324 }
6325
6326 addr = obj->gtt_offset;
6327 } else {
6328 int align = IS_I830(dev) ? 16 * 1024 : 256;
6329 ret = i915_gem_attach_phys_object(dev, obj,
6330 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6331 align);
6332 if (ret) {
6333 DRM_ERROR("failed to attach phys object\n");
6334 goto fail_locked;
6335 }
6336 addr = obj->phys_obj->handle->busaddr;
6337 }
6338
6339 if (IS_GEN2(dev))
6340 I915_WRITE(CURSIZE, (height << 12) | width);
6341
6342 finish:
6343 if (intel_crtc->cursor_bo) {
6344 if (dev_priv->info->cursor_needs_physical) {
6345 if (intel_crtc->cursor_bo != obj)
6346 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6347 } else
6348 i915_gem_object_unpin(intel_crtc->cursor_bo);
6349 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6350 }
6351
6352 mutex_unlock(&dev->struct_mutex);
6353
6354 intel_crtc->cursor_addr = addr;
6355 intel_crtc->cursor_bo = obj;
6356 intel_crtc->cursor_width = width;
6357 intel_crtc->cursor_height = height;
6358
6359 intel_crtc_update_cursor(crtc, true);
6360
6361 return 0;
6362 fail_unpin:
6363 i915_gem_object_unpin(obj);
6364 fail_locked:
6365 mutex_unlock(&dev->struct_mutex);
6366 fail:
6367 drm_gem_object_unreference_unlocked(&obj->base);
6368 return ret;
6369 }
6370
6371 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6372 {
6373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6374
6375 intel_crtc->cursor_x = x;
6376 intel_crtc->cursor_y = y;
6377
6378 intel_crtc_update_cursor(crtc, true);
6379
6380 return 0;
6381 }
6382
6383 /** Sets the color ramps on behalf of RandR */
6384 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6385 u16 blue, int regno)
6386 {
6387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388
6389 intel_crtc->lut_r[regno] = red >> 8;
6390 intel_crtc->lut_g[regno] = green >> 8;
6391 intel_crtc->lut_b[regno] = blue >> 8;
6392 }
6393
6394 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6395 u16 *blue, int regno)
6396 {
6397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398
6399 *red = intel_crtc->lut_r[regno] << 8;
6400 *green = intel_crtc->lut_g[regno] << 8;
6401 *blue = intel_crtc->lut_b[regno] << 8;
6402 }
6403
6404 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6405 u16 *blue, uint32_t start, uint32_t size)
6406 {
6407 int end = (start + size > 256) ? 256 : start + size, i;
6408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6409
6410 for (i = start; i < end; i++) {
6411 intel_crtc->lut_r[i] = red[i] >> 8;
6412 intel_crtc->lut_g[i] = green[i] >> 8;
6413 intel_crtc->lut_b[i] = blue[i] >> 8;
6414 }
6415
6416 intel_crtc_load_lut(crtc);
6417 }
6418
6419 /**
6420 * Get a pipe with a simple mode set on it for doing load-based monitor
6421 * detection.
6422 *
6423 * It will be up to the load-detect code to adjust the pipe as appropriate for
6424 * its requirements. The pipe will be connected to no other encoders.
6425 *
6426 * Currently this code will only succeed if there is a pipe with no encoders
6427 * configured for it. In the future, it could choose to temporarily disable
6428 * some outputs to free up a pipe for its use.
6429 *
6430 * \return crtc, or NULL if no pipes are available.
6431 */
6432
6433 /* VESA 640x480x72Hz mode to set on the pipe */
6434 static struct drm_display_mode load_detect_mode = {
6435 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6436 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6437 };
6438
6439 static struct drm_framebuffer *
6440 intel_framebuffer_create(struct drm_device *dev,
6441 struct drm_mode_fb_cmd2 *mode_cmd,
6442 struct drm_i915_gem_object *obj)
6443 {
6444 struct intel_framebuffer *intel_fb;
6445 int ret;
6446
6447 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6448 if (!intel_fb) {
6449 drm_gem_object_unreference_unlocked(&obj->base);
6450 return ERR_PTR(-ENOMEM);
6451 }
6452
6453 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6454 if (ret) {
6455 drm_gem_object_unreference_unlocked(&obj->base);
6456 kfree(intel_fb);
6457 return ERR_PTR(ret);
6458 }
6459
6460 return &intel_fb->base;
6461 }
6462
6463 static u32
6464 intel_framebuffer_pitch_for_width(int width, int bpp)
6465 {
6466 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6467 return ALIGN(pitch, 64);
6468 }
6469
6470 static u32
6471 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6472 {
6473 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6474 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6475 }
6476
6477 static struct drm_framebuffer *
6478 intel_framebuffer_create_for_mode(struct drm_device *dev,
6479 struct drm_display_mode *mode,
6480 int depth, int bpp)
6481 {
6482 struct drm_i915_gem_object *obj;
6483 struct drm_mode_fb_cmd2 mode_cmd;
6484
6485 obj = i915_gem_alloc_object(dev,
6486 intel_framebuffer_size_for_mode(mode, bpp));
6487 if (obj == NULL)
6488 return ERR_PTR(-ENOMEM);
6489
6490 mode_cmd.width = mode->hdisplay;
6491 mode_cmd.height = mode->vdisplay;
6492 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6493 bpp);
6494 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6495
6496 return intel_framebuffer_create(dev, &mode_cmd, obj);
6497 }
6498
6499 static struct drm_framebuffer *
6500 mode_fits_in_fbdev(struct drm_device *dev,
6501 struct drm_display_mode *mode)
6502 {
6503 struct drm_i915_private *dev_priv = dev->dev_private;
6504 struct drm_i915_gem_object *obj;
6505 struct drm_framebuffer *fb;
6506
6507 if (dev_priv->fbdev == NULL)
6508 return NULL;
6509
6510 obj = dev_priv->fbdev->ifb.obj;
6511 if (obj == NULL)
6512 return NULL;
6513
6514 fb = &dev_priv->fbdev->ifb.base;
6515 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6516 fb->bits_per_pixel))
6517 return NULL;
6518
6519 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6520 return NULL;
6521
6522 return fb;
6523 }
6524
6525 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6526 struct drm_display_mode *mode,
6527 struct intel_load_detect_pipe *old)
6528 {
6529 struct intel_crtc *intel_crtc;
6530 struct intel_encoder *intel_encoder =
6531 intel_attached_encoder(connector);
6532 struct drm_crtc *possible_crtc;
6533 struct drm_encoder *encoder = &intel_encoder->base;
6534 struct drm_crtc *crtc = NULL;
6535 struct drm_device *dev = encoder->dev;
6536 struct drm_framebuffer *fb;
6537 int i = -1;
6538
6539 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6540 connector->base.id, drm_get_connector_name(connector),
6541 encoder->base.id, drm_get_encoder_name(encoder));
6542
6543 /*
6544 * Algorithm gets a little messy:
6545 *
6546 * - if the connector already has an assigned crtc, use it (but make
6547 * sure it's on first)
6548 *
6549 * - try to find the first unused crtc that can drive this connector,
6550 * and use that if we find one
6551 */
6552
6553 /* See if we already have a CRTC for this connector */
6554 if (encoder->crtc) {
6555 crtc = encoder->crtc;
6556
6557 old->dpms_mode = connector->dpms;
6558 old->load_detect_temp = false;
6559
6560 /* Make sure the crtc and connector are running */
6561 if (connector->dpms != DRM_MODE_DPMS_ON)
6562 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6563
6564 return true;
6565 }
6566
6567 /* Find an unused one (if possible) */
6568 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6569 i++;
6570 if (!(encoder->possible_crtcs & (1 << i)))
6571 continue;
6572 if (!possible_crtc->enabled) {
6573 crtc = possible_crtc;
6574 break;
6575 }
6576 }
6577
6578 /*
6579 * If we didn't find an unused CRTC, don't use any.
6580 */
6581 if (!crtc) {
6582 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6583 return false;
6584 }
6585
6586 intel_encoder->new_crtc = to_intel_crtc(crtc);
6587 to_intel_connector(connector)->new_encoder = intel_encoder;
6588
6589 intel_crtc = to_intel_crtc(crtc);
6590 old->dpms_mode = connector->dpms;
6591 old->load_detect_temp = true;
6592 old->release_fb = NULL;
6593
6594 if (!mode)
6595 mode = &load_detect_mode;
6596
6597 /* We need a framebuffer large enough to accommodate all accesses
6598 * that the plane may generate whilst we perform load detection.
6599 * We can not rely on the fbcon either being present (we get called
6600 * during its initialisation to detect all boot displays, or it may
6601 * not even exist) or that it is large enough to satisfy the
6602 * requested mode.
6603 */
6604 fb = mode_fits_in_fbdev(dev, mode);
6605 if (fb == NULL) {
6606 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6607 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6608 old->release_fb = fb;
6609 } else
6610 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6611 if (IS_ERR(fb)) {
6612 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6613 goto fail;
6614 }
6615
6616 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6617 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6618 if (old->release_fb)
6619 old->release_fb->funcs->destroy(old->release_fb);
6620 goto fail;
6621 }
6622
6623 /* let the connector get through one full cycle before testing */
6624 intel_wait_for_vblank(dev, intel_crtc->pipe);
6625
6626 return true;
6627 fail:
6628 connector->encoder = NULL;
6629 encoder->crtc = NULL;
6630 return false;
6631 }
6632
6633 void intel_release_load_detect_pipe(struct drm_connector *connector,
6634 struct intel_load_detect_pipe *old)
6635 {
6636 struct intel_encoder *intel_encoder =
6637 intel_attached_encoder(connector);
6638 struct drm_encoder *encoder = &intel_encoder->base;
6639
6640 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6641 connector->base.id, drm_get_connector_name(connector),
6642 encoder->base.id, drm_get_encoder_name(encoder));
6643
6644 if (old->load_detect_temp) {
6645 struct drm_crtc *crtc = encoder->crtc;
6646
6647 to_intel_connector(connector)->new_encoder = NULL;
6648 intel_encoder->new_crtc = NULL;
6649 intel_set_mode(crtc, NULL, 0, 0, NULL);
6650
6651 if (old->release_fb)
6652 old->release_fb->funcs->destroy(old->release_fb);
6653
6654 return;
6655 }
6656
6657 /* Switch crtc and encoder back off if necessary */
6658 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6659 connector->funcs->dpms(connector, old->dpms_mode);
6660 }
6661
6662 /* Returns the clock of the currently programmed mode of the given pipe. */
6663 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6664 {
6665 struct drm_i915_private *dev_priv = dev->dev_private;
6666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6667 int pipe = intel_crtc->pipe;
6668 u32 dpll = I915_READ(DPLL(pipe));
6669 u32 fp;
6670 intel_clock_t clock;
6671
6672 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6673 fp = I915_READ(FP0(pipe));
6674 else
6675 fp = I915_READ(FP1(pipe));
6676
6677 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6678 if (IS_PINEVIEW(dev)) {
6679 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6680 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6681 } else {
6682 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6683 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6684 }
6685
6686 if (!IS_GEN2(dev)) {
6687 if (IS_PINEVIEW(dev))
6688 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6689 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6690 else
6691 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6692 DPLL_FPA01_P1_POST_DIV_SHIFT);
6693
6694 switch (dpll & DPLL_MODE_MASK) {
6695 case DPLLB_MODE_DAC_SERIAL:
6696 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6697 5 : 10;
6698 break;
6699 case DPLLB_MODE_LVDS:
6700 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6701 7 : 14;
6702 break;
6703 default:
6704 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6705 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6706 return 0;
6707 }
6708
6709 /* XXX: Handle the 100Mhz refclk */
6710 intel_clock(dev, 96000, &clock);
6711 } else {
6712 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6713
6714 if (is_lvds) {
6715 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6716 DPLL_FPA01_P1_POST_DIV_SHIFT);
6717 clock.p2 = 14;
6718
6719 if ((dpll & PLL_REF_INPUT_MASK) ==
6720 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6721 /* XXX: might not be 66MHz */
6722 intel_clock(dev, 66000, &clock);
6723 } else
6724 intel_clock(dev, 48000, &clock);
6725 } else {
6726 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6727 clock.p1 = 2;
6728 else {
6729 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6730 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6731 }
6732 if (dpll & PLL_P2_DIVIDE_BY_4)
6733 clock.p2 = 4;
6734 else
6735 clock.p2 = 2;
6736
6737 intel_clock(dev, 48000, &clock);
6738 }
6739 }
6740
6741 /* XXX: It would be nice to validate the clocks, but we can't reuse
6742 * i830PllIsValid() because it relies on the xf86_config connector
6743 * configuration being accurate, which it isn't necessarily.
6744 */
6745
6746 return clock.dot;
6747 }
6748
6749 /** Returns the currently programmed mode of the given pipe. */
6750 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6751 struct drm_crtc *crtc)
6752 {
6753 struct drm_i915_private *dev_priv = dev->dev_private;
6754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6755 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6756 struct drm_display_mode *mode;
6757 int htot = I915_READ(HTOTAL(cpu_transcoder));
6758 int hsync = I915_READ(HSYNC(cpu_transcoder));
6759 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6760 int vsync = I915_READ(VSYNC(cpu_transcoder));
6761
6762 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6763 if (!mode)
6764 return NULL;
6765
6766 mode->clock = intel_crtc_clock_get(dev, crtc);
6767 mode->hdisplay = (htot & 0xffff) + 1;
6768 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6769 mode->hsync_start = (hsync & 0xffff) + 1;
6770 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6771 mode->vdisplay = (vtot & 0xffff) + 1;
6772 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6773 mode->vsync_start = (vsync & 0xffff) + 1;
6774 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6775
6776 drm_mode_set_name(mode);
6777
6778 return mode;
6779 }
6780
6781 static void intel_increase_pllclock(struct drm_crtc *crtc)
6782 {
6783 struct drm_device *dev = crtc->dev;
6784 drm_i915_private_t *dev_priv = dev->dev_private;
6785 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6786 int pipe = intel_crtc->pipe;
6787 int dpll_reg = DPLL(pipe);
6788 int dpll;
6789
6790 if (HAS_PCH_SPLIT(dev))
6791 return;
6792
6793 if (!dev_priv->lvds_downclock_avail)
6794 return;
6795
6796 dpll = I915_READ(dpll_reg);
6797 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6798 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6799
6800 assert_panel_unlocked(dev_priv, pipe);
6801
6802 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6803 I915_WRITE(dpll_reg, dpll);
6804 intel_wait_for_vblank(dev, pipe);
6805
6806 dpll = I915_READ(dpll_reg);
6807 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6808 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6809 }
6810 }
6811
6812 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6813 {
6814 struct drm_device *dev = crtc->dev;
6815 drm_i915_private_t *dev_priv = dev->dev_private;
6816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6817
6818 if (HAS_PCH_SPLIT(dev))
6819 return;
6820
6821 if (!dev_priv->lvds_downclock_avail)
6822 return;
6823
6824 /*
6825 * Since this is called by a timer, we should never get here in
6826 * the manual case.
6827 */
6828 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6829 int pipe = intel_crtc->pipe;
6830 int dpll_reg = DPLL(pipe);
6831 int dpll;
6832
6833 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6834
6835 assert_panel_unlocked(dev_priv, pipe);
6836
6837 dpll = I915_READ(dpll_reg);
6838 dpll |= DISPLAY_RATE_SELECT_FPA1;
6839 I915_WRITE(dpll_reg, dpll);
6840 intel_wait_for_vblank(dev, pipe);
6841 dpll = I915_READ(dpll_reg);
6842 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6843 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6844 }
6845
6846 }
6847
6848 void intel_mark_busy(struct drm_device *dev)
6849 {
6850 i915_update_gfx_val(dev->dev_private);
6851 }
6852
6853 void intel_mark_idle(struct drm_device *dev)
6854 {
6855 }
6856
6857 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6858 {
6859 struct drm_device *dev = obj->base.dev;
6860 struct drm_crtc *crtc;
6861
6862 if (!i915_powersave)
6863 return;
6864
6865 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6866 if (!crtc->fb)
6867 continue;
6868
6869 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6870 intel_increase_pllclock(crtc);
6871 }
6872 }
6873
6874 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6875 {
6876 struct drm_device *dev = obj->base.dev;
6877 struct drm_crtc *crtc;
6878
6879 if (!i915_powersave)
6880 return;
6881
6882 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6883 if (!crtc->fb)
6884 continue;
6885
6886 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6887 intel_decrease_pllclock(crtc);
6888 }
6889 }
6890
6891 static void intel_crtc_destroy(struct drm_crtc *crtc)
6892 {
6893 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6894 struct drm_device *dev = crtc->dev;
6895 struct intel_unpin_work *work;
6896 unsigned long flags;
6897
6898 spin_lock_irqsave(&dev->event_lock, flags);
6899 work = intel_crtc->unpin_work;
6900 intel_crtc->unpin_work = NULL;
6901 spin_unlock_irqrestore(&dev->event_lock, flags);
6902
6903 if (work) {
6904 cancel_work_sync(&work->work);
6905 kfree(work);
6906 }
6907
6908 drm_crtc_cleanup(crtc);
6909
6910 kfree(intel_crtc);
6911 }
6912
6913 static void intel_unpin_work_fn(struct work_struct *__work)
6914 {
6915 struct intel_unpin_work *work =
6916 container_of(__work, struct intel_unpin_work, work);
6917
6918 mutex_lock(&work->dev->struct_mutex);
6919 intel_unpin_fb_obj(work->old_fb_obj);
6920 drm_gem_object_unreference(&work->pending_flip_obj->base);
6921 drm_gem_object_unreference(&work->old_fb_obj->base);
6922
6923 intel_update_fbc(work->dev);
6924 mutex_unlock(&work->dev->struct_mutex);
6925 kfree(work);
6926 }
6927
6928 static void do_intel_finish_page_flip(struct drm_device *dev,
6929 struct drm_crtc *crtc)
6930 {
6931 drm_i915_private_t *dev_priv = dev->dev_private;
6932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6933 struct intel_unpin_work *work;
6934 struct drm_i915_gem_object *obj;
6935 struct drm_pending_vblank_event *e;
6936 struct timeval tvbl;
6937 unsigned long flags;
6938
6939 /* Ignore early vblank irqs */
6940 if (intel_crtc == NULL)
6941 return;
6942
6943 spin_lock_irqsave(&dev->event_lock, flags);
6944 work = intel_crtc->unpin_work;
6945 if (work == NULL || !work->pending) {
6946 spin_unlock_irqrestore(&dev->event_lock, flags);
6947 return;
6948 }
6949
6950 intel_crtc->unpin_work = NULL;
6951
6952 if (work->event) {
6953 e = work->event;
6954 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
6955
6956 e->event.tv_sec = tvbl.tv_sec;
6957 e->event.tv_usec = tvbl.tv_usec;
6958
6959 list_add_tail(&e->base.link,
6960 &e->base.file_priv->event_list);
6961 wake_up_interruptible(&e->base.file_priv->event_wait);
6962 }
6963
6964 drm_vblank_put(dev, intel_crtc->pipe);
6965
6966 spin_unlock_irqrestore(&dev->event_lock, flags);
6967
6968 obj = work->old_fb_obj;
6969
6970 atomic_clear_mask(1 << intel_crtc->plane,
6971 &obj->pending_flip.counter);
6972
6973 wake_up(&dev_priv->pending_flip_queue);
6974 schedule_work(&work->work);
6975
6976 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6977 }
6978
6979 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6980 {
6981 drm_i915_private_t *dev_priv = dev->dev_private;
6982 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6983
6984 do_intel_finish_page_flip(dev, crtc);
6985 }
6986
6987 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6988 {
6989 drm_i915_private_t *dev_priv = dev->dev_private;
6990 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6991
6992 do_intel_finish_page_flip(dev, crtc);
6993 }
6994
6995 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6996 {
6997 drm_i915_private_t *dev_priv = dev->dev_private;
6998 struct intel_crtc *intel_crtc =
6999 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7000 unsigned long flags;
7001
7002 spin_lock_irqsave(&dev->event_lock, flags);
7003 if (intel_crtc->unpin_work) {
7004 if ((++intel_crtc->unpin_work->pending) > 1)
7005 DRM_ERROR("Prepared flip multiple times\n");
7006 } else {
7007 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7008 }
7009 spin_unlock_irqrestore(&dev->event_lock, flags);
7010 }
7011
7012 static int intel_gen2_queue_flip(struct drm_device *dev,
7013 struct drm_crtc *crtc,
7014 struct drm_framebuffer *fb,
7015 struct drm_i915_gem_object *obj)
7016 {
7017 struct drm_i915_private *dev_priv = dev->dev_private;
7018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019 u32 flip_mask;
7020 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7021 int ret;
7022
7023 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7024 if (ret)
7025 goto err;
7026
7027 ret = intel_ring_begin(ring, 6);
7028 if (ret)
7029 goto err_unpin;
7030
7031 /* Can't queue multiple flips, so wait for the previous
7032 * one to finish before executing the next.
7033 */
7034 if (intel_crtc->plane)
7035 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7036 else
7037 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7038 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7039 intel_ring_emit(ring, MI_NOOP);
7040 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7041 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7042 intel_ring_emit(ring, fb->pitches[0]);
7043 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7044 intel_ring_emit(ring, 0); /* aux display base address, unused */
7045 intel_ring_advance(ring);
7046 return 0;
7047
7048 err_unpin:
7049 intel_unpin_fb_obj(obj);
7050 err:
7051 return ret;
7052 }
7053
7054 static int intel_gen3_queue_flip(struct drm_device *dev,
7055 struct drm_crtc *crtc,
7056 struct drm_framebuffer *fb,
7057 struct drm_i915_gem_object *obj)
7058 {
7059 struct drm_i915_private *dev_priv = dev->dev_private;
7060 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7061 u32 flip_mask;
7062 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7063 int ret;
7064
7065 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7066 if (ret)
7067 goto err;
7068
7069 ret = intel_ring_begin(ring, 6);
7070 if (ret)
7071 goto err_unpin;
7072
7073 if (intel_crtc->plane)
7074 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7075 else
7076 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7077 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7078 intel_ring_emit(ring, MI_NOOP);
7079 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7080 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7081 intel_ring_emit(ring, fb->pitches[0]);
7082 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7083 intel_ring_emit(ring, MI_NOOP);
7084
7085 intel_ring_advance(ring);
7086 return 0;
7087
7088 err_unpin:
7089 intel_unpin_fb_obj(obj);
7090 err:
7091 return ret;
7092 }
7093
7094 static int intel_gen4_queue_flip(struct drm_device *dev,
7095 struct drm_crtc *crtc,
7096 struct drm_framebuffer *fb,
7097 struct drm_i915_gem_object *obj)
7098 {
7099 struct drm_i915_private *dev_priv = dev->dev_private;
7100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101 uint32_t pf, pipesrc;
7102 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7103 int ret;
7104
7105 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7106 if (ret)
7107 goto err;
7108
7109 ret = intel_ring_begin(ring, 4);
7110 if (ret)
7111 goto err_unpin;
7112
7113 /* i965+ uses the linear or tiled offsets from the
7114 * Display Registers (which do not change across a page-flip)
7115 * so we need only reprogram the base address.
7116 */
7117 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7118 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7119 intel_ring_emit(ring, fb->pitches[0]);
7120 intel_ring_emit(ring,
7121 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7122 obj->tiling_mode);
7123
7124 /* XXX Enabling the panel-fitter across page-flip is so far
7125 * untested on non-native modes, so ignore it for now.
7126 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7127 */
7128 pf = 0;
7129 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7130 intel_ring_emit(ring, pf | pipesrc);
7131 intel_ring_advance(ring);
7132 return 0;
7133
7134 err_unpin:
7135 intel_unpin_fb_obj(obj);
7136 err:
7137 return ret;
7138 }
7139
7140 static int intel_gen6_queue_flip(struct drm_device *dev,
7141 struct drm_crtc *crtc,
7142 struct drm_framebuffer *fb,
7143 struct drm_i915_gem_object *obj)
7144 {
7145 struct drm_i915_private *dev_priv = dev->dev_private;
7146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7147 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7148 uint32_t pf, pipesrc;
7149 int ret;
7150
7151 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7152 if (ret)
7153 goto err;
7154
7155 ret = intel_ring_begin(ring, 4);
7156 if (ret)
7157 goto err_unpin;
7158
7159 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7160 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7161 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7162 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7163
7164 /* Contrary to the suggestions in the documentation,
7165 * "Enable Panel Fitter" does not seem to be required when page
7166 * flipping with a non-native mode, and worse causes a normal
7167 * modeset to fail.
7168 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7169 */
7170 pf = 0;
7171 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7172 intel_ring_emit(ring, pf | pipesrc);
7173 intel_ring_advance(ring);
7174 return 0;
7175
7176 err_unpin:
7177 intel_unpin_fb_obj(obj);
7178 err:
7179 return ret;
7180 }
7181
7182 /*
7183 * On gen7 we currently use the blit ring because (in early silicon at least)
7184 * the render ring doesn't give us interrpts for page flip completion, which
7185 * means clients will hang after the first flip is queued. Fortunately the
7186 * blit ring generates interrupts properly, so use it instead.
7187 */
7188 static int intel_gen7_queue_flip(struct drm_device *dev,
7189 struct drm_crtc *crtc,
7190 struct drm_framebuffer *fb,
7191 struct drm_i915_gem_object *obj)
7192 {
7193 struct drm_i915_private *dev_priv = dev->dev_private;
7194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7195 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7196 uint32_t plane_bit = 0;
7197 int ret;
7198
7199 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7200 if (ret)
7201 goto err;
7202
7203 switch(intel_crtc->plane) {
7204 case PLANE_A:
7205 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7206 break;
7207 case PLANE_B:
7208 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7209 break;
7210 case PLANE_C:
7211 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7212 break;
7213 default:
7214 WARN_ONCE(1, "unknown plane in flip command\n");
7215 ret = -ENODEV;
7216 goto err_unpin;
7217 }
7218
7219 ret = intel_ring_begin(ring, 4);
7220 if (ret)
7221 goto err_unpin;
7222
7223 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7224 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7225 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7226 intel_ring_emit(ring, (MI_NOOP));
7227 intel_ring_advance(ring);
7228 return 0;
7229
7230 err_unpin:
7231 intel_unpin_fb_obj(obj);
7232 err:
7233 return ret;
7234 }
7235
7236 static int intel_default_queue_flip(struct drm_device *dev,
7237 struct drm_crtc *crtc,
7238 struct drm_framebuffer *fb,
7239 struct drm_i915_gem_object *obj)
7240 {
7241 return -ENODEV;
7242 }
7243
7244 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7245 struct drm_framebuffer *fb,
7246 struct drm_pending_vblank_event *event)
7247 {
7248 struct drm_device *dev = crtc->dev;
7249 struct drm_i915_private *dev_priv = dev->dev_private;
7250 struct intel_framebuffer *intel_fb;
7251 struct drm_i915_gem_object *obj;
7252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7253 struct intel_unpin_work *work;
7254 unsigned long flags;
7255 int ret;
7256
7257 /* Can't change pixel format via MI display flips. */
7258 if (fb->pixel_format != crtc->fb->pixel_format)
7259 return -EINVAL;
7260
7261 /*
7262 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7263 * Note that pitch changes could also affect these register.
7264 */
7265 if (INTEL_INFO(dev)->gen > 3 &&
7266 (fb->offsets[0] != crtc->fb->offsets[0] ||
7267 fb->pitches[0] != crtc->fb->pitches[0]))
7268 return -EINVAL;
7269
7270 work = kzalloc(sizeof *work, GFP_KERNEL);
7271 if (work == NULL)
7272 return -ENOMEM;
7273
7274 work->event = event;
7275 work->dev = crtc->dev;
7276 intel_fb = to_intel_framebuffer(crtc->fb);
7277 work->old_fb_obj = intel_fb->obj;
7278 INIT_WORK(&work->work, intel_unpin_work_fn);
7279
7280 ret = drm_vblank_get(dev, intel_crtc->pipe);
7281 if (ret)
7282 goto free_work;
7283
7284 /* We borrow the event spin lock for protecting unpin_work */
7285 spin_lock_irqsave(&dev->event_lock, flags);
7286 if (intel_crtc->unpin_work) {
7287 spin_unlock_irqrestore(&dev->event_lock, flags);
7288 kfree(work);
7289 drm_vblank_put(dev, intel_crtc->pipe);
7290
7291 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7292 return -EBUSY;
7293 }
7294 intel_crtc->unpin_work = work;
7295 spin_unlock_irqrestore(&dev->event_lock, flags);
7296
7297 intel_fb = to_intel_framebuffer(fb);
7298 obj = intel_fb->obj;
7299
7300 ret = i915_mutex_lock_interruptible(dev);
7301 if (ret)
7302 goto cleanup;
7303
7304 /* Reference the objects for the scheduled work. */
7305 drm_gem_object_reference(&work->old_fb_obj->base);
7306 drm_gem_object_reference(&obj->base);
7307
7308 crtc->fb = fb;
7309
7310 work->pending_flip_obj = obj;
7311
7312 work->enable_stall_check = true;
7313
7314 /* Block clients from rendering to the new back buffer until
7315 * the flip occurs and the object is no longer visible.
7316 */
7317 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7318
7319 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7320 if (ret)
7321 goto cleanup_pending;
7322
7323 intel_disable_fbc(dev);
7324 intel_mark_fb_busy(obj);
7325 mutex_unlock(&dev->struct_mutex);
7326
7327 trace_i915_flip_request(intel_crtc->plane, obj);
7328
7329 return 0;
7330
7331 cleanup_pending:
7332 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
7333 drm_gem_object_unreference(&work->old_fb_obj->base);
7334 drm_gem_object_unreference(&obj->base);
7335 mutex_unlock(&dev->struct_mutex);
7336
7337 cleanup:
7338 spin_lock_irqsave(&dev->event_lock, flags);
7339 intel_crtc->unpin_work = NULL;
7340 spin_unlock_irqrestore(&dev->event_lock, flags);
7341
7342 drm_vblank_put(dev, intel_crtc->pipe);
7343 free_work:
7344 kfree(work);
7345
7346 return ret;
7347 }
7348
7349 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7350 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7351 .load_lut = intel_crtc_load_lut,
7352 .disable = intel_crtc_noop,
7353 };
7354
7355 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7356 {
7357 struct intel_encoder *other_encoder;
7358 struct drm_crtc *crtc = &encoder->new_crtc->base;
7359
7360 if (WARN_ON(!crtc))
7361 return false;
7362
7363 list_for_each_entry(other_encoder,
7364 &crtc->dev->mode_config.encoder_list,
7365 base.head) {
7366
7367 if (&other_encoder->new_crtc->base != crtc ||
7368 encoder == other_encoder)
7369 continue;
7370 else
7371 return true;
7372 }
7373
7374 return false;
7375 }
7376
7377 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7378 struct drm_crtc *crtc)
7379 {
7380 struct drm_device *dev;
7381 struct drm_crtc *tmp;
7382 int crtc_mask = 1;
7383
7384 WARN(!crtc, "checking null crtc?\n");
7385
7386 dev = crtc->dev;
7387
7388 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7389 if (tmp == crtc)
7390 break;
7391 crtc_mask <<= 1;
7392 }
7393
7394 if (encoder->possible_crtcs & crtc_mask)
7395 return true;
7396 return false;
7397 }
7398
7399 /**
7400 * intel_modeset_update_staged_output_state
7401 *
7402 * Updates the staged output configuration state, e.g. after we've read out the
7403 * current hw state.
7404 */
7405 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7406 {
7407 struct intel_encoder *encoder;
7408 struct intel_connector *connector;
7409
7410 list_for_each_entry(connector, &dev->mode_config.connector_list,
7411 base.head) {
7412 connector->new_encoder =
7413 to_intel_encoder(connector->base.encoder);
7414 }
7415
7416 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7417 base.head) {
7418 encoder->new_crtc =
7419 to_intel_crtc(encoder->base.crtc);
7420 }
7421 }
7422
7423 /**
7424 * intel_modeset_commit_output_state
7425 *
7426 * This function copies the stage display pipe configuration to the real one.
7427 */
7428 static void intel_modeset_commit_output_state(struct drm_device *dev)
7429 {
7430 struct intel_encoder *encoder;
7431 struct intel_connector *connector;
7432
7433 list_for_each_entry(connector, &dev->mode_config.connector_list,
7434 base.head) {
7435 connector->base.encoder = &connector->new_encoder->base;
7436 }
7437
7438 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7439 base.head) {
7440 encoder->base.crtc = &encoder->new_crtc->base;
7441 }
7442 }
7443
7444 static struct drm_display_mode *
7445 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7446 struct drm_display_mode *mode)
7447 {
7448 struct drm_device *dev = crtc->dev;
7449 struct drm_display_mode *adjusted_mode;
7450 struct drm_encoder_helper_funcs *encoder_funcs;
7451 struct intel_encoder *encoder;
7452
7453 adjusted_mode = drm_mode_duplicate(dev, mode);
7454 if (!adjusted_mode)
7455 return ERR_PTR(-ENOMEM);
7456
7457 /* Pass our mode to the connectors and the CRTC to give them a chance to
7458 * adjust it according to limitations or connector properties, and also
7459 * a chance to reject the mode entirely.
7460 */
7461 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7462 base.head) {
7463
7464 if (&encoder->new_crtc->base != crtc)
7465 continue;
7466 encoder_funcs = encoder->base.helper_private;
7467 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7468 adjusted_mode))) {
7469 DRM_DEBUG_KMS("Encoder fixup failed\n");
7470 goto fail;
7471 }
7472 }
7473
7474 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7475 DRM_DEBUG_KMS("CRTC fixup failed\n");
7476 goto fail;
7477 }
7478 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7479
7480 return adjusted_mode;
7481 fail:
7482 drm_mode_destroy(dev, adjusted_mode);
7483 return ERR_PTR(-EINVAL);
7484 }
7485
7486 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7487 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7488 static void
7489 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7490 unsigned *prepare_pipes, unsigned *disable_pipes)
7491 {
7492 struct intel_crtc *intel_crtc;
7493 struct drm_device *dev = crtc->dev;
7494 struct intel_encoder *encoder;
7495 struct intel_connector *connector;
7496 struct drm_crtc *tmp_crtc;
7497
7498 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7499
7500 /* Check which crtcs have changed outputs connected to them, these need
7501 * to be part of the prepare_pipes mask. We don't (yet) support global
7502 * modeset across multiple crtcs, so modeset_pipes will only have one
7503 * bit set at most. */
7504 list_for_each_entry(connector, &dev->mode_config.connector_list,
7505 base.head) {
7506 if (connector->base.encoder == &connector->new_encoder->base)
7507 continue;
7508
7509 if (connector->base.encoder) {
7510 tmp_crtc = connector->base.encoder->crtc;
7511
7512 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7513 }
7514
7515 if (connector->new_encoder)
7516 *prepare_pipes |=
7517 1 << connector->new_encoder->new_crtc->pipe;
7518 }
7519
7520 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7521 base.head) {
7522 if (encoder->base.crtc == &encoder->new_crtc->base)
7523 continue;
7524
7525 if (encoder->base.crtc) {
7526 tmp_crtc = encoder->base.crtc;
7527
7528 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7529 }
7530
7531 if (encoder->new_crtc)
7532 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7533 }
7534
7535 /* Check for any pipes that will be fully disabled ... */
7536 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7537 base.head) {
7538 bool used = false;
7539
7540 /* Don't try to disable disabled crtcs. */
7541 if (!intel_crtc->base.enabled)
7542 continue;
7543
7544 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7545 base.head) {
7546 if (encoder->new_crtc == intel_crtc)
7547 used = true;
7548 }
7549
7550 if (!used)
7551 *disable_pipes |= 1 << intel_crtc->pipe;
7552 }
7553
7554
7555 /* set_mode is also used to update properties on life display pipes. */
7556 intel_crtc = to_intel_crtc(crtc);
7557 if (crtc->enabled)
7558 *prepare_pipes |= 1 << intel_crtc->pipe;
7559
7560 /* We only support modeset on one single crtc, hence we need to do that
7561 * only for the passed in crtc iff we change anything else than just
7562 * disable crtcs.
7563 *
7564 * This is actually not true, to be fully compatible with the old crtc
7565 * helper we automatically disable _any_ output (i.e. doesn't need to be
7566 * connected to the crtc we're modesetting on) if it's disconnected.
7567 * Which is a rather nutty api (since changed the output configuration
7568 * without userspace's explicit request can lead to confusion), but
7569 * alas. Hence we currently need to modeset on all pipes we prepare. */
7570 if (*prepare_pipes)
7571 *modeset_pipes = *prepare_pipes;
7572
7573 /* ... and mask these out. */
7574 *modeset_pipes &= ~(*disable_pipes);
7575 *prepare_pipes &= ~(*disable_pipes);
7576 }
7577
7578 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7579 {
7580 struct drm_encoder *encoder;
7581 struct drm_device *dev = crtc->dev;
7582
7583 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7584 if (encoder->crtc == crtc)
7585 return true;
7586
7587 return false;
7588 }
7589
7590 static void
7591 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7592 {
7593 struct intel_encoder *intel_encoder;
7594 struct intel_crtc *intel_crtc;
7595 struct drm_connector *connector;
7596
7597 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7598 base.head) {
7599 if (!intel_encoder->base.crtc)
7600 continue;
7601
7602 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7603
7604 if (prepare_pipes & (1 << intel_crtc->pipe))
7605 intel_encoder->connectors_active = false;
7606 }
7607
7608 intel_modeset_commit_output_state(dev);
7609
7610 /* Update computed state. */
7611 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7612 base.head) {
7613 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7614 }
7615
7616 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7617 if (!connector->encoder || !connector->encoder->crtc)
7618 continue;
7619
7620 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7621
7622 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7623 struct drm_property *dpms_property =
7624 dev->mode_config.dpms_property;
7625
7626 connector->dpms = DRM_MODE_DPMS_ON;
7627 drm_connector_property_set_value(connector,
7628 dpms_property,
7629 DRM_MODE_DPMS_ON);
7630
7631 intel_encoder = to_intel_encoder(connector->encoder);
7632 intel_encoder->connectors_active = true;
7633 }
7634 }
7635
7636 }
7637
7638 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7639 list_for_each_entry((intel_crtc), \
7640 &(dev)->mode_config.crtc_list, \
7641 base.head) \
7642 if (mask & (1 <<(intel_crtc)->pipe)) \
7643
7644 void
7645 intel_modeset_check_state(struct drm_device *dev)
7646 {
7647 struct intel_crtc *crtc;
7648 struct intel_encoder *encoder;
7649 struct intel_connector *connector;
7650
7651 list_for_each_entry(connector, &dev->mode_config.connector_list,
7652 base.head) {
7653 /* This also checks the encoder/connector hw state with the
7654 * ->get_hw_state callbacks. */
7655 intel_connector_check_state(connector);
7656
7657 WARN(&connector->new_encoder->base != connector->base.encoder,
7658 "connector's staged encoder doesn't match current encoder\n");
7659 }
7660
7661 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7662 base.head) {
7663 bool enabled = false;
7664 bool active = false;
7665 enum pipe pipe, tracked_pipe;
7666
7667 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7668 encoder->base.base.id,
7669 drm_get_encoder_name(&encoder->base));
7670
7671 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7672 "encoder's stage crtc doesn't match current crtc\n");
7673 WARN(encoder->connectors_active && !encoder->base.crtc,
7674 "encoder's active_connectors set, but no crtc\n");
7675
7676 list_for_each_entry(connector, &dev->mode_config.connector_list,
7677 base.head) {
7678 if (connector->base.encoder != &encoder->base)
7679 continue;
7680 enabled = true;
7681 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7682 active = true;
7683 }
7684 WARN(!!encoder->base.crtc != enabled,
7685 "encoder's enabled state mismatch "
7686 "(expected %i, found %i)\n",
7687 !!encoder->base.crtc, enabled);
7688 WARN(active && !encoder->base.crtc,
7689 "active encoder with no crtc\n");
7690
7691 WARN(encoder->connectors_active != active,
7692 "encoder's computed active state doesn't match tracked active state "
7693 "(expected %i, found %i)\n", active, encoder->connectors_active);
7694
7695 active = encoder->get_hw_state(encoder, &pipe);
7696 WARN(active != encoder->connectors_active,
7697 "encoder's hw state doesn't match sw tracking "
7698 "(expected %i, found %i)\n",
7699 encoder->connectors_active, active);
7700
7701 if (!encoder->base.crtc)
7702 continue;
7703
7704 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7705 WARN(active && pipe != tracked_pipe,
7706 "active encoder's pipe doesn't match"
7707 "(expected %i, found %i)\n",
7708 tracked_pipe, pipe);
7709
7710 }
7711
7712 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7713 base.head) {
7714 bool enabled = false;
7715 bool active = false;
7716
7717 DRM_DEBUG_KMS("[CRTC:%d]\n",
7718 crtc->base.base.id);
7719
7720 WARN(crtc->active && !crtc->base.enabled,
7721 "active crtc, but not enabled in sw tracking\n");
7722
7723 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7724 base.head) {
7725 if (encoder->base.crtc != &crtc->base)
7726 continue;
7727 enabled = true;
7728 if (encoder->connectors_active)
7729 active = true;
7730 }
7731 WARN(active != crtc->active,
7732 "crtc's computed active state doesn't match tracked active state "
7733 "(expected %i, found %i)\n", active, crtc->active);
7734 WARN(enabled != crtc->base.enabled,
7735 "crtc's computed enabled state doesn't match tracked enabled state "
7736 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7737
7738 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7739 }
7740 }
7741
7742 bool intel_set_mode(struct drm_crtc *crtc,
7743 struct drm_display_mode *mode,
7744 int x, int y, struct drm_framebuffer *fb)
7745 {
7746 struct drm_device *dev = crtc->dev;
7747 drm_i915_private_t *dev_priv = dev->dev_private;
7748 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7749 struct intel_crtc *intel_crtc;
7750 unsigned disable_pipes, prepare_pipes, modeset_pipes;
7751 bool ret = true;
7752
7753 intel_modeset_affected_pipes(crtc, &modeset_pipes,
7754 &prepare_pipes, &disable_pipes);
7755
7756 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7757 modeset_pipes, prepare_pipes, disable_pipes);
7758
7759 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7760 intel_crtc_disable(&intel_crtc->base);
7761
7762 saved_hwmode = crtc->hwmode;
7763 saved_mode = crtc->mode;
7764
7765 /* Hack: Because we don't (yet) support global modeset on multiple
7766 * crtcs, we don't keep track of the new mode for more than one crtc.
7767 * Hence simply check whether any bit is set in modeset_pipes in all the
7768 * pieces of code that are not yet converted to deal with mutliple crtcs
7769 * changing their mode at the same time. */
7770 adjusted_mode = NULL;
7771 if (modeset_pipes) {
7772 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7773 if (IS_ERR(adjusted_mode)) {
7774 return false;
7775 }
7776 }
7777
7778 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7779 if (intel_crtc->base.enabled)
7780 dev_priv->display.crtc_disable(&intel_crtc->base);
7781 }
7782
7783 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7784 * to set it here already despite that we pass it down the callchain.
7785 */
7786 if (modeset_pipes)
7787 crtc->mode = *mode;
7788
7789 /* Only after disabling all output pipelines that will be changed can we
7790 * update the the output configuration. */
7791 intel_modeset_update_state(dev, prepare_pipes);
7792
7793 if (dev_priv->display.modeset_global_resources)
7794 dev_priv->display.modeset_global_resources(dev);
7795
7796 /* Set up the DPLL and any encoders state that needs to adjust or depend
7797 * on the DPLL.
7798 */
7799 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7800 ret = !intel_crtc_mode_set(&intel_crtc->base,
7801 mode, adjusted_mode,
7802 x, y, fb);
7803 if (!ret)
7804 goto done;
7805 }
7806
7807 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7808 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7809 dev_priv->display.crtc_enable(&intel_crtc->base);
7810
7811 if (modeset_pipes) {
7812 /* Store real post-adjustment hardware mode. */
7813 crtc->hwmode = *adjusted_mode;
7814
7815 /* Calculate and store various constants which
7816 * are later needed by vblank and swap-completion
7817 * timestamping. They are derived from true hwmode.
7818 */
7819 drm_calc_timestamping_constants(crtc);
7820 }
7821
7822 /* FIXME: add subpixel order */
7823 done:
7824 drm_mode_destroy(dev, adjusted_mode);
7825 if (!ret && crtc->enabled) {
7826 crtc->hwmode = saved_hwmode;
7827 crtc->mode = saved_mode;
7828 } else {
7829 intel_modeset_check_state(dev);
7830 }
7831
7832 return ret;
7833 }
7834
7835 #undef for_each_intel_crtc_masked
7836
7837 static void intel_set_config_free(struct intel_set_config *config)
7838 {
7839 if (!config)
7840 return;
7841
7842 kfree(config->save_connector_encoders);
7843 kfree(config->save_encoder_crtcs);
7844 kfree(config);
7845 }
7846
7847 static int intel_set_config_save_state(struct drm_device *dev,
7848 struct intel_set_config *config)
7849 {
7850 struct drm_encoder *encoder;
7851 struct drm_connector *connector;
7852 int count;
7853
7854 config->save_encoder_crtcs =
7855 kcalloc(dev->mode_config.num_encoder,
7856 sizeof(struct drm_crtc *), GFP_KERNEL);
7857 if (!config->save_encoder_crtcs)
7858 return -ENOMEM;
7859
7860 config->save_connector_encoders =
7861 kcalloc(dev->mode_config.num_connector,
7862 sizeof(struct drm_encoder *), GFP_KERNEL);
7863 if (!config->save_connector_encoders)
7864 return -ENOMEM;
7865
7866 /* Copy data. Note that driver private data is not affected.
7867 * Should anything bad happen only the expected state is
7868 * restored, not the drivers personal bookkeeping.
7869 */
7870 count = 0;
7871 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7872 config->save_encoder_crtcs[count++] = encoder->crtc;
7873 }
7874
7875 count = 0;
7876 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7877 config->save_connector_encoders[count++] = connector->encoder;
7878 }
7879
7880 return 0;
7881 }
7882
7883 static void intel_set_config_restore_state(struct drm_device *dev,
7884 struct intel_set_config *config)
7885 {
7886 struct intel_encoder *encoder;
7887 struct intel_connector *connector;
7888 int count;
7889
7890 count = 0;
7891 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7892 encoder->new_crtc =
7893 to_intel_crtc(config->save_encoder_crtcs[count++]);
7894 }
7895
7896 count = 0;
7897 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7898 connector->new_encoder =
7899 to_intel_encoder(config->save_connector_encoders[count++]);
7900 }
7901 }
7902
7903 static void
7904 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7905 struct intel_set_config *config)
7906 {
7907
7908 /* We should be able to check here if the fb has the same properties
7909 * and then just flip_or_move it */
7910 if (set->crtc->fb != set->fb) {
7911 /* If we have no fb then treat it as a full mode set */
7912 if (set->crtc->fb == NULL) {
7913 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7914 config->mode_changed = true;
7915 } else if (set->fb == NULL) {
7916 config->mode_changed = true;
7917 } else if (set->fb->depth != set->crtc->fb->depth) {
7918 config->mode_changed = true;
7919 } else if (set->fb->bits_per_pixel !=
7920 set->crtc->fb->bits_per_pixel) {
7921 config->mode_changed = true;
7922 } else
7923 config->fb_changed = true;
7924 }
7925
7926 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7927 config->fb_changed = true;
7928
7929 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7930 DRM_DEBUG_KMS("modes are different, full mode set\n");
7931 drm_mode_debug_printmodeline(&set->crtc->mode);
7932 drm_mode_debug_printmodeline(set->mode);
7933 config->mode_changed = true;
7934 }
7935 }
7936
7937 static int
7938 intel_modeset_stage_output_state(struct drm_device *dev,
7939 struct drm_mode_set *set,
7940 struct intel_set_config *config)
7941 {
7942 struct drm_crtc *new_crtc;
7943 struct intel_connector *connector;
7944 struct intel_encoder *encoder;
7945 int count, ro;
7946
7947 /* The upper layers ensure that we either disabl a crtc or have a list
7948 * of connectors. For paranoia, double-check this. */
7949 WARN_ON(!set->fb && (set->num_connectors != 0));
7950 WARN_ON(set->fb && (set->num_connectors == 0));
7951
7952 count = 0;
7953 list_for_each_entry(connector, &dev->mode_config.connector_list,
7954 base.head) {
7955 /* Otherwise traverse passed in connector list and get encoders
7956 * for them. */
7957 for (ro = 0; ro < set->num_connectors; ro++) {
7958 if (set->connectors[ro] == &connector->base) {
7959 connector->new_encoder = connector->encoder;
7960 break;
7961 }
7962 }
7963
7964 /* If we disable the crtc, disable all its connectors. Also, if
7965 * the connector is on the changing crtc but not on the new
7966 * connector list, disable it. */
7967 if ((!set->fb || ro == set->num_connectors) &&
7968 connector->base.encoder &&
7969 connector->base.encoder->crtc == set->crtc) {
7970 connector->new_encoder = NULL;
7971
7972 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7973 connector->base.base.id,
7974 drm_get_connector_name(&connector->base));
7975 }
7976
7977
7978 if (&connector->new_encoder->base != connector->base.encoder) {
7979 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7980 config->mode_changed = true;
7981 }
7982
7983 /* Disable all disconnected encoders. */
7984 if (connector->base.status == connector_status_disconnected)
7985 connector->new_encoder = NULL;
7986 }
7987 /* connector->new_encoder is now updated for all connectors. */
7988
7989 /* Update crtc of enabled connectors. */
7990 count = 0;
7991 list_for_each_entry(connector, &dev->mode_config.connector_list,
7992 base.head) {
7993 if (!connector->new_encoder)
7994 continue;
7995
7996 new_crtc = connector->new_encoder->base.crtc;
7997
7998 for (ro = 0; ro < set->num_connectors; ro++) {
7999 if (set->connectors[ro] == &connector->base)
8000 new_crtc = set->crtc;
8001 }
8002
8003 /* Make sure the new CRTC will work with the encoder */
8004 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8005 new_crtc)) {
8006 return -EINVAL;
8007 }
8008 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8009
8010 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8011 connector->base.base.id,
8012 drm_get_connector_name(&connector->base),
8013 new_crtc->base.id);
8014 }
8015
8016 /* Check for any encoders that needs to be disabled. */
8017 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8018 base.head) {
8019 list_for_each_entry(connector,
8020 &dev->mode_config.connector_list,
8021 base.head) {
8022 if (connector->new_encoder == encoder) {
8023 WARN_ON(!connector->new_encoder->new_crtc);
8024
8025 goto next_encoder;
8026 }
8027 }
8028 encoder->new_crtc = NULL;
8029 next_encoder:
8030 /* Only now check for crtc changes so we don't miss encoders
8031 * that will be disabled. */
8032 if (&encoder->new_crtc->base != encoder->base.crtc) {
8033 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8034 config->mode_changed = true;
8035 }
8036 }
8037 /* Now we've also updated encoder->new_crtc for all encoders. */
8038
8039 return 0;
8040 }
8041
8042 static int intel_crtc_set_config(struct drm_mode_set *set)
8043 {
8044 struct drm_device *dev;
8045 struct drm_mode_set save_set;
8046 struct intel_set_config *config;
8047 int ret;
8048
8049 BUG_ON(!set);
8050 BUG_ON(!set->crtc);
8051 BUG_ON(!set->crtc->helper_private);
8052
8053 if (!set->mode)
8054 set->fb = NULL;
8055
8056 /* The fb helper likes to play gross jokes with ->mode_set_config.
8057 * Unfortunately the crtc helper doesn't do much at all for this case,
8058 * so we have to cope with this madness until the fb helper is fixed up. */
8059 if (set->fb && set->num_connectors == 0)
8060 return 0;
8061
8062 if (set->fb) {
8063 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8064 set->crtc->base.id, set->fb->base.id,
8065 (int)set->num_connectors, set->x, set->y);
8066 } else {
8067 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8068 }
8069
8070 dev = set->crtc->dev;
8071
8072 ret = -ENOMEM;
8073 config = kzalloc(sizeof(*config), GFP_KERNEL);
8074 if (!config)
8075 goto out_config;
8076
8077 ret = intel_set_config_save_state(dev, config);
8078 if (ret)
8079 goto out_config;
8080
8081 save_set.crtc = set->crtc;
8082 save_set.mode = &set->crtc->mode;
8083 save_set.x = set->crtc->x;
8084 save_set.y = set->crtc->y;
8085 save_set.fb = set->crtc->fb;
8086
8087 /* Compute whether we need a full modeset, only an fb base update or no
8088 * change at all. In the future we might also check whether only the
8089 * mode changed, e.g. for LVDS where we only change the panel fitter in
8090 * such cases. */
8091 intel_set_config_compute_mode_changes(set, config);
8092
8093 ret = intel_modeset_stage_output_state(dev, set, config);
8094 if (ret)
8095 goto fail;
8096
8097 if (config->mode_changed) {
8098 if (set->mode) {
8099 DRM_DEBUG_KMS("attempting to set mode from"
8100 " userspace\n");
8101 drm_mode_debug_printmodeline(set->mode);
8102 }
8103
8104 if (!intel_set_mode(set->crtc, set->mode,
8105 set->x, set->y, set->fb)) {
8106 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8107 set->crtc->base.id);
8108 ret = -EINVAL;
8109 goto fail;
8110 }
8111 } else if (config->fb_changed) {
8112 ret = intel_pipe_set_base(set->crtc,
8113 set->x, set->y, set->fb);
8114 }
8115
8116 intel_set_config_free(config);
8117
8118 return 0;
8119
8120 fail:
8121 intel_set_config_restore_state(dev, config);
8122
8123 /* Try to restore the config */
8124 if (config->mode_changed &&
8125 !intel_set_mode(save_set.crtc, save_set.mode,
8126 save_set.x, save_set.y, save_set.fb))
8127 DRM_ERROR("failed to restore config after modeset failure\n");
8128
8129 out_config:
8130 intel_set_config_free(config);
8131 return ret;
8132 }
8133
8134 static const struct drm_crtc_funcs intel_crtc_funcs = {
8135 .cursor_set = intel_crtc_cursor_set,
8136 .cursor_move = intel_crtc_cursor_move,
8137 .gamma_set = intel_crtc_gamma_set,
8138 .set_config = intel_crtc_set_config,
8139 .destroy = intel_crtc_destroy,
8140 .page_flip = intel_crtc_page_flip,
8141 };
8142
8143 static void intel_cpu_pll_init(struct drm_device *dev)
8144 {
8145 if (IS_HASWELL(dev))
8146 intel_ddi_pll_init(dev);
8147 }
8148
8149 static void intel_pch_pll_init(struct drm_device *dev)
8150 {
8151 drm_i915_private_t *dev_priv = dev->dev_private;
8152 int i;
8153
8154 if (dev_priv->num_pch_pll == 0) {
8155 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8156 return;
8157 }
8158
8159 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8160 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8161 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8162 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8163 }
8164 }
8165
8166 static void intel_crtc_init(struct drm_device *dev, int pipe)
8167 {
8168 drm_i915_private_t *dev_priv = dev->dev_private;
8169 struct intel_crtc *intel_crtc;
8170 int i;
8171
8172 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8173 if (intel_crtc == NULL)
8174 return;
8175
8176 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8177
8178 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8179 for (i = 0; i < 256; i++) {
8180 intel_crtc->lut_r[i] = i;
8181 intel_crtc->lut_g[i] = i;
8182 intel_crtc->lut_b[i] = i;
8183 }
8184
8185 /* Swap pipes & planes for FBC on pre-965 */
8186 intel_crtc->pipe = pipe;
8187 intel_crtc->plane = pipe;
8188 intel_crtc->cpu_transcoder = pipe;
8189 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8190 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8191 intel_crtc->plane = !pipe;
8192 }
8193
8194 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8195 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8196 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8197 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8198
8199 intel_crtc->bpp = 24; /* default for pre-Ironlake */
8200
8201 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8202 }
8203
8204 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8205 struct drm_file *file)
8206 {
8207 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8208 struct drm_mode_object *drmmode_obj;
8209 struct intel_crtc *crtc;
8210
8211 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8212 return -ENODEV;
8213
8214 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8215 DRM_MODE_OBJECT_CRTC);
8216
8217 if (!drmmode_obj) {
8218 DRM_ERROR("no such CRTC id\n");
8219 return -EINVAL;
8220 }
8221
8222 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8223 pipe_from_crtc_id->pipe = crtc->pipe;
8224
8225 return 0;
8226 }
8227
8228 static int intel_encoder_clones(struct intel_encoder *encoder)
8229 {
8230 struct drm_device *dev = encoder->base.dev;
8231 struct intel_encoder *source_encoder;
8232 int index_mask = 0;
8233 int entry = 0;
8234
8235 list_for_each_entry(source_encoder,
8236 &dev->mode_config.encoder_list, base.head) {
8237
8238 if (encoder == source_encoder)
8239 index_mask |= (1 << entry);
8240
8241 /* Intel hw has only one MUX where enocoders could be cloned. */
8242 if (encoder->cloneable && source_encoder->cloneable)
8243 index_mask |= (1 << entry);
8244
8245 entry++;
8246 }
8247
8248 return index_mask;
8249 }
8250
8251 static bool has_edp_a(struct drm_device *dev)
8252 {
8253 struct drm_i915_private *dev_priv = dev->dev_private;
8254
8255 if (!IS_MOBILE(dev))
8256 return false;
8257
8258 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8259 return false;
8260
8261 if (IS_GEN5(dev) &&
8262 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8263 return false;
8264
8265 return true;
8266 }
8267
8268 static void intel_setup_outputs(struct drm_device *dev)
8269 {
8270 struct drm_i915_private *dev_priv = dev->dev_private;
8271 struct intel_encoder *encoder;
8272 bool dpd_is_edp = false;
8273 bool has_lvds;
8274
8275 has_lvds = intel_lvds_init(dev);
8276 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8277 /* disable the panel fitter on everything but LVDS */
8278 I915_WRITE(PFIT_CONTROL, 0);
8279 }
8280
8281 intel_crt_init(dev);
8282
8283 if (IS_HASWELL(dev)) {
8284 int found;
8285
8286 /* Haswell uses DDI functions to detect digital outputs */
8287 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8288 /* DDI A only supports eDP */
8289 if (found)
8290 intel_ddi_init(dev, PORT_A);
8291
8292 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8293 * register */
8294 found = I915_READ(SFUSE_STRAP);
8295
8296 if (found & SFUSE_STRAP_DDIB_DETECTED)
8297 intel_ddi_init(dev, PORT_B);
8298 if (found & SFUSE_STRAP_DDIC_DETECTED)
8299 intel_ddi_init(dev, PORT_C);
8300 if (found & SFUSE_STRAP_DDID_DETECTED)
8301 intel_ddi_init(dev, PORT_D);
8302 } else if (HAS_PCH_SPLIT(dev)) {
8303 int found;
8304 dpd_is_edp = intel_dpd_is_edp(dev);
8305
8306 if (has_edp_a(dev))
8307 intel_dp_init(dev, DP_A, PORT_A);
8308
8309 if (I915_READ(HDMIB) & PORT_DETECTED) {
8310 /* PCH SDVOB multiplex with HDMIB */
8311 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8312 if (!found)
8313 intel_hdmi_init(dev, HDMIB, PORT_B);
8314 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8315 intel_dp_init(dev, PCH_DP_B, PORT_B);
8316 }
8317
8318 if (I915_READ(HDMIC) & PORT_DETECTED)
8319 intel_hdmi_init(dev, HDMIC, PORT_C);
8320
8321 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8322 intel_hdmi_init(dev, HDMID, PORT_D);
8323
8324 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8325 intel_dp_init(dev, PCH_DP_C, PORT_C);
8326
8327 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8328 intel_dp_init(dev, PCH_DP_D, PORT_D);
8329 } else if (IS_VALLEYVIEW(dev)) {
8330 int found;
8331
8332 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8333 if (I915_READ(DP_C) & DP_DETECTED)
8334 intel_dp_init(dev, DP_C, PORT_C);
8335
8336 if (I915_READ(SDVOB) & PORT_DETECTED) {
8337 /* SDVOB multiplex with HDMIB */
8338 found = intel_sdvo_init(dev, SDVOB, true);
8339 if (!found)
8340 intel_hdmi_init(dev, SDVOB, PORT_B);
8341 if (!found && (I915_READ(DP_B) & DP_DETECTED))
8342 intel_dp_init(dev, DP_B, PORT_B);
8343 }
8344
8345 if (I915_READ(SDVOC) & PORT_DETECTED)
8346 intel_hdmi_init(dev, SDVOC, PORT_C);
8347
8348 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8349 bool found = false;
8350
8351 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8352 DRM_DEBUG_KMS("probing SDVOB\n");
8353 found = intel_sdvo_init(dev, SDVOB, true);
8354 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8355 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8356 intel_hdmi_init(dev, SDVOB, PORT_B);
8357 }
8358
8359 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8360 DRM_DEBUG_KMS("probing DP_B\n");
8361 intel_dp_init(dev, DP_B, PORT_B);
8362 }
8363 }
8364
8365 /* Before G4X SDVOC doesn't have its own detect register */
8366
8367 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8368 DRM_DEBUG_KMS("probing SDVOC\n");
8369 found = intel_sdvo_init(dev, SDVOC, false);
8370 }
8371
8372 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8373
8374 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8375 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8376 intel_hdmi_init(dev, SDVOC, PORT_C);
8377 }
8378 if (SUPPORTS_INTEGRATED_DP(dev)) {
8379 DRM_DEBUG_KMS("probing DP_C\n");
8380 intel_dp_init(dev, DP_C, PORT_C);
8381 }
8382 }
8383
8384 if (SUPPORTS_INTEGRATED_DP(dev) &&
8385 (I915_READ(DP_D) & DP_DETECTED)) {
8386 DRM_DEBUG_KMS("probing DP_D\n");
8387 intel_dp_init(dev, DP_D, PORT_D);
8388 }
8389 } else if (IS_GEN2(dev))
8390 intel_dvo_init(dev);
8391
8392 if (SUPPORTS_TV(dev))
8393 intel_tv_init(dev);
8394
8395 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8396 encoder->base.possible_crtcs = encoder->crtc_mask;
8397 encoder->base.possible_clones =
8398 intel_encoder_clones(encoder);
8399 }
8400
8401 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8402 ironlake_init_pch_refclk(dev);
8403
8404 drm_helper_move_panel_connectors_to_head(dev);
8405 }
8406
8407 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8408 {
8409 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8410
8411 drm_framebuffer_cleanup(fb);
8412 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8413
8414 kfree(intel_fb);
8415 }
8416
8417 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8418 struct drm_file *file,
8419 unsigned int *handle)
8420 {
8421 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8422 struct drm_i915_gem_object *obj = intel_fb->obj;
8423
8424 return drm_gem_handle_create(file, &obj->base, handle);
8425 }
8426
8427 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8428 .destroy = intel_user_framebuffer_destroy,
8429 .create_handle = intel_user_framebuffer_create_handle,
8430 };
8431
8432 int intel_framebuffer_init(struct drm_device *dev,
8433 struct intel_framebuffer *intel_fb,
8434 struct drm_mode_fb_cmd2 *mode_cmd,
8435 struct drm_i915_gem_object *obj)
8436 {
8437 int ret;
8438
8439 if (obj->tiling_mode == I915_TILING_Y)
8440 return -EINVAL;
8441
8442 if (mode_cmd->pitches[0] & 63)
8443 return -EINVAL;
8444
8445 /* FIXME <= Gen4 stride limits are bit unclear */
8446 if (mode_cmd->pitches[0] > 32768)
8447 return -EINVAL;
8448
8449 if (obj->tiling_mode != I915_TILING_NONE &&
8450 mode_cmd->pitches[0] != obj->stride)
8451 return -EINVAL;
8452
8453 /* Reject formats not supported by any plane early. */
8454 switch (mode_cmd->pixel_format) {
8455 case DRM_FORMAT_C8:
8456 case DRM_FORMAT_RGB565:
8457 case DRM_FORMAT_XRGB8888:
8458 case DRM_FORMAT_ARGB8888:
8459 break;
8460 case DRM_FORMAT_XRGB1555:
8461 case DRM_FORMAT_ARGB1555:
8462 if (INTEL_INFO(dev)->gen > 3)
8463 return -EINVAL;
8464 break;
8465 case DRM_FORMAT_XBGR8888:
8466 case DRM_FORMAT_ABGR8888:
8467 case DRM_FORMAT_XRGB2101010:
8468 case DRM_FORMAT_ARGB2101010:
8469 case DRM_FORMAT_XBGR2101010:
8470 case DRM_FORMAT_ABGR2101010:
8471 if (INTEL_INFO(dev)->gen < 4)
8472 return -EINVAL;
8473 break;
8474 case DRM_FORMAT_YUYV:
8475 case DRM_FORMAT_UYVY:
8476 case DRM_FORMAT_YVYU:
8477 case DRM_FORMAT_VYUY:
8478 if (INTEL_INFO(dev)->gen < 6)
8479 return -EINVAL;
8480 break;
8481 default:
8482 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8483 return -EINVAL;
8484 }
8485
8486 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8487 if (mode_cmd->offsets[0] != 0)
8488 return -EINVAL;
8489
8490 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8491 if (ret) {
8492 DRM_ERROR("framebuffer init failed %d\n", ret);
8493 return ret;
8494 }
8495
8496 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8497 intel_fb->obj = obj;
8498 return 0;
8499 }
8500
8501 static struct drm_framebuffer *
8502 intel_user_framebuffer_create(struct drm_device *dev,
8503 struct drm_file *filp,
8504 struct drm_mode_fb_cmd2 *mode_cmd)
8505 {
8506 struct drm_i915_gem_object *obj;
8507
8508 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8509 mode_cmd->handles[0]));
8510 if (&obj->base == NULL)
8511 return ERR_PTR(-ENOENT);
8512
8513 return intel_framebuffer_create(dev, mode_cmd, obj);
8514 }
8515
8516 static const struct drm_mode_config_funcs intel_mode_funcs = {
8517 .fb_create = intel_user_framebuffer_create,
8518 .output_poll_changed = intel_fb_output_poll_changed,
8519 };
8520
8521 /* Set up chip specific display functions */
8522 static void intel_init_display(struct drm_device *dev)
8523 {
8524 struct drm_i915_private *dev_priv = dev->dev_private;
8525
8526 /* We always want a DPMS function */
8527 if (IS_HASWELL(dev)) {
8528 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8529 dev_priv->display.crtc_enable = haswell_crtc_enable;
8530 dev_priv->display.crtc_disable = haswell_crtc_disable;
8531 dev_priv->display.off = haswell_crtc_off;
8532 dev_priv->display.update_plane = ironlake_update_plane;
8533 } else if (HAS_PCH_SPLIT(dev)) {
8534 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8535 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8536 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8537 dev_priv->display.off = ironlake_crtc_off;
8538 dev_priv->display.update_plane = ironlake_update_plane;
8539 } else {
8540 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8541 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8542 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8543 dev_priv->display.off = i9xx_crtc_off;
8544 dev_priv->display.update_plane = i9xx_update_plane;
8545 }
8546
8547 /* Returns the core display clock speed */
8548 if (IS_VALLEYVIEW(dev))
8549 dev_priv->display.get_display_clock_speed =
8550 valleyview_get_display_clock_speed;
8551 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8552 dev_priv->display.get_display_clock_speed =
8553 i945_get_display_clock_speed;
8554 else if (IS_I915G(dev))
8555 dev_priv->display.get_display_clock_speed =
8556 i915_get_display_clock_speed;
8557 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8558 dev_priv->display.get_display_clock_speed =
8559 i9xx_misc_get_display_clock_speed;
8560 else if (IS_I915GM(dev))
8561 dev_priv->display.get_display_clock_speed =
8562 i915gm_get_display_clock_speed;
8563 else if (IS_I865G(dev))
8564 dev_priv->display.get_display_clock_speed =
8565 i865_get_display_clock_speed;
8566 else if (IS_I85X(dev))
8567 dev_priv->display.get_display_clock_speed =
8568 i855_get_display_clock_speed;
8569 else /* 852, 830 */
8570 dev_priv->display.get_display_clock_speed =
8571 i830_get_display_clock_speed;
8572
8573 if (HAS_PCH_SPLIT(dev)) {
8574 if (IS_GEN5(dev)) {
8575 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8576 dev_priv->display.write_eld = ironlake_write_eld;
8577 } else if (IS_GEN6(dev)) {
8578 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8579 dev_priv->display.write_eld = ironlake_write_eld;
8580 } else if (IS_IVYBRIDGE(dev)) {
8581 /* FIXME: detect B0+ stepping and use auto training */
8582 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8583 dev_priv->display.write_eld = ironlake_write_eld;
8584 dev_priv->display.modeset_global_resources =
8585 ivb_modeset_global_resources;
8586 } else if (IS_HASWELL(dev)) {
8587 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8588 dev_priv->display.write_eld = haswell_write_eld;
8589 } else
8590 dev_priv->display.update_wm = NULL;
8591 } else if (IS_G4X(dev)) {
8592 dev_priv->display.write_eld = g4x_write_eld;
8593 }
8594
8595 /* Default just returns -ENODEV to indicate unsupported */
8596 dev_priv->display.queue_flip = intel_default_queue_flip;
8597
8598 switch (INTEL_INFO(dev)->gen) {
8599 case 2:
8600 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8601 break;
8602
8603 case 3:
8604 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8605 break;
8606
8607 case 4:
8608 case 5:
8609 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8610 break;
8611
8612 case 6:
8613 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8614 break;
8615 case 7:
8616 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8617 break;
8618 }
8619 }
8620
8621 /*
8622 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8623 * resume, or other times. This quirk makes sure that's the case for
8624 * affected systems.
8625 */
8626 static void quirk_pipea_force(struct drm_device *dev)
8627 {
8628 struct drm_i915_private *dev_priv = dev->dev_private;
8629
8630 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8631 DRM_INFO("applying pipe a force quirk\n");
8632 }
8633
8634 /*
8635 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8636 */
8637 static void quirk_ssc_force_disable(struct drm_device *dev)
8638 {
8639 struct drm_i915_private *dev_priv = dev->dev_private;
8640 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8641 DRM_INFO("applying lvds SSC disable quirk\n");
8642 }
8643
8644 /*
8645 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8646 * brightness value
8647 */
8648 static void quirk_invert_brightness(struct drm_device *dev)
8649 {
8650 struct drm_i915_private *dev_priv = dev->dev_private;
8651 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8652 DRM_INFO("applying inverted panel brightness quirk\n");
8653 }
8654
8655 struct intel_quirk {
8656 int device;
8657 int subsystem_vendor;
8658 int subsystem_device;
8659 void (*hook)(struct drm_device *dev);
8660 };
8661
8662 static struct intel_quirk intel_quirks[] = {
8663 /* HP Mini needs pipe A force quirk (LP: #322104) */
8664 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8665
8666 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8667 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8668
8669 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8670 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8671
8672 /* 830/845 need to leave pipe A & dpll A up */
8673 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8674 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8675
8676 /* Lenovo U160 cannot use SSC on LVDS */
8677 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8678
8679 /* Sony Vaio Y cannot use SSC on LVDS */
8680 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8681
8682 /* Acer Aspire 5734Z must invert backlight brightness */
8683 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8684 };
8685
8686 static void intel_init_quirks(struct drm_device *dev)
8687 {
8688 struct pci_dev *d = dev->pdev;
8689 int i;
8690
8691 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8692 struct intel_quirk *q = &intel_quirks[i];
8693
8694 if (d->device == q->device &&
8695 (d->subsystem_vendor == q->subsystem_vendor ||
8696 q->subsystem_vendor == PCI_ANY_ID) &&
8697 (d->subsystem_device == q->subsystem_device ||
8698 q->subsystem_device == PCI_ANY_ID))
8699 q->hook(dev);
8700 }
8701 }
8702
8703 /* Disable the VGA plane that we never use */
8704 static void i915_disable_vga(struct drm_device *dev)
8705 {
8706 struct drm_i915_private *dev_priv = dev->dev_private;
8707 u8 sr1;
8708 u32 vga_reg;
8709
8710 if (HAS_PCH_SPLIT(dev))
8711 vga_reg = CPU_VGACNTRL;
8712 else
8713 vga_reg = VGACNTRL;
8714
8715 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8716 outb(SR01, VGA_SR_INDEX);
8717 sr1 = inb(VGA_SR_DATA);
8718 outb(sr1 | 1<<5, VGA_SR_DATA);
8719 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8720 udelay(300);
8721
8722 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8723 POSTING_READ(vga_reg);
8724 }
8725
8726 void intel_modeset_init_hw(struct drm_device *dev)
8727 {
8728 /* We attempt to init the necessary power wells early in the initialization
8729 * time, so the subsystems that expect power to be enabled can work.
8730 */
8731 intel_init_power_wells(dev);
8732
8733 intel_prepare_ddi(dev);
8734
8735 intel_init_clock_gating(dev);
8736
8737 mutex_lock(&dev->struct_mutex);
8738 intel_enable_gt_powersave(dev);
8739 mutex_unlock(&dev->struct_mutex);
8740 }
8741
8742 void intel_modeset_init(struct drm_device *dev)
8743 {
8744 struct drm_i915_private *dev_priv = dev->dev_private;
8745 int i, ret;
8746
8747 drm_mode_config_init(dev);
8748
8749 dev->mode_config.min_width = 0;
8750 dev->mode_config.min_height = 0;
8751
8752 dev->mode_config.preferred_depth = 24;
8753 dev->mode_config.prefer_shadow = 1;
8754
8755 dev->mode_config.funcs = &intel_mode_funcs;
8756
8757 intel_init_quirks(dev);
8758
8759 intel_init_pm(dev);
8760
8761 intel_init_display(dev);
8762
8763 if (IS_GEN2(dev)) {
8764 dev->mode_config.max_width = 2048;
8765 dev->mode_config.max_height = 2048;
8766 } else if (IS_GEN3(dev)) {
8767 dev->mode_config.max_width = 4096;
8768 dev->mode_config.max_height = 4096;
8769 } else {
8770 dev->mode_config.max_width = 8192;
8771 dev->mode_config.max_height = 8192;
8772 }
8773 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8774
8775 DRM_DEBUG_KMS("%d display pipe%s available.\n",
8776 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8777
8778 for (i = 0; i < dev_priv->num_pipe; i++) {
8779 intel_crtc_init(dev, i);
8780 ret = intel_plane_init(dev, i);
8781 if (ret)
8782 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8783 }
8784
8785 intel_cpu_pll_init(dev);
8786 intel_pch_pll_init(dev);
8787
8788 /* Just disable it once at startup */
8789 i915_disable_vga(dev);
8790 intel_setup_outputs(dev);
8791 }
8792
8793 static void
8794 intel_connector_break_all_links(struct intel_connector *connector)
8795 {
8796 connector->base.dpms = DRM_MODE_DPMS_OFF;
8797 connector->base.encoder = NULL;
8798 connector->encoder->connectors_active = false;
8799 connector->encoder->base.crtc = NULL;
8800 }
8801
8802 static void intel_enable_pipe_a(struct drm_device *dev)
8803 {
8804 struct intel_connector *connector;
8805 struct drm_connector *crt = NULL;
8806 struct intel_load_detect_pipe load_detect_temp;
8807
8808 /* We can't just switch on the pipe A, we need to set things up with a
8809 * proper mode and output configuration. As a gross hack, enable pipe A
8810 * by enabling the load detect pipe once. */
8811 list_for_each_entry(connector,
8812 &dev->mode_config.connector_list,
8813 base.head) {
8814 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8815 crt = &connector->base;
8816 break;
8817 }
8818 }
8819
8820 if (!crt)
8821 return;
8822
8823 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8824 intel_release_load_detect_pipe(crt, &load_detect_temp);
8825
8826
8827 }
8828
8829 static bool
8830 intel_check_plane_mapping(struct intel_crtc *crtc)
8831 {
8832 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8833 u32 reg, val;
8834
8835 if (dev_priv->num_pipe == 1)
8836 return true;
8837
8838 reg = DSPCNTR(!crtc->plane);
8839 val = I915_READ(reg);
8840
8841 if ((val & DISPLAY_PLANE_ENABLE) &&
8842 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8843 return false;
8844
8845 return true;
8846 }
8847
8848 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8849 {
8850 struct drm_device *dev = crtc->base.dev;
8851 struct drm_i915_private *dev_priv = dev->dev_private;
8852 u32 reg;
8853
8854 /* Clear any frame start delays used for debugging left by the BIOS */
8855 reg = PIPECONF(crtc->cpu_transcoder);
8856 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8857
8858 /* We need to sanitize the plane -> pipe mapping first because this will
8859 * disable the crtc (and hence change the state) if it is wrong. Note
8860 * that gen4+ has a fixed plane -> pipe mapping. */
8861 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8862 struct intel_connector *connector;
8863 bool plane;
8864
8865 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8866 crtc->base.base.id);
8867
8868 /* Pipe has the wrong plane attached and the plane is active.
8869 * Temporarily change the plane mapping and disable everything
8870 * ... */
8871 plane = crtc->plane;
8872 crtc->plane = !plane;
8873 dev_priv->display.crtc_disable(&crtc->base);
8874 crtc->plane = plane;
8875
8876 /* ... and break all links. */
8877 list_for_each_entry(connector, &dev->mode_config.connector_list,
8878 base.head) {
8879 if (connector->encoder->base.crtc != &crtc->base)
8880 continue;
8881
8882 intel_connector_break_all_links(connector);
8883 }
8884
8885 WARN_ON(crtc->active);
8886 crtc->base.enabled = false;
8887 }
8888
8889 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8890 crtc->pipe == PIPE_A && !crtc->active) {
8891 /* BIOS forgot to enable pipe A, this mostly happens after
8892 * resume. Force-enable the pipe to fix this, the update_dpms
8893 * call below we restore the pipe to the right state, but leave
8894 * the required bits on. */
8895 intel_enable_pipe_a(dev);
8896 }
8897
8898 /* Adjust the state of the output pipe according to whether we
8899 * have active connectors/encoders. */
8900 intel_crtc_update_dpms(&crtc->base);
8901
8902 if (crtc->active != crtc->base.enabled) {
8903 struct intel_encoder *encoder;
8904
8905 /* This can happen either due to bugs in the get_hw_state
8906 * functions or because the pipe is force-enabled due to the
8907 * pipe A quirk. */
8908 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8909 crtc->base.base.id,
8910 crtc->base.enabled ? "enabled" : "disabled",
8911 crtc->active ? "enabled" : "disabled");
8912
8913 crtc->base.enabled = crtc->active;
8914
8915 /* Because we only establish the connector -> encoder ->
8916 * crtc links if something is active, this means the
8917 * crtc is now deactivated. Break the links. connector
8918 * -> encoder links are only establish when things are
8919 * actually up, hence no need to break them. */
8920 WARN_ON(crtc->active);
8921
8922 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8923 WARN_ON(encoder->connectors_active);
8924 encoder->base.crtc = NULL;
8925 }
8926 }
8927 }
8928
8929 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8930 {
8931 struct intel_connector *connector;
8932 struct drm_device *dev = encoder->base.dev;
8933
8934 /* We need to check both for a crtc link (meaning that the
8935 * encoder is active and trying to read from a pipe) and the
8936 * pipe itself being active. */
8937 bool has_active_crtc = encoder->base.crtc &&
8938 to_intel_crtc(encoder->base.crtc)->active;
8939
8940 if (encoder->connectors_active && !has_active_crtc) {
8941 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8942 encoder->base.base.id,
8943 drm_get_encoder_name(&encoder->base));
8944
8945 /* Connector is active, but has no active pipe. This is
8946 * fallout from our resume register restoring. Disable
8947 * the encoder manually again. */
8948 if (encoder->base.crtc) {
8949 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8950 encoder->base.base.id,
8951 drm_get_encoder_name(&encoder->base));
8952 encoder->disable(encoder);
8953 }
8954
8955 /* Inconsistent output/port/pipe state happens presumably due to
8956 * a bug in one of the get_hw_state functions. Or someplace else
8957 * in our code, like the register restore mess on resume. Clamp
8958 * things to off as a safer default. */
8959 list_for_each_entry(connector,
8960 &dev->mode_config.connector_list,
8961 base.head) {
8962 if (connector->encoder != encoder)
8963 continue;
8964
8965 intel_connector_break_all_links(connector);
8966 }
8967 }
8968 /* Enabled encoders without active connectors will be fixed in
8969 * the crtc fixup. */
8970 }
8971
8972 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8973 * and i915 state tracking structures. */
8974 void intel_modeset_setup_hw_state(struct drm_device *dev)
8975 {
8976 struct drm_i915_private *dev_priv = dev->dev_private;
8977 enum pipe pipe;
8978 u32 tmp;
8979 struct intel_crtc *crtc;
8980 struct intel_encoder *encoder;
8981 struct intel_connector *connector;
8982
8983 if (IS_HASWELL(dev)) {
8984 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8985
8986 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8987 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8988 case TRANS_DDI_EDP_INPUT_A_ON:
8989 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8990 pipe = PIPE_A;
8991 break;
8992 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8993 pipe = PIPE_B;
8994 break;
8995 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8996 pipe = PIPE_C;
8997 break;
8998 }
8999
9000 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9001 crtc->cpu_transcoder = TRANSCODER_EDP;
9002
9003 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9004 pipe_name(pipe));
9005 }
9006 }
9007
9008 for_each_pipe(pipe) {
9009 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9010
9011 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
9012 if (tmp & PIPECONF_ENABLE)
9013 crtc->active = true;
9014 else
9015 crtc->active = false;
9016
9017 crtc->base.enabled = crtc->active;
9018
9019 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9020 crtc->base.base.id,
9021 crtc->active ? "enabled" : "disabled");
9022 }
9023
9024 if (IS_HASWELL(dev))
9025 intel_ddi_setup_hw_pll_state(dev);
9026
9027 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9028 base.head) {
9029 pipe = 0;
9030
9031 if (encoder->get_hw_state(encoder, &pipe)) {
9032 encoder->base.crtc =
9033 dev_priv->pipe_to_crtc_mapping[pipe];
9034 } else {
9035 encoder->base.crtc = NULL;
9036 }
9037
9038 encoder->connectors_active = false;
9039 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9040 encoder->base.base.id,
9041 drm_get_encoder_name(&encoder->base),
9042 encoder->base.crtc ? "enabled" : "disabled",
9043 pipe);
9044 }
9045
9046 list_for_each_entry(connector, &dev->mode_config.connector_list,
9047 base.head) {
9048 if (connector->get_hw_state(connector)) {
9049 connector->base.dpms = DRM_MODE_DPMS_ON;
9050 connector->encoder->connectors_active = true;
9051 connector->base.encoder = &connector->encoder->base;
9052 } else {
9053 connector->base.dpms = DRM_MODE_DPMS_OFF;
9054 connector->base.encoder = NULL;
9055 }
9056 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9057 connector->base.base.id,
9058 drm_get_connector_name(&connector->base),
9059 connector->base.encoder ? "enabled" : "disabled");
9060 }
9061
9062 /* HW state is read out, now we need to sanitize this mess. */
9063 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9064 base.head) {
9065 intel_sanitize_encoder(encoder);
9066 }
9067
9068 for_each_pipe(pipe) {
9069 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9070 intel_sanitize_crtc(crtc);
9071 }
9072
9073 intel_modeset_update_staged_output_state(dev);
9074
9075 intel_modeset_check_state(dev);
9076
9077 drm_mode_config_reset(dev);
9078 }
9079
9080 void intel_modeset_gem_init(struct drm_device *dev)
9081 {
9082 intel_modeset_init_hw(dev);
9083
9084 intel_setup_overlay(dev);
9085
9086 intel_modeset_setup_hw_state(dev);
9087 }
9088
9089 void intel_modeset_cleanup(struct drm_device *dev)
9090 {
9091 struct drm_i915_private *dev_priv = dev->dev_private;
9092 struct drm_crtc *crtc;
9093 struct intel_crtc *intel_crtc;
9094
9095 drm_kms_helper_poll_fini(dev);
9096 mutex_lock(&dev->struct_mutex);
9097
9098 intel_unregister_dsm_handler();
9099
9100
9101 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9102 /* Skip inactive CRTCs */
9103 if (!crtc->fb)
9104 continue;
9105
9106 intel_crtc = to_intel_crtc(crtc);
9107 intel_increase_pllclock(crtc);
9108 }
9109
9110 intel_disable_fbc(dev);
9111
9112 intel_disable_gt_powersave(dev);
9113
9114 ironlake_teardown_rc6(dev);
9115
9116 if (IS_VALLEYVIEW(dev))
9117 vlv_init_dpio(dev);
9118
9119 mutex_unlock(&dev->struct_mutex);
9120
9121 /* Disable the irq before mode object teardown, for the irq might
9122 * enqueue unpin/hotplug work. */
9123 drm_irq_uninstall(dev);
9124 cancel_work_sync(&dev_priv->hotplug_work);
9125 cancel_work_sync(&dev_priv->rps.work);
9126
9127 /* flush any delayed tasks or pending work */
9128 flush_scheduled_work();
9129
9130 drm_mode_config_cleanup(dev);
9131 }
9132
9133 /*
9134 * Return which encoder is currently attached for connector.
9135 */
9136 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9137 {
9138 return &intel_attached_encoder(connector)->base;
9139 }
9140
9141 void intel_connector_attach_encoder(struct intel_connector *connector,
9142 struct intel_encoder *encoder)
9143 {
9144 connector->encoder = encoder;
9145 drm_mode_connector_attach_encoder(&connector->base,
9146 &encoder->base);
9147 }
9148
9149 /*
9150 * set vga decode state - true == enable VGA decode
9151 */
9152 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9153 {
9154 struct drm_i915_private *dev_priv = dev->dev_private;
9155 u16 gmch_ctrl;
9156
9157 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9158 if (state)
9159 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9160 else
9161 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9162 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9163 return 0;
9164 }
9165
9166 #ifdef CONFIG_DEBUG_FS
9167 #include <linux/seq_file.h>
9168
9169 struct intel_display_error_state {
9170 struct intel_cursor_error_state {
9171 u32 control;
9172 u32 position;
9173 u32 base;
9174 u32 size;
9175 } cursor[I915_MAX_PIPES];
9176
9177 struct intel_pipe_error_state {
9178 u32 conf;
9179 u32 source;
9180
9181 u32 htotal;
9182 u32 hblank;
9183 u32 hsync;
9184 u32 vtotal;
9185 u32 vblank;
9186 u32 vsync;
9187 } pipe[I915_MAX_PIPES];
9188
9189 struct intel_plane_error_state {
9190 u32 control;
9191 u32 stride;
9192 u32 size;
9193 u32 pos;
9194 u32 addr;
9195 u32 surface;
9196 u32 tile_offset;
9197 } plane[I915_MAX_PIPES];
9198 };
9199
9200 struct intel_display_error_state *
9201 intel_display_capture_error_state(struct drm_device *dev)
9202 {
9203 drm_i915_private_t *dev_priv = dev->dev_private;
9204 struct intel_display_error_state *error;
9205 enum transcoder cpu_transcoder;
9206 int i;
9207
9208 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9209 if (error == NULL)
9210 return NULL;
9211
9212 for_each_pipe(i) {
9213 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9214
9215 error->cursor[i].control = I915_READ(CURCNTR(i));
9216 error->cursor[i].position = I915_READ(CURPOS(i));
9217 error->cursor[i].base = I915_READ(CURBASE(i));
9218
9219 error->plane[i].control = I915_READ(DSPCNTR(i));
9220 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9221 error->plane[i].size = I915_READ(DSPSIZE(i));
9222 error->plane[i].pos = I915_READ(DSPPOS(i));
9223 error->plane[i].addr = I915_READ(DSPADDR(i));
9224 if (INTEL_INFO(dev)->gen >= 4) {
9225 error->plane[i].surface = I915_READ(DSPSURF(i));
9226 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9227 }
9228
9229 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9230 error->pipe[i].source = I915_READ(PIPESRC(i));
9231 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9232 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9233 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9234 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9235 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9236 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9237 }
9238
9239 return error;
9240 }
9241
9242 void
9243 intel_display_print_error_state(struct seq_file *m,
9244 struct drm_device *dev,
9245 struct intel_display_error_state *error)
9246 {
9247 drm_i915_private_t *dev_priv = dev->dev_private;
9248 int i;
9249
9250 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9251 for_each_pipe(i) {
9252 seq_printf(m, "Pipe [%d]:\n", i);
9253 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9254 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9255 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9256 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9257 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9258 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9259 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9260 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9261
9262 seq_printf(m, "Plane [%d]:\n", i);
9263 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9264 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9265 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9266 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9267 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9268 if (INTEL_INFO(dev)->gen >= 4) {
9269 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9270 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9271 }
9272
9273 seq_printf(m, "Cursor [%d]:\n", i);
9274 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9275 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9276 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9277 }
9278 }
9279 #endif
Linux kernel - Deliverables
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