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drm/i915: check for div-by-zero in vlv_PLL_is_optimal
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105
106 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107 {
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112 }
113
114 typedef struct {
115 int min, max;
116 } intel_range_t;
117
118 typedef struct {
119 int dot_limit;
120 int p2_slow, p2_fast;
121 } intel_p2_t;
122
123 typedef struct intel_limit intel_limit_t;
124 struct intel_limit {
125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
127 };
128
129 int
130 intel_pch_rawclk(struct drm_device *dev)
131 {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137 }
138
139 static inline u32 /* units of 100MHz */
140 intel_fdi_link_freq(struct drm_device *dev)
141 {
142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
147 }
148
149 static const intel_limit_t intel_limits_i8xx_dac = {
150 .dot = { .min = 25000, .max = 350000 },
151 .vco = { .min = 908000, .max = 1512000 },
152 .n = { .min = 2, .max = 16 },
153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
160 };
161
162 static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
164 .vco = { .min = 908000, .max = 1512000 },
165 .n = { .min = 2, .max = 16 },
166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173 };
174
175 static const intel_limit_t intel_limits_i8xx_lvds = {
176 .dot = { .min = 25000, .max = 350000 },
177 .vco = { .min = 908000, .max = 1512000 },
178 .n = { .min = 2, .max = 16 },
179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
186 };
187
188 static const intel_limit_t intel_limits_i9xx_sdvo = {
189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
199 };
200
201 static const intel_limit_t intel_limits_i9xx_lvds = {
202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
212 };
213
214
215 static const intel_limit_t intel_limits_g4x_sdvo = {
216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
227 },
228 };
229
230 static const intel_limit_t intel_limits_g4x_hdmi = {
231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
241 };
242
243 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
254 },
255 };
256
257 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
268 },
269 };
270
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 };
285
286 static const intel_limit_t intel_limits_pineview_lvds = {
287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
297 };
298
299 /* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
304 static const intel_limit_t intel_limits_ironlake_dac = {
305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
315 };
316
317 static const intel_limit_t intel_limits_ironlake_single_lvds = {
318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
328 };
329
330 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
341 };
342
343 /* LVDS 100mhz refclk limits. */
344 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
352 .p1 = { .min = 2, .max = 8 },
353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
355 };
356
357 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
365 .p1 = { .min = 2, .max = 6 },
366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
368 };
369
370 static const intel_limit_t intel_limits_vlv = {
371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
378 .vco = { .min = 4000000, .max = 6000000 },
379 .n = { .min = 1, .max = 7 },
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p1 = { .min = 2, .max = 3 },
383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
384 };
385
386 static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
394 .vco = { .min = 4800000, .max = 6480000 },
395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400 };
401
402 static void vlv_clock(int refclk, intel_clock_t *clock)
403 {
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
410 }
411
412 /**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
415 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
416 {
417 struct drm_device *dev = crtc->base.dev;
418 struct intel_encoder *encoder;
419
420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
421 if (encoder->type == type)
422 return true;
423
424 return false;
425 }
426
427 /**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
446 int refclk)
447 {
448 struct drm_device *dev = crtc->base.dev;
449 const intel_limit_t *limit;
450
451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
452 if (intel_is_dual_link_lvds(dev)) {
453 if (refclk == 100000)
454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
458 if (refclk == 100000)
459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
463 } else
464 limit = &intel_limits_ironlake_dac;
465
466 return limit;
467 }
468
469 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
470 {
471 struct drm_device *dev = crtc->base.dev;
472 const intel_limit_t *limit;
473
474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
475 if (intel_is_dual_link_lvds(dev))
476 limit = &intel_limits_g4x_dual_channel_lvds;
477 else
478 limit = &intel_limits_g4x_single_channel_lvds;
479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
481 limit = &intel_limits_g4x_hdmi;
482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
483 limit = &intel_limits_g4x_sdvo;
484 } else /* The option is for other outputs */
485 limit = &intel_limits_i9xx_sdvo;
486
487 return limit;
488 }
489
490 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
491 {
492 struct drm_device *dev = crtc->base.dev;
493 const intel_limit_t *limit;
494
495 if (HAS_PCH_SPLIT(dev))
496 limit = intel_ironlake_limit(crtc, refclk);
497 else if (IS_G4X(dev)) {
498 limit = intel_g4x_limit(crtc);
499 } else if (IS_PINEVIEW(dev)) {
500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
501 limit = &intel_limits_pineview_lvds;
502 else
503 limit = &intel_limits_pineview_sdvo;
504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
506 } else if (IS_VALLEYVIEW(dev)) {
507 limit = &intel_limits_vlv;
508 } else if (!IS_GEN2(dev)) {
509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
513 } else {
514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
515 limit = &intel_limits_i8xx_lvds;
516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
517 limit = &intel_limits_i8xx_dvo;
518 else
519 limit = &intel_limits_i8xx_dac;
520 }
521 return limit;
522 }
523
524 /* m1 is reserved as 0 in Pineview, n is a ring counter */
525 static void pineview_clock(int refclk, intel_clock_t *clock)
526 {
527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
533 }
534
535 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536 {
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538 }
539
540 static void i9xx_clock(int refclk, intel_clock_t *clock)
541 {
542 clock->m = i9xx_dpll_compute_m(clock);
543 clock->p = clock->p1 * clock->p2;
544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
548 }
549
550 static void chv_clock(int refclk, intel_clock_t *clock)
551 {
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559 }
560
561 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
562 /**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
567 static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
570 {
571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
574 INTELPllInvalid("p1 out of range\n");
575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
576 INTELPllInvalid("m2 out of range\n");
577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
578 INTELPllInvalid("m1 out of range\n");
579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
592 INTELPllInvalid("vco out of range\n");
593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
597 INTELPllInvalid("dot out of range\n");
598
599 return true;
600 }
601
602 static bool
603 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
606 {
607 struct drm_device *dev = crtc->base.dev;
608 intel_clock_t clock;
609 int err = target;
610
611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
612 /*
613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
616 */
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629
630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
634 if (clock.m2 >= clock.m1)
635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
640 int this_err;
641
642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661 }
662
663 static bool
664 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
667 {
668 struct drm_device *dev = crtc->base.dev;
669 intel_clock_t clock;
670 int err = target;
671
672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
673 /*
674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
677 */
678 if (intel_is_dual_link_lvds(dev))
679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
689 memset(best_clock, 0, sizeof(*best_clock));
690
691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
699 int this_err;
700
701 pineview_clock(refclk, &clock);
702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
704 continue;
705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720 }
721
722 static bool
723 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
726 {
727 struct drm_device *dev = crtc->base.dev;
728 intel_clock_t clock;
729 int max_n;
730 bool found;
731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
733 found = false;
734
735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
736 if (intel_is_dual_link_lvds(dev))
737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
749 /* based on hardware requirement, prefer smaller n to precision */
750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
751 /* based on hardware requirement, prefere larger m1,m2 */
752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
760 i9xx_clock(refclk, &clock);
761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
763 continue;
764
765 this_err = abs(clock.dot - target);
766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
776 return found;
777 }
778
779 /*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788 {
789 if (WARN_ON_ONCE(!target_freq))
790 return false;
791
792 *error_ppm = div_u64(1000000ULL *
793 abs(target_freq - calculated_clock->dot),
794 target_freq);
795 /*
796 * Prefer a better P value over a better (smaller) error if the error
797 * is small. Ensure this preference for future configurations too by
798 * setting the error to 0.
799 */
800 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
801 *error_ppm = 0;
802
803 return true;
804 }
805
806 return *error_ppm + 10 < best_error_ppm;
807 }
808
809 static bool
810 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
811 int target, int refclk, intel_clock_t *match_clock,
812 intel_clock_t *best_clock)
813 {
814 struct drm_device *dev = crtc->base.dev;
815 intel_clock_t clock;
816 unsigned int bestppm = 1000000;
817 /* min update 19.2 MHz */
818 int max_n = min(limit->n.max, refclk / 19200);
819 bool found = false;
820
821 target *= 5; /* fast clock */
822
823 memset(best_clock, 0, sizeof(*best_clock));
824
825 /* based on hardware requirement, prefer smaller n to precision */
826 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
827 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
828 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
829 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
830 clock.p = clock.p1 * clock.p2;
831 /* based on hardware requirement, prefer bigger m1,m2 values */
832 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
833 unsigned int ppm;
834
835 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
836 refclk * clock.m1);
837
838 vlv_clock(refclk, &clock);
839
840 if (!intel_PLL_is_valid(dev, limit,
841 &clock))
842 continue;
843
844 if (!vlv_PLL_is_optimal(dev, target,
845 &clock,
846 best_clock,
847 bestppm, &ppm))
848 continue;
849
850 *best_clock = clock;
851 bestppm = ppm;
852 found = true;
853 }
854 }
855 }
856 }
857
858 return found;
859 }
860
861 static bool
862 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 struct drm_device *dev = crtc->base.dev;
867 intel_clock_t clock;
868 uint64_t m2;
869 int found = false;
870
871 memset(best_clock, 0, sizeof(*best_clock));
872
873 /*
874 * Based on hardware doc, the n always set to 1, and m1 always
875 * set to 2. If requires to support 200Mhz refclk, we need to
876 * revisit this because n may not 1 anymore.
877 */
878 clock.n = 1, clock.m1 = 2;
879 target *= 5; /* fast clock */
880
881 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
882 for (clock.p2 = limit->p2.p2_fast;
883 clock.p2 >= limit->p2.p2_slow;
884 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
885
886 clock.p = clock.p1 * clock.p2;
887
888 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
889 clock.n) << 22, refclk * clock.m1);
890
891 if (m2 > INT_MAX/clock.m1)
892 continue;
893
894 clock.m2 = m2;
895
896 chv_clock(refclk, &clock);
897
898 if (!intel_PLL_is_valid(dev, limit, &clock))
899 continue;
900
901 /* based on hardware requirement, prefer bigger p
902 */
903 if (clock.p > best_clock->p) {
904 *best_clock = clock;
905 found = true;
906 }
907 }
908 }
909
910 return found;
911 }
912
913 bool intel_crtc_active(struct drm_crtc *crtc)
914 {
915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
916
917 /* Be paranoid as we can arrive here with only partial
918 * state retrieved from the hardware during setup.
919 *
920 * We can ditch the adjusted_mode.crtc_clock check as soon
921 * as Haswell has gained clock readout/fastboot support.
922 *
923 * We can ditch the crtc->primary->fb check as soon as we can
924 * properly reconstruct framebuffers.
925 *
926 * FIXME: The intel_crtc->active here should be switched to
927 * crtc->state->active once we have proper CRTC states wired up
928 * for atomic.
929 */
930 return intel_crtc->active && crtc->primary->state->fb &&
931 intel_crtc->config->base.adjusted_mode.crtc_clock;
932 }
933
934 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
935 enum pipe pipe)
936 {
937 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
939
940 return intel_crtc->config->cpu_transcoder;
941 }
942
943 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
944 {
945 struct drm_i915_private *dev_priv = dev->dev_private;
946 u32 reg = PIPEDSL(pipe);
947 u32 line1, line2;
948 u32 line_mask;
949
950 if (IS_GEN2(dev))
951 line_mask = DSL_LINEMASK_GEN2;
952 else
953 line_mask = DSL_LINEMASK_GEN3;
954
955 line1 = I915_READ(reg) & line_mask;
956 mdelay(5);
957 line2 = I915_READ(reg) & line_mask;
958
959 return line1 == line2;
960 }
961
962 /*
963 * intel_wait_for_pipe_off - wait for pipe to turn off
964 * @crtc: crtc whose pipe to wait for
965 *
966 * After disabling a pipe, we can't wait for vblank in the usual way,
967 * spinning on the vblank interrupt status bit, since we won't actually
968 * see an interrupt when the pipe is disabled.
969 *
970 * On Gen4 and above:
971 * wait for the pipe register state bit to turn off
972 *
973 * Otherwise:
974 * wait for the display line value to settle (it usually
975 * ends up stopping at the start of the next frame).
976 *
977 */
978 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
979 {
980 struct drm_device *dev = crtc->base.dev;
981 struct drm_i915_private *dev_priv = dev->dev_private;
982 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
983 enum pipe pipe = crtc->pipe;
984
985 if (INTEL_INFO(dev)->gen >= 4) {
986 int reg = PIPECONF(cpu_transcoder);
987
988 /* Wait for the Pipe State to go off */
989 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
990 100))
991 WARN(1, "pipe_off wait timed out\n");
992 } else {
993 /* Wait for the display line to settle */
994 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
995 WARN(1, "pipe_off wait timed out\n");
996 }
997 }
998
999 /*
1000 * ibx_digital_port_connected - is the specified port connected?
1001 * @dev_priv: i915 private structure
1002 * @port: the port to test
1003 *
1004 * Returns true if @port is connected, false otherwise.
1005 */
1006 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1007 struct intel_digital_port *port)
1008 {
1009 u32 bit;
1010
1011 if (HAS_PCH_IBX(dev_priv->dev)) {
1012 switch (port->port) {
1013 case PORT_B:
1014 bit = SDE_PORTB_HOTPLUG;
1015 break;
1016 case PORT_C:
1017 bit = SDE_PORTC_HOTPLUG;
1018 break;
1019 case PORT_D:
1020 bit = SDE_PORTD_HOTPLUG;
1021 break;
1022 default:
1023 return true;
1024 }
1025 } else {
1026 switch (port->port) {
1027 case PORT_B:
1028 bit = SDE_PORTB_HOTPLUG_CPT;
1029 break;
1030 case PORT_C:
1031 bit = SDE_PORTC_HOTPLUG_CPT;
1032 break;
1033 case PORT_D:
1034 bit = SDE_PORTD_HOTPLUG_CPT;
1035 break;
1036 default:
1037 return true;
1038 }
1039 }
1040
1041 return I915_READ(SDEISR) & bit;
1042 }
1043
1044 static const char *state_string(bool enabled)
1045 {
1046 return enabled ? "on" : "off";
1047 }
1048
1049 /* Only for pre-ILK configs */
1050 void assert_pll(struct drm_i915_private *dev_priv,
1051 enum pipe pipe, bool state)
1052 {
1053 int reg;
1054 u32 val;
1055 bool cur_state;
1056
1057 reg = DPLL(pipe);
1058 val = I915_READ(reg);
1059 cur_state = !!(val & DPLL_VCO_ENABLE);
1060 I915_STATE_WARN(cur_state != state,
1061 "PLL state assertion failure (expected %s, current %s)\n",
1062 state_string(state), state_string(cur_state));
1063 }
1064
1065 /* XXX: the dsi pll is shared between MIPI DSI ports */
1066 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1067 {
1068 u32 val;
1069 bool cur_state;
1070
1071 mutex_lock(&dev_priv->dpio_lock);
1072 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1073 mutex_unlock(&dev_priv->dpio_lock);
1074
1075 cur_state = val & DSI_PLL_VCO_EN;
1076 I915_STATE_WARN(cur_state != state,
1077 "DSI PLL state assertion failure (expected %s, current %s)\n",
1078 state_string(state), state_string(cur_state));
1079 }
1080 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1081 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1082
1083 struct intel_shared_dpll *
1084 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1085 {
1086 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1087
1088 if (crtc->config->shared_dpll < 0)
1089 return NULL;
1090
1091 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1092 }
1093
1094 /* For ILK+ */
1095 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1096 struct intel_shared_dpll *pll,
1097 bool state)
1098 {
1099 bool cur_state;
1100 struct intel_dpll_hw_state hw_state;
1101
1102 if (WARN (!pll,
1103 "asserting DPLL %s with no DPLL\n", state_string(state)))
1104 return;
1105
1106 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1107 I915_STATE_WARN(cur_state != state,
1108 "%s assertion failure (expected %s, current %s)\n",
1109 pll->name, state_string(state), state_string(cur_state));
1110 }
1111
1112 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1113 enum pipe pipe, bool state)
1114 {
1115 int reg;
1116 u32 val;
1117 bool cur_state;
1118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1119 pipe);
1120
1121 if (HAS_DDI(dev_priv->dev)) {
1122 /* DDI does not have a specific FDI_TX register */
1123 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1124 val = I915_READ(reg);
1125 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1126 } else {
1127 reg = FDI_TX_CTL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & FDI_TX_ENABLE);
1130 }
1131 I915_STATE_WARN(cur_state != state,
1132 "FDI TX state assertion failure (expected %s, current %s)\n",
1133 state_string(state), state_string(cur_state));
1134 }
1135 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1136 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1137
1138 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1139 enum pipe pipe, bool state)
1140 {
1141 int reg;
1142 u32 val;
1143 bool cur_state;
1144
1145 reg = FDI_RX_CTL(pipe);
1146 val = I915_READ(reg);
1147 cur_state = !!(val & FDI_RX_ENABLE);
1148 I915_STATE_WARN(cur_state != state,
1149 "FDI RX state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151 }
1152 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1153 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1154
1155 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1156 enum pipe pipe)
1157 {
1158 int reg;
1159 u32 val;
1160
1161 /* ILK FDI PLL is always enabled */
1162 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1163 return;
1164
1165 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1166 if (HAS_DDI(dev_priv->dev))
1167 return;
1168
1169 reg = FDI_TX_CTL(pipe);
1170 val = I915_READ(reg);
1171 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1172 }
1173
1174 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1175 enum pipe pipe, bool state)
1176 {
1177 int reg;
1178 u32 val;
1179 bool cur_state;
1180
1181 reg = FDI_RX_CTL(pipe);
1182 val = I915_READ(reg);
1183 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1184 I915_STATE_WARN(cur_state != state,
1185 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1186 state_string(state), state_string(cur_state));
1187 }
1188
1189 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191 {
1192 struct drm_device *dev = dev_priv->dev;
1193 int pp_reg;
1194 u32 val;
1195 enum pipe panel_pipe = PIPE_A;
1196 bool locked = true;
1197
1198 if (WARN_ON(HAS_DDI(dev)))
1199 return;
1200
1201 if (HAS_PCH_SPLIT(dev)) {
1202 u32 port_sel;
1203
1204 pp_reg = PCH_PP_CONTROL;
1205 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1206
1207 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1208 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1209 panel_pipe = PIPE_B;
1210 /* XXX: else fix for eDP */
1211 } else if (IS_VALLEYVIEW(dev)) {
1212 /* presumably write lock depends on pipe, not port select */
1213 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1214 panel_pipe = pipe;
1215 } else {
1216 pp_reg = PP_CONTROL;
1217 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1218 panel_pipe = PIPE_B;
1219 }
1220
1221 val = I915_READ(pp_reg);
1222 if (!(val & PANEL_POWER_ON) ||
1223 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1224 locked = false;
1225
1226 I915_STATE_WARN(panel_pipe == pipe && locked,
1227 "panel assertion failure, pipe %c regs locked\n",
1228 pipe_name(pipe));
1229 }
1230
1231 static void assert_cursor(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, bool state)
1233 {
1234 struct drm_device *dev = dev_priv->dev;
1235 bool cur_state;
1236
1237 if (IS_845G(dev) || IS_I865G(dev))
1238 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1239 else
1240 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1241
1242 I915_STATE_WARN(cur_state != state,
1243 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1244 pipe_name(pipe), state_string(state), state_string(cur_state));
1245 }
1246 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1247 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1248
1249 void assert_pipe(struct drm_i915_private *dev_priv,
1250 enum pipe pipe, bool state)
1251 {
1252 int reg;
1253 u32 val;
1254 bool cur_state;
1255 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1256 pipe);
1257
1258 /* if we need the pipe quirk it must be always on */
1259 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1260 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1261 state = true;
1262
1263 if (!intel_display_power_is_enabled(dev_priv,
1264 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1265 cur_state = false;
1266 } else {
1267 reg = PIPECONF(cpu_transcoder);
1268 val = I915_READ(reg);
1269 cur_state = !!(val & PIPECONF_ENABLE);
1270 }
1271
1272 I915_STATE_WARN(cur_state != state,
1273 "pipe %c assertion failure (expected %s, current %s)\n",
1274 pipe_name(pipe), state_string(state), state_string(cur_state));
1275 }
1276
1277 static void assert_plane(struct drm_i915_private *dev_priv,
1278 enum plane plane, bool state)
1279 {
1280 int reg;
1281 u32 val;
1282 bool cur_state;
1283
1284 reg = DSPCNTR(plane);
1285 val = I915_READ(reg);
1286 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1287 I915_STATE_WARN(cur_state != state,
1288 "plane %c assertion failure (expected %s, current %s)\n",
1289 plane_name(plane), state_string(state), state_string(cur_state));
1290 }
1291
1292 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1293 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1294
1295 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe)
1297 {
1298 struct drm_device *dev = dev_priv->dev;
1299 int reg, i;
1300 u32 val;
1301 int cur_pipe;
1302
1303 /* Primary planes are fixed to pipes on gen4+ */
1304 if (INTEL_INFO(dev)->gen >= 4) {
1305 reg = DSPCNTR(pipe);
1306 val = I915_READ(reg);
1307 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1308 "plane %c assertion failure, should be disabled but not\n",
1309 plane_name(pipe));
1310 return;
1311 }
1312
1313 /* Need to check both planes against the pipe */
1314 for_each_pipe(dev_priv, i) {
1315 reg = DSPCNTR(i);
1316 val = I915_READ(reg);
1317 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1318 DISPPLANE_SEL_PIPE_SHIFT;
1319 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1320 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1321 plane_name(i), pipe_name(pipe));
1322 }
1323 }
1324
1325 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1326 enum pipe pipe)
1327 {
1328 struct drm_device *dev = dev_priv->dev;
1329 int reg, sprite;
1330 u32 val;
1331
1332 if (INTEL_INFO(dev)->gen >= 9) {
1333 for_each_sprite(dev_priv, pipe, sprite) {
1334 val = I915_READ(PLANE_CTL(pipe, sprite));
1335 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1336 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1337 sprite, pipe_name(pipe));
1338 }
1339 } else if (IS_VALLEYVIEW(dev)) {
1340 for_each_sprite(dev_priv, pipe, sprite) {
1341 reg = SPCNTR(pipe, sprite);
1342 val = I915_READ(reg);
1343 I915_STATE_WARN(val & SP_ENABLE,
1344 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1345 sprite_name(pipe, sprite), pipe_name(pipe));
1346 }
1347 } else if (INTEL_INFO(dev)->gen >= 7) {
1348 reg = SPRCTL(pipe);
1349 val = I915_READ(reg);
1350 I915_STATE_WARN(val & SPRITE_ENABLE,
1351 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1352 plane_name(pipe), pipe_name(pipe));
1353 } else if (INTEL_INFO(dev)->gen >= 5) {
1354 reg = DVSCNTR(pipe);
1355 val = I915_READ(reg);
1356 I915_STATE_WARN(val & DVS_ENABLE,
1357 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1358 plane_name(pipe), pipe_name(pipe));
1359 }
1360 }
1361
1362 static void assert_vblank_disabled(struct drm_crtc *crtc)
1363 {
1364 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1365 drm_crtc_vblank_put(crtc);
1366 }
1367
1368 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1369 {
1370 u32 val;
1371 bool enabled;
1372
1373 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1374
1375 val = I915_READ(PCH_DREF_CONTROL);
1376 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1377 DREF_SUPERSPREAD_SOURCE_MASK));
1378 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1379 }
1380
1381 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1382 enum pipe pipe)
1383 {
1384 int reg;
1385 u32 val;
1386 bool enabled;
1387
1388 reg = PCH_TRANSCONF(pipe);
1389 val = I915_READ(reg);
1390 enabled = !!(val & TRANS_ENABLE);
1391 I915_STATE_WARN(enabled,
1392 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1393 pipe_name(pipe));
1394 }
1395
1396 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1397 enum pipe pipe, u32 port_sel, u32 val)
1398 {
1399 if ((val & DP_PORT_EN) == 0)
1400 return false;
1401
1402 if (HAS_PCH_CPT(dev_priv->dev)) {
1403 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1404 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1405 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1406 return false;
1407 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1408 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1409 return false;
1410 } else {
1411 if ((val & DP_PIPE_MASK) != (pipe << 30))
1412 return false;
1413 }
1414 return true;
1415 }
1416
1417 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1418 enum pipe pipe, u32 val)
1419 {
1420 if ((val & SDVO_ENABLE) == 0)
1421 return false;
1422
1423 if (HAS_PCH_CPT(dev_priv->dev)) {
1424 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1425 return false;
1426 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1427 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1428 return false;
1429 } else {
1430 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1431 return false;
1432 }
1433 return true;
1434 }
1435
1436 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, u32 val)
1438 {
1439 if ((val & LVDS_PORT_EN) == 0)
1440 return false;
1441
1442 if (HAS_PCH_CPT(dev_priv->dev)) {
1443 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1444 return false;
1445 } else {
1446 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1447 return false;
1448 }
1449 return true;
1450 }
1451
1452 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1453 enum pipe pipe, u32 val)
1454 {
1455 if ((val & ADPA_DAC_ENABLE) == 0)
1456 return false;
1457 if (HAS_PCH_CPT(dev_priv->dev)) {
1458 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1459 return false;
1460 } else {
1461 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1462 return false;
1463 }
1464 return true;
1465 }
1466
1467 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1468 enum pipe pipe, int reg, u32 port_sel)
1469 {
1470 u32 val = I915_READ(reg);
1471 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1472 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1473 reg, pipe_name(pipe));
1474
1475 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1476 && (val & DP_PIPEB_SELECT),
1477 "IBX PCH dp port still using transcoder B\n");
1478 }
1479
1480 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1481 enum pipe pipe, int reg)
1482 {
1483 u32 val = I915_READ(reg);
1484 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1485 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1486 reg, pipe_name(pipe));
1487
1488 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1489 && (val & SDVO_PIPE_B_SELECT),
1490 "IBX PCH hdmi port still using transcoder B\n");
1491 }
1492
1493 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1494 enum pipe pipe)
1495 {
1496 int reg;
1497 u32 val;
1498
1499 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1500 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1501 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1502
1503 reg = PCH_ADPA;
1504 val = I915_READ(reg);
1505 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1506 "PCH VGA enabled on transcoder %c, should be disabled\n",
1507 pipe_name(pipe));
1508
1509 reg = PCH_LVDS;
1510 val = I915_READ(reg);
1511 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1512 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1513 pipe_name(pipe));
1514
1515 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1516 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1517 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1518 }
1519
1520 static void intel_init_dpio(struct drm_device *dev)
1521 {
1522 struct drm_i915_private *dev_priv = dev->dev_private;
1523
1524 if (!IS_VALLEYVIEW(dev))
1525 return;
1526
1527 /*
1528 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1529 * CHV x1 PHY (DP/HDMI D)
1530 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1531 */
1532 if (IS_CHERRYVIEW(dev)) {
1533 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1534 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1535 } else {
1536 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1537 }
1538 }
1539
1540 static void vlv_enable_pll(struct intel_crtc *crtc,
1541 const struct intel_crtc_state *pipe_config)
1542 {
1543 struct drm_device *dev = crtc->base.dev;
1544 struct drm_i915_private *dev_priv = dev->dev_private;
1545 int reg = DPLL(crtc->pipe);
1546 u32 dpll = pipe_config->dpll_hw_state.dpll;
1547
1548 assert_pipe_disabled(dev_priv, crtc->pipe);
1549
1550 /* No really, not for ILK+ */
1551 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1552
1553 /* PLL is protected by panel, make sure we can write it */
1554 if (IS_MOBILE(dev_priv->dev))
1555 assert_panel_unlocked(dev_priv, crtc->pipe);
1556
1557 I915_WRITE(reg, dpll);
1558 POSTING_READ(reg);
1559 udelay(150);
1560
1561 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1562 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1563
1564 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1565 POSTING_READ(DPLL_MD(crtc->pipe));
1566
1567 /* We do this three times for luck */
1568 I915_WRITE(reg, dpll);
1569 POSTING_READ(reg);
1570 udelay(150); /* wait for warmup */
1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150); /* wait for warmup */
1574 I915_WRITE(reg, dpll);
1575 POSTING_READ(reg);
1576 udelay(150); /* wait for warmup */
1577 }
1578
1579 static void chv_enable_pll(struct intel_crtc *crtc,
1580 const struct intel_crtc_state *pipe_config)
1581 {
1582 struct drm_device *dev = crtc->base.dev;
1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584 int pipe = crtc->pipe;
1585 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1586 u32 tmp;
1587
1588 assert_pipe_disabled(dev_priv, crtc->pipe);
1589
1590 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1591
1592 mutex_lock(&dev_priv->dpio_lock);
1593
1594 /* Enable back the 10bit clock to display controller */
1595 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1596 tmp |= DPIO_DCLKP_EN;
1597 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1598
1599 /*
1600 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1601 */
1602 udelay(1);
1603
1604 /* Enable PLL */
1605 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1606
1607 /* Check PLL is locked */
1608 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1609 DRM_ERROR("PLL %d failed to lock\n", pipe);
1610
1611 /* not sure when this should be written */
1612 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1613 POSTING_READ(DPLL_MD(pipe));
1614
1615 mutex_unlock(&dev_priv->dpio_lock);
1616 }
1617
1618 static int intel_num_dvo_pipes(struct drm_device *dev)
1619 {
1620 struct intel_crtc *crtc;
1621 int count = 0;
1622
1623 for_each_intel_crtc(dev, crtc)
1624 count += crtc->active &&
1625 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1626
1627 return count;
1628 }
1629
1630 static void i9xx_enable_pll(struct intel_crtc *crtc)
1631 {
1632 struct drm_device *dev = crtc->base.dev;
1633 struct drm_i915_private *dev_priv = dev->dev_private;
1634 int reg = DPLL(crtc->pipe);
1635 u32 dpll = crtc->config->dpll_hw_state.dpll;
1636
1637 assert_pipe_disabled(dev_priv, crtc->pipe);
1638
1639 /* No really, not for ILK+ */
1640 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1641
1642 /* PLL is protected by panel, make sure we can write it */
1643 if (IS_MOBILE(dev) && !IS_I830(dev))
1644 assert_panel_unlocked(dev_priv, crtc->pipe);
1645
1646 /* Enable DVO 2x clock on both PLLs if necessary */
1647 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1648 /*
1649 * It appears to be important that we don't enable this
1650 * for the current pipe before otherwise configuring the
1651 * PLL. No idea how this should be handled if multiple
1652 * DVO outputs are enabled simultaneosly.
1653 */
1654 dpll |= DPLL_DVO_2X_MODE;
1655 I915_WRITE(DPLL(!crtc->pipe),
1656 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1657 }
1658
1659 /* Wait for the clocks to stabilize. */
1660 POSTING_READ(reg);
1661 udelay(150);
1662
1663 if (INTEL_INFO(dev)->gen >= 4) {
1664 I915_WRITE(DPLL_MD(crtc->pipe),
1665 crtc->config->dpll_hw_state.dpll_md);
1666 } else {
1667 /* The pixel multiplier can only be updated once the
1668 * DPLL is enabled and the clocks are stable.
1669 *
1670 * So write it again.
1671 */
1672 I915_WRITE(reg, dpll);
1673 }
1674
1675 /* We do this three times for luck */
1676 I915_WRITE(reg, dpll);
1677 POSTING_READ(reg);
1678 udelay(150); /* wait for warmup */
1679 I915_WRITE(reg, dpll);
1680 POSTING_READ(reg);
1681 udelay(150); /* wait for warmup */
1682 I915_WRITE(reg, dpll);
1683 POSTING_READ(reg);
1684 udelay(150); /* wait for warmup */
1685 }
1686
1687 /**
1688 * i9xx_disable_pll - disable a PLL
1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe PLL to disable
1691 *
1692 * Disable the PLL for @pipe, making sure the pipe is off first.
1693 *
1694 * Note! This is for pre-ILK only.
1695 */
1696 static void i9xx_disable_pll(struct intel_crtc *crtc)
1697 {
1698 struct drm_device *dev = crtc->base.dev;
1699 struct drm_i915_private *dev_priv = dev->dev_private;
1700 enum pipe pipe = crtc->pipe;
1701
1702 /* Disable DVO 2x clock on both PLLs if necessary */
1703 if (IS_I830(dev) &&
1704 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1705 intel_num_dvo_pipes(dev) == 1) {
1706 I915_WRITE(DPLL(PIPE_B),
1707 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1708 I915_WRITE(DPLL(PIPE_A),
1709 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1710 }
1711
1712 /* Don't disable pipe or pipe PLLs if needed */
1713 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1714 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1715 return;
1716
1717 /* Make sure the pipe isn't still relying on us */
1718 assert_pipe_disabled(dev_priv, pipe);
1719
1720 I915_WRITE(DPLL(pipe), 0);
1721 POSTING_READ(DPLL(pipe));
1722 }
1723
1724 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1725 {
1726 u32 val = 0;
1727
1728 /* Make sure the pipe isn't still relying on us */
1729 assert_pipe_disabled(dev_priv, pipe);
1730
1731 /*
1732 * Leave integrated clock source and reference clock enabled for pipe B.
1733 * The latter is needed for VGA hotplug / manual detection.
1734 */
1735 if (pipe == PIPE_B)
1736 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1737 I915_WRITE(DPLL(pipe), val);
1738 POSTING_READ(DPLL(pipe));
1739
1740 }
1741
1742 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1743 {
1744 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1745 u32 val;
1746
1747 /* Make sure the pipe isn't still relying on us */
1748 assert_pipe_disabled(dev_priv, pipe);
1749
1750 /* Set PLL en = 0 */
1751 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1752 if (pipe != PIPE_A)
1753 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1754 I915_WRITE(DPLL(pipe), val);
1755 POSTING_READ(DPLL(pipe));
1756
1757 mutex_lock(&dev_priv->dpio_lock);
1758
1759 /* Disable 10bit clock to display controller */
1760 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1761 val &= ~DPIO_DCLKP_EN;
1762 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1763
1764 /* disable left/right clock distribution */
1765 if (pipe != PIPE_B) {
1766 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1767 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1768 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1769 } else {
1770 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1771 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1772 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1773 }
1774
1775 mutex_unlock(&dev_priv->dpio_lock);
1776 }
1777
1778 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1779 struct intel_digital_port *dport)
1780 {
1781 u32 port_mask;
1782 int dpll_reg;
1783
1784 switch (dport->port) {
1785 case PORT_B:
1786 port_mask = DPLL_PORTB_READY_MASK;
1787 dpll_reg = DPLL(0);
1788 break;
1789 case PORT_C:
1790 port_mask = DPLL_PORTC_READY_MASK;
1791 dpll_reg = DPLL(0);
1792 break;
1793 case PORT_D:
1794 port_mask = DPLL_PORTD_READY_MASK;
1795 dpll_reg = DPIO_PHY_STATUS;
1796 break;
1797 default:
1798 BUG();
1799 }
1800
1801 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1802 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1803 port_name(dport->port), I915_READ(dpll_reg));
1804 }
1805
1806 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1807 {
1808 struct drm_device *dev = crtc->base.dev;
1809 struct drm_i915_private *dev_priv = dev->dev_private;
1810 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1811
1812 if (WARN_ON(pll == NULL))
1813 return;
1814
1815 WARN_ON(!pll->config.crtc_mask);
1816 if (pll->active == 0) {
1817 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1818 WARN_ON(pll->on);
1819 assert_shared_dpll_disabled(dev_priv, pll);
1820
1821 pll->mode_set(dev_priv, pll);
1822 }
1823 }
1824
1825 /**
1826 * intel_enable_shared_dpll - enable PCH PLL
1827 * @dev_priv: i915 private structure
1828 * @pipe: pipe PLL to enable
1829 *
1830 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1831 * drives the transcoder clock.
1832 */
1833 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1834 {
1835 struct drm_device *dev = crtc->base.dev;
1836 struct drm_i915_private *dev_priv = dev->dev_private;
1837 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1838
1839 if (WARN_ON(pll == NULL))
1840 return;
1841
1842 if (WARN_ON(pll->config.crtc_mask == 0))
1843 return;
1844
1845 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1846 pll->name, pll->active, pll->on,
1847 crtc->base.base.id);
1848
1849 if (pll->active++) {
1850 WARN_ON(!pll->on);
1851 assert_shared_dpll_enabled(dev_priv, pll);
1852 return;
1853 }
1854 WARN_ON(pll->on);
1855
1856 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1857
1858 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1859 pll->enable(dev_priv, pll);
1860 pll->on = true;
1861 }
1862
1863 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1864 {
1865 struct drm_device *dev = crtc->base.dev;
1866 struct drm_i915_private *dev_priv = dev->dev_private;
1867 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1868
1869 /* PCH only available on ILK+ */
1870 BUG_ON(INTEL_INFO(dev)->gen < 5);
1871 if (WARN_ON(pll == NULL))
1872 return;
1873
1874 if (WARN_ON(pll->config.crtc_mask == 0))
1875 return;
1876
1877 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1878 pll->name, pll->active, pll->on,
1879 crtc->base.base.id);
1880
1881 if (WARN_ON(pll->active == 0)) {
1882 assert_shared_dpll_disabled(dev_priv, pll);
1883 return;
1884 }
1885
1886 assert_shared_dpll_enabled(dev_priv, pll);
1887 WARN_ON(!pll->on);
1888 if (--pll->active)
1889 return;
1890
1891 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1892 pll->disable(dev_priv, pll);
1893 pll->on = false;
1894
1895 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1896 }
1897
1898 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1899 enum pipe pipe)
1900 {
1901 struct drm_device *dev = dev_priv->dev;
1902 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1904 uint32_t reg, val, pipeconf_val;
1905
1906 /* PCH only available on ILK+ */
1907 BUG_ON(!HAS_PCH_SPLIT(dev));
1908
1909 /* Make sure PCH DPLL is enabled */
1910 assert_shared_dpll_enabled(dev_priv,
1911 intel_crtc_to_shared_dpll(intel_crtc));
1912
1913 /* FDI must be feeding us bits for PCH ports */
1914 assert_fdi_tx_enabled(dev_priv, pipe);
1915 assert_fdi_rx_enabled(dev_priv, pipe);
1916
1917 if (HAS_PCH_CPT(dev)) {
1918 /* Workaround: Set the timing override bit before enabling the
1919 * pch transcoder. */
1920 reg = TRANS_CHICKEN2(pipe);
1921 val = I915_READ(reg);
1922 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1923 I915_WRITE(reg, val);
1924 }
1925
1926 reg = PCH_TRANSCONF(pipe);
1927 val = I915_READ(reg);
1928 pipeconf_val = I915_READ(PIPECONF(pipe));
1929
1930 if (HAS_PCH_IBX(dev_priv->dev)) {
1931 /*
1932 * make the BPC in transcoder be consistent with
1933 * that in pipeconf reg.
1934 */
1935 val &= ~PIPECONF_BPC_MASK;
1936 val |= pipeconf_val & PIPECONF_BPC_MASK;
1937 }
1938
1939 val &= ~TRANS_INTERLACE_MASK;
1940 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1941 if (HAS_PCH_IBX(dev_priv->dev) &&
1942 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1943 val |= TRANS_LEGACY_INTERLACED_ILK;
1944 else
1945 val |= TRANS_INTERLACED;
1946 else
1947 val |= TRANS_PROGRESSIVE;
1948
1949 I915_WRITE(reg, val | TRANS_ENABLE);
1950 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1951 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1952 }
1953
1954 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1955 enum transcoder cpu_transcoder)
1956 {
1957 u32 val, pipeconf_val;
1958
1959 /* PCH only available on ILK+ */
1960 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1961
1962 /* FDI must be feeding us bits for PCH ports */
1963 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1964 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1965
1966 /* Workaround: set timing override bit. */
1967 val = I915_READ(_TRANSA_CHICKEN2);
1968 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1969 I915_WRITE(_TRANSA_CHICKEN2, val);
1970
1971 val = TRANS_ENABLE;
1972 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1973
1974 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1975 PIPECONF_INTERLACED_ILK)
1976 val |= TRANS_INTERLACED;
1977 else
1978 val |= TRANS_PROGRESSIVE;
1979
1980 I915_WRITE(LPT_TRANSCONF, val);
1981 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1982 DRM_ERROR("Failed to enable PCH transcoder\n");
1983 }
1984
1985 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1986 enum pipe pipe)
1987 {
1988 struct drm_device *dev = dev_priv->dev;
1989 uint32_t reg, val;
1990
1991 /* FDI relies on the transcoder */
1992 assert_fdi_tx_disabled(dev_priv, pipe);
1993 assert_fdi_rx_disabled(dev_priv, pipe);
1994
1995 /* Ports must be off as well */
1996 assert_pch_ports_disabled(dev_priv, pipe);
1997
1998 reg = PCH_TRANSCONF(pipe);
1999 val = I915_READ(reg);
2000 val &= ~TRANS_ENABLE;
2001 I915_WRITE(reg, val);
2002 /* wait for PCH transcoder off, transcoder state */
2003 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2004 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2005
2006 if (!HAS_PCH_IBX(dev)) {
2007 /* Workaround: Clear the timing override chicken bit again. */
2008 reg = TRANS_CHICKEN2(pipe);
2009 val = I915_READ(reg);
2010 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2011 I915_WRITE(reg, val);
2012 }
2013 }
2014
2015 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2016 {
2017 u32 val;
2018
2019 val = I915_READ(LPT_TRANSCONF);
2020 val &= ~TRANS_ENABLE;
2021 I915_WRITE(LPT_TRANSCONF, val);
2022 /* wait for PCH transcoder off, transcoder state */
2023 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2024 DRM_ERROR("Failed to disable PCH transcoder\n");
2025
2026 /* Workaround: clear timing override bit. */
2027 val = I915_READ(_TRANSA_CHICKEN2);
2028 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2029 I915_WRITE(_TRANSA_CHICKEN2, val);
2030 }
2031
2032 /**
2033 * intel_enable_pipe - enable a pipe, asserting requirements
2034 * @crtc: crtc responsible for the pipe
2035 *
2036 * Enable @crtc's pipe, making sure that various hardware specific requirements
2037 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2038 */
2039 static void intel_enable_pipe(struct intel_crtc *crtc)
2040 {
2041 struct drm_device *dev = crtc->base.dev;
2042 struct drm_i915_private *dev_priv = dev->dev_private;
2043 enum pipe pipe = crtc->pipe;
2044 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2045 pipe);
2046 enum pipe pch_transcoder;
2047 int reg;
2048 u32 val;
2049
2050 assert_planes_disabled(dev_priv, pipe);
2051 assert_cursor_disabled(dev_priv, pipe);
2052 assert_sprites_disabled(dev_priv, pipe);
2053
2054 if (HAS_PCH_LPT(dev_priv->dev))
2055 pch_transcoder = TRANSCODER_A;
2056 else
2057 pch_transcoder = pipe;
2058
2059 /*
2060 * A pipe without a PLL won't actually be able to drive bits from
2061 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2062 * need the check.
2063 */
2064 if (!HAS_PCH_SPLIT(dev_priv->dev))
2065 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2066 assert_dsi_pll_enabled(dev_priv);
2067 else
2068 assert_pll_enabled(dev_priv, pipe);
2069 else {
2070 if (crtc->config->has_pch_encoder) {
2071 /* if driving the PCH, we need FDI enabled */
2072 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2073 assert_fdi_tx_pll_enabled(dev_priv,
2074 (enum pipe) cpu_transcoder);
2075 }
2076 /* FIXME: assert CPU port conditions for SNB+ */
2077 }
2078
2079 reg = PIPECONF(cpu_transcoder);
2080 val = I915_READ(reg);
2081 if (val & PIPECONF_ENABLE) {
2082 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2083 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2084 return;
2085 }
2086
2087 I915_WRITE(reg, val | PIPECONF_ENABLE);
2088 POSTING_READ(reg);
2089 }
2090
2091 /**
2092 * intel_disable_pipe - disable a pipe, asserting requirements
2093 * @crtc: crtc whose pipes is to be disabled
2094 *
2095 * Disable the pipe of @crtc, making sure that various hardware
2096 * specific requirements are met, if applicable, e.g. plane
2097 * disabled, panel fitter off, etc.
2098 *
2099 * Will wait until the pipe has shut down before returning.
2100 */
2101 static void intel_disable_pipe(struct intel_crtc *crtc)
2102 {
2103 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2104 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2105 enum pipe pipe = crtc->pipe;
2106 int reg;
2107 u32 val;
2108
2109 /*
2110 * Make sure planes won't keep trying to pump pixels to us,
2111 * or we might hang the display.
2112 */
2113 assert_planes_disabled(dev_priv, pipe);
2114 assert_cursor_disabled(dev_priv, pipe);
2115 assert_sprites_disabled(dev_priv, pipe);
2116
2117 reg = PIPECONF(cpu_transcoder);
2118 val = I915_READ(reg);
2119 if ((val & PIPECONF_ENABLE) == 0)
2120 return;
2121
2122 /*
2123 * Double wide has implications for planes
2124 * so best keep it disabled when not needed.
2125 */
2126 if (crtc->config->double_wide)
2127 val &= ~PIPECONF_DOUBLE_WIDE;
2128
2129 /* Don't disable pipe or pipe PLLs if needed */
2130 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2131 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2132 val &= ~PIPECONF_ENABLE;
2133
2134 I915_WRITE(reg, val);
2135 if ((val & PIPECONF_ENABLE) == 0)
2136 intel_wait_for_pipe_off(crtc);
2137 }
2138
2139 /*
2140 * Plane regs are double buffered, going from enabled->disabled needs a
2141 * trigger in order to latch. The display address reg provides this.
2142 */
2143 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2144 enum plane plane)
2145 {
2146 struct drm_device *dev = dev_priv->dev;
2147 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2148
2149 I915_WRITE(reg, I915_READ(reg));
2150 POSTING_READ(reg);
2151 }
2152
2153 /**
2154 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2155 * @plane: plane to be enabled
2156 * @crtc: crtc for the plane
2157 *
2158 * Enable @plane on @crtc, making sure that the pipe is running first.
2159 */
2160 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2161 struct drm_crtc *crtc)
2162 {
2163 struct drm_device *dev = plane->dev;
2164 struct drm_i915_private *dev_priv = dev->dev_private;
2165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2166
2167 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170 if (intel_crtc->primary_enabled)
2171 return;
2172
2173 intel_crtc->primary_enabled = true;
2174
2175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
2177
2178 /*
2179 * BDW signals flip done immediately if the plane
2180 * is disabled, even if the plane enable is already
2181 * armed to occur at the next vblank :(
2182 */
2183 if (IS_BROADWELL(dev))
2184 intel_wait_for_vblank(dev, intel_crtc->pipe);
2185 }
2186
2187 /**
2188 * intel_disable_primary_hw_plane - disable the primary hardware plane
2189 * @plane: plane to be disabled
2190 * @crtc: crtc for the plane
2191 *
2192 * Disable @plane on @crtc, making sure that the pipe is running first.
2193 */
2194 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2195 struct drm_crtc *crtc)
2196 {
2197 struct drm_device *dev = plane->dev;
2198 struct drm_i915_private *dev_priv = dev->dev_private;
2199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2200
2201 if (WARN_ON(!intel_crtc->active))
2202 return;
2203
2204 if (!intel_crtc->primary_enabled)
2205 return;
2206
2207 intel_crtc->primary_enabled = false;
2208
2209 dev_priv->display.update_primary_plane(crtc, plane->fb,
2210 crtc->x, crtc->y);
2211 }
2212
2213 static bool need_vtd_wa(struct drm_device *dev)
2214 {
2215 #ifdef CONFIG_INTEL_IOMMU
2216 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2217 return true;
2218 #endif
2219 return false;
2220 }
2221
2222 int
2223 intel_fb_align_height(struct drm_device *dev, int height,
2224 uint32_t pixel_format,
2225 uint64_t fb_format_modifier)
2226 {
2227 int tile_height;
2228 uint32_t bits_per_pixel;
2229
2230 switch (fb_format_modifier) {
2231 case DRM_FORMAT_MOD_NONE:
2232 tile_height = 1;
2233 break;
2234 case I915_FORMAT_MOD_X_TILED:
2235 tile_height = IS_GEN2(dev) ? 16 : 8;
2236 break;
2237 case I915_FORMAT_MOD_Y_TILED:
2238 tile_height = 32;
2239 break;
2240 case I915_FORMAT_MOD_Yf_TILED:
2241 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2242 switch (bits_per_pixel) {
2243 default:
2244 case 8:
2245 tile_height = 64;
2246 break;
2247 case 16:
2248 case 32:
2249 tile_height = 32;
2250 break;
2251 case 64:
2252 tile_height = 16;
2253 break;
2254 case 128:
2255 WARN_ONCE(1,
2256 "128-bit pixels are not supported for display!");
2257 tile_height = 16;
2258 break;
2259 }
2260 break;
2261 default:
2262 MISSING_CASE(fb_format_modifier);
2263 tile_height = 1;
2264 break;
2265 }
2266
2267 return ALIGN(height, tile_height);
2268 }
2269
2270 int
2271 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2272 struct drm_framebuffer *fb,
2273 struct intel_engine_cs *pipelined)
2274 {
2275 struct drm_device *dev = fb->dev;
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2278 u32 alignment;
2279 int ret;
2280
2281 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2282
2283 switch (fb->modifier[0]) {
2284 case DRM_FORMAT_MOD_NONE:
2285 if (INTEL_INFO(dev)->gen >= 9)
2286 alignment = 256 * 1024;
2287 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2288 alignment = 128 * 1024;
2289 else if (INTEL_INFO(dev)->gen >= 4)
2290 alignment = 4 * 1024;
2291 else
2292 alignment = 64 * 1024;
2293 break;
2294 case I915_FORMAT_MOD_X_TILED:
2295 if (INTEL_INFO(dev)->gen >= 9)
2296 alignment = 256 * 1024;
2297 else {
2298 /* pin() will align the object as required by fence */
2299 alignment = 0;
2300 }
2301 break;
2302 case I915_FORMAT_MOD_Y_TILED:
2303 case I915_FORMAT_MOD_Yf_TILED:
2304 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2305 "Y tiling bo slipped through, driver bug!\n"))
2306 return -EINVAL;
2307 alignment = 1 * 1024 * 1024;
2308 break;
2309 default:
2310 MISSING_CASE(fb->modifier[0]);
2311 return -EINVAL;
2312 }
2313
2314 /* Note that the w/a also requires 64 PTE of padding following the
2315 * bo. We currently fill all unused PTE with the shadow page and so
2316 * we should always have valid PTE following the scanout preventing
2317 * the VT-d warning.
2318 */
2319 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2320 alignment = 256 * 1024;
2321
2322 /*
2323 * Global gtt pte registers are special registers which actually forward
2324 * writes to a chunk of system memory. Which means that there is no risk
2325 * that the register values disappear as soon as we call
2326 * intel_runtime_pm_put(), so it is correct to wrap only the
2327 * pin/unpin/fence and not more.
2328 */
2329 intel_runtime_pm_get(dev_priv);
2330
2331 dev_priv->mm.interruptible = false;
2332 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2333 if (ret)
2334 goto err_interruptible;
2335
2336 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2337 * fence, whereas 965+ only requires a fence if using
2338 * framebuffer compression. For simplicity, we always install
2339 * a fence as the cost is not that onerous.
2340 */
2341 ret = i915_gem_object_get_fence(obj);
2342 if (ret)
2343 goto err_unpin;
2344
2345 i915_gem_object_pin_fence(obj);
2346
2347 dev_priv->mm.interruptible = true;
2348 intel_runtime_pm_put(dev_priv);
2349 return 0;
2350
2351 err_unpin:
2352 i915_gem_object_unpin_from_display_plane(obj);
2353 err_interruptible:
2354 dev_priv->mm.interruptible = true;
2355 intel_runtime_pm_put(dev_priv);
2356 return ret;
2357 }
2358
2359 static void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2360 {
2361 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2362
2363 i915_gem_object_unpin_fence(obj);
2364 i915_gem_object_unpin_from_display_plane(obj);
2365 }
2366
2367 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2368 * is assumed to be a power-of-two. */
2369 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2370 unsigned int tiling_mode,
2371 unsigned int cpp,
2372 unsigned int pitch)
2373 {
2374 if (tiling_mode != I915_TILING_NONE) {
2375 unsigned int tile_rows, tiles;
2376
2377 tile_rows = *y / 8;
2378 *y %= 8;
2379
2380 tiles = *x / (512/cpp);
2381 *x %= 512/cpp;
2382
2383 return tile_rows * pitch * 8 + tiles * 4096;
2384 } else {
2385 unsigned int offset;
2386
2387 offset = *y * pitch + *x * cpp;
2388 *y = 0;
2389 *x = (offset & 4095) / cpp;
2390 return offset & -4096;
2391 }
2392 }
2393
2394 static int i9xx_format_to_fourcc(int format)
2395 {
2396 switch (format) {
2397 case DISPPLANE_8BPP:
2398 return DRM_FORMAT_C8;
2399 case DISPPLANE_BGRX555:
2400 return DRM_FORMAT_XRGB1555;
2401 case DISPPLANE_BGRX565:
2402 return DRM_FORMAT_RGB565;
2403 default:
2404 case DISPPLANE_BGRX888:
2405 return DRM_FORMAT_XRGB8888;
2406 case DISPPLANE_RGBX888:
2407 return DRM_FORMAT_XBGR8888;
2408 case DISPPLANE_BGRX101010:
2409 return DRM_FORMAT_XRGB2101010;
2410 case DISPPLANE_RGBX101010:
2411 return DRM_FORMAT_XBGR2101010;
2412 }
2413 }
2414
2415 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2416 {
2417 switch (format) {
2418 case PLANE_CTL_FORMAT_RGB_565:
2419 return DRM_FORMAT_RGB565;
2420 default:
2421 case PLANE_CTL_FORMAT_XRGB_8888:
2422 if (rgb_order) {
2423 if (alpha)
2424 return DRM_FORMAT_ABGR8888;
2425 else
2426 return DRM_FORMAT_XBGR8888;
2427 } else {
2428 if (alpha)
2429 return DRM_FORMAT_ARGB8888;
2430 else
2431 return DRM_FORMAT_XRGB8888;
2432 }
2433 case PLANE_CTL_FORMAT_XRGB_2101010:
2434 if (rgb_order)
2435 return DRM_FORMAT_XBGR2101010;
2436 else
2437 return DRM_FORMAT_XRGB2101010;
2438 }
2439 }
2440
2441 static bool
2442 intel_alloc_plane_obj(struct intel_crtc *crtc,
2443 struct intel_initial_plane_config *plane_config)
2444 {
2445 struct drm_device *dev = crtc->base.dev;
2446 struct drm_i915_gem_object *obj = NULL;
2447 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2448 struct drm_framebuffer *fb = &plane_config->fb->base;
2449 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2450 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2451 PAGE_SIZE);
2452
2453 size_aligned -= base_aligned;
2454
2455 if (plane_config->size == 0)
2456 return false;
2457
2458 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2459 base_aligned,
2460 base_aligned,
2461 size_aligned);
2462 if (!obj)
2463 return false;
2464
2465 obj->tiling_mode = plane_config->tiling;
2466 if (obj->tiling_mode == I915_TILING_X)
2467 obj->stride = fb->pitches[0];
2468
2469 mode_cmd.pixel_format = fb->pixel_format;
2470 mode_cmd.width = fb->width;
2471 mode_cmd.height = fb->height;
2472 mode_cmd.pitches[0] = fb->pitches[0];
2473 mode_cmd.modifier[0] = fb->modifier[0];
2474 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2475
2476 mutex_lock(&dev->struct_mutex);
2477
2478 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2479 &mode_cmd, obj)) {
2480 DRM_DEBUG_KMS("intel fb init failed\n");
2481 goto out_unref_obj;
2482 }
2483
2484 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2485 mutex_unlock(&dev->struct_mutex);
2486
2487 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2488 return true;
2489
2490 out_unref_obj:
2491 drm_gem_object_unreference(&obj->base);
2492 mutex_unlock(&dev->struct_mutex);
2493 return false;
2494 }
2495
2496 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2497 static void
2498 update_state_fb(struct drm_plane *plane)
2499 {
2500 if (plane->fb == plane->state->fb)
2501 return;
2502
2503 if (plane->state->fb)
2504 drm_framebuffer_unreference(plane->state->fb);
2505 plane->state->fb = plane->fb;
2506 if (plane->state->fb)
2507 drm_framebuffer_reference(plane->state->fb);
2508 }
2509
2510 static void
2511 intel_find_plane_obj(struct intel_crtc *intel_crtc,
2512 struct intel_initial_plane_config *plane_config)
2513 {
2514 struct drm_device *dev = intel_crtc->base.dev;
2515 struct drm_i915_private *dev_priv = dev->dev_private;
2516 struct drm_crtc *c;
2517 struct intel_crtc *i;
2518 struct drm_i915_gem_object *obj;
2519
2520 if (!plane_config->fb)
2521 return;
2522
2523 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
2524 struct drm_plane *primary = intel_crtc->base.primary;
2525
2526 primary->fb = &plane_config->fb->base;
2527 primary->state->crtc = &intel_crtc->base;
2528 update_state_fb(primary);
2529
2530 return;
2531 }
2532
2533 kfree(plane_config->fb);
2534
2535 /*
2536 * Failed to alloc the obj, check to see if we should share
2537 * an fb with another CRTC instead
2538 */
2539 for_each_crtc(dev, c) {
2540 i = to_intel_crtc(c);
2541
2542 if (c == &intel_crtc->base)
2543 continue;
2544
2545 if (!i->active)
2546 continue;
2547
2548 obj = intel_fb_obj(c->primary->fb);
2549 if (obj == NULL)
2550 continue;
2551
2552 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2553 struct drm_plane *primary = intel_crtc->base.primary;
2554
2555 if (obj->tiling_mode != I915_TILING_NONE)
2556 dev_priv->preserve_bios_swizzle = true;
2557
2558 drm_framebuffer_reference(c->primary->fb);
2559 primary->fb = c->primary->fb;
2560 primary->state->crtc = &intel_crtc->base;
2561 update_state_fb(intel_crtc->base.primary);
2562 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2563 break;
2564 }
2565 }
2566 }
2567
2568 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2569 struct drm_framebuffer *fb,
2570 int x, int y)
2571 {
2572 struct drm_device *dev = crtc->dev;
2573 struct drm_i915_private *dev_priv = dev->dev_private;
2574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2575 struct drm_i915_gem_object *obj;
2576 int plane = intel_crtc->plane;
2577 unsigned long linear_offset;
2578 u32 dspcntr;
2579 u32 reg = DSPCNTR(plane);
2580 int pixel_size;
2581
2582 if (!intel_crtc->primary_enabled) {
2583 I915_WRITE(reg, 0);
2584 if (INTEL_INFO(dev)->gen >= 4)
2585 I915_WRITE(DSPSURF(plane), 0);
2586 else
2587 I915_WRITE(DSPADDR(plane), 0);
2588 POSTING_READ(reg);
2589 return;
2590 }
2591
2592 obj = intel_fb_obj(fb);
2593 if (WARN_ON(obj == NULL))
2594 return;
2595
2596 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2597
2598 dspcntr = DISPPLANE_GAMMA_ENABLE;
2599
2600 dspcntr |= DISPLAY_PLANE_ENABLE;
2601
2602 if (INTEL_INFO(dev)->gen < 4) {
2603 if (intel_crtc->pipe == PIPE_B)
2604 dspcntr |= DISPPLANE_SEL_PIPE_B;
2605
2606 /* pipesrc and dspsize control the size that is scaled from,
2607 * which should always be the user's requested size.
2608 */
2609 I915_WRITE(DSPSIZE(plane),
2610 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2611 (intel_crtc->config->pipe_src_w - 1));
2612 I915_WRITE(DSPPOS(plane), 0);
2613 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2614 I915_WRITE(PRIMSIZE(plane),
2615 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2616 (intel_crtc->config->pipe_src_w - 1));
2617 I915_WRITE(PRIMPOS(plane), 0);
2618 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2619 }
2620
2621 switch (fb->pixel_format) {
2622 case DRM_FORMAT_C8:
2623 dspcntr |= DISPPLANE_8BPP;
2624 break;
2625 case DRM_FORMAT_XRGB1555:
2626 case DRM_FORMAT_ARGB1555:
2627 dspcntr |= DISPPLANE_BGRX555;
2628 break;
2629 case DRM_FORMAT_RGB565:
2630 dspcntr |= DISPPLANE_BGRX565;
2631 break;
2632 case DRM_FORMAT_XRGB8888:
2633 case DRM_FORMAT_ARGB8888:
2634 dspcntr |= DISPPLANE_BGRX888;
2635 break;
2636 case DRM_FORMAT_XBGR8888:
2637 case DRM_FORMAT_ABGR8888:
2638 dspcntr |= DISPPLANE_RGBX888;
2639 break;
2640 case DRM_FORMAT_XRGB2101010:
2641 case DRM_FORMAT_ARGB2101010:
2642 dspcntr |= DISPPLANE_BGRX101010;
2643 break;
2644 case DRM_FORMAT_XBGR2101010:
2645 case DRM_FORMAT_ABGR2101010:
2646 dspcntr |= DISPPLANE_RGBX101010;
2647 break;
2648 default:
2649 BUG();
2650 }
2651
2652 if (INTEL_INFO(dev)->gen >= 4 &&
2653 obj->tiling_mode != I915_TILING_NONE)
2654 dspcntr |= DISPPLANE_TILED;
2655
2656 if (IS_G4X(dev))
2657 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2658
2659 linear_offset = y * fb->pitches[0] + x * pixel_size;
2660
2661 if (INTEL_INFO(dev)->gen >= 4) {
2662 intel_crtc->dspaddr_offset =
2663 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2664 pixel_size,
2665 fb->pitches[0]);
2666 linear_offset -= intel_crtc->dspaddr_offset;
2667 } else {
2668 intel_crtc->dspaddr_offset = linear_offset;
2669 }
2670
2671 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2672 dspcntr |= DISPPLANE_ROTATE_180;
2673
2674 x += (intel_crtc->config->pipe_src_w - 1);
2675 y += (intel_crtc->config->pipe_src_h - 1);
2676
2677 /* Finding the last pixel of the last line of the display
2678 data and adding to linear_offset*/
2679 linear_offset +=
2680 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2681 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2682 }
2683
2684 I915_WRITE(reg, dspcntr);
2685
2686 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2687 if (INTEL_INFO(dev)->gen >= 4) {
2688 I915_WRITE(DSPSURF(plane),
2689 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2690 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2691 I915_WRITE(DSPLINOFF(plane), linear_offset);
2692 } else
2693 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2694 POSTING_READ(reg);
2695 }
2696
2697 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2698 struct drm_framebuffer *fb,
2699 int x, int y)
2700 {
2701 struct drm_device *dev = crtc->dev;
2702 struct drm_i915_private *dev_priv = dev->dev_private;
2703 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2704 struct drm_i915_gem_object *obj;
2705 int plane = intel_crtc->plane;
2706 unsigned long linear_offset;
2707 u32 dspcntr;
2708 u32 reg = DSPCNTR(plane);
2709 int pixel_size;
2710
2711 if (!intel_crtc->primary_enabled) {
2712 I915_WRITE(reg, 0);
2713 I915_WRITE(DSPSURF(plane), 0);
2714 POSTING_READ(reg);
2715 return;
2716 }
2717
2718 obj = intel_fb_obj(fb);
2719 if (WARN_ON(obj == NULL))
2720 return;
2721
2722 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2723
2724 dspcntr = DISPPLANE_GAMMA_ENABLE;
2725
2726 dspcntr |= DISPLAY_PLANE_ENABLE;
2727
2728 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2729 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2730
2731 switch (fb->pixel_format) {
2732 case DRM_FORMAT_C8:
2733 dspcntr |= DISPPLANE_8BPP;
2734 break;
2735 case DRM_FORMAT_RGB565:
2736 dspcntr |= DISPPLANE_BGRX565;
2737 break;
2738 case DRM_FORMAT_XRGB8888:
2739 case DRM_FORMAT_ARGB8888:
2740 dspcntr |= DISPPLANE_BGRX888;
2741 break;
2742 case DRM_FORMAT_XBGR8888:
2743 case DRM_FORMAT_ABGR8888:
2744 dspcntr |= DISPPLANE_RGBX888;
2745 break;
2746 case DRM_FORMAT_XRGB2101010:
2747 case DRM_FORMAT_ARGB2101010:
2748 dspcntr |= DISPPLANE_BGRX101010;
2749 break;
2750 case DRM_FORMAT_XBGR2101010:
2751 case DRM_FORMAT_ABGR2101010:
2752 dspcntr |= DISPPLANE_RGBX101010;
2753 break;
2754 default:
2755 BUG();
2756 }
2757
2758 if (obj->tiling_mode != I915_TILING_NONE)
2759 dspcntr |= DISPPLANE_TILED;
2760
2761 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2762 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2763
2764 linear_offset = y * fb->pitches[0] + x * pixel_size;
2765 intel_crtc->dspaddr_offset =
2766 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2767 pixel_size,
2768 fb->pitches[0]);
2769 linear_offset -= intel_crtc->dspaddr_offset;
2770 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2771 dspcntr |= DISPPLANE_ROTATE_180;
2772
2773 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2774 x += (intel_crtc->config->pipe_src_w - 1);
2775 y += (intel_crtc->config->pipe_src_h - 1);
2776
2777 /* Finding the last pixel of the last line of the display
2778 data and adding to linear_offset*/
2779 linear_offset +=
2780 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2781 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2782 }
2783 }
2784
2785 I915_WRITE(reg, dspcntr);
2786
2787 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2788 I915_WRITE(DSPSURF(plane),
2789 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2790 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2791 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2792 } else {
2793 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2794 I915_WRITE(DSPLINOFF(plane), linear_offset);
2795 }
2796 POSTING_READ(reg);
2797 }
2798
2799 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2800 uint32_t pixel_format)
2801 {
2802 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2803
2804 /*
2805 * The stride is either expressed as a multiple of 64 bytes
2806 * chunks for linear buffers or in number of tiles for tiled
2807 * buffers.
2808 */
2809 switch (fb_modifier) {
2810 case DRM_FORMAT_MOD_NONE:
2811 return 64;
2812 case I915_FORMAT_MOD_X_TILED:
2813 if (INTEL_INFO(dev)->gen == 2)
2814 return 128;
2815 return 512;
2816 case I915_FORMAT_MOD_Y_TILED:
2817 /* No need to check for old gens and Y tiling since this is
2818 * about the display engine and those will be blocked before
2819 * we get here.
2820 */
2821 return 128;
2822 case I915_FORMAT_MOD_Yf_TILED:
2823 if (bits_per_pixel == 8)
2824 return 64;
2825 else
2826 return 128;
2827 default:
2828 MISSING_CASE(fb_modifier);
2829 return 64;
2830 }
2831 }
2832
2833 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2834 struct drm_framebuffer *fb,
2835 int x, int y)
2836 {
2837 struct drm_device *dev = crtc->dev;
2838 struct drm_i915_private *dev_priv = dev->dev_private;
2839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2840 struct drm_i915_gem_object *obj;
2841 int pipe = intel_crtc->pipe;
2842 u32 plane_ctl, stride_div;
2843
2844 if (!intel_crtc->primary_enabled) {
2845 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2846 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2847 POSTING_READ(PLANE_CTL(pipe, 0));
2848 return;
2849 }
2850
2851 plane_ctl = PLANE_CTL_ENABLE |
2852 PLANE_CTL_PIPE_GAMMA_ENABLE |
2853 PLANE_CTL_PIPE_CSC_ENABLE;
2854
2855 switch (fb->pixel_format) {
2856 case DRM_FORMAT_RGB565:
2857 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2858 break;
2859 case DRM_FORMAT_XRGB8888:
2860 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2861 break;
2862 case DRM_FORMAT_ARGB8888:
2863 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2864 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2865 break;
2866 case DRM_FORMAT_XBGR8888:
2867 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2868 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2869 break;
2870 case DRM_FORMAT_ABGR8888:
2871 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2872 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2873 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2874 break;
2875 case DRM_FORMAT_XRGB2101010:
2876 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2877 break;
2878 case DRM_FORMAT_XBGR2101010:
2879 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2880 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2881 break;
2882 default:
2883 BUG();
2884 }
2885
2886 switch (fb->modifier[0]) {
2887 case DRM_FORMAT_MOD_NONE:
2888 break;
2889 case I915_FORMAT_MOD_X_TILED:
2890 plane_ctl |= PLANE_CTL_TILED_X;
2891 break;
2892 case I915_FORMAT_MOD_Y_TILED:
2893 plane_ctl |= PLANE_CTL_TILED_Y;
2894 break;
2895 case I915_FORMAT_MOD_Yf_TILED:
2896 plane_ctl |= PLANE_CTL_TILED_YF;
2897 break;
2898 default:
2899 MISSING_CASE(fb->modifier[0]);
2900 }
2901
2902 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2903 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
2904 plane_ctl |= PLANE_CTL_ROTATE_180;
2905
2906 obj = intel_fb_obj(fb);
2907 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2908 fb->pixel_format);
2909
2910 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2911
2912 I915_WRITE(PLANE_POS(pipe, 0), 0);
2913 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2914 I915_WRITE(PLANE_SIZE(pipe, 0),
2915 (intel_crtc->config->pipe_src_h - 1) << 16 |
2916 (intel_crtc->config->pipe_src_w - 1));
2917 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
2918 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2919
2920 POSTING_READ(PLANE_SURF(pipe, 0));
2921 }
2922
2923 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2924 static int
2925 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2926 int x, int y, enum mode_set_atomic state)
2927 {
2928 struct drm_device *dev = crtc->dev;
2929 struct drm_i915_private *dev_priv = dev->dev_private;
2930
2931 if (dev_priv->display.disable_fbc)
2932 dev_priv->display.disable_fbc(dev);
2933
2934 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2935
2936 return 0;
2937 }
2938
2939 static void intel_complete_page_flips(struct drm_device *dev)
2940 {
2941 struct drm_crtc *crtc;
2942
2943 for_each_crtc(dev, crtc) {
2944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2945 enum plane plane = intel_crtc->plane;
2946
2947 intel_prepare_page_flip(dev, plane);
2948 intel_finish_page_flip_plane(dev, plane);
2949 }
2950 }
2951
2952 static void intel_update_primary_planes(struct drm_device *dev)
2953 {
2954 struct drm_i915_private *dev_priv = dev->dev_private;
2955 struct drm_crtc *crtc;
2956
2957 for_each_crtc(dev, crtc) {
2958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2959
2960 drm_modeset_lock(&crtc->mutex, NULL);
2961 /*
2962 * FIXME: Once we have proper support for primary planes (and
2963 * disabling them without disabling the entire crtc) allow again
2964 * a NULL crtc->primary->fb.
2965 */
2966 if (intel_crtc->active && crtc->primary->fb)
2967 dev_priv->display.update_primary_plane(crtc,
2968 crtc->primary->fb,
2969 crtc->x,
2970 crtc->y);
2971 drm_modeset_unlock(&crtc->mutex);
2972 }
2973 }
2974
2975 void intel_prepare_reset(struct drm_device *dev)
2976 {
2977 struct drm_i915_private *dev_priv = to_i915(dev);
2978 struct intel_crtc *crtc;
2979
2980 /* no reset support for gen2 */
2981 if (IS_GEN2(dev))
2982 return;
2983
2984 /* reset doesn't touch the display */
2985 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
2986 return;
2987
2988 drm_modeset_lock_all(dev);
2989
2990 /*
2991 * Disabling the crtcs gracefully seems nicer. Also the
2992 * g33 docs say we should at least disable all the planes.
2993 */
2994 for_each_intel_crtc(dev, crtc) {
2995 if (crtc->active)
2996 dev_priv->display.crtc_disable(&crtc->base);
2997 }
2998 }
2999
3000 void intel_finish_reset(struct drm_device *dev)
3001 {
3002 struct drm_i915_private *dev_priv = to_i915(dev);
3003
3004 /*
3005 * Flips in the rings will be nuked by the reset,
3006 * so complete all pending flips so that user space
3007 * will get its events and not get stuck.
3008 */
3009 intel_complete_page_flips(dev);
3010
3011 /* no reset support for gen2 */
3012 if (IS_GEN2(dev))
3013 return;
3014
3015 /* reset doesn't touch the display */
3016 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3017 /*
3018 * Flips in the rings have been nuked by the reset,
3019 * so update the base address of all primary
3020 * planes to the the last fb to make sure we're
3021 * showing the correct fb after a reset.
3022 */
3023 intel_update_primary_planes(dev);
3024 return;
3025 }
3026
3027 /*
3028 * The display has been reset as well,
3029 * so need a full re-initialization.
3030 */
3031 intel_runtime_pm_disable_interrupts(dev_priv);
3032 intel_runtime_pm_enable_interrupts(dev_priv);
3033
3034 intel_modeset_init_hw(dev);
3035
3036 spin_lock_irq(&dev_priv->irq_lock);
3037 if (dev_priv->display.hpd_irq_setup)
3038 dev_priv->display.hpd_irq_setup(dev);
3039 spin_unlock_irq(&dev_priv->irq_lock);
3040
3041 intel_modeset_setup_hw_state(dev, true);
3042
3043 intel_hpd_init(dev_priv);
3044
3045 drm_modeset_unlock_all(dev);
3046 }
3047
3048 static int
3049 intel_finish_fb(struct drm_framebuffer *old_fb)
3050 {
3051 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3052 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3053 bool was_interruptible = dev_priv->mm.interruptible;
3054 int ret;
3055
3056 /* Big Hammer, we also need to ensure that any pending
3057 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3058 * current scanout is retired before unpinning the old
3059 * framebuffer.
3060 *
3061 * This should only fail upon a hung GPU, in which case we
3062 * can safely continue.
3063 */
3064 dev_priv->mm.interruptible = false;
3065 ret = i915_gem_object_finish_gpu(obj);
3066 dev_priv->mm.interruptible = was_interruptible;
3067
3068 return ret;
3069 }
3070
3071 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3072 {
3073 struct drm_device *dev = crtc->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076 bool pending;
3077
3078 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3079 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3080 return false;
3081
3082 spin_lock_irq(&dev->event_lock);
3083 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3084 spin_unlock_irq(&dev->event_lock);
3085
3086 return pending;
3087 }
3088
3089 static void intel_update_pipe_size(struct intel_crtc *crtc)
3090 {
3091 struct drm_device *dev = crtc->base.dev;
3092 struct drm_i915_private *dev_priv = dev->dev_private;
3093 const struct drm_display_mode *adjusted_mode;
3094
3095 if (!i915.fastboot)
3096 return;
3097
3098 /*
3099 * Update pipe size and adjust fitter if needed: the reason for this is
3100 * that in compute_mode_changes we check the native mode (not the pfit
3101 * mode) to see if we can flip rather than do a full mode set. In the
3102 * fastboot case, we'll flip, but if we don't update the pipesrc and
3103 * pfit state, we'll end up with a big fb scanned out into the wrong
3104 * sized surface.
3105 *
3106 * To fix this properly, we need to hoist the checks up into
3107 * compute_mode_changes (or above), check the actual pfit state and
3108 * whether the platform allows pfit disable with pipe active, and only
3109 * then update the pipesrc and pfit state, even on the flip path.
3110 */
3111
3112 adjusted_mode = &crtc->config->base.adjusted_mode;
3113
3114 I915_WRITE(PIPESRC(crtc->pipe),
3115 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3116 (adjusted_mode->crtc_vdisplay - 1));
3117 if (!crtc->config->pch_pfit.enabled &&
3118 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3119 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3120 I915_WRITE(PF_CTL(crtc->pipe), 0);
3121 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3122 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3123 }
3124 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3125 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3126 }
3127
3128 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3129 {
3130 struct drm_device *dev = crtc->dev;
3131 struct drm_i915_private *dev_priv = dev->dev_private;
3132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133 int pipe = intel_crtc->pipe;
3134 u32 reg, temp;
3135
3136 /* enable normal train */
3137 reg = FDI_TX_CTL(pipe);
3138 temp = I915_READ(reg);
3139 if (IS_IVYBRIDGE(dev)) {
3140 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3141 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3142 } else {
3143 temp &= ~FDI_LINK_TRAIN_NONE;
3144 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3145 }
3146 I915_WRITE(reg, temp);
3147
3148 reg = FDI_RX_CTL(pipe);
3149 temp = I915_READ(reg);
3150 if (HAS_PCH_CPT(dev)) {
3151 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3152 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3153 } else {
3154 temp &= ~FDI_LINK_TRAIN_NONE;
3155 temp |= FDI_LINK_TRAIN_NONE;
3156 }
3157 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3158
3159 /* wait one idle pattern time */
3160 POSTING_READ(reg);
3161 udelay(1000);
3162
3163 /* IVB wants error correction enabled */
3164 if (IS_IVYBRIDGE(dev))
3165 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3166 FDI_FE_ERRC_ENABLE);
3167 }
3168
3169 /* The FDI link training functions for ILK/Ibexpeak. */
3170 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3171 {
3172 struct drm_device *dev = crtc->dev;
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3175 int pipe = intel_crtc->pipe;
3176 u32 reg, temp, tries;
3177
3178 /* FDI needs bits from pipe first */
3179 assert_pipe_enabled(dev_priv, pipe);
3180
3181 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3182 for train result */
3183 reg = FDI_RX_IMR(pipe);
3184 temp = I915_READ(reg);
3185 temp &= ~FDI_RX_SYMBOL_LOCK;
3186 temp &= ~FDI_RX_BIT_LOCK;
3187 I915_WRITE(reg, temp);
3188 I915_READ(reg);
3189 udelay(150);
3190
3191 /* enable CPU FDI TX and PCH FDI RX */
3192 reg = FDI_TX_CTL(pipe);
3193 temp = I915_READ(reg);
3194 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3195 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3196 temp &= ~FDI_LINK_TRAIN_NONE;
3197 temp |= FDI_LINK_TRAIN_PATTERN_1;
3198 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3199
3200 reg = FDI_RX_CTL(pipe);
3201 temp = I915_READ(reg);
3202 temp &= ~FDI_LINK_TRAIN_NONE;
3203 temp |= FDI_LINK_TRAIN_PATTERN_1;
3204 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3205
3206 POSTING_READ(reg);
3207 udelay(150);
3208
3209 /* Ironlake workaround, enable clock pointer after FDI enable*/
3210 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3211 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3212 FDI_RX_PHASE_SYNC_POINTER_EN);
3213
3214 reg = FDI_RX_IIR(pipe);
3215 for (tries = 0; tries < 5; tries++) {
3216 temp = I915_READ(reg);
3217 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3218
3219 if ((temp & FDI_RX_BIT_LOCK)) {
3220 DRM_DEBUG_KMS("FDI train 1 done.\n");
3221 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3222 break;
3223 }
3224 }
3225 if (tries == 5)
3226 DRM_ERROR("FDI train 1 fail!\n");
3227
3228 /* Train 2 */
3229 reg = FDI_TX_CTL(pipe);
3230 temp = I915_READ(reg);
3231 temp &= ~FDI_LINK_TRAIN_NONE;
3232 temp |= FDI_LINK_TRAIN_PATTERN_2;
3233 I915_WRITE(reg, temp);
3234
3235 reg = FDI_RX_CTL(pipe);
3236 temp = I915_READ(reg);
3237 temp &= ~FDI_LINK_TRAIN_NONE;
3238 temp |= FDI_LINK_TRAIN_PATTERN_2;
3239 I915_WRITE(reg, temp);
3240
3241 POSTING_READ(reg);
3242 udelay(150);
3243
3244 reg = FDI_RX_IIR(pipe);
3245 for (tries = 0; tries < 5; tries++) {
3246 temp = I915_READ(reg);
3247 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3248
3249 if (temp & FDI_RX_SYMBOL_LOCK) {
3250 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3251 DRM_DEBUG_KMS("FDI train 2 done.\n");
3252 break;
3253 }
3254 }
3255 if (tries == 5)
3256 DRM_ERROR("FDI train 2 fail!\n");
3257
3258 DRM_DEBUG_KMS("FDI train done\n");
3259
3260 }
3261
3262 static const int snb_b_fdi_train_param[] = {
3263 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3264 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3265 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3266 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3267 };
3268
3269 /* The FDI link training functions for SNB/Cougarpoint. */
3270 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3271 {
3272 struct drm_device *dev = crtc->dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3275 int pipe = intel_crtc->pipe;
3276 u32 reg, temp, i, retry;
3277
3278 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3279 for train result */
3280 reg = FDI_RX_IMR(pipe);
3281 temp = I915_READ(reg);
3282 temp &= ~FDI_RX_SYMBOL_LOCK;
3283 temp &= ~FDI_RX_BIT_LOCK;
3284 I915_WRITE(reg, temp);
3285
3286 POSTING_READ(reg);
3287 udelay(150);
3288
3289 /* enable CPU FDI TX and PCH FDI RX */
3290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3293 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3294 temp &= ~FDI_LINK_TRAIN_NONE;
3295 temp |= FDI_LINK_TRAIN_PATTERN_1;
3296 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3297 /* SNB-B */
3298 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3299 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3300
3301 I915_WRITE(FDI_RX_MISC(pipe),
3302 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3303
3304 reg = FDI_RX_CTL(pipe);
3305 temp = I915_READ(reg);
3306 if (HAS_PCH_CPT(dev)) {
3307 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3308 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3309 } else {
3310 temp &= ~FDI_LINK_TRAIN_NONE;
3311 temp |= FDI_LINK_TRAIN_PATTERN_1;
3312 }
3313 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3314
3315 POSTING_READ(reg);
3316 udelay(150);
3317
3318 for (i = 0; i < 4; i++) {
3319 reg = FDI_TX_CTL(pipe);
3320 temp = I915_READ(reg);
3321 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3322 temp |= snb_b_fdi_train_param[i];
3323 I915_WRITE(reg, temp);
3324
3325 POSTING_READ(reg);
3326 udelay(500);
3327
3328 for (retry = 0; retry < 5; retry++) {
3329 reg = FDI_RX_IIR(pipe);
3330 temp = I915_READ(reg);
3331 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3332 if (temp & FDI_RX_BIT_LOCK) {
3333 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3334 DRM_DEBUG_KMS("FDI train 1 done.\n");
3335 break;
3336 }
3337 udelay(50);
3338 }
3339 if (retry < 5)
3340 break;
3341 }
3342 if (i == 4)
3343 DRM_ERROR("FDI train 1 fail!\n");
3344
3345 /* Train 2 */
3346 reg = FDI_TX_CTL(pipe);
3347 temp = I915_READ(reg);
3348 temp &= ~FDI_LINK_TRAIN_NONE;
3349 temp |= FDI_LINK_TRAIN_PATTERN_2;
3350 if (IS_GEN6(dev)) {
3351 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3352 /* SNB-B */
3353 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3354 }
3355 I915_WRITE(reg, temp);
3356
3357 reg = FDI_RX_CTL(pipe);
3358 temp = I915_READ(reg);
3359 if (HAS_PCH_CPT(dev)) {
3360 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3361 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3362 } else {
3363 temp &= ~FDI_LINK_TRAIN_NONE;
3364 temp |= FDI_LINK_TRAIN_PATTERN_2;
3365 }
3366 I915_WRITE(reg, temp);
3367
3368 POSTING_READ(reg);
3369 udelay(150);
3370
3371 for (i = 0; i < 4; i++) {
3372 reg = FDI_TX_CTL(pipe);
3373 temp = I915_READ(reg);
3374 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3375 temp |= snb_b_fdi_train_param[i];
3376 I915_WRITE(reg, temp);
3377
3378 POSTING_READ(reg);
3379 udelay(500);
3380
3381 for (retry = 0; retry < 5; retry++) {
3382 reg = FDI_RX_IIR(pipe);
3383 temp = I915_READ(reg);
3384 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3385 if (temp & FDI_RX_SYMBOL_LOCK) {
3386 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3387 DRM_DEBUG_KMS("FDI train 2 done.\n");
3388 break;
3389 }
3390 udelay(50);
3391 }
3392 if (retry < 5)
3393 break;
3394 }
3395 if (i == 4)
3396 DRM_ERROR("FDI train 2 fail!\n");
3397
3398 DRM_DEBUG_KMS("FDI train done.\n");
3399 }
3400
3401 /* Manual link training for Ivy Bridge A0 parts */
3402 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3403 {
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3407 int pipe = intel_crtc->pipe;
3408 u32 reg, temp, i, j;
3409
3410 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3411 for train result */
3412 reg = FDI_RX_IMR(pipe);
3413 temp = I915_READ(reg);
3414 temp &= ~FDI_RX_SYMBOL_LOCK;
3415 temp &= ~FDI_RX_BIT_LOCK;
3416 I915_WRITE(reg, temp);
3417
3418 POSTING_READ(reg);
3419 udelay(150);
3420
3421 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3422 I915_READ(FDI_RX_IIR(pipe)));
3423
3424 /* Try each vswing and preemphasis setting twice before moving on */
3425 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3426 /* disable first in case we need to retry */
3427 reg = FDI_TX_CTL(pipe);
3428 temp = I915_READ(reg);
3429 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3430 temp &= ~FDI_TX_ENABLE;
3431 I915_WRITE(reg, temp);
3432
3433 reg = FDI_RX_CTL(pipe);
3434 temp = I915_READ(reg);
3435 temp &= ~FDI_LINK_TRAIN_AUTO;
3436 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3437 temp &= ~FDI_RX_ENABLE;
3438 I915_WRITE(reg, temp);
3439
3440 /* enable CPU FDI TX and PCH FDI RX */
3441 reg = FDI_TX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3444 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3445 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3446 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3447 temp |= snb_b_fdi_train_param[j/2];
3448 temp |= FDI_COMPOSITE_SYNC;
3449 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3450
3451 I915_WRITE(FDI_RX_MISC(pipe),
3452 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3453
3454 reg = FDI_RX_CTL(pipe);
3455 temp = I915_READ(reg);
3456 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3457 temp |= FDI_COMPOSITE_SYNC;
3458 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3459
3460 POSTING_READ(reg);
3461 udelay(1); /* should be 0.5us */
3462
3463 for (i = 0; i < 4; i++) {
3464 reg = FDI_RX_IIR(pipe);
3465 temp = I915_READ(reg);
3466 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3467
3468 if (temp & FDI_RX_BIT_LOCK ||
3469 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3470 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3471 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3472 i);
3473 break;
3474 }
3475 udelay(1); /* should be 0.5us */
3476 }
3477 if (i == 4) {
3478 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3479 continue;
3480 }
3481
3482 /* Train 2 */
3483 reg = FDI_TX_CTL(pipe);
3484 temp = I915_READ(reg);
3485 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3486 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3487 I915_WRITE(reg, temp);
3488
3489 reg = FDI_RX_CTL(pipe);
3490 temp = I915_READ(reg);
3491 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3492 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3493 I915_WRITE(reg, temp);
3494
3495 POSTING_READ(reg);
3496 udelay(2); /* should be 1.5us */
3497
3498 for (i = 0; i < 4; i++) {
3499 reg = FDI_RX_IIR(pipe);
3500 temp = I915_READ(reg);
3501 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3502
3503 if (temp & FDI_RX_SYMBOL_LOCK ||
3504 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3505 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3506 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3507 i);
3508 goto train_done;
3509 }
3510 udelay(2); /* should be 1.5us */
3511 }
3512 if (i == 4)
3513 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3514 }
3515
3516 train_done:
3517 DRM_DEBUG_KMS("FDI train done.\n");
3518 }
3519
3520 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3521 {
3522 struct drm_device *dev = intel_crtc->base.dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 int pipe = intel_crtc->pipe;
3525 u32 reg, temp;
3526
3527
3528 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3529 reg = FDI_RX_CTL(pipe);
3530 temp = I915_READ(reg);
3531 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3532 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3533 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3534 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3535
3536 POSTING_READ(reg);
3537 udelay(200);
3538
3539 /* Switch from Rawclk to PCDclk */
3540 temp = I915_READ(reg);
3541 I915_WRITE(reg, temp | FDI_PCDCLK);
3542
3543 POSTING_READ(reg);
3544 udelay(200);
3545
3546 /* Enable CPU FDI TX PLL, always on for Ironlake */
3547 reg = FDI_TX_CTL(pipe);
3548 temp = I915_READ(reg);
3549 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3550 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3551
3552 POSTING_READ(reg);
3553 udelay(100);
3554 }
3555 }
3556
3557 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3558 {
3559 struct drm_device *dev = intel_crtc->base.dev;
3560 struct drm_i915_private *dev_priv = dev->dev_private;
3561 int pipe = intel_crtc->pipe;
3562 u32 reg, temp;
3563
3564 /* Switch from PCDclk to Rawclk */
3565 reg = FDI_RX_CTL(pipe);
3566 temp = I915_READ(reg);
3567 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3568
3569 /* Disable CPU FDI TX PLL */
3570 reg = FDI_TX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3573
3574 POSTING_READ(reg);
3575 udelay(100);
3576
3577 reg = FDI_RX_CTL(pipe);
3578 temp = I915_READ(reg);
3579 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3580
3581 /* Wait for the clocks to turn off. */
3582 POSTING_READ(reg);
3583 udelay(100);
3584 }
3585
3586 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3587 {
3588 struct drm_device *dev = crtc->dev;
3589 struct drm_i915_private *dev_priv = dev->dev_private;
3590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3591 int pipe = intel_crtc->pipe;
3592 u32 reg, temp;
3593
3594 /* disable CPU FDI tx and PCH FDI rx */
3595 reg = FDI_TX_CTL(pipe);
3596 temp = I915_READ(reg);
3597 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3598 POSTING_READ(reg);
3599
3600 reg = FDI_RX_CTL(pipe);
3601 temp = I915_READ(reg);
3602 temp &= ~(0x7 << 16);
3603 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3604 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3605
3606 POSTING_READ(reg);
3607 udelay(100);
3608
3609 /* Ironlake workaround, disable clock pointer after downing FDI */
3610 if (HAS_PCH_IBX(dev))
3611 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3612
3613 /* still set train pattern 1 */
3614 reg = FDI_TX_CTL(pipe);
3615 temp = I915_READ(reg);
3616 temp &= ~FDI_LINK_TRAIN_NONE;
3617 temp |= FDI_LINK_TRAIN_PATTERN_1;
3618 I915_WRITE(reg, temp);
3619
3620 reg = FDI_RX_CTL(pipe);
3621 temp = I915_READ(reg);
3622 if (HAS_PCH_CPT(dev)) {
3623 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3624 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3625 } else {
3626 temp &= ~FDI_LINK_TRAIN_NONE;
3627 temp |= FDI_LINK_TRAIN_PATTERN_1;
3628 }
3629 /* BPC in FDI rx is consistent with that in PIPECONF */
3630 temp &= ~(0x07 << 16);
3631 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3632 I915_WRITE(reg, temp);
3633
3634 POSTING_READ(reg);
3635 udelay(100);
3636 }
3637
3638 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3639 {
3640 struct intel_crtc *crtc;
3641
3642 /* Note that we don't need to be called with mode_config.lock here
3643 * as our list of CRTC objects is static for the lifetime of the
3644 * device and so cannot disappear as we iterate. Similarly, we can
3645 * happily treat the predicates as racy, atomic checks as userspace
3646 * cannot claim and pin a new fb without at least acquring the
3647 * struct_mutex and so serialising with us.
3648 */
3649 for_each_intel_crtc(dev, crtc) {
3650 if (atomic_read(&crtc->unpin_work_count) == 0)
3651 continue;
3652
3653 if (crtc->unpin_work)
3654 intel_wait_for_vblank(dev, crtc->pipe);
3655
3656 return true;
3657 }
3658
3659 return false;
3660 }
3661
3662 static void page_flip_completed(struct intel_crtc *intel_crtc)
3663 {
3664 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3665 struct intel_unpin_work *work = intel_crtc->unpin_work;
3666
3667 /* ensure that the unpin work is consistent wrt ->pending. */
3668 smp_rmb();
3669 intel_crtc->unpin_work = NULL;
3670
3671 if (work->event)
3672 drm_send_vblank_event(intel_crtc->base.dev,
3673 intel_crtc->pipe,
3674 work->event);
3675
3676 drm_crtc_vblank_put(&intel_crtc->base);
3677
3678 wake_up_all(&dev_priv->pending_flip_queue);
3679 queue_work(dev_priv->wq, &work->work);
3680
3681 trace_i915_flip_complete(intel_crtc->plane,
3682 work->pending_flip_obj);
3683 }
3684
3685 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3686 {
3687 struct drm_device *dev = crtc->dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689
3690 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3691 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3692 !intel_crtc_has_pending_flip(crtc),
3693 60*HZ) == 0)) {
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695
3696 spin_lock_irq(&dev->event_lock);
3697 if (intel_crtc->unpin_work) {
3698 WARN_ONCE(1, "Removing stuck page flip\n");
3699 page_flip_completed(intel_crtc);
3700 }
3701 spin_unlock_irq(&dev->event_lock);
3702 }
3703
3704 if (crtc->primary->fb) {
3705 mutex_lock(&dev->struct_mutex);
3706 intel_finish_fb(crtc->primary->fb);
3707 mutex_unlock(&dev->struct_mutex);
3708 }
3709 }
3710
3711 /* Program iCLKIP clock to the desired frequency */
3712 static void lpt_program_iclkip(struct drm_crtc *crtc)
3713 {
3714 struct drm_device *dev = crtc->dev;
3715 struct drm_i915_private *dev_priv = dev->dev_private;
3716 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3717 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3718 u32 temp;
3719
3720 mutex_lock(&dev_priv->dpio_lock);
3721
3722 /* It is necessary to ungate the pixclk gate prior to programming
3723 * the divisors, and gate it back when it is done.
3724 */
3725 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3726
3727 /* Disable SSCCTL */
3728 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3729 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3730 SBI_SSCCTL_DISABLE,
3731 SBI_ICLK);
3732
3733 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3734 if (clock == 20000) {
3735 auxdiv = 1;
3736 divsel = 0x41;
3737 phaseinc = 0x20;
3738 } else {
3739 /* The iCLK virtual clock root frequency is in MHz,
3740 * but the adjusted_mode->crtc_clock in in KHz. To get the
3741 * divisors, it is necessary to divide one by another, so we
3742 * convert the virtual clock precision to KHz here for higher
3743 * precision.
3744 */
3745 u32 iclk_virtual_root_freq = 172800 * 1000;
3746 u32 iclk_pi_range = 64;
3747 u32 desired_divisor, msb_divisor_value, pi_value;
3748
3749 desired_divisor = (iclk_virtual_root_freq / clock);
3750 msb_divisor_value = desired_divisor / iclk_pi_range;
3751 pi_value = desired_divisor % iclk_pi_range;
3752
3753 auxdiv = 0;
3754 divsel = msb_divisor_value - 2;
3755 phaseinc = pi_value;
3756 }
3757
3758 /* This should not happen with any sane values */
3759 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3760 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3761 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3762 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3763
3764 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3765 clock,
3766 auxdiv,
3767 divsel,
3768 phasedir,
3769 phaseinc);
3770
3771 /* Program SSCDIVINTPHASE6 */
3772 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3773 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3774 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3775 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3776 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3777 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3778 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3779 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3780
3781 /* Program SSCAUXDIV */
3782 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3783 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3784 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3785 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3786
3787 /* Enable modulator and associated divider */
3788 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3789 temp &= ~SBI_SSCCTL_DISABLE;
3790 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3791
3792 /* Wait for initialization time */
3793 udelay(24);
3794
3795 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3796
3797 mutex_unlock(&dev_priv->dpio_lock);
3798 }
3799
3800 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3801 enum pipe pch_transcoder)
3802 {
3803 struct drm_device *dev = crtc->base.dev;
3804 struct drm_i915_private *dev_priv = dev->dev_private;
3805 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
3806
3807 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3808 I915_READ(HTOTAL(cpu_transcoder)));
3809 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3810 I915_READ(HBLANK(cpu_transcoder)));
3811 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3812 I915_READ(HSYNC(cpu_transcoder)));
3813
3814 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3815 I915_READ(VTOTAL(cpu_transcoder)));
3816 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3817 I915_READ(VBLANK(cpu_transcoder)));
3818 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3819 I915_READ(VSYNC(cpu_transcoder)));
3820 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3821 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3822 }
3823
3824 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
3825 {
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 uint32_t temp;
3828
3829 temp = I915_READ(SOUTH_CHICKEN1);
3830 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
3831 return;
3832
3833 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3834 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3835
3836 temp &= ~FDI_BC_BIFURCATION_SELECT;
3837 if (enable)
3838 temp |= FDI_BC_BIFURCATION_SELECT;
3839
3840 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
3841 I915_WRITE(SOUTH_CHICKEN1, temp);
3842 POSTING_READ(SOUTH_CHICKEN1);
3843 }
3844
3845 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3846 {
3847 struct drm_device *dev = intel_crtc->base.dev;
3848
3849 switch (intel_crtc->pipe) {
3850 case PIPE_A:
3851 break;
3852 case PIPE_B:
3853 if (intel_crtc->config->fdi_lanes > 2)
3854 cpt_set_fdi_bc_bifurcation(dev, false);
3855 else
3856 cpt_set_fdi_bc_bifurcation(dev, true);
3857
3858 break;
3859 case PIPE_C:
3860 cpt_set_fdi_bc_bifurcation(dev, true);
3861
3862 break;
3863 default:
3864 BUG();
3865 }
3866 }
3867
3868 /*
3869 * Enable PCH resources required for PCH ports:
3870 * - PCH PLLs
3871 * - FDI training & RX/TX
3872 * - update transcoder timings
3873 * - DP transcoding bits
3874 * - transcoder
3875 */
3876 static void ironlake_pch_enable(struct drm_crtc *crtc)
3877 {
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3881 int pipe = intel_crtc->pipe;
3882 u32 reg, temp;
3883
3884 assert_pch_transcoder_disabled(dev_priv, pipe);
3885
3886 if (IS_IVYBRIDGE(dev))
3887 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3888
3889 /* Write the TU size bits before fdi link training, so that error
3890 * detection works. */
3891 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3892 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3893
3894 /* For PCH output, training FDI link */
3895 dev_priv->display.fdi_link_train(crtc);
3896
3897 /* We need to program the right clock selection before writing the pixel
3898 * mutliplier into the DPLL. */
3899 if (HAS_PCH_CPT(dev)) {
3900 u32 sel;
3901
3902 temp = I915_READ(PCH_DPLL_SEL);
3903 temp |= TRANS_DPLL_ENABLE(pipe);
3904 sel = TRANS_DPLLB_SEL(pipe);
3905 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
3906 temp |= sel;
3907 else
3908 temp &= ~sel;
3909 I915_WRITE(PCH_DPLL_SEL, temp);
3910 }
3911
3912 /* XXX: pch pll's can be enabled any time before we enable the PCH
3913 * transcoder, and we actually should do this to not upset any PCH
3914 * transcoder that already use the clock when we share it.
3915 *
3916 * Note that enable_shared_dpll tries to do the right thing, but
3917 * get_shared_dpll unconditionally resets the pll - we need that to have
3918 * the right LVDS enable sequence. */
3919 intel_enable_shared_dpll(intel_crtc);
3920
3921 /* set transcoder timing, panel must allow it */
3922 assert_panel_unlocked(dev_priv, pipe);
3923 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3924
3925 intel_fdi_normal_train(crtc);
3926
3927 /* For PCH DP, enable TRANS_DP_CTL */
3928 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
3929 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3930 reg = TRANS_DP_CTL(pipe);
3931 temp = I915_READ(reg);
3932 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3933 TRANS_DP_SYNC_MASK |
3934 TRANS_DP_BPC_MASK);
3935 temp |= (TRANS_DP_OUTPUT_ENABLE |
3936 TRANS_DP_ENH_FRAMING);
3937 temp |= bpc << 9; /* same format but at 11:9 */
3938
3939 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3940 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3941 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3942 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3943
3944 switch (intel_trans_dp_port_sel(crtc)) {
3945 case PCH_DP_B:
3946 temp |= TRANS_DP_PORT_SEL_B;
3947 break;
3948 case PCH_DP_C:
3949 temp |= TRANS_DP_PORT_SEL_C;
3950 break;
3951 case PCH_DP_D:
3952 temp |= TRANS_DP_PORT_SEL_D;
3953 break;
3954 default:
3955 BUG();
3956 }
3957
3958 I915_WRITE(reg, temp);
3959 }
3960
3961 ironlake_enable_pch_transcoder(dev_priv, pipe);
3962 }
3963
3964 static void lpt_pch_enable(struct drm_crtc *crtc)
3965 {
3966 struct drm_device *dev = crtc->dev;
3967 struct drm_i915_private *dev_priv = dev->dev_private;
3968 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3969 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
3970
3971 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3972
3973 lpt_program_iclkip(crtc);
3974
3975 /* Set transcoder timing. */
3976 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3977
3978 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3979 }
3980
3981 void intel_put_shared_dpll(struct intel_crtc *crtc)
3982 {
3983 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3984
3985 if (pll == NULL)
3986 return;
3987
3988 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3989 WARN(1, "bad %s crtc mask\n", pll->name);
3990 return;
3991 }
3992
3993 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3994 if (pll->config.crtc_mask == 0) {
3995 WARN_ON(pll->on);
3996 WARN_ON(pll->active);
3997 }
3998
3999 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4000 }
4001
4002 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4003 struct intel_crtc_state *crtc_state)
4004 {
4005 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4006 struct intel_shared_dpll *pll;
4007 enum intel_dpll_id i;
4008
4009 if (HAS_PCH_IBX(dev_priv->dev)) {
4010 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4011 i = (enum intel_dpll_id) crtc->pipe;
4012 pll = &dev_priv->shared_dplls[i];
4013
4014 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4015 crtc->base.base.id, pll->name);
4016
4017 WARN_ON(pll->new_config->crtc_mask);
4018
4019 goto found;
4020 }
4021
4022 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4023 pll = &dev_priv->shared_dplls[i];
4024
4025 /* Only want to check enabled timings first */
4026 if (pll->new_config->crtc_mask == 0)
4027 continue;
4028
4029 if (memcmp(&crtc_state->dpll_hw_state,
4030 &pll->new_config->hw_state,
4031 sizeof(pll->new_config->hw_state)) == 0) {
4032 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4033 crtc->base.base.id, pll->name,
4034 pll->new_config->crtc_mask,
4035 pll->active);
4036 goto found;
4037 }
4038 }
4039
4040 /* Ok no matching timings, maybe there's a free one? */
4041 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4042 pll = &dev_priv->shared_dplls[i];
4043 if (pll->new_config->crtc_mask == 0) {
4044 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4045 crtc->base.base.id, pll->name);
4046 goto found;
4047 }
4048 }
4049
4050 return NULL;
4051
4052 found:
4053 if (pll->new_config->crtc_mask == 0)
4054 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4055
4056 crtc_state->shared_dpll = i;
4057 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4058 pipe_name(crtc->pipe));
4059
4060 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4061
4062 return pll;
4063 }
4064
4065 /**
4066 * intel_shared_dpll_start_config - start a new PLL staged config
4067 * @dev_priv: DRM device
4068 * @clear_pipes: mask of pipes that will have their PLLs freed
4069 *
4070 * Starts a new PLL staged config, copying the current config but
4071 * releasing the references of pipes specified in clear_pipes.
4072 */
4073 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4074 unsigned clear_pipes)
4075 {
4076 struct intel_shared_dpll *pll;
4077 enum intel_dpll_id i;
4078
4079 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4080 pll = &dev_priv->shared_dplls[i];
4081
4082 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4083 GFP_KERNEL);
4084 if (!pll->new_config)
4085 goto cleanup;
4086
4087 pll->new_config->crtc_mask &= ~clear_pipes;
4088 }
4089
4090 return 0;
4091
4092 cleanup:
4093 while (--i >= 0) {
4094 pll = &dev_priv->shared_dplls[i];
4095 kfree(pll->new_config);
4096 pll->new_config = NULL;
4097 }
4098
4099 return -ENOMEM;
4100 }
4101
4102 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4103 {
4104 struct intel_shared_dpll *pll;
4105 enum intel_dpll_id i;
4106
4107 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4108 pll = &dev_priv->shared_dplls[i];
4109
4110 WARN_ON(pll->new_config == &pll->config);
4111
4112 pll->config = *pll->new_config;
4113 kfree(pll->new_config);
4114 pll->new_config = NULL;
4115 }
4116 }
4117
4118 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4119 {
4120 struct intel_shared_dpll *pll;
4121 enum intel_dpll_id i;
4122
4123 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4124 pll = &dev_priv->shared_dplls[i];
4125
4126 WARN_ON(pll->new_config == &pll->config);
4127
4128 kfree(pll->new_config);
4129 pll->new_config = NULL;
4130 }
4131 }
4132
4133 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4134 {
4135 struct drm_i915_private *dev_priv = dev->dev_private;
4136 int dslreg = PIPEDSL(pipe);
4137 u32 temp;
4138
4139 temp = I915_READ(dslreg);
4140 udelay(500);
4141 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4142 if (wait_for(I915_READ(dslreg) != temp, 5))
4143 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4144 }
4145 }
4146
4147 static void skylake_pfit_enable(struct intel_crtc *crtc)
4148 {
4149 struct drm_device *dev = crtc->base.dev;
4150 struct drm_i915_private *dev_priv = dev->dev_private;
4151 int pipe = crtc->pipe;
4152
4153 if (crtc->config->pch_pfit.enabled) {
4154 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
4155 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4156 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4157 }
4158 }
4159
4160 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4161 {
4162 struct drm_device *dev = crtc->base.dev;
4163 struct drm_i915_private *dev_priv = dev->dev_private;
4164 int pipe = crtc->pipe;
4165
4166 if (crtc->config->pch_pfit.enabled) {
4167 /* Force use of hard-coded filter coefficients
4168 * as some pre-programmed values are broken,
4169 * e.g. x201.
4170 */
4171 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4172 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4173 PF_PIPE_SEL_IVB(pipe));
4174 else
4175 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4176 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4177 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4178 }
4179 }
4180
4181 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4182 {
4183 struct drm_device *dev = crtc->dev;
4184 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4185 struct drm_plane *plane;
4186 struct intel_plane *intel_plane;
4187
4188 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4189 intel_plane = to_intel_plane(plane);
4190 if (intel_plane->pipe == pipe)
4191 intel_plane_restore(&intel_plane->base);
4192 }
4193 }
4194
4195 /*
4196 * Disable a plane internally without actually modifying the plane's state.
4197 * This will allow us to easily restore the plane later by just reprogramming
4198 * its state.
4199 */
4200 static void disable_plane_internal(struct drm_plane *plane)
4201 {
4202 struct intel_plane *intel_plane = to_intel_plane(plane);
4203 struct drm_plane_state *state =
4204 plane->funcs->atomic_duplicate_state(plane);
4205 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4206
4207 intel_state->visible = false;
4208 intel_plane->commit_plane(plane, intel_state);
4209
4210 intel_plane_destroy_state(plane, state);
4211 }
4212
4213 static void intel_disable_sprite_planes(struct drm_crtc *crtc)
4214 {
4215 struct drm_device *dev = crtc->dev;
4216 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4217 struct drm_plane *plane;
4218 struct intel_plane *intel_plane;
4219
4220 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4221 intel_plane = to_intel_plane(plane);
4222 if (plane->fb && intel_plane->pipe == pipe)
4223 disable_plane_internal(plane);
4224 }
4225 }
4226
4227 void hsw_enable_ips(struct intel_crtc *crtc)
4228 {
4229 struct drm_device *dev = crtc->base.dev;
4230 struct drm_i915_private *dev_priv = dev->dev_private;
4231
4232 if (!crtc->config->ips_enabled)
4233 return;
4234
4235 /* We can only enable IPS after we enable a plane and wait for a vblank */
4236 intel_wait_for_vblank(dev, crtc->pipe);
4237
4238 assert_plane_enabled(dev_priv, crtc->plane);
4239 if (IS_BROADWELL(dev)) {
4240 mutex_lock(&dev_priv->rps.hw_lock);
4241 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4242 mutex_unlock(&dev_priv->rps.hw_lock);
4243 /* Quoting Art Runyan: "its not safe to expect any particular
4244 * value in IPS_CTL bit 31 after enabling IPS through the
4245 * mailbox." Moreover, the mailbox may return a bogus state,
4246 * so we need to just enable it and continue on.
4247 */
4248 } else {
4249 I915_WRITE(IPS_CTL, IPS_ENABLE);
4250 /* The bit only becomes 1 in the next vblank, so this wait here
4251 * is essentially intel_wait_for_vblank. If we don't have this
4252 * and don't wait for vblanks until the end of crtc_enable, then
4253 * the HW state readout code will complain that the expected
4254 * IPS_CTL value is not the one we read. */
4255 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4256 DRM_ERROR("Timed out waiting for IPS enable\n");
4257 }
4258 }
4259
4260 void hsw_disable_ips(struct intel_crtc *crtc)
4261 {
4262 struct drm_device *dev = crtc->base.dev;
4263 struct drm_i915_private *dev_priv = dev->dev_private;
4264
4265 if (!crtc->config->ips_enabled)
4266 return;
4267
4268 assert_plane_enabled(dev_priv, crtc->plane);
4269 if (IS_BROADWELL(dev)) {
4270 mutex_lock(&dev_priv->rps.hw_lock);
4271 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4272 mutex_unlock(&dev_priv->rps.hw_lock);
4273 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4274 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4275 DRM_ERROR("Timed out waiting for IPS disable\n");
4276 } else {
4277 I915_WRITE(IPS_CTL, 0);
4278 POSTING_READ(IPS_CTL);
4279 }
4280
4281 /* We need to wait for a vblank before we can disable the plane. */
4282 intel_wait_for_vblank(dev, crtc->pipe);
4283 }
4284
4285 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4286 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4287 {
4288 struct drm_device *dev = crtc->dev;
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4291 enum pipe pipe = intel_crtc->pipe;
4292 int palreg = PALETTE(pipe);
4293 int i;
4294 bool reenable_ips = false;
4295
4296 /* The clocks have to be on to load the palette. */
4297 if (!crtc->state->enable || !intel_crtc->active)
4298 return;
4299
4300 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4301 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4302 assert_dsi_pll_enabled(dev_priv);
4303 else
4304 assert_pll_enabled(dev_priv, pipe);
4305 }
4306
4307 /* use legacy palette for Ironlake */
4308 if (!HAS_GMCH_DISPLAY(dev))
4309 palreg = LGC_PALETTE(pipe);
4310
4311 /* Workaround : Do not read or write the pipe palette/gamma data while
4312 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4313 */
4314 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4315 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4316 GAMMA_MODE_MODE_SPLIT)) {
4317 hsw_disable_ips(intel_crtc);
4318 reenable_ips = true;
4319 }
4320
4321 for (i = 0; i < 256; i++) {
4322 I915_WRITE(palreg + 4 * i,
4323 (intel_crtc->lut_r[i] << 16) |
4324 (intel_crtc->lut_g[i] << 8) |
4325 intel_crtc->lut_b[i]);
4326 }
4327
4328 if (reenable_ips)
4329 hsw_enable_ips(intel_crtc);
4330 }
4331
4332 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4333 {
4334 if (!enable && intel_crtc->overlay) {
4335 struct drm_device *dev = intel_crtc->base.dev;
4336 struct drm_i915_private *dev_priv = dev->dev_private;
4337
4338 mutex_lock(&dev->struct_mutex);
4339 dev_priv->mm.interruptible = false;
4340 (void) intel_overlay_switch_off(intel_crtc->overlay);
4341 dev_priv->mm.interruptible = true;
4342 mutex_unlock(&dev->struct_mutex);
4343 }
4344
4345 /* Let userspace switch the overlay on again. In most cases userspace
4346 * has to recompute where to put it anyway.
4347 */
4348 }
4349
4350 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4351 {
4352 struct drm_device *dev = crtc->dev;
4353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4354 int pipe = intel_crtc->pipe;
4355
4356 intel_enable_primary_hw_plane(crtc->primary, crtc);
4357 intel_enable_sprite_planes(crtc);
4358 intel_crtc_update_cursor(crtc, true);
4359 intel_crtc_dpms_overlay(intel_crtc, true);
4360
4361 hsw_enable_ips(intel_crtc);
4362
4363 mutex_lock(&dev->struct_mutex);
4364 intel_fbc_update(dev);
4365 mutex_unlock(&dev->struct_mutex);
4366
4367 /*
4368 * FIXME: Once we grow proper nuclear flip support out of this we need
4369 * to compute the mask of flip planes precisely. For the time being
4370 * consider this a flip from a NULL plane.
4371 */
4372 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4373 }
4374
4375 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4376 {
4377 struct drm_device *dev = crtc->dev;
4378 struct drm_i915_private *dev_priv = dev->dev_private;
4379 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4380 int pipe = intel_crtc->pipe;
4381
4382 intel_crtc_wait_for_pending_flips(crtc);
4383
4384 if (dev_priv->fbc.crtc == intel_crtc)
4385 intel_fbc_disable(dev);
4386
4387 hsw_disable_ips(intel_crtc);
4388
4389 intel_crtc_dpms_overlay(intel_crtc, false);
4390 intel_crtc_update_cursor(crtc, false);
4391 intel_disable_sprite_planes(crtc);
4392 intel_disable_primary_hw_plane(crtc->primary, crtc);
4393
4394 /*
4395 * FIXME: Once we grow proper nuclear flip support out of this we need
4396 * to compute the mask of flip planes precisely. For the time being
4397 * consider this a flip to a NULL plane.
4398 */
4399 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4400 }
4401
4402 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4403 {
4404 struct drm_device *dev = crtc->dev;
4405 struct drm_i915_private *dev_priv = dev->dev_private;
4406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4407 struct intel_encoder *encoder;
4408 int pipe = intel_crtc->pipe;
4409
4410 WARN_ON(!crtc->state->enable);
4411
4412 if (intel_crtc->active)
4413 return;
4414
4415 if (intel_crtc->config->has_pch_encoder)
4416 intel_prepare_shared_dpll(intel_crtc);
4417
4418 if (intel_crtc->config->has_dp_encoder)
4419 intel_dp_set_m_n(intel_crtc, M1_N1);
4420
4421 intel_set_pipe_timings(intel_crtc);
4422
4423 if (intel_crtc->config->has_pch_encoder) {
4424 intel_cpu_transcoder_set_m_n(intel_crtc,
4425 &intel_crtc->config->fdi_m_n, NULL);
4426 }
4427
4428 ironlake_set_pipeconf(crtc);
4429
4430 intel_crtc->active = true;
4431
4432 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4433 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4434
4435 for_each_encoder_on_crtc(dev, crtc, encoder)
4436 if (encoder->pre_enable)
4437 encoder->pre_enable(encoder);
4438
4439 if (intel_crtc->config->has_pch_encoder) {
4440 /* Note: FDI PLL enabling _must_ be done before we enable the
4441 * cpu pipes, hence this is separate from all the other fdi/pch
4442 * enabling. */
4443 ironlake_fdi_pll_enable(intel_crtc);
4444 } else {
4445 assert_fdi_tx_disabled(dev_priv, pipe);
4446 assert_fdi_rx_disabled(dev_priv, pipe);
4447 }
4448
4449 ironlake_pfit_enable(intel_crtc);
4450
4451 /*
4452 * On ILK+ LUT must be loaded before the pipe is running but with
4453 * clocks enabled
4454 */
4455 intel_crtc_load_lut(crtc);
4456
4457 intel_update_watermarks(crtc);
4458 intel_enable_pipe(intel_crtc);
4459
4460 if (intel_crtc->config->has_pch_encoder)
4461 ironlake_pch_enable(crtc);
4462
4463 assert_vblank_disabled(crtc);
4464 drm_crtc_vblank_on(crtc);
4465
4466 for_each_encoder_on_crtc(dev, crtc, encoder)
4467 encoder->enable(encoder);
4468
4469 if (HAS_PCH_CPT(dev))
4470 cpt_verify_modeset(dev, intel_crtc->pipe);
4471
4472 intel_crtc_enable_planes(crtc);
4473 }
4474
4475 /* IPS only exists on ULT machines and is tied to pipe A. */
4476 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4477 {
4478 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4479 }
4480
4481 /*
4482 * This implements the workaround described in the "notes" section of the mode
4483 * set sequence documentation. When going from no pipes or single pipe to
4484 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4485 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4486 */
4487 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4488 {
4489 struct drm_device *dev = crtc->base.dev;
4490 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4491
4492 /* We want to get the other_active_crtc only if there's only 1 other
4493 * active crtc. */
4494 for_each_intel_crtc(dev, crtc_it) {
4495 if (!crtc_it->active || crtc_it == crtc)
4496 continue;
4497
4498 if (other_active_crtc)
4499 return;
4500
4501 other_active_crtc = crtc_it;
4502 }
4503 if (!other_active_crtc)
4504 return;
4505
4506 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4507 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4508 }
4509
4510 static void haswell_crtc_enable(struct drm_crtc *crtc)
4511 {
4512 struct drm_device *dev = crtc->dev;
4513 struct drm_i915_private *dev_priv = dev->dev_private;
4514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4515 struct intel_encoder *encoder;
4516 int pipe = intel_crtc->pipe;
4517
4518 WARN_ON(!crtc->state->enable);
4519
4520 if (intel_crtc->active)
4521 return;
4522
4523 if (intel_crtc_to_shared_dpll(intel_crtc))
4524 intel_enable_shared_dpll(intel_crtc);
4525
4526 if (intel_crtc->config->has_dp_encoder)
4527 intel_dp_set_m_n(intel_crtc, M1_N1);
4528
4529 intel_set_pipe_timings(intel_crtc);
4530
4531 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4532 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4533 intel_crtc->config->pixel_multiplier - 1);
4534 }
4535
4536 if (intel_crtc->config->has_pch_encoder) {
4537 intel_cpu_transcoder_set_m_n(intel_crtc,
4538 &intel_crtc->config->fdi_m_n, NULL);
4539 }
4540
4541 haswell_set_pipeconf(crtc);
4542
4543 intel_set_pipe_csc(crtc);
4544
4545 intel_crtc->active = true;
4546
4547 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4548 for_each_encoder_on_crtc(dev, crtc, encoder)
4549 if (encoder->pre_enable)
4550 encoder->pre_enable(encoder);
4551
4552 if (intel_crtc->config->has_pch_encoder) {
4553 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4554 true);
4555 dev_priv->display.fdi_link_train(crtc);
4556 }
4557
4558 intel_ddi_enable_pipe_clock(intel_crtc);
4559
4560 if (IS_SKYLAKE(dev))
4561 skylake_pfit_enable(intel_crtc);
4562 else
4563 ironlake_pfit_enable(intel_crtc);
4564
4565 /*
4566 * On ILK+ LUT must be loaded before the pipe is running but with
4567 * clocks enabled
4568 */
4569 intel_crtc_load_lut(crtc);
4570
4571 intel_ddi_set_pipe_settings(crtc);
4572 intel_ddi_enable_transcoder_func(crtc);
4573
4574 intel_update_watermarks(crtc);
4575 intel_enable_pipe(intel_crtc);
4576
4577 if (intel_crtc->config->has_pch_encoder)
4578 lpt_pch_enable(crtc);
4579
4580 if (intel_crtc->config->dp_encoder_is_mst)
4581 intel_ddi_set_vc_payload_alloc(crtc, true);
4582
4583 assert_vblank_disabled(crtc);
4584 drm_crtc_vblank_on(crtc);
4585
4586 for_each_encoder_on_crtc(dev, crtc, encoder) {
4587 encoder->enable(encoder);
4588 intel_opregion_notify_encoder(encoder, true);
4589 }
4590
4591 /* If we change the relative order between pipe/planes enabling, we need
4592 * to change the workaround. */
4593 haswell_mode_set_planes_workaround(intel_crtc);
4594 intel_crtc_enable_planes(crtc);
4595 }
4596
4597 static void skylake_pfit_disable(struct intel_crtc *crtc)
4598 {
4599 struct drm_device *dev = crtc->base.dev;
4600 struct drm_i915_private *dev_priv = dev->dev_private;
4601 int pipe = crtc->pipe;
4602
4603 /* To avoid upsetting the power well on haswell only disable the pfit if
4604 * it's in use. The hw state code will make sure we get this right. */
4605 if (crtc->config->pch_pfit.enabled) {
4606 I915_WRITE(PS_CTL(pipe), 0);
4607 I915_WRITE(PS_WIN_POS(pipe), 0);
4608 I915_WRITE(PS_WIN_SZ(pipe), 0);
4609 }
4610 }
4611
4612 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4613 {
4614 struct drm_device *dev = crtc->base.dev;
4615 struct drm_i915_private *dev_priv = dev->dev_private;
4616 int pipe = crtc->pipe;
4617
4618 /* To avoid upsetting the power well on haswell only disable the pfit if
4619 * it's in use. The hw state code will make sure we get this right. */
4620 if (crtc->config->pch_pfit.enabled) {
4621 I915_WRITE(PF_CTL(pipe), 0);
4622 I915_WRITE(PF_WIN_POS(pipe), 0);
4623 I915_WRITE(PF_WIN_SZ(pipe), 0);
4624 }
4625 }
4626
4627 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4628 {
4629 struct drm_device *dev = crtc->dev;
4630 struct drm_i915_private *dev_priv = dev->dev_private;
4631 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4632 struct intel_encoder *encoder;
4633 int pipe = intel_crtc->pipe;
4634 u32 reg, temp;
4635
4636 if (!intel_crtc->active)
4637 return;
4638
4639 intel_crtc_disable_planes(crtc);
4640
4641 for_each_encoder_on_crtc(dev, crtc, encoder)
4642 encoder->disable(encoder);
4643
4644 drm_crtc_vblank_off(crtc);
4645 assert_vblank_disabled(crtc);
4646
4647 if (intel_crtc->config->has_pch_encoder)
4648 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4649
4650 intel_disable_pipe(intel_crtc);
4651
4652 ironlake_pfit_disable(intel_crtc);
4653
4654 for_each_encoder_on_crtc(dev, crtc, encoder)
4655 if (encoder->post_disable)
4656 encoder->post_disable(encoder);
4657
4658 if (intel_crtc->config->has_pch_encoder) {
4659 ironlake_fdi_disable(crtc);
4660
4661 ironlake_disable_pch_transcoder(dev_priv, pipe);
4662
4663 if (HAS_PCH_CPT(dev)) {
4664 /* disable TRANS_DP_CTL */
4665 reg = TRANS_DP_CTL(pipe);
4666 temp = I915_READ(reg);
4667 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4668 TRANS_DP_PORT_SEL_MASK);
4669 temp |= TRANS_DP_PORT_SEL_NONE;
4670 I915_WRITE(reg, temp);
4671
4672 /* disable DPLL_SEL */
4673 temp = I915_READ(PCH_DPLL_SEL);
4674 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4675 I915_WRITE(PCH_DPLL_SEL, temp);
4676 }
4677
4678 /* disable PCH DPLL */
4679 intel_disable_shared_dpll(intel_crtc);
4680
4681 ironlake_fdi_pll_disable(intel_crtc);
4682 }
4683
4684 intel_crtc->active = false;
4685 intel_update_watermarks(crtc);
4686
4687 mutex_lock(&dev->struct_mutex);
4688 intel_fbc_update(dev);
4689 mutex_unlock(&dev->struct_mutex);
4690 }
4691
4692 static void haswell_crtc_disable(struct drm_crtc *crtc)
4693 {
4694 struct drm_device *dev = crtc->dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4697 struct intel_encoder *encoder;
4698 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4699
4700 if (!intel_crtc->active)
4701 return;
4702
4703 intel_crtc_disable_planes(crtc);
4704
4705 for_each_encoder_on_crtc(dev, crtc, encoder) {
4706 intel_opregion_notify_encoder(encoder, false);
4707 encoder->disable(encoder);
4708 }
4709
4710 drm_crtc_vblank_off(crtc);
4711 assert_vblank_disabled(crtc);
4712
4713 if (intel_crtc->config->has_pch_encoder)
4714 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4715 false);
4716 intel_disable_pipe(intel_crtc);
4717
4718 if (intel_crtc->config->dp_encoder_is_mst)
4719 intel_ddi_set_vc_payload_alloc(crtc, false);
4720
4721 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4722
4723 if (IS_SKYLAKE(dev))
4724 skylake_pfit_disable(intel_crtc);
4725 else
4726 ironlake_pfit_disable(intel_crtc);
4727
4728 intel_ddi_disable_pipe_clock(intel_crtc);
4729
4730 if (intel_crtc->config->has_pch_encoder) {
4731 lpt_disable_pch_transcoder(dev_priv);
4732 intel_ddi_fdi_disable(crtc);
4733 }
4734
4735 for_each_encoder_on_crtc(dev, crtc, encoder)
4736 if (encoder->post_disable)
4737 encoder->post_disable(encoder);
4738
4739 intel_crtc->active = false;
4740 intel_update_watermarks(crtc);
4741
4742 mutex_lock(&dev->struct_mutex);
4743 intel_fbc_update(dev);
4744 mutex_unlock(&dev->struct_mutex);
4745
4746 if (intel_crtc_to_shared_dpll(intel_crtc))
4747 intel_disable_shared_dpll(intel_crtc);
4748 }
4749
4750 static void ironlake_crtc_off(struct drm_crtc *crtc)
4751 {
4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 intel_put_shared_dpll(intel_crtc);
4754 }
4755
4756
4757 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4758 {
4759 struct drm_device *dev = crtc->base.dev;
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 struct intel_crtc_state *pipe_config = crtc->config;
4762
4763 if (!pipe_config->gmch_pfit.control)
4764 return;
4765
4766 /*
4767 * The panel fitter should only be adjusted whilst the pipe is disabled,
4768 * according to register description and PRM.
4769 */
4770 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4771 assert_pipe_disabled(dev_priv, crtc->pipe);
4772
4773 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4774 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4775
4776 /* Border color in case we don't scale up to the full screen. Black by
4777 * default, change to something else for debugging. */
4778 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4779 }
4780
4781 static enum intel_display_power_domain port_to_power_domain(enum port port)
4782 {
4783 switch (port) {
4784 case PORT_A:
4785 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4786 case PORT_B:
4787 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4788 case PORT_C:
4789 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4790 case PORT_D:
4791 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4792 default:
4793 WARN_ON_ONCE(1);
4794 return POWER_DOMAIN_PORT_OTHER;
4795 }
4796 }
4797
4798 #define for_each_power_domain(domain, mask) \
4799 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4800 if ((1 << (domain)) & (mask))
4801
4802 enum intel_display_power_domain
4803 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4804 {
4805 struct drm_device *dev = intel_encoder->base.dev;
4806 struct intel_digital_port *intel_dig_port;
4807
4808 switch (intel_encoder->type) {
4809 case INTEL_OUTPUT_UNKNOWN:
4810 /* Only DDI platforms should ever use this output type */
4811 WARN_ON_ONCE(!HAS_DDI(dev));
4812 case INTEL_OUTPUT_DISPLAYPORT:
4813 case INTEL_OUTPUT_HDMI:
4814 case INTEL_OUTPUT_EDP:
4815 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4816 return port_to_power_domain(intel_dig_port->port);
4817 case INTEL_OUTPUT_DP_MST:
4818 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4819 return port_to_power_domain(intel_dig_port->port);
4820 case INTEL_OUTPUT_ANALOG:
4821 return POWER_DOMAIN_PORT_CRT;
4822 case INTEL_OUTPUT_DSI:
4823 return POWER_DOMAIN_PORT_DSI;
4824 default:
4825 return POWER_DOMAIN_PORT_OTHER;
4826 }
4827 }
4828
4829 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4830 {
4831 struct drm_device *dev = crtc->dev;
4832 struct intel_encoder *intel_encoder;
4833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4834 enum pipe pipe = intel_crtc->pipe;
4835 unsigned long mask;
4836 enum transcoder transcoder;
4837
4838 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4839
4840 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4841 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4842 if (intel_crtc->config->pch_pfit.enabled ||
4843 intel_crtc->config->pch_pfit.force_thru)
4844 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4845
4846 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4847 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4848
4849 return mask;
4850 }
4851
4852 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4853 {
4854 struct drm_i915_private *dev_priv = dev->dev_private;
4855 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4856 struct intel_crtc *crtc;
4857
4858 /*
4859 * First get all needed power domains, then put all unneeded, to avoid
4860 * any unnecessary toggling of the power wells.
4861 */
4862 for_each_intel_crtc(dev, crtc) {
4863 enum intel_display_power_domain domain;
4864
4865 if (!crtc->base.state->enable)
4866 continue;
4867
4868 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4869
4870 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4871 intel_display_power_get(dev_priv, domain);
4872 }
4873
4874 if (dev_priv->display.modeset_global_resources)
4875 dev_priv->display.modeset_global_resources(dev);
4876
4877 for_each_intel_crtc(dev, crtc) {
4878 enum intel_display_power_domain domain;
4879
4880 for_each_power_domain(domain, crtc->enabled_power_domains)
4881 intel_display_power_put(dev_priv, domain);
4882
4883 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4884 }
4885
4886 intel_display_set_init_power(dev_priv, false);
4887 }
4888
4889 /* returns HPLL frequency in kHz */
4890 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4891 {
4892 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4893
4894 /* Obtain SKU information */
4895 mutex_lock(&dev_priv->dpio_lock);
4896 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4897 CCK_FUSE_HPLL_FREQ_MASK;
4898 mutex_unlock(&dev_priv->dpio_lock);
4899
4900 return vco_freq[hpll_freq] * 1000;
4901 }
4902
4903 static void vlv_update_cdclk(struct drm_device *dev)
4904 {
4905 struct drm_i915_private *dev_priv = dev->dev_private;
4906
4907 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4908 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4909 dev_priv->vlv_cdclk_freq);
4910
4911 /*
4912 * Program the gmbus_freq based on the cdclk frequency.
4913 * BSpec erroneously claims we should aim for 4MHz, but
4914 * in fact 1MHz is the correct frequency.
4915 */
4916 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
4917 }
4918
4919 /* Adjust CDclk dividers to allow high res or save power if possible */
4920 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4921 {
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923 u32 val, cmd;
4924
4925 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4926
4927 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4928 cmd = 2;
4929 else if (cdclk == 266667)
4930 cmd = 1;
4931 else
4932 cmd = 0;
4933
4934 mutex_lock(&dev_priv->rps.hw_lock);
4935 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4936 val &= ~DSPFREQGUAR_MASK;
4937 val |= (cmd << DSPFREQGUAR_SHIFT);
4938 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4939 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4940 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4941 50)) {
4942 DRM_ERROR("timed out waiting for CDclk change\n");
4943 }
4944 mutex_unlock(&dev_priv->rps.hw_lock);
4945
4946 if (cdclk == 400000) {
4947 u32 divider;
4948
4949 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
4950
4951 mutex_lock(&dev_priv->dpio_lock);
4952 /* adjust cdclk divider */
4953 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4954 val &= ~DISPLAY_FREQUENCY_VALUES;
4955 val |= divider;
4956 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4957
4958 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4959 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4960 50))
4961 DRM_ERROR("timed out waiting for CDclk change\n");
4962 mutex_unlock(&dev_priv->dpio_lock);
4963 }
4964
4965 mutex_lock(&dev_priv->dpio_lock);
4966 /* adjust self-refresh exit latency value */
4967 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4968 val &= ~0x7f;
4969
4970 /*
4971 * For high bandwidth configs, we set a higher latency in the bunit
4972 * so that the core display fetch happens in time to avoid underruns.
4973 */
4974 if (cdclk == 400000)
4975 val |= 4500 / 250; /* 4.5 usec */
4976 else
4977 val |= 3000 / 250; /* 3.0 usec */
4978 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4979 mutex_unlock(&dev_priv->dpio_lock);
4980
4981 vlv_update_cdclk(dev);
4982 }
4983
4984 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4985 {
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 u32 val, cmd;
4988
4989 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4990
4991 switch (cdclk) {
4992 case 333333:
4993 case 320000:
4994 case 266667:
4995 case 200000:
4996 break;
4997 default:
4998 MISSING_CASE(cdclk);
4999 return;
5000 }
5001
5002 /*
5003 * Specs are full of misinformation, but testing on actual
5004 * hardware has shown that we just need to write the desired
5005 * CCK divider into the Punit register.
5006 */
5007 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5008
5009 mutex_lock(&dev_priv->rps.hw_lock);
5010 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5011 val &= ~DSPFREQGUAR_MASK_CHV;
5012 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5013 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5014 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5015 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5016 50)) {
5017 DRM_ERROR("timed out waiting for CDclk change\n");
5018 }
5019 mutex_unlock(&dev_priv->rps.hw_lock);
5020
5021 vlv_update_cdclk(dev);
5022 }
5023
5024 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5025 int max_pixclk)
5026 {
5027 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5028 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5029
5030 /*
5031 * Really only a few cases to deal with, as only 4 CDclks are supported:
5032 * 200MHz
5033 * 267MHz
5034 * 320/333MHz (depends on HPLL freq)
5035 * 400MHz (VLV only)
5036 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5037 * of the lower bin and adjust if needed.
5038 *
5039 * We seem to get an unstable or solid color picture at 200MHz.
5040 * Not sure what's wrong. For now use 200MHz only when all pipes
5041 * are off.
5042 */
5043 if (!IS_CHERRYVIEW(dev_priv) &&
5044 max_pixclk > freq_320*limit/100)
5045 return 400000;
5046 else if (max_pixclk > 266667*limit/100)
5047 return freq_320;
5048 else if (max_pixclk > 0)
5049 return 266667;
5050 else
5051 return 200000;
5052 }
5053
5054 /* compute the max pixel clock for new configuration */
5055 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
5056 {
5057 struct drm_device *dev = dev_priv->dev;
5058 struct intel_crtc *intel_crtc;
5059 int max_pixclk = 0;
5060
5061 for_each_intel_crtc(dev, intel_crtc) {
5062 if (intel_crtc->new_enabled)
5063 max_pixclk = max(max_pixclk,
5064 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
5065 }
5066
5067 return max_pixclk;
5068 }
5069
5070 static void valleyview_modeset_global_pipes(struct drm_device *dev,
5071 unsigned *prepare_pipes)
5072 {
5073 struct drm_i915_private *dev_priv = dev->dev_private;
5074 struct intel_crtc *intel_crtc;
5075 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5076
5077 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5078 dev_priv->vlv_cdclk_freq)
5079 return;
5080
5081 /* disable/enable all currently active pipes while we change cdclk */
5082 for_each_intel_crtc(dev, intel_crtc)
5083 if (intel_crtc->base.state->enable)
5084 *prepare_pipes |= (1 << intel_crtc->pipe);
5085 }
5086
5087 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5088 {
5089 unsigned int credits, default_credits;
5090
5091 if (IS_CHERRYVIEW(dev_priv))
5092 default_credits = PFI_CREDIT(12);
5093 else
5094 default_credits = PFI_CREDIT(8);
5095
5096 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5097 /* CHV suggested value is 31 or 63 */
5098 if (IS_CHERRYVIEW(dev_priv))
5099 credits = PFI_CREDIT_31;
5100 else
5101 credits = PFI_CREDIT(15);
5102 } else {
5103 credits = default_credits;
5104 }
5105
5106 /*
5107 * WA - write default credits before re-programming
5108 * FIXME: should we also set the resend bit here?
5109 */
5110 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5111 default_credits);
5112
5113 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5114 credits | PFI_CREDIT_RESEND);
5115
5116 /*
5117 * FIXME is this guaranteed to clear
5118 * immediately or should we poll for it?
5119 */
5120 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5121 }
5122
5123 static void valleyview_modeset_global_resources(struct drm_device *dev)
5124 {
5125 struct drm_i915_private *dev_priv = dev->dev_private;
5126 int max_pixclk = intel_mode_max_pixclk(dev_priv);
5127 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5128
5129 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
5130 /*
5131 * FIXME: We can end up here with all power domains off, yet
5132 * with a CDCLK frequency other than the minimum. To account
5133 * for this take the PIPE-A power domain, which covers the HW
5134 * blocks needed for the following programming. This can be
5135 * removed once it's guaranteed that we get here either with
5136 * the minimum CDCLK set, or the required power domains
5137 * enabled.
5138 */
5139 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5140
5141 if (IS_CHERRYVIEW(dev))
5142 cherryview_set_cdclk(dev, req_cdclk);
5143 else
5144 valleyview_set_cdclk(dev, req_cdclk);
5145
5146 vlv_program_pfi_credits(dev_priv);
5147
5148 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5149 }
5150 }
5151
5152 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5153 {
5154 struct drm_device *dev = crtc->dev;
5155 struct drm_i915_private *dev_priv = to_i915(dev);
5156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5157 struct intel_encoder *encoder;
5158 int pipe = intel_crtc->pipe;
5159 bool is_dsi;
5160
5161 WARN_ON(!crtc->state->enable);
5162
5163 if (intel_crtc->active)
5164 return;
5165
5166 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5167
5168 if (!is_dsi) {
5169 if (IS_CHERRYVIEW(dev))
5170 chv_prepare_pll(intel_crtc, intel_crtc->config);
5171 else
5172 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5173 }
5174
5175 if (intel_crtc->config->has_dp_encoder)
5176 intel_dp_set_m_n(intel_crtc, M1_N1);
5177
5178 intel_set_pipe_timings(intel_crtc);
5179
5180 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5181 struct drm_i915_private *dev_priv = dev->dev_private;
5182
5183 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5184 I915_WRITE(CHV_CANVAS(pipe), 0);
5185 }
5186
5187 i9xx_set_pipeconf(intel_crtc);
5188
5189 intel_crtc->active = true;
5190
5191 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5192
5193 for_each_encoder_on_crtc(dev, crtc, encoder)
5194 if (encoder->pre_pll_enable)
5195 encoder->pre_pll_enable(encoder);
5196
5197 if (!is_dsi) {
5198 if (IS_CHERRYVIEW(dev))
5199 chv_enable_pll(intel_crtc, intel_crtc->config);
5200 else
5201 vlv_enable_pll(intel_crtc, intel_crtc->config);
5202 }
5203
5204 for_each_encoder_on_crtc(dev, crtc, encoder)
5205 if (encoder->pre_enable)
5206 encoder->pre_enable(encoder);
5207
5208 i9xx_pfit_enable(intel_crtc);
5209
5210 intel_crtc_load_lut(crtc);
5211
5212 intel_update_watermarks(crtc);
5213 intel_enable_pipe(intel_crtc);
5214
5215 assert_vblank_disabled(crtc);
5216 drm_crtc_vblank_on(crtc);
5217
5218 for_each_encoder_on_crtc(dev, crtc, encoder)
5219 encoder->enable(encoder);
5220
5221 intel_crtc_enable_planes(crtc);
5222
5223 /* Underruns don't raise interrupts, so check manually. */
5224 i9xx_check_fifo_underruns(dev_priv);
5225 }
5226
5227 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5228 {
5229 struct drm_device *dev = crtc->base.dev;
5230 struct drm_i915_private *dev_priv = dev->dev_private;
5231
5232 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5233 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5234 }
5235
5236 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5237 {
5238 struct drm_device *dev = crtc->dev;
5239 struct drm_i915_private *dev_priv = to_i915(dev);
5240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5241 struct intel_encoder *encoder;
5242 int pipe = intel_crtc->pipe;
5243
5244 WARN_ON(!crtc->state->enable);
5245
5246 if (intel_crtc->active)
5247 return;
5248
5249 i9xx_set_pll_dividers(intel_crtc);
5250
5251 if (intel_crtc->config->has_dp_encoder)
5252 intel_dp_set_m_n(intel_crtc, M1_N1);
5253
5254 intel_set_pipe_timings(intel_crtc);
5255
5256 i9xx_set_pipeconf(intel_crtc);
5257
5258 intel_crtc->active = true;
5259
5260 if (!IS_GEN2(dev))
5261 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5262
5263 for_each_encoder_on_crtc(dev, crtc, encoder)
5264 if (encoder->pre_enable)
5265 encoder->pre_enable(encoder);
5266
5267 i9xx_enable_pll(intel_crtc);
5268
5269 i9xx_pfit_enable(intel_crtc);
5270
5271 intel_crtc_load_lut(crtc);
5272
5273 intel_update_watermarks(crtc);
5274 intel_enable_pipe(intel_crtc);
5275
5276 assert_vblank_disabled(crtc);
5277 drm_crtc_vblank_on(crtc);
5278
5279 for_each_encoder_on_crtc(dev, crtc, encoder)
5280 encoder->enable(encoder);
5281
5282 intel_crtc_enable_planes(crtc);
5283
5284 /*
5285 * Gen2 reports pipe underruns whenever all planes are disabled.
5286 * So don't enable underrun reporting before at least some planes
5287 * are enabled.
5288 * FIXME: Need to fix the logic to work when we turn off all planes
5289 * but leave the pipe running.
5290 */
5291 if (IS_GEN2(dev))
5292 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5293
5294 /* Underruns don't raise interrupts, so check manually. */
5295 i9xx_check_fifo_underruns(dev_priv);
5296 }
5297
5298 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5299 {
5300 struct drm_device *dev = crtc->base.dev;
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302
5303 if (!crtc->config->gmch_pfit.control)
5304 return;
5305
5306 assert_pipe_disabled(dev_priv, crtc->pipe);
5307
5308 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5309 I915_READ(PFIT_CONTROL));
5310 I915_WRITE(PFIT_CONTROL, 0);
5311 }
5312
5313 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5314 {
5315 struct drm_device *dev = crtc->dev;
5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5318 struct intel_encoder *encoder;
5319 int pipe = intel_crtc->pipe;
5320
5321 if (!intel_crtc->active)
5322 return;
5323
5324 /*
5325 * Gen2 reports pipe underruns whenever all planes are disabled.
5326 * So diasble underrun reporting before all the planes get disabled.
5327 * FIXME: Need to fix the logic to work when we turn off all planes
5328 * but leave the pipe running.
5329 */
5330 if (IS_GEN2(dev))
5331 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5332
5333 /*
5334 * Vblank time updates from the shadow to live plane control register
5335 * are blocked if the memory self-refresh mode is active at that
5336 * moment. So to make sure the plane gets truly disabled, disable
5337 * first the self-refresh mode. The self-refresh enable bit in turn
5338 * will be checked/applied by the HW only at the next frame start
5339 * event which is after the vblank start event, so we need to have a
5340 * wait-for-vblank between disabling the plane and the pipe.
5341 */
5342 intel_set_memory_cxsr(dev_priv, false);
5343 intel_crtc_disable_planes(crtc);
5344
5345 /*
5346 * On gen2 planes are double buffered but the pipe isn't, so we must
5347 * wait for planes to fully turn off before disabling the pipe.
5348 * We also need to wait on all gmch platforms because of the
5349 * self-refresh mode constraint explained above.
5350 */
5351 intel_wait_for_vblank(dev, pipe);
5352
5353 for_each_encoder_on_crtc(dev, crtc, encoder)
5354 encoder->disable(encoder);
5355
5356 drm_crtc_vblank_off(crtc);
5357 assert_vblank_disabled(crtc);
5358
5359 intel_disable_pipe(intel_crtc);
5360
5361 i9xx_pfit_disable(intel_crtc);
5362
5363 for_each_encoder_on_crtc(dev, crtc, encoder)
5364 if (encoder->post_disable)
5365 encoder->post_disable(encoder);
5366
5367 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5368 if (IS_CHERRYVIEW(dev))
5369 chv_disable_pll(dev_priv, pipe);
5370 else if (IS_VALLEYVIEW(dev))
5371 vlv_disable_pll(dev_priv, pipe);
5372 else
5373 i9xx_disable_pll(intel_crtc);
5374 }
5375
5376 if (!IS_GEN2(dev))
5377 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5378
5379 intel_crtc->active = false;
5380 intel_update_watermarks(crtc);
5381
5382 mutex_lock(&dev->struct_mutex);
5383 intel_fbc_update(dev);
5384 mutex_unlock(&dev->struct_mutex);
5385 }
5386
5387 static void i9xx_crtc_off(struct drm_crtc *crtc)
5388 {
5389 }
5390
5391 /* Master function to enable/disable CRTC and corresponding power wells */
5392 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5393 {
5394 struct drm_device *dev = crtc->dev;
5395 struct drm_i915_private *dev_priv = dev->dev_private;
5396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5397 enum intel_display_power_domain domain;
5398 unsigned long domains;
5399
5400 if (enable) {
5401 if (!intel_crtc->active) {
5402 domains = get_crtc_power_domains(crtc);
5403 for_each_power_domain(domain, domains)
5404 intel_display_power_get(dev_priv, domain);
5405 intel_crtc->enabled_power_domains = domains;
5406
5407 dev_priv->display.crtc_enable(crtc);
5408 }
5409 } else {
5410 if (intel_crtc->active) {
5411 dev_priv->display.crtc_disable(crtc);
5412
5413 domains = intel_crtc->enabled_power_domains;
5414 for_each_power_domain(domain, domains)
5415 intel_display_power_put(dev_priv, domain);
5416 intel_crtc->enabled_power_domains = 0;
5417 }
5418 }
5419 }
5420
5421 /**
5422 * Sets the power management mode of the pipe and plane.
5423 */
5424 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5425 {
5426 struct drm_device *dev = crtc->dev;
5427 struct intel_encoder *intel_encoder;
5428 bool enable = false;
5429
5430 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5431 enable |= intel_encoder->connectors_active;
5432
5433 intel_crtc_control(crtc, enable);
5434 }
5435
5436 static void intel_crtc_disable(struct drm_crtc *crtc)
5437 {
5438 struct drm_device *dev = crtc->dev;
5439 struct drm_connector *connector;
5440 struct drm_i915_private *dev_priv = dev->dev_private;
5441
5442 /* crtc should still be enabled when we disable it. */
5443 WARN_ON(!crtc->state->enable);
5444
5445 dev_priv->display.crtc_disable(crtc);
5446 dev_priv->display.off(crtc);
5447
5448 crtc->primary->funcs->disable_plane(crtc->primary);
5449
5450 /* Update computed state. */
5451 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5452 if (!connector->encoder || !connector->encoder->crtc)
5453 continue;
5454
5455 if (connector->encoder->crtc != crtc)
5456 continue;
5457
5458 connector->dpms = DRM_MODE_DPMS_OFF;
5459 to_intel_encoder(connector->encoder)->connectors_active = false;
5460 }
5461 }
5462
5463 void intel_encoder_destroy(struct drm_encoder *encoder)
5464 {
5465 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5466
5467 drm_encoder_cleanup(encoder);
5468 kfree(intel_encoder);
5469 }
5470
5471 /* Simple dpms helper for encoders with just one connector, no cloning and only
5472 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5473 * state of the entire output pipe. */
5474 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5475 {
5476 if (mode == DRM_MODE_DPMS_ON) {
5477 encoder->connectors_active = true;
5478
5479 intel_crtc_update_dpms(encoder->base.crtc);
5480 } else {
5481 encoder->connectors_active = false;
5482
5483 intel_crtc_update_dpms(encoder->base.crtc);
5484 }
5485 }
5486
5487 /* Cross check the actual hw state with our own modeset state tracking (and it's
5488 * internal consistency). */
5489 static void intel_connector_check_state(struct intel_connector *connector)
5490 {
5491 if (connector->get_hw_state(connector)) {
5492 struct intel_encoder *encoder = connector->encoder;
5493 struct drm_crtc *crtc;
5494 bool encoder_enabled;
5495 enum pipe pipe;
5496
5497 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5498 connector->base.base.id,
5499 connector->base.name);
5500
5501 /* there is no real hw state for MST connectors */
5502 if (connector->mst_port)
5503 return;
5504
5505 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5506 "wrong connector dpms state\n");
5507 I915_STATE_WARN(connector->base.encoder != &encoder->base,
5508 "active connector not linked to encoder\n");
5509
5510 if (encoder) {
5511 I915_STATE_WARN(!encoder->connectors_active,
5512 "encoder->connectors_active not set\n");
5513
5514 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5515 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5516 if (I915_STATE_WARN_ON(!encoder->base.crtc))
5517 return;
5518
5519 crtc = encoder->base.crtc;
5520
5521 I915_STATE_WARN(!crtc->state->enable,
5522 "crtc not enabled\n");
5523 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5524 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
5525 "encoder active on the wrong pipe\n");
5526 }
5527 }
5528 }
5529
5530 /* Even simpler default implementation, if there's really no special case to
5531 * consider. */
5532 void intel_connector_dpms(struct drm_connector *connector, int mode)
5533 {
5534 /* All the simple cases only support two dpms states. */
5535 if (mode != DRM_MODE_DPMS_ON)
5536 mode = DRM_MODE_DPMS_OFF;
5537
5538 if (mode == connector->dpms)
5539 return;
5540
5541 connector->dpms = mode;
5542
5543 /* Only need to change hw state when actually enabled */
5544 if (connector->encoder)
5545 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5546
5547 intel_modeset_check_state(connector->dev);
5548 }
5549
5550 /* Simple connector->get_hw_state implementation for encoders that support only
5551 * one connector and no cloning and hence the encoder state determines the state
5552 * of the connector. */
5553 bool intel_connector_get_hw_state(struct intel_connector *connector)
5554 {
5555 enum pipe pipe = 0;
5556 struct intel_encoder *encoder = connector->encoder;
5557
5558 return encoder->get_hw_state(encoder, &pipe);
5559 }
5560
5561 static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5562 {
5563 struct intel_crtc *crtc =
5564 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5565
5566 if (crtc->base.state->enable &&
5567 crtc->config->has_pch_encoder)
5568 return crtc->config->fdi_lanes;
5569
5570 return 0;
5571 }
5572
5573 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5574 struct intel_crtc_state *pipe_config)
5575 {
5576 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5577 pipe_name(pipe), pipe_config->fdi_lanes);
5578 if (pipe_config->fdi_lanes > 4) {
5579 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5580 pipe_name(pipe), pipe_config->fdi_lanes);
5581 return false;
5582 }
5583
5584 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5585 if (pipe_config->fdi_lanes > 2) {
5586 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5587 pipe_config->fdi_lanes);
5588 return false;
5589 } else {
5590 return true;
5591 }
5592 }
5593
5594 if (INTEL_INFO(dev)->num_pipes == 2)
5595 return true;
5596
5597 /* Ivybridge 3 pipe is really complicated */
5598 switch (pipe) {
5599 case PIPE_A:
5600 return true;
5601 case PIPE_B:
5602 if (pipe_config->fdi_lanes > 2 &&
5603 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
5604 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5605 pipe_name(pipe), pipe_config->fdi_lanes);
5606 return false;
5607 }
5608 return true;
5609 case PIPE_C:
5610 if (pipe_config->fdi_lanes > 2) {
5611 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5612 pipe_name(pipe), pipe_config->fdi_lanes);
5613 return false;
5614 }
5615 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
5616 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5617 return false;
5618 }
5619 return true;
5620 default:
5621 BUG();
5622 }
5623 }
5624
5625 #define RETRY 1
5626 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5627 struct intel_crtc_state *pipe_config)
5628 {
5629 struct drm_device *dev = intel_crtc->base.dev;
5630 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5631 int lane, link_bw, fdi_dotclock;
5632 bool setup_ok, needs_recompute = false;
5633
5634 retry:
5635 /* FDI is a binary signal running at ~2.7GHz, encoding
5636 * each output octet as 10 bits. The actual frequency
5637 * is stored as a divider into a 100MHz clock, and the
5638 * mode pixel clock is stored in units of 1KHz.
5639 * Hence the bw of each lane in terms of the mode signal
5640 * is:
5641 */
5642 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5643
5644 fdi_dotclock = adjusted_mode->crtc_clock;
5645
5646 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5647 pipe_config->pipe_bpp);
5648
5649 pipe_config->fdi_lanes = lane;
5650
5651 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5652 link_bw, &pipe_config->fdi_m_n);
5653
5654 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5655 intel_crtc->pipe, pipe_config);
5656 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5657 pipe_config->pipe_bpp -= 2*3;
5658 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5659 pipe_config->pipe_bpp);
5660 needs_recompute = true;
5661 pipe_config->bw_constrained = true;
5662
5663 goto retry;
5664 }
5665
5666 if (needs_recompute)
5667 return RETRY;
5668
5669 return setup_ok ? 0 : -EINVAL;
5670 }
5671
5672 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5673 struct intel_crtc_state *pipe_config)
5674 {
5675 pipe_config->ips_enabled = i915.enable_ips &&
5676 hsw_crtc_supports_ips(crtc) &&
5677 pipe_config->pipe_bpp <= 24;
5678 }
5679
5680 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5681 struct intel_crtc_state *pipe_config)
5682 {
5683 struct drm_device *dev = crtc->base.dev;
5684 struct drm_i915_private *dev_priv = dev->dev_private;
5685 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
5686
5687 /* FIXME should check pixel clock limits on all platforms */
5688 if (INTEL_INFO(dev)->gen < 4) {
5689 int clock_limit =
5690 dev_priv->display.get_display_clock_speed(dev);
5691
5692 /*
5693 * Enable pixel doubling when the dot clock
5694 * is > 90% of the (display) core speed.
5695 *
5696 * GDG double wide on either pipe,
5697 * otherwise pipe A only.
5698 */
5699 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5700 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5701 clock_limit *= 2;
5702 pipe_config->double_wide = true;
5703 }
5704
5705 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5706 return -EINVAL;
5707 }
5708
5709 /*
5710 * Pipe horizontal size must be even in:
5711 * - DVO ganged mode
5712 * - LVDS dual channel mode
5713 * - Double wide pipe
5714 */
5715 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5716 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5717 pipe_config->pipe_src_w &= ~1;
5718
5719 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5720 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5721 */
5722 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5723 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5724 return -EINVAL;
5725
5726 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5727 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5728 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5729 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5730 * for lvds. */
5731 pipe_config->pipe_bpp = 8*3;
5732 }
5733
5734 if (HAS_IPS(dev))
5735 hsw_compute_ips_config(crtc, pipe_config);
5736
5737 if (pipe_config->has_pch_encoder)
5738 return ironlake_fdi_compute_config(crtc, pipe_config);
5739
5740 return 0;
5741 }
5742
5743 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5744 {
5745 struct drm_i915_private *dev_priv = dev->dev_private;
5746 u32 val;
5747 int divider;
5748
5749 if (dev_priv->hpll_freq == 0)
5750 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5751
5752 mutex_lock(&dev_priv->dpio_lock);
5753 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5754 mutex_unlock(&dev_priv->dpio_lock);
5755
5756 divider = val & DISPLAY_FREQUENCY_VALUES;
5757
5758 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5759 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5760 "cdclk change in progress\n");
5761
5762 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
5763 }
5764
5765 static int i945_get_display_clock_speed(struct drm_device *dev)
5766 {
5767 return 400000;
5768 }
5769
5770 static int i915_get_display_clock_speed(struct drm_device *dev)
5771 {
5772 return 333000;
5773 }
5774
5775 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5776 {
5777 return 200000;
5778 }
5779
5780 static int pnv_get_display_clock_speed(struct drm_device *dev)
5781 {
5782 u16 gcfgc = 0;
5783
5784 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5785
5786 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5787 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5788 return 267000;
5789 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5790 return 333000;
5791 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5792 return 444000;
5793 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5794 return 200000;
5795 default:
5796 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5797 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5798 return 133000;
5799 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5800 return 167000;
5801 }
5802 }
5803
5804 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5805 {
5806 u16 gcfgc = 0;
5807
5808 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5809
5810 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5811 return 133000;
5812 else {
5813 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5814 case GC_DISPLAY_CLOCK_333_MHZ:
5815 return 333000;
5816 default:
5817 case GC_DISPLAY_CLOCK_190_200_MHZ:
5818 return 190000;
5819 }
5820 }
5821 }
5822
5823 static int i865_get_display_clock_speed(struct drm_device *dev)
5824 {
5825 return 266000;
5826 }
5827
5828 static int i855_get_display_clock_speed(struct drm_device *dev)
5829 {
5830 u16 hpllcc = 0;
5831 /* Assume that the hardware is in the high speed state. This
5832 * should be the default.
5833 */
5834 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5835 case GC_CLOCK_133_200:
5836 case GC_CLOCK_100_200:
5837 return 200000;
5838 case GC_CLOCK_166_250:
5839 return 250000;
5840 case GC_CLOCK_100_133:
5841 return 133000;
5842 }
5843
5844 /* Shouldn't happen */
5845 return 0;
5846 }
5847
5848 static int i830_get_display_clock_speed(struct drm_device *dev)
5849 {
5850 return 133000;
5851 }
5852
5853 static void
5854 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5855 {
5856 while (*num > DATA_LINK_M_N_MASK ||
5857 *den > DATA_LINK_M_N_MASK) {
5858 *num >>= 1;
5859 *den >>= 1;
5860 }
5861 }
5862
5863 static void compute_m_n(unsigned int m, unsigned int n,
5864 uint32_t *ret_m, uint32_t *ret_n)
5865 {
5866 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5867 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5868 intel_reduce_m_n_ratio(ret_m, ret_n);
5869 }
5870
5871 void
5872 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5873 int pixel_clock, int link_clock,
5874 struct intel_link_m_n *m_n)
5875 {
5876 m_n->tu = 64;
5877
5878 compute_m_n(bits_per_pixel * pixel_clock,
5879 link_clock * nlanes * 8,
5880 &m_n->gmch_m, &m_n->gmch_n);
5881
5882 compute_m_n(pixel_clock, link_clock,
5883 &m_n->link_m, &m_n->link_n);
5884 }
5885
5886 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5887 {
5888 if (i915.panel_use_ssc >= 0)
5889 return i915.panel_use_ssc != 0;
5890 return dev_priv->vbt.lvds_use_ssc
5891 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5892 }
5893
5894 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5895 {
5896 struct drm_device *dev = crtc->base.dev;
5897 struct drm_i915_private *dev_priv = dev->dev_private;
5898 int refclk;
5899
5900 if (IS_VALLEYVIEW(dev)) {
5901 refclk = 100000;
5902 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5903 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5904 refclk = dev_priv->vbt.lvds_ssc_freq;
5905 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5906 } else if (!IS_GEN2(dev)) {
5907 refclk = 96000;
5908 } else {
5909 refclk = 48000;
5910 }
5911
5912 return refclk;
5913 }
5914
5915 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5916 {
5917 return (1 << dpll->n) << 16 | dpll->m2;
5918 }
5919
5920 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5921 {
5922 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5923 }
5924
5925 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5926 struct intel_crtc_state *crtc_state,
5927 intel_clock_t *reduced_clock)
5928 {
5929 struct drm_device *dev = crtc->base.dev;
5930 u32 fp, fp2 = 0;
5931
5932 if (IS_PINEVIEW(dev)) {
5933 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
5934 if (reduced_clock)
5935 fp2 = pnv_dpll_compute_fp(reduced_clock);
5936 } else {
5937 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
5938 if (reduced_clock)
5939 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5940 }
5941
5942 crtc_state->dpll_hw_state.fp0 = fp;
5943
5944 crtc->lowfreq_avail = false;
5945 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5946 reduced_clock && i915.powersave) {
5947 crtc_state->dpll_hw_state.fp1 = fp2;
5948 crtc->lowfreq_avail = true;
5949 } else {
5950 crtc_state->dpll_hw_state.fp1 = fp;
5951 }
5952 }
5953
5954 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5955 pipe)
5956 {
5957 u32 reg_val;
5958
5959 /*
5960 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5961 * and set it to a reasonable value instead.
5962 */
5963 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5964 reg_val &= 0xffffff00;
5965 reg_val |= 0x00000030;
5966 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5967
5968 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5969 reg_val &= 0x8cffffff;
5970 reg_val = 0x8c000000;
5971 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5972
5973 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5974 reg_val &= 0xffffff00;
5975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5976
5977 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5978 reg_val &= 0x00ffffff;
5979 reg_val |= 0xb0000000;
5980 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5981 }
5982
5983 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5984 struct intel_link_m_n *m_n)
5985 {
5986 struct drm_device *dev = crtc->base.dev;
5987 struct drm_i915_private *dev_priv = dev->dev_private;
5988 int pipe = crtc->pipe;
5989
5990 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5991 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5992 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5993 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5994 }
5995
5996 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5997 struct intel_link_m_n *m_n,
5998 struct intel_link_m_n *m2_n2)
5999 {
6000 struct drm_device *dev = crtc->base.dev;
6001 struct drm_i915_private *dev_priv = dev->dev_private;
6002 int pipe = crtc->pipe;
6003 enum transcoder transcoder = crtc->config->cpu_transcoder;
6004
6005 if (INTEL_INFO(dev)->gen >= 5) {
6006 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6007 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6008 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6009 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6010 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6011 * for gen < 8) and if DRRS is supported (to make sure the
6012 * registers are not unnecessarily accessed).
6013 */
6014 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6015 crtc->config->has_drrs) {
6016 I915_WRITE(PIPE_DATA_M2(transcoder),
6017 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6018 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6019 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6020 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6021 }
6022 } else {
6023 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6024 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6025 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6026 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6027 }
6028 }
6029
6030 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6031 {
6032 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6033
6034 if (m_n == M1_N1) {
6035 dp_m_n = &crtc->config->dp_m_n;
6036 dp_m2_n2 = &crtc->config->dp_m2_n2;
6037 } else if (m_n == M2_N2) {
6038
6039 /*
6040 * M2_N2 registers are not supported. Hence m2_n2 divider value
6041 * needs to be programmed into M1_N1.
6042 */
6043 dp_m_n = &crtc->config->dp_m2_n2;
6044 } else {
6045 DRM_ERROR("Unsupported divider value\n");
6046 return;
6047 }
6048
6049 if (crtc->config->has_pch_encoder)
6050 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6051 else
6052 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6053 }
6054
6055 static void vlv_update_pll(struct intel_crtc *crtc,
6056 struct intel_crtc_state *pipe_config)
6057 {
6058 u32 dpll, dpll_md;
6059
6060 /*
6061 * Enable DPIO clock input. We should never disable the reference
6062 * clock for pipe B, since VGA hotplug / manual detection depends
6063 * on it.
6064 */
6065 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6066 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6067 /* We should never disable this, set it here for state tracking */
6068 if (crtc->pipe == PIPE_B)
6069 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6070 dpll |= DPLL_VCO_ENABLE;
6071 pipe_config->dpll_hw_state.dpll = dpll;
6072
6073 dpll_md = (pipe_config->pixel_multiplier - 1)
6074 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6075 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6076 }
6077
6078 static void vlv_prepare_pll(struct intel_crtc *crtc,
6079 const struct intel_crtc_state *pipe_config)
6080 {
6081 struct drm_device *dev = crtc->base.dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 int pipe = crtc->pipe;
6084 u32 mdiv;
6085 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6086 u32 coreclk, reg_val;
6087
6088 mutex_lock(&dev_priv->dpio_lock);
6089
6090 bestn = pipe_config->dpll.n;
6091 bestm1 = pipe_config->dpll.m1;
6092 bestm2 = pipe_config->dpll.m2;
6093 bestp1 = pipe_config->dpll.p1;
6094 bestp2 = pipe_config->dpll.p2;
6095
6096 /* See eDP HDMI DPIO driver vbios notes doc */
6097
6098 /* PLL B needs special handling */
6099 if (pipe == PIPE_B)
6100 vlv_pllb_recal_opamp(dev_priv, pipe);
6101
6102 /* Set up Tx target for periodic Rcomp update */
6103 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6104
6105 /* Disable target IRef on PLL */
6106 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6107 reg_val &= 0x00ffffff;
6108 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6109
6110 /* Disable fast lock */
6111 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6112
6113 /* Set idtafcrecal before PLL is enabled */
6114 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6115 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6116 mdiv |= ((bestn << DPIO_N_SHIFT));
6117 mdiv |= (1 << DPIO_K_SHIFT);
6118
6119 /*
6120 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6121 * but we don't support that).
6122 * Note: don't use the DAC post divider as it seems unstable.
6123 */
6124 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6125 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6126
6127 mdiv |= DPIO_ENABLE_CALIBRATION;
6128 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6129
6130 /* Set HBR and RBR LPF coefficients */
6131 if (pipe_config->port_clock == 162000 ||
6132 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6133 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6134 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6135 0x009f0003);
6136 else
6137 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6138 0x00d0000f);
6139
6140 if (pipe_config->has_dp_encoder) {
6141 /* Use SSC source */
6142 if (pipe == PIPE_A)
6143 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6144 0x0df40000);
6145 else
6146 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6147 0x0df70000);
6148 } else { /* HDMI or VGA */
6149 /* Use bend source */
6150 if (pipe == PIPE_A)
6151 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6152 0x0df70000);
6153 else
6154 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6155 0x0df40000);
6156 }
6157
6158 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6159 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6160 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6161 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6162 coreclk |= 0x01000000;
6163 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6164
6165 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6166 mutex_unlock(&dev_priv->dpio_lock);
6167 }
6168
6169 static void chv_update_pll(struct intel_crtc *crtc,
6170 struct intel_crtc_state *pipe_config)
6171 {
6172 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6173 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6174 DPLL_VCO_ENABLE;
6175 if (crtc->pipe != PIPE_A)
6176 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6177
6178 pipe_config->dpll_hw_state.dpll_md =
6179 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6180 }
6181
6182 static void chv_prepare_pll(struct intel_crtc *crtc,
6183 const struct intel_crtc_state *pipe_config)
6184 {
6185 struct drm_device *dev = crtc->base.dev;
6186 struct drm_i915_private *dev_priv = dev->dev_private;
6187 int pipe = crtc->pipe;
6188 int dpll_reg = DPLL(crtc->pipe);
6189 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6190 u32 loopfilter, tribuf_calcntr;
6191 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
6192 u32 dpio_val;
6193 int vco;
6194
6195 bestn = pipe_config->dpll.n;
6196 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6197 bestm1 = pipe_config->dpll.m1;
6198 bestm2 = pipe_config->dpll.m2 >> 22;
6199 bestp1 = pipe_config->dpll.p1;
6200 bestp2 = pipe_config->dpll.p2;
6201 vco = pipe_config->dpll.vco;
6202 dpio_val = 0;
6203 loopfilter = 0;
6204
6205 /*
6206 * Enable Refclk and SSC
6207 */
6208 I915_WRITE(dpll_reg,
6209 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
6210
6211 mutex_lock(&dev_priv->dpio_lock);
6212
6213 /* p1 and p2 divider */
6214 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6215 5 << DPIO_CHV_S1_DIV_SHIFT |
6216 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6217 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6218 1 << DPIO_CHV_K_DIV_SHIFT);
6219
6220 /* Feedback post-divider - m2 */
6221 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6222
6223 /* Feedback refclk divider - n and m1 */
6224 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6225 DPIO_CHV_M1_DIV_BY_2 |
6226 1 << DPIO_CHV_N_DIV_SHIFT);
6227
6228 /* M2 fraction division */
6229 if (bestm2_frac)
6230 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6231
6232 /* M2 fraction division enable */
6233 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6234 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6235 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6236 if (bestm2_frac)
6237 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6238 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
6239
6240 /* Program digital lock detect threshold */
6241 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6242 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6243 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6244 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6245 if (!bestm2_frac)
6246 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6247 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6248
6249 /* Loop filter */
6250 if (vco == 5400000) {
6251 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6252 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6253 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6254 tribuf_calcntr = 0x9;
6255 } else if (vco <= 6200000) {
6256 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6257 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6258 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6259 tribuf_calcntr = 0x9;
6260 } else if (vco <= 6480000) {
6261 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6262 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6263 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6264 tribuf_calcntr = 0x8;
6265 } else {
6266 /* Not supported. Apply the same limits as in the max case */
6267 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6268 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6269 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6270 tribuf_calcntr = 0;
6271 }
6272 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6273
6274 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
6275 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6276 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6277 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6278
6279 /* AFC Recal */
6280 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6281 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6282 DPIO_AFC_RECAL);
6283
6284 mutex_unlock(&dev_priv->dpio_lock);
6285 }
6286
6287 /**
6288 * vlv_force_pll_on - forcibly enable just the PLL
6289 * @dev_priv: i915 private structure
6290 * @pipe: pipe PLL to enable
6291 * @dpll: PLL configuration
6292 *
6293 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6294 * in cases where we need the PLL enabled even when @pipe is not going to
6295 * be enabled.
6296 */
6297 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6298 const struct dpll *dpll)
6299 {
6300 struct intel_crtc *crtc =
6301 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6302 struct intel_crtc_state pipe_config = {
6303 .pixel_multiplier = 1,
6304 .dpll = *dpll,
6305 };
6306
6307 if (IS_CHERRYVIEW(dev)) {
6308 chv_update_pll(crtc, &pipe_config);
6309 chv_prepare_pll(crtc, &pipe_config);
6310 chv_enable_pll(crtc, &pipe_config);
6311 } else {
6312 vlv_update_pll(crtc, &pipe_config);
6313 vlv_prepare_pll(crtc, &pipe_config);
6314 vlv_enable_pll(crtc, &pipe_config);
6315 }
6316 }
6317
6318 /**
6319 * vlv_force_pll_off - forcibly disable just the PLL
6320 * @dev_priv: i915 private structure
6321 * @pipe: pipe PLL to disable
6322 *
6323 * Disable the PLL for @pipe. To be used in cases where we need
6324 * the PLL enabled even when @pipe is not going to be enabled.
6325 */
6326 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6327 {
6328 if (IS_CHERRYVIEW(dev))
6329 chv_disable_pll(to_i915(dev), pipe);
6330 else
6331 vlv_disable_pll(to_i915(dev), pipe);
6332 }
6333
6334 static void i9xx_update_pll(struct intel_crtc *crtc,
6335 struct intel_crtc_state *crtc_state,
6336 intel_clock_t *reduced_clock,
6337 int num_connectors)
6338 {
6339 struct drm_device *dev = crtc->base.dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 u32 dpll;
6342 bool is_sdvo;
6343 struct dpll *clock = &crtc_state->dpll;
6344
6345 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6346
6347 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6348 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6349
6350 dpll = DPLL_VGA_MODE_DIS;
6351
6352 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6353 dpll |= DPLLB_MODE_LVDS;
6354 else
6355 dpll |= DPLLB_MODE_DAC_SERIAL;
6356
6357 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6358 dpll |= (crtc_state->pixel_multiplier - 1)
6359 << SDVO_MULTIPLIER_SHIFT_HIRES;
6360 }
6361
6362 if (is_sdvo)
6363 dpll |= DPLL_SDVO_HIGH_SPEED;
6364
6365 if (crtc_state->has_dp_encoder)
6366 dpll |= DPLL_SDVO_HIGH_SPEED;
6367
6368 /* compute bitmask from p1 value */
6369 if (IS_PINEVIEW(dev))
6370 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6371 else {
6372 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6373 if (IS_G4X(dev) && reduced_clock)
6374 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6375 }
6376 switch (clock->p2) {
6377 case 5:
6378 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6379 break;
6380 case 7:
6381 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6382 break;
6383 case 10:
6384 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6385 break;
6386 case 14:
6387 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6388 break;
6389 }
6390 if (INTEL_INFO(dev)->gen >= 4)
6391 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6392
6393 if (crtc_state->sdvo_tv_clock)
6394 dpll |= PLL_REF_INPUT_TVCLKINBC;
6395 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6396 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6397 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6398 else
6399 dpll |= PLL_REF_INPUT_DREFCLK;
6400
6401 dpll |= DPLL_VCO_ENABLE;
6402 crtc_state->dpll_hw_state.dpll = dpll;
6403
6404 if (INTEL_INFO(dev)->gen >= 4) {
6405 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
6406 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6407 crtc_state->dpll_hw_state.dpll_md = dpll_md;
6408 }
6409 }
6410
6411 static void i8xx_update_pll(struct intel_crtc *crtc,
6412 struct intel_crtc_state *crtc_state,
6413 intel_clock_t *reduced_clock,
6414 int num_connectors)
6415 {
6416 struct drm_device *dev = crtc->base.dev;
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6418 u32 dpll;
6419 struct dpll *clock = &crtc_state->dpll;
6420
6421 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
6422
6423 dpll = DPLL_VGA_MODE_DIS;
6424
6425 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6426 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6427 } else {
6428 if (clock->p1 == 2)
6429 dpll |= PLL_P1_DIVIDE_BY_TWO;
6430 else
6431 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6432 if (clock->p2 == 4)
6433 dpll |= PLL_P2_DIVIDE_BY_4;
6434 }
6435
6436 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6437 dpll |= DPLL_DVO_2X_MODE;
6438
6439 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6440 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6441 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6442 else
6443 dpll |= PLL_REF_INPUT_DREFCLK;
6444
6445 dpll |= DPLL_VCO_ENABLE;
6446 crtc_state->dpll_hw_state.dpll = dpll;
6447 }
6448
6449 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6450 {
6451 struct drm_device *dev = intel_crtc->base.dev;
6452 struct drm_i915_private *dev_priv = dev->dev_private;
6453 enum pipe pipe = intel_crtc->pipe;
6454 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
6455 struct drm_display_mode *adjusted_mode =
6456 &intel_crtc->config->base.adjusted_mode;
6457 uint32_t crtc_vtotal, crtc_vblank_end;
6458 int vsyncshift = 0;
6459
6460 /* We need to be careful not to changed the adjusted mode, for otherwise
6461 * the hw state checker will get angry at the mismatch. */
6462 crtc_vtotal = adjusted_mode->crtc_vtotal;
6463 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6464
6465 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6466 /* the chip adds 2 halflines automatically */
6467 crtc_vtotal -= 1;
6468 crtc_vblank_end -= 1;
6469
6470 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6471 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6472 else
6473 vsyncshift = adjusted_mode->crtc_hsync_start -
6474 adjusted_mode->crtc_htotal / 2;
6475 if (vsyncshift < 0)
6476 vsyncshift += adjusted_mode->crtc_htotal;
6477 }
6478
6479 if (INTEL_INFO(dev)->gen > 3)
6480 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6481
6482 I915_WRITE(HTOTAL(cpu_transcoder),
6483 (adjusted_mode->crtc_hdisplay - 1) |
6484 ((adjusted_mode->crtc_htotal - 1) << 16));
6485 I915_WRITE(HBLANK(cpu_transcoder),
6486 (adjusted_mode->crtc_hblank_start - 1) |
6487 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6488 I915_WRITE(HSYNC(cpu_transcoder),
6489 (adjusted_mode->crtc_hsync_start - 1) |
6490 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6491
6492 I915_WRITE(VTOTAL(cpu_transcoder),
6493 (adjusted_mode->crtc_vdisplay - 1) |
6494 ((crtc_vtotal - 1) << 16));
6495 I915_WRITE(VBLANK(cpu_transcoder),
6496 (adjusted_mode->crtc_vblank_start - 1) |
6497 ((crtc_vblank_end - 1) << 16));
6498 I915_WRITE(VSYNC(cpu_transcoder),
6499 (adjusted_mode->crtc_vsync_start - 1) |
6500 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6501
6502 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6503 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6504 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6505 * bits. */
6506 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6507 (pipe == PIPE_B || pipe == PIPE_C))
6508 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6509
6510 /* pipesrc controls the size that is scaled from, which should
6511 * always be the user's requested size.
6512 */
6513 I915_WRITE(PIPESRC(pipe),
6514 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6515 (intel_crtc->config->pipe_src_h - 1));
6516 }
6517
6518 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6519 struct intel_crtc_state *pipe_config)
6520 {
6521 struct drm_device *dev = crtc->base.dev;
6522 struct drm_i915_private *dev_priv = dev->dev_private;
6523 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6524 uint32_t tmp;
6525
6526 tmp = I915_READ(HTOTAL(cpu_transcoder));
6527 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6528 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6529 tmp = I915_READ(HBLANK(cpu_transcoder));
6530 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6531 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6532 tmp = I915_READ(HSYNC(cpu_transcoder));
6533 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6534 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6535
6536 tmp = I915_READ(VTOTAL(cpu_transcoder));
6537 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6538 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6539 tmp = I915_READ(VBLANK(cpu_transcoder));
6540 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6541 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6542 tmp = I915_READ(VSYNC(cpu_transcoder));
6543 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6544 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6545
6546 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6547 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6548 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6549 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
6550 }
6551
6552 tmp = I915_READ(PIPESRC(crtc->pipe));
6553 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6554 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6555
6556 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6557 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
6558 }
6559
6560 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6561 struct intel_crtc_state *pipe_config)
6562 {
6563 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6564 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6565 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6566 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
6567
6568 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6569 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6570 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6571 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
6572
6573 mode->flags = pipe_config->base.adjusted_mode.flags;
6574
6575 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6576 mode->flags |= pipe_config->base.adjusted_mode.flags;
6577 }
6578
6579 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6580 {
6581 struct drm_device *dev = intel_crtc->base.dev;
6582 struct drm_i915_private *dev_priv = dev->dev_private;
6583 uint32_t pipeconf;
6584
6585 pipeconf = 0;
6586
6587 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6588 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6589 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6590
6591 if (intel_crtc->config->double_wide)
6592 pipeconf |= PIPECONF_DOUBLE_WIDE;
6593
6594 /* only g4x and later have fancy bpc/dither controls */
6595 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6596 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6597 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
6598 pipeconf |= PIPECONF_DITHER_EN |
6599 PIPECONF_DITHER_TYPE_SP;
6600
6601 switch (intel_crtc->config->pipe_bpp) {
6602 case 18:
6603 pipeconf |= PIPECONF_6BPC;
6604 break;
6605 case 24:
6606 pipeconf |= PIPECONF_8BPC;
6607 break;
6608 case 30:
6609 pipeconf |= PIPECONF_10BPC;
6610 break;
6611 default:
6612 /* Case prevented by intel_choose_pipe_bpp_dither. */
6613 BUG();
6614 }
6615 }
6616
6617 if (HAS_PIPE_CXSR(dev)) {
6618 if (intel_crtc->lowfreq_avail) {
6619 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6620 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6621 } else {
6622 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6623 }
6624 }
6625
6626 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6627 if (INTEL_INFO(dev)->gen < 4 ||
6628 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6629 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6630 else
6631 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6632 } else
6633 pipeconf |= PIPECONF_PROGRESSIVE;
6634
6635 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
6636 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6637
6638 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6639 POSTING_READ(PIPECONF(intel_crtc->pipe));
6640 }
6641
6642 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6643 struct intel_crtc_state *crtc_state)
6644 {
6645 struct drm_device *dev = crtc->base.dev;
6646 struct drm_i915_private *dev_priv = dev->dev_private;
6647 int refclk, num_connectors = 0;
6648 intel_clock_t clock, reduced_clock;
6649 bool ok, has_reduced_clock = false;
6650 bool is_lvds = false, is_dsi = false;
6651 struct intel_encoder *encoder;
6652 const intel_limit_t *limit;
6653
6654 for_each_intel_encoder(dev, encoder) {
6655 if (encoder->new_crtc != crtc)
6656 continue;
6657
6658 switch (encoder->type) {
6659 case INTEL_OUTPUT_LVDS:
6660 is_lvds = true;
6661 break;
6662 case INTEL_OUTPUT_DSI:
6663 is_dsi = true;
6664 break;
6665 default:
6666 break;
6667 }
6668
6669 num_connectors++;
6670 }
6671
6672 if (is_dsi)
6673 return 0;
6674
6675 if (!crtc_state->clock_set) {
6676 refclk = i9xx_get_refclk(crtc, num_connectors);
6677
6678 /*
6679 * Returns a set of divisors for the desired target clock with
6680 * the given refclk, or FALSE. The returned values represent
6681 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6682 * 2) / p1 / p2.
6683 */
6684 limit = intel_limit(crtc, refclk);
6685 ok = dev_priv->display.find_dpll(limit, crtc,
6686 crtc_state->port_clock,
6687 refclk, NULL, &clock);
6688 if (!ok) {
6689 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6690 return -EINVAL;
6691 }
6692
6693 if (is_lvds && dev_priv->lvds_downclock_avail) {
6694 /*
6695 * Ensure we match the reduced clock's P to the target
6696 * clock. If the clocks don't match, we can't switch
6697 * the display clock by using the FP0/FP1. In such case
6698 * we will disable the LVDS downclock feature.
6699 */
6700 has_reduced_clock =
6701 dev_priv->display.find_dpll(limit, crtc,
6702 dev_priv->lvds_downclock,
6703 refclk, &clock,
6704 &reduced_clock);
6705 }
6706 /* Compat-code for transition, will disappear. */
6707 crtc_state->dpll.n = clock.n;
6708 crtc_state->dpll.m1 = clock.m1;
6709 crtc_state->dpll.m2 = clock.m2;
6710 crtc_state->dpll.p1 = clock.p1;
6711 crtc_state->dpll.p2 = clock.p2;
6712 }
6713
6714 if (IS_GEN2(dev)) {
6715 i8xx_update_pll(crtc, crtc_state,
6716 has_reduced_clock ? &reduced_clock : NULL,
6717 num_connectors);
6718 } else if (IS_CHERRYVIEW(dev)) {
6719 chv_update_pll(crtc, crtc_state);
6720 } else if (IS_VALLEYVIEW(dev)) {
6721 vlv_update_pll(crtc, crtc_state);
6722 } else {
6723 i9xx_update_pll(crtc, crtc_state,
6724 has_reduced_clock ? &reduced_clock : NULL,
6725 num_connectors);
6726 }
6727
6728 return 0;
6729 }
6730
6731 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6732 struct intel_crtc_state *pipe_config)
6733 {
6734 struct drm_device *dev = crtc->base.dev;
6735 struct drm_i915_private *dev_priv = dev->dev_private;
6736 uint32_t tmp;
6737
6738 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6739 return;
6740
6741 tmp = I915_READ(PFIT_CONTROL);
6742 if (!(tmp & PFIT_ENABLE))
6743 return;
6744
6745 /* Check whether the pfit is attached to our pipe. */
6746 if (INTEL_INFO(dev)->gen < 4) {
6747 if (crtc->pipe != PIPE_B)
6748 return;
6749 } else {
6750 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6751 return;
6752 }
6753
6754 pipe_config->gmch_pfit.control = tmp;
6755 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6756 if (INTEL_INFO(dev)->gen < 5)
6757 pipe_config->gmch_pfit.lvds_border_bits =
6758 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6759 }
6760
6761 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6762 struct intel_crtc_state *pipe_config)
6763 {
6764 struct drm_device *dev = crtc->base.dev;
6765 struct drm_i915_private *dev_priv = dev->dev_private;
6766 int pipe = pipe_config->cpu_transcoder;
6767 intel_clock_t clock;
6768 u32 mdiv;
6769 int refclk = 100000;
6770
6771 /* In case of MIPI DPLL will not even be used */
6772 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6773 return;
6774
6775 mutex_lock(&dev_priv->dpio_lock);
6776 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6777 mutex_unlock(&dev_priv->dpio_lock);
6778
6779 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6780 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6781 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6782 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6783 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6784
6785 vlv_clock(refclk, &clock);
6786
6787 /* clock.dot is the fast clock */
6788 pipe_config->port_clock = clock.dot / 5;
6789 }
6790
6791 static void
6792 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6793 struct intel_initial_plane_config *plane_config)
6794 {
6795 struct drm_device *dev = crtc->base.dev;
6796 struct drm_i915_private *dev_priv = dev->dev_private;
6797 u32 val, base, offset;
6798 int pipe = crtc->pipe, plane = crtc->plane;
6799 int fourcc, pixel_format;
6800 int aligned_height;
6801 struct drm_framebuffer *fb;
6802 struct intel_framebuffer *intel_fb;
6803
6804 val = I915_READ(DSPCNTR(plane));
6805 if (!(val & DISPLAY_PLANE_ENABLE))
6806 return;
6807
6808 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6809 if (!intel_fb) {
6810 DRM_DEBUG_KMS("failed to alloc fb\n");
6811 return;
6812 }
6813
6814 fb = &intel_fb->base;
6815
6816 if (INTEL_INFO(dev)->gen >= 4) {
6817 if (val & DISPPLANE_TILED) {
6818 plane_config->tiling = I915_TILING_X;
6819 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6820 }
6821 }
6822
6823 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6824 fourcc = i9xx_format_to_fourcc(pixel_format);
6825 fb->pixel_format = fourcc;
6826 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
6827
6828 if (INTEL_INFO(dev)->gen >= 4) {
6829 if (plane_config->tiling)
6830 offset = I915_READ(DSPTILEOFF(plane));
6831 else
6832 offset = I915_READ(DSPLINOFF(plane));
6833 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6834 } else {
6835 base = I915_READ(DSPADDR(plane));
6836 }
6837 plane_config->base = base;
6838
6839 val = I915_READ(PIPESRC(pipe));
6840 fb->width = ((val >> 16) & 0xfff) + 1;
6841 fb->height = ((val >> 0) & 0xfff) + 1;
6842
6843 val = I915_READ(DSPSTRIDE(pipe));
6844 fb->pitches[0] = val & 0xffffffc0;
6845
6846 aligned_height = intel_fb_align_height(dev, fb->height,
6847 fb->pixel_format,
6848 fb->modifier[0]);
6849
6850 plane_config->size = fb->pitches[0] * aligned_height;
6851
6852 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6853 pipe_name(pipe), plane, fb->width, fb->height,
6854 fb->bits_per_pixel, base, fb->pitches[0],
6855 plane_config->size);
6856
6857 plane_config->fb = intel_fb;
6858 }
6859
6860 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6861 struct intel_crtc_state *pipe_config)
6862 {
6863 struct drm_device *dev = crtc->base.dev;
6864 struct drm_i915_private *dev_priv = dev->dev_private;
6865 int pipe = pipe_config->cpu_transcoder;
6866 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6867 intel_clock_t clock;
6868 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6869 int refclk = 100000;
6870
6871 mutex_lock(&dev_priv->dpio_lock);
6872 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6873 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6874 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6875 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6876 mutex_unlock(&dev_priv->dpio_lock);
6877
6878 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6879 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6880 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6881 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6882 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6883
6884 chv_clock(refclk, &clock);
6885
6886 /* clock.dot is the fast clock */
6887 pipe_config->port_clock = clock.dot / 5;
6888 }
6889
6890 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6891 struct intel_crtc_state *pipe_config)
6892 {
6893 struct drm_device *dev = crtc->base.dev;
6894 struct drm_i915_private *dev_priv = dev->dev_private;
6895 uint32_t tmp;
6896
6897 if (!intel_display_power_is_enabled(dev_priv,
6898 POWER_DOMAIN_PIPE(crtc->pipe)))
6899 return false;
6900
6901 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6902 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6903
6904 tmp = I915_READ(PIPECONF(crtc->pipe));
6905 if (!(tmp & PIPECONF_ENABLE))
6906 return false;
6907
6908 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6909 switch (tmp & PIPECONF_BPC_MASK) {
6910 case PIPECONF_6BPC:
6911 pipe_config->pipe_bpp = 18;
6912 break;
6913 case PIPECONF_8BPC:
6914 pipe_config->pipe_bpp = 24;
6915 break;
6916 case PIPECONF_10BPC:
6917 pipe_config->pipe_bpp = 30;
6918 break;
6919 default:
6920 break;
6921 }
6922 }
6923
6924 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6925 pipe_config->limited_color_range = true;
6926
6927 if (INTEL_INFO(dev)->gen < 4)
6928 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6929
6930 intel_get_pipe_timings(crtc, pipe_config);
6931
6932 i9xx_get_pfit_config(crtc, pipe_config);
6933
6934 if (INTEL_INFO(dev)->gen >= 4) {
6935 tmp = I915_READ(DPLL_MD(crtc->pipe));
6936 pipe_config->pixel_multiplier =
6937 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6938 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6939 pipe_config->dpll_hw_state.dpll_md = tmp;
6940 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6941 tmp = I915_READ(DPLL(crtc->pipe));
6942 pipe_config->pixel_multiplier =
6943 ((tmp & SDVO_MULTIPLIER_MASK)
6944 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6945 } else {
6946 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6947 * port and will be fixed up in the encoder->get_config
6948 * function. */
6949 pipe_config->pixel_multiplier = 1;
6950 }
6951 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6952 if (!IS_VALLEYVIEW(dev)) {
6953 /*
6954 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6955 * on 830. Filter it out here so that we don't
6956 * report errors due to that.
6957 */
6958 if (IS_I830(dev))
6959 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6960
6961 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6962 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6963 } else {
6964 /* Mask out read-only status bits. */
6965 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6966 DPLL_PORTC_READY_MASK |
6967 DPLL_PORTB_READY_MASK);
6968 }
6969
6970 if (IS_CHERRYVIEW(dev))
6971 chv_crtc_clock_get(crtc, pipe_config);
6972 else if (IS_VALLEYVIEW(dev))
6973 vlv_crtc_clock_get(crtc, pipe_config);
6974 else
6975 i9xx_crtc_clock_get(crtc, pipe_config);
6976
6977 return true;
6978 }
6979
6980 static void ironlake_init_pch_refclk(struct drm_device *dev)
6981 {
6982 struct drm_i915_private *dev_priv = dev->dev_private;
6983 struct intel_encoder *encoder;
6984 u32 val, final;
6985 bool has_lvds = false;
6986 bool has_cpu_edp = false;
6987 bool has_panel = false;
6988 bool has_ck505 = false;
6989 bool can_ssc = false;
6990
6991 /* We need to take the global config into account */
6992 for_each_intel_encoder(dev, encoder) {
6993 switch (encoder->type) {
6994 case INTEL_OUTPUT_LVDS:
6995 has_panel = true;
6996 has_lvds = true;
6997 break;
6998 case INTEL_OUTPUT_EDP:
6999 has_panel = true;
7000 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7001 has_cpu_edp = true;
7002 break;
7003 default:
7004 break;
7005 }
7006 }
7007
7008 if (HAS_PCH_IBX(dev)) {
7009 has_ck505 = dev_priv->vbt.display_clock_mode;
7010 can_ssc = has_ck505;
7011 } else {
7012 has_ck505 = false;
7013 can_ssc = true;
7014 }
7015
7016 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7017 has_panel, has_lvds, has_ck505);
7018
7019 /* Ironlake: try to setup display ref clock before DPLL
7020 * enabling. This is only under driver's control after
7021 * PCH B stepping, previous chipset stepping should be
7022 * ignoring this setting.
7023 */
7024 val = I915_READ(PCH_DREF_CONTROL);
7025
7026 /* As we must carefully and slowly disable/enable each source in turn,
7027 * compute the final state we want first and check if we need to
7028 * make any changes at all.
7029 */
7030 final = val;
7031 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7032 if (has_ck505)
7033 final |= DREF_NONSPREAD_CK505_ENABLE;
7034 else
7035 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7036
7037 final &= ~DREF_SSC_SOURCE_MASK;
7038 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7039 final &= ~DREF_SSC1_ENABLE;
7040
7041 if (has_panel) {
7042 final |= DREF_SSC_SOURCE_ENABLE;
7043
7044 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7045 final |= DREF_SSC1_ENABLE;
7046
7047 if (has_cpu_edp) {
7048 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7049 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7050 else
7051 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7052 } else
7053 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7054 } else {
7055 final |= DREF_SSC_SOURCE_DISABLE;
7056 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7057 }
7058
7059 if (final == val)
7060 return;
7061
7062 /* Always enable nonspread source */
7063 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7064
7065 if (has_ck505)
7066 val |= DREF_NONSPREAD_CK505_ENABLE;
7067 else
7068 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7069
7070 if (has_panel) {
7071 val &= ~DREF_SSC_SOURCE_MASK;
7072 val |= DREF_SSC_SOURCE_ENABLE;
7073
7074 /* SSC must be turned on before enabling the CPU output */
7075 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7076 DRM_DEBUG_KMS("Using SSC on panel\n");
7077 val |= DREF_SSC1_ENABLE;
7078 } else
7079 val &= ~DREF_SSC1_ENABLE;
7080
7081 /* Get SSC going before enabling the outputs */
7082 I915_WRITE(PCH_DREF_CONTROL, val);
7083 POSTING_READ(PCH_DREF_CONTROL);
7084 udelay(200);
7085
7086 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7087
7088 /* Enable CPU source on CPU attached eDP */
7089 if (has_cpu_edp) {
7090 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7091 DRM_DEBUG_KMS("Using SSC on eDP\n");
7092 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7093 } else
7094 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7095 } else
7096 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7097
7098 I915_WRITE(PCH_DREF_CONTROL, val);
7099 POSTING_READ(PCH_DREF_CONTROL);
7100 udelay(200);
7101 } else {
7102 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7103
7104 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7105
7106 /* Turn off CPU output */
7107 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7108
7109 I915_WRITE(PCH_DREF_CONTROL, val);
7110 POSTING_READ(PCH_DREF_CONTROL);
7111 udelay(200);
7112
7113 /* Turn off the SSC source */
7114 val &= ~DREF_SSC_SOURCE_MASK;
7115 val |= DREF_SSC_SOURCE_DISABLE;
7116
7117 /* Turn off SSC1 */
7118 val &= ~DREF_SSC1_ENABLE;
7119
7120 I915_WRITE(PCH_DREF_CONTROL, val);
7121 POSTING_READ(PCH_DREF_CONTROL);
7122 udelay(200);
7123 }
7124
7125 BUG_ON(val != final);
7126 }
7127
7128 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7129 {
7130 uint32_t tmp;
7131
7132 tmp = I915_READ(SOUTH_CHICKEN2);
7133 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7134 I915_WRITE(SOUTH_CHICKEN2, tmp);
7135
7136 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7137 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7138 DRM_ERROR("FDI mPHY reset assert timeout\n");
7139
7140 tmp = I915_READ(SOUTH_CHICKEN2);
7141 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7142 I915_WRITE(SOUTH_CHICKEN2, tmp);
7143
7144 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7145 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7146 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7147 }
7148
7149 /* WaMPhyProgramming:hsw */
7150 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7151 {
7152 uint32_t tmp;
7153
7154 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7155 tmp &= ~(0xFF << 24);
7156 tmp |= (0x12 << 24);
7157 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7158
7159 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7160 tmp |= (1 << 11);
7161 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7162
7163 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7164 tmp |= (1 << 11);
7165 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7166
7167 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7168 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7169 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7170
7171 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7172 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7173 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7174
7175 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7176 tmp &= ~(7 << 13);
7177 tmp |= (5 << 13);
7178 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
7179
7180 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7181 tmp &= ~(7 << 13);
7182 tmp |= (5 << 13);
7183 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
7184
7185 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7186 tmp &= ~0xFF;
7187 tmp |= 0x1C;
7188 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7189
7190 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7191 tmp &= ~0xFF;
7192 tmp |= 0x1C;
7193 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7194
7195 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7196 tmp &= ~(0xFF << 16);
7197 tmp |= (0x1C << 16);
7198 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7199
7200 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7201 tmp &= ~(0xFF << 16);
7202 tmp |= (0x1C << 16);
7203 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7204
7205 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7206 tmp |= (1 << 27);
7207 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
7208
7209 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7210 tmp |= (1 << 27);
7211 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
7212
7213 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7214 tmp &= ~(0xF << 28);
7215 tmp |= (4 << 28);
7216 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
7217
7218 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7219 tmp &= ~(0xF << 28);
7220 tmp |= (4 << 28);
7221 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
7222 }
7223
7224 /* Implements 3 different sequences from BSpec chapter "Display iCLK
7225 * Programming" based on the parameters passed:
7226 * - Sequence to enable CLKOUT_DP
7227 * - Sequence to enable CLKOUT_DP without spread
7228 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7229 */
7230 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7231 bool with_fdi)
7232 {
7233 struct drm_i915_private *dev_priv = dev->dev_private;
7234 uint32_t reg, tmp;
7235
7236 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7237 with_spread = true;
7238 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7239 with_fdi, "LP PCH doesn't have FDI\n"))
7240 with_fdi = false;
7241
7242 mutex_lock(&dev_priv->dpio_lock);
7243
7244 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7245 tmp &= ~SBI_SSCCTL_DISABLE;
7246 tmp |= SBI_SSCCTL_PATHALT;
7247 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7248
7249 udelay(24);
7250
7251 if (with_spread) {
7252 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7253 tmp &= ~SBI_SSCCTL_PATHALT;
7254 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7255
7256 if (with_fdi) {
7257 lpt_reset_fdi_mphy(dev_priv);
7258 lpt_program_fdi_mphy(dev_priv);
7259 }
7260 }
7261
7262 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7263 SBI_GEN0 : SBI_DBUFF0;
7264 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7265 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7266 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7267
7268 mutex_unlock(&dev_priv->dpio_lock);
7269 }
7270
7271 /* Sequence to disable CLKOUT_DP */
7272 static void lpt_disable_clkout_dp(struct drm_device *dev)
7273 {
7274 struct drm_i915_private *dev_priv = dev->dev_private;
7275 uint32_t reg, tmp;
7276
7277 mutex_lock(&dev_priv->dpio_lock);
7278
7279 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7280 SBI_GEN0 : SBI_DBUFF0;
7281 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7282 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7283 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7284
7285 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7286 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7287 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7288 tmp |= SBI_SSCCTL_PATHALT;
7289 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7290 udelay(32);
7291 }
7292 tmp |= SBI_SSCCTL_DISABLE;
7293 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7294 }
7295
7296 mutex_unlock(&dev_priv->dpio_lock);
7297 }
7298
7299 static void lpt_init_pch_refclk(struct drm_device *dev)
7300 {
7301 struct intel_encoder *encoder;
7302 bool has_vga = false;
7303
7304 for_each_intel_encoder(dev, encoder) {
7305 switch (encoder->type) {
7306 case INTEL_OUTPUT_ANALOG:
7307 has_vga = true;
7308 break;
7309 default:
7310 break;
7311 }
7312 }
7313
7314 if (has_vga)
7315 lpt_enable_clkout_dp(dev, true, true);
7316 else
7317 lpt_disable_clkout_dp(dev);
7318 }
7319
7320 /*
7321 * Initialize reference clocks when the driver loads
7322 */
7323 void intel_init_pch_refclk(struct drm_device *dev)
7324 {
7325 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7326 ironlake_init_pch_refclk(dev);
7327 else if (HAS_PCH_LPT(dev))
7328 lpt_init_pch_refclk(dev);
7329 }
7330
7331 static int ironlake_get_refclk(struct drm_crtc *crtc)
7332 {
7333 struct drm_device *dev = crtc->dev;
7334 struct drm_i915_private *dev_priv = dev->dev_private;
7335 struct intel_encoder *encoder;
7336 int num_connectors = 0;
7337 bool is_lvds = false;
7338
7339 for_each_intel_encoder(dev, encoder) {
7340 if (encoder->new_crtc != to_intel_crtc(crtc))
7341 continue;
7342
7343 switch (encoder->type) {
7344 case INTEL_OUTPUT_LVDS:
7345 is_lvds = true;
7346 break;
7347 default:
7348 break;
7349 }
7350 num_connectors++;
7351 }
7352
7353 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7354 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7355 dev_priv->vbt.lvds_ssc_freq);
7356 return dev_priv->vbt.lvds_ssc_freq;
7357 }
7358
7359 return 120000;
7360 }
7361
7362 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7363 {
7364 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7366 int pipe = intel_crtc->pipe;
7367 uint32_t val;
7368
7369 val = 0;
7370
7371 switch (intel_crtc->config->pipe_bpp) {
7372 case 18:
7373 val |= PIPECONF_6BPC;
7374 break;
7375 case 24:
7376 val |= PIPECONF_8BPC;
7377 break;
7378 case 30:
7379 val |= PIPECONF_10BPC;
7380 break;
7381 case 36:
7382 val |= PIPECONF_12BPC;
7383 break;
7384 default:
7385 /* Case prevented by intel_choose_pipe_bpp_dither. */
7386 BUG();
7387 }
7388
7389 if (intel_crtc->config->dither)
7390 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7391
7392 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7393 val |= PIPECONF_INTERLACED_ILK;
7394 else
7395 val |= PIPECONF_PROGRESSIVE;
7396
7397 if (intel_crtc->config->limited_color_range)
7398 val |= PIPECONF_COLOR_RANGE_SELECT;
7399
7400 I915_WRITE(PIPECONF(pipe), val);
7401 POSTING_READ(PIPECONF(pipe));
7402 }
7403
7404 /*
7405 * Set up the pipe CSC unit.
7406 *
7407 * Currently only full range RGB to limited range RGB conversion
7408 * is supported, but eventually this should handle various
7409 * RGB<->YCbCr scenarios as well.
7410 */
7411 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7412 {
7413 struct drm_device *dev = crtc->dev;
7414 struct drm_i915_private *dev_priv = dev->dev_private;
7415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7416 int pipe = intel_crtc->pipe;
7417 uint16_t coeff = 0x7800; /* 1.0 */
7418
7419 /*
7420 * TODO: Check what kind of values actually come out of the pipe
7421 * with these coeff/postoff values and adjust to get the best
7422 * accuracy. Perhaps we even need to take the bpc value into
7423 * consideration.
7424 */
7425
7426 if (intel_crtc->config->limited_color_range)
7427 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7428
7429 /*
7430 * GY/GU and RY/RU should be the other way around according
7431 * to BSpec, but reality doesn't agree. Just set them up in
7432 * a way that results in the correct picture.
7433 */
7434 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7435 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7436
7437 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7438 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7439
7440 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7441 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7442
7443 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7444 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7445 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7446
7447 if (INTEL_INFO(dev)->gen > 6) {
7448 uint16_t postoff = 0;
7449
7450 if (intel_crtc->config->limited_color_range)
7451 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7452
7453 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7454 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7455 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7456
7457 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7458 } else {
7459 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7460
7461 if (intel_crtc->config->limited_color_range)
7462 mode |= CSC_BLACK_SCREEN_OFFSET;
7463
7464 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7465 }
7466 }
7467
7468 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7469 {
7470 struct drm_device *dev = crtc->dev;
7471 struct drm_i915_private *dev_priv = dev->dev_private;
7472 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7473 enum pipe pipe = intel_crtc->pipe;
7474 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7475 uint32_t val;
7476
7477 val = 0;
7478
7479 if (IS_HASWELL(dev) && intel_crtc->config->dither)
7480 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7481
7482 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7483 val |= PIPECONF_INTERLACED_ILK;
7484 else
7485 val |= PIPECONF_PROGRESSIVE;
7486
7487 I915_WRITE(PIPECONF(cpu_transcoder), val);
7488 POSTING_READ(PIPECONF(cpu_transcoder));
7489
7490 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7491 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7492
7493 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7494 val = 0;
7495
7496 switch (intel_crtc->config->pipe_bpp) {
7497 case 18:
7498 val |= PIPEMISC_DITHER_6_BPC;
7499 break;
7500 case 24:
7501 val |= PIPEMISC_DITHER_8_BPC;
7502 break;
7503 case 30:
7504 val |= PIPEMISC_DITHER_10_BPC;
7505 break;
7506 case 36:
7507 val |= PIPEMISC_DITHER_12_BPC;
7508 break;
7509 default:
7510 /* Case prevented by pipe_config_set_bpp. */
7511 BUG();
7512 }
7513
7514 if (intel_crtc->config->dither)
7515 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7516
7517 I915_WRITE(PIPEMISC(pipe), val);
7518 }
7519 }
7520
7521 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7522 struct intel_crtc_state *crtc_state,
7523 intel_clock_t *clock,
7524 bool *has_reduced_clock,
7525 intel_clock_t *reduced_clock)
7526 {
7527 struct drm_device *dev = crtc->dev;
7528 struct drm_i915_private *dev_priv = dev->dev_private;
7529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7530 int refclk;
7531 const intel_limit_t *limit;
7532 bool ret, is_lvds = false;
7533
7534 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7535
7536 refclk = ironlake_get_refclk(crtc);
7537
7538 /*
7539 * Returns a set of divisors for the desired target clock with the given
7540 * refclk, or FALSE. The returned values represent the clock equation:
7541 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7542 */
7543 limit = intel_limit(intel_crtc, refclk);
7544 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7545 crtc_state->port_clock,
7546 refclk, NULL, clock);
7547 if (!ret)
7548 return false;
7549
7550 if (is_lvds && dev_priv->lvds_downclock_avail) {
7551 /*
7552 * Ensure we match the reduced clock's P to the target clock.
7553 * If the clocks don't match, we can't switch the display clock
7554 * by using the FP0/FP1. In such case we will disable the LVDS
7555 * downclock feature.
7556 */
7557 *has_reduced_clock =
7558 dev_priv->display.find_dpll(limit, intel_crtc,
7559 dev_priv->lvds_downclock,
7560 refclk, clock,
7561 reduced_clock);
7562 }
7563
7564 return true;
7565 }
7566
7567 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7568 {
7569 /*
7570 * Account for spread spectrum to avoid
7571 * oversubscribing the link. Max center spread
7572 * is 2.5%; use 5% for safety's sake.
7573 */
7574 u32 bps = target_clock * bpp * 21 / 20;
7575 return DIV_ROUND_UP(bps, link_bw * 8);
7576 }
7577
7578 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7579 {
7580 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7581 }
7582
7583 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7584 struct intel_crtc_state *crtc_state,
7585 u32 *fp,
7586 intel_clock_t *reduced_clock, u32 *fp2)
7587 {
7588 struct drm_crtc *crtc = &intel_crtc->base;
7589 struct drm_device *dev = crtc->dev;
7590 struct drm_i915_private *dev_priv = dev->dev_private;
7591 struct intel_encoder *intel_encoder;
7592 uint32_t dpll;
7593 int factor, num_connectors = 0;
7594 bool is_lvds = false, is_sdvo = false;
7595
7596 for_each_intel_encoder(dev, intel_encoder) {
7597 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7598 continue;
7599
7600 switch (intel_encoder->type) {
7601 case INTEL_OUTPUT_LVDS:
7602 is_lvds = true;
7603 break;
7604 case INTEL_OUTPUT_SDVO:
7605 case INTEL_OUTPUT_HDMI:
7606 is_sdvo = true;
7607 break;
7608 default:
7609 break;
7610 }
7611
7612 num_connectors++;
7613 }
7614
7615 /* Enable autotuning of the PLL clock (if permissible) */
7616 factor = 21;
7617 if (is_lvds) {
7618 if ((intel_panel_use_ssc(dev_priv) &&
7619 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7620 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7621 factor = 25;
7622 } else if (crtc_state->sdvo_tv_clock)
7623 factor = 20;
7624
7625 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7626 *fp |= FP_CB_TUNE;
7627
7628 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7629 *fp2 |= FP_CB_TUNE;
7630
7631 dpll = 0;
7632
7633 if (is_lvds)
7634 dpll |= DPLLB_MODE_LVDS;
7635 else
7636 dpll |= DPLLB_MODE_DAC_SERIAL;
7637
7638 dpll |= (crtc_state->pixel_multiplier - 1)
7639 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7640
7641 if (is_sdvo)
7642 dpll |= DPLL_SDVO_HIGH_SPEED;
7643 if (crtc_state->has_dp_encoder)
7644 dpll |= DPLL_SDVO_HIGH_SPEED;
7645
7646 /* compute bitmask from p1 value */
7647 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7648 /* also FPA1 */
7649 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7650
7651 switch (crtc_state->dpll.p2) {
7652 case 5:
7653 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7654 break;
7655 case 7:
7656 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7657 break;
7658 case 10:
7659 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7660 break;
7661 case 14:
7662 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7663 break;
7664 }
7665
7666 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7667 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7668 else
7669 dpll |= PLL_REF_INPUT_DREFCLK;
7670
7671 return dpll | DPLL_VCO_ENABLE;
7672 }
7673
7674 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7675 struct intel_crtc_state *crtc_state)
7676 {
7677 struct drm_device *dev = crtc->base.dev;
7678 intel_clock_t clock, reduced_clock;
7679 u32 dpll = 0, fp = 0, fp2 = 0;
7680 bool ok, has_reduced_clock = false;
7681 bool is_lvds = false;
7682 struct intel_shared_dpll *pll;
7683
7684 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7685
7686 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7687 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7688
7689 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
7690 &has_reduced_clock, &reduced_clock);
7691 if (!ok && !crtc_state->clock_set) {
7692 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7693 return -EINVAL;
7694 }
7695 /* Compat-code for transition, will disappear. */
7696 if (!crtc_state->clock_set) {
7697 crtc_state->dpll.n = clock.n;
7698 crtc_state->dpll.m1 = clock.m1;
7699 crtc_state->dpll.m2 = clock.m2;
7700 crtc_state->dpll.p1 = clock.p1;
7701 crtc_state->dpll.p2 = clock.p2;
7702 }
7703
7704 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7705 if (crtc_state->has_pch_encoder) {
7706 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7707 if (has_reduced_clock)
7708 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7709
7710 dpll = ironlake_compute_dpll(crtc, crtc_state,
7711 &fp, &reduced_clock,
7712 has_reduced_clock ? &fp2 : NULL);
7713
7714 crtc_state->dpll_hw_state.dpll = dpll;
7715 crtc_state->dpll_hw_state.fp0 = fp;
7716 if (has_reduced_clock)
7717 crtc_state->dpll_hw_state.fp1 = fp2;
7718 else
7719 crtc_state->dpll_hw_state.fp1 = fp;
7720
7721 pll = intel_get_shared_dpll(crtc, crtc_state);
7722 if (pll == NULL) {
7723 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7724 pipe_name(crtc->pipe));
7725 return -EINVAL;
7726 }
7727 }
7728
7729 if (is_lvds && has_reduced_clock && i915.powersave)
7730 crtc->lowfreq_avail = true;
7731 else
7732 crtc->lowfreq_avail = false;
7733
7734 return 0;
7735 }
7736
7737 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7738 struct intel_link_m_n *m_n)
7739 {
7740 struct drm_device *dev = crtc->base.dev;
7741 struct drm_i915_private *dev_priv = dev->dev_private;
7742 enum pipe pipe = crtc->pipe;
7743
7744 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7745 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7746 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7747 & ~TU_SIZE_MASK;
7748 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7749 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7750 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7751 }
7752
7753 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7754 enum transcoder transcoder,
7755 struct intel_link_m_n *m_n,
7756 struct intel_link_m_n *m2_n2)
7757 {
7758 struct drm_device *dev = crtc->base.dev;
7759 struct drm_i915_private *dev_priv = dev->dev_private;
7760 enum pipe pipe = crtc->pipe;
7761
7762 if (INTEL_INFO(dev)->gen >= 5) {
7763 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7764 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7765 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7766 & ~TU_SIZE_MASK;
7767 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7768 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7769 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7770 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7771 * gen < 8) and if DRRS is supported (to make sure the
7772 * registers are not unnecessarily read).
7773 */
7774 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7775 crtc->config->has_drrs) {
7776 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7777 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7778 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7779 & ~TU_SIZE_MASK;
7780 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7781 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7782 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7783 }
7784 } else {
7785 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7786 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7787 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7788 & ~TU_SIZE_MASK;
7789 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7790 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7791 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7792 }
7793 }
7794
7795 void intel_dp_get_m_n(struct intel_crtc *crtc,
7796 struct intel_crtc_state *pipe_config)
7797 {
7798 if (pipe_config->has_pch_encoder)
7799 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7800 else
7801 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7802 &pipe_config->dp_m_n,
7803 &pipe_config->dp_m2_n2);
7804 }
7805
7806 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7807 struct intel_crtc_state *pipe_config)
7808 {
7809 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7810 &pipe_config->fdi_m_n, NULL);
7811 }
7812
7813 static void skylake_get_pfit_config(struct intel_crtc *crtc,
7814 struct intel_crtc_state *pipe_config)
7815 {
7816 struct drm_device *dev = crtc->base.dev;
7817 struct drm_i915_private *dev_priv = dev->dev_private;
7818 uint32_t tmp;
7819
7820 tmp = I915_READ(PS_CTL(crtc->pipe));
7821
7822 if (tmp & PS_ENABLE) {
7823 pipe_config->pch_pfit.enabled = true;
7824 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7825 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7826 }
7827 }
7828
7829 static void
7830 skylake_get_initial_plane_config(struct intel_crtc *crtc,
7831 struct intel_initial_plane_config *plane_config)
7832 {
7833 struct drm_device *dev = crtc->base.dev;
7834 struct drm_i915_private *dev_priv = dev->dev_private;
7835 u32 val, base, offset, stride_mult, tiling;
7836 int pipe = crtc->pipe;
7837 int fourcc, pixel_format;
7838 int aligned_height;
7839 struct drm_framebuffer *fb;
7840 struct intel_framebuffer *intel_fb;
7841
7842 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7843 if (!intel_fb) {
7844 DRM_DEBUG_KMS("failed to alloc fb\n");
7845 return;
7846 }
7847
7848 fb = &intel_fb->base;
7849
7850 val = I915_READ(PLANE_CTL(pipe, 0));
7851 if (!(val & PLANE_CTL_ENABLE))
7852 goto error;
7853
7854 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7855 fourcc = skl_format_to_fourcc(pixel_format,
7856 val & PLANE_CTL_ORDER_RGBX,
7857 val & PLANE_CTL_ALPHA_MASK);
7858 fb->pixel_format = fourcc;
7859 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7860
7861 tiling = val & PLANE_CTL_TILED_MASK;
7862 switch (tiling) {
7863 case PLANE_CTL_TILED_LINEAR:
7864 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7865 break;
7866 case PLANE_CTL_TILED_X:
7867 plane_config->tiling = I915_TILING_X;
7868 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7869 break;
7870 case PLANE_CTL_TILED_Y:
7871 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7872 break;
7873 case PLANE_CTL_TILED_YF:
7874 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7875 break;
7876 default:
7877 MISSING_CASE(tiling);
7878 goto error;
7879 }
7880
7881 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7882 plane_config->base = base;
7883
7884 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7885
7886 val = I915_READ(PLANE_SIZE(pipe, 0));
7887 fb->height = ((val >> 16) & 0xfff) + 1;
7888 fb->width = ((val >> 0) & 0x1fff) + 1;
7889
7890 val = I915_READ(PLANE_STRIDE(pipe, 0));
7891 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7892 fb->pixel_format);
7893 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7894
7895 aligned_height = intel_fb_align_height(dev, fb->height,
7896 fb->pixel_format,
7897 fb->modifier[0]);
7898
7899 plane_config->size = fb->pitches[0] * aligned_height;
7900
7901 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7902 pipe_name(pipe), fb->width, fb->height,
7903 fb->bits_per_pixel, base, fb->pitches[0],
7904 plane_config->size);
7905
7906 plane_config->fb = intel_fb;
7907 return;
7908
7909 error:
7910 kfree(fb);
7911 }
7912
7913 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7914 struct intel_crtc_state *pipe_config)
7915 {
7916 struct drm_device *dev = crtc->base.dev;
7917 struct drm_i915_private *dev_priv = dev->dev_private;
7918 uint32_t tmp;
7919
7920 tmp = I915_READ(PF_CTL(crtc->pipe));
7921
7922 if (tmp & PF_ENABLE) {
7923 pipe_config->pch_pfit.enabled = true;
7924 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7925 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7926
7927 /* We currently do not free assignements of panel fitters on
7928 * ivb/hsw (since we don't use the higher upscaling modes which
7929 * differentiates them) so just WARN about this case for now. */
7930 if (IS_GEN7(dev)) {
7931 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7932 PF_PIPE_SEL_IVB(crtc->pipe));
7933 }
7934 }
7935 }
7936
7937 static void
7938 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7939 struct intel_initial_plane_config *plane_config)
7940 {
7941 struct drm_device *dev = crtc->base.dev;
7942 struct drm_i915_private *dev_priv = dev->dev_private;
7943 u32 val, base, offset;
7944 int pipe = crtc->pipe;
7945 int fourcc, pixel_format;
7946 int aligned_height;
7947 struct drm_framebuffer *fb;
7948 struct intel_framebuffer *intel_fb;
7949
7950 val = I915_READ(DSPCNTR(pipe));
7951 if (!(val & DISPLAY_PLANE_ENABLE))
7952 return;
7953
7954 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7955 if (!intel_fb) {
7956 DRM_DEBUG_KMS("failed to alloc fb\n");
7957 return;
7958 }
7959
7960 fb = &intel_fb->base;
7961
7962 if (INTEL_INFO(dev)->gen >= 4) {
7963 if (val & DISPPLANE_TILED) {
7964 plane_config->tiling = I915_TILING_X;
7965 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7966 }
7967 }
7968
7969 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7970 fourcc = i9xx_format_to_fourcc(pixel_format);
7971 fb->pixel_format = fourcc;
7972 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7973
7974 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
7975 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7976 offset = I915_READ(DSPOFFSET(pipe));
7977 } else {
7978 if (plane_config->tiling)
7979 offset = I915_READ(DSPTILEOFF(pipe));
7980 else
7981 offset = I915_READ(DSPLINOFF(pipe));
7982 }
7983 plane_config->base = base;
7984
7985 val = I915_READ(PIPESRC(pipe));
7986 fb->width = ((val >> 16) & 0xfff) + 1;
7987 fb->height = ((val >> 0) & 0xfff) + 1;
7988
7989 val = I915_READ(DSPSTRIDE(pipe));
7990 fb->pitches[0] = val & 0xffffffc0;
7991
7992 aligned_height = intel_fb_align_height(dev, fb->height,
7993 fb->pixel_format,
7994 fb->modifier[0]);
7995
7996 plane_config->size = fb->pitches[0] * aligned_height;
7997
7998 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7999 pipe_name(pipe), fb->width, fb->height,
8000 fb->bits_per_pixel, base, fb->pitches[0],
8001 plane_config->size);
8002
8003 plane_config->fb = intel_fb;
8004 }
8005
8006 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8007 struct intel_crtc_state *pipe_config)
8008 {
8009 struct drm_device *dev = crtc->base.dev;
8010 struct drm_i915_private *dev_priv = dev->dev_private;
8011 uint32_t tmp;
8012
8013 if (!intel_display_power_is_enabled(dev_priv,
8014 POWER_DOMAIN_PIPE(crtc->pipe)))
8015 return false;
8016
8017 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8018 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8019
8020 tmp = I915_READ(PIPECONF(crtc->pipe));
8021 if (!(tmp & PIPECONF_ENABLE))
8022 return false;
8023
8024 switch (tmp & PIPECONF_BPC_MASK) {
8025 case PIPECONF_6BPC:
8026 pipe_config->pipe_bpp = 18;
8027 break;
8028 case PIPECONF_8BPC:
8029 pipe_config->pipe_bpp = 24;
8030 break;
8031 case PIPECONF_10BPC:
8032 pipe_config->pipe_bpp = 30;
8033 break;
8034 case PIPECONF_12BPC:
8035 pipe_config->pipe_bpp = 36;
8036 break;
8037 default:
8038 break;
8039 }
8040
8041 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8042 pipe_config->limited_color_range = true;
8043
8044 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8045 struct intel_shared_dpll *pll;
8046
8047 pipe_config->has_pch_encoder = true;
8048
8049 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8050 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8051 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8052
8053 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8054
8055 if (HAS_PCH_IBX(dev_priv->dev)) {
8056 pipe_config->shared_dpll =
8057 (enum intel_dpll_id) crtc->pipe;
8058 } else {
8059 tmp = I915_READ(PCH_DPLL_SEL);
8060 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8061 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8062 else
8063 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8064 }
8065
8066 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8067
8068 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8069 &pipe_config->dpll_hw_state));
8070
8071 tmp = pipe_config->dpll_hw_state.dpll;
8072 pipe_config->pixel_multiplier =
8073 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8074 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8075
8076 ironlake_pch_clock_get(crtc, pipe_config);
8077 } else {
8078 pipe_config->pixel_multiplier = 1;
8079 }
8080
8081 intel_get_pipe_timings(crtc, pipe_config);
8082
8083 ironlake_get_pfit_config(crtc, pipe_config);
8084
8085 return true;
8086 }
8087
8088 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8089 {
8090 struct drm_device *dev = dev_priv->dev;
8091 struct intel_crtc *crtc;
8092
8093 for_each_intel_crtc(dev, crtc)
8094 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8095 pipe_name(crtc->pipe));
8096
8097 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8098 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8099 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8100 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8101 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8102 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8103 "CPU PWM1 enabled\n");
8104 if (IS_HASWELL(dev))
8105 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8106 "CPU PWM2 enabled\n");
8107 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8108 "PCH PWM1 enabled\n");
8109 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8110 "Utility pin enabled\n");
8111 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8112
8113 /*
8114 * In theory we can still leave IRQs enabled, as long as only the HPD
8115 * interrupts remain enabled. We used to check for that, but since it's
8116 * gen-specific and since we only disable LCPLL after we fully disable
8117 * the interrupts, the check below should be enough.
8118 */
8119 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8120 }
8121
8122 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8123 {
8124 struct drm_device *dev = dev_priv->dev;
8125
8126 if (IS_HASWELL(dev))
8127 return I915_READ(D_COMP_HSW);
8128 else
8129 return I915_READ(D_COMP_BDW);
8130 }
8131
8132 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8133 {
8134 struct drm_device *dev = dev_priv->dev;
8135
8136 if (IS_HASWELL(dev)) {
8137 mutex_lock(&dev_priv->rps.hw_lock);
8138 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8139 val))
8140 DRM_ERROR("Failed to write to D_COMP\n");
8141 mutex_unlock(&dev_priv->rps.hw_lock);
8142 } else {
8143 I915_WRITE(D_COMP_BDW, val);
8144 POSTING_READ(D_COMP_BDW);
8145 }
8146 }
8147
8148 /*
8149 * This function implements pieces of two sequences from BSpec:
8150 * - Sequence for display software to disable LCPLL
8151 * - Sequence for display software to allow package C8+
8152 * The steps implemented here are just the steps that actually touch the LCPLL
8153 * register. Callers should take care of disabling all the display engine
8154 * functions, doing the mode unset, fixing interrupts, etc.
8155 */
8156 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8157 bool switch_to_fclk, bool allow_power_down)
8158 {
8159 uint32_t val;
8160
8161 assert_can_disable_lcpll(dev_priv);
8162
8163 val = I915_READ(LCPLL_CTL);
8164
8165 if (switch_to_fclk) {
8166 val |= LCPLL_CD_SOURCE_FCLK;
8167 I915_WRITE(LCPLL_CTL, val);
8168
8169 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8170 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8171 DRM_ERROR("Switching to FCLK failed\n");
8172
8173 val = I915_READ(LCPLL_CTL);
8174 }
8175
8176 val |= LCPLL_PLL_DISABLE;
8177 I915_WRITE(LCPLL_CTL, val);
8178 POSTING_READ(LCPLL_CTL);
8179
8180 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8181 DRM_ERROR("LCPLL still locked\n");
8182
8183 val = hsw_read_dcomp(dev_priv);
8184 val |= D_COMP_COMP_DISABLE;
8185 hsw_write_dcomp(dev_priv, val);
8186 ndelay(100);
8187
8188 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8189 1))
8190 DRM_ERROR("D_COMP RCOMP still in progress\n");
8191
8192 if (allow_power_down) {
8193 val = I915_READ(LCPLL_CTL);
8194 val |= LCPLL_POWER_DOWN_ALLOW;
8195 I915_WRITE(LCPLL_CTL, val);
8196 POSTING_READ(LCPLL_CTL);
8197 }
8198 }
8199
8200 /*
8201 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8202 * source.
8203 */
8204 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
8205 {
8206 uint32_t val;
8207
8208 val = I915_READ(LCPLL_CTL);
8209
8210 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8211 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8212 return;
8213
8214 /*
8215 * Make sure we're not on PC8 state before disabling PC8, otherwise
8216 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
8217 */
8218 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
8219
8220 if (val & LCPLL_POWER_DOWN_ALLOW) {
8221 val &= ~LCPLL_POWER_DOWN_ALLOW;
8222 I915_WRITE(LCPLL_CTL, val);
8223 POSTING_READ(LCPLL_CTL);
8224 }
8225
8226 val = hsw_read_dcomp(dev_priv);
8227 val |= D_COMP_COMP_FORCE;
8228 val &= ~D_COMP_COMP_DISABLE;
8229 hsw_write_dcomp(dev_priv, val);
8230
8231 val = I915_READ(LCPLL_CTL);
8232 val &= ~LCPLL_PLL_DISABLE;
8233 I915_WRITE(LCPLL_CTL, val);
8234
8235 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8236 DRM_ERROR("LCPLL not locked yet\n");
8237
8238 if (val & LCPLL_CD_SOURCE_FCLK) {
8239 val = I915_READ(LCPLL_CTL);
8240 val &= ~LCPLL_CD_SOURCE_FCLK;
8241 I915_WRITE(LCPLL_CTL, val);
8242
8243 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8244 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8245 DRM_ERROR("Switching back to LCPLL failed\n");
8246 }
8247
8248 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
8249 }
8250
8251 /*
8252 * Package states C8 and deeper are really deep PC states that can only be
8253 * reached when all the devices on the system allow it, so even if the graphics
8254 * device allows PC8+, it doesn't mean the system will actually get to these
8255 * states. Our driver only allows PC8+ when going into runtime PM.
8256 *
8257 * The requirements for PC8+ are that all the outputs are disabled, the power
8258 * well is disabled and most interrupts are disabled, and these are also
8259 * requirements for runtime PM. When these conditions are met, we manually do
8260 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8261 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8262 * hang the machine.
8263 *
8264 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8265 * the state of some registers, so when we come back from PC8+ we need to
8266 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8267 * need to take care of the registers kept by RC6. Notice that this happens even
8268 * if we don't put the device in PCI D3 state (which is what currently happens
8269 * because of the runtime PM support).
8270 *
8271 * For more, read "Display Sequences for Package C8" on the hardware
8272 * documentation.
8273 */
8274 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
8275 {
8276 struct drm_device *dev = dev_priv->dev;
8277 uint32_t val;
8278
8279 DRM_DEBUG_KMS("Enabling package C8+\n");
8280
8281 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8282 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8283 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8284 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8285 }
8286
8287 lpt_disable_clkout_dp(dev);
8288 hsw_disable_lcpll(dev_priv, true, true);
8289 }
8290
8291 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
8292 {
8293 struct drm_device *dev = dev_priv->dev;
8294 uint32_t val;
8295
8296 DRM_DEBUG_KMS("Disabling package C8+\n");
8297
8298 hsw_restore_lcpll(dev_priv);
8299 lpt_init_pch_refclk(dev);
8300
8301 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8302 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8303 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8304 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8305 }
8306
8307 intel_prepare_ddi(dev);
8308 }
8309
8310 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8311 struct intel_crtc_state *crtc_state)
8312 {
8313 if (!intel_ddi_pll_select(crtc, crtc_state))
8314 return -EINVAL;
8315
8316 crtc->lowfreq_avail = false;
8317
8318 return 0;
8319 }
8320
8321 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8322 enum port port,
8323 struct intel_crtc_state *pipe_config)
8324 {
8325 u32 temp, dpll_ctl1;
8326
8327 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8328 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8329
8330 switch (pipe_config->ddi_pll_sel) {
8331 case SKL_DPLL0:
8332 /*
8333 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8334 * of the shared DPLL framework and thus needs to be read out
8335 * separately
8336 */
8337 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8338 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8339 break;
8340 case SKL_DPLL1:
8341 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8342 break;
8343 case SKL_DPLL2:
8344 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8345 break;
8346 case SKL_DPLL3:
8347 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8348 break;
8349 }
8350 }
8351
8352 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8353 enum port port,
8354 struct intel_crtc_state *pipe_config)
8355 {
8356 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8357
8358 switch (pipe_config->ddi_pll_sel) {
8359 case PORT_CLK_SEL_WRPLL1:
8360 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8361 break;
8362 case PORT_CLK_SEL_WRPLL2:
8363 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8364 break;
8365 }
8366 }
8367
8368 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
8369 struct intel_crtc_state *pipe_config)
8370 {
8371 struct drm_device *dev = crtc->base.dev;
8372 struct drm_i915_private *dev_priv = dev->dev_private;
8373 struct intel_shared_dpll *pll;
8374 enum port port;
8375 uint32_t tmp;
8376
8377 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8378
8379 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8380
8381 if (IS_SKYLAKE(dev))
8382 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8383 else
8384 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8385
8386 if (pipe_config->shared_dpll >= 0) {
8387 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8388
8389 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8390 &pipe_config->dpll_hw_state));
8391 }
8392
8393 /*
8394 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8395 * DDI E. So just check whether this pipe is wired to DDI E and whether
8396 * the PCH transcoder is on.
8397 */
8398 if (INTEL_INFO(dev)->gen < 9 &&
8399 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8400 pipe_config->has_pch_encoder = true;
8401
8402 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8403 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8404 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8405
8406 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8407 }
8408 }
8409
8410 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8411 struct intel_crtc_state *pipe_config)
8412 {
8413 struct drm_device *dev = crtc->base.dev;
8414 struct drm_i915_private *dev_priv = dev->dev_private;
8415 enum intel_display_power_domain pfit_domain;
8416 uint32_t tmp;
8417
8418 if (!intel_display_power_is_enabled(dev_priv,
8419 POWER_DOMAIN_PIPE(crtc->pipe)))
8420 return false;
8421
8422 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8423 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8424
8425 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8426 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8427 enum pipe trans_edp_pipe;
8428 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8429 default:
8430 WARN(1, "unknown pipe linked to edp transcoder\n");
8431 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8432 case TRANS_DDI_EDP_INPUT_A_ON:
8433 trans_edp_pipe = PIPE_A;
8434 break;
8435 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8436 trans_edp_pipe = PIPE_B;
8437 break;
8438 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8439 trans_edp_pipe = PIPE_C;
8440 break;
8441 }
8442
8443 if (trans_edp_pipe == crtc->pipe)
8444 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8445 }
8446
8447 if (!intel_display_power_is_enabled(dev_priv,
8448 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8449 return false;
8450
8451 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8452 if (!(tmp & PIPECONF_ENABLE))
8453 return false;
8454
8455 haswell_get_ddi_port_state(crtc, pipe_config);
8456
8457 intel_get_pipe_timings(crtc, pipe_config);
8458
8459 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8460 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8461 if (IS_SKYLAKE(dev))
8462 skylake_get_pfit_config(crtc, pipe_config);
8463 else
8464 ironlake_get_pfit_config(crtc, pipe_config);
8465 }
8466
8467 if (IS_HASWELL(dev))
8468 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8469 (I915_READ(IPS_CTL) & IPS_ENABLE);
8470
8471 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8472 pipe_config->pixel_multiplier =
8473 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8474 } else {
8475 pipe_config->pixel_multiplier = 1;
8476 }
8477
8478 return true;
8479 }
8480
8481 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8482 {
8483 struct drm_device *dev = crtc->dev;
8484 struct drm_i915_private *dev_priv = dev->dev_private;
8485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8486 uint32_t cntl = 0, size = 0;
8487
8488 if (base) {
8489 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8490 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
8491 unsigned int stride = roundup_pow_of_two(width) * 4;
8492
8493 switch (stride) {
8494 default:
8495 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8496 width, stride);
8497 stride = 256;
8498 /* fallthrough */
8499 case 256:
8500 case 512:
8501 case 1024:
8502 case 2048:
8503 break;
8504 }
8505
8506 cntl |= CURSOR_ENABLE |
8507 CURSOR_GAMMA_ENABLE |
8508 CURSOR_FORMAT_ARGB |
8509 CURSOR_STRIDE(stride);
8510
8511 size = (height << 12) | width;
8512 }
8513
8514 if (intel_crtc->cursor_cntl != 0 &&
8515 (intel_crtc->cursor_base != base ||
8516 intel_crtc->cursor_size != size ||
8517 intel_crtc->cursor_cntl != cntl)) {
8518 /* On these chipsets we can only modify the base/size/stride
8519 * whilst the cursor is disabled.
8520 */
8521 I915_WRITE(_CURACNTR, 0);
8522 POSTING_READ(_CURACNTR);
8523 intel_crtc->cursor_cntl = 0;
8524 }
8525
8526 if (intel_crtc->cursor_base != base) {
8527 I915_WRITE(_CURABASE, base);
8528 intel_crtc->cursor_base = base;
8529 }
8530
8531 if (intel_crtc->cursor_size != size) {
8532 I915_WRITE(CURSIZE, size);
8533 intel_crtc->cursor_size = size;
8534 }
8535
8536 if (intel_crtc->cursor_cntl != cntl) {
8537 I915_WRITE(_CURACNTR, cntl);
8538 POSTING_READ(_CURACNTR);
8539 intel_crtc->cursor_cntl = cntl;
8540 }
8541 }
8542
8543 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8544 {
8545 struct drm_device *dev = crtc->dev;
8546 struct drm_i915_private *dev_priv = dev->dev_private;
8547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8548 int pipe = intel_crtc->pipe;
8549 uint32_t cntl;
8550
8551 cntl = 0;
8552 if (base) {
8553 cntl = MCURSOR_GAMMA_ENABLE;
8554 switch (intel_crtc->base.cursor->state->crtc_w) {
8555 case 64:
8556 cntl |= CURSOR_MODE_64_ARGB_AX;
8557 break;
8558 case 128:
8559 cntl |= CURSOR_MODE_128_ARGB_AX;
8560 break;
8561 case 256:
8562 cntl |= CURSOR_MODE_256_ARGB_AX;
8563 break;
8564 default:
8565 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
8566 return;
8567 }
8568 cntl |= pipe << 28; /* Connect to correct pipe */
8569
8570 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8571 cntl |= CURSOR_PIPE_CSC_ENABLE;
8572 }
8573
8574 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
8575 cntl |= CURSOR_ROTATE_180;
8576
8577 if (intel_crtc->cursor_cntl != cntl) {
8578 I915_WRITE(CURCNTR(pipe), cntl);
8579 POSTING_READ(CURCNTR(pipe));
8580 intel_crtc->cursor_cntl = cntl;
8581 }
8582
8583 /* and commit changes on next vblank */
8584 I915_WRITE(CURBASE(pipe), base);
8585 POSTING_READ(CURBASE(pipe));
8586
8587 intel_crtc->cursor_base = base;
8588 }
8589
8590 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8591 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8592 bool on)
8593 {
8594 struct drm_device *dev = crtc->dev;
8595 struct drm_i915_private *dev_priv = dev->dev_private;
8596 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8597 int pipe = intel_crtc->pipe;
8598 int x = crtc->cursor_x;
8599 int y = crtc->cursor_y;
8600 u32 base = 0, pos = 0;
8601
8602 if (on)
8603 base = intel_crtc->cursor_addr;
8604
8605 if (x >= intel_crtc->config->pipe_src_w)
8606 base = 0;
8607
8608 if (y >= intel_crtc->config->pipe_src_h)
8609 base = 0;
8610
8611 if (x < 0) {
8612 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
8613 base = 0;
8614
8615 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8616 x = -x;
8617 }
8618 pos |= x << CURSOR_X_SHIFT;
8619
8620 if (y < 0) {
8621 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
8622 base = 0;
8623
8624 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8625 y = -y;
8626 }
8627 pos |= y << CURSOR_Y_SHIFT;
8628
8629 if (base == 0 && intel_crtc->cursor_base == 0)
8630 return;
8631
8632 I915_WRITE(CURPOS(pipe), pos);
8633
8634 /* ILK+ do this automagically */
8635 if (HAS_GMCH_DISPLAY(dev) &&
8636 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
8637 base += (intel_crtc->base.cursor->state->crtc_h *
8638 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
8639 }
8640
8641 if (IS_845G(dev) || IS_I865G(dev))
8642 i845_update_cursor(crtc, base);
8643 else
8644 i9xx_update_cursor(crtc, base);
8645 }
8646
8647 static bool cursor_size_ok(struct drm_device *dev,
8648 uint32_t width, uint32_t height)
8649 {
8650 if (width == 0 || height == 0)
8651 return false;
8652
8653 /*
8654 * 845g/865g are special in that they are only limited by
8655 * the width of their cursors, the height is arbitrary up to
8656 * the precision of the register. Everything else requires
8657 * square cursors, limited to a few power-of-two sizes.
8658 */
8659 if (IS_845G(dev) || IS_I865G(dev)) {
8660 if ((width & 63) != 0)
8661 return false;
8662
8663 if (width > (IS_845G(dev) ? 64 : 512))
8664 return false;
8665
8666 if (height > 1023)
8667 return false;
8668 } else {
8669 switch (width | height) {
8670 case 256:
8671 case 128:
8672 if (IS_GEN2(dev))
8673 return false;
8674 case 64:
8675 break;
8676 default:
8677 return false;
8678 }
8679 }
8680
8681 return true;
8682 }
8683
8684 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8685 u16 *blue, uint32_t start, uint32_t size)
8686 {
8687 int end = (start + size > 256) ? 256 : start + size, i;
8688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8689
8690 for (i = start; i < end; i++) {
8691 intel_crtc->lut_r[i] = red[i] >> 8;
8692 intel_crtc->lut_g[i] = green[i] >> 8;
8693 intel_crtc->lut_b[i] = blue[i] >> 8;
8694 }
8695
8696 intel_crtc_load_lut(crtc);
8697 }
8698
8699 /* VESA 640x480x72Hz mode to set on the pipe */
8700 static struct drm_display_mode load_detect_mode = {
8701 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8702 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8703 };
8704
8705 struct drm_framebuffer *
8706 __intel_framebuffer_create(struct drm_device *dev,
8707 struct drm_mode_fb_cmd2 *mode_cmd,
8708 struct drm_i915_gem_object *obj)
8709 {
8710 struct intel_framebuffer *intel_fb;
8711 int ret;
8712
8713 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8714 if (!intel_fb) {
8715 drm_gem_object_unreference(&obj->base);
8716 return ERR_PTR(-ENOMEM);
8717 }
8718
8719 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8720 if (ret)
8721 goto err;
8722
8723 return &intel_fb->base;
8724 err:
8725 drm_gem_object_unreference(&obj->base);
8726 kfree(intel_fb);
8727
8728 return ERR_PTR(ret);
8729 }
8730
8731 static struct drm_framebuffer *
8732 intel_framebuffer_create(struct drm_device *dev,
8733 struct drm_mode_fb_cmd2 *mode_cmd,
8734 struct drm_i915_gem_object *obj)
8735 {
8736 struct drm_framebuffer *fb;
8737 int ret;
8738
8739 ret = i915_mutex_lock_interruptible(dev);
8740 if (ret)
8741 return ERR_PTR(ret);
8742 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8743 mutex_unlock(&dev->struct_mutex);
8744
8745 return fb;
8746 }
8747
8748 static u32
8749 intel_framebuffer_pitch_for_width(int width, int bpp)
8750 {
8751 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8752 return ALIGN(pitch, 64);
8753 }
8754
8755 static u32
8756 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8757 {
8758 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8759 return PAGE_ALIGN(pitch * mode->vdisplay);
8760 }
8761
8762 static struct drm_framebuffer *
8763 intel_framebuffer_create_for_mode(struct drm_device *dev,
8764 struct drm_display_mode *mode,
8765 int depth, int bpp)
8766 {
8767 struct drm_i915_gem_object *obj;
8768 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8769
8770 obj = i915_gem_alloc_object(dev,
8771 intel_framebuffer_size_for_mode(mode, bpp));
8772 if (obj == NULL)
8773 return ERR_PTR(-ENOMEM);
8774
8775 mode_cmd.width = mode->hdisplay;
8776 mode_cmd.height = mode->vdisplay;
8777 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8778 bpp);
8779 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8780
8781 return intel_framebuffer_create(dev, &mode_cmd, obj);
8782 }
8783
8784 static struct drm_framebuffer *
8785 mode_fits_in_fbdev(struct drm_device *dev,
8786 struct drm_display_mode *mode)
8787 {
8788 #ifdef CONFIG_DRM_I915_FBDEV
8789 struct drm_i915_private *dev_priv = dev->dev_private;
8790 struct drm_i915_gem_object *obj;
8791 struct drm_framebuffer *fb;
8792
8793 if (!dev_priv->fbdev)
8794 return NULL;
8795
8796 if (!dev_priv->fbdev->fb)
8797 return NULL;
8798
8799 obj = dev_priv->fbdev->fb->obj;
8800 BUG_ON(!obj);
8801
8802 fb = &dev_priv->fbdev->fb->base;
8803 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8804 fb->bits_per_pixel))
8805 return NULL;
8806
8807 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8808 return NULL;
8809
8810 return fb;
8811 #else
8812 return NULL;
8813 #endif
8814 }
8815
8816 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8817 struct drm_display_mode *mode,
8818 struct intel_load_detect_pipe *old,
8819 struct drm_modeset_acquire_ctx *ctx)
8820 {
8821 struct intel_crtc *intel_crtc;
8822 struct intel_encoder *intel_encoder =
8823 intel_attached_encoder(connector);
8824 struct drm_crtc *possible_crtc;
8825 struct drm_encoder *encoder = &intel_encoder->base;
8826 struct drm_crtc *crtc = NULL;
8827 struct drm_device *dev = encoder->dev;
8828 struct drm_framebuffer *fb;
8829 struct drm_mode_config *config = &dev->mode_config;
8830 int ret, i = -1;
8831
8832 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8833 connector->base.id, connector->name,
8834 encoder->base.id, encoder->name);
8835
8836 retry:
8837 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8838 if (ret)
8839 goto fail_unlock;
8840
8841 /*
8842 * Algorithm gets a little messy:
8843 *
8844 * - if the connector already has an assigned crtc, use it (but make
8845 * sure it's on first)
8846 *
8847 * - try to find the first unused crtc that can drive this connector,
8848 * and use that if we find one
8849 */
8850
8851 /* See if we already have a CRTC for this connector */
8852 if (encoder->crtc) {
8853 crtc = encoder->crtc;
8854
8855 ret = drm_modeset_lock(&crtc->mutex, ctx);
8856 if (ret)
8857 goto fail_unlock;
8858 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8859 if (ret)
8860 goto fail_unlock;
8861
8862 old->dpms_mode = connector->dpms;
8863 old->load_detect_temp = false;
8864
8865 /* Make sure the crtc and connector are running */
8866 if (connector->dpms != DRM_MODE_DPMS_ON)
8867 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8868
8869 return true;
8870 }
8871
8872 /* Find an unused one (if possible) */
8873 for_each_crtc(dev, possible_crtc) {
8874 i++;
8875 if (!(encoder->possible_crtcs & (1 << i)))
8876 continue;
8877 if (possible_crtc->state->enable)
8878 continue;
8879 /* This can occur when applying the pipe A quirk on resume. */
8880 if (to_intel_crtc(possible_crtc)->new_enabled)
8881 continue;
8882
8883 crtc = possible_crtc;
8884 break;
8885 }
8886
8887 /*
8888 * If we didn't find an unused CRTC, don't use any.
8889 */
8890 if (!crtc) {
8891 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8892 goto fail_unlock;
8893 }
8894
8895 ret = drm_modeset_lock(&crtc->mutex, ctx);
8896 if (ret)
8897 goto fail_unlock;
8898 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8899 if (ret)
8900 goto fail_unlock;
8901 intel_encoder->new_crtc = to_intel_crtc(crtc);
8902 to_intel_connector(connector)->new_encoder = intel_encoder;
8903
8904 intel_crtc = to_intel_crtc(crtc);
8905 intel_crtc->new_enabled = true;
8906 intel_crtc->new_config = intel_crtc->config;
8907 old->dpms_mode = connector->dpms;
8908 old->load_detect_temp = true;
8909 old->release_fb = NULL;
8910
8911 if (!mode)
8912 mode = &load_detect_mode;
8913
8914 /* We need a framebuffer large enough to accommodate all accesses
8915 * that the plane may generate whilst we perform load detection.
8916 * We can not rely on the fbcon either being present (we get called
8917 * during its initialisation to detect all boot displays, or it may
8918 * not even exist) or that it is large enough to satisfy the
8919 * requested mode.
8920 */
8921 fb = mode_fits_in_fbdev(dev, mode);
8922 if (fb == NULL) {
8923 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8924 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8925 old->release_fb = fb;
8926 } else
8927 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8928 if (IS_ERR(fb)) {
8929 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8930 goto fail;
8931 }
8932
8933 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8934 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8935 if (old->release_fb)
8936 old->release_fb->funcs->destroy(old->release_fb);
8937 goto fail;
8938 }
8939 crtc->primary->crtc = crtc;
8940
8941 /* let the connector get through one full cycle before testing */
8942 intel_wait_for_vblank(dev, intel_crtc->pipe);
8943 return true;
8944
8945 fail:
8946 intel_crtc->new_enabled = crtc->state->enable;
8947 if (intel_crtc->new_enabled)
8948 intel_crtc->new_config = intel_crtc->config;
8949 else
8950 intel_crtc->new_config = NULL;
8951 fail_unlock:
8952 if (ret == -EDEADLK) {
8953 drm_modeset_backoff(ctx);
8954 goto retry;
8955 }
8956
8957 return false;
8958 }
8959
8960 void intel_release_load_detect_pipe(struct drm_connector *connector,
8961 struct intel_load_detect_pipe *old)
8962 {
8963 struct intel_encoder *intel_encoder =
8964 intel_attached_encoder(connector);
8965 struct drm_encoder *encoder = &intel_encoder->base;
8966 struct drm_crtc *crtc = encoder->crtc;
8967 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8968
8969 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8970 connector->base.id, connector->name,
8971 encoder->base.id, encoder->name);
8972
8973 if (old->load_detect_temp) {
8974 to_intel_connector(connector)->new_encoder = NULL;
8975 intel_encoder->new_crtc = NULL;
8976 intel_crtc->new_enabled = false;
8977 intel_crtc->new_config = NULL;
8978 intel_set_mode(crtc, NULL, 0, 0, NULL);
8979
8980 if (old->release_fb) {
8981 drm_framebuffer_unregister_private(old->release_fb);
8982 drm_framebuffer_unreference(old->release_fb);
8983 }
8984
8985 return;
8986 }
8987
8988 /* Switch crtc and encoder back off if necessary */
8989 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8990 connector->funcs->dpms(connector, old->dpms_mode);
8991 }
8992
8993 static int i9xx_pll_refclk(struct drm_device *dev,
8994 const struct intel_crtc_state *pipe_config)
8995 {
8996 struct drm_i915_private *dev_priv = dev->dev_private;
8997 u32 dpll = pipe_config->dpll_hw_state.dpll;
8998
8999 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
9000 return dev_priv->vbt.lvds_ssc_freq;
9001 else if (HAS_PCH_SPLIT(dev))
9002 return 120000;
9003 else if (!IS_GEN2(dev))
9004 return 96000;
9005 else
9006 return 48000;
9007 }
9008
9009 /* Returns the clock of the currently programmed mode of the given pipe. */
9010 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
9011 struct intel_crtc_state *pipe_config)
9012 {
9013 struct drm_device *dev = crtc->base.dev;
9014 struct drm_i915_private *dev_priv = dev->dev_private;
9015 int pipe = pipe_config->cpu_transcoder;
9016 u32 dpll = pipe_config->dpll_hw_state.dpll;
9017 u32 fp;
9018 intel_clock_t clock;
9019 int refclk = i9xx_pll_refclk(dev, pipe_config);
9020
9021 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
9022 fp = pipe_config->dpll_hw_state.fp0;
9023 else
9024 fp = pipe_config->dpll_hw_state.fp1;
9025
9026 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
9027 if (IS_PINEVIEW(dev)) {
9028 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9029 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
9030 } else {
9031 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9032 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9033 }
9034
9035 if (!IS_GEN2(dev)) {
9036 if (IS_PINEVIEW(dev))
9037 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9038 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
9039 else
9040 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
9041 DPLL_FPA01_P1_POST_DIV_SHIFT);
9042
9043 switch (dpll & DPLL_MODE_MASK) {
9044 case DPLLB_MODE_DAC_SERIAL:
9045 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9046 5 : 10;
9047 break;
9048 case DPLLB_MODE_LVDS:
9049 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9050 7 : 14;
9051 break;
9052 default:
9053 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
9054 "mode\n", (int)(dpll & DPLL_MODE_MASK));
9055 return;
9056 }
9057
9058 if (IS_PINEVIEW(dev))
9059 pineview_clock(refclk, &clock);
9060 else
9061 i9xx_clock(refclk, &clock);
9062 } else {
9063 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
9064 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
9065
9066 if (is_lvds) {
9067 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9068 DPLL_FPA01_P1_POST_DIV_SHIFT);
9069
9070 if (lvds & LVDS_CLKB_POWER_UP)
9071 clock.p2 = 7;
9072 else
9073 clock.p2 = 14;
9074 } else {
9075 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9076 clock.p1 = 2;
9077 else {
9078 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9079 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9080 }
9081 if (dpll & PLL_P2_DIVIDE_BY_4)
9082 clock.p2 = 4;
9083 else
9084 clock.p2 = 2;
9085 }
9086
9087 i9xx_clock(refclk, &clock);
9088 }
9089
9090 /*
9091 * This value includes pixel_multiplier. We will use
9092 * port_clock to compute adjusted_mode.crtc_clock in the
9093 * encoder's get_config() function.
9094 */
9095 pipe_config->port_clock = clock.dot;
9096 }
9097
9098 int intel_dotclock_calculate(int link_freq,
9099 const struct intel_link_m_n *m_n)
9100 {
9101 /*
9102 * The calculation for the data clock is:
9103 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
9104 * But we want to avoid losing precison if possible, so:
9105 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
9106 *
9107 * and the link clock is simpler:
9108 * link_clock = (m * link_clock) / n
9109 */
9110
9111 if (!m_n->link_n)
9112 return 0;
9113
9114 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9115 }
9116
9117 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
9118 struct intel_crtc_state *pipe_config)
9119 {
9120 struct drm_device *dev = crtc->base.dev;
9121
9122 /* read out port_clock from the DPLL */
9123 i9xx_crtc_clock_get(crtc, pipe_config);
9124
9125 /*
9126 * This value does not include pixel_multiplier.
9127 * We will check that port_clock and adjusted_mode.crtc_clock
9128 * agree once we know their relationship in the encoder's
9129 * get_config() function.
9130 */
9131 pipe_config->base.adjusted_mode.crtc_clock =
9132 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9133 &pipe_config->fdi_m_n);
9134 }
9135
9136 /** Returns the currently programmed mode of the given pipe. */
9137 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9138 struct drm_crtc *crtc)
9139 {
9140 struct drm_i915_private *dev_priv = dev->dev_private;
9141 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9142 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
9143 struct drm_display_mode *mode;
9144 struct intel_crtc_state pipe_config;
9145 int htot = I915_READ(HTOTAL(cpu_transcoder));
9146 int hsync = I915_READ(HSYNC(cpu_transcoder));
9147 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9148 int vsync = I915_READ(VSYNC(cpu_transcoder));
9149 enum pipe pipe = intel_crtc->pipe;
9150
9151 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9152 if (!mode)
9153 return NULL;
9154
9155 /*
9156 * Construct a pipe_config sufficient for getting the clock info
9157 * back out of crtc_clock_get.
9158 *
9159 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9160 * to use a real value here instead.
9161 */
9162 pipe_config.cpu_transcoder = (enum transcoder) pipe;
9163 pipe_config.pixel_multiplier = 1;
9164 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9165 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9166 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
9167 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9168
9169 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
9170 mode->hdisplay = (htot & 0xffff) + 1;
9171 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9172 mode->hsync_start = (hsync & 0xffff) + 1;
9173 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9174 mode->vdisplay = (vtot & 0xffff) + 1;
9175 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9176 mode->vsync_start = (vsync & 0xffff) + 1;
9177 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9178
9179 drm_mode_set_name(mode);
9180
9181 return mode;
9182 }
9183
9184 static void intel_decrease_pllclock(struct drm_crtc *crtc)
9185 {
9186 struct drm_device *dev = crtc->dev;
9187 struct drm_i915_private *dev_priv = dev->dev_private;
9188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9189
9190 if (!HAS_GMCH_DISPLAY(dev))
9191 return;
9192
9193 if (!dev_priv->lvds_downclock_avail)
9194 return;
9195
9196 /*
9197 * Since this is called by a timer, we should never get here in
9198 * the manual case.
9199 */
9200 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
9201 int pipe = intel_crtc->pipe;
9202 int dpll_reg = DPLL(pipe);
9203 int dpll;
9204
9205 DRM_DEBUG_DRIVER("downclocking LVDS\n");
9206
9207 assert_panel_unlocked(dev_priv, pipe);
9208
9209 dpll = I915_READ(dpll_reg);
9210 dpll |= DISPLAY_RATE_SELECT_FPA1;
9211 I915_WRITE(dpll_reg, dpll);
9212 intel_wait_for_vblank(dev, pipe);
9213 dpll = I915_READ(dpll_reg);
9214 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
9215 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
9216 }
9217
9218 }
9219
9220 void intel_mark_busy(struct drm_device *dev)
9221 {
9222 struct drm_i915_private *dev_priv = dev->dev_private;
9223
9224 if (dev_priv->mm.busy)
9225 return;
9226
9227 intel_runtime_pm_get(dev_priv);
9228 i915_update_gfx_val(dev_priv);
9229 if (INTEL_INFO(dev)->gen >= 6)
9230 gen6_rps_busy(dev_priv);
9231 dev_priv->mm.busy = true;
9232 }
9233
9234 void intel_mark_idle(struct drm_device *dev)
9235 {
9236 struct drm_i915_private *dev_priv = dev->dev_private;
9237 struct drm_crtc *crtc;
9238
9239 if (!dev_priv->mm.busy)
9240 return;
9241
9242 dev_priv->mm.busy = false;
9243
9244 if (!i915.powersave)
9245 goto out;
9246
9247 for_each_crtc(dev, crtc) {
9248 if (!crtc->primary->fb)
9249 continue;
9250
9251 intel_decrease_pllclock(crtc);
9252 }
9253
9254 if (INTEL_INFO(dev)->gen >= 6)
9255 gen6_rps_idle(dev->dev_private);
9256
9257 out:
9258 intel_runtime_pm_put(dev_priv);
9259 }
9260
9261 static void intel_crtc_set_state(struct intel_crtc *crtc,
9262 struct intel_crtc_state *crtc_state)
9263 {
9264 kfree(crtc->config);
9265 crtc->config = crtc_state;
9266 crtc->base.state = &crtc_state->base;
9267 }
9268
9269 static void intel_crtc_destroy(struct drm_crtc *crtc)
9270 {
9271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9272 struct drm_device *dev = crtc->dev;
9273 struct intel_unpin_work *work;
9274
9275 spin_lock_irq(&dev->event_lock);
9276 work = intel_crtc->unpin_work;
9277 intel_crtc->unpin_work = NULL;
9278 spin_unlock_irq(&dev->event_lock);
9279
9280 if (work) {
9281 cancel_work_sync(&work->work);
9282 kfree(work);
9283 }
9284
9285 intel_crtc_set_state(intel_crtc, NULL);
9286 drm_crtc_cleanup(crtc);
9287
9288 kfree(intel_crtc);
9289 }
9290
9291 static void intel_unpin_work_fn(struct work_struct *__work)
9292 {
9293 struct intel_unpin_work *work =
9294 container_of(__work, struct intel_unpin_work, work);
9295 struct drm_device *dev = work->crtc->dev;
9296 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
9297
9298 mutex_lock(&dev->struct_mutex);
9299 intel_unpin_fb_obj(intel_fb_obj(work->old_fb));
9300 drm_gem_object_unreference(&work->pending_flip_obj->base);
9301
9302 intel_fbc_update(dev);
9303
9304 if (work->flip_queued_req)
9305 i915_gem_request_assign(&work->flip_queued_req, NULL);
9306 mutex_unlock(&dev->struct_mutex);
9307
9308 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9309 drm_framebuffer_unreference(work->old_fb);
9310
9311 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9312 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9313
9314 kfree(work);
9315 }
9316
9317 static void do_intel_finish_page_flip(struct drm_device *dev,
9318 struct drm_crtc *crtc)
9319 {
9320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9321 struct intel_unpin_work *work;
9322 unsigned long flags;
9323
9324 /* Ignore early vblank irqs */
9325 if (intel_crtc == NULL)
9326 return;
9327
9328 /*
9329 * This is called both by irq handlers and the reset code (to complete
9330 * lost pageflips) so needs the full irqsave spinlocks.
9331 */
9332 spin_lock_irqsave(&dev->event_lock, flags);
9333 work = intel_crtc->unpin_work;
9334
9335 /* Ensure we don't miss a work->pending update ... */
9336 smp_rmb();
9337
9338 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9339 spin_unlock_irqrestore(&dev->event_lock, flags);
9340 return;
9341 }
9342
9343 page_flip_completed(intel_crtc);
9344
9345 spin_unlock_irqrestore(&dev->event_lock, flags);
9346 }
9347
9348 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9349 {
9350 struct drm_i915_private *dev_priv = dev->dev_private;
9351 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9352
9353 do_intel_finish_page_flip(dev, crtc);
9354 }
9355
9356 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9357 {
9358 struct drm_i915_private *dev_priv = dev->dev_private;
9359 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9360
9361 do_intel_finish_page_flip(dev, crtc);
9362 }
9363
9364 /* Is 'a' after or equal to 'b'? */
9365 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9366 {
9367 return !((a - b) & 0x80000000);
9368 }
9369
9370 static bool page_flip_finished(struct intel_crtc *crtc)
9371 {
9372 struct drm_device *dev = crtc->base.dev;
9373 struct drm_i915_private *dev_priv = dev->dev_private;
9374
9375 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9376 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9377 return true;
9378
9379 /*
9380 * The relevant registers doen't exist on pre-ctg.
9381 * As the flip done interrupt doesn't trigger for mmio
9382 * flips on gmch platforms, a flip count check isn't
9383 * really needed there. But since ctg has the registers,
9384 * include it in the check anyway.
9385 */
9386 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9387 return true;
9388
9389 /*
9390 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9391 * used the same base address. In that case the mmio flip might
9392 * have completed, but the CS hasn't even executed the flip yet.
9393 *
9394 * A flip count check isn't enough as the CS might have updated
9395 * the base address just after start of vblank, but before we
9396 * managed to process the interrupt. This means we'd complete the
9397 * CS flip too soon.
9398 *
9399 * Combining both checks should get us a good enough result. It may
9400 * still happen that the CS flip has been executed, but has not
9401 * yet actually completed. But in case the base address is the same
9402 * anyway, we don't really care.
9403 */
9404 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9405 crtc->unpin_work->gtt_offset &&
9406 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9407 crtc->unpin_work->flip_count);
9408 }
9409
9410 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9411 {
9412 struct drm_i915_private *dev_priv = dev->dev_private;
9413 struct intel_crtc *intel_crtc =
9414 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9415 unsigned long flags;
9416
9417
9418 /*
9419 * This is called both by irq handlers and the reset code (to complete
9420 * lost pageflips) so needs the full irqsave spinlocks.
9421 *
9422 * NB: An MMIO update of the plane base pointer will also
9423 * generate a page-flip completion irq, i.e. every modeset
9424 * is also accompanied by a spurious intel_prepare_page_flip().
9425 */
9426 spin_lock_irqsave(&dev->event_lock, flags);
9427 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9428 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9429 spin_unlock_irqrestore(&dev->event_lock, flags);
9430 }
9431
9432 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9433 {
9434 /* Ensure that the work item is consistent when activating it ... */
9435 smp_wmb();
9436 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9437 /* and that it is marked active as soon as the irq could fire. */
9438 smp_wmb();
9439 }
9440
9441 static int intel_gen2_queue_flip(struct drm_device *dev,
9442 struct drm_crtc *crtc,
9443 struct drm_framebuffer *fb,
9444 struct drm_i915_gem_object *obj,
9445 struct intel_engine_cs *ring,
9446 uint32_t flags)
9447 {
9448 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9449 u32 flip_mask;
9450 int ret;
9451
9452 ret = intel_ring_begin(ring, 6);
9453 if (ret)
9454 return ret;
9455
9456 /* Can't queue multiple flips, so wait for the previous
9457 * one to finish before executing the next.
9458 */
9459 if (intel_crtc->plane)
9460 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9461 else
9462 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9463 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9464 intel_ring_emit(ring, MI_NOOP);
9465 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9466 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9467 intel_ring_emit(ring, fb->pitches[0]);
9468 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9469 intel_ring_emit(ring, 0); /* aux display base address, unused */
9470
9471 intel_mark_page_flip_active(intel_crtc);
9472 __intel_ring_advance(ring);
9473 return 0;
9474 }
9475
9476 static int intel_gen3_queue_flip(struct drm_device *dev,
9477 struct drm_crtc *crtc,
9478 struct drm_framebuffer *fb,
9479 struct drm_i915_gem_object *obj,
9480 struct intel_engine_cs *ring,
9481 uint32_t flags)
9482 {
9483 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9484 u32 flip_mask;
9485 int ret;
9486
9487 ret = intel_ring_begin(ring, 6);
9488 if (ret)
9489 return ret;
9490
9491 if (intel_crtc->plane)
9492 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9493 else
9494 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9495 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9496 intel_ring_emit(ring, MI_NOOP);
9497 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9498 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9499 intel_ring_emit(ring, fb->pitches[0]);
9500 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9501 intel_ring_emit(ring, MI_NOOP);
9502
9503 intel_mark_page_flip_active(intel_crtc);
9504 __intel_ring_advance(ring);
9505 return 0;
9506 }
9507
9508 static int intel_gen4_queue_flip(struct drm_device *dev,
9509 struct drm_crtc *crtc,
9510 struct drm_framebuffer *fb,
9511 struct drm_i915_gem_object *obj,
9512 struct intel_engine_cs *ring,
9513 uint32_t flags)
9514 {
9515 struct drm_i915_private *dev_priv = dev->dev_private;
9516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9517 uint32_t pf, pipesrc;
9518 int ret;
9519
9520 ret = intel_ring_begin(ring, 4);
9521 if (ret)
9522 return ret;
9523
9524 /* i965+ uses the linear or tiled offsets from the
9525 * Display Registers (which do not change across a page-flip)
9526 * so we need only reprogram the base address.
9527 */
9528 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9529 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9530 intel_ring_emit(ring, fb->pitches[0]);
9531 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9532 obj->tiling_mode);
9533
9534 /* XXX Enabling the panel-fitter across page-flip is so far
9535 * untested on non-native modes, so ignore it for now.
9536 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9537 */
9538 pf = 0;
9539 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9540 intel_ring_emit(ring, pf | pipesrc);
9541
9542 intel_mark_page_flip_active(intel_crtc);
9543 __intel_ring_advance(ring);
9544 return 0;
9545 }
9546
9547 static int intel_gen6_queue_flip(struct drm_device *dev,
9548 struct drm_crtc *crtc,
9549 struct drm_framebuffer *fb,
9550 struct drm_i915_gem_object *obj,
9551 struct intel_engine_cs *ring,
9552 uint32_t flags)
9553 {
9554 struct drm_i915_private *dev_priv = dev->dev_private;
9555 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9556 uint32_t pf, pipesrc;
9557 int ret;
9558
9559 ret = intel_ring_begin(ring, 4);
9560 if (ret)
9561 return ret;
9562
9563 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9564 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9565 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9566 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9567
9568 /* Contrary to the suggestions in the documentation,
9569 * "Enable Panel Fitter" does not seem to be required when page
9570 * flipping with a non-native mode, and worse causes a normal
9571 * modeset to fail.
9572 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9573 */
9574 pf = 0;
9575 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9576 intel_ring_emit(ring, pf | pipesrc);
9577
9578 intel_mark_page_flip_active(intel_crtc);
9579 __intel_ring_advance(ring);
9580 return 0;
9581 }
9582
9583 static int intel_gen7_queue_flip(struct drm_device *dev,
9584 struct drm_crtc *crtc,
9585 struct drm_framebuffer *fb,
9586 struct drm_i915_gem_object *obj,
9587 struct intel_engine_cs *ring,
9588 uint32_t flags)
9589 {
9590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9591 uint32_t plane_bit = 0;
9592 int len, ret;
9593
9594 switch (intel_crtc->plane) {
9595 case PLANE_A:
9596 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9597 break;
9598 case PLANE_B:
9599 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9600 break;
9601 case PLANE_C:
9602 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9603 break;
9604 default:
9605 WARN_ONCE(1, "unknown plane in flip command\n");
9606 return -ENODEV;
9607 }
9608
9609 len = 4;
9610 if (ring->id == RCS) {
9611 len += 6;
9612 /*
9613 * On Gen 8, SRM is now taking an extra dword to accommodate
9614 * 48bits addresses, and we need a NOOP for the batch size to
9615 * stay even.
9616 */
9617 if (IS_GEN8(dev))
9618 len += 2;
9619 }
9620
9621 /*
9622 * BSpec MI_DISPLAY_FLIP for IVB:
9623 * "The full packet must be contained within the same cache line."
9624 *
9625 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9626 * cacheline, if we ever start emitting more commands before
9627 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9628 * then do the cacheline alignment, and finally emit the
9629 * MI_DISPLAY_FLIP.
9630 */
9631 ret = intel_ring_cacheline_align(ring);
9632 if (ret)
9633 return ret;
9634
9635 ret = intel_ring_begin(ring, len);
9636 if (ret)
9637 return ret;
9638
9639 /* Unmask the flip-done completion message. Note that the bspec says that
9640 * we should do this for both the BCS and RCS, and that we must not unmask
9641 * more than one flip event at any time (or ensure that one flip message
9642 * can be sent by waiting for flip-done prior to queueing new flips).
9643 * Experimentation says that BCS works despite DERRMR masking all
9644 * flip-done completion events and that unmasking all planes at once
9645 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9646 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9647 */
9648 if (ring->id == RCS) {
9649 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9650 intel_ring_emit(ring, DERRMR);
9651 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9652 DERRMR_PIPEB_PRI_FLIP_DONE |
9653 DERRMR_PIPEC_PRI_FLIP_DONE));
9654 if (IS_GEN8(dev))
9655 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9656 MI_SRM_LRM_GLOBAL_GTT);
9657 else
9658 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9659 MI_SRM_LRM_GLOBAL_GTT);
9660 intel_ring_emit(ring, DERRMR);
9661 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9662 if (IS_GEN8(dev)) {
9663 intel_ring_emit(ring, 0);
9664 intel_ring_emit(ring, MI_NOOP);
9665 }
9666 }
9667
9668 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9669 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9670 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9671 intel_ring_emit(ring, (MI_NOOP));
9672
9673 intel_mark_page_flip_active(intel_crtc);
9674 __intel_ring_advance(ring);
9675 return 0;
9676 }
9677
9678 static bool use_mmio_flip(struct intel_engine_cs *ring,
9679 struct drm_i915_gem_object *obj)
9680 {
9681 /*
9682 * This is not being used for older platforms, because
9683 * non-availability of flip done interrupt forces us to use
9684 * CS flips. Older platforms derive flip done using some clever
9685 * tricks involving the flip_pending status bits and vblank irqs.
9686 * So using MMIO flips there would disrupt this mechanism.
9687 */
9688
9689 if (ring == NULL)
9690 return true;
9691
9692 if (INTEL_INFO(ring->dev)->gen < 5)
9693 return false;
9694
9695 if (i915.use_mmio_flip < 0)
9696 return false;
9697 else if (i915.use_mmio_flip > 0)
9698 return true;
9699 else if (i915.enable_execlists)
9700 return true;
9701 else
9702 return ring != i915_gem_request_get_ring(obj->last_read_req);
9703 }
9704
9705 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9706 {
9707 struct drm_device *dev = intel_crtc->base.dev;
9708 struct drm_i915_private *dev_priv = dev->dev_private;
9709 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9710 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9711 struct drm_i915_gem_object *obj = intel_fb->obj;
9712 const enum pipe pipe = intel_crtc->pipe;
9713 u32 ctl, stride;
9714
9715 ctl = I915_READ(PLANE_CTL(pipe, 0));
9716 ctl &= ~PLANE_CTL_TILED_MASK;
9717 if (obj->tiling_mode == I915_TILING_X)
9718 ctl |= PLANE_CTL_TILED_X;
9719
9720 /*
9721 * The stride is either expressed as a multiple of 64 bytes chunks for
9722 * linear buffers or in number of tiles for tiled buffers.
9723 */
9724 stride = fb->pitches[0] >> 6;
9725 if (obj->tiling_mode == I915_TILING_X)
9726 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9727
9728 /*
9729 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9730 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9731 */
9732 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9733 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9734
9735 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9736 POSTING_READ(PLANE_SURF(pipe, 0));
9737 }
9738
9739 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
9740 {
9741 struct drm_device *dev = intel_crtc->base.dev;
9742 struct drm_i915_private *dev_priv = dev->dev_private;
9743 struct intel_framebuffer *intel_fb =
9744 to_intel_framebuffer(intel_crtc->base.primary->fb);
9745 struct drm_i915_gem_object *obj = intel_fb->obj;
9746 u32 dspcntr;
9747 u32 reg;
9748
9749 reg = DSPCNTR(intel_crtc->plane);
9750 dspcntr = I915_READ(reg);
9751
9752 if (obj->tiling_mode != I915_TILING_NONE)
9753 dspcntr |= DISPPLANE_TILED;
9754 else
9755 dspcntr &= ~DISPPLANE_TILED;
9756
9757 I915_WRITE(reg, dspcntr);
9758
9759 I915_WRITE(DSPSURF(intel_crtc->plane),
9760 intel_crtc->unpin_work->gtt_offset);
9761 POSTING_READ(DSPSURF(intel_crtc->plane));
9762
9763 }
9764
9765 /*
9766 * XXX: This is the temporary way to update the plane registers until we get
9767 * around to using the usual plane update functions for MMIO flips
9768 */
9769 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9770 {
9771 struct drm_device *dev = intel_crtc->base.dev;
9772 bool atomic_update;
9773 u32 start_vbl_count;
9774
9775 intel_mark_page_flip_active(intel_crtc);
9776
9777 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9778
9779 if (INTEL_INFO(dev)->gen >= 9)
9780 skl_do_mmio_flip(intel_crtc);
9781 else
9782 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9783 ilk_do_mmio_flip(intel_crtc);
9784
9785 if (atomic_update)
9786 intel_pipe_update_end(intel_crtc, start_vbl_count);
9787 }
9788
9789 static void intel_mmio_flip_work_func(struct work_struct *work)
9790 {
9791 struct intel_crtc *crtc =
9792 container_of(work, struct intel_crtc, mmio_flip.work);
9793 struct intel_mmio_flip *mmio_flip;
9794
9795 mmio_flip = &crtc->mmio_flip;
9796 if (mmio_flip->req)
9797 WARN_ON(__i915_wait_request(mmio_flip->req,
9798 crtc->reset_counter,
9799 false, NULL, NULL) != 0);
9800
9801 intel_do_mmio_flip(crtc);
9802 if (mmio_flip->req) {
9803 mutex_lock(&crtc->base.dev->struct_mutex);
9804 i915_gem_request_assign(&mmio_flip->req, NULL);
9805 mutex_unlock(&crtc->base.dev->struct_mutex);
9806 }
9807 }
9808
9809 static int intel_queue_mmio_flip(struct drm_device *dev,
9810 struct drm_crtc *crtc,
9811 struct drm_framebuffer *fb,
9812 struct drm_i915_gem_object *obj,
9813 struct intel_engine_cs *ring,
9814 uint32_t flags)
9815 {
9816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9817
9818 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9819 obj->last_write_req);
9820
9821 schedule_work(&intel_crtc->mmio_flip.work);
9822
9823 return 0;
9824 }
9825
9826 static int intel_default_queue_flip(struct drm_device *dev,
9827 struct drm_crtc *crtc,
9828 struct drm_framebuffer *fb,
9829 struct drm_i915_gem_object *obj,
9830 struct intel_engine_cs *ring,
9831 uint32_t flags)
9832 {
9833 return -ENODEV;
9834 }
9835
9836 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9837 struct drm_crtc *crtc)
9838 {
9839 struct drm_i915_private *dev_priv = dev->dev_private;
9840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9841 struct intel_unpin_work *work = intel_crtc->unpin_work;
9842 u32 addr;
9843
9844 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9845 return true;
9846
9847 if (!work->enable_stall_check)
9848 return false;
9849
9850 if (work->flip_ready_vblank == 0) {
9851 if (work->flip_queued_req &&
9852 !i915_gem_request_completed(work->flip_queued_req, true))
9853 return false;
9854
9855 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
9856 }
9857
9858 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
9859 return false;
9860
9861 /* Potential stall - if we see that the flip has happened,
9862 * assume a missed interrupt. */
9863 if (INTEL_INFO(dev)->gen >= 4)
9864 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9865 else
9866 addr = I915_READ(DSPADDR(intel_crtc->plane));
9867
9868 /* There is a potential issue here with a false positive after a flip
9869 * to the same address. We could address this by checking for a
9870 * non-incrementing frame counter.
9871 */
9872 return addr == work->gtt_offset;
9873 }
9874
9875 void intel_check_page_flip(struct drm_device *dev, int pipe)
9876 {
9877 struct drm_i915_private *dev_priv = dev->dev_private;
9878 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9880
9881 WARN_ON(!in_interrupt());
9882
9883 if (crtc == NULL)
9884 return;
9885
9886 spin_lock(&dev->event_lock);
9887 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9888 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9889 intel_crtc->unpin_work->flip_queued_vblank,
9890 drm_vblank_count(dev, pipe));
9891 page_flip_completed(intel_crtc);
9892 }
9893 spin_unlock(&dev->event_lock);
9894 }
9895
9896 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9897 struct drm_framebuffer *fb,
9898 struct drm_pending_vblank_event *event,
9899 uint32_t page_flip_flags)
9900 {
9901 struct drm_device *dev = crtc->dev;
9902 struct drm_i915_private *dev_priv = dev->dev_private;
9903 struct drm_framebuffer *old_fb = crtc->primary->fb;
9904 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9906 struct drm_plane *primary = crtc->primary;
9907 enum pipe pipe = intel_crtc->pipe;
9908 struct intel_unpin_work *work;
9909 struct intel_engine_cs *ring;
9910 int ret;
9911
9912 /*
9913 * drm_mode_page_flip_ioctl() should already catch this, but double
9914 * check to be safe. In the future we may enable pageflipping from
9915 * a disabled primary plane.
9916 */
9917 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9918 return -EBUSY;
9919
9920 /* Can't change pixel format via MI display flips. */
9921 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9922 return -EINVAL;
9923
9924 /*
9925 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9926 * Note that pitch changes could also affect these register.
9927 */
9928 if (INTEL_INFO(dev)->gen > 3 &&
9929 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9930 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9931 return -EINVAL;
9932
9933 if (i915_terminally_wedged(&dev_priv->gpu_error))
9934 goto out_hang;
9935
9936 work = kzalloc(sizeof(*work), GFP_KERNEL);
9937 if (work == NULL)
9938 return -ENOMEM;
9939
9940 work->event = event;
9941 work->crtc = crtc;
9942 work->old_fb = old_fb;
9943 INIT_WORK(&work->work, intel_unpin_work_fn);
9944
9945 ret = drm_crtc_vblank_get(crtc);
9946 if (ret)
9947 goto free_work;
9948
9949 /* We borrow the event spin lock for protecting unpin_work */
9950 spin_lock_irq(&dev->event_lock);
9951 if (intel_crtc->unpin_work) {
9952 /* Before declaring the flip queue wedged, check if
9953 * the hardware completed the operation behind our backs.
9954 */
9955 if (__intel_pageflip_stall_check(dev, crtc)) {
9956 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9957 page_flip_completed(intel_crtc);
9958 } else {
9959 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9960 spin_unlock_irq(&dev->event_lock);
9961
9962 drm_crtc_vblank_put(crtc);
9963 kfree(work);
9964 return -EBUSY;
9965 }
9966 }
9967 intel_crtc->unpin_work = work;
9968 spin_unlock_irq(&dev->event_lock);
9969
9970 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9971 flush_workqueue(dev_priv->wq);
9972
9973 /* Reference the objects for the scheduled work. */
9974 drm_framebuffer_reference(work->old_fb);
9975 drm_gem_object_reference(&obj->base);
9976
9977 crtc->primary->fb = fb;
9978 update_state_fb(crtc->primary);
9979
9980 work->pending_flip_obj = obj;
9981
9982 ret = i915_mutex_lock_interruptible(dev);
9983 if (ret)
9984 goto cleanup;
9985
9986 atomic_inc(&intel_crtc->unpin_work_count);
9987 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9988
9989 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9990 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9991
9992 if (IS_VALLEYVIEW(dev)) {
9993 ring = &dev_priv->ring[BCS];
9994 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
9995 /* vlv: DISPLAY_FLIP fails to change tiling */
9996 ring = NULL;
9997 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
9998 ring = &dev_priv->ring[BCS];
9999 } else if (INTEL_INFO(dev)->gen >= 7) {
10000 ring = i915_gem_request_get_ring(obj->last_read_req);
10001 if (ring == NULL || ring->id != RCS)
10002 ring = &dev_priv->ring[BCS];
10003 } else {
10004 ring = &dev_priv->ring[RCS];
10005 }
10006
10007 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
10008 if (ret)
10009 goto cleanup_pending;
10010
10011 work->gtt_offset =
10012 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
10013
10014 if (use_mmio_flip(ring, obj)) {
10015 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10016 page_flip_flags);
10017 if (ret)
10018 goto cleanup_unpin;
10019
10020 i915_gem_request_assign(&work->flip_queued_req,
10021 obj->last_write_req);
10022 } else {
10023 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
10024 page_flip_flags);
10025 if (ret)
10026 goto cleanup_unpin;
10027
10028 i915_gem_request_assign(&work->flip_queued_req,
10029 intel_ring_get_request(ring));
10030 }
10031
10032 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
10033 work->enable_stall_check = true;
10034
10035 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
10036 INTEL_FRONTBUFFER_PRIMARY(pipe));
10037
10038 intel_fbc_disable(dev);
10039 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10040 mutex_unlock(&dev->struct_mutex);
10041
10042 trace_i915_flip_request(intel_crtc->plane, obj);
10043
10044 return 0;
10045
10046 cleanup_unpin:
10047 intel_unpin_fb_obj(obj);
10048 cleanup_pending:
10049 atomic_dec(&intel_crtc->unpin_work_count);
10050 mutex_unlock(&dev->struct_mutex);
10051 cleanup:
10052 crtc->primary->fb = old_fb;
10053 update_state_fb(crtc->primary);
10054
10055 drm_gem_object_unreference_unlocked(&obj->base);
10056 drm_framebuffer_unreference(work->old_fb);
10057
10058 spin_lock_irq(&dev->event_lock);
10059 intel_crtc->unpin_work = NULL;
10060 spin_unlock_irq(&dev->event_lock);
10061
10062 drm_crtc_vblank_put(crtc);
10063 free_work:
10064 kfree(work);
10065
10066 if (ret == -EIO) {
10067 out_hang:
10068 ret = intel_plane_restore(primary);
10069 if (ret == 0 && event) {
10070 spin_lock_irq(&dev->event_lock);
10071 drm_send_vblank_event(dev, pipe, event);
10072 spin_unlock_irq(&dev->event_lock);
10073 }
10074 }
10075 return ret;
10076 }
10077
10078 static struct drm_crtc_helper_funcs intel_helper_funcs = {
10079 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10080 .load_lut = intel_crtc_load_lut,
10081 .atomic_begin = intel_begin_crtc_commit,
10082 .atomic_flush = intel_finish_crtc_commit,
10083 };
10084
10085 /**
10086 * intel_modeset_update_staged_output_state
10087 *
10088 * Updates the staged output configuration state, e.g. after we've read out the
10089 * current hw state.
10090 */
10091 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
10092 {
10093 struct intel_crtc *crtc;
10094 struct intel_encoder *encoder;
10095 struct intel_connector *connector;
10096
10097 for_each_intel_connector(dev, connector) {
10098 connector->new_encoder =
10099 to_intel_encoder(connector->base.encoder);
10100 }
10101
10102 for_each_intel_encoder(dev, encoder) {
10103 encoder->new_crtc =
10104 to_intel_crtc(encoder->base.crtc);
10105 }
10106
10107 for_each_intel_crtc(dev, crtc) {
10108 crtc->new_enabled = crtc->base.state->enable;
10109
10110 if (crtc->new_enabled)
10111 crtc->new_config = crtc->config;
10112 else
10113 crtc->new_config = NULL;
10114 }
10115 }
10116
10117 /**
10118 * intel_modeset_commit_output_state
10119 *
10120 * This function copies the stage display pipe configuration to the real one.
10121 */
10122 static void intel_modeset_commit_output_state(struct drm_device *dev)
10123 {
10124 struct intel_crtc *crtc;
10125 struct intel_encoder *encoder;
10126 struct intel_connector *connector;
10127
10128 for_each_intel_connector(dev, connector) {
10129 connector->base.encoder = &connector->new_encoder->base;
10130 }
10131
10132 for_each_intel_encoder(dev, encoder) {
10133 encoder->base.crtc = &encoder->new_crtc->base;
10134 }
10135
10136 for_each_intel_crtc(dev, crtc) {
10137 crtc->base.state->enable = crtc->new_enabled;
10138 crtc->base.enabled = crtc->new_enabled;
10139 }
10140 }
10141
10142 static void
10143 connected_sink_compute_bpp(struct intel_connector *connector,
10144 struct intel_crtc_state *pipe_config)
10145 {
10146 int bpp = pipe_config->pipe_bpp;
10147
10148 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10149 connector->base.base.id,
10150 connector->base.name);
10151
10152 /* Don't use an invalid EDID bpc value */
10153 if (connector->base.display_info.bpc &&
10154 connector->base.display_info.bpc * 3 < bpp) {
10155 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10156 bpp, connector->base.display_info.bpc*3);
10157 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10158 }
10159
10160 /* Clamp bpp to 8 on screens without EDID 1.4 */
10161 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10162 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10163 bpp);
10164 pipe_config->pipe_bpp = 24;
10165 }
10166 }
10167
10168 static int
10169 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10170 struct drm_framebuffer *fb,
10171 struct intel_crtc_state *pipe_config)
10172 {
10173 struct drm_device *dev = crtc->base.dev;
10174 struct intel_connector *connector;
10175 int bpp;
10176
10177 switch (fb->pixel_format) {
10178 case DRM_FORMAT_C8:
10179 bpp = 8*3; /* since we go through a colormap */
10180 break;
10181 case DRM_FORMAT_XRGB1555:
10182 case DRM_FORMAT_ARGB1555:
10183 /* checked in intel_framebuffer_init already */
10184 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10185 return -EINVAL;
10186 case DRM_FORMAT_RGB565:
10187 bpp = 6*3; /* min is 18bpp */
10188 break;
10189 case DRM_FORMAT_XBGR8888:
10190 case DRM_FORMAT_ABGR8888:
10191 /* checked in intel_framebuffer_init already */
10192 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10193 return -EINVAL;
10194 case DRM_FORMAT_XRGB8888:
10195 case DRM_FORMAT_ARGB8888:
10196 bpp = 8*3;
10197 break;
10198 case DRM_FORMAT_XRGB2101010:
10199 case DRM_FORMAT_ARGB2101010:
10200 case DRM_FORMAT_XBGR2101010:
10201 case DRM_FORMAT_ABGR2101010:
10202 /* checked in intel_framebuffer_init already */
10203 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10204 return -EINVAL;
10205 bpp = 10*3;
10206 break;
10207 /* TODO: gen4+ supports 16 bpc floating point, too. */
10208 default:
10209 DRM_DEBUG_KMS("unsupported depth\n");
10210 return -EINVAL;
10211 }
10212
10213 pipe_config->pipe_bpp = bpp;
10214
10215 /* Clamp display bpp to EDID value */
10216 for_each_intel_connector(dev, connector) {
10217 if (!connector->new_encoder ||
10218 connector->new_encoder->new_crtc != crtc)
10219 continue;
10220
10221 connected_sink_compute_bpp(connector, pipe_config);
10222 }
10223
10224 return bpp;
10225 }
10226
10227 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10228 {
10229 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10230 "type: 0x%x flags: 0x%x\n",
10231 mode->crtc_clock,
10232 mode->crtc_hdisplay, mode->crtc_hsync_start,
10233 mode->crtc_hsync_end, mode->crtc_htotal,
10234 mode->crtc_vdisplay, mode->crtc_vsync_start,
10235 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10236 }
10237
10238 static void intel_dump_pipe_config(struct intel_crtc *crtc,
10239 struct intel_crtc_state *pipe_config,
10240 const char *context)
10241 {
10242 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10243 context, pipe_name(crtc->pipe));
10244
10245 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10246 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10247 pipe_config->pipe_bpp, pipe_config->dither);
10248 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10249 pipe_config->has_pch_encoder,
10250 pipe_config->fdi_lanes,
10251 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10252 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10253 pipe_config->fdi_m_n.tu);
10254 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10255 pipe_config->has_dp_encoder,
10256 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10257 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10258 pipe_config->dp_m_n.tu);
10259
10260 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10261 pipe_config->has_dp_encoder,
10262 pipe_config->dp_m2_n2.gmch_m,
10263 pipe_config->dp_m2_n2.gmch_n,
10264 pipe_config->dp_m2_n2.link_m,
10265 pipe_config->dp_m2_n2.link_n,
10266 pipe_config->dp_m2_n2.tu);
10267
10268 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10269 pipe_config->has_audio,
10270 pipe_config->has_infoframe);
10271
10272 DRM_DEBUG_KMS("requested mode:\n");
10273 drm_mode_debug_printmodeline(&pipe_config->base.mode);
10274 DRM_DEBUG_KMS("adjusted mode:\n");
10275 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10276 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
10277 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
10278 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10279 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
10280 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10281 pipe_config->gmch_pfit.control,
10282 pipe_config->gmch_pfit.pgm_ratios,
10283 pipe_config->gmch_pfit.lvds_border_bits);
10284 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
10285 pipe_config->pch_pfit.pos,
10286 pipe_config->pch_pfit.size,
10287 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
10288 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
10289 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
10290 }
10291
10292 static bool encoders_cloneable(const struct intel_encoder *a,
10293 const struct intel_encoder *b)
10294 {
10295 /* masks could be asymmetric, so check both ways */
10296 return a == b || (a->cloneable & (1 << b->type) &&
10297 b->cloneable & (1 << a->type));
10298 }
10299
10300 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10301 struct intel_encoder *encoder)
10302 {
10303 struct drm_device *dev = crtc->base.dev;
10304 struct intel_encoder *source_encoder;
10305
10306 for_each_intel_encoder(dev, source_encoder) {
10307 if (source_encoder->new_crtc != crtc)
10308 continue;
10309
10310 if (!encoders_cloneable(encoder, source_encoder))
10311 return false;
10312 }
10313
10314 return true;
10315 }
10316
10317 static bool check_encoder_cloning(struct intel_crtc *crtc)
10318 {
10319 struct drm_device *dev = crtc->base.dev;
10320 struct intel_encoder *encoder;
10321
10322 for_each_intel_encoder(dev, encoder) {
10323 if (encoder->new_crtc != crtc)
10324 continue;
10325
10326 if (!check_single_encoder_cloning(crtc, encoder))
10327 return false;
10328 }
10329
10330 return true;
10331 }
10332
10333 static bool check_digital_port_conflicts(struct drm_device *dev)
10334 {
10335 struct intel_connector *connector;
10336 unsigned int used_ports = 0;
10337
10338 /*
10339 * Walk the connector list instead of the encoder
10340 * list to detect the problem on ddi platforms
10341 * where there's just one encoder per digital port.
10342 */
10343 for_each_intel_connector(dev, connector) {
10344 struct intel_encoder *encoder = connector->new_encoder;
10345
10346 if (!encoder)
10347 continue;
10348
10349 WARN_ON(!encoder->new_crtc);
10350
10351 switch (encoder->type) {
10352 unsigned int port_mask;
10353 case INTEL_OUTPUT_UNKNOWN:
10354 if (WARN_ON(!HAS_DDI(dev)))
10355 break;
10356 case INTEL_OUTPUT_DISPLAYPORT:
10357 case INTEL_OUTPUT_HDMI:
10358 case INTEL_OUTPUT_EDP:
10359 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10360
10361 /* the same port mustn't appear more than once */
10362 if (used_ports & port_mask)
10363 return false;
10364
10365 used_ports |= port_mask;
10366 default:
10367 break;
10368 }
10369 }
10370
10371 return true;
10372 }
10373
10374 static struct intel_crtc_state *
10375 intel_modeset_pipe_config(struct drm_crtc *crtc,
10376 struct drm_framebuffer *fb,
10377 struct drm_display_mode *mode)
10378 {
10379 struct drm_device *dev = crtc->dev;
10380 struct intel_encoder *encoder;
10381 struct intel_crtc_state *pipe_config;
10382 int plane_bpp, ret = -EINVAL;
10383 bool retry = true;
10384
10385 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10386 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10387 return ERR_PTR(-EINVAL);
10388 }
10389
10390 if (!check_digital_port_conflicts(dev)) {
10391 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10392 return ERR_PTR(-EINVAL);
10393 }
10394
10395 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10396 if (!pipe_config)
10397 return ERR_PTR(-ENOMEM);
10398
10399 pipe_config->base.crtc = crtc;
10400 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10401 drm_mode_copy(&pipe_config->base.mode, mode);
10402
10403 pipe_config->cpu_transcoder =
10404 (enum transcoder) to_intel_crtc(crtc)->pipe;
10405 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10406
10407 /*
10408 * Sanitize sync polarity flags based on requested ones. If neither
10409 * positive or negative polarity is requested, treat this as meaning
10410 * negative polarity.
10411 */
10412 if (!(pipe_config->base.adjusted_mode.flags &
10413 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10414 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10415
10416 if (!(pipe_config->base.adjusted_mode.flags &
10417 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10418 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10419
10420 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10421 * plane pixel format and any sink constraints into account. Returns the
10422 * source plane bpp so that dithering can be selected on mismatches
10423 * after encoders and crtc also have had their say. */
10424 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10425 fb, pipe_config);
10426 if (plane_bpp < 0)
10427 goto fail;
10428
10429 /*
10430 * Determine the real pipe dimensions. Note that stereo modes can
10431 * increase the actual pipe size due to the frame doubling and
10432 * insertion of additional space for blanks between the frame. This
10433 * is stored in the crtc timings. We use the requested mode to do this
10434 * computation to clearly distinguish it from the adjusted mode, which
10435 * can be changed by the connectors in the below retry loop.
10436 */
10437 drm_crtc_get_hv_timing(&pipe_config->base.mode,
10438 &pipe_config->pipe_src_w,
10439 &pipe_config->pipe_src_h);
10440
10441 encoder_retry:
10442 /* Ensure the port clock defaults are reset when retrying. */
10443 pipe_config->port_clock = 0;
10444 pipe_config->pixel_multiplier = 1;
10445
10446 /* Fill in default crtc timings, allow encoders to overwrite them. */
10447 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10448 CRTC_STEREO_DOUBLE);
10449
10450 /* Pass our mode to the connectors and the CRTC to give them a chance to
10451 * adjust it according to limitations or connector properties, and also
10452 * a chance to reject the mode entirely.
10453 */
10454 for_each_intel_encoder(dev, encoder) {
10455
10456 if (&encoder->new_crtc->base != crtc)
10457 continue;
10458
10459 if (!(encoder->compute_config(encoder, pipe_config))) {
10460 DRM_DEBUG_KMS("Encoder config failure\n");
10461 goto fail;
10462 }
10463 }
10464
10465 /* Set default port clock if not overwritten by the encoder. Needs to be
10466 * done afterwards in case the encoder adjusts the mode. */
10467 if (!pipe_config->port_clock)
10468 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
10469 * pipe_config->pixel_multiplier;
10470
10471 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10472 if (ret < 0) {
10473 DRM_DEBUG_KMS("CRTC fixup failed\n");
10474 goto fail;
10475 }
10476
10477 if (ret == RETRY) {
10478 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10479 ret = -EINVAL;
10480 goto fail;
10481 }
10482
10483 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10484 retry = false;
10485 goto encoder_retry;
10486 }
10487
10488 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10489 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10490 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10491
10492 return pipe_config;
10493 fail:
10494 kfree(pipe_config);
10495 return ERR_PTR(ret);
10496 }
10497
10498 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10499 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10500 static void
10501 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10502 unsigned *prepare_pipes, unsigned *disable_pipes)
10503 {
10504 struct intel_crtc *intel_crtc;
10505 struct drm_device *dev = crtc->dev;
10506 struct intel_encoder *encoder;
10507 struct intel_connector *connector;
10508 struct drm_crtc *tmp_crtc;
10509
10510 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10511
10512 /* Check which crtcs have changed outputs connected to them, these need
10513 * to be part of the prepare_pipes mask. We don't (yet) support global
10514 * modeset across multiple crtcs, so modeset_pipes will only have one
10515 * bit set at most. */
10516 for_each_intel_connector(dev, connector) {
10517 if (connector->base.encoder == &connector->new_encoder->base)
10518 continue;
10519
10520 if (connector->base.encoder) {
10521 tmp_crtc = connector->base.encoder->crtc;
10522
10523 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10524 }
10525
10526 if (connector->new_encoder)
10527 *prepare_pipes |=
10528 1 << connector->new_encoder->new_crtc->pipe;
10529 }
10530
10531 for_each_intel_encoder(dev, encoder) {
10532 if (encoder->base.crtc == &encoder->new_crtc->base)
10533 continue;
10534
10535 if (encoder->base.crtc) {
10536 tmp_crtc = encoder->base.crtc;
10537
10538 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10539 }
10540
10541 if (encoder->new_crtc)
10542 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10543 }
10544
10545 /* Check for pipes that will be enabled/disabled ... */
10546 for_each_intel_crtc(dev, intel_crtc) {
10547 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
10548 continue;
10549
10550 if (!intel_crtc->new_enabled)
10551 *disable_pipes |= 1 << intel_crtc->pipe;
10552 else
10553 *prepare_pipes |= 1 << intel_crtc->pipe;
10554 }
10555
10556
10557 /* set_mode is also used to update properties on life display pipes. */
10558 intel_crtc = to_intel_crtc(crtc);
10559 if (intel_crtc->new_enabled)
10560 *prepare_pipes |= 1 << intel_crtc->pipe;
10561
10562 /*
10563 * For simplicity do a full modeset on any pipe where the output routing
10564 * changed. We could be more clever, but that would require us to be
10565 * more careful with calling the relevant encoder->mode_set functions.
10566 */
10567 if (*prepare_pipes)
10568 *modeset_pipes = *prepare_pipes;
10569
10570 /* ... and mask these out. */
10571 *modeset_pipes &= ~(*disable_pipes);
10572 *prepare_pipes &= ~(*disable_pipes);
10573
10574 /*
10575 * HACK: We don't (yet) fully support global modesets. intel_set_config
10576 * obies this rule, but the modeset restore mode of
10577 * intel_modeset_setup_hw_state does not.
10578 */
10579 *modeset_pipes &= 1 << intel_crtc->pipe;
10580 *prepare_pipes &= 1 << intel_crtc->pipe;
10581
10582 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10583 *modeset_pipes, *prepare_pipes, *disable_pipes);
10584 }
10585
10586 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10587 {
10588 struct drm_encoder *encoder;
10589 struct drm_device *dev = crtc->dev;
10590
10591 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10592 if (encoder->crtc == crtc)
10593 return true;
10594
10595 return false;
10596 }
10597
10598 static void
10599 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10600 {
10601 struct drm_i915_private *dev_priv = dev->dev_private;
10602 struct intel_encoder *intel_encoder;
10603 struct intel_crtc *intel_crtc;
10604 struct drm_connector *connector;
10605
10606 intel_shared_dpll_commit(dev_priv);
10607
10608 for_each_intel_encoder(dev, intel_encoder) {
10609 if (!intel_encoder->base.crtc)
10610 continue;
10611
10612 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10613
10614 if (prepare_pipes & (1 << intel_crtc->pipe))
10615 intel_encoder->connectors_active = false;
10616 }
10617
10618 intel_modeset_commit_output_state(dev);
10619
10620 /* Double check state. */
10621 for_each_intel_crtc(dev, intel_crtc) {
10622 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
10623 WARN_ON(intel_crtc->new_config &&
10624 intel_crtc->new_config != intel_crtc->config);
10625 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
10626 }
10627
10628 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10629 if (!connector->encoder || !connector->encoder->crtc)
10630 continue;
10631
10632 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10633
10634 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10635 struct drm_property *dpms_property =
10636 dev->mode_config.dpms_property;
10637
10638 connector->dpms = DRM_MODE_DPMS_ON;
10639 drm_object_property_set_value(&connector->base,
10640 dpms_property,
10641 DRM_MODE_DPMS_ON);
10642
10643 intel_encoder = to_intel_encoder(connector->encoder);
10644 intel_encoder->connectors_active = true;
10645 }
10646 }
10647
10648 }
10649
10650 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10651 {
10652 int diff;
10653
10654 if (clock1 == clock2)
10655 return true;
10656
10657 if (!clock1 || !clock2)
10658 return false;
10659
10660 diff = abs(clock1 - clock2);
10661
10662 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10663 return true;
10664
10665 return false;
10666 }
10667
10668 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10669 list_for_each_entry((intel_crtc), \
10670 &(dev)->mode_config.crtc_list, \
10671 base.head) \
10672 if (mask & (1 <<(intel_crtc)->pipe))
10673
10674 static bool
10675 intel_pipe_config_compare(struct drm_device *dev,
10676 struct intel_crtc_state *current_config,
10677 struct intel_crtc_state *pipe_config)
10678 {
10679 #define PIPE_CONF_CHECK_X(name) \
10680 if (current_config->name != pipe_config->name) { \
10681 DRM_ERROR("mismatch in " #name " " \
10682 "(expected 0x%08x, found 0x%08x)\n", \
10683 current_config->name, \
10684 pipe_config->name); \
10685 return false; \
10686 }
10687
10688 #define PIPE_CONF_CHECK_I(name) \
10689 if (current_config->name != pipe_config->name) { \
10690 DRM_ERROR("mismatch in " #name " " \
10691 "(expected %i, found %i)\n", \
10692 current_config->name, \
10693 pipe_config->name); \
10694 return false; \
10695 }
10696
10697 /* This is required for BDW+ where there is only one set of registers for
10698 * switching between high and low RR.
10699 * This macro can be used whenever a comparison has to be made between one
10700 * hw state and multiple sw state variables.
10701 */
10702 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10703 if ((current_config->name != pipe_config->name) && \
10704 (current_config->alt_name != pipe_config->name)) { \
10705 DRM_ERROR("mismatch in " #name " " \
10706 "(expected %i or %i, found %i)\n", \
10707 current_config->name, \
10708 current_config->alt_name, \
10709 pipe_config->name); \
10710 return false; \
10711 }
10712
10713 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10714 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10715 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10716 "(expected %i, found %i)\n", \
10717 current_config->name & (mask), \
10718 pipe_config->name & (mask)); \
10719 return false; \
10720 }
10721
10722 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10723 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10724 DRM_ERROR("mismatch in " #name " " \
10725 "(expected %i, found %i)\n", \
10726 current_config->name, \
10727 pipe_config->name); \
10728 return false; \
10729 }
10730
10731 #define PIPE_CONF_QUIRK(quirk) \
10732 ((current_config->quirks | pipe_config->quirks) & (quirk))
10733
10734 PIPE_CONF_CHECK_I(cpu_transcoder);
10735
10736 PIPE_CONF_CHECK_I(has_pch_encoder);
10737 PIPE_CONF_CHECK_I(fdi_lanes);
10738 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10739 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10740 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10741 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10742 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10743
10744 PIPE_CONF_CHECK_I(has_dp_encoder);
10745
10746 if (INTEL_INFO(dev)->gen < 8) {
10747 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10748 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10749 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10750 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10751 PIPE_CONF_CHECK_I(dp_m_n.tu);
10752
10753 if (current_config->has_drrs) {
10754 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10755 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10756 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10757 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10758 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10759 }
10760 } else {
10761 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10762 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10763 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10764 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10765 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10766 }
10767
10768 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10769 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10770 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10771 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10772 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10773 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
10774
10775 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10776 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10777 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10778 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10779 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10780 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
10781
10782 PIPE_CONF_CHECK_I(pixel_multiplier);
10783 PIPE_CONF_CHECK_I(has_hdmi_sink);
10784 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10785 IS_VALLEYVIEW(dev))
10786 PIPE_CONF_CHECK_I(limited_color_range);
10787 PIPE_CONF_CHECK_I(has_infoframe);
10788
10789 PIPE_CONF_CHECK_I(has_audio);
10790
10791 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10792 DRM_MODE_FLAG_INTERLACE);
10793
10794 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10795 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10796 DRM_MODE_FLAG_PHSYNC);
10797 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10798 DRM_MODE_FLAG_NHSYNC);
10799 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10800 DRM_MODE_FLAG_PVSYNC);
10801 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
10802 DRM_MODE_FLAG_NVSYNC);
10803 }
10804
10805 PIPE_CONF_CHECK_I(pipe_src_w);
10806 PIPE_CONF_CHECK_I(pipe_src_h);
10807
10808 /*
10809 * FIXME: BIOS likes to set up a cloned config with lvds+external
10810 * screen. Since we don't yet re-compute the pipe config when moving
10811 * just the lvds port away to another pipe the sw tracking won't match.
10812 *
10813 * Proper atomic modesets with recomputed global state will fix this.
10814 * Until then just don't check gmch state for inherited modes.
10815 */
10816 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10817 PIPE_CONF_CHECK_I(gmch_pfit.control);
10818 /* pfit ratios are autocomputed by the hw on gen4+ */
10819 if (INTEL_INFO(dev)->gen < 4)
10820 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10821 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10822 }
10823
10824 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10825 if (current_config->pch_pfit.enabled) {
10826 PIPE_CONF_CHECK_I(pch_pfit.pos);
10827 PIPE_CONF_CHECK_I(pch_pfit.size);
10828 }
10829
10830 /* BDW+ don't expose a synchronous way to read the state */
10831 if (IS_HASWELL(dev))
10832 PIPE_CONF_CHECK_I(ips_enabled);
10833
10834 PIPE_CONF_CHECK_I(double_wide);
10835
10836 PIPE_CONF_CHECK_X(ddi_pll_sel);
10837
10838 PIPE_CONF_CHECK_I(shared_dpll);
10839 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10840 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10841 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10842 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10843 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10844 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10845 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10846 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
10847
10848 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10849 PIPE_CONF_CHECK_I(pipe_bpp);
10850
10851 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
10852 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10853
10854 #undef PIPE_CONF_CHECK_X
10855 #undef PIPE_CONF_CHECK_I
10856 #undef PIPE_CONF_CHECK_I_ALT
10857 #undef PIPE_CONF_CHECK_FLAGS
10858 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10859 #undef PIPE_CONF_QUIRK
10860
10861 return true;
10862 }
10863
10864 static void check_wm_state(struct drm_device *dev)
10865 {
10866 struct drm_i915_private *dev_priv = dev->dev_private;
10867 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10868 struct intel_crtc *intel_crtc;
10869 int plane;
10870
10871 if (INTEL_INFO(dev)->gen < 9)
10872 return;
10873
10874 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10875 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10876
10877 for_each_intel_crtc(dev, intel_crtc) {
10878 struct skl_ddb_entry *hw_entry, *sw_entry;
10879 const enum pipe pipe = intel_crtc->pipe;
10880
10881 if (!intel_crtc->active)
10882 continue;
10883
10884 /* planes */
10885 for_each_plane(dev_priv, pipe, plane) {
10886 hw_entry = &hw_ddb.plane[pipe][plane];
10887 sw_entry = &sw_ddb->plane[pipe][plane];
10888
10889 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10890 continue;
10891
10892 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10893 "(expected (%u,%u), found (%u,%u))\n",
10894 pipe_name(pipe), plane + 1,
10895 sw_entry->start, sw_entry->end,
10896 hw_entry->start, hw_entry->end);
10897 }
10898
10899 /* cursor */
10900 hw_entry = &hw_ddb.cursor[pipe];
10901 sw_entry = &sw_ddb->cursor[pipe];
10902
10903 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10904 continue;
10905
10906 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10907 "(expected (%u,%u), found (%u,%u))\n",
10908 pipe_name(pipe),
10909 sw_entry->start, sw_entry->end,
10910 hw_entry->start, hw_entry->end);
10911 }
10912 }
10913
10914 static void
10915 check_connector_state(struct drm_device *dev)
10916 {
10917 struct intel_connector *connector;
10918
10919 for_each_intel_connector(dev, connector) {
10920 /* This also checks the encoder/connector hw state with the
10921 * ->get_hw_state callbacks. */
10922 intel_connector_check_state(connector);
10923
10924 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
10925 "connector's staged encoder doesn't match current encoder\n");
10926 }
10927 }
10928
10929 static void
10930 check_encoder_state(struct drm_device *dev)
10931 {
10932 struct intel_encoder *encoder;
10933 struct intel_connector *connector;
10934
10935 for_each_intel_encoder(dev, encoder) {
10936 bool enabled = false;
10937 bool active = false;
10938 enum pipe pipe, tracked_pipe;
10939
10940 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10941 encoder->base.base.id,
10942 encoder->base.name);
10943
10944 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
10945 "encoder's stage crtc doesn't match current crtc\n");
10946 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
10947 "encoder's active_connectors set, but no crtc\n");
10948
10949 for_each_intel_connector(dev, connector) {
10950 if (connector->base.encoder != &encoder->base)
10951 continue;
10952 enabled = true;
10953 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10954 active = true;
10955 }
10956 /*
10957 * for MST connectors if we unplug the connector is gone
10958 * away but the encoder is still connected to a crtc
10959 * until a modeset happens in response to the hotplug.
10960 */
10961 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10962 continue;
10963
10964 I915_STATE_WARN(!!encoder->base.crtc != enabled,
10965 "encoder's enabled state mismatch "
10966 "(expected %i, found %i)\n",
10967 !!encoder->base.crtc, enabled);
10968 I915_STATE_WARN(active && !encoder->base.crtc,
10969 "active encoder with no crtc\n");
10970
10971 I915_STATE_WARN(encoder->connectors_active != active,
10972 "encoder's computed active state doesn't match tracked active state "
10973 "(expected %i, found %i)\n", active, encoder->connectors_active);
10974
10975 active = encoder->get_hw_state(encoder, &pipe);
10976 I915_STATE_WARN(active != encoder->connectors_active,
10977 "encoder's hw state doesn't match sw tracking "
10978 "(expected %i, found %i)\n",
10979 encoder->connectors_active, active);
10980
10981 if (!encoder->base.crtc)
10982 continue;
10983
10984 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10985 I915_STATE_WARN(active && pipe != tracked_pipe,
10986 "active encoder's pipe doesn't match"
10987 "(expected %i, found %i)\n",
10988 tracked_pipe, pipe);
10989
10990 }
10991 }
10992
10993 static void
10994 check_crtc_state(struct drm_device *dev)
10995 {
10996 struct drm_i915_private *dev_priv = dev->dev_private;
10997 struct intel_crtc *crtc;
10998 struct intel_encoder *encoder;
10999 struct intel_crtc_state pipe_config;
11000
11001 for_each_intel_crtc(dev, crtc) {
11002 bool enabled = false;
11003 bool active = false;
11004
11005 memset(&pipe_config, 0, sizeof(pipe_config));
11006
11007 DRM_DEBUG_KMS("[CRTC:%d]\n",
11008 crtc->base.base.id);
11009
11010 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
11011 "active crtc, but not enabled in sw tracking\n");
11012
11013 for_each_intel_encoder(dev, encoder) {
11014 if (encoder->base.crtc != &crtc->base)
11015 continue;
11016 enabled = true;
11017 if (encoder->connectors_active)
11018 active = true;
11019 }
11020
11021 I915_STATE_WARN(active != crtc->active,
11022 "crtc's computed active state doesn't match tracked active state "
11023 "(expected %i, found %i)\n", active, crtc->active);
11024 I915_STATE_WARN(enabled != crtc->base.state->enable,
11025 "crtc's computed enabled state doesn't match tracked enabled state "
11026 "(expected %i, found %i)\n", enabled,
11027 crtc->base.state->enable);
11028
11029 active = dev_priv->display.get_pipe_config(crtc,
11030 &pipe_config);
11031
11032 /* hw state is inconsistent with the pipe quirk */
11033 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11034 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
11035 active = crtc->active;
11036
11037 for_each_intel_encoder(dev, encoder) {
11038 enum pipe pipe;
11039 if (encoder->base.crtc != &crtc->base)
11040 continue;
11041 if (encoder->get_hw_state(encoder, &pipe))
11042 encoder->get_config(encoder, &pipe_config);
11043 }
11044
11045 I915_STATE_WARN(crtc->active != active,
11046 "crtc active state doesn't match with hw state "
11047 "(expected %i, found %i)\n", crtc->active, active);
11048
11049 if (active &&
11050 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
11051 I915_STATE_WARN(1, "pipe state doesn't match!\n");
11052 intel_dump_pipe_config(crtc, &pipe_config,
11053 "[hw state]");
11054 intel_dump_pipe_config(crtc, crtc->config,
11055 "[sw state]");
11056 }
11057 }
11058 }
11059
11060 static void
11061 check_shared_dpll_state(struct drm_device *dev)
11062 {
11063 struct drm_i915_private *dev_priv = dev->dev_private;
11064 struct intel_crtc *crtc;
11065 struct intel_dpll_hw_state dpll_hw_state;
11066 int i;
11067
11068 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11069 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11070 int enabled_crtcs = 0, active_crtcs = 0;
11071 bool active;
11072
11073 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11074
11075 DRM_DEBUG_KMS("%s\n", pll->name);
11076
11077 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11078
11079 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
11080 "more active pll users than references: %i vs %i\n",
11081 pll->active, hweight32(pll->config.crtc_mask));
11082 I915_STATE_WARN(pll->active && !pll->on,
11083 "pll in active use but not on in sw tracking\n");
11084 I915_STATE_WARN(pll->on && !pll->active,
11085 "pll in on but not on in use in sw tracking\n");
11086 I915_STATE_WARN(pll->on != active,
11087 "pll on state mismatch (expected %i, found %i)\n",
11088 pll->on, active);
11089
11090 for_each_intel_crtc(dev, crtc) {
11091 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
11092 enabled_crtcs++;
11093 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11094 active_crtcs++;
11095 }
11096 I915_STATE_WARN(pll->active != active_crtcs,
11097 "pll active crtcs mismatch (expected %i, found %i)\n",
11098 pll->active, active_crtcs);
11099 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
11100 "pll enabled crtcs mismatch (expected %i, found %i)\n",
11101 hweight32(pll->config.crtc_mask), enabled_crtcs);
11102
11103 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
11104 sizeof(dpll_hw_state)),
11105 "pll hw state mismatch\n");
11106 }
11107 }
11108
11109 void
11110 intel_modeset_check_state(struct drm_device *dev)
11111 {
11112 check_wm_state(dev);
11113 check_connector_state(dev);
11114 check_encoder_state(dev);
11115 check_crtc_state(dev);
11116 check_shared_dpll_state(dev);
11117 }
11118
11119 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
11120 int dotclock)
11121 {
11122 /*
11123 * FDI already provided one idea for the dotclock.
11124 * Yell if the encoder disagrees.
11125 */
11126 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
11127 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
11128 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
11129 }
11130
11131 static void update_scanline_offset(struct intel_crtc *crtc)
11132 {
11133 struct drm_device *dev = crtc->base.dev;
11134
11135 /*
11136 * The scanline counter increments at the leading edge of hsync.
11137 *
11138 * On most platforms it starts counting from vtotal-1 on the
11139 * first active line. That means the scanline counter value is
11140 * always one less than what we would expect. Ie. just after
11141 * start of vblank, which also occurs at start of hsync (on the
11142 * last active line), the scanline counter will read vblank_start-1.
11143 *
11144 * On gen2 the scanline counter starts counting from 1 instead
11145 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11146 * to keep the value positive), instead of adding one.
11147 *
11148 * On HSW+ the behaviour of the scanline counter depends on the output
11149 * type. For DP ports it behaves like most other platforms, but on HDMI
11150 * there's an extra 1 line difference. So we need to add two instead of
11151 * one to the value.
11152 */
11153 if (IS_GEN2(dev)) {
11154 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
11155 int vtotal;
11156
11157 vtotal = mode->crtc_vtotal;
11158 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11159 vtotal /= 2;
11160
11161 crtc->scanline_offset = vtotal - 1;
11162 } else if (HAS_DDI(dev) &&
11163 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
11164 crtc->scanline_offset = 2;
11165 } else
11166 crtc->scanline_offset = 1;
11167 }
11168
11169 static struct intel_crtc_state *
11170 intel_modeset_compute_config(struct drm_crtc *crtc,
11171 struct drm_display_mode *mode,
11172 struct drm_framebuffer *fb,
11173 unsigned *modeset_pipes,
11174 unsigned *prepare_pipes,
11175 unsigned *disable_pipes)
11176 {
11177 struct intel_crtc_state *pipe_config = NULL;
11178
11179 intel_modeset_affected_pipes(crtc, modeset_pipes,
11180 prepare_pipes, disable_pipes);
11181
11182 if ((*modeset_pipes) == 0)
11183 goto out;
11184
11185 /*
11186 * Note this needs changes when we start tracking multiple modes
11187 * and crtcs. At that point we'll need to compute the whole config
11188 * (i.e. one pipe_config for each crtc) rather than just the one
11189 * for this crtc.
11190 */
11191 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11192 if (IS_ERR(pipe_config)) {
11193 goto out;
11194 }
11195 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11196 "[modeset]");
11197
11198 out:
11199 return pipe_config;
11200 }
11201
11202 static int __intel_set_mode_setup_plls(struct drm_device *dev,
11203 unsigned modeset_pipes,
11204 unsigned disable_pipes)
11205 {
11206 struct drm_i915_private *dev_priv = to_i915(dev);
11207 unsigned clear_pipes = modeset_pipes | disable_pipes;
11208 struct intel_crtc *intel_crtc;
11209 int ret = 0;
11210
11211 if (!dev_priv->display.crtc_compute_clock)
11212 return 0;
11213
11214 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11215 if (ret)
11216 goto done;
11217
11218 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11219 struct intel_crtc_state *state = intel_crtc->new_config;
11220 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11221 state);
11222 if (ret) {
11223 intel_shared_dpll_abort_config(dev_priv);
11224 goto done;
11225 }
11226 }
11227
11228 done:
11229 return ret;
11230 }
11231
11232 static int __intel_set_mode(struct drm_crtc *crtc,
11233 struct drm_display_mode *mode,
11234 int x, int y, struct drm_framebuffer *fb,
11235 struct intel_crtc_state *pipe_config,
11236 unsigned modeset_pipes,
11237 unsigned prepare_pipes,
11238 unsigned disable_pipes)
11239 {
11240 struct drm_device *dev = crtc->dev;
11241 struct drm_i915_private *dev_priv = dev->dev_private;
11242 struct drm_display_mode *saved_mode;
11243 struct intel_crtc *intel_crtc;
11244 int ret = 0;
11245
11246 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
11247 if (!saved_mode)
11248 return -ENOMEM;
11249
11250 *saved_mode = crtc->mode;
11251
11252 if (modeset_pipes)
11253 to_intel_crtc(crtc)->new_config = pipe_config;
11254
11255 /*
11256 * See if the config requires any additional preparation, e.g.
11257 * to adjust global state with pipes off. We need to do this
11258 * here so we can get the modeset_pipe updated config for the new
11259 * mode set on this crtc. For other crtcs we need to use the
11260 * adjusted_mode bits in the crtc directly.
11261 */
11262 if (IS_VALLEYVIEW(dev)) {
11263 valleyview_modeset_global_pipes(dev, &prepare_pipes);
11264
11265 /* may have added more to prepare_pipes than we should */
11266 prepare_pipes &= ~disable_pipes;
11267 }
11268
11269 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11270 if (ret)
11271 goto done;
11272
11273 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11274 intel_crtc_disable(&intel_crtc->base);
11275
11276 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11277 if (intel_crtc->base.state->enable)
11278 dev_priv->display.crtc_disable(&intel_crtc->base);
11279 }
11280
11281 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11282 * to set it here already despite that we pass it down the callchain.
11283 *
11284 * Note we'll need to fix this up when we start tracking multiple
11285 * pipes; here we assume a single modeset_pipe and only track the
11286 * single crtc and mode.
11287 */
11288 if (modeset_pipes) {
11289 crtc->mode = *mode;
11290 /* mode_set/enable/disable functions rely on a correct pipe
11291 * config. */
11292 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
11293
11294 /*
11295 * Calculate and store various constants which
11296 * are later needed by vblank and swap-completion
11297 * timestamping. They are derived from true hwmode.
11298 */
11299 drm_calc_timestamping_constants(crtc,
11300 &pipe_config->base.adjusted_mode);
11301 }
11302
11303 /* Only after disabling all output pipelines that will be changed can we
11304 * update the the output configuration. */
11305 intel_modeset_update_state(dev, prepare_pipes);
11306
11307 modeset_update_crtc_power_domains(dev);
11308
11309 /* Set up the DPLL and any encoders state that needs to adjust or depend
11310 * on the DPLL.
11311 */
11312 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11313 struct drm_plane *primary = intel_crtc->base.primary;
11314 int vdisplay, hdisplay;
11315
11316 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11317 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11318 fb, 0, 0,
11319 hdisplay, vdisplay,
11320 x << 16, y << 16,
11321 hdisplay << 16, vdisplay << 16);
11322 }
11323
11324 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
11325 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11326 update_scanline_offset(intel_crtc);
11327
11328 dev_priv->display.crtc_enable(&intel_crtc->base);
11329 }
11330
11331 /* FIXME: add subpixel order */
11332 done:
11333 if (ret && crtc->state->enable)
11334 crtc->mode = *saved_mode;
11335
11336 kfree(saved_mode);
11337 return ret;
11338 }
11339
11340 static int intel_set_mode_pipes(struct drm_crtc *crtc,
11341 struct drm_display_mode *mode,
11342 int x, int y, struct drm_framebuffer *fb,
11343 struct intel_crtc_state *pipe_config,
11344 unsigned modeset_pipes,
11345 unsigned prepare_pipes,
11346 unsigned disable_pipes)
11347 {
11348 int ret;
11349
11350 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11351 prepare_pipes, disable_pipes);
11352
11353 if (ret == 0)
11354 intel_modeset_check_state(crtc->dev);
11355
11356 return ret;
11357 }
11358
11359 static int intel_set_mode(struct drm_crtc *crtc,
11360 struct drm_display_mode *mode,
11361 int x, int y, struct drm_framebuffer *fb)
11362 {
11363 struct intel_crtc_state *pipe_config;
11364 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11365
11366 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11367 &modeset_pipes,
11368 &prepare_pipes,
11369 &disable_pipes);
11370
11371 if (IS_ERR(pipe_config))
11372 return PTR_ERR(pipe_config);
11373
11374 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11375 modeset_pipes, prepare_pipes,
11376 disable_pipes);
11377 }
11378
11379 void intel_crtc_restore_mode(struct drm_crtc *crtc)
11380 {
11381 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
11382 }
11383
11384 #undef for_each_intel_crtc_masked
11385
11386 static void intel_set_config_free(struct intel_set_config *config)
11387 {
11388 if (!config)
11389 return;
11390
11391 kfree(config->save_connector_encoders);
11392 kfree(config->save_encoder_crtcs);
11393 kfree(config->save_crtc_enabled);
11394 kfree(config);
11395 }
11396
11397 static int intel_set_config_save_state(struct drm_device *dev,
11398 struct intel_set_config *config)
11399 {
11400 struct drm_crtc *crtc;
11401 struct drm_encoder *encoder;
11402 struct drm_connector *connector;
11403 int count;
11404
11405 config->save_crtc_enabled =
11406 kcalloc(dev->mode_config.num_crtc,
11407 sizeof(bool), GFP_KERNEL);
11408 if (!config->save_crtc_enabled)
11409 return -ENOMEM;
11410
11411 config->save_encoder_crtcs =
11412 kcalloc(dev->mode_config.num_encoder,
11413 sizeof(struct drm_crtc *), GFP_KERNEL);
11414 if (!config->save_encoder_crtcs)
11415 return -ENOMEM;
11416
11417 config->save_connector_encoders =
11418 kcalloc(dev->mode_config.num_connector,
11419 sizeof(struct drm_encoder *), GFP_KERNEL);
11420 if (!config->save_connector_encoders)
11421 return -ENOMEM;
11422
11423 /* Copy data. Note that driver private data is not affected.
11424 * Should anything bad happen only the expected state is
11425 * restored, not the drivers personal bookkeeping.
11426 */
11427 count = 0;
11428 for_each_crtc(dev, crtc) {
11429 config->save_crtc_enabled[count++] = crtc->state->enable;
11430 }
11431
11432 count = 0;
11433 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11434 config->save_encoder_crtcs[count++] = encoder->crtc;
11435 }
11436
11437 count = 0;
11438 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11439 config->save_connector_encoders[count++] = connector->encoder;
11440 }
11441
11442 return 0;
11443 }
11444
11445 static void intel_set_config_restore_state(struct drm_device *dev,
11446 struct intel_set_config *config)
11447 {
11448 struct intel_crtc *crtc;
11449 struct intel_encoder *encoder;
11450 struct intel_connector *connector;
11451 int count;
11452
11453 count = 0;
11454 for_each_intel_crtc(dev, crtc) {
11455 crtc->new_enabled = config->save_crtc_enabled[count++];
11456
11457 if (crtc->new_enabled)
11458 crtc->new_config = crtc->config;
11459 else
11460 crtc->new_config = NULL;
11461 }
11462
11463 count = 0;
11464 for_each_intel_encoder(dev, encoder) {
11465 encoder->new_crtc =
11466 to_intel_crtc(config->save_encoder_crtcs[count++]);
11467 }
11468
11469 count = 0;
11470 for_each_intel_connector(dev, connector) {
11471 connector->new_encoder =
11472 to_intel_encoder(config->save_connector_encoders[count++]);
11473 }
11474 }
11475
11476 static bool
11477 is_crtc_connector_off(struct drm_mode_set *set)
11478 {
11479 int i;
11480
11481 if (set->num_connectors == 0)
11482 return false;
11483
11484 if (WARN_ON(set->connectors == NULL))
11485 return false;
11486
11487 for (i = 0; i < set->num_connectors; i++)
11488 if (set->connectors[i]->encoder &&
11489 set->connectors[i]->encoder->crtc == set->crtc &&
11490 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11491 return true;
11492
11493 return false;
11494 }
11495
11496 static void
11497 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11498 struct intel_set_config *config)
11499 {
11500
11501 /* We should be able to check here if the fb has the same properties
11502 * and then just flip_or_move it */
11503 if (is_crtc_connector_off(set)) {
11504 config->mode_changed = true;
11505 } else if (set->crtc->primary->fb != set->fb) {
11506 /*
11507 * If we have no fb, we can only flip as long as the crtc is
11508 * active, otherwise we need a full mode set. The crtc may
11509 * be active if we've only disabled the primary plane, or
11510 * in fastboot situations.
11511 */
11512 if (set->crtc->primary->fb == NULL) {
11513 struct intel_crtc *intel_crtc =
11514 to_intel_crtc(set->crtc);
11515
11516 if (intel_crtc->active) {
11517 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11518 config->fb_changed = true;
11519 } else {
11520 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11521 config->mode_changed = true;
11522 }
11523 } else if (set->fb == NULL) {
11524 config->mode_changed = true;
11525 } else if (set->fb->pixel_format !=
11526 set->crtc->primary->fb->pixel_format) {
11527 config->mode_changed = true;
11528 } else {
11529 config->fb_changed = true;
11530 }
11531 }
11532
11533 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11534 config->fb_changed = true;
11535
11536 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11537 DRM_DEBUG_KMS("modes are different, full mode set\n");
11538 drm_mode_debug_printmodeline(&set->crtc->mode);
11539 drm_mode_debug_printmodeline(set->mode);
11540 config->mode_changed = true;
11541 }
11542
11543 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11544 set->crtc->base.id, config->mode_changed, config->fb_changed);
11545 }
11546
11547 static int
11548 intel_modeset_stage_output_state(struct drm_device *dev,
11549 struct drm_mode_set *set,
11550 struct intel_set_config *config)
11551 {
11552 struct intel_connector *connector;
11553 struct intel_encoder *encoder;
11554 struct intel_crtc *crtc;
11555 int ro;
11556
11557 /* The upper layers ensure that we either disable a crtc or have a list
11558 * of connectors. For paranoia, double-check this. */
11559 WARN_ON(!set->fb && (set->num_connectors != 0));
11560 WARN_ON(set->fb && (set->num_connectors == 0));
11561
11562 for_each_intel_connector(dev, connector) {
11563 /* Otherwise traverse passed in connector list and get encoders
11564 * for them. */
11565 for (ro = 0; ro < set->num_connectors; ro++) {
11566 if (set->connectors[ro] == &connector->base) {
11567 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11568 break;
11569 }
11570 }
11571
11572 /* If we disable the crtc, disable all its connectors. Also, if
11573 * the connector is on the changing crtc but not on the new
11574 * connector list, disable it. */
11575 if ((!set->fb || ro == set->num_connectors) &&
11576 connector->base.encoder &&
11577 connector->base.encoder->crtc == set->crtc) {
11578 connector->new_encoder = NULL;
11579
11580 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11581 connector->base.base.id,
11582 connector->base.name);
11583 }
11584
11585
11586 if (&connector->new_encoder->base != connector->base.encoder) {
11587 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11588 connector->base.base.id,
11589 connector->base.name);
11590 config->mode_changed = true;
11591 }
11592 }
11593 /* connector->new_encoder is now updated for all connectors. */
11594
11595 /* Update crtc of enabled connectors. */
11596 for_each_intel_connector(dev, connector) {
11597 struct drm_crtc *new_crtc;
11598
11599 if (!connector->new_encoder)
11600 continue;
11601
11602 new_crtc = connector->new_encoder->base.crtc;
11603
11604 for (ro = 0; ro < set->num_connectors; ro++) {
11605 if (set->connectors[ro] == &connector->base)
11606 new_crtc = set->crtc;
11607 }
11608
11609 /* Make sure the new CRTC will work with the encoder */
11610 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11611 new_crtc)) {
11612 return -EINVAL;
11613 }
11614 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11615
11616 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11617 connector->base.base.id,
11618 connector->base.name,
11619 new_crtc->base.id);
11620 }
11621
11622 /* Check for any encoders that needs to be disabled. */
11623 for_each_intel_encoder(dev, encoder) {
11624 int num_connectors = 0;
11625 for_each_intel_connector(dev, connector) {
11626 if (connector->new_encoder == encoder) {
11627 WARN_ON(!connector->new_encoder->new_crtc);
11628 num_connectors++;
11629 }
11630 }
11631
11632 if (num_connectors == 0)
11633 encoder->new_crtc = NULL;
11634 else if (num_connectors > 1)
11635 return -EINVAL;
11636
11637 /* Only now check for crtc changes so we don't miss encoders
11638 * that will be disabled. */
11639 if (&encoder->new_crtc->base != encoder->base.crtc) {
11640 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11641 encoder->base.base.id,
11642 encoder->base.name);
11643 config->mode_changed = true;
11644 }
11645 }
11646 /* Now we've also updated encoder->new_crtc for all encoders. */
11647 for_each_intel_connector(dev, connector) {
11648 if (connector->new_encoder)
11649 if (connector->new_encoder != connector->encoder)
11650 connector->encoder = connector->new_encoder;
11651 }
11652 for_each_intel_crtc(dev, crtc) {
11653 crtc->new_enabled = false;
11654
11655 for_each_intel_encoder(dev, encoder) {
11656 if (encoder->new_crtc == crtc) {
11657 crtc->new_enabled = true;
11658 break;
11659 }
11660 }
11661
11662 if (crtc->new_enabled != crtc->base.state->enable) {
11663 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11664 crtc->base.base.id,
11665 crtc->new_enabled ? "en" : "dis");
11666 config->mode_changed = true;
11667 }
11668
11669 if (crtc->new_enabled)
11670 crtc->new_config = crtc->config;
11671 else
11672 crtc->new_config = NULL;
11673 }
11674
11675 return 0;
11676 }
11677
11678 static void disable_crtc_nofb(struct intel_crtc *crtc)
11679 {
11680 struct drm_device *dev = crtc->base.dev;
11681 struct intel_encoder *encoder;
11682 struct intel_connector *connector;
11683
11684 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11685 pipe_name(crtc->pipe));
11686
11687 for_each_intel_connector(dev, connector) {
11688 if (connector->new_encoder &&
11689 connector->new_encoder->new_crtc == crtc)
11690 connector->new_encoder = NULL;
11691 }
11692
11693 for_each_intel_encoder(dev, encoder) {
11694 if (encoder->new_crtc == crtc)
11695 encoder->new_crtc = NULL;
11696 }
11697
11698 crtc->new_enabled = false;
11699 crtc->new_config = NULL;
11700 }
11701
11702 static int intel_crtc_set_config(struct drm_mode_set *set)
11703 {
11704 struct drm_device *dev;
11705 struct drm_mode_set save_set;
11706 struct intel_set_config *config;
11707 struct intel_crtc_state *pipe_config;
11708 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11709 int ret;
11710
11711 BUG_ON(!set);
11712 BUG_ON(!set->crtc);
11713 BUG_ON(!set->crtc->helper_private);
11714
11715 /* Enforce sane interface api - has been abused by the fb helper. */
11716 BUG_ON(!set->mode && set->fb);
11717 BUG_ON(set->fb && set->num_connectors == 0);
11718
11719 if (set->fb) {
11720 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11721 set->crtc->base.id, set->fb->base.id,
11722 (int)set->num_connectors, set->x, set->y);
11723 } else {
11724 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11725 }
11726
11727 dev = set->crtc->dev;
11728
11729 ret = -ENOMEM;
11730 config = kzalloc(sizeof(*config), GFP_KERNEL);
11731 if (!config)
11732 goto out_config;
11733
11734 ret = intel_set_config_save_state(dev, config);
11735 if (ret)
11736 goto out_config;
11737
11738 save_set.crtc = set->crtc;
11739 save_set.mode = &set->crtc->mode;
11740 save_set.x = set->crtc->x;
11741 save_set.y = set->crtc->y;
11742 save_set.fb = set->crtc->primary->fb;
11743
11744 /* Compute whether we need a full modeset, only an fb base update or no
11745 * change at all. In the future we might also check whether only the
11746 * mode changed, e.g. for LVDS where we only change the panel fitter in
11747 * such cases. */
11748 intel_set_config_compute_mode_changes(set, config);
11749
11750 ret = intel_modeset_stage_output_state(dev, set, config);
11751 if (ret)
11752 goto fail;
11753
11754 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11755 set->fb,
11756 &modeset_pipes,
11757 &prepare_pipes,
11758 &disable_pipes);
11759 if (IS_ERR(pipe_config)) {
11760 ret = PTR_ERR(pipe_config);
11761 goto fail;
11762 } else if (pipe_config) {
11763 if (pipe_config->has_audio !=
11764 to_intel_crtc(set->crtc)->config->has_audio)
11765 config->mode_changed = true;
11766
11767 /*
11768 * Note we have an issue here with infoframes: current code
11769 * only updates them on the full mode set path per hw
11770 * requirements. So here we should be checking for any
11771 * required changes and forcing a mode set.
11772 */
11773 }
11774
11775 /* set_mode will free it in the mode_changed case */
11776 if (!config->mode_changed)
11777 kfree(pipe_config);
11778
11779 intel_update_pipe_size(to_intel_crtc(set->crtc));
11780
11781 if (config->mode_changed) {
11782 ret = intel_set_mode_pipes(set->crtc, set->mode,
11783 set->x, set->y, set->fb, pipe_config,
11784 modeset_pipes, prepare_pipes,
11785 disable_pipes);
11786 } else if (config->fb_changed) {
11787 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11788 struct drm_plane *primary = set->crtc->primary;
11789 int vdisplay, hdisplay;
11790
11791 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11792 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11793 0, 0, hdisplay, vdisplay,
11794 set->x << 16, set->y << 16,
11795 hdisplay << 16, vdisplay << 16);
11796
11797 /*
11798 * We need to make sure the primary plane is re-enabled if it
11799 * has previously been turned off.
11800 */
11801 if (!intel_crtc->primary_enabled && ret == 0) {
11802 WARN_ON(!intel_crtc->active);
11803 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11804 }
11805
11806 /*
11807 * In the fastboot case this may be our only check of the
11808 * state after boot. It would be better to only do it on
11809 * the first update, but we don't have a nice way of doing that
11810 * (and really, set_config isn't used much for high freq page
11811 * flipping, so increasing its cost here shouldn't be a big
11812 * deal).
11813 */
11814 if (i915.fastboot && ret == 0)
11815 intel_modeset_check_state(set->crtc->dev);
11816 }
11817
11818 if (ret) {
11819 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11820 set->crtc->base.id, ret);
11821 fail:
11822 intel_set_config_restore_state(dev, config);
11823
11824 /*
11825 * HACK: if the pipe was on, but we didn't have a framebuffer,
11826 * force the pipe off to avoid oopsing in the modeset code
11827 * due to fb==NULL. This should only happen during boot since
11828 * we don't yet reconstruct the FB from the hardware state.
11829 */
11830 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11831 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11832
11833 /* Try to restore the config */
11834 if (config->mode_changed &&
11835 intel_set_mode(save_set.crtc, save_set.mode,
11836 save_set.x, save_set.y, save_set.fb))
11837 DRM_ERROR("failed to restore config after modeset failure\n");
11838 }
11839
11840 out_config:
11841 intel_set_config_free(config);
11842 return ret;
11843 }
11844
11845 static const struct drm_crtc_funcs intel_crtc_funcs = {
11846 .gamma_set = intel_crtc_gamma_set,
11847 .set_config = intel_crtc_set_config,
11848 .destroy = intel_crtc_destroy,
11849 .page_flip = intel_crtc_page_flip,
11850 .atomic_duplicate_state = intel_crtc_duplicate_state,
11851 .atomic_destroy_state = intel_crtc_destroy_state,
11852 };
11853
11854 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11855 struct intel_shared_dpll *pll,
11856 struct intel_dpll_hw_state *hw_state)
11857 {
11858 uint32_t val;
11859
11860 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11861 return false;
11862
11863 val = I915_READ(PCH_DPLL(pll->id));
11864 hw_state->dpll = val;
11865 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11866 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11867
11868 return val & DPLL_VCO_ENABLE;
11869 }
11870
11871 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11872 struct intel_shared_dpll *pll)
11873 {
11874 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11875 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11876 }
11877
11878 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11879 struct intel_shared_dpll *pll)
11880 {
11881 /* PCH refclock must be enabled first */
11882 ibx_assert_pch_refclk_enabled(dev_priv);
11883
11884 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11885
11886 /* Wait for the clocks to stabilize. */
11887 POSTING_READ(PCH_DPLL(pll->id));
11888 udelay(150);
11889
11890 /* The pixel multiplier can only be updated once the
11891 * DPLL is enabled and the clocks are stable.
11892 *
11893 * So write it again.
11894 */
11895 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11896 POSTING_READ(PCH_DPLL(pll->id));
11897 udelay(200);
11898 }
11899
11900 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11901 struct intel_shared_dpll *pll)
11902 {
11903 struct drm_device *dev = dev_priv->dev;
11904 struct intel_crtc *crtc;
11905
11906 /* Make sure no transcoder isn't still depending on us. */
11907 for_each_intel_crtc(dev, crtc) {
11908 if (intel_crtc_to_shared_dpll(crtc) == pll)
11909 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11910 }
11911
11912 I915_WRITE(PCH_DPLL(pll->id), 0);
11913 POSTING_READ(PCH_DPLL(pll->id));
11914 udelay(200);
11915 }
11916
11917 static char *ibx_pch_dpll_names[] = {
11918 "PCH DPLL A",
11919 "PCH DPLL B",
11920 };
11921
11922 static void ibx_pch_dpll_init(struct drm_device *dev)
11923 {
11924 struct drm_i915_private *dev_priv = dev->dev_private;
11925 int i;
11926
11927 dev_priv->num_shared_dpll = 2;
11928
11929 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11930 dev_priv->shared_dplls[i].id = i;
11931 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11932 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11933 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11934 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11935 dev_priv->shared_dplls[i].get_hw_state =
11936 ibx_pch_dpll_get_hw_state;
11937 }
11938 }
11939
11940 static void intel_shared_dpll_init(struct drm_device *dev)
11941 {
11942 struct drm_i915_private *dev_priv = dev->dev_private;
11943
11944 if (HAS_DDI(dev))
11945 intel_ddi_pll_init(dev);
11946 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11947 ibx_pch_dpll_init(dev);
11948 else
11949 dev_priv->num_shared_dpll = 0;
11950
11951 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11952 }
11953
11954 /**
11955 * intel_prepare_plane_fb - Prepare fb for usage on plane
11956 * @plane: drm plane to prepare for
11957 * @fb: framebuffer to prepare for presentation
11958 *
11959 * Prepares a framebuffer for usage on a display plane. Generally this
11960 * involves pinning the underlying object and updating the frontbuffer tracking
11961 * bits. Some older platforms need special physical address handling for
11962 * cursor planes.
11963 *
11964 * Returns 0 on success, negative error code on failure.
11965 */
11966 int
11967 intel_prepare_plane_fb(struct drm_plane *plane,
11968 struct drm_framebuffer *fb,
11969 const struct drm_plane_state *new_state)
11970 {
11971 struct drm_device *dev = plane->dev;
11972 struct intel_plane *intel_plane = to_intel_plane(plane);
11973 enum pipe pipe = intel_plane->pipe;
11974 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11975 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11976 unsigned frontbuffer_bits = 0;
11977 int ret = 0;
11978
11979 if (!obj)
11980 return 0;
11981
11982 switch (plane->type) {
11983 case DRM_PLANE_TYPE_PRIMARY:
11984 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
11985 break;
11986 case DRM_PLANE_TYPE_CURSOR:
11987 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
11988 break;
11989 case DRM_PLANE_TYPE_OVERLAY:
11990 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
11991 break;
11992 }
11993
11994 mutex_lock(&dev->struct_mutex);
11995
11996 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
11997 INTEL_INFO(dev)->cursor_needs_physical) {
11998 int align = IS_I830(dev) ? 16 * 1024 : 256;
11999 ret = i915_gem_object_attach_phys(obj, align);
12000 if (ret)
12001 DRM_DEBUG_KMS("failed to attach phys object\n");
12002 } else {
12003 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
12004 }
12005
12006 if (ret == 0)
12007 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12008
12009 mutex_unlock(&dev->struct_mutex);
12010
12011 return ret;
12012 }
12013
12014 /**
12015 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12016 * @plane: drm plane to clean up for
12017 * @fb: old framebuffer that was on plane
12018 *
12019 * Cleans up a framebuffer that has just been removed from a plane.
12020 */
12021 void
12022 intel_cleanup_plane_fb(struct drm_plane *plane,
12023 struct drm_framebuffer *fb,
12024 const struct drm_plane_state *old_state)
12025 {
12026 struct drm_device *dev = plane->dev;
12027 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12028
12029 if (WARN_ON(!obj))
12030 return;
12031
12032 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12033 !INTEL_INFO(dev)->cursor_needs_physical) {
12034 mutex_lock(&dev->struct_mutex);
12035 intel_unpin_fb_obj(obj);
12036 mutex_unlock(&dev->struct_mutex);
12037 }
12038 }
12039
12040 static int
12041 intel_check_primary_plane(struct drm_plane *plane,
12042 struct intel_plane_state *state)
12043 {
12044 struct drm_device *dev = plane->dev;
12045 struct drm_i915_private *dev_priv = dev->dev_private;
12046 struct drm_crtc *crtc = state->base.crtc;
12047 struct intel_crtc *intel_crtc;
12048 struct drm_framebuffer *fb = state->base.fb;
12049 struct drm_rect *dest = &state->dst;
12050 struct drm_rect *src = &state->src;
12051 const struct drm_rect *clip = &state->clip;
12052 int ret;
12053
12054 crtc = crtc ? crtc : plane->crtc;
12055 intel_crtc = to_intel_crtc(crtc);
12056
12057 ret = drm_plane_helper_check_update(plane, crtc, fb,
12058 src, dest, clip,
12059 DRM_PLANE_HELPER_NO_SCALING,
12060 DRM_PLANE_HELPER_NO_SCALING,
12061 false, true, &state->visible);
12062 if (ret)
12063 return ret;
12064
12065 if (intel_crtc->active) {
12066 intel_crtc->atomic.wait_for_flips = true;
12067
12068 /*
12069 * FBC does not work on some platforms for rotated
12070 * planes, so disable it when rotation is not 0 and
12071 * update it when rotation is set back to 0.
12072 *
12073 * FIXME: This is redundant with the fbc update done in
12074 * the primary plane enable function except that that
12075 * one is done too late. We eventually need to unify
12076 * this.
12077 */
12078 if (intel_crtc->primary_enabled &&
12079 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
12080 dev_priv->fbc.crtc == intel_crtc &&
12081 state->base.rotation != BIT(DRM_ROTATE_0)) {
12082 intel_crtc->atomic.disable_fbc = true;
12083 }
12084
12085 if (state->visible) {
12086 /*
12087 * BDW signals flip done immediately if the plane
12088 * is disabled, even if the plane enable is already
12089 * armed to occur at the next vblank :(
12090 */
12091 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12092 intel_crtc->atomic.wait_vblank = true;
12093 }
12094
12095 intel_crtc->atomic.fb_bits |=
12096 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12097
12098 intel_crtc->atomic.update_fbc = true;
12099
12100 /* Update watermarks on tiling changes. */
12101 if (!plane->state->fb || !state->base.fb ||
12102 plane->state->fb->modifier[0] !=
12103 state->base.fb->modifier[0])
12104 intel_crtc->atomic.update_wm = true;
12105 }
12106
12107 return 0;
12108 }
12109
12110 static void
12111 intel_commit_primary_plane(struct drm_plane *plane,
12112 struct intel_plane_state *state)
12113 {
12114 struct drm_crtc *crtc = state->base.crtc;
12115 struct drm_framebuffer *fb = state->base.fb;
12116 struct drm_device *dev = plane->dev;
12117 struct drm_i915_private *dev_priv = dev->dev_private;
12118 struct intel_crtc *intel_crtc;
12119 struct drm_rect *src = &state->src;
12120
12121 crtc = crtc ? crtc : plane->crtc;
12122 intel_crtc = to_intel_crtc(crtc);
12123
12124 plane->fb = fb;
12125 crtc->x = src->x1 >> 16;
12126 crtc->y = src->y1 >> 16;
12127
12128 if (intel_crtc->active) {
12129 if (state->visible) {
12130 /* FIXME: kill this fastboot hack */
12131 intel_update_pipe_size(intel_crtc);
12132
12133 intel_crtc->primary_enabled = true;
12134
12135 dev_priv->display.update_primary_plane(crtc, plane->fb,
12136 crtc->x, crtc->y);
12137 } else {
12138 /*
12139 * If clipping results in a non-visible primary plane,
12140 * we'll disable the primary plane. Note that this is
12141 * a bit different than what happens if userspace
12142 * explicitly disables the plane by passing fb=0
12143 * because plane->fb still gets set and pinned.
12144 */
12145 intel_disable_primary_hw_plane(plane, crtc);
12146 }
12147 }
12148 }
12149
12150 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
12151 {
12152 struct drm_device *dev = crtc->dev;
12153 struct drm_i915_private *dev_priv = dev->dev_private;
12154 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12155 struct intel_plane *intel_plane;
12156 struct drm_plane *p;
12157 unsigned fb_bits = 0;
12158
12159 /* Track fb's for any planes being disabled */
12160 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12161 intel_plane = to_intel_plane(p);
12162
12163 if (intel_crtc->atomic.disabled_planes &
12164 (1 << drm_plane_index(p))) {
12165 switch (p->type) {
12166 case DRM_PLANE_TYPE_PRIMARY:
12167 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12168 break;
12169 case DRM_PLANE_TYPE_CURSOR:
12170 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12171 break;
12172 case DRM_PLANE_TYPE_OVERLAY:
12173 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12174 break;
12175 }
12176
12177 mutex_lock(&dev->struct_mutex);
12178 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12179 mutex_unlock(&dev->struct_mutex);
12180 }
12181 }
12182
12183 if (intel_crtc->atomic.wait_for_flips)
12184 intel_crtc_wait_for_pending_flips(crtc);
12185
12186 if (intel_crtc->atomic.disable_fbc)
12187 intel_fbc_disable(dev);
12188
12189 if (intel_crtc->atomic.pre_disable_primary)
12190 intel_pre_disable_primary(crtc);
12191
12192 if (intel_crtc->atomic.update_wm)
12193 intel_update_watermarks(crtc);
12194
12195 intel_runtime_pm_get(dev_priv);
12196
12197 /* Perform vblank evasion around commit operation */
12198 if (intel_crtc->active)
12199 intel_crtc->atomic.evade =
12200 intel_pipe_update_start(intel_crtc,
12201 &intel_crtc->atomic.start_vbl_count);
12202 }
12203
12204 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12205 {
12206 struct drm_device *dev = crtc->dev;
12207 struct drm_i915_private *dev_priv = dev->dev_private;
12208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12209 struct drm_plane *p;
12210
12211 if (intel_crtc->atomic.evade)
12212 intel_pipe_update_end(intel_crtc,
12213 intel_crtc->atomic.start_vbl_count);
12214
12215 intel_runtime_pm_put(dev_priv);
12216
12217 if (intel_crtc->atomic.wait_vblank)
12218 intel_wait_for_vblank(dev, intel_crtc->pipe);
12219
12220 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12221
12222 if (intel_crtc->atomic.update_fbc) {
12223 mutex_lock(&dev->struct_mutex);
12224 intel_fbc_update(dev);
12225 mutex_unlock(&dev->struct_mutex);
12226 }
12227
12228 if (intel_crtc->atomic.post_enable_primary)
12229 intel_post_enable_primary(crtc);
12230
12231 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12232 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12233 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12234 false, false);
12235
12236 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
12237 }
12238
12239 /**
12240 * intel_plane_destroy - destroy a plane
12241 * @plane: plane to destroy
12242 *
12243 * Common destruction function for all types of planes (primary, cursor,
12244 * sprite).
12245 */
12246 void intel_plane_destroy(struct drm_plane *plane)
12247 {
12248 struct intel_plane *intel_plane = to_intel_plane(plane);
12249 drm_plane_cleanup(plane);
12250 kfree(intel_plane);
12251 }
12252
12253 const struct drm_plane_funcs intel_plane_funcs = {
12254 .update_plane = drm_plane_helper_update,
12255 .disable_plane = drm_plane_helper_disable,
12256 .destroy = intel_plane_destroy,
12257 .set_property = drm_atomic_helper_plane_set_property,
12258 .atomic_get_property = intel_plane_atomic_get_property,
12259 .atomic_set_property = intel_plane_atomic_set_property,
12260 .atomic_duplicate_state = intel_plane_duplicate_state,
12261 .atomic_destroy_state = intel_plane_destroy_state,
12262
12263 };
12264
12265 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12266 int pipe)
12267 {
12268 struct intel_plane *primary;
12269 struct intel_plane_state *state;
12270 const uint32_t *intel_primary_formats;
12271 int num_formats;
12272
12273 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12274 if (primary == NULL)
12275 return NULL;
12276
12277 state = intel_create_plane_state(&primary->base);
12278 if (!state) {
12279 kfree(primary);
12280 return NULL;
12281 }
12282 primary->base.state = &state->base;
12283
12284 primary->can_scale = false;
12285 primary->max_downscale = 1;
12286 primary->pipe = pipe;
12287 primary->plane = pipe;
12288 primary->check_plane = intel_check_primary_plane;
12289 primary->commit_plane = intel_commit_primary_plane;
12290 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12291 primary->plane = !pipe;
12292
12293 if (INTEL_INFO(dev)->gen <= 3) {
12294 intel_primary_formats = intel_primary_formats_gen2;
12295 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12296 } else {
12297 intel_primary_formats = intel_primary_formats_gen4;
12298 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12299 }
12300
12301 drm_universal_plane_init(dev, &primary->base, 0,
12302 &intel_plane_funcs,
12303 intel_primary_formats, num_formats,
12304 DRM_PLANE_TYPE_PRIMARY);
12305
12306 if (INTEL_INFO(dev)->gen >= 4) {
12307 if (!dev->mode_config.rotation_property)
12308 dev->mode_config.rotation_property =
12309 drm_mode_create_rotation_property(dev,
12310 BIT(DRM_ROTATE_0) |
12311 BIT(DRM_ROTATE_180));
12312 if (dev->mode_config.rotation_property)
12313 drm_object_attach_property(&primary->base.base,
12314 dev->mode_config.rotation_property,
12315 state->base.rotation);
12316 }
12317
12318 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12319
12320 return &primary->base;
12321 }
12322
12323 static int
12324 intel_check_cursor_plane(struct drm_plane *plane,
12325 struct intel_plane_state *state)
12326 {
12327 struct drm_crtc *crtc = state->base.crtc;
12328 struct drm_device *dev = plane->dev;
12329 struct drm_framebuffer *fb = state->base.fb;
12330 struct drm_rect *dest = &state->dst;
12331 struct drm_rect *src = &state->src;
12332 const struct drm_rect *clip = &state->clip;
12333 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12334 struct intel_crtc *intel_crtc;
12335 unsigned stride;
12336 int ret;
12337
12338 crtc = crtc ? crtc : plane->crtc;
12339 intel_crtc = to_intel_crtc(crtc);
12340
12341 ret = drm_plane_helper_check_update(plane, crtc, fb,
12342 src, dest, clip,
12343 DRM_PLANE_HELPER_NO_SCALING,
12344 DRM_PLANE_HELPER_NO_SCALING,
12345 true, true, &state->visible);
12346 if (ret)
12347 return ret;
12348
12349
12350 /* if we want to turn off the cursor ignore width and height */
12351 if (!obj)
12352 goto finish;
12353
12354 /* Check for which cursor types we support */
12355 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12356 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12357 state->base.crtc_w, state->base.crtc_h);
12358 return -EINVAL;
12359 }
12360
12361 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12362 if (obj->base.size < stride * state->base.crtc_h) {
12363 DRM_DEBUG_KMS("buffer is too small\n");
12364 return -ENOMEM;
12365 }
12366
12367 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
12368 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12369 ret = -EINVAL;
12370 }
12371
12372 finish:
12373 if (intel_crtc->active) {
12374 if (plane->state->crtc_w != state->base.crtc_w)
12375 intel_crtc->atomic.update_wm = true;
12376
12377 intel_crtc->atomic.fb_bits |=
12378 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12379 }
12380
12381 return ret;
12382 }
12383
12384 static void
12385 intel_commit_cursor_plane(struct drm_plane *plane,
12386 struct intel_plane_state *state)
12387 {
12388 struct drm_crtc *crtc = state->base.crtc;
12389 struct drm_device *dev = plane->dev;
12390 struct intel_crtc *intel_crtc;
12391 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
12392 uint32_t addr;
12393
12394 crtc = crtc ? crtc : plane->crtc;
12395 intel_crtc = to_intel_crtc(crtc);
12396
12397 plane->fb = state->base.fb;
12398 crtc->cursor_x = state->base.crtc_x;
12399 crtc->cursor_y = state->base.crtc_y;
12400
12401 if (intel_crtc->cursor_bo == obj)
12402 goto update;
12403
12404 if (!obj)
12405 addr = 0;
12406 else if (!INTEL_INFO(dev)->cursor_needs_physical)
12407 addr = i915_gem_obj_ggtt_offset(obj);
12408 else
12409 addr = obj->phys_handle->busaddr;
12410
12411 intel_crtc->cursor_addr = addr;
12412 intel_crtc->cursor_bo = obj;
12413 update:
12414
12415 if (intel_crtc->active)
12416 intel_crtc_update_cursor(crtc, state->visible);
12417 }
12418
12419 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12420 int pipe)
12421 {
12422 struct intel_plane *cursor;
12423 struct intel_plane_state *state;
12424
12425 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12426 if (cursor == NULL)
12427 return NULL;
12428
12429 state = intel_create_plane_state(&cursor->base);
12430 if (!state) {
12431 kfree(cursor);
12432 return NULL;
12433 }
12434 cursor->base.state = &state->base;
12435
12436 cursor->can_scale = false;
12437 cursor->max_downscale = 1;
12438 cursor->pipe = pipe;
12439 cursor->plane = pipe;
12440 cursor->check_plane = intel_check_cursor_plane;
12441 cursor->commit_plane = intel_commit_cursor_plane;
12442
12443 drm_universal_plane_init(dev, &cursor->base, 0,
12444 &intel_plane_funcs,
12445 intel_cursor_formats,
12446 ARRAY_SIZE(intel_cursor_formats),
12447 DRM_PLANE_TYPE_CURSOR);
12448
12449 if (INTEL_INFO(dev)->gen >= 4) {
12450 if (!dev->mode_config.rotation_property)
12451 dev->mode_config.rotation_property =
12452 drm_mode_create_rotation_property(dev,
12453 BIT(DRM_ROTATE_0) |
12454 BIT(DRM_ROTATE_180));
12455 if (dev->mode_config.rotation_property)
12456 drm_object_attach_property(&cursor->base.base,
12457 dev->mode_config.rotation_property,
12458 state->base.rotation);
12459 }
12460
12461 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12462
12463 return &cursor->base;
12464 }
12465
12466 static void intel_crtc_init(struct drm_device *dev, int pipe)
12467 {
12468 struct drm_i915_private *dev_priv = dev->dev_private;
12469 struct intel_crtc *intel_crtc;
12470 struct intel_crtc_state *crtc_state = NULL;
12471 struct drm_plane *primary = NULL;
12472 struct drm_plane *cursor = NULL;
12473 int i, ret;
12474
12475 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12476 if (intel_crtc == NULL)
12477 return;
12478
12479 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12480 if (!crtc_state)
12481 goto fail;
12482 intel_crtc_set_state(intel_crtc, crtc_state);
12483 crtc_state->base.crtc = &intel_crtc->base;
12484
12485 primary = intel_primary_plane_create(dev, pipe);
12486 if (!primary)
12487 goto fail;
12488
12489 cursor = intel_cursor_plane_create(dev, pipe);
12490 if (!cursor)
12491 goto fail;
12492
12493 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12494 cursor, &intel_crtc_funcs);
12495 if (ret)
12496 goto fail;
12497
12498 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12499 for (i = 0; i < 256; i++) {
12500 intel_crtc->lut_r[i] = i;
12501 intel_crtc->lut_g[i] = i;
12502 intel_crtc->lut_b[i] = i;
12503 }
12504
12505 /*
12506 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12507 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12508 */
12509 intel_crtc->pipe = pipe;
12510 intel_crtc->plane = pipe;
12511 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12512 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12513 intel_crtc->plane = !pipe;
12514 }
12515
12516 intel_crtc->cursor_base = ~0;
12517 intel_crtc->cursor_cntl = ~0;
12518 intel_crtc->cursor_size = ~0;
12519
12520 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12521 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12522 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12523 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12524
12525 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12526
12527 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12528
12529 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12530 return;
12531
12532 fail:
12533 if (primary)
12534 drm_plane_cleanup(primary);
12535 if (cursor)
12536 drm_plane_cleanup(cursor);
12537 kfree(crtc_state);
12538 kfree(intel_crtc);
12539 }
12540
12541 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12542 {
12543 struct drm_encoder *encoder = connector->base.encoder;
12544 struct drm_device *dev = connector->base.dev;
12545
12546 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12547
12548 if (!encoder || WARN_ON(!encoder->crtc))
12549 return INVALID_PIPE;
12550
12551 return to_intel_crtc(encoder->crtc)->pipe;
12552 }
12553
12554 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12555 struct drm_file *file)
12556 {
12557 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12558 struct drm_crtc *drmmode_crtc;
12559 struct intel_crtc *crtc;
12560
12561 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12562
12563 if (!drmmode_crtc) {
12564 DRM_ERROR("no such CRTC id\n");
12565 return -ENOENT;
12566 }
12567
12568 crtc = to_intel_crtc(drmmode_crtc);
12569 pipe_from_crtc_id->pipe = crtc->pipe;
12570
12571 return 0;
12572 }
12573
12574 static int intel_encoder_clones(struct intel_encoder *encoder)
12575 {
12576 struct drm_device *dev = encoder->base.dev;
12577 struct intel_encoder *source_encoder;
12578 int index_mask = 0;
12579 int entry = 0;
12580
12581 for_each_intel_encoder(dev, source_encoder) {
12582 if (encoders_cloneable(encoder, source_encoder))
12583 index_mask |= (1 << entry);
12584
12585 entry++;
12586 }
12587
12588 return index_mask;
12589 }
12590
12591 static bool has_edp_a(struct drm_device *dev)
12592 {
12593 struct drm_i915_private *dev_priv = dev->dev_private;
12594
12595 if (!IS_MOBILE(dev))
12596 return false;
12597
12598 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12599 return false;
12600
12601 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12602 return false;
12603
12604 return true;
12605 }
12606
12607 static bool intel_crt_present(struct drm_device *dev)
12608 {
12609 struct drm_i915_private *dev_priv = dev->dev_private;
12610
12611 if (INTEL_INFO(dev)->gen >= 9)
12612 return false;
12613
12614 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12615 return false;
12616
12617 if (IS_CHERRYVIEW(dev))
12618 return false;
12619
12620 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12621 return false;
12622
12623 return true;
12624 }
12625
12626 static void intel_setup_outputs(struct drm_device *dev)
12627 {
12628 struct drm_i915_private *dev_priv = dev->dev_private;
12629 struct intel_encoder *encoder;
12630 struct drm_connector *connector;
12631 bool dpd_is_edp = false;
12632
12633 intel_lvds_init(dev);
12634
12635 if (intel_crt_present(dev))
12636 intel_crt_init(dev);
12637
12638 if (HAS_DDI(dev)) {
12639 int found;
12640
12641 /*
12642 * Haswell uses DDI functions to detect digital outputs.
12643 * On SKL pre-D0 the strap isn't connected, so we assume
12644 * it's there.
12645 */
12646 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12647 /* WaIgnoreDDIAStrap: skl */
12648 if (found ||
12649 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
12650 intel_ddi_init(dev, PORT_A);
12651
12652 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12653 * register */
12654 found = I915_READ(SFUSE_STRAP);
12655
12656 if (found & SFUSE_STRAP_DDIB_DETECTED)
12657 intel_ddi_init(dev, PORT_B);
12658 if (found & SFUSE_STRAP_DDIC_DETECTED)
12659 intel_ddi_init(dev, PORT_C);
12660 if (found & SFUSE_STRAP_DDID_DETECTED)
12661 intel_ddi_init(dev, PORT_D);
12662 } else if (HAS_PCH_SPLIT(dev)) {
12663 int found;
12664 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12665
12666 if (has_edp_a(dev))
12667 intel_dp_init(dev, DP_A, PORT_A);
12668
12669 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12670 /* PCH SDVOB multiplex with HDMIB */
12671 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12672 if (!found)
12673 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12674 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12675 intel_dp_init(dev, PCH_DP_B, PORT_B);
12676 }
12677
12678 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12679 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12680
12681 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12682 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12683
12684 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12685 intel_dp_init(dev, PCH_DP_C, PORT_C);
12686
12687 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12688 intel_dp_init(dev, PCH_DP_D, PORT_D);
12689 } else if (IS_VALLEYVIEW(dev)) {
12690 /*
12691 * The DP_DETECTED bit is the latched state of the DDC
12692 * SDA pin at boot. However since eDP doesn't require DDC
12693 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12694 * eDP ports may have been muxed to an alternate function.
12695 * Thus we can't rely on the DP_DETECTED bit alone to detect
12696 * eDP ports. Consult the VBT as well as DP_DETECTED to
12697 * detect eDP ports.
12698 */
12699 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12700 !intel_dp_is_edp(dev, PORT_B))
12701 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12702 PORT_B);
12703 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12704 intel_dp_is_edp(dev, PORT_B))
12705 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12706
12707 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12708 !intel_dp_is_edp(dev, PORT_C))
12709 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12710 PORT_C);
12711 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12712 intel_dp_is_edp(dev, PORT_C))
12713 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12714
12715 if (IS_CHERRYVIEW(dev)) {
12716 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12717 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12718 PORT_D);
12719 /* eDP not supported on port D, so don't check VBT */
12720 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12721 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12722 }
12723
12724 intel_dsi_init(dev);
12725 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12726 bool found = false;
12727
12728 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12729 DRM_DEBUG_KMS("probing SDVOB\n");
12730 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12731 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12732 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12733 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12734 }
12735
12736 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12737 intel_dp_init(dev, DP_B, PORT_B);
12738 }
12739
12740 /* Before G4X SDVOC doesn't have its own detect register */
12741
12742 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12743 DRM_DEBUG_KMS("probing SDVOC\n");
12744 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12745 }
12746
12747 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12748
12749 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12750 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12751 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12752 }
12753 if (SUPPORTS_INTEGRATED_DP(dev))
12754 intel_dp_init(dev, DP_C, PORT_C);
12755 }
12756
12757 if (SUPPORTS_INTEGRATED_DP(dev) &&
12758 (I915_READ(DP_D) & DP_DETECTED))
12759 intel_dp_init(dev, DP_D, PORT_D);
12760 } else if (IS_GEN2(dev))
12761 intel_dvo_init(dev);
12762
12763 if (SUPPORTS_TV(dev))
12764 intel_tv_init(dev);
12765
12766 /*
12767 * FIXME: We don't have full atomic support yet, but we want to be
12768 * able to enable/test plane updates via the atomic interface in the
12769 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12770 * will take some atomic codepaths to lookup properties during
12771 * drmModeGetConnector() that unconditionally dereference
12772 * connector->state.
12773 *
12774 * We create a dummy connector state here for each connector to ensure
12775 * the DRM core doesn't try to dereference a NULL connector->state.
12776 * The actual connector properties will never be updated or contain
12777 * useful information, but since we're doing this specifically for
12778 * testing/debug of the plane operations (and only when a specific
12779 * kernel module option is given), that shouldn't really matter.
12780 *
12781 * Once atomic support for crtc's + connectors lands, this loop should
12782 * be removed since we'll be setting up real connector state, which
12783 * will contain Intel-specific properties.
12784 */
12785 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12786 list_for_each_entry(connector,
12787 &dev->mode_config.connector_list,
12788 head) {
12789 if (!WARN_ON(connector->state)) {
12790 connector->state =
12791 kzalloc(sizeof(*connector->state),
12792 GFP_KERNEL);
12793 }
12794 }
12795 }
12796
12797 intel_psr_init(dev);
12798
12799 for_each_intel_encoder(dev, encoder) {
12800 encoder->base.possible_crtcs = encoder->crtc_mask;
12801 encoder->base.possible_clones =
12802 intel_encoder_clones(encoder);
12803 }
12804
12805 intel_init_pch_refclk(dev);
12806
12807 drm_helper_move_panel_connectors_to_head(dev);
12808 }
12809
12810 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12811 {
12812 struct drm_device *dev = fb->dev;
12813 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12814
12815 drm_framebuffer_cleanup(fb);
12816 mutex_lock(&dev->struct_mutex);
12817 WARN_ON(!intel_fb->obj->framebuffer_references--);
12818 drm_gem_object_unreference(&intel_fb->obj->base);
12819 mutex_unlock(&dev->struct_mutex);
12820 kfree(intel_fb);
12821 }
12822
12823 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12824 struct drm_file *file,
12825 unsigned int *handle)
12826 {
12827 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12828 struct drm_i915_gem_object *obj = intel_fb->obj;
12829
12830 return drm_gem_handle_create(file, &obj->base, handle);
12831 }
12832
12833 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12834 .destroy = intel_user_framebuffer_destroy,
12835 .create_handle = intel_user_framebuffer_create_handle,
12836 };
12837
12838 static
12839 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12840 uint32_t pixel_format)
12841 {
12842 u32 gen = INTEL_INFO(dev)->gen;
12843
12844 if (gen >= 9) {
12845 /* "The stride in bytes must not exceed the of the size of 8K
12846 * pixels and 32K bytes."
12847 */
12848 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12849 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12850 return 32*1024;
12851 } else if (gen >= 4) {
12852 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12853 return 16*1024;
12854 else
12855 return 32*1024;
12856 } else if (gen >= 3) {
12857 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12858 return 8*1024;
12859 else
12860 return 16*1024;
12861 } else {
12862 /* XXX DSPC is limited to 4k tiled */
12863 return 8*1024;
12864 }
12865 }
12866
12867 static int intel_framebuffer_init(struct drm_device *dev,
12868 struct intel_framebuffer *intel_fb,
12869 struct drm_mode_fb_cmd2 *mode_cmd,
12870 struct drm_i915_gem_object *obj)
12871 {
12872 int aligned_height;
12873 int ret;
12874 u32 pitch_limit, stride_alignment;
12875
12876 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12877
12878 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12879 /* Enforce that fb modifier and tiling mode match, but only for
12880 * X-tiled. This is needed for FBC. */
12881 if (!!(obj->tiling_mode == I915_TILING_X) !=
12882 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12883 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12884 return -EINVAL;
12885 }
12886 } else {
12887 if (obj->tiling_mode == I915_TILING_X)
12888 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12889 else if (obj->tiling_mode == I915_TILING_Y) {
12890 DRM_DEBUG("No Y tiling for legacy addfb\n");
12891 return -EINVAL;
12892 }
12893 }
12894
12895 /* Passed in modifier sanity checking. */
12896 switch (mode_cmd->modifier[0]) {
12897 case I915_FORMAT_MOD_Y_TILED:
12898 case I915_FORMAT_MOD_Yf_TILED:
12899 if (INTEL_INFO(dev)->gen < 9) {
12900 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
12901 mode_cmd->modifier[0]);
12902 return -EINVAL;
12903 }
12904 case DRM_FORMAT_MOD_NONE:
12905 case I915_FORMAT_MOD_X_TILED:
12906 break;
12907 default:
12908 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
12909 mode_cmd->modifier[0]);
12910 return -EINVAL;
12911 }
12912
12913 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
12914 mode_cmd->pixel_format);
12915 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
12916 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
12917 mode_cmd->pitches[0], stride_alignment);
12918 return -EINVAL;
12919 }
12920
12921 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
12922 mode_cmd->pixel_format);
12923 if (mode_cmd->pitches[0] > pitch_limit) {
12924 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
12925 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
12926 "tiled" : "linear",
12927 mode_cmd->pitches[0], pitch_limit);
12928 return -EINVAL;
12929 }
12930
12931 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
12932 mode_cmd->pitches[0] != obj->stride) {
12933 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12934 mode_cmd->pitches[0], obj->stride);
12935 return -EINVAL;
12936 }
12937
12938 /* Reject formats not supported by any plane early. */
12939 switch (mode_cmd->pixel_format) {
12940 case DRM_FORMAT_C8:
12941 case DRM_FORMAT_RGB565:
12942 case DRM_FORMAT_XRGB8888:
12943 case DRM_FORMAT_ARGB8888:
12944 break;
12945 case DRM_FORMAT_XRGB1555:
12946 case DRM_FORMAT_ARGB1555:
12947 if (INTEL_INFO(dev)->gen > 3) {
12948 DRM_DEBUG("unsupported pixel format: %s\n",
12949 drm_get_format_name(mode_cmd->pixel_format));
12950 return -EINVAL;
12951 }
12952 break;
12953 case DRM_FORMAT_XBGR8888:
12954 case DRM_FORMAT_ABGR8888:
12955 case DRM_FORMAT_XRGB2101010:
12956 case DRM_FORMAT_ARGB2101010:
12957 case DRM_FORMAT_XBGR2101010:
12958 case DRM_FORMAT_ABGR2101010:
12959 if (INTEL_INFO(dev)->gen < 4) {
12960 DRM_DEBUG("unsupported pixel format: %s\n",
12961 drm_get_format_name(mode_cmd->pixel_format));
12962 return -EINVAL;
12963 }
12964 break;
12965 case DRM_FORMAT_YUYV:
12966 case DRM_FORMAT_UYVY:
12967 case DRM_FORMAT_YVYU:
12968 case DRM_FORMAT_VYUY:
12969 if (INTEL_INFO(dev)->gen < 5) {
12970 DRM_DEBUG("unsupported pixel format: %s\n",
12971 drm_get_format_name(mode_cmd->pixel_format));
12972 return -EINVAL;
12973 }
12974 break;
12975 default:
12976 DRM_DEBUG("unsupported pixel format: %s\n",
12977 drm_get_format_name(mode_cmd->pixel_format));
12978 return -EINVAL;
12979 }
12980
12981 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12982 if (mode_cmd->offsets[0] != 0)
12983 return -EINVAL;
12984
12985 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
12986 mode_cmd->pixel_format,
12987 mode_cmd->modifier[0]);
12988 /* FIXME drm helper for size checks (especially planar formats)? */
12989 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12990 return -EINVAL;
12991
12992 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12993 intel_fb->obj = obj;
12994 intel_fb->obj->framebuffer_references++;
12995
12996 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12997 if (ret) {
12998 DRM_ERROR("framebuffer init failed %d\n", ret);
12999 return ret;
13000 }
13001
13002 return 0;
13003 }
13004
13005 static struct drm_framebuffer *
13006 intel_user_framebuffer_create(struct drm_device *dev,
13007 struct drm_file *filp,
13008 struct drm_mode_fb_cmd2 *mode_cmd)
13009 {
13010 struct drm_i915_gem_object *obj;
13011
13012 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13013 mode_cmd->handles[0]));
13014 if (&obj->base == NULL)
13015 return ERR_PTR(-ENOENT);
13016
13017 return intel_framebuffer_create(dev, mode_cmd, obj);
13018 }
13019
13020 #ifndef CONFIG_DRM_I915_FBDEV
13021 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
13022 {
13023 }
13024 #endif
13025
13026 static const struct drm_mode_config_funcs intel_mode_funcs = {
13027 .fb_create = intel_user_framebuffer_create,
13028 .output_poll_changed = intel_fbdev_output_poll_changed,
13029 .atomic_check = intel_atomic_check,
13030 .atomic_commit = intel_atomic_commit,
13031 };
13032
13033 /* Set up chip specific display functions */
13034 static void intel_init_display(struct drm_device *dev)
13035 {
13036 struct drm_i915_private *dev_priv = dev->dev_private;
13037
13038 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13039 dev_priv->display.find_dpll = g4x_find_best_dpll;
13040 else if (IS_CHERRYVIEW(dev))
13041 dev_priv->display.find_dpll = chv_find_best_dpll;
13042 else if (IS_VALLEYVIEW(dev))
13043 dev_priv->display.find_dpll = vlv_find_best_dpll;
13044 else if (IS_PINEVIEW(dev))
13045 dev_priv->display.find_dpll = pnv_find_best_dpll;
13046 else
13047 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13048
13049 if (INTEL_INFO(dev)->gen >= 9) {
13050 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13051 dev_priv->display.get_initial_plane_config =
13052 skylake_get_initial_plane_config;
13053 dev_priv->display.crtc_compute_clock =
13054 haswell_crtc_compute_clock;
13055 dev_priv->display.crtc_enable = haswell_crtc_enable;
13056 dev_priv->display.crtc_disable = haswell_crtc_disable;
13057 dev_priv->display.off = ironlake_crtc_off;
13058 dev_priv->display.update_primary_plane =
13059 skylake_update_primary_plane;
13060 } else if (HAS_DDI(dev)) {
13061 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
13062 dev_priv->display.get_initial_plane_config =
13063 ironlake_get_initial_plane_config;
13064 dev_priv->display.crtc_compute_clock =
13065 haswell_crtc_compute_clock;
13066 dev_priv->display.crtc_enable = haswell_crtc_enable;
13067 dev_priv->display.crtc_disable = haswell_crtc_disable;
13068 dev_priv->display.off = ironlake_crtc_off;
13069 dev_priv->display.update_primary_plane =
13070 ironlake_update_primary_plane;
13071 } else if (HAS_PCH_SPLIT(dev)) {
13072 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
13073 dev_priv->display.get_initial_plane_config =
13074 ironlake_get_initial_plane_config;
13075 dev_priv->display.crtc_compute_clock =
13076 ironlake_crtc_compute_clock;
13077 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13078 dev_priv->display.crtc_disable = ironlake_crtc_disable;
13079 dev_priv->display.off = ironlake_crtc_off;
13080 dev_priv->display.update_primary_plane =
13081 ironlake_update_primary_plane;
13082 } else if (IS_VALLEYVIEW(dev)) {
13083 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13084 dev_priv->display.get_initial_plane_config =
13085 i9xx_get_initial_plane_config;
13086 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13087 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13088 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13089 dev_priv->display.off = i9xx_crtc_off;
13090 dev_priv->display.update_primary_plane =
13091 i9xx_update_primary_plane;
13092 } else {
13093 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
13094 dev_priv->display.get_initial_plane_config =
13095 i9xx_get_initial_plane_config;
13096 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
13097 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13098 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13099 dev_priv->display.off = i9xx_crtc_off;
13100 dev_priv->display.update_primary_plane =
13101 i9xx_update_primary_plane;
13102 }
13103
13104 /* Returns the core display clock speed */
13105 if (IS_VALLEYVIEW(dev))
13106 dev_priv->display.get_display_clock_speed =
13107 valleyview_get_display_clock_speed;
13108 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
13109 dev_priv->display.get_display_clock_speed =
13110 i945_get_display_clock_speed;
13111 else if (IS_I915G(dev))
13112 dev_priv->display.get_display_clock_speed =
13113 i915_get_display_clock_speed;
13114 else if (IS_I945GM(dev) || IS_845G(dev))
13115 dev_priv->display.get_display_clock_speed =
13116 i9xx_misc_get_display_clock_speed;
13117 else if (IS_PINEVIEW(dev))
13118 dev_priv->display.get_display_clock_speed =
13119 pnv_get_display_clock_speed;
13120 else if (IS_I915GM(dev))
13121 dev_priv->display.get_display_clock_speed =
13122 i915gm_get_display_clock_speed;
13123 else if (IS_I865G(dev))
13124 dev_priv->display.get_display_clock_speed =
13125 i865_get_display_clock_speed;
13126 else if (IS_I85X(dev))
13127 dev_priv->display.get_display_clock_speed =
13128 i855_get_display_clock_speed;
13129 else /* 852, 830 */
13130 dev_priv->display.get_display_clock_speed =
13131 i830_get_display_clock_speed;
13132
13133 if (IS_GEN5(dev)) {
13134 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
13135 } else if (IS_GEN6(dev)) {
13136 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
13137 } else if (IS_IVYBRIDGE(dev)) {
13138 /* FIXME: detect B0+ stepping and use auto training */
13139 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
13140 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
13141 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
13142 } else if (IS_VALLEYVIEW(dev)) {
13143 dev_priv->display.modeset_global_resources =
13144 valleyview_modeset_global_resources;
13145 }
13146
13147 switch (INTEL_INFO(dev)->gen) {
13148 case 2:
13149 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13150 break;
13151
13152 case 3:
13153 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13154 break;
13155
13156 case 4:
13157 case 5:
13158 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13159 break;
13160
13161 case 6:
13162 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13163 break;
13164 case 7:
13165 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
13166 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13167 break;
13168 case 9:
13169 /* Drop through - unsupported since execlist only. */
13170 default:
13171 /* Default just returns -ENODEV to indicate unsupported */
13172 dev_priv->display.queue_flip = intel_default_queue_flip;
13173 }
13174
13175 intel_panel_init_backlight_funcs(dev);
13176
13177 mutex_init(&dev_priv->pps_mutex);
13178 }
13179
13180 /*
13181 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13182 * resume, or other times. This quirk makes sure that's the case for
13183 * affected systems.
13184 */
13185 static void quirk_pipea_force(struct drm_device *dev)
13186 {
13187 struct drm_i915_private *dev_priv = dev->dev_private;
13188
13189 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
13190 DRM_INFO("applying pipe a force quirk\n");
13191 }
13192
13193 static void quirk_pipeb_force(struct drm_device *dev)
13194 {
13195 struct drm_i915_private *dev_priv = dev->dev_private;
13196
13197 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13198 DRM_INFO("applying pipe b force quirk\n");
13199 }
13200
13201 /*
13202 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13203 */
13204 static void quirk_ssc_force_disable(struct drm_device *dev)
13205 {
13206 struct drm_i915_private *dev_priv = dev->dev_private;
13207 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
13208 DRM_INFO("applying lvds SSC disable quirk\n");
13209 }
13210
13211 /*
13212 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13213 * brightness value
13214 */
13215 static void quirk_invert_brightness(struct drm_device *dev)
13216 {
13217 struct drm_i915_private *dev_priv = dev->dev_private;
13218 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
13219 DRM_INFO("applying inverted panel brightness quirk\n");
13220 }
13221
13222 /* Some VBT's incorrectly indicate no backlight is present */
13223 static void quirk_backlight_present(struct drm_device *dev)
13224 {
13225 struct drm_i915_private *dev_priv = dev->dev_private;
13226 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13227 DRM_INFO("applying backlight present quirk\n");
13228 }
13229
13230 struct intel_quirk {
13231 int device;
13232 int subsystem_vendor;
13233 int subsystem_device;
13234 void (*hook)(struct drm_device *dev);
13235 };
13236
13237 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13238 struct intel_dmi_quirk {
13239 void (*hook)(struct drm_device *dev);
13240 const struct dmi_system_id (*dmi_id_list)[];
13241 };
13242
13243 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13244 {
13245 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13246 return 1;
13247 }
13248
13249 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13250 {
13251 .dmi_id_list = &(const struct dmi_system_id[]) {
13252 {
13253 .callback = intel_dmi_reverse_brightness,
13254 .ident = "NCR Corporation",
13255 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13256 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13257 },
13258 },
13259 { } /* terminating entry */
13260 },
13261 .hook = quirk_invert_brightness,
13262 },
13263 };
13264
13265 static struct intel_quirk intel_quirks[] = {
13266 /* HP Mini needs pipe A force quirk (LP: #322104) */
13267 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
13268
13269 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13270 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13271
13272 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13273 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13274
13275 /* 830 needs to leave pipe A & dpll A up */
13276 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13277
13278 /* 830 needs to leave pipe B & dpll B up */
13279 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13280
13281 /* Lenovo U160 cannot use SSC on LVDS */
13282 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
13283
13284 /* Sony Vaio Y cannot use SSC on LVDS */
13285 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
13286
13287 /* Acer Aspire 5734Z must invert backlight brightness */
13288 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13289
13290 /* Acer/eMachines G725 */
13291 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13292
13293 /* Acer/eMachines e725 */
13294 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13295
13296 /* Acer/Packard Bell NCL20 */
13297 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13298
13299 /* Acer Aspire 4736Z */
13300 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
13301
13302 /* Acer Aspire 5336 */
13303 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
13304
13305 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13306 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
13307
13308 /* Acer C720 Chromebook (Core i3 4005U) */
13309 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13310
13311 /* Apple Macbook 2,1 (Core 2 T7400) */
13312 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13313
13314 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13315 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
13316
13317 /* HP Chromebook 14 (Celeron 2955U) */
13318 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13319
13320 /* Dell Chromebook 11 */
13321 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13322 };
13323
13324 static void intel_init_quirks(struct drm_device *dev)
13325 {
13326 struct pci_dev *d = dev->pdev;
13327 int i;
13328
13329 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13330 struct intel_quirk *q = &intel_quirks[i];
13331
13332 if (d->device == q->device &&
13333 (d->subsystem_vendor == q->subsystem_vendor ||
13334 q->subsystem_vendor == PCI_ANY_ID) &&
13335 (d->subsystem_device == q->subsystem_device ||
13336 q->subsystem_device == PCI_ANY_ID))
13337 q->hook(dev);
13338 }
13339 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13340 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13341 intel_dmi_quirks[i].hook(dev);
13342 }
13343 }
13344
13345 /* Disable the VGA plane that we never use */
13346 static void i915_disable_vga(struct drm_device *dev)
13347 {
13348 struct drm_i915_private *dev_priv = dev->dev_private;
13349 u8 sr1;
13350 u32 vga_reg = i915_vgacntrl_reg(dev);
13351
13352 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
13353 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
13354 outb(SR01, VGA_SR_INDEX);
13355 sr1 = inb(VGA_SR_DATA);
13356 outb(sr1 | 1<<5, VGA_SR_DATA);
13357 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13358 udelay(300);
13359
13360 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
13361 POSTING_READ(vga_reg);
13362 }
13363
13364 void intel_modeset_init_hw(struct drm_device *dev)
13365 {
13366 intel_prepare_ddi(dev);
13367
13368 if (IS_VALLEYVIEW(dev))
13369 vlv_update_cdclk(dev);
13370
13371 intel_init_clock_gating(dev);
13372
13373 intel_enable_gt_powersave(dev);
13374 }
13375
13376 void intel_modeset_init(struct drm_device *dev)
13377 {
13378 struct drm_i915_private *dev_priv = dev->dev_private;
13379 int sprite, ret;
13380 enum pipe pipe;
13381 struct intel_crtc *crtc;
13382
13383 drm_mode_config_init(dev);
13384
13385 dev->mode_config.min_width = 0;
13386 dev->mode_config.min_height = 0;
13387
13388 dev->mode_config.preferred_depth = 24;
13389 dev->mode_config.prefer_shadow = 1;
13390
13391 dev->mode_config.allow_fb_modifiers = true;
13392
13393 dev->mode_config.funcs = &intel_mode_funcs;
13394
13395 intel_init_quirks(dev);
13396
13397 intel_init_pm(dev);
13398
13399 if (INTEL_INFO(dev)->num_pipes == 0)
13400 return;
13401
13402 intel_init_display(dev);
13403 intel_init_audio(dev);
13404
13405 if (IS_GEN2(dev)) {
13406 dev->mode_config.max_width = 2048;
13407 dev->mode_config.max_height = 2048;
13408 } else if (IS_GEN3(dev)) {
13409 dev->mode_config.max_width = 4096;
13410 dev->mode_config.max_height = 4096;
13411 } else {
13412 dev->mode_config.max_width = 8192;
13413 dev->mode_config.max_height = 8192;
13414 }
13415
13416 if (IS_845G(dev) || IS_I865G(dev)) {
13417 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13418 dev->mode_config.cursor_height = 1023;
13419 } else if (IS_GEN2(dev)) {
13420 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13421 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13422 } else {
13423 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13424 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13425 }
13426
13427 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
13428
13429 DRM_DEBUG_KMS("%d display pipe%s available.\n",
13430 INTEL_INFO(dev)->num_pipes,
13431 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
13432
13433 for_each_pipe(dev_priv, pipe) {
13434 intel_crtc_init(dev, pipe);
13435 for_each_sprite(dev_priv, pipe, sprite) {
13436 ret = intel_plane_init(dev, pipe, sprite);
13437 if (ret)
13438 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
13439 pipe_name(pipe), sprite_name(pipe, sprite), ret);
13440 }
13441 }
13442
13443 intel_init_dpio(dev);
13444
13445 intel_shared_dpll_init(dev);
13446
13447 /* Just disable it once at startup */
13448 i915_disable_vga(dev);
13449 intel_setup_outputs(dev);
13450
13451 /* Just in case the BIOS is doing something questionable. */
13452 intel_fbc_disable(dev);
13453
13454 drm_modeset_lock_all(dev);
13455 intel_modeset_setup_hw_state(dev, false);
13456 drm_modeset_unlock_all(dev);
13457
13458 for_each_intel_crtc(dev, crtc) {
13459 if (!crtc->active)
13460 continue;
13461
13462 /*
13463 * Note that reserving the BIOS fb up front prevents us
13464 * from stuffing other stolen allocations like the ring
13465 * on top. This prevents some ugliness at boot time, and
13466 * can even allow for smooth boot transitions if the BIOS
13467 * fb is large enough for the active pipe configuration.
13468 */
13469 if (dev_priv->display.get_initial_plane_config) {
13470 dev_priv->display.get_initial_plane_config(crtc,
13471 &crtc->plane_config);
13472 /*
13473 * If the fb is shared between multiple heads, we'll
13474 * just get the first one.
13475 */
13476 intel_find_plane_obj(crtc, &crtc->plane_config);
13477 }
13478 }
13479 }
13480
13481 static void intel_enable_pipe_a(struct drm_device *dev)
13482 {
13483 struct intel_connector *connector;
13484 struct drm_connector *crt = NULL;
13485 struct intel_load_detect_pipe load_detect_temp;
13486 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
13487
13488 /* We can't just switch on the pipe A, we need to set things up with a
13489 * proper mode and output configuration. As a gross hack, enable pipe A
13490 * by enabling the load detect pipe once. */
13491 for_each_intel_connector(dev, connector) {
13492 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13493 crt = &connector->base;
13494 break;
13495 }
13496 }
13497
13498 if (!crt)
13499 return;
13500
13501 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13502 intel_release_load_detect_pipe(crt, &load_detect_temp);
13503 }
13504
13505 static bool
13506 intel_check_plane_mapping(struct intel_crtc *crtc)
13507 {
13508 struct drm_device *dev = crtc->base.dev;
13509 struct drm_i915_private *dev_priv = dev->dev_private;
13510 u32 reg, val;
13511
13512 if (INTEL_INFO(dev)->num_pipes == 1)
13513 return true;
13514
13515 reg = DSPCNTR(!crtc->plane);
13516 val = I915_READ(reg);
13517
13518 if ((val & DISPLAY_PLANE_ENABLE) &&
13519 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13520 return false;
13521
13522 return true;
13523 }
13524
13525 static void intel_sanitize_crtc(struct intel_crtc *crtc)
13526 {
13527 struct drm_device *dev = crtc->base.dev;
13528 struct drm_i915_private *dev_priv = dev->dev_private;
13529 u32 reg;
13530
13531 /* Clear any frame start delays used for debugging left by the BIOS */
13532 reg = PIPECONF(crtc->config->cpu_transcoder);
13533 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13534
13535 /* restore vblank interrupts to correct state */
13536 drm_crtc_vblank_reset(&crtc->base);
13537 if (crtc->active) {
13538 update_scanline_offset(crtc);
13539 drm_crtc_vblank_on(&crtc->base);
13540 }
13541
13542 /* We need to sanitize the plane -> pipe mapping first because this will
13543 * disable the crtc (and hence change the state) if it is wrong. Note
13544 * that gen4+ has a fixed plane -> pipe mapping. */
13545 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13546 struct intel_connector *connector;
13547 bool plane;
13548
13549 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13550 crtc->base.base.id);
13551
13552 /* Pipe has the wrong plane attached and the plane is active.
13553 * Temporarily change the plane mapping and disable everything
13554 * ... */
13555 plane = crtc->plane;
13556 crtc->plane = !plane;
13557 crtc->primary_enabled = true;
13558 dev_priv->display.crtc_disable(&crtc->base);
13559 crtc->plane = plane;
13560
13561 /* ... and break all links. */
13562 for_each_intel_connector(dev, connector) {
13563 if (connector->encoder->base.crtc != &crtc->base)
13564 continue;
13565
13566 connector->base.dpms = DRM_MODE_DPMS_OFF;
13567 connector->base.encoder = NULL;
13568 }
13569 /* multiple connectors may have the same encoder:
13570 * handle them and break crtc link separately */
13571 for_each_intel_connector(dev, connector)
13572 if (connector->encoder->base.crtc == &crtc->base) {
13573 connector->encoder->base.crtc = NULL;
13574 connector->encoder->connectors_active = false;
13575 }
13576
13577 WARN_ON(crtc->active);
13578 crtc->base.state->enable = false;
13579 crtc->base.enabled = false;
13580 }
13581
13582 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13583 crtc->pipe == PIPE_A && !crtc->active) {
13584 /* BIOS forgot to enable pipe A, this mostly happens after
13585 * resume. Force-enable the pipe to fix this, the update_dpms
13586 * call below we restore the pipe to the right state, but leave
13587 * the required bits on. */
13588 intel_enable_pipe_a(dev);
13589 }
13590
13591 /* Adjust the state of the output pipe according to whether we
13592 * have active connectors/encoders. */
13593 intel_crtc_update_dpms(&crtc->base);
13594
13595 if (crtc->active != crtc->base.state->enable) {
13596 struct intel_encoder *encoder;
13597
13598 /* This can happen either due to bugs in the get_hw_state
13599 * functions or because the pipe is force-enabled due to the
13600 * pipe A quirk. */
13601 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13602 crtc->base.base.id,
13603 crtc->base.state->enable ? "enabled" : "disabled",
13604 crtc->active ? "enabled" : "disabled");
13605
13606 crtc->base.state->enable = crtc->active;
13607 crtc->base.enabled = crtc->active;
13608
13609 /* Because we only establish the connector -> encoder ->
13610 * crtc links if something is active, this means the
13611 * crtc is now deactivated. Break the links. connector
13612 * -> encoder links are only establish when things are
13613 * actually up, hence no need to break them. */
13614 WARN_ON(crtc->active);
13615
13616 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13617 WARN_ON(encoder->connectors_active);
13618 encoder->base.crtc = NULL;
13619 }
13620 }
13621
13622 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13623 /*
13624 * We start out with underrun reporting disabled to avoid races.
13625 * For correct bookkeeping mark this on active crtcs.
13626 *
13627 * Also on gmch platforms we dont have any hardware bits to
13628 * disable the underrun reporting. Which means we need to start
13629 * out with underrun reporting disabled also on inactive pipes,
13630 * since otherwise we'll complain about the garbage we read when
13631 * e.g. coming up after runtime pm.
13632 *
13633 * No protection against concurrent access is required - at
13634 * worst a fifo underrun happens which also sets this to false.
13635 */
13636 crtc->cpu_fifo_underrun_disabled = true;
13637 crtc->pch_fifo_underrun_disabled = true;
13638 }
13639 }
13640
13641 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13642 {
13643 struct intel_connector *connector;
13644 struct drm_device *dev = encoder->base.dev;
13645
13646 /* We need to check both for a crtc link (meaning that the
13647 * encoder is active and trying to read from a pipe) and the
13648 * pipe itself being active. */
13649 bool has_active_crtc = encoder->base.crtc &&
13650 to_intel_crtc(encoder->base.crtc)->active;
13651
13652 if (encoder->connectors_active && !has_active_crtc) {
13653 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13654 encoder->base.base.id,
13655 encoder->base.name);
13656
13657 /* Connector is active, but has no active pipe. This is
13658 * fallout from our resume register restoring. Disable
13659 * the encoder manually again. */
13660 if (encoder->base.crtc) {
13661 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13662 encoder->base.base.id,
13663 encoder->base.name);
13664 encoder->disable(encoder);
13665 if (encoder->post_disable)
13666 encoder->post_disable(encoder);
13667 }
13668 encoder->base.crtc = NULL;
13669 encoder->connectors_active = false;
13670
13671 /* Inconsistent output/port/pipe state happens presumably due to
13672 * a bug in one of the get_hw_state functions. Or someplace else
13673 * in our code, like the register restore mess on resume. Clamp
13674 * things to off as a safer default. */
13675 for_each_intel_connector(dev, connector) {
13676 if (connector->encoder != encoder)
13677 continue;
13678 connector->base.dpms = DRM_MODE_DPMS_OFF;
13679 connector->base.encoder = NULL;
13680 }
13681 }
13682 /* Enabled encoders without active connectors will be fixed in
13683 * the crtc fixup. */
13684 }
13685
13686 void i915_redisable_vga_power_on(struct drm_device *dev)
13687 {
13688 struct drm_i915_private *dev_priv = dev->dev_private;
13689 u32 vga_reg = i915_vgacntrl_reg(dev);
13690
13691 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13692 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13693 i915_disable_vga(dev);
13694 }
13695 }
13696
13697 void i915_redisable_vga(struct drm_device *dev)
13698 {
13699 struct drm_i915_private *dev_priv = dev->dev_private;
13700
13701 /* This function can be called both from intel_modeset_setup_hw_state or
13702 * at a very early point in our resume sequence, where the power well
13703 * structures are not yet restored. Since this function is at a very
13704 * paranoid "someone might have enabled VGA while we were not looking"
13705 * level, just check if the power well is enabled instead of trying to
13706 * follow the "don't touch the power well if we don't need it" policy
13707 * the rest of the driver uses. */
13708 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13709 return;
13710
13711 i915_redisable_vga_power_on(dev);
13712 }
13713
13714 static bool primary_get_hw_state(struct intel_crtc *crtc)
13715 {
13716 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13717
13718 if (!crtc->active)
13719 return false;
13720
13721 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13722 }
13723
13724 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13725 {
13726 struct drm_i915_private *dev_priv = dev->dev_private;
13727 enum pipe pipe;
13728 struct intel_crtc *crtc;
13729 struct intel_encoder *encoder;
13730 struct intel_connector *connector;
13731 int i;
13732
13733 for_each_intel_crtc(dev, crtc) {
13734 memset(crtc->config, 0, sizeof(*crtc->config));
13735
13736 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13737
13738 crtc->active = dev_priv->display.get_pipe_config(crtc,
13739 crtc->config);
13740
13741 crtc->base.state->enable = crtc->active;
13742 crtc->base.enabled = crtc->active;
13743 crtc->primary_enabled = primary_get_hw_state(crtc);
13744
13745 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13746 crtc->base.base.id,
13747 crtc->active ? "enabled" : "disabled");
13748 }
13749
13750 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13751 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13752
13753 pll->on = pll->get_hw_state(dev_priv, pll,
13754 &pll->config.hw_state);
13755 pll->active = 0;
13756 pll->config.crtc_mask = 0;
13757 for_each_intel_crtc(dev, crtc) {
13758 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13759 pll->active++;
13760 pll->config.crtc_mask |= 1 << crtc->pipe;
13761 }
13762 }
13763
13764 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13765 pll->name, pll->config.crtc_mask, pll->on);
13766
13767 if (pll->config.crtc_mask)
13768 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13769 }
13770
13771 for_each_intel_encoder(dev, encoder) {
13772 pipe = 0;
13773
13774 if (encoder->get_hw_state(encoder, &pipe)) {
13775 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13776 encoder->base.crtc = &crtc->base;
13777 encoder->get_config(encoder, crtc->config);
13778 } else {
13779 encoder->base.crtc = NULL;
13780 }
13781
13782 encoder->connectors_active = false;
13783 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13784 encoder->base.base.id,
13785 encoder->base.name,
13786 encoder->base.crtc ? "enabled" : "disabled",
13787 pipe_name(pipe));
13788 }
13789
13790 for_each_intel_connector(dev, connector) {
13791 if (connector->get_hw_state(connector)) {
13792 connector->base.dpms = DRM_MODE_DPMS_ON;
13793 connector->encoder->connectors_active = true;
13794 connector->base.encoder = &connector->encoder->base;
13795 } else {
13796 connector->base.dpms = DRM_MODE_DPMS_OFF;
13797 connector->base.encoder = NULL;
13798 }
13799 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13800 connector->base.base.id,
13801 connector->base.name,
13802 connector->base.encoder ? "enabled" : "disabled");
13803 }
13804 }
13805
13806 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13807 * and i915 state tracking structures. */
13808 void intel_modeset_setup_hw_state(struct drm_device *dev,
13809 bool force_restore)
13810 {
13811 struct drm_i915_private *dev_priv = dev->dev_private;
13812 enum pipe pipe;
13813 struct intel_crtc *crtc;
13814 struct intel_encoder *encoder;
13815 int i;
13816
13817 intel_modeset_readout_hw_state(dev);
13818
13819 /*
13820 * Now that we have the config, copy it to each CRTC struct
13821 * Note that this could go away if we move to using crtc_config
13822 * checking everywhere.
13823 */
13824 for_each_intel_crtc(dev, crtc) {
13825 if (crtc->active && i915.fastboot) {
13826 intel_mode_from_pipe_config(&crtc->base.mode,
13827 crtc->config);
13828 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13829 crtc->base.base.id);
13830 drm_mode_debug_printmodeline(&crtc->base.mode);
13831 }
13832 }
13833
13834 /* HW state is read out, now we need to sanitize this mess. */
13835 for_each_intel_encoder(dev, encoder) {
13836 intel_sanitize_encoder(encoder);
13837 }
13838
13839 for_each_pipe(dev_priv, pipe) {
13840 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13841 intel_sanitize_crtc(crtc);
13842 intel_dump_pipe_config(crtc, crtc->config,
13843 "[setup_hw_state]");
13844 }
13845
13846 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13847 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13848
13849 if (!pll->on || pll->active)
13850 continue;
13851
13852 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13853
13854 pll->disable(dev_priv, pll);
13855 pll->on = false;
13856 }
13857
13858 if (IS_GEN9(dev))
13859 skl_wm_get_hw_state(dev);
13860 else if (HAS_PCH_SPLIT(dev))
13861 ilk_wm_get_hw_state(dev);
13862
13863 if (force_restore) {
13864 i915_redisable_vga(dev);
13865
13866 /*
13867 * We need to use raw interfaces for restoring state to avoid
13868 * checking (bogus) intermediate states.
13869 */
13870 for_each_pipe(dev_priv, pipe) {
13871 struct drm_crtc *crtc =
13872 dev_priv->pipe_to_crtc_mapping[pipe];
13873
13874 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13875 crtc->primary->fb);
13876 }
13877 } else {
13878 intel_modeset_update_staged_output_state(dev);
13879 }
13880
13881 intel_modeset_check_state(dev);
13882 }
13883
13884 void intel_modeset_gem_init(struct drm_device *dev)
13885 {
13886 struct drm_i915_private *dev_priv = dev->dev_private;
13887 struct drm_crtc *c;
13888 struct drm_i915_gem_object *obj;
13889
13890 mutex_lock(&dev->struct_mutex);
13891 intel_init_gt_powersave(dev);
13892 mutex_unlock(&dev->struct_mutex);
13893
13894 /*
13895 * There may be no VBT; and if the BIOS enabled SSC we can
13896 * just keep using it to avoid unnecessary flicker. Whereas if the
13897 * BIOS isn't using it, don't assume it will work even if the VBT
13898 * indicates as much.
13899 */
13900 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13901 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
13902 DREF_SSC1_ENABLE);
13903
13904 intel_modeset_init_hw(dev);
13905
13906 intel_setup_overlay(dev);
13907
13908 /*
13909 * Make sure any fbs we allocated at startup are properly
13910 * pinned & fenced. When we do the allocation it's too early
13911 * for this.
13912 */
13913 mutex_lock(&dev->struct_mutex);
13914 for_each_crtc(dev, c) {
13915 obj = intel_fb_obj(c->primary->fb);
13916 if (obj == NULL)
13917 continue;
13918
13919 if (intel_pin_and_fence_fb_obj(c->primary,
13920 c->primary->fb,
13921 NULL)) {
13922 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13923 to_intel_crtc(c)->pipe);
13924 drm_framebuffer_unreference(c->primary->fb);
13925 c->primary->fb = NULL;
13926 update_state_fb(c->primary);
13927 }
13928 }
13929 mutex_unlock(&dev->struct_mutex);
13930
13931 intel_backlight_register(dev);
13932 }
13933
13934 void intel_connector_unregister(struct intel_connector *intel_connector)
13935 {
13936 struct drm_connector *connector = &intel_connector->base;
13937
13938 intel_panel_destroy_backlight(connector);
13939 drm_connector_unregister(connector);
13940 }
13941
13942 void intel_modeset_cleanup(struct drm_device *dev)
13943 {
13944 struct drm_i915_private *dev_priv = dev->dev_private;
13945 struct drm_connector *connector;
13946
13947 intel_disable_gt_powersave(dev);
13948
13949 intel_backlight_unregister(dev);
13950
13951 /*
13952 * Interrupts and polling as the first thing to avoid creating havoc.
13953 * Too much stuff here (turning of connectors, ...) would
13954 * experience fancy races otherwise.
13955 */
13956 intel_irq_uninstall(dev_priv);
13957
13958 /*
13959 * Due to the hpd irq storm handling the hotplug work can re-arm the
13960 * poll handlers. Hence disable polling after hpd handling is shut down.
13961 */
13962 drm_kms_helper_poll_fini(dev);
13963
13964 mutex_lock(&dev->struct_mutex);
13965
13966 intel_unregister_dsm_handler();
13967
13968 intel_fbc_disable(dev);
13969
13970 mutex_unlock(&dev->struct_mutex);
13971
13972 /* flush any delayed tasks or pending work */
13973 flush_scheduled_work();
13974
13975 /* destroy the backlight and sysfs files before encoders/connectors */
13976 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13977 struct intel_connector *intel_connector;
13978
13979 intel_connector = to_intel_connector(connector);
13980 intel_connector->unregister(intel_connector);
13981 }
13982
13983 drm_mode_config_cleanup(dev);
13984
13985 intel_cleanup_overlay(dev);
13986
13987 mutex_lock(&dev->struct_mutex);
13988 intel_cleanup_gt_powersave(dev);
13989 mutex_unlock(&dev->struct_mutex);
13990 }
13991
13992 /*
13993 * Return which encoder is currently attached for connector.
13994 */
13995 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13996 {
13997 return &intel_attached_encoder(connector)->base;
13998 }
13999
14000 void intel_connector_attach_encoder(struct intel_connector *connector,
14001 struct intel_encoder *encoder)
14002 {
14003 connector->encoder = encoder;
14004 drm_mode_connector_attach_encoder(&connector->base,
14005 &encoder->base);
14006 }
14007
14008 /*
14009 * set vga decode state - true == enable VGA decode
14010 */
14011 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14012 {
14013 struct drm_i915_private *dev_priv = dev->dev_private;
14014 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
14015 u16 gmch_ctrl;
14016
14017 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14018 DRM_ERROR("failed to read control word\n");
14019 return -EIO;
14020 }
14021
14022 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14023 return 0;
14024
14025 if (state)
14026 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14027 else
14028 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
14029
14030 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14031 DRM_ERROR("failed to write control word\n");
14032 return -EIO;
14033 }
14034
14035 return 0;
14036 }
14037
14038 struct intel_display_error_state {
14039
14040 u32 power_well_driver;
14041
14042 int num_transcoders;
14043
14044 struct intel_cursor_error_state {
14045 u32 control;
14046 u32 position;
14047 u32 base;
14048 u32 size;
14049 } cursor[I915_MAX_PIPES];
14050
14051 struct intel_pipe_error_state {
14052 bool power_domain_on;
14053 u32 source;
14054 u32 stat;
14055 } pipe[I915_MAX_PIPES];
14056
14057 struct intel_plane_error_state {
14058 u32 control;
14059 u32 stride;
14060 u32 size;
14061 u32 pos;
14062 u32 addr;
14063 u32 surface;
14064 u32 tile_offset;
14065 } plane[I915_MAX_PIPES];
14066
14067 struct intel_transcoder_error_state {
14068 bool power_domain_on;
14069 enum transcoder cpu_transcoder;
14070
14071 u32 conf;
14072
14073 u32 htotal;
14074 u32 hblank;
14075 u32 hsync;
14076 u32 vtotal;
14077 u32 vblank;
14078 u32 vsync;
14079 } transcoder[4];
14080 };
14081
14082 struct intel_display_error_state *
14083 intel_display_capture_error_state(struct drm_device *dev)
14084 {
14085 struct drm_i915_private *dev_priv = dev->dev_private;
14086 struct intel_display_error_state *error;
14087 int transcoders[] = {
14088 TRANSCODER_A,
14089 TRANSCODER_B,
14090 TRANSCODER_C,
14091 TRANSCODER_EDP,
14092 };
14093 int i;
14094
14095 if (INTEL_INFO(dev)->num_pipes == 0)
14096 return NULL;
14097
14098 error = kzalloc(sizeof(*error), GFP_ATOMIC);
14099 if (error == NULL)
14100 return NULL;
14101
14102 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14103 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14104
14105 for_each_pipe(dev_priv, i) {
14106 error->pipe[i].power_domain_on =
14107 __intel_display_power_is_enabled(dev_priv,
14108 POWER_DOMAIN_PIPE(i));
14109 if (!error->pipe[i].power_domain_on)
14110 continue;
14111
14112 error->cursor[i].control = I915_READ(CURCNTR(i));
14113 error->cursor[i].position = I915_READ(CURPOS(i));
14114 error->cursor[i].base = I915_READ(CURBASE(i));
14115
14116 error->plane[i].control = I915_READ(DSPCNTR(i));
14117 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
14118 if (INTEL_INFO(dev)->gen <= 3) {
14119 error->plane[i].size = I915_READ(DSPSIZE(i));
14120 error->plane[i].pos = I915_READ(DSPPOS(i));
14121 }
14122 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14123 error->plane[i].addr = I915_READ(DSPADDR(i));
14124 if (INTEL_INFO(dev)->gen >= 4) {
14125 error->plane[i].surface = I915_READ(DSPSURF(i));
14126 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14127 }
14128
14129 error->pipe[i].source = I915_READ(PIPESRC(i));
14130
14131 if (HAS_GMCH_DISPLAY(dev))
14132 error->pipe[i].stat = I915_READ(PIPESTAT(i));
14133 }
14134
14135 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14136 if (HAS_DDI(dev_priv->dev))
14137 error->num_transcoders++; /* Account for eDP. */
14138
14139 for (i = 0; i < error->num_transcoders; i++) {
14140 enum transcoder cpu_transcoder = transcoders[i];
14141
14142 error->transcoder[i].power_domain_on =
14143 __intel_display_power_is_enabled(dev_priv,
14144 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
14145 if (!error->transcoder[i].power_domain_on)
14146 continue;
14147
14148 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14149
14150 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14151 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14152 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14153 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14154 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14155 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14156 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14157 }
14158
14159 return error;
14160 }
14161
14162 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14163
14164 void
14165 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
14166 struct drm_device *dev,
14167 struct intel_display_error_state *error)
14168 {
14169 struct drm_i915_private *dev_priv = dev->dev_private;
14170 int i;
14171
14172 if (!error)
14173 return;
14174
14175 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
14176 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
14177 err_printf(m, "PWR_WELL_CTL2: %08x\n",
14178 error->power_well_driver);
14179 for_each_pipe(dev_priv, i) {
14180 err_printf(m, "Pipe [%d]:\n", i);
14181 err_printf(m, " Power: %s\n",
14182 error->pipe[i].power_domain_on ? "on" : "off");
14183 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
14184 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
14185
14186 err_printf(m, "Plane [%d]:\n", i);
14187 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14188 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
14189 if (INTEL_INFO(dev)->gen <= 3) {
14190 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14191 err_printf(m, " POS: %08x\n", error->plane[i].pos);
14192 }
14193 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14194 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
14195 if (INTEL_INFO(dev)->gen >= 4) {
14196 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14197 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
14198 }
14199
14200 err_printf(m, "Cursor [%d]:\n", i);
14201 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14202 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14203 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
14204 }
14205
14206 for (i = 0; i < error->num_transcoders; i++) {
14207 err_printf(m, "CPU transcoder: %c\n",
14208 transcoder_name(error->transcoder[i].cpu_transcoder));
14209 err_printf(m, " Power: %s\n",
14210 error->transcoder[i].power_domain_on ? "on" : "off");
14211 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14212 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14213 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14214 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14215 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14216 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14217 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14218 }
14219 }
14220
14221 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14222 {
14223 struct intel_crtc *crtc;
14224
14225 for_each_intel_crtc(dev, crtc) {
14226 struct intel_unpin_work *work;
14227
14228 spin_lock_irq(&dev->event_lock);
14229
14230 work = crtc->unpin_work;
14231
14232 if (work && work->event &&
14233 work->event->base.file_priv == file) {
14234 kfree(work->event);
14235 work->event = NULL;
14236 }
14237
14238 spin_unlock_irq(&dev->event_lock);
14239 }
14240 }
Linux kernel - Deliverables
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