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drm/i915: call intel_tile_height with correct parameter
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47
48 /* Primary plane formats supported by all gen */
49 #define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55 /* Primary plane formats for gen <= 3 */
56 static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60 };
61
62 /* Primary plane formats for gen >= 4 */
63 static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71 };
72
73 /* Cursor formats */
74 static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76 };
77
78 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79
80 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_state *pipe_config);
82 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_state *pipe_config);
84
85 static int intel_set_mode(struct drm_crtc *crtc,
86 struct drm_atomic_state *state);
87 static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
91 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
93 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
96 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
97 static void haswell_set_pipeconf(struct drm_crtc *crtc);
98 static void intel_set_pipe_csc(struct drm_crtc *crtc);
99 static void vlv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_state *pipe_config);
101 static void chv_prepare_pll(struct intel_crtc *crtc,
102 const struct intel_crtc_state *pipe_config);
103 static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104 static void intel_finish_crtc_commit(struct drm_crtc *crtc);
105 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
106 struct intel_crtc_state *crtc_state);
107 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
108 int num_connectors);
109 static void intel_crtc_enable_planes(struct drm_crtc *crtc);
110 static void intel_crtc_disable_planes(struct drm_crtc *crtc);
111
112 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
113 {
114 if (!connector->mst_port)
115 return connector->encoder;
116 else
117 return &connector->mst_port->mst_encoders[pipe]->base;
118 }
119
120 typedef struct {
121 int min, max;
122 } intel_range_t;
123
124 typedef struct {
125 int dot_limit;
126 int p2_slow, p2_fast;
127 } intel_p2_t;
128
129 typedef struct intel_limit intel_limit_t;
130 struct intel_limit {
131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
133 };
134
135 int
136 intel_pch_rawclk(struct drm_device *dev)
137 {
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143 }
144
145 static inline u32 /* units of 100MHz */
146 intel_fdi_link_freq(struct drm_device *dev)
147 {
148 if (IS_GEN5(dev)) {
149 struct drm_i915_private *dev_priv = dev->dev_private;
150 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
151 } else
152 return 27;
153 }
154
155 static const intel_limit_t intel_limits_i8xx_dac = {
156 .dot = { .min = 25000, .max = 350000 },
157 .vco = { .min = 908000, .max = 1512000 },
158 .n = { .min = 2, .max = 16 },
159 .m = { .min = 96, .max = 140 },
160 .m1 = { .min = 18, .max = 26 },
161 .m2 = { .min = 6, .max = 16 },
162 .p = { .min = 4, .max = 128 },
163 .p1 = { .min = 2, .max = 33 },
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 4, .p2_fast = 2 },
166 };
167
168 static const intel_limit_t intel_limits_i8xx_dvo = {
169 .dot = { .min = 25000, .max = 350000 },
170 .vco = { .min = 908000, .max = 1512000 },
171 .n = { .min = 2, .max = 16 },
172 .m = { .min = 96, .max = 140 },
173 .m1 = { .min = 18, .max = 26 },
174 .m2 = { .min = 6, .max = 16 },
175 .p = { .min = 4, .max = 128 },
176 .p1 = { .min = 2, .max = 33 },
177 .p2 = { .dot_limit = 165000,
178 .p2_slow = 4, .p2_fast = 4 },
179 };
180
181 static const intel_limit_t intel_limits_i8xx_lvds = {
182 .dot = { .min = 25000, .max = 350000 },
183 .vco = { .min = 908000, .max = 1512000 },
184 .n = { .min = 2, .max = 16 },
185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 1, .max = 6 },
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 14, .p2_fast = 7 },
192 };
193
194 static const intel_limit_t intel_limits_i9xx_sdvo = {
195 .dot = { .min = 20000, .max = 400000 },
196 .vco = { .min = 1400000, .max = 2800000 },
197 .n = { .min = 1, .max = 6 },
198 .m = { .min = 70, .max = 120 },
199 .m1 = { .min = 8, .max = 18 },
200 .m2 = { .min = 3, .max = 7 },
201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
205 };
206
207 static const intel_limit_t intel_limits_i9xx_lvds = {
208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1400000, .max = 2800000 },
210 .n = { .min = 1, .max = 6 },
211 .m = { .min = 70, .max = 120 },
212 .m1 = { .min = 8, .max = 18 },
213 .m2 = { .min = 3, .max = 7 },
214 .p = { .min = 7, .max = 98 },
215 .p1 = { .min = 1, .max = 8 },
216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 7 },
218 };
219
220
221 static const intel_limit_t intel_limits_g4x_sdvo = {
222 .dot = { .min = 25000, .max = 270000 },
223 .vco = { .min = 1750000, .max = 3500000},
224 .n = { .min = 1, .max = 4 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 10, .max = 30 },
229 .p1 = { .min = 1, .max = 3},
230 .p2 = { .dot_limit = 270000,
231 .p2_slow = 10,
232 .p2_fast = 10
233 },
234 };
235
236 static const intel_limit_t intel_limits_g4x_hdmi = {
237 .dot = { .min = 22000, .max = 400000 },
238 .vco = { .min = 1750000, .max = 3500000},
239 .n = { .min = 1, .max = 4 },
240 .m = { .min = 104, .max = 138 },
241 .m1 = { .min = 16, .max = 23 },
242 .m2 = { .min = 5, .max = 11 },
243 .p = { .min = 5, .max = 80 },
244 .p1 = { .min = 1, .max = 8},
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 10, .p2_fast = 5 },
247 };
248
249 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
250 .dot = { .min = 20000, .max = 115000 },
251 .vco = { .min = 1750000, .max = 3500000 },
252 .n = { .min = 1, .max = 3 },
253 .m = { .min = 104, .max = 138 },
254 .m1 = { .min = 17, .max = 23 },
255 .m2 = { .min = 5, .max = 11 },
256 .p = { .min = 28, .max = 112 },
257 .p1 = { .min = 2, .max = 8 },
258 .p2 = { .dot_limit = 0,
259 .p2_slow = 14, .p2_fast = 14
260 },
261 };
262
263 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
264 .dot = { .min = 80000, .max = 224000 },
265 .vco = { .min = 1750000, .max = 3500000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 104, .max = 138 },
268 .m1 = { .min = 17, .max = 23 },
269 .m2 = { .min = 5, .max = 11 },
270 .p = { .min = 14, .max = 42 },
271 .p1 = { .min = 2, .max = 6 },
272 .p2 = { .dot_limit = 0,
273 .p2_slow = 7, .p2_fast = 7
274 },
275 };
276
277 static const intel_limit_t intel_limits_pineview_sdvo = {
278 .dot = { .min = 20000, .max = 400000},
279 .vco = { .min = 1700000, .max = 3500000 },
280 /* Pineview's Ncounter is a ring counter */
281 .n = { .min = 3, .max = 6 },
282 .m = { .min = 2, .max = 256 },
283 /* Pineview only has one combined m divider, which we treat as m2. */
284 .m1 = { .min = 0, .max = 0 },
285 .m2 = { .min = 0, .max = 254 },
286 .p = { .min = 5, .max = 80 },
287 .p1 = { .min = 1, .max = 8 },
288 .p2 = { .dot_limit = 200000,
289 .p2_slow = 10, .p2_fast = 5 },
290 };
291
292 static const intel_limit_t intel_limits_pineview_lvds = {
293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1700000, .max = 3500000 },
295 .n = { .min = 3, .max = 6 },
296 .m = { .min = 2, .max = 256 },
297 .m1 = { .min = 0, .max = 0 },
298 .m2 = { .min = 0, .max = 254 },
299 .p = { .min = 7, .max = 112 },
300 .p1 = { .min = 1, .max = 8 },
301 .p2 = { .dot_limit = 112000,
302 .p2_slow = 14, .p2_fast = 14 },
303 };
304
305 /* Ironlake / Sandybridge
306 *
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
309 */
310 static const intel_limit_t intel_limits_ironlake_dac = {
311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 5 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 5, .max = 80 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 10, .p2_fast = 5 },
321 };
322
323 static const intel_limit_t intel_limits_ironlake_single_lvds = {
324 .dot = { .min = 25000, .max = 350000 },
325 .vco = { .min = 1760000, .max = 3510000 },
326 .n = { .min = 1, .max = 3 },
327 .m = { .min = 79, .max = 118 },
328 .m1 = { .min = 12, .max = 22 },
329 .m2 = { .min = 5, .max = 9 },
330 .p = { .min = 28, .max = 112 },
331 .p1 = { .min = 2, .max = 8 },
332 .p2 = { .dot_limit = 225000,
333 .p2_slow = 14, .p2_fast = 14 },
334 };
335
336 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 14, .max = 56 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 7, .p2_fast = 7 },
347 };
348
349 /* LVDS 100mhz refclk limits. */
350 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
351 .dot = { .min = 25000, .max = 350000 },
352 .vco = { .min = 1760000, .max = 3510000 },
353 .n = { .min = 1, .max = 2 },
354 .m = { .min = 79, .max = 126 },
355 .m1 = { .min = 12, .max = 22 },
356 .m2 = { .min = 5, .max = 9 },
357 .p = { .min = 28, .max = 112 },
358 .p1 = { .min = 2, .max = 8 },
359 .p2 = { .dot_limit = 225000,
360 .p2_slow = 14, .p2_fast = 14 },
361 };
362
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 };
375
376 static const intel_limit_t intel_limits_vlv = {
377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
384 .vco = { .min = 4000000, .max = 6000000 },
385 .n = { .min = 1, .max = 7 },
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p1 = { .min = 2, .max = 3 },
389 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
390 };
391
392 static const intel_limit_t intel_limits_chv = {
393 /*
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
398 */
399 .dot = { .min = 25000 * 5, .max = 540000 * 5},
400 .vco = { .min = 4800000, .max = 6480000 },
401 .n = { .min = 1, .max = 1 },
402 .m1 = { .min = 2, .max = 2 },
403 .m2 = { .min = 24 << 22, .max = 175 << 22 },
404 .p1 = { .min = 2, .max = 4 },
405 .p2 = { .p2_slow = 1, .p2_fast = 14 },
406 };
407
408 static const intel_limit_t intel_limits_bxt = {
409 /* FIXME: find real dot limits */
410 .dot = { .min = 0, .max = INT_MAX },
411 .vco = { .min = 4800000, .max = 6480000 },
412 .n = { .min = 1, .max = 1 },
413 .m1 = { .min = 2, .max = 2 },
414 /* FIXME: find real m2 limits */
415 .m2 = { .min = 2 << 22, .max = 255 << 22 },
416 .p1 = { .min = 2, .max = 4 },
417 .p2 = { .p2_slow = 1, .p2_fast = 20 },
418 };
419
420 static void vlv_clock(int refclk, intel_clock_t *clock)
421 {
422 clock->m = clock->m1 * clock->m2;
423 clock->p = clock->p1 * clock->p2;
424 if (WARN_ON(clock->n == 0 || clock->p == 0))
425 return;
426 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
427 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
428 }
429
430 /**
431 * Returns whether any output on the specified pipe is of the specified type
432 */
433 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
434 {
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
439 if (encoder->type == type)
440 return true;
441
442 return false;
443 }
444
445 /**
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
449 * encoder->crtc.
450 */
451 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
452 int type)
453 {
454 struct drm_atomic_state *state = crtc_state->base.state;
455 struct drm_connector *connector;
456 struct drm_connector_state *connector_state;
457 struct intel_encoder *encoder;
458 int i, num_connectors = 0;
459
460 for_each_connector_in_state(state, connector, connector_state, i) {
461 if (connector_state->crtc != crtc_state->base.crtc)
462 continue;
463
464 num_connectors++;
465
466 encoder = to_intel_encoder(connector_state->best_encoder);
467 if (encoder->type == type)
468 return true;
469 }
470
471 WARN_ON(num_connectors == 0);
472
473 return false;
474 }
475
476 static const intel_limit_t *
477 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
478 {
479 struct drm_device *dev = crtc_state->base.crtc->dev;
480 const intel_limit_t *limit;
481
482 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
483 if (intel_is_dual_link_lvds(dev)) {
484 if (refclk == 100000)
485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
489 if (refclk == 100000)
490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
494 } else
495 limit = &intel_limits_ironlake_dac;
496
497 return limit;
498 }
499
500 static const intel_limit_t *
501 intel_g4x_limit(struct intel_crtc_state *crtc_state)
502 {
503 struct drm_device *dev = crtc_state->base.crtc->dev;
504 const intel_limit_t *limit;
505
506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
507 if (intel_is_dual_link_lvds(dev))
508 limit = &intel_limits_g4x_dual_channel_lvds;
509 else
510 limit = &intel_limits_g4x_single_channel_lvds;
511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
512 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
513 limit = &intel_limits_g4x_hdmi;
514 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
515 limit = &intel_limits_g4x_sdvo;
516 } else /* The option is for other outputs */
517 limit = &intel_limits_i9xx_sdvo;
518
519 return limit;
520 }
521
522 static const intel_limit_t *
523 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
524 {
525 struct drm_device *dev = crtc_state->base.crtc->dev;
526 const intel_limit_t *limit;
527
528 if (IS_BROXTON(dev))
529 limit = &intel_limits_bxt;
530 else if (HAS_PCH_SPLIT(dev))
531 limit = intel_ironlake_limit(crtc_state, refclk);
532 else if (IS_G4X(dev)) {
533 limit = intel_g4x_limit(crtc_state);
534 } else if (IS_PINEVIEW(dev)) {
535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
536 limit = &intel_limits_pineview_lvds;
537 else
538 limit = &intel_limits_pineview_sdvo;
539 } else if (IS_CHERRYVIEW(dev)) {
540 limit = &intel_limits_chv;
541 } else if (IS_VALLEYVIEW(dev)) {
542 limit = &intel_limits_vlv;
543 } else if (!IS_GEN2(dev)) {
544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
545 limit = &intel_limits_i9xx_lvds;
546 else
547 limit = &intel_limits_i9xx_sdvo;
548 } else {
549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
550 limit = &intel_limits_i8xx_lvds;
551 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
552 limit = &intel_limits_i8xx_dvo;
553 else
554 limit = &intel_limits_i8xx_dac;
555 }
556 return limit;
557 }
558
559 /* m1 is reserved as 0 in Pineview, n is a ring counter */
560 static void pineview_clock(int refclk, intel_clock_t *clock)
561 {
562 clock->m = clock->m2 + 2;
563 clock->p = clock->p1 * clock->p2;
564 if (WARN_ON(clock->n == 0 || clock->p == 0))
565 return;
566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
568 }
569
570 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571 {
572 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
573 }
574
575 static void i9xx_clock(int refclk, intel_clock_t *clock)
576 {
577 clock->m = i9xx_dpll_compute_m(clock);
578 clock->p = clock->p1 * clock->p2;
579 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 return;
581 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
583 }
584
585 static void chv_clock(int refclk, intel_clock_t *clock)
586 {
587 clock->m = clock->m1 * clock->m2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return;
591 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->n << 22);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594 }
595
596 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
597 /**
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
600 */
601
602 static bool intel_PLL_is_valid(struct drm_device *dev,
603 const intel_limit_t *limit,
604 const intel_clock_t *clock)
605 {
606 if (clock->n < limit->n.min || limit->n.max < clock->n)
607 INTELPllInvalid("n out of range\n");
608 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
609 INTELPllInvalid("p1 out of range\n");
610 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
611 INTELPllInvalid("m2 out of range\n");
612 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
613 INTELPllInvalid("m1 out of range\n");
614
615 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
616 if (clock->m1 <= clock->m2)
617 INTELPllInvalid("m1 <= m2\n");
618
619 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
620 if (clock->p < limit->p.min || limit->p.max < clock->p)
621 INTELPllInvalid("p out of range\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid("m out of range\n");
624 }
625
626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
627 INTELPllInvalid("vco out of range\n");
628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
632 INTELPllInvalid("dot out of range\n");
633
634 return true;
635 }
636
637 static bool
638 i9xx_find_best_dpll(const intel_limit_t *limit,
639 struct intel_crtc_state *crtc_state,
640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
642 {
643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
644 struct drm_device *dev = crtc->base.dev;
645 intel_clock_t clock;
646 int err = target;
647
648 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
649 /*
650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
653 */
654 if (intel_is_dual_link_lvds(dev))
655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
665 memset(best_clock, 0, sizeof(*best_clock));
666
667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
671 if (clock.m2 >= clock.m1)
672 break;
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
677 int this_err;
678
679 i9xx_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
682 continue;
683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698 }
699
700 static bool
701 pnv_find_best_dpll(const intel_limit_t *limit,
702 struct intel_crtc_state *crtc_state,
703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
705 {
706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
707 struct drm_device *dev = crtc->base.dev;
708 intel_clock_t clock;
709 int err = target;
710
711 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
712 /*
713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
716 */
717 if (intel_is_dual_link_lvds(dev))
718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
728 memset(best_clock, 0, sizeof(*best_clock));
729
730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
738 int this_err;
739
740 pineview_clock(refclk, &clock);
741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
743 continue;
744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759 }
760
761 static bool
762 g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
766 {
767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
768 struct drm_device *dev = crtc->base.dev;
769 intel_clock_t clock;
770 int max_n;
771 bool found;
772 /* approximately equals target * 0.00585 */
773 int err_most = (target >> 8) + (target >> 9);
774 found = false;
775
776 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
777 if (intel_is_dual_link_lvds(dev))
778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
790 /* based on hardware requirement, prefer smaller n to precision */
791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
792 /* based on hardware requirement, prefere larger m1,m2 */
793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
801 i9xx_clock(refclk, &clock);
802 if (!intel_PLL_is_valid(dev, limit,
803 &clock))
804 continue;
805
806 this_err = abs(clock.dot - target);
807 if (this_err < err_most) {
808 *best_clock = clock;
809 err_most = this_err;
810 max_n = clock.n;
811 found = true;
812 }
813 }
814 }
815 }
816 }
817 return found;
818 }
819
820 /*
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
823 */
824 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
825 const intel_clock_t *calculated_clock,
826 const intel_clock_t *best_clock,
827 unsigned int best_error_ppm,
828 unsigned int *error_ppm)
829 {
830 /*
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
833 */
834 if (IS_CHERRYVIEW(dev)) {
835 *error_ppm = 0;
836
837 return calculated_clock->p > best_clock->p;
838 }
839
840 if (WARN_ON_ONCE(!target_freq))
841 return false;
842
843 *error_ppm = div_u64(1000000ULL *
844 abs(target_freq - calculated_clock->dot),
845 target_freq);
846 /*
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
850 */
851 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
852 *error_ppm = 0;
853
854 return true;
855 }
856
857 return *error_ppm + 10 < best_error_ppm;
858 }
859
860 static bool
861 vlv_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865 {
866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
867 struct drm_device *dev = crtc->base.dev;
868 intel_clock_t clock;
869 unsigned int bestppm = 1000000;
870 /* min update 19.2 MHz */
871 int max_n = min(limit->n.max, refclk / 19200);
872 bool found = false;
873
874 target *= 5; /* fast clock */
875
876 memset(best_clock, 0, sizeof(*best_clock));
877
878 /* based on hardware requirement, prefer smaller n to precision */
879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
880 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
881 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
882 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
883 clock.p = clock.p1 * clock.p2;
884 /* based on hardware requirement, prefer bigger m1,m2 values */
885 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
886 unsigned int ppm;
887
888 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
889 refclk * clock.m1);
890
891 vlv_clock(refclk, &clock);
892
893 if (!intel_PLL_is_valid(dev, limit,
894 &clock))
895 continue;
896
897 if (!vlv_PLL_is_optimal(dev, target,
898 &clock,
899 best_clock,
900 bestppm, &ppm))
901 continue;
902
903 *best_clock = clock;
904 bestppm = ppm;
905 found = true;
906 }
907 }
908 }
909 }
910
911 return found;
912 }
913
914 static bool
915 chv_find_best_dpll(const intel_limit_t *limit,
916 struct intel_crtc_state *crtc_state,
917 int target, int refclk, intel_clock_t *match_clock,
918 intel_clock_t *best_clock)
919 {
920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
921 struct drm_device *dev = crtc->base.dev;
922 unsigned int best_error_ppm;
923 intel_clock_t clock;
924 uint64_t m2;
925 int found = false;
926
927 memset(best_clock, 0, sizeof(*best_clock));
928 best_error_ppm = 1000000;
929
930 /*
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
934 */
935 clock.n = 1, clock.m1 = 2;
936 target *= 5; /* fast clock */
937
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast;
940 clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
942 unsigned int error_ppm;
943
944 clock.p = clock.p1 * clock.p2;
945
946 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
947 clock.n) << 22, refclk * clock.m1);
948
949 if (m2 > INT_MAX/clock.m1)
950 continue;
951
952 clock.m2 = m2;
953
954 chv_clock(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit, &clock))
957 continue;
958
959 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
960 best_error_ppm, &error_ppm))
961 continue;
962
963 *best_clock = clock;
964 best_error_ppm = error_ppm;
965 found = true;
966 }
967 }
968
969 return found;
970 }
971
972 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
973 intel_clock_t *best_clock)
974 {
975 int refclk = i9xx_get_refclk(crtc_state, 0);
976
977 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
978 target_clock, refclk, NULL, best_clock);
979 }
980
981 bool intel_crtc_active(struct drm_crtc *crtc)
982 {
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
987 *
988 * We can ditch the adjusted_mode.crtc_clock check as soon
989 * as Haswell has gained clock readout/fastboot support.
990 *
991 * We can ditch the crtc->primary->fb check as soon as we can
992 * properly reconstruct framebuffers.
993 *
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
996 * for atomic.
997 */
998 return intel_crtc->active && crtc->primary->state->fb &&
999 intel_crtc->config->base.adjusted_mode.crtc_clock;
1000 }
1001
1002 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003 enum pipe pipe)
1004 {
1005 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
1008 return intel_crtc->config->cpu_transcoder;
1009 }
1010
1011 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012 {
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 u32 reg = PIPEDSL(pipe);
1015 u32 line1, line2;
1016 u32 line_mask;
1017
1018 if (IS_GEN2(dev))
1019 line_mask = DSL_LINEMASK_GEN2;
1020 else
1021 line_mask = DSL_LINEMASK_GEN3;
1022
1023 line1 = I915_READ(reg) & line_mask;
1024 mdelay(5);
1025 line2 = I915_READ(reg) & line_mask;
1026
1027 return line1 == line2;
1028 }
1029
1030 /*
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
1032 * @crtc: crtc whose pipe to wait for
1033 *
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1037 *
1038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1040 *
1041 * Otherwise:
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
1044 *
1045 */
1046 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1047 {
1048 struct drm_device *dev = crtc->base.dev;
1049 struct drm_i915_private *dev_priv = dev->dev_private;
1050 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1051 enum pipe pipe = crtc->pipe;
1052
1053 if (INTEL_INFO(dev)->gen >= 4) {
1054 int reg = PIPECONF(cpu_transcoder);
1055
1056 /* Wait for the Pipe State to go off */
1057 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058 100))
1059 WARN(1, "pipe_off wait timed out\n");
1060 } else {
1061 /* Wait for the display line to settle */
1062 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1063 WARN(1, "pipe_off wait timed out\n");
1064 }
1065 }
1066
1067 /*
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1071 *
1072 * Returns true if @port is connected, false otherwise.
1073 */
1074 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075 struct intel_digital_port *port)
1076 {
1077 u32 bit;
1078
1079 if (HAS_PCH_IBX(dev_priv->dev)) {
1080 switch (port->port) {
1081 case PORT_B:
1082 bit = SDE_PORTB_HOTPLUG;
1083 break;
1084 case PORT_C:
1085 bit = SDE_PORTC_HOTPLUG;
1086 break;
1087 case PORT_D:
1088 bit = SDE_PORTD_HOTPLUG;
1089 break;
1090 default:
1091 return true;
1092 }
1093 } else {
1094 switch (port->port) {
1095 case PORT_B:
1096 bit = SDE_PORTB_HOTPLUG_CPT;
1097 break;
1098 case PORT_C:
1099 bit = SDE_PORTC_HOTPLUG_CPT;
1100 break;
1101 case PORT_D:
1102 bit = SDE_PORTD_HOTPLUG_CPT;
1103 break;
1104 default:
1105 return true;
1106 }
1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110 }
1111
1112 static const char *state_string(bool enabled)
1113 {
1114 return enabled ? "on" : "off";
1115 }
1116
1117 /* Only for pre-ILK configs */
1118 void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
1120 {
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
1128 I915_STATE_WARN(cur_state != state,
1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131 }
1132
1133 /* XXX: the dsi pll is shared between MIPI DSI ports */
1134 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135 {
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->dpio_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->dpio_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
1144 I915_STATE_WARN(cur_state != state,
1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147 }
1148 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
1151 struct intel_shared_dpll *
1152 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153 {
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
1156 if (crtc->config->shared_dpll < 0)
1157 return NULL;
1158
1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1160 }
1161
1162 /* For ILK+ */
1163 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
1166 {
1167 bool cur_state;
1168 struct intel_dpll_hw_state hw_state;
1169
1170 if (WARN (!pll,
1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
1172 return;
1173
1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1175 I915_STATE_WARN(cur_state != state,
1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
1178 }
1179
1180 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182 {
1183 int reg;
1184 u32 val;
1185 bool cur_state;
1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
1188
1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1192 val = I915_READ(reg);
1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
1199 I915_STATE_WARN(cur_state != state,
1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202 }
1203 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208 {
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
1216 I915_STATE_WARN(cur_state != state,
1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219 }
1220 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225 {
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1231 return;
1232
1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1234 if (HAS_DDI(dev_priv->dev))
1235 return;
1236
1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1240 }
1241
1242 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
1244 {
1245 int reg;
1246 u32 val;
1247 bool cur_state;
1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1252 I915_STATE_WARN(cur_state != state,
1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
1255 }
1256
1257 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
1259 {
1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
1264 bool locked = true;
1265
1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
1272 pp_reg = PCH_PP_CONTROL;
1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
1283 } else {
1284 pp_reg = PP_CONTROL;
1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1292 locked = false;
1293
1294 I915_STATE_WARN(panel_pipe == pipe && locked,
1295 "panel assertion failure, pipe %c regs locked\n",
1296 pipe_name(pipe));
1297 }
1298
1299 static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301 {
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
1305 if (IS_845G(dev) || IS_I865G(dev))
1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1307 else
1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1309
1310 I915_STATE_WARN(cur_state != state,
1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313 }
1314 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
1317 void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
1319 {
1320 int reg;
1321 u32 val;
1322 bool cur_state;
1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
1325
1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1329 state = true;
1330
1331 if (!intel_display_power_is_enabled(dev_priv,
1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
1340 I915_STATE_WARN(cur_state != state,
1341 "pipe %c assertion failure (expected %s, current %s)\n",
1342 pipe_name(pipe), state_string(state), state_string(cur_state));
1343 }
1344
1345 static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
1347 {
1348 int reg;
1349 u32 val;
1350 bool cur_state;
1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1355 I915_STATE_WARN(cur_state != state,
1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
1358 }
1359
1360 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
1363 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365 {
1366 struct drm_device *dev = dev_priv->dev;
1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
1378 return;
1379 }
1380
1381 /* Need to check both planes against the pipe */
1382 for_each_pipe(dev_priv, i) {
1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
1390 }
1391 }
1392
1393 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395 {
1396 struct drm_device *dev = dev_priv->dev;
1397 int reg, sprite;
1398 u32 val;
1399
1400 if (INTEL_INFO(dev)->gen >= 9) {
1401 for_each_sprite(dev_priv, pipe, sprite) {
1402 val = I915_READ(PLANE_CTL(pipe, sprite));
1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
1408 for_each_sprite(dev_priv, pipe, sprite) {
1409 reg = SPCNTR(pipe, sprite);
1410 val = I915_READ(reg);
1411 I915_STATE_WARN(val & SP_ENABLE,
1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1413 sprite_name(pipe, sprite), pipe_name(pipe));
1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
1417 val = I915_READ(reg);
1418 I915_STATE_WARN(val & SPRITE_ENABLE,
1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
1423 val = I915_READ(reg);
1424 I915_STATE_WARN(val & DVS_ENABLE,
1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1426 plane_name(pipe), pipe_name(pipe));
1427 }
1428 }
1429
1430 static void assert_vblank_disabled(struct drm_crtc *crtc)
1431 {
1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1433 drm_crtc_vblank_put(crtc);
1434 }
1435
1436 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1437 {
1438 u32 val;
1439 bool enabled;
1440
1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1442
1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1447 }
1448
1449 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
1451 {
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
1456 reg = PCH_TRANSCONF(pipe);
1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
1459 I915_STATE_WARN(enabled,
1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
1462 }
1463
1464 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
1466 {
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483 }
1484
1485 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487 {
1488 if ((val & SDVO_ENABLE) == 0)
1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1493 return false;
1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1497 } else {
1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1499 return false;
1500 }
1501 return true;
1502 }
1503
1504 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506 {
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518 }
1519
1520 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522 {
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533 }
1534
1535 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1536 enum pipe pipe, int reg, u32 port_sel)
1537 {
1538 u32 val = I915_READ(reg);
1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1541 reg, pipe_name(pipe));
1542
1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1544 && (val & DP_PIPEB_SELECT),
1545 "IBX PCH dp port still using transcoder B\n");
1546 }
1547
1548 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550 {
1551 u32 val = I915_READ(reg);
1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1554 reg, pipe_name(pipe));
1555
1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1557 && (val & SDVO_PIPE_B_SELECT),
1558 "IBX PCH hdmi port still using transcoder B\n");
1559 }
1560
1561 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563 {
1564 int reg;
1565 u32 val;
1566
1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
1575 pipe_name(pipe));
1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1581 pipe_name(pipe));
1582
1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1586 }
1587
1588 static void intel_init_dpio(struct drm_device *dev)
1589 {
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
1606 }
1607
1608 static void vlv_enable_pll(struct intel_crtc *crtc,
1609 const struct intel_crtc_state *pipe_config)
1610 {
1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
1615
1616 assert_pipe_disabled(dev_priv, crtc->pipe);
1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
1622 if (IS_MOBILE(dev_priv->dev))
1623 assert_panel_unlocked(dev_priv, crtc->pipe);
1624
1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1633 POSTING_READ(DPLL_MD(crtc->pipe));
1634
1635 /* We do this three times for luck */
1636 I915_WRITE(reg, dpll);
1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
1639 I915_WRITE(reg, dpll);
1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
1642 I915_WRITE(reg, dpll);
1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645 }
1646
1647 static void chv_enable_pll(struct intel_crtc *crtc,
1648 const struct intel_crtc_state *pipe_config)
1649 {
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->dpio_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 /*
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669 */
1670 udelay(1);
1671
1672 /* Enable PLL */
1673 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1674
1675 /* Check PLL is locked */
1676 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1677 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
1679 /* not sure when this should be written */
1680 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1681 POSTING_READ(DPLL_MD(pipe));
1682
1683 mutex_unlock(&dev_priv->dpio_lock);
1684 }
1685
1686 static int intel_num_dvo_pipes(struct drm_device *dev)
1687 {
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->active &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1694
1695 return count;
1696 }
1697
1698 static void i9xx_enable_pll(struct intel_crtc *crtc)
1699 {
1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
1704
1705 assert_pipe_disabled(dev_priv, crtc->pipe);
1706
1707 /* No really, not for ILK+ */
1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1709
1710 /* PLL is protected by panel, make sure we can write it */
1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
1713
1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
1726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
1733 crtc->config->dpll_hw_state.dpll_md);
1734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
1742
1743 /* We do this three times for luck */
1744 I915_WRITE(reg, dpll);
1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
1747 I915_WRITE(reg, dpll);
1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
1750 I915_WRITE(reg, dpll);
1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753 }
1754
1755 /**
1756 * i9xx_disable_pll - disable a PLL
1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
1764 static void i9xx_disable_pll(struct intel_crtc *crtc)
1765 {
1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1773 intel_num_dvo_pipes(dev) == 1) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
1788 I915_WRITE(DPLL(pipe), 0);
1789 POSTING_READ(DPLL(pipe));
1790 }
1791
1792 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793 {
1794 u32 val = 0;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
1799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
1803 if (pipe == PIPE_B)
1804 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1805 I915_WRITE(DPLL(pipe), val);
1806 POSTING_READ(DPLL(pipe));
1807
1808 }
1809
1810 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811 {
1812 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1813 u32 val;
1814
1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
1817
1818 /* Set PLL en = 0 */
1819 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
1824
1825 mutex_lock(&dev_priv->dpio_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
1832 /* disable left/right clock distribution */
1833 if (pipe != PIPE_B) {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 } else {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841 }
1842
1843 mutex_unlock(&dev_priv->dpio_lock);
1844 }
1845
1846 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1847 struct intel_digital_port *dport,
1848 unsigned int expected_mask)
1849 {
1850 u32 port_mask;
1851 int dpll_reg;
1852
1853 switch (dport->port) {
1854 case PORT_B:
1855 port_mask = DPLL_PORTB_READY_MASK;
1856 dpll_reg = DPLL(0);
1857 break;
1858 case PORT_C:
1859 port_mask = DPLL_PORTC_READY_MASK;
1860 dpll_reg = DPLL(0);
1861 expected_mask <<= 4;
1862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
1866 break;
1867 default:
1868 BUG();
1869 }
1870
1871 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1872 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1873 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1874 }
1875
1876 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877 {
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
1882 if (WARN_ON(pll == NULL))
1883 return;
1884
1885 WARN_ON(!pll->config.crtc_mask);
1886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893 }
1894
1895 /**
1896 * intel_enable_shared_dpll - enable PCH PLL
1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
1903 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1904 {
1905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
1907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1908
1909 if (WARN_ON(pll == NULL))
1910 return;
1911
1912 if (WARN_ON(pll->config.crtc_mask == 0))
1913 return;
1914
1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1916 pll->name, pll->active, pll->on,
1917 crtc->base.base.id);
1918
1919 if (pll->active++) {
1920 WARN_ON(!pll->on);
1921 assert_shared_dpll_enabled(dev_priv, pll);
1922 return;
1923 }
1924 WARN_ON(pll->on);
1925
1926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
1928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1929 pll->enable(dev_priv, pll);
1930 pll->on = true;
1931 }
1932
1933 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1934 {
1935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
1937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1938
1939 /* PCH only available on ILK+ */
1940 BUG_ON(INTEL_INFO(dev)->gen < 5);
1941 if (WARN_ON(pll == NULL))
1942 return;
1943
1944 if (WARN_ON(pll->config.crtc_mask == 0))
1945 return;
1946
1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
1949 crtc->base.base.id);
1950
1951 if (WARN_ON(pll->active == 0)) {
1952 assert_shared_dpll_disabled(dev_priv, pll);
1953 return;
1954 }
1955
1956 assert_shared_dpll_enabled(dev_priv, pll);
1957 WARN_ON(!pll->on);
1958 if (--pll->active)
1959 return;
1960
1961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1962 pll->disable(dev_priv, pll);
1963 pll->on = false;
1964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1966 }
1967
1968 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
1970 {
1971 struct drm_device *dev = dev_priv->dev;
1972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1974 uint32_t reg, val, pipeconf_val;
1975
1976 /* PCH only available on ILK+ */
1977 BUG_ON(!HAS_PCH_SPLIT(dev));
1978
1979 /* Make sure PCH DPLL is enabled */
1980 assert_shared_dpll_enabled(dev_priv,
1981 intel_crtc_to_shared_dpll(intel_crtc));
1982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
1987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
1994 }
1995
1996 reg = PCH_TRANSCONF(pipe);
1997 val = I915_READ(reg);
1998 pipeconf_val = I915_READ(PIPECONF(pipe));
1999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
2005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
2007 }
2008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2011 if (HAS_PCH_IBX(dev_priv->dev) &&
2012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
2019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2022 }
2023
2024 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2025 enum transcoder cpu_transcoder)
2026 {
2027 u32 val, pipeconf_val;
2028
2029 /* PCH only available on ILK+ */
2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2031
2032 /* FDI must be feeding us bits for PCH ports */
2033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2035
2036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
2038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
2041 val = TRANS_ENABLE;
2042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2043
2044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
2046 val |= TRANS_INTERLACED;
2047 else
2048 val |= TRANS_PROGRESSIVE;
2049
2050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2052 DRM_ERROR("Failed to enable PCH transcoder\n");
2053 }
2054
2055 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
2057 {
2058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
2060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
2068 reg = PCH_TRANSCONF(pipe);
2069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
2083 }
2084
2085 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2086 {
2087 u32 val;
2088
2089 val = I915_READ(LPT_TRANSCONF);
2090 val &= ~TRANS_ENABLE;
2091 I915_WRITE(LPT_TRANSCONF, val);
2092 /* wait for PCH transcoder off, transcoder state */
2093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2094 DRM_ERROR("Failed to disable PCH transcoder\n");
2095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
2098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2099 I915_WRITE(_TRANSA_CHICKEN2, val);
2100 }
2101
2102 /**
2103 * intel_enable_pipe - enable a pipe, asserting requirements
2104 * @crtc: crtc responsible for the pipe
2105 *
2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2108 */
2109 static void intel_enable_pipe(struct intel_crtc *crtc)
2110 {
2111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
2114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
2116 enum pipe pch_transcoder;
2117 int reg;
2118 u32 val;
2119
2120 assert_planes_disabled(dev_priv, pipe);
2121 assert_cursor_disabled(dev_priv, pipe);
2122 assert_sprites_disabled(dev_priv, pipe);
2123
2124 if (HAS_PCH_LPT(dev_priv->dev))
2125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
2129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
2134 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
2139 else {
2140 if (crtc->config->has_pch_encoder) {
2141 /* if driving the PCH, we need FDI enabled */
2142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
2145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
2148
2149 reg = PIPECONF(cpu_transcoder);
2150 val = I915_READ(reg);
2151 if (val & PIPECONF_ENABLE) {
2152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2154 return;
2155 }
2156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
2158 POSTING_READ(reg);
2159 }
2160
2161 /**
2162 * intel_disable_pipe - disable a pipe, asserting requirements
2163 * @crtc: crtc whose pipes is to be disabled
2164 *
2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
2171 static void intel_disable_pipe(struct intel_crtc *crtc)
2172 {
2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2175 enum pipe pipe = crtc->pipe;
2176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
2184 assert_cursor_disabled(dev_priv, pipe);
2185 assert_sprites_disabled(dev_priv, pipe);
2186
2187 reg = PIPECONF(cpu_transcoder);
2188 val = I915_READ(reg);
2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
2196 if (crtc->config->double_wide)
2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
2207 }
2208
2209 /*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
2213 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
2215 {
2216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
2221 }
2222
2223 /**
2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
2227 *
2228 * Enable @plane on @crtc, making sure that the pipe is running first.
2229 */
2230 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
2232 {
2233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2239 to_intel_plane_state(plane->state)->visible = true;
2240
2241 dev_priv->display.update_primary_plane(crtc, plane->fb,
2242 crtc->x, crtc->y);
2243 }
2244
2245 static bool need_vtd_wa(struct drm_device *dev)
2246 {
2247 #ifdef CONFIG_INTEL_IOMMU
2248 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2249 return true;
2250 #endif
2251 return false;
2252 }
2253
2254 unsigned int
2255 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2256 uint64_t fb_format_modifier)
2257 {
2258 unsigned int tile_height;
2259 uint32_t pixel_bytes;
2260
2261 switch (fb_format_modifier) {
2262 case DRM_FORMAT_MOD_NONE:
2263 tile_height = 1;
2264 break;
2265 case I915_FORMAT_MOD_X_TILED:
2266 tile_height = IS_GEN2(dev) ? 16 : 8;
2267 break;
2268 case I915_FORMAT_MOD_Y_TILED:
2269 tile_height = 32;
2270 break;
2271 case I915_FORMAT_MOD_Yf_TILED:
2272 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2273 switch (pixel_bytes) {
2274 default:
2275 case 1:
2276 tile_height = 64;
2277 break;
2278 case 2:
2279 case 4:
2280 tile_height = 32;
2281 break;
2282 case 8:
2283 tile_height = 16;
2284 break;
2285 case 16:
2286 WARN_ONCE(1,
2287 "128-bit pixels are not supported for display!");
2288 tile_height = 16;
2289 break;
2290 }
2291 break;
2292 default:
2293 MISSING_CASE(fb_format_modifier);
2294 tile_height = 1;
2295 break;
2296 }
2297
2298 return tile_height;
2299 }
2300
2301 unsigned int
2302 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2303 uint32_t pixel_format, uint64_t fb_format_modifier)
2304 {
2305 return ALIGN(height, intel_tile_height(dev, pixel_format,
2306 fb_format_modifier));
2307 }
2308
2309 static int
2310 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2311 const struct drm_plane_state *plane_state)
2312 {
2313 struct intel_rotation_info *info = &view->rotation_info;
2314
2315 *view = i915_ggtt_view_normal;
2316
2317 if (!plane_state)
2318 return 0;
2319
2320 if (!intel_rotation_90_or_270(plane_state->rotation))
2321 return 0;
2322
2323 *view = i915_ggtt_view_rotated;
2324
2325 info->height = fb->height;
2326 info->pixel_format = fb->pixel_format;
2327 info->pitch = fb->pitches[0];
2328 info->fb_modifier = fb->modifier[0];
2329
2330 return 0;
2331 }
2332
2333 int
2334 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
2336 const struct drm_plane_state *plane_state,
2337 struct intel_engine_cs *pipelined)
2338 {
2339 struct drm_device *dev = fb->dev;
2340 struct drm_i915_private *dev_priv = dev->dev_private;
2341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2342 struct i915_ggtt_view view;
2343 u32 alignment;
2344 int ret;
2345
2346 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347
2348 switch (fb->modifier[0]) {
2349 case DRM_FORMAT_MOD_NONE:
2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2353 alignment = 128 * 1024;
2354 else if (INTEL_INFO(dev)->gen >= 4)
2355 alignment = 4 * 1024;
2356 else
2357 alignment = 64 * 1024;
2358 break;
2359 case I915_FORMAT_MOD_X_TILED:
2360 if (INTEL_INFO(dev)->gen >= 9)
2361 alignment = 256 * 1024;
2362 else {
2363 /* pin() will align the object as required by fence */
2364 alignment = 0;
2365 }
2366 break;
2367 case I915_FORMAT_MOD_Y_TILED:
2368 case I915_FORMAT_MOD_Yf_TILED:
2369 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2370 "Y tiling bo slipped through, driver bug!\n"))
2371 return -EINVAL;
2372 alignment = 1 * 1024 * 1024;
2373 break;
2374 default:
2375 MISSING_CASE(fb->modifier[0]);
2376 return -EINVAL;
2377 }
2378
2379 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2380 if (ret)
2381 return ret;
2382
2383 /* Note that the w/a also requires 64 PTE of padding following the
2384 * bo. We currently fill all unused PTE with the shadow page and so
2385 * we should always have valid PTE following the scanout preventing
2386 * the VT-d warning.
2387 */
2388 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2389 alignment = 256 * 1024;
2390
2391 /*
2392 * Global gtt pte registers are special registers which actually forward
2393 * writes to a chunk of system memory. Which means that there is no risk
2394 * that the register values disappear as soon as we call
2395 * intel_runtime_pm_put(), so it is correct to wrap only the
2396 * pin/unpin/fence and not more.
2397 */
2398 intel_runtime_pm_get(dev_priv);
2399
2400 dev_priv->mm.interruptible = false;
2401 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
2402 &view);
2403 if (ret)
2404 goto err_interruptible;
2405
2406 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407 * fence, whereas 965+ only requires a fence if using
2408 * framebuffer compression. For simplicity, we always install
2409 * a fence as the cost is not that onerous.
2410 */
2411 ret = i915_gem_object_get_fence(obj);
2412 if (ret)
2413 goto err_unpin;
2414
2415 i915_gem_object_pin_fence(obj);
2416
2417 dev_priv->mm.interruptible = true;
2418 intel_runtime_pm_put(dev_priv);
2419 return 0;
2420
2421 err_unpin:
2422 i915_gem_object_unpin_from_display_plane(obj, &view);
2423 err_interruptible:
2424 dev_priv->mm.interruptible = true;
2425 intel_runtime_pm_put(dev_priv);
2426 return ret;
2427 }
2428
2429 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2430 const struct drm_plane_state *plane_state)
2431 {
2432 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2433 struct i915_ggtt_view view;
2434 int ret;
2435
2436 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2437
2438 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2439 WARN_ONCE(ret, "Couldn't get view from plane state!");
2440
2441 i915_gem_object_unpin_fence(obj);
2442 i915_gem_object_unpin_from_display_plane(obj, &view);
2443 }
2444
2445 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2446 * is assumed to be a power-of-two. */
2447 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
2451 {
2452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
2454
2455 tile_rows = *y / 8;
2456 *y %= 8;
2457
2458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
2463 unsigned int offset;
2464
2465 offset = *y * pitch + *x * cpp;
2466 *y = 0;
2467 *x = (offset & 4095) / cpp;
2468 return offset & -4096;
2469 }
2470 }
2471
2472 static int i9xx_format_to_fourcc(int format)
2473 {
2474 switch (format) {
2475 case DISPPLANE_8BPP:
2476 return DRM_FORMAT_C8;
2477 case DISPPLANE_BGRX555:
2478 return DRM_FORMAT_XRGB1555;
2479 case DISPPLANE_BGRX565:
2480 return DRM_FORMAT_RGB565;
2481 default:
2482 case DISPPLANE_BGRX888:
2483 return DRM_FORMAT_XRGB8888;
2484 case DISPPLANE_RGBX888:
2485 return DRM_FORMAT_XBGR8888;
2486 case DISPPLANE_BGRX101010:
2487 return DRM_FORMAT_XRGB2101010;
2488 case DISPPLANE_RGBX101010:
2489 return DRM_FORMAT_XBGR2101010;
2490 }
2491 }
2492
2493 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2494 {
2495 switch (format) {
2496 case PLANE_CTL_FORMAT_RGB_565:
2497 return DRM_FORMAT_RGB565;
2498 default:
2499 case PLANE_CTL_FORMAT_XRGB_8888:
2500 if (rgb_order) {
2501 if (alpha)
2502 return DRM_FORMAT_ABGR8888;
2503 else
2504 return DRM_FORMAT_XBGR8888;
2505 } else {
2506 if (alpha)
2507 return DRM_FORMAT_ARGB8888;
2508 else
2509 return DRM_FORMAT_XRGB8888;
2510 }
2511 case PLANE_CTL_FORMAT_XRGB_2101010:
2512 if (rgb_order)
2513 return DRM_FORMAT_XBGR2101010;
2514 else
2515 return DRM_FORMAT_XRGB2101010;
2516 }
2517 }
2518
2519 static bool
2520 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2521 struct intel_initial_plane_config *plane_config)
2522 {
2523 struct drm_device *dev = crtc->base.dev;
2524 struct drm_i915_gem_object *obj = NULL;
2525 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2526 struct drm_framebuffer *fb = &plane_config->fb->base;
2527 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529 PAGE_SIZE);
2530
2531 size_aligned -= base_aligned;
2532
2533 if (plane_config->size == 0)
2534 return false;
2535
2536 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2537 base_aligned,
2538 base_aligned,
2539 size_aligned);
2540 if (!obj)
2541 return false;
2542
2543 obj->tiling_mode = plane_config->tiling;
2544 if (obj->tiling_mode == I915_TILING_X)
2545 obj->stride = fb->pitches[0];
2546
2547 mode_cmd.pixel_format = fb->pixel_format;
2548 mode_cmd.width = fb->width;
2549 mode_cmd.height = fb->height;
2550 mode_cmd.pitches[0] = fb->pitches[0];
2551 mode_cmd.modifier[0] = fb->modifier[0];
2552 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2553
2554 mutex_lock(&dev->struct_mutex);
2555 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2556 &mode_cmd, obj)) {
2557 DRM_DEBUG_KMS("intel fb init failed\n");
2558 goto out_unref_obj;
2559 }
2560 mutex_unlock(&dev->struct_mutex);
2561
2562 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2563 return true;
2564
2565 out_unref_obj:
2566 drm_gem_object_unreference(&obj->base);
2567 mutex_unlock(&dev->struct_mutex);
2568 return false;
2569 }
2570
2571 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2572 static void
2573 update_state_fb(struct drm_plane *plane)
2574 {
2575 if (plane->fb == plane->state->fb)
2576 return;
2577
2578 if (plane->state->fb)
2579 drm_framebuffer_unreference(plane->state->fb);
2580 plane->state->fb = plane->fb;
2581 if (plane->state->fb)
2582 drm_framebuffer_reference(plane->state->fb);
2583 }
2584
2585 static void
2586 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2587 struct intel_initial_plane_config *plane_config)
2588 {
2589 struct drm_device *dev = intel_crtc->base.dev;
2590 struct drm_i915_private *dev_priv = dev->dev_private;
2591 struct drm_crtc *c;
2592 struct intel_crtc *i;
2593 struct drm_i915_gem_object *obj;
2594 struct drm_plane *primary = intel_crtc->base.primary;
2595 struct drm_framebuffer *fb;
2596
2597 if (!plane_config->fb)
2598 return;
2599
2600 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2601 fb = &plane_config->fb->base;
2602 goto valid_fb;
2603 }
2604
2605 kfree(plane_config->fb);
2606
2607 /*
2608 * Failed to alloc the obj, check to see if we should share
2609 * an fb with another CRTC instead
2610 */
2611 for_each_crtc(dev, c) {
2612 i = to_intel_crtc(c);
2613
2614 if (c == &intel_crtc->base)
2615 continue;
2616
2617 if (!i->active)
2618 continue;
2619
2620 fb = c->primary->fb;
2621 if (!fb)
2622 continue;
2623
2624 obj = intel_fb_obj(fb);
2625 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2626 drm_framebuffer_reference(fb);
2627 goto valid_fb;
2628 }
2629 }
2630
2631 return;
2632
2633 valid_fb:
2634 obj = intel_fb_obj(fb);
2635 if (obj->tiling_mode != I915_TILING_NONE)
2636 dev_priv->preserve_bios_swizzle = true;
2637
2638 primary->fb = fb;
2639 primary->state->crtc = &intel_crtc->base;
2640 primary->crtc = &intel_crtc->base;
2641 update_state_fb(primary);
2642 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2643 }
2644
2645 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2646 struct drm_framebuffer *fb,
2647 int x, int y)
2648 {
2649 struct drm_device *dev = crtc->dev;
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2652 struct drm_plane *primary = crtc->primary;
2653 bool visible = to_intel_plane_state(primary->state)->visible;
2654 struct drm_i915_gem_object *obj;
2655 int plane = intel_crtc->plane;
2656 unsigned long linear_offset;
2657 u32 dspcntr;
2658 u32 reg = DSPCNTR(plane);
2659 int pixel_size;
2660
2661 if (!visible || !fb) {
2662 I915_WRITE(reg, 0);
2663 if (INTEL_INFO(dev)->gen >= 4)
2664 I915_WRITE(DSPSURF(plane), 0);
2665 else
2666 I915_WRITE(DSPADDR(plane), 0);
2667 POSTING_READ(reg);
2668 return;
2669 }
2670
2671 obj = intel_fb_obj(fb);
2672 if (WARN_ON(obj == NULL))
2673 return;
2674
2675 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676
2677 dspcntr = DISPPLANE_GAMMA_ENABLE;
2678
2679 dspcntr |= DISPLAY_PLANE_ENABLE;
2680
2681 if (INTEL_INFO(dev)->gen < 4) {
2682 if (intel_crtc->pipe == PIPE_B)
2683 dspcntr |= DISPPLANE_SEL_PIPE_B;
2684
2685 /* pipesrc and dspsize control the size that is scaled from,
2686 * which should always be the user's requested size.
2687 */
2688 I915_WRITE(DSPSIZE(plane),
2689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
2691 I915_WRITE(DSPPOS(plane), 0);
2692 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2693 I915_WRITE(PRIMSIZE(plane),
2694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
2696 I915_WRITE(PRIMPOS(plane), 0);
2697 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2698 }
2699
2700 switch (fb->pixel_format) {
2701 case DRM_FORMAT_C8:
2702 dspcntr |= DISPPLANE_8BPP;
2703 break;
2704 case DRM_FORMAT_XRGB1555:
2705 case DRM_FORMAT_ARGB1555:
2706 dspcntr |= DISPPLANE_BGRX555;
2707 break;
2708 case DRM_FORMAT_RGB565:
2709 dspcntr |= DISPPLANE_BGRX565;
2710 break;
2711 case DRM_FORMAT_XRGB8888:
2712 case DRM_FORMAT_ARGB8888:
2713 dspcntr |= DISPPLANE_BGRX888;
2714 break;
2715 case DRM_FORMAT_XBGR8888:
2716 case DRM_FORMAT_ABGR8888:
2717 dspcntr |= DISPPLANE_RGBX888;
2718 break;
2719 case DRM_FORMAT_XRGB2101010:
2720 case DRM_FORMAT_ARGB2101010:
2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
2724 case DRM_FORMAT_ABGR2101010:
2725 dspcntr |= DISPPLANE_RGBX101010;
2726 break;
2727 default:
2728 BUG();
2729 }
2730
2731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
2734
2735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
2739
2740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
2742 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2743 pixel_size,
2744 fb->pitches[0]);
2745 linear_offset -= intel_crtc->dspaddr_offset;
2746 } else {
2747 intel_crtc->dspaddr_offset = linear_offset;
2748 }
2749
2750 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2751 dspcntr |= DISPPLANE_ROTATE_180;
2752
2753 x += (intel_crtc->config->pipe_src_w - 1);
2754 y += (intel_crtc->config->pipe_src_h - 1);
2755
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2758 linear_offset +=
2759 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2761 }
2762
2763 I915_WRITE(reg, dspcntr);
2764
2765 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2766 if (INTEL_INFO(dev)->gen >= 4) {
2767 I915_WRITE(DSPSURF(plane),
2768 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2769 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2770 I915_WRITE(DSPLINOFF(plane), linear_offset);
2771 } else
2772 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2773 POSTING_READ(reg);
2774 }
2775
2776 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2777 struct drm_framebuffer *fb,
2778 int x, int y)
2779 {
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2783 struct drm_plane *primary = crtc->primary;
2784 bool visible = to_intel_plane_state(primary->state)->visible;
2785 struct drm_i915_gem_object *obj;
2786 int plane = intel_crtc->plane;
2787 unsigned long linear_offset;
2788 u32 dspcntr;
2789 u32 reg = DSPCNTR(plane);
2790 int pixel_size;
2791
2792 if (!visible || !fb) {
2793 I915_WRITE(reg, 0);
2794 I915_WRITE(DSPSURF(plane), 0);
2795 POSTING_READ(reg);
2796 return;
2797 }
2798
2799 obj = intel_fb_obj(fb);
2800 if (WARN_ON(obj == NULL))
2801 return;
2802
2803 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2804
2805 dspcntr = DISPPLANE_GAMMA_ENABLE;
2806
2807 dspcntr |= DISPLAY_PLANE_ENABLE;
2808
2809 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2811
2812 switch (fb->pixel_format) {
2813 case DRM_FORMAT_C8:
2814 dspcntr |= DISPPLANE_8BPP;
2815 break;
2816 case DRM_FORMAT_RGB565:
2817 dspcntr |= DISPPLANE_BGRX565;
2818 break;
2819 case DRM_FORMAT_XRGB8888:
2820 case DRM_FORMAT_ARGB8888:
2821 dspcntr |= DISPPLANE_BGRX888;
2822 break;
2823 case DRM_FORMAT_XBGR8888:
2824 case DRM_FORMAT_ABGR8888:
2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
2828 case DRM_FORMAT_ARGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
2832 case DRM_FORMAT_ABGR2101010:
2833 dspcntr |= DISPPLANE_RGBX101010;
2834 break;
2835 default:
2836 BUG();
2837 }
2838
2839 if (obj->tiling_mode != I915_TILING_NONE)
2840 dspcntr |= DISPPLANE_TILED;
2841
2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2843 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2844
2845 linear_offset = y * fb->pitches[0] + x * pixel_size;
2846 intel_crtc->dspaddr_offset =
2847 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2848 pixel_size,
2849 fb->pitches[0]);
2850 linear_offset -= intel_crtc->dspaddr_offset;
2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
2867
2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
2877 POSTING_READ(reg);
2878 }
2879
2880 u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882 {
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912 }
2913
2914 unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916 {
2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2920 view = &i915_ggtt_view_rotated;
2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923 }
2924
2925 /*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928 void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929 {
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 if (!intel_crtc || !intel_crtc->config)
2936 return;
2937
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2941
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950 }
2951 }
2952 }
2953
2954 u32 skl_plane_ctl_format(uint32_t pixel_format)
2955 {
2956 u32 plane_ctl_format = 0;
2957 switch (pixel_format) {
2958 case DRM_FORMAT_RGB565:
2959 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
2960 break;
2961 case DRM_FORMAT_XBGR8888:
2962 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2963 break;
2964 case DRM_FORMAT_XRGB8888:
2965 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
2966 break;
2967 /*
2968 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2969 * to be already pre-multiplied. We need to add a knob (or a different
2970 * DRM_FORMAT) for user-space to configure that.
2971 */
2972 case DRM_FORMAT_ABGR8888:
2973 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2974 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2975 break;
2976 case DRM_FORMAT_ARGB8888:
2977 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2978 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2979 break;
2980 case DRM_FORMAT_XRGB2101010:
2981 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
2982 break;
2983 case DRM_FORMAT_XBGR2101010:
2984 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2985 break;
2986 case DRM_FORMAT_YUYV:
2987 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2988 break;
2989 case DRM_FORMAT_YVYU:
2990 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2991 break;
2992 case DRM_FORMAT_UYVY:
2993 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
2994 break;
2995 case DRM_FORMAT_VYUY:
2996 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
2997 break;
2998 default:
2999 BUG();
3000 }
3001 return plane_ctl_format;
3002 }
3003
3004 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3005 {
3006 u32 plane_ctl_tiling = 0;
3007 switch (fb_modifier) {
3008 case DRM_FORMAT_MOD_NONE:
3009 break;
3010 case I915_FORMAT_MOD_X_TILED:
3011 plane_ctl_tiling = PLANE_CTL_TILED_X;
3012 break;
3013 case I915_FORMAT_MOD_Y_TILED:
3014 plane_ctl_tiling = PLANE_CTL_TILED_Y;
3015 break;
3016 case I915_FORMAT_MOD_Yf_TILED:
3017 plane_ctl_tiling = PLANE_CTL_TILED_YF;
3018 break;
3019 default:
3020 MISSING_CASE(fb_modifier);
3021 }
3022 return plane_ctl_tiling;
3023 }
3024
3025 u32 skl_plane_ctl_rotation(unsigned int rotation)
3026 {
3027 u32 plane_ctl_rotation = 0;
3028 switch (rotation) {
3029 case BIT(DRM_ROTATE_0):
3030 break;
3031 case BIT(DRM_ROTATE_90):
3032 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3033 break;
3034 case BIT(DRM_ROTATE_180):
3035 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3036 break;
3037 case BIT(DRM_ROTATE_270):
3038 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3039 break;
3040 default:
3041 MISSING_CASE(rotation);
3042 }
3043
3044 return plane_ctl_rotation;
3045 }
3046
3047 static void skylake_update_primary_plane(struct drm_crtc *crtc,
3048 struct drm_framebuffer *fb,
3049 int x, int y)
3050 {
3051 struct drm_device *dev = crtc->dev;
3052 struct drm_i915_private *dev_priv = dev->dev_private;
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054 struct drm_plane *plane = crtc->primary;
3055 bool visible = to_intel_plane_state(plane->state)->visible;
3056 struct drm_i915_gem_object *obj;
3057 int pipe = intel_crtc->pipe;
3058 u32 plane_ctl, stride_div, stride;
3059 u32 tile_height, plane_offset, plane_size;
3060 unsigned int rotation;
3061 int x_offset, y_offset;
3062 unsigned long surf_addr;
3063 struct intel_crtc_state *crtc_state = intel_crtc->config;
3064 struct intel_plane_state *plane_state;
3065 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3066 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3067 int scaler_id = -1;
3068
3069 plane_state = to_intel_plane_state(plane->state);
3070
3071 if (!visible || !fb) {
3072 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3073 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3074 POSTING_READ(PLANE_CTL(pipe, 0));
3075 return;
3076 }
3077
3078 plane_ctl = PLANE_CTL_ENABLE |
3079 PLANE_CTL_PIPE_GAMMA_ENABLE |
3080 PLANE_CTL_PIPE_CSC_ENABLE;
3081
3082 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3083 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3084 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3085
3086 rotation = plane->state->rotation;
3087 plane_ctl |= skl_plane_ctl_rotation(rotation);
3088
3089 obj = intel_fb_obj(fb);
3090 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3091 fb->pixel_format);
3092 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3093
3094 /*
3095 * FIXME: intel_plane_state->src, dst aren't set when transitional
3096 * update_plane helpers are called from legacy paths.
3097 * Once full atomic crtc is available, below check can be avoided.
3098 */
3099 if (drm_rect_width(&plane_state->src)) {
3100 scaler_id = plane_state->scaler_id;
3101 src_x = plane_state->src.x1 >> 16;
3102 src_y = plane_state->src.y1 >> 16;
3103 src_w = drm_rect_width(&plane_state->src) >> 16;
3104 src_h = drm_rect_height(&plane_state->src) >> 16;
3105 dst_x = plane_state->dst.x1;
3106 dst_y = plane_state->dst.y1;
3107 dst_w = drm_rect_width(&plane_state->dst);
3108 dst_h = drm_rect_height(&plane_state->dst);
3109
3110 WARN_ON(x != src_x || y != src_y);
3111 } else {
3112 src_w = intel_crtc->config->pipe_src_w;
3113 src_h = intel_crtc->config->pipe_src_h;
3114 }
3115
3116 if (intel_rotation_90_or_270(rotation)) {
3117 /* stride = Surface height in tiles */
3118 tile_height = intel_tile_height(dev, fb->pixel_format,
3119 fb->modifier[0]);
3120 stride = DIV_ROUND_UP(fb->height, tile_height);
3121 x_offset = stride * tile_height - y - src_h;
3122 y_offset = x;
3123 plane_size = (src_w - 1) << 16 | (src_h - 1);
3124 } else {
3125 stride = fb->pitches[0] / stride_div;
3126 x_offset = x;
3127 y_offset = y;
3128 plane_size = (src_h - 1) << 16 | (src_w - 1);
3129 }
3130 plane_offset = y_offset << 16 | x_offset;
3131
3132 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3133 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3134 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3135 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3136
3137 if (scaler_id >= 0) {
3138 uint32_t ps_ctrl = 0;
3139
3140 WARN_ON(!dst_w || !dst_h);
3141 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3142 crtc_state->scaler_state.scalers[scaler_id].mode;
3143 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3144 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3145 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3146 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3147 I915_WRITE(PLANE_POS(pipe, 0), 0);
3148 } else {
3149 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3150 }
3151
3152 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3153
3154 POSTING_READ(PLANE_SURF(pipe, 0));
3155 }
3156
3157 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3158 static int
3159 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3160 int x, int y, enum mode_set_atomic state)
3161 {
3162 struct drm_device *dev = crtc->dev;
3163 struct drm_i915_private *dev_priv = dev->dev_private;
3164
3165 if (dev_priv->display.disable_fbc)
3166 dev_priv->display.disable_fbc(dev);
3167
3168 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3169
3170 return 0;
3171 }
3172
3173 static void intel_complete_page_flips(struct drm_device *dev)
3174 {
3175 struct drm_crtc *crtc;
3176
3177 for_each_crtc(dev, crtc) {
3178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3179 enum plane plane = intel_crtc->plane;
3180
3181 intel_prepare_page_flip(dev, plane);
3182 intel_finish_page_flip_plane(dev, plane);
3183 }
3184 }
3185
3186 static void intel_update_primary_planes(struct drm_device *dev)
3187 {
3188 struct drm_i915_private *dev_priv = dev->dev_private;
3189 struct drm_crtc *crtc;
3190
3191 for_each_crtc(dev, crtc) {
3192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3193
3194 drm_modeset_lock(&crtc->mutex, NULL);
3195 /*
3196 * FIXME: Once we have proper support for primary planes (and
3197 * disabling them without disabling the entire crtc) allow again
3198 * a NULL crtc->primary->fb.
3199 */
3200 if (intel_crtc->active && crtc->primary->fb)
3201 dev_priv->display.update_primary_plane(crtc,
3202 crtc->primary->fb,
3203 crtc->x,
3204 crtc->y);
3205 drm_modeset_unlock(&crtc->mutex);
3206 }
3207 }
3208
3209 void intel_crtc_reset(struct intel_crtc *crtc)
3210 {
3211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3212
3213 if (!crtc->active)
3214 return;
3215
3216 intel_crtc_disable_planes(&crtc->base);
3217 dev_priv->display.crtc_disable(&crtc->base);
3218 dev_priv->display.crtc_enable(&crtc->base);
3219 intel_crtc_enable_planes(&crtc->base);
3220 }
3221
3222 void intel_prepare_reset(struct drm_device *dev)
3223 {
3224 struct drm_i915_private *dev_priv = to_i915(dev);
3225 struct intel_crtc *crtc;
3226
3227 /* no reset support for gen2 */
3228 if (IS_GEN2(dev))
3229 return;
3230
3231 /* reset doesn't touch the display */
3232 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3233 return;
3234
3235 drm_modeset_lock_all(dev);
3236
3237 /*
3238 * Disabling the crtcs gracefully seems nicer. Also the
3239 * g33 docs say we should at least disable all the planes.
3240 */
3241 for_each_intel_crtc(dev, crtc) {
3242 if (!crtc->active)
3243 continue;
3244
3245 intel_crtc_disable_planes(&crtc->base);
3246 dev_priv->display.crtc_disable(&crtc->base);
3247 }
3248 }
3249
3250 void intel_finish_reset(struct drm_device *dev)
3251 {
3252 struct drm_i915_private *dev_priv = to_i915(dev);
3253
3254 /*
3255 * Flips in the rings will be nuked by the reset,
3256 * so complete all pending flips so that user space
3257 * will get its events and not get stuck.
3258 */
3259 intel_complete_page_flips(dev);
3260
3261 /* no reset support for gen2 */
3262 if (IS_GEN2(dev))
3263 return;
3264
3265 /* reset doesn't touch the display */
3266 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3267 /*
3268 * Flips in the rings have been nuked by the reset,
3269 * so update the base address of all primary
3270 * planes to the the last fb to make sure we're
3271 * showing the correct fb after a reset.
3272 */
3273 intel_update_primary_planes(dev);
3274 return;
3275 }
3276
3277 /*
3278 * The display has been reset as well,
3279 * so need a full re-initialization.
3280 */
3281 intel_runtime_pm_disable_interrupts(dev_priv);
3282 intel_runtime_pm_enable_interrupts(dev_priv);
3283
3284 intel_modeset_init_hw(dev);
3285
3286 spin_lock_irq(&dev_priv->irq_lock);
3287 if (dev_priv->display.hpd_irq_setup)
3288 dev_priv->display.hpd_irq_setup(dev);
3289 spin_unlock_irq(&dev_priv->irq_lock);
3290
3291 intel_modeset_setup_hw_state(dev, true);
3292
3293 intel_hpd_init(dev_priv);
3294
3295 drm_modeset_unlock_all(dev);
3296 }
3297
3298 static int
3299 intel_finish_fb(struct drm_framebuffer *old_fb)
3300 {
3301 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
3302 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3303 bool was_interruptible = dev_priv->mm.interruptible;
3304 int ret;
3305
3306 /* Big Hammer, we also need to ensure that any pending
3307 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3308 * current scanout is retired before unpinning the old
3309 * framebuffer.
3310 *
3311 * This should only fail upon a hung GPU, in which case we
3312 * can safely continue.
3313 */
3314 dev_priv->mm.interruptible = false;
3315 ret = i915_gem_object_finish_gpu(obj);
3316 dev_priv->mm.interruptible = was_interruptible;
3317
3318 return ret;
3319 }
3320
3321 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3322 {
3323 struct drm_device *dev = crtc->dev;
3324 struct drm_i915_private *dev_priv = dev->dev_private;
3325 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3326 bool pending;
3327
3328 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3329 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3330 return false;
3331
3332 spin_lock_irq(&dev->event_lock);
3333 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3334 spin_unlock_irq(&dev->event_lock);
3335
3336 return pending;
3337 }
3338
3339 static void intel_update_pipe_size(struct intel_crtc *crtc)
3340 {
3341 struct drm_device *dev = crtc->base.dev;
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343 const struct drm_display_mode *adjusted_mode;
3344
3345 if (!i915.fastboot)
3346 return;
3347
3348 /*
3349 * Update pipe size and adjust fitter if needed: the reason for this is
3350 * that in compute_mode_changes we check the native mode (not the pfit
3351 * mode) to see if we can flip rather than do a full mode set. In the
3352 * fastboot case, we'll flip, but if we don't update the pipesrc and
3353 * pfit state, we'll end up with a big fb scanned out into the wrong
3354 * sized surface.
3355 *
3356 * To fix this properly, we need to hoist the checks up into
3357 * compute_mode_changes (or above), check the actual pfit state and
3358 * whether the platform allows pfit disable with pipe active, and only
3359 * then update the pipesrc and pfit state, even on the flip path.
3360 */
3361
3362 adjusted_mode = &crtc->config->base.adjusted_mode;
3363
3364 I915_WRITE(PIPESRC(crtc->pipe),
3365 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3366 (adjusted_mode->crtc_vdisplay - 1));
3367 if (!crtc->config->pch_pfit.enabled &&
3368 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3369 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3370 I915_WRITE(PF_CTL(crtc->pipe), 0);
3371 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3372 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3373 }
3374 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3375 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
3376 }
3377
3378 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3379 {
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383 int pipe = intel_crtc->pipe;
3384 u32 reg, temp;
3385
3386 /* enable normal train */
3387 reg = FDI_TX_CTL(pipe);
3388 temp = I915_READ(reg);
3389 if (IS_IVYBRIDGE(dev)) {
3390 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3391 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3392 } else {
3393 temp &= ~FDI_LINK_TRAIN_NONE;
3394 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3395 }
3396 I915_WRITE(reg, temp);
3397
3398 reg = FDI_RX_CTL(pipe);
3399 temp = I915_READ(reg);
3400 if (HAS_PCH_CPT(dev)) {
3401 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3402 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3403 } else {
3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_NONE;
3406 }
3407 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3408
3409 /* wait one idle pattern time */
3410 POSTING_READ(reg);
3411 udelay(1000);
3412
3413 /* IVB wants error correction enabled */
3414 if (IS_IVYBRIDGE(dev))
3415 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3416 FDI_FE_ERRC_ENABLE);
3417 }
3418
3419 /* The FDI link training functions for ILK/Ibexpeak. */
3420 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3421 {
3422 struct drm_device *dev = crtc->dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3425 int pipe = intel_crtc->pipe;
3426 u32 reg, temp, tries;
3427
3428 /* FDI needs bits from pipe first */
3429 assert_pipe_enabled(dev_priv, pipe);
3430
3431 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3432 for train result */
3433 reg = FDI_RX_IMR(pipe);
3434 temp = I915_READ(reg);
3435 temp &= ~FDI_RX_SYMBOL_LOCK;
3436 temp &= ~FDI_RX_BIT_LOCK;
3437 I915_WRITE(reg, temp);
3438 I915_READ(reg);
3439 udelay(150);
3440
3441 /* enable CPU FDI TX and PCH FDI RX */
3442 reg = FDI_TX_CTL(pipe);
3443 temp = I915_READ(reg);
3444 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3445 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3446 temp &= ~FDI_LINK_TRAIN_NONE;
3447 temp |= FDI_LINK_TRAIN_PATTERN_1;
3448 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3449
3450 reg = FDI_RX_CTL(pipe);
3451 temp = I915_READ(reg);
3452 temp &= ~FDI_LINK_TRAIN_NONE;
3453 temp |= FDI_LINK_TRAIN_PATTERN_1;
3454 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3455
3456 POSTING_READ(reg);
3457 udelay(150);
3458
3459 /* Ironlake workaround, enable clock pointer after FDI enable*/
3460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3462 FDI_RX_PHASE_SYNC_POINTER_EN);
3463
3464 reg = FDI_RX_IIR(pipe);
3465 for (tries = 0; tries < 5; tries++) {
3466 temp = I915_READ(reg);
3467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3468
3469 if ((temp & FDI_RX_BIT_LOCK)) {
3470 DRM_DEBUG_KMS("FDI train 1 done.\n");
3471 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3472 break;
3473 }
3474 }
3475 if (tries == 5)
3476 DRM_ERROR("FDI train 1 fail!\n");
3477
3478 /* Train 2 */
3479 reg = FDI_TX_CTL(pipe);
3480 temp = I915_READ(reg);
3481 temp &= ~FDI_LINK_TRAIN_NONE;
3482 temp |= FDI_LINK_TRAIN_PATTERN_2;
3483 I915_WRITE(reg, temp);
3484
3485 reg = FDI_RX_CTL(pipe);
3486 temp = I915_READ(reg);
3487 temp &= ~FDI_LINK_TRAIN_NONE;
3488 temp |= FDI_LINK_TRAIN_PATTERN_2;
3489 I915_WRITE(reg, temp);
3490
3491 POSTING_READ(reg);
3492 udelay(150);
3493
3494 reg = FDI_RX_IIR(pipe);
3495 for (tries = 0; tries < 5; tries++) {
3496 temp = I915_READ(reg);
3497 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3498
3499 if (temp & FDI_RX_SYMBOL_LOCK) {
3500 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3501 DRM_DEBUG_KMS("FDI train 2 done.\n");
3502 break;
3503 }
3504 }
3505 if (tries == 5)
3506 DRM_ERROR("FDI train 2 fail!\n");
3507
3508 DRM_DEBUG_KMS("FDI train done\n");
3509
3510 }
3511
3512 static const int snb_b_fdi_train_param[] = {
3513 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3514 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3515 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3516 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3517 };
3518
3519 /* The FDI link training functions for SNB/Cougarpoint. */
3520 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3521 {
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525 int pipe = intel_crtc->pipe;
3526 u32 reg, temp, i, retry;
3527
3528 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3529 for train result */
3530 reg = FDI_RX_IMR(pipe);
3531 temp = I915_READ(reg);
3532 temp &= ~FDI_RX_SYMBOL_LOCK;
3533 temp &= ~FDI_RX_BIT_LOCK;
3534 I915_WRITE(reg, temp);
3535
3536 POSTING_READ(reg);
3537 udelay(150);
3538
3539 /* enable CPU FDI TX and PCH FDI RX */
3540 reg = FDI_TX_CTL(pipe);
3541 temp = I915_READ(reg);
3542 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3543 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3544 temp &= ~FDI_LINK_TRAIN_NONE;
3545 temp |= FDI_LINK_TRAIN_PATTERN_1;
3546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3547 /* SNB-B */
3548 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3549 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3550
3551 I915_WRITE(FDI_RX_MISC(pipe),
3552 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3553
3554 reg = FDI_RX_CTL(pipe);
3555 temp = I915_READ(reg);
3556 if (HAS_PCH_CPT(dev)) {
3557 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3558 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3559 } else {
3560 temp &= ~FDI_LINK_TRAIN_NONE;
3561 temp |= FDI_LINK_TRAIN_PATTERN_1;
3562 }
3563 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3564
3565 POSTING_READ(reg);
3566 udelay(150);
3567
3568 for (i = 0; i < 4; i++) {
3569 reg = FDI_TX_CTL(pipe);
3570 temp = I915_READ(reg);
3571 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3572 temp |= snb_b_fdi_train_param[i];
3573 I915_WRITE(reg, temp);
3574
3575 POSTING_READ(reg);
3576 udelay(500);
3577
3578 for (retry = 0; retry < 5; retry++) {
3579 reg = FDI_RX_IIR(pipe);
3580 temp = I915_READ(reg);
3581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3582 if (temp & FDI_RX_BIT_LOCK) {
3583 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3584 DRM_DEBUG_KMS("FDI train 1 done.\n");
3585 break;
3586 }
3587 udelay(50);
3588 }
3589 if (retry < 5)
3590 break;
3591 }
3592 if (i == 4)
3593 DRM_ERROR("FDI train 1 fail!\n");
3594
3595 /* Train 2 */
3596 reg = FDI_TX_CTL(pipe);
3597 temp = I915_READ(reg);
3598 temp &= ~FDI_LINK_TRAIN_NONE;
3599 temp |= FDI_LINK_TRAIN_PATTERN_2;
3600 if (IS_GEN6(dev)) {
3601 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3602 /* SNB-B */
3603 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3604 }
3605 I915_WRITE(reg, temp);
3606
3607 reg = FDI_RX_CTL(pipe);
3608 temp = I915_READ(reg);
3609 if (HAS_PCH_CPT(dev)) {
3610 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3611 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3612 } else {
3613 temp &= ~FDI_LINK_TRAIN_NONE;
3614 temp |= FDI_LINK_TRAIN_PATTERN_2;
3615 }
3616 I915_WRITE(reg, temp);
3617
3618 POSTING_READ(reg);
3619 udelay(150);
3620
3621 for (i = 0; i < 4; i++) {
3622 reg = FDI_TX_CTL(pipe);
3623 temp = I915_READ(reg);
3624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3625 temp |= snb_b_fdi_train_param[i];
3626 I915_WRITE(reg, temp);
3627
3628 POSTING_READ(reg);
3629 udelay(500);
3630
3631 for (retry = 0; retry < 5; retry++) {
3632 reg = FDI_RX_IIR(pipe);
3633 temp = I915_READ(reg);
3634 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3635 if (temp & FDI_RX_SYMBOL_LOCK) {
3636 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3637 DRM_DEBUG_KMS("FDI train 2 done.\n");
3638 break;
3639 }
3640 udelay(50);
3641 }
3642 if (retry < 5)
3643 break;
3644 }
3645 if (i == 4)
3646 DRM_ERROR("FDI train 2 fail!\n");
3647
3648 DRM_DEBUG_KMS("FDI train done.\n");
3649 }
3650
3651 /* Manual link training for Ivy Bridge A0 parts */
3652 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3653 {
3654 struct drm_device *dev = crtc->dev;
3655 struct drm_i915_private *dev_priv = dev->dev_private;
3656 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3657 int pipe = intel_crtc->pipe;
3658 u32 reg, temp, i, j;
3659
3660 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3661 for train result */
3662 reg = FDI_RX_IMR(pipe);
3663 temp = I915_READ(reg);
3664 temp &= ~FDI_RX_SYMBOL_LOCK;
3665 temp &= ~FDI_RX_BIT_LOCK;
3666 I915_WRITE(reg, temp);
3667
3668 POSTING_READ(reg);
3669 udelay(150);
3670
3671 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3672 I915_READ(FDI_RX_IIR(pipe)));
3673
3674 /* Try each vswing and preemphasis setting twice before moving on */
3675 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3676 /* disable first in case we need to retry */
3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
3679 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3680 temp &= ~FDI_TX_ENABLE;
3681 I915_WRITE(reg, temp);
3682
3683 reg = FDI_RX_CTL(pipe);
3684 temp = I915_READ(reg);
3685 temp &= ~FDI_LINK_TRAIN_AUTO;
3686 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3687 temp &= ~FDI_RX_ENABLE;
3688 I915_WRITE(reg, temp);
3689
3690 /* enable CPU FDI TX and PCH FDI RX */
3691 reg = FDI_TX_CTL(pipe);
3692 temp = I915_READ(reg);
3693 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3694 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3695 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3696 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3697 temp |= snb_b_fdi_train_param[j/2];
3698 temp |= FDI_COMPOSITE_SYNC;
3699 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3700
3701 I915_WRITE(FDI_RX_MISC(pipe),
3702 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3703
3704 reg = FDI_RX_CTL(pipe);
3705 temp = I915_READ(reg);
3706 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3707 temp |= FDI_COMPOSITE_SYNC;
3708 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3709
3710 POSTING_READ(reg);
3711 udelay(1); /* should be 0.5us */
3712
3713 for (i = 0; i < 4; i++) {
3714 reg = FDI_RX_IIR(pipe);
3715 temp = I915_READ(reg);
3716 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3717
3718 if (temp & FDI_RX_BIT_LOCK ||
3719 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3720 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3721 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3722 i);
3723 break;
3724 }
3725 udelay(1); /* should be 0.5us */
3726 }
3727 if (i == 4) {
3728 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3729 continue;
3730 }
3731
3732 /* Train 2 */
3733 reg = FDI_TX_CTL(pipe);
3734 temp = I915_READ(reg);
3735 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3736 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3737 I915_WRITE(reg, temp);
3738
3739 reg = FDI_RX_CTL(pipe);
3740 temp = I915_READ(reg);
3741 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3742 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3743 I915_WRITE(reg, temp);
3744
3745 POSTING_READ(reg);
3746 udelay(2); /* should be 1.5us */
3747
3748 for (i = 0; i < 4; i++) {
3749 reg = FDI_RX_IIR(pipe);
3750 temp = I915_READ(reg);
3751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3752
3753 if (temp & FDI_RX_SYMBOL_LOCK ||
3754 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3755 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3756 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3757 i);
3758 goto train_done;
3759 }
3760 udelay(2); /* should be 1.5us */
3761 }
3762 if (i == 4)
3763 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3764 }
3765
3766 train_done:
3767 DRM_DEBUG_KMS("FDI train done.\n");
3768 }
3769
3770 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3771 {
3772 struct drm_device *dev = intel_crtc->base.dev;
3773 struct drm_i915_private *dev_priv = dev->dev_private;
3774 int pipe = intel_crtc->pipe;
3775 u32 reg, temp;
3776
3777
3778 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3779 reg = FDI_RX_CTL(pipe);
3780 temp = I915_READ(reg);
3781 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3782 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3783 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3784 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3785
3786 POSTING_READ(reg);
3787 udelay(200);
3788
3789 /* Switch from Rawclk to PCDclk */
3790 temp = I915_READ(reg);
3791 I915_WRITE(reg, temp | FDI_PCDCLK);
3792
3793 POSTING_READ(reg);
3794 udelay(200);
3795
3796 /* Enable CPU FDI TX PLL, always on for Ironlake */
3797 reg = FDI_TX_CTL(pipe);
3798 temp = I915_READ(reg);
3799 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3800 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3801
3802 POSTING_READ(reg);
3803 udelay(100);
3804 }
3805 }
3806
3807 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3808 {
3809 struct drm_device *dev = intel_crtc->base.dev;
3810 struct drm_i915_private *dev_priv = dev->dev_private;
3811 int pipe = intel_crtc->pipe;
3812 u32 reg, temp;
3813
3814 /* Switch from PCDclk to Rawclk */
3815 reg = FDI_RX_CTL(pipe);
3816 temp = I915_READ(reg);
3817 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3818
3819 /* Disable CPU FDI TX PLL */
3820 reg = FDI_TX_CTL(pipe);
3821 temp = I915_READ(reg);
3822 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3823
3824 POSTING_READ(reg);
3825 udelay(100);
3826
3827 reg = FDI_RX_CTL(pipe);
3828 temp = I915_READ(reg);
3829 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3830
3831 /* Wait for the clocks to turn off. */
3832 POSTING_READ(reg);
3833 udelay(100);
3834 }
3835
3836 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3837 {
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3841 int pipe = intel_crtc->pipe;
3842 u32 reg, temp;
3843
3844 /* disable CPU FDI tx and PCH FDI rx */
3845 reg = FDI_TX_CTL(pipe);
3846 temp = I915_READ(reg);
3847 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3848 POSTING_READ(reg);
3849
3850 reg = FDI_RX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~(0x7 << 16);
3853 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3854 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3855
3856 POSTING_READ(reg);
3857 udelay(100);
3858
3859 /* Ironlake workaround, disable clock pointer after downing FDI */
3860 if (HAS_PCH_IBX(dev))
3861 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3862
3863 /* still set train pattern 1 */
3864 reg = FDI_TX_CTL(pipe);
3865 temp = I915_READ(reg);
3866 temp &= ~FDI_LINK_TRAIN_NONE;
3867 temp |= FDI_LINK_TRAIN_PATTERN_1;
3868 I915_WRITE(reg, temp);
3869
3870 reg = FDI_RX_CTL(pipe);
3871 temp = I915_READ(reg);
3872 if (HAS_PCH_CPT(dev)) {
3873 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3874 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3875 } else {
3876 temp &= ~FDI_LINK_TRAIN_NONE;
3877 temp |= FDI_LINK_TRAIN_PATTERN_1;
3878 }
3879 /* BPC in FDI rx is consistent with that in PIPECONF */
3880 temp &= ~(0x07 << 16);
3881 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3882 I915_WRITE(reg, temp);
3883
3884 POSTING_READ(reg);
3885 udelay(100);
3886 }
3887
3888 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3889 {
3890 struct intel_crtc *crtc;
3891
3892 /* Note that we don't need to be called with mode_config.lock here
3893 * as our list of CRTC objects is static for the lifetime of the
3894 * device and so cannot disappear as we iterate. Similarly, we can
3895 * happily treat the predicates as racy, atomic checks as userspace
3896 * cannot claim and pin a new fb without at least acquring the
3897 * struct_mutex and so serialising with us.
3898 */
3899 for_each_intel_crtc(dev, crtc) {
3900 if (atomic_read(&crtc->unpin_work_count) == 0)
3901 continue;
3902
3903 if (crtc->unpin_work)
3904 intel_wait_for_vblank(dev, crtc->pipe);
3905
3906 return true;
3907 }
3908
3909 return false;
3910 }
3911
3912 static void page_flip_completed(struct intel_crtc *intel_crtc)
3913 {
3914 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3915 struct intel_unpin_work *work = intel_crtc->unpin_work;
3916
3917 /* ensure that the unpin work is consistent wrt ->pending. */
3918 smp_rmb();
3919 intel_crtc->unpin_work = NULL;
3920
3921 if (work->event)
3922 drm_send_vblank_event(intel_crtc->base.dev,
3923 intel_crtc->pipe,
3924 work->event);
3925
3926 drm_crtc_vblank_put(&intel_crtc->base);
3927
3928 wake_up_all(&dev_priv->pending_flip_queue);
3929 queue_work(dev_priv->wq, &work->work);
3930
3931 trace_i915_flip_complete(intel_crtc->plane,
3932 work->pending_flip_obj);
3933 }
3934
3935 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3936 {
3937 struct drm_device *dev = crtc->dev;
3938 struct drm_i915_private *dev_priv = dev->dev_private;
3939
3940 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3941 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3942 !intel_crtc_has_pending_flip(crtc),
3943 60*HZ) == 0)) {
3944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3945
3946 spin_lock_irq(&dev->event_lock);
3947 if (intel_crtc->unpin_work) {
3948 WARN_ONCE(1, "Removing stuck page flip\n");
3949 page_flip_completed(intel_crtc);
3950 }
3951 spin_unlock_irq(&dev->event_lock);
3952 }
3953
3954 if (crtc->primary->fb) {
3955 mutex_lock(&dev->struct_mutex);
3956 intel_finish_fb(crtc->primary->fb);
3957 mutex_unlock(&dev->struct_mutex);
3958 }
3959 }
3960
3961 /* Program iCLKIP clock to the desired frequency */
3962 static void lpt_program_iclkip(struct drm_crtc *crtc)
3963 {
3964 struct drm_device *dev = crtc->dev;
3965 struct drm_i915_private *dev_priv = dev->dev_private;
3966 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3967 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3968 u32 temp;
3969
3970 mutex_lock(&dev_priv->dpio_lock);
3971
3972 /* It is necessary to ungate the pixclk gate prior to programming
3973 * the divisors, and gate it back when it is done.
3974 */
3975 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3976
3977 /* Disable SSCCTL */
3978 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3979 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3980 SBI_SSCCTL_DISABLE,
3981 SBI_ICLK);
3982
3983 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3984 if (clock == 20000) {
3985 auxdiv = 1;
3986 divsel = 0x41;
3987 phaseinc = 0x20;
3988 } else {
3989 /* The iCLK virtual clock root frequency is in MHz,
3990 * but the adjusted_mode->crtc_clock in in KHz. To get the
3991 * divisors, it is necessary to divide one by another, so we
3992 * convert the virtual clock precision to KHz here for higher
3993 * precision.
3994 */
3995 u32 iclk_virtual_root_freq = 172800 * 1000;
3996 u32 iclk_pi_range = 64;
3997 u32 desired_divisor, msb_divisor_value, pi_value;
3998
3999 desired_divisor = (iclk_virtual_root_freq / clock);
4000 msb_divisor_value = desired_divisor / iclk_pi_range;
4001 pi_value = desired_divisor % iclk_pi_range;
4002
4003 auxdiv = 0;
4004 divsel = msb_divisor_value - 2;
4005 phaseinc = pi_value;
4006 }
4007
4008 /* This should not happen with any sane values */
4009 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4010 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4011 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4012 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4013
4014 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4015 clock,
4016 auxdiv,
4017 divsel,
4018 phasedir,
4019 phaseinc);
4020
4021 /* Program SSCDIVINTPHASE6 */
4022 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4023 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4024 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4025 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4026 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4027 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4028 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4029 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4030
4031 /* Program SSCAUXDIV */
4032 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4033 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4034 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4035 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4036
4037 /* Enable modulator and associated divider */
4038 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4039 temp &= ~SBI_SSCCTL_DISABLE;
4040 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4041
4042 /* Wait for initialization time */
4043 udelay(24);
4044
4045 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4046
4047 mutex_unlock(&dev_priv->dpio_lock);
4048 }
4049
4050 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4051 enum pipe pch_transcoder)
4052 {
4053 struct drm_device *dev = crtc->base.dev;
4054 struct drm_i915_private *dev_priv = dev->dev_private;
4055 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4056
4057 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4058 I915_READ(HTOTAL(cpu_transcoder)));
4059 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4060 I915_READ(HBLANK(cpu_transcoder)));
4061 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4062 I915_READ(HSYNC(cpu_transcoder)));
4063
4064 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4065 I915_READ(VTOTAL(cpu_transcoder)));
4066 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4067 I915_READ(VBLANK(cpu_transcoder)));
4068 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4069 I915_READ(VSYNC(cpu_transcoder)));
4070 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4071 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4072 }
4073
4074 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4075 {
4076 struct drm_i915_private *dev_priv = dev->dev_private;
4077 uint32_t temp;
4078
4079 temp = I915_READ(SOUTH_CHICKEN1);
4080 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4081 return;
4082
4083 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4084 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4085
4086 temp &= ~FDI_BC_BIFURCATION_SELECT;
4087 if (enable)
4088 temp |= FDI_BC_BIFURCATION_SELECT;
4089
4090 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4091 I915_WRITE(SOUTH_CHICKEN1, temp);
4092 POSTING_READ(SOUTH_CHICKEN1);
4093 }
4094
4095 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4096 {
4097 struct drm_device *dev = intel_crtc->base.dev;
4098
4099 switch (intel_crtc->pipe) {
4100 case PIPE_A:
4101 break;
4102 case PIPE_B:
4103 if (intel_crtc->config->fdi_lanes > 2)
4104 cpt_set_fdi_bc_bifurcation(dev, false);
4105 else
4106 cpt_set_fdi_bc_bifurcation(dev, true);
4107
4108 break;
4109 case PIPE_C:
4110 cpt_set_fdi_bc_bifurcation(dev, true);
4111
4112 break;
4113 default:
4114 BUG();
4115 }
4116 }
4117
4118 /*
4119 * Enable PCH resources required for PCH ports:
4120 * - PCH PLLs
4121 * - FDI training & RX/TX
4122 * - update transcoder timings
4123 * - DP transcoding bits
4124 * - transcoder
4125 */
4126 static void ironlake_pch_enable(struct drm_crtc *crtc)
4127 {
4128 struct drm_device *dev = crtc->dev;
4129 struct drm_i915_private *dev_priv = dev->dev_private;
4130 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4131 int pipe = intel_crtc->pipe;
4132 u32 reg, temp;
4133
4134 assert_pch_transcoder_disabled(dev_priv, pipe);
4135
4136 if (IS_IVYBRIDGE(dev))
4137 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4138
4139 /* Write the TU size bits before fdi link training, so that error
4140 * detection works. */
4141 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4142 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4143
4144 /* For PCH output, training FDI link */
4145 dev_priv->display.fdi_link_train(crtc);
4146
4147 /* We need to program the right clock selection before writing the pixel
4148 * mutliplier into the DPLL. */
4149 if (HAS_PCH_CPT(dev)) {
4150 u32 sel;
4151
4152 temp = I915_READ(PCH_DPLL_SEL);
4153 temp |= TRANS_DPLL_ENABLE(pipe);
4154 sel = TRANS_DPLLB_SEL(pipe);
4155 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4156 temp |= sel;
4157 else
4158 temp &= ~sel;
4159 I915_WRITE(PCH_DPLL_SEL, temp);
4160 }
4161
4162 /* XXX: pch pll's can be enabled any time before we enable the PCH
4163 * transcoder, and we actually should do this to not upset any PCH
4164 * transcoder that already use the clock when we share it.
4165 *
4166 * Note that enable_shared_dpll tries to do the right thing, but
4167 * get_shared_dpll unconditionally resets the pll - we need that to have
4168 * the right LVDS enable sequence. */
4169 intel_enable_shared_dpll(intel_crtc);
4170
4171 /* set transcoder timing, panel must allow it */
4172 assert_panel_unlocked(dev_priv, pipe);
4173 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4174
4175 intel_fdi_normal_train(crtc);
4176
4177 /* For PCH DP, enable TRANS_DP_CTL */
4178 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4179 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4180 reg = TRANS_DP_CTL(pipe);
4181 temp = I915_READ(reg);
4182 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4183 TRANS_DP_SYNC_MASK |
4184 TRANS_DP_BPC_MASK);
4185 temp |= (TRANS_DP_OUTPUT_ENABLE |
4186 TRANS_DP_ENH_FRAMING);
4187 temp |= bpc << 9; /* same format but at 11:9 */
4188
4189 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
4190 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4191 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
4192 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4193
4194 switch (intel_trans_dp_port_sel(crtc)) {
4195 case PCH_DP_B:
4196 temp |= TRANS_DP_PORT_SEL_B;
4197 break;
4198 case PCH_DP_C:
4199 temp |= TRANS_DP_PORT_SEL_C;
4200 break;
4201 case PCH_DP_D:
4202 temp |= TRANS_DP_PORT_SEL_D;
4203 break;
4204 default:
4205 BUG();
4206 }
4207
4208 I915_WRITE(reg, temp);
4209 }
4210
4211 ironlake_enable_pch_transcoder(dev_priv, pipe);
4212 }
4213
4214 static void lpt_pch_enable(struct drm_crtc *crtc)
4215 {
4216 struct drm_device *dev = crtc->dev;
4217 struct drm_i915_private *dev_priv = dev->dev_private;
4218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4219 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4220
4221 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4222
4223 lpt_program_iclkip(crtc);
4224
4225 /* Set transcoder timing. */
4226 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4227
4228 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4229 }
4230
4231 void intel_put_shared_dpll(struct intel_crtc *crtc)
4232 {
4233 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4234
4235 if (pll == NULL)
4236 return;
4237
4238 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
4239 WARN(1, "bad %s crtc mask\n", pll->name);
4240 return;
4241 }
4242
4243 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4244 if (pll->config.crtc_mask == 0) {
4245 WARN_ON(pll->on);
4246 WARN_ON(pll->active);
4247 }
4248
4249 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
4250 }
4251
4252 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4253 struct intel_crtc_state *crtc_state)
4254 {
4255 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4256 struct intel_shared_dpll *pll;
4257 enum intel_dpll_id i;
4258
4259 if (HAS_PCH_IBX(dev_priv->dev)) {
4260 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4261 i = (enum intel_dpll_id) crtc->pipe;
4262 pll = &dev_priv->shared_dplls[i];
4263
4264 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4265 crtc->base.base.id, pll->name);
4266
4267 WARN_ON(pll->new_config->crtc_mask);
4268
4269 goto found;
4270 }
4271
4272 if (IS_BROXTON(dev_priv->dev)) {
4273 /* PLL is attached to port in bxt */
4274 struct intel_encoder *encoder;
4275 struct intel_digital_port *intel_dig_port;
4276
4277 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4278 if (WARN_ON(!encoder))
4279 return NULL;
4280
4281 intel_dig_port = enc_to_dig_port(&encoder->base);
4282 /* 1:1 mapping between ports and PLLs */
4283 i = (enum intel_dpll_id)intel_dig_port->port;
4284 pll = &dev_priv->shared_dplls[i];
4285 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4286 crtc->base.base.id, pll->name);
4287 WARN_ON(pll->new_config->crtc_mask);
4288
4289 goto found;
4290 }
4291
4292 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4293 pll = &dev_priv->shared_dplls[i];
4294
4295 /* Only want to check enabled timings first */
4296 if (pll->new_config->crtc_mask == 0)
4297 continue;
4298
4299 if (memcmp(&crtc_state->dpll_hw_state,
4300 &pll->new_config->hw_state,
4301 sizeof(pll->new_config->hw_state)) == 0) {
4302 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4303 crtc->base.base.id, pll->name,
4304 pll->new_config->crtc_mask,
4305 pll->active);
4306 goto found;
4307 }
4308 }
4309
4310 /* Ok no matching timings, maybe there's a free one? */
4311 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4312 pll = &dev_priv->shared_dplls[i];
4313 if (pll->new_config->crtc_mask == 0) {
4314 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4315 crtc->base.base.id, pll->name);
4316 goto found;
4317 }
4318 }
4319
4320 return NULL;
4321
4322 found:
4323 if (pll->new_config->crtc_mask == 0)
4324 pll->new_config->hw_state = crtc_state->dpll_hw_state;
4325
4326 crtc_state->shared_dpll = i;
4327 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4328 pipe_name(crtc->pipe));
4329
4330 pll->new_config->crtc_mask |= 1 << crtc->pipe;
4331
4332 return pll;
4333 }
4334
4335 /**
4336 * intel_shared_dpll_start_config - start a new PLL staged config
4337 * @dev_priv: DRM device
4338 * @clear_pipes: mask of pipes that will have their PLLs freed
4339 *
4340 * Starts a new PLL staged config, copying the current config but
4341 * releasing the references of pipes specified in clear_pipes.
4342 */
4343 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4344 unsigned clear_pipes)
4345 {
4346 struct intel_shared_dpll *pll;
4347 enum intel_dpll_id i;
4348
4349 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4350 pll = &dev_priv->shared_dplls[i];
4351
4352 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4353 GFP_KERNEL);
4354 if (!pll->new_config)
4355 goto cleanup;
4356
4357 pll->new_config->crtc_mask &= ~clear_pipes;
4358 }
4359
4360 return 0;
4361
4362 cleanup:
4363 while (--i >= 0) {
4364 pll = &dev_priv->shared_dplls[i];
4365 kfree(pll->new_config);
4366 pll->new_config = NULL;
4367 }
4368
4369 return -ENOMEM;
4370 }
4371
4372 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4373 {
4374 struct intel_shared_dpll *pll;
4375 enum intel_dpll_id i;
4376
4377 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4378 pll = &dev_priv->shared_dplls[i];
4379
4380 WARN_ON(pll->new_config == &pll->config);
4381
4382 pll->config = *pll->new_config;
4383 kfree(pll->new_config);
4384 pll->new_config = NULL;
4385 }
4386 }
4387
4388 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4389 {
4390 struct intel_shared_dpll *pll;
4391 enum intel_dpll_id i;
4392
4393 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4394 pll = &dev_priv->shared_dplls[i];
4395
4396 WARN_ON(pll->new_config == &pll->config);
4397
4398 kfree(pll->new_config);
4399 pll->new_config = NULL;
4400 }
4401 }
4402
4403 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4404 {
4405 struct drm_i915_private *dev_priv = dev->dev_private;
4406 int dslreg = PIPEDSL(pipe);
4407 u32 temp;
4408
4409 temp = I915_READ(dslreg);
4410 udelay(500);
4411 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4412 if (wait_for(I915_READ(dslreg) != temp, 5))
4413 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4414 }
4415 }
4416
4417 /**
4418 * skl_update_scaler_users - Stages update to crtc's scaler state
4419 * @intel_crtc: crtc
4420 * @crtc_state: crtc_state
4421 * @plane: plane (NULL indicates crtc is requesting update)
4422 * @plane_state: plane's state
4423 * @force_detach: request unconditional detachment of scaler
4424 *
4425 * This function updates scaler state for requested plane or crtc.
4426 * To request scaler usage update for a plane, caller shall pass plane pointer.
4427 * To request scaler usage update for crtc, caller shall pass plane pointer
4428 * as NULL.
4429 *
4430 * Return
4431 * 0 - scaler_usage updated successfully
4432 * error - requested scaling cannot be supported or other error condition
4433 */
4434 int
4435 skl_update_scaler_users(
4436 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4437 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4438 int force_detach)
4439 {
4440 int need_scaling;
4441 int idx;
4442 int src_w, src_h, dst_w, dst_h;
4443 int *scaler_id;
4444 struct drm_framebuffer *fb;
4445 struct intel_crtc_scaler_state *scaler_state;
4446 unsigned int rotation;
4447
4448 if (!intel_crtc || !crtc_state)
4449 return 0;
4450
4451 scaler_state = &crtc_state->scaler_state;
4452
4453 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4454 fb = intel_plane ? plane_state->base.fb : NULL;
4455
4456 if (intel_plane) {
4457 src_w = drm_rect_width(&plane_state->src) >> 16;
4458 src_h = drm_rect_height(&plane_state->src) >> 16;
4459 dst_w = drm_rect_width(&plane_state->dst);
4460 dst_h = drm_rect_height(&plane_state->dst);
4461 scaler_id = &plane_state->scaler_id;
4462 rotation = plane_state->base.rotation;
4463 } else {
4464 struct drm_display_mode *adjusted_mode =
4465 &crtc_state->base.adjusted_mode;
4466 src_w = crtc_state->pipe_src_w;
4467 src_h = crtc_state->pipe_src_h;
4468 dst_w = adjusted_mode->hdisplay;
4469 dst_h = adjusted_mode->vdisplay;
4470 scaler_id = &scaler_state->scaler_id;
4471 rotation = DRM_ROTATE_0;
4472 }
4473
4474 need_scaling = intel_rotation_90_or_270(rotation) ?
4475 (src_h != dst_w || src_w != dst_h):
4476 (src_w != dst_w || src_h != dst_h);
4477
4478 /*
4479 * if plane is being disabled or scaler is no more required or force detach
4480 * - free scaler binded to this plane/crtc
4481 * - in order to do this, update crtc->scaler_usage
4482 *
4483 * Here scaler state in crtc_state is set free so that
4484 * scaler can be assigned to other user. Actual register
4485 * update to free the scaler is done in plane/panel-fit programming.
4486 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4487 */
4488 if (force_detach || !need_scaling || (intel_plane &&
4489 (!fb || !plane_state->visible))) {
4490 if (*scaler_id >= 0) {
4491 scaler_state->scaler_users &= ~(1 << idx);
4492 scaler_state->scalers[*scaler_id].in_use = 0;
4493
4494 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4495 "crtc_state = %p scaler_users = 0x%x\n",
4496 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4497 intel_plane ? intel_plane->base.base.id :
4498 intel_crtc->base.base.id, crtc_state,
4499 scaler_state->scaler_users);
4500 *scaler_id = -1;
4501 }
4502 return 0;
4503 }
4504
4505 /* range checks */
4506 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4507 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4508
4509 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4510 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4511 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4512 "size is out of scaler range\n",
4513 intel_plane ? "PLANE" : "CRTC",
4514 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4515 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4516 return -EINVAL;
4517 }
4518
4519 /* check colorkey */
4520 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4521 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4522 intel_plane->base.base.id);
4523 return -EINVAL;
4524 }
4525
4526 /* Check src format */
4527 if (intel_plane) {
4528 switch (fb->pixel_format) {
4529 case DRM_FORMAT_RGB565:
4530 case DRM_FORMAT_XBGR8888:
4531 case DRM_FORMAT_XRGB8888:
4532 case DRM_FORMAT_ABGR8888:
4533 case DRM_FORMAT_ARGB8888:
4534 case DRM_FORMAT_XRGB2101010:
4535 case DRM_FORMAT_ARGB2101010:
4536 case DRM_FORMAT_XBGR2101010:
4537 case DRM_FORMAT_ABGR2101010:
4538 case DRM_FORMAT_YUYV:
4539 case DRM_FORMAT_YVYU:
4540 case DRM_FORMAT_UYVY:
4541 case DRM_FORMAT_VYUY:
4542 break;
4543 default:
4544 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4545 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4546 return -EINVAL;
4547 }
4548 }
4549
4550 /* mark this plane as a scaler user in crtc_state */
4551 scaler_state->scaler_users |= (1 << idx);
4552 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4553 "crtc_state = %p scaler_users = 0x%x\n",
4554 intel_plane ? "PLANE" : "CRTC",
4555 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4556 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4557 return 0;
4558 }
4559
4560 static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
4561 {
4562 struct drm_device *dev = crtc->base.dev;
4563 struct drm_i915_private *dev_priv = dev->dev_private;
4564 int pipe = crtc->pipe;
4565 struct intel_crtc_scaler_state *scaler_state =
4566 &crtc->config->scaler_state;
4567
4568 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4569
4570 /* To update pfit, first update scaler state */
4571 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4572 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4573 skl_detach_scalers(crtc);
4574 if (!enable)
4575 return;
4576
4577 if (crtc->config->pch_pfit.enabled) {
4578 int id;
4579
4580 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4581 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4582 return;
4583 }
4584
4585 id = scaler_state->scaler_id;
4586 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4587 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4588 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4589 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4590
4591 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4592 }
4593 }
4594
4595 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4596 {
4597 struct drm_device *dev = crtc->base.dev;
4598 struct drm_i915_private *dev_priv = dev->dev_private;
4599 int pipe = crtc->pipe;
4600
4601 if (crtc->config->pch_pfit.enabled) {
4602 /* Force use of hard-coded filter coefficients
4603 * as some pre-programmed values are broken,
4604 * e.g. x201.
4605 */
4606 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4607 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4608 PF_PIPE_SEL_IVB(pipe));
4609 else
4610 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4611 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4612 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4613 }
4614 }
4615
4616 static void intel_enable_sprite_planes(struct drm_crtc *crtc)
4617 {
4618 struct drm_device *dev = crtc->dev;
4619 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4620 struct drm_plane *plane;
4621 struct intel_plane *intel_plane;
4622
4623 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4624 intel_plane = to_intel_plane(plane);
4625 if (intel_plane->pipe == pipe)
4626 intel_plane_restore(&intel_plane->base);
4627 }
4628 }
4629
4630 void hsw_enable_ips(struct intel_crtc *crtc)
4631 {
4632 struct drm_device *dev = crtc->base.dev;
4633 struct drm_i915_private *dev_priv = dev->dev_private;
4634
4635 if (!crtc->config->ips_enabled)
4636 return;
4637
4638 /* We can only enable IPS after we enable a plane and wait for a vblank */
4639 intel_wait_for_vblank(dev, crtc->pipe);
4640
4641 assert_plane_enabled(dev_priv, crtc->plane);
4642 if (IS_BROADWELL(dev)) {
4643 mutex_lock(&dev_priv->rps.hw_lock);
4644 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4645 mutex_unlock(&dev_priv->rps.hw_lock);
4646 /* Quoting Art Runyan: "its not safe to expect any particular
4647 * value in IPS_CTL bit 31 after enabling IPS through the
4648 * mailbox." Moreover, the mailbox may return a bogus state,
4649 * so we need to just enable it and continue on.
4650 */
4651 } else {
4652 I915_WRITE(IPS_CTL, IPS_ENABLE);
4653 /* The bit only becomes 1 in the next vblank, so this wait here
4654 * is essentially intel_wait_for_vblank. If we don't have this
4655 * and don't wait for vblanks until the end of crtc_enable, then
4656 * the HW state readout code will complain that the expected
4657 * IPS_CTL value is not the one we read. */
4658 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4659 DRM_ERROR("Timed out waiting for IPS enable\n");
4660 }
4661 }
4662
4663 void hsw_disable_ips(struct intel_crtc *crtc)
4664 {
4665 struct drm_device *dev = crtc->base.dev;
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667
4668 if (!crtc->config->ips_enabled)
4669 return;
4670
4671 assert_plane_enabled(dev_priv, crtc->plane);
4672 if (IS_BROADWELL(dev)) {
4673 mutex_lock(&dev_priv->rps.hw_lock);
4674 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4675 mutex_unlock(&dev_priv->rps.hw_lock);
4676 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4677 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4678 DRM_ERROR("Timed out waiting for IPS disable\n");
4679 } else {
4680 I915_WRITE(IPS_CTL, 0);
4681 POSTING_READ(IPS_CTL);
4682 }
4683
4684 /* We need to wait for a vblank before we can disable the plane. */
4685 intel_wait_for_vblank(dev, crtc->pipe);
4686 }
4687
4688 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4689 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4690 {
4691 struct drm_device *dev = crtc->dev;
4692 struct drm_i915_private *dev_priv = dev->dev_private;
4693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4694 enum pipe pipe = intel_crtc->pipe;
4695 int palreg = PALETTE(pipe);
4696 int i;
4697 bool reenable_ips = false;
4698
4699 /* The clocks have to be on to load the palette. */
4700 if (!crtc->state->enable || !intel_crtc->active)
4701 return;
4702
4703 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4704 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4705 assert_dsi_pll_enabled(dev_priv);
4706 else
4707 assert_pll_enabled(dev_priv, pipe);
4708 }
4709
4710 /* use legacy palette for Ironlake */
4711 if (!HAS_GMCH_DISPLAY(dev))
4712 palreg = LGC_PALETTE(pipe);
4713
4714 /* Workaround : Do not read or write the pipe palette/gamma data while
4715 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4716 */
4717 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4718 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4719 GAMMA_MODE_MODE_SPLIT)) {
4720 hsw_disable_ips(intel_crtc);
4721 reenable_ips = true;
4722 }
4723
4724 for (i = 0; i < 256; i++) {
4725 I915_WRITE(palreg + 4 * i,
4726 (intel_crtc->lut_r[i] << 16) |
4727 (intel_crtc->lut_g[i] << 8) |
4728 intel_crtc->lut_b[i]);
4729 }
4730
4731 if (reenable_ips)
4732 hsw_enable_ips(intel_crtc);
4733 }
4734
4735 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4736 {
4737 if (intel_crtc->overlay) {
4738 struct drm_device *dev = intel_crtc->base.dev;
4739 struct drm_i915_private *dev_priv = dev->dev_private;
4740
4741 mutex_lock(&dev->struct_mutex);
4742 dev_priv->mm.interruptible = false;
4743 (void) intel_overlay_switch_off(intel_crtc->overlay);
4744 dev_priv->mm.interruptible = true;
4745 mutex_unlock(&dev->struct_mutex);
4746 }
4747
4748 /* Let userspace switch the overlay on again. In most cases userspace
4749 * has to recompute where to put it anyway.
4750 */
4751 }
4752
4753 /**
4754 * intel_post_enable_primary - Perform operations after enabling primary plane
4755 * @crtc: the CRTC whose primary plane was just enabled
4756 *
4757 * Performs potentially sleeping operations that must be done after the primary
4758 * plane is enabled, such as updating FBC and IPS. Note that this may be
4759 * called due to an explicit primary plane update, or due to an implicit
4760 * re-enable that is caused when a sprite plane is updated to no longer
4761 * completely hide the primary plane.
4762 */
4763 static void
4764 intel_post_enable_primary(struct drm_crtc *crtc)
4765 {
4766 struct drm_device *dev = crtc->dev;
4767 struct drm_i915_private *dev_priv = dev->dev_private;
4768 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4769 int pipe = intel_crtc->pipe;
4770
4771 /*
4772 * BDW signals flip done immediately if the plane
4773 * is disabled, even if the plane enable is already
4774 * armed to occur at the next vblank :(
4775 */
4776 if (IS_BROADWELL(dev))
4777 intel_wait_for_vblank(dev, pipe);
4778
4779 /*
4780 * FIXME IPS should be fine as long as one plane is
4781 * enabled, but in practice it seems to have problems
4782 * when going from primary only to sprite only and vice
4783 * versa.
4784 */
4785 hsw_enable_ips(intel_crtc);
4786
4787 mutex_lock(&dev->struct_mutex);
4788 intel_fbc_update(dev);
4789 mutex_unlock(&dev->struct_mutex);
4790
4791 /*
4792 * Gen2 reports pipe underruns whenever all planes are disabled.
4793 * So don't enable underrun reporting before at least some planes
4794 * are enabled.
4795 * FIXME: Need to fix the logic to work when we turn off all planes
4796 * but leave the pipe running.
4797 */
4798 if (IS_GEN2(dev))
4799 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4800
4801 /* Underruns don't raise interrupts, so check manually. */
4802 if (HAS_GMCH_DISPLAY(dev))
4803 i9xx_check_fifo_underruns(dev_priv);
4804 }
4805
4806 /**
4807 * intel_pre_disable_primary - Perform operations before disabling primary plane
4808 * @crtc: the CRTC whose primary plane is to be disabled
4809 *
4810 * Performs potentially sleeping operations that must be done before the
4811 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4812 * be called due to an explicit primary plane update, or due to an implicit
4813 * disable that is caused when a sprite plane completely hides the primary
4814 * plane.
4815 */
4816 static void
4817 intel_pre_disable_primary(struct drm_crtc *crtc)
4818 {
4819 struct drm_device *dev = crtc->dev;
4820 struct drm_i915_private *dev_priv = dev->dev_private;
4821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4822 int pipe = intel_crtc->pipe;
4823
4824 /*
4825 * Gen2 reports pipe underruns whenever all planes are disabled.
4826 * So diasble underrun reporting before all the planes get disabled.
4827 * FIXME: Need to fix the logic to work when we turn off all planes
4828 * but leave the pipe running.
4829 */
4830 if (IS_GEN2(dev))
4831 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4832
4833 /*
4834 * Vblank time updates from the shadow to live plane control register
4835 * are blocked if the memory self-refresh mode is active at that
4836 * moment. So to make sure the plane gets truly disabled, disable
4837 * first the self-refresh mode. The self-refresh enable bit in turn
4838 * will be checked/applied by the HW only at the next frame start
4839 * event which is after the vblank start event, so we need to have a
4840 * wait-for-vblank between disabling the plane and the pipe.
4841 */
4842 if (HAS_GMCH_DISPLAY(dev))
4843 intel_set_memory_cxsr(dev_priv, false);
4844
4845 mutex_lock(&dev->struct_mutex);
4846 if (dev_priv->fbc.crtc == intel_crtc)
4847 intel_fbc_disable(dev);
4848 mutex_unlock(&dev->struct_mutex);
4849
4850 /*
4851 * FIXME IPS should be fine as long as one plane is
4852 * enabled, but in practice it seems to have problems
4853 * when going from primary only to sprite only and vice
4854 * versa.
4855 */
4856 hsw_disable_ips(intel_crtc);
4857 }
4858
4859 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4860 {
4861 intel_enable_primary_hw_plane(crtc->primary, crtc);
4862 intel_enable_sprite_planes(crtc);
4863 intel_crtc_update_cursor(crtc, true);
4864
4865 intel_post_enable_primary(crtc);
4866 }
4867
4868 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4869 {
4870 struct drm_device *dev = crtc->dev;
4871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4872 struct intel_plane *intel_plane;
4873 int pipe = intel_crtc->pipe;
4874
4875 intel_crtc_wait_for_pending_flips(crtc);
4876
4877 intel_pre_disable_primary(crtc);
4878
4879 intel_crtc_dpms_overlay_disable(intel_crtc);
4880 for_each_intel_plane(dev, intel_plane) {
4881 if (intel_plane->pipe == pipe) {
4882 struct drm_crtc *from = intel_plane->base.crtc;
4883
4884 intel_plane->disable_plane(&intel_plane->base,
4885 from ?: crtc, true);
4886 }
4887 }
4888
4889 /*
4890 * FIXME: Once we grow proper nuclear flip support out of this we need
4891 * to compute the mask of flip planes precisely. For the time being
4892 * consider this a flip to a NULL plane.
4893 */
4894 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4895 }
4896
4897 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4898 {
4899 struct drm_device *dev = crtc->dev;
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4902 struct intel_encoder *encoder;
4903 int pipe = intel_crtc->pipe;
4904
4905 WARN_ON(!crtc->state->enable);
4906
4907 if (intel_crtc->active)
4908 return;
4909
4910 if (intel_crtc->config->has_pch_encoder)
4911 intel_prepare_shared_dpll(intel_crtc);
4912
4913 if (intel_crtc->config->has_dp_encoder)
4914 intel_dp_set_m_n(intel_crtc, M1_N1);
4915
4916 intel_set_pipe_timings(intel_crtc);
4917
4918 if (intel_crtc->config->has_pch_encoder) {
4919 intel_cpu_transcoder_set_m_n(intel_crtc,
4920 &intel_crtc->config->fdi_m_n, NULL);
4921 }
4922
4923 ironlake_set_pipeconf(crtc);
4924
4925 intel_crtc->active = true;
4926
4927 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4928 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4929
4930 for_each_encoder_on_crtc(dev, crtc, encoder)
4931 if (encoder->pre_enable)
4932 encoder->pre_enable(encoder);
4933
4934 if (intel_crtc->config->has_pch_encoder) {
4935 /* Note: FDI PLL enabling _must_ be done before we enable the
4936 * cpu pipes, hence this is separate from all the other fdi/pch
4937 * enabling. */
4938 ironlake_fdi_pll_enable(intel_crtc);
4939 } else {
4940 assert_fdi_tx_disabled(dev_priv, pipe);
4941 assert_fdi_rx_disabled(dev_priv, pipe);
4942 }
4943
4944 ironlake_pfit_enable(intel_crtc);
4945
4946 /*
4947 * On ILK+ LUT must be loaded before the pipe is running but with
4948 * clocks enabled
4949 */
4950 intel_crtc_load_lut(crtc);
4951
4952 intel_update_watermarks(crtc);
4953 intel_enable_pipe(intel_crtc);
4954
4955 if (intel_crtc->config->has_pch_encoder)
4956 ironlake_pch_enable(crtc);
4957
4958 assert_vblank_disabled(crtc);
4959 drm_crtc_vblank_on(crtc);
4960
4961 for_each_encoder_on_crtc(dev, crtc, encoder)
4962 encoder->enable(encoder);
4963
4964 if (HAS_PCH_CPT(dev))
4965 cpt_verify_modeset(dev, intel_crtc->pipe);
4966 }
4967
4968 /* IPS only exists on ULT machines and is tied to pipe A. */
4969 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4970 {
4971 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4972 }
4973
4974 /*
4975 * This implements the workaround described in the "notes" section of the mode
4976 * set sequence documentation. When going from no pipes or single pipe to
4977 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4978 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4979 */
4980 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4981 {
4982 struct drm_device *dev = crtc->base.dev;
4983 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4984
4985 /* We want to get the other_active_crtc only if there's only 1 other
4986 * active crtc. */
4987 for_each_intel_crtc(dev, crtc_it) {
4988 if (!crtc_it->active || crtc_it == crtc)
4989 continue;
4990
4991 if (other_active_crtc)
4992 return;
4993
4994 other_active_crtc = crtc_it;
4995 }
4996 if (!other_active_crtc)
4997 return;
4998
4999 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5000 intel_wait_for_vblank(dev, other_active_crtc->pipe);
5001 }
5002
5003 static void haswell_crtc_enable(struct drm_crtc *crtc)
5004 {
5005 struct drm_device *dev = crtc->dev;
5006 struct drm_i915_private *dev_priv = dev->dev_private;
5007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5008 struct intel_encoder *encoder;
5009 int pipe = intel_crtc->pipe;
5010
5011 WARN_ON(!crtc->state->enable);
5012
5013 if (intel_crtc->active)
5014 return;
5015
5016 if (intel_crtc_to_shared_dpll(intel_crtc))
5017 intel_enable_shared_dpll(intel_crtc);
5018
5019 if (intel_crtc->config->has_dp_encoder)
5020 intel_dp_set_m_n(intel_crtc, M1_N1);
5021
5022 intel_set_pipe_timings(intel_crtc);
5023
5024 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5025 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5026 intel_crtc->config->pixel_multiplier - 1);
5027 }
5028
5029 if (intel_crtc->config->has_pch_encoder) {
5030 intel_cpu_transcoder_set_m_n(intel_crtc,
5031 &intel_crtc->config->fdi_m_n, NULL);
5032 }
5033
5034 haswell_set_pipeconf(crtc);
5035
5036 intel_set_pipe_csc(crtc);
5037
5038 intel_crtc->active = true;
5039
5040 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5041 for_each_encoder_on_crtc(dev, crtc, encoder)
5042 if (encoder->pre_enable)
5043 encoder->pre_enable(encoder);
5044
5045 if (intel_crtc->config->has_pch_encoder) {
5046 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5047 true);
5048 dev_priv->display.fdi_link_train(crtc);
5049 }
5050
5051 intel_ddi_enable_pipe_clock(intel_crtc);
5052
5053 if (INTEL_INFO(dev)->gen == 9)
5054 skylake_pfit_update(intel_crtc, 1);
5055 else if (INTEL_INFO(dev)->gen < 9)
5056 ironlake_pfit_enable(intel_crtc);
5057 else
5058 MISSING_CASE(INTEL_INFO(dev)->gen);
5059
5060 /*
5061 * On ILK+ LUT must be loaded before the pipe is running but with
5062 * clocks enabled
5063 */
5064 intel_crtc_load_lut(crtc);
5065
5066 intel_ddi_set_pipe_settings(crtc);
5067 intel_ddi_enable_transcoder_func(crtc);
5068
5069 intel_update_watermarks(crtc);
5070 intel_enable_pipe(intel_crtc);
5071
5072 if (intel_crtc->config->has_pch_encoder)
5073 lpt_pch_enable(crtc);
5074
5075 if (intel_crtc->config->dp_encoder_is_mst)
5076 intel_ddi_set_vc_payload_alloc(crtc, true);
5077
5078 assert_vblank_disabled(crtc);
5079 drm_crtc_vblank_on(crtc);
5080
5081 for_each_encoder_on_crtc(dev, crtc, encoder) {
5082 encoder->enable(encoder);
5083 intel_opregion_notify_encoder(encoder, true);
5084 }
5085
5086 /* If we change the relative order between pipe/planes enabling, we need
5087 * to change the workaround. */
5088 haswell_mode_set_planes_workaround(intel_crtc);
5089 }
5090
5091 static void ironlake_pfit_disable(struct intel_crtc *crtc)
5092 {
5093 struct drm_device *dev = crtc->base.dev;
5094 struct drm_i915_private *dev_priv = dev->dev_private;
5095 int pipe = crtc->pipe;
5096
5097 /* To avoid upsetting the power well on haswell only disable the pfit if
5098 * it's in use. The hw state code will make sure we get this right. */
5099 if (crtc->config->pch_pfit.enabled) {
5100 I915_WRITE(PF_CTL(pipe), 0);
5101 I915_WRITE(PF_WIN_POS(pipe), 0);
5102 I915_WRITE(PF_WIN_SZ(pipe), 0);
5103 }
5104 }
5105
5106 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5107 {
5108 struct drm_device *dev = crtc->dev;
5109 struct drm_i915_private *dev_priv = dev->dev_private;
5110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5111 struct intel_encoder *encoder;
5112 int pipe = intel_crtc->pipe;
5113 u32 reg, temp;
5114
5115 if (!intel_crtc->active)
5116 return;
5117
5118 for_each_encoder_on_crtc(dev, crtc, encoder)
5119 encoder->disable(encoder);
5120
5121 drm_crtc_vblank_off(crtc);
5122 assert_vblank_disabled(crtc);
5123
5124 if (intel_crtc->config->has_pch_encoder)
5125 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5126
5127 intel_disable_pipe(intel_crtc);
5128
5129 ironlake_pfit_disable(intel_crtc);
5130
5131 for_each_encoder_on_crtc(dev, crtc, encoder)
5132 if (encoder->post_disable)
5133 encoder->post_disable(encoder);
5134
5135 if (intel_crtc->config->has_pch_encoder) {
5136 ironlake_fdi_disable(crtc);
5137
5138 ironlake_disable_pch_transcoder(dev_priv, pipe);
5139
5140 if (HAS_PCH_CPT(dev)) {
5141 /* disable TRANS_DP_CTL */
5142 reg = TRANS_DP_CTL(pipe);
5143 temp = I915_READ(reg);
5144 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5145 TRANS_DP_PORT_SEL_MASK);
5146 temp |= TRANS_DP_PORT_SEL_NONE;
5147 I915_WRITE(reg, temp);
5148
5149 /* disable DPLL_SEL */
5150 temp = I915_READ(PCH_DPLL_SEL);
5151 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5152 I915_WRITE(PCH_DPLL_SEL, temp);
5153 }
5154
5155 /* disable PCH DPLL */
5156 intel_disable_shared_dpll(intel_crtc);
5157
5158 ironlake_fdi_pll_disable(intel_crtc);
5159 }
5160
5161 intel_crtc->active = false;
5162 intel_update_watermarks(crtc);
5163
5164 mutex_lock(&dev->struct_mutex);
5165 intel_fbc_update(dev);
5166 mutex_unlock(&dev->struct_mutex);
5167 }
5168
5169 static void haswell_crtc_disable(struct drm_crtc *crtc)
5170 {
5171 struct drm_device *dev = crtc->dev;
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5174 struct intel_encoder *encoder;
5175 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5176
5177 if (!intel_crtc->active)
5178 return;
5179
5180 for_each_encoder_on_crtc(dev, crtc, encoder) {
5181 intel_opregion_notify_encoder(encoder, false);
5182 encoder->disable(encoder);
5183 }
5184
5185 drm_crtc_vblank_off(crtc);
5186 assert_vblank_disabled(crtc);
5187
5188 if (intel_crtc->config->has_pch_encoder)
5189 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5190 false);
5191 intel_disable_pipe(intel_crtc);
5192
5193 if (intel_crtc->config->dp_encoder_is_mst)
5194 intel_ddi_set_vc_payload_alloc(crtc, false);
5195
5196 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5197
5198 if (INTEL_INFO(dev)->gen == 9)
5199 skylake_pfit_update(intel_crtc, 0);
5200 else if (INTEL_INFO(dev)->gen < 9)
5201 ironlake_pfit_disable(intel_crtc);
5202 else
5203 MISSING_CASE(INTEL_INFO(dev)->gen);
5204
5205 intel_ddi_disable_pipe_clock(intel_crtc);
5206
5207 if (intel_crtc->config->has_pch_encoder) {
5208 lpt_disable_pch_transcoder(dev_priv);
5209 intel_ddi_fdi_disable(crtc);
5210 }
5211
5212 for_each_encoder_on_crtc(dev, crtc, encoder)
5213 if (encoder->post_disable)
5214 encoder->post_disable(encoder);
5215
5216 intel_crtc->active = false;
5217 intel_update_watermarks(crtc);
5218
5219 mutex_lock(&dev->struct_mutex);
5220 intel_fbc_update(dev);
5221 mutex_unlock(&dev->struct_mutex);
5222
5223 if (intel_crtc_to_shared_dpll(intel_crtc))
5224 intel_disable_shared_dpll(intel_crtc);
5225 }
5226
5227 static void ironlake_crtc_off(struct drm_crtc *crtc)
5228 {
5229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5230 intel_put_shared_dpll(intel_crtc);
5231 }
5232
5233
5234 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5235 {
5236 struct drm_device *dev = crtc->base.dev;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 struct intel_crtc_state *pipe_config = crtc->config;
5239
5240 if (!pipe_config->gmch_pfit.control)
5241 return;
5242
5243 /*
5244 * The panel fitter should only be adjusted whilst the pipe is disabled,
5245 * according to register description and PRM.
5246 */
5247 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5248 assert_pipe_disabled(dev_priv, crtc->pipe);
5249
5250 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5251 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5252
5253 /* Border color in case we don't scale up to the full screen. Black by
5254 * default, change to something else for debugging. */
5255 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5256 }
5257
5258 static enum intel_display_power_domain port_to_power_domain(enum port port)
5259 {
5260 switch (port) {
5261 case PORT_A:
5262 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5263 case PORT_B:
5264 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5265 case PORT_C:
5266 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5267 case PORT_D:
5268 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5269 default:
5270 WARN_ON_ONCE(1);
5271 return POWER_DOMAIN_PORT_OTHER;
5272 }
5273 }
5274
5275 #define for_each_power_domain(domain, mask) \
5276 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5277 if ((1 << (domain)) & (mask))
5278
5279 enum intel_display_power_domain
5280 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5281 {
5282 struct drm_device *dev = intel_encoder->base.dev;
5283 struct intel_digital_port *intel_dig_port;
5284
5285 switch (intel_encoder->type) {
5286 case INTEL_OUTPUT_UNKNOWN:
5287 /* Only DDI platforms should ever use this output type */
5288 WARN_ON_ONCE(!HAS_DDI(dev));
5289 case INTEL_OUTPUT_DISPLAYPORT:
5290 case INTEL_OUTPUT_HDMI:
5291 case INTEL_OUTPUT_EDP:
5292 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5293 return port_to_power_domain(intel_dig_port->port);
5294 case INTEL_OUTPUT_DP_MST:
5295 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5296 return port_to_power_domain(intel_dig_port->port);
5297 case INTEL_OUTPUT_ANALOG:
5298 return POWER_DOMAIN_PORT_CRT;
5299 case INTEL_OUTPUT_DSI:
5300 return POWER_DOMAIN_PORT_DSI;
5301 default:
5302 return POWER_DOMAIN_PORT_OTHER;
5303 }
5304 }
5305
5306 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5307 {
5308 struct drm_device *dev = crtc->dev;
5309 struct intel_encoder *intel_encoder;
5310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5311 enum pipe pipe = intel_crtc->pipe;
5312 unsigned long mask;
5313 enum transcoder transcoder;
5314
5315 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5316
5317 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5318 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5319 if (intel_crtc->config->pch_pfit.enabled ||
5320 intel_crtc->config->pch_pfit.force_thru)
5321 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5322
5323 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5324 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5325
5326 return mask;
5327 }
5328
5329 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5330 {
5331 struct drm_device *dev = state->dev;
5332 struct drm_i915_private *dev_priv = dev->dev_private;
5333 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5334 struct intel_crtc *crtc;
5335
5336 /*
5337 * First get all needed power domains, then put all unneeded, to avoid
5338 * any unnecessary toggling of the power wells.
5339 */
5340 for_each_intel_crtc(dev, crtc) {
5341 enum intel_display_power_domain domain;
5342
5343 if (!crtc->base.state->enable)
5344 continue;
5345
5346 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
5347
5348 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5349 intel_display_power_get(dev_priv, domain);
5350 }
5351
5352 if (dev_priv->display.modeset_global_resources)
5353 dev_priv->display.modeset_global_resources(state);
5354
5355 for_each_intel_crtc(dev, crtc) {
5356 enum intel_display_power_domain domain;
5357
5358 for_each_power_domain(domain, crtc->enabled_power_domains)
5359 intel_display_power_put(dev_priv, domain);
5360
5361 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5362 }
5363
5364 intel_display_set_init_power(dev_priv, false);
5365 }
5366
5367 void broxton_set_cdclk(struct drm_device *dev, int frequency)
5368 {
5369 struct drm_i915_private *dev_priv = dev->dev_private;
5370 uint32_t divider;
5371 uint32_t ratio;
5372 uint32_t current_freq;
5373 int ret;
5374
5375 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5376 switch (frequency) {
5377 case 144000:
5378 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5379 ratio = BXT_DE_PLL_RATIO(60);
5380 break;
5381 case 288000:
5382 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5383 ratio = BXT_DE_PLL_RATIO(60);
5384 break;
5385 case 384000:
5386 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5387 ratio = BXT_DE_PLL_RATIO(60);
5388 break;
5389 case 576000:
5390 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5391 ratio = BXT_DE_PLL_RATIO(60);
5392 break;
5393 case 624000:
5394 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5395 ratio = BXT_DE_PLL_RATIO(65);
5396 break;
5397 case 19200:
5398 /*
5399 * Bypass frequency with DE PLL disabled. Init ratio, divider
5400 * to suppress GCC warning.
5401 */
5402 ratio = 0;
5403 divider = 0;
5404 break;
5405 default:
5406 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5407
5408 return;
5409 }
5410
5411 mutex_lock(&dev_priv->rps.hw_lock);
5412 /* Inform power controller of upcoming frequency change */
5413 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5414 0x80000000);
5415 mutex_unlock(&dev_priv->rps.hw_lock);
5416
5417 if (ret) {
5418 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5419 ret, frequency);
5420 return;
5421 }
5422
5423 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5424 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5425 current_freq = current_freq * 500 + 1000;
5426
5427 /*
5428 * DE PLL has to be disabled when
5429 * - setting to 19.2MHz (bypass, PLL isn't used)
5430 * - before setting to 624MHz (PLL needs toggling)
5431 * - before setting to any frequency from 624MHz (PLL needs toggling)
5432 */
5433 if (frequency == 19200 || frequency == 624000 ||
5434 current_freq == 624000) {
5435 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5436 /* Timeout 200us */
5437 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5438 1))
5439 DRM_ERROR("timout waiting for DE PLL unlock\n");
5440 }
5441
5442 if (frequency != 19200) {
5443 uint32_t val;
5444
5445 val = I915_READ(BXT_DE_PLL_CTL);
5446 val &= ~BXT_DE_PLL_RATIO_MASK;
5447 val |= ratio;
5448 I915_WRITE(BXT_DE_PLL_CTL, val);
5449
5450 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5451 /* Timeout 200us */
5452 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5453 DRM_ERROR("timeout waiting for DE PLL lock\n");
5454
5455 val = I915_READ(CDCLK_CTL);
5456 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5457 val |= divider;
5458 /*
5459 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5460 * enable otherwise.
5461 */
5462 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5463 if (frequency >= 500000)
5464 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5465
5466 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5467 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5468 val |= (frequency - 1000) / 500;
5469 I915_WRITE(CDCLK_CTL, val);
5470 }
5471
5472 mutex_lock(&dev_priv->rps.hw_lock);
5473 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5474 DIV_ROUND_UP(frequency, 25000));
5475 mutex_unlock(&dev_priv->rps.hw_lock);
5476
5477 if (ret) {
5478 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5479 ret, frequency);
5480 return;
5481 }
5482
5483 dev_priv->cdclk_freq = frequency;
5484 }
5485
5486 void broxton_init_cdclk(struct drm_device *dev)
5487 {
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 uint32_t val;
5490
5491 /*
5492 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5493 * or else the reset will hang because there is no PCH to respond.
5494 * Move the handshake programming to initialization sequence.
5495 * Previously was left up to BIOS.
5496 */
5497 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5498 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5499 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5500
5501 /* Enable PG1 for cdclk */
5502 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5503
5504 /* check if cd clock is enabled */
5505 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5506 DRM_DEBUG_KMS("Display already initialized\n");
5507 return;
5508 }
5509
5510 /*
5511 * FIXME:
5512 * - The initial CDCLK needs to be read from VBT.
5513 * Need to make this change after VBT has changes for BXT.
5514 * - check if setting the max (or any) cdclk freq is really necessary
5515 * here, it belongs to modeset time
5516 */
5517 broxton_set_cdclk(dev, 624000);
5518
5519 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5520 POSTING_READ(DBUF_CTL);
5521
5522 udelay(10);
5523
5524 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5525 DRM_ERROR("DBuf power enable timeout!\n");
5526 }
5527
5528 void broxton_uninit_cdclk(struct drm_device *dev)
5529 {
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531
5532 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5533 POSTING_READ(DBUF_CTL);
5534
5535 udelay(10);
5536
5537 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5538 DRM_ERROR("DBuf power disable timeout!\n");
5539
5540 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5541 broxton_set_cdclk(dev, 19200);
5542
5543 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5544 }
5545
5546 /* returns HPLL frequency in kHz */
5547 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
5548 {
5549 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
5550
5551 /* Obtain SKU information */
5552 mutex_lock(&dev_priv->dpio_lock);
5553 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5554 CCK_FUSE_HPLL_FREQ_MASK;
5555 mutex_unlock(&dev_priv->dpio_lock);
5556
5557 return vco_freq[hpll_freq] * 1000;
5558 }
5559
5560 static void vlv_update_cdclk(struct drm_device *dev)
5561 {
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563
5564 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5565 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5566 dev_priv->cdclk_freq);
5567
5568 /*
5569 * Program the gmbus_freq based on the cdclk frequency.
5570 * BSpec erroneously claims we should aim for 4MHz, but
5571 * in fact 1MHz is the correct frequency.
5572 */
5573 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5574 }
5575
5576 /* Adjust CDclk dividers to allow high res or save power if possible */
5577 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5578 {
5579 struct drm_i915_private *dev_priv = dev->dev_private;
5580 u32 val, cmd;
5581
5582 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5583 != dev_priv->cdclk_freq);
5584
5585 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5586 cmd = 2;
5587 else if (cdclk == 266667)
5588 cmd = 1;
5589 else
5590 cmd = 0;
5591
5592 mutex_lock(&dev_priv->rps.hw_lock);
5593 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5594 val &= ~DSPFREQGUAR_MASK;
5595 val |= (cmd << DSPFREQGUAR_SHIFT);
5596 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5597 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5598 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5599 50)) {
5600 DRM_ERROR("timed out waiting for CDclk change\n");
5601 }
5602 mutex_unlock(&dev_priv->rps.hw_lock);
5603
5604 if (cdclk == 400000) {
5605 u32 divider;
5606
5607 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5608
5609 mutex_lock(&dev_priv->dpio_lock);
5610 /* adjust cdclk divider */
5611 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5612 val &= ~DISPLAY_FREQUENCY_VALUES;
5613 val |= divider;
5614 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5615
5616 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5617 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5618 50))
5619 DRM_ERROR("timed out waiting for CDclk change\n");
5620 mutex_unlock(&dev_priv->dpio_lock);
5621 }
5622
5623 mutex_lock(&dev_priv->dpio_lock);
5624 /* adjust self-refresh exit latency value */
5625 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5626 val &= ~0x7f;
5627
5628 /*
5629 * For high bandwidth configs, we set a higher latency in the bunit
5630 * so that the core display fetch happens in time to avoid underruns.
5631 */
5632 if (cdclk == 400000)
5633 val |= 4500 / 250; /* 4.5 usec */
5634 else
5635 val |= 3000 / 250; /* 3.0 usec */
5636 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5637 mutex_unlock(&dev_priv->dpio_lock);
5638
5639 vlv_update_cdclk(dev);
5640 }
5641
5642 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5643 {
5644 struct drm_i915_private *dev_priv = dev->dev_private;
5645 u32 val, cmd;
5646
5647 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5648 != dev_priv->cdclk_freq);
5649
5650 switch (cdclk) {
5651 case 333333:
5652 case 320000:
5653 case 266667:
5654 case 200000:
5655 break;
5656 default:
5657 MISSING_CASE(cdclk);
5658 return;
5659 }
5660
5661 /*
5662 * Specs are full of misinformation, but testing on actual
5663 * hardware has shown that we just need to write the desired
5664 * CCK divider into the Punit register.
5665 */
5666 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5667
5668 mutex_lock(&dev_priv->rps.hw_lock);
5669 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5670 val &= ~DSPFREQGUAR_MASK_CHV;
5671 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5672 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5673 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5674 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5675 50)) {
5676 DRM_ERROR("timed out waiting for CDclk change\n");
5677 }
5678 mutex_unlock(&dev_priv->rps.hw_lock);
5679
5680 vlv_update_cdclk(dev);
5681 }
5682
5683 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5684 int max_pixclk)
5685 {
5686 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
5687 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
5688
5689 /*
5690 * Really only a few cases to deal with, as only 4 CDclks are supported:
5691 * 200MHz
5692 * 267MHz
5693 * 320/333MHz (depends on HPLL freq)
5694 * 400MHz (VLV only)
5695 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5696 * of the lower bin and adjust if needed.
5697 *
5698 * We seem to get an unstable or solid color picture at 200MHz.
5699 * Not sure what's wrong. For now use 200MHz only when all pipes
5700 * are off.
5701 */
5702 if (!IS_CHERRYVIEW(dev_priv) &&
5703 max_pixclk > freq_320*limit/100)
5704 return 400000;
5705 else if (max_pixclk > 266667*limit/100)
5706 return freq_320;
5707 else if (max_pixclk > 0)
5708 return 266667;
5709 else
5710 return 200000;
5711 }
5712
5713 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5714 int max_pixclk)
5715 {
5716 /*
5717 * FIXME:
5718 * - remove the guardband, it's not needed on BXT
5719 * - set 19.2MHz bypass frequency if there are no active pipes
5720 */
5721 if (max_pixclk > 576000*9/10)
5722 return 624000;
5723 else if (max_pixclk > 384000*9/10)
5724 return 576000;
5725 else if (max_pixclk > 288000*9/10)
5726 return 384000;
5727 else if (max_pixclk > 144000*9/10)
5728 return 288000;
5729 else
5730 return 144000;
5731 }
5732
5733 /* Compute the max pixel clock for new configuration. Uses atomic state if
5734 * that's non-NULL, look at current state otherwise. */
5735 static int intel_mode_max_pixclk(struct drm_device *dev,
5736 struct drm_atomic_state *state)
5737 {
5738 struct intel_crtc *intel_crtc;
5739 struct intel_crtc_state *crtc_state;
5740 int max_pixclk = 0;
5741
5742 for_each_intel_crtc(dev, intel_crtc) {
5743 if (state)
5744 crtc_state =
5745 intel_atomic_get_crtc_state(state, intel_crtc);
5746 else
5747 crtc_state = intel_crtc->config;
5748 if (IS_ERR(crtc_state))
5749 return PTR_ERR(crtc_state);
5750
5751 if (!crtc_state->base.enable)
5752 continue;
5753
5754 max_pixclk = max(max_pixclk,
5755 crtc_state->base.adjusted_mode.crtc_clock);
5756 }
5757
5758 return max_pixclk;
5759 }
5760
5761 static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
5762 {
5763 struct drm_i915_private *dev_priv = to_i915(state->dev);
5764 struct drm_crtc *crtc;
5765 struct drm_crtc_state *crtc_state;
5766 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
5767 int cdclk, i;
5768
5769 if (max_pixclk < 0)
5770 return max_pixclk;
5771
5772 if (IS_VALLEYVIEW(dev_priv))
5773 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5774 else
5775 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5776
5777 if (cdclk == dev_priv->cdclk_freq)
5778 return 0;
5779
5780 /* add all active pipes to the state */
5781 for_each_crtc(state->dev, crtc) {
5782 if (!crtc->state->enable)
5783 continue;
5784
5785 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5786 if (IS_ERR(crtc_state))
5787 return PTR_ERR(crtc_state);
5788 }
5789
5790 /* disable/enable all currently active pipes while we change cdclk */
5791 for_each_crtc_in_state(state, crtc, crtc_state, i)
5792 if (crtc_state->enable)
5793 crtc_state->mode_changed = true;
5794
5795 return 0;
5796 }
5797
5798 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5799 {
5800 unsigned int credits, default_credits;
5801
5802 if (IS_CHERRYVIEW(dev_priv))
5803 default_credits = PFI_CREDIT(12);
5804 else
5805 default_credits = PFI_CREDIT(8);
5806
5807 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5808 /* CHV suggested value is 31 or 63 */
5809 if (IS_CHERRYVIEW(dev_priv))
5810 credits = PFI_CREDIT_31;
5811 else
5812 credits = PFI_CREDIT(15);
5813 } else {
5814 credits = default_credits;
5815 }
5816
5817 /*
5818 * WA - write default credits before re-programming
5819 * FIXME: should we also set the resend bit here?
5820 */
5821 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5822 default_credits);
5823
5824 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5825 credits | PFI_CREDIT_RESEND);
5826
5827 /*
5828 * FIXME is this guaranteed to clear
5829 * immediately or should we poll for it?
5830 */
5831 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5832 }
5833
5834 static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
5835 {
5836 struct drm_device *dev = old_state->dev;
5837 struct drm_i915_private *dev_priv = dev->dev_private;
5838 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
5839 int req_cdclk;
5840
5841 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5842 * never fail. */
5843 if (WARN_ON(max_pixclk < 0))
5844 return;
5845
5846 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5847
5848 if (req_cdclk != dev_priv->cdclk_freq) {
5849 /*
5850 * FIXME: We can end up here with all power domains off, yet
5851 * with a CDCLK frequency other than the minimum. To account
5852 * for this take the PIPE-A power domain, which covers the HW
5853 * blocks needed for the following programming. This can be
5854 * removed once it's guaranteed that we get here either with
5855 * the minimum CDCLK set, or the required power domains
5856 * enabled.
5857 */
5858 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5859
5860 if (IS_CHERRYVIEW(dev))
5861 cherryview_set_cdclk(dev, req_cdclk);
5862 else
5863 valleyview_set_cdclk(dev, req_cdclk);
5864
5865 vlv_program_pfi_credits(dev_priv);
5866
5867 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
5868 }
5869 }
5870
5871 static void valleyview_crtc_enable(struct drm_crtc *crtc)
5872 {
5873 struct drm_device *dev = crtc->dev;
5874 struct drm_i915_private *dev_priv = to_i915(dev);
5875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5876 struct intel_encoder *encoder;
5877 int pipe = intel_crtc->pipe;
5878 bool is_dsi;
5879
5880 WARN_ON(!crtc->state->enable);
5881
5882 if (intel_crtc->active)
5883 return;
5884
5885 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
5886
5887 if (!is_dsi) {
5888 if (IS_CHERRYVIEW(dev))
5889 chv_prepare_pll(intel_crtc, intel_crtc->config);
5890 else
5891 vlv_prepare_pll(intel_crtc, intel_crtc->config);
5892 }
5893
5894 if (intel_crtc->config->has_dp_encoder)
5895 intel_dp_set_m_n(intel_crtc, M1_N1);
5896
5897 intel_set_pipe_timings(intel_crtc);
5898
5899 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5900 struct drm_i915_private *dev_priv = dev->dev_private;
5901
5902 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5903 I915_WRITE(CHV_CANVAS(pipe), 0);
5904 }
5905
5906 i9xx_set_pipeconf(intel_crtc);
5907
5908 intel_crtc->active = true;
5909
5910 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5911
5912 for_each_encoder_on_crtc(dev, crtc, encoder)
5913 if (encoder->pre_pll_enable)
5914 encoder->pre_pll_enable(encoder);
5915
5916 if (!is_dsi) {
5917 if (IS_CHERRYVIEW(dev))
5918 chv_enable_pll(intel_crtc, intel_crtc->config);
5919 else
5920 vlv_enable_pll(intel_crtc, intel_crtc->config);
5921 }
5922
5923 for_each_encoder_on_crtc(dev, crtc, encoder)
5924 if (encoder->pre_enable)
5925 encoder->pre_enable(encoder);
5926
5927 i9xx_pfit_enable(intel_crtc);
5928
5929 intel_crtc_load_lut(crtc);
5930
5931 intel_update_watermarks(crtc);
5932 intel_enable_pipe(intel_crtc);
5933
5934 assert_vblank_disabled(crtc);
5935 drm_crtc_vblank_on(crtc);
5936
5937 for_each_encoder_on_crtc(dev, crtc, encoder)
5938 encoder->enable(encoder);
5939 }
5940
5941 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5942 {
5943 struct drm_device *dev = crtc->base.dev;
5944 struct drm_i915_private *dev_priv = dev->dev_private;
5945
5946 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5947 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
5948 }
5949
5950 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5951 {
5952 struct drm_device *dev = crtc->dev;
5953 struct drm_i915_private *dev_priv = to_i915(dev);
5954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5955 struct intel_encoder *encoder;
5956 int pipe = intel_crtc->pipe;
5957
5958 WARN_ON(!crtc->state->enable);
5959
5960 if (intel_crtc->active)
5961 return;
5962
5963 i9xx_set_pll_dividers(intel_crtc);
5964
5965 if (intel_crtc->config->has_dp_encoder)
5966 intel_dp_set_m_n(intel_crtc, M1_N1);
5967
5968 intel_set_pipe_timings(intel_crtc);
5969
5970 i9xx_set_pipeconf(intel_crtc);
5971
5972 intel_crtc->active = true;
5973
5974 if (!IS_GEN2(dev))
5975 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5976
5977 for_each_encoder_on_crtc(dev, crtc, encoder)
5978 if (encoder->pre_enable)
5979 encoder->pre_enable(encoder);
5980
5981 i9xx_enable_pll(intel_crtc);
5982
5983 i9xx_pfit_enable(intel_crtc);
5984
5985 intel_crtc_load_lut(crtc);
5986
5987 intel_update_watermarks(crtc);
5988 intel_enable_pipe(intel_crtc);
5989
5990 assert_vblank_disabled(crtc);
5991 drm_crtc_vblank_on(crtc);
5992
5993 for_each_encoder_on_crtc(dev, crtc, encoder)
5994 encoder->enable(encoder);
5995 }
5996
5997 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5998 {
5999 struct drm_device *dev = crtc->base.dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001
6002 if (!crtc->config->gmch_pfit.control)
6003 return;
6004
6005 assert_pipe_disabled(dev_priv, crtc->pipe);
6006
6007 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6008 I915_READ(PFIT_CONTROL));
6009 I915_WRITE(PFIT_CONTROL, 0);
6010 }
6011
6012 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6013 {
6014 struct drm_device *dev = crtc->dev;
6015 struct drm_i915_private *dev_priv = dev->dev_private;
6016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6017 struct intel_encoder *encoder;
6018 int pipe = intel_crtc->pipe;
6019
6020 if (!intel_crtc->active)
6021 return;
6022
6023 /*
6024 * On gen2 planes are double buffered but the pipe isn't, so we must
6025 * wait for planes to fully turn off before disabling the pipe.
6026 * We also need to wait on all gmch platforms because of the
6027 * self-refresh mode constraint explained above.
6028 */
6029 intel_wait_for_vblank(dev, pipe);
6030
6031 for_each_encoder_on_crtc(dev, crtc, encoder)
6032 encoder->disable(encoder);
6033
6034 drm_crtc_vblank_off(crtc);
6035 assert_vblank_disabled(crtc);
6036
6037 intel_disable_pipe(intel_crtc);
6038
6039 i9xx_pfit_disable(intel_crtc);
6040
6041 for_each_encoder_on_crtc(dev, crtc, encoder)
6042 if (encoder->post_disable)
6043 encoder->post_disable(encoder);
6044
6045 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
6046 if (IS_CHERRYVIEW(dev))
6047 chv_disable_pll(dev_priv, pipe);
6048 else if (IS_VALLEYVIEW(dev))
6049 vlv_disable_pll(dev_priv, pipe);
6050 else
6051 i9xx_disable_pll(intel_crtc);
6052 }
6053
6054 if (!IS_GEN2(dev))
6055 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6056
6057 intel_crtc->active = false;
6058 intel_update_watermarks(crtc);
6059
6060 mutex_lock(&dev->struct_mutex);
6061 intel_fbc_update(dev);
6062 mutex_unlock(&dev->struct_mutex);
6063 }
6064
6065 static void i9xx_crtc_off(struct drm_crtc *crtc)
6066 {
6067 }
6068
6069 /* Master function to enable/disable CRTC and corresponding power wells */
6070 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
6071 {
6072 struct drm_device *dev = crtc->dev;
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6075 enum intel_display_power_domain domain;
6076 unsigned long domains;
6077
6078 if (enable) {
6079 if (!intel_crtc->active) {
6080 domains = get_crtc_power_domains(crtc);
6081 for_each_power_domain(domain, domains)
6082 intel_display_power_get(dev_priv, domain);
6083 intel_crtc->enabled_power_domains = domains;
6084
6085 dev_priv->display.crtc_enable(crtc);
6086 intel_crtc_enable_planes(crtc);
6087 }
6088 } else {
6089 if (intel_crtc->active) {
6090 intel_crtc_disable_planes(crtc);
6091 dev_priv->display.crtc_disable(crtc);
6092
6093 domains = intel_crtc->enabled_power_domains;
6094 for_each_power_domain(domain, domains)
6095 intel_display_power_put(dev_priv, domain);
6096 intel_crtc->enabled_power_domains = 0;
6097 }
6098 }
6099 }
6100
6101 /**
6102 * Sets the power management mode of the pipe and plane.
6103 */
6104 void intel_crtc_update_dpms(struct drm_crtc *crtc)
6105 {
6106 struct drm_device *dev = crtc->dev;
6107 struct intel_encoder *intel_encoder;
6108 bool enable = false;
6109
6110 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6111 enable |= intel_encoder->connectors_active;
6112
6113 intel_crtc_control(crtc, enable);
6114
6115 crtc->state->active = enable;
6116 }
6117
6118 static void intel_crtc_disable(struct drm_crtc *crtc)
6119 {
6120 struct drm_device *dev = crtc->dev;
6121 struct drm_connector *connector;
6122 struct drm_i915_private *dev_priv = dev->dev_private;
6123
6124 /* crtc should still be enabled when we disable it. */
6125 WARN_ON(!crtc->state->enable);
6126
6127 intel_crtc_disable_planes(crtc);
6128 dev_priv->display.crtc_disable(crtc);
6129 dev_priv->display.off(crtc);
6130
6131 drm_plane_helper_disable(crtc->primary);
6132
6133 /* Update computed state. */
6134 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6135 if (!connector->encoder || !connector->encoder->crtc)
6136 continue;
6137
6138 if (connector->encoder->crtc != crtc)
6139 continue;
6140
6141 connector->dpms = DRM_MODE_DPMS_OFF;
6142 to_intel_encoder(connector->encoder)->connectors_active = false;
6143 }
6144 }
6145
6146 void intel_encoder_destroy(struct drm_encoder *encoder)
6147 {
6148 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6149
6150 drm_encoder_cleanup(encoder);
6151 kfree(intel_encoder);
6152 }
6153
6154 /* Simple dpms helper for encoders with just one connector, no cloning and only
6155 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6156 * state of the entire output pipe. */
6157 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
6158 {
6159 if (mode == DRM_MODE_DPMS_ON) {
6160 encoder->connectors_active = true;
6161
6162 intel_crtc_update_dpms(encoder->base.crtc);
6163 } else {
6164 encoder->connectors_active = false;
6165
6166 intel_crtc_update_dpms(encoder->base.crtc);
6167 }
6168 }
6169
6170 /* Cross check the actual hw state with our own modeset state tracking (and it's
6171 * internal consistency). */
6172 static void intel_connector_check_state(struct intel_connector *connector)
6173 {
6174 if (connector->get_hw_state(connector)) {
6175 struct intel_encoder *encoder = connector->encoder;
6176 struct drm_crtc *crtc;
6177 bool encoder_enabled;
6178 enum pipe pipe;
6179
6180 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6181 connector->base.base.id,
6182 connector->base.name);
6183
6184 /* there is no real hw state for MST connectors */
6185 if (connector->mst_port)
6186 return;
6187
6188 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
6189 "wrong connector dpms state\n");
6190 I915_STATE_WARN(connector->base.encoder != &encoder->base,
6191 "active connector not linked to encoder\n");
6192
6193 if (encoder) {
6194 I915_STATE_WARN(!encoder->connectors_active,
6195 "encoder->connectors_active not set\n");
6196
6197 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
6198 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6199 if (I915_STATE_WARN_ON(!encoder->base.crtc))
6200 return;
6201
6202 crtc = encoder->base.crtc;
6203
6204 I915_STATE_WARN(!crtc->state->enable,
6205 "crtc not enabled\n");
6206 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6207 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
6208 "encoder active on the wrong pipe\n");
6209 }
6210 }
6211 }
6212
6213 int intel_connector_init(struct intel_connector *connector)
6214 {
6215 struct drm_connector_state *connector_state;
6216
6217 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6218 if (!connector_state)
6219 return -ENOMEM;
6220
6221 connector->base.state = connector_state;
6222 return 0;
6223 }
6224
6225 struct intel_connector *intel_connector_alloc(void)
6226 {
6227 struct intel_connector *connector;
6228
6229 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6230 if (!connector)
6231 return NULL;
6232
6233 if (intel_connector_init(connector) < 0) {
6234 kfree(connector);
6235 return NULL;
6236 }
6237
6238 return connector;
6239 }
6240
6241 /* Even simpler default implementation, if there's really no special case to
6242 * consider. */
6243 void intel_connector_dpms(struct drm_connector *connector, int mode)
6244 {
6245 /* All the simple cases only support two dpms states. */
6246 if (mode != DRM_MODE_DPMS_ON)
6247 mode = DRM_MODE_DPMS_OFF;
6248
6249 if (mode == connector->dpms)
6250 return;
6251
6252 connector->dpms = mode;
6253
6254 /* Only need to change hw state when actually enabled */
6255 if (connector->encoder)
6256 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
6257
6258 intel_modeset_check_state(connector->dev);
6259 }
6260
6261 /* Simple connector->get_hw_state implementation for encoders that support only
6262 * one connector and no cloning and hence the encoder state determines the state
6263 * of the connector. */
6264 bool intel_connector_get_hw_state(struct intel_connector *connector)
6265 {
6266 enum pipe pipe = 0;
6267 struct intel_encoder *encoder = connector->encoder;
6268
6269 return encoder->get_hw_state(encoder, &pipe);
6270 }
6271
6272 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6273 {
6274 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6275 return crtc_state->fdi_lanes;
6276
6277 return 0;
6278 }
6279
6280 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6281 struct intel_crtc_state *pipe_config)
6282 {
6283 struct drm_atomic_state *state = pipe_config->base.state;
6284 struct intel_crtc *other_crtc;
6285 struct intel_crtc_state *other_crtc_state;
6286
6287 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6288 pipe_name(pipe), pipe_config->fdi_lanes);
6289 if (pipe_config->fdi_lanes > 4) {
6290 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6291 pipe_name(pipe), pipe_config->fdi_lanes);
6292 return -EINVAL;
6293 }
6294
6295 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6296 if (pipe_config->fdi_lanes > 2) {
6297 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6298 pipe_config->fdi_lanes);
6299 return -EINVAL;
6300 } else {
6301 return 0;
6302 }
6303 }
6304
6305 if (INTEL_INFO(dev)->num_pipes == 2)
6306 return 0;
6307
6308 /* Ivybridge 3 pipe is really complicated */
6309 switch (pipe) {
6310 case PIPE_A:
6311 return 0;
6312 case PIPE_B:
6313 if (pipe_config->fdi_lanes <= 2)
6314 return 0;
6315
6316 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6317 other_crtc_state =
6318 intel_atomic_get_crtc_state(state, other_crtc);
6319 if (IS_ERR(other_crtc_state))
6320 return PTR_ERR(other_crtc_state);
6321
6322 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6323 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6324 pipe_name(pipe), pipe_config->fdi_lanes);
6325 return -EINVAL;
6326 }
6327 return 0;
6328 case PIPE_C:
6329 if (pipe_config->fdi_lanes > 2) {
6330 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6331 pipe_name(pipe), pipe_config->fdi_lanes);
6332 return -EINVAL;
6333 }
6334
6335 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6336 other_crtc_state =
6337 intel_atomic_get_crtc_state(state, other_crtc);
6338 if (IS_ERR(other_crtc_state))
6339 return PTR_ERR(other_crtc_state);
6340
6341 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6342 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6343 return -EINVAL;
6344 }
6345 return 0;
6346 default:
6347 BUG();
6348 }
6349 }
6350
6351 #define RETRY 1
6352 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6353 struct intel_crtc_state *pipe_config)
6354 {
6355 struct drm_device *dev = intel_crtc->base.dev;
6356 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6357 int lane, link_bw, fdi_dotclock, ret;
6358 bool needs_recompute = false;
6359
6360 retry:
6361 /* FDI is a binary signal running at ~2.7GHz, encoding
6362 * each output octet as 10 bits. The actual frequency
6363 * is stored as a divider into a 100MHz clock, and the
6364 * mode pixel clock is stored in units of 1KHz.
6365 * Hence the bw of each lane in terms of the mode signal
6366 * is:
6367 */
6368 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6369
6370 fdi_dotclock = adjusted_mode->crtc_clock;
6371
6372 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6373 pipe_config->pipe_bpp);
6374
6375 pipe_config->fdi_lanes = lane;
6376
6377 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6378 link_bw, &pipe_config->fdi_m_n);
6379
6380 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6381 intel_crtc->pipe, pipe_config);
6382 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6383 pipe_config->pipe_bpp -= 2*3;
6384 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6385 pipe_config->pipe_bpp);
6386 needs_recompute = true;
6387 pipe_config->bw_constrained = true;
6388
6389 goto retry;
6390 }
6391
6392 if (needs_recompute)
6393 return RETRY;
6394
6395 return ret;
6396 }
6397
6398 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6399 struct intel_crtc_state *pipe_config)
6400 {
6401 pipe_config->ips_enabled = i915.enable_ips &&
6402 hsw_crtc_supports_ips(crtc) &&
6403 pipe_config->pipe_bpp <= 24;
6404 }
6405
6406 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6407 struct intel_crtc_state *pipe_config)
6408 {
6409 struct drm_device *dev = crtc->base.dev;
6410 struct drm_i915_private *dev_priv = dev->dev_private;
6411 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6412 int ret;
6413
6414 /* FIXME should check pixel clock limits on all platforms */
6415 if (INTEL_INFO(dev)->gen < 4) {
6416 int clock_limit =
6417 dev_priv->display.get_display_clock_speed(dev);
6418
6419 /*
6420 * Enable pixel doubling when the dot clock
6421 * is > 90% of the (display) core speed.
6422 *
6423 * GDG double wide on either pipe,
6424 * otherwise pipe A only.
6425 */
6426 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
6427 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
6428 clock_limit *= 2;
6429 pipe_config->double_wide = true;
6430 }
6431
6432 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
6433 return -EINVAL;
6434 }
6435
6436 /*
6437 * Pipe horizontal size must be even in:
6438 * - DVO ganged mode
6439 * - LVDS dual channel mode
6440 * - Double wide pipe
6441 */
6442 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6443 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6444 pipe_config->pipe_src_w &= ~1;
6445
6446 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6447 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6448 */
6449 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6450 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
6451 return -EINVAL;
6452
6453 if (HAS_IPS(dev))
6454 hsw_compute_ips_config(crtc, pipe_config);
6455
6456 if (pipe_config->has_pch_encoder)
6457 return ironlake_fdi_compute_config(crtc, pipe_config);
6458
6459 /* FIXME: remove below call once atomic mode set is place and all crtc
6460 * related checks called from atomic_crtc_check function */
6461 ret = 0;
6462 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6463 crtc, pipe_config->base.state);
6464 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6465
6466 return ret;
6467 }
6468
6469 static int skylake_get_display_clock_speed(struct drm_device *dev)
6470 {
6471 struct drm_i915_private *dev_priv = to_i915(dev);
6472 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6473 uint32_t cdctl = I915_READ(CDCLK_CTL);
6474 uint32_t linkrate;
6475
6476 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6477 WARN(1, "LCPLL1 not enabled\n");
6478 return 24000; /* 24MHz is the cd freq with NSSC ref */
6479 }
6480
6481 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6482 return 540000;
6483
6484 linkrate = (I915_READ(DPLL_CTRL1) &
6485 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6486
6487 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6488 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6489 /* vco 8640 */
6490 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6491 case CDCLK_FREQ_450_432:
6492 return 432000;
6493 case CDCLK_FREQ_337_308:
6494 return 308570;
6495 case CDCLK_FREQ_675_617:
6496 return 617140;
6497 default:
6498 WARN(1, "Unknown cd freq selection\n");
6499 }
6500 } else {
6501 /* vco 8100 */
6502 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6503 case CDCLK_FREQ_450_432:
6504 return 450000;
6505 case CDCLK_FREQ_337_308:
6506 return 337500;
6507 case CDCLK_FREQ_675_617:
6508 return 675000;
6509 default:
6510 WARN(1, "Unknown cd freq selection\n");
6511 }
6512 }
6513
6514 /* error case, do as if DPLL0 isn't enabled */
6515 return 24000;
6516 }
6517
6518 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6519 {
6520 struct drm_i915_private *dev_priv = dev->dev_private;
6521 uint32_t lcpll = I915_READ(LCPLL_CTL);
6522 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6523
6524 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6525 return 800000;
6526 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6527 return 450000;
6528 else if (freq == LCPLL_CLK_FREQ_450)
6529 return 450000;
6530 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6531 return 540000;
6532 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6533 return 337500;
6534 else
6535 return 675000;
6536 }
6537
6538 static int haswell_get_display_clock_speed(struct drm_device *dev)
6539 {
6540 struct drm_i915_private *dev_priv = dev->dev_private;
6541 uint32_t lcpll = I915_READ(LCPLL_CTL);
6542 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6543
6544 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6545 return 800000;
6546 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6547 return 450000;
6548 else if (freq == LCPLL_CLK_FREQ_450)
6549 return 450000;
6550 else if (IS_HSW_ULT(dev))
6551 return 337500;
6552 else
6553 return 540000;
6554 }
6555
6556 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6557 {
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559 u32 val;
6560 int divider;
6561
6562 if (dev_priv->hpll_freq == 0)
6563 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6564
6565 mutex_lock(&dev_priv->dpio_lock);
6566 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6567 mutex_unlock(&dev_priv->dpio_lock);
6568
6569 divider = val & DISPLAY_FREQUENCY_VALUES;
6570
6571 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6572 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6573 "cdclk change in progress\n");
6574
6575 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
6576 }
6577
6578 static int ilk_get_display_clock_speed(struct drm_device *dev)
6579 {
6580 return 450000;
6581 }
6582
6583 static int i945_get_display_clock_speed(struct drm_device *dev)
6584 {
6585 return 400000;
6586 }
6587
6588 static int i915_get_display_clock_speed(struct drm_device *dev)
6589 {
6590 return 333333;
6591 }
6592
6593 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6594 {
6595 return 200000;
6596 }
6597
6598 static int pnv_get_display_clock_speed(struct drm_device *dev)
6599 {
6600 u16 gcfgc = 0;
6601
6602 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6603
6604 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6605 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6606 return 266667;
6607 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6608 return 333333;
6609 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6610 return 444444;
6611 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6612 return 200000;
6613 default:
6614 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6615 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6616 return 133333;
6617 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6618 return 166667;
6619 }
6620 }
6621
6622 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6623 {
6624 u16 gcfgc = 0;
6625
6626 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6627
6628 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6629 return 133333;
6630 else {
6631 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6632 case GC_DISPLAY_CLOCK_333_MHZ:
6633 return 333333;
6634 default:
6635 case GC_DISPLAY_CLOCK_190_200_MHZ:
6636 return 190000;
6637 }
6638 }
6639 }
6640
6641 static int i865_get_display_clock_speed(struct drm_device *dev)
6642 {
6643 return 266667;
6644 }
6645
6646 static int i855_get_display_clock_speed(struct drm_device *dev)
6647 {
6648 u16 hpllcc = 0;
6649 /* Assume that the hardware is in the high speed state. This
6650 * should be the default.
6651 */
6652 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6653 case GC_CLOCK_133_200:
6654 case GC_CLOCK_100_200:
6655 return 200000;
6656 case GC_CLOCK_166_250:
6657 return 250000;
6658 case GC_CLOCK_100_133:
6659 return 133333;
6660 }
6661
6662 /* Shouldn't happen */
6663 return 0;
6664 }
6665
6666 static int i830_get_display_clock_speed(struct drm_device *dev)
6667 {
6668 return 133333;
6669 }
6670
6671 static void
6672 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
6673 {
6674 while (*num > DATA_LINK_M_N_MASK ||
6675 *den > DATA_LINK_M_N_MASK) {
6676 *num >>= 1;
6677 *den >>= 1;
6678 }
6679 }
6680
6681 static void compute_m_n(unsigned int m, unsigned int n,
6682 uint32_t *ret_m, uint32_t *ret_n)
6683 {
6684 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6685 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6686 intel_reduce_m_n_ratio(ret_m, ret_n);
6687 }
6688
6689 void
6690 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6691 int pixel_clock, int link_clock,
6692 struct intel_link_m_n *m_n)
6693 {
6694 m_n->tu = 64;
6695
6696 compute_m_n(bits_per_pixel * pixel_clock,
6697 link_clock * nlanes * 8,
6698 &m_n->gmch_m, &m_n->gmch_n);
6699
6700 compute_m_n(pixel_clock, link_clock,
6701 &m_n->link_m, &m_n->link_n);
6702 }
6703
6704 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6705 {
6706 if (i915.panel_use_ssc >= 0)
6707 return i915.panel_use_ssc != 0;
6708 return dev_priv->vbt.lvds_use_ssc
6709 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
6710 }
6711
6712 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6713 int num_connectors)
6714 {
6715 struct drm_device *dev = crtc_state->base.crtc->dev;
6716 struct drm_i915_private *dev_priv = dev->dev_private;
6717 int refclk;
6718
6719 WARN_ON(!crtc_state->base.state);
6720
6721 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
6722 refclk = 100000;
6723 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6724 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6725 refclk = dev_priv->vbt.lvds_ssc_freq;
6726 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
6727 } else if (!IS_GEN2(dev)) {
6728 refclk = 96000;
6729 } else {
6730 refclk = 48000;
6731 }
6732
6733 return refclk;
6734 }
6735
6736 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
6737 {
6738 return (1 << dpll->n) << 16 | dpll->m2;
6739 }
6740
6741 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6742 {
6743 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
6744 }
6745
6746 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
6747 struct intel_crtc_state *crtc_state,
6748 intel_clock_t *reduced_clock)
6749 {
6750 struct drm_device *dev = crtc->base.dev;
6751 u32 fp, fp2 = 0;
6752
6753 if (IS_PINEVIEW(dev)) {
6754 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
6755 if (reduced_clock)
6756 fp2 = pnv_dpll_compute_fp(reduced_clock);
6757 } else {
6758 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
6759 if (reduced_clock)
6760 fp2 = i9xx_dpll_compute_fp(reduced_clock);
6761 }
6762
6763 crtc_state->dpll_hw_state.fp0 = fp;
6764
6765 crtc->lowfreq_avail = false;
6766 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
6767 reduced_clock) {
6768 crtc_state->dpll_hw_state.fp1 = fp2;
6769 crtc->lowfreq_avail = true;
6770 } else {
6771 crtc_state->dpll_hw_state.fp1 = fp;
6772 }
6773 }
6774
6775 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6776 pipe)
6777 {
6778 u32 reg_val;
6779
6780 /*
6781 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6782 * and set it to a reasonable value instead.
6783 */
6784 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6785 reg_val &= 0xffffff00;
6786 reg_val |= 0x00000030;
6787 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6788
6789 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6790 reg_val &= 0x8cffffff;
6791 reg_val = 0x8c000000;
6792 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6793
6794 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
6795 reg_val &= 0xffffff00;
6796 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
6797
6798 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
6799 reg_val &= 0x00ffffff;
6800 reg_val |= 0xb0000000;
6801 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
6802 }
6803
6804 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6805 struct intel_link_m_n *m_n)
6806 {
6807 struct drm_device *dev = crtc->base.dev;
6808 struct drm_i915_private *dev_priv = dev->dev_private;
6809 int pipe = crtc->pipe;
6810
6811 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6812 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6813 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6814 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
6815 }
6816
6817 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
6818 struct intel_link_m_n *m_n,
6819 struct intel_link_m_n *m2_n2)
6820 {
6821 struct drm_device *dev = crtc->base.dev;
6822 struct drm_i915_private *dev_priv = dev->dev_private;
6823 int pipe = crtc->pipe;
6824 enum transcoder transcoder = crtc->config->cpu_transcoder;
6825
6826 if (INTEL_INFO(dev)->gen >= 5) {
6827 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6828 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6829 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6830 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
6831 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6832 * for gen < 8) and if DRRS is supported (to make sure the
6833 * registers are not unnecessarily accessed).
6834 */
6835 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6836 crtc->config->has_drrs) {
6837 I915_WRITE(PIPE_DATA_M2(transcoder),
6838 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6839 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6840 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6841 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6842 }
6843 } else {
6844 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6845 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6846 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6847 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
6848 }
6849 }
6850
6851 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
6852 {
6853 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6854
6855 if (m_n == M1_N1) {
6856 dp_m_n = &crtc->config->dp_m_n;
6857 dp_m2_n2 = &crtc->config->dp_m2_n2;
6858 } else if (m_n == M2_N2) {
6859
6860 /*
6861 * M2_N2 registers are not supported. Hence m2_n2 divider value
6862 * needs to be programmed into M1_N1.
6863 */
6864 dp_m_n = &crtc->config->dp_m2_n2;
6865 } else {
6866 DRM_ERROR("Unsupported divider value\n");
6867 return;
6868 }
6869
6870 if (crtc->config->has_pch_encoder)
6871 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
6872 else
6873 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
6874 }
6875
6876 static void vlv_update_pll(struct intel_crtc *crtc,
6877 struct intel_crtc_state *pipe_config)
6878 {
6879 u32 dpll, dpll_md;
6880
6881 /*
6882 * Enable DPIO clock input. We should never disable the reference
6883 * clock for pipe B, since VGA hotplug / manual detection depends
6884 * on it.
6885 */
6886 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6887 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6888 /* We should never disable this, set it here for state tracking */
6889 if (crtc->pipe == PIPE_B)
6890 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6891 dpll |= DPLL_VCO_ENABLE;
6892 pipe_config->dpll_hw_state.dpll = dpll;
6893
6894 dpll_md = (pipe_config->pixel_multiplier - 1)
6895 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6896 pipe_config->dpll_hw_state.dpll_md = dpll_md;
6897 }
6898
6899 static void vlv_prepare_pll(struct intel_crtc *crtc,
6900 const struct intel_crtc_state *pipe_config)
6901 {
6902 struct drm_device *dev = crtc->base.dev;
6903 struct drm_i915_private *dev_priv = dev->dev_private;
6904 int pipe = crtc->pipe;
6905 u32 mdiv;
6906 u32 bestn, bestm1, bestm2, bestp1, bestp2;
6907 u32 coreclk, reg_val;
6908
6909 mutex_lock(&dev_priv->dpio_lock);
6910
6911 bestn = pipe_config->dpll.n;
6912 bestm1 = pipe_config->dpll.m1;
6913 bestm2 = pipe_config->dpll.m2;
6914 bestp1 = pipe_config->dpll.p1;
6915 bestp2 = pipe_config->dpll.p2;
6916
6917 /* See eDP HDMI DPIO driver vbios notes doc */
6918
6919 /* PLL B needs special handling */
6920 if (pipe == PIPE_B)
6921 vlv_pllb_recal_opamp(dev_priv, pipe);
6922
6923 /* Set up Tx target for periodic Rcomp update */
6924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
6925
6926 /* Disable target IRef on PLL */
6927 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
6928 reg_val &= 0x00ffffff;
6929 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
6930
6931 /* Disable fast lock */
6932 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
6933
6934 /* Set idtafcrecal before PLL is enabled */
6935 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6936 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6937 mdiv |= ((bestn << DPIO_N_SHIFT));
6938 mdiv |= (1 << DPIO_K_SHIFT);
6939
6940 /*
6941 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6942 * but we don't support that).
6943 * Note: don't use the DAC post divider as it seems unstable.
6944 */
6945 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
6946 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6947
6948 mdiv |= DPIO_ENABLE_CALIBRATION;
6949 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
6950
6951 /* Set HBR and RBR LPF coefficients */
6952 if (pipe_config->port_clock == 162000 ||
6953 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6954 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
6955 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6956 0x009f0003);
6957 else
6958 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
6959 0x00d0000f);
6960
6961 if (pipe_config->has_dp_encoder) {
6962 /* Use SSC source */
6963 if (pipe == PIPE_A)
6964 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6965 0x0df40000);
6966 else
6967 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6968 0x0df70000);
6969 } else { /* HDMI or VGA */
6970 /* Use bend source */
6971 if (pipe == PIPE_A)
6972 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6973 0x0df70000);
6974 else
6975 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
6976 0x0df40000);
6977 }
6978
6979 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
6980 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
6981 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6982 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
6983 coreclk |= 0x01000000;
6984 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
6985
6986 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
6987 mutex_unlock(&dev_priv->dpio_lock);
6988 }
6989
6990 static void chv_update_pll(struct intel_crtc *crtc,
6991 struct intel_crtc_state *pipe_config)
6992 {
6993 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
6994 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6995 DPLL_VCO_ENABLE;
6996 if (crtc->pipe != PIPE_A)
6997 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6998
6999 pipe_config->dpll_hw_state.dpll_md =
7000 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7001 }
7002
7003 static void chv_prepare_pll(struct intel_crtc *crtc,
7004 const struct intel_crtc_state *pipe_config)
7005 {
7006 struct drm_device *dev = crtc->base.dev;
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 int pipe = crtc->pipe;
7009 int dpll_reg = DPLL(crtc->pipe);
7010 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7011 u32 loopfilter, tribuf_calcntr;
7012 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7013 u32 dpio_val;
7014 int vco;
7015
7016 bestn = pipe_config->dpll.n;
7017 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7018 bestm1 = pipe_config->dpll.m1;
7019 bestm2 = pipe_config->dpll.m2 >> 22;
7020 bestp1 = pipe_config->dpll.p1;
7021 bestp2 = pipe_config->dpll.p2;
7022 vco = pipe_config->dpll.vco;
7023 dpio_val = 0;
7024 loopfilter = 0;
7025
7026 /*
7027 * Enable Refclk and SSC
7028 */
7029 I915_WRITE(dpll_reg,
7030 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7031
7032 mutex_lock(&dev_priv->dpio_lock);
7033
7034 /* p1 and p2 divider */
7035 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7036 5 << DPIO_CHV_S1_DIV_SHIFT |
7037 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7038 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7039 1 << DPIO_CHV_K_DIV_SHIFT);
7040
7041 /* Feedback post-divider - m2 */
7042 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7043
7044 /* Feedback refclk divider - n and m1 */
7045 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7046 DPIO_CHV_M1_DIV_BY_2 |
7047 1 << DPIO_CHV_N_DIV_SHIFT);
7048
7049 /* M2 fraction division */
7050 if (bestm2_frac)
7051 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7052
7053 /* M2 fraction division enable */
7054 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7055 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7056 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7057 if (bestm2_frac)
7058 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7059 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7060
7061 /* Program digital lock detect threshold */
7062 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7063 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7064 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7065 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7066 if (!bestm2_frac)
7067 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7068 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7069
7070 /* Loop filter */
7071 if (vco == 5400000) {
7072 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7073 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7074 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7075 tribuf_calcntr = 0x9;
7076 } else if (vco <= 6200000) {
7077 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7078 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7079 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7080 tribuf_calcntr = 0x9;
7081 } else if (vco <= 6480000) {
7082 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7083 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7084 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7085 tribuf_calcntr = 0x8;
7086 } else {
7087 /* Not supported. Apply the same limits as in the max case */
7088 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7089 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7090 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7091 tribuf_calcntr = 0;
7092 }
7093 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7094
7095 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7096 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7097 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7098 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7099
7100 /* AFC Recal */
7101 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7102 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7103 DPIO_AFC_RECAL);
7104
7105 mutex_unlock(&dev_priv->dpio_lock);
7106 }
7107
7108 /**
7109 * vlv_force_pll_on - forcibly enable just the PLL
7110 * @dev_priv: i915 private structure
7111 * @pipe: pipe PLL to enable
7112 * @dpll: PLL configuration
7113 *
7114 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7115 * in cases where we need the PLL enabled even when @pipe is not going to
7116 * be enabled.
7117 */
7118 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7119 const struct dpll *dpll)
7120 {
7121 struct intel_crtc *crtc =
7122 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7123 struct intel_crtc_state pipe_config = {
7124 .base.crtc = &crtc->base,
7125 .pixel_multiplier = 1,
7126 .dpll = *dpll,
7127 };
7128
7129 if (IS_CHERRYVIEW(dev)) {
7130 chv_update_pll(crtc, &pipe_config);
7131 chv_prepare_pll(crtc, &pipe_config);
7132 chv_enable_pll(crtc, &pipe_config);
7133 } else {
7134 vlv_update_pll(crtc, &pipe_config);
7135 vlv_prepare_pll(crtc, &pipe_config);
7136 vlv_enable_pll(crtc, &pipe_config);
7137 }
7138 }
7139
7140 /**
7141 * vlv_force_pll_off - forcibly disable just the PLL
7142 * @dev_priv: i915 private structure
7143 * @pipe: pipe PLL to disable
7144 *
7145 * Disable the PLL for @pipe. To be used in cases where we need
7146 * the PLL enabled even when @pipe is not going to be enabled.
7147 */
7148 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7149 {
7150 if (IS_CHERRYVIEW(dev))
7151 chv_disable_pll(to_i915(dev), pipe);
7152 else
7153 vlv_disable_pll(to_i915(dev), pipe);
7154 }
7155
7156 static void i9xx_update_pll(struct intel_crtc *crtc,
7157 struct intel_crtc_state *crtc_state,
7158 intel_clock_t *reduced_clock,
7159 int num_connectors)
7160 {
7161 struct drm_device *dev = crtc->base.dev;
7162 struct drm_i915_private *dev_priv = dev->dev_private;
7163 u32 dpll;
7164 bool is_sdvo;
7165 struct dpll *clock = &crtc_state->dpll;
7166
7167 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7168
7169 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7170 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7171
7172 dpll = DPLL_VGA_MODE_DIS;
7173
7174 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7175 dpll |= DPLLB_MODE_LVDS;
7176 else
7177 dpll |= DPLLB_MODE_DAC_SERIAL;
7178
7179 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7180 dpll |= (crtc_state->pixel_multiplier - 1)
7181 << SDVO_MULTIPLIER_SHIFT_HIRES;
7182 }
7183
7184 if (is_sdvo)
7185 dpll |= DPLL_SDVO_HIGH_SPEED;
7186
7187 if (crtc_state->has_dp_encoder)
7188 dpll |= DPLL_SDVO_HIGH_SPEED;
7189
7190 /* compute bitmask from p1 value */
7191 if (IS_PINEVIEW(dev))
7192 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7193 else {
7194 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7195 if (IS_G4X(dev) && reduced_clock)
7196 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7197 }
7198 switch (clock->p2) {
7199 case 5:
7200 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7201 break;
7202 case 7:
7203 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7204 break;
7205 case 10:
7206 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7207 break;
7208 case 14:
7209 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7210 break;
7211 }
7212 if (INTEL_INFO(dev)->gen >= 4)
7213 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7214
7215 if (crtc_state->sdvo_tv_clock)
7216 dpll |= PLL_REF_INPUT_TVCLKINBC;
7217 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7218 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7219 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7220 else
7221 dpll |= PLL_REF_INPUT_DREFCLK;
7222
7223 dpll |= DPLL_VCO_ENABLE;
7224 crtc_state->dpll_hw_state.dpll = dpll;
7225
7226 if (INTEL_INFO(dev)->gen >= 4) {
7227 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7228 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7229 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7230 }
7231 }
7232
7233 static void i8xx_update_pll(struct intel_crtc *crtc,
7234 struct intel_crtc_state *crtc_state,
7235 intel_clock_t *reduced_clock,
7236 int num_connectors)
7237 {
7238 struct drm_device *dev = crtc->base.dev;
7239 struct drm_i915_private *dev_priv = dev->dev_private;
7240 u32 dpll;
7241 struct dpll *clock = &crtc_state->dpll;
7242
7243 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7244
7245 dpll = DPLL_VGA_MODE_DIS;
7246
7247 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7248 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7249 } else {
7250 if (clock->p1 == 2)
7251 dpll |= PLL_P1_DIVIDE_BY_TWO;
7252 else
7253 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7254 if (clock->p2 == 4)
7255 dpll |= PLL_P2_DIVIDE_BY_4;
7256 }
7257
7258 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7259 dpll |= DPLL_DVO_2X_MODE;
7260
7261 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7262 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7263 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7264 else
7265 dpll |= PLL_REF_INPUT_DREFCLK;
7266
7267 dpll |= DPLL_VCO_ENABLE;
7268 crtc_state->dpll_hw_state.dpll = dpll;
7269 }
7270
7271 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7272 {
7273 struct drm_device *dev = intel_crtc->base.dev;
7274 struct drm_i915_private *dev_priv = dev->dev_private;
7275 enum pipe pipe = intel_crtc->pipe;
7276 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7277 struct drm_display_mode *adjusted_mode =
7278 &intel_crtc->config->base.adjusted_mode;
7279 uint32_t crtc_vtotal, crtc_vblank_end;
7280 int vsyncshift = 0;
7281
7282 /* We need to be careful not to changed the adjusted mode, for otherwise
7283 * the hw state checker will get angry at the mismatch. */
7284 crtc_vtotal = adjusted_mode->crtc_vtotal;
7285 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7286
7287 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7288 /* the chip adds 2 halflines automatically */
7289 crtc_vtotal -= 1;
7290 crtc_vblank_end -= 1;
7291
7292 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7293 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7294 else
7295 vsyncshift = adjusted_mode->crtc_hsync_start -
7296 adjusted_mode->crtc_htotal / 2;
7297 if (vsyncshift < 0)
7298 vsyncshift += adjusted_mode->crtc_htotal;
7299 }
7300
7301 if (INTEL_INFO(dev)->gen > 3)
7302 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7303
7304 I915_WRITE(HTOTAL(cpu_transcoder),
7305 (adjusted_mode->crtc_hdisplay - 1) |
7306 ((adjusted_mode->crtc_htotal - 1) << 16));
7307 I915_WRITE(HBLANK(cpu_transcoder),
7308 (adjusted_mode->crtc_hblank_start - 1) |
7309 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7310 I915_WRITE(HSYNC(cpu_transcoder),
7311 (adjusted_mode->crtc_hsync_start - 1) |
7312 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7313
7314 I915_WRITE(VTOTAL(cpu_transcoder),
7315 (adjusted_mode->crtc_vdisplay - 1) |
7316 ((crtc_vtotal - 1) << 16));
7317 I915_WRITE(VBLANK(cpu_transcoder),
7318 (adjusted_mode->crtc_vblank_start - 1) |
7319 ((crtc_vblank_end - 1) << 16));
7320 I915_WRITE(VSYNC(cpu_transcoder),
7321 (adjusted_mode->crtc_vsync_start - 1) |
7322 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7323
7324 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7325 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7326 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7327 * bits. */
7328 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7329 (pipe == PIPE_B || pipe == PIPE_C))
7330 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7331
7332 /* pipesrc controls the size that is scaled from, which should
7333 * always be the user's requested size.
7334 */
7335 I915_WRITE(PIPESRC(pipe),
7336 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7337 (intel_crtc->config->pipe_src_h - 1));
7338 }
7339
7340 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7341 struct intel_crtc_state *pipe_config)
7342 {
7343 struct drm_device *dev = crtc->base.dev;
7344 struct drm_i915_private *dev_priv = dev->dev_private;
7345 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7346 uint32_t tmp;
7347
7348 tmp = I915_READ(HTOTAL(cpu_transcoder));
7349 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7350 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7351 tmp = I915_READ(HBLANK(cpu_transcoder));
7352 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7353 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7354 tmp = I915_READ(HSYNC(cpu_transcoder));
7355 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7356 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7357
7358 tmp = I915_READ(VTOTAL(cpu_transcoder));
7359 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7360 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7361 tmp = I915_READ(VBLANK(cpu_transcoder));
7362 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7363 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7364 tmp = I915_READ(VSYNC(cpu_transcoder));
7365 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7366 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7367
7368 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7369 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7370 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7371 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7372 }
7373
7374 tmp = I915_READ(PIPESRC(crtc->pipe));
7375 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7376 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7377
7378 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7379 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7380 }
7381
7382 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7383 struct intel_crtc_state *pipe_config)
7384 {
7385 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7386 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7387 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7388 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7389
7390 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7391 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7392 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7393 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7394
7395 mode->flags = pipe_config->base.adjusted_mode.flags;
7396
7397 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7398 mode->flags |= pipe_config->base.adjusted_mode.flags;
7399 }
7400
7401 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7402 {
7403 struct drm_device *dev = intel_crtc->base.dev;
7404 struct drm_i915_private *dev_priv = dev->dev_private;
7405 uint32_t pipeconf;
7406
7407 pipeconf = 0;
7408
7409 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7410 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7411 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7412
7413 if (intel_crtc->config->double_wide)
7414 pipeconf |= PIPECONF_DOUBLE_WIDE;
7415
7416 /* only g4x and later have fancy bpc/dither controls */
7417 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7418 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7419 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7420 pipeconf |= PIPECONF_DITHER_EN |
7421 PIPECONF_DITHER_TYPE_SP;
7422
7423 switch (intel_crtc->config->pipe_bpp) {
7424 case 18:
7425 pipeconf |= PIPECONF_6BPC;
7426 break;
7427 case 24:
7428 pipeconf |= PIPECONF_8BPC;
7429 break;
7430 case 30:
7431 pipeconf |= PIPECONF_10BPC;
7432 break;
7433 default:
7434 /* Case prevented by intel_choose_pipe_bpp_dither. */
7435 BUG();
7436 }
7437 }
7438
7439 if (HAS_PIPE_CXSR(dev)) {
7440 if (intel_crtc->lowfreq_avail) {
7441 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7442 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7443 } else {
7444 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
7445 }
7446 }
7447
7448 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
7449 if (INTEL_INFO(dev)->gen < 4 ||
7450 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7451 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7452 else
7453 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7454 } else
7455 pipeconf |= PIPECONF_PROGRESSIVE;
7456
7457 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
7458 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
7459
7460 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7461 POSTING_READ(PIPECONF(intel_crtc->pipe));
7462 }
7463
7464 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7465 struct intel_crtc_state *crtc_state)
7466 {
7467 struct drm_device *dev = crtc->base.dev;
7468 struct drm_i915_private *dev_priv = dev->dev_private;
7469 int refclk, num_connectors = 0;
7470 intel_clock_t clock, reduced_clock;
7471 bool ok, has_reduced_clock = false;
7472 bool is_lvds = false, is_dsi = false;
7473 struct intel_encoder *encoder;
7474 const intel_limit_t *limit;
7475 struct drm_atomic_state *state = crtc_state->base.state;
7476 struct drm_connector *connector;
7477 struct drm_connector_state *connector_state;
7478 int i;
7479
7480 for_each_connector_in_state(state, connector, connector_state, i) {
7481 if (connector_state->crtc != &crtc->base)
7482 continue;
7483
7484 encoder = to_intel_encoder(connector_state->best_encoder);
7485
7486 switch (encoder->type) {
7487 case INTEL_OUTPUT_LVDS:
7488 is_lvds = true;
7489 break;
7490 case INTEL_OUTPUT_DSI:
7491 is_dsi = true;
7492 break;
7493 default:
7494 break;
7495 }
7496
7497 num_connectors++;
7498 }
7499
7500 if (is_dsi)
7501 return 0;
7502
7503 if (!crtc_state->clock_set) {
7504 refclk = i9xx_get_refclk(crtc_state, num_connectors);
7505
7506 /*
7507 * Returns a set of divisors for the desired target clock with
7508 * the given refclk, or FALSE. The returned values represent
7509 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7510 * 2) / p1 / p2.
7511 */
7512 limit = intel_limit(crtc_state, refclk);
7513 ok = dev_priv->display.find_dpll(limit, crtc_state,
7514 crtc_state->port_clock,
7515 refclk, NULL, &clock);
7516 if (!ok) {
7517 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7518 return -EINVAL;
7519 }
7520
7521 if (is_lvds && dev_priv->lvds_downclock_avail) {
7522 /*
7523 * Ensure we match the reduced clock's P to the target
7524 * clock. If the clocks don't match, we can't switch
7525 * the display clock by using the FP0/FP1. In such case
7526 * we will disable the LVDS downclock feature.
7527 */
7528 has_reduced_clock =
7529 dev_priv->display.find_dpll(limit, crtc_state,
7530 dev_priv->lvds_downclock,
7531 refclk, &clock,
7532 &reduced_clock);
7533 }
7534 /* Compat-code for transition, will disappear. */
7535 crtc_state->dpll.n = clock.n;
7536 crtc_state->dpll.m1 = clock.m1;
7537 crtc_state->dpll.m2 = clock.m2;
7538 crtc_state->dpll.p1 = clock.p1;
7539 crtc_state->dpll.p2 = clock.p2;
7540 }
7541
7542 if (IS_GEN2(dev)) {
7543 i8xx_update_pll(crtc, crtc_state,
7544 has_reduced_clock ? &reduced_clock : NULL,
7545 num_connectors);
7546 } else if (IS_CHERRYVIEW(dev)) {
7547 chv_update_pll(crtc, crtc_state);
7548 } else if (IS_VALLEYVIEW(dev)) {
7549 vlv_update_pll(crtc, crtc_state);
7550 } else {
7551 i9xx_update_pll(crtc, crtc_state,
7552 has_reduced_clock ? &reduced_clock : NULL,
7553 num_connectors);
7554 }
7555
7556 return 0;
7557 }
7558
7559 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
7560 struct intel_crtc_state *pipe_config)
7561 {
7562 struct drm_device *dev = crtc->base.dev;
7563 struct drm_i915_private *dev_priv = dev->dev_private;
7564 uint32_t tmp;
7565
7566 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7567 return;
7568
7569 tmp = I915_READ(PFIT_CONTROL);
7570 if (!(tmp & PFIT_ENABLE))
7571 return;
7572
7573 /* Check whether the pfit is attached to our pipe. */
7574 if (INTEL_INFO(dev)->gen < 4) {
7575 if (crtc->pipe != PIPE_B)
7576 return;
7577 } else {
7578 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7579 return;
7580 }
7581
7582 pipe_config->gmch_pfit.control = tmp;
7583 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7584 if (INTEL_INFO(dev)->gen < 5)
7585 pipe_config->gmch_pfit.lvds_border_bits =
7586 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7587 }
7588
7589 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
7590 struct intel_crtc_state *pipe_config)
7591 {
7592 struct drm_device *dev = crtc->base.dev;
7593 struct drm_i915_private *dev_priv = dev->dev_private;
7594 int pipe = pipe_config->cpu_transcoder;
7595 intel_clock_t clock;
7596 u32 mdiv;
7597 int refclk = 100000;
7598
7599 /* In case of MIPI DPLL will not even be used */
7600 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7601 return;
7602
7603 mutex_lock(&dev_priv->dpio_lock);
7604 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
7605 mutex_unlock(&dev_priv->dpio_lock);
7606
7607 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7608 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7609 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7610 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7611 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7612
7613 vlv_clock(refclk, &clock);
7614
7615 /* clock.dot is the fast clock */
7616 pipe_config->port_clock = clock.dot / 5;
7617 }
7618
7619 static void
7620 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7621 struct intel_initial_plane_config *plane_config)
7622 {
7623 struct drm_device *dev = crtc->base.dev;
7624 struct drm_i915_private *dev_priv = dev->dev_private;
7625 u32 val, base, offset;
7626 int pipe = crtc->pipe, plane = crtc->plane;
7627 int fourcc, pixel_format;
7628 unsigned int aligned_height;
7629 struct drm_framebuffer *fb;
7630 struct intel_framebuffer *intel_fb;
7631
7632 val = I915_READ(DSPCNTR(plane));
7633 if (!(val & DISPLAY_PLANE_ENABLE))
7634 return;
7635
7636 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7637 if (!intel_fb) {
7638 DRM_DEBUG_KMS("failed to alloc fb\n");
7639 return;
7640 }
7641
7642 fb = &intel_fb->base;
7643
7644 if (INTEL_INFO(dev)->gen >= 4) {
7645 if (val & DISPPLANE_TILED) {
7646 plane_config->tiling = I915_TILING_X;
7647 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7648 }
7649 }
7650
7651 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7652 fourcc = i9xx_format_to_fourcc(pixel_format);
7653 fb->pixel_format = fourcc;
7654 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7655
7656 if (INTEL_INFO(dev)->gen >= 4) {
7657 if (plane_config->tiling)
7658 offset = I915_READ(DSPTILEOFF(plane));
7659 else
7660 offset = I915_READ(DSPLINOFF(plane));
7661 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7662 } else {
7663 base = I915_READ(DSPADDR(plane));
7664 }
7665 plane_config->base = base;
7666
7667 val = I915_READ(PIPESRC(pipe));
7668 fb->width = ((val >> 16) & 0xfff) + 1;
7669 fb->height = ((val >> 0) & 0xfff) + 1;
7670
7671 val = I915_READ(DSPSTRIDE(pipe));
7672 fb->pitches[0] = val & 0xffffffc0;
7673
7674 aligned_height = intel_fb_align_height(dev, fb->height,
7675 fb->pixel_format,
7676 fb->modifier[0]);
7677
7678 plane_config->size = fb->pitches[0] * aligned_height;
7679
7680 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7681 pipe_name(pipe), plane, fb->width, fb->height,
7682 fb->bits_per_pixel, base, fb->pitches[0],
7683 plane_config->size);
7684
7685 plane_config->fb = intel_fb;
7686 }
7687
7688 static void chv_crtc_clock_get(struct intel_crtc *crtc,
7689 struct intel_crtc_state *pipe_config)
7690 {
7691 struct drm_device *dev = crtc->base.dev;
7692 struct drm_i915_private *dev_priv = dev->dev_private;
7693 int pipe = pipe_config->cpu_transcoder;
7694 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7695 intel_clock_t clock;
7696 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7697 int refclk = 100000;
7698
7699 mutex_lock(&dev_priv->dpio_lock);
7700 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7701 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7702 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7703 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7704 mutex_unlock(&dev_priv->dpio_lock);
7705
7706 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7707 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7708 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7709 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7710 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7711
7712 chv_clock(refclk, &clock);
7713
7714 /* clock.dot is the fast clock */
7715 pipe_config->port_clock = clock.dot / 5;
7716 }
7717
7718 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
7719 struct intel_crtc_state *pipe_config)
7720 {
7721 struct drm_device *dev = crtc->base.dev;
7722 struct drm_i915_private *dev_priv = dev->dev_private;
7723 uint32_t tmp;
7724
7725 if (!intel_display_power_is_enabled(dev_priv,
7726 POWER_DOMAIN_PIPE(crtc->pipe)))
7727 return false;
7728
7729 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7730 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7731
7732 tmp = I915_READ(PIPECONF(crtc->pipe));
7733 if (!(tmp & PIPECONF_ENABLE))
7734 return false;
7735
7736 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7737 switch (tmp & PIPECONF_BPC_MASK) {
7738 case PIPECONF_6BPC:
7739 pipe_config->pipe_bpp = 18;
7740 break;
7741 case PIPECONF_8BPC:
7742 pipe_config->pipe_bpp = 24;
7743 break;
7744 case PIPECONF_10BPC:
7745 pipe_config->pipe_bpp = 30;
7746 break;
7747 default:
7748 break;
7749 }
7750 }
7751
7752 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7753 pipe_config->limited_color_range = true;
7754
7755 if (INTEL_INFO(dev)->gen < 4)
7756 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7757
7758 intel_get_pipe_timings(crtc, pipe_config);
7759
7760 i9xx_get_pfit_config(crtc, pipe_config);
7761
7762 if (INTEL_INFO(dev)->gen >= 4) {
7763 tmp = I915_READ(DPLL_MD(crtc->pipe));
7764 pipe_config->pixel_multiplier =
7765 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7766 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
7767 pipe_config->dpll_hw_state.dpll_md = tmp;
7768 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7769 tmp = I915_READ(DPLL(crtc->pipe));
7770 pipe_config->pixel_multiplier =
7771 ((tmp & SDVO_MULTIPLIER_MASK)
7772 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7773 } else {
7774 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7775 * port and will be fixed up in the encoder->get_config
7776 * function. */
7777 pipe_config->pixel_multiplier = 1;
7778 }
7779 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7780 if (!IS_VALLEYVIEW(dev)) {
7781 /*
7782 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7783 * on 830. Filter it out here so that we don't
7784 * report errors due to that.
7785 */
7786 if (IS_I830(dev))
7787 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7788
7789 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7790 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
7791 } else {
7792 /* Mask out read-only status bits. */
7793 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7794 DPLL_PORTC_READY_MASK |
7795 DPLL_PORTB_READY_MASK);
7796 }
7797
7798 if (IS_CHERRYVIEW(dev))
7799 chv_crtc_clock_get(crtc, pipe_config);
7800 else if (IS_VALLEYVIEW(dev))
7801 vlv_crtc_clock_get(crtc, pipe_config);
7802 else
7803 i9xx_crtc_clock_get(crtc, pipe_config);
7804
7805 return true;
7806 }
7807
7808 static void ironlake_init_pch_refclk(struct drm_device *dev)
7809 {
7810 struct drm_i915_private *dev_priv = dev->dev_private;
7811 struct intel_encoder *encoder;
7812 u32 val, final;
7813 bool has_lvds = false;
7814 bool has_cpu_edp = false;
7815 bool has_panel = false;
7816 bool has_ck505 = false;
7817 bool can_ssc = false;
7818
7819 /* We need to take the global config into account */
7820 for_each_intel_encoder(dev, encoder) {
7821 switch (encoder->type) {
7822 case INTEL_OUTPUT_LVDS:
7823 has_panel = true;
7824 has_lvds = true;
7825 break;
7826 case INTEL_OUTPUT_EDP:
7827 has_panel = true;
7828 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
7829 has_cpu_edp = true;
7830 break;
7831 default:
7832 break;
7833 }
7834 }
7835
7836 if (HAS_PCH_IBX(dev)) {
7837 has_ck505 = dev_priv->vbt.display_clock_mode;
7838 can_ssc = has_ck505;
7839 } else {
7840 has_ck505 = false;
7841 can_ssc = true;
7842 }
7843
7844 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7845 has_panel, has_lvds, has_ck505);
7846
7847 /* Ironlake: try to setup display ref clock before DPLL
7848 * enabling. This is only under driver's control after
7849 * PCH B stepping, previous chipset stepping should be
7850 * ignoring this setting.
7851 */
7852 val = I915_READ(PCH_DREF_CONTROL);
7853
7854 /* As we must carefully and slowly disable/enable each source in turn,
7855 * compute the final state we want first and check if we need to
7856 * make any changes at all.
7857 */
7858 final = val;
7859 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7860 if (has_ck505)
7861 final |= DREF_NONSPREAD_CK505_ENABLE;
7862 else
7863 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7864
7865 final &= ~DREF_SSC_SOURCE_MASK;
7866 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7867 final &= ~DREF_SSC1_ENABLE;
7868
7869 if (has_panel) {
7870 final |= DREF_SSC_SOURCE_ENABLE;
7871
7872 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7873 final |= DREF_SSC1_ENABLE;
7874
7875 if (has_cpu_edp) {
7876 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7877 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7878 else
7879 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7880 } else
7881 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7882 } else {
7883 final |= DREF_SSC_SOURCE_DISABLE;
7884 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7885 }
7886
7887 if (final == val)
7888 return;
7889
7890 /* Always enable nonspread source */
7891 val &= ~DREF_NONSPREAD_SOURCE_MASK;
7892
7893 if (has_ck505)
7894 val |= DREF_NONSPREAD_CK505_ENABLE;
7895 else
7896 val |= DREF_NONSPREAD_SOURCE_ENABLE;
7897
7898 if (has_panel) {
7899 val &= ~DREF_SSC_SOURCE_MASK;
7900 val |= DREF_SSC_SOURCE_ENABLE;
7901
7902 /* SSC must be turned on before enabling the CPU output */
7903 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7904 DRM_DEBUG_KMS("Using SSC on panel\n");
7905 val |= DREF_SSC1_ENABLE;
7906 } else
7907 val &= ~DREF_SSC1_ENABLE;
7908
7909 /* Get SSC going before enabling the outputs */
7910 I915_WRITE(PCH_DREF_CONTROL, val);
7911 POSTING_READ(PCH_DREF_CONTROL);
7912 udelay(200);
7913
7914 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7915
7916 /* Enable CPU source on CPU attached eDP */
7917 if (has_cpu_edp) {
7918 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
7919 DRM_DEBUG_KMS("Using SSC on eDP\n");
7920 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7921 } else
7922 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7923 } else
7924 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7925
7926 I915_WRITE(PCH_DREF_CONTROL, val);
7927 POSTING_READ(PCH_DREF_CONTROL);
7928 udelay(200);
7929 } else {
7930 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7931
7932 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7933
7934 /* Turn off CPU output */
7935 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7936
7937 I915_WRITE(PCH_DREF_CONTROL, val);
7938 POSTING_READ(PCH_DREF_CONTROL);
7939 udelay(200);
7940
7941 /* Turn off the SSC source */
7942 val &= ~DREF_SSC_SOURCE_MASK;
7943 val |= DREF_SSC_SOURCE_DISABLE;
7944
7945 /* Turn off SSC1 */
7946 val &= ~DREF_SSC1_ENABLE;
7947
7948 I915_WRITE(PCH_DREF_CONTROL, val);
7949 POSTING_READ(PCH_DREF_CONTROL);
7950 udelay(200);
7951 }
7952
7953 BUG_ON(val != final);
7954 }
7955
7956 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
7957 {
7958 uint32_t tmp;
7959
7960 tmp = I915_READ(SOUTH_CHICKEN2);
7961 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7962 I915_WRITE(SOUTH_CHICKEN2, tmp);
7963
7964 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7965 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7966 DRM_ERROR("FDI mPHY reset assert timeout\n");
7967
7968 tmp = I915_READ(SOUTH_CHICKEN2);
7969 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7970 I915_WRITE(SOUTH_CHICKEN2, tmp);
7971
7972 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7973 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7974 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
7975 }
7976
7977 /* WaMPhyProgramming:hsw */
7978 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7979 {
7980 uint32_t tmp;
7981
7982 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7983 tmp &= ~(0xFF << 24);
7984 tmp |= (0x12 << 24);
7985 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7986
7987 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7988 tmp |= (1 << 11);
7989 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7990
7991 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7992 tmp |= (1 << 11);
7993 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7994
7995 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7996 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7997 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7998
7999 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8000 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8001 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8002
8003 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8004 tmp &= ~(7 << 13);
8005 tmp |= (5 << 13);
8006 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8007
8008 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8009 tmp &= ~(7 << 13);
8010 tmp |= (5 << 13);
8011 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8012
8013 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8014 tmp &= ~0xFF;
8015 tmp |= 0x1C;
8016 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8017
8018 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8019 tmp &= ~0xFF;
8020 tmp |= 0x1C;
8021 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8022
8023 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8024 tmp &= ~(0xFF << 16);
8025 tmp |= (0x1C << 16);
8026 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8027
8028 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8029 tmp &= ~(0xFF << 16);
8030 tmp |= (0x1C << 16);
8031 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8032
8033 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8034 tmp |= (1 << 27);
8035 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8036
8037 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8038 tmp |= (1 << 27);
8039 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8040
8041 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8042 tmp &= ~(0xF << 28);
8043 tmp |= (4 << 28);
8044 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8045
8046 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8047 tmp &= ~(0xF << 28);
8048 tmp |= (4 << 28);
8049 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8050 }
8051
8052 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8053 * Programming" based on the parameters passed:
8054 * - Sequence to enable CLKOUT_DP
8055 * - Sequence to enable CLKOUT_DP without spread
8056 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8057 */
8058 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8059 bool with_fdi)
8060 {
8061 struct drm_i915_private *dev_priv = dev->dev_private;
8062 uint32_t reg, tmp;
8063
8064 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8065 with_spread = true;
8066 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8067 with_fdi, "LP PCH doesn't have FDI\n"))
8068 with_fdi = false;
8069
8070 mutex_lock(&dev_priv->dpio_lock);
8071
8072 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8073 tmp &= ~SBI_SSCCTL_DISABLE;
8074 tmp |= SBI_SSCCTL_PATHALT;
8075 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8076
8077 udelay(24);
8078
8079 if (with_spread) {
8080 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8081 tmp &= ~SBI_SSCCTL_PATHALT;
8082 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8083
8084 if (with_fdi) {
8085 lpt_reset_fdi_mphy(dev_priv);
8086 lpt_program_fdi_mphy(dev_priv);
8087 }
8088 }
8089
8090 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8091 SBI_GEN0 : SBI_DBUFF0;
8092 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8093 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8094 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8095
8096 mutex_unlock(&dev_priv->dpio_lock);
8097 }
8098
8099 /* Sequence to disable CLKOUT_DP */
8100 static void lpt_disable_clkout_dp(struct drm_device *dev)
8101 {
8102 struct drm_i915_private *dev_priv = dev->dev_private;
8103 uint32_t reg, tmp;
8104
8105 mutex_lock(&dev_priv->dpio_lock);
8106
8107 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8108 SBI_GEN0 : SBI_DBUFF0;
8109 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8110 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8111 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8112
8113 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8114 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8115 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8116 tmp |= SBI_SSCCTL_PATHALT;
8117 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8118 udelay(32);
8119 }
8120 tmp |= SBI_SSCCTL_DISABLE;
8121 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8122 }
8123
8124 mutex_unlock(&dev_priv->dpio_lock);
8125 }
8126
8127 static void lpt_init_pch_refclk(struct drm_device *dev)
8128 {
8129 struct intel_encoder *encoder;
8130 bool has_vga = false;
8131
8132 for_each_intel_encoder(dev, encoder) {
8133 switch (encoder->type) {
8134 case INTEL_OUTPUT_ANALOG:
8135 has_vga = true;
8136 break;
8137 default:
8138 break;
8139 }
8140 }
8141
8142 if (has_vga)
8143 lpt_enable_clkout_dp(dev, true, true);
8144 else
8145 lpt_disable_clkout_dp(dev);
8146 }
8147
8148 /*
8149 * Initialize reference clocks when the driver loads
8150 */
8151 void intel_init_pch_refclk(struct drm_device *dev)
8152 {
8153 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8154 ironlake_init_pch_refclk(dev);
8155 else if (HAS_PCH_LPT(dev))
8156 lpt_init_pch_refclk(dev);
8157 }
8158
8159 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8160 {
8161 struct drm_device *dev = crtc_state->base.crtc->dev;
8162 struct drm_i915_private *dev_priv = dev->dev_private;
8163 struct drm_atomic_state *state = crtc_state->base.state;
8164 struct drm_connector *connector;
8165 struct drm_connector_state *connector_state;
8166 struct intel_encoder *encoder;
8167 int num_connectors = 0, i;
8168 bool is_lvds = false;
8169
8170 for_each_connector_in_state(state, connector, connector_state, i) {
8171 if (connector_state->crtc != crtc_state->base.crtc)
8172 continue;
8173
8174 encoder = to_intel_encoder(connector_state->best_encoder);
8175
8176 switch (encoder->type) {
8177 case INTEL_OUTPUT_LVDS:
8178 is_lvds = true;
8179 break;
8180 default:
8181 break;
8182 }
8183 num_connectors++;
8184 }
8185
8186 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8187 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8188 dev_priv->vbt.lvds_ssc_freq);
8189 return dev_priv->vbt.lvds_ssc_freq;
8190 }
8191
8192 return 120000;
8193 }
8194
8195 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8196 {
8197 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8198 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8199 int pipe = intel_crtc->pipe;
8200 uint32_t val;
8201
8202 val = 0;
8203
8204 switch (intel_crtc->config->pipe_bpp) {
8205 case 18:
8206 val |= PIPECONF_6BPC;
8207 break;
8208 case 24:
8209 val |= PIPECONF_8BPC;
8210 break;
8211 case 30:
8212 val |= PIPECONF_10BPC;
8213 break;
8214 case 36:
8215 val |= PIPECONF_12BPC;
8216 break;
8217 default:
8218 /* Case prevented by intel_choose_pipe_bpp_dither. */
8219 BUG();
8220 }
8221
8222 if (intel_crtc->config->dither)
8223 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8224
8225 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8226 val |= PIPECONF_INTERLACED_ILK;
8227 else
8228 val |= PIPECONF_PROGRESSIVE;
8229
8230 if (intel_crtc->config->limited_color_range)
8231 val |= PIPECONF_COLOR_RANGE_SELECT;
8232
8233 I915_WRITE(PIPECONF(pipe), val);
8234 POSTING_READ(PIPECONF(pipe));
8235 }
8236
8237 /*
8238 * Set up the pipe CSC unit.
8239 *
8240 * Currently only full range RGB to limited range RGB conversion
8241 * is supported, but eventually this should handle various
8242 * RGB<->YCbCr scenarios as well.
8243 */
8244 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8245 {
8246 struct drm_device *dev = crtc->dev;
8247 struct drm_i915_private *dev_priv = dev->dev_private;
8248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8249 int pipe = intel_crtc->pipe;
8250 uint16_t coeff = 0x7800; /* 1.0 */
8251
8252 /*
8253 * TODO: Check what kind of values actually come out of the pipe
8254 * with these coeff/postoff values and adjust to get the best
8255 * accuracy. Perhaps we even need to take the bpc value into
8256 * consideration.
8257 */
8258
8259 if (intel_crtc->config->limited_color_range)
8260 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8261
8262 /*
8263 * GY/GU and RY/RU should be the other way around according
8264 * to BSpec, but reality doesn't agree. Just set them up in
8265 * a way that results in the correct picture.
8266 */
8267 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8268 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8269
8270 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8271 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8272
8273 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8274 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8275
8276 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8277 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8278 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8279
8280 if (INTEL_INFO(dev)->gen > 6) {
8281 uint16_t postoff = 0;
8282
8283 if (intel_crtc->config->limited_color_range)
8284 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8285
8286 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8287 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8288 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8289
8290 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8291 } else {
8292 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8293
8294 if (intel_crtc->config->limited_color_range)
8295 mode |= CSC_BLACK_SCREEN_OFFSET;
8296
8297 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8298 }
8299 }
8300
8301 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8302 {
8303 struct drm_device *dev = crtc->dev;
8304 struct drm_i915_private *dev_priv = dev->dev_private;
8305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8306 enum pipe pipe = intel_crtc->pipe;
8307 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8308 uint32_t val;
8309
8310 val = 0;
8311
8312 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8313 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8314
8315 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8316 val |= PIPECONF_INTERLACED_ILK;
8317 else
8318 val |= PIPECONF_PROGRESSIVE;
8319
8320 I915_WRITE(PIPECONF(cpu_transcoder), val);
8321 POSTING_READ(PIPECONF(cpu_transcoder));
8322
8323 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8324 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8325
8326 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8327 val = 0;
8328
8329 switch (intel_crtc->config->pipe_bpp) {
8330 case 18:
8331 val |= PIPEMISC_DITHER_6_BPC;
8332 break;
8333 case 24:
8334 val |= PIPEMISC_DITHER_8_BPC;
8335 break;
8336 case 30:
8337 val |= PIPEMISC_DITHER_10_BPC;
8338 break;
8339 case 36:
8340 val |= PIPEMISC_DITHER_12_BPC;
8341 break;
8342 default:
8343 /* Case prevented by pipe_config_set_bpp. */
8344 BUG();
8345 }
8346
8347 if (intel_crtc->config->dither)
8348 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8349
8350 I915_WRITE(PIPEMISC(pipe), val);
8351 }
8352 }
8353
8354 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8355 struct intel_crtc_state *crtc_state,
8356 intel_clock_t *clock,
8357 bool *has_reduced_clock,
8358 intel_clock_t *reduced_clock)
8359 {
8360 struct drm_device *dev = crtc->dev;
8361 struct drm_i915_private *dev_priv = dev->dev_private;
8362 int refclk;
8363 const intel_limit_t *limit;
8364 bool ret, is_lvds = false;
8365
8366 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
8367
8368 refclk = ironlake_get_refclk(crtc_state);
8369
8370 /*
8371 * Returns a set of divisors for the desired target clock with the given
8372 * refclk, or FALSE. The returned values represent the clock equation:
8373 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8374 */
8375 limit = intel_limit(crtc_state, refclk);
8376 ret = dev_priv->display.find_dpll(limit, crtc_state,
8377 crtc_state->port_clock,
8378 refclk, NULL, clock);
8379 if (!ret)
8380 return false;
8381
8382 if (is_lvds && dev_priv->lvds_downclock_avail) {
8383 /*
8384 * Ensure we match the reduced clock's P to the target clock.
8385 * If the clocks don't match, we can't switch the display clock
8386 * by using the FP0/FP1. In such case we will disable the LVDS
8387 * downclock feature.
8388 */
8389 *has_reduced_clock =
8390 dev_priv->display.find_dpll(limit, crtc_state,
8391 dev_priv->lvds_downclock,
8392 refclk, clock,
8393 reduced_clock);
8394 }
8395
8396 return true;
8397 }
8398
8399 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8400 {
8401 /*
8402 * Account for spread spectrum to avoid
8403 * oversubscribing the link. Max center spread
8404 * is 2.5%; use 5% for safety's sake.
8405 */
8406 u32 bps = target_clock * bpp * 21 / 20;
8407 return DIV_ROUND_UP(bps, link_bw * 8);
8408 }
8409
8410 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8411 {
8412 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8413 }
8414
8415 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8416 struct intel_crtc_state *crtc_state,
8417 u32 *fp,
8418 intel_clock_t *reduced_clock, u32 *fp2)
8419 {
8420 struct drm_crtc *crtc = &intel_crtc->base;
8421 struct drm_device *dev = crtc->dev;
8422 struct drm_i915_private *dev_priv = dev->dev_private;
8423 struct drm_atomic_state *state = crtc_state->base.state;
8424 struct drm_connector *connector;
8425 struct drm_connector_state *connector_state;
8426 struct intel_encoder *encoder;
8427 uint32_t dpll;
8428 int factor, num_connectors = 0, i;
8429 bool is_lvds = false, is_sdvo = false;
8430
8431 for_each_connector_in_state(state, connector, connector_state, i) {
8432 if (connector_state->crtc != crtc_state->base.crtc)
8433 continue;
8434
8435 encoder = to_intel_encoder(connector_state->best_encoder);
8436
8437 switch (encoder->type) {
8438 case INTEL_OUTPUT_LVDS:
8439 is_lvds = true;
8440 break;
8441 case INTEL_OUTPUT_SDVO:
8442 case INTEL_OUTPUT_HDMI:
8443 is_sdvo = true;
8444 break;
8445 default:
8446 break;
8447 }
8448
8449 num_connectors++;
8450 }
8451
8452 /* Enable autotuning of the PLL clock (if permissible) */
8453 factor = 21;
8454 if (is_lvds) {
8455 if ((intel_panel_use_ssc(dev_priv) &&
8456 dev_priv->vbt.lvds_ssc_freq == 100000) ||
8457 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8458 factor = 25;
8459 } else if (crtc_state->sdvo_tv_clock)
8460 factor = 20;
8461
8462 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
8463 *fp |= FP_CB_TUNE;
8464
8465 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8466 *fp2 |= FP_CB_TUNE;
8467
8468 dpll = 0;
8469
8470 if (is_lvds)
8471 dpll |= DPLLB_MODE_LVDS;
8472 else
8473 dpll |= DPLLB_MODE_DAC_SERIAL;
8474
8475 dpll |= (crtc_state->pixel_multiplier - 1)
8476 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
8477
8478 if (is_sdvo)
8479 dpll |= DPLL_SDVO_HIGH_SPEED;
8480 if (crtc_state->has_dp_encoder)
8481 dpll |= DPLL_SDVO_HIGH_SPEED;
8482
8483 /* compute bitmask from p1 value */
8484 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
8485 /* also FPA1 */
8486 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
8487
8488 switch (crtc_state->dpll.p2) {
8489 case 5:
8490 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8491 break;
8492 case 7:
8493 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8494 break;
8495 case 10:
8496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8497 break;
8498 case 14:
8499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8500 break;
8501 }
8502
8503 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
8504 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
8505 else
8506 dpll |= PLL_REF_INPUT_DREFCLK;
8507
8508 return dpll | DPLL_VCO_ENABLE;
8509 }
8510
8511 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8512 struct intel_crtc_state *crtc_state)
8513 {
8514 struct drm_device *dev = crtc->base.dev;
8515 intel_clock_t clock, reduced_clock;
8516 u32 dpll = 0, fp = 0, fp2 = 0;
8517 bool ok, has_reduced_clock = false;
8518 bool is_lvds = false;
8519 struct intel_shared_dpll *pll;
8520
8521 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
8522
8523 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8524 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
8525
8526 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
8527 &has_reduced_clock, &reduced_clock);
8528 if (!ok && !crtc_state->clock_set) {
8529 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8530 return -EINVAL;
8531 }
8532 /* Compat-code for transition, will disappear. */
8533 if (!crtc_state->clock_set) {
8534 crtc_state->dpll.n = clock.n;
8535 crtc_state->dpll.m1 = clock.m1;
8536 crtc_state->dpll.m2 = clock.m2;
8537 crtc_state->dpll.p1 = clock.p1;
8538 crtc_state->dpll.p2 = clock.p2;
8539 }
8540
8541 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8542 if (crtc_state->has_pch_encoder) {
8543 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
8544 if (has_reduced_clock)
8545 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
8546
8547 dpll = ironlake_compute_dpll(crtc, crtc_state,
8548 &fp, &reduced_clock,
8549 has_reduced_clock ? &fp2 : NULL);
8550
8551 crtc_state->dpll_hw_state.dpll = dpll;
8552 crtc_state->dpll_hw_state.fp0 = fp;
8553 if (has_reduced_clock)
8554 crtc_state->dpll_hw_state.fp1 = fp2;
8555 else
8556 crtc_state->dpll_hw_state.fp1 = fp;
8557
8558 pll = intel_get_shared_dpll(crtc, crtc_state);
8559 if (pll == NULL) {
8560 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
8561 pipe_name(crtc->pipe));
8562 return -EINVAL;
8563 }
8564 }
8565
8566 if (is_lvds && has_reduced_clock)
8567 crtc->lowfreq_avail = true;
8568 else
8569 crtc->lowfreq_avail = false;
8570
8571 return 0;
8572 }
8573
8574 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8575 struct intel_link_m_n *m_n)
8576 {
8577 struct drm_device *dev = crtc->base.dev;
8578 struct drm_i915_private *dev_priv = dev->dev_private;
8579 enum pipe pipe = crtc->pipe;
8580
8581 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8582 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8583 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8584 & ~TU_SIZE_MASK;
8585 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8586 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8587 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8588 }
8589
8590 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8591 enum transcoder transcoder,
8592 struct intel_link_m_n *m_n,
8593 struct intel_link_m_n *m2_n2)
8594 {
8595 struct drm_device *dev = crtc->base.dev;
8596 struct drm_i915_private *dev_priv = dev->dev_private;
8597 enum pipe pipe = crtc->pipe;
8598
8599 if (INTEL_INFO(dev)->gen >= 5) {
8600 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8601 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8602 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8603 & ~TU_SIZE_MASK;
8604 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8605 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8606 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8607 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8608 * gen < 8) and if DRRS is supported (to make sure the
8609 * registers are not unnecessarily read).
8610 */
8611 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
8612 crtc->config->has_drrs) {
8613 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8614 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8615 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8616 & ~TU_SIZE_MASK;
8617 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8618 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8619 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8620 }
8621 } else {
8622 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8623 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8624 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8625 & ~TU_SIZE_MASK;
8626 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8627 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8628 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8629 }
8630 }
8631
8632 void intel_dp_get_m_n(struct intel_crtc *crtc,
8633 struct intel_crtc_state *pipe_config)
8634 {
8635 if (pipe_config->has_pch_encoder)
8636 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8637 else
8638 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8639 &pipe_config->dp_m_n,
8640 &pipe_config->dp_m2_n2);
8641 }
8642
8643 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
8644 struct intel_crtc_state *pipe_config)
8645 {
8646 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
8647 &pipe_config->fdi_m_n, NULL);
8648 }
8649
8650 static void skylake_get_pfit_config(struct intel_crtc *crtc,
8651 struct intel_crtc_state *pipe_config)
8652 {
8653 struct drm_device *dev = crtc->base.dev;
8654 struct drm_i915_private *dev_priv = dev->dev_private;
8655 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8656 uint32_t ps_ctrl = 0;
8657 int id = -1;
8658 int i;
8659
8660 /* find scaler attached to this pipe */
8661 for (i = 0; i < crtc->num_scalers; i++) {
8662 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8663 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8664 id = i;
8665 pipe_config->pch_pfit.enabled = true;
8666 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8667 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8668 break;
8669 }
8670 }
8671
8672 scaler_state->scaler_id = id;
8673 if (id >= 0) {
8674 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8675 } else {
8676 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
8677 }
8678 }
8679
8680 static void
8681 skylake_get_initial_plane_config(struct intel_crtc *crtc,
8682 struct intel_initial_plane_config *plane_config)
8683 {
8684 struct drm_device *dev = crtc->base.dev;
8685 struct drm_i915_private *dev_priv = dev->dev_private;
8686 u32 val, base, offset, stride_mult, tiling;
8687 int pipe = crtc->pipe;
8688 int fourcc, pixel_format;
8689 unsigned int aligned_height;
8690 struct drm_framebuffer *fb;
8691 struct intel_framebuffer *intel_fb;
8692
8693 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8694 if (!intel_fb) {
8695 DRM_DEBUG_KMS("failed to alloc fb\n");
8696 return;
8697 }
8698
8699 fb = &intel_fb->base;
8700
8701 val = I915_READ(PLANE_CTL(pipe, 0));
8702 if (!(val & PLANE_CTL_ENABLE))
8703 goto error;
8704
8705 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8706 fourcc = skl_format_to_fourcc(pixel_format,
8707 val & PLANE_CTL_ORDER_RGBX,
8708 val & PLANE_CTL_ALPHA_MASK);
8709 fb->pixel_format = fourcc;
8710 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8711
8712 tiling = val & PLANE_CTL_TILED_MASK;
8713 switch (tiling) {
8714 case PLANE_CTL_TILED_LINEAR:
8715 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8716 break;
8717 case PLANE_CTL_TILED_X:
8718 plane_config->tiling = I915_TILING_X;
8719 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8720 break;
8721 case PLANE_CTL_TILED_Y:
8722 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8723 break;
8724 case PLANE_CTL_TILED_YF:
8725 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8726 break;
8727 default:
8728 MISSING_CASE(tiling);
8729 goto error;
8730 }
8731
8732 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8733 plane_config->base = base;
8734
8735 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8736
8737 val = I915_READ(PLANE_SIZE(pipe, 0));
8738 fb->height = ((val >> 16) & 0xfff) + 1;
8739 fb->width = ((val >> 0) & 0x1fff) + 1;
8740
8741 val = I915_READ(PLANE_STRIDE(pipe, 0));
8742 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8743 fb->pixel_format);
8744 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8745
8746 aligned_height = intel_fb_align_height(dev, fb->height,
8747 fb->pixel_format,
8748 fb->modifier[0]);
8749
8750 plane_config->size = fb->pitches[0] * aligned_height;
8751
8752 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8753 pipe_name(pipe), fb->width, fb->height,
8754 fb->bits_per_pixel, base, fb->pitches[0],
8755 plane_config->size);
8756
8757 plane_config->fb = intel_fb;
8758 return;
8759
8760 error:
8761 kfree(fb);
8762 }
8763
8764 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
8765 struct intel_crtc_state *pipe_config)
8766 {
8767 struct drm_device *dev = crtc->base.dev;
8768 struct drm_i915_private *dev_priv = dev->dev_private;
8769 uint32_t tmp;
8770
8771 tmp = I915_READ(PF_CTL(crtc->pipe));
8772
8773 if (tmp & PF_ENABLE) {
8774 pipe_config->pch_pfit.enabled = true;
8775 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8776 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
8777
8778 /* We currently do not free assignements of panel fitters on
8779 * ivb/hsw (since we don't use the higher upscaling modes which
8780 * differentiates them) so just WARN about this case for now. */
8781 if (IS_GEN7(dev)) {
8782 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8783 PF_PIPE_SEL_IVB(crtc->pipe));
8784 }
8785 }
8786 }
8787
8788 static void
8789 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8790 struct intel_initial_plane_config *plane_config)
8791 {
8792 struct drm_device *dev = crtc->base.dev;
8793 struct drm_i915_private *dev_priv = dev->dev_private;
8794 u32 val, base, offset;
8795 int pipe = crtc->pipe;
8796 int fourcc, pixel_format;
8797 unsigned int aligned_height;
8798 struct drm_framebuffer *fb;
8799 struct intel_framebuffer *intel_fb;
8800
8801 val = I915_READ(DSPCNTR(pipe));
8802 if (!(val & DISPLAY_PLANE_ENABLE))
8803 return;
8804
8805 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8806 if (!intel_fb) {
8807 DRM_DEBUG_KMS("failed to alloc fb\n");
8808 return;
8809 }
8810
8811 fb = &intel_fb->base;
8812
8813 if (INTEL_INFO(dev)->gen >= 4) {
8814 if (val & DISPPLANE_TILED) {
8815 plane_config->tiling = I915_TILING_X;
8816 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8817 }
8818 }
8819
8820 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8821 fourcc = i9xx_format_to_fourcc(pixel_format);
8822 fb->pixel_format = fourcc;
8823 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8824
8825 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
8826 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
8827 offset = I915_READ(DSPOFFSET(pipe));
8828 } else {
8829 if (plane_config->tiling)
8830 offset = I915_READ(DSPTILEOFF(pipe));
8831 else
8832 offset = I915_READ(DSPLINOFF(pipe));
8833 }
8834 plane_config->base = base;
8835
8836 val = I915_READ(PIPESRC(pipe));
8837 fb->width = ((val >> 16) & 0xfff) + 1;
8838 fb->height = ((val >> 0) & 0xfff) + 1;
8839
8840 val = I915_READ(DSPSTRIDE(pipe));
8841 fb->pitches[0] = val & 0xffffffc0;
8842
8843 aligned_height = intel_fb_align_height(dev, fb->height,
8844 fb->pixel_format,
8845 fb->modifier[0]);
8846
8847 plane_config->size = fb->pitches[0] * aligned_height;
8848
8849 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8850 pipe_name(pipe), fb->width, fb->height,
8851 fb->bits_per_pixel, base, fb->pitches[0],
8852 plane_config->size);
8853
8854 plane_config->fb = intel_fb;
8855 }
8856
8857 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
8858 struct intel_crtc_state *pipe_config)
8859 {
8860 struct drm_device *dev = crtc->base.dev;
8861 struct drm_i915_private *dev_priv = dev->dev_private;
8862 uint32_t tmp;
8863
8864 if (!intel_display_power_is_enabled(dev_priv,
8865 POWER_DOMAIN_PIPE(crtc->pipe)))
8866 return false;
8867
8868 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8869 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8870
8871 tmp = I915_READ(PIPECONF(crtc->pipe));
8872 if (!(tmp & PIPECONF_ENABLE))
8873 return false;
8874
8875 switch (tmp & PIPECONF_BPC_MASK) {
8876 case PIPECONF_6BPC:
8877 pipe_config->pipe_bpp = 18;
8878 break;
8879 case PIPECONF_8BPC:
8880 pipe_config->pipe_bpp = 24;
8881 break;
8882 case PIPECONF_10BPC:
8883 pipe_config->pipe_bpp = 30;
8884 break;
8885 case PIPECONF_12BPC:
8886 pipe_config->pipe_bpp = 36;
8887 break;
8888 default:
8889 break;
8890 }
8891
8892 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8893 pipe_config->limited_color_range = true;
8894
8895 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
8896 struct intel_shared_dpll *pll;
8897
8898 pipe_config->has_pch_encoder = true;
8899
8900 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8901 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8902 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8903
8904 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8905
8906 if (HAS_PCH_IBX(dev_priv->dev)) {
8907 pipe_config->shared_dpll =
8908 (enum intel_dpll_id) crtc->pipe;
8909 } else {
8910 tmp = I915_READ(PCH_DPLL_SEL);
8911 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8912 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8913 else
8914 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8915 }
8916
8917 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8918
8919 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8920 &pipe_config->dpll_hw_state));
8921
8922 tmp = pipe_config->dpll_hw_state.dpll;
8923 pipe_config->pixel_multiplier =
8924 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8925 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
8926
8927 ironlake_pch_clock_get(crtc, pipe_config);
8928 } else {
8929 pipe_config->pixel_multiplier = 1;
8930 }
8931
8932 intel_get_pipe_timings(crtc, pipe_config);
8933
8934 ironlake_get_pfit_config(crtc, pipe_config);
8935
8936 return true;
8937 }
8938
8939 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8940 {
8941 struct drm_device *dev = dev_priv->dev;
8942 struct intel_crtc *crtc;
8943
8944 for_each_intel_crtc(dev, crtc)
8945 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
8946 pipe_name(crtc->pipe));
8947
8948 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8949 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8950 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8951 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8952 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8953 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
8954 "CPU PWM1 enabled\n");
8955 if (IS_HASWELL(dev))
8956 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
8957 "CPU PWM2 enabled\n");
8958 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
8959 "PCH PWM1 enabled\n");
8960 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
8961 "Utility pin enabled\n");
8962 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
8963
8964 /*
8965 * In theory we can still leave IRQs enabled, as long as only the HPD
8966 * interrupts remain enabled. We used to check for that, but since it's
8967 * gen-specific and since we only disable LCPLL after we fully disable
8968 * the interrupts, the check below should be enough.
8969 */
8970 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
8971 }
8972
8973 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8974 {
8975 struct drm_device *dev = dev_priv->dev;
8976
8977 if (IS_HASWELL(dev))
8978 return I915_READ(D_COMP_HSW);
8979 else
8980 return I915_READ(D_COMP_BDW);
8981 }
8982
8983 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8984 {
8985 struct drm_device *dev = dev_priv->dev;
8986
8987 if (IS_HASWELL(dev)) {
8988 mutex_lock(&dev_priv->rps.hw_lock);
8989 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8990 val))
8991 DRM_ERROR("Failed to write to D_COMP\n");
8992 mutex_unlock(&dev_priv->rps.hw_lock);
8993 } else {
8994 I915_WRITE(D_COMP_BDW, val);
8995 POSTING_READ(D_COMP_BDW);
8996 }
8997 }
8998
8999 /*
9000 * This function implements pieces of two sequences from BSpec:
9001 * - Sequence for display software to disable LCPLL
9002 * - Sequence for display software to allow package C8+
9003 * The steps implemented here are just the steps that actually touch the LCPLL
9004 * register. Callers should take care of disabling all the display engine
9005 * functions, doing the mode unset, fixing interrupts, etc.
9006 */
9007 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9008 bool switch_to_fclk, bool allow_power_down)
9009 {
9010 uint32_t val;
9011
9012 assert_can_disable_lcpll(dev_priv);
9013
9014 val = I915_READ(LCPLL_CTL);
9015
9016 if (switch_to_fclk) {
9017 val |= LCPLL_CD_SOURCE_FCLK;
9018 I915_WRITE(LCPLL_CTL, val);
9019
9020 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9021 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9022 DRM_ERROR("Switching to FCLK failed\n");
9023
9024 val = I915_READ(LCPLL_CTL);
9025 }
9026
9027 val |= LCPLL_PLL_DISABLE;
9028 I915_WRITE(LCPLL_CTL, val);
9029 POSTING_READ(LCPLL_CTL);
9030
9031 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9032 DRM_ERROR("LCPLL still locked\n");
9033
9034 val = hsw_read_dcomp(dev_priv);
9035 val |= D_COMP_COMP_DISABLE;
9036 hsw_write_dcomp(dev_priv, val);
9037 ndelay(100);
9038
9039 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9040 1))
9041 DRM_ERROR("D_COMP RCOMP still in progress\n");
9042
9043 if (allow_power_down) {
9044 val = I915_READ(LCPLL_CTL);
9045 val |= LCPLL_POWER_DOWN_ALLOW;
9046 I915_WRITE(LCPLL_CTL, val);
9047 POSTING_READ(LCPLL_CTL);
9048 }
9049 }
9050
9051 /*
9052 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9053 * source.
9054 */
9055 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9056 {
9057 uint32_t val;
9058
9059 val = I915_READ(LCPLL_CTL);
9060
9061 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9062 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9063 return;
9064
9065 /*
9066 * Make sure we're not on PC8 state before disabling PC8, otherwise
9067 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9068 */
9069 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9070
9071 if (val & LCPLL_POWER_DOWN_ALLOW) {
9072 val &= ~LCPLL_POWER_DOWN_ALLOW;
9073 I915_WRITE(LCPLL_CTL, val);
9074 POSTING_READ(LCPLL_CTL);
9075 }
9076
9077 val = hsw_read_dcomp(dev_priv);
9078 val |= D_COMP_COMP_FORCE;
9079 val &= ~D_COMP_COMP_DISABLE;
9080 hsw_write_dcomp(dev_priv, val);
9081
9082 val = I915_READ(LCPLL_CTL);
9083 val &= ~LCPLL_PLL_DISABLE;
9084 I915_WRITE(LCPLL_CTL, val);
9085
9086 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9087 DRM_ERROR("LCPLL not locked yet\n");
9088
9089 if (val & LCPLL_CD_SOURCE_FCLK) {
9090 val = I915_READ(LCPLL_CTL);
9091 val &= ~LCPLL_CD_SOURCE_FCLK;
9092 I915_WRITE(LCPLL_CTL, val);
9093
9094 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9095 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9096 DRM_ERROR("Switching back to LCPLL failed\n");
9097 }
9098
9099 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9100 }
9101
9102 /*
9103 * Package states C8 and deeper are really deep PC states that can only be
9104 * reached when all the devices on the system allow it, so even if the graphics
9105 * device allows PC8+, it doesn't mean the system will actually get to these
9106 * states. Our driver only allows PC8+ when going into runtime PM.
9107 *
9108 * The requirements for PC8+ are that all the outputs are disabled, the power
9109 * well is disabled and most interrupts are disabled, and these are also
9110 * requirements for runtime PM. When these conditions are met, we manually do
9111 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9112 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9113 * hang the machine.
9114 *
9115 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9116 * the state of some registers, so when we come back from PC8+ we need to
9117 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9118 * need to take care of the registers kept by RC6. Notice that this happens even
9119 * if we don't put the device in PCI D3 state (which is what currently happens
9120 * because of the runtime PM support).
9121 *
9122 * For more, read "Display Sequences for Package C8" on the hardware
9123 * documentation.
9124 */
9125 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9126 {
9127 struct drm_device *dev = dev_priv->dev;
9128 uint32_t val;
9129
9130 DRM_DEBUG_KMS("Enabling package C8+\n");
9131
9132 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9133 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9134 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9135 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9136 }
9137
9138 lpt_disable_clkout_dp(dev);
9139 hsw_disable_lcpll(dev_priv, true, true);
9140 }
9141
9142 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9143 {
9144 struct drm_device *dev = dev_priv->dev;
9145 uint32_t val;
9146
9147 DRM_DEBUG_KMS("Disabling package C8+\n");
9148
9149 hsw_restore_lcpll(dev_priv);
9150 lpt_init_pch_refclk(dev);
9151
9152 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9153 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9154 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9155 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9156 }
9157
9158 intel_prepare_ddi(dev);
9159 }
9160
9161 static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
9162 {
9163 struct drm_device *dev = old_state->dev;
9164 struct drm_i915_private *dev_priv = dev->dev_private;
9165 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
9166 int req_cdclk;
9167
9168 /* see the comment in valleyview_modeset_global_resources */
9169 if (WARN_ON(max_pixclk < 0))
9170 return;
9171
9172 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9173
9174 if (req_cdclk != dev_priv->cdclk_freq)
9175 broxton_set_cdclk(dev, req_cdclk);
9176 }
9177
9178 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9179 struct intel_crtc_state *crtc_state)
9180 {
9181 if (!intel_ddi_pll_select(crtc, crtc_state))
9182 return -EINVAL;
9183
9184 crtc->lowfreq_avail = false;
9185
9186 return 0;
9187 }
9188
9189 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9190 enum port port,
9191 struct intel_crtc_state *pipe_config)
9192 {
9193 switch (port) {
9194 case PORT_A:
9195 pipe_config->ddi_pll_sel = SKL_DPLL0;
9196 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9197 break;
9198 case PORT_B:
9199 pipe_config->ddi_pll_sel = SKL_DPLL1;
9200 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9201 break;
9202 case PORT_C:
9203 pipe_config->ddi_pll_sel = SKL_DPLL2;
9204 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9205 break;
9206 default:
9207 DRM_ERROR("Incorrect port type\n");
9208 }
9209 }
9210
9211 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9212 enum port port,
9213 struct intel_crtc_state *pipe_config)
9214 {
9215 u32 temp, dpll_ctl1;
9216
9217 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9218 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9219
9220 switch (pipe_config->ddi_pll_sel) {
9221 case SKL_DPLL0:
9222 /*
9223 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9224 * of the shared DPLL framework and thus needs to be read out
9225 * separately
9226 */
9227 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9228 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9229 break;
9230 case SKL_DPLL1:
9231 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9232 break;
9233 case SKL_DPLL2:
9234 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9235 break;
9236 case SKL_DPLL3:
9237 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9238 break;
9239 }
9240 }
9241
9242 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9243 enum port port,
9244 struct intel_crtc_state *pipe_config)
9245 {
9246 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9247
9248 switch (pipe_config->ddi_pll_sel) {
9249 case PORT_CLK_SEL_WRPLL1:
9250 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9251 break;
9252 case PORT_CLK_SEL_WRPLL2:
9253 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9254 break;
9255 }
9256 }
9257
9258 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9259 struct intel_crtc_state *pipe_config)
9260 {
9261 struct drm_device *dev = crtc->base.dev;
9262 struct drm_i915_private *dev_priv = dev->dev_private;
9263 struct intel_shared_dpll *pll;
9264 enum port port;
9265 uint32_t tmp;
9266
9267 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9268
9269 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9270
9271 if (IS_SKYLAKE(dev))
9272 skylake_get_ddi_pll(dev_priv, port, pipe_config);
9273 else if (IS_BROXTON(dev))
9274 bxt_get_ddi_pll(dev_priv, port, pipe_config);
9275 else
9276 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9277
9278 if (pipe_config->shared_dpll >= 0) {
9279 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9280
9281 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9282 &pipe_config->dpll_hw_state));
9283 }
9284
9285 /*
9286 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9287 * DDI E. So just check whether this pipe is wired to DDI E and whether
9288 * the PCH transcoder is on.
9289 */
9290 if (INTEL_INFO(dev)->gen < 9 &&
9291 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
9292 pipe_config->has_pch_encoder = true;
9293
9294 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9295 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9296 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9297
9298 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9299 }
9300 }
9301
9302 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
9303 struct intel_crtc_state *pipe_config)
9304 {
9305 struct drm_device *dev = crtc->base.dev;
9306 struct drm_i915_private *dev_priv = dev->dev_private;
9307 enum intel_display_power_domain pfit_domain;
9308 uint32_t tmp;
9309
9310 if (!intel_display_power_is_enabled(dev_priv,
9311 POWER_DOMAIN_PIPE(crtc->pipe)))
9312 return false;
9313
9314 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9315 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9316
9317 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9318 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9319 enum pipe trans_edp_pipe;
9320 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9321 default:
9322 WARN(1, "unknown pipe linked to edp transcoder\n");
9323 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9324 case TRANS_DDI_EDP_INPUT_A_ON:
9325 trans_edp_pipe = PIPE_A;
9326 break;
9327 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9328 trans_edp_pipe = PIPE_B;
9329 break;
9330 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9331 trans_edp_pipe = PIPE_C;
9332 break;
9333 }
9334
9335 if (trans_edp_pipe == crtc->pipe)
9336 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9337 }
9338
9339 if (!intel_display_power_is_enabled(dev_priv,
9340 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
9341 return false;
9342
9343 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
9344 if (!(tmp & PIPECONF_ENABLE))
9345 return false;
9346
9347 haswell_get_ddi_port_state(crtc, pipe_config);
9348
9349 intel_get_pipe_timings(crtc, pipe_config);
9350
9351 if (INTEL_INFO(dev)->gen >= 9) {
9352 skl_init_scalers(dev, crtc, pipe_config);
9353 }
9354
9355 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
9356 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
9357 if (INTEL_INFO(dev)->gen == 9)
9358 skylake_get_pfit_config(crtc, pipe_config);
9359 else if (INTEL_INFO(dev)->gen < 9)
9360 ironlake_get_pfit_config(crtc, pipe_config);
9361 else
9362 MISSING_CASE(INTEL_INFO(dev)->gen);
9363
9364 } else {
9365 pipe_config->scaler_state.scaler_id = -1;
9366 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9367 }
9368
9369 if (IS_HASWELL(dev))
9370 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9371 (I915_READ(IPS_CTL) & IPS_ENABLE);
9372
9373 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9374 pipe_config->pixel_multiplier =
9375 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9376 } else {
9377 pipe_config->pixel_multiplier = 1;
9378 }
9379
9380 return true;
9381 }
9382
9383 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9384 {
9385 struct drm_device *dev = crtc->dev;
9386 struct drm_i915_private *dev_priv = dev->dev_private;
9387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9388 uint32_t cntl = 0, size = 0;
9389
9390 if (base) {
9391 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9392 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
9393 unsigned int stride = roundup_pow_of_two(width) * 4;
9394
9395 switch (stride) {
9396 default:
9397 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9398 width, stride);
9399 stride = 256;
9400 /* fallthrough */
9401 case 256:
9402 case 512:
9403 case 1024:
9404 case 2048:
9405 break;
9406 }
9407
9408 cntl |= CURSOR_ENABLE |
9409 CURSOR_GAMMA_ENABLE |
9410 CURSOR_FORMAT_ARGB |
9411 CURSOR_STRIDE(stride);
9412
9413 size = (height << 12) | width;
9414 }
9415
9416 if (intel_crtc->cursor_cntl != 0 &&
9417 (intel_crtc->cursor_base != base ||
9418 intel_crtc->cursor_size != size ||
9419 intel_crtc->cursor_cntl != cntl)) {
9420 /* On these chipsets we can only modify the base/size/stride
9421 * whilst the cursor is disabled.
9422 */
9423 I915_WRITE(_CURACNTR, 0);
9424 POSTING_READ(_CURACNTR);
9425 intel_crtc->cursor_cntl = 0;
9426 }
9427
9428 if (intel_crtc->cursor_base != base) {
9429 I915_WRITE(_CURABASE, base);
9430 intel_crtc->cursor_base = base;
9431 }
9432
9433 if (intel_crtc->cursor_size != size) {
9434 I915_WRITE(CURSIZE, size);
9435 intel_crtc->cursor_size = size;
9436 }
9437
9438 if (intel_crtc->cursor_cntl != cntl) {
9439 I915_WRITE(_CURACNTR, cntl);
9440 POSTING_READ(_CURACNTR);
9441 intel_crtc->cursor_cntl = cntl;
9442 }
9443 }
9444
9445 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
9446 {
9447 struct drm_device *dev = crtc->dev;
9448 struct drm_i915_private *dev_priv = dev->dev_private;
9449 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9450 int pipe = intel_crtc->pipe;
9451 uint32_t cntl;
9452
9453 cntl = 0;
9454 if (base) {
9455 cntl = MCURSOR_GAMMA_ENABLE;
9456 switch (intel_crtc->base.cursor->state->crtc_w) {
9457 case 64:
9458 cntl |= CURSOR_MODE_64_ARGB_AX;
9459 break;
9460 case 128:
9461 cntl |= CURSOR_MODE_128_ARGB_AX;
9462 break;
9463 case 256:
9464 cntl |= CURSOR_MODE_256_ARGB_AX;
9465 break;
9466 default:
9467 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
9468 return;
9469 }
9470 cntl |= pipe << 28; /* Connect to correct pipe */
9471
9472 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9473 cntl |= CURSOR_PIPE_CSC_ENABLE;
9474 }
9475
9476 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
9477 cntl |= CURSOR_ROTATE_180;
9478
9479 if (intel_crtc->cursor_cntl != cntl) {
9480 I915_WRITE(CURCNTR(pipe), cntl);
9481 POSTING_READ(CURCNTR(pipe));
9482 intel_crtc->cursor_cntl = cntl;
9483 }
9484
9485 /* and commit changes on next vblank */
9486 I915_WRITE(CURBASE(pipe), base);
9487 POSTING_READ(CURBASE(pipe));
9488
9489 intel_crtc->cursor_base = base;
9490 }
9491
9492 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
9493 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9494 bool on)
9495 {
9496 struct drm_device *dev = crtc->dev;
9497 struct drm_i915_private *dev_priv = dev->dev_private;
9498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9499 int pipe = intel_crtc->pipe;
9500 int x = crtc->cursor_x;
9501 int y = crtc->cursor_y;
9502 u32 base = 0, pos = 0;
9503
9504 if (on)
9505 base = intel_crtc->cursor_addr;
9506
9507 if (x >= intel_crtc->config->pipe_src_w)
9508 base = 0;
9509
9510 if (y >= intel_crtc->config->pipe_src_h)
9511 base = 0;
9512
9513 if (x < 0) {
9514 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
9515 base = 0;
9516
9517 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9518 x = -x;
9519 }
9520 pos |= x << CURSOR_X_SHIFT;
9521
9522 if (y < 0) {
9523 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
9524 base = 0;
9525
9526 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9527 y = -y;
9528 }
9529 pos |= y << CURSOR_Y_SHIFT;
9530
9531 if (base == 0 && intel_crtc->cursor_base == 0)
9532 return;
9533
9534 I915_WRITE(CURPOS(pipe), pos);
9535
9536 /* ILK+ do this automagically */
9537 if (HAS_GMCH_DISPLAY(dev) &&
9538 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
9539 base += (intel_crtc->base.cursor->state->crtc_h *
9540 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
9541 }
9542
9543 if (IS_845G(dev) || IS_I865G(dev))
9544 i845_update_cursor(crtc, base);
9545 else
9546 i9xx_update_cursor(crtc, base);
9547 }
9548
9549 static bool cursor_size_ok(struct drm_device *dev,
9550 uint32_t width, uint32_t height)
9551 {
9552 if (width == 0 || height == 0)
9553 return false;
9554
9555 /*
9556 * 845g/865g are special in that they are only limited by
9557 * the width of their cursors, the height is arbitrary up to
9558 * the precision of the register. Everything else requires
9559 * square cursors, limited to a few power-of-two sizes.
9560 */
9561 if (IS_845G(dev) || IS_I865G(dev)) {
9562 if ((width & 63) != 0)
9563 return false;
9564
9565 if (width > (IS_845G(dev) ? 64 : 512))
9566 return false;
9567
9568 if (height > 1023)
9569 return false;
9570 } else {
9571 switch (width | height) {
9572 case 256:
9573 case 128:
9574 if (IS_GEN2(dev))
9575 return false;
9576 case 64:
9577 break;
9578 default:
9579 return false;
9580 }
9581 }
9582
9583 return true;
9584 }
9585
9586 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
9587 u16 *blue, uint32_t start, uint32_t size)
9588 {
9589 int end = (start + size > 256) ? 256 : start + size, i;
9590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9591
9592 for (i = start; i < end; i++) {
9593 intel_crtc->lut_r[i] = red[i] >> 8;
9594 intel_crtc->lut_g[i] = green[i] >> 8;
9595 intel_crtc->lut_b[i] = blue[i] >> 8;
9596 }
9597
9598 intel_crtc_load_lut(crtc);
9599 }
9600
9601 /* VESA 640x480x72Hz mode to set on the pipe */
9602 static struct drm_display_mode load_detect_mode = {
9603 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9604 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9605 };
9606
9607 struct drm_framebuffer *
9608 __intel_framebuffer_create(struct drm_device *dev,
9609 struct drm_mode_fb_cmd2 *mode_cmd,
9610 struct drm_i915_gem_object *obj)
9611 {
9612 struct intel_framebuffer *intel_fb;
9613 int ret;
9614
9615 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9616 if (!intel_fb) {
9617 drm_gem_object_unreference(&obj->base);
9618 return ERR_PTR(-ENOMEM);
9619 }
9620
9621 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
9622 if (ret)
9623 goto err;
9624
9625 return &intel_fb->base;
9626 err:
9627 drm_gem_object_unreference(&obj->base);
9628 kfree(intel_fb);
9629
9630 return ERR_PTR(ret);
9631 }
9632
9633 static struct drm_framebuffer *
9634 intel_framebuffer_create(struct drm_device *dev,
9635 struct drm_mode_fb_cmd2 *mode_cmd,
9636 struct drm_i915_gem_object *obj)
9637 {
9638 struct drm_framebuffer *fb;
9639 int ret;
9640
9641 ret = i915_mutex_lock_interruptible(dev);
9642 if (ret)
9643 return ERR_PTR(ret);
9644 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9645 mutex_unlock(&dev->struct_mutex);
9646
9647 return fb;
9648 }
9649
9650 static u32
9651 intel_framebuffer_pitch_for_width(int width, int bpp)
9652 {
9653 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9654 return ALIGN(pitch, 64);
9655 }
9656
9657 static u32
9658 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9659 {
9660 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
9661 return PAGE_ALIGN(pitch * mode->vdisplay);
9662 }
9663
9664 static struct drm_framebuffer *
9665 intel_framebuffer_create_for_mode(struct drm_device *dev,
9666 struct drm_display_mode *mode,
9667 int depth, int bpp)
9668 {
9669 struct drm_i915_gem_object *obj;
9670 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
9671
9672 obj = i915_gem_alloc_object(dev,
9673 intel_framebuffer_size_for_mode(mode, bpp));
9674 if (obj == NULL)
9675 return ERR_PTR(-ENOMEM);
9676
9677 mode_cmd.width = mode->hdisplay;
9678 mode_cmd.height = mode->vdisplay;
9679 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9680 bpp);
9681 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
9682
9683 return intel_framebuffer_create(dev, &mode_cmd, obj);
9684 }
9685
9686 static struct drm_framebuffer *
9687 mode_fits_in_fbdev(struct drm_device *dev,
9688 struct drm_display_mode *mode)
9689 {
9690 #ifdef CONFIG_DRM_I915_FBDEV
9691 struct drm_i915_private *dev_priv = dev->dev_private;
9692 struct drm_i915_gem_object *obj;
9693 struct drm_framebuffer *fb;
9694
9695 if (!dev_priv->fbdev)
9696 return NULL;
9697
9698 if (!dev_priv->fbdev->fb)
9699 return NULL;
9700
9701 obj = dev_priv->fbdev->fb->obj;
9702 BUG_ON(!obj);
9703
9704 fb = &dev_priv->fbdev->fb->base;
9705 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9706 fb->bits_per_pixel))
9707 return NULL;
9708
9709 if (obj->base.size < mode->vdisplay * fb->pitches[0])
9710 return NULL;
9711
9712 return fb;
9713 #else
9714 return NULL;
9715 #endif
9716 }
9717
9718 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9719 struct drm_crtc *crtc,
9720 struct drm_display_mode *mode,
9721 struct drm_framebuffer *fb,
9722 int x, int y)
9723 {
9724 struct drm_plane_state *plane_state;
9725 int hdisplay, vdisplay;
9726 int ret;
9727
9728 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9729 if (IS_ERR(plane_state))
9730 return PTR_ERR(plane_state);
9731
9732 if (mode)
9733 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9734 else
9735 hdisplay = vdisplay = 0;
9736
9737 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9738 if (ret)
9739 return ret;
9740 drm_atomic_set_fb_for_plane(plane_state, fb);
9741 plane_state->crtc_x = 0;
9742 plane_state->crtc_y = 0;
9743 plane_state->crtc_w = hdisplay;
9744 plane_state->crtc_h = vdisplay;
9745 plane_state->src_x = x << 16;
9746 plane_state->src_y = y << 16;
9747 plane_state->src_w = hdisplay << 16;
9748 plane_state->src_h = vdisplay << 16;
9749
9750 return 0;
9751 }
9752
9753 bool intel_get_load_detect_pipe(struct drm_connector *connector,
9754 struct drm_display_mode *mode,
9755 struct intel_load_detect_pipe *old,
9756 struct drm_modeset_acquire_ctx *ctx)
9757 {
9758 struct intel_crtc *intel_crtc;
9759 struct intel_encoder *intel_encoder =
9760 intel_attached_encoder(connector);
9761 struct drm_crtc *possible_crtc;
9762 struct drm_encoder *encoder = &intel_encoder->base;
9763 struct drm_crtc *crtc = NULL;
9764 struct drm_device *dev = encoder->dev;
9765 struct drm_framebuffer *fb;
9766 struct drm_mode_config *config = &dev->mode_config;
9767 struct drm_atomic_state *state = NULL;
9768 struct drm_connector_state *connector_state;
9769 struct intel_crtc_state *crtc_state;
9770 int ret, i = -1;
9771
9772 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9773 connector->base.id, connector->name,
9774 encoder->base.id, encoder->name);
9775
9776 retry:
9777 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9778 if (ret)
9779 goto fail_unlock;
9780
9781 /*
9782 * Algorithm gets a little messy:
9783 *
9784 * - if the connector already has an assigned crtc, use it (but make
9785 * sure it's on first)
9786 *
9787 * - try to find the first unused crtc that can drive this connector,
9788 * and use that if we find one
9789 */
9790
9791 /* See if we already have a CRTC for this connector */
9792 if (encoder->crtc) {
9793 crtc = encoder->crtc;
9794
9795 ret = drm_modeset_lock(&crtc->mutex, ctx);
9796 if (ret)
9797 goto fail_unlock;
9798 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9799 if (ret)
9800 goto fail_unlock;
9801
9802 old->dpms_mode = connector->dpms;
9803 old->load_detect_temp = false;
9804
9805 /* Make sure the crtc and connector are running */
9806 if (connector->dpms != DRM_MODE_DPMS_ON)
9807 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
9808
9809 return true;
9810 }
9811
9812 /* Find an unused one (if possible) */
9813 for_each_crtc(dev, possible_crtc) {
9814 i++;
9815 if (!(encoder->possible_crtcs & (1 << i)))
9816 continue;
9817 if (possible_crtc->state->enable)
9818 continue;
9819 /* This can occur when applying the pipe A quirk on resume. */
9820 if (to_intel_crtc(possible_crtc)->new_enabled)
9821 continue;
9822
9823 crtc = possible_crtc;
9824 break;
9825 }
9826
9827 /*
9828 * If we didn't find an unused CRTC, don't use any.
9829 */
9830 if (!crtc) {
9831 DRM_DEBUG_KMS("no pipe available for load-detect\n");
9832 goto fail_unlock;
9833 }
9834
9835 ret = drm_modeset_lock(&crtc->mutex, ctx);
9836 if (ret)
9837 goto fail_unlock;
9838 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9839 if (ret)
9840 goto fail_unlock;
9841 intel_encoder->new_crtc = to_intel_crtc(crtc);
9842 to_intel_connector(connector)->new_encoder = intel_encoder;
9843
9844 intel_crtc = to_intel_crtc(crtc);
9845 intel_crtc->new_enabled = true;
9846 old->dpms_mode = connector->dpms;
9847 old->load_detect_temp = true;
9848 old->release_fb = NULL;
9849
9850 state = drm_atomic_state_alloc(dev);
9851 if (!state)
9852 return false;
9853
9854 state->acquire_ctx = ctx;
9855
9856 connector_state = drm_atomic_get_connector_state(state, connector);
9857 if (IS_ERR(connector_state)) {
9858 ret = PTR_ERR(connector_state);
9859 goto fail;
9860 }
9861
9862 connector_state->crtc = crtc;
9863 connector_state->best_encoder = &intel_encoder->base;
9864
9865 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9866 if (IS_ERR(crtc_state)) {
9867 ret = PTR_ERR(crtc_state);
9868 goto fail;
9869 }
9870
9871 crtc_state->base.active = crtc_state->base.enable = true;
9872
9873 if (!mode)
9874 mode = &load_detect_mode;
9875
9876 /* We need a framebuffer large enough to accommodate all accesses
9877 * that the plane may generate whilst we perform load detection.
9878 * We can not rely on the fbcon either being present (we get called
9879 * during its initialisation to detect all boot displays, or it may
9880 * not even exist) or that it is large enough to satisfy the
9881 * requested mode.
9882 */
9883 fb = mode_fits_in_fbdev(dev, mode);
9884 if (fb == NULL) {
9885 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
9886 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9887 old->release_fb = fb;
9888 } else
9889 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
9890 if (IS_ERR(fb)) {
9891 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
9892 goto fail;
9893 }
9894
9895 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9896 if (ret)
9897 goto fail;
9898
9899 drm_mode_copy(&crtc_state->base.mode, mode);
9900
9901 if (intel_set_mode(crtc, state)) {
9902 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
9903 if (old->release_fb)
9904 old->release_fb->funcs->destroy(old->release_fb);
9905 goto fail;
9906 }
9907 crtc->primary->crtc = crtc;
9908
9909 /* let the connector get through one full cycle before testing */
9910 intel_wait_for_vblank(dev, intel_crtc->pipe);
9911 return true;
9912
9913 fail:
9914 intel_crtc->new_enabled = crtc->state->enable;
9915 fail_unlock:
9916 drm_atomic_state_free(state);
9917 state = NULL;
9918
9919 if (ret == -EDEADLK) {
9920 drm_modeset_backoff(ctx);
9921 goto retry;
9922 }
9923
9924 return false;
9925 }
9926
9927 void intel_release_load_detect_pipe(struct drm_connector *connector,
9928 struct intel_load_detect_pipe *old,
9929 struct drm_modeset_acquire_ctx *ctx)
9930 {
9931 struct drm_device *dev = connector->dev;
9932 struct intel_encoder *intel_encoder =
9933 intel_attached_encoder(connector);
9934 struct drm_encoder *encoder = &intel_encoder->base;
9935 struct drm_crtc *crtc = encoder->crtc;
9936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9937 struct drm_atomic_state *state;
9938 struct drm_connector_state *connector_state;
9939 struct intel_crtc_state *crtc_state;
9940 int ret;
9941
9942 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
9943 connector->base.id, connector->name,
9944 encoder->base.id, encoder->name);
9945
9946 if (old->load_detect_temp) {
9947 state = drm_atomic_state_alloc(dev);
9948 if (!state)
9949 goto fail;
9950
9951 state->acquire_ctx = ctx;
9952
9953 connector_state = drm_atomic_get_connector_state(state, connector);
9954 if (IS_ERR(connector_state))
9955 goto fail;
9956
9957 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9958 if (IS_ERR(crtc_state))
9959 goto fail;
9960
9961 to_intel_connector(connector)->new_encoder = NULL;
9962 intel_encoder->new_crtc = NULL;
9963 intel_crtc->new_enabled = false;
9964
9965 connector_state->best_encoder = NULL;
9966 connector_state->crtc = NULL;
9967
9968 crtc_state->base.enable = crtc_state->base.active = false;
9969
9970 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9971 0, 0);
9972 if (ret)
9973 goto fail;
9974
9975 ret = intel_set_mode(crtc, state);
9976 if (ret)
9977 goto fail;
9978
9979 if (old->release_fb) {
9980 drm_framebuffer_unregister_private(old->release_fb);
9981 drm_framebuffer_unreference(old->release_fb);
9982 }
9983
9984 return;
9985 }
9986
9987 /* Switch crtc and encoder back off if necessary */
9988 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9989 connector->funcs->dpms(connector, old->dpms_mode);
9990
9991 return;
9992 fail:
9993 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9994 drm_atomic_state_free(state);
9995 }
9996
9997 static int i9xx_pll_refclk(struct drm_device *dev,
9998 const struct intel_crtc_state *pipe_config)
9999 {
10000 struct drm_i915_private *dev_priv = dev->dev_private;
10001 u32 dpll = pipe_config->dpll_hw_state.dpll;
10002
10003 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10004 return dev_priv->vbt.lvds_ssc_freq;
10005 else if (HAS_PCH_SPLIT(dev))
10006 return 120000;
10007 else if (!IS_GEN2(dev))
10008 return 96000;
10009 else
10010 return 48000;
10011 }
10012
10013 /* Returns the clock of the currently programmed mode of the given pipe. */
10014 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10015 struct intel_crtc_state *pipe_config)
10016 {
10017 struct drm_device *dev = crtc->base.dev;
10018 struct drm_i915_private *dev_priv = dev->dev_private;
10019 int pipe = pipe_config->cpu_transcoder;
10020 u32 dpll = pipe_config->dpll_hw_state.dpll;
10021 u32 fp;
10022 intel_clock_t clock;
10023 int refclk = i9xx_pll_refclk(dev, pipe_config);
10024
10025 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10026 fp = pipe_config->dpll_hw_state.fp0;
10027 else
10028 fp = pipe_config->dpll_hw_state.fp1;
10029
10030 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10031 if (IS_PINEVIEW(dev)) {
10032 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10033 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10034 } else {
10035 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10036 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10037 }
10038
10039 if (!IS_GEN2(dev)) {
10040 if (IS_PINEVIEW(dev))
10041 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10042 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10043 else
10044 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10045 DPLL_FPA01_P1_POST_DIV_SHIFT);
10046
10047 switch (dpll & DPLL_MODE_MASK) {
10048 case DPLLB_MODE_DAC_SERIAL:
10049 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10050 5 : 10;
10051 break;
10052 case DPLLB_MODE_LVDS:
10053 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10054 7 : 14;
10055 break;
10056 default:
10057 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10058 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10059 return;
10060 }
10061
10062 if (IS_PINEVIEW(dev))
10063 pineview_clock(refclk, &clock);
10064 else
10065 i9xx_clock(refclk, &clock);
10066 } else {
10067 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10068 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10069
10070 if (is_lvds) {
10071 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10072 DPLL_FPA01_P1_POST_DIV_SHIFT);
10073
10074 if (lvds & LVDS_CLKB_POWER_UP)
10075 clock.p2 = 7;
10076 else
10077 clock.p2 = 14;
10078 } else {
10079 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10080 clock.p1 = 2;
10081 else {
10082 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10083 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10084 }
10085 if (dpll & PLL_P2_DIVIDE_BY_4)
10086 clock.p2 = 4;
10087 else
10088 clock.p2 = 2;
10089 }
10090
10091 i9xx_clock(refclk, &clock);
10092 }
10093
10094 /*
10095 * This value includes pixel_multiplier. We will use
10096 * port_clock to compute adjusted_mode.crtc_clock in the
10097 * encoder's get_config() function.
10098 */
10099 pipe_config->port_clock = clock.dot;
10100 }
10101
10102 int intel_dotclock_calculate(int link_freq,
10103 const struct intel_link_m_n *m_n)
10104 {
10105 /*
10106 * The calculation for the data clock is:
10107 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10108 * But we want to avoid losing precison if possible, so:
10109 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10110 *
10111 * and the link clock is simpler:
10112 * link_clock = (m * link_clock) / n
10113 */
10114
10115 if (!m_n->link_n)
10116 return 0;
10117
10118 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10119 }
10120
10121 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10122 struct intel_crtc_state *pipe_config)
10123 {
10124 struct drm_device *dev = crtc->base.dev;
10125
10126 /* read out port_clock from the DPLL */
10127 i9xx_crtc_clock_get(crtc, pipe_config);
10128
10129 /*
10130 * This value does not include pixel_multiplier.
10131 * We will check that port_clock and adjusted_mode.crtc_clock
10132 * agree once we know their relationship in the encoder's
10133 * get_config() function.
10134 */
10135 pipe_config->base.adjusted_mode.crtc_clock =
10136 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10137 &pipe_config->fdi_m_n);
10138 }
10139
10140 /** Returns the currently programmed mode of the given pipe. */
10141 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10142 struct drm_crtc *crtc)
10143 {
10144 struct drm_i915_private *dev_priv = dev->dev_private;
10145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10146 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10147 struct drm_display_mode *mode;
10148 struct intel_crtc_state pipe_config;
10149 int htot = I915_READ(HTOTAL(cpu_transcoder));
10150 int hsync = I915_READ(HSYNC(cpu_transcoder));
10151 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10152 int vsync = I915_READ(VSYNC(cpu_transcoder));
10153 enum pipe pipe = intel_crtc->pipe;
10154
10155 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10156 if (!mode)
10157 return NULL;
10158
10159 /*
10160 * Construct a pipe_config sufficient for getting the clock info
10161 * back out of crtc_clock_get.
10162 *
10163 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10164 * to use a real value here instead.
10165 */
10166 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10167 pipe_config.pixel_multiplier = 1;
10168 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10169 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10170 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10171 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10172
10173 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10174 mode->hdisplay = (htot & 0xffff) + 1;
10175 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10176 mode->hsync_start = (hsync & 0xffff) + 1;
10177 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10178 mode->vdisplay = (vtot & 0xffff) + 1;
10179 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10180 mode->vsync_start = (vsync & 0xffff) + 1;
10181 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10182
10183 drm_mode_set_name(mode);
10184
10185 return mode;
10186 }
10187
10188 static void intel_decrease_pllclock(struct drm_crtc *crtc)
10189 {
10190 struct drm_device *dev = crtc->dev;
10191 struct drm_i915_private *dev_priv = dev->dev_private;
10192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10193
10194 if (!HAS_GMCH_DISPLAY(dev))
10195 return;
10196
10197 if (!dev_priv->lvds_downclock_avail)
10198 return;
10199
10200 /*
10201 * Since this is called by a timer, we should never get here in
10202 * the manual case.
10203 */
10204 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
10205 int pipe = intel_crtc->pipe;
10206 int dpll_reg = DPLL(pipe);
10207 int dpll;
10208
10209 DRM_DEBUG_DRIVER("downclocking LVDS\n");
10210
10211 assert_panel_unlocked(dev_priv, pipe);
10212
10213 dpll = I915_READ(dpll_reg);
10214 dpll |= DISPLAY_RATE_SELECT_FPA1;
10215 I915_WRITE(dpll_reg, dpll);
10216 intel_wait_for_vblank(dev, pipe);
10217 dpll = I915_READ(dpll_reg);
10218 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
10219 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
10220 }
10221
10222 }
10223
10224 void intel_mark_busy(struct drm_device *dev)
10225 {
10226 struct drm_i915_private *dev_priv = dev->dev_private;
10227
10228 if (dev_priv->mm.busy)
10229 return;
10230
10231 intel_runtime_pm_get(dev_priv);
10232 i915_update_gfx_val(dev_priv);
10233 if (INTEL_INFO(dev)->gen >= 6)
10234 gen6_rps_busy(dev_priv);
10235 dev_priv->mm.busy = true;
10236 }
10237
10238 void intel_mark_idle(struct drm_device *dev)
10239 {
10240 struct drm_i915_private *dev_priv = dev->dev_private;
10241 struct drm_crtc *crtc;
10242
10243 if (!dev_priv->mm.busy)
10244 return;
10245
10246 dev_priv->mm.busy = false;
10247
10248 for_each_crtc(dev, crtc) {
10249 if (!crtc->primary->fb)
10250 continue;
10251
10252 intel_decrease_pllclock(crtc);
10253 }
10254
10255 if (INTEL_INFO(dev)->gen >= 6)
10256 gen6_rps_idle(dev->dev_private);
10257
10258 intel_runtime_pm_put(dev_priv);
10259 }
10260
10261 static void intel_crtc_destroy(struct drm_crtc *crtc)
10262 {
10263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10264 struct drm_device *dev = crtc->dev;
10265 struct intel_unpin_work *work;
10266
10267 spin_lock_irq(&dev->event_lock);
10268 work = intel_crtc->unpin_work;
10269 intel_crtc->unpin_work = NULL;
10270 spin_unlock_irq(&dev->event_lock);
10271
10272 if (work) {
10273 cancel_work_sync(&work->work);
10274 kfree(work);
10275 }
10276
10277 drm_crtc_cleanup(crtc);
10278
10279 kfree(intel_crtc);
10280 }
10281
10282 static void intel_unpin_work_fn(struct work_struct *__work)
10283 {
10284 struct intel_unpin_work *work =
10285 container_of(__work, struct intel_unpin_work, work);
10286 struct drm_device *dev = work->crtc->dev;
10287 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
10288
10289 mutex_lock(&dev->struct_mutex);
10290 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
10291 drm_gem_object_unreference(&work->pending_flip_obj->base);
10292
10293 intel_fbc_update(dev);
10294
10295 if (work->flip_queued_req)
10296 i915_gem_request_assign(&work->flip_queued_req, NULL);
10297 mutex_unlock(&dev->struct_mutex);
10298
10299 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
10300 drm_framebuffer_unreference(work->old_fb);
10301
10302 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10303 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10304
10305 kfree(work);
10306 }
10307
10308 static void do_intel_finish_page_flip(struct drm_device *dev,
10309 struct drm_crtc *crtc)
10310 {
10311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10312 struct intel_unpin_work *work;
10313 unsigned long flags;
10314
10315 /* Ignore early vblank irqs */
10316 if (intel_crtc == NULL)
10317 return;
10318
10319 /*
10320 * This is called both by irq handlers and the reset code (to complete
10321 * lost pageflips) so needs the full irqsave spinlocks.
10322 */
10323 spin_lock_irqsave(&dev->event_lock, flags);
10324 work = intel_crtc->unpin_work;
10325
10326 /* Ensure we don't miss a work->pending update ... */
10327 smp_rmb();
10328
10329 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
10330 spin_unlock_irqrestore(&dev->event_lock, flags);
10331 return;
10332 }
10333
10334 page_flip_completed(intel_crtc);
10335
10336 spin_unlock_irqrestore(&dev->event_lock, flags);
10337 }
10338
10339 void intel_finish_page_flip(struct drm_device *dev, int pipe)
10340 {
10341 struct drm_i915_private *dev_priv = dev->dev_private;
10342 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10343
10344 do_intel_finish_page_flip(dev, crtc);
10345 }
10346
10347 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10348 {
10349 struct drm_i915_private *dev_priv = dev->dev_private;
10350 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10351
10352 do_intel_finish_page_flip(dev, crtc);
10353 }
10354
10355 /* Is 'a' after or equal to 'b'? */
10356 static bool g4x_flip_count_after_eq(u32 a, u32 b)
10357 {
10358 return !((a - b) & 0x80000000);
10359 }
10360
10361 static bool page_flip_finished(struct intel_crtc *crtc)
10362 {
10363 struct drm_device *dev = crtc->base.dev;
10364 struct drm_i915_private *dev_priv = dev->dev_private;
10365
10366 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10367 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10368 return true;
10369
10370 /*
10371 * The relevant registers doen't exist on pre-ctg.
10372 * As the flip done interrupt doesn't trigger for mmio
10373 * flips on gmch platforms, a flip count check isn't
10374 * really needed there. But since ctg has the registers,
10375 * include it in the check anyway.
10376 */
10377 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10378 return true;
10379
10380 /*
10381 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10382 * used the same base address. In that case the mmio flip might
10383 * have completed, but the CS hasn't even executed the flip yet.
10384 *
10385 * A flip count check isn't enough as the CS might have updated
10386 * the base address just after start of vblank, but before we
10387 * managed to process the interrupt. This means we'd complete the
10388 * CS flip too soon.
10389 *
10390 * Combining both checks should get us a good enough result. It may
10391 * still happen that the CS flip has been executed, but has not
10392 * yet actually completed. But in case the base address is the same
10393 * anyway, we don't really care.
10394 */
10395 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10396 crtc->unpin_work->gtt_offset &&
10397 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10398 crtc->unpin_work->flip_count);
10399 }
10400
10401 void intel_prepare_page_flip(struct drm_device *dev, int plane)
10402 {
10403 struct drm_i915_private *dev_priv = dev->dev_private;
10404 struct intel_crtc *intel_crtc =
10405 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10406 unsigned long flags;
10407
10408
10409 /*
10410 * This is called both by irq handlers and the reset code (to complete
10411 * lost pageflips) so needs the full irqsave spinlocks.
10412 *
10413 * NB: An MMIO update of the plane base pointer will also
10414 * generate a page-flip completion irq, i.e. every modeset
10415 * is also accompanied by a spurious intel_prepare_page_flip().
10416 */
10417 spin_lock_irqsave(&dev->event_lock, flags);
10418 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
10419 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
10420 spin_unlock_irqrestore(&dev->event_lock, flags);
10421 }
10422
10423 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
10424 {
10425 /* Ensure that the work item is consistent when activating it ... */
10426 smp_wmb();
10427 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10428 /* and that it is marked active as soon as the irq could fire. */
10429 smp_wmb();
10430 }
10431
10432 static int intel_gen2_queue_flip(struct drm_device *dev,
10433 struct drm_crtc *crtc,
10434 struct drm_framebuffer *fb,
10435 struct drm_i915_gem_object *obj,
10436 struct intel_engine_cs *ring,
10437 uint32_t flags)
10438 {
10439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10440 u32 flip_mask;
10441 int ret;
10442
10443 ret = intel_ring_begin(ring, 6);
10444 if (ret)
10445 return ret;
10446
10447 /* Can't queue multiple flips, so wait for the previous
10448 * one to finish before executing the next.
10449 */
10450 if (intel_crtc->plane)
10451 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10452 else
10453 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10454 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10455 intel_ring_emit(ring, MI_NOOP);
10456 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10457 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10458 intel_ring_emit(ring, fb->pitches[0]);
10459 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10460 intel_ring_emit(ring, 0); /* aux display base address, unused */
10461
10462 intel_mark_page_flip_active(intel_crtc);
10463 __intel_ring_advance(ring);
10464 return 0;
10465 }
10466
10467 static int intel_gen3_queue_flip(struct drm_device *dev,
10468 struct drm_crtc *crtc,
10469 struct drm_framebuffer *fb,
10470 struct drm_i915_gem_object *obj,
10471 struct intel_engine_cs *ring,
10472 uint32_t flags)
10473 {
10474 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10475 u32 flip_mask;
10476 int ret;
10477
10478 ret = intel_ring_begin(ring, 6);
10479 if (ret)
10480 return ret;
10481
10482 if (intel_crtc->plane)
10483 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10484 else
10485 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
10486 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10487 intel_ring_emit(ring, MI_NOOP);
10488 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10489 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10490 intel_ring_emit(ring, fb->pitches[0]);
10491 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10492 intel_ring_emit(ring, MI_NOOP);
10493
10494 intel_mark_page_flip_active(intel_crtc);
10495 __intel_ring_advance(ring);
10496 return 0;
10497 }
10498
10499 static int intel_gen4_queue_flip(struct drm_device *dev,
10500 struct drm_crtc *crtc,
10501 struct drm_framebuffer *fb,
10502 struct drm_i915_gem_object *obj,
10503 struct intel_engine_cs *ring,
10504 uint32_t flags)
10505 {
10506 struct drm_i915_private *dev_priv = dev->dev_private;
10507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10508 uint32_t pf, pipesrc;
10509 int ret;
10510
10511 ret = intel_ring_begin(ring, 4);
10512 if (ret)
10513 return ret;
10514
10515 /* i965+ uses the linear or tiled offsets from the
10516 * Display Registers (which do not change across a page-flip)
10517 * so we need only reprogram the base address.
10518 */
10519 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10520 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10521 intel_ring_emit(ring, fb->pitches[0]);
10522 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
10523 obj->tiling_mode);
10524
10525 /* XXX Enabling the panel-fitter across page-flip is so far
10526 * untested on non-native modes, so ignore it for now.
10527 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10528 */
10529 pf = 0;
10530 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10531 intel_ring_emit(ring, pf | pipesrc);
10532
10533 intel_mark_page_flip_active(intel_crtc);
10534 __intel_ring_advance(ring);
10535 return 0;
10536 }
10537
10538 static int intel_gen6_queue_flip(struct drm_device *dev,
10539 struct drm_crtc *crtc,
10540 struct drm_framebuffer *fb,
10541 struct drm_i915_gem_object *obj,
10542 struct intel_engine_cs *ring,
10543 uint32_t flags)
10544 {
10545 struct drm_i915_private *dev_priv = dev->dev_private;
10546 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10547 uint32_t pf, pipesrc;
10548 int ret;
10549
10550 ret = intel_ring_begin(ring, 4);
10551 if (ret)
10552 return ret;
10553
10554 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10555 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10556 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
10557 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10558
10559 /* Contrary to the suggestions in the documentation,
10560 * "Enable Panel Fitter" does not seem to be required when page
10561 * flipping with a non-native mode, and worse causes a normal
10562 * modeset to fail.
10563 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10564 */
10565 pf = 0;
10566 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
10567 intel_ring_emit(ring, pf | pipesrc);
10568
10569 intel_mark_page_flip_active(intel_crtc);
10570 __intel_ring_advance(ring);
10571 return 0;
10572 }
10573
10574 static int intel_gen7_queue_flip(struct drm_device *dev,
10575 struct drm_crtc *crtc,
10576 struct drm_framebuffer *fb,
10577 struct drm_i915_gem_object *obj,
10578 struct intel_engine_cs *ring,
10579 uint32_t flags)
10580 {
10581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10582 uint32_t plane_bit = 0;
10583 int len, ret;
10584
10585 switch (intel_crtc->plane) {
10586 case PLANE_A:
10587 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10588 break;
10589 case PLANE_B:
10590 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10591 break;
10592 case PLANE_C:
10593 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10594 break;
10595 default:
10596 WARN_ONCE(1, "unknown plane in flip command\n");
10597 return -ENODEV;
10598 }
10599
10600 len = 4;
10601 if (ring->id == RCS) {
10602 len += 6;
10603 /*
10604 * On Gen 8, SRM is now taking an extra dword to accommodate
10605 * 48bits addresses, and we need a NOOP for the batch size to
10606 * stay even.
10607 */
10608 if (IS_GEN8(dev))
10609 len += 2;
10610 }
10611
10612 /*
10613 * BSpec MI_DISPLAY_FLIP for IVB:
10614 * "The full packet must be contained within the same cache line."
10615 *
10616 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10617 * cacheline, if we ever start emitting more commands before
10618 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10619 * then do the cacheline alignment, and finally emit the
10620 * MI_DISPLAY_FLIP.
10621 */
10622 ret = intel_ring_cacheline_align(ring);
10623 if (ret)
10624 return ret;
10625
10626 ret = intel_ring_begin(ring, len);
10627 if (ret)
10628 return ret;
10629
10630 /* Unmask the flip-done completion message. Note that the bspec says that
10631 * we should do this for both the BCS and RCS, and that we must not unmask
10632 * more than one flip event at any time (or ensure that one flip message
10633 * can be sent by waiting for flip-done prior to queueing new flips).
10634 * Experimentation says that BCS works despite DERRMR masking all
10635 * flip-done completion events and that unmasking all planes at once
10636 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10637 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10638 */
10639 if (ring->id == RCS) {
10640 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10641 intel_ring_emit(ring, DERRMR);
10642 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10643 DERRMR_PIPEB_PRI_FLIP_DONE |
10644 DERRMR_PIPEC_PRI_FLIP_DONE));
10645 if (IS_GEN8(dev))
10646 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10647 MI_SRM_LRM_GLOBAL_GTT);
10648 else
10649 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10650 MI_SRM_LRM_GLOBAL_GTT);
10651 intel_ring_emit(ring, DERRMR);
10652 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
10653 if (IS_GEN8(dev)) {
10654 intel_ring_emit(ring, 0);
10655 intel_ring_emit(ring, MI_NOOP);
10656 }
10657 }
10658
10659 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
10660 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
10661 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
10662 intel_ring_emit(ring, (MI_NOOP));
10663
10664 intel_mark_page_flip_active(intel_crtc);
10665 __intel_ring_advance(ring);
10666 return 0;
10667 }
10668
10669 static bool use_mmio_flip(struct intel_engine_cs *ring,
10670 struct drm_i915_gem_object *obj)
10671 {
10672 /*
10673 * This is not being used for older platforms, because
10674 * non-availability of flip done interrupt forces us to use
10675 * CS flips. Older platforms derive flip done using some clever
10676 * tricks involving the flip_pending status bits and vblank irqs.
10677 * So using MMIO flips there would disrupt this mechanism.
10678 */
10679
10680 if (ring == NULL)
10681 return true;
10682
10683 if (INTEL_INFO(ring->dev)->gen < 5)
10684 return false;
10685
10686 if (i915.use_mmio_flip < 0)
10687 return false;
10688 else if (i915.use_mmio_flip > 0)
10689 return true;
10690 else if (i915.enable_execlists)
10691 return true;
10692 else
10693 return ring != i915_gem_request_get_ring(obj->last_read_req);
10694 }
10695
10696 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10697 {
10698 struct drm_device *dev = intel_crtc->base.dev;
10699 struct drm_i915_private *dev_priv = dev->dev_private;
10700 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
10701 const enum pipe pipe = intel_crtc->pipe;
10702 u32 ctl, stride;
10703
10704 ctl = I915_READ(PLANE_CTL(pipe, 0));
10705 ctl &= ~PLANE_CTL_TILED_MASK;
10706 switch (fb->modifier[0]) {
10707 case DRM_FORMAT_MOD_NONE:
10708 break;
10709 case I915_FORMAT_MOD_X_TILED:
10710 ctl |= PLANE_CTL_TILED_X;
10711 break;
10712 case I915_FORMAT_MOD_Y_TILED:
10713 ctl |= PLANE_CTL_TILED_Y;
10714 break;
10715 case I915_FORMAT_MOD_Yf_TILED:
10716 ctl |= PLANE_CTL_TILED_YF;
10717 break;
10718 default:
10719 MISSING_CASE(fb->modifier[0]);
10720 }
10721
10722 /*
10723 * The stride is either expressed as a multiple of 64 bytes chunks for
10724 * linear buffers or in number of tiles for tiled buffers.
10725 */
10726 stride = fb->pitches[0] /
10727 intel_fb_stride_alignment(dev, fb->modifier[0],
10728 fb->pixel_format);
10729
10730 /*
10731 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10732 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10733 */
10734 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10735 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10736
10737 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10738 POSTING_READ(PLANE_SURF(pipe, 0));
10739 }
10740
10741 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
10742 {
10743 struct drm_device *dev = intel_crtc->base.dev;
10744 struct drm_i915_private *dev_priv = dev->dev_private;
10745 struct intel_framebuffer *intel_fb =
10746 to_intel_framebuffer(intel_crtc->base.primary->fb);
10747 struct drm_i915_gem_object *obj = intel_fb->obj;
10748 u32 dspcntr;
10749 u32 reg;
10750
10751 reg = DSPCNTR(intel_crtc->plane);
10752 dspcntr = I915_READ(reg);
10753
10754 if (obj->tiling_mode != I915_TILING_NONE)
10755 dspcntr |= DISPPLANE_TILED;
10756 else
10757 dspcntr &= ~DISPPLANE_TILED;
10758
10759 I915_WRITE(reg, dspcntr);
10760
10761 I915_WRITE(DSPSURF(intel_crtc->plane),
10762 intel_crtc->unpin_work->gtt_offset);
10763 POSTING_READ(DSPSURF(intel_crtc->plane));
10764
10765 }
10766
10767 /*
10768 * XXX: This is the temporary way to update the plane registers until we get
10769 * around to using the usual plane update functions for MMIO flips
10770 */
10771 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10772 {
10773 struct drm_device *dev = intel_crtc->base.dev;
10774 bool atomic_update;
10775 u32 start_vbl_count;
10776
10777 intel_mark_page_flip_active(intel_crtc);
10778
10779 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10780
10781 if (INTEL_INFO(dev)->gen >= 9)
10782 skl_do_mmio_flip(intel_crtc);
10783 else
10784 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10785 ilk_do_mmio_flip(intel_crtc);
10786
10787 if (atomic_update)
10788 intel_pipe_update_end(intel_crtc, start_vbl_count);
10789 }
10790
10791 static void intel_mmio_flip_work_func(struct work_struct *work)
10792 {
10793 struct intel_crtc *crtc =
10794 container_of(work, struct intel_crtc, mmio_flip.work);
10795 struct intel_mmio_flip *mmio_flip;
10796
10797 mmio_flip = &crtc->mmio_flip;
10798 if (mmio_flip->req)
10799 WARN_ON(__i915_wait_request(mmio_flip->req,
10800 crtc->reset_counter,
10801 false, NULL, NULL) != 0);
10802
10803 intel_do_mmio_flip(crtc);
10804 if (mmio_flip->req) {
10805 mutex_lock(&crtc->base.dev->struct_mutex);
10806 i915_gem_request_assign(&mmio_flip->req, NULL);
10807 mutex_unlock(&crtc->base.dev->struct_mutex);
10808 }
10809 }
10810
10811 static int intel_queue_mmio_flip(struct drm_device *dev,
10812 struct drm_crtc *crtc,
10813 struct drm_framebuffer *fb,
10814 struct drm_i915_gem_object *obj,
10815 struct intel_engine_cs *ring,
10816 uint32_t flags)
10817 {
10818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10819
10820 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10821 obj->last_write_req);
10822
10823 schedule_work(&intel_crtc->mmio_flip.work);
10824
10825 return 0;
10826 }
10827
10828 static int intel_default_queue_flip(struct drm_device *dev,
10829 struct drm_crtc *crtc,
10830 struct drm_framebuffer *fb,
10831 struct drm_i915_gem_object *obj,
10832 struct intel_engine_cs *ring,
10833 uint32_t flags)
10834 {
10835 return -ENODEV;
10836 }
10837
10838 static bool __intel_pageflip_stall_check(struct drm_device *dev,
10839 struct drm_crtc *crtc)
10840 {
10841 struct drm_i915_private *dev_priv = dev->dev_private;
10842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10843 struct intel_unpin_work *work = intel_crtc->unpin_work;
10844 u32 addr;
10845
10846 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10847 return true;
10848
10849 if (!work->enable_stall_check)
10850 return false;
10851
10852 if (work->flip_ready_vblank == 0) {
10853 if (work->flip_queued_req &&
10854 !i915_gem_request_completed(work->flip_queued_req, true))
10855 return false;
10856
10857 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
10858 }
10859
10860 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
10861 return false;
10862
10863 /* Potential stall - if we see that the flip has happened,
10864 * assume a missed interrupt. */
10865 if (INTEL_INFO(dev)->gen >= 4)
10866 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10867 else
10868 addr = I915_READ(DSPADDR(intel_crtc->plane));
10869
10870 /* There is a potential issue here with a false positive after a flip
10871 * to the same address. We could address this by checking for a
10872 * non-incrementing frame counter.
10873 */
10874 return addr == work->gtt_offset;
10875 }
10876
10877 void intel_check_page_flip(struct drm_device *dev, int pipe)
10878 {
10879 struct drm_i915_private *dev_priv = dev->dev_private;
10880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10882 struct intel_unpin_work *work;
10883
10884 WARN_ON(!in_interrupt());
10885
10886 if (crtc == NULL)
10887 return;
10888
10889 spin_lock(&dev->event_lock);
10890 work = intel_crtc->unpin_work;
10891 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
10892 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
10893 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
10894 page_flip_completed(intel_crtc);
10895 work = NULL;
10896 }
10897 if (work != NULL &&
10898 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10899 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
10900 spin_unlock(&dev->event_lock);
10901 }
10902
10903 static int intel_crtc_page_flip(struct drm_crtc *crtc,
10904 struct drm_framebuffer *fb,
10905 struct drm_pending_vblank_event *event,
10906 uint32_t page_flip_flags)
10907 {
10908 struct drm_device *dev = crtc->dev;
10909 struct drm_i915_private *dev_priv = dev->dev_private;
10910 struct drm_framebuffer *old_fb = crtc->primary->fb;
10911 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10912 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10913 struct drm_plane *primary = crtc->primary;
10914 enum pipe pipe = intel_crtc->pipe;
10915 struct intel_unpin_work *work;
10916 struct intel_engine_cs *ring;
10917 bool mmio_flip;
10918 int ret;
10919
10920 /*
10921 * drm_mode_page_flip_ioctl() should already catch this, but double
10922 * check to be safe. In the future we may enable pageflipping from
10923 * a disabled primary plane.
10924 */
10925 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10926 return -EBUSY;
10927
10928 /* Can't change pixel format via MI display flips. */
10929 if (fb->pixel_format != crtc->primary->fb->pixel_format)
10930 return -EINVAL;
10931
10932 /*
10933 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10934 * Note that pitch changes could also affect these register.
10935 */
10936 if (INTEL_INFO(dev)->gen > 3 &&
10937 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10938 fb->pitches[0] != crtc->primary->fb->pitches[0]))
10939 return -EINVAL;
10940
10941 if (i915_terminally_wedged(&dev_priv->gpu_error))
10942 goto out_hang;
10943
10944 work = kzalloc(sizeof(*work), GFP_KERNEL);
10945 if (work == NULL)
10946 return -ENOMEM;
10947
10948 work->event = event;
10949 work->crtc = crtc;
10950 work->old_fb = old_fb;
10951 INIT_WORK(&work->work, intel_unpin_work_fn);
10952
10953 ret = drm_crtc_vblank_get(crtc);
10954 if (ret)
10955 goto free_work;
10956
10957 /* We borrow the event spin lock for protecting unpin_work */
10958 spin_lock_irq(&dev->event_lock);
10959 if (intel_crtc->unpin_work) {
10960 /* Before declaring the flip queue wedged, check if
10961 * the hardware completed the operation behind our backs.
10962 */
10963 if (__intel_pageflip_stall_check(dev, crtc)) {
10964 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10965 page_flip_completed(intel_crtc);
10966 } else {
10967 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
10968 spin_unlock_irq(&dev->event_lock);
10969
10970 drm_crtc_vblank_put(crtc);
10971 kfree(work);
10972 return -EBUSY;
10973 }
10974 }
10975 intel_crtc->unpin_work = work;
10976 spin_unlock_irq(&dev->event_lock);
10977
10978 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10979 flush_workqueue(dev_priv->wq);
10980
10981 /* Reference the objects for the scheduled work. */
10982 drm_framebuffer_reference(work->old_fb);
10983 drm_gem_object_reference(&obj->base);
10984
10985 crtc->primary->fb = fb;
10986 update_state_fb(crtc->primary);
10987
10988 work->pending_flip_obj = obj;
10989
10990 ret = i915_mutex_lock_interruptible(dev);
10991 if (ret)
10992 goto cleanup;
10993
10994 atomic_inc(&intel_crtc->unpin_work_count);
10995 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
10996
10997 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
10998 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
10999
11000 if (IS_VALLEYVIEW(dev)) {
11001 ring = &dev_priv->ring[BCS];
11002 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11003 /* vlv: DISPLAY_FLIP fails to change tiling */
11004 ring = NULL;
11005 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11006 ring = &dev_priv->ring[BCS];
11007 } else if (INTEL_INFO(dev)->gen >= 7) {
11008 ring = i915_gem_request_get_ring(obj->last_read_req);
11009 if (ring == NULL || ring->id != RCS)
11010 ring = &dev_priv->ring[BCS];
11011 } else {
11012 ring = &dev_priv->ring[RCS];
11013 }
11014
11015 mmio_flip = use_mmio_flip(ring, obj);
11016
11017 /* When using CS flips, we want to emit semaphores between rings.
11018 * However, when using mmio flips we will create a task to do the
11019 * synchronisation, so all we want here is to pin the framebuffer
11020 * into the display plane and skip any waits.
11021 */
11022 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11023 crtc->primary->state,
11024 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
11025 if (ret)
11026 goto cleanup_pending;
11027
11028 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11029 + intel_crtc->dspaddr_offset;
11030
11031 if (mmio_flip) {
11032 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11033 page_flip_flags);
11034 if (ret)
11035 goto cleanup_unpin;
11036
11037 i915_gem_request_assign(&work->flip_queued_req,
11038 obj->last_write_req);
11039 } else {
11040 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
11041 page_flip_flags);
11042 if (ret)
11043 goto cleanup_unpin;
11044
11045 i915_gem_request_assign(&work->flip_queued_req,
11046 intel_ring_get_request(ring));
11047 }
11048
11049 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11050 work->enable_stall_check = true;
11051
11052 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11053 INTEL_FRONTBUFFER_PRIMARY(pipe));
11054
11055 intel_fbc_disable(dev);
11056 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11057 mutex_unlock(&dev->struct_mutex);
11058
11059 trace_i915_flip_request(intel_crtc->plane, obj);
11060
11061 return 0;
11062
11063 cleanup_unpin:
11064 intel_unpin_fb_obj(fb, crtc->primary->state);
11065 cleanup_pending:
11066 atomic_dec(&intel_crtc->unpin_work_count);
11067 mutex_unlock(&dev->struct_mutex);
11068 cleanup:
11069 crtc->primary->fb = old_fb;
11070 update_state_fb(crtc->primary);
11071
11072 drm_gem_object_unreference_unlocked(&obj->base);
11073 drm_framebuffer_unreference(work->old_fb);
11074
11075 spin_lock_irq(&dev->event_lock);
11076 intel_crtc->unpin_work = NULL;
11077 spin_unlock_irq(&dev->event_lock);
11078
11079 drm_crtc_vblank_put(crtc);
11080 free_work:
11081 kfree(work);
11082
11083 if (ret == -EIO) {
11084 out_hang:
11085 ret = intel_plane_restore(primary);
11086 if (ret == 0 && event) {
11087 spin_lock_irq(&dev->event_lock);
11088 drm_send_vblank_event(dev, pipe, event);
11089 spin_unlock_irq(&dev->event_lock);
11090 }
11091 }
11092 return ret;
11093 }
11094
11095 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
11096 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11097 .load_lut = intel_crtc_load_lut,
11098 .atomic_begin = intel_begin_crtc_commit,
11099 .atomic_flush = intel_finish_crtc_commit,
11100 };
11101
11102 /**
11103 * intel_modeset_update_staged_output_state
11104 *
11105 * Updates the staged output configuration state, e.g. after we've read out the
11106 * current hw state.
11107 */
11108 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
11109 {
11110 struct intel_crtc *crtc;
11111 struct intel_encoder *encoder;
11112 struct intel_connector *connector;
11113
11114 for_each_intel_connector(dev, connector) {
11115 connector->new_encoder =
11116 to_intel_encoder(connector->base.encoder);
11117 }
11118
11119 for_each_intel_encoder(dev, encoder) {
11120 encoder->new_crtc =
11121 to_intel_crtc(encoder->base.crtc);
11122 }
11123
11124 for_each_intel_crtc(dev, crtc) {
11125 crtc->new_enabled = crtc->base.state->enable;
11126 }
11127 }
11128
11129 /* Transitional helper to copy current connector/encoder state to
11130 * connector->state. This is needed so that code that is partially
11131 * converted to atomic does the right thing.
11132 */
11133 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11134 {
11135 struct intel_connector *connector;
11136
11137 for_each_intel_connector(dev, connector) {
11138 if (connector->base.encoder) {
11139 connector->base.state->best_encoder =
11140 connector->base.encoder;
11141 connector->base.state->crtc =
11142 connector->base.encoder->crtc;
11143 } else {
11144 connector->base.state->best_encoder = NULL;
11145 connector->base.state->crtc = NULL;
11146 }
11147 }
11148 }
11149
11150 /* Fixup legacy state after an atomic state swap.
11151 */
11152 static void intel_modeset_fixup_state(struct drm_atomic_state *state)
11153 {
11154 struct intel_crtc *crtc;
11155 struct intel_encoder *encoder;
11156 struct intel_connector *connector;
11157
11158 for_each_intel_connector(state->dev, connector) {
11159 connector->base.encoder = connector->base.state->best_encoder;
11160 if (connector->base.encoder)
11161 connector->base.encoder->crtc =
11162 connector->base.state->crtc;
11163 }
11164
11165 /* Update crtc of disabled encoders */
11166 for_each_intel_encoder(state->dev, encoder) {
11167 int num_connectors = 0;
11168
11169 for_each_intel_connector(state->dev, connector)
11170 if (connector->base.encoder == &encoder->base)
11171 num_connectors++;
11172
11173 if (num_connectors == 0)
11174 encoder->base.crtc = NULL;
11175 }
11176
11177 for_each_intel_crtc(state->dev, crtc) {
11178 crtc->base.enabled = crtc->base.state->enable;
11179 crtc->config = to_intel_crtc_state(crtc->base.state);
11180 }
11181
11182 /* Copy the new configuration to the staged state, to keep the few
11183 * pieces of code that haven't been converted yet happy */
11184 intel_modeset_update_staged_output_state(state->dev);
11185 }
11186
11187 static void
11188 connected_sink_compute_bpp(struct intel_connector *connector,
11189 struct intel_crtc_state *pipe_config)
11190 {
11191 int bpp = pipe_config->pipe_bpp;
11192
11193 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11194 connector->base.base.id,
11195 connector->base.name);
11196
11197 /* Don't use an invalid EDID bpc value */
11198 if (connector->base.display_info.bpc &&
11199 connector->base.display_info.bpc * 3 < bpp) {
11200 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11201 bpp, connector->base.display_info.bpc*3);
11202 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11203 }
11204
11205 /* Clamp bpp to 8 on screens without EDID 1.4 */
11206 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11207 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11208 bpp);
11209 pipe_config->pipe_bpp = 24;
11210 }
11211 }
11212
11213 static int
11214 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
11215 struct intel_crtc_state *pipe_config)
11216 {
11217 struct drm_device *dev = crtc->base.dev;
11218 struct drm_atomic_state *state;
11219 struct drm_connector *connector;
11220 struct drm_connector_state *connector_state;
11221 int bpp, i;
11222
11223 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
11224 bpp = 10*3;
11225 else if (INTEL_INFO(dev)->gen >= 5)
11226 bpp = 12*3;
11227 else
11228 bpp = 8*3;
11229
11230
11231 pipe_config->pipe_bpp = bpp;
11232
11233 state = pipe_config->base.state;
11234
11235 /* Clamp display bpp to EDID value */
11236 for_each_connector_in_state(state, connector, connector_state, i) {
11237 if (connector_state->crtc != &crtc->base)
11238 continue;
11239
11240 connected_sink_compute_bpp(to_intel_connector(connector),
11241 pipe_config);
11242 }
11243
11244 return bpp;
11245 }
11246
11247 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11248 {
11249 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11250 "type: 0x%x flags: 0x%x\n",
11251 mode->crtc_clock,
11252 mode->crtc_hdisplay, mode->crtc_hsync_start,
11253 mode->crtc_hsync_end, mode->crtc_htotal,
11254 mode->crtc_vdisplay, mode->crtc_vsync_start,
11255 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11256 }
11257
11258 static void intel_dump_pipe_config(struct intel_crtc *crtc,
11259 struct intel_crtc_state *pipe_config,
11260 const char *context)
11261 {
11262 struct drm_device *dev = crtc->base.dev;
11263 struct drm_plane *plane;
11264 struct intel_plane *intel_plane;
11265 struct intel_plane_state *state;
11266 struct drm_framebuffer *fb;
11267
11268 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11269 context, pipe_config, pipe_name(crtc->pipe));
11270
11271 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11272 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11273 pipe_config->pipe_bpp, pipe_config->dither);
11274 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11275 pipe_config->has_pch_encoder,
11276 pipe_config->fdi_lanes,
11277 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11278 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11279 pipe_config->fdi_m_n.tu);
11280 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11281 pipe_config->has_dp_encoder,
11282 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11283 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11284 pipe_config->dp_m_n.tu);
11285
11286 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11287 pipe_config->has_dp_encoder,
11288 pipe_config->dp_m2_n2.gmch_m,
11289 pipe_config->dp_m2_n2.gmch_n,
11290 pipe_config->dp_m2_n2.link_m,
11291 pipe_config->dp_m2_n2.link_n,
11292 pipe_config->dp_m2_n2.tu);
11293
11294 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11295 pipe_config->has_audio,
11296 pipe_config->has_infoframe);
11297
11298 DRM_DEBUG_KMS("requested mode:\n");
11299 drm_mode_debug_printmodeline(&pipe_config->base.mode);
11300 DRM_DEBUG_KMS("adjusted mode:\n");
11301 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11302 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
11303 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
11304 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11305 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
11306 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11307 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11308 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
11309 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11310 pipe_config->gmch_pfit.control,
11311 pipe_config->gmch_pfit.pgm_ratios,
11312 pipe_config->gmch_pfit.lvds_border_bits);
11313 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
11314 pipe_config->pch_pfit.pos,
11315 pipe_config->pch_pfit.size,
11316 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
11317 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
11318 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
11319
11320 DRM_DEBUG_KMS("planes on this crtc\n");
11321 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11322 intel_plane = to_intel_plane(plane);
11323 if (intel_plane->pipe != crtc->pipe)
11324 continue;
11325
11326 state = to_intel_plane_state(plane->state);
11327 fb = state->base.fb;
11328 if (!fb) {
11329 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11330 "disabled, scaler_id = %d\n",
11331 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11332 plane->base.id, intel_plane->pipe,
11333 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11334 drm_plane_index(plane), state->scaler_id);
11335 continue;
11336 }
11337
11338 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11339 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11340 plane->base.id, intel_plane->pipe,
11341 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11342 drm_plane_index(plane));
11343 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11344 fb->base.id, fb->width, fb->height, fb->pixel_format);
11345 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11346 state->scaler_id,
11347 state->src.x1 >> 16, state->src.y1 >> 16,
11348 drm_rect_width(&state->src) >> 16,
11349 drm_rect_height(&state->src) >> 16,
11350 state->dst.x1, state->dst.y1,
11351 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11352 }
11353 }
11354
11355 static bool encoders_cloneable(const struct intel_encoder *a,
11356 const struct intel_encoder *b)
11357 {
11358 /* masks could be asymmetric, so check both ways */
11359 return a == b || (a->cloneable & (1 << b->type) &&
11360 b->cloneable & (1 << a->type));
11361 }
11362
11363 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11364 struct intel_crtc *crtc,
11365 struct intel_encoder *encoder)
11366 {
11367 struct intel_encoder *source_encoder;
11368 struct drm_connector *connector;
11369 struct drm_connector_state *connector_state;
11370 int i;
11371
11372 for_each_connector_in_state(state, connector, connector_state, i) {
11373 if (connector_state->crtc != &crtc->base)
11374 continue;
11375
11376 source_encoder =
11377 to_intel_encoder(connector_state->best_encoder);
11378 if (!encoders_cloneable(encoder, source_encoder))
11379 return false;
11380 }
11381
11382 return true;
11383 }
11384
11385 static bool check_encoder_cloning(struct drm_atomic_state *state,
11386 struct intel_crtc *crtc)
11387 {
11388 struct intel_encoder *encoder;
11389 struct drm_connector *connector;
11390 struct drm_connector_state *connector_state;
11391 int i;
11392
11393 for_each_connector_in_state(state, connector, connector_state, i) {
11394 if (connector_state->crtc != &crtc->base)
11395 continue;
11396
11397 encoder = to_intel_encoder(connector_state->best_encoder);
11398 if (!check_single_encoder_cloning(state, crtc, encoder))
11399 return false;
11400 }
11401
11402 return true;
11403 }
11404
11405 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
11406 {
11407 struct drm_device *dev = state->dev;
11408 struct intel_encoder *encoder;
11409 struct drm_connector *connector;
11410 struct drm_connector_state *connector_state;
11411 unsigned int used_ports = 0;
11412 int i;
11413
11414 /*
11415 * Walk the connector list instead of the encoder
11416 * list to detect the problem on ddi platforms
11417 * where there's just one encoder per digital port.
11418 */
11419 for_each_connector_in_state(state, connector, connector_state, i) {
11420 if (!connector_state->best_encoder)
11421 continue;
11422
11423 encoder = to_intel_encoder(connector_state->best_encoder);
11424
11425 WARN_ON(!connector_state->crtc);
11426
11427 switch (encoder->type) {
11428 unsigned int port_mask;
11429 case INTEL_OUTPUT_UNKNOWN:
11430 if (WARN_ON(!HAS_DDI(dev)))
11431 break;
11432 case INTEL_OUTPUT_DISPLAYPORT:
11433 case INTEL_OUTPUT_HDMI:
11434 case INTEL_OUTPUT_EDP:
11435 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11436
11437 /* the same port mustn't appear more than once */
11438 if (used_ports & port_mask)
11439 return false;
11440
11441 used_ports |= port_mask;
11442 default:
11443 break;
11444 }
11445 }
11446
11447 return true;
11448 }
11449
11450 static void
11451 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11452 {
11453 struct drm_crtc_state tmp_state;
11454 struct intel_crtc_scaler_state scaler_state;
11455 struct intel_dpll_hw_state dpll_hw_state;
11456 enum intel_dpll_id shared_dpll;
11457
11458 /* Clear only the intel specific part of the crtc state excluding scalers */
11459 tmp_state = crtc_state->base;
11460 scaler_state = crtc_state->scaler_state;
11461 shared_dpll = crtc_state->shared_dpll;
11462 dpll_hw_state = crtc_state->dpll_hw_state;
11463
11464 memset(crtc_state, 0, sizeof *crtc_state);
11465
11466 crtc_state->base = tmp_state;
11467 crtc_state->scaler_state = scaler_state;
11468 crtc_state->shared_dpll = shared_dpll;
11469 crtc_state->dpll_hw_state = dpll_hw_state;
11470 }
11471
11472 static int
11473 intel_modeset_pipe_config(struct drm_crtc *crtc,
11474 struct drm_atomic_state *state,
11475 struct intel_crtc_state *pipe_config)
11476 {
11477 struct intel_encoder *encoder;
11478 struct drm_connector *connector;
11479 struct drm_connector_state *connector_state;
11480 int base_bpp, ret = -EINVAL;
11481 int i;
11482 bool retry = true;
11483
11484 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
11485 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11486 return -EINVAL;
11487 }
11488
11489 if (!check_digital_port_conflicts(state)) {
11490 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11491 return -EINVAL;
11492 }
11493
11494 clear_intel_crtc_state(pipe_config);
11495
11496 pipe_config->cpu_transcoder =
11497 (enum transcoder) to_intel_crtc(crtc)->pipe;
11498
11499 /*
11500 * Sanitize sync polarity flags based on requested ones. If neither
11501 * positive or negative polarity is requested, treat this as meaning
11502 * negative polarity.
11503 */
11504 if (!(pipe_config->base.adjusted_mode.flags &
11505 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
11506 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
11507
11508 if (!(pipe_config->base.adjusted_mode.flags &
11509 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
11510 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
11511
11512 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11513 * plane pixel format and any sink constraints into account. Returns the
11514 * source plane bpp so that dithering can be selected on mismatches
11515 * after encoders and crtc also have had their say. */
11516 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11517 pipe_config);
11518 if (base_bpp < 0)
11519 goto fail;
11520
11521 /*
11522 * Determine the real pipe dimensions. Note that stereo modes can
11523 * increase the actual pipe size due to the frame doubling and
11524 * insertion of additional space for blanks between the frame. This
11525 * is stored in the crtc timings. We use the requested mode to do this
11526 * computation to clearly distinguish it from the adjusted mode, which
11527 * can be changed by the connectors in the below retry loop.
11528 */
11529 drm_crtc_get_hv_timing(&pipe_config->base.mode,
11530 &pipe_config->pipe_src_w,
11531 &pipe_config->pipe_src_h);
11532
11533 encoder_retry:
11534 /* Ensure the port clock defaults are reset when retrying. */
11535 pipe_config->port_clock = 0;
11536 pipe_config->pixel_multiplier = 1;
11537
11538 /* Fill in default crtc timings, allow encoders to overwrite them. */
11539 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11540 CRTC_STEREO_DOUBLE);
11541
11542 /* Pass our mode to the connectors and the CRTC to give them a chance to
11543 * adjust it according to limitations or connector properties, and also
11544 * a chance to reject the mode entirely.
11545 */
11546 for_each_connector_in_state(state, connector, connector_state, i) {
11547 if (connector_state->crtc != crtc)
11548 continue;
11549
11550 encoder = to_intel_encoder(connector_state->best_encoder);
11551
11552 if (!(encoder->compute_config(encoder, pipe_config))) {
11553 DRM_DEBUG_KMS("Encoder config failure\n");
11554 goto fail;
11555 }
11556 }
11557
11558 /* Set default port clock if not overwritten by the encoder. Needs to be
11559 * done afterwards in case the encoder adjusts the mode. */
11560 if (!pipe_config->port_clock)
11561 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
11562 * pipe_config->pixel_multiplier;
11563
11564 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
11565 if (ret < 0) {
11566 DRM_DEBUG_KMS("CRTC fixup failed\n");
11567 goto fail;
11568 }
11569
11570 if (ret == RETRY) {
11571 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11572 ret = -EINVAL;
11573 goto fail;
11574 }
11575
11576 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11577 retry = false;
11578 goto encoder_retry;
11579 }
11580
11581 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
11582 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
11583 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
11584
11585 return 0;
11586 fail:
11587 return ret;
11588 }
11589
11590 static bool intel_crtc_in_use(struct drm_crtc *crtc)
11591 {
11592 struct drm_encoder *encoder;
11593 struct drm_device *dev = crtc->dev;
11594
11595 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11596 if (encoder->crtc == crtc)
11597 return true;
11598
11599 return false;
11600 }
11601
11602 static bool
11603 needs_modeset(struct drm_crtc_state *state)
11604 {
11605 return state->mode_changed || state->active_changed;
11606 }
11607
11608 static void
11609 intel_modeset_update_state(struct drm_atomic_state *state)
11610 {
11611 struct drm_device *dev = state->dev;
11612 struct drm_i915_private *dev_priv = dev->dev_private;
11613 struct intel_encoder *intel_encoder;
11614 struct drm_crtc *crtc;
11615 struct drm_crtc_state *crtc_state;
11616 struct drm_connector *connector;
11617 int i;
11618
11619 intel_shared_dpll_commit(dev_priv);
11620
11621 for_each_intel_encoder(dev, intel_encoder) {
11622 if (!intel_encoder->base.crtc)
11623 continue;
11624
11625 for_each_crtc_in_state(state, crtc, crtc_state, i)
11626 if (crtc == intel_encoder->base.crtc)
11627 break;
11628
11629 if (crtc != intel_encoder->base.crtc)
11630 continue;
11631
11632 if (crtc_state->enable && needs_modeset(crtc_state))
11633 intel_encoder->connectors_active = false;
11634 }
11635
11636 drm_atomic_helper_swap_state(state->dev, state);
11637 intel_modeset_fixup_state(state);
11638
11639 /* Double check state. */
11640 for_each_crtc(dev, crtc) {
11641 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
11642 }
11643
11644 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11645 if (!connector->encoder || !connector->encoder->crtc)
11646 continue;
11647
11648 for_each_crtc_in_state(state, crtc, crtc_state, i)
11649 if (crtc == connector->encoder->crtc)
11650 break;
11651
11652 if (crtc != connector->encoder->crtc)
11653 continue;
11654
11655 if (crtc->state->enable && needs_modeset(crtc->state)) {
11656 struct drm_property *dpms_property =
11657 dev->mode_config.dpms_property;
11658
11659 connector->dpms = DRM_MODE_DPMS_ON;
11660 drm_object_property_set_value(&connector->base,
11661 dpms_property,
11662 DRM_MODE_DPMS_ON);
11663
11664 intel_encoder = to_intel_encoder(connector->encoder);
11665 intel_encoder->connectors_active = true;
11666 }
11667 }
11668
11669 }
11670
11671 static bool intel_fuzzy_clock_check(int clock1, int clock2)
11672 {
11673 int diff;
11674
11675 if (clock1 == clock2)
11676 return true;
11677
11678 if (!clock1 || !clock2)
11679 return false;
11680
11681 diff = abs(clock1 - clock2);
11682
11683 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11684 return true;
11685
11686 return false;
11687 }
11688
11689 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11690 list_for_each_entry((intel_crtc), \
11691 &(dev)->mode_config.crtc_list, \
11692 base.head) \
11693 if (mask & (1 <<(intel_crtc)->pipe))
11694
11695 static bool
11696 intel_pipe_config_compare(struct drm_device *dev,
11697 struct intel_crtc_state *current_config,
11698 struct intel_crtc_state *pipe_config)
11699 {
11700 #define PIPE_CONF_CHECK_X(name) \
11701 if (current_config->name != pipe_config->name) { \
11702 DRM_ERROR("mismatch in " #name " " \
11703 "(expected 0x%08x, found 0x%08x)\n", \
11704 current_config->name, \
11705 pipe_config->name); \
11706 return false; \
11707 }
11708
11709 #define PIPE_CONF_CHECK_I(name) \
11710 if (current_config->name != pipe_config->name) { \
11711 DRM_ERROR("mismatch in " #name " " \
11712 "(expected %i, found %i)\n", \
11713 current_config->name, \
11714 pipe_config->name); \
11715 return false; \
11716 }
11717
11718 /* This is required for BDW+ where there is only one set of registers for
11719 * switching between high and low RR.
11720 * This macro can be used whenever a comparison has to be made between one
11721 * hw state and multiple sw state variables.
11722 */
11723 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11724 if ((current_config->name != pipe_config->name) && \
11725 (current_config->alt_name != pipe_config->name)) { \
11726 DRM_ERROR("mismatch in " #name " " \
11727 "(expected %i or %i, found %i)\n", \
11728 current_config->name, \
11729 current_config->alt_name, \
11730 pipe_config->name); \
11731 return false; \
11732 }
11733
11734 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
11735 if ((current_config->name ^ pipe_config->name) & (mask)) { \
11736 DRM_ERROR("mismatch in " #name "(" #mask ") " \
11737 "(expected %i, found %i)\n", \
11738 current_config->name & (mask), \
11739 pipe_config->name & (mask)); \
11740 return false; \
11741 }
11742
11743 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11744 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11745 DRM_ERROR("mismatch in " #name " " \
11746 "(expected %i, found %i)\n", \
11747 current_config->name, \
11748 pipe_config->name); \
11749 return false; \
11750 }
11751
11752 #define PIPE_CONF_QUIRK(quirk) \
11753 ((current_config->quirks | pipe_config->quirks) & (quirk))
11754
11755 PIPE_CONF_CHECK_I(cpu_transcoder);
11756
11757 PIPE_CONF_CHECK_I(has_pch_encoder);
11758 PIPE_CONF_CHECK_I(fdi_lanes);
11759 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11760 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11761 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11762 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11763 PIPE_CONF_CHECK_I(fdi_m_n.tu);
11764
11765 PIPE_CONF_CHECK_I(has_dp_encoder);
11766
11767 if (INTEL_INFO(dev)->gen < 8) {
11768 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11769 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11770 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11771 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11772 PIPE_CONF_CHECK_I(dp_m_n.tu);
11773
11774 if (current_config->has_drrs) {
11775 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11776 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11777 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11778 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11779 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11780 }
11781 } else {
11782 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11783 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11784 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11785 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11786 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11787 }
11788
11789 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11790 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11791 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11792 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11793 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11794 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
11795
11796 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11797 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11798 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11799 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11800 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11801 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
11802
11803 PIPE_CONF_CHECK_I(pixel_multiplier);
11804 PIPE_CONF_CHECK_I(has_hdmi_sink);
11805 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11806 IS_VALLEYVIEW(dev))
11807 PIPE_CONF_CHECK_I(limited_color_range);
11808 PIPE_CONF_CHECK_I(has_infoframe);
11809
11810 PIPE_CONF_CHECK_I(has_audio);
11811
11812 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11813 DRM_MODE_FLAG_INTERLACE);
11814
11815 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
11816 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11817 DRM_MODE_FLAG_PHSYNC);
11818 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11819 DRM_MODE_FLAG_NHSYNC);
11820 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11821 DRM_MODE_FLAG_PVSYNC);
11822 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
11823 DRM_MODE_FLAG_NVSYNC);
11824 }
11825
11826 PIPE_CONF_CHECK_I(pipe_src_w);
11827 PIPE_CONF_CHECK_I(pipe_src_h);
11828
11829 /*
11830 * FIXME: BIOS likes to set up a cloned config with lvds+external
11831 * screen. Since we don't yet re-compute the pipe config when moving
11832 * just the lvds port away to another pipe the sw tracking won't match.
11833 *
11834 * Proper atomic modesets with recomputed global state will fix this.
11835 * Until then just don't check gmch state for inherited modes.
11836 */
11837 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11838 PIPE_CONF_CHECK_I(gmch_pfit.control);
11839 /* pfit ratios are autocomputed by the hw on gen4+ */
11840 if (INTEL_INFO(dev)->gen < 4)
11841 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11842 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11843 }
11844
11845 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11846 if (current_config->pch_pfit.enabled) {
11847 PIPE_CONF_CHECK_I(pch_pfit.pos);
11848 PIPE_CONF_CHECK_I(pch_pfit.size);
11849 }
11850
11851 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11852
11853 /* BDW+ don't expose a synchronous way to read the state */
11854 if (IS_HASWELL(dev))
11855 PIPE_CONF_CHECK_I(ips_enabled);
11856
11857 PIPE_CONF_CHECK_I(double_wide);
11858
11859 PIPE_CONF_CHECK_X(ddi_pll_sel);
11860
11861 PIPE_CONF_CHECK_I(shared_dpll);
11862 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
11863 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
11864 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11865 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
11866 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
11867 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11868 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11869 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
11870
11871 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11872 PIPE_CONF_CHECK_I(pipe_bpp);
11873
11874 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
11875 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
11876
11877 #undef PIPE_CONF_CHECK_X
11878 #undef PIPE_CONF_CHECK_I
11879 #undef PIPE_CONF_CHECK_I_ALT
11880 #undef PIPE_CONF_CHECK_FLAGS
11881 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
11882 #undef PIPE_CONF_QUIRK
11883
11884 return true;
11885 }
11886
11887 static void check_wm_state(struct drm_device *dev)
11888 {
11889 struct drm_i915_private *dev_priv = dev->dev_private;
11890 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11891 struct intel_crtc *intel_crtc;
11892 int plane;
11893
11894 if (INTEL_INFO(dev)->gen < 9)
11895 return;
11896
11897 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11898 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11899
11900 for_each_intel_crtc(dev, intel_crtc) {
11901 struct skl_ddb_entry *hw_entry, *sw_entry;
11902 const enum pipe pipe = intel_crtc->pipe;
11903
11904 if (!intel_crtc->active)
11905 continue;
11906
11907 /* planes */
11908 for_each_plane(dev_priv, pipe, plane) {
11909 hw_entry = &hw_ddb.plane[pipe][plane];
11910 sw_entry = &sw_ddb->plane[pipe][plane];
11911
11912 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11913 continue;
11914
11915 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11916 "(expected (%u,%u), found (%u,%u))\n",
11917 pipe_name(pipe), plane + 1,
11918 sw_entry->start, sw_entry->end,
11919 hw_entry->start, hw_entry->end);
11920 }
11921
11922 /* cursor */
11923 hw_entry = &hw_ddb.cursor[pipe];
11924 sw_entry = &sw_ddb->cursor[pipe];
11925
11926 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11927 continue;
11928
11929 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11930 "(expected (%u,%u), found (%u,%u))\n",
11931 pipe_name(pipe),
11932 sw_entry->start, sw_entry->end,
11933 hw_entry->start, hw_entry->end);
11934 }
11935 }
11936
11937 static void
11938 check_connector_state(struct drm_device *dev)
11939 {
11940 struct intel_connector *connector;
11941
11942 for_each_intel_connector(dev, connector) {
11943 /* This also checks the encoder/connector hw state with the
11944 * ->get_hw_state callbacks. */
11945 intel_connector_check_state(connector);
11946
11947 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
11948 "connector's staged encoder doesn't match current encoder\n");
11949 }
11950 }
11951
11952 static void
11953 check_encoder_state(struct drm_device *dev)
11954 {
11955 struct intel_encoder *encoder;
11956 struct intel_connector *connector;
11957
11958 for_each_intel_encoder(dev, encoder) {
11959 bool enabled = false;
11960 bool active = false;
11961 enum pipe pipe, tracked_pipe;
11962
11963 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11964 encoder->base.base.id,
11965 encoder->base.name);
11966
11967 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
11968 "encoder's stage crtc doesn't match current crtc\n");
11969 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
11970 "encoder's active_connectors set, but no crtc\n");
11971
11972 for_each_intel_connector(dev, connector) {
11973 if (connector->base.encoder != &encoder->base)
11974 continue;
11975 enabled = true;
11976 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11977 active = true;
11978 }
11979 /*
11980 * for MST connectors if we unplug the connector is gone
11981 * away but the encoder is still connected to a crtc
11982 * until a modeset happens in response to the hotplug.
11983 */
11984 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11985 continue;
11986
11987 I915_STATE_WARN(!!encoder->base.crtc != enabled,
11988 "encoder's enabled state mismatch "
11989 "(expected %i, found %i)\n",
11990 !!encoder->base.crtc, enabled);
11991 I915_STATE_WARN(active && !encoder->base.crtc,
11992 "active encoder with no crtc\n");
11993
11994 I915_STATE_WARN(encoder->connectors_active != active,
11995 "encoder's computed active state doesn't match tracked active state "
11996 "(expected %i, found %i)\n", active, encoder->connectors_active);
11997
11998 active = encoder->get_hw_state(encoder, &pipe);
11999 I915_STATE_WARN(active != encoder->connectors_active,
12000 "encoder's hw state doesn't match sw tracking "
12001 "(expected %i, found %i)\n",
12002 encoder->connectors_active, active);
12003
12004 if (!encoder->base.crtc)
12005 continue;
12006
12007 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
12008 I915_STATE_WARN(active && pipe != tracked_pipe,
12009 "active encoder's pipe doesn't match"
12010 "(expected %i, found %i)\n",
12011 tracked_pipe, pipe);
12012
12013 }
12014 }
12015
12016 static void
12017 check_crtc_state(struct drm_device *dev)
12018 {
12019 struct drm_i915_private *dev_priv = dev->dev_private;
12020 struct intel_crtc *crtc;
12021 struct intel_encoder *encoder;
12022 struct intel_crtc_state pipe_config;
12023
12024 for_each_intel_crtc(dev, crtc) {
12025 bool enabled = false;
12026 bool active = false;
12027
12028 memset(&pipe_config, 0, sizeof(pipe_config));
12029
12030 DRM_DEBUG_KMS("[CRTC:%d]\n",
12031 crtc->base.base.id);
12032
12033 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
12034 "active crtc, but not enabled in sw tracking\n");
12035
12036 for_each_intel_encoder(dev, encoder) {
12037 if (encoder->base.crtc != &crtc->base)
12038 continue;
12039 enabled = true;
12040 if (encoder->connectors_active)
12041 active = true;
12042 }
12043
12044 I915_STATE_WARN(active != crtc->active,
12045 "crtc's computed active state doesn't match tracked active state "
12046 "(expected %i, found %i)\n", active, crtc->active);
12047 I915_STATE_WARN(enabled != crtc->base.state->enable,
12048 "crtc's computed enabled state doesn't match tracked enabled state "
12049 "(expected %i, found %i)\n", enabled,
12050 crtc->base.state->enable);
12051
12052 active = dev_priv->display.get_pipe_config(crtc,
12053 &pipe_config);
12054
12055 /* hw state is inconsistent with the pipe quirk */
12056 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12057 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
12058 active = crtc->active;
12059
12060 for_each_intel_encoder(dev, encoder) {
12061 enum pipe pipe;
12062 if (encoder->base.crtc != &crtc->base)
12063 continue;
12064 if (encoder->get_hw_state(encoder, &pipe))
12065 encoder->get_config(encoder, &pipe_config);
12066 }
12067
12068 I915_STATE_WARN(crtc->active != active,
12069 "crtc active state doesn't match with hw state "
12070 "(expected %i, found %i)\n", crtc->active, active);
12071
12072 if (active &&
12073 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
12074 I915_STATE_WARN(1, "pipe state doesn't match!\n");
12075 intel_dump_pipe_config(crtc, &pipe_config,
12076 "[hw state]");
12077 intel_dump_pipe_config(crtc, crtc->config,
12078 "[sw state]");
12079 }
12080 }
12081 }
12082
12083 static void
12084 check_shared_dpll_state(struct drm_device *dev)
12085 {
12086 struct drm_i915_private *dev_priv = dev->dev_private;
12087 struct intel_crtc *crtc;
12088 struct intel_dpll_hw_state dpll_hw_state;
12089 int i;
12090
12091 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12092 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12093 int enabled_crtcs = 0, active_crtcs = 0;
12094 bool active;
12095
12096 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12097
12098 DRM_DEBUG_KMS("%s\n", pll->name);
12099
12100 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12101
12102 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
12103 "more active pll users than references: %i vs %i\n",
12104 pll->active, hweight32(pll->config.crtc_mask));
12105 I915_STATE_WARN(pll->active && !pll->on,
12106 "pll in active use but not on in sw tracking\n");
12107 I915_STATE_WARN(pll->on && !pll->active,
12108 "pll in on but not on in use in sw tracking\n");
12109 I915_STATE_WARN(pll->on != active,
12110 "pll on state mismatch (expected %i, found %i)\n",
12111 pll->on, active);
12112
12113 for_each_intel_crtc(dev, crtc) {
12114 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
12115 enabled_crtcs++;
12116 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12117 active_crtcs++;
12118 }
12119 I915_STATE_WARN(pll->active != active_crtcs,
12120 "pll active crtcs mismatch (expected %i, found %i)\n",
12121 pll->active, active_crtcs);
12122 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
12123 "pll enabled crtcs mismatch (expected %i, found %i)\n",
12124 hweight32(pll->config.crtc_mask), enabled_crtcs);
12125
12126 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
12127 sizeof(dpll_hw_state)),
12128 "pll hw state mismatch\n");
12129 }
12130 }
12131
12132 void
12133 intel_modeset_check_state(struct drm_device *dev)
12134 {
12135 check_wm_state(dev);
12136 check_connector_state(dev);
12137 check_encoder_state(dev);
12138 check_crtc_state(dev);
12139 check_shared_dpll_state(dev);
12140 }
12141
12142 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
12143 int dotclock)
12144 {
12145 /*
12146 * FDI already provided one idea for the dotclock.
12147 * Yell if the encoder disagrees.
12148 */
12149 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
12150 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
12151 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
12152 }
12153
12154 static void update_scanline_offset(struct intel_crtc *crtc)
12155 {
12156 struct drm_device *dev = crtc->base.dev;
12157
12158 /*
12159 * The scanline counter increments at the leading edge of hsync.
12160 *
12161 * On most platforms it starts counting from vtotal-1 on the
12162 * first active line. That means the scanline counter value is
12163 * always one less than what we would expect. Ie. just after
12164 * start of vblank, which also occurs at start of hsync (on the
12165 * last active line), the scanline counter will read vblank_start-1.
12166 *
12167 * On gen2 the scanline counter starts counting from 1 instead
12168 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12169 * to keep the value positive), instead of adding one.
12170 *
12171 * On HSW+ the behaviour of the scanline counter depends on the output
12172 * type. For DP ports it behaves like most other platforms, but on HDMI
12173 * there's an extra 1 line difference. So we need to add two instead of
12174 * one to the value.
12175 */
12176 if (IS_GEN2(dev)) {
12177 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
12178 int vtotal;
12179
12180 vtotal = mode->crtc_vtotal;
12181 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12182 vtotal /= 2;
12183
12184 crtc->scanline_offset = vtotal - 1;
12185 } else if (HAS_DDI(dev) &&
12186 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
12187 crtc->scanline_offset = 2;
12188 } else
12189 crtc->scanline_offset = 1;
12190 }
12191
12192 static struct intel_crtc_state *
12193 intel_modeset_compute_config(struct drm_crtc *crtc,
12194 struct drm_atomic_state *state)
12195 {
12196 struct intel_crtc_state *pipe_config;
12197 int ret = 0;
12198
12199 ret = drm_atomic_add_affected_connectors(state, crtc);
12200 if (ret)
12201 return ERR_PTR(ret);
12202
12203 ret = drm_atomic_helper_check_modeset(state->dev, state);
12204 if (ret)
12205 return ERR_PTR(ret);
12206
12207 /*
12208 * Note this needs changes when we start tracking multiple modes
12209 * and crtcs. At that point we'll need to compute the whole config
12210 * (i.e. one pipe_config for each crtc) rather than just the one
12211 * for this crtc.
12212 */
12213 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12214 if (IS_ERR(pipe_config))
12215 return pipe_config;
12216
12217 if (!pipe_config->base.enable)
12218 return pipe_config;
12219
12220 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
12221 if (ret)
12222 return ERR_PTR(ret);
12223
12224 /* Check things that can only be changed through modeset */
12225 if (pipe_config->has_audio !=
12226 to_intel_crtc(crtc)->config->has_audio)
12227 pipe_config->base.mode_changed = true;
12228
12229 /*
12230 * Note we have an issue here with infoframes: current code
12231 * only updates them on the full mode set path per hw
12232 * requirements. So here we should be checking for any
12233 * required changes and forcing a mode set.
12234 */
12235
12236 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
12237
12238 ret = drm_atomic_helper_check_planes(state->dev, state);
12239 if (ret)
12240 return ERR_PTR(ret);
12241
12242 return pipe_config;
12243 }
12244
12245 static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
12246 {
12247 struct drm_device *dev = state->dev;
12248 struct drm_i915_private *dev_priv = to_i915(dev);
12249 unsigned clear_pipes = 0;
12250 struct intel_crtc *intel_crtc;
12251 struct intel_crtc_state *intel_crtc_state;
12252 struct drm_crtc *crtc;
12253 struct drm_crtc_state *crtc_state;
12254 int ret = 0;
12255 int i;
12256
12257 if (!dev_priv->display.crtc_compute_clock)
12258 return 0;
12259
12260 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12261 intel_crtc = to_intel_crtc(crtc);
12262 intel_crtc_state = to_intel_crtc_state(crtc_state);
12263
12264 if (needs_modeset(crtc_state)) {
12265 clear_pipes |= 1 << intel_crtc->pipe;
12266 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
12267 memset(&intel_crtc_state->dpll_hw_state, 0,
12268 sizeof(intel_crtc_state->dpll_hw_state));
12269 }
12270 }
12271
12272 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12273 if (ret)
12274 goto done;
12275
12276 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12277 if (!needs_modeset(crtc_state) || !crtc_state->enable)
12278 continue;
12279
12280 intel_crtc = to_intel_crtc(crtc);
12281 intel_crtc_state = to_intel_crtc_state(crtc_state);
12282
12283 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12284 intel_crtc_state);
12285 if (ret) {
12286 intel_shared_dpll_abort_config(dev_priv);
12287 goto done;
12288 }
12289 }
12290
12291 done:
12292 return ret;
12293 }
12294
12295 /* Code that should eventually be part of atomic_check() */
12296 static int __intel_set_mode_checks(struct drm_atomic_state *state)
12297 {
12298 struct drm_device *dev = state->dev;
12299 int ret;
12300
12301 /*
12302 * See if the config requires any additional preparation, e.g.
12303 * to adjust global state with pipes off. We need to do this
12304 * here so we can get the modeset_pipe updated config for the new
12305 * mode set on this crtc. For other crtcs we need to use the
12306 * adjusted_mode bits in the crtc directly.
12307 */
12308 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12309 ret = valleyview_modeset_global_pipes(state);
12310 if (ret)
12311 return ret;
12312 }
12313
12314 ret = __intel_set_mode_setup_plls(state);
12315 if (ret)
12316 return ret;
12317
12318 return 0;
12319 }
12320
12321 static int __intel_set_mode(struct drm_crtc *modeset_crtc,
12322 struct intel_crtc_state *pipe_config)
12323 {
12324 struct drm_device *dev = modeset_crtc->dev;
12325 struct drm_i915_private *dev_priv = dev->dev_private;
12326 struct drm_atomic_state *state = pipe_config->base.state;
12327 struct drm_crtc *crtc;
12328 struct drm_crtc_state *crtc_state;
12329 int ret = 0;
12330 int i;
12331
12332 ret = __intel_set_mode_checks(state);
12333 if (ret < 0)
12334 return ret;
12335
12336 ret = drm_atomic_helper_prepare_planes(dev, state);
12337 if (ret)
12338 return ret;
12339
12340 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12341 if (!needs_modeset(crtc_state))
12342 continue;
12343
12344 if (!crtc_state->enable) {
12345 intel_crtc_disable(crtc);
12346 } else if (crtc->state->enable) {
12347 intel_crtc_disable_planes(crtc);
12348 dev_priv->display.crtc_disable(crtc);
12349 }
12350 }
12351
12352 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12353 * to set it here already despite that we pass it down the callchain.
12354 *
12355 * Note we'll need to fix this up when we start tracking multiple
12356 * pipes; here we assume a single modeset_pipe and only track the
12357 * single crtc and mode.
12358 */
12359 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
12360 modeset_crtc->mode = pipe_config->base.mode;
12361
12362 /*
12363 * Calculate and store various constants which
12364 * are later needed by vblank and swap-completion
12365 * timestamping. They are derived from true hwmode.
12366 */
12367 drm_calc_timestamping_constants(modeset_crtc,
12368 &pipe_config->base.adjusted_mode);
12369 }
12370
12371 /* Only after disabling all output pipelines that will be changed can we
12372 * update the the output configuration. */
12373 intel_modeset_update_state(state);
12374
12375 /* The state has been swaped above, so state actually contains the
12376 * old state now. */
12377
12378 modeset_update_crtc_power_domains(state);
12379
12380 drm_atomic_helper_commit_planes(dev, state);
12381
12382 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
12383 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12384 if (!needs_modeset(crtc->state) || !crtc->state->enable)
12385 continue;
12386
12387 update_scanline_offset(to_intel_crtc(crtc));
12388
12389 dev_priv->display.crtc_enable(crtc);
12390 intel_crtc_enable_planes(crtc);
12391 }
12392
12393 /* FIXME: add subpixel order */
12394
12395 drm_atomic_helper_cleanup_planes(dev, state);
12396
12397 drm_atomic_state_free(state);
12398
12399 return 0;
12400 }
12401
12402 static int intel_set_mode_with_config(struct drm_crtc *crtc,
12403 struct intel_crtc_state *pipe_config)
12404 {
12405 int ret;
12406
12407 ret = __intel_set_mode(crtc, pipe_config);
12408
12409 if (ret == 0)
12410 intel_modeset_check_state(crtc->dev);
12411
12412 return ret;
12413 }
12414
12415 static int intel_set_mode(struct drm_crtc *crtc,
12416 struct drm_atomic_state *state)
12417 {
12418 struct intel_crtc_state *pipe_config;
12419 int ret = 0;
12420
12421 pipe_config = intel_modeset_compute_config(crtc, state);
12422 if (IS_ERR(pipe_config)) {
12423 ret = PTR_ERR(pipe_config);
12424 goto out;
12425 }
12426
12427 ret = intel_set_mode_with_config(crtc, pipe_config);
12428 if (ret)
12429 goto out;
12430
12431 out:
12432 return ret;
12433 }
12434
12435 void intel_crtc_restore_mode(struct drm_crtc *crtc)
12436 {
12437 struct drm_device *dev = crtc->dev;
12438 struct drm_atomic_state *state;
12439 struct intel_crtc *intel_crtc;
12440 struct intel_encoder *encoder;
12441 struct intel_connector *connector;
12442 struct drm_connector_state *connector_state;
12443 struct intel_crtc_state *crtc_state;
12444 int ret;
12445
12446 state = drm_atomic_state_alloc(dev);
12447 if (!state) {
12448 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12449 crtc->base.id);
12450 return;
12451 }
12452
12453 state->acquire_ctx = dev->mode_config.acquire_ctx;
12454
12455 /* The force restore path in the HW readout code relies on the staged
12456 * config still keeping the user requested config while the actual
12457 * state has been overwritten by the configuration read from HW. We
12458 * need to copy the staged config to the atomic state, otherwise the
12459 * mode set will just reapply the state the HW is already in. */
12460 for_each_intel_encoder(dev, encoder) {
12461 if (&encoder->new_crtc->base != crtc)
12462 continue;
12463
12464 for_each_intel_connector(dev, connector) {
12465 if (connector->new_encoder != encoder)
12466 continue;
12467
12468 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12469 if (IS_ERR(connector_state)) {
12470 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12471 connector->base.base.id,
12472 connector->base.name,
12473 PTR_ERR(connector_state));
12474 continue;
12475 }
12476
12477 connector_state->crtc = crtc;
12478 connector_state->best_encoder = &encoder->base;
12479 }
12480 }
12481
12482 for_each_intel_crtc(dev, intel_crtc) {
12483 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12484 continue;
12485
12486 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12487 if (IS_ERR(crtc_state)) {
12488 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12489 intel_crtc->base.base.id,
12490 PTR_ERR(crtc_state));
12491 continue;
12492 }
12493
12494 crtc_state->base.active = crtc_state->base.enable =
12495 intel_crtc->new_enabled;
12496
12497 if (&intel_crtc->base == crtc)
12498 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
12499 }
12500
12501 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12502 crtc->primary->fb, crtc->x, crtc->y);
12503
12504 ret = intel_set_mode(crtc, state);
12505 if (ret)
12506 drm_atomic_state_free(state);
12507 }
12508
12509 #undef for_each_intel_crtc_masked
12510
12511 static bool intel_connector_in_mode_set(struct intel_connector *connector,
12512 struct drm_mode_set *set)
12513 {
12514 int ro;
12515
12516 for (ro = 0; ro < set->num_connectors; ro++)
12517 if (set->connectors[ro] == &connector->base)
12518 return true;
12519
12520 return false;
12521 }
12522
12523 static int
12524 intel_modeset_stage_output_state(struct drm_device *dev,
12525 struct drm_mode_set *set,
12526 struct drm_atomic_state *state)
12527 {
12528 struct intel_connector *connector;
12529 struct drm_connector *drm_connector;
12530 struct drm_connector_state *connector_state;
12531 struct drm_crtc *crtc;
12532 struct drm_crtc_state *crtc_state;
12533 int i, ret;
12534
12535 /* The upper layers ensure that we either disable a crtc or have a list
12536 * of connectors. For paranoia, double-check this. */
12537 WARN_ON(!set->fb && (set->num_connectors != 0));
12538 WARN_ON(set->fb && (set->num_connectors == 0));
12539
12540 for_each_intel_connector(dev, connector) {
12541 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12542
12543 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12544 continue;
12545
12546 connector_state =
12547 drm_atomic_get_connector_state(state, &connector->base);
12548 if (IS_ERR(connector_state))
12549 return PTR_ERR(connector_state);
12550
12551 if (in_mode_set) {
12552 int pipe = to_intel_crtc(set->crtc)->pipe;
12553 connector_state->best_encoder =
12554 &intel_find_encoder(connector, pipe)->base;
12555 }
12556
12557 if (connector->base.state->crtc != set->crtc)
12558 continue;
12559
12560 /* If we disable the crtc, disable all its connectors. Also, if
12561 * the connector is on the changing crtc but not on the new
12562 * connector list, disable it. */
12563 if (!set->fb || !in_mode_set) {
12564 connector_state->best_encoder = NULL;
12565
12566 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12567 connector->base.base.id,
12568 connector->base.name);
12569 }
12570 }
12571 /* connector->new_encoder is now updated for all connectors. */
12572
12573 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12574 connector = to_intel_connector(drm_connector);
12575
12576 if (!connector_state->best_encoder) {
12577 ret = drm_atomic_set_crtc_for_connector(connector_state,
12578 NULL);
12579 if (ret)
12580 return ret;
12581
12582 continue;
12583 }
12584
12585 if (intel_connector_in_mode_set(connector, set)) {
12586 struct drm_crtc *crtc = connector->base.state->crtc;
12587
12588 /* If this connector was in a previous crtc, add it
12589 * to the state. We might need to disable it. */
12590 if (crtc) {
12591 crtc_state =
12592 drm_atomic_get_crtc_state(state, crtc);
12593 if (IS_ERR(crtc_state))
12594 return PTR_ERR(crtc_state);
12595 }
12596
12597 ret = drm_atomic_set_crtc_for_connector(connector_state,
12598 set->crtc);
12599 if (ret)
12600 return ret;
12601 }
12602
12603 /* Make sure the new CRTC will work with the encoder */
12604 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12605 connector_state->crtc)) {
12606 return -EINVAL;
12607 }
12608
12609 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12610 connector->base.base.id,
12611 connector->base.name,
12612 connector_state->crtc->base.id);
12613
12614 if (connector_state->best_encoder != &connector->encoder->base)
12615 connector->encoder =
12616 to_intel_encoder(connector_state->best_encoder);
12617 }
12618
12619 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12620 bool has_connectors;
12621
12622 ret = drm_atomic_add_affected_connectors(state, crtc);
12623 if (ret)
12624 return ret;
12625
12626 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12627 if (has_connectors != crtc_state->enable)
12628 crtc_state->enable =
12629 crtc_state->active = has_connectors;
12630 }
12631
12632 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12633 set->fb, set->x, set->y);
12634 if (ret)
12635 return ret;
12636
12637 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12638 if (IS_ERR(crtc_state))
12639 return PTR_ERR(crtc_state);
12640
12641 if (set->mode)
12642 drm_mode_copy(&crtc_state->mode, set->mode);
12643
12644 if (set->num_connectors)
12645 crtc_state->active = true;
12646
12647 return 0;
12648 }
12649
12650 static bool primary_plane_visible(struct drm_crtc *crtc)
12651 {
12652 struct intel_plane_state *plane_state =
12653 to_intel_plane_state(crtc->primary->state);
12654
12655 return plane_state->visible;
12656 }
12657
12658 static int intel_crtc_set_config(struct drm_mode_set *set)
12659 {
12660 struct drm_device *dev;
12661 struct drm_atomic_state *state = NULL;
12662 struct intel_crtc_state *pipe_config;
12663 bool primary_plane_was_visible;
12664 int ret;
12665
12666 BUG_ON(!set);
12667 BUG_ON(!set->crtc);
12668 BUG_ON(!set->crtc->helper_private);
12669
12670 /* Enforce sane interface api - has been abused by the fb helper. */
12671 BUG_ON(!set->mode && set->fb);
12672 BUG_ON(set->fb && set->num_connectors == 0);
12673
12674 if (set->fb) {
12675 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12676 set->crtc->base.id, set->fb->base.id,
12677 (int)set->num_connectors, set->x, set->y);
12678 } else {
12679 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
12680 }
12681
12682 dev = set->crtc->dev;
12683
12684 state = drm_atomic_state_alloc(dev);
12685 if (!state)
12686 return -ENOMEM;
12687
12688 state->acquire_ctx = dev->mode_config.acquire_ctx;
12689
12690 ret = intel_modeset_stage_output_state(dev, set, state);
12691 if (ret)
12692 goto out;
12693
12694 pipe_config = intel_modeset_compute_config(set->crtc, state);
12695 if (IS_ERR(pipe_config)) {
12696 ret = PTR_ERR(pipe_config);
12697 goto out;
12698 }
12699
12700 intel_update_pipe_size(to_intel_crtc(set->crtc));
12701
12702 primary_plane_was_visible = primary_plane_visible(set->crtc);
12703
12704 ret = intel_set_mode_with_config(set->crtc, pipe_config);
12705
12706 if (ret == 0 &&
12707 pipe_config->base.enable &&
12708 pipe_config->base.planes_changed &&
12709 !needs_modeset(&pipe_config->base)) {
12710 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
12711
12712 /*
12713 * We need to make sure the primary plane is re-enabled if it
12714 * has previously been turned off.
12715 */
12716 if (ret == 0 && !primary_plane_was_visible &&
12717 primary_plane_visible(set->crtc)) {
12718 WARN_ON(!intel_crtc->active);
12719 intel_post_enable_primary(set->crtc);
12720 }
12721
12722 /*
12723 * In the fastboot case this may be our only check of the
12724 * state after boot. It would be better to only do it on
12725 * the first update, but we don't have a nice way of doing that
12726 * (and really, set_config isn't used much for high freq page
12727 * flipping, so increasing its cost here shouldn't be a big
12728 * deal).
12729 */
12730 if (i915.fastboot && ret == 0)
12731 intel_modeset_check_state(set->crtc->dev);
12732 }
12733
12734 if (ret) {
12735 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12736 set->crtc->base.id, ret);
12737 }
12738
12739 out:
12740 if (ret)
12741 drm_atomic_state_free(state);
12742 return ret;
12743 }
12744
12745 static const struct drm_crtc_funcs intel_crtc_funcs = {
12746 .gamma_set = intel_crtc_gamma_set,
12747 .set_config = intel_crtc_set_config,
12748 .destroy = intel_crtc_destroy,
12749 .page_flip = intel_crtc_page_flip,
12750 .atomic_duplicate_state = intel_crtc_duplicate_state,
12751 .atomic_destroy_state = intel_crtc_destroy_state,
12752 };
12753
12754 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12755 struct intel_shared_dpll *pll,
12756 struct intel_dpll_hw_state *hw_state)
12757 {
12758 uint32_t val;
12759
12760 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
12761 return false;
12762
12763 val = I915_READ(PCH_DPLL(pll->id));
12764 hw_state->dpll = val;
12765 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12766 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
12767
12768 return val & DPLL_VCO_ENABLE;
12769 }
12770
12771 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12772 struct intel_shared_dpll *pll)
12773 {
12774 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12775 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
12776 }
12777
12778 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12779 struct intel_shared_dpll *pll)
12780 {
12781 /* PCH refclock must be enabled first */
12782 ibx_assert_pch_refclk_enabled(dev_priv);
12783
12784 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12785
12786 /* Wait for the clocks to stabilize. */
12787 POSTING_READ(PCH_DPLL(pll->id));
12788 udelay(150);
12789
12790 /* The pixel multiplier can only be updated once the
12791 * DPLL is enabled and the clocks are stable.
12792 *
12793 * So write it again.
12794 */
12795 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
12796 POSTING_READ(PCH_DPLL(pll->id));
12797 udelay(200);
12798 }
12799
12800 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12801 struct intel_shared_dpll *pll)
12802 {
12803 struct drm_device *dev = dev_priv->dev;
12804 struct intel_crtc *crtc;
12805
12806 /* Make sure no transcoder isn't still depending on us. */
12807 for_each_intel_crtc(dev, crtc) {
12808 if (intel_crtc_to_shared_dpll(crtc) == pll)
12809 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
12810 }
12811
12812 I915_WRITE(PCH_DPLL(pll->id), 0);
12813 POSTING_READ(PCH_DPLL(pll->id));
12814 udelay(200);
12815 }
12816
12817 static char *ibx_pch_dpll_names[] = {
12818 "PCH DPLL A",
12819 "PCH DPLL B",
12820 };
12821
12822 static void ibx_pch_dpll_init(struct drm_device *dev)
12823 {
12824 struct drm_i915_private *dev_priv = dev->dev_private;
12825 int i;
12826
12827 dev_priv->num_shared_dpll = 2;
12828
12829 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12830 dev_priv->shared_dplls[i].id = i;
12831 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
12832 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
12833 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12834 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
12835 dev_priv->shared_dplls[i].get_hw_state =
12836 ibx_pch_dpll_get_hw_state;
12837 }
12838 }
12839
12840 static void intel_shared_dpll_init(struct drm_device *dev)
12841 {
12842 struct drm_i915_private *dev_priv = dev->dev_private;
12843
12844 if (HAS_DDI(dev))
12845 intel_ddi_pll_init(dev);
12846 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
12847 ibx_pch_dpll_init(dev);
12848 else
12849 dev_priv->num_shared_dpll = 0;
12850
12851 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
12852 }
12853
12854 /**
12855 * intel_wm_need_update - Check whether watermarks need updating
12856 * @plane: drm plane
12857 * @state: new plane state
12858 *
12859 * Check current plane state versus the new one to determine whether
12860 * watermarks need to be recalculated.
12861 *
12862 * Returns true or false.
12863 */
12864 bool intel_wm_need_update(struct drm_plane *plane,
12865 struct drm_plane_state *state)
12866 {
12867 /* Update watermarks on tiling changes. */
12868 if (!plane->state->fb || !state->fb ||
12869 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12870 plane->state->rotation != state->rotation)
12871 return true;
12872
12873 return false;
12874 }
12875
12876 /**
12877 * intel_prepare_plane_fb - Prepare fb for usage on plane
12878 * @plane: drm plane to prepare for
12879 * @fb: framebuffer to prepare for presentation
12880 *
12881 * Prepares a framebuffer for usage on a display plane. Generally this
12882 * involves pinning the underlying object and updating the frontbuffer tracking
12883 * bits. Some older platforms need special physical address handling for
12884 * cursor planes.
12885 *
12886 * Returns 0 on success, negative error code on failure.
12887 */
12888 int
12889 intel_prepare_plane_fb(struct drm_plane *plane,
12890 struct drm_framebuffer *fb,
12891 const struct drm_plane_state *new_state)
12892 {
12893 struct drm_device *dev = plane->dev;
12894 struct intel_plane *intel_plane = to_intel_plane(plane);
12895 enum pipe pipe = intel_plane->pipe;
12896 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12897 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12898 unsigned frontbuffer_bits = 0;
12899 int ret = 0;
12900
12901 if (!obj)
12902 return 0;
12903
12904 switch (plane->type) {
12905 case DRM_PLANE_TYPE_PRIMARY:
12906 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12907 break;
12908 case DRM_PLANE_TYPE_CURSOR:
12909 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12910 break;
12911 case DRM_PLANE_TYPE_OVERLAY:
12912 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12913 break;
12914 }
12915
12916 mutex_lock(&dev->struct_mutex);
12917
12918 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12919 INTEL_INFO(dev)->cursor_needs_physical) {
12920 int align = IS_I830(dev) ? 16 * 1024 : 256;
12921 ret = i915_gem_object_attach_phys(obj, align);
12922 if (ret)
12923 DRM_DEBUG_KMS("failed to attach phys object\n");
12924 } else {
12925 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
12926 }
12927
12928 if (ret == 0)
12929 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
12930
12931 mutex_unlock(&dev->struct_mutex);
12932
12933 return ret;
12934 }
12935
12936 /**
12937 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12938 * @plane: drm plane to clean up for
12939 * @fb: old framebuffer that was on plane
12940 *
12941 * Cleans up a framebuffer that has just been removed from a plane.
12942 */
12943 void
12944 intel_cleanup_plane_fb(struct drm_plane *plane,
12945 struct drm_framebuffer *fb,
12946 const struct drm_plane_state *old_state)
12947 {
12948 struct drm_device *dev = plane->dev;
12949 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12950
12951 if (WARN_ON(!obj))
12952 return;
12953
12954 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12955 !INTEL_INFO(dev)->cursor_needs_physical) {
12956 mutex_lock(&dev->struct_mutex);
12957 intel_unpin_fb_obj(fb, old_state);
12958 mutex_unlock(&dev->struct_mutex);
12959 }
12960 }
12961
12962 int
12963 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12964 {
12965 int max_scale;
12966 struct drm_device *dev;
12967 struct drm_i915_private *dev_priv;
12968 int crtc_clock, cdclk;
12969
12970 if (!intel_crtc || !crtc_state)
12971 return DRM_PLANE_HELPER_NO_SCALING;
12972
12973 dev = intel_crtc->base.dev;
12974 dev_priv = dev->dev_private;
12975 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
12976 cdclk = dev_priv->display.get_display_clock_speed(dev);
12977
12978 if (!crtc_clock || !cdclk)
12979 return DRM_PLANE_HELPER_NO_SCALING;
12980
12981 /*
12982 * skl max scale is lower of:
12983 * close to 3 but not 3, -1 is for that purpose
12984 * or
12985 * cdclk/crtc_clock
12986 */
12987 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
12988
12989 return max_scale;
12990 }
12991
12992 static int
12993 intel_check_primary_plane(struct drm_plane *plane,
12994 struct intel_plane_state *state)
12995 {
12996 struct drm_device *dev = plane->dev;
12997 struct drm_i915_private *dev_priv = dev->dev_private;
12998 struct drm_crtc *crtc = state->base.crtc;
12999 struct intel_crtc *intel_crtc;
13000 struct intel_crtc_state *crtc_state;
13001 struct drm_framebuffer *fb = state->base.fb;
13002 struct drm_rect *dest = &state->dst;
13003 struct drm_rect *src = &state->src;
13004 const struct drm_rect *clip = &state->clip;
13005 bool can_position = false;
13006 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13007 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
13008 int ret;
13009
13010 crtc = crtc ? crtc : plane->crtc;
13011 intel_crtc = to_intel_crtc(crtc);
13012 crtc_state = state->base.state ?
13013 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
13014
13015 if (INTEL_INFO(dev)->gen >= 9) {
13016 min_scale = 1;
13017 max_scale = skl_max_scale(intel_crtc, crtc_state);
13018 can_position = true;
13019 }
13020
13021 ret = drm_plane_helper_check_update(plane, crtc, fb,
13022 src, dest, clip,
13023 min_scale,
13024 max_scale,
13025 can_position, true,
13026 &state->visible);
13027 if (ret)
13028 return ret;
13029
13030 if (intel_crtc->active) {
13031 struct intel_plane_state *old_state =
13032 to_intel_plane_state(plane->state);
13033
13034 intel_crtc->atomic.wait_for_flips = true;
13035
13036 /*
13037 * FBC does not work on some platforms for rotated
13038 * planes, so disable it when rotation is not 0 and
13039 * update it when rotation is set back to 0.
13040 *
13041 * FIXME: This is redundant with the fbc update done in
13042 * the primary plane enable function except that that
13043 * one is done too late. We eventually need to unify
13044 * this.
13045 */
13046 if (state->visible &&
13047 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
13048 dev_priv->fbc.crtc == intel_crtc &&
13049 state->base.rotation != BIT(DRM_ROTATE_0)) {
13050 intel_crtc->atomic.disable_fbc = true;
13051 }
13052
13053 if (state->visible && !old_state->visible) {
13054 /*
13055 * BDW signals flip done immediately if the plane
13056 * is disabled, even if the plane enable is already
13057 * armed to occur at the next vblank :(
13058 */
13059 if (IS_BROADWELL(dev))
13060 intel_crtc->atomic.wait_vblank = true;
13061 }
13062
13063 intel_crtc->atomic.fb_bits |=
13064 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13065
13066 intel_crtc->atomic.update_fbc = true;
13067
13068 if (intel_wm_need_update(plane, &state->base))
13069 intel_crtc->atomic.update_wm = true;
13070 }
13071
13072 if (INTEL_INFO(dev)->gen >= 9) {
13073 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13074 to_intel_plane(plane), state, 0);
13075 if (ret)
13076 return ret;
13077 }
13078
13079 return 0;
13080 }
13081
13082 static void
13083 intel_commit_primary_plane(struct drm_plane *plane,
13084 struct intel_plane_state *state)
13085 {
13086 struct drm_crtc *crtc = state->base.crtc;
13087 struct drm_framebuffer *fb = state->base.fb;
13088 struct drm_device *dev = plane->dev;
13089 struct drm_i915_private *dev_priv = dev->dev_private;
13090 struct intel_crtc *intel_crtc;
13091 struct drm_rect *src = &state->src;
13092
13093 crtc = crtc ? crtc : plane->crtc;
13094 intel_crtc = to_intel_crtc(crtc);
13095
13096 plane->fb = fb;
13097 crtc->x = src->x1 >> 16;
13098 crtc->y = src->y1 >> 16;
13099
13100 if (intel_crtc->active) {
13101 if (state->visible)
13102 /* FIXME: kill this fastboot hack */
13103 intel_update_pipe_size(intel_crtc);
13104
13105 dev_priv->display.update_primary_plane(crtc, plane->fb,
13106 crtc->x, crtc->y);
13107 }
13108 }
13109
13110 static void
13111 intel_disable_primary_plane(struct drm_plane *plane,
13112 struct drm_crtc *crtc,
13113 bool force)
13114 {
13115 struct drm_device *dev = plane->dev;
13116 struct drm_i915_private *dev_priv = dev->dev_private;
13117
13118 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13119 }
13120
13121 static void intel_begin_crtc_commit(struct drm_crtc *crtc)
13122 {
13123 struct drm_device *dev = crtc->dev;
13124 struct drm_i915_private *dev_priv = dev->dev_private;
13125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13126 struct intel_plane *intel_plane;
13127 struct drm_plane *p;
13128 unsigned fb_bits = 0;
13129
13130 /* Track fb's for any planes being disabled */
13131 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13132 intel_plane = to_intel_plane(p);
13133
13134 if (intel_crtc->atomic.disabled_planes &
13135 (1 << drm_plane_index(p))) {
13136 switch (p->type) {
13137 case DRM_PLANE_TYPE_PRIMARY:
13138 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13139 break;
13140 case DRM_PLANE_TYPE_CURSOR:
13141 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13142 break;
13143 case DRM_PLANE_TYPE_OVERLAY:
13144 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13145 break;
13146 }
13147
13148 mutex_lock(&dev->struct_mutex);
13149 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13150 mutex_unlock(&dev->struct_mutex);
13151 }
13152 }
13153
13154 if (intel_crtc->atomic.wait_for_flips)
13155 intel_crtc_wait_for_pending_flips(crtc);
13156
13157 if (intel_crtc->atomic.disable_fbc)
13158 intel_fbc_disable(dev);
13159
13160 if (intel_crtc->atomic.pre_disable_primary)
13161 intel_pre_disable_primary(crtc);
13162
13163 if (intel_crtc->atomic.update_wm)
13164 intel_update_watermarks(crtc);
13165
13166 intel_runtime_pm_get(dev_priv);
13167
13168 /* Perform vblank evasion around commit operation */
13169 if (intel_crtc->active)
13170 intel_crtc->atomic.evade =
13171 intel_pipe_update_start(intel_crtc,
13172 &intel_crtc->atomic.start_vbl_count);
13173 }
13174
13175 static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13176 {
13177 struct drm_device *dev = crtc->dev;
13178 struct drm_i915_private *dev_priv = dev->dev_private;
13179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13180 struct drm_plane *p;
13181
13182 if (intel_crtc->atomic.evade)
13183 intel_pipe_update_end(intel_crtc,
13184 intel_crtc->atomic.start_vbl_count);
13185
13186 intel_runtime_pm_put(dev_priv);
13187
13188 if (intel_crtc->atomic.wait_vblank)
13189 intel_wait_for_vblank(dev, intel_crtc->pipe);
13190
13191 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13192
13193 if (intel_crtc->atomic.update_fbc) {
13194 mutex_lock(&dev->struct_mutex);
13195 intel_fbc_update(dev);
13196 mutex_unlock(&dev->struct_mutex);
13197 }
13198
13199 if (intel_crtc->atomic.post_enable_primary)
13200 intel_post_enable_primary(crtc);
13201
13202 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13203 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13204 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13205 false, false);
13206
13207 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
13208 }
13209
13210 /**
13211 * intel_plane_destroy - destroy a plane
13212 * @plane: plane to destroy
13213 *
13214 * Common destruction function for all types of planes (primary, cursor,
13215 * sprite).
13216 */
13217 void intel_plane_destroy(struct drm_plane *plane)
13218 {
13219 struct intel_plane *intel_plane = to_intel_plane(plane);
13220 drm_plane_cleanup(plane);
13221 kfree(intel_plane);
13222 }
13223
13224 const struct drm_plane_funcs intel_plane_funcs = {
13225 .update_plane = drm_atomic_helper_update_plane,
13226 .disable_plane = drm_atomic_helper_disable_plane,
13227 .destroy = intel_plane_destroy,
13228 .set_property = drm_atomic_helper_plane_set_property,
13229 .atomic_get_property = intel_plane_atomic_get_property,
13230 .atomic_set_property = intel_plane_atomic_set_property,
13231 .atomic_duplicate_state = intel_plane_duplicate_state,
13232 .atomic_destroy_state = intel_plane_destroy_state,
13233
13234 };
13235
13236 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13237 int pipe)
13238 {
13239 struct intel_plane *primary;
13240 struct intel_plane_state *state;
13241 const uint32_t *intel_primary_formats;
13242 int num_formats;
13243
13244 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13245 if (primary == NULL)
13246 return NULL;
13247
13248 state = intel_create_plane_state(&primary->base);
13249 if (!state) {
13250 kfree(primary);
13251 return NULL;
13252 }
13253 primary->base.state = &state->base;
13254
13255 primary->can_scale = false;
13256 primary->max_downscale = 1;
13257 if (INTEL_INFO(dev)->gen >= 9) {
13258 primary->can_scale = true;
13259 }
13260 state->scaler_id = -1;
13261 primary->pipe = pipe;
13262 primary->plane = pipe;
13263 primary->check_plane = intel_check_primary_plane;
13264 primary->commit_plane = intel_commit_primary_plane;
13265 primary->disable_plane = intel_disable_primary_plane;
13266 primary->ckey.flags = I915_SET_COLORKEY_NONE;
13267 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13268 primary->plane = !pipe;
13269
13270 if (INTEL_INFO(dev)->gen <= 3) {
13271 intel_primary_formats = intel_primary_formats_gen2;
13272 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13273 } else {
13274 intel_primary_formats = intel_primary_formats_gen4;
13275 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13276 }
13277
13278 drm_universal_plane_init(dev, &primary->base, 0,
13279 &intel_plane_funcs,
13280 intel_primary_formats, num_formats,
13281 DRM_PLANE_TYPE_PRIMARY);
13282
13283 if (INTEL_INFO(dev)->gen >= 4)
13284 intel_create_rotation_property(dev, primary);
13285
13286 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13287
13288 return &primary->base;
13289 }
13290
13291 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13292 {
13293 if (!dev->mode_config.rotation_property) {
13294 unsigned long flags = BIT(DRM_ROTATE_0) |
13295 BIT(DRM_ROTATE_180);
13296
13297 if (INTEL_INFO(dev)->gen >= 9)
13298 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13299
13300 dev->mode_config.rotation_property =
13301 drm_mode_create_rotation_property(dev, flags);
13302 }
13303 if (dev->mode_config.rotation_property)
13304 drm_object_attach_property(&plane->base.base,
13305 dev->mode_config.rotation_property,
13306 plane->base.state->rotation);
13307 }
13308
13309 static int
13310 intel_check_cursor_plane(struct drm_plane *plane,
13311 struct intel_plane_state *state)
13312 {
13313 struct drm_crtc *crtc = state->base.crtc;
13314 struct drm_device *dev = plane->dev;
13315 struct drm_framebuffer *fb = state->base.fb;
13316 struct drm_rect *dest = &state->dst;
13317 struct drm_rect *src = &state->src;
13318 const struct drm_rect *clip = &state->clip;
13319 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13320 struct intel_crtc *intel_crtc;
13321 unsigned stride;
13322 int ret;
13323
13324 crtc = crtc ? crtc : plane->crtc;
13325 intel_crtc = to_intel_crtc(crtc);
13326
13327 ret = drm_plane_helper_check_update(plane, crtc, fb,
13328 src, dest, clip,
13329 DRM_PLANE_HELPER_NO_SCALING,
13330 DRM_PLANE_HELPER_NO_SCALING,
13331 true, true, &state->visible);
13332 if (ret)
13333 return ret;
13334
13335
13336 /* if we want to turn off the cursor ignore width and height */
13337 if (!obj)
13338 goto finish;
13339
13340 /* Check for which cursor types we support */
13341 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13342 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13343 state->base.crtc_w, state->base.crtc_h);
13344 return -EINVAL;
13345 }
13346
13347 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13348 if (obj->base.size < stride * state->base.crtc_h) {
13349 DRM_DEBUG_KMS("buffer is too small\n");
13350 return -ENOMEM;
13351 }
13352
13353 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
13354 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13355 ret = -EINVAL;
13356 }
13357
13358 finish:
13359 if (intel_crtc->active) {
13360 if (plane->state->crtc_w != state->base.crtc_w)
13361 intel_crtc->atomic.update_wm = true;
13362
13363 intel_crtc->atomic.fb_bits |=
13364 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13365 }
13366
13367 return ret;
13368 }
13369
13370 static void
13371 intel_disable_cursor_plane(struct drm_plane *plane,
13372 struct drm_crtc *crtc,
13373 bool force)
13374 {
13375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13376
13377 if (!force) {
13378 plane->fb = NULL;
13379 intel_crtc->cursor_bo = NULL;
13380 intel_crtc->cursor_addr = 0;
13381 }
13382
13383 intel_crtc_update_cursor(crtc, false);
13384 }
13385
13386 static void
13387 intel_commit_cursor_plane(struct drm_plane *plane,
13388 struct intel_plane_state *state)
13389 {
13390 struct drm_crtc *crtc = state->base.crtc;
13391 struct drm_device *dev = plane->dev;
13392 struct intel_crtc *intel_crtc;
13393 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
13394 uint32_t addr;
13395
13396 crtc = crtc ? crtc : plane->crtc;
13397 intel_crtc = to_intel_crtc(crtc);
13398
13399 plane->fb = state->base.fb;
13400 crtc->cursor_x = state->base.crtc_x;
13401 crtc->cursor_y = state->base.crtc_y;
13402
13403 if (intel_crtc->cursor_bo == obj)
13404 goto update;
13405
13406 if (!obj)
13407 addr = 0;
13408 else if (!INTEL_INFO(dev)->cursor_needs_physical)
13409 addr = i915_gem_obj_ggtt_offset(obj);
13410 else
13411 addr = obj->phys_handle->busaddr;
13412
13413 intel_crtc->cursor_addr = addr;
13414 intel_crtc->cursor_bo = obj;
13415 update:
13416
13417 if (intel_crtc->active)
13418 intel_crtc_update_cursor(crtc, state->visible);
13419 }
13420
13421 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13422 int pipe)
13423 {
13424 struct intel_plane *cursor;
13425 struct intel_plane_state *state;
13426
13427 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13428 if (cursor == NULL)
13429 return NULL;
13430
13431 state = intel_create_plane_state(&cursor->base);
13432 if (!state) {
13433 kfree(cursor);
13434 return NULL;
13435 }
13436 cursor->base.state = &state->base;
13437
13438 cursor->can_scale = false;
13439 cursor->max_downscale = 1;
13440 cursor->pipe = pipe;
13441 cursor->plane = pipe;
13442 state->scaler_id = -1;
13443 cursor->check_plane = intel_check_cursor_plane;
13444 cursor->commit_plane = intel_commit_cursor_plane;
13445 cursor->disable_plane = intel_disable_cursor_plane;
13446
13447 drm_universal_plane_init(dev, &cursor->base, 0,
13448 &intel_plane_funcs,
13449 intel_cursor_formats,
13450 ARRAY_SIZE(intel_cursor_formats),
13451 DRM_PLANE_TYPE_CURSOR);
13452
13453 if (INTEL_INFO(dev)->gen >= 4) {
13454 if (!dev->mode_config.rotation_property)
13455 dev->mode_config.rotation_property =
13456 drm_mode_create_rotation_property(dev,
13457 BIT(DRM_ROTATE_0) |
13458 BIT(DRM_ROTATE_180));
13459 if (dev->mode_config.rotation_property)
13460 drm_object_attach_property(&cursor->base.base,
13461 dev->mode_config.rotation_property,
13462 state->base.rotation);
13463 }
13464
13465 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13466
13467 return &cursor->base;
13468 }
13469
13470 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13471 struct intel_crtc_state *crtc_state)
13472 {
13473 int i;
13474 struct intel_scaler *intel_scaler;
13475 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13476
13477 for (i = 0; i < intel_crtc->num_scalers; i++) {
13478 intel_scaler = &scaler_state->scalers[i];
13479 intel_scaler->in_use = 0;
13480 intel_scaler->id = i;
13481
13482 intel_scaler->mode = PS_SCALER_MODE_DYN;
13483 }
13484
13485 scaler_state->scaler_id = -1;
13486 }
13487
13488 static void intel_crtc_init(struct drm_device *dev, int pipe)
13489 {
13490 struct drm_i915_private *dev_priv = dev->dev_private;
13491 struct intel_crtc *intel_crtc;
13492 struct intel_crtc_state *crtc_state = NULL;
13493 struct drm_plane *primary = NULL;
13494 struct drm_plane *cursor = NULL;
13495 int i, ret;
13496
13497 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
13498 if (intel_crtc == NULL)
13499 return;
13500
13501 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13502 if (!crtc_state)
13503 goto fail;
13504 intel_crtc->config = crtc_state;
13505 intel_crtc->base.state = &crtc_state->base;
13506 crtc_state->base.crtc = &intel_crtc->base;
13507
13508 /* initialize shared scalers */
13509 if (INTEL_INFO(dev)->gen >= 9) {
13510 if (pipe == PIPE_C)
13511 intel_crtc->num_scalers = 1;
13512 else
13513 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13514
13515 skl_init_scalers(dev, intel_crtc, crtc_state);
13516 }
13517
13518 primary = intel_primary_plane_create(dev, pipe);
13519 if (!primary)
13520 goto fail;
13521
13522 cursor = intel_cursor_plane_create(dev, pipe);
13523 if (!cursor)
13524 goto fail;
13525
13526 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
13527 cursor, &intel_crtc_funcs);
13528 if (ret)
13529 goto fail;
13530
13531 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
13532 for (i = 0; i < 256; i++) {
13533 intel_crtc->lut_r[i] = i;
13534 intel_crtc->lut_g[i] = i;
13535 intel_crtc->lut_b[i] = i;
13536 }
13537
13538 /*
13539 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
13540 * is hooked to pipe B. Hence we want plane A feeding pipe B.
13541 */
13542 intel_crtc->pipe = pipe;
13543 intel_crtc->plane = pipe;
13544 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
13545 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
13546 intel_crtc->plane = !pipe;
13547 }
13548
13549 intel_crtc->cursor_base = ~0;
13550 intel_crtc->cursor_cntl = ~0;
13551 intel_crtc->cursor_size = ~0;
13552
13553 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13554 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13555 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13556 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13557
13558 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13559
13560 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
13561
13562 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
13563 return;
13564
13565 fail:
13566 if (primary)
13567 drm_plane_cleanup(primary);
13568 if (cursor)
13569 drm_plane_cleanup(cursor);
13570 kfree(crtc_state);
13571 kfree(intel_crtc);
13572 }
13573
13574 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13575 {
13576 struct drm_encoder *encoder = connector->base.encoder;
13577 struct drm_device *dev = connector->base.dev;
13578
13579 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
13580
13581 if (!encoder || WARN_ON(!encoder->crtc))
13582 return INVALID_PIPE;
13583
13584 return to_intel_crtc(encoder->crtc)->pipe;
13585 }
13586
13587 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
13588 struct drm_file *file)
13589 {
13590 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
13591 struct drm_crtc *drmmode_crtc;
13592 struct intel_crtc *crtc;
13593
13594 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
13595
13596 if (!drmmode_crtc) {
13597 DRM_ERROR("no such CRTC id\n");
13598 return -ENOENT;
13599 }
13600
13601 crtc = to_intel_crtc(drmmode_crtc);
13602 pipe_from_crtc_id->pipe = crtc->pipe;
13603
13604 return 0;
13605 }
13606
13607 static int intel_encoder_clones(struct intel_encoder *encoder)
13608 {
13609 struct drm_device *dev = encoder->base.dev;
13610 struct intel_encoder *source_encoder;
13611 int index_mask = 0;
13612 int entry = 0;
13613
13614 for_each_intel_encoder(dev, source_encoder) {
13615 if (encoders_cloneable(encoder, source_encoder))
13616 index_mask |= (1 << entry);
13617
13618 entry++;
13619 }
13620
13621 return index_mask;
13622 }
13623
13624 static bool has_edp_a(struct drm_device *dev)
13625 {
13626 struct drm_i915_private *dev_priv = dev->dev_private;
13627
13628 if (!IS_MOBILE(dev))
13629 return false;
13630
13631 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13632 return false;
13633
13634 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
13635 return false;
13636
13637 return true;
13638 }
13639
13640 static bool intel_crt_present(struct drm_device *dev)
13641 {
13642 struct drm_i915_private *dev_priv = dev->dev_private;
13643
13644 if (INTEL_INFO(dev)->gen >= 9)
13645 return false;
13646
13647 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
13648 return false;
13649
13650 if (IS_CHERRYVIEW(dev))
13651 return false;
13652
13653 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13654 return false;
13655
13656 return true;
13657 }
13658
13659 static void intel_setup_outputs(struct drm_device *dev)
13660 {
13661 struct drm_i915_private *dev_priv = dev->dev_private;
13662 struct intel_encoder *encoder;
13663 bool dpd_is_edp = false;
13664
13665 intel_lvds_init(dev);
13666
13667 if (intel_crt_present(dev))
13668 intel_crt_init(dev);
13669
13670 if (IS_BROXTON(dev)) {
13671 /*
13672 * FIXME: Broxton doesn't support port detection via the
13673 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13674 * detect the ports.
13675 */
13676 intel_ddi_init(dev, PORT_A);
13677 intel_ddi_init(dev, PORT_B);
13678 intel_ddi_init(dev, PORT_C);
13679 } else if (HAS_DDI(dev)) {
13680 int found;
13681
13682 /*
13683 * Haswell uses DDI functions to detect digital outputs.
13684 * On SKL pre-D0 the strap isn't connected, so we assume
13685 * it's there.
13686 */
13687 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
13688 /* WaIgnoreDDIAStrap: skl */
13689 if (found ||
13690 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
13691 intel_ddi_init(dev, PORT_A);
13692
13693 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13694 * register */
13695 found = I915_READ(SFUSE_STRAP);
13696
13697 if (found & SFUSE_STRAP_DDIB_DETECTED)
13698 intel_ddi_init(dev, PORT_B);
13699 if (found & SFUSE_STRAP_DDIC_DETECTED)
13700 intel_ddi_init(dev, PORT_C);
13701 if (found & SFUSE_STRAP_DDID_DETECTED)
13702 intel_ddi_init(dev, PORT_D);
13703 } else if (HAS_PCH_SPLIT(dev)) {
13704 int found;
13705 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
13706
13707 if (has_edp_a(dev))
13708 intel_dp_init(dev, DP_A, PORT_A);
13709
13710 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
13711 /* PCH SDVOB multiplex with HDMIB */
13712 found = intel_sdvo_init(dev, PCH_SDVOB, true);
13713 if (!found)
13714 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
13715 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
13716 intel_dp_init(dev, PCH_DP_B, PORT_B);
13717 }
13718
13719 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
13720 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
13721
13722 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
13723 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
13724
13725 if (I915_READ(PCH_DP_C) & DP_DETECTED)
13726 intel_dp_init(dev, PCH_DP_C, PORT_C);
13727
13728 if (I915_READ(PCH_DP_D) & DP_DETECTED)
13729 intel_dp_init(dev, PCH_DP_D, PORT_D);
13730 } else if (IS_VALLEYVIEW(dev)) {
13731 /*
13732 * The DP_DETECTED bit is the latched state of the DDC
13733 * SDA pin at boot. However since eDP doesn't require DDC
13734 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13735 * eDP ports may have been muxed to an alternate function.
13736 * Thus we can't rely on the DP_DETECTED bit alone to detect
13737 * eDP ports. Consult the VBT as well as DP_DETECTED to
13738 * detect eDP ports.
13739 */
13740 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13741 !intel_dp_is_edp(dev, PORT_B))
13742 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13743 PORT_B);
13744 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13745 intel_dp_is_edp(dev, PORT_B))
13746 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
13747
13748 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13749 !intel_dp_is_edp(dev, PORT_C))
13750 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13751 PORT_C);
13752 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13753 intel_dp_is_edp(dev, PORT_C))
13754 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
13755
13756 if (IS_CHERRYVIEW(dev)) {
13757 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
13758 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13759 PORT_D);
13760 /* eDP not supported on port D, so don't check VBT */
13761 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13762 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
13763 }
13764
13765 intel_dsi_init(dev);
13766 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
13767 bool found = false;
13768
13769 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13770 DRM_DEBUG_KMS("probing SDVOB\n");
13771 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
13772 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13773 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
13774 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
13775 }
13776
13777 if (!found && SUPPORTS_INTEGRATED_DP(dev))
13778 intel_dp_init(dev, DP_B, PORT_B);
13779 }
13780
13781 /* Before G4X SDVOC doesn't have its own detect register */
13782
13783 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
13784 DRM_DEBUG_KMS("probing SDVOC\n");
13785 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
13786 }
13787
13788 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
13789
13790 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13791 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
13792 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
13793 }
13794 if (SUPPORTS_INTEGRATED_DP(dev))
13795 intel_dp_init(dev, DP_C, PORT_C);
13796 }
13797
13798 if (SUPPORTS_INTEGRATED_DP(dev) &&
13799 (I915_READ(DP_D) & DP_DETECTED))
13800 intel_dp_init(dev, DP_D, PORT_D);
13801 } else if (IS_GEN2(dev))
13802 intel_dvo_init(dev);
13803
13804 if (SUPPORTS_TV(dev))
13805 intel_tv_init(dev);
13806
13807 intel_psr_init(dev);
13808
13809 for_each_intel_encoder(dev, encoder) {
13810 encoder->base.possible_crtcs = encoder->crtc_mask;
13811 encoder->base.possible_clones =
13812 intel_encoder_clones(encoder);
13813 }
13814
13815 intel_init_pch_refclk(dev);
13816
13817 drm_helper_move_panel_connectors_to_head(dev);
13818 }
13819
13820 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13821 {
13822 struct drm_device *dev = fb->dev;
13823 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13824
13825 drm_framebuffer_cleanup(fb);
13826 mutex_lock(&dev->struct_mutex);
13827 WARN_ON(!intel_fb->obj->framebuffer_references--);
13828 drm_gem_object_unreference(&intel_fb->obj->base);
13829 mutex_unlock(&dev->struct_mutex);
13830 kfree(intel_fb);
13831 }
13832
13833 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
13834 struct drm_file *file,
13835 unsigned int *handle)
13836 {
13837 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
13838 struct drm_i915_gem_object *obj = intel_fb->obj;
13839
13840 return drm_gem_handle_create(file, &obj->base, handle);
13841 }
13842
13843 static const struct drm_framebuffer_funcs intel_fb_funcs = {
13844 .destroy = intel_user_framebuffer_destroy,
13845 .create_handle = intel_user_framebuffer_create_handle,
13846 };
13847
13848 static
13849 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13850 uint32_t pixel_format)
13851 {
13852 u32 gen = INTEL_INFO(dev)->gen;
13853
13854 if (gen >= 9) {
13855 /* "The stride in bytes must not exceed the of the size of 8K
13856 * pixels and 32K bytes."
13857 */
13858 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13859 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13860 return 32*1024;
13861 } else if (gen >= 4) {
13862 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13863 return 16*1024;
13864 else
13865 return 32*1024;
13866 } else if (gen >= 3) {
13867 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13868 return 8*1024;
13869 else
13870 return 16*1024;
13871 } else {
13872 /* XXX DSPC is limited to 4k tiled */
13873 return 8*1024;
13874 }
13875 }
13876
13877 static int intel_framebuffer_init(struct drm_device *dev,
13878 struct intel_framebuffer *intel_fb,
13879 struct drm_mode_fb_cmd2 *mode_cmd,
13880 struct drm_i915_gem_object *obj)
13881 {
13882 unsigned int aligned_height;
13883 int ret;
13884 u32 pitch_limit, stride_alignment;
13885
13886 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13887
13888 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13889 /* Enforce that fb modifier and tiling mode match, but only for
13890 * X-tiled. This is needed for FBC. */
13891 if (!!(obj->tiling_mode == I915_TILING_X) !=
13892 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13893 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13894 return -EINVAL;
13895 }
13896 } else {
13897 if (obj->tiling_mode == I915_TILING_X)
13898 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13899 else if (obj->tiling_mode == I915_TILING_Y) {
13900 DRM_DEBUG("No Y tiling for legacy addfb\n");
13901 return -EINVAL;
13902 }
13903 }
13904
13905 /* Passed in modifier sanity checking. */
13906 switch (mode_cmd->modifier[0]) {
13907 case I915_FORMAT_MOD_Y_TILED:
13908 case I915_FORMAT_MOD_Yf_TILED:
13909 if (INTEL_INFO(dev)->gen < 9) {
13910 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13911 mode_cmd->modifier[0]);
13912 return -EINVAL;
13913 }
13914 case DRM_FORMAT_MOD_NONE:
13915 case I915_FORMAT_MOD_X_TILED:
13916 break;
13917 default:
13918 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13919 mode_cmd->modifier[0]);
13920 return -EINVAL;
13921 }
13922
13923 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13924 mode_cmd->pixel_format);
13925 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13926 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13927 mode_cmd->pitches[0], stride_alignment);
13928 return -EINVAL;
13929 }
13930
13931 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13932 mode_cmd->pixel_format);
13933 if (mode_cmd->pitches[0] > pitch_limit) {
13934 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13935 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
13936 "tiled" : "linear",
13937 mode_cmd->pitches[0], pitch_limit);
13938 return -EINVAL;
13939 }
13940
13941 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
13942 mode_cmd->pitches[0] != obj->stride) {
13943 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13944 mode_cmd->pitches[0], obj->stride);
13945 return -EINVAL;
13946 }
13947
13948 /* Reject formats not supported by any plane early. */
13949 switch (mode_cmd->pixel_format) {
13950 case DRM_FORMAT_C8:
13951 case DRM_FORMAT_RGB565:
13952 case DRM_FORMAT_XRGB8888:
13953 case DRM_FORMAT_ARGB8888:
13954 break;
13955 case DRM_FORMAT_XRGB1555:
13956 case DRM_FORMAT_ARGB1555:
13957 if (INTEL_INFO(dev)->gen > 3) {
13958 DRM_DEBUG("unsupported pixel format: %s\n",
13959 drm_get_format_name(mode_cmd->pixel_format));
13960 return -EINVAL;
13961 }
13962 break;
13963 case DRM_FORMAT_XBGR8888:
13964 case DRM_FORMAT_ABGR8888:
13965 case DRM_FORMAT_XRGB2101010:
13966 case DRM_FORMAT_ARGB2101010:
13967 case DRM_FORMAT_XBGR2101010:
13968 case DRM_FORMAT_ABGR2101010:
13969 if (INTEL_INFO(dev)->gen < 4) {
13970 DRM_DEBUG("unsupported pixel format: %s\n",
13971 drm_get_format_name(mode_cmd->pixel_format));
13972 return -EINVAL;
13973 }
13974 break;
13975 case DRM_FORMAT_YUYV:
13976 case DRM_FORMAT_UYVY:
13977 case DRM_FORMAT_YVYU:
13978 case DRM_FORMAT_VYUY:
13979 if (INTEL_INFO(dev)->gen < 5) {
13980 DRM_DEBUG("unsupported pixel format: %s\n",
13981 drm_get_format_name(mode_cmd->pixel_format));
13982 return -EINVAL;
13983 }
13984 break;
13985 default:
13986 DRM_DEBUG("unsupported pixel format: %s\n",
13987 drm_get_format_name(mode_cmd->pixel_format));
13988 return -EINVAL;
13989 }
13990
13991 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13992 if (mode_cmd->offsets[0] != 0)
13993 return -EINVAL;
13994
13995 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
13996 mode_cmd->pixel_format,
13997 mode_cmd->modifier[0]);
13998 /* FIXME drm helper for size checks (especially planar formats)? */
13999 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14000 return -EINVAL;
14001
14002 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14003 intel_fb->obj = obj;
14004 intel_fb->obj->framebuffer_references++;
14005
14006 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14007 if (ret) {
14008 DRM_ERROR("framebuffer init failed %d\n", ret);
14009 return ret;
14010 }
14011
14012 return 0;
14013 }
14014
14015 static struct drm_framebuffer *
14016 intel_user_framebuffer_create(struct drm_device *dev,
14017 struct drm_file *filp,
14018 struct drm_mode_fb_cmd2 *mode_cmd)
14019 {
14020 struct drm_i915_gem_object *obj;
14021
14022 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14023 mode_cmd->handles[0]));
14024 if (&obj->base == NULL)
14025 return ERR_PTR(-ENOENT);
14026
14027 return intel_framebuffer_create(dev, mode_cmd, obj);
14028 }
14029
14030 #ifndef CONFIG_DRM_I915_FBDEV
14031 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14032 {
14033 }
14034 #endif
14035
14036 static const struct drm_mode_config_funcs intel_mode_funcs = {
14037 .fb_create = intel_user_framebuffer_create,
14038 .output_poll_changed = intel_fbdev_output_poll_changed,
14039 .atomic_check = intel_atomic_check,
14040 .atomic_commit = intel_atomic_commit,
14041 };
14042
14043 /* Set up chip specific display functions */
14044 static void intel_init_display(struct drm_device *dev)
14045 {
14046 struct drm_i915_private *dev_priv = dev->dev_private;
14047
14048 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14049 dev_priv->display.find_dpll = g4x_find_best_dpll;
14050 else if (IS_CHERRYVIEW(dev))
14051 dev_priv->display.find_dpll = chv_find_best_dpll;
14052 else if (IS_VALLEYVIEW(dev))
14053 dev_priv->display.find_dpll = vlv_find_best_dpll;
14054 else if (IS_PINEVIEW(dev))
14055 dev_priv->display.find_dpll = pnv_find_best_dpll;
14056 else
14057 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14058
14059 if (INTEL_INFO(dev)->gen >= 9) {
14060 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14061 dev_priv->display.get_initial_plane_config =
14062 skylake_get_initial_plane_config;
14063 dev_priv->display.crtc_compute_clock =
14064 haswell_crtc_compute_clock;
14065 dev_priv->display.crtc_enable = haswell_crtc_enable;
14066 dev_priv->display.crtc_disable = haswell_crtc_disable;
14067 dev_priv->display.off = ironlake_crtc_off;
14068 dev_priv->display.update_primary_plane =
14069 skylake_update_primary_plane;
14070 } else if (HAS_DDI(dev)) {
14071 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14072 dev_priv->display.get_initial_plane_config =
14073 ironlake_get_initial_plane_config;
14074 dev_priv->display.crtc_compute_clock =
14075 haswell_crtc_compute_clock;
14076 dev_priv->display.crtc_enable = haswell_crtc_enable;
14077 dev_priv->display.crtc_disable = haswell_crtc_disable;
14078 dev_priv->display.off = ironlake_crtc_off;
14079 dev_priv->display.update_primary_plane =
14080 ironlake_update_primary_plane;
14081 } else if (HAS_PCH_SPLIT(dev)) {
14082 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
14083 dev_priv->display.get_initial_plane_config =
14084 ironlake_get_initial_plane_config;
14085 dev_priv->display.crtc_compute_clock =
14086 ironlake_crtc_compute_clock;
14087 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14088 dev_priv->display.crtc_disable = ironlake_crtc_disable;
14089 dev_priv->display.off = ironlake_crtc_off;
14090 dev_priv->display.update_primary_plane =
14091 ironlake_update_primary_plane;
14092 } else if (IS_VALLEYVIEW(dev)) {
14093 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14094 dev_priv->display.get_initial_plane_config =
14095 i9xx_get_initial_plane_config;
14096 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14097 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14098 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14099 dev_priv->display.off = i9xx_crtc_off;
14100 dev_priv->display.update_primary_plane =
14101 i9xx_update_primary_plane;
14102 } else {
14103 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
14104 dev_priv->display.get_initial_plane_config =
14105 i9xx_get_initial_plane_config;
14106 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
14107 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14108 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14109 dev_priv->display.off = i9xx_crtc_off;
14110 dev_priv->display.update_primary_plane =
14111 i9xx_update_primary_plane;
14112 }
14113
14114 /* Returns the core display clock speed */
14115 if (IS_SKYLAKE(dev))
14116 dev_priv->display.get_display_clock_speed =
14117 skylake_get_display_clock_speed;
14118 else if (IS_BROADWELL(dev))
14119 dev_priv->display.get_display_clock_speed =
14120 broadwell_get_display_clock_speed;
14121 else if (IS_HASWELL(dev))
14122 dev_priv->display.get_display_clock_speed =
14123 haswell_get_display_clock_speed;
14124 else if (IS_VALLEYVIEW(dev))
14125 dev_priv->display.get_display_clock_speed =
14126 valleyview_get_display_clock_speed;
14127 else if (IS_GEN5(dev))
14128 dev_priv->display.get_display_clock_speed =
14129 ilk_get_display_clock_speed;
14130 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14131 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
14132 dev_priv->display.get_display_clock_speed =
14133 i945_get_display_clock_speed;
14134 else if (IS_I915G(dev))
14135 dev_priv->display.get_display_clock_speed =
14136 i915_get_display_clock_speed;
14137 else if (IS_I945GM(dev) || IS_845G(dev))
14138 dev_priv->display.get_display_clock_speed =
14139 i9xx_misc_get_display_clock_speed;
14140 else if (IS_PINEVIEW(dev))
14141 dev_priv->display.get_display_clock_speed =
14142 pnv_get_display_clock_speed;
14143 else if (IS_I915GM(dev))
14144 dev_priv->display.get_display_clock_speed =
14145 i915gm_get_display_clock_speed;
14146 else if (IS_I865G(dev))
14147 dev_priv->display.get_display_clock_speed =
14148 i865_get_display_clock_speed;
14149 else if (IS_I85X(dev))
14150 dev_priv->display.get_display_clock_speed =
14151 i855_get_display_clock_speed;
14152 else /* 852, 830 */
14153 dev_priv->display.get_display_clock_speed =
14154 i830_get_display_clock_speed;
14155
14156 if (IS_GEN5(dev)) {
14157 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
14158 } else if (IS_GEN6(dev)) {
14159 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
14160 } else if (IS_IVYBRIDGE(dev)) {
14161 /* FIXME: detect B0+ stepping and use auto training */
14162 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
14163 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
14164 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
14165 } else if (IS_VALLEYVIEW(dev)) {
14166 dev_priv->display.modeset_global_resources =
14167 valleyview_modeset_global_resources;
14168 } else if (IS_BROXTON(dev)) {
14169 dev_priv->display.modeset_global_resources =
14170 broxton_modeset_global_resources;
14171 }
14172
14173 switch (INTEL_INFO(dev)->gen) {
14174 case 2:
14175 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14176 break;
14177
14178 case 3:
14179 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14180 break;
14181
14182 case 4:
14183 case 5:
14184 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14185 break;
14186
14187 case 6:
14188 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14189 break;
14190 case 7:
14191 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
14192 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14193 break;
14194 case 9:
14195 /* Drop through - unsupported since execlist only. */
14196 default:
14197 /* Default just returns -ENODEV to indicate unsupported */
14198 dev_priv->display.queue_flip = intel_default_queue_flip;
14199 }
14200
14201 intel_panel_init_backlight_funcs(dev);
14202
14203 mutex_init(&dev_priv->pps_mutex);
14204 }
14205
14206 /*
14207 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14208 * resume, or other times. This quirk makes sure that's the case for
14209 * affected systems.
14210 */
14211 static void quirk_pipea_force(struct drm_device *dev)
14212 {
14213 struct drm_i915_private *dev_priv = dev->dev_private;
14214
14215 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
14216 DRM_INFO("applying pipe a force quirk\n");
14217 }
14218
14219 static void quirk_pipeb_force(struct drm_device *dev)
14220 {
14221 struct drm_i915_private *dev_priv = dev->dev_private;
14222
14223 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14224 DRM_INFO("applying pipe b force quirk\n");
14225 }
14226
14227 /*
14228 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14229 */
14230 static void quirk_ssc_force_disable(struct drm_device *dev)
14231 {
14232 struct drm_i915_private *dev_priv = dev->dev_private;
14233 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
14234 DRM_INFO("applying lvds SSC disable quirk\n");
14235 }
14236
14237 /*
14238 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14239 * brightness value
14240 */
14241 static void quirk_invert_brightness(struct drm_device *dev)
14242 {
14243 struct drm_i915_private *dev_priv = dev->dev_private;
14244 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
14245 DRM_INFO("applying inverted panel brightness quirk\n");
14246 }
14247
14248 /* Some VBT's incorrectly indicate no backlight is present */
14249 static void quirk_backlight_present(struct drm_device *dev)
14250 {
14251 struct drm_i915_private *dev_priv = dev->dev_private;
14252 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14253 DRM_INFO("applying backlight present quirk\n");
14254 }
14255
14256 struct intel_quirk {
14257 int device;
14258 int subsystem_vendor;
14259 int subsystem_device;
14260 void (*hook)(struct drm_device *dev);
14261 };
14262
14263 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14264 struct intel_dmi_quirk {
14265 void (*hook)(struct drm_device *dev);
14266 const struct dmi_system_id (*dmi_id_list)[];
14267 };
14268
14269 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14270 {
14271 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14272 return 1;
14273 }
14274
14275 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14276 {
14277 .dmi_id_list = &(const struct dmi_system_id[]) {
14278 {
14279 .callback = intel_dmi_reverse_brightness,
14280 .ident = "NCR Corporation",
14281 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14282 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14283 },
14284 },
14285 { } /* terminating entry */
14286 },
14287 .hook = quirk_invert_brightness,
14288 },
14289 };
14290
14291 static struct intel_quirk intel_quirks[] = {
14292 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14293 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14294
14295 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14296 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14297
14298 /* 830 needs to leave pipe A & dpll A up */
14299 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14300
14301 /* 830 needs to leave pipe B & dpll B up */
14302 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14303
14304 /* Lenovo U160 cannot use SSC on LVDS */
14305 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
14306
14307 /* Sony Vaio Y cannot use SSC on LVDS */
14308 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
14309
14310 /* Acer Aspire 5734Z must invert backlight brightness */
14311 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14312
14313 /* Acer/eMachines G725 */
14314 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14315
14316 /* Acer/eMachines e725 */
14317 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14318
14319 /* Acer/Packard Bell NCL20 */
14320 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14321
14322 /* Acer Aspire 4736Z */
14323 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
14324
14325 /* Acer Aspire 5336 */
14326 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
14327
14328 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14329 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
14330
14331 /* Acer C720 Chromebook (Core i3 4005U) */
14332 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14333
14334 /* Apple Macbook 2,1 (Core 2 T7400) */
14335 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14336
14337 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14338 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
14339
14340 /* HP Chromebook 14 (Celeron 2955U) */
14341 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
14342
14343 /* Dell Chromebook 11 */
14344 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
14345 };
14346
14347 static void intel_init_quirks(struct drm_device *dev)
14348 {
14349 struct pci_dev *d = dev->pdev;
14350 int i;
14351
14352 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14353 struct intel_quirk *q = &intel_quirks[i];
14354
14355 if (d->device == q->device &&
14356 (d->subsystem_vendor == q->subsystem_vendor ||
14357 q->subsystem_vendor == PCI_ANY_ID) &&
14358 (d->subsystem_device == q->subsystem_device ||
14359 q->subsystem_device == PCI_ANY_ID))
14360 q->hook(dev);
14361 }
14362 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14363 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14364 intel_dmi_quirks[i].hook(dev);
14365 }
14366 }
14367
14368 /* Disable the VGA plane that we never use */
14369 static void i915_disable_vga(struct drm_device *dev)
14370 {
14371 struct drm_i915_private *dev_priv = dev->dev_private;
14372 u8 sr1;
14373 u32 vga_reg = i915_vgacntrl_reg(dev);
14374
14375 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
14376 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
14377 outb(SR01, VGA_SR_INDEX);
14378 sr1 = inb(VGA_SR_DATA);
14379 outb(sr1 | 1<<5, VGA_SR_DATA);
14380 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14381 udelay(300);
14382
14383 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
14384 POSTING_READ(vga_reg);
14385 }
14386
14387 void intel_modeset_init_hw(struct drm_device *dev)
14388 {
14389 intel_prepare_ddi(dev);
14390
14391 if (IS_VALLEYVIEW(dev))
14392 vlv_update_cdclk(dev);
14393
14394 intel_init_clock_gating(dev);
14395
14396 intel_enable_gt_powersave(dev);
14397 }
14398
14399 void intel_modeset_init(struct drm_device *dev)
14400 {
14401 struct drm_i915_private *dev_priv = dev->dev_private;
14402 int sprite, ret;
14403 enum pipe pipe;
14404 struct intel_crtc *crtc;
14405
14406 drm_mode_config_init(dev);
14407
14408 dev->mode_config.min_width = 0;
14409 dev->mode_config.min_height = 0;
14410
14411 dev->mode_config.preferred_depth = 24;
14412 dev->mode_config.prefer_shadow = 1;
14413
14414 dev->mode_config.allow_fb_modifiers = true;
14415
14416 dev->mode_config.funcs = &intel_mode_funcs;
14417
14418 intel_init_quirks(dev);
14419
14420 intel_init_pm(dev);
14421
14422 if (INTEL_INFO(dev)->num_pipes == 0)
14423 return;
14424
14425 intel_init_display(dev);
14426 intel_init_audio(dev);
14427
14428 if (IS_GEN2(dev)) {
14429 dev->mode_config.max_width = 2048;
14430 dev->mode_config.max_height = 2048;
14431 } else if (IS_GEN3(dev)) {
14432 dev->mode_config.max_width = 4096;
14433 dev->mode_config.max_height = 4096;
14434 } else {
14435 dev->mode_config.max_width = 8192;
14436 dev->mode_config.max_height = 8192;
14437 }
14438
14439 if (IS_845G(dev) || IS_I865G(dev)) {
14440 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14441 dev->mode_config.cursor_height = 1023;
14442 } else if (IS_GEN2(dev)) {
14443 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14444 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14445 } else {
14446 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14447 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14448 }
14449
14450 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
14451
14452 DRM_DEBUG_KMS("%d display pipe%s available.\n",
14453 INTEL_INFO(dev)->num_pipes,
14454 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
14455
14456 for_each_pipe(dev_priv, pipe) {
14457 intel_crtc_init(dev, pipe);
14458 for_each_sprite(dev_priv, pipe, sprite) {
14459 ret = intel_plane_init(dev, pipe, sprite);
14460 if (ret)
14461 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
14462 pipe_name(pipe), sprite_name(pipe, sprite), ret);
14463 }
14464 }
14465
14466 intel_init_dpio(dev);
14467
14468 intel_shared_dpll_init(dev);
14469
14470 /* Just disable it once at startup */
14471 i915_disable_vga(dev);
14472 intel_setup_outputs(dev);
14473
14474 /* Just in case the BIOS is doing something questionable. */
14475 intel_fbc_disable(dev);
14476
14477 drm_modeset_lock_all(dev);
14478 intel_modeset_setup_hw_state(dev, false);
14479 drm_modeset_unlock_all(dev);
14480
14481 for_each_intel_crtc(dev, crtc) {
14482 if (!crtc->active)
14483 continue;
14484
14485 /*
14486 * Note that reserving the BIOS fb up front prevents us
14487 * from stuffing other stolen allocations like the ring
14488 * on top. This prevents some ugliness at boot time, and
14489 * can even allow for smooth boot transitions if the BIOS
14490 * fb is large enough for the active pipe configuration.
14491 */
14492 if (dev_priv->display.get_initial_plane_config) {
14493 dev_priv->display.get_initial_plane_config(crtc,
14494 &crtc->plane_config);
14495 /*
14496 * If the fb is shared between multiple heads, we'll
14497 * just get the first one.
14498 */
14499 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
14500 }
14501 }
14502 }
14503
14504 static void intel_enable_pipe_a(struct drm_device *dev)
14505 {
14506 struct intel_connector *connector;
14507 struct drm_connector *crt = NULL;
14508 struct intel_load_detect_pipe load_detect_temp;
14509 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
14510
14511 /* We can't just switch on the pipe A, we need to set things up with a
14512 * proper mode and output configuration. As a gross hack, enable pipe A
14513 * by enabling the load detect pipe once. */
14514 for_each_intel_connector(dev, connector) {
14515 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14516 crt = &connector->base;
14517 break;
14518 }
14519 }
14520
14521 if (!crt)
14522 return;
14523
14524 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
14525 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
14526 }
14527
14528 static bool
14529 intel_check_plane_mapping(struct intel_crtc *crtc)
14530 {
14531 struct drm_device *dev = crtc->base.dev;
14532 struct drm_i915_private *dev_priv = dev->dev_private;
14533 u32 reg, val;
14534
14535 if (INTEL_INFO(dev)->num_pipes == 1)
14536 return true;
14537
14538 reg = DSPCNTR(!crtc->plane);
14539 val = I915_READ(reg);
14540
14541 if ((val & DISPLAY_PLANE_ENABLE) &&
14542 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14543 return false;
14544
14545 return true;
14546 }
14547
14548 static void intel_sanitize_crtc(struct intel_crtc *crtc)
14549 {
14550 struct drm_device *dev = crtc->base.dev;
14551 struct drm_i915_private *dev_priv = dev->dev_private;
14552 u32 reg;
14553
14554 /* Clear any frame start delays used for debugging left by the BIOS */
14555 reg = PIPECONF(crtc->config->cpu_transcoder);
14556 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14557
14558 /* restore vblank interrupts to correct state */
14559 drm_crtc_vblank_reset(&crtc->base);
14560 if (crtc->active) {
14561 update_scanline_offset(crtc);
14562 drm_crtc_vblank_on(&crtc->base);
14563 }
14564
14565 /* We need to sanitize the plane -> pipe mapping first because this will
14566 * disable the crtc (and hence change the state) if it is wrong. Note
14567 * that gen4+ has a fixed plane -> pipe mapping. */
14568 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
14569 struct intel_connector *connector;
14570 bool plane;
14571
14572 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14573 crtc->base.base.id);
14574
14575 /* Pipe has the wrong plane attached and the plane is active.
14576 * Temporarily change the plane mapping and disable everything
14577 * ... */
14578 plane = crtc->plane;
14579 to_intel_plane_state(crtc->base.primary->state)->visible = true;
14580 crtc->plane = !plane;
14581 intel_crtc_disable_planes(&crtc->base);
14582 dev_priv->display.crtc_disable(&crtc->base);
14583 crtc->plane = plane;
14584
14585 /* ... and break all links. */
14586 for_each_intel_connector(dev, connector) {
14587 if (connector->encoder->base.crtc != &crtc->base)
14588 continue;
14589
14590 connector->base.dpms = DRM_MODE_DPMS_OFF;
14591 connector->base.encoder = NULL;
14592 }
14593 /* multiple connectors may have the same encoder:
14594 * handle them and break crtc link separately */
14595 for_each_intel_connector(dev, connector)
14596 if (connector->encoder->base.crtc == &crtc->base) {
14597 connector->encoder->base.crtc = NULL;
14598 connector->encoder->connectors_active = false;
14599 }
14600
14601 WARN_ON(crtc->active);
14602 crtc->base.state->enable = false;
14603 crtc->base.state->active = false;
14604 crtc->base.enabled = false;
14605 }
14606
14607 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14608 crtc->pipe == PIPE_A && !crtc->active) {
14609 /* BIOS forgot to enable pipe A, this mostly happens after
14610 * resume. Force-enable the pipe to fix this, the update_dpms
14611 * call below we restore the pipe to the right state, but leave
14612 * the required bits on. */
14613 intel_enable_pipe_a(dev);
14614 }
14615
14616 /* Adjust the state of the output pipe according to whether we
14617 * have active connectors/encoders. */
14618 intel_crtc_update_dpms(&crtc->base);
14619
14620 if (crtc->active != crtc->base.state->enable) {
14621 struct intel_encoder *encoder;
14622
14623 /* This can happen either due to bugs in the get_hw_state
14624 * functions or because the pipe is force-enabled due to the
14625 * pipe A quirk. */
14626 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14627 crtc->base.base.id,
14628 crtc->base.state->enable ? "enabled" : "disabled",
14629 crtc->active ? "enabled" : "disabled");
14630
14631 crtc->base.state->enable = crtc->active;
14632 crtc->base.state->active = crtc->active;
14633 crtc->base.enabled = crtc->active;
14634
14635 /* Because we only establish the connector -> encoder ->
14636 * crtc links if something is active, this means the
14637 * crtc is now deactivated. Break the links. connector
14638 * -> encoder links are only establish when things are
14639 * actually up, hence no need to break them. */
14640 WARN_ON(crtc->active);
14641
14642 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14643 WARN_ON(encoder->connectors_active);
14644 encoder->base.crtc = NULL;
14645 }
14646 }
14647
14648 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
14649 /*
14650 * We start out with underrun reporting disabled to avoid races.
14651 * For correct bookkeeping mark this on active crtcs.
14652 *
14653 * Also on gmch platforms we dont have any hardware bits to
14654 * disable the underrun reporting. Which means we need to start
14655 * out with underrun reporting disabled also on inactive pipes,
14656 * since otherwise we'll complain about the garbage we read when
14657 * e.g. coming up after runtime pm.
14658 *
14659 * No protection against concurrent access is required - at
14660 * worst a fifo underrun happens which also sets this to false.
14661 */
14662 crtc->cpu_fifo_underrun_disabled = true;
14663 crtc->pch_fifo_underrun_disabled = true;
14664 }
14665 }
14666
14667 static void intel_sanitize_encoder(struct intel_encoder *encoder)
14668 {
14669 struct intel_connector *connector;
14670 struct drm_device *dev = encoder->base.dev;
14671
14672 /* We need to check both for a crtc link (meaning that the
14673 * encoder is active and trying to read from a pipe) and the
14674 * pipe itself being active. */
14675 bool has_active_crtc = encoder->base.crtc &&
14676 to_intel_crtc(encoder->base.crtc)->active;
14677
14678 if (encoder->connectors_active && !has_active_crtc) {
14679 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14680 encoder->base.base.id,
14681 encoder->base.name);
14682
14683 /* Connector is active, but has no active pipe. This is
14684 * fallout from our resume register restoring. Disable
14685 * the encoder manually again. */
14686 if (encoder->base.crtc) {
14687 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14688 encoder->base.base.id,
14689 encoder->base.name);
14690 encoder->disable(encoder);
14691 if (encoder->post_disable)
14692 encoder->post_disable(encoder);
14693 }
14694 encoder->base.crtc = NULL;
14695 encoder->connectors_active = false;
14696
14697 /* Inconsistent output/port/pipe state happens presumably due to
14698 * a bug in one of the get_hw_state functions. Or someplace else
14699 * in our code, like the register restore mess on resume. Clamp
14700 * things to off as a safer default. */
14701 for_each_intel_connector(dev, connector) {
14702 if (connector->encoder != encoder)
14703 continue;
14704 connector->base.dpms = DRM_MODE_DPMS_OFF;
14705 connector->base.encoder = NULL;
14706 }
14707 }
14708 /* Enabled encoders without active connectors will be fixed in
14709 * the crtc fixup. */
14710 }
14711
14712 void i915_redisable_vga_power_on(struct drm_device *dev)
14713 {
14714 struct drm_i915_private *dev_priv = dev->dev_private;
14715 u32 vga_reg = i915_vgacntrl_reg(dev);
14716
14717 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14718 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14719 i915_disable_vga(dev);
14720 }
14721 }
14722
14723 void i915_redisable_vga(struct drm_device *dev)
14724 {
14725 struct drm_i915_private *dev_priv = dev->dev_private;
14726
14727 /* This function can be called both from intel_modeset_setup_hw_state or
14728 * at a very early point in our resume sequence, where the power well
14729 * structures are not yet restored. Since this function is at a very
14730 * paranoid "someone might have enabled VGA while we were not looking"
14731 * level, just check if the power well is enabled instead of trying to
14732 * follow the "don't touch the power well if we don't need it" policy
14733 * the rest of the driver uses. */
14734 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
14735 return;
14736
14737 i915_redisable_vga_power_on(dev);
14738 }
14739
14740 static bool primary_get_hw_state(struct intel_crtc *crtc)
14741 {
14742 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14743
14744 if (!crtc->active)
14745 return false;
14746
14747 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14748 }
14749
14750 static void intel_modeset_readout_hw_state(struct drm_device *dev)
14751 {
14752 struct drm_i915_private *dev_priv = dev->dev_private;
14753 enum pipe pipe;
14754 struct intel_crtc *crtc;
14755 struct intel_encoder *encoder;
14756 struct intel_connector *connector;
14757 int i;
14758
14759 for_each_intel_crtc(dev, crtc) {
14760 struct drm_plane *primary = crtc->base.primary;
14761 struct intel_plane_state *plane_state;
14762
14763 memset(crtc->config, 0, sizeof(*crtc->config));
14764
14765 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
14766
14767 crtc->active = dev_priv->display.get_pipe_config(crtc,
14768 crtc->config);
14769
14770 crtc->base.state->enable = crtc->active;
14771 crtc->base.state->active = crtc->active;
14772 crtc->base.enabled = crtc->active;
14773
14774 plane_state = to_intel_plane_state(primary->state);
14775 plane_state->visible = primary_get_hw_state(crtc);
14776
14777 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14778 crtc->base.base.id,
14779 crtc->active ? "enabled" : "disabled");
14780 }
14781
14782 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14783 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14784
14785 pll->on = pll->get_hw_state(dev_priv, pll,
14786 &pll->config.hw_state);
14787 pll->active = 0;
14788 pll->config.crtc_mask = 0;
14789 for_each_intel_crtc(dev, crtc) {
14790 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
14791 pll->active++;
14792 pll->config.crtc_mask |= 1 << crtc->pipe;
14793 }
14794 }
14795
14796 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
14797 pll->name, pll->config.crtc_mask, pll->on);
14798
14799 if (pll->config.crtc_mask)
14800 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
14801 }
14802
14803 for_each_intel_encoder(dev, encoder) {
14804 pipe = 0;
14805
14806 if (encoder->get_hw_state(encoder, &pipe)) {
14807 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14808 encoder->base.crtc = &crtc->base;
14809 encoder->get_config(encoder, crtc->config);
14810 } else {
14811 encoder->base.crtc = NULL;
14812 }
14813
14814 encoder->connectors_active = false;
14815 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
14816 encoder->base.base.id,
14817 encoder->base.name,
14818 encoder->base.crtc ? "enabled" : "disabled",
14819 pipe_name(pipe));
14820 }
14821
14822 for_each_intel_connector(dev, connector) {
14823 if (connector->get_hw_state(connector)) {
14824 connector->base.dpms = DRM_MODE_DPMS_ON;
14825 connector->encoder->connectors_active = true;
14826 connector->base.encoder = &connector->encoder->base;
14827 } else {
14828 connector->base.dpms = DRM_MODE_DPMS_OFF;
14829 connector->base.encoder = NULL;
14830 }
14831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14832 connector->base.base.id,
14833 connector->base.name,
14834 connector->base.encoder ? "enabled" : "disabled");
14835 }
14836 }
14837
14838 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14839 * and i915 state tracking structures. */
14840 void intel_modeset_setup_hw_state(struct drm_device *dev,
14841 bool force_restore)
14842 {
14843 struct drm_i915_private *dev_priv = dev->dev_private;
14844 enum pipe pipe;
14845 struct intel_crtc *crtc;
14846 struct intel_encoder *encoder;
14847 int i;
14848
14849 intel_modeset_readout_hw_state(dev);
14850
14851 /*
14852 * Now that we have the config, copy it to each CRTC struct
14853 * Note that this could go away if we move to using crtc_config
14854 * checking everywhere.
14855 */
14856 for_each_intel_crtc(dev, crtc) {
14857 if (crtc->active && i915.fastboot) {
14858 intel_mode_from_pipe_config(&crtc->base.mode,
14859 crtc->config);
14860 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14861 crtc->base.base.id);
14862 drm_mode_debug_printmodeline(&crtc->base.mode);
14863 }
14864 }
14865
14866 /* HW state is read out, now we need to sanitize this mess. */
14867 for_each_intel_encoder(dev, encoder) {
14868 intel_sanitize_encoder(encoder);
14869 }
14870
14871 for_each_pipe(dev_priv, pipe) {
14872 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14873 intel_sanitize_crtc(crtc);
14874 intel_dump_pipe_config(crtc, crtc->config,
14875 "[setup_hw_state]");
14876 }
14877
14878 intel_modeset_update_connector_atomic_state(dev);
14879
14880 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14881 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14882
14883 if (!pll->on || pll->active)
14884 continue;
14885
14886 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14887
14888 pll->disable(dev_priv, pll);
14889 pll->on = false;
14890 }
14891
14892 if (IS_GEN9(dev))
14893 skl_wm_get_hw_state(dev);
14894 else if (HAS_PCH_SPLIT(dev))
14895 ilk_wm_get_hw_state(dev);
14896
14897 if (force_restore) {
14898 i915_redisable_vga(dev);
14899
14900 /*
14901 * We need to use raw interfaces for restoring state to avoid
14902 * checking (bogus) intermediate states.
14903 */
14904 for_each_pipe(dev_priv, pipe) {
14905 struct drm_crtc *crtc =
14906 dev_priv->pipe_to_crtc_mapping[pipe];
14907
14908 intel_crtc_restore_mode(crtc);
14909 }
14910 } else {
14911 intel_modeset_update_staged_output_state(dev);
14912 }
14913
14914 intel_modeset_check_state(dev);
14915 }
14916
14917 void intel_modeset_gem_init(struct drm_device *dev)
14918 {
14919 struct drm_i915_private *dev_priv = dev->dev_private;
14920 struct drm_crtc *c;
14921 struct drm_i915_gem_object *obj;
14922 int ret;
14923
14924 mutex_lock(&dev->struct_mutex);
14925 intel_init_gt_powersave(dev);
14926 mutex_unlock(&dev->struct_mutex);
14927
14928 /*
14929 * There may be no VBT; and if the BIOS enabled SSC we can
14930 * just keep using it to avoid unnecessary flicker. Whereas if the
14931 * BIOS isn't using it, don't assume it will work even if the VBT
14932 * indicates as much.
14933 */
14934 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14935 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14936 DREF_SSC1_ENABLE);
14937
14938 intel_modeset_init_hw(dev);
14939
14940 intel_setup_overlay(dev);
14941
14942 /*
14943 * Make sure any fbs we allocated at startup are properly
14944 * pinned & fenced. When we do the allocation it's too early
14945 * for this.
14946 */
14947 for_each_crtc(dev, c) {
14948 obj = intel_fb_obj(c->primary->fb);
14949 if (obj == NULL)
14950 continue;
14951
14952 mutex_lock(&dev->struct_mutex);
14953 ret = intel_pin_and_fence_fb_obj(c->primary,
14954 c->primary->fb,
14955 c->primary->state,
14956 NULL);
14957 mutex_unlock(&dev->struct_mutex);
14958 if (ret) {
14959 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14960 to_intel_crtc(c)->pipe);
14961 drm_framebuffer_unreference(c->primary->fb);
14962 c->primary->fb = NULL;
14963 update_state_fb(c->primary);
14964 }
14965 }
14966
14967 intel_backlight_register(dev);
14968 }
14969
14970 void intel_connector_unregister(struct intel_connector *intel_connector)
14971 {
14972 struct drm_connector *connector = &intel_connector->base;
14973
14974 intel_panel_destroy_backlight(connector);
14975 drm_connector_unregister(connector);
14976 }
14977
14978 void intel_modeset_cleanup(struct drm_device *dev)
14979 {
14980 struct drm_i915_private *dev_priv = dev->dev_private;
14981 struct drm_connector *connector;
14982
14983 intel_disable_gt_powersave(dev);
14984
14985 intel_backlight_unregister(dev);
14986
14987 /*
14988 * Interrupts and polling as the first thing to avoid creating havoc.
14989 * Too much stuff here (turning of connectors, ...) would
14990 * experience fancy races otherwise.
14991 */
14992 intel_irq_uninstall(dev_priv);
14993
14994 /*
14995 * Due to the hpd irq storm handling the hotplug work can re-arm the
14996 * poll handlers. Hence disable polling after hpd handling is shut down.
14997 */
14998 drm_kms_helper_poll_fini(dev);
14999
15000 mutex_lock(&dev->struct_mutex);
15001
15002 intel_unregister_dsm_handler();
15003
15004 intel_fbc_disable(dev);
15005
15006 mutex_unlock(&dev->struct_mutex);
15007
15008 /* flush any delayed tasks or pending work */
15009 flush_scheduled_work();
15010
15011 /* destroy the backlight and sysfs files before encoders/connectors */
15012 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
15013 struct intel_connector *intel_connector;
15014
15015 intel_connector = to_intel_connector(connector);
15016 intel_connector->unregister(intel_connector);
15017 }
15018
15019 drm_mode_config_cleanup(dev);
15020
15021 intel_cleanup_overlay(dev);
15022
15023 mutex_lock(&dev->struct_mutex);
15024 intel_cleanup_gt_powersave(dev);
15025 mutex_unlock(&dev->struct_mutex);
15026 }
15027
15028 /*
15029 * Return which encoder is currently attached for connector.
15030 */
15031 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
15032 {
15033 return &intel_attached_encoder(connector)->base;
15034 }
15035
15036 void intel_connector_attach_encoder(struct intel_connector *connector,
15037 struct intel_encoder *encoder)
15038 {
15039 connector->encoder = encoder;
15040 drm_mode_connector_attach_encoder(&connector->base,
15041 &encoder->base);
15042 }
15043
15044 /*
15045 * set vga decode state - true == enable VGA decode
15046 */
15047 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15048 {
15049 struct drm_i915_private *dev_priv = dev->dev_private;
15050 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
15051 u16 gmch_ctrl;
15052
15053 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15054 DRM_ERROR("failed to read control word\n");
15055 return -EIO;
15056 }
15057
15058 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15059 return 0;
15060
15061 if (state)
15062 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15063 else
15064 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
15065
15066 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15067 DRM_ERROR("failed to write control word\n");
15068 return -EIO;
15069 }
15070
15071 return 0;
15072 }
15073
15074 struct intel_display_error_state {
15075
15076 u32 power_well_driver;
15077
15078 int num_transcoders;
15079
15080 struct intel_cursor_error_state {
15081 u32 control;
15082 u32 position;
15083 u32 base;
15084 u32 size;
15085 } cursor[I915_MAX_PIPES];
15086
15087 struct intel_pipe_error_state {
15088 bool power_domain_on;
15089 u32 source;
15090 u32 stat;
15091 } pipe[I915_MAX_PIPES];
15092
15093 struct intel_plane_error_state {
15094 u32 control;
15095 u32 stride;
15096 u32 size;
15097 u32 pos;
15098 u32 addr;
15099 u32 surface;
15100 u32 tile_offset;
15101 } plane[I915_MAX_PIPES];
15102
15103 struct intel_transcoder_error_state {
15104 bool power_domain_on;
15105 enum transcoder cpu_transcoder;
15106
15107 u32 conf;
15108
15109 u32 htotal;
15110 u32 hblank;
15111 u32 hsync;
15112 u32 vtotal;
15113 u32 vblank;
15114 u32 vsync;
15115 } transcoder[4];
15116 };
15117
15118 struct intel_display_error_state *
15119 intel_display_capture_error_state(struct drm_device *dev)
15120 {
15121 struct drm_i915_private *dev_priv = dev->dev_private;
15122 struct intel_display_error_state *error;
15123 int transcoders[] = {
15124 TRANSCODER_A,
15125 TRANSCODER_B,
15126 TRANSCODER_C,
15127 TRANSCODER_EDP,
15128 };
15129 int i;
15130
15131 if (INTEL_INFO(dev)->num_pipes == 0)
15132 return NULL;
15133
15134 error = kzalloc(sizeof(*error), GFP_ATOMIC);
15135 if (error == NULL)
15136 return NULL;
15137
15138 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15139 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15140
15141 for_each_pipe(dev_priv, i) {
15142 error->pipe[i].power_domain_on =
15143 __intel_display_power_is_enabled(dev_priv,
15144 POWER_DOMAIN_PIPE(i));
15145 if (!error->pipe[i].power_domain_on)
15146 continue;
15147
15148 error->cursor[i].control = I915_READ(CURCNTR(i));
15149 error->cursor[i].position = I915_READ(CURPOS(i));
15150 error->cursor[i].base = I915_READ(CURBASE(i));
15151
15152 error->plane[i].control = I915_READ(DSPCNTR(i));
15153 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
15154 if (INTEL_INFO(dev)->gen <= 3) {
15155 error->plane[i].size = I915_READ(DSPSIZE(i));
15156 error->plane[i].pos = I915_READ(DSPPOS(i));
15157 }
15158 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15159 error->plane[i].addr = I915_READ(DSPADDR(i));
15160 if (INTEL_INFO(dev)->gen >= 4) {
15161 error->plane[i].surface = I915_READ(DSPSURF(i));
15162 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15163 }
15164
15165 error->pipe[i].source = I915_READ(PIPESRC(i));
15166
15167 if (HAS_GMCH_DISPLAY(dev))
15168 error->pipe[i].stat = I915_READ(PIPESTAT(i));
15169 }
15170
15171 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15172 if (HAS_DDI(dev_priv->dev))
15173 error->num_transcoders++; /* Account for eDP. */
15174
15175 for (i = 0; i < error->num_transcoders; i++) {
15176 enum transcoder cpu_transcoder = transcoders[i];
15177
15178 error->transcoder[i].power_domain_on =
15179 __intel_display_power_is_enabled(dev_priv,
15180 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
15181 if (!error->transcoder[i].power_domain_on)
15182 continue;
15183
15184 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15185
15186 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15187 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15188 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15189 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15190 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15191 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15192 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
15193 }
15194
15195 return error;
15196 }
15197
15198 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15199
15200 void
15201 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
15202 struct drm_device *dev,
15203 struct intel_display_error_state *error)
15204 {
15205 struct drm_i915_private *dev_priv = dev->dev_private;
15206 int i;
15207
15208 if (!error)
15209 return;
15210
15211 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
15212 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
15213 err_printf(m, "PWR_WELL_CTL2: %08x\n",
15214 error->power_well_driver);
15215 for_each_pipe(dev_priv, i) {
15216 err_printf(m, "Pipe [%d]:\n", i);
15217 err_printf(m, " Power: %s\n",
15218 error->pipe[i].power_domain_on ? "on" : "off");
15219 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
15220 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
15221
15222 err_printf(m, "Plane [%d]:\n", i);
15223 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15224 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
15225 if (INTEL_INFO(dev)->gen <= 3) {
15226 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15227 err_printf(m, " POS: %08x\n", error->plane[i].pos);
15228 }
15229 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15230 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
15231 if (INTEL_INFO(dev)->gen >= 4) {
15232 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15233 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
15234 }
15235
15236 err_printf(m, "Cursor [%d]:\n", i);
15237 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15238 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15239 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
15240 }
15241
15242 for (i = 0; i < error->num_transcoders; i++) {
15243 err_printf(m, "CPU transcoder: %c\n",
15244 transcoder_name(error->transcoder[i].cpu_transcoder));
15245 err_printf(m, " Power: %s\n",
15246 error->transcoder[i].power_domain_on ? "on" : "off");
15247 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15248 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15249 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15250 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15251 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15252 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15253 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15254 }
15255 }
15256
15257 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15258 {
15259 struct intel_crtc *crtc;
15260
15261 for_each_intel_crtc(dev, crtc) {
15262 struct intel_unpin_work *work;
15263
15264 spin_lock_irq(&dev->event_lock);
15265
15266 work = crtc->unpin_work;
15267
15268 if (work && work->event &&
15269 work->event->base.file_priv == file) {
15270 kfree(work->event);
15271 work->event = NULL;
15272 }
15273
15274 spin_unlock_irq(&dev->event_lock);
15275 }
15276 }
Linux kernel - Deliverables
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