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drm/i915/audio: add DOC comment describing HDA over HDMI/DP
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
77
78 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
79 struct intel_crtc_config *pipe_config);
80 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
81 struct intel_crtc_config *pipe_config);
82
83 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
84 int x, int y, struct drm_framebuffer *old_fb);
85 static int intel_framebuffer_init(struct drm_device *dev,
86 struct intel_framebuffer *ifb,
87 struct drm_mode_fb_cmd2 *mode_cmd,
88 struct drm_i915_gem_object *obj);
89 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
90 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
91 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
92 struct intel_link_m_n *m_n,
93 struct intel_link_m_n *m2_n2);
94 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
95 static void haswell_set_pipeconf(struct drm_crtc *crtc);
96 static void intel_set_pipe_csc(struct drm_crtc *crtc);
97 static void vlv_prepare_pll(struct intel_crtc *crtc,
98 const struct intel_crtc_config *pipe_config);
99 static void chv_prepare_pll(struct intel_crtc *crtc,
100 const struct intel_crtc_config *pipe_config);
101
102 static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
103 {
104 if (!connector->mst_port)
105 return connector->encoder;
106 else
107 return &connector->mst_port->mst_encoders[pipe]->base;
108 }
109
110 typedef struct {
111 int min, max;
112 } intel_range_t;
113
114 typedef struct {
115 int dot_limit;
116 int p2_slow, p2_fast;
117 } intel_p2_t;
118
119 typedef struct intel_limit intel_limit_t;
120 struct intel_limit {
121 intel_range_t dot, vco, n, m, m1, m2, p, p1;
122 intel_p2_t p2;
123 };
124
125 int
126 intel_pch_rawclk(struct drm_device *dev)
127 {
128 struct drm_i915_private *dev_priv = dev->dev_private;
129
130 WARN_ON(!HAS_PCH_SPLIT(dev));
131
132 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
133 }
134
135 static inline u32 /* units of 100MHz */
136 intel_fdi_link_freq(struct drm_device *dev)
137 {
138 if (IS_GEN5(dev)) {
139 struct drm_i915_private *dev_priv = dev->dev_private;
140 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
141 } else
142 return 27;
143 }
144
145 static const intel_limit_t intel_limits_i8xx_dac = {
146 .dot = { .min = 25000, .max = 350000 },
147 .vco = { .min = 908000, .max = 1512000 },
148 .n = { .min = 2, .max = 16 },
149 .m = { .min = 96, .max = 140 },
150 .m1 = { .min = 18, .max = 26 },
151 .m2 = { .min = 6, .max = 16 },
152 .p = { .min = 4, .max = 128 },
153 .p1 = { .min = 2, .max = 33 },
154 .p2 = { .dot_limit = 165000,
155 .p2_slow = 4, .p2_fast = 2 },
156 };
157
158 static const intel_limit_t intel_limits_i8xx_dvo = {
159 .dot = { .min = 25000, .max = 350000 },
160 .vco = { .min = 908000, .max = 1512000 },
161 .n = { .min = 2, .max = 16 },
162 .m = { .min = 96, .max = 140 },
163 .m1 = { .min = 18, .max = 26 },
164 .m2 = { .min = 6, .max = 16 },
165 .p = { .min = 4, .max = 128 },
166 .p1 = { .min = 2, .max = 33 },
167 .p2 = { .dot_limit = 165000,
168 .p2_slow = 4, .p2_fast = 4 },
169 };
170
171 static const intel_limit_t intel_limits_i8xx_lvds = {
172 .dot = { .min = 25000, .max = 350000 },
173 .vco = { .min = 908000, .max = 1512000 },
174 .n = { .min = 2, .max = 16 },
175 .m = { .min = 96, .max = 140 },
176 .m1 = { .min = 18, .max = 26 },
177 .m2 = { .min = 6, .max = 16 },
178 .p = { .min = 4, .max = 128 },
179 .p1 = { .min = 1, .max = 6 },
180 .p2 = { .dot_limit = 165000,
181 .p2_slow = 14, .p2_fast = 7 },
182 };
183
184 static const intel_limit_t intel_limits_i9xx_sdvo = {
185 .dot = { .min = 20000, .max = 400000 },
186 .vco = { .min = 1400000, .max = 2800000 },
187 .n = { .min = 1, .max = 6 },
188 .m = { .min = 70, .max = 120 },
189 .m1 = { .min = 8, .max = 18 },
190 .m2 = { .min = 3, .max = 7 },
191 .p = { .min = 5, .max = 80 },
192 .p1 = { .min = 1, .max = 8 },
193 .p2 = { .dot_limit = 200000,
194 .p2_slow = 10, .p2_fast = 5 },
195 };
196
197 static const intel_limit_t intel_limits_i9xx_lvds = {
198 .dot = { .min = 20000, .max = 400000 },
199 .vco = { .min = 1400000, .max = 2800000 },
200 .n = { .min = 1, .max = 6 },
201 .m = { .min = 70, .max = 120 },
202 .m1 = { .min = 8, .max = 18 },
203 .m2 = { .min = 3, .max = 7 },
204 .p = { .min = 7, .max = 98 },
205 .p1 = { .min = 1, .max = 8 },
206 .p2 = { .dot_limit = 112000,
207 .p2_slow = 14, .p2_fast = 7 },
208 };
209
210
211 static const intel_limit_t intel_limits_g4x_sdvo = {
212 .dot = { .min = 25000, .max = 270000 },
213 .vco = { .min = 1750000, .max = 3500000},
214 .n = { .min = 1, .max = 4 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 10, .max = 30 },
219 .p1 = { .min = 1, .max = 3},
220 .p2 = { .dot_limit = 270000,
221 .p2_slow = 10,
222 .p2_fast = 10
223 },
224 };
225
226 static const intel_limit_t intel_limits_g4x_hdmi = {
227 .dot = { .min = 22000, .max = 400000 },
228 .vco = { .min = 1750000, .max = 3500000},
229 .n = { .min = 1, .max = 4 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 16, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8},
235 .p2 = { .dot_limit = 165000,
236 .p2_slow = 10, .p2_fast = 5 },
237 };
238
239 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
240 .dot = { .min = 20000, .max = 115000 },
241 .vco = { .min = 1750000, .max = 3500000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 104, .max = 138 },
244 .m1 = { .min = 17, .max = 23 },
245 .m2 = { .min = 5, .max = 11 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 0,
249 .p2_slow = 14, .p2_fast = 14
250 },
251 };
252
253 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
254 .dot = { .min = 80000, .max = 224000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 14, .max = 42 },
261 .p1 = { .min = 2, .max = 6 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 7, .p2_fast = 7
264 },
265 };
266
267 static const intel_limit_t intel_limits_pineview_sdvo = {
268 .dot = { .min = 20000, .max = 400000},
269 .vco = { .min = 1700000, .max = 3500000 },
270 /* Pineview's Ncounter is a ring counter */
271 .n = { .min = 3, .max = 6 },
272 .m = { .min = 2, .max = 256 },
273 /* Pineview only has one combined m divider, which we treat as m2. */
274 .m1 = { .min = 0, .max = 0 },
275 .m2 = { .min = 0, .max = 254 },
276 .p = { .min = 5, .max = 80 },
277 .p1 = { .min = 1, .max = 8 },
278 .p2 = { .dot_limit = 200000,
279 .p2_slow = 10, .p2_fast = 5 },
280 };
281
282 static const intel_limit_t intel_limits_pineview_lvds = {
283 .dot = { .min = 20000, .max = 400000 },
284 .vco = { .min = 1700000, .max = 3500000 },
285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
287 .m1 = { .min = 0, .max = 0 },
288 .m2 = { .min = 0, .max = 254 },
289 .p = { .min = 7, .max = 112 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 112000,
292 .p2_slow = 14, .p2_fast = 14 },
293 };
294
295 /* Ironlake / Sandybridge
296 *
297 * We calculate clock using (register_value + 2) for N/M1/M2, so here
298 * the range value for them is (actual_value - 2).
299 */
300 static const intel_limit_t intel_limits_ironlake_dac = {
301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 5 },
304 .m = { .min = 79, .max = 127 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 5, .max = 80 },
308 .p1 = { .min = 1, .max = 8 },
309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 10, .p2_fast = 5 },
311 };
312
313 static const intel_limit_t intel_limits_ironlake_single_lvds = {
314 .dot = { .min = 25000, .max = 350000 },
315 .vco = { .min = 1760000, .max = 3510000 },
316 .n = { .min = 1, .max = 3 },
317 .m = { .min = 79, .max = 118 },
318 .m1 = { .min = 12, .max = 22 },
319 .m2 = { .min = 5, .max = 9 },
320 .p = { .min = 28, .max = 112 },
321 .p1 = { .min = 2, .max = 8 },
322 .p2 = { .dot_limit = 225000,
323 .p2_slow = 14, .p2_fast = 14 },
324 };
325
326 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
327 .dot = { .min = 25000, .max = 350000 },
328 .vco = { .min = 1760000, .max = 3510000 },
329 .n = { .min = 1, .max = 3 },
330 .m = { .min = 79, .max = 127 },
331 .m1 = { .min = 12, .max = 22 },
332 .m2 = { .min = 5, .max = 9 },
333 .p = { .min = 14, .max = 56 },
334 .p1 = { .min = 2, .max = 8 },
335 .p2 = { .dot_limit = 225000,
336 .p2_slow = 7, .p2_fast = 7 },
337 };
338
339 /* LVDS 100mhz refclk limits. */
340 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 2 },
344 .m = { .min = 79, .max = 126 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 28, .max = 112 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 14, .p2_fast = 14 },
351 };
352
353 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000 },
356 .n = { .min = 1, .max = 3 },
357 .m = { .min = 79, .max = 126 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 14, .max = 42 },
361 .p1 = { .min = 2, .max = 6 },
362 .p2 = { .dot_limit = 225000,
363 .p2_slow = 7, .p2_fast = 7 },
364 };
365
366 static const intel_limit_t intel_limits_vlv = {
367 /*
368 * These are the data rate limits (measured in fast clocks)
369 * since those are the strictest limits we have. The fast
370 * clock and actual rate limits are more relaxed, so checking
371 * them would make no difference.
372 */
373 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
374 .vco = { .min = 4000000, .max = 6000000 },
375 .n = { .min = 1, .max = 7 },
376 .m1 = { .min = 2, .max = 3 },
377 .m2 = { .min = 11, .max = 156 },
378 .p1 = { .min = 2, .max = 3 },
379 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
380 };
381
382 static const intel_limit_t intel_limits_chv = {
383 /*
384 * These are the data rate limits (measured in fast clocks)
385 * since those are the strictest limits we have. The fast
386 * clock and actual rate limits are more relaxed, so checking
387 * them would make no difference.
388 */
389 .dot = { .min = 25000 * 5, .max = 540000 * 5},
390 .vco = { .min = 4860000, .max = 6700000 },
391 .n = { .min = 1, .max = 1 },
392 .m1 = { .min = 2, .max = 2 },
393 .m2 = { .min = 24 << 22, .max = 175 << 22 },
394 .p1 = { .min = 2, .max = 4 },
395 .p2 = { .p2_slow = 1, .p2_fast = 14 },
396 };
397
398 static void vlv_clock(int refclk, intel_clock_t *clock)
399 {
400 clock->m = clock->m1 * clock->m2;
401 clock->p = clock->p1 * clock->p2;
402 if (WARN_ON(clock->n == 0 || clock->p == 0))
403 return;
404 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
405 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
406 }
407
408 /**
409 * Returns whether any output on the specified pipe is of the specified type
410 */
411 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
412 {
413 struct drm_device *dev = crtc->base.dev;
414 struct intel_encoder *encoder;
415
416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
417 if (encoder->type == type)
418 return true;
419
420 return false;
421 }
422
423 /**
424 * Returns whether any output on the specified pipe will have the specified
425 * type after a staged modeset is complete, i.e., the same as
426 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
427 * encoder->crtc.
428 */
429 static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
430 {
431 struct drm_device *dev = crtc->base.dev;
432 struct intel_encoder *encoder;
433
434 for_each_intel_encoder(dev, encoder)
435 if (encoder->new_crtc == crtc && encoder->type == type)
436 return true;
437
438 return false;
439 }
440
441 static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
442 int refclk)
443 {
444 struct drm_device *dev = crtc->base.dev;
445 const intel_limit_t *limit;
446
447 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
448 if (intel_is_dual_link_lvds(dev)) {
449 if (refclk == 100000)
450 limit = &intel_limits_ironlake_dual_lvds_100m;
451 else
452 limit = &intel_limits_ironlake_dual_lvds;
453 } else {
454 if (refclk == 100000)
455 limit = &intel_limits_ironlake_single_lvds_100m;
456 else
457 limit = &intel_limits_ironlake_single_lvds;
458 }
459 } else
460 limit = &intel_limits_ironlake_dac;
461
462 return limit;
463 }
464
465 static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
466 {
467 struct drm_device *dev = crtc->base.dev;
468 const intel_limit_t *limit;
469
470 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
471 if (intel_is_dual_link_lvds(dev))
472 limit = &intel_limits_g4x_dual_channel_lvds;
473 else
474 limit = &intel_limits_g4x_single_channel_lvds;
475 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
476 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
477 limit = &intel_limits_g4x_hdmi;
478 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
479 limit = &intel_limits_g4x_sdvo;
480 } else /* The option is for other outputs */
481 limit = &intel_limits_i9xx_sdvo;
482
483 return limit;
484 }
485
486 static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
487 {
488 struct drm_device *dev = crtc->base.dev;
489 const intel_limit_t *limit;
490
491 if (HAS_PCH_SPLIT(dev))
492 limit = intel_ironlake_limit(crtc, refclk);
493 else if (IS_G4X(dev)) {
494 limit = intel_g4x_limit(crtc);
495 } else if (IS_PINEVIEW(dev)) {
496 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
497 limit = &intel_limits_pineview_lvds;
498 else
499 limit = &intel_limits_pineview_sdvo;
500 } else if (IS_CHERRYVIEW(dev)) {
501 limit = &intel_limits_chv;
502 } else if (IS_VALLEYVIEW(dev)) {
503 limit = &intel_limits_vlv;
504 } else if (!IS_GEN2(dev)) {
505 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
506 limit = &intel_limits_i9xx_lvds;
507 else
508 limit = &intel_limits_i9xx_sdvo;
509 } else {
510 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
511 limit = &intel_limits_i8xx_lvds;
512 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
513 limit = &intel_limits_i8xx_dvo;
514 else
515 limit = &intel_limits_i8xx_dac;
516 }
517 return limit;
518 }
519
520 /* m1 is reserved as 0 in Pineview, n is a ring counter */
521 static void pineview_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = clock->m2 + 2;
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
528 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
529 }
530
531 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
532 {
533 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
534 }
535
536 static void i9xx_clock(int refclk, intel_clock_t *clock)
537 {
538 clock->m = i9xx_dpll_compute_m(clock);
539 clock->p = clock->p1 * clock->p2;
540 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
541 return;
542 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
543 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
544 }
545
546 static void chv_clock(int refclk, intel_clock_t *clock)
547 {
548 clock->m = clock->m1 * clock->m2;
549 clock->p = clock->p1 * clock->p2;
550 if (WARN_ON(clock->n == 0 || clock->p == 0))
551 return;
552 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
553 clock->n << 22);
554 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
555 }
556
557 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
558 /**
559 * Returns whether the given set of divisors are valid for a given refclk with
560 * the given connectors.
561 */
562
563 static bool intel_PLL_is_valid(struct drm_device *dev,
564 const intel_limit_t *limit,
565 const intel_clock_t *clock)
566 {
567 if (clock->n < limit->n.min || limit->n.max < clock->n)
568 INTELPllInvalid("n out of range\n");
569 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
570 INTELPllInvalid("p1 out of range\n");
571 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
572 INTELPllInvalid("m2 out of range\n");
573 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
574 INTELPllInvalid("m1 out of range\n");
575
576 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
577 if (clock->m1 <= clock->m2)
578 INTELPllInvalid("m1 <= m2\n");
579
580 if (!IS_VALLEYVIEW(dev)) {
581 if (clock->p < limit->p.min || limit->p.max < clock->p)
582 INTELPllInvalid("p out of range\n");
583 if (clock->m < limit->m.min || limit->m.max < clock->m)
584 INTELPllInvalid("m out of range\n");
585 }
586
587 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
588 INTELPllInvalid("vco out of range\n");
589 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
590 * connector, etc., rather than just a single range.
591 */
592 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
593 INTELPllInvalid("dot out of range\n");
594
595 return true;
596 }
597
598 static bool
599 i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
600 int target, int refclk, intel_clock_t *match_clock,
601 intel_clock_t *best_clock)
602 {
603 struct drm_device *dev = crtc->base.dev;
604 intel_clock_t clock;
605 int err = target;
606
607 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
608 /*
609 * For LVDS just rely on its current settings for dual-channel.
610 * We haven't figured out how to reliably set up different
611 * single/dual channel state, if we even can.
612 */
613 if (intel_is_dual_link_lvds(dev))
614 clock.p2 = limit->p2.p2_fast;
615 else
616 clock.p2 = limit->p2.p2_slow;
617 } else {
618 if (target < limit->p2.dot_limit)
619 clock.p2 = limit->p2.p2_slow;
620 else
621 clock.p2 = limit->p2.p2_fast;
622 }
623
624 memset(best_clock, 0, sizeof(*best_clock));
625
626 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
627 clock.m1++) {
628 for (clock.m2 = limit->m2.min;
629 clock.m2 <= limit->m2.max; clock.m2++) {
630 if (clock.m2 >= clock.m1)
631 break;
632 for (clock.n = limit->n.min;
633 clock.n <= limit->n.max; clock.n++) {
634 for (clock.p1 = limit->p1.min;
635 clock.p1 <= limit->p1.max; clock.p1++) {
636 int this_err;
637
638 i9xx_clock(refclk, &clock);
639 if (!intel_PLL_is_valid(dev, limit,
640 &clock))
641 continue;
642 if (match_clock &&
643 clock.p != match_clock->p)
644 continue;
645
646 this_err = abs(clock.dot - target);
647 if (this_err < err) {
648 *best_clock = clock;
649 err = this_err;
650 }
651 }
652 }
653 }
654 }
655
656 return (err != target);
657 }
658
659 static bool
660 pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
661 int target, int refclk, intel_clock_t *match_clock,
662 intel_clock_t *best_clock)
663 {
664 struct drm_device *dev = crtc->base.dev;
665 intel_clock_t clock;
666 int err = target;
667
668 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
669 /*
670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
673 */
674 if (intel_is_dual_link_lvds(dev))
675 clock.p2 = limit->p2.p2_fast;
676 else
677 clock.p2 = limit->p2.p2_slow;
678 } else {
679 if (target < limit->p2.dot_limit)
680 clock.p2 = limit->p2.p2_slow;
681 else
682 clock.p2 = limit->p2.p2_fast;
683 }
684
685 memset(best_clock, 0, sizeof(*best_clock));
686
687 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
688 clock.m1++) {
689 for (clock.m2 = limit->m2.min;
690 clock.m2 <= limit->m2.max; clock.m2++) {
691 for (clock.n = limit->n.min;
692 clock.n <= limit->n.max; clock.n++) {
693 for (clock.p1 = limit->p1.min;
694 clock.p1 <= limit->p1.max; clock.p1++) {
695 int this_err;
696
697 pineview_clock(refclk, &clock);
698 if (!intel_PLL_is_valid(dev, limit,
699 &clock))
700 continue;
701 if (match_clock &&
702 clock.p != match_clock->p)
703 continue;
704
705 this_err = abs(clock.dot - target);
706 if (this_err < err) {
707 *best_clock = clock;
708 err = this_err;
709 }
710 }
711 }
712 }
713 }
714
715 return (err != target);
716 }
717
718 static bool
719 g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
720 int target, int refclk, intel_clock_t *match_clock,
721 intel_clock_t *best_clock)
722 {
723 struct drm_device *dev = crtc->base.dev;
724 intel_clock_t clock;
725 int max_n;
726 bool found;
727 /* approximately equals target * 0.00585 */
728 int err_most = (target >> 8) + (target >> 9);
729 found = false;
730
731 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
732 if (intel_is_dual_link_lvds(dev))
733 clock.p2 = limit->p2.p2_fast;
734 else
735 clock.p2 = limit->p2.p2_slow;
736 } else {
737 if (target < limit->p2.dot_limit)
738 clock.p2 = limit->p2.p2_slow;
739 else
740 clock.p2 = limit->p2.p2_fast;
741 }
742
743 memset(best_clock, 0, sizeof(*best_clock));
744 max_n = limit->n.max;
745 /* based on hardware requirement, prefer smaller n to precision */
746 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
747 /* based on hardware requirement, prefere larger m1,m2 */
748 for (clock.m1 = limit->m1.max;
749 clock.m1 >= limit->m1.min; clock.m1--) {
750 for (clock.m2 = limit->m2.max;
751 clock.m2 >= limit->m2.min; clock.m2--) {
752 for (clock.p1 = limit->p1.max;
753 clock.p1 >= limit->p1.min; clock.p1--) {
754 int this_err;
755
756 i9xx_clock(refclk, &clock);
757 if (!intel_PLL_is_valid(dev, limit,
758 &clock))
759 continue;
760
761 this_err = abs(clock.dot - target);
762 if (this_err < err_most) {
763 *best_clock = clock;
764 err_most = this_err;
765 max_n = clock.n;
766 found = true;
767 }
768 }
769 }
770 }
771 }
772 return found;
773 }
774
775 static bool
776 vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
777 int target, int refclk, intel_clock_t *match_clock,
778 intel_clock_t *best_clock)
779 {
780 struct drm_device *dev = crtc->base.dev;
781 intel_clock_t clock;
782 unsigned int bestppm = 1000000;
783 /* min update 19.2 MHz */
784 int max_n = min(limit->n.max, refclk / 19200);
785 bool found = false;
786
787 target *= 5; /* fast clock */
788
789 memset(best_clock, 0, sizeof(*best_clock));
790
791 /* based on hardware requirement, prefer smaller n to precision */
792 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
793 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
794 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
795 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
796 clock.p = clock.p1 * clock.p2;
797 /* based on hardware requirement, prefer bigger m1,m2 values */
798 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
799 unsigned int ppm, diff;
800
801 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
802 refclk * clock.m1);
803
804 vlv_clock(refclk, &clock);
805
806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
808 continue;
809
810 diff = abs(clock.dot - target);
811 ppm = div_u64(1000000ULL * diff, target);
812
813 if (ppm < 100 && clock.p > best_clock->p) {
814 bestppm = 0;
815 *best_clock = clock;
816 found = true;
817 }
818
819 if (bestppm >= 10 && ppm < bestppm - 10) {
820 bestppm = ppm;
821 *best_clock = clock;
822 found = true;
823 }
824 }
825 }
826 }
827 }
828
829 return found;
830 }
831
832 static bool
833 chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
834 int target, int refclk, intel_clock_t *match_clock,
835 intel_clock_t *best_clock)
836 {
837 struct drm_device *dev = crtc->base.dev;
838 intel_clock_t clock;
839 uint64_t m2;
840 int found = false;
841
842 memset(best_clock, 0, sizeof(*best_clock));
843
844 /*
845 * Based on hardware doc, the n always set to 1, and m1 always
846 * set to 2. If requires to support 200Mhz refclk, we need to
847 * revisit this because n may not 1 anymore.
848 */
849 clock.n = 1, clock.m1 = 2;
850 target *= 5; /* fast clock */
851
852 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
853 for (clock.p2 = limit->p2.p2_fast;
854 clock.p2 >= limit->p2.p2_slow;
855 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
856
857 clock.p = clock.p1 * clock.p2;
858
859 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
860 clock.n) << 22, refclk * clock.m1);
861
862 if (m2 > INT_MAX/clock.m1)
863 continue;
864
865 clock.m2 = m2;
866
867 chv_clock(refclk, &clock);
868
869 if (!intel_PLL_is_valid(dev, limit, &clock))
870 continue;
871
872 /* based on hardware requirement, prefer bigger p
873 */
874 if (clock.p > best_clock->p) {
875 *best_clock = clock;
876 found = true;
877 }
878 }
879 }
880
881 return found;
882 }
883
884 bool intel_crtc_active(struct drm_crtc *crtc)
885 {
886 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
887
888 /* Be paranoid as we can arrive here with only partial
889 * state retrieved from the hardware during setup.
890 *
891 * We can ditch the adjusted_mode.crtc_clock check as soon
892 * as Haswell has gained clock readout/fastboot support.
893 *
894 * We can ditch the crtc->primary->fb check as soon as we can
895 * properly reconstruct framebuffers.
896 */
897 return intel_crtc->active && crtc->primary->fb &&
898 intel_crtc->config.adjusted_mode.crtc_clock;
899 }
900
901 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
902 enum pipe pipe)
903 {
904 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906
907 return intel_crtc->config.cpu_transcoder;
908 }
909
910 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
911 {
912 struct drm_i915_private *dev_priv = dev->dev_private;
913 u32 reg = PIPEDSL(pipe);
914 u32 line1, line2;
915 u32 line_mask;
916
917 if (IS_GEN2(dev))
918 line_mask = DSL_LINEMASK_GEN2;
919 else
920 line_mask = DSL_LINEMASK_GEN3;
921
922 line1 = I915_READ(reg) & line_mask;
923 mdelay(5);
924 line2 = I915_READ(reg) & line_mask;
925
926 return line1 == line2;
927 }
928
929 /*
930 * intel_wait_for_pipe_off - wait for pipe to turn off
931 * @crtc: crtc whose pipe to wait for
932 *
933 * After disabling a pipe, we can't wait for vblank in the usual way,
934 * spinning on the vblank interrupt status bit, since we won't actually
935 * see an interrupt when the pipe is disabled.
936 *
937 * On Gen4 and above:
938 * wait for the pipe register state bit to turn off
939 *
940 * Otherwise:
941 * wait for the display line value to settle (it usually
942 * ends up stopping at the start of the next frame).
943 *
944 */
945 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
946 {
947 struct drm_device *dev = crtc->base.dev;
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
950 enum pipe pipe = crtc->pipe;
951
952 if (INTEL_INFO(dev)->gen >= 4) {
953 int reg = PIPECONF(cpu_transcoder);
954
955 /* Wait for the Pipe State to go off */
956 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
957 100))
958 WARN(1, "pipe_off wait timed out\n");
959 } else {
960 /* Wait for the display line to settle */
961 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
962 WARN(1, "pipe_off wait timed out\n");
963 }
964 }
965
966 /*
967 * ibx_digital_port_connected - is the specified port connected?
968 * @dev_priv: i915 private structure
969 * @port: the port to test
970 *
971 * Returns true if @port is connected, false otherwise.
972 */
973 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
974 struct intel_digital_port *port)
975 {
976 u32 bit;
977
978 if (HAS_PCH_IBX(dev_priv->dev)) {
979 switch (port->port) {
980 case PORT_B:
981 bit = SDE_PORTB_HOTPLUG;
982 break;
983 case PORT_C:
984 bit = SDE_PORTC_HOTPLUG;
985 break;
986 case PORT_D:
987 bit = SDE_PORTD_HOTPLUG;
988 break;
989 default:
990 return true;
991 }
992 } else {
993 switch (port->port) {
994 case PORT_B:
995 bit = SDE_PORTB_HOTPLUG_CPT;
996 break;
997 case PORT_C:
998 bit = SDE_PORTC_HOTPLUG_CPT;
999 break;
1000 case PORT_D:
1001 bit = SDE_PORTD_HOTPLUG_CPT;
1002 break;
1003 default:
1004 return true;
1005 }
1006 }
1007
1008 return I915_READ(SDEISR) & bit;
1009 }
1010
1011 static const char *state_string(bool enabled)
1012 {
1013 return enabled ? "on" : "off";
1014 }
1015
1016 /* Only for pre-ILK configs */
1017 void assert_pll(struct drm_i915_private *dev_priv,
1018 enum pipe pipe, bool state)
1019 {
1020 int reg;
1021 u32 val;
1022 bool cur_state;
1023
1024 reg = DPLL(pipe);
1025 val = I915_READ(reg);
1026 cur_state = !!(val & DPLL_VCO_ENABLE);
1027 WARN(cur_state != state,
1028 "PLL state assertion failure (expected %s, current %s)\n",
1029 state_string(state), state_string(cur_state));
1030 }
1031
1032 /* XXX: the dsi pll is shared between MIPI DSI ports */
1033 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1034 {
1035 u32 val;
1036 bool cur_state;
1037
1038 mutex_lock(&dev_priv->dpio_lock);
1039 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1040 mutex_unlock(&dev_priv->dpio_lock);
1041
1042 cur_state = val & DSI_PLL_VCO_EN;
1043 WARN(cur_state != state,
1044 "DSI PLL state assertion failure (expected %s, current %s)\n",
1045 state_string(state), state_string(cur_state));
1046 }
1047 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1048 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1049
1050 struct intel_shared_dpll *
1051 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1052 {
1053 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1054
1055 if (crtc->config.shared_dpll < 0)
1056 return NULL;
1057
1058 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1059 }
1060
1061 /* For ILK+ */
1062 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1063 struct intel_shared_dpll *pll,
1064 bool state)
1065 {
1066 bool cur_state;
1067 struct intel_dpll_hw_state hw_state;
1068
1069 if (WARN (!pll,
1070 "asserting DPLL %s with no DPLL\n", state_string(state)))
1071 return;
1072
1073 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1074 WARN(cur_state != state,
1075 "%s assertion failure (expected %s, current %s)\n",
1076 pll->name, state_string(state), state_string(cur_state));
1077 }
1078
1079 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1080 enum pipe pipe, bool state)
1081 {
1082 int reg;
1083 u32 val;
1084 bool cur_state;
1085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1086 pipe);
1087
1088 if (HAS_DDI(dev_priv->dev)) {
1089 /* DDI does not have a specific FDI_TX register */
1090 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1091 val = I915_READ(reg);
1092 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1093 } else {
1094 reg = FDI_TX_CTL(pipe);
1095 val = I915_READ(reg);
1096 cur_state = !!(val & FDI_TX_ENABLE);
1097 }
1098 WARN(cur_state != state,
1099 "FDI TX state assertion failure (expected %s, current %s)\n",
1100 state_string(state), state_string(cur_state));
1101 }
1102 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1103 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1104
1105 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1106 enum pipe pipe, bool state)
1107 {
1108 int reg;
1109 u32 val;
1110 bool cur_state;
1111
1112 reg = FDI_RX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_RX_ENABLE);
1115 WARN(cur_state != state,
1116 "FDI RX state assertion failure (expected %s, current %s)\n",
1117 state_string(state), state_string(cur_state));
1118 }
1119 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1120 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1121
1122 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1123 enum pipe pipe)
1124 {
1125 int reg;
1126 u32 val;
1127
1128 /* ILK FDI PLL is always enabled */
1129 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1130 return;
1131
1132 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1133 if (HAS_DDI(dev_priv->dev))
1134 return;
1135
1136 reg = FDI_TX_CTL(pipe);
1137 val = I915_READ(reg);
1138 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1139 }
1140
1141 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1142 enum pipe pipe, bool state)
1143 {
1144 int reg;
1145 u32 val;
1146 bool cur_state;
1147
1148 reg = FDI_RX_CTL(pipe);
1149 val = I915_READ(reg);
1150 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1151 WARN(cur_state != state,
1152 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1153 state_string(state), state_string(cur_state));
1154 }
1155
1156 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1157 enum pipe pipe)
1158 {
1159 struct drm_device *dev = dev_priv->dev;
1160 int pp_reg;
1161 u32 val;
1162 enum pipe panel_pipe = PIPE_A;
1163 bool locked = true;
1164
1165 if (WARN_ON(HAS_DDI(dev)))
1166 return;
1167
1168 if (HAS_PCH_SPLIT(dev)) {
1169 u32 port_sel;
1170
1171 pp_reg = PCH_PP_CONTROL;
1172 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1173
1174 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1175 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1176 panel_pipe = PIPE_B;
1177 /* XXX: else fix for eDP */
1178 } else if (IS_VALLEYVIEW(dev)) {
1179 /* presumably write lock depends on pipe, not port select */
1180 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1181 panel_pipe = pipe;
1182 } else {
1183 pp_reg = PP_CONTROL;
1184 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1185 panel_pipe = PIPE_B;
1186 }
1187
1188 val = I915_READ(pp_reg);
1189 if (!(val & PANEL_POWER_ON) ||
1190 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1191 locked = false;
1192
1193 WARN(panel_pipe == pipe && locked,
1194 "panel assertion failure, pipe %c regs locked\n",
1195 pipe_name(pipe));
1196 }
1197
1198 static void assert_cursor(struct drm_i915_private *dev_priv,
1199 enum pipe pipe, bool state)
1200 {
1201 struct drm_device *dev = dev_priv->dev;
1202 bool cur_state;
1203
1204 if (IS_845G(dev) || IS_I865G(dev))
1205 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1206 else
1207 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1208
1209 WARN(cur_state != state,
1210 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1211 pipe_name(pipe), state_string(state), state_string(cur_state));
1212 }
1213 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1214 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1215
1216 void assert_pipe(struct drm_i915_private *dev_priv,
1217 enum pipe pipe, bool state)
1218 {
1219 int reg;
1220 u32 val;
1221 bool cur_state;
1222 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1223 pipe);
1224
1225 /* if we need the pipe quirk it must be always on */
1226 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1227 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1228 state = true;
1229
1230 if (!intel_display_power_is_enabled(dev_priv,
1231 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1232 cur_state = false;
1233 } else {
1234 reg = PIPECONF(cpu_transcoder);
1235 val = I915_READ(reg);
1236 cur_state = !!(val & PIPECONF_ENABLE);
1237 }
1238
1239 WARN(cur_state != state,
1240 "pipe %c assertion failure (expected %s, current %s)\n",
1241 pipe_name(pipe), state_string(state), state_string(cur_state));
1242 }
1243
1244 static void assert_plane(struct drm_i915_private *dev_priv,
1245 enum plane plane, bool state)
1246 {
1247 int reg;
1248 u32 val;
1249 bool cur_state;
1250
1251 reg = DSPCNTR(plane);
1252 val = I915_READ(reg);
1253 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1254 WARN(cur_state != state,
1255 "plane %c assertion failure (expected %s, current %s)\n",
1256 plane_name(plane), state_string(state), state_string(cur_state));
1257 }
1258
1259 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1260 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1261
1262 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe)
1264 {
1265 struct drm_device *dev = dev_priv->dev;
1266 int reg, i;
1267 u32 val;
1268 int cur_pipe;
1269
1270 /* Primary planes are fixed to pipes on gen4+ */
1271 if (INTEL_INFO(dev)->gen >= 4) {
1272 reg = DSPCNTR(pipe);
1273 val = I915_READ(reg);
1274 WARN(val & DISPLAY_PLANE_ENABLE,
1275 "plane %c assertion failure, should be disabled but not\n",
1276 plane_name(pipe));
1277 return;
1278 }
1279
1280 /* Need to check both planes against the pipe */
1281 for_each_pipe(dev_priv, i) {
1282 reg = DSPCNTR(i);
1283 val = I915_READ(reg);
1284 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1285 DISPPLANE_SEL_PIPE_SHIFT;
1286 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1287 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1288 plane_name(i), pipe_name(pipe));
1289 }
1290 }
1291
1292 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1293 enum pipe pipe)
1294 {
1295 struct drm_device *dev = dev_priv->dev;
1296 int reg, sprite;
1297 u32 val;
1298
1299 if (INTEL_INFO(dev)->gen >= 9) {
1300 for_each_sprite(pipe, sprite) {
1301 val = I915_READ(PLANE_CTL(pipe, sprite));
1302 WARN(val & PLANE_CTL_ENABLE,
1303 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1304 sprite, pipe_name(pipe));
1305 }
1306 } else if (IS_VALLEYVIEW(dev)) {
1307 for_each_sprite(pipe, sprite) {
1308 reg = SPCNTR(pipe, sprite);
1309 val = I915_READ(reg);
1310 WARN(val & SP_ENABLE,
1311 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1312 sprite_name(pipe, sprite), pipe_name(pipe));
1313 }
1314 } else if (INTEL_INFO(dev)->gen >= 7) {
1315 reg = SPRCTL(pipe);
1316 val = I915_READ(reg);
1317 WARN(val & SPRITE_ENABLE,
1318 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1319 plane_name(pipe), pipe_name(pipe));
1320 } else if (INTEL_INFO(dev)->gen >= 5) {
1321 reg = DVSCNTR(pipe);
1322 val = I915_READ(reg);
1323 WARN(val & DVS_ENABLE,
1324 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1325 plane_name(pipe), pipe_name(pipe));
1326 }
1327 }
1328
1329 static void assert_vblank_disabled(struct drm_crtc *crtc)
1330 {
1331 if (WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1332 drm_crtc_vblank_put(crtc);
1333 }
1334
1335 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1336 {
1337 u32 val;
1338 bool enabled;
1339
1340 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1341
1342 val = I915_READ(PCH_DREF_CONTROL);
1343 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1344 DREF_SUPERSPREAD_SOURCE_MASK));
1345 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1346 }
1347
1348 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1349 enum pipe pipe)
1350 {
1351 int reg;
1352 u32 val;
1353 bool enabled;
1354
1355 reg = PCH_TRANSCONF(pipe);
1356 val = I915_READ(reg);
1357 enabled = !!(val & TRANS_ENABLE);
1358 WARN(enabled,
1359 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1360 pipe_name(pipe));
1361 }
1362
1363 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 port_sel, u32 val)
1365 {
1366 if ((val & DP_PORT_EN) == 0)
1367 return false;
1368
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1371 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1372 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1373 return false;
1374 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1375 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1376 return false;
1377 } else {
1378 if ((val & DP_PIPE_MASK) != (pipe << 30))
1379 return false;
1380 }
1381 return true;
1382 }
1383
1384 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1385 enum pipe pipe, u32 val)
1386 {
1387 if ((val & SDVO_ENABLE) == 0)
1388 return false;
1389
1390 if (HAS_PCH_CPT(dev_priv->dev)) {
1391 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1392 return false;
1393 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1394 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1395 return false;
1396 } else {
1397 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1398 return false;
1399 }
1400 return true;
1401 }
1402
1403 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1404 enum pipe pipe, u32 val)
1405 {
1406 if ((val & LVDS_PORT_EN) == 0)
1407 return false;
1408
1409 if (HAS_PCH_CPT(dev_priv->dev)) {
1410 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1411 return false;
1412 } else {
1413 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1414 return false;
1415 }
1416 return true;
1417 }
1418
1419 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1420 enum pipe pipe, u32 val)
1421 {
1422 if ((val & ADPA_DAC_ENABLE) == 0)
1423 return false;
1424 if (HAS_PCH_CPT(dev_priv->dev)) {
1425 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1426 return false;
1427 } else {
1428 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1429 return false;
1430 }
1431 return true;
1432 }
1433
1434 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1435 enum pipe pipe, int reg, u32 port_sel)
1436 {
1437 u32 val = I915_READ(reg);
1438 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1439 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1440 reg, pipe_name(pipe));
1441
1442 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1443 && (val & DP_PIPEB_SELECT),
1444 "IBX PCH dp port still using transcoder B\n");
1445 }
1446
1447 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1448 enum pipe pipe, int reg)
1449 {
1450 u32 val = I915_READ(reg);
1451 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1452 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1453 reg, pipe_name(pipe));
1454
1455 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1456 && (val & SDVO_PIPE_B_SELECT),
1457 "IBX PCH hdmi port still using transcoder B\n");
1458 }
1459
1460 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1461 enum pipe pipe)
1462 {
1463 int reg;
1464 u32 val;
1465
1466 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1467 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1468 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1469
1470 reg = PCH_ADPA;
1471 val = I915_READ(reg);
1472 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1473 "PCH VGA enabled on transcoder %c, should be disabled\n",
1474 pipe_name(pipe));
1475
1476 reg = PCH_LVDS;
1477 val = I915_READ(reg);
1478 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1479 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1480 pipe_name(pipe));
1481
1482 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1483 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1484 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1485 }
1486
1487 static void intel_init_dpio(struct drm_device *dev)
1488 {
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490
1491 if (!IS_VALLEYVIEW(dev))
1492 return;
1493
1494 /*
1495 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1496 * CHV x1 PHY (DP/HDMI D)
1497 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1498 */
1499 if (IS_CHERRYVIEW(dev)) {
1500 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1501 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1502 } else {
1503 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1504 }
1505 }
1506
1507 static void vlv_enable_pll(struct intel_crtc *crtc,
1508 const struct intel_crtc_config *pipe_config)
1509 {
1510 struct drm_device *dev = crtc->base.dev;
1511 struct drm_i915_private *dev_priv = dev->dev_private;
1512 int reg = DPLL(crtc->pipe);
1513 u32 dpll = pipe_config->dpll_hw_state.dpll;
1514
1515 assert_pipe_disabled(dev_priv, crtc->pipe);
1516
1517 /* No really, not for ILK+ */
1518 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1519
1520 /* PLL is protected by panel, make sure we can write it */
1521 if (IS_MOBILE(dev_priv->dev))
1522 assert_panel_unlocked(dev_priv, crtc->pipe);
1523
1524 I915_WRITE(reg, dpll);
1525 POSTING_READ(reg);
1526 udelay(150);
1527
1528 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1529 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1530
1531 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1532 POSTING_READ(DPLL_MD(crtc->pipe));
1533
1534 /* We do this three times for luck */
1535 I915_WRITE(reg, dpll);
1536 POSTING_READ(reg);
1537 udelay(150); /* wait for warmup */
1538 I915_WRITE(reg, dpll);
1539 POSTING_READ(reg);
1540 udelay(150); /* wait for warmup */
1541 I915_WRITE(reg, dpll);
1542 POSTING_READ(reg);
1543 udelay(150); /* wait for warmup */
1544 }
1545
1546 static void chv_enable_pll(struct intel_crtc *crtc,
1547 const struct intel_crtc_config *pipe_config)
1548 {
1549 struct drm_device *dev = crtc->base.dev;
1550 struct drm_i915_private *dev_priv = dev->dev_private;
1551 int pipe = crtc->pipe;
1552 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1553 u32 tmp;
1554
1555 assert_pipe_disabled(dev_priv, crtc->pipe);
1556
1557 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1558
1559 mutex_lock(&dev_priv->dpio_lock);
1560
1561 /* Enable back the 10bit clock to display controller */
1562 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1563 tmp |= DPIO_DCLKP_EN;
1564 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1565
1566 /*
1567 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1568 */
1569 udelay(1);
1570
1571 /* Enable PLL */
1572 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1573
1574 /* Check PLL is locked */
1575 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("PLL %d failed to lock\n", pipe);
1577
1578 /* not sure when this should be written */
1579 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1580 POSTING_READ(DPLL_MD(pipe));
1581
1582 mutex_unlock(&dev_priv->dpio_lock);
1583 }
1584
1585 static int intel_num_dvo_pipes(struct drm_device *dev)
1586 {
1587 struct intel_crtc *crtc;
1588 int count = 0;
1589
1590 for_each_intel_crtc(dev, crtc)
1591 count += crtc->active &&
1592 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1593
1594 return count;
1595 }
1596
1597 static void i9xx_enable_pll(struct intel_crtc *crtc)
1598 {
1599 struct drm_device *dev = crtc->base.dev;
1600 struct drm_i915_private *dev_priv = dev->dev_private;
1601 int reg = DPLL(crtc->pipe);
1602 u32 dpll = crtc->config.dpll_hw_state.dpll;
1603
1604 assert_pipe_disabled(dev_priv, crtc->pipe);
1605
1606 /* No really, not for ILK+ */
1607 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1608
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev) && !IS_I830(dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613 /* Enable DVO 2x clock on both PLLs if necessary */
1614 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1615 /*
1616 * It appears to be important that we don't enable this
1617 * for the current pipe before otherwise configuring the
1618 * PLL. No idea how this should be handled if multiple
1619 * DVO outputs are enabled simultaneosly.
1620 */
1621 dpll |= DPLL_DVO_2X_MODE;
1622 I915_WRITE(DPLL(!crtc->pipe),
1623 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1624 }
1625
1626 /* Wait for the clocks to stabilize. */
1627 POSTING_READ(reg);
1628 udelay(150);
1629
1630 if (INTEL_INFO(dev)->gen >= 4) {
1631 I915_WRITE(DPLL_MD(crtc->pipe),
1632 crtc->config.dpll_hw_state.dpll_md);
1633 } else {
1634 /* The pixel multiplier can only be updated once the
1635 * DPLL is enabled and the clocks are stable.
1636 *
1637 * So write it again.
1638 */
1639 I915_WRITE(reg, dpll);
1640 }
1641
1642 /* We do this three times for luck */
1643 I915_WRITE(reg, dpll);
1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
1646 I915_WRITE(reg, dpll);
1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649 I915_WRITE(reg, dpll);
1650 POSTING_READ(reg);
1651 udelay(150); /* wait for warmup */
1652 }
1653
1654 /**
1655 * i9xx_disable_pll - disable a PLL
1656 * @dev_priv: i915 private structure
1657 * @pipe: pipe PLL to disable
1658 *
1659 * Disable the PLL for @pipe, making sure the pipe is off first.
1660 *
1661 * Note! This is for pre-ILK only.
1662 */
1663 static void i9xx_disable_pll(struct intel_crtc *crtc)
1664 {
1665 struct drm_device *dev = crtc->base.dev;
1666 struct drm_i915_private *dev_priv = dev->dev_private;
1667 enum pipe pipe = crtc->pipe;
1668
1669 /* Disable DVO 2x clock on both PLLs if necessary */
1670 if (IS_I830(dev) &&
1671 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1672 intel_num_dvo_pipes(dev) == 1) {
1673 I915_WRITE(DPLL(PIPE_B),
1674 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1675 I915_WRITE(DPLL(PIPE_A),
1676 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1677 }
1678
1679 /* Don't disable pipe or pipe PLLs if needed */
1680 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1681 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1682 return;
1683
1684 /* Make sure the pipe isn't still relying on us */
1685 assert_pipe_disabled(dev_priv, pipe);
1686
1687 I915_WRITE(DPLL(pipe), 0);
1688 POSTING_READ(DPLL(pipe));
1689 }
1690
1691 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1692 {
1693 u32 val = 0;
1694
1695 /* Make sure the pipe isn't still relying on us */
1696 assert_pipe_disabled(dev_priv, pipe);
1697
1698 /*
1699 * Leave integrated clock source and reference clock enabled for pipe B.
1700 * The latter is needed for VGA hotplug / manual detection.
1701 */
1702 if (pipe == PIPE_B)
1703 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1704 I915_WRITE(DPLL(pipe), val);
1705 POSTING_READ(DPLL(pipe));
1706
1707 }
1708
1709 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1710 {
1711 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1712 u32 val;
1713
1714 /* Make sure the pipe isn't still relying on us */
1715 assert_pipe_disabled(dev_priv, pipe);
1716
1717 /* Set PLL en = 0 */
1718 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
1719 if (pipe != PIPE_A)
1720 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1721 I915_WRITE(DPLL(pipe), val);
1722 POSTING_READ(DPLL(pipe));
1723
1724 mutex_lock(&dev_priv->dpio_lock);
1725
1726 /* Disable 10bit clock to display controller */
1727 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1728 val &= ~DPIO_DCLKP_EN;
1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1730
1731 /* disable left/right clock distribution */
1732 if (pipe != PIPE_B) {
1733 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1734 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1735 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1736 } else {
1737 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1738 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1739 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1740 }
1741
1742 mutex_unlock(&dev_priv->dpio_lock);
1743 }
1744
1745 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1746 struct intel_digital_port *dport)
1747 {
1748 u32 port_mask;
1749 int dpll_reg;
1750
1751 switch (dport->port) {
1752 case PORT_B:
1753 port_mask = DPLL_PORTB_READY_MASK;
1754 dpll_reg = DPLL(0);
1755 break;
1756 case PORT_C:
1757 port_mask = DPLL_PORTC_READY_MASK;
1758 dpll_reg = DPLL(0);
1759 break;
1760 case PORT_D:
1761 port_mask = DPLL_PORTD_READY_MASK;
1762 dpll_reg = DPIO_PHY_STATUS;
1763 break;
1764 default:
1765 BUG();
1766 }
1767
1768 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1769 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1770 port_name(dport->port), I915_READ(dpll_reg));
1771 }
1772
1773 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1774 {
1775 struct drm_device *dev = crtc->base.dev;
1776 struct drm_i915_private *dev_priv = dev->dev_private;
1777 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1778
1779 if (WARN_ON(pll == NULL))
1780 return;
1781
1782 WARN_ON(!pll->config.crtc_mask);
1783 if (pll->active == 0) {
1784 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1785 WARN_ON(pll->on);
1786 assert_shared_dpll_disabled(dev_priv, pll);
1787
1788 pll->mode_set(dev_priv, pll);
1789 }
1790 }
1791
1792 /**
1793 * intel_enable_shared_dpll - enable PCH PLL
1794 * @dev_priv: i915 private structure
1795 * @pipe: pipe PLL to enable
1796 *
1797 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1798 * drives the transcoder clock.
1799 */
1800 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1801 {
1802 struct drm_device *dev = crtc->base.dev;
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1804 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1805
1806 if (WARN_ON(pll == NULL))
1807 return;
1808
1809 if (WARN_ON(pll->config.crtc_mask == 0))
1810 return;
1811
1812 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1813 pll->name, pll->active, pll->on,
1814 crtc->base.base.id);
1815
1816 if (pll->active++) {
1817 WARN_ON(!pll->on);
1818 assert_shared_dpll_enabled(dev_priv, pll);
1819 return;
1820 }
1821 WARN_ON(pll->on);
1822
1823 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1824
1825 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1826 pll->enable(dev_priv, pll);
1827 pll->on = true;
1828 }
1829
1830 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1831 {
1832 struct drm_device *dev = crtc->base.dev;
1833 struct drm_i915_private *dev_priv = dev->dev_private;
1834 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1835
1836 /* PCH only available on ILK+ */
1837 BUG_ON(INTEL_INFO(dev)->gen < 5);
1838 if (WARN_ON(pll == NULL))
1839 return;
1840
1841 if (WARN_ON(pll->config.crtc_mask == 0))
1842 return;
1843
1844 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1845 pll->name, pll->active, pll->on,
1846 crtc->base.base.id);
1847
1848 if (WARN_ON(pll->active == 0)) {
1849 assert_shared_dpll_disabled(dev_priv, pll);
1850 return;
1851 }
1852
1853 assert_shared_dpll_enabled(dev_priv, pll);
1854 WARN_ON(!pll->on);
1855 if (--pll->active)
1856 return;
1857
1858 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1859 pll->disable(dev_priv, pll);
1860 pll->on = false;
1861
1862 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1863 }
1864
1865 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1866 enum pipe pipe)
1867 {
1868 struct drm_device *dev = dev_priv->dev;
1869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1871 uint32_t reg, val, pipeconf_val;
1872
1873 /* PCH only available on ILK+ */
1874 BUG_ON(!HAS_PCH_SPLIT(dev));
1875
1876 /* Make sure PCH DPLL is enabled */
1877 assert_shared_dpll_enabled(dev_priv,
1878 intel_crtc_to_shared_dpll(intel_crtc));
1879
1880 /* FDI must be feeding us bits for PCH ports */
1881 assert_fdi_tx_enabled(dev_priv, pipe);
1882 assert_fdi_rx_enabled(dev_priv, pipe);
1883
1884 if (HAS_PCH_CPT(dev)) {
1885 /* Workaround: Set the timing override bit before enabling the
1886 * pch transcoder. */
1887 reg = TRANS_CHICKEN2(pipe);
1888 val = I915_READ(reg);
1889 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1890 I915_WRITE(reg, val);
1891 }
1892
1893 reg = PCH_TRANSCONF(pipe);
1894 val = I915_READ(reg);
1895 pipeconf_val = I915_READ(PIPECONF(pipe));
1896
1897 if (HAS_PCH_IBX(dev_priv->dev)) {
1898 /*
1899 * make the BPC in transcoder be consistent with
1900 * that in pipeconf reg.
1901 */
1902 val &= ~PIPECONF_BPC_MASK;
1903 val |= pipeconf_val & PIPECONF_BPC_MASK;
1904 }
1905
1906 val &= ~TRANS_INTERLACE_MASK;
1907 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1908 if (HAS_PCH_IBX(dev_priv->dev) &&
1909 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
1910 val |= TRANS_LEGACY_INTERLACED_ILK;
1911 else
1912 val |= TRANS_INTERLACED;
1913 else
1914 val |= TRANS_PROGRESSIVE;
1915
1916 I915_WRITE(reg, val | TRANS_ENABLE);
1917 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1918 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1919 }
1920
1921 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1922 enum transcoder cpu_transcoder)
1923 {
1924 u32 val, pipeconf_val;
1925
1926 /* PCH only available on ILK+ */
1927 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
1928
1929 /* FDI must be feeding us bits for PCH ports */
1930 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1931 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1932
1933 /* Workaround: set timing override bit. */
1934 val = I915_READ(_TRANSA_CHICKEN2);
1935 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1936 I915_WRITE(_TRANSA_CHICKEN2, val);
1937
1938 val = TRANS_ENABLE;
1939 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1940
1941 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1942 PIPECONF_INTERLACED_ILK)
1943 val |= TRANS_INTERLACED;
1944 else
1945 val |= TRANS_PROGRESSIVE;
1946
1947 I915_WRITE(LPT_TRANSCONF, val);
1948 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1949 DRM_ERROR("Failed to enable PCH transcoder\n");
1950 }
1951
1952 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1953 enum pipe pipe)
1954 {
1955 struct drm_device *dev = dev_priv->dev;
1956 uint32_t reg, val;
1957
1958 /* FDI relies on the transcoder */
1959 assert_fdi_tx_disabled(dev_priv, pipe);
1960 assert_fdi_rx_disabled(dev_priv, pipe);
1961
1962 /* Ports must be off as well */
1963 assert_pch_ports_disabled(dev_priv, pipe);
1964
1965 reg = PCH_TRANSCONF(pipe);
1966 val = I915_READ(reg);
1967 val &= ~TRANS_ENABLE;
1968 I915_WRITE(reg, val);
1969 /* wait for PCH transcoder off, transcoder state */
1970 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1971 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1972
1973 if (!HAS_PCH_IBX(dev)) {
1974 /* Workaround: Clear the timing override chicken bit again. */
1975 reg = TRANS_CHICKEN2(pipe);
1976 val = I915_READ(reg);
1977 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1978 I915_WRITE(reg, val);
1979 }
1980 }
1981
1982 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1983 {
1984 u32 val;
1985
1986 val = I915_READ(LPT_TRANSCONF);
1987 val &= ~TRANS_ENABLE;
1988 I915_WRITE(LPT_TRANSCONF, val);
1989 /* wait for PCH transcoder off, transcoder state */
1990 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1991 DRM_ERROR("Failed to disable PCH transcoder\n");
1992
1993 /* Workaround: clear timing override bit. */
1994 val = I915_READ(_TRANSA_CHICKEN2);
1995 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1996 I915_WRITE(_TRANSA_CHICKEN2, val);
1997 }
1998
1999 /**
2000 * intel_enable_pipe - enable a pipe, asserting requirements
2001 * @crtc: crtc responsible for the pipe
2002 *
2003 * Enable @crtc's pipe, making sure that various hardware specific requirements
2004 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2005 */
2006 static void intel_enable_pipe(struct intel_crtc *crtc)
2007 {
2008 struct drm_device *dev = crtc->base.dev;
2009 struct drm_i915_private *dev_priv = dev->dev_private;
2010 enum pipe pipe = crtc->pipe;
2011 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2012 pipe);
2013 enum pipe pch_transcoder;
2014 int reg;
2015 u32 val;
2016
2017 assert_planes_disabled(dev_priv, pipe);
2018 assert_cursor_disabled(dev_priv, pipe);
2019 assert_sprites_disabled(dev_priv, pipe);
2020
2021 if (HAS_PCH_LPT(dev_priv->dev))
2022 pch_transcoder = TRANSCODER_A;
2023 else
2024 pch_transcoder = pipe;
2025
2026 /*
2027 * A pipe without a PLL won't actually be able to drive bits from
2028 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2029 * need the check.
2030 */
2031 if (!HAS_PCH_SPLIT(dev_priv->dev))
2032 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
2033 assert_dsi_pll_enabled(dev_priv);
2034 else
2035 assert_pll_enabled(dev_priv, pipe);
2036 else {
2037 if (crtc->config.has_pch_encoder) {
2038 /* if driving the PCH, we need FDI enabled */
2039 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2040 assert_fdi_tx_pll_enabled(dev_priv,
2041 (enum pipe) cpu_transcoder);
2042 }
2043 /* FIXME: assert CPU port conditions for SNB+ */
2044 }
2045
2046 reg = PIPECONF(cpu_transcoder);
2047 val = I915_READ(reg);
2048 if (val & PIPECONF_ENABLE) {
2049 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2050 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2051 return;
2052 }
2053
2054 I915_WRITE(reg, val | PIPECONF_ENABLE);
2055 POSTING_READ(reg);
2056 }
2057
2058 /**
2059 * intel_disable_pipe - disable a pipe, asserting requirements
2060 * @crtc: crtc whose pipes is to be disabled
2061 *
2062 * Disable the pipe of @crtc, making sure that various hardware
2063 * specific requirements are met, if applicable, e.g. plane
2064 * disabled, panel fitter off, etc.
2065 *
2066 * Will wait until the pipe has shut down before returning.
2067 */
2068 static void intel_disable_pipe(struct intel_crtc *crtc)
2069 {
2070 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2071 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2072 enum pipe pipe = crtc->pipe;
2073 int reg;
2074 u32 val;
2075
2076 /*
2077 * Make sure planes won't keep trying to pump pixels to us,
2078 * or we might hang the display.
2079 */
2080 assert_planes_disabled(dev_priv, pipe);
2081 assert_cursor_disabled(dev_priv, pipe);
2082 assert_sprites_disabled(dev_priv, pipe);
2083
2084 reg = PIPECONF(cpu_transcoder);
2085 val = I915_READ(reg);
2086 if ((val & PIPECONF_ENABLE) == 0)
2087 return;
2088
2089 /*
2090 * Double wide has implications for planes
2091 * so best keep it disabled when not needed.
2092 */
2093 if (crtc->config.double_wide)
2094 val &= ~PIPECONF_DOUBLE_WIDE;
2095
2096 /* Don't disable pipe or pipe PLLs if needed */
2097 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2098 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2099 val &= ~PIPECONF_ENABLE;
2100
2101 I915_WRITE(reg, val);
2102 if ((val & PIPECONF_ENABLE) == 0)
2103 intel_wait_for_pipe_off(crtc);
2104 }
2105
2106 /*
2107 * Plane regs are double buffered, going from enabled->disabled needs a
2108 * trigger in order to latch. The display address reg provides this.
2109 */
2110 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2111 enum plane plane)
2112 {
2113 struct drm_device *dev = dev_priv->dev;
2114 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2115
2116 I915_WRITE(reg, I915_READ(reg));
2117 POSTING_READ(reg);
2118 }
2119
2120 /**
2121 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2122 * @plane: plane to be enabled
2123 * @crtc: crtc for the plane
2124 *
2125 * Enable @plane on @crtc, making sure that the pipe is running first.
2126 */
2127 static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2128 struct drm_crtc *crtc)
2129 {
2130 struct drm_device *dev = plane->dev;
2131 struct drm_i915_private *dev_priv = dev->dev_private;
2132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2133
2134 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2135 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2136
2137 if (intel_crtc->primary_enabled)
2138 return;
2139
2140 intel_crtc->primary_enabled = true;
2141
2142 dev_priv->display.update_primary_plane(crtc, plane->fb,
2143 crtc->x, crtc->y);
2144
2145 /*
2146 * BDW signals flip done immediately if the plane
2147 * is disabled, even if the plane enable is already
2148 * armed to occur at the next vblank :(
2149 */
2150 if (IS_BROADWELL(dev))
2151 intel_wait_for_vblank(dev, intel_crtc->pipe);
2152 }
2153
2154 /**
2155 * intel_disable_primary_hw_plane - disable the primary hardware plane
2156 * @plane: plane to be disabled
2157 * @crtc: crtc for the plane
2158 *
2159 * Disable @plane on @crtc, making sure that the pipe is running first.
2160 */
2161 static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2162 struct drm_crtc *crtc)
2163 {
2164 struct drm_device *dev = plane->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
2166 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2167
2168 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
2169
2170 if (!intel_crtc->primary_enabled)
2171 return;
2172
2173 intel_crtc->primary_enabled = false;
2174
2175 dev_priv->display.update_primary_plane(crtc, plane->fb,
2176 crtc->x, crtc->y);
2177 }
2178
2179 static bool need_vtd_wa(struct drm_device *dev)
2180 {
2181 #ifdef CONFIG_INTEL_IOMMU
2182 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2183 return true;
2184 #endif
2185 return false;
2186 }
2187
2188 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2189 {
2190 int tile_height;
2191
2192 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2193 return ALIGN(height, tile_height);
2194 }
2195
2196 int
2197 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2198 struct drm_framebuffer *fb,
2199 struct intel_engine_cs *pipelined)
2200 {
2201 struct drm_device *dev = fb->dev;
2202 struct drm_i915_private *dev_priv = dev->dev_private;
2203 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2204 u32 alignment;
2205 int ret;
2206
2207 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2208
2209 switch (obj->tiling_mode) {
2210 case I915_TILING_NONE:
2211 if (INTEL_INFO(dev)->gen >= 9)
2212 alignment = 256 * 1024;
2213 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2214 alignment = 128 * 1024;
2215 else if (INTEL_INFO(dev)->gen >= 4)
2216 alignment = 4 * 1024;
2217 else
2218 alignment = 64 * 1024;
2219 break;
2220 case I915_TILING_X:
2221 if (INTEL_INFO(dev)->gen >= 9)
2222 alignment = 256 * 1024;
2223 else {
2224 /* pin() will align the object as required by fence */
2225 alignment = 0;
2226 }
2227 break;
2228 case I915_TILING_Y:
2229 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2230 return -EINVAL;
2231 default:
2232 BUG();
2233 }
2234
2235 /* Note that the w/a also requires 64 PTE of padding following the
2236 * bo. We currently fill all unused PTE with the shadow page and so
2237 * we should always have valid PTE following the scanout preventing
2238 * the VT-d warning.
2239 */
2240 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2241 alignment = 256 * 1024;
2242
2243 /*
2244 * Global gtt pte registers are special registers which actually forward
2245 * writes to a chunk of system memory. Which means that there is no risk
2246 * that the register values disappear as soon as we call
2247 * intel_runtime_pm_put(), so it is correct to wrap only the
2248 * pin/unpin/fence and not more.
2249 */
2250 intel_runtime_pm_get(dev_priv);
2251
2252 dev_priv->mm.interruptible = false;
2253 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2254 if (ret)
2255 goto err_interruptible;
2256
2257 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2258 * fence, whereas 965+ only requires a fence if using
2259 * framebuffer compression. For simplicity, we always install
2260 * a fence as the cost is not that onerous.
2261 */
2262 ret = i915_gem_object_get_fence(obj);
2263 if (ret)
2264 goto err_unpin;
2265
2266 i915_gem_object_pin_fence(obj);
2267
2268 dev_priv->mm.interruptible = true;
2269 intel_runtime_pm_put(dev_priv);
2270 return 0;
2271
2272 err_unpin:
2273 i915_gem_object_unpin_from_display_plane(obj);
2274 err_interruptible:
2275 dev_priv->mm.interruptible = true;
2276 intel_runtime_pm_put(dev_priv);
2277 return ret;
2278 }
2279
2280 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2281 {
2282 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2283
2284 i915_gem_object_unpin_fence(obj);
2285 i915_gem_object_unpin_from_display_plane(obj);
2286 }
2287
2288 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2289 * is assumed to be a power-of-two. */
2290 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2291 unsigned int tiling_mode,
2292 unsigned int cpp,
2293 unsigned int pitch)
2294 {
2295 if (tiling_mode != I915_TILING_NONE) {
2296 unsigned int tile_rows, tiles;
2297
2298 tile_rows = *y / 8;
2299 *y %= 8;
2300
2301 tiles = *x / (512/cpp);
2302 *x %= 512/cpp;
2303
2304 return tile_rows * pitch * 8 + tiles * 4096;
2305 } else {
2306 unsigned int offset;
2307
2308 offset = *y * pitch + *x * cpp;
2309 *y = 0;
2310 *x = (offset & 4095) / cpp;
2311 return offset & -4096;
2312 }
2313 }
2314
2315 int intel_format_to_fourcc(int format)
2316 {
2317 switch (format) {
2318 case DISPPLANE_8BPP:
2319 return DRM_FORMAT_C8;
2320 case DISPPLANE_BGRX555:
2321 return DRM_FORMAT_XRGB1555;
2322 case DISPPLANE_BGRX565:
2323 return DRM_FORMAT_RGB565;
2324 default:
2325 case DISPPLANE_BGRX888:
2326 return DRM_FORMAT_XRGB8888;
2327 case DISPPLANE_RGBX888:
2328 return DRM_FORMAT_XBGR8888;
2329 case DISPPLANE_BGRX101010:
2330 return DRM_FORMAT_XRGB2101010;
2331 case DISPPLANE_RGBX101010:
2332 return DRM_FORMAT_XBGR2101010;
2333 }
2334 }
2335
2336 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2337 struct intel_plane_config *plane_config)
2338 {
2339 struct drm_device *dev = crtc->base.dev;
2340 struct drm_i915_gem_object *obj = NULL;
2341 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2342 u32 base = plane_config->base;
2343
2344 if (plane_config->size == 0)
2345 return false;
2346
2347 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2348 plane_config->size);
2349 if (!obj)
2350 return false;
2351
2352 if (plane_config->tiled) {
2353 obj->tiling_mode = I915_TILING_X;
2354 obj->stride = crtc->base.primary->fb->pitches[0];
2355 }
2356
2357 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2358 mode_cmd.width = crtc->base.primary->fb->width;
2359 mode_cmd.height = crtc->base.primary->fb->height;
2360 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2361
2362 mutex_lock(&dev->struct_mutex);
2363
2364 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2365 &mode_cmd, obj)) {
2366 DRM_DEBUG_KMS("intel fb init failed\n");
2367 goto out_unref_obj;
2368 }
2369
2370 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
2371 mutex_unlock(&dev->struct_mutex);
2372
2373 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2374 return true;
2375
2376 out_unref_obj:
2377 drm_gem_object_unreference(&obj->base);
2378 mutex_unlock(&dev->struct_mutex);
2379 return false;
2380 }
2381
2382 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2383 struct intel_plane_config *plane_config)
2384 {
2385 struct drm_device *dev = intel_crtc->base.dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct drm_crtc *c;
2388 struct intel_crtc *i;
2389 struct drm_i915_gem_object *obj;
2390
2391 if (!intel_crtc->base.primary->fb)
2392 return;
2393
2394 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2395 return;
2396
2397 kfree(intel_crtc->base.primary->fb);
2398 intel_crtc->base.primary->fb = NULL;
2399
2400 /*
2401 * Failed to alloc the obj, check to see if we should share
2402 * an fb with another CRTC instead
2403 */
2404 for_each_crtc(dev, c) {
2405 i = to_intel_crtc(c);
2406
2407 if (c == &intel_crtc->base)
2408 continue;
2409
2410 if (!i->active)
2411 continue;
2412
2413 obj = intel_fb_obj(c->primary->fb);
2414 if (obj == NULL)
2415 continue;
2416
2417 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2418 if (obj->tiling_mode != I915_TILING_NONE)
2419 dev_priv->preserve_bios_swizzle = true;
2420
2421 drm_framebuffer_reference(c->primary->fb);
2422 intel_crtc->base.primary->fb = c->primary->fb;
2423 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
2424 break;
2425 }
2426 }
2427 }
2428
2429 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2430 struct drm_framebuffer *fb,
2431 int x, int y)
2432 {
2433 struct drm_device *dev = crtc->dev;
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2436 struct drm_i915_gem_object *obj;
2437 int plane = intel_crtc->plane;
2438 unsigned long linear_offset;
2439 u32 dspcntr;
2440 u32 reg = DSPCNTR(plane);
2441 int pixel_size;
2442
2443 if (!intel_crtc->primary_enabled) {
2444 I915_WRITE(reg, 0);
2445 if (INTEL_INFO(dev)->gen >= 4)
2446 I915_WRITE(DSPSURF(plane), 0);
2447 else
2448 I915_WRITE(DSPADDR(plane), 0);
2449 POSTING_READ(reg);
2450 return;
2451 }
2452
2453 obj = intel_fb_obj(fb);
2454 if (WARN_ON(obj == NULL))
2455 return;
2456
2457 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2458
2459 dspcntr = DISPPLANE_GAMMA_ENABLE;
2460
2461 dspcntr |= DISPLAY_PLANE_ENABLE;
2462
2463 if (INTEL_INFO(dev)->gen < 4) {
2464 if (intel_crtc->pipe == PIPE_B)
2465 dspcntr |= DISPPLANE_SEL_PIPE_B;
2466
2467 /* pipesrc and dspsize control the size that is scaled from,
2468 * which should always be the user's requested size.
2469 */
2470 I915_WRITE(DSPSIZE(plane),
2471 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2472 (intel_crtc->config.pipe_src_w - 1));
2473 I915_WRITE(DSPPOS(plane), 0);
2474 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2475 I915_WRITE(PRIMSIZE(plane),
2476 ((intel_crtc->config.pipe_src_h - 1) << 16) |
2477 (intel_crtc->config.pipe_src_w - 1));
2478 I915_WRITE(PRIMPOS(plane), 0);
2479 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2480 }
2481
2482 switch (fb->pixel_format) {
2483 case DRM_FORMAT_C8:
2484 dspcntr |= DISPPLANE_8BPP;
2485 break;
2486 case DRM_FORMAT_XRGB1555:
2487 case DRM_FORMAT_ARGB1555:
2488 dspcntr |= DISPPLANE_BGRX555;
2489 break;
2490 case DRM_FORMAT_RGB565:
2491 dspcntr |= DISPPLANE_BGRX565;
2492 break;
2493 case DRM_FORMAT_XRGB8888:
2494 case DRM_FORMAT_ARGB8888:
2495 dspcntr |= DISPPLANE_BGRX888;
2496 break;
2497 case DRM_FORMAT_XBGR8888:
2498 case DRM_FORMAT_ABGR8888:
2499 dspcntr |= DISPPLANE_RGBX888;
2500 break;
2501 case DRM_FORMAT_XRGB2101010:
2502 case DRM_FORMAT_ARGB2101010:
2503 dspcntr |= DISPPLANE_BGRX101010;
2504 break;
2505 case DRM_FORMAT_XBGR2101010:
2506 case DRM_FORMAT_ABGR2101010:
2507 dspcntr |= DISPPLANE_RGBX101010;
2508 break;
2509 default:
2510 BUG();
2511 }
2512
2513 if (INTEL_INFO(dev)->gen >= 4 &&
2514 obj->tiling_mode != I915_TILING_NONE)
2515 dspcntr |= DISPPLANE_TILED;
2516
2517 if (IS_G4X(dev))
2518 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2519
2520 linear_offset = y * fb->pitches[0] + x * pixel_size;
2521
2522 if (INTEL_INFO(dev)->gen >= 4) {
2523 intel_crtc->dspaddr_offset =
2524 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2525 pixel_size,
2526 fb->pitches[0]);
2527 linear_offset -= intel_crtc->dspaddr_offset;
2528 } else {
2529 intel_crtc->dspaddr_offset = linear_offset;
2530 }
2531
2532 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2533 dspcntr |= DISPPLANE_ROTATE_180;
2534
2535 x += (intel_crtc->config.pipe_src_w - 1);
2536 y += (intel_crtc->config.pipe_src_h - 1);
2537
2538 /* Finding the last pixel of the last line of the display
2539 data and adding to linear_offset*/
2540 linear_offset +=
2541 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2542 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2543 }
2544
2545 I915_WRITE(reg, dspcntr);
2546
2547 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2548 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2549 fb->pitches[0]);
2550 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2551 if (INTEL_INFO(dev)->gen >= 4) {
2552 I915_WRITE(DSPSURF(plane),
2553 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2554 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2555 I915_WRITE(DSPLINOFF(plane), linear_offset);
2556 } else
2557 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2558 POSTING_READ(reg);
2559 }
2560
2561 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2562 struct drm_framebuffer *fb,
2563 int x, int y)
2564 {
2565 struct drm_device *dev = crtc->dev;
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2568 struct drm_i915_gem_object *obj;
2569 int plane = intel_crtc->plane;
2570 unsigned long linear_offset;
2571 u32 dspcntr;
2572 u32 reg = DSPCNTR(plane);
2573 int pixel_size;
2574
2575 if (!intel_crtc->primary_enabled) {
2576 I915_WRITE(reg, 0);
2577 I915_WRITE(DSPSURF(plane), 0);
2578 POSTING_READ(reg);
2579 return;
2580 }
2581
2582 obj = intel_fb_obj(fb);
2583 if (WARN_ON(obj == NULL))
2584 return;
2585
2586 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2587
2588 dspcntr = DISPPLANE_GAMMA_ENABLE;
2589
2590 dspcntr |= DISPLAY_PLANE_ENABLE;
2591
2592 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2593 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2594
2595 switch (fb->pixel_format) {
2596 case DRM_FORMAT_C8:
2597 dspcntr |= DISPPLANE_8BPP;
2598 break;
2599 case DRM_FORMAT_RGB565:
2600 dspcntr |= DISPPLANE_BGRX565;
2601 break;
2602 case DRM_FORMAT_XRGB8888:
2603 case DRM_FORMAT_ARGB8888:
2604 dspcntr |= DISPPLANE_BGRX888;
2605 break;
2606 case DRM_FORMAT_XBGR8888:
2607 case DRM_FORMAT_ABGR8888:
2608 dspcntr |= DISPPLANE_RGBX888;
2609 break;
2610 case DRM_FORMAT_XRGB2101010:
2611 case DRM_FORMAT_ARGB2101010:
2612 dspcntr |= DISPPLANE_BGRX101010;
2613 break;
2614 case DRM_FORMAT_XBGR2101010:
2615 case DRM_FORMAT_ABGR2101010:
2616 dspcntr |= DISPPLANE_RGBX101010;
2617 break;
2618 default:
2619 BUG();
2620 }
2621
2622 if (obj->tiling_mode != I915_TILING_NONE)
2623 dspcntr |= DISPPLANE_TILED;
2624
2625 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2626 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2627
2628 linear_offset = y * fb->pitches[0] + x * pixel_size;
2629 intel_crtc->dspaddr_offset =
2630 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2631 pixel_size,
2632 fb->pitches[0]);
2633 linear_offset -= intel_crtc->dspaddr_offset;
2634 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) {
2635 dspcntr |= DISPPLANE_ROTATE_180;
2636
2637 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2638 x += (intel_crtc->config.pipe_src_w - 1);
2639 y += (intel_crtc->config.pipe_src_h - 1);
2640
2641 /* Finding the last pixel of the last line of the display
2642 data and adding to linear_offset*/
2643 linear_offset +=
2644 (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] +
2645 (intel_crtc->config.pipe_src_w - 1) * pixel_size;
2646 }
2647 }
2648
2649 I915_WRITE(reg, dspcntr);
2650
2651 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2652 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2653 fb->pitches[0]);
2654 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2655 I915_WRITE(DSPSURF(plane),
2656 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2657 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2658 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2659 } else {
2660 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2661 I915_WRITE(DSPLINOFF(plane), linear_offset);
2662 }
2663 POSTING_READ(reg);
2664 }
2665
2666 static void skylake_update_primary_plane(struct drm_crtc *crtc,
2667 struct drm_framebuffer *fb,
2668 int x, int y)
2669 {
2670 struct drm_device *dev = crtc->dev;
2671 struct drm_i915_private *dev_priv = dev->dev_private;
2672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2673 struct intel_framebuffer *intel_fb;
2674 struct drm_i915_gem_object *obj;
2675 int pipe = intel_crtc->pipe;
2676 u32 plane_ctl, stride;
2677
2678 if (!intel_crtc->primary_enabled) {
2679 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2680 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2681 POSTING_READ(PLANE_CTL(pipe, 0));
2682 return;
2683 }
2684
2685 plane_ctl = PLANE_CTL_ENABLE |
2686 PLANE_CTL_PIPE_GAMMA_ENABLE |
2687 PLANE_CTL_PIPE_CSC_ENABLE;
2688
2689 switch (fb->pixel_format) {
2690 case DRM_FORMAT_RGB565:
2691 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2692 break;
2693 case DRM_FORMAT_XRGB8888:
2694 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2695 break;
2696 case DRM_FORMAT_XBGR8888:
2697 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2698 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2699 break;
2700 case DRM_FORMAT_XRGB2101010:
2701 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2702 break;
2703 case DRM_FORMAT_XBGR2101010:
2704 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2705 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2706 break;
2707 default:
2708 BUG();
2709 }
2710
2711 intel_fb = to_intel_framebuffer(fb);
2712 obj = intel_fb->obj;
2713
2714 /*
2715 * The stride is either expressed as a multiple of 64 bytes chunks for
2716 * linear buffers or in number of tiles for tiled buffers.
2717 */
2718 switch (obj->tiling_mode) {
2719 case I915_TILING_NONE:
2720 stride = fb->pitches[0] >> 6;
2721 break;
2722 case I915_TILING_X:
2723 plane_ctl |= PLANE_CTL_TILED_X;
2724 stride = fb->pitches[0] >> 9;
2725 break;
2726 default:
2727 BUG();
2728 }
2729
2730 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
2731 if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180))
2732 plane_ctl |= PLANE_CTL_ROTATE_180;
2733
2734 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
2735
2736 DRM_DEBUG_KMS("Writing base %08lX %d,%d,%d,%d pitch=%d\n",
2737 i915_gem_obj_ggtt_offset(obj),
2738 x, y, fb->width, fb->height,
2739 fb->pitches[0]);
2740
2741 I915_WRITE(PLANE_POS(pipe, 0), 0);
2742 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2743 I915_WRITE(PLANE_SIZE(pipe, 0),
2744 (intel_crtc->config.pipe_src_h - 1) << 16 |
2745 (intel_crtc->config.pipe_src_w - 1));
2746 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
2747 I915_WRITE(PLANE_SURF(pipe, 0), i915_gem_obj_ggtt_offset(obj));
2748
2749 POSTING_READ(PLANE_SURF(pipe, 0));
2750 }
2751
2752 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2753 static int
2754 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2755 int x, int y, enum mode_set_atomic state)
2756 {
2757 struct drm_device *dev = crtc->dev;
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759
2760 if (dev_priv->display.disable_fbc)
2761 dev_priv->display.disable_fbc(dev);
2762
2763 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2764
2765 return 0;
2766 }
2767
2768 void intel_display_handle_reset(struct drm_device *dev)
2769 {
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct drm_crtc *crtc;
2772
2773 /*
2774 * Flips in the rings have been nuked by the reset,
2775 * so complete all pending flips so that user space
2776 * will get its events and not get stuck.
2777 *
2778 * Also update the base address of all primary
2779 * planes to the the last fb to make sure we're
2780 * showing the correct fb after a reset.
2781 *
2782 * Need to make two loops over the crtcs so that we
2783 * don't try to grab a crtc mutex before the
2784 * pending_flip_queue really got woken up.
2785 */
2786
2787 for_each_crtc(dev, crtc) {
2788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2789 enum plane plane = intel_crtc->plane;
2790
2791 intel_prepare_page_flip(dev, plane);
2792 intel_finish_page_flip_plane(dev, plane);
2793 }
2794
2795 for_each_crtc(dev, crtc) {
2796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2797
2798 drm_modeset_lock(&crtc->mutex, NULL);
2799 /*
2800 * FIXME: Once we have proper support for primary planes (and
2801 * disabling them without disabling the entire crtc) allow again
2802 * a NULL crtc->primary->fb.
2803 */
2804 if (intel_crtc->active && crtc->primary->fb)
2805 dev_priv->display.update_primary_plane(crtc,
2806 crtc->primary->fb,
2807 crtc->x,
2808 crtc->y);
2809 drm_modeset_unlock(&crtc->mutex);
2810 }
2811 }
2812
2813 static int
2814 intel_finish_fb(struct drm_framebuffer *old_fb)
2815 {
2816 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2817 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2818 bool was_interruptible = dev_priv->mm.interruptible;
2819 int ret;
2820
2821 /* Big Hammer, we also need to ensure that any pending
2822 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2823 * current scanout is retired before unpinning the old
2824 * framebuffer.
2825 *
2826 * This should only fail upon a hung GPU, in which case we
2827 * can safely continue.
2828 */
2829 dev_priv->mm.interruptible = false;
2830 ret = i915_gem_object_finish_gpu(obj);
2831 dev_priv->mm.interruptible = was_interruptible;
2832
2833 return ret;
2834 }
2835
2836 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2837 {
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_i915_private *dev_priv = dev->dev_private;
2840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2841 bool pending;
2842
2843 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2844 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2845 return false;
2846
2847 spin_lock_irq(&dev->event_lock);
2848 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2849 spin_unlock_irq(&dev->event_lock);
2850
2851 return pending;
2852 }
2853
2854 static void intel_update_pipe_size(struct intel_crtc *crtc)
2855 {
2856 struct drm_device *dev = crtc->base.dev;
2857 struct drm_i915_private *dev_priv = dev->dev_private;
2858 const struct drm_display_mode *adjusted_mode;
2859
2860 if (!i915.fastboot)
2861 return;
2862
2863 /*
2864 * Update pipe size and adjust fitter if needed: the reason for this is
2865 * that in compute_mode_changes we check the native mode (not the pfit
2866 * mode) to see if we can flip rather than do a full mode set. In the
2867 * fastboot case, we'll flip, but if we don't update the pipesrc and
2868 * pfit state, we'll end up with a big fb scanned out into the wrong
2869 * sized surface.
2870 *
2871 * To fix this properly, we need to hoist the checks up into
2872 * compute_mode_changes (or above), check the actual pfit state and
2873 * whether the platform allows pfit disable with pipe active, and only
2874 * then update the pipesrc and pfit state, even on the flip path.
2875 */
2876
2877 adjusted_mode = &crtc->config.adjusted_mode;
2878
2879 I915_WRITE(PIPESRC(crtc->pipe),
2880 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2881 (adjusted_mode->crtc_vdisplay - 1));
2882 if (!crtc->config.pch_pfit.enabled &&
2883 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2884 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2885 I915_WRITE(PF_CTL(crtc->pipe), 0);
2886 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
2887 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
2888 }
2889 crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2890 crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2891 }
2892
2893 static int
2894 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2895 struct drm_framebuffer *fb)
2896 {
2897 struct drm_device *dev = crtc->dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900 enum pipe pipe = intel_crtc->pipe;
2901 struct drm_framebuffer *old_fb = crtc->primary->fb;
2902 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
2903 int ret;
2904
2905 if (intel_crtc_has_pending_flip(crtc)) {
2906 DRM_ERROR("pipe is still busy with an old pageflip\n");
2907 return -EBUSY;
2908 }
2909
2910 /* no fb bound */
2911 if (!fb) {
2912 DRM_ERROR("No FB bound\n");
2913 return 0;
2914 }
2915
2916 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2917 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2918 plane_name(intel_crtc->plane),
2919 INTEL_INFO(dev)->num_pipes);
2920 return -EINVAL;
2921 }
2922
2923 mutex_lock(&dev->struct_mutex);
2924 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
2925 if (ret == 0)
2926 i915_gem_track_fb(old_obj, intel_fb_obj(fb),
2927 INTEL_FRONTBUFFER_PRIMARY(pipe));
2928 mutex_unlock(&dev->struct_mutex);
2929 if (ret != 0) {
2930 DRM_ERROR("pin & fence failed\n");
2931 return ret;
2932 }
2933
2934 intel_update_pipe_size(intel_crtc);
2935
2936 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2937
2938 if (intel_crtc->active)
2939 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
2940
2941 crtc->primary->fb = fb;
2942 crtc->x = x;
2943 crtc->y = y;
2944
2945 if (old_fb) {
2946 if (intel_crtc->active && old_fb != fb)
2947 intel_wait_for_vblank(dev, intel_crtc->pipe);
2948 mutex_lock(&dev->struct_mutex);
2949 intel_unpin_fb_obj(old_obj);
2950 mutex_unlock(&dev->struct_mutex);
2951 }
2952
2953 mutex_lock(&dev->struct_mutex);
2954 intel_update_fbc(dev);
2955 mutex_unlock(&dev->struct_mutex);
2956
2957 return 0;
2958 }
2959
2960 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2961 {
2962 struct drm_device *dev = crtc->dev;
2963 struct drm_i915_private *dev_priv = dev->dev_private;
2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 int pipe = intel_crtc->pipe;
2966 u32 reg, temp;
2967
2968 /* enable normal train */
2969 reg = FDI_TX_CTL(pipe);
2970 temp = I915_READ(reg);
2971 if (IS_IVYBRIDGE(dev)) {
2972 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2973 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2974 } else {
2975 temp &= ~FDI_LINK_TRAIN_NONE;
2976 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2977 }
2978 I915_WRITE(reg, temp);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2985 } else {
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_NONE;
2988 }
2989 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2990
2991 /* wait one idle pattern time */
2992 POSTING_READ(reg);
2993 udelay(1000);
2994
2995 /* IVB wants error correction enabled */
2996 if (IS_IVYBRIDGE(dev))
2997 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2998 FDI_FE_ERRC_ENABLE);
2999 }
3000
3001 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
3002 {
3003 return crtc->base.enabled && crtc->active &&
3004 crtc->config.has_pch_encoder;
3005 }
3006
3007 static void ivb_modeset_global_resources(struct drm_device *dev)
3008 {
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *pipe_B_crtc =
3011 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3012 struct intel_crtc *pipe_C_crtc =
3013 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
3014 uint32_t temp;
3015
3016 /*
3017 * When everything is off disable fdi C so that we could enable fdi B
3018 * with all lanes. Note that we don't care about enabled pipes without
3019 * an enabled pch encoder.
3020 */
3021 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
3022 !pipe_has_enabled_pch(pipe_C_crtc)) {
3023 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3024 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3025
3026 temp = I915_READ(SOUTH_CHICKEN1);
3027 temp &= ~FDI_BC_BIFURCATION_SELECT;
3028 DRM_DEBUG_KMS("disabling fdi C rx\n");
3029 I915_WRITE(SOUTH_CHICKEN1, temp);
3030 }
3031 }
3032
3033 /* The FDI link training functions for ILK/Ibexpeak. */
3034 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3035 {
3036 struct drm_device *dev = crtc->dev;
3037 struct drm_i915_private *dev_priv = dev->dev_private;
3038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3039 int pipe = intel_crtc->pipe;
3040 u32 reg, temp, tries;
3041
3042 /* FDI needs bits from pipe first */
3043 assert_pipe_enabled(dev_priv, pipe);
3044
3045 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3046 for train result */
3047 reg = FDI_RX_IMR(pipe);
3048 temp = I915_READ(reg);
3049 temp &= ~FDI_RX_SYMBOL_LOCK;
3050 temp &= ~FDI_RX_BIT_LOCK;
3051 I915_WRITE(reg, temp);
3052 I915_READ(reg);
3053 udelay(150);
3054
3055 /* enable CPU FDI TX and PCH FDI RX */
3056 reg = FDI_TX_CTL(pipe);
3057 temp = I915_READ(reg);
3058 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3059 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3060 temp &= ~FDI_LINK_TRAIN_NONE;
3061 temp |= FDI_LINK_TRAIN_PATTERN_1;
3062 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3063
3064 reg = FDI_RX_CTL(pipe);
3065 temp = I915_READ(reg);
3066 temp &= ~FDI_LINK_TRAIN_NONE;
3067 temp |= FDI_LINK_TRAIN_PATTERN_1;
3068 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3069
3070 POSTING_READ(reg);
3071 udelay(150);
3072
3073 /* Ironlake workaround, enable clock pointer after FDI enable*/
3074 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3075 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3076 FDI_RX_PHASE_SYNC_POINTER_EN);
3077
3078 reg = FDI_RX_IIR(pipe);
3079 for (tries = 0; tries < 5; tries++) {
3080 temp = I915_READ(reg);
3081 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3082
3083 if ((temp & FDI_RX_BIT_LOCK)) {
3084 DRM_DEBUG_KMS("FDI train 1 done.\n");
3085 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3086 break;
3087 }
3088 }
3089 if (tries == 5)
3090 DRM_ERROR("FDI train 1 fail!\n");
3091
3092 /* Train 2 */
3093 reg = FDI_TX_CTL(pipe);
3094 temp = I915_READ(reg);
3095 temp &= ~FDI_LINK_TRAIN_NONE;
3096 temp |= FDI_LINK_TRAIN_PATTERN_2;
3097 I915_WRITE(reg, temp);
3098
3099 reg = FDI_RX_CTL(pipe);
3100 temp = I915_READ(reg);
3101 temp &= ~FDI_LINK_TRAIN_NONE;
3102 temp |= FDI_LINK_TRAIN_PATTERN_2;
3103 I915_WRITE(reg, temp);
3104
3105 POSTING_READ(reg);
3106 udelay(150);
3107
3108 reg = FDI_RX_IIR(pipe);
3109 for (tries = 0; tries < 5; tries++) {
3110 temp = I915_READ(reg);
3111 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3112
3113 if (temp & FDI_RX_SYMBOL_LOCK) {
3114 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3115 DRM_DEBUG_KMS("FDI train 2 done.\n");
3116 break;
3117 }
3118 }
3119 if (tries == 5)
3120 DRM_ERROR("FDI train 2 fail!\n");
3121
3122 DRM_DEBUG_KMS("FDI train done\n");
3123
3124 }
3125
3126 static const int snb_b_fdi_train_param[] = {
3127 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3128 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3129 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3130 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3131 };
3132
3133 /* The FDI link training functions for SNB/Cougarpoint. */
3134 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3135 {
3136 struct drm_device *dev = crtc->dev;
3137 struct drm_i915_private *dev_priv = dev->dev_private;
3138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3139 int pipe = intel_crtc->pipe;
3140 u32 reg, temp, i, retry;
3141
3142 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3143 for train result */
3144 reg = FDI_RX_IMR(pipe);
3145 temp = I915_READ(reg);
3146 temp &= ~FDI_RX_SYMBOL_LOCK;
3147 temp &= ~FDI_RX_BIT_LOCK;
3148 I915_WRITE(reg, temp);
3149
3150 POSTING_READ(reg);
3151 udelay(150);
3152
3153 /* enable CPU FDI TX and PCH FDI RX */
3154 reg = FDI_TX_CTL(pipe);
3155 temp = I915_READ(reg);
3156 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3157 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3158 temp &= ~FDI_LINK_TRAIN_NONE;
3159 temp |= FDI_LINK_TRAIN_PATTERN_1;
3160 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3161 /* SNB-B */
3162 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3163 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3164
3165 I915_WRITE(FDI_RX_MISC(pipe),
3166 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3167
3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 if (HAS_PCH_CPT(dev)) {
3171 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3172 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3173 } else {
3174 temp &= ~FDI_LINK_TRAIN_NONE;
3175 temp |= FDI_LINK_TRAIN_PATTERN_1;
3176 }
3177 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3178
3179 POSTING_READ(reg);
3180 udelay(150);
3181
3182 for (i = 0; i < 4; i++) {
3183 reg = FDI_TX_CTL(pipe);
3184 temp = I915_READ(reg);
3185 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3186 temp |= snb_b_fdi_train_param[i];
3187 I915_WRITE(reg, temp);
3188
3189 POSTING_READ(reg);
3190 udelay(500);
3191
3192 for (retry = 0; retry < 5; retry++) {
3193 reg = FDI_RX_IIR(pipe);
3194 temp = I915_READ(reg);
3195 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3196 if (temp & FDI_RX_BIT_LOCK) {
3197 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3198 DRM_DEBUG_KMS("FDI train 1 done.\n");
3199 break;
3200 }
3201 udelay(50);
3202 }
3203 if (retry < 5)
3204 break;
3205 }
3206 if (i == 4)
3207 DRM_ERROR("FDI train 1 fail!\n");
3208
3209 /* Train 2 */
3210 reg = FDI_TX_CTL(pipe);
3211 temp = I915_READ(reg);
3212 temp &= ~FDI_LINK_TRAIN_NONE;
3213 temp |= FDI_LINK_TRAIN_PATTERN_2;
3214 if (IS_GEN6(dev)) {
3215 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3216 /* SNB-B */
3217 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3218 }
3219 I915_WRITE(reg, temp);
3220
3221 reg = FDI_RX_CTL(pipe);
3222 temp = I915_READ(reg);
3223 if (HAS_PCH_CPT(dev)) {
3224 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3225 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3226 } else {
3227 temp &= ~FDI_LINK_TRAIN_NONE;
3228 temp |= FDI_LINK_TRAIN_PATTERN_2;
3229 }
3230 I915_WRITE(reg, temp);
3231
3232 POSTING_READ(reg);
3233 udelay(150);
3234
3235 for (i = 0; i < 4; i++) {
3236 reg = FDI_TX_CTL(pipe);
3237 temp = I915_READ(reg);
3238 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3239 temp |= snb_b_fdi_train_param[i];
3240 I915_WRITE(reg, temp);
3241
3242 POSTING_READ(reg);
3243 udelay(500);
3244
3245 for (retry = 0; retry < 5; retry++) {
3246 reg = FDI_RX_IIR(pipe);
3247 temp = I915_READ(reg);
3248 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3249 if (temp & FDI_RX_SYMBOL_LOCK) {
3250 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3251 DRM_DEBUG_KMS("FDI train 2 done.\n");
3252 break;
3253 }
3254 udelay(50);
3255 }
3256 if (retry < 5)
3257 break;
3258 }
3259 if (i == 4)
3260 DRM_ERROR("FDI train 2 fail!\n");
3261
3262 DRM_DEBUG_KMS("FDI train done.\n");
3263 }
3264
3265 /* Manual link training for Ivy Bridge A0 parts */
3266 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3267 {
3268 struct drm_device *dev = crtc->dev;
3269 struct drm_i915_private *dev_priv = dev->dev_private;
3270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3271 int pipe = intel_crtc->pipe;
3272 u32 reg, temp, i, j;
3273
3274 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3275 for train result */
3276 reg = FDI_RX_IMR(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~FDI_RX_SYMBOL_LOCK;
3279 temp &= ~FDI_RX_BIT_LOCK;
3280 I915_WRITE(reg, temp);
3281
3282 POSTING_READ(reg);
3283 udelay(150);
3284
3285 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3286 I915_READ(FDI_RX_IIR(pipe)));
3287
3288 /* Try each vswing and preemphasis setting twice before moving on */
3289 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3290 /* disable first in case we need to retry */
3291 reg = FDI_TX_CTL(pipe);
3292 temp = I915_READ(reg);
3293 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3294 temp &= ~FDI_TX_ENABLE;
3295 I915_WRITE(reg, temp);
3296
3297 reg = FDI_RX_CTL(pipe);
3298 temp = I915_READ(reg);
3299 temp &= ~FDI_LINK_TRAIN_AUTO;
3300 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3301 temp &= ~FDI_RX_ENABLE;
3302 I915_WRITE(reg, temp);
3303
3304 /* enable CPU FDI TX and PCH FDI RX */
3305 reg = FDI_TX_CTL(pipe);
3306 temp = I915_READ(reg);
3307 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3308 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3309 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3310 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3311 temp |= snb_b_fdi_train_param[j/2];
3312 temp |= FDI_COMPOSITE_SYNC;
3313 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3314
3315 I915_WRITE(FDI_RX_MISC(pipe),
3316 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3317
3318 reg = FDI_RX_CTL(pipe);
3319 temp = I915_READ(reg);
3320 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3321 temp |= FDI_COMPOSITE_SYNC;
3322 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3323
3324 POSTING_READ(reg);
3325 udelay(1); /* should be 0.5us */
3326
3327 for (i = 0; i < 4; i++) {
3328 reg = FDI_RX_IIR(pipe);
3329 temp = I915_READ(reg);
3330 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3331
3332 if (temp & FDI_RX_BIT_LOCK ||
3333 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3334 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3335 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3336 i);
3337 break;
3338 }
3339 udelay(1); /* should be 0.5us */
3340 }
3341 if (i == 4) {
3342 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3343 continue;
3344 }
3345
3346 /* Train 2 */
3347 reg = FDI_TX_CTL(pipe);
3348 temp = I915_READ(reg);
3349 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3350 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3351 I915_WRITE(reg, temp);
3352
3353 reg = FDI_RX_CTL(pipe);
3354 temp = I915_READ(reg);
3355 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3356 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3357 I915_WRITE(reg, temp);
3358
3359 POSTING_READ(reg);
3360 udelay(2); /* should be 1.5us */
3361
3362 for (i = 0; i < 4; i++) {
3363 reg = FDI_RX_IIR(pipe);
3364 temp = I915_READ(reg);
3365 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3366
3367 if (temp & FDI_RX_SYMBOL_LOCK ||
3368 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3369 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3370 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3371 i);
3372 goto train_done;
3373 }
3374 udelay(2); /* should be 1.5us */
3375 }
3376 if (i == 4)
3377 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3378 }
3379
3380 train_done:
3381 DRM_DEBUG_KMS("FDI train done.\n");
3382 }
3383
3384 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3385 {
3386 struct drm_device *dev = intel_crtc->base.dev;
3387 struct drm_i915_private *dev_priv = dev->dev_private;
3388 int pipe = intel_crtc->pipe;
3389 u32 reg, temp;
3390
3391
3392 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3393 reg = FDI_RX_CTL(pipe);
3394 temp = I915_READ(reg);
3395 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3396 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3397 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3398 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3399
3400 POSTING_READ(reg);
3401 udelay(200);
3402
3403 /* Switch from Rawclk to PCDclk */
3404 temp = I915_READ(reg);
3405 I915_WRITE(reg, temp | FDI_PCDCLK);
3406
3407 POSTING_READ(reg);
3408 udelay(200);
3409
3410 /* Enable CPU FDI TX PLL, always on for Ironlake */
3411 reg = FDI_TX_CTL(pipe);
3412 temp = I915_READ(reg);
3413 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3414 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3415
3416 POSTING_READ(reg);
3417 udelay(100);
3418 }
3419 }
3420
3421 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3422 {
3423 struct drm_device *dev = intel_crtc->base.dev;
3424 struct drm_i915_private *dev_priv = dev->dev_private;
3425 int pipe = intel_crtc->pipe;
3426 u32 reg, temp;
3427
3428 /* Switch from PCDclk to Rawclk */
3429 reg = FDI_RX_CTL(pipe);
3430 temp = I915_READ(reg);
3431 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3432
3433 /* Disable CPU FDI TX PLL */
3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
3436 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3437
3438 POSTING_READ(reg);
3439 udelay(100);
3440
3441 reg = FDI_RX_CTL(pipe);
3442 temp = I915_READ(reg);
3443 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3444
3445 /* Wait for the clocks to turn off. */
3446 POSTING_READ(reg);
3447 udelay(100);
3448 }
3449
3450 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3451 {
3452 struct drm_device *dev = crtc->dev;
3453 struct drm_i915_private *dev_priv = dev->dev_private;
3454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3455 int pipe = intel_crtc->pipe;
3456 u32 reg, temp;
3457
3458 /* disable CPU FDI tx and PCH FDI rx */
3459 reg = FDI_TX_CTL(pipe);
3460 temp = I915_READ(reg);
3461 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3462 POSTING_READ(reg);
3463
3464 reg = FDI_RX_CTL(pipe);
3465 temp = I915_READ(reg);
3466 temp &= ~(0x7 << 16);
3467 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3468 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3469
3470 POSTING_READ(reg);
3471 udelay(100);
3472
3473 /* Ironlake workaround, disable clock pointer after downing FDI */
3474 if (HAS_PCH_IBX(dev))
3475 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3476
3477 /* still set train pattern 1 */
3478 reg = FDI_TX_CTL(pipe);
3479 temp = I915_READ(reg);
3480 temp &= ~FDI_LINK_TRAIN_NONE;
3481 temp |= FDI_LINK_TRAIN_PATTERN_1;
3482 I915_WRITE(reg, temp);
3483
3484 reg = FDI_RX_CTL(pipe);
3485 temp = I915_READ(reg);
3486 if (HAS_PCH_CPT(dev)) {
3487 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3488 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3489 } else {
3490 temp &= ~FDI_LINK_TRAIN_NONE;
3491 temp |= FDI_LINK_TRAIN_PATTERN_1;
3492 }
3493 /* BPC in FDI rx is consistent with that in PIPECONF */
3494 temp &= ~(0x07 << 16);
3495 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3496 I915_WRITE(reg, temp);
3497
3498 POSTING_READ(reg);
3499 udelay(100);
3500 }
3501
3502 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3503 {
3504 struct intel_crtc *crtc;
3505
3506 /* Note that we don't need to be called with mode_config.lock here
3507 * as our list of CRTC objects is static for the lifetime of the
3508 * device and so cannot disappear as we iterate. Similarly, we can
3509 * happily treat the predicates as racy, atomic checks as userspace
3510 * cannot claim and pin a new fb without at least acquring the
3511 * struct_mutex and so serialising with us.
3512 */
3513 for_each_intel_crtc(dev, crtc) {
3514 if (atomic_read(&crtc->unpin_work_count) == 0)
3515 continue;
3516
3517 if (crtc->unpin_work)
3518 intel_wait_for_vblank(dev, crtc->pipe);
3519
3520 return true;
3521 }
3522
3523 return false;
3524 }
3525
3526 static void page_flip_completed(struct intel_crtc *intel_crtc)
3527 {
3528 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3529 struct intel_unpin_work *work = intel_crtc->unpin_work;
3530
3531 /* ensure that the unpin work is consistent wrt ->pending. */
3532 smp_rmb();
3533 intel_crtc->unpin_work = NULL;
3534
3535 if (work->event)
3536 drm_send_vblank_event(intel_crtc->base.dev,
3537 intel_crtc->pipe,
3538 work->event);
3539
3540 drm_crtc_vblank_put(&intel_crtc->base);
3541
3542 wake_up_all(&dev_priv->pending_flip_queue);
3543 queue_work(dev_priv->wq, &work->work);
3544
3545 trace_i915_flip_complete(intel_crtc->plane,
3546 work->pending_flip_obj);
3547 }
3548
3549 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3550 {
3551 struct drm_device *dev = crtc->dev;
3552 struct drm_i915_private *dev_priv = dev->dev_private;
3553
3554 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3555 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3556 !intel_crtc_has_pending_flip(crtc),
3557 60*HZ) == 0)) {
3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3559
3560 spin_lock_irq(&dev->event_lock);
3561 if (intel_crtc->unpin_work) {
3562 WARN_ONCE(1, "Removing stuck page flip\n");
3563 page_flip_completed(intel_crtc);
3564 }
3565 spin_unlock_irq(&dev->event_lock);
3566 }
3567
3568 if (crtc->primary->fb) {
3569 mutex_lock(&dev->struct_mutex);
3570 intel_finish_fb(crtc->primary->fb);
3571 mutex_unlock(&dev->struct_mutex);
3572 }
3573 }
3574
3575 /* Program iCLKIP clock to the desired frequency */
3576 static void lpt_program_iclkip(struct drm_crtc *crtc)
3577 {
3578 struct drm_device *dev = crtc->dev;
3579 struct drm_i915_private *dev_priv = dev->dev_private;
3580 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3581 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3582 u32 temp;
3583
3584 mutex_lock(&dev_priv->dpio_lock);
3585
3586 /* It is necessary to ungate the pixclk gate prior to programming
3587 * the divisors, and gate it back when it is done.
3588 */
3589 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3590
3591 /* Disable SSCCTL */
3592 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3593 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3594 SBI_SSCCTL_DISABLE,
3595 SBI_ICLK);
3596
3597 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3598 if (clock == 20000) {
3599 auxdiv = 1;
3600 divsel = 0x41;
3601 phaseinc = 0x20;
3602 } else {
3603 /* The iCLK virtual clock root frequency is in MHz,
3604 * but the adjusted_mode->crtc_clock in in KHz. To get the
3605 * divisors, it is necessary to divide one by another, so we
3606 * convert the virtual clock precision to KHz here for higher
3607 * precision.
3608 */
3609 u32 iclk_virtual_root_freq = 172800 * 1000;
3610 u32 iclk_pi_range = 64;
3611 u32 desired_divisor, msb_divisor_value, pi_value;
3612
3613 desired_divisor = (iclk_virtual_root_freq / clock);
3614 msb_divisor_value = desired_divisor / iclk_pi_range;
3615 pi_value = desired_divisor % iclk_pi_range;
3616
3617 auxdiv = 0;
3618 divsel = msb_divisor_value - 2;
3619 phaseinc = pi_value;
3620 }
3621
3622 /* This should not happen with any sane values */
3623 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3624 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3625 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3626 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3627
3628 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3629 clock,
3630 auxdiv,
3631 divsel,
3632 phasedir,
3633 phaseinc);
3634
3635 /* Program SSCDIVINTPHASE6 */
3636 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3637 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3638 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3639 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3640 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3641 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3642 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3643 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3644
3645 /* Program SSCAUXDIV */
3646 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3647 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3648 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3649 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3650
3651 /* Enable modulator and associated divider */
3652 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3653 temp &= ~SBI_SSCCTL_DISABLE;
3654 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3655
3656 /* Wait for initialization time */
3657 udelay(24);
3658
3659 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3660
3661 mutex_unlock(&dev_priv->dpio_lock);
3662 }
3663
3664 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3665 enum pipe pch_transcoder)
3666 {
3667 struct drm_device *dev = crtc->base.dev;
3668 struct drm_i915_private *dev_priv = dev->dev_private;
3669 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3670
3671 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3672 I915_READ(HTOTAL(cpu_transcoder)));
3673 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3674 I915_READ(HBLANK(cpu_transcoder)));
3675 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3676 I915_READ(HSYNC(cpu_transcoder)));
3677
3678 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3679 I915_READ(VTOTAL(cpu_transcoder)));
3680 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3681 I915_READ(VBLANK(cpu_transcoder)));
3682 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3683 I915_READ(VSYNC(cpu_transcoder)));
3684 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3685 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3686 }
3687
3688 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3689 {
3690 struct drm_i915_private *dev_priv = dev->dev_private;
3691 uint32_t temp;
3692
3693 temp = I915_READ(SOUTH_CHICKEN1);
3694 if (temp & FDI_BC_BIFURCATION_SELECT)
3695 return;
3696
3697 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3698 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3699
3700 temp |= FDI_BC_BIFURCATION_SELECT;
3701 DRM_DEBUG_KMS("enabling fdi C rx\n");
3702 I915_WRITE(SOUTH_CHICKEN1, temp);
3703 POSTING_READ(SOUTH_CHICKEN1);
3704 }
3705
3706 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3707 {
3708 struct drm_device *dev = intel_crtc->base.dev;
3709 struct drm_i915_private *dev_priv = dev->dev_private;
3710
3711 switch (intel_crtc->pipe) {
3712 case PIPE_A:
3713 break;
3714 case PIPE_B:
3715 if (intel_crtc->config.fdi_lanes > 2)
3716 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3717 else
3718 cpt_enable_fdi_bc_bifurcation(dev);
3719
3720 break;
3721 case PIPE_C:
3722 cpt_enable_fdi_bc_bifurcation(dev);
3723
3724 break;
3725 default:
3726 BUG();
3727 }
3728 }
3729
3730 /*
3731 * Enable PCH resources required for PCH ports:
3732 * - PCH PLLs
3733 * - FDI training & RX/TX
3734 * - update transcoder timings
3735 * - DP transcoding bits
3736 * - transcoder
3737 */
3738 static void ironlake_pch_enable(struct drm_crtc *crtc)
3739 {
3740 struct drm_device *dev = crtc->dev;
3741 struct drm_i915_private *dev_priv = dev->dev_private;
3742 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3743 int pipe = intel_crtc->pipe;
3744 u32 reg, temp;
3745
3746 assert_pch_transcoder_disabled(dev_priv, pipe);
3747
3748 if (IS_IVYBRIDGE(dev))
3749 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3750
3751 /* Write the TU size bits before fdi link training, so that error
3752 * detection works. */
3753 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3754 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3755
3756 /* For PCH output, training FDI link */
3757 dev_priv->display.fdi_link_train(crtc);
3758
3759 /* We need to program the right clock selection before writing the pixel
3760 * mutliplier into the DPLL. */
3761 if (HAS_PCH_CPT(dev)) {
3762 u32 sel;
3763
3764 temp = I915_READ(PCH_DPLL_SEL);
3765 temp |= TRANS_DPLL_ENABLE(pipe);
3766 sel = TRANS_DPLLB_SEL(pipe);
3767 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3768 temp |= sel;
3769 else
3770 temp &= ~sel;
3771 I915_WRITE(PCH_DPLL_SEL, temp);
3772 }
3773
3774 /* XXX: pch pll's can be enabled any time before we enable the PCH
3775 * transcoder, and we actually should do this to not upset any PCH
3776 * transcoder that already use the clock when we share it.
3777 *
3778 * Note that enable_shared_dpll tries to do the right thing, but
3779 * get_shared_dpll unconditionally resets the pll - we need that to have
3780 * the right LVDS enable sequence. */
3781 intel_enable_shared_dpll(intel_crtc);
3782
3783 /* set transcoder timing, panel must allow it */
3784 assert_panel_unlocked(dev_priv, pipe);
3785 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3786
3787 intel_fdi_normal_train(crtc);
3788
3789 /* For PCH DP, enable TRANS_DP_CTL */
3790 if (HAS_PCH_CPT(dev) && intel_crtc->config.has_dp_encoder) {
3791 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3792 reg = TRANS_DP_CTL(pipe);
3793 temp = I915_READ(reg);
3794 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3795 TRANS_DP_SYNC_MASK |
3796 TRANS_DP_BPC_MASK);
3797 temp |= (TRANS_DP_OUTPUT_ENABLE |
3798 TRANS_DP_ENH_FRAMING);
3799 temp |= bpc << 9; /* same format but at 11:9 */
3800
3801 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3802 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3803 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3804 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3805
3806 switch (intel_trans_dp_port_sel(crtc)) {
3807 case PCH_DP_B:
3808 temp |= TRANS_DP_PORT_SEL_B;
3809 break;
3810 case PCH_DP_C:
3811 temp |= TRANS_DP_PORT_SEL_C;
3812 break;
3813 case PCH_DP_D:
3814 temp |= TRANS_DP_PORT_SEL_D;
3815 break;
3816 default:
3817 BUG();
3818 }
3819
3820 I915_WRITE(reg, temp);
3821 }
3822
3823 ironlake_enable_pch_transcoder(dev_priv, pipe);
3824 }
3825
3826 static void lpt_pch_enable(struct drm_crtc *crtc)
3827 {
3828 struct drm_device *dev = crtc->dev;
3829 struct drm_i915_private *dev_priv = dev->dev_private;
3830 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3831 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3832
3833 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3834
3835 lpt_program_iclkip(crtc);
3836
3837 /* Set transcoder timing. */
3838 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3839
3840 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3841 }
3842
3843 void intel_put_shared_dpll(struct intel_crtc *crtc)
3844 {
3845 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3846
3847 if (pll == NULL)
3848 return;
3849
3850 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
3851 WARN(1, "bad %s crtc mask\n", pll->name);
3852 return;
3853 }
3854
3855 pll->config.crtc_mask &= ~(1 << crtc->pipe);
3856 if (pll->config.crtc_mask == 0) {
3857 WARN_ON(pll->on);
3858 WARN_ON(pll->active);
3859 }
3860
3861 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3862 }
3863
3864 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3865 {
3866 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3867 struct intel_shared_dpll *pll;
3868 enum intel_dpll_id i;
3869
3870 if (HAS_PCH_IBX(dev_priv->dev)) {
3871 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3872 i = (enum intel_dpll_id) crtc->pipe;
3873 pll = &dev_priv->shared_dplls[i];
3874
3875 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3876 crtc->base.base.id, pll->name);
3877
3878 WARN_ON(pll->new_config->crtc_mask);
3879
3880 goto found;
3881 }
3882
3883 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3884 pll = &dev_priv->shared_dplls[i];
3885
3886 /* Only want to check enabled timings first */
3887 if (pll->new_config->crtc_mask == 0)
3888 continue;
3889
3890 if (memcmp(&crtc->new_config->dpll_hw_state,
3891 &pll->new_config->hw_state,
3892 sizeof(pll->new_config->hw_state)) == 0) {
3893 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
3894 crtc->base.base.id, pll->name,
3895 pll->new_config->crtc_mask,
3896 pll->active);
3897 goto found;
3898 }
3899 }
3900
3901 /* Ok no matching timings, maybe there's a free one? */
3902 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3903 pll = &dev_priv->shared_dplls[i];
3904 if (pll->new_config->crtc_mask == 0) {
3905 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3906 crtc->base.base.id, pll->name);
3907 goto found;
3908 }
3909 }
3910
3911 return NULL;
3912
3913 found:
3914 if (pll->new_config->crtc_mask == 0)
3915 pll->new_config->hw_state = crtc->new_config->dpll_hw_state;
3916
3917 crtc->new_config->shared_dpll = i;
3918 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3919 pipe_name(crtc->pipe));
3920
3921 pll->new_config->crtc_mask |= 1 << crtc->pipe;
3922
3923 return pll;
3924 }
3925
3926 /**
3927 * intel_shared_dpll_start_config - start a new PLL staged config
3928 * @dev_priv: DRM device
3929 * @clear_pipes: mask of pipes that will have their PLLs freed
3930 *
3931 * Starts a new PLL staged config, copying the current config but
3932 * releasing the references of pipes specified in clear_pipes.
3933 */
3934 static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
3935 unsigned clear_pipes)
3936 {
3937 struct intel_shared_dpll *pll;
3938 enum intel_dpll_id i;
3939
3940 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3941 pll = &dev_priv->shared_dplls[i];
3942
3943 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
3944 GFP_KERNEL);
3945 if (!pll->new_config)
3946 goto cleanup;
3947
3948 pll->new_config->crtc_mask &= ~clear_pipes;
3949 }
3950
3951 return 0;
3952
3953 cleanup:
3954 while (--i >= 0) {
3955 pll = &dev_priv->shared_dplls[i];
3956 pll->new_config = NULL;
3957 }
3958
3959 return -ENOMEM;
3960 }
3961
3962 static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
3963 {
3964 struct intel_shared_dpll *pll;
3965 enum intel_dpll_id i;
3966
3967 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3968 pll = &dev_priv->shared_dplls[i];
3969
3970 WARN_ON(pll->new_config == &pll->config);
3971
3972 pll->config = *pll->new_config;
3973 kfree(pll->new_config);
3974 pll->new_config = NULL;
3975 }
3976 }
3977
3978 static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
3979 {
3980 struct intel_shared_dpll *pll;
3981 enum intel_dpll_id i;
3982
3983 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3984 pll = &dev_priv->shared_dplls[i];
3985
3986 WARN_ON(pll->new_config == &pll->config);
3987
3988 kfree(pll->new_config);
3989 pll->new_config = NULL;
3990 }
3991 }
3992
3993 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3994 {
3995 struct drm_i915_private *dev_priv = dev->dev_private;
3996 int dslreg = PIPEDSL(pipe);
3997 u32 temp;
3998
3999 temp = I915_READ(dslreg);
4000 udelay(500);
4001 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4002 if (wait_for(I915_READ(dslreg) != temp, 5))
4003 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4004 }
4005 }
4006
4007 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4008 {
4009 struct drm_device *dev = crtc->base.dev;
4010 struct drm_i915_private *dev_priv = dev->dev_private;
4011 int pipe = crtc->pipe;
4012
4013 if (crtc->config.pch_pfit.enabled) {
4014 /* Force use of hard-coded filter coefficients
4015 * as some pre-programmed values are broken,
4016 * e.g. x201.
4017 */
4018 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4019 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4020 PF_PIPE_SEL_IVB(pipe));
4021 else
4022 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4023 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
4024 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
4025 }
4026 }
4027
4028 static void intel_enable_planes(struct drm_crtc *crtc)
4029 {
4030 struct drm_device *dev = crtc->dev;
4031 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4032 struct drm_plane *plane;
4033 struct intel_plane *intel_plane;
4034
4035 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4036 intel_plane = to_intel_plane(plane);
4037 if (intel_plane->pipe == pipe)
4038 intel_plane_restore(&intel_plane->base);
4039 }
4040 }
4041
4042 static void intel_disable_planes(struct drm_crtc *crtc)
4043 {
4044 struct drm_device *dev = crtc->dev;
4045 enum pipe pipe = to_intel_crtc(crtc)->pipe;
4046 struct drm_plane *plane;
4047 struct intel_plane *intel_plane;
4048
4049 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4050 intel_plane = to_intel_plane(plane);
4051 if (intel_plane->pipe == pipe)
4052 intel_plane_disable(&intel_plane->base);
4053 }
4054 }
4055
4056 void hsw_enable_ips(struct intel_crtc *crtc)
4057 {
4058 struct drm_device *dev = crtc->base.dev;
4059 struct drm_i915_private *dev_priv = dev->dev_private;
4060
4061 if (!crtc->config.ips_enabled)
4062 return;
4063
4064 /* We can only enable IPS after we enable a plane and wait for a vblank */
4065 intel_wait_for_vblank(dev, crtc->pipe);
4066
4067 assert_plane_enabled(dev_priv, crtc->plane);
4068 if (IS_BROADWELL(dev)) {
4069 mutex_lock(&dev_priv->rps.hw_lock);
4070 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4071 mutex_unlock(&dev_priv->rps.hw_lock);
4072 /* Quoting Art Runyan: "its not safe to expect any particular
4073 * value in IPS_CTL bit 31 after enabling IPS through the
4074 * mailbox." Moreover, the mailbox may return a bogus state,
4075 * so we need to just enable it and continue on.
4076 */
4077 } else {
4078 I915_WRITE(IPS_CTL, IPS_ENABLE);
4079 /* The bit only becomes 1 in the next vblank, so this wait here
4080 * is essentially intel_wait_for_vblank. If we don't have this
4081 * and don't wait for vblanks until the end of crtc_enable, then
4082 * the HW state readout code will complain that the expected
4083 * IPS_CTL value is not the one we read. */
4084 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4085 DRM_ERROR("Timed out waiting for IPS enable\n");
4086 }
4087 }
4088
4089 void hsw_disable_ips(struct intel_crtc *crtc)
4090 {
4091 struct drm_device *dev = crtc->base.dev;
4092 struct drm_i915_private *dev_priv = dev->dev_private;
4093
4094 if (!crtc->config.ips_enabled)
4095 return;
4096
4097 assert_plane_enabled(dev_priv, crtc->plane);
4098 if (IS_BROADWELL(dev)) {
4099 mutex_lock(&dev_priv->rps.hw_lock);
4100 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4101 mutex_unlock(&dev_priv->rps.hw_lock);
4102 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4103 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4104 DRM_ERROR("Timed out waiting for IPS disable\n");
4105 } else {
4106 I915_WRITE(IPS_CTL, 0);
4107 POSTING_READ(IPS_CTL);
4108 }
4109
4110 /* We need to wait for a vblank before we can disable the plane. */
4111 intel_wait_for_vblank(dev, crtc->pipe);
4112 }
4113
4114 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4115 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4116 {
4117 struct drm_device *dev = crtc->dev;
4118 struct drm_i915_private *dev_priv = dev->dev_private;
4119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4120 enum pipe pipe = intel_crtc->pipe;
4121 int palreg = PALETTE(pipe);
4122 int i;
4123 bool reenable_ips = false;
4124
4125 /* The clocks have to be on to load the palette. */
4126 if (!crtc->enabled || !intel_crtc->active)
4127 return;
4128
4129 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
4130 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
4131 assert_dsi_pll_enabled(dev_priv);
4132 else
4133 assert_pll_enabled(dev_priv, pipe);
4134 }
4135
4136 /* use legacy palette for Ironlake */
4137 if (!HAS_GMCH_DISPLAY(dev))
4138 palreg = LGC_PALETTE(pipe);
4139
4140 /* Workaround : Do not read or write the pipe palette/gamma data while
4141 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4142 */
4143 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
4144 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4145 GAMMA_MODE_MODE_SPLIT)) {
4146 hsw_disable_ips(intel_crtc);
4147 reenable_ips = true;
4148 }
4149
4150 for (i = 0; i < 256; i++) {
4151 I915_WRITE(palreg + 4 * i,
4152 (intel_crtc->lut_r[i] << 16) |
4153 (intel_crtc->lut_g[i] << 8) |
4154 intel_crtc->lut_b[i]);
4155 }
4156
4157 if (reenable_ips)
4158 hsw_enable_ips(intel_crtc);
4159 }
4160
4161 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4162 {
4163 if (!enable && intel_crtc->overlay) {
4164 struct drm_device *dev = intel_crtc->base.dev;
4165 struct drm_i915_private *dev_priv = dev->dev_private;
4166
4167 mutex_lock(&dev->struct_mutex);
4168 dev_priv->mm.interruptible = false;
4169 (void) intel_overlay_switch_off(intel_crtc->overlay);
4170 dev_priv->mm.interruptible = true;
4171 mutex_unlock(&dev->struct_mutex);
4172 }
4173
4174 /* Let userspace switch the overlay on again. In most cases userspace
4175 * has to recompute where to put it anyway.
4176 */
4177 }
4178
4179 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4180 {
4181 struct drm_device *dev = crtc->dev;
4182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4183 int pipe = intel_crtc->pipe;
4184
4185 intel_enable_primary_hw_plane(crtc->primary, crtc);
4186 intel_enable_planes(crtc);
4187 intel_crtc_update_cursor(crtc, true);
4188 intel_crtc_dpms_overlay(intel_crtc, true);
4189
4190 hsw_enable_ips(intel_crtc);
4191
4192 mutex_lock(&dev->struct_mutex);
4193 intel_update_fbc(dev);
4194 mutex_unlock(&dev->struct_mutex);
4195
4196 /*
4197 * FIXME: Once we grow proper nuclear flip support out of this we need
4198 * to compute the mask of flip planes precisely. For the time being
4199 * consider this a flip from a NULL plane.
4200 */
4201 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4202 }
4203
4204 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4205 {
4206 struct drm_device *dev = crtc->dev;
4207 struct drm_i915_private *dev_priv = dev->dev_private;
4208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4209 int pipe = intel_crtc->pipe;
4210 int plane = intel_crtc->plane;
4211
4212 intel_crtc_wait_for_pending_flips(crtc);
4213
4214 if (dev_priv->fbc.plane == plane)
4215 intel_disable_fbc(dev);
4216
4217 hsw_disable_ips(intel_crtc);
4218
4219 intel_crtc_dpms_overlay(intel_crtc, false);
4220 intel_crtc_update_cursor(crtc, false);
4221 intel_disable_planes(crtc);
4222 intel_disable_primary_hw_plane(crtc->primary, crtc);
4223
4224 /*
4225 * FIXME: Once we grow proper nuclear flip support out of this we need
4226 * to compute the mask of flip planes precisely. For the time being
4227 * consider this a flip to a NULL plane.
4228 */
4229 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4230 }
4231
4232 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4233 {
4234 struct drm_device *dev = crtc->dev;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4237 struct intel_encoder *encoder;
4238 int pipe = intel_crtc->pipe;
4239
4240 WARN_ON(!crtc->enabled);
4241
4242 if (intel_crtc->active)
4243 return;
4244
4245 if (intel_crtc->config.has_pch_encoder)
4246 intel_prepare_shared_dpll(intel_crtc);
4247
4248 if (intel_crtc->config.has_dp_encoder)
4249 intel_dp_set_m_n(intel_crtc);
4250
4251 intel_set_pipe_timings(intel_crtc);
4252
4253 if (intel_crtc->config.has_pch_encoder) {
4254 intel_cpu_transcoder_set_m_n(intel_crtc,
4255 &intel_crtc->config.fdi_m_n, NULL);
4256 }
4257
4258 ironlake_set_pipeconf(crtc);
4259
4260 intel_crtc->active = true;
4261
4262 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4263 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4264
4265 for_each_encoder_on_crtc(dev, crtc, encoder)
4266 if (encoder->pre_enable)
4267 encoder->pre_enable(encoder);
4268
4269 if (intel_crtc->config.has_pch_encoder) {
4270 /* Note: FDI PLL enabling _must_ be done before we enable the
4271 * cpu pipes, hence this is separate from all the other fdi/pch
4272 * enabling. */
4273 ironlake_fdi_pll_enable(intel_crtc);
4274 } else {
4275 assert_fdi_tx_disabled(dev_priv, pipe);
4276 assert_fdi_rx_disabled(dev_priv, pipe);
4277 }
4278
4279 ironlake_pfit_enable(intel_crtc);
4280
4281 /*
4282 * On ILK+ LUT must be loaded before the pipe is running but with
4283 * clocks enabled
4284 */
4285 intel_crtc_load_lut(crtc);
4286
4287 intel_update_watermarks(crtc);
4288 intel_enable_pipe(intel_crtc);
4289
4290 if (intel_crtc->config.has_pch_encoder)
4291 ironlake_pch_enable(crtc);
4292
4293 for_each_encoder_on_crtc(dev, crtc, encoder)
4294 encoder->enable(encoder);
4295
4296 if (HAS_PCH_CPT(dev))
4297 cpt_verify_modeset(dev, intel_crtc->pipe);
4298
4299 assert_vblank_disabled(crtc);
4300 drm_crtc_vblank_on(crtc);
4301
4302 intel_crtc_enable_planes(crtc);
4303 }
4304
4305 /* IPS only exists on ULT machines and is tied to pipe A. */
4306 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4307 {
4308 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4309 }
4310
4311 /*
4312 * This implements the workaround described in the "notes" section of the mode
4313 * set sequence documentation. When going from no pipes or single pipe to
4314 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4315 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4316 */
4317 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4318 {
4319 struct drm_device *dev = crtc->base.dev;
4320 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4321
4322 /* We want to get the other_active_crtc only if there's only 1 other
4323 * active crtc. */
4324 for_each_intel_crtc(dev, crtc_it) {
4325 if (!crtc_it->active || crtc_it == crtc)
4326 continue;
4327
4328 if (other_active_crtc)
4329 return;
4330
4331 other_active_crtc = crtc_it;
4332 }
4333 if (!other_active_crtc)
4334 return;
4335
4336 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4337 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4338 }
4339
4340 static void haswell_crtc_enable(struct drm_crtc *crtc)
4341 {
4342 struct drm_device *dev = crtc->dev;
4343 struct drm_i915_private *dev_priv = dev->dev_private;
4344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4345 struct intel_encoder *encoder;
4346 int pipe = intel_crtc->pipe;
4347
4348 WARN_ON(!crtc->enabled);
4349
4350 if (intel_crtc->active)
4351 return;
4352
4353 if (intel_crtc_to_shared_dpll(intel_crtc))
4354 intel_enable_shared_dpll(intel_crtc);
4355
4356 if (intel_crtc->config.has_dp_encoder)
4357 intel_dp_set_m_n(intel_crtc);
4358
4359 intel_set_pipe_timings(intel_crtc);
4360
4361 if (intel_crtc->config.cpu_transcoder != TRANSCODER_EDP) {
4362 I915_WRITE(PIPE_MULT(intel_crtc->config.cpu_transcoder),
4363 intel_crtc->config.pixel_multiplier - 1);
4364 }
4365
4366 if (intel_crtc->config.has_pch_encoder) {
4367 intel_cpu_transcoder_set_m_n(intel_crtc,
4368 &intel_crtc->config.fdi_m_n, NULL);
4369 }
4370
4371 haswell_set_pipeconf(crtc);
4372
4373 intel_set_pipe_csc(crtc);
4374
4375 intel_crtc->active = true;
4376
4377 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4378 for_each_encoder_on_crtc(dev, crtc, encoder)
4379 if (encoder->pre_enable)
4380 encoder->pre_enable(encoder);
4381
4382 if (intel_crtc->config.has_pch_encoder) {
4383 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4384 true);
4385 dev_priv->display.fdi_link_train(crtc);
4386 }
4387
4388 intel_ddi_enable_pipe_clock(intel_crtc);
4389
4390 ironlake_pfit_enable(intel_crtc);
4391
4392 /*
4393 * On ILK+ LUT must be loaded before the pipe is running but with
4394 * clocks enabled
4395 */
4396 intel_crtc_load_lut(crtc);
4397
4398 intel_ddi_set_pipe_settings(crtc);
4399 intel_ddi_enable_transcoder_func(crtc);
4400
4401 intel_update_watermarks(crtc);
4402 intel_enable_pipe(intel_crtc);
4403
4404 if (intel_crtc->config.has_pch_encoder)
4405 lpt_pch_enable(crtc);
4406
4407 if (intel_crtc->config.dp_encoder_is_mst)
4408 intel_ddi_set_vc_payload_alloc(crtc, true);
4409
4410 for_each_encoder_on_crtc(dev, crtc, encoder) {
4411 encoder->enable(encoder);
4412 intel_opregion_notify_encoder(encoder, true);
4413 }
4414
4415 assert_vblank_disabled(crtc);
4416 drm_crtc_vblank_on(crtc);
4417
4418 /* If we change the relative order between pipe/planes enabling, we need
4419 * to change the workaround. */
4420 haswell_mode_set_planes_workaround(intel_crtc);
4421 intel_crtc_enable_planes(crtc);
4422 }
4423
4424 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4425 {
4426 struct drm_device *dev = crtc->base.dev;
4427 struct drm_i915_private *dev_priv = dev->dev_private;
4428 int pipe = crtc->pipe;
4429
4430 /* To avoid upsetting the power well on haswell only disable the pfit if
4431 * it's in use. The hw state code will make sure we get this right. */
4432 if (crtc->config.pch_pfit.enabled) {
4433 I915_WRITE(PF_CTL(pipe), 0);
4434 I915_WRITE(PF_WIN_POS(pipe), 0);
4435 I915_WRITE(PF_WIN_SZ(pipe), 0);
4436 }
4437 }
4438
4439 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4440 {
4441 struct drm_device *dev = crtc->dev;
4442 struct drm_i915_private *dev_priv = dev->dev_private;
4443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4444 struct intel_encoder *encoder;
4445 int pipe = intel_crtc->pipe;
4446 u32 reg, temp;
4447
4448 if (!intel_crtc->active)
4449 return;
4450
4451 intel_crtc_disable_planes(crtc);
4452
4453 drm_crtc_vblank_off(crtc);
4454 assert_vblank_disabled(crtc);
4455
4456 for_each_encoder_on_crtc(dev, crtc, encoder)
4457 encoder->disable(encoder);
4458
4459 if (intel_crtc->config.has_pch_encoder)
4460 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4461
4462 intel_disable_pipe(intel_crtc);
4463
4464 ironlake_pfit_disable(intel_crtc);
4465
4466 for_each_encoder_on_crtc(dev, crtc, encoder)
4467 if (encoder->post_disable)
4468 encoder->post_disable(encoder);
4469
4470 if (intel_crtc->config.has_pch_encoder) {
4471 ironlake_fdi_disable(crtc);
4472
4473 ironlake_disable_pch_transcoder(dev_priv, pipe);
4474 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4475
4476 if (HAS_PCH_CPT(dev)) {
4477 /* disable TRANS_DP_CTL */
4478 reg = TRANS_DP_CTL(pipe);
4479 temp = I915_READ(reg);
4480 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4481 TRANS_DP_PORT_SEL_MASK);
4482 temp |= TRANS_DP_PORT_SEL_NONE;
4483 I915_WRITE(reg, temp);
4484
4485 /* disable DPLL_SEL */
4486 temp = I915_READ(PCH_DPLL_SEL);
4487 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4488 I915_WRITE(PCH_DPLL_SEL, temp);
4489 }
4490
4491 /* disable PCH DPLL */
4492 intel_disable_shared_dpll(intel_crtc);
4493
4494 ironlake_fdi_pll_disable(intel_crtc);
4495 }
4496
4497 intel_crtc->active = false;
4498 intel_update_watermarks(crtc);
4499
4500 mutex_lock(&dev->struct_mutex);
4501 intel_update_fbc(dev);
4502 mutex_unlock(&dev->struct_mutex);
4503 }
4504
4505 static void haswell_crtc_disable(struct drm_crtc *crtc)
4506 {
4507 struct drm_device *dev = crtc->dev;
4508 struct drm_i915_private *dev_priv = dev->dev_private;
4509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4510 struct intel_encoder *encoder;
4511 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4512
4513 if (!intel_crtc->active)
4514 return;
4515
4516 intel_crtc_disable_planes(crtc);
4517
4518 drm_crtc_vblank_off(crtc);
4519 assert_vblank_disabled(crtc);
4520
4521 for_each_encoder_on_crtc(dev, crtc, encoder) {
4522 intel_opregion_notify_encoder(encoder, false);
4523 encoder->disable(encoder);
4524 }
4525
4526 if (intel_crtc->config.has_pch_encoder)
4527 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4528 false);
4529 intel_disable_pipe(intel_crtc);
4530
4531 if (intel_crtc->config.dp_encoder_is_mst)
4532 intel_ddi_set_vc_payload_alloc(crtc, false);
4533
4534 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4535
4536 ironlake_pfit_disable(intel_crtc);
4537
4538 intel_ddi_disable_pipe_clock(intel_crtc);
4539
4540 if (intel_crtc->config.has_pch_encoder) {
4541 lpt_disable_pch_transcoder(dev_priv);
4542 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4543 true);
4544 intel_ddi_fdi_disable(crtc);
4545 }
4546
4547 for_each_encoder_on_crtc(dev, crtc, encoder)
4548 if (encoder->post_disable)
4549 encoder->post_disable(encoder);
4550
4551 intel_crtc->active = false;
4552 intel_update_watermarks(crtc);
4553
4554 mutex_lock(&dev->struct_mutex);
4555 intel_update_fbc(dev);
4556 mutex_unlock(&dev->struct_mutex);
4557
4558 if (intel_crtc_to_shared_dpll(intel_crtc))
4559 intel_disable_shared_dpll(intel_crtc);
4560 }
4561
4562 static void ironlake_crtc_off(struct drm_crtc *crtc)
4563 {
4564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4565 intel_put_shared_dpll(intel_crtc);
4566 }
4567
4568
4569 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4570 {
4571 struct drm_device *dev = crtc->base.dev;
4572 struct drm_i915_private *dev_priv = dev->dev_private;
4573 struct intel_crtc_config *pipe_config = &crtc->config;
4574
4575 if (!crtc->config.gmch_pfit.control)
4576 return;
4577
4578 /*
4579 * The panel fitter should only be adjusted whilst the pipe is disabled,
4580 * according to register description and PRM.
4581 */
4582 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4583 assert_pipe_disabled(dev_priv, crtc->pipe);
4584
4585 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4586 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4587
4588 /* Border color in case we don't scale up to the full screen. Black by
4589 * default, change to something else for debugging. */
4590 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4591 }
4592
4593 static enum intel_display_power_domain port_to_power_domain(enum port port)
4594 {
4595 switch (port) {
4596 case PORT_A:
4597 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4598 case PORT_B:
4599 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4600 case PORT_C:
4601 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4602 case PORT_D:
4603 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4604 default:
4605 WARN_ON_ONCE(1);
4606 return POWER_DOMAIN_PORT_OTHER;
4607 }
4608 }
4609
4610 #define for_each_power_domain(domain, mask) \
4611 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4612 if ((1 << (domain)) & (mask))
4613
4614 enum intel_display_power_domain
4615 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4616 {
4617 struct drm_device *dev = intel_encoder->base.dev;
4618 struct intel_digital_port *intel_dig_port;
4619
4620 switch (intel_encoder->type) {
4621 case INTEL_OUTPUT_UNKNOWN:
4622 /* Only DDI platforms should ever use this output type */
4623 WARN_ON_ONCE(!HAS_DDI(dev));
4624 case INTEL_OUTPUT_DISPLAYPORT:
4625 case INTEL_OUTPUT_HDMI:
4626 case INTEL_OUTPUT_EDP:
4627 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4628 return port_to_power_domain(intel_dig_port->port);
4629 case INTEL_OUTPUT_DP_MST:
4630 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4631 return port_to_power_domain(intel_dig_port->port);
4632 case INTEL_OUTPUT_ANALOG:
4633 return POWER_DOMAIN_PORT_CRT;
4634 case INTEL_OUTPUT_DSI:
4635 return POWER_DOMAIN_PORT_DSI;
4636 default:
4637 return POWER_DOMAIN_PORT_OTHER;
4638 }
4639 }
4640
4641 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4642 {
4643 struct drm_device *dev = crtc->dev;
4644 struct intel_encoder *intel_encoder;
4645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4646 enum pipe pipe = intel_crtc->pipe;
4647 unsigned long mask;
4648 enum transcoder transcoder;
4649
4650 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4651
4652 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4653 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4654 if (intel_crtc->config.pch_pfit.enabled ||
4655 intel_crtc->config.pch_pfit.force_thru)
4656 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4657
4658 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4659 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4660
4661 return mask;
4662 }
4663
4664 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4665 {
4666 struct drm_i915_private *dev_priv = dev->dev_private;
4667 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4668 struct intel_crtc *crtc;
4669
4670 /*
4671 * First get all needed power domains, then put all unneeded, to avoid
4672 * any unnecessary toggling of the power wells.
4673 */
4674 for_each_intel_crtc(dev, crtc) {
4675 enum intel_display_power_domain domain;
4676
4677 if (!crtc->base.enabled)
4678 continue;
4679
4680 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4681
4682 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4683 intel_display_power_get(dev_priv, domain);
4684 }
4685
4686 for_each_intel_crtc(dev, crtc) {
4687 enum intel_display_power_domain domain;
4688
4689 for_each_power_domain(domain, crtc->enabled_power_domains)
4690 intel_display_power_put(dev_priv, domain);
4691
4692 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4693 }
4694
4695 intel_display_set_init_power(dev_priv, false);
4696 }
4697
4698 /* returns HPLL frequency in kHz */
4699 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
4700 {
4701 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4702
4703 /* Obtain SKU information */
4704 mutex_lock(&dev_priv->dpio_lock);
4705 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4706 CCK_FUSE_HPLL_FREQ_MASK;
4707 mutex_unlock(&dev_priv->dpio_lock);
4708
4709 return vco_freq[hpll_freq] * 1000;
4710 }
4711
4712 static void vlv_update_cdclk(struct drm_device *dev)
4713 {
4714 struct drm_i915_private *dev_priv = dev->dev_private;
4715
4716 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
4717 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
4718 dev_priv->vlv_cdclk_freq);
4719
4720 /*
4721 * Program the gmbus_freq based on the cdclk frequency.
4722 * BSpec erroneously claims we should aim for 4MHz, but
4723 * in fact 1MHz is the correct frequency.
4724 */
4725 I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq);
4726 }
4727
4728 /* Adjust CDclk dividers to allow high res or save power if possible */
4729 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4730 {
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732 u32 val, cmd;
4733
4734 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4735
4736 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
4737 cmd = 2;
4738 else if (cdclk == 266667)
4739 cmd = 1;
4740 else
4741 cmd = 0;
4742
4743 mutex_lock(&dev_priv->rps.hw_lock);
4744 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4745 val &= ~DSPFREQGUAR_MASK;
4746 val |= (cmd << DSPFREQGUAR_SHIFT);
4747 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4748 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4749 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4750 50)) {
4751 DRM_ERROR("timed out waiting for CDclk change\n");
4752 }
4753 mutex_unlock(&dev_priv->rps.hw_lock);
4754
4755 if (cdclk == 400000) {
4756 u32 divider, vco;
4757
4758 vco = valleyview_get_vco(dev_priv);
4759 divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1;
4760
4761 mutex_lock(&dev_priv->dpio_lock);
4762 /* adjust cdclk divider */
4763 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4764 val &= ~DISPLAY_FREQUENCY_VALUES;
4765 val |= divider;
4766 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4767
4768 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
4769 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
4770 50))
4771 DRM_ERROR("timed out waiting for CDclk change\n");
4772 mutex_unlock(&dev_priv->dpio_lock);
4773 }
4774
4775 mutex_lock(&dev_priv->dpio_lock);
4776 /* adjust self-refresh exit latency value */
4777 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4778 val &= ~0x7f;
4779
4780 /*
4781 * For high bandwidth configs, we set a higher latency in the bunit
4782 * so that the core display fetch happens in time to avoid underruns.
4783 */
4784 if (cdclk == 400000)
4785 val |= 4500 / 250; /* 4.5 usec */
4786 else
4787 val |= 3000 / 250; /* 3.0 usec */
4788 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4789 mutex_unlock(&dev_priv->dpio_lock);
4790
4791 vlv_update_cdclk(dev);
4792 }
4793
4794 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
4795 {
4796 struct drm_i915_private *dev_priv = dev->dev_private;
4797 u32 val, cmd;
4798
4799 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
4800
4801 switch (cdclk) {
4802 case 400000:
4803 cmd = 3;
4804 break;
4805 case 333333:
4806 case 320000:
4807 cmd = 2;
4808 break;
4809 case 266667:
4810 cmd = 1;
4811 break;
4812 case 200000:
4813 cmd = 0;
4814 break;
4815 default:
4816 WARN_ON(1);
4817 return;
4818 }
4819
4820 mutex_lock(&dev_priv->rps.hw_lock);
4821 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4822 val &= ~DSPFREQGUAR_MASK_CHV;
4823 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
4824 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4825 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4826 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
4827 50)) {
4828 DRM_ERROR("timed out waiting for CDclk change\n");
4829 }
4830 mutex_unlock(&dev_priv->rps.hw_lock);
4831
4832 vlv_update_cdclk(dev);
4833 }
4834
4835 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4836 int max_pixclk)
4837 {
4838 int vco = valleyview_get_vco(dev_priv);
4839 int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000;
4840
4841 /* FIXME: Punit isn't quite ready yet */
4842 if (IS_CHERRYVIEW(dev_priv->dev))
4843 return 400000;
4844
4845 /*
4846 * Really only a few cases to deal with, as only 4 CDclks are supported:
4847 * 200MHz
4848 * 267MHz
4849 * 320/333MHz (depends on HPLL freq)
4850 * 400MHz
4851 * So we check to see whether we're above 90% of the lower bin and
4852 * adjust if needed.
4853 *
4854 * We seem to get an unstable or solid color picture at 200MHz.
4855 * Not sure what's wrong. For now use 200MHz only when all pipes
4856 * are off.
4857 */
4858 if (max_pixclk > freq_320*9/10)
4859 return 400000;
4860 else if (max_pixclk > 266667*9/10)
4861 return freq_320;
4862 else if (max_pixclk > 0)
4863 return 266667;
4864 else
4865 return 200000;
4866 }
4867
4868 /* compute the max pixel clock for new configuration */
4869 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4870 {
4871 struct drm_device *dev = dev_priv->dev;
4872 struct intel_crtc *intel_crtc;
4873 int max_pixclk = 0;
4874
4875 for_each_intel_crtc(dev, intel_crtc) {
4876 if (intel_crtc->new_enabled)
4877 max_pixclk = max(max_pixclk,
4878 intel_crtc->new_config->adjusted_mode.crtc_clock);
4879 }
4880
4881 return max_pixclk;
4882 }
4883
4884 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4885 unsigned *prepare_pipes)
4886 {
4887 struct drm_i915_private *dev_priv = dev->dev_private;
4888 struct intel_crtc *intel_crtc;
4889 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4890
4891 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4892 dev_priv->vlv_cdclk_freq)
4893 return;
4894
4895 /* disable/enable all currently active pipes while we change cdclk */
4896 for_each_intel_crtc(dev, intel_crtc)
4897 if (intel_crtc->base.enabled)
4898 *prepare_pipes |= (1 << intel_crtc->pipe);
4899 }
4900
4901 static void valleyview_modeset_global_resources(struct drm_device *dev)
4902 {
4903 struct drm_i915_private *dev_priv = dev->dev_private;
4904 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4905 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4906
4907 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
4908 if (IS_CHERRYVIEW(dev))
4909 cherryview_set_cdclk(dev, req_cdclk);
4910 else
4911 valleyview_set_cdclk(dev, req_cdclk);
4912 }
4913
4914 modeset_update_crtc_power_domains(dev);
4915 }
4916
4917 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4918 {
4919 struct drm_device *dev = crtc->dev;
4920 struct drm_i915_private *dev_priv = to_i915(dev);
4921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4922 struct intel_encoder *encoder;
4923 int pipe = intel_crtc->pipe;
4924 bool is_dsi;
4925
4926 WARN_ON(!crtc->enabled);
4927
4928 if (intel_crtc->active)
4929 return;
4930
4931 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
4932
4933 if (!is_dsi) {
4934 if (IS_CHERRYVIEW(dev))
4935 chv_prepare_pll(intel_crtc, &intel_crtc->config);
4936 else
4937 vlv_prepare_pll(intel_crtc, &intel_crtc->config);
4938 }
4939
4940 if (intel_crtc->config.has_dp_encoder)
4941 intel_dp_set_m_n(intel_crtc);
4942
4943 intel_set_pipe_timings(intel_crtc);
4944
4945 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
4946 struct drm_i915_private *dev_priv = dev->dev_private;
4947
4948 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
4949 I915_WRITE(CHV_CANVAS(pipe), 0);
4950 }
4951
4952 i9xx_set_pipeconf(intel_crtc);
4953
4954 intel_crtc->active = true;
4955
4956 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957
4958 for_each_encoder_on_crtc(dev, crtc, encoder)
4959 if (encoder->pre_pll_enable)
4960 encoder->pre_pll_enable(encoder);
4961
4962 if (!is_dsi) {
4963 if (IS_CHERRYVIEW(dev))
4964 chv_enable_pll(intel_crtc, &intel_crtc->config);
4965 else
4966 vlv_enable_pll(intel_crtc, &intel_crtc->config);
4967 }
4968
4969 for_each_encoder_on_crtc(dev, crtc, encoder)
4970 if (encoder->pre_enable)
4971 encoder->pre_enable(encoder);
4972
4973 i9xx_pfit_enable(intel_crtc);
4974
4975 intel_crtc_load_lut(crtc);
4976
4977 intel_update_watermarks(crtc);
4978 intel_enable_pipe(intel_crtc);
4979
4980 for_each_encoder_on_crtc(dev, crtc, encoder)
4981 encoder->enable(encoder);
4982
4983 assert_vblank_disabled(crtc);
4984 drm_crtc_vblank_on(crtc);
4985
4986 intel_crtc_enable_planes(crtc);
4987
4988 /* Underruns don't raise interrupts, so check manually. */
4989 i9xx_check_fifo_underruns(dev_priv);
4990 }
4991
4992 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4993 {
4994 struct drm_device *dev = crtc->base.dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996
4997 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4998 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4999 }
5000
5001 static void i9xx_crtc_enable(struct drm_crtc *crtc)
5002 {
5003 struct drm_device *dev = crtc->dev;
5004 struct drm_i915_private *dev_priv = to_i915(dev);
5005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5006 struct intel_encoder *encoder;
5007 int pipe = intel_crtc->pipe;
5008
5009 WARN_ON(!crtc->enabled);
5010
5011 if (intel_crtc->active)
5012 return;
5013
5014 i9xx_set_pll_dividers(intel_crtc);
5015
5016 if (intel_crtc->config.has_dp_encoder)
5017 intel_dp_set_m_n(intel_crtc);
5018
5019 intel_set_pipe_timings(intel_crtc);
5020
5021 i9xx_set_pipeconf(intel_crtc);
5022
5023 intel_crtc->active = true;
5024
5025 if (!IS_GEN2(dev))
5026 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5027
5028 for_each_encoder_on_crtc(dev, crtc, encoder)
5029 if (encoder->pre_enable)
5030 encoder->pre_enable(encoder);
5031
5032 i9xx_enable_pll(intel_crtc);
5033
5034 i9xx_pfit_enable(intel_crtc);
5035
5036 intel_crtc_load_lut(crtc);
5037
5038 intel_update_watermarks(crtc);
5039 intel_enable_pipe(intel_crtc);
5040
5041 for_each_encoder_on_crtc(dev, crtc, encoder)
5042 encoder->enable(encoder);
5043
5044 assert_vblank_disabled(crtc);
5045 drm_crtc_vblank_on(crtc);
5046
5047 intel_crtc_enable_planes(crtc);
5048
5049 /*
5050 * Gen2 reports pipe underruns whenever all planes are disabled.
5051 * So don't enable underrun reporting before at least some planes
5052 * are enabled.
5053 * FIXME: Need to fix the logic to work when we turn off all planes
5054 * but leave the pipe running.
5055 */
5056 if (IS_GEN2(dev))
5057 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5058
5059 /* Underruns don't raise interrupts, so check manually. */
5060 i9xx_check_fifo_underruns(dev_priv);
5061 }
5062
5063 static void i9xx_pfit_disable(struct intel_crtc *crtc)
5064 {
5065 struct drm_device *dev = crtc->base.dev;
5066 struct drm_i915_private *dev_priv = dev->dev_private;
5067
5068 if (!crtc->config.gmch_pfit.control)
5069 return;
5070
5071 assert_pipe_disabled(dev_priv, crtc->pipe);
5072
5073 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5074 I915_READ(PFIT_CONTROL));
5075 I915_WRITE(PFIT_CONTROL, 0);
5076 }
5077
5078 static void i9xx_crtc_disable(struct drm_crtc *crtc)
5079 {
5080 struct drm_device *dev = crtc->dev;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5083 struct intel_encoder *encoder;
5084 int pipe = intel_crtc->pipe;
5085
5086 if (!intel_crtc->active)
5087 return;
5088
5089 /*
5090 * Gen2 reports pipe underruns whenever all planes are disabled.
5091 * So diasble underrun reporting before all the planes get disabled.
5092 * FIXME: Need to fix the logic to work when we turn off all planes
5093 * but leave the pipe running.
5094 */
5095 if (IS_GEN2(dev))
5096 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5097
5098 /*
5099 * Vblank time updates from the shadow to live plane control register
5100 * are blocked if the memory self-refresh mode is active at that
5101 * moment. So to make sure the plane gets truly disabled, disable
5102 * first the self-refresh mode. The self-refresh enable bit in turn
5103 * will be checked/applied by the HW only at the next frame start
5104 * event which is after the vblank start event, so we need to have a
5105 * wait-for-vblank between disabling the plane and the pipe.
5106 */
5107 intel_set_memory_cxsr(dev_priv, false);
5108 intel_crtc_disable_planes(crtc);
5109
5110 /*
5111 * On gen2 planes are double buffered but the pipe isn't, so we must
5112 * wait for planes to fully turn off before disabling the pipe.
5113 * We also need to wait on all gmch platforms because of the
5114 * self-refresh mode constraint explained above.
5115 */
5116 intel_wait_for_vblank(dev, pipe);
5117
5118 drm_crtc_vblank_off(crtc);
5119 assert_vblank_disabled(crtc);
5120
5121 for_each_encoder_on_crtc(dev, crtc, encoder)
5122 encoder->disable(encoder);
5123
5124 intel_disable_pipe(intel_crtc);
5125
5126 i9xx_pfit_disable(intel_crtc);
5127
5128 for_each_encoder_on_crtc(dev, crtc, encoder)
5129 if (encoder->post_disable)
5130 encoder->post_disable(encoder);
5131
5132 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
5133 if (IS_CHERRYVIEW(dev))
5134 chv_disable_pll(dev_priv, pipe);
5135 else if (IS_VALLEYVIEW(dev))
5136 vlv_disable_pll(dev_priv, pipe);
5137 else
5138 i9xx_disable_pll(intel_crtc);
5139 }
5140
5141 if (!IS_GEN2(dev))
5142 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5143
5144 intel_crtc->active = false;
5145 intel_update_watermarks(crtc);
5146
5147 mutex_lock(&dev->struct_mutex);
5148 intel_update_fbc(dev);
5149 mutex_unlock(&dev->struct_mutex);
5150 }
5151
5152 static void i9xx_crtc_off(struct drm_crtc *crtc)
5153 {
5154 }
5155
5156 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
5157 bool enabled)
5158 {
5159 struct drm_device *dev = crtc->dev;
5160 struct drm_i915_master_private *master_priv;
5161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5162 int pipe = intel_crtc->pipe;
5163
5164 if (!dev->primary->master)
5165 return;
5166
5167 master_priv = dev->primary->master->driver_priv;
5168 if (!master_priv->sarea_priv)
5169 return;
5170
5171 switch (pipe) {
5172 case 0:
5173 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
5174 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
5175 break;
5176 case 1:
5177 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
5178 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
5179 break;
5180 default:
5181 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
5182 break;
5183 }
5184 }
5185
5186 /* Master function to enable/disable CRTC and corresponding power wells */
5187 void intel_crtc_control(struct drm_crtc *crtc, bool enable)
5188 {
5189 struct drm_device *dev = crtc->dev;
5190 struct drm_i915_private *dev_priv = dev->dev_private;
5191 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5192 enum intel_display_power_domain domain;
5193 unsigned long domains;
5194
5195 if (enable) {
5196 if (!intel_crtc->active) {
5197 domains = get_crtc_power_domains(crtc);
5198 for_each_power_domain(domain, domains)
5199 intel_display_power_get(dev_priv, domain);
5200 intel_crtc->enabled_power_domains = domains;
5201
5202 dev_priv->display.crtc_enable(crtc);
5203 }
5204 } else {
5205 if (intel_crtc->active) {
5206 dev_priv->display.crtc_disable(crtc);
5207
5208 domains = intel_crtc->enabled_power_domains;
5209 for_each_power_domain(domain, domains)
5210 intel_display_power_put(dev_priv, domain);
5211 intel_crtc->enabled_power_domains = 0;
5212 }
5213 }
5214 }
5215
5216 /**
5217 * Sets the power management mode of the pipe and plane.
5218 */
5219 void intel_crtc_update_dpms(struct drm_crtc *crtc)
5220 {
5221 struct drm_device *dev = crtc->dev;
5222 struct intel_encoder *intel_encoder;
5223 bool enable = false;
5224
5225 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5226 enable |= intel_encoder->connectors_active;
5227
5228 intel_crtc_control(crtc, enable);
5229
5230 intel_crtc_update_sarea(crtc, enable);
5231 }
5232
5233 static void intel_crtc_disable(struct drm_crtc *crtc)
5234 {
5235 struct drm_device *dev = crtc->dev;
5236 struct drm_connector *connector;
5237 struct drm_i915_private *dev_priv = dev->dev_private;
5238 struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb);
5239 enum pipe pipe = to_intel_crtc(crtc)->pipe;
5240
5241 /* crtc should still be enabled when we disable it. */
5242 WARN_ON(!crtc->enabled);
5243
5244 dev_priv->display.crtc_disable(crtc);
5245 intel_crtc_update_sarea(crtc, false);
5246 dev_priv->display.off(crtc);
5247
5248 if (crtc->primary->fb) {
5249 mutex_lock(&dev->struct_mutex);
5250 intel_unpin_fb_obj(old_obj);
5251 i915_gem_track_fb(old_obj, NULL,
5252 INTEL_FRONTBUFFER_PRIMARY(pipe));
5253 mutex_unlock(&dev->struct_mutex);
5254 crtc->primary->fb = NULL;
5255 }
5256
5257 /* Update computed state. */
5258 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5259 if (!connector->encoder || !connector->encoder->crtc)
5260 continue;
5261
5262 if (connector->encoder->crtc != crtc)
5263 continue;
5264
5265 connector->dpms = DRM_MODE_DPMS_OFF;
5266 to_intel_encoder(connector->encoder)->connectors_active = false;
5267 }
5268 }
5269
5270 void intel_encoder_destroy(struct drm_encoder *encoder)
5271 {
5272 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
5273
5274 drm_encoder_cleanup(encoder);
5275 kfree(intel_encoder);
5276 }
5277
5278 /* Simple dpms helper for encoders with just one connector, no cloning and only
5279 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5280 * state of the entire output pipe. */
5281 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
5282 {
5283 if (mode == DRM_MODE_DPMS_ON) {
5284 encoder->connectors_active = true;
5285
5286 intel_crtc_update_dpms(encoder->base.crtc);
5287 } else {
5288 encoder->connectors_active = false;
5289
5290 intel_crtc_update_dpms(encoder->base.crtc);
5291 }
5292 }
5293
5294 /* Cross check the actual hw state with our own modeset state tracking (and it's
5295 * internal consistency). */
5296 static void intel_connector_check_state(struct intel_connector *connector)
5297 {
5298 if (connector->get_hw_state(connector)) {
5299 struct intel_encoder *encoder = connector->encoder;
5300 struct drm_crtc *crtc;
5301 bool encoder_enabled;
5302 enum pipe pipe;
5303
5304 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5305 connector->base.base.id,
5306 connector->base.name);
5307
5308 /* there is no real hw state for MST connectors */
5309 if (connector->mst_port)
5310 return;
5311
5312 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5313 "wrong connector dpms state\n");
5314 WARN(connector->base.encoder != &encoder->base,
5315 "active connector not linked to encoder\n");
5316
5317 if (encoder) {
5318 WARN(!encoder->connectors_active,
5319 "encoder->connectors_active not set\n");
5320
5321 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5322 WARN(!encoder_enabled, "encoder not enabled\n");
5323 if (WARN_ON(!encoder->base.crtc))
5324 return;
5325
5326 crtc = encoder->base.crtc;
5327
5328 WARN(!crtc->enabled, "crtc not enabled\n");
5329 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5330 WARN(pipe != to_intel_crtc(crtc)->pipe,
5331 "encoder active on the wrong pipe\n");
5332 }
5333 }
5334 }
5335
5336 /* Even simpler default implementation, if there's really no special case to
5337 * consider. */
5338 void intel_connector_dpms(struct drm_connector *connector, int mode)
5339 {
5340 /* All the simple cases only support two dpms states. */
5341 if (mode != DRM_MODE_DPMS_ON)
5342 mode = DRM_MODE_DPMS_OFF;
5343
5344 if (mode == connector->dpms)
5345 return;
5346
5347 connector->dpms = mode;
5348
5349 /* Only need to change hw state when actually enabled */
5350 if (connector->encoder)
5351 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5352
5353 intel_modeset_check_state(connector->dev);
5354 }
5355
5356 /* Simple connector->get_hw_state implementation for encoders that support only
5357 * one connector and no cloning and hence the encoder state determines the state
5358 * of the connector. */
5359 bool intel_connector_get_hw_state(struct intel_connector *connector)
5360 {
5361 enum pipe pipe = 0;
5362 struct intel_encoder *encoder = connector->encoder;
5363
5364 return encoder->get_hw_state(encoder, &pipe);
5365 }
5366
5367 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5368 struct intel_crtc_config *pipe_config)
5369 {
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5371 struct intel_crtc *pipe_B_crtc =
5372 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5373
5374 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5375 pipe_name(pipe), pipe_config->fdi_lanes);
5376 if (pipe_config->fdi_lanes > 4) {
5377 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5378 pipe_name(pipe), pipe_config->fdi_lanes);
5379 return false;
5380 }
5381
5382 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5383 if (pipe_config->fdi_lanes > 2) {
5384 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5385 pipe_config->fdi_lanes);
5386 return false;
5387 } else {
5388 return true;
5389 }
5390 }
5391
5392 if (INTEL_INFO(dev)->num_pipes == 2)
5393 return true;
5394
5395 /* Ivybridge 3 pipe is really complicated */
5396 switch (pipe) {
5397 case PIPE_A:
5398 return true;
5399 case PIPE_B:
5400 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5401 pipe_config->fdi_lanes > 2) {
5402 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5403 pipe_name(pipe), pipe_config->fdi_lanes);
5404 return false;
5405 }
5406 return true;
5407 case PIPE_C:
5408 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5409 pipe_B_crtc->config.fdi_lanes <= 2) {
5410 if (pipe_config->fdi_lanes > 2) {
5411 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5412 pipe_name(pipe), pipe_config->fdi_lanes);
5413 return false;
5414 }
5415 } else {
5416 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5417 return false;
5418 }
5419 return true;
5420 default:
5421 BUG();
5422 }
5423 }
5424
5425 #define RETRY 1
5426 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5427 struct intel_crtc_config *pipe_config)
5428 {
5429 struct drm_device *dev = intel_crtc->base.dev;
5430 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5431 int lane, link_bw, fdi_dotclock;
5432 bool setup_ok, needs_recompute = false;
5433
5434 retry:
5435 /* FDI is a binary signal running at ~2.7GHz, encoding
5436 * each output octet as 10 bits. The actual frequency
5437 * is stored as a divider into a 100MHz clock, and the
5438 * mode pixel clock is stored in units of 1KHz.
5439 * Hence the bw of each lane in terms of the mode signal
5440 * is:
5441 */
5442 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5443
5444 fdi_dotclock = adjusted_mode->crtc_clock;
5445
5446 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5447 pipe_config->pipe_bpp);
5448
5449 pipe_config->fdi_lanes = lane;
5450
5451 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5452 link_bw, &pipe_config->fdi_m_n);
5453
5454 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5455 intel_crtc->pipe, pipe_config);
5456 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5457 pipe_config->pipe_bpp -= 2*3;
5458 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5459 pipe_config->pipe_bpp);
5460 needs_recompute = true;
5461 pipe_config->bw_constrained = true;
5462
5463 goto retry;
5464 }
5465
5466 if (needs_recompute)
5467 return RETRY;
5468
5469 return setup_ok ? 0 : -EINVAL;
5470 }
5471
5472 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5473 struct intel_crtc_config *pipe_config)
5474 {
5475 pipe_config->ips_enabled = i915.enable_ips &&
5476 hsw_crtc_supports_ips(crtc) &&
5477 pipe_config->pipe_bpp <= 24;
5478 }
5479
5480 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5481 struct intel_crtc_config *pipe_config)
5482 {
5483 struct drm_device *dev = crtc->base.dev;
5484 struct drm_i915_private *dev_priv = dev->dev_private;
5485 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5486
5487 /* FIXME should check pixel clock limits on all platforms */
5488 if (INTEL_INFO(dev)->gen < 4) {
5489 int clock_limit =
5490 dev_priv->display.get_display_clock_speed(dev);
5491
5492 /*
5493 * Enable pixel doubling when the dot clock
5494 * is > 90% of the (display) core speed.
5495 *
5496 * GDG double wide on either pipe,
5497 * otherwise pipe A only.
5498 */
5499 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5500 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5501 clock_limit *= 2;
5502 pipe_config->double_wide = true;
5503 }
5504
5505 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5506 return -EINVAL;
5507 }
5508
5509 /*
5510 * Pipe horizontal size must be even in:
5511 * - DVO ganged mode
5512 * - LVDS dual channel mode
5513 * - Double wide pipe
5514 */
5515 if ((intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5516 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5517 pipe_config->pipe_src_w &= ~1;
5518
5519 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5520 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5521 */
5522 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5523 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5524 return -EINVAL;
5525
5526 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5527 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5528 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5529 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5530 * for lvds. */
5531 pipe_config->pipe_bpp = 8*3;
5532 }
5533
5534 if (HAS_IPS(dev))
5535 hsw_compute_ips_config(crtc, pipe_config);
5536
5537 if (pipe_config->has_pch_encoder)
5538 return ironlake_fdi_compute_config(crtc, pipe_config);
5539
5540 return 0;
5541 }
5542
5543 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5544 {
5545 struct drm_i915_private *dev_priv = dev->dev_private;
5546 int vco = valleyview_get_vco(dev_priv);
5547 u32 val;
5548 int divider;
5549
5550 /* FIXME: Punit isn't quite ready yet */
5551 if (IS_CHERRYVIEW(dev))
5552 return 400000;
5553
5554 mutex_lock(&dev_priv->dpio_lock);
5555 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5556 mutex_unlock(&dev_priv->dpio_lock);
5557
5558 divider = val & DISPLAY_FREQUENCY_VALUES;
5559
5560 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5561 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5562 "cdclk change in progress\n");
5563
5564 return DIV_ROUND_CLOSEST(vco << 1, divider + 1);
5565 }
5566
5567 static int i945_get_display_clock_speed(struct drm_device *dev)
5568 {
5569 return 400000;
5570 }
5571
5572 static int i915_get_display_clock_speed(struct drm_device *dev)
5573 {
5574 return 333000;
5575 }
5576
5577 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5578 {
5579 return 200000;
5580 }
5581
5582 static int pnv_get_display_clock_speed(struct drm_device *dev)
5583 {
5584 u16 gcfgc = 0;
5585
5586 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5587
5588 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5589 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5590 return 267000;
5591 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5592 return 333000;
5593 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5594 return 444000;
5595 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5596 return 200000;
5597 default:
5598 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5599 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5600 return 133000;
5601 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5602 return 167000;
5603 }
5604 }
5605
5606 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5607 {
5608 u16 gcfgc = 0;
5609
5610 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5611
5612 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5613 return 133000;
5614 else {
5615 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5616 case GC_DISPLAY_CLOCK_333_MHZ:
5617 return 333000;
5618 default:
5619 case GC_DISPLAY_CLOCK_190_200_MHZ:
5620 return 190000;
5621 }
5622 }
5623 }
5624
5625 static int i865_get_display_clock_speed(struct drm_device *dev)
5626 {
5627 return 266000;
5628 }
5629
5630 static int i855_get_display_clock_speed(struct drm_device *dev)
5631 {
5632 u16 hpllcc = 0;
5633 /* Assume that the hardware is in the high speed state. This
5634 * should be the default.
5635 */
5636 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5637 case GC_CLOCK_133_200:
5638 case GC_CLOCK_100_200:
5639 return 200000;
5640 case GC_CLOCK_166_250:
5641 return 250000;
5642 case GC_CLOCK_100_133:
5643 return 133000;
5644 }
5645
5646 /* Shouldn't happen */
5647 return 0;
5648 }
5649
5650 static int i830_get_display_clock_speed(struct drm_device *dev)
5651 {
5652 return 133000;
5653 }
5654
5655 static void
5656 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5657 {
5658 while (*num > DATA_LINK_M_N_MASK ||
5659 *den > DATA_LINK_M_N_MASK) {
5660 *num >>= 1;
5661 *den >>= 1;
5662 }
5663 }
5664
5665 static void compute_m_n(unsigned int m, unsigned int n,
5666 uint32_t *ret_m, uint32_t *ret_n)
5667 {
5668 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5669 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5670 intel_reduce_m_n_ratio(ret_m, ret_n);
5671 }
5672
5673 void
5674 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5675 int pixel_clock, int link_clock,
5676 struct intel_link_m_n *m_n)
5677 {
5678 m_n->tu = 64;
5679
5680 compute_m_n(bits_per_pixel * pixel_clock,
5681 link_clock * nlanes * 8,
5682 &m_n->gmch_m, &m_n->gmch_n);
5683
5684 compute_m_n(pixel_clock, link_clock,
5685 &m_n->link_m, &m_n->link_n);
5686 }
5687
5688 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5689 {
5690 if (i915.panel_use_ssc >= 0)
5691 return i915.panel_use_ssc != 0;
5692 return dev_priv->vbt.lvds_use_ssc
5693 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5694 }
5695
5696 static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
5697 {
5698 struct drm_device *dev = crtc->base.dev;
5699 struct drm_i915_private *dev_priv = dev->dev_private;
5700 int refclk;
5701
5702 if (IS_VALLEYVIEW(dev)) {
5703 refclk = 100000;
5704 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
5705 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5706 refclk = dev_priv->vbt.lvds_ssc_freq;
5707 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5708 } else if (!IS_GEN2(dev)) {
5709 refclk = 96000;
5710 } else {
5711 refclk = 48000;
5712 }
5713
5714 return refclk;
5715 }
5716
5717 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5718 {
5719 return (1 << dpll->n) << 16 | dpll->m2;
5720 }
5721
5722 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5723 {
5724 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5725 }
5726
5727 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5728 intel_clock_t *reduced_clock)
5729 {
5730 struct drm_device *dev = crtc->base.dev;
5731 u32 fp, fp2 = 0;
5732
5733 if (IS_PINEVIEW(dev)) {
5734 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5735 if (reduced_clock)
5736 fp2 = pnv_dpll_compute_fp(reduced_clock);
5737 } else {
5738 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5739 if (reduced_clock)
5740 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5741 }
5742
5743 crtc->config.dpll_hw_state.fp0 = fp;
5744
5745 crtc->lowfreq_avail = false;
5746 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5747 reduced_clock && i915.powersave) {
5748 crtc->config.dpll_hw_state.fp1 = fp2;
5749 crtc->lowfreq_avail = true;
5750 } else {
5751 crtc->config.dpll_hw_state.fp1 = fp;
5752 }
5753 }
5754
5755 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5756 pipe)
5757 {
5758 u32 reg_val;
5759
5760 /*
5761 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5762 * and set it to a reasonable value instead.
5763 */
5764 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5765 reg_val &= 0xffffff00;
5766 reg_val |= 0x00000030;
5767 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5768
5769 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5770 reg_val &= 0x8cffffff;
5771 reg_val = 0x8c000000;
5772 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5773
5774 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5775 reg_val &= 0xffffff00;
5776 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5777
5778 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5779 reg_val &= 0x00ffffff;
5780 reg_val |= 0xb0000000;
5781 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5782 }
5783
5784 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5785 struct intel_link_m_n *m_n)
5786 {
5787 struct drm_device *dev = crtc->base.dev;
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 int pipe = crtc->pipe;
5790
5791 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5792 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5793 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5794 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5795 }
5796
5797 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5798 struct intel_link_m_n *m_n,
5799 struct intel_link_m_n *m2_n2)
5800 {
5801 struct drm_device *dev = crtc->base.dev;
5802 struct drm_i915_private *dev_priv = dev->dev_private;
5803 int pipe = crtc->pipe;
5804 enum transcoder transcoder = crtc->config.cpu_transcoder;
5805
5806 if (INTEL_INFO(dev)->gen >= 5) {
5807 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5808 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5809 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5810 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5811 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
5812 * for gen < 8) and if DRRS is supported (to make sure the
5813 * registers are not unnecessarily accessed).
5814 */
5815 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
5816 crtc->config.has_drrs) {
5817 I915_WRITE(PIPE_DATA_M2(transcoder),
5818 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
5819 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
5820 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
5821 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
5822 }
5823 } else {
5824 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5825 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5826 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5827 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5828 }
5829 }
5830
5831 void intel_dp_set_m_n(struct intel_crtc *crtc)
5832 {
5833 if (crtc->config.has_pch_encoder)
5834 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5835 else
5836 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n,
5837 &crtc->config.dp_m2_n2);
5838 }
5839
5840 static void vlv_update_pll(struct intel_crtc *crtc,
5841 struct intel_crtc_config *pipe_config)
5842 {
5843 u32 dpll, dpll_md;
5844
5845 /*
5846 * Enable DPIO clock input. We should never disable the reference
5847 * clock for pipe B, since VGA hotplug / manual detection depends
5848 * on it.
5849 */
5850 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5851 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5852 /* We should never disable this, set it here for state tracking */
5853 if (crtc->pipe == PIPE_B)
5854 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5855 dpll |= DPLL_VCO_ENABLE;
5856 pipe_config->dpll_hw_state.dpll = dpll;
5857
5858 dpll_md = (pipe_config->pixel_multiplier - 1)
5859 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5860 pipe_config->dpll_hw_state.dpll_md = dpll_md;
5861 }
5862
5863 static void vlv_prepare_pll(struct intel_crtc *crtc,
5864 const struct intel_crtc_config *pipe_config)
5865 {
5866 struct drm_device *dev = crtc->base.dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 int pipe = crtc->pipe;
5869 u32 mdiv;
5870 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5871 u32 coreclk, reg_val;
5872
5873 mutex_lock(&dev_priv->dpio_lock);
5874
5875 bestn = pipe_config->dpll.n;
5876 bestm1 = pipe_config->dpll.m1;
5877 bestm2 = pipe_config->dpll.m2;
5878 bestp1 = pipe_config->dpll.p1;
5879 bestp2 = pipe_config->dpll.p2;
5880
5881 /* See eDP HDMI DPIO driver vbios notes doc */
5882
5883 /* PLL B needs special handling */
5884 if (pipe == PIPE_B)
5885 vlv_pllb_recal_opamp(dev_priv, pipe);
5886
5887 /* Set up Tx target for periodic Rcomp update */
5888 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5889
5890 /* Disable target IRef on PLL */
5891 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5892 reg_val &= 0x00ffffff;
5893 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5894
5895 /* Disable fast lock */
5896 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5897
5898 /* Set idtafcrecal before PLL is enabled */
5899 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5900 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5901 mdiv |= ((bestn << DPIO_N_SHIFT));
5902 mdiv |= (1 << DPIO_K_SHIFT);
5903
5904 /*
5905 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5906 * but we don't support that).
5907 * Note: don't use the DAC post divider as it seems unstable.
5908 */
5909 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5910 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5911
5912 mdiv |= DPIO_ENABLE_CALIBRATION;
5913 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5914
5915 /* Set HBR and RBR LPF coefficients */
5916 if (pipe_config->port_clock == 162000 ||
5917 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
5918 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
5919 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5920 0x009f0003);
5921 else
5922 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5923 0x00d0000f);
5924
5925 if (crtc->config.has_dp_encoder) {
5926 /* Use SSC source */
5927 if (pipe == PIPE_A)
5928 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5929 0x0df40000);
5930 else
5931 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5932 0x0df70000);
5933 } else { /* HDMI or VGA */
5934 /* Use bend source */
5935 if (pipe == PIPE_A)
5936 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5937 0x0df70000);
5938 else
5939 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5940 0x0df40000);
5941 }
5942
5943 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5944 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5945 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
5946 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5947 coreclk |= 0x01000000;
5948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5949
5950 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5951 mutex_unlock(&dev_priv->dpio_lock);
5952 }
5953
5954 static void chv_update_pll(struct intel_crtc *crtc,
5955 struct intel_crtc_config *pipe_config)
5956 {
5957 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5958 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5959 DPLL_VCO_ENABLE;
5960 if (crtc->pipe != PIPE_A)
5961 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5962
5963 pipe_config->dpll_hw_state.dpll_md =
5964 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5965 }
5966
5967 static void chv_prepare_pll(struct intel_crtc *crtc,
5968 const struct intel_crtc_config *pipe_config)
5969 {
5970 struct drm_device *dev = crtc->base.dev;
5971 struct drm_i915_private *dev_priv = dev->dev_private;
5972 int pipe = crtc->pipe;
5973 int dpll_reg = DPLL(crtc->pipe);
5974 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5975 u32 loopfilter, intcoeff;
5976 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5977 int refclk;
5978
5979 bestn = pipe_config->dpll.n;
5980 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
5981 bestm1 = pipe_config->dpll.m1;
5982 bestm2 = pipe_config->dpll.m2 >> 22;
5983 bestp1 = pipe_config->dpll.p1;
5984 bestp2 = pipe_config->dpll.p2;
5985
5986 /*
5987 * Enable Refclk and SSC
5988 */
5989 I915_WRITE(dpll_reg,
5990 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5991
5992 mutex_lock(&dev_priv->dpio_lock);
5993
5994 /* p1 and p2 divider */
5995 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5996 5 << DPIO_CHV_S1_DIV_SHIFT |
5997 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5998 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5999 1 << DPIO_CHV_K_DIV_SHIFT);
6000
6001 /* Feedback post-divider - m2 */
6002 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6003
6004 /* Feedback refclk divider - n and m1 */
6005 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6006 DPIO_CHV_M1_DIV_BY_2 |
6007 1 << DPIO_CHV_N_DIV_SHIFT);
6008
6009 /* M2 fraction division */
6010 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
6011
6012 /* M2 fraction division enable */
6013 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
6014 DPIO_CHV_FRAC_DIV_EN |
6015 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
6016
6017 /* Loop filter */
6018 refclk = i9xx_get_refclk(crtc, 0);
6019 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
6020 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
6021 if (refclk == 100000)
6022 intcoeff = 11;
6023 else if (refclk == 38400)
6024 intcoeff = 10;
6025 else
6026 intcoeff = 9;
6027 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
6028 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6029
6030 /* AFC Recal */
6031 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6032 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6033 DPIO_AFC_RECAL);
6034
6035 mutex_unlock(&dev_priv->dpio_lock);
6036 }
6037
6038 /**
6039 * vlv_force_pll_on - forcibly enable just the PLL
6040 * @dev_priv: i915 private structure
6041 * @pipe: pipe PLL to enable
6042 * @dpll: PLL configuration
6043 *
6044 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6045 * in cases where we need the PLL enabled even when @pipe is not going to
6046 * be enabled.
6047 */
6048 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6049 const struct dpll *dpll)
6050 {
6051 struct intel_crtc *crtc =
6052 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
6053 struct intel_crtc_config pipe_config = {
6054 .pixel_multiplier = 1,
6055 .dpll = *dpll,
6056 };
6057
6058 if (IS_CHERRYVIEW(dev)) {
6059 chv_update_pll(crtc, &pipe_config);
6060 chv_prepare_pll(crtc, &pipe_config);
6061 chv_enable_pll(crtc, &pipe_config);
6062 } else {
6063 vlv_update_pll(crtc, &pipe_config);
6064 vlv_prepare_pll(crtc, &pipe_config);
6065 vlv_enable_pll(crtc, &pipe_config);
6066 }
6067 }
6068
6069 /**
6070 * vlv_force_pll_off - forcibly disable just the PLL
6071 * @dev_priv: i915 private structure
6072 * @pipe: pipe PLL to disable
6073 *
6074 * Disable the PLL for @pipe. To be used in cases where we need
6075 * the PLL enabled even when @pipe is not going to be enabled.
6076 */
6077 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6078 {
6079 if (IS_CHERRYVIEW(dev))
6080 chv_disable_pll(to_i915(dev), pipe);
6081 else
6082 vlv_disable_pll(to_i915(dev), pipe);
6083 }
6084
6085 static void i9xx_update_pll(struct intel_crtc *crtc,
6086 intel_clock_t *reduced_clock,
6087 int num_connectors)
6088 {
6089 struct drm_device *dev = crtc->base.dev;
6090 struct drm_i915_private *dev_priv = dev->dev_private;
6091 u32 dpll;
6092 bool is_sdvo;
6093 struct dpll *clock = &crtc->new_config->dpll;
6094
6095 i9xx_update_pll_dividers(crtc, reduced_clock);
6096
6097 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6098 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
6099
6100 dpll = DPLL_VGA_MODE_DIS;
6101
6102 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
6103 dpll |= DPLLB_MODE_LVDS;
6104 else
6105 dpll |= DPLLB_MODE_DAC_SERIAL;
6106
6107 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6108 dpll |= (crtc->new_config->pixel_multiplier - 1)
6109 << SDVO_MULTIPLIER_SHIFT_HIRES;
6110 }
6111
6112 if (is_sdvo)
6113 dpll |= DPLL_SDVO_HIGH_SPEED;
6114
6115 if (crtc->new_config->has_dp_encoder)
6116 dpll |= DPLL_SDVO_HIGH_SPEED;
6117
6118 /* compute bitmask from p1 value */
6119 if (IS_PINEVIEW(dev))
6120 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6121 else {
6122 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6123 if (IS_G4X(dev) && reduced_clock)
6124 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6125 }
6126 switch (clock->p2) {
6127 case 5:
6128 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6129 break;
6130 case 7:
6131 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6132 break;
6133 case 10:
6134 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6135 break;
6136 case 14:
6137 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6138 break;
6139 }
6140 if (INTEL_INFO(dev)->gen >= 4)
6141 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6142
6143 if (crtc->new_config->sdvo_tv_clock)
6144 dpll |= PLL_REF_INPUT_TVCLKINBC;
6145 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6146 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6147 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6148 else
6149 dpll |= PLL_REF_INPUT_DREFCLK;
6150
6151 dpll |= DPLL_VCO_ENABLE;
6152 crtc->new_config->dpll_hw_state.dpll = dpll;
6153
6154 if (INTEL_INFO(dev)->gen >= 4) {
6155 u32 dpll_md = (crtc->new_config->pixel_multiplier - 1)
6156 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
6157 crtc->new_config->dpll_hw_state.dpll_md = dpll_md;
6158 }
6159 }
6160
6161 static void i8xx_update_pll(struct intel_crtc *crtc,
6162 intel_clock_t *reduced_clock,
6163 int num_connectors)
6164 {
6165 struct drm_device *dev = crtc->base.dev;
6166 struct drm_i915_private *dev_priv = dev->dev_private;
6167 u32 dpll;
6168 struct dpll *clock = &crtc->new_config->dpll;
6169
6170 i9xx_update_pll_dividers(crtc, reduced_clock);
6171
6172 dpll = DPLL_VGA_MODE_DIS;
6173
6174 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
6175 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6176 } else {
6177 if (clock->p1 == 2)
6178 dpll |= PLL_P1_DIVIDE_BY_TWO;
6179 else
6180 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6181 if (clock->p2 == 4)
6182 dpll |= PLL_P2_DIVIDE_BY_4;
6183 }
6184
6185 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
6186 dpll |= DPLL_DVO_2X_MODE;
6187
6188 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
6189 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6190 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6191 else
6192 dpll |= PLL_REF_INPUT_DREFCLK;
6193
6194 dpll |= DPLL_VCO_ENABLE;
6195 crtc->new_config->dpll_hw_state.dpll = dpll;
6196 }
6197
6198 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
6199 {
6200 struct drm_device *dev = intel_crtc->base.dev;
6201 struct drm_i915_private *dev_priv = dev->dev_private;
6202 enum pipe pipe = intel_crtc->pipe;
6203 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6204 struct drm_display_mode *adjusted_mode =
6205 &intel_crtc->config.adjusted_mode;
6206 uint32_t crtc_vtotal, crtc_vblank_end;
6207 int vsyncshift = 0;
6208
6209 /* We need to be careful not to changed the adjusted mode, for otherwise
6210 * the hw state checker will get angry at the mismatch. */
6211 crtc_vtotal = adjusted_mode->crtc_vtotal;
6212 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
6213
6214 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
6215 /* the chip adds 2 halflines automatically */
6216 crtc_vtotal -= 1;
6217 crtc_vblank_end -= 1;
6218
6219 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6220 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6221 else
6222 vsyncshift = adjusted_mode->crtc_hsync_start -
6223 adjusted_mode->crtc_htotal / 2;
6224 if (vsyncshift < 0)
6225 vsyncshift += adjusted_mode->crtc_htotal;
6226 }
6227
6228 if (INTEL_INFO(dev)->gen > 3)
6229 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
6230
6231 I915_WRITE(HTOTAL(cpu_transcoder),
6232 (adjusted_mode->crtc_hdisplay - 1) |
6233 ((adjusted_mode->crtc_htotal - 1) << 16));
6234 I915_WRITE(HBLANK(cpu_transcoder),
6235 (adjusted_mode->crtc_hblank_start - 1) |
6236 ((adjusted_mode->crtc_hblank_end - 1) << 16));
6237 I915_WRITE(HSYNC(cpu_transcoder),
6238 (adjusted_mode->crtc_hsync_start - 1) |
6239 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6240
6241 I915_WRITE(VTOTAL(cpu_transcoder),
6242 (adjusted_mode->crtc_vdisplay - 1) |
6243 ((crtc_vtotal - 1) << 16));
6244 I915_WRITE(VBLANK(cpu_transcoder),
6245 (adjusted_mode->crtc_vblank_start - 1) |
6246 ((crtc_vblank_end - 1) << 16));
6247 I915_WRITE(VSYNC(cpu_transcoder),
6248 (adjusted_mode->crtc_vsync_start - 1) |
6249 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6250
6251 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6252 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6253 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6254 * bits. */
6255 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6256 (pipe == PIPE_B || pipe == PIPE_C))
6257 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6258
6259 /* pipesrc controls the size that is scaled from, which should
6260 * always be the user's requested size.
6261 */
6262 I915_WRITE(PIPESRC(pipe),
6263 ((intel_crtc->config.pipe_src_w - 1) << 16) |
6264 (intel_crtc->config.pipe_src_h - 1));
6265 }
6266
6267 static void intel_get_pipe_timings(struct intel_crtc *crtc,
6268 struct intel_crtc_config *pipe_config)
6269 {
6270 struct drm_device *dev = crtc->base.dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6273 uint32_t tmp;
6274
6275 tmp = I915_READ(HTOTAL(cpu_transcoder));
6276 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6277 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
6278 tmp = I915_READ(HBLANK(cpu_transcoder));
6279 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6280 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
6281 tmp = I915_READ(HSYNC(cpu_transcoder));
6282 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6283 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
6284
6285 tmp = I915_READ(VTOTAL(cpu_transcoder));
6286 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6287 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
6288 tmp = I915_READ(VBLANK(cpu_transcoder));
6289 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6290 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
6291 tmp = I915_READ(VSYNC(cpu_transcoder));
6292 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6293 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
6294
6295 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
6296 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6297 pipe_config->adjusted_mode.crtc_vtotal += 1;
6298 pipe_config->adjusted_mode.crtc_vblank_end += 1;
6299 }
6300
6301 tmp = I915_READ(PIPESRC(crtc->pipe));
6302 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6303 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6304
6305 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
6306 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
6307 }
6308
6309 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
6310 struct intel_crtc_config *pipe_config)
6311 {
6312 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
6313 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
6314 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
6315 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
6316
6317 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
6318 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
6319 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
6320 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
6321
6322 mode->flags = pipe_config->adjusted_mode.flags;
6323
6324 mode->clock = pipe_config->adjusted_mode.crtc_clock;
6325 mode->flags |= pipe_config->adjusted_mode.flags;
6326 }
6327
6328 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6329 {
6330 struct drm_device *dev = intel_crtc->base.dev;
6331 struct drm_i915_private *dev_priv = dev->dev_private;
6332 uint32_t pipeconf;
6333
6334 pipeconf = 0;
6335
6336 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6337 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6338 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
6339
6340 if (intel_crtc->config.double_wide)
6341 pipeconf |= PIPECONF_DOUBLE_WIDE;
6342
6343 /* only g4x and later have fancy bpc/dither controls */
6344 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6345 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6346 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
6347 pipeconf |= PIPECONF_DITHER_EN |
6348 PIPECONF_DITHER_TYPE_SP;
6349
6350 switch (intel_crtc->config.pipe_bpp) {
6351 case 18:
6352 pipeconf |= PIPECONF_6BPC;
6353 break;
6354 case 24:
6355 pipeconf |= PIPECONF_8BPC;
6356 break;
6357 case 30:
6358 pipeconf |= PIPECONF_10BPC;
6359 break;
6360 default:
6361 /* Case prevented by intel_choose_pipe_bpp_dither. */
6362 BUG();
6363 }
6364 }
6365
6366 if (HAS_PIPE_CXSR(dev)) {
6367 if (intel_crtc->lowfreq_avail) {
6368 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6369 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6370 } else {
6371 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
6372 }
6373 }
6374
6375 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
6376 if (INTEL_INFO(dev)->gen < 4 ||
6377 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
6378 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6379 else
6380 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6381 } else
6382 pipeconf |= PIPECONF_PROGRESSIVE;
6383
6384 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
6385 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
6386
6387 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6388 POSTING_READ(PIPECONF(intel_crtc->pipe));
6389 }
6390
6391 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc)
6392 {
6393 struct drm_device *dev = crtc->base.dev;
6394 struct drm_i915_private *dev_priv = dev->dev_private;
6395 int refclk, num_connectors = 0;
6396 intel_clock_t clock, reduced_clock;
6397 bool ok, has_reduced_clock = false;
6398 bool is_lvds = false, is_dsi = false;
6399 struct intel_encoder *encoder;
6400 const intel_limit_t *limit;
6401
6402 for_each_intel_encoder(dev, encoder) {
6403 if (encoder->new_crtc != crtc)
6404 continue;
6405
6406 switch (encoder->type) {
6407 case INTEL_OUTPUT_LVDS:
6408 is_lvds = true;
6409 break;
6410 case INTEL_OUTPUT_DSI:
6411 is_dsi = true;
6412 break;
6413 default:
6414 break;
6415 }
6416
6417 num_connectors++;
6418 }
6419
6420 if (is_dsi)
6421 return 0;
6422
6423 if (!crtc->new_config->clock_set) {
6424 refclk = i9xx_get_refclk(crtc, num_connectors);
6425
6426 /*
6427 * Returns a set of divisors for the desired target clock with
6428 * the given refclk, or FALSE. The returned values represent
6429 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6430 * 2) / p1 / p2.
6431 */
6432 limit = intel_limit(crtc, refclk);
6433 ok = dev_priv->display.find_dpll(limit, crtc,
6434 crtc->new_config->port_clock,
6435 refclk, NULL, &clock);
6436 if (!ok) {
6437 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6438 return -EINVAL;
6439 }
6440
6441 if (is_lvds && dev_priv->lvds_downclock_avail) {
6442 /*
6443 * Ensure we match the reduced clock's P to the target
6444 * clock. If the clocks don't match, we can't switch
6445 * the display clock by using the FP0/FP1. In such case
6446 * we will disable the LVDS downclock feature.
6447 */
6448 has_reduced_clock =
6449 dev_priv->display.find_dpll(limit, crtc,
6450 dev_priv->lvds_downclock,
6451 refclk, &clock,
6452 &reduced_clock);
6453 }
6454 /* Compat-code for transition, will disappear. */
6455 crtc->new_config->dpll.n = clock.n;
6456 crtc->new_config->dpll.m1 = clock.m1;
6457 crtc->new_config->dpll.m2 = clock.m2;
6458 crtc->new_config->dpll.p1 = clock.p1;
6459 crtc->new_config->dpll.p2 = clock.p2;
6460 }
6461
6462 if (IS_GEN2(dev)) {
6463 i8xx_update_pll(crtc,
6464 has_reduced_clock ? &reduced_clock : NULL,
6465 num_connectors);
6466 } else if (IS_CHERRYVIEW(dev)) {
6467 chv_update_pll(crtc, crtc->new_config);
6468 } else if (IS_VALLEYVIEW(dev)) {
6469 vlv_update_pll(crtc, crtc->new_config);
6470 } else {
6471 i9xx_update_pll(crtc,
6472 has_reduced_clock ? &reduced_clock : NULL,
6473 num_connectors);
6474 }
6475
6476 return 0;
6477 }
6478
6479 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6480 struct intel_crtc_config *pipe_config)
6481 {
6482 struct drm_device *dev = crtc->base.dev;
6483 struct drm_i915_private *dev_priv = dev->dev_private;
6484 uint32_t tmp;
6485
6486 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6487 return;
6488
6489 tmp = I915_READ(PFIT_CONTROL);
6490 if (!(tmp & PFIT_ENABLE))
6491 return;
6492
6493 /* Check whether the pfit is attached to our pipe. */
6494 if (INTEL_INFO(dev)->gen < 4) {
6495 if (crtc->pipe != PIPE_B)
6496 return;
6497 } else {
6498 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6499 return;
6500 }
6501
6502 pipe_config->gmch_pfit.control = tmp;
6503 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6504 if (INTEL_INFO(dev)->gen < 5)
6505 pipe_config->gmch_pfit.lvds_border_bits =
6506 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6507 }
6508
6509 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6510 struct intel_crtc_config *pipe_config)
6511 {
6512 struct drm_device *dev = crtc->base.dev;
6513 struct drm_i915_private *dev_priv = dev->dev_private;
6514 int pipe = pipe_config->cpu_transcoder;
6515 intel_clock_t clock;
6516 u32 mdiv;
6517 int refclk = 100000;
6518
6519 /* In case of MIPI DPLL will not even be used */
6520 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6521 return;
6522
6523 mutex_lock(&dev_priv->dpio_lock);
6524 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6525 mutex_unlock(&dev_priv->dpio_lock);
6526
6527 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6528 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6529 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6530 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6531 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6532
6533 vlv_clock(refclk, &clock);
6534
6535 /* clock.dot is the fast clock */
6536 pipe_config->port_clock = clock.dot / 5;
6537 }
6538
6539 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6540 struct intel_plane_config *plane_config)
6541 {
6542 struct drm_device *dev = crtc->base.dev;
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544 u32 val, base, offset;
6545 int pipe = crtc->pipe, plane = crtc->plane;
6546 int fourcc, pixel_format;
6547 int aligned_height;
6548
6549 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6550 if (!crtc->base.primary->fb) {
6551 DRM_DEBUG_KMS("failed to alloc fb\n");
6552 return;
6553 }
6554
6555 val = I915_READ(DSPCNTR(plane));
6556
6557 if (INTEL_INFO(dev)->gen >= 4)
6558 if (val & DISPPLANE_TILED)
6559 plane_config->tiled = true;
6560
6561 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6562 fourcc = intel_format_to_fourcc(pixel_format);
6563 crtc->base.primary->fb->pixel_format = fourcc;
6564 crtc->base.primary->fb->bits_per_pixel =
6565 drm_format_plane_cpp(fourcc, 0) * 8;
6566
6567 if (INTEL_INFO(dev)->gen >= 4) {
6568 if (plane_config->tiled)
6569 offset = I915_READ(DSPTILEOFF(plane));
6570 else
6571 offset = I915_READ(DSPLINOFF(plane));
6572 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6573 } else {
6574 base = I915_READ(DSPADDR(plane));
6575 }
6576 plane_config->base = base;
6577
6578 val = I915_READ(PIPESRC(pipe));
6579 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6580 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6581
6582 val = I915_READ(DSPSTRIDE(pipe));
6583 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
6584
6585 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6586 plane_config->tiled);
6587
6588 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
6589 aligned_height);
6590
6591 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6592 pipe, plane, crtc->base.primary->fb->width,
6593 crtc->base.primary->fb->height,
6594 crtc->base.primary->fb->bits_per_pixel, base,
6595 crtc->base.primary->fb->pitches[0],
6596 plane_config->size);
6597
6598 }
6599
6600 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6601 struct intel_crtc_config *pipe_config)
6602 {
6603 struct drm_device *dev = crtc->base.dev;
6604 struct drm_i915_private *dev_priv = dev->dev_private;
6605 int pipe = pipe_config->cpu_transcoder;
6606 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6607 intel_clock_t clock;
6608 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6609 int refclk = 100000;
6610
6611 mutex_lock(&dev_priv->dpio_lock);
6612 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6613 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6614 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6615 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6616 mutex_unlock(&dev_priv->dpio_lock);
6617
6618 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6619 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6620 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6621 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6622 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6623
6624 chv_clock(refclk, &clock);
6625
6626 /* clock.dot is the fast clock */
6627 pipe_config->port_clock = clock.dot / 5;
6628 }
6629
6630 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6631 struct intel_crtc_config *pipe_config)
6632 {
6633 struct drm_device *dev = crtc->base.dev;
6634 struct drm_i915_private *dev_priv = dev->dev_private;
6635 uint32_t tmp;
6636
6637 if (!intel_display_power_is_enabled(dev_priv,
6638 POWER_DOMAIN_PIPE(crtc->pipe)))
6639 return false;
6640
6641 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6642 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6643
6644 tmp = I915_READ(PIPECONF(crtc->pipe));
6645 if (!(tmp & PIPECONF_ENABLE))
6646 return false;
6647
6648 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6649 switch (tmp & PIPECONF_BPC_MASK) {
6650 case PIPECONF_6BPC:
6651 pipe_config->pipe_bpp = 18;
6652 break;
6653 case PIPECONF_8BPC:
6654 pipe_config->pipe_bpp = 24;
6655 break;
6656 case PIPECONF_10BPC:
6657 pipe_config->pipe_bpp = 30;
6658 break;
6659 default:
6660 break;
6661 }
6662 }
6663
6664 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6665 pipe_config->limited_color_range = true;
6666
6667 if (INTEL_INFO(dev)->gen < 4)
6668 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6669
6670 intel_get_pipe_timings(crtc, pipe_config);
6671
6672 i9xx_get_pfit_config(crtc, pipe_config);
6673
6674 if (INTEL_INFO(dev)->gen >= 4) {
6675 tmp = I915_READ(DPLL_MD(crtc->pipe));
6676 pipe_config->pixel_multiplier =
6677 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6678 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6679 pipe_config->dpll_hw_state.dpll_md = tmp;
6680 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6681 tmp = I915_READ(DPLL(crtc->pipe));
6682 pipe_config->pixel_multiplier =
6683 ((tmp & SDVO_MULTIPLIER_MASK)
6684 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6685 } else {
6686 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6687 * port and will be fixed up in the encoder->get_config
6688 * function. */
6689 pipe_config->pixel_multiplier = 1;
6690 }
6691 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6692 if (!IS_VALLEYVIEW(dev)) {
6693 /*
6694 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
6695 * on 830. Filter it out here so that we don't
6696 * report errors due to that.
6697 */
6698 if (IS_I830(dev))
6699 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
6700
6701 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6702 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6703 } else {
6704 /* Mask out read-only status bits. */
6705 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6706 DPLL_PORTC_READY_MASK |
6707 DPLL_PORTB_READY_MASK);
6708 }
6709
6710 if (IS_CHERRYVIEW(dev))
6711 chv_crtc_clock_get(crtc, pipe_config);
6712 else if (IS_VALLEYVIEW(dev))
6713 vlv_crtc_clock_get(crtc, pipe_config);
6714 else
6715 i9xx_crtc_clock_get(crtc, pipe_config);
6716
6717 return true;
6718 }
6719
6720 static void ironlake_init_pch_refclk(struct drm_device *dev)
6721 {
6722 struct drm_i915_private *dev_priv = dev->dev_private;
6723 struct intel_encoder *encoder;
6724 u32 val, final;
6725 bool has_lvds = false;
6726 bool has_cpu_edp = false;
6727 bool has_panel = false;
6728 bool has_ck505 = false;
6729 bool can_ssc = false;
6730
6731 /* We need to take the global config into account */
6732 for_each_intel_encoder(dev, encoder) {
6733 switch (encoder->type) {
6734 case INTEL_OUTPUT_LVDS:
6735 has_panel = true;
6736 has_lvds = true;
6737 break;
6738 case INTEL_OUTPUT_EDP:
6739 has_panel = true;
6740 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6741 has_cpu_edp = true;
6742 break;
6743 default:
6744 break;
6745 }
6746 }
6747
6748 if (HAS_PCH_IBX(dev)) {
6749 has_ck505 = dev_priv->vbt.display_clock_mode;
6750 can_ssc = has_ck505;
6751 } else {
6752 has_ck505 = false;
6753 can_ssc = true;
6754 }
6755
6756 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6757 has_panel, has_lvds, has_ck505);
6758
6759 /* Ironlake: try to setup display ref clock before DPLL
6760 * enabling. This is only under driver's control after
6761 * PCH B stepping, previous chipset stepping should be
6762 * ignoring this setting.
6763 */
6764 val = I915_READ(PCH_DREF_CONTROL);
6765
6766 /* As we must carefully and slowly disable/enable each source in turn,
6767 * compute the final state we want first and check if we need to
6768 * make any changes at all.
6769 */
6770 final = val;
6771 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6772 if (has_ck505)
6773 final |= DREF_NONSPREAD_CK505_ENABLE;
6774 else
6775 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6776
6777 final &= ~DREF_SSC_SOURCE_MASK;
6778 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6779 final &= ~DREF_SSC1_ENABLE;
6780
6781 if (has_panel) {
6782 final |= DREF_SSC_SOURCE_ENABLE;
6783
6784 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6785 final |= DREF_SSC1_ENABLE;
6786
6787 if (has_cpu_edp) {
6788 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6789 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6790 else
6791 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6792 } else
6793 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6794 } else {
6795 final |= DREF_SSC_SOURCE_DISABLE;
6796 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6797 }
6798
6799 if (final == val)
6800 return;
6801
6802 /* Always enable nonspread source */
6803 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6804
6805 if (has_ck505)
6806 val |= DREF_NONSPREAD_CK505_ENABLE;
6807 else
6808 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6809
6810 if (has_panel) {
6811 val &= ~DREF_SSC_SOURCE_MASK;
6812 val |= DREF_SSC_SOURCE_ENABLE;
6813
6814 /* SSC must be turned on before enabling the CPU output */
6815 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6816 DRM_DEBUG_KMS("Using SSC on panel\n");
6817 val |= DREF_SSC1_ENABLE;
6818 } else
6819 val &= ~DREF_SSC1_ENABLE;
6820
6821 /* Get SSC going before enabling the outputs */
6822 I915_WRITE(PCH_DREF_CONTROL, val);
6823 POSTING_READ(PCH_DREF_CONTROL);
6824 udelay(200);
6825
6826 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6827
6828 /* Enable CPU source on CPU attached eDP */
6829 if (has_cpu_edp) {
6830 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6831 DRM_DEBUG_KMS("Using SSC on eDP\n");
6832 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6833 } else
6834 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6835 } else
6836 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6837
6838 I915_WRITE(PCH_DREF_CONTROL, val);
6839 POSTING_READ(PCH_DREF_CONTROL);
6840 udelay(200);
6841 } else {
6842 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6843
6844 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6845
6846 /* Turn off CPU output */
6847 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6848
6849 I915_WRITE(PCH_DREF_CONTROL, val);
6850 POSTING_READ(PCH_DREF_CONTROL);
6851 udelay(200);
6852
6853 /* Turn off the SSC source */
6854 val &= ~DREF_SSC_SOURCE_MASK;
6855 val |= DREF_SSC_SOURCE_DISABLE;
6856
6857 /* Turn off SSC1 */
6858 val &= ~DREF_SSC1_ENABLE;
6859
6860 I915_WRITE(PCH_DREF_CONTROL, val);
6861 POSTING_READ(PCH_DREF_CONTROL);
6862 udelay(200);
6863 }
6864
6865 BUG_ON(val != final);
6866 }
6867
6868 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6869 {
6870 uint32_t tmp;
6871
6872 tmp = I915_READ(SOUTH_CHICKEN2);
6873 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6874 I915_WRITE(SOUTH_CHICKEN2, tmp);
6875
6876 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6877 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6878 DRM_ERROR("FDI mPHY reset assert timeout\n");
6879
6880 tmp = I915_READ(SOUTH_CHICKEN2);
6881 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6882 I915_WRITE(SOUTH_CHICKEN2, tmp);
6883
6884 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6885 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6886 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6887 }
6888
6889 /* WaMPhyProgramming:hsw */
6890 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6891 {
6892 uint32_t tmp;
6893
6894 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6895 tmp &= ~(0xFF << 24);
6896 tmp |= (0x12 << 24);
6897 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6898
6899 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6900 tmp |= (1 << 11);
6901 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6902
6903 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6904 tmp |= (1 << 11);
6905 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6906
6907 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6908 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6909 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6910
6911 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6912 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6913 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6914
6915 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6916 tmp &= ~(7 << 13);
6917 tmp |= (5 << 13);
6918 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6919
6920 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6921 tmp &= ~(7 << 13);
6922 tmp |= (5 << 13);
6923 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6924
6925 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6926 tmp &= ~0xFF;
6927 tmp |= 0x1C;
6928 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6929
6930 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6931 tmp &= ~0xFF;
6932 tmp |= 0x1C;
6933 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6934
6935 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6936 tmp &= ~(0xFF << 16);
6937 tmp |= (0x1C << 16);
6938 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6939
6940 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6941 tmp &= ~(0xFF << 16);
6942 tmp |= (0x1C << 16);
6943 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6944
6945 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6946 tmp |= (1 << 27);
6947 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6948
6949 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6950 tmp |= (1 << 27);
6951 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6952
6953 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6954 tmp &= ~(0xF << 28);
6955 tmp |= (4 << 28);
6956 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6957
6958 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6959 tmp &= ~(0xF << 28);
6960 tmp |= (4 << 28);
6961 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6962 }
6963
6964 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6965 * Programming" based on the parameters passed:
6966 * - Sequence to enable CLKOUT_DP
6967 * - Sequence to enable CLKOUT_DP without spread
6968 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6969 */
6970 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6971 bool with_fdi)
6972 {
6973 struct drm_i915_private *dev_priv = dev->dev_private;
6974 uint32_t reg, tmp;
6975
6976 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6977 with_spread = true;
6978 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6979 with_fdi, "LP PCH doesn't have FDI\n"))
6980 with_fdi = false;
6981
6982 mutex_lock(&dev_priv->dpio_lock);
6983
6984 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6985 tmp &= ~SBI_SSCCTL_DISABLE;
6986 tmp |= SBI_SSCCTL_PATHALT;
6987 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6988
6989 udelay(24);
6990
6991 if (with_spread) {
6992 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6993 tmp &= ~SBI_SSCCTL_PATHALT;
6994 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6995
6996 if (with_fdi) {
6997 lpt_reset_fdi_mphy(dev_priv);
6998 lpt_program_fdi_mphy(dev_priv);
6999 }
7000 }
7001
7002 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7003 SBI_GEN0 : SBI_DBUFF0;
7004 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7005 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7006 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7007
7008 mutex_unlock(&dev_priv->dpio_lock);
7009 }
7010
7011 /* Sequence to disable CLKOUT_DP */
7012 static void lpt_disable_clkout_dp(struct drm_device *dev)
7013 {
7014 struct drm_i915_private *dev_priv = dev->dev_private;
7015 uint32_t reg, tmp;
7016
7017 mutex_lock(&dev_priv->dpio_lock);
7018
7019 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7020 SBI_GEN0 : SBI_DBUFF0;
7021 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7022 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7023 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7024
7025 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7026 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7027 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7028 tmp |= SBI_SSCCTL_PATHALT;
7029 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7030 udelay(32);
7031 }
7032 tmp |= SBI_SSCCTL_DISABLE;
7033 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7034 }
7035
7036 mutex_unlock(&dev_priv->dpio_lock);
7037 }
7038
7039 static void lpt_init_pch_refclk(struct drm_device *dev)
7040 {
7041 struct intel_encoder *encoder;
7042 bool has_vga = false;
7043
7044 for_each_intel_encoder(dev, encoder) {
7045 switch (encoder->type) {
7046 case INTEL_OUTPUT_ANALOG:
7047 has_vga = true;
7048 break;
7049 default:
7050 break;
7051 }
7052 }
7053
7054 if (has_vga)
7055 lpt_enable_clkout_dp(dev, true, true);
7056 else
7057 lpt_disable_clkout_dp(dev);
7058 }
7059
7060 /*
7061 * Initialize reference clocks when the driver loads
7062 */
7063 void intel_init_pch_refclk(struct drm_device *dev)
7064 {
7065 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7066 ironlake_init_pch_refclk(dev);
7067 else if (HAS_PCH_LPT(dev))
7068 lpt_init_pch_refclk(dev);
7069 }
7070
7071 static int ironlake_get_refclk(struct drm_crtc *crtc)
7072 {
7073 struct drm_device *dev = crtc->dev;
7074 struct drm_i915_private *dev_priv = dev->dev_private;
7075 struct intel_encoder *encoder;
7076 int num_connectors = 0;
7077 bool is_lvds = false;
7078
7079 for_each_intel_encoder(dev, encoder) {
7080 if (encoder->new_crtc != to_intel_crtc(crtc))
7081 continue;
7082
7083 switch (encoder->type) {
7084 case INTEL_OUTPUT_LVDS:
7085 is_lvds = true;
7086 break;
7087 default:
7088 break;
7089 }
7090 num_connectors++;
7091 }
7092
7093 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7094 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
7095 dev_priv->vbt.lvds_ssc_freq);
7096 return dev_priv->vbt.lvds_ssc_freq;
7097 }
7098
7099 return 120000;
7100 }
7101
7102 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
7103 {
7104 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
7105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7106 int pipe = intel_crtc->pipe;
7107 uint32_t val;
7108
7109 val = 0;
7110
7111 switch (intel_crtc->config.pipe_bpp) {
7112 case 18:
7113 val |= PIPECONF_6BPC;
7114 break;
7115 case 24:
7116 val |= PIPECONF_8BPC;
7117 break;
7118 case 30:
7119 val |= PIPECONF_10BPC;
7120 break;
7121 case 36:
7122 val |= PIPECONF_12BPC;
7123 break;
7124 default:
7125 /* Case prevented by intel_choose_pipe_bpp_dither. */
7126 BUG();
7127 }
7128
7129 if (intel_crtc->config.dither)
7130 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7131
7132 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7133 val |= PIPECONF_INTERLACED_ILK;
7134 else
7135 val |= PIPECONF_PROGRESSIVE;
7136
7137 if (intel_crtc->config.limited_color_range)
7138 val |= PIPECONF_COLOR_RANGE_SELECT;
7139
7140 I915_WRITE(PIPECONF(pipe), val);
7141 POSTING_READ(PIPECONF(pipe));
7142 }
7143
7144 /*
7145 * Set up the pipe CSC unit.
7146 *
7147 * Currently only full range RGB to limited range RGB conversion
7148 * is supported, but eventually this should handle various
7149 * RGB<->YCbCr scenarios as well.
7150 */
7151 static void intel_set_pipe_csc(struct drm_crtc *crtc)
7152 {
7153 struct drm_device *dev = crtc->dev;
7154 struct drm_i915_private *dev_priv = dev->dev_private;
7155 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7156 int pipe = intel_crtc->pipe;
7157 uint16_t coeff = 0x7800; /* 1.0 */
7158
7159 /*
7160 * TODO: Check what kind of values actually come out of the pipe
7161 * with these coeff/postoff values and adjust to get the best
7162 * accuracy. Perhaps we even need to take the bpc value into
7163 * consideration.
7164 */
7165
7166 if (intel_crtc->config.limited_color_range)
7167 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7168
7169 /*
7170 * GY/GU and RY/RU should be the other way around according
7171 * to BSpec, but reality doesn't agree. Just set them up in
7172 * a way that results in the correct picture.
7173 */
7174 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7175 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7176
7177 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7178 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7179
7180 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7181 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7182
7183 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7184 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7185 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7186
7187 if (INTEL_INFO(dev)->gen > 6) {
7188 uint16_t postoff = 0;
7189
7190 if (intel_crtc->config.limited_color_range)
7191 postoff = (16 * (1 << 12) / 255) & 0x1fff;
7192
7193 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7194 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7195 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7196
7197 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7198 } else {
7199 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7200
7201 if (intel_crtc->config.limited_color_range)
7202 mode |= CSC_BLACK_SCREEN_OFFSET;
7203
7204 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7205 }
7206 }
7207
7208 static void haswell_set_pipeconf(struct drm_crtc *crtc)
7209 {
7210 struct drm_device *dev = crtc->dev;
7211 struct drm_i915_private *dev_priv = dev->dev_private;
7212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7213 enum pipe pipe = intel_crtc->pipe;
7214 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7215 uint32_t val;
7216
7217 val = 0;
7218
7219 if (IS_HASWELL(dev) && intel_crtc->config.dither)
7220 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7221
7222 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
7223 val |= PIPECONF_INTERLACED_ILK;
7224 else
7225 val |= PIPECONF_PROGRESSIVE;
7226
7227 I915_WRITE(PIPECONF(cpu_transcoder), val);
7228 POSTING_READ(PIPECONF(cpu_transcoder));
7229
7230 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7231 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
7232
7233 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
7234 val = 0;
7235
7236 switch (intel_crtc->config.pipe_bpp) {
7237 case 18:
7238 val |= PIPEMISC_DITHER_6_BPC;
7239 break;
7240 case 24:
7241 val |= PIPEMISC_DITHER_8_BPC;
7242 break;
7243 case 30:
7244 val |= PIPEMISC_DITHER_10_BPC;
7245 break;
7246 case 36:
7247 val |= PIPEMISC_DITHER_12_BPC;
7248 break;
7249 default:
7250 /* Case prevented by pipe_config_set_bpp. */
7251 BUG();
7252 }
7253
7254 if (intel_crtc->config.dither)
7255 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7256
7257 I915_WRITE(PIPEMISC(pipe), val);
7258 }
7259 }
7260
7261 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
7262 intel_clock_t *clock,
7263 bool *has_reduced_clock,
7264 intel_clock_t *reduced_clock)
7265 {
7266 struct drm_device *dev = crtc->dev;
7267 struct drm_i915_private *dev_priv = dev->dev_private;
7268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7269 int refclk;
7270 const intel_limit_t *limit;
7271 bool ret, is_lvds = false;
7272
7273 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
7274
7275 refclk = ironlake_get_refclk(crtc);
7276
7277 /*
7278 * Returns a set of divisors for the desired target clock with the given
7279 * refclk, or FALSE. The returned values represent the clock equation:
7280 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7281 */
7282 limit = intel_limit(intel_crtc, refclk);
7283 ret = dev_priv->display.find_dpll(limit, intel_crtc,
7284 intel_crtc->new_config->port_clock,
7285 refclk, NULL, clock);
7286 if (!ret)
7287 return false;
7288
7289 if (is_lvds && dev_priv->lvds_downclock_avail) {
7290 /*
7291 * Ensure we match the reduced clock's P to the target clock.
7292 * If the clocks don't match, we can't switch the display clock
7293 * by using the FP0/FP1. In such case we will disable the LVDS
7294 * downclock feature.
7295 */
7296 *has_reduced_clock =
7297 dev_priv->display.find_dpll(limit, intel_crtc,
7298 dev_priv->lvds_downclock,
7299 refclk, clock,
7300 reduced_clock);
7301 }
7302
7303 return true;
7304 }
7305
7306 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7307 {
7308 /*
7309 * Account for spread spectrum to avoid
7310 * oversubscribing the link. Max center spread
7311 * is 2.5%; use 5% for safety's sake.
7312 */
7313 u32 bps = target_clock * bpp * 21 / 20;
7314 return DIV_ROUND_UP(bps, link_bw * 8);
7315 }
7316
7317 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
7318 {
7319 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
7320 }
7321
7322 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7323 u32 *fp,
7324 intel_clock_t *reduced_clock, u32 *fp2)
7325 {
7326 struct drm_crtc *crtc = &intel_crtc->base;
7327 struct drm_device *dev = crtc->dev;
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 struct intel_encoder *intel_encoder;
7330 uint32_t dpll;
7331 int factor, num_connectors = 0;
7332 bool is_lvds = false, is_sdvo = false;
7333
7334 for_each_intel_encoder(dev, intel_encoder) {
7335 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7336 continue;
7337
7338 switch (intel_encoder->type) {
7339 case INTEL_OUTPUT_LVDS:
7340 is_lvds = true;
7341 break;
7342 case INTEL_OUTPUT_SDVO:
7343 case INTEL_OUTPUT_HDMI:
7344 is_sdvo = true;
7345 break;
7346 default:
7347 break;
7348 }
7349
7350 num_connectors++;
7351 }
7352
7353 /* Enable autotuning of the PLL clock (if permissible) */
7354 factor = 21;
7355 if (is_lvds) {
7356 if ((intel_panel_use_ssc(dev_priv) &&
7357 dev_priv->vbt.lvds_ssc_freq == 100000) ||
7358 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
7359 factor = 25;
7360 } else if (intel_crtc->new_config->sdvo_tv_clock)
7361 factor = 20;
7362
7363 if (ironlake_needs_fb_cb_tune(&intel_crtc->new_config->dpll, factor))
7364 *fp |= FP_CB_TUNE;
7365
7366 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7367 *fp2 |= FP_CB_TUNE;
7368
7369 dpll = 0;
7370
7371 if (is_lvds)
7372 dpll |= DPLLB_MODE_LVDS;
7373 else
7374 dpll |= DPLLB_MODE_DAC_SERIAL;
7375
7376 dpll |= (intel_crtc->new_config->pixel_multiplier - 1)
7377 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
7378
7379 if (is_sdvo)
7380 dpll |= DPLL_SDVO_HIGH_SPEED;
7381 if (intel_crtc->new_config->has_dp_encoder)
7382 dpll |= DPLL_SDVO_HIGH_SPEED;
7383
7384 /* compute bitmask from p1 value */
7385 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7386 /* also FPA1 */
7387 dpll |= (1 << (intel_crtc->new_config->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7388
7389 switch (intel_crtc->new_config->dpll.p2) {
7390 case 5:
7391 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7392 break;
7393 case 7:
7394 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7395 break;
7396 case 10:
7397 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7398 break;
7399 case 14:
7400 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7401 break;
7402 }
7403
7404 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7405 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7406 else
7407 dpll |= PLL_REF_INPUT_DREFCLK;
7408
7409 return dpll | DPLL_VCO_ENABLE;
7410 }
7411
7412 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc)
7413 {
7414 struct drm_device *dev = crtc->base.dev;
7415 intel_clock_t clock, reduced_clock;
7416 u32 dpll = 0, fp = 0, fp2 = 0;
7417 bool ok, has_reduced_clock = false;
7418 bool is_lvds = false;
7419 struct intel_shared_dpll *pll;
7420
7421 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
7422
7423 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7424 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7425
7426 ok = ironlake_compute_clocks(&crtc->base, &clock,
7427 &has_reduced_clock, &reduced_clock);
7428 if (!ok && !crtc->new_config->clock_set) {
7429 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7430 return -EINVAL;
7431 }
7432 /* Compat-code for transition, will disappear. */
7433 if (!crtc->new_config->clock_set) {
7434 crtc->new_config->dpll.n = clock.n;
7435 crtc->new_config->dpll.m1 = clock.m1;
7436 crtc->new_config->dpll.m2 = clock.m2;
7437 crtc->new_config->dpll.p1 = clock.p1;
7438 crtc->new_config->dpll.p2 = clock.p2;
7439 }
7440
7441 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7442 if (crtc->new_config->has_pch_encoder) {
7443 fp = i9xx_dpll_compute_fp(&crtc->new_config->dpll);
7444 if (has_reduced_clock)
7445 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7446
7447 dpll = ironlake_compute_dpll(crtc,
7448 &fp, &reduced_clock,
7449 has_reduced_clock ? &fp2 : NULL);
7450
7451 crtc->new_config->dpll_hw_state.dpll = dpll;
7452 crtc->new_config->dpll_hw_state.fp0 = fp;
7453 if (has_reduced_clock)
7454 crtc->new_config->dpll_hw_state.fp1 = fp2;
7455 else
7456 crtc->new_config->dpll_hw_state.fp1 = fp;
7457
7458 pll = intel_get_shared_dpll(crtc);
7459 if (pll == NULL) {
7460 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7461 pipe_name(crtc->pipe));
7462 return -EINVAL;
7463 }
7464 }
7465
7466 if (is_lvds && has_reduced_clock && i915.powersave)
7467 crtc->lowfreq_avail = true;
7468 else
7469 crtc->lowfreq_avail = false;
7470
7471 return 0;
7472 }
7473
7474 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7475 struct intel_link_m_n *m_n)
7476 {
7477 struct drm_device *dev = crtc->base.dev;
7478 struct drm_i915_private *dev_priv = dev->dev_private;
7479 enum pipe pipe = crtc->pipe;
7480
7481 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7482 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7483 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7484 & ~TU_SIZE_MASK;
7485 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7486 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7487 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7488 }
7489
7490 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7491 enum transcoder transcoder,
7492 struct intel_link_m_n *m_n,
7493 struct intel_link_m_n *m2_n2)
7494 {
7495 struct drm_device *dev = crtc->base.dev;
7496 struct drm_i915_private *dev_priv = dev->dev_private;
7497 enum pipe pipe = crtc->pipe;
7498
7499 if (INTEL_INFO(dev)->gen >= 5) {
7500 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7501 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7502 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7503 & ~TU_SIZE_MASK;
7504 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7505 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7506 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7507 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7508 * gen < 8) and if DRRS is supported (to make sure the
7509 * registers are not unnecessarily read).
7510 */
7511 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
7512 crtc->config.has_drrs) {
7513 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7514 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7515 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7516 & ~TU_SIZE_MASK;
7517 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7518 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7519 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7520 }
7521 } else {
7522 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7523 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7524 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7525 & ~TU_SIZE_MASK;
7526 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7527 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7528 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7529 }
7530 }
7531
7532 void intel_dp_get_m_n(struct intel_crtc *crtc,
7533 struct intel_crtc_config *pipe_config)
7534 {
7535 if (crtc->config.has_pch_encoder)
7536 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7537 else
7538 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7539 &pipe_config->dp_m_n,
7540 &pipe_config->dp_m2_n2);
7541 }
7542
7543 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7544 struct intel_crtc_config *pipe_config)
7545 {
7546 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7547 &pipe_config->fdi_m_n, NULL);
7548 }
7549
7550 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7551 struct intel_crtc_config *pipe_config)
7552 {
7553 struct drm_device *dev = crtc->base.dev;
7554 struct drm_i915_private *dev_priv = dev->dev_private;
7555 uint32_t tmp;
7556
7557 tmp = I915_READ(PF_CTL(crtc->pipe));
7558
7559 if (tmp & PF_ENABLE) {
7560 pipe_config->pch_pfit.enabled = true;
7561 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7562 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7563
7564 /* We currently do not free assignements of panel fitters on
7565 * ivb/hsw (since we don't use the higher upscaling modes which
7566 * differentiates them) so just WARN about this case for now. */
7567 if (IS_GEN7(dev)) {
7568 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7569 PF_PIPE_SEL_IVB(crtc->pipe));
7570 }
7571 }
7572 }
7573
7574 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7575 struct intel_plane_config *plane_config)
7576 {
7577 struct drm_device *dev = crtc->base.dev;
7578 struct drm_i915_private *dev_priv = dev->dev_private;
7579 u32 val, base, offset;
7580 int pipe = crtc->pipe, plane = crtc->plane;
7581 int fourcc, pixel_format;
7582 int aligned_height;
7583
7584 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7585 if (!crtc->base.primary->fb) {
7586 DRM_DEBUG_KMS("failed to alloc fb\n");
7587 return;
7588 }
7589
7590 val = I915_READ(DSPCNTR(plane));
7591
7592 if (INTEL_INFO(dev)->gen >= 4)
7593 if (val & DISPPLANE_TILED)
7594 plane_config->tiled = true;
7595
7596 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7597 fourcc = intel_format_to_fourcc(pixel_format);
7598 crtc->base.primary->fb->pixel_format = fourcc;
7599 crtc->base.primary->fb->bits_per_pixel =
7600 drm_format_plane_cpp(fourcc, 0) * 8;
7601
7602 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7603 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7604 offset = I915_READ(DSPOFFSET(plane));
7605 } else {
7606 if (plane_config->tiled)
7607 offset = I915_READ(DSPTILEOFF(plane));
7608 else
7609 offset = I915_READ(DSPLINOFF(plane));
7610 }
7611 plane_config->base = base;
7612
7613 val = I915_READ(PIPESRC(pipe));
7614 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7615 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7616
7617 val = I915_READ(DSPSTRIDE(pipe));
7618 crtc->base.primary->fb->pitches[0] = val & 0xffffffc0;
7619
7620 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7621 plane_config->tiled);
7622
7623 plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] *
7624 aligned_height);
7625
7626 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7627 pipe, plane, crtc->base.primary->fb->width,
7628 crtc->base.primary->fb->height,
7629 crtc->base.primary->fb->bits_per_pixel, base,
7630 crtc->base.primary->fb->pitches[0],
7631 plane_config->size);
7632 }
7633
7634 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7635 struct intel_crtc_config *pipe_config)
7636 {
7637 struct drm_device *dev = crtc->base.dev;
7638 struct drm_i915_private *dev_priv = dev->dev_private;
7639 uint32_t tmp;
7640
7641 if (!intel_display_power_is_enabled(dev_priv,
7642 POWER_DOMAIN_PIPE(crtc->pipe)))
7643 return false;
7644
7645 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7646 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7647
7648 tmp = I915_READ(PIPECONF(crtc->pipe));
7649 if (!(tmp & PIPECONF_ENABLE))
7650 return false;
7651
7652 switch (tmp & PIPECONF_BPC_MASK) {
7653 case PIPECONF_6BPC:
7654 pipe_config->pipe_bpp = 18;
7655 break;
7656 case PIPECONF_8BPC:
7657 pipe_config->pipe_bpp = 24;
7658 break;
7659 case PIPECONF_10BPC:
7660 pipe_config->pipe_bpp = 30;
7661 break;
7662 case PIPECONF_12BPC:
7663 pipe_config->pipe_bpp = 36;
7664 break;
7665 default:
7666 break;
7667 }
7668
7669 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7670 pipe_config->limited_color_range = true;
7671
7672 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7673 struct intel_shared_dpll *pll;
7674
7675 pipe_config->has_pch_encoder = true;
7676
7677 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7678 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7679 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7680
7681 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7682
7683 if (HAS_PCH_IBX(dev_priv->dev)) {
7684 pipe_config->shared_dpll =
7685 (enum intel_dpll_id) crtc->pipe;
7686 } else {
7687 tmp = I915_READ(PCH_DPLL_SEL);
7688 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7689 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7690 else
7691 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7692 }
7693
7694 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7695
7696 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7697 &pipe_config->dpll_hw_state));
7698
7699 tmp = pipe_config->dpll_hw_state.dpll;
7700 pipe_config->pixel_multiplier =
7701 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7702 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7703
7704 ironlake_pch_clock_get(crtc, pipe_config);
7705 } else {
7706 pipe_config->pixel_multiplier = 1;
7707 }
7708
7709 intel_get_pipe_timings(crtc, pipe_config);
7710
7711 ironlake_get_pfit_config(crtc, pipe_config);
7712
7713 return true;
7714 }
7715
7716 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7717 {
7718 struct drm_device *dev = dev_priv->dev;
7719 struct intel_crtc *crtc;
7720
7721 for_each_intel_crtc(dev, crtc)
7722 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7723 pipe_name(crtc->pipe));
7724
7725 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7726 WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
7727 WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
7728 WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
7729 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7730 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7731 "CPU PWM1 enabled\n");
7732 if (IS_HASWELL(dev))
7733 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7734 "CPU PWM2 enabled\n");
7735 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7736 "PCH PWM1 enabled\n");
7737 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7738 "Utility pin enabled\n");
7739 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7740
7741 /*
7742 * In theory we can still leave IRQs enabled, as long as only the HPD
7743 * interrupts remain enabled. We used to check for that, but since it's
7744 * gen-specific and since we only disable LCPLL after we fully disable
7745 * the interrupts, the check below should be enough.
7746 */
7747 WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
7748 }
7749
7750 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
7751 {
7752 struct drm_device *dev = dev_priv->dev;
7753
7754 if (IS_HASWELL(dev))
7755 return I915_READ(D_COMP_HSW);
7756 else
7757 return I915_READ(D_COMP_BDW);
7758 }
7759
7760 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7761 {
7762 struct drm_device *dev = dev_priv->dev;
7763
7764 if (IS_HASWELL(dev)) {
7765 mutex_lock(&dev_priv->rps.hw_lock);
7766 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7767 val))
7768 DRM_ERROR("Failed to write to D_COMP\n");
7769 mutex_unlock(&dev_priv->rps.hw_lock);
7770 } else {
7771 I915_WRITE(D_COMP_BDW, val);
7772 POSTING_READ(D_COMP_BDW);
7773 }
7774 }
7775
7776 /*
7777 * This function implements pieces of two sequences from BSpec:
7778 * - Sequence for display software to disable LCPLL
7779 * - Sequence for display software to allow package C8+
7780 * The steps implemented here are just the steps that actually touch the LCPLL
7781 * register. Callers should take care of disabling all the display engine
7782 * functions, doing the mode unset, fixing interrupts, etc.
7783 */
7784 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7785 bool switch_to_fclk, bool allow_power_down)
7786 {
7787 uint32_t val;
7788
7789 assert_can_disable_lcpll(dev_priv);
7790
7791 val = I915_READ(LCPLL_CTL);
7792
7793 if (switch_to_fclk) {
7794 val |= LCPLL_CD_SOURCE_FCLK;
7795 I915_WRITE(LCPLL_CTL, val);
7796
7797 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7798 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7799 DRM_ERROR("Switching to FCLK failed\n");
7800
7801 val = I915_READ(LCPLL_CTL);
7802 }
7803
7804 val |= LCPLL_PLL_DISABLE;
7805 I915_WRITE(LCPLL_CTL, val);
7806 POSTING_READ(LCPLL_CTL);
7807
7808 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7809 DRM_ERROR("LCPLL still locked\n");
7810
7811 val = hsw_read_dcomp(dev_priv);
7812 val |= D_COMP_COMP_DISABLE;
7813 hsw_write_dcomp(dev_priv, val);
7814 ndelay(100);
7815
7816 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
7817 1))
7818 DRM_ERROR("D_COMP RCOMP still in progress\n");
7819
7820 if (allow_power_down) {
7821 val = I915_READ(LCPLL_CTL);
7822 val |= LCPLL_POWER_DOWN_ALLOW;
7823 I915_WRITE(LCPLL_CTL, val);
7824 POSTING_READ(LCPLL_CTL);
7825 }
7826 }
7827
7828 /*
7829 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7830 * source.
7831 */
7832 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7833 {
7834 uint32_t val;
7835
7836 val = I915_READ(LCPLL_CTL);
7837
7838 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7839 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7840 return;
7841
7842 /*
7843 * Make sure we're not on PC8 state before disabling PC8, otherwise
7844 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7845 *
7846 * The other problem is that hsw_restore_lcpll() is called as part of
7847 * the runtime PM resume sequence, so we can't just call
7848 * gen6_gt_force_wake_get() because that function calls
7849 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7850 * while we are on the resume sequence. So to solve this problem we have
7851 * to call special forcewake code that doesn't touch runtime PM and
7852 * doesn't enable the forcewake delayed work.
7853 */
7854 spin_lock_irq(&dev_priv->uncore.lock);
7855 if (dev_priv->uncore.forcewake_count++ == 0)
7856 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7857 spin_unlock_irq(&dev_priv->uncore.lock);
7858
7859 if (val & LCPLL_POWER_DOWN_ALLOW) {
7860 val &= ~LCPLL_POWER_DOWN_ALLOW;
7861 I915_WRITE(LCPLL_CTL, val);
7862 POSTING_READ(LCPLL_CTL);
7863 }
7864
7865 val = hsw_read_dcomp(dev_priv);
7866 val |= D_COMP_COMP_FORCE;
7867 val &= ~D_COMP_COMP_DISABLE;
7868 hsw_write_dcomp(dev_priv, val);
7869
7870 val = I915_READ(LCPLL_CTL);
7871 val &= ~LCPLL_PLL_DISABLE;
7872 I915_WRITE(LCPLL_CTL, val);
7873
7874 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7875 DRM_ERROR("LCPLL not locked yet\n");
7876
7877 if (val & LCPLL_CD_SOURCE_FCLK) {
7878 val = I915_READ(LCPLL_CTL);
7879 val &= ~LCPLL_CD_SOURCE_FCLK;
7880 I915_WRITE(LCPLL_CTL, val);
7881
7882 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7883 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7884 DRM_ERROR("Switching back to LCPLL failed\n");
7885 }
7886
7887 /* See the big comment above. */
7888 spin_lock_irq(&dev_priv->uncore.lock);
7889 if (--dev_priv->uncore.forcewake_count == 0)
7890 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7891 spin_unlock_irq(&dev_priv->uncore.lock);
7892 }
7893
7894 /*
7895 * Package states C8 and deeper are really deep PC states that can only be
7896 * reached when all the devices on the system allow it, so even if the graphics
7897 * device allows PC8+, it doesn't mean the system will actually get to these
7898 * states. Our driver only allows PC8+ when going into runtime PM.
7899 *
7900 * The requirements for PC8+ are that all the outputs are disabled, the power
7901 * well is disabled and most interrupts are disabled, and these are also
7902 * requirements for runtime PM. When these conditions are met, we manually do
7903 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7904 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7905 * hang the machine.
7906 *
7907 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7908 * the state of some registers, so when we come back from PC8+ we need to
7909 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7910 * need to take care of the registers kept by RC6. Notice that this happens even
7911 * if we don't put the device in PCI D3 state (which is what currently happens
7912 * because of the runtime PM support).
7913 *
7914 * For more, read "Display Sequences for Package C8" on the hardware
7915 * documentation.
7916 */
7917 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7918 {
7919 struct drm_device *dev = dev_priv->dev;
7920 uint32_t val;
7921
7922 DRM_DEBUG_KMS("Enabling package C8+\n");
7923
7924 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7925 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7926 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7927 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7928 }
7929
7930 lpt_disable_clkout_dp(dev);
7931 hsw_disable_lcpll(dev_priv, true, true);
7932 }
7933
7934 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7935 {
7936 struct drm_device *dev = dev_priv->dev;
7937 uint32_t val;
7938
7939 DRM_DEBUG_KMS("Disabling package C8+\n");
7940
7941 hsw_restore_lcpll(dev_priv);
7942 lpt_init_pch_refclk(dev);
7943
7944 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7945 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7946 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7947 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7948 }
7949
7950 intel_prepare_ddi(dev);
7951 }
7952
7953 static void snb_modeset_global_resources(struct drm_device *dev)
7954 {
7955 modeset_update_crtc_power_domains(dev);
7956 }
7957
7958 static void haswell_modeset_global_resources(struct drm_device *dev)
7959 {
7960 modeset_update_crtc_power_domains(dev);
7961 }
7962
7963 static int haswell_crtc_compute_clock(struct intel_crtc *crtc)
7964 {
7965 if (!intel_ddi_pll_select(crtc))
7966 return -EINVAL;
7967
7968 crtc->lowfreq_avail = false;
7969
7970 return 0;
7971 }
7972
7973 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
7974 enum port port,
7975 struct intel_crtc_config *pipe_config)
7976 {
7977 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
7978
7979 switch (pipe_config->ddi_pll_sel) {
7980 case PORT_CLK_SEL_WRPLL1:
7981 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
7982 break;
7983 case PORT_CLK_SEL_WRPLL2:
7984 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
7985 break;
7986 }
7987 }
7988
7989 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
7990 struct intel_crtc_config *pipe_config)
7991 {
7992 struct drm_device *dev = crtc->base.dev;
7993 struct drm_i915_private *dev_priv = dev->dev_private;
7994 struct intel_shared_dpll *pll;
7995 enum port port;
7996 uint32_t tmp;
7997
7998 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7999
8000 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8001
8002 haswell_get_ddi_pll(dev_priv, port, pipe_config);
8003
8004 if (pipe_config->shared_dpll >= 0) {
8005 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8006
8007 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8008 &pipe_config->dpll_hw_state));
8009 }
8010
8011 /*
8012 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8013 * DDI E. So just check whether this pipe is wired to DDI E and whether
8014 * the PCH transcoder is on.
8015 */
8016 if (INTEL_INFO(dev)->gen < 9 &&
8017 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
8018 pipe_config->has_pch_encoder = true;
8019
8020 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8021 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8022 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8023
8024 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8025 }
8026 }
8027
8028 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
8029 struct intel_crtc_config *pipe_config)
8030 {
8031 struct drm_device *dev = crtc->base.dev;
8032 struct drm_i915_private *dev_priv = dev->dev_private;
8033 enum intel_display_power_domain pfit_domain;
8034 uint32_t tmp;
8035
8036 if (!intel_display_power_is_enabled(dev_priv,
8037 POWER_DOMAIN_PIPE(crtc->pipe)))
8038 return false;
8039
8040 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8041 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8042
8043 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8044 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8045 enum pipe trans_edp_pipe;
8046 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8047 default:
8048 WARN(1, "unknown pipe linked to edp transcoder\n");
8049 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8050 case TRANS_DDI_EDP_INPUT_A_ON:
8051 trans_edp_pipe = PIPE_A;
8052 break;
8053 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8054 trans_edp_pipe = PIPE_B;
8055 break;
8056 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8057 trans_edp_pipe = PIPE_C;
8058 break;
8059 }
8060
8061 if (trans_edp_pipe == crtc->pipe)
8062 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8063 }
8064
8065 if (!intel_display_power_is_enabled(dev_priv,
8066 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
8067 return false;
8068
8069 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
8070 if (!(tmp & PIPECONF_ENABLE))
8071 return false;
8072
8073 haswell_get_ddi_port_state(crtc, pipe_config);
8074
8075 intel_get_pipe_timings(crtc, pipe_config);
8076
8077 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
8078 if (intel_display_power_is_enabled(dev_priv, pfit_domain))
8079 ironlake_get_pfit_config(crtc, pipe_config);
8080
8081 if (IS_HASWELL(dev))
8082 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8083 (I915_READ(IPS_CTL) & IPS_ENABLE);
8084
8085 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8086 pipe_config->pixel_multiplier =
8087 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8088 } else {
8089 pipe_config->pixel_multiplier = 1;
8090 }
8091
8092 return true;
8093 }
8094
8095 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8096 {
8097 struct drm_device *dev = crtc->dev;
8098 struct drm_i915_private *dev_priv = dev->dev_private;
8099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8100 uint32_t cntl = 0, size = 0;
8101
8102 if (base) {
8103 unsigned int width = intel_crtc->cursor_width;
8104 unsigned int height = intel_crtc->cursor_height;
8105 unsigned int stride = roundup_pow_of_two(width) * 4;
8106
8107 switch (stride) {
8108 default:
8109 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8110 width, stride);
8111 stride = 256;
8112 /* fallthrough */
8113 case 256:
8114 case 512:
8115 case 1024:
8116 case 2048:
8117 break;
8118 }
8119
8120 cntl |= CURSOR_ENABLE |
8121 CURSOR_GAMMA_ENABLE |
8122 CURSOR_FORMAT_ARGB |
8123 CURSOR_STRIDE(stride);
8124
8125 size = (height << 12) | width;
8126 }
8127
8128 if (intel_crtc->cursor_cntl != 0 &&
8129 (intel_crtc->cursor_base != base ||
8130 intel_crtc->cursor_size != size ||
8131 intel_crtc->cursor_cntl != cntl)) {
8132 /* On these chipsets we can only modify the base/size/stride
8133 * whilst the cursor is disabled.
8134 */
8135 I915_WRITE(_CURACNTR, 0);
8136 POSTING_READ(_CURACNTR);
8137 intel_crtc->cursor_cntl = 0;
8138 }
8139
8140 if (intel_crtc->cursor_base != base) {
8141 I915_WRITE(_CURABASE, base);
8142 intel_crtc->cursor_base = base;
8143 }
8144
8145 if (intel_crtc->cursor_size != size) {
8146 I915_WRITE(CURSIZE, size);
8147 intel_crtc->cursor_size = size;
8148 }
8149
8150 if (intel_crtc->cursor_cntl != cntl) {
8151 I915_WRITE(_CURACNTR, cntl);
8152 POSTING_READ(_CURACNTR);
8153 intel_crtc->cursor_cntl = cntl;
8154 }
8155 }
8156
8157 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
8158 {
8159 struct drm_device *dev = crtc->dev;
8160 struct drm_i915_private *dev_priv = dev->dev_private;
8161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8162 int pipe = intel_crtc->pipe;
8163 uint32_t cntl;
8164
8165 cntl = 0;
8166 if (base) {
8167 cntl = MCURSOR_GAMMA_ENABLE;
8168 switch (intel_crtc->cursor_width) {
8169 case 64:
8170 cntl |= CURSOR_MODE_64_ARGB_AX;
8171 break;
8172 case 128:
8173 cntl |= CURSOR_MODE_128_ARGB_AX;
8174 break;
8175 case 256:
8176 cntl |= CURSOR_MODE_256_ARGB_AX;
8177 break;
8178 default:
8179 WARN_ON(1);
8180 return;
8181 }
8182 cntl |= pipe << 28; /* Connect to correct pipe */
8183
8184 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8185 cntl |= CURSOR_PIPE_CSC_ENABLE;
8186 }
8187
8188 if (to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180))
8189 cntl |= CURSOR_ROTATE_180;
8190
8191 if (intel_crtc->cursor_cntl != cntl) {
8192 I915_WRITE(CURCNTR(pipe), cntl);
8193 POSTING_READ(CURCNTR(pipe));
8194 intel_crtc->cursor_cntl = cntl;
8195 }
8196
8197 /* and commit changes on next vblank */
8198 I915_WRITE(CURBASE(pipe), base);
8199 POSTING_READ(CURBASE(pipe));
8200
8201 intel_crtc->cursor_base = base;
8202 }
8203
8204 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8205 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8206 bool on)
8207 {
8208 struct drm_device *dev = crtc->dev;
8209 struct drm_i915_private *dev_priv = dev->dev_private;
8210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8211 int pipe = intel_crtc->pipe;
8212 int x = crtc->cursor_x;
8213 int y = crtc->cursor_y;
8214 u32 base = 0, pos = 0;
8215
8216 if (on)
8217 base = intel_crtc->cursor_addr;
8218
8219 if (x >= intel_crtc->config.pipe_src_w)
8220 base = 0;
8221
8222 if (y >= intel_crtc->config.pipe_src_h)
8223 base = 0;
8224
8225 if (x < 0) {
8226 if (x + intel_crtc->cursor_width <= 0)
8227 base = 0;
8228
8229 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8230 x = -x;
8231 }
8232 pos |= x << CURSOR_X_SHIFT;
8233
8234 if (y < 0) {
8235 if (y + intel_crtc->cursor_height <= 0)
8236 base = 0;
8237
8238 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8239 y = -y;
8240 }
8241 pos |= y << CURSOR_Y_SHIFT;
8242
8243 if (base == 0 && intel_crtc->cursor_base == 0)
8244 return;
8245
8246 I915_WRITE(CURPOS(pipe), pos);
8247
8248 /* ILK+ do this automagically */
8249 if (HAS_GMCH_DISPLAY(dev) &&
8250 to_intel_plane(crtc->cursor)->rotation == BIT(DRM_ROTATE_180)) {
8251 base += (intel_crtc->cursor_height *
8252 intel_crtc->cursor_width - 1) * 4;
8253 }
8254
8255 if (IS_845G(dev) || IS_I865G(dev))
8256 i845_update_cursor(crtc, base);
8257 else
8258 i9xx_update_cursor(crtc, base);
8259 }
8260
8261 static bool cursor_size_ok(struct drm_device *dev,
8262 uint32_t width, uint32_t height)
8263 {
8264 if (width == 0 || height == 0)
8265 return false;
8266
8267 /*
8268 * 845g/865g are special in that they are only limited by
8269 * the width of their cursors, the height is arbitrary up to
8270 * the precision of the register. Everything else requires
8271 * square cursors, limited to a few power-of-two sizes.
8272 */
8273 if (IS_845G(dev) || IS_I865G(dev)) {
8274 if ((width & 63) != 0)
8275 return false;
8276
8277 if (width > (IS_845G(dev) ? 64 : 512))
8278 return false;
8279
8280 if (height > 1023)
8281 return false;
8282 } else {
8283 switch (width | height) {
8284 case 256:
8285 case 128:
8286 if (IS_GEN2(dev))
8287 return false;
8288 case 64:
8289 break;
8290 default:
8291 return false;
8292 }
8293 }
8294
8295 return true;
8296 }
8297
8298 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8299 struct drm_i915_gem_object *obj,
8300 uint32_t width, uint32_t height)
8301 {
8302 struct drm_device *dev = crtc->dev;
8303 struct drm_i915_private *dev_priv = dev->dev_private;
8304 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8305 enum pipe pipe = intel_crtc->pipe;
8306 unsigned old_width;
8307 uint32_t addr;
8308 int ret;
8309
8310 /* if we want to turn off the cursor ignore width and height */
8311 if (!obj) {
8312 DRM_DEBUG_KMS("cursor off\n");
8313 addr = 0;
8314 mutex_lock(&dev->struct_mutex);
8315 goto finish;
8316 }
8317
8318 /* we only need to pin inside GTT if cursor is non-phy */
8319 mutex_lock(&dev->struct_mutex);
8320 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8321 unsigned alignment;
8322
8323 /*
8324 * Global gtt pte registers are special registers which actually
8325 * forward writes to a chunk of system memory. Which means that
8326 * there is no risk that the register values disappear as soon
8327 * as we call intel_runtime_pm_put(), so it is correct to wrap
8328 * only the pin/unpin/fence and not more.
8329 */
8330 intel_runtime_pm_get(dev_priv);
8331
8332 /* Note that the w/a also requires 2 PTE of padding following
8333 * the bo. We currently fill all unused PTE with the shadow
8334 * page and so we should always have valid PTE following the
8335 * cursor preventing the VT-d warning.
8336 */
8337 alignment = 0;
8338 if (need_vtd_wa(dev))
8339 alignment = 64*1024;
8340
8341 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8342 if (ret) {
8343 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8344 intel_runtime_pm_put(dev_priv);
8345 goto fail_locked;
8346 }
8347
8348 ret = i915_gem_object_put_fence(obj);
8349 if (ret) {
8350 DRM_DEBUG_KMS("failed to release fence for cursor");
8351 intel_runtime_pm_put(dev_priv);
8352 goto fail_unpin;
8353 }
8354
8355 addr = i915_gem_obj_ggtt_offset(obj);
8356
8357 intel_runtime_pm_put(dev_priv);
8358 } else {
8359 int align = IS_I830(dev) ? 16 * 1024 : 256;
8360 ret = i915_gem_object_attach_phys(obj, align);
8361 if (ret) {
8362 DRM_DEBUG_KMS("failed to attach phys object\n");
8363 goto fail_locked;
8364 }
8365 addr = obj->phys_handle->busaddr;
8366 }
8367
8368 finish:
8369 if (intel_crtc->cursor_bo) {
8370 if (!INTEL_INFO(dev)->cursor_needs_physical)
8371 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8372 }
8373
8374 i915_gem_track_fb(intel_crtc->cursor_bo, obj,
8375 INTEL_FRONTBUFFER_CURSOR(pipe));
8376 mutex_unlock(&dev->struct_mutex);
8377
8378 old_width = intel_crtc->cursor_width;
8379
8380 intel_crtc->cursor_addr = addr;
8381 intel_crtc->cursor_bo = obj;
8382 intel_crtc->cursor_width = width;
8383 intel_crtc->cursor_height = height;
8384
8385 if (intel_crtc->active) {
8386 if (old_width != width)
8387 intel_update_watermarks(crtc);
8388 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8389
8390 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe));
8391 }
8392
8393 return 0;
8394 fail_unpin:
8395 i915_gem_object_unpin_from_display_plane(obj);
8396 fail_locked:
8397 mutex_unlock(&dev->struct_mutex);
8398 return ret;
8399 }
8400
8401 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8402 u16 *blue, uint32_t start, uint32_t size)
8403 {
8404 int end = (start + size > 256) ? 256 : start + size, i;
8405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8406
8407 for (i = start; i < end; i++) {
8408 intel_crtc->lut_r[i] = red[i] >> 8;
8409 intel_crtc->lut_g[i] = green[i] >> 8;
8410 intel_crtc->lut_b[i] = blue[i] >> 8;
8411 }
8412
8413 intel_crtc_load_lut(crtc);
8414 }
8415
8416 /* VESA 640x480x72Hz mode to set on the pipe */
8417 static struct drm_display_mode load_detect_mode = {
8418 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8419 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8420 };
8421
8422 struct drm_framebuffer *
8423 __intel_framebuffer_create(struct drm_device *dev,
8424 struct drm_mode_fb_cmd2 *mode_cmd,
8425 struct drm_i915_gem_object *obj)
8426 {
8427 struct intel_framebuffer *intel_fb;
8428 int ret;
8429
8430 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8431 if (!intel_fb) {
8432 drm_gem_object_unreference_unlocked(&obj->base);
8433 return ERR_PTR(-ENOMEM);
8434 }
8435
8436 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8437 if (ret)
8438 goto err;
8439
8440 return &intel_fb->base;
8441 err:
8442 drm_gem_object_unreference_unlocked(&obj->base);
8443 kfree(intel_fb);
8444
8445 return ERR_PTR(ret);
8446 }
8447
8448 static struct drm_framebuffer *
8449 intel_framebuffer_create(struct drm_device *dev,
8450 struct drm_mode_fb_cmd2 *mode_cmd,
8451 struct drm_i915_gem_object *obj)
8452 {
8453 struct drm_framebuffer *fb;
8454 int ret;
8455
8456 ret = i915_mutex_lock_interruptible(dev);
8457 if (ret)
8458 return ERR_PTR(ret);
8459 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8460 mutex_unlock(&dev->struct_mutex);
8461
8462 return fb;
8463 }
8464
8465 static u32
8466 intel_framebuffer_pitch_for_width(int width, int bpp)
8467 {
8468 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8469 return ALIGN(pitch, 64);
8470 }
8471
8472 static u32
8473 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8474 {
8475 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8476 return PAGE_ALIGN(pitch * mode->vdisplay);
8477 }
8478
8479 static struct drm_framebuffer *
8480 intel_framebuffer_create_for_mode(struct drm_device *dev,
8481 struct drm_display_mode *mode,
8482 int depth, int bpp)
8483 {
8484 struct drm_i915_gem_object *obj;
8485 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8486
8487 obj = i915_gem_alloc_object(dev,
8488 intel_framebuffer_size_for_mode(mode, bpp));
8489 if (obj == NULL)
8490 return ERR_PTR(-ENOMEM);
8491
8492 mode_cmd.width = mode->hdisplay;
8493 mode_cmd.height = mode->vdisplay;
8494 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8495 bpp);
8496 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8497
8498 return intel_framebuffer_create(dev, &mode_cmd, obj);
8499 }
8500
8501 static struct drm_framebuffer *
8502 mode_fits_in_fbdev(struct drm_device *dev,
8503 struct drm_display_mode *mode)
8504 {
8505 #ifdef CONFIG_DRM_I915_FBDEV
8506 struct drm_i915_private *dev_priv = dev->dev_private;
8507 struct drm_i915_gem_object *obj;
8508 struct drm_framebuffer *fb;
8509
8510 if (!dev_priv->fbdev)
8511 return NULL;
8512
8513 if (!dev_priv->fbdev->fb)
8514 return NULL;
8515
8516 obj = dev_priv->fbdev->fb->obj;
8517 BUG_ON(!obj);
8518
8519 fb = &dev_priv->fbdev->fb->base;
8520 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8521 fb->bits_per_pixel))
8522 return NULL;
8523
8524 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8525 return NULL;
8526
8527 return fb;
8528 #else
8529 return NULL;
8530 #endif
8531 }
8532
8533 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8534 struct drm_display_mode *mode,
8535 struct intel_load_detect_pipe *old,
8536 struct drm_modeset_acquire_ctx *ctx)
8537 {
8538 struct intel_crtc *intel_crtc;
8539 struct intel_encoder *intel_encoder =
8540 intel_attached_encoder(connector);
8541 struct drm_crtc *possible_crtc;
8542 struct drm_encoder *encoder = &intel_encoder->base;
8543 struct drm_crtc *crtc = NULL;
8544 struct drm_device *dev = encoder->dev;
8545 struct drm_framebuffer *fb;
8546 struct drm_mode_config *config = &dev->mode_config;
8547 int ret, i = -1;
8548
8549 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8550 connector->base.id, connector->name,
8551 encoder->base.id, encoder->name);
8552
8553 retry:
8554 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8555 if (ret)
8556 goto fail_unlock;
8557
8558 /*
8559 * Algorithm gets a little messy:
8560 *
8561 * - if the connector already has an assigned crtc, use it (but make
8562 * sure it's on first)
8563 *
8564 * - try to find the first unused crtc that can drive this connector,
8565 * and use that if we find one
8566 */
8567
8568 /* See if we already have a CRTC for this connector */
8569 if (encoder->crtc) {
8570 crtc = encoder->crtc;
8571
8572 ret = drm_modeset_lock(&crtc->mutex, ctx);
8573 if (ret)
8574 goto fail_unlock;
8575
8576 old->dpms_mode = connector->dpms;
8577 old->load_detect_temp = false;
8578
8579 /* Make sure the crtc and connector are running */
8580 if (connector->dpms != DRM_MODE_DPMS_ON)
8581 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8582
8583 return true;
8584 }
8585
8586 /* Find an unused one (if possible) */
8587 for_each_crtc(dev, possible_crtc) {
8588 i++;
8589 if (!(encoder->possible_crtcs & (1 << i)))
8590 continue;
8591 if (possible_crtc->enabled)
8592 continue;
8593 /* This can occur when applying the pipe A quirk on resume. */
8594 if (to_intel_crtc(possible_crtc)->new_enabled)
8595 continue;
8596
8597 crtc = possible_crtc;
8598 break;
8599 }
8600
8601 /*
8602 * If we didn't find an unused CRTC, don't use any.
8603 */
8604 if (!crtc) {
8605 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8606 goto fail_unlock;
8607 }
8608
8609 ret = drm_modeset_lock(&crtc->mutex, ctx);
8610 if (ret)
8611 goto fail_unlock;
8612 intel_encoder->new_crtc = to_intel_crtc(crtc);
8613 to_intel_connector(connector)->new_encoder = intel_encoder;
8614
8615 intel_crtc = to_intel_crtc(crtc);
8616 intel_crtc->new_enabled = true;
8617 intel_crtc->new_config = &intel_crtc->config;
8618 old->dpms_mode = connector->dpms;
8619 old->load_detect_temp = true;
8620 old->release_fb = NULL;
8621
8622 if (!mode)
8623 mode = &load_detect_mode;
8624
8625 /* We need a framebuffer large enough to accommodate all accesses
8626 * that the plane may generate whilst we perform load detection.
8627 * We can not rely on the fbcon either being present (we get called
8628 * during its initialisation to detect all boot displays, or it may
8629 * not even exist) or that it is large enough to satisfy the
8630 * requested mode.
8631 */
8632 fb = mode_fits_in_fbdev(dev, mode);
8633 if (fb == NULL) {
8634 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8635 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8636 old->release_fb = fb;
8637 } else
8638 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8639 if (IS_ERR(fb)) {
8640 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8641 goto fail;
8642 }
8643
8644 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8645 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8646 if (old->release_fb)
8647 old->release_fb->funcs->destroy(old->release_fb);
8648 goto fail;
8649 }
8650
8651 /* let the connector get through one full cycle before testing */
8652 intel_wait_for_vblank(dev, intel_crtc->pipe);
8653 return true;
8654
8655 fail:
8656 intel_crtc->new_enabled = crtc->enabled;
8657 if (intel_crtc->new_enabled)
8658 intel_crtc->new_config = &intel_crtc->config;
8659 else
8660 intel_crtc->new_config = NULL;
8661 fail_unlock:
8662 if (ret == -EDEADLK) {
8663 drm_modeset_backoff(ctx);
8664 goto retry;
8665 }
8666
8667 return false;
8668 }
8669
8670 void intel_release_load_detect_pipe(struct drm_connector *connector,
8671 struct intel_load_detect_pipe *old)
8672 {
8673 struct intel_encoder *intel_encoder =
8674 intel_attached_encoder(connector);
8675 struct drm_encoder *encoder = &intel_encoder->base;
8676 struct drm_crtc *crtc = encoder->crtc;
8677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8678
8679 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8680 connector->base.id, connector->name,
8681 encoder->base.id, encoder->name);
8682
8683 if (old->load_detect_temp) {
8684 to_intel_connector(connector)->new_encoder = NULL;
8685 intel_encoder->new_crtc = NULL;
8686 intel_crtc->new_enabled = false;
8687 intel_crtc->new_config = NULL;
8688 intel_set_mode(crtc, NULL, 0, 0, NULL);
8689
8690 if (old->release_fb) {
8691 drm_framebuffer_unregister_private(old->release_fb);
8692 drm_framebuffer_unreference(old->release_fb);
8693 }
8694
8695 return;
8696 }
8697
8698 /* Switch crtc and encoder back off if necessary */
8699 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8700 connector->funcs->dpms(connector, old->dpms_mode);
8701 }
8702
8703 static int i9xx_pll_refclk(struct drm_device *dev,
8704 const struct intel_crtc_config *pipe_config)
8705 {
8706 struct drm_i915_private *dev_priv = dev->dev_private;
8707 u32 dpll = pipe_config->dpll_hw_state.dpll;
8708
8709 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8710 return dev_priv->vbt.lvds_ssc_freq;
8711 else if (HAS_PCH_SPLIT(dev))
8712 return 120000;
8713 else if (!IS_GEN2(dev))
8714 return 96000;
8715 else
8716 return 48000;
8717 }
8718
8719 /* Returns the clock of the currently programmed mode of the given pipe. */
8720 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8721 struct intel_crtc_config *pipe_config)
8722 {
8723 struct drm_device *dev = crtc->base.dev;
8724 struct drm_i915_private *dev_priv = dev->dev_private;
8725 int pipe = pipe_config->cpu_transcoder;
8726 u32 dpll = pipe_config->dpll_hw_state.dpll;
8727 u32 fp;
8728 intel_clock_t clock;
8729 int refclk = i9xx_pll_refclk(dev, pipe_config);
8730
8731 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8732 fp = pipe_config->dpll_hw_state.fp0;
8733 else
8734 fp = pipe_config->dpll_hw_state.fp1;
8735
8736 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8737 if (IS_PINEVIEW(dev)) {
8738 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8739 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8740 } else {
8741 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8742 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8743 }
8744
8745 if (!IS_GEN2(dev)) {
8746 if (IS_PINEVIEW(dev))
8747 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8748 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8749 else
8750 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8751 DPLL_FPA01_P1_POST_DIV_SHIFT);
8752
8753 switch (dpll & DPLL_MODE_MASK) {
8754 case DPLLB_MODE_DAC_SERIAL:
8755 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8756 5 : 10;
8757 break;
8758 case DPLLB_MODE_LVDS:
8759 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8760 7 : 14;
8761 break;
8762 default:
8763 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8764 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8765 return;
8766 }
8767
8768 if (IS_PINEVIEW(dev))
8769 pineview_clock(refclk, &clock);
8770 else
8771 i9xx_clock(refclk, &clock);
8772 } else {
8773 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8774 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8775
8776 if (is_lvds) {
8777 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8778 DPLL_FPA01_P1_POST_DIV_SHIFT);
8779
8780 if (lvds & LVDS_CLKB_POWER_UP)
8781 clock.p2 = 7;
8782 else
8783 clock.p2 = 14;
8784 } else {
8785 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8786 clock.p1 = 2;
8787 else {
8788 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8789 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8790 }
8791 if (dpll & PLL_P2_DIVIDE_BY_4)
8792 clock.p2 = 4;
8793 else
8794 clock.p2 = 2;
8795 }
8796
8797 i9xx_clock(refclk, &clock);
8798 }
8799
8800 /*
8801 * This value includes pixel_multiplier. We will use
8802 * port_clock to compute adjusted_mode.crtc_clock in the
8803 * encoder's get_config() function.
8804 */
8805 pipe_config->port_clock = clock.dot;
8806 }
8807
8808 int intel_dotclock_calculate(int link_freq,
8809 const struct intel_link_m_n *m_n)
8810 {
8811 /*
8812 * The calculation for the data clock is:
8813 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8814 * But we want to avoid losing precison if possible, so:
8815 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8816 *
8817 * and the link clock is simpler:
8818 * link_clock = (m * link_clock) / n
8819 */
8820
8821 if (!m_n->link_n)
8822 return 0;
8823
8824 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8825 }
8826
8827 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8828 struct intel_crtc_config *pipe_config)
8829 {
8830 struct drm_device *dev = crtc->base.dev;
8831
8832 /* read out port_clock from the DPLL */
8833 i9xx_crtc_clock_get(crtc, pipe_config);
8834
8835 /*
8836 * This value does not include pixel_multiplier.
8837 * We will check that port_clock and adjusted_mode.crtc_clock
8838 * agree once we know their relationship in the encoder's
8839 * get_config() function.
8840 */
8841 pipe_config->adjusted_mode.crtc_clock =
8842 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8843 &pipe_config->fdi_m_n);
8844 }
8845
8846 /** Returns the currently programmed mode of the given pipe. */
8847 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8848 struct drm_crtc *crtc)
8849 {
8850 struct drm_i915_private *dev_priv = dev->dev_private;
8851 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8852 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8853 struct drm_display_mode *mode;
8854 struct intel_crtc_config pipe_config;
8855 int htot = I915_READ(HTOTAL(cpu_transcoder));
8856 int hsync = I915_READ(HSYNC(cpu_transcoder));
8857 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8858 int vsync = I915_READ(VSYNC(cpu_transcoder));
8859 enum pipe pipe = intel_crtc->pipe;
8860
8861 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8862 if (!mode)
8863 return NULL;
8864
8865 /*
8866 * Construct a pipe_config sufficient for getting the clock info
8867 * back out of crtc_clock_get.
8868 *
8869 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8870 * to use a real value here instead.
8871 */
8872 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8873 pipe_config.pixel_multiplier = 1;
8874 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8875 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8876 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8877 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8878
8879 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8880 mode->hdisplay = (htot & 0xffff) + 1;
8881 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8882 mode->hsync_start = (hsync & 0xffff) + 1;
8883 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8884 mode->vdisplay = (vtot & 0xffff) + 1;
8885 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8886 mode->vsync_start = (vsync & 0xffff) + 1;
8887 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8888
8889 drm_mode_set_name(mode);
8890
8891 return mode;
8892 }
8893
8894 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8895 {
8896 struct drm_device *dev = crtc->dev;
8897 struct drm_i915_private *dev_priv = dev->dev_private;
8898 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8899
8900 if (!HAS_GMCH_DISPLAY(dev))
8901 return;
8902
8903 if (!dev_priv->lvds_downclock_avail)
8904 return;
8905
8906 /*
8907 * Since this is called by a timer, we should never get here in
8908 * the manual case.
8909 */
8910 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8911 int pipe = intel_crtc->pipe;
8912 int dpll_reg = DPLL(pipe);
8913 int dpll;
8914
8915 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8916
8917 assert_panel_unlocked(dev_priv, pipe);
8918
8919 dpll = I915_READ(dpll_reg);
8920 dpll |= DISPLAY_RATE_SELECT_FPA1;
8921 I915_WRITE(dpll_reg, dpll);
8922 intel_wait_for_vblank(dev, pipe);
8923 dpll = I915_READ(dpll_reg);
8924 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8925 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8926 }
8927
8928 }
8929
8930 void intel_mark_busy(struct drm_device *dev)
8931 {
8932 struct drm_i915_private *dev_priv = dev->dev_private;
8933
8934 if (dev_priv->mm.busy)
8935 return;
8936
8937 intel_runtime_pm_get(dev_priv);
8938 i915_update_gfx_val(dev_priv);
8939 dev_priv->mm.busy = true;
8940 }
8941
8942 void intel_mark_idle(struct drm_device *dev)
8943 {
8944 struct drm_i915_private *dev_priv = dev->dev_private;
8945 struct drm_crtc *crtc;
8946
8947 if (!dev_priv->mm.busy)
8948 return;
8949
8950 dev_priv->mm.busy = false;
8951
8952 if (!i915.powersave)
8953 goto out;
8954
8955 for_each_crtc(dev, crtc) {
8956 if (!crtc->primary->fb)
8957 continue;
8958
8959 intel_decrease_pllclock(crtc);
8960 }
8961
8962 if (INTEL_INFO(dev)->gen >= 6)
8963 gen6_rps_idle(dev->dev_private);
8964
8965 out:
8966 intel_runtime_pm_put(dev_priv);
8967 }
8968
8969 static void intel_crtc_destroy(struct drm_crtc *crtc)
8970 {
8971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8972 struct drm_device *dev = crtc->dev;
8973 struct intel_unpin_work *work;
8974
8975 spin_lock_irq(&dev->event_lock);
8976 work = intel_crtc->unpin_work;
8977 intel_crtc->unpin_work = NULL;
8978 spin_unlock_irq(&dev->event_lock);
8979
8980 if (work) {
8981 cancel_work_sync(&work->work);
8982 kfree(work);
8983 }
8984
8985 drm_crtc_cleanup(crtc);
8986
8987 kfree(intel_crtc);
8988 }
8989
8990 static void intel_unpin_work_fn(struct work_struct *__work)
8991 {
8992 struct intel_unpin_work *work =
8993 container_of(__work, struct intel_unpin_work, work);
8994 struct drm_device *dev = work->crtc->dev;
8995 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
8996
8997 mutex_lock(&dev->struct_mutex);
8998 intel_unpin_fb_obj(work->old_fb_obj);
8999 drm_gem_object_unreference(&work->pending_flip_obj->base);
9000 drm_gem_object_unreference(&work->old_fb_obj->base);
9001
9002 intel_update_fbc(dev);
9003 mutex_unlock(&dev->struct_mutex);
9004
9005 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9006
9007 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9008 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9009
9010 kfree(work);
9011 }
9012
9013 static void do_intel_finish_page_flip(struct drm_device *dev,
9014 struct drm_crtc *crtc)
9015 {
9016 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9017 struct intel_unpin_work *work;
9018 unsigned long flags;
9019
9020 /* Ignore early vblank irqs */
9021 if (intel_crtc == NULL)
9022 return;
9023
9024 /*
9025 * This is called both by irq handlers and the reset code (to complete
9026 * lost pageflips) so needs the full irqsave spinlocks.
9027 */
9028 spin_lock_irqsave(&dev->event_lock, flags);
9029 work = intel_crtc->unpin_work;
9030
9031 /* Ensure we don't miss a work->pending update ... */
9032 smp_rmb();
9033
9034 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
9035 spin_unlock_irqrestore(&dev->event_lock, flags);
9036 return;
9037 }
9038
9039 page_flip_completed(intel_crtc);
9040
9041 spin_unlock_irqrestore(&dev->event_lock, flags);
9042 }
9043
9044 void intel_finish_page_flip(struct drm_device *dev, int pipe)
9045 {
9046 struct drm_i915_private *dev_priv = dev->dev_private;
9047 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9048
9049 do_intel_finish_page_flip(dev, crtc);
9050 }
9051
9052 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9053 {
9054 struct drm_i915_private *dev_priv = dev->dev_private;
9055 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9056
9057 do_intel_finish_page_flip(dev, crtc);
9058 }
9059
9060 /* Is 'a' after or equal to 'b'? */
9061 static bool g4x_flip_count_after_eq(u32 a, u32 b)
9062 {
9063 return !((a - b) & 0x80000000);
9064 }
9065
9066 static bool page_flip_finished(struct intel_crtc *crtc)
9067 {
9068 struct drm_device *dev = crtc->base.dev;
9069 struct drm_i915_private *dev_priv = dev->dev_private;
9070
9071 /*
9072 * The relevant registers doen't exist on pre-ctg.
9073 * As the flip done interrupt doesn't trigger for mmio
9074 * flips on gmch platforms, a flip count check isn't
9075 * really needed there. But since ctg has the registers,
9076 * include it in the check anyway.
9077 */
9078 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9079 return true;
9080
9081 /*
9082 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9083 * used the same base address. In that case the mmio flip might
9084 * have completed, but the CS hasn't even executed the flip yet.
9085 *
9086 * A flip count check isn't enough as the CS might have updated
9087 * the base address just after start of vblank, but before we
9088 * managed to process the interrupt. This means we'd complete the
9089 * CS flip too soon.
9090 *
9091 * Combining both checks should get us a good enough result. It may
9092 * still happen that the CS flip has been executed, but has not
9093 * yet actually completed. But in case the base address is the same
9094 * anyway, we don't really care.
9095 */
9096 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9097 crtc->unpin_work->gtt_offset &&
9098 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9099 crtc->unpin_work->flip_count);
9100 }
9101
9102 void intel_prepare_page_flip(struct drm_device *dev, int plane)
9103 {
9104 struct drm_i915_private *dev_priv = dev->dev_private;
9105 struct intel_crtc *intel_crtc =
9106 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9107 unsigned long flags;
9108
9109
9110 /*
9111 * This is called both by irq handlers and the reset code (to complete
9112 * lost pageflips) so needs the full irqsave spinlocks.
9113 *
9114 * NB: An MMIO update of the plane base pointer will also
9115 * generate a page-flip completion irq, i.e. every modeset
9116 * is also accompanied by a spurious intel_prepare_page_flip().
9117 */
9118 spin_lock_irqsave(&dev->event_lock, flags);
9119 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9120 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9121 spin_unlock_irqrestore(&dev->event_lock, flags);
9122 }
9123
9124 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9125 {
9126 /* Ensure that the work item is consistent when activating it ... */
9127 smp_wmb();
9128 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9129 /* and that it is marked active as soon as the irq could fire. */
9130 smp_wmb();
9131 }
9132
9133 static int intel_gen2_queue_flip(struct drm_device *dev,
9134 struct drm_crtc *crtc,
9135 struct drm_framebuffer *fb,
9136 struct drm_i915_gem_object *obj,
9137 struct intel_engine_cs *ring,
9138 uint32_t flags)
9139 {
9140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9141 u32 flip_mask;
9142 int ret;
9143
9144 ret = intel_ring_begin(ring, 6);
9145 if (ret)
9146 return ret;
9147
9148 /* Can't queue multiple flips, so wait for the previous
9149 * one to finish before executing the next.
9150 */
9151 if (intel_crtc->plane)
9152 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9153 else
9154 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9155 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9156 intel_ring_emit(ring, MI_NOOP);
9157 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9158 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9159 intel_ring_emit(ring, fb->pitches[0]);
9160 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9161 intel_ring_emit(ring, 0); /* aux display base address, unused */
9162
9163 intel_mark_page_flip_active(intel_crtc);
9164 __intel_ring_advance(ring);
9165 return 0;
9166 }
9167
9168 static int intel_gen3_queue_flip(struct drm_device *dev,
9169 struct drm_crtc *crtc,
9170 struct drm_framebuffer *fb,
9171 struct drm_i915_gem_object *obj,
9172 struct intel_engine_cs *ring,
9173 uint32_t flags)
9174 {
9175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9176 u32 flip_mask;
9177 int ret;
9178
9179 ret = intel_ring_begin(ring, 6);
9180 if (ret)
9181 return ret;
9182
9183 if (intel_crtc->plane)
9184 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9185 else
9186 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9187 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9188 intel_ring_emit(ring, MI_NOOP);
9189 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9190 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9191 intel_ring_emit(ring, fb->pitches[0]);
9192 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9193 intel_ring_emit(ring, MI_NOOP);
9194
9195 intel_mark_page_flip_active(intel_crtc);
9196 __intel_ring_advance(ring);
9197 return 0;
9198 }
9199
9200 static int intel_gen4_queue_flip(struct drm_device *dev,
9201 struct drm_crtc *crtc,
9202 struct drm_framebuffer *fb,
9203 struct drm_i915_gem_object *obj,
9204 struct intel_engine_cs *ring,
9205 uint32_t flags)
9206 {
9207 struct drm_i915_private *dev_priv = dev->dev_private;
9208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9209 uint32_t pf, pipesrc;
9210 int ret;
9211
9212 ret = intel_ring_begin(ring, 4);
9213 if (ret)
9214 return ret;
9215
9216 /* i965+ uses the linear or tiled offsets from the
9217 * Display Registers (which do not change across a page-flip)
9218 * so we need only reprogram the base address.
9219 */
9220 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9221 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9222 intel_ring_emit(ring, fb->pitches[0]);
9223 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9224 obj->tiling_mode);
9225
9226 /* XXX Enabling the panel-fitter across page-flip is so far
9227 * untested on non-native modes, so ignore it for now.
9228 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9229 */
9230 pf = 0;
9231 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9232 intel_ring_emit(ring, pf | pipesrc);
9233
9234 intel_mark_page_flip_active(intel_crtc);
9235 __intel_ring_advance(ring);
9236 return 0;
9237 }
9238
9239 static int intel_gen6_queue_flip(struct drm_device *dev,
9240 struct drm_crtc *crtc,
9241 struct drm_framebuffer *fb,
9242 struct drm_i915_gem_object *obj,
9243 struct intel_engine_cs *ring,
9244 uint32_t flags)
9245 {
9246 struct drm_i915_private *dev_priv = dev->dev_private;
9247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9248 uint32_t pf, pipesrc;
9249 int ret;
9250
9251 ret = intel_ring_begin(ring, 4);
9252 if (ret)
9253 return ret;
9254
9255 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9256 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9257 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9258 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9259
9260 /* Contrary to the suggestions in the documentation,
9261 * "Enable Panel Fitter" does not seem to be required when page
9262 * flipping with a non-native mode, and worse causes a normal
9263 * modeset to fail.
9264 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9265 */
9266 pf = 0;
9267 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9268 intel_ring_emit(ring, pf | pipesrc);
9269
9270 intel_mark_page_flip_active(intel_crtc);
9271 __intel_ring_advance(ring);
9272 return 0;
9273 }
9274
9275 static int intel_gen7_queue_flip(struct drm_device *dev,
9276 struct drm_crtc *crtc,
9277 struct drm_framebuffer *fb,
9278 struct drm_i915_gem_object *obj,
9279 struct intel_engine_cs *ring,
9280 uint32_t flags)
9281 {
9282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9283 uint32_t plane_bit = 0;
9284 int len, ret;
9285
9286 switch (intel_crtc->plane) {
9287 case PLANE_A:
9288 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9289 break;
9290 case PLANE_B:
9291 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9292 break;
9293 case PLANE_C:
9294 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9295 break;
9296 default:
9297 WARN_ONCE(1, "unknown plane in flip command\n");
9298 return -ENODEV;
9299 }
9300
9301 len = 4;
9302 if (ring->id == RCS) {
9303 len += 6;
9304 /*
9305 * On Gen 8, SRM is now taking an extra dword to accommodate
9306 * 48bits addresses, and we need a NOOP for the batch size to
9307 * stay even.
9308 */
9309 if (IS_GEN8(dev))
9310 len += 2;
9311 }
9312
9313 /*
9314 * BSpec MI_DISPLAY_FLIP for IVB:
9315 * "The full packet must be contained within the same cache line."
9316 *
9317 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9318 * cacheline, if we ever start emitting more commands before
9319 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9320 * then do the cacheline alignment, and finally emit the
9321 * MI_DISPLAY_FLIP.
9322 */
9323 ret = intel_ring_cacheline_align(ring);
9324 if (ret)
9325 return ret;
9326
9327 ret = intel_ring_begin(ring, len);
9328 if (ret)
9329 return ret;
9330
9331 /* Unmask the flip-done completion message. Note that the bspec says that
9332 * we should do this for both the BCS and RCS, and that we must not unmask
9333 * more than one flip event at any time (or ensure that one flip message
9334 * can be sent by waiting for flip-done prior to queueing new flips).
9335 * Experimentation says that BCS works despite DERRMR masking all
9336 * flip-done completion events and that unmasking all planes at once
9337 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9338 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9339 */
9340 if (ring->id == RCS) {
9341 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9342 intel_ring_emit(ring, DERRMR);
9343 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9344 DERRMR_PIPEB_PRI_FLIP_DONE |
9345 DERRMR_PIPEC_PRI_FLIP_DONE));
9346 if (IS_GEN8(dev))
9347 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9348 MI_SRM_LRM_GLOBAL_GTT);
9349 else
9350 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9351 MI_SRM_LRM_GLOBAL_GTT);
9352 intel_ring_emit(ring, DERRMR);
9353 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9354 if (IS_GEN8(dev)) {
9355 intel_ring_emit(ring, 0);
9356 intel_ring_emit(ring, MI_NOOP);
9357 }
9358 }
9359
9360 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9361 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9362 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9363 intel_ring_emit(ring, (MI_NOOP));
9364
9365 intel_mark_page_flip_active(intel_crtc);
9366 __intel_ring_advance(ring);
9367 return 0;
9368 }
9369
9370 static bool use_mmio_flip(struct intel_engine_cs *ring,
9371 struct drm_i915_gem_object *obj)
9372 {
9373 /*
9374 * This is not being used for older platforms, because
9375 * non-availability of flip done interrupt forces us to use
9376 * CS flips. Older platforms derive flip done using some clever
9377 * tricks involving the flip_pending status bits and vblank irqs.
9378 * So using MMIO flips there would disrupt this mechanism.
9379 */
9380
9381 if (ring == NULL)
9382 return true;
9383
9384 if (INTEL_INFO(ring->dev)->gen < 5)
9385 return false;
9386
9387 if (i915.use_mmio_flip < 0)
9388 return false;
9389 else if (i915.use_mmio_flip > 0)
9390 return true;
9391 else if (i915.enable_execlists)
9392 return true;
9393 else
9394 return ring != obj->ring;
9395 }
9396
9397 static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9398 {
9399 struct drm_device *dev = intel_crtc->base.dev;
9400 struct drm_i915_private *dev_priv = dev->dev_private;
9401 struct intel_framebuffer *intel_fb =
9402 to_intel_framebuffer(intel_crtc->base.primary->fb);
9403 struct drm_i915_gem_object *obj = intel_fb->obj;
9404 bool atomic_update;
9405 u32 start_vbl_count;
9406 u32 dspcntr;
9407 u32 reg;
9408
9409 intel_mark_page_flip_active(intel_crtc);
9410
9411 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9412
9413 reg = DSPCNTR(intel_crtc->plane);
9414 dspcntr = I915_READ(reg);
9415
9416 if (obj->tiling_mode != I915_TILING_NONE)
9417 dspcntr |= DISPPLANE_TILED;
9418 else
9419 dspcntr &= ~DISPPLANE_TILED;
9420
9421 I915_WRITE(reg, dspcntr);
9422
9423 I915_WRITE(DSPSURF(intel_crtc->plane),
9424 intel_crtc->unpin_work->gtt_offset);
9425 POSTING_READ(DSPSURF(intel_crtc->plane));
9426
9427 if (atomic_update)
9428 intel_pipe_update_end(intel_crtc, start_vbl_count);
9429
9430 spin_lock_irq(&dev_priv->mmio_flip_lock);
9431 intel_crtc->mmio_flip.status = INTEL_MMIO_FLIP_IDLE;
9432 spin_unlock_irq(&dev_priv->mmio_flip_lock);
9433 }
9434
9435 static void intel_mmio_flip_work_func(struct work_struct *work)
9436 {
9437 struct intel_crtc *intel_crtc =
9438 container_of(work, struct intel_crtc, mmio_flip.work);
9439
9440 intel_do_mmio_flip(intel_crtc);
9441 }
9442
9443 static int intel_postpone_flip(struct drm_i915_gem_object *obj)
9444 {
9445 struct intel_engine_cs *ring;
9446 int ret;
9447
9448 lockdep_assert_held(&obj->base.dev->struct_mutex);
9449
9450 if (!obj->last_write_seqno)
9451 return 0;
9452
9453 ring = obj->ring;
9454
9455 if (i915_seqno_passed(ring->get_seqno(ring, true),
9456 obj->last_write_seqno))
9457 return 0;
9458
9459 ret = i915_gem_check_olr(ring, obj->last_write_seqno);
9460 if (ret)
9461 return ret;
9462
9463 if (WARN_ON(!ring->irq_get(ring)))
9464 return 0;
9465
9466 return 1;
9467 }
9468
9469 void intel_notify_mmio_flip(struct intel_engine_cs *ring)
9470 {
9471 struct drm_i915_private *dev_priv = to_i915(ring->dev);
9472 struct intel_crtc *intel_crtc;
9473 unsigned long irq_flags;
9474 u32 seqno;
9475
9476 seqno = ring->get_seqno(ring, false);
9477
9478 spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags);
9479 for_each_intel_crtc(ring->dev, intel_crtc) {
9480 struct intel_mmio_flip *mmio_flip;
9481
9482 mmio_flip = &intel_crtc->mmio_flip;
9483 if (mmio_flip->status != INTEL_MMIO_FLIP_WAIT_RING)
9484 continue;
9485
9486 if (ring->id != mmio_flip->ring_id)
9487 continue;
9488
9489 if (i915_seqno_passed(seqno, mmio_flip->seqno)) {
9490 schedule_work(&intel_crtc->mmio_flip.work);
9491 mmio_flip->status = INTEL_MMIO_FLIP_WORK_SCHEDULED;
9492 ring->irq_put(ring);
9493 }
9494 }
9495 spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags);
9496 }
9497
9498 static int intel_queue_mmio_flip(struct drm_device *dev,
9499 struct drm_crtc *crtc,
9500 struct drm_framebuffer *fb,
9501 struct drm_i915_gem_object *obj,
9502 struct intel_engine_cs *ring,
9503 uint32_t flags)
9504 {
9505 struct drm_i915_private *dev_priv = dev->dev_private;
9506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9507 int ret;
9508
9509 if (WARN_ON(intel_crtc->mmio_flip.status != INTEL_MMIO_FLIP_IDLE))
9510 return -EBUSY;
9511
9512 ret = intel_postpone_flip(obj);
9513 if (ret < 0)
9514 return ret;
9515 if (ret == 0) {
9516 intel_do_mmio_flip(intel_crtc);
9517 return 0;
9518 }
9519
9520 spin_lock_irq(&dev_priv->mmio_flip_lock);
9521 intel_crtc->mmio_flip.status = INTEL_MMIO_FLIP_WAIT_RING;
9522 intel_crtc->mmio_flip.seqno = obj->last_write_seqno;
9523 intel_crtc->mmio_flip.ring_id = obj->ring->id;
9524 spin_unlock_irq(&dev_priv->mmio_flip_lock);
9525
9526 /*
9527 * Double check to catch cases where irq fired before
9528 * mmio flip data was ready
9529 */
9530 intel_notify_mmio_flip(obj->ring);
9531 return 0;
9532 }
9533
9534 static int intel_default_queue_flip(struct drm_device *dev,
9535 struct drm_crtc *crtc,
9536 struct drm_framebuffer *fb,
9537 struct drm_i915_gem_object *obj,
9538 struct intel_engine_cs *ring,
9539 uint32_t flags)
9540 {
9541 return -ENODEV;
9542 }
9543
9544 static bool __intel_pageflip_stall_check(struct drm_device *dev,
9545 struct drm_crtc *crtc)
9546 {
9547 struct drm_i915_private *dev_priv = dev->dev_private;
9548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9549 struct intel_unpin_work *work = intel_crtc->unpin_work;
9550 u32 addr;
9551
9552 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9553 return true;
9554
9555 if (!work->enable_stall_check)
9556 return false;
9557
9558 if (work->flip_ready_vblank == 0) {
9559 if (work->flip_queued_ring &&
9560 !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true),
9561 work->flip_queued_seqno))
9562 return false;
9563
9564 work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9565 }
9566
9567 if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3)
9568 return false;
9569
9570 /* Potential stall - if we see that the flip has happened,
9571 * assume a missed interrupt. */
9572 if (INTEL_INFO(dev)->gen >= 4)
9573 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9574 else
9575 addr = I915_READ(DSPADDR(intel_crtc->plane));
9576
9577 /* There is a potential issue here with a false positive after a flip
9578 * to the same address. We could address this by checking for a
9579 * non-incrementing frame counter.
9580 */
9581 return addr == work->gtt_offset;
9582 }
9583
9584 void intel_check_page_flip(struct drm_device *dev, int pipe)
9585 {
9586 struct drm_i915_private *dev_priv = dev->dev_private;
9587 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9589
9590 WARN_ON(!in_irq());
9591
9592 if (crtc == NULL)
9593 return;
9594
9595 spin_lock(&dev->event_lock);
9596 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9597 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
9598 intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe));
9599 page_flip_completed(intel_crtc);
9600 }
9601 spin_unlock(&dev->event_lock);
9602 }
9603
9604 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9605 struct drm_framebuffer *fb,
9606 struct drm_pending_vblank_event *event,
9607 uint32_t page_flip_flags)
9608 {
9609 struct drm_device *dev = crtc->dev;
9610 struct drm_i915_private *dev_priv = dev->dev_private;
9611 struct drm_framebuffer *old_fb = crtc->primary->fb;
9612 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
9613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9614 enum pipe pipe = intel_crtc->pipe;
9615 struct intel_unpin_work *work;
9616 struct intel_engine_cs *ring;
9617 int ret;
9618
9619 /*
9620 * drm_mode_page_flip_ioctl() should already catch this, but double
9621 * check to be safe. In the future we may enable pageflipping from
9622 * a disabled primary plane.
9623 */
9624 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9625 return -EBUSY;
9626
9627 /* Can't change pixel format via MI display flips. */
9628 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9629 return -EINVAL;
9630
9631 /*
9632 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9633 * Note that pitch changes could also affect these register.
9634 */
9635 if (INTEL_INFO(dev)->gen > 3 &&
9636 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9637 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9638 return -EINVAL;
9639
9640 if (i915_terminally_wedged(&dev_priv->gpu_error))
9641 goto out_hang;
9642
9643 work = kzalloc(sizeof(*work), GFP_KERNEL);
9644 if (work == NULL)
9645 return -ENOMEM;
9646
9647 work->event = event;
9648 work->crtc = crtc;
9649 work->old_fb_obj = intel_fb_obj(old_fb);
9650 INIT_WORK(&work->work, intel_unpin_work_fn);
9651
9652 ret = drm_crtc_vblank_get(crtc);
9653 if (ret)
9654 goto free_work;
9655
9656 /* We borrow the event spin lock for protecting unpin_work */
9657 spin_lock_irq(&dev->event_lock);
9658 if (intel_crtc->unpin_work) {
9659 /* Before declaring the flip queue wedged, check if
9660 * the hardware completed the operation behind our backs.
9661 */
9662 if (__intel_pageflip_stall_check(dev, crtc)) {
9663 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
9664 page_flip_completed(intel_crtc);
9665 } else {
9666 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9667 spin_unlock_irq(&dev->event_lock);
9668
9669 drm_crtc_vblank_put(crtc);
9670 kfree(work);
9671 return -EBUSY;
9672 }
9673 }
9674 intel_crtc->unpin_work = work;
9675 spin_unlock_irq(&dev->event_lock);
9676
9677 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9678 flush_workqueue(dev_priv->wq);
9679
9680 ret = i915_mutex_lock_interruptible(dev);
9681 if (ret)
9682 goto cleanup;
9683
9684 /* Reference the objects for the scheduled work. */
9685 drm_gem_object_reference(&work->old_fb_obj->base);
9686 drm_gem_object_reference(&obj->base);
9687
9688 crtc->primary->fb = fb;
9689
9690 work->pending_flip_obj = obj;
9691
9692 atomic_inc(&intel_crtc->unpin_work_count);
9693 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9694
9695 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9696 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
9697
9698 if (IS_VALLEYVIEW(dev)) {
9699 ring = &dev_priv->ring[BCS];
9700 if (obj->tiling_mode != work->old_fb_obj->tiling_mode)
9701 /* vlv: DISPLAY_FLIP fails to change tiling */
9702 ring = NULL;
9703 } else if (IS_IVYBRIDGE(dev)) {
9704 ring = &dev_priv->ring[BCS];
9705 } else if (INTEL_INFO(dev)->gen >= 7) {
9706 ring = obj->ring;
9707 if (ring == NULL || ring->id != RCS)
9708 ring = &dev_priv->ring[BCS];
9709 } else {
9710 ring = &dev_priv->ring[RCS];
9711 }
9712
9713 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, ring);
9714 if (ret)
9715 goto cleanup_pending;
9716
9717 work->gtt_offset =
9718 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9719
9720 if (use_mmio_flip(ring, obj)) {
9721 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
9722 page_flip_flags);
9723 if (ret)
9724 goto cleanup_unpin;
9725
9726 work->flip_queued_seqno = obj->last_write_seqno;
9727 work->flip_queued_ring = obj->ring;
9728 } else {
9729 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
9730 page_flip_flags);
9731 if (ret)
9732 goto cleanup_unpin;
9733
9734 work->flip_queued_seqno = intel_ring_get_seqno(ring);
9735 work->flip_queued_ring = ring;
9736 }
9737
9738 work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe);
9739 work->enable_stall_check = true;
9740
9741 i915_gem_track_fb(work->old_fb_obj, obj,
9742 INTEL_FRONTBUFFER_PRIMARY(pipe));
9743
9744 intel_disable_fbc(dev);
9745 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
9746 mutex_unlock(&dev->struct_mutex);
9747
9748 trace_i915_flip_request(intel_crtc->plane, obj);
9749
9750 return 0;
9751
9752 cleanup_unpin:
9753 intel_unpin_fb_obj(obj);
9754 cleanup_pending:
9755 atomic_dec(&intel_crtc->unpin_work_count);
9756 crtc->primary->fb = old_fb;
9757 drm_gem_object_unreference(&work->old_fb_obj->base);
9758 drm_gem_object_unreference(&obj->base);
9759 mutex_unlock(&dev->struct_mutex);
9760
9761 cleanup:
9762 spin_lock_irq(&dev->event_lock);
9763 intel_crtc->unpin_work = NULL;
9764 spin_unlock_irq(&dev->event_lock);
9765
9766 drm_crtc_vblank_put(crtc);
9767 free_work:
9768 kfree(work);
9769
9770 if (ret == -EIO) {
9771 out_hang:
9772 intel_crtc_wait_for_pending_flips(crtc);
9773 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9774 if (ret == 0 && event) {
9775 spin_lock_irq(&dev->event_lock);
9776 drm_send_vblank_event(dev, pipe, event);
9777 spin_unlock_irq(&dev->event_lock);
9778 }
9779 }
9780 return ret;
9781 }
9782
9783 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9784 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9785 .load_lut = intel_crtc_load_lut,
9786 };
9787
9788 /**
9789 * intel_modeset_update_staged_output_state
9790 *
9791 * Updates the staged output configuration state, e.g. after we've read out the
9792 * current hw state.
9793 */
9794 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9795 {
9796 struct intel_crtc *crtc;
9797 struct intel_encoder *encoder;
9798 struct intel_connector *connector;
9799
9800 list_for_each_entry(connector, &dev->mode_config.connector_list,
9801 base.head) {
9802 connector->new_encoder =
9803 to_intel_encoder(connector->base.encoder);
9804 }
9805
9806 for_each_intel_encoder(dev, encoder) {
9807 encoder->new_crtc =
9808 to_intel_crtc(encoder->base.crtc);
9809 }
9810
9811 for_each_intel_crtc(dev, crtc) {
9812 crtc->new_enabled = crtc->base.enabled;
9813
9814 if (crtc->new_enabled)
9815 crtc->new_config = &crtc->config;
9816 else
9817 crtc->new_config = NULL;
9818 }
9819 }
9820
9821 /**
9822 * intel_modeset_commit_output_state
9823 *
9824 * This function copies the stage display pipe configuration to the real one.
9825 */
9826 static void intel_modeset_commit_output_state(struct drm_device *dev)
9827 {
9828 struct intel_crtc *crtc;
9829 struct intel_encoder *encoder;
9830 struct intel_connector *connector;
9831
9832 list_for_each_entry(connector, &dev->mode_config.connector_list,
9833 base.head) {
9834 connector->base.encoder = &connector->new_encoder->base;
9835 }
9836
9837 for_each_intel_encoder(dev, encoder) {
9838 encoder->base.crtc = &encoder->new_crtc->base;
9839 }
9840
9841 for_each_intel_crtc(dev, crtc) {
9842 crtc->base.enabled = crtc->new_enabled;
9843 }
9844 }
9845
9846 static void
9847 connected_sink_compute_bpp(struct intel_connector *connector,
9848 struct intel_crtc_config *pipe_config)
9849 {
9850 int bpp = pipe_config->pipe_bpp;
9851
9852 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9853 connector->base.base.id,
9854 connector->base.name);
9855
9856 /* Don't use an invalid EDID bpc value */
9857 if (connector->base.display_info.bpc &&
9858 connector->base.display_info.bpc * 3 < bpp) {
9859 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9860 bpp, connector->base.display_info.bpc*3);
9861 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9862 }
9863
9864 /* Clamp bpp to 8 on screens without EDID 1.4 */
9865 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9866 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9867 bpp);
9868 pipe_config->pipe_bpp = 24;
9869 }
9870 }
9871
9872 static int
9873 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9874 struct drm_framebuffer *fb,
9875 struct intel_crtc_config *pipe_config)
9876 {
9877 struct drm_device *dev = crtc->base.dev;
9878 struct intel_connector *connector;
9879 int bpp;
9880
9881 switch (fb->pixel_format) {
9882 case DRM_FORMAT_C8:
9883 bpp = 8*3; /* since we go through a colormap */
9884 break;
9885 case DRM_FORMAT_XRGB1555:
9886 case DRM_FORMAT_ARGB1555:
9887 /* checked in intel_framebuffer_init already */
9888 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9889 return -EINVAL;
9890 case DRM_FORMAT_RGB565:
9891 bpp = 6*3; /* min is 18bpp */
9892 break;
9893 case DRM_FORMAT_XBGR8888:
9894 case DRM_FORMAT_ABGR8888:
9895 /* checked in intel_framebuffer_init already */
9896 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9897 return -EINVAL;
9898 case DRM_FORMAT_XRGB8888:
9899 case DRM_FORMAT_ARGB8888:
9900 bpp = 8*3;
9901 break;
9902 case DRM_FORMAT_XRGB2101010:
9903 case DRM_FORMAT_ARGB2101010:
9904 case DRM_FORMAT_XBGR2101010:
9905 case DRM_FORMAT_ABGR2101010:
9906 /* checked in intel_framebuffer_init already */
9907 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9908 return -EINVAL;
9909 bpp = 10*3;
9910 break;
9911 /* TODO: gen4+ supports 16 bpc floating point, too. */
9912 default:
9913 DRM_DEBUG_KMS("unsupported depth\n");
9914 return -EINVAL;
9915 }
9916
9917 pipe_config->pipe_bpp = bpp;
9918
9919 /* Clamp display bpp to EDID value */
9920 list_for_each_entry(connector, &dev->mode_config.connector_list,
9921 base.head) {
9922 if (!connector->new_encoder ||
9923 connector->new_encoder->new_crtc != crtc)
9924 continue;
9925
9926 connected_sink_compute_bpp(connector, pipe_config);
9927 }
9928
9929 return bpp;
9930 }
9931
9932 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9933 {
9934 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9935 "type: 0x%x flags: 0x%x\n",
9936 mode->crtc_clock,
9937 mode->crtc_hdisplay, mode->crtc_hsync_start,
9938 mode->crtc_hsync_end, mode->crtc_htotal,
9939 mode->crtc_vdisplay, mode->crtc_vsync_start,
9940 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9941 }
9942
9943 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9944 struct intel_crtc_config *pipe_config,
9945 const char *context)
9946 {
9947 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9948 context, pipe_name(crtc->pipe));
9949
9950 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9951 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9952 pipe_config->pipe_bpp, pipe_config->dither);
9953 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9954 pipe_config->has_pch_encoder,
9955 pipe_config->fdi_lanes,
9956 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9957 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9958 pipe_config->fdi_m_n.tu);
9959 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9960 pipe_config->has_dp_encoder,
9961 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9962 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9963 pipe_config->dp_m_n.tu);
9964
9965 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
9966 pipe_config->has_dp_encoder,
9967 pipe_config->dp_m2_n2.gmch_m,
9968 pipe_config->dp_m2_n2.gmch_n,
9969 pipe_config->dp_m2_n2.link_m,
9970 pipe_config->dp_m2_n2.link_n,
9971 pipe_config->dp_m2_n2.tu);
9972
9973 DRM_DEBUG_KMS("requested mode:\n");
9974 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9975 DRM_DEBUG_KMS("adjusted mode:\n");
9976 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9977 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9978 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9979 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9980 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9981 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9982 pipe_config->gmch_pfit.control,
9983 pipe_config->gmch_pfit.pgm_ratios,
9984 pipe_config->gmch_pfit.lvds_border_bits);
9985 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9986 pipe_config->pch_pfit.pos,
9987 pipe_config->pch_pfit.size,
9988 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9989 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9990 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9991 }
9992
9993 static bool encoders_cloneable(const struct intel_encoder *a,
9994 const struct intel_encoder *b)
9995 {
9996 /* masks could be asymmetric, so check both ways */
9997 return a == b || (a->cloneable & (1 << b->type) &&
9998 b->cloneable & (1 << a->type));
9999 }
10000
10001 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10002 struct intel_encoder *encoder)
10003 {
10004 struct drm_device *dev = crtc->base.dev;
10005 struct intel_encoder *source_encoder;
10006
10007 for_each_intel_encoder(dev, source_encoder) {
10008 if (source_encoder->new_crtc != crtc)
10009 continue;
10010
10011 if (!encoders_cloneable(encoder, source_encoder))
10012 return false;
10013 }
10014
10015 return true;
10016 }
10017
10018 static bool check_encoder_cloning(struct intel_crtc *crtc)
10019 {
10020 struct drm_device *dev = crtc->base.dev;
10021 struct intel_encoder *encoder;
10022
10023 for_each_intel_encoder(dev, encoder) {
10024 if (encoder->new_crtc != crtc)
10025 continue;
10026
10027 if (!check_single_encoder_cloning(crtc, encoder))
10028 return false;
10029 }
10030
10031 return true;
10032 }
10033
10034 static struct intel_crtc_config *
10035 intel_modeset_pipe_config(struct drm_crtc *crtc,
10036 struct drm_framebuffer *fb,
10037 struct drm_display_mode *mode)
10038 {
10039 struct drm_device *dev = crtc->dev;
10040 struct intel_encoder *encoder;
10041 struct intel_crtc_config *pipe_config;
10042 int plane_bpp, ret = -EINVAL;
10043 bool retry = true;
10044
10045 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
10046 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10047 return ERR_PTR(-EINVAL);
10048 }
10049
10050 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10051 if (!pipe_config)
10052 return ERR_PTR(-ENOMEM);
10053
10054 drm_mode_copy(&pipe_config->adjusted_mode, mode);
10055 drm_mode_copy(&pipe_config->requested_mode, mode);
10056
10057 pipe_config->cpu_transcoder =
10058 (enum transcoder) to_intel_crtc(crtc)->pipe;
10059 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10060
10061 /*
10062 * Sanitize sync polarity flags based on requested ones. If neither
10063 * positive or negative polarity is requested, treat this as meaning
10064 * negative polarity.
10065 */
10066 if (!(pipe_config->adjusted_mode.flags &
10067 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
10068 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
10069
10070 if (!(pipe_config->adjusted_mode.flags &
10071 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
10072 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
10073
10074 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10075 * plane pixel format and any sink constraints into account. Returns the
10076 * source plane bpp so that dithering can be selected on mismatches
10077 * after encoders and crtc also have had their say. */
10078 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10079 fb, pipe_config);
10080 if (plane_bpp < 0)
10081 goto fail;
10082
10083 /*
10084 * Determine the real pipe dimensions. Note that stereo modes can
10085 * increase the actual pipe size due to the frame doubling and
10086 * insertion of additional space for blanks between the frame. This
10087 * is stored in the crtc timings. We use the requested mode to do this
10088 * computation to clearly distinguish it from the adjusted mode, which
10089 * can be changed by the connectors in the below retry loop.
10090 */
10091 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
10092 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
10093 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
10094
10095 encoder_retry:
10096 /* Ensure the port clock defaults are reset when retrying. */
10097 pipe_config->port_clock = 0;
10098 pipe_config->pixel_multiplier = 1;
10099
10100 /* Fill in default crtc timings, allow encoders to overwrite them. */
10101 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
10102
10103 /* Pass our mode to the connectors and the CRTC to give them a chance to
10104 * adjust it according to limitations or connector properties, and also
10105 * a chance to reject the mode entirely.
10106 */
10107 for_each_intel_encoder(dev, encoder) {
10108
10109 if (&encoder->new_crtc->base != crtc)
10110 continue;
10111
10112 if (!(encoder->compute_config(encoder, pipe_config))) {
10113 DRM_DEBUG_KMS("Encoder config failure\n");
10114 goto fail;
10115 }
10116 }
10117
10118 /* Set default port clock if not overwritten by the encoder. Needs to be
10119 * done afterwards in case the encoder adjusts the mode. */
10120 if (!pipe_config->port_clock)
10121 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
10122 * pipe_config->pixel_multiplier;
10123
10124 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
10125 if (ret < 0) {
10126 DRM_DEBUG_KMS("CRTC fixup failed\n");
10127 goto fail;
10128 }
10129
10130 if (ret == RETRY) {
10131 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10132 ret = -EINVAL;
10133 goto fail;
10134 }
10135
10136 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10137 retry = false;
10138 goto encoder_retry;
10139 }
10140
10141 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10142 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10143 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10144
10145 return pipe_config;
10146 fail:
10147 kfree(pipe_config);
10148 return ERR_PTR(ret);
10149 }
10150
10151 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
10152 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10153 static void
10154 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10155 unsigned *prepare_pipes, unsigned *disable_pipes)
10156 {
10157 struct intel_crtc *intel_crtc;
10158 struct drm_device *dev = crtc->dev;
10159 struct intel_encoder *encoder;
10160 struct intel_connector *connector;
10161 struct drm_crtc *tmp_crtc;
10162
10163 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
10164
10165 /* Check which crtcs have changed outputs connected to them, these need
10166 * to be part of the prepare_pipes mask. We don't (yet) support global
10167 * modeset across multiple crtcs, so modeset_pipes will only have one
10168 * bit set at most. */
10169 list_for_each_entry(connector, &dev->mode_config.connector_list,
10170 base.head) {
10171 if (connector->base.encoder == &connector->new_encoder->base)
10172 continue;
10173
10174 if (connector->base.encoder) {
10175 tmp_crtc = connector->base.encoder->crtc;
10176
10177 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10178 }
10179
10180 if (connector->new_encoder)
10181 *prepare_pipes |=
10182 1 << connector->new_encoder->new_crtc->pipe;
10183 }
10184
10185 for_each_intel_encoder(dev, encoder) {
10186 if (encoder->base.crtc == &encoder->new_crtc->base)
10187 continue;
10188
10189 if (encoder->base.crtc) {
10190 tmp_crtc = encoder->base.crtc;
10191
10192 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10193 }
10194
10195 if (encoder->new_crtc)
10196 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
10197 }
10198
10199 /* Check for pipes that will be enabled/disabled ... */
10200 for_each_intel_crtc(dev, intel_crtc) {
10201 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
10202 continue;
10203
10204 if (!intel_crtc->new_enabled)
10205 *disable_pipes |= 1 << intel_crtc->pipe;
10206 else
10207 *prepare_pipes |= 1 << intel_crtc->pipe;
10208 }
10209
10210
10211 /* set_mode is also used to update properties on life display pipes. */
10212 intel_crtc = to_intel_crtc(crtc);
10213 if (intel_crtc->new_enabled)
10214 *prepare_pipes |= 1 << intel_crtc->pipe;
10215
10216 /*
10217 * For simplicity do a full modeset on any pipe where the output routing
10218 * changed. We could be more clever, but that would require us to be
10219 * more careful with calling the relevant encoder->mode_set functions.
10220 */
10221 if (*prepare_pipes)
10222 *modeset_pipes = *prepare_pipes;
10223
10224 /* ... and mask these out. */
10225 *modeset_pipes &= ~(*disable_pipes);
10226 *prepare_pipes &= ~(*disable_pipes);
10227
10228 /*
10229 * HACK: We don't (yet) fully support global modesets. intel_set_config
10230 * obies this rule, but the modeset restore mode of
10231 * intel_modeset_setup_hw_state does not.
10232 */
10233 *modeset_pipes &= 1 << intel_crtc->pipe;
10234 *prepare_pipes &= 1 << intel_crtc->pipe;
10235
10236 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10237 *modeset_pipes, *prepare_pipes, *disable_pipes);
10238 }
10239
10240 static bool intel_crtc_in_use(struct drm_crtc *crtc)
10241 {
10242 struct drm_encoder *encoder;
10243 struct drm_device *dev = crtc->dev;
10244
10245 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10246 if (encoder->crtc == crtc)
10247 return true;
10248
10249 return false;
10250 }
10251
10252 static void
10253 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10254 {
10255 struct drm_i915_private *dev_priv = dev->dev_private;
10256 struct intel_encoder *intel_encoder;
10257 struct intel_crtc *intel_crtc;
10258 struct drm_connector *connector;
10259
10260 intel_shared_dpll_commit(dev_priv);
10261
10262 for_each_intel_encoder(dev, intel_encoder) {
10263 if (!intel_encoder->base.crtc)
10264 continue;
10265
10266 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10267
10268 if (prepare_pipes & (1 << intel_crtc->pipe))
10269 intel_encoder->connectors_active = false;
10270 }
10271
10272 intel_modeset_commit_output_state(dev);
10273
10274 /* Double check state. */
10275 for_each_intel_crtc(dev, intel_crtc) {
10276 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
10277 WARN_ON(intel_crtc->new_config &&
10278 intel_crtc->new_config != &intel_crtc->config);
10279 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
10280 }
10281
10282 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10283 if (!connector->encoder || !connector->encoder->crtc)
10284 continue;
10285
10286 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10287
10288 if (prepare_pipes & (1 << intel_crtc->pipe)) {
10289 struct drm_property *dpms_property =
10290 dev->mode_config.dpms_property;
10291
10292 connector->dpms = DRM_MODE_DPMS_ON;
10293 drm_object_property_set_value(&connector->base,
10294 dpms_property,
10295 DRM_MODE_DPMS_ON);
10296
10297 intel_encoder = to_intel_encoder(connector->encoder);
10298 intel_encoder->connectors_active = true;
10299 }
10300 }
10301
10302 }
10303
10304 static bool intel_fuzzy_clock_check(int clock1, int clock2)
10305 {
10306 int diff;
10307
10308 if (clock1 == clock2)
10309 return true;
10310
10311 if (!clock1 || !clock2)
10312 return false;
10313
10314 diff = abs(clock1 - clock2);
10315
10316 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10317 return true;
10318
10319 return false;
10320 }
10321
10322 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10323 list_for_each_entry((intel_crtc), \
10324 &(dev)->mode_config.crtc_list, \
10325 base.head) \
10326 if (mask & (1 <<(intel_crtc)->pipe))
10327
10328 static bool
10329 intel_pipe_config_compare(struct drm_device *dev,
10330 struct intel_crtc_config *current_config,
10331 struct intel_crtc_config *pipe_config)
10332 {
10333 #define PIPE_CONF_CHECK_X(name) \
10334 if (current_config->name != pipe_config->name) { \
10335 DRM_ERROR("mismatch in " #name " " \
10336 "(expected 0x%08x, found 0x%08x)\n", \
10337 current_config->name, \
10338 pipe_config->name); \
10339 return false; \
10340 }
10341
10342 #define PIPE_CONF_CHECK_I(name) \
10343 if (current_config->name != pipe_config->name) { \
10344 DRM_ERROR("mismatch in " #name " " \
10345 "(expected %i, found %i)\n", \
10346 current_config->name, \
10347 pipe_config->name); \
10348 return false; \
10349 }
10350
10351 /* This is required for BDW+ where there is only one set of registers for
10352 * switching between high and low RR.
10353 * This macro can be used whenever a comparison has to be made between one
10354 * hw state and multiple sw state variables.
10355 */
10356 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10357 if ((current_config->name != pipe_config->name) && \
10358 (current_config->alt_name != pipe_config->name)) { \
10359 DRM_ERROR("mismatch in " #name " " \
10360 "(expected %i or %i, found %i)\n", \
10361 current_config->name, \
10362 current_config->alt_name, \
10363 pipe_config->name); \
10364 return false; \
10365 }
10366
10367 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
10368 if ((current_config->name ^ pipe_config->name) & (mask)) { \
10369 DRM_ERROR("mismatch in " #name "(" #mask ") " \
10370 "(expected %i, found %i)\n", \
10371 current_config->name & (mask), \
10372 pipe_config->name & (mask)); \
10373 return false; \
10374 }
10375
10376 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10377 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10378 DRM_ERROR("mismatch in " #name " " \
10379 "(expected %i, found %i)\n", \
10380 current_config->name, \
10381 pipe_config->name); \
10382 return false; \
10383 }
10384
10385 #define PIPE_CONF_QUIRK(quirk) \
10386 ((current_config->quirks | pipe_config->quirks) & (quirk))
10387
10388 PIPE_CONF_CHECK_I(cpu_transcoder);
10389
10390 PIPE_CONF_CHECK_I(has_pch_encoder);
10391 PIPE_CONF_CHECK_I(fdi_lanes);
10392 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10393 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10394 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10395 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10396 PIPE_CONF_CHECK_I(fdi_m_n.tu);
10397
10398 PIPE_CONF_CHECK_I(has_dp_encoder);
10399
10400 if (INTEL_INFO(dev)->gen < 8) {
10401 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10402 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10403 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10404 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10405 PIPE_CONF_CHECK_I(dp_m_n.tu);
10406
10407 if (current_config->has_drrs) {
10408 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10409 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10410 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10411 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10412 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10413 }
10414 } else {
10415 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10416 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10417 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10418 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10419 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10420 }
10421
10422 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10423 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10424 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10425 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10426 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10427 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10428
10429 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10430 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10431 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10432 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10433 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10434 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10435
10436 PIPE_CONF_CHECK_I(pixel_multiplier);
10437 PIPE_CONF_CHECK_I(has_hdmi_sink);
10438 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10439 IS_VALLEYVIEW(dev))
10440 PIPE_CONF_CHECK_I(limited_color_range);
10441
10442 PIPE_CONF_CHECK_I(has_audio);
10443
10444 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10445 DRM_MODE_FLAG_INTERLACE);
10446
10447 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10448 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10449 DRM_MODE_FLAG_PHSYNC);
10450 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10451 DRM_MODE_FLAG_NHSYNC);
10452 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10453 DRM_MODE_FLAG_PVSYNC);
10454 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10455 DRM_MODE_FLAG_NVSYNC);
10456 }
10457
10458 PIPE_CONF_CHECK_I(pipe_src_w);
10459 PIPE_CONF_CHECK_I(pipe_src_h);
10460
10461 /*
10462 * FIXME: BIOS likes to set up a cloned config with lvds+external
10463 * screen. Since we don't yet re-compute the pipe config when moving
10464 * just the lvds port away to another pipe the sw tracking won't match.
10465 *
10466 * Proper atomic modesets with recomputed global state will fix this.
10467 * Until then just don't check gmch state for inherited modes.
10468 */
10469 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10470 PIPE_CONF_CHECK_I(gmch_pfit.control);
10471 /* pfit ratios are autocomputed by the hw on gen4+ */
10472 if (INTEL_INFO(dev)->gen < 4)
10473 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10474 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10475 }
10476
10477 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10478 if (current_config->pch_pfit.enabled) {
10479 PIPE_CONF_CHECK_I(pch_pfit.pos);
10480 PIPE_CONF_CHECK_I(pch_pfit.size);
10481 }
10482
10483 /* BDW+ don't expose a synchronous way to read the state */
10484 if (IS_HASWELL(dev))
10485 PIPE_CONF_CHECK_I(ips_enabled);
10486
10487 PIPE_CONF_CHECK_I(double_wide);
10488
10489 PIPE_CONF_CHECK_X(ddi_pll_sel);
10490
10491 PIPE_CONF_CHECK_I(shared_dpll);
10492 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10493 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10494 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10495 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10496 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
10497
10498 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10499 PIPE_CONF_CHECK_I(pipe_bpp);
10500
10501 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10502 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10503
10504 #undef PIPE_CONF_CHECK_X
10505 #undef PIPE_CONF_CHECK_I
10506 #undef PIPE_CONF_CHECK_I_ALT
10507 #undef PIPE_CONF_CHECK_FLAGS
10508 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10509 #undef PIPE_CONF_QUIRK
10510
10511 return true;
10512 }
10513
10514 static void check_wm_state(struct drm_device *dev)
10515 {
10516 struct drm_i915_private *dev_priv = dev->dev_private;
10517 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10518 struct intel_crtc *intel_crtc;
10519 int plane;
10520
10521 if (INTEL_INFO(dev)->gen < 9)
10522 return;
10523
10524 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10525 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10526
10527 for_each_intel_crtc(dev, intel_crtc) {
10528 struct skl_ddb_entry *hw_entry, *sw_entry;
10529 const enum pipe pipe = intel_crtc->pipe;
10530
10531 if (!intel_crtc->active)
10532 continue;
10533
10534 /* planes */
10535 for_each_plane(pipe, plane) {
10536 hw_entry = &hw_ddb.plane[pipe][plane];
10537 sw_entry = &sw_ddb->plane[pipe][plane];
10538
10539 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10540 continue;
10541
10542 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10543 "(expected (%u,%u), found (%u,%u))\n",
10544 pipe_name(pipe), plane + 1,
10545 sw_entry->start, sw_entry->end,
10546 hw_entry->start, hw_entry->end);
10547 }
10548
10549 /* cursor */
10550 hw_entry = &hw_ddb.cursor[pipe];
10551 sw_entry = &sw_ddb->cursor[pipe];
10552
10553 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10554 continue;
10555
10556 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10557 "(expected (%u,%u), found (%u,%u))\n",
10558 pipe_name(pipe),
10559 sw_entry->start, sw_entry->end,
10560 hw_entry->start, hw_entry->end);
10561 }
10562 }
10563
10564 static void
10565 check_connector_state(struct drm_device *dev)
10566 {
10567 struct intel_connector *connector;
10568
10569 list_for_each_entry(connector, &dev->mode_config.connector_list,
10570 base.head) {
10571 /* This also checks the encoder/connector hw state with the
10572 * ->get_hw_state callbacks. */
10573 intel_connector_check_state(connector);
10574
10575 WARN(&connector->new_encoder->base != connector->base.encoder,
10576 "connector's staged encoder doesn't match current encoder\n");
10577 }
10578 }
10579
10580 static void
10581 check_encoder_state(struct drm_device *dev)
10582 {
10583 struct intel_encoder *encoder;
10584 struct intel_connector *connector;
10585
10586 for_each_intel_encoder(dev, encoder) {
10587 bool enabled = false;
10588 bool active = false;
10589 enum pipe pipe, tracked_pipe;
10590
10591 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10592 encoder->base.base.id,
10593 encoder->base.name);
10594
10595 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10596 "encoder's stage crtc doesn't match current crtc\n");
10597 WARN(encoder->connectors_active && !encoder->base.crtc,
10598 "encoder's active_connectors set, but no crtc\n");
10599
10600 list_for_each_entry(connector, &dev->mode_config.connector_list,
10601 base.head) {
10602 if (connector->base.encoder != &encoder->base)
10603 continue;
10604 enabled = true;
10605 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10606 active = true;
10607 }
10608 /*
10609 * for MST connectors if we unplug the connector is gone
10610 * away but the encoder is still connected to a crtc
10611 * until a modeset happens in response to the hotplug.
10612 */
10613 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
10614 continue;
10615
10616 WARN(!!encoder->base.crtc != enabled,
10617 "encoder's enabled state mismatch "
10618 "(expected %i, found %i)\n",
10619 !!encoder->base.crtc, enabled);
10620 WARN(active && !encoder->base.crtc,
10621 "active encoder with no crtc\n");
10622
10623 WARN(encoder->connectors_active != active,
10624 "encoder's computed active state doesn't match tracked active state "
10625 "(expected %i, found %i)\n", active, encoder->connectors_active);
10626
10627 active = encoder->get_hw_state(encoder, &pipe);
10628 WARN(active != encoder->connectors_active,
10629 "encoder's hw state doesn't match sw tracking "
10630 "(expected %i, found %i)\n",
10631 encoder->connectors_active, active);
10632
10633 if (!encoder->base.crtc)
10634 continue;
10635
10636 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10637 WARN(active && pipe != tracked_pipe,
10638 "active encoder's pipe doesn't match"
10639 "(expected %i, found %i)\n",
10640 tracked_pipe, pipe);
10641
10642 }
10643 }
10644
10645 static void
10646 check_crtc_state(struct drm_device *dev)
10647 {
10648 struct drm_i915_private *dev_priv = dev->dev_private;
10649 struct intel_crtc *crtc;
10650 struct intel_encoder *encoder;
10651 struct intel_crtc_config pipe_config;
10652
10653 for_each_intel_crtc(dev, crtc) {
10654 bool enabled = false;
10655 bool active = false;
10656
10657 memset(&pipe_config, 0, sizeof(pipe_config));
10658
10659 DRM_DEBUG_KMS("[CRTC:%d]\n",
10660 crtc->base.base.id);
10661
10662 WARN(crtc->active && !crtc->base.enabled,
10663 "active crtc, but not enabled in sw tracking\n");
10664
10665 for_each_intel_encoder(dev, encoder) {
10666 if (encoder->base.crtc != &crtc->base)
10667 continue;
10668 enabled = true;
10669 if (encoder->connectors_active)
10670 active = true;
10671 }
10672
10673 WARN(active != crtc->active,
10674 "crtc's computed active state doesn't match tracked active state "
10675 "(expected %i, found %i)\n", active, crtc->active);
10676 WARN(enabled != crtc->base.enabled,
10677 "crtc's computed enabled state doesn't match tracked enabled state "
10678 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10679
10680 active = dev_priv->display.get_pipe_config(crtc,
10681 &pipe_config);
10682
10683 /* hw state is inconsistent with the pipe quirk */
10684 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
10685 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
10686 active = crtc->active;
10687
10688 for_each_intel_encoder(dev, encoder) {
10689 enum pipe pipe;
10690 if (encoder->base.crtc != &crtc->base)
10691 continue;
10692 if (encoder->get_hw_state(encoder, &pipe))
10693 encoder->get_config(encoder, &pipe_config);
10694 }
10695
10696 WARN(crtc->active != active,
10697 "crtc active state doesn't match with hw state "
10698 "(expected %i, found %i)\n", crtc->active, active);
10699
10700 if (active &&
10701 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10702 WARN(1, "pipe state doesn't match!\n");
10703 intel_dump_pipe_config(crtc, &pipe_config,
10704 "[hw state]");
10705 intel_dump_pipe_config(crtc, &crtc->config,
10706 "[sw state]");
10707 }
10708 }
10709 }
10710
10711 static void
10712 check_shared_dpll_state(struct drm_device *dev)
10713 {
10714 struct drm_i915_private *dev_priv = dev->dev_private;
10715 struct intel_crtc *crtc;
10716 struct intel_dpll_hw_state dpll_hw_state;
10717 int i;
10718
10719 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10720 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10721 int enabled_crtcs = 0, active_crtcs = 0;
10722 bool active;
10723
10724 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10725
10726 DRM_DEBUG_KMS("%s\n", pll->name);
10727
10728 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10729
10730 WARN(pll->active > hweight32(pll->config.crtc_mask),
10731 "more active pll users than references: %i vs %i\n",
10732 pll->active, hweight32(pll->config.crtc_mask));
10733 WARN(pll->active && !pll->on,
10734 "pll in active use but not on in sw tracking\n");
10735 WARN(pll->on && !pll->active,
10736 "pll in on but not on in use in sw tracking\n");
10737 WARN(pll->on != active,
10738 "pll on state mismatch (expected %i, found %i)\n",
10739 pll->on, active);
10740
10741 for_each_intel_crtc(dev, crtc) {
10742 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10743 enabled_crtcs++;
10744 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10745 active_crtcs++;
10746 }
10747 WARN(pll->active != active_crtcs,
10748 "pll active crtcs mismatch (expected %i, found %i)\n",
10749 pll->active, active_crtcs);
10750 WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
10751 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10752 hweight32(pll->config.crtc_mask), enabled_crtcs);
10753
10754 WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
10755 sizeof(dpll_hw_state)),
10756 "pll hw state mismatch\n");
10757 }
10758 }
10759
10760 void
10761 intel_modeset_check_state(struct drm_device *dev)
10762 {
10763 check_wm_state(dev);
10764 check_connector_state(dev);
10765 check_encoder_state(dev);
10766 check_crtc_state(dev);
10767 check_shared_dpll_state(dev);
10768 }
10769
10770 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10771 int dotclock)
10772 {
10773 /*
10774 * FDI already provided one idea for the dotclock.
10775 * Yell if the encoder disagrees.
10776 */
10777 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10778 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10779 pipe_config->adjusted_mode.crtc_clock, dotclock);
10780 }
10781
10782 static void update_scanline_offset(struct intel_crtc *crtc)
10783 {
10784 struct drm_device *dev = crtc->base.dev;
10785
10786 /*
10787 * The scanline counter increments at the leading edge of hsync.
10788 *
10789 * On most platforms it starts counting from vtotal-1 on the
10790 * first active line. That means the scanline counter value is
10791 * always one less than what we would expect. Ie. just after
10792 * start of vblank, which also occurs at start of hsync (on the
10793 * last active line), the scanline counter will read vblank_start-1.
10794 *
10795 * On gen2 the scanline counter starts counting from 1 instead
10796 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10797 * to keep the value positive), instead of adding one.
10798 *
10799 * On HSW+ the behaviour of the scanline counter depends on the output
10800 * type. For DP ports it behaves like most other platforms, but on HDMI
10801 * there's an extra 1 line difference. So we need to add two instead of
10802 * one to the value.
10803 */
10804 if (IS_GEN2(dev)) {
10805 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10806 int vtotal;
10807
10808 vtotal = mode->crtc_vtotal;
10809 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10810 vtotal /= 2;
10811
10812 crtc->scanline_offset = vtotal - 1;
10813 } else if (HAS_DDI(dev) &&
10814 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
10815 crtc->scanline_offset = 2;
10816 } else
10817 crtc->scanline_offset = 1;
10818 }
10819
10820 static int __intel_set_mode(struct drm_crtc *crtc,
10821 struct drm_display_mode *mode,
10822 int x, int y, struct drm_framebuffer *fb)
10823 {
10824 struct drm_device *dev = crtc->dev;
10825 struct drm_i915_private *dev_priv = dev->dev_private;
10826 struct drm_display_mode *saved_mode;
10827 struct intel_crtc_config *pipe_config = NULL;
10828 struct intel_crtc *intel_crtc;
10829 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10830 int ret = 0;
10831
10832 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10833 if (!saved_mode)
10834 return -ENOMEM;
10835
10836 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10837 &prepare_pipes, &disable_pipes);
10838
10839 *saved_mode = crtc->mode;
10840
10841 /* Hack: Because we don't (yet) support global modeset on multiple
10842 * crtcs, we don't keep track of the new mode for more than one crtc.
10843 * Hence simply check whether any bit is set in modeset_pipes in all the
10844 * pieces of code that are not yet converted to deal with mutliple crtcs
10845 * changing their mode at the same time. */
10846 if (modeset_pipes) {
10847 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10848 if (IS_ERR(pipe_config)) {
10849 ret = PTR_ERR(pipe_config);
10850 pipe_config = NULL;
10851
10852 goto out;
10853 }
10854 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10855 "[modeset]");
10856 to_intel_crtc(crtc)->new_config = pipe_config;
10857 }
10858
10859 /*
10860 * See if the config requires any additional preparation, e.g.
10861 * to adjust global state with pipes off. We need to do this
10862 * here so we can get the modeset_pipe updated config for the new
10863 * mode set on this crtc. For other crtcs we need to use the
10864 * adjusted_mode bits in the crtc directly.
10865 */
10866 if (IS_VALLEYVIEW(dev)) {
10867 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10868
10869 /* may have added more to prepare_pipes than we should */
10870 prepare_pipes &= ~disable_pipes;
10871 }
10872
10873 if (dev_priv->display.crtc_compute_clock) {
10874 unsigned clear_pipes = modeset_pipes | disable_pipes;
10875
10876 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
10877 if (ret)
10878 goto done;
10879
10880 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10881 ret = dev_priv->display.crtc_compute_clock(intel_crtc);
10882 if (ret) {
10883 intel_shared_dpll_abort_config(dev_priv);
10884 goto done;
10885 }
10886 }
10887 }
10888
10889 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10890 intel_crtc_disable(&intel_crtc->base);
10891
10892 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10893 if (intel_crtc->base.enabled)
10894 dev_priv->display.crtc_disable(&intel_crtc->base);
10895 }
10896
10897 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10898 * to set it here already despite that we pass it down the callchain.
10899 */
10900 if (modeset_pipes) {
10901 crtc->mode = *mode;
10902 /* mode_set/enable/disable functions rely on a correct pipe
10903 * config. */
10904 to_intel_crtc(crtc)->config = *pipe_config;
10905 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10906
10907 /*
10908 * Calculate and store various constants which
10909 * are later needed by vblank and swap-completion
10910 * timestamping. They are derived from true hwmode.
10911 */
10912 drm_calc_timestamping_constants(crtc,
10913 &pipe_config->adjusted_mode);
10914 }
10915
10916 /* Only after disabling all output pipelines that will be changed can we
10917 * update the the output configuration. */
10918 intel_modeset_update_state(dev, prepare_pipes);
10919
10920 if (dev_priv->display.modeset_global_resources)
10921 dev_priv->display.modeset_global_resources(dev);
10922
10923 /* Set up the DPLL and any encoders state that needs to adjust or depend
10924 * on the DPLL.
10925 */
10926 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10927 struct drm_framebuffer *old_fb = crtc->primary->fb;
10928 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb);
10929 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
10930
10931 mutex_lock(&dev->struct_mutex);
10932 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb, NULL);
10933 if (ret != 0) {
10934 DRM_ERROR("pin & fence failed\n");
10935 mutex_unlock(&dev->struct_mutex);
10936 goto done;
10937 }
10938 if (old_fb)
10939 intel_unpin_fb_obj(old_obj);
10940 i915_gem_track_fb(old_obj, obj,
10941 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
10942 mutex_unlock(&dev->struct_mutex);
10943
10944 crtc->primary->fb = fb;
10945 crtc->x = x;
10946 crtc->y = y;
10947 }
10948
10949 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10950 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10951 update_scanline_offset(intel_crtc);
10952
10953 dev_priv->display.crtc_enable(&intel_crtc->base);
10954 }
10955
10956 /* FIXME: add subpixel order */
10957 done:
10958 if (ret && crtc->enabled)
10959 crtc->mode = *saved_mode;
10960
10961 out:
10962 kfree(pipe_config);
10963 kfree(saved_mode);
10964 return ret;
10965 }
10966
10967 static int intel_set_mode(struct drm_crtc *crtc,
10968 struct drm_display_mode *mode,
10969 int x, int y, struct drm_framebuffer *fb)
10970 {
10971 int ret;
10972
10973 ret = __intel_set_mode(crtc, mode, x, y, fb);
10974
10975 if (ret == 0)
10976 intel_modeset_check_state(crtc->dev);
10977
10978 return ret;
10979 }
10980
10981 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10982 {
10983 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10984 }
10985
10986 #undef for_each_intel_crtc_masked
10987
10988 static void intel_set_config_free(struct intel_set_config *config)
10989 {
10990 if (!config)
10991 return;
10992
10993 kfree(config->save_connector_encoders);
10994 kfree(config->save_encoder_crtcs);
10995 kfree(config->save_crtc_enabled);
10996 kfree(config);
10997 }
10998
10999 static int intel_set_config_save_state(struct drm_device *dev,
11000 struct intel_set_config *config)
11001 {
11002 struct drm_crtc *crtc;
11003 struct drm_encoder *encoder;
11004 struct drm_connector *connector;
11005 int count;
11006
11007 config->save_crtc_enabled =
11008 kcalloc(dev->mode_config.num_crtc,
11009 sizeof(bool), GFP_KERNEL);
11010 if (!config->save_crtc_enabled)
11011 return -ENOMEM;
11012
11013 config->save_encoder_crtcs =
11014 kcalloc(dev->mode_config.num_encoder,
11015 sizeof(struct drm_crtc *), GFP_KERNEL);
11016 if (!config->save_encoder_crtcs)
11017 return -ENOMEM;
11018
11019 config->save_connector_encoders =
11020 kcalloc(dev->mode_config.num_connector,
11021 sizeof(struct drm_encoder *), GFP_KERNEL);
11022 if (!config->save_connector_encoders)
11023 return -ENOMEM;
11024
11025 /* Copy data. Note that driver private data is not affected.
11026 * Should anything bad happen only the expected state is
11027 * restored, not the drivers personal bookkeeping.
11028 */
11029 count = 0;
11030 for_each_crtc(dev, crtc) {
11031 config->save_crtc_enabled[count++] = crtc->enabled;
11032 }
11033
11034 count = 0;
11035 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
11036 config->save_encoder_crtcs[count++] = encoder->crtc;
11037 }
11038
11039 count = 0;
11040 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11041 config->save_connector_encoders[count++] = connector->encoder;
11042 }
11043
11044 return 0;
11045 }
11046
11047 static void intel_set_config_restore_state(struct drm_device *dev,
11048 struct intel_set_config *config)
11049 {
11050 struct intel_crtc *crtc;
11051 struct intel_encoder *encoder;
11052 struct intel_connector *connector;
11053 int count;
11054
11055 count = 0;
11056 for_each_intel_crtc(dev, crtc) {
11057 crtc->new_enabled = config->save_crtc_enabled[count++];
11058
11059 if (crtc->new_enabled)
11060 crtc->new_config = &crtc->config;
11061 else
11062 crtc->new_config = NULL;
11063 }
11064
11065 count = 0;
11066 for_each_intel_encoder(dev, encoder) {
11067 encoder->new_crtc =
11068 to_intel_crtc(config->save_encoder_crtcs[count++]);
11069 }
11070
11071 count = 0;
11072 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11073 connector->new_encoder =
11074 to_intel_encoder(config->save_connector_encoders[count++]);
11075 }
11076 }
11077
11078 static bool
11079 is_crtc_connector_off(struct drm_mode_set *set)
11080 {
11081 int i;
11082
11083 if (set->num_connectors == 0)
11084 return false;
11085
11086 if (WARN_ON(set->connectors == NULL))
11087 return false;
11088
11089 for (i = 0; i < set->num_connectors; i++)
11090 if (set->connectors[i]->encoder &&
11091 set->connectors[i]->encoder->crtc == set->crtc &&
11092 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
11093 return true;
11094
11095 return false;
11096 }
11097
11098 static void
11099 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11100 struct intel_set_config *config)
11101 {
11102
11103 /* We should be able to check here if the fb has the same properties
11104 * and then just flip_or_move it */
11105 if (is_crtc_connector_off(set)) {
11106 config->mode_changed = true;
11107 } else if (set->crtc->primary->fb != set->fb) {
11108 /*
11109 * If we have no fb, we can only flip as long as the crtc is
11110 * active, otherwise we need a full mode set. The crtc may
11111 * be active if we've only disabled the primary plane, or
11112 * in fastboot situations.
11113 */
11114 if (set->crtc->primary->fb == NULL) {
11115 struct intel_crtc *intel_crtc =
11116 to_intel_crtc(set->crtc);
11117
11118 if (intel_crtc->active) {
11119 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11120 config->fb_changed = true;
11121 } else {
11122 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11123 config->mode_changed = true;
11124 }
11125 } else if (set->fb == NULL) {
11126 config->mode_changed = true;
11127 } else if (set->fb->pixel_format !=
11128 set->crtc->primary->fb->pixel_format) {
11129 config->mode_changed = true;
11130 } else {
11131 config->fb_changed = true;
11132 }
11133 }
11134
11135 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
11136 config->fb_changed = true;
11137
11138 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11139 DRM_DEBUG_KMS("modes are different, full mode set\n");
11140 drm_mode_debug_printmodeline(&set->crtc->mode);
11141 drm_mode_debug_printmodeline(set->mode);
11142 config->mode_changed = true;
11143 }
11144
11145 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11146 set->crtc->base.id, config->mode_changed, config->fb_changed);
11147 }
11148
11149 static int
11150 intel_modeset_stage_output_state(struct drm_device *dev,
11151 struct drm_mode_set *set,
11152 struct intel_set_config *config)
11153 {
11154 struct intel_connector *connector;
11155 struct intel_encoder *encoder;
11156 struct intel_crtc *crtc;
11157 int ro;
11158
11159 /* The upper layers ensure that we either disable a crtc or have a list
11160 * of connectors. For paranoia, double-check this. */
11161 WARN_ON(!set->fb && (set->num_connectors != 0));
11162 WARN_ON(set->fb && (set->num_connectors == 0));
11163
11164 list_for_each_entry(connector, &dev->mode_config.connector_list,
11165 base.head) {
11166 /* Otherwise traverse passed in connector list and get encoders
11167 * for them. */
11168 for (ro = 0; ro < set->num_connectors; ro++) {
11169 if (set->connectors[ro] == &connector->base) {
11170 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
11171 break;
11172 }
11173 }
11174
11175 /* If we disable the crtc, disable all its connectors. Also, if
11176 * the connector is on the changing crtc but not on the new
11177 * connector list, disable it. */
11178 if ((!set->fb || ro == set->num_connectors) &&
11179 connector->base.encoder &&
11180 connector->base.encoder->crtc == set->crtc) {
11181 connector->new_encoder = NULL;
11182
11183 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11184 connector->base.base.id,
11185 connector->base.name);
11186 }
11187
11188
11189 if (&connector->new_encoder->base != connector->base.encoder) {
11190 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
11191 config->mode_changed = true;
11192 }
11193 }
11194 /* connector->new_encoder is now updated for all connectors. */
11195
11196 /* Update crtc of enabled connectors. */
11197 list_for_each_entry(connector, &dev->mode_config.connector_list,
11198 base.head) {
11199 struct drm_crtc *new_crtc;
11200
11201 if (!connector->new_encoder)
11202 continue;
11203
11204 new_crtc = connector->new_encoder->base.crtc;
11205
11206 for (ro = 0; ro < set->num_connectors; ro++) {
11207 if (set->connectors[ro] == &connector->base)
11208 new_crtc = set->crtc;
11209 }
11210
11211 /* Make sure the new CRTC will work with the encoder */
11212 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11213 new_crtc)) {
11214 return -EINVAL;
11215 }
11216 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
11217
11218 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11219 connector->base.base.id,
11220 connector->base.name,
11221 new_crtc->base.id);
11222 }
11223
11224 /* Check for any encoders that needs to be disabled. */
11225 for_each_intel_encoder(dev, encoder) {
11226 int num_connectors = 0;
11227 list_for_each_entry(connector,
11228 &dev->mode_config.connector_list,
11229 base.head) {
11230 if (connector->new_encoder == encoder) {
11231 WARN_ON(!connector->new_encoder->new_crtc);
11232 num_connectors++;
11233 }
11234 }
11235
11236 if (num_connectors == 0)
11237 encoder->new_crtc = NULL;
11238 else if (num_connectors > 1)
11239 return -EINVAL;
11240
11241 /* Only now check for crtc changes so we don't miss encoders
11242 * that will be disabled. */
11243 if (&encoder->new_crtc->base != encoder->base.crtc) {
11244 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
11245 config->mode_changed = true;
11246 }
11247 }
11248 /* Now we've also updated encoder->new_crtc for all encoders. */
11249 list_for_each_entry(connector, &dev->mode_config.connector_list,
11250 base.head) {
11251 if (connector->new_encoder)
11252 if (connector->new_encoder != connector->encoder)
11253 connector->encoder = connector->new_encoder;
11254 }
11255 for_each_intel_crtc(dev, crtc) {
11256 crtc->new_enabled = false;
11257
11258 for_each_intel_encoder(dev, encoder) {
11259 if (encoder->new_crtc == crtc) {
11260 crtc->new_enabled = true;
11261 break;
11262 }
11263 }
11264
11265 if (crtc->new_enabled != crtc->base.enabled) {
11266 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
11267 crtc->new_enabled ? "en" : "dis");
11268 config->mode_changed = true;
11269 }
11270
11271 if (crtc->new_enabled)
11272 crtc->new_config = &crtc->config;
11273 else
11274 crtc->new_config = NULL;
11275 }
11276
11277 return 0;
11278 }
11279
11280 static void disable_crtc_nofb(struct intel_crtc *crtc)
11281 {
11282 struct drm_device *dev = crtc->base.dev;
11283 struct intel_encoder *encoder;
11284 struct intel_connector *connector;
11285
11286 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11287 pipe_name(crtc->pipe));
11288
11289 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
11290 if (connector->new_encoder &&
11291 connector->new_encoder->new_crtc == crtc)
11292 connector->new_encoder = NULL;
11293 }
11294
11295 for_each_intel_encoder(dev, encoder) {
11296 if (encoder->new_crtc == crtc)
11297 encoder->new_crtc = NULL;
11298 }
11299
11300 crtc->new_enabled = false;
11301 crtc->new_config = NULL;
11302 }
11303
11304 static int intel_crtc_set_config(struct drm_mode_set *set)
11305 {
11306 struct drm_device *dev;
11307 struct drm_mode_set save_set;
11308 struct intel_set_config *config;
11309 int ret;
11310
11311 BUG_ON(!set);
11312 BUG_ON(!set->crtc);
11313 BUG_ON(!set->crtc->helper_private);
11314
11315 /* Enforce sane interface api - has been abused by the fb helper. */
11316 BUG_ON(!set->mode && set->fb);
11317 BUG_ON(set->fb && set->num_connectors == 0);
11318
11319 if (set->fb) {
11320 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11321 set->crtc->base.id, set->fb->base.id,
11322 (int)set->num_connectors, set->x, set->y);
11323 } else {
11324 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
11325 }
11326
11327 dev = set->crtc->dev;
11328
11329 ret = -ENOMEM;
11330 config = kzalloc(sizeof(*config), GFP_KERNEL);
11331 if (!config)
11332 goto out_config;
11333
11334 ret = intel_set_config_save_state(dev, config);
11335 if (ret)
11336 goto out_config;
11337
11338 save_set.crtc = set->crtc;
11339 save_set.mode = &set->crtc->mode;
11340 save_set.x = set->crtc->x;
11341 save_set.y = set->crtc->y;
11342 save_set.fb = set->crtc->primary->fb;
11343
11344 /* Compute whether we need a full modeset, only an fb base update or no
11345 * change at all. In the future we might also check whether only the
11346 * mode changed, e.g. for LVDS where we only change the panel fitter in
11347 * such cases. */
11348 intel_set_config_compute_mode_changes(set, config);
11349
11350 ret = intel_modeset_stage_output_state(dev, set, config);
11351 if (ret)
11352 goto fail;
11353
11354 if (config->mode_changed) {
11355 ret = intel_set_mode(set->crtc, set->mode,
11356 set->x, set->y, set->fb);
11357 } else if (config->fb_changed) {
11358 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
11359
11360 intel_crtc_wait_for_pending_flips(set->crtc);
11361
11362 ret = intel_pipe_set_base(set->crtc,
11363 set->x, set->y, set->fb);
11364
11365 /*
11366 * We need to make sure the primary plane is re-enabled if it
11367 * has previously been turned off.
11368 */
11369 if (!intel_crtc->primary_enabled && ret == 0) {
11370 WARN_ON(!intel_crtc->active);
11371 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
11372 }
11373
11374 /*
11375 * In the fastboot case this may be our only check of the
11376 * state after boot. It would be better to only do it on
11377 * the first update, but we don't have a nice way of doing that
11378 * (and really, set_config isn't used much for high freq page
11379 * flipping, so increasing its cost here shouldn't be a big
11380 * deal).
11381 */
11382 if (i915.fastboot && ret == 0)
11383 intel_modeset_check_state(set->crtc->dev);
11384 }
11385
11386 if (ret) {
11387 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11388 set->crtc->base.id, ret);
11389 fail:
11390 intel_set_config_restore_state(dev, config);
11391
11392 /*
11393 * HACK: if the pipe was on, but we didn't have a framebuffer,
11394 * force the pipe off to avoid oopsing in the modeset code
11395 * due to fb==NULL. This should only happen during boot since
11396 * we don't yet reconstruct the FB from the hardware state.
11397 */
11398 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11399 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11400
11401 /* Try to restore the config */
11402 if (config->mode_changed &&
11403 intel_set_mode(save_set.crtc, save_set.mode,
11404 save_set.x, save_set.y, save_set.fb))
11405 DRM_ERROR("failed to restore config after modeset failure\n");
11406 }
11407
11408 out_config:
11409 intel_set_config_free(config);
11410 return ret;
11411 }
11412
11413 static const struct drm_crtc_funcs intel_crtc_funcs = {
11414 .gamma_set = intel_crtc_gamma_set,
11415 .set_config = intel_crtc_set_config,
11416 .destroy = intel_crtc_destroy,
11417 .page_flip = intel_crtc_page_flip,
11418 };
11419
11420 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11421 struct intel_shared_dpll *pll,
11422 struct intel_dpll_hw_state *hw_state)
11423 {
11424 uint32_t val;
11425
11426 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
11427 return false;
11428
11429 val = I915_READ(PCH_DPLL(pll->id));
11430 hw_state->dpll = val;
11431 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11432 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
11433
11434 return val & DPLL_VCO_ENABLE;
11435 }
11436
11437 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11438 struct intel_shared_dpll *pll)
11439 {
11440 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11441 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
11442 }
11443
11444 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11445 struct intel_shared_dpll *pll)
11446 {
11447 /* PCH refclock must be enabled first */
11448 ibx_assert_pch_refclk_enabled(dev_priv);
11449
11450 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11451
11452 /* Wait for the clocks to stabilize. */
11453 POSTING_READ(PCH_DPLL(pll->id));
11454 udelay(150);
11455
11456 /* The pixel multiplier can only be updated once the
11457 * DPLL is enabled and the clocks are stable.
11458 *
11459 * So write it again.
11460 */
11461 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
11462 POSTING_READ(PCH_DPLL(pll->id));
11463 udelay(200);
11464 }
11465
11466 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11467 struct intel_shared_dpll *pll)
11468 {
11469 struct drm_device *dev = dev_priv->dev;
11470 struct intel_crtc *crtc;
11471
11472 /* Make sure no transcoder isn't still depending on us. */
11473 for_each_intel_crtc(dev, crtc) {
11474 if (intel_crtc_to_shared_dpll(crtc) == pll)
11475 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
11476 }
11477
11478 I915_WRITE(PCH_DPLL(pll->id), 0);
11479 POSTING_READ(PCH_DPLL(pll->id));
11480 udelay(200);
11481 }
11482
11483 static char *ibx_pch_dpll_names[] = {
11484 "PCH DPLL A",
11485 "PCH DPLL B",
11486 };
11487
11488 static void ibx_pch_dpll_init(struct drm_device *dev)
11489 {
11490 struct drm_i915_private *dev_priv = dev->dev_private;
11491 int i;
11492
11493 dev_priv->num_shared_dpll = 2;
11494
11495 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11496 dev_priv->shared_dplls[i].id = i;
11497 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11498 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11499 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11500 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11501 dev_priv->shared_dplls[i].get_hw_state =
11502 ibx_pch_dpll_get_hw_state;
11503 }
11504 }
11505
11506 static void intel_shared_dpll_init(struct drm_device *dev)
11507 {
11508 struct drm_i915_private *dev_priv = dev->dev_private;
11509
11510 if (HAS_DDI(dev))
11511 intel_ddi_pll_init(dev);
11512 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11513 ibx_pch_dpll_init(dev);
11514 else
11515 dev_priv->num_shared_dpll = 0;
11516
11517 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11518 }
11519
11520 static int
11521 intel_primary_plane_disable(struct drm_plane *plane)
11522 {
11523 struct drm_device *dev = plane->dev;
11524 struct intel_crtc *intel_crtc;
11525
11526 if (!plane->fb)
11527 return 0;
11528
11529 BUG_ON(!plane->crtc);
11530
11531 intel_crtc = to_intel_crtc(plane->crtc);
11532
11533 /*
11534 * Even though we checked plane->fb above, it's still possible that
11535 * the primary plane has been implicitly disabled because the crtc
11536 * coordinates given weren't visible, or because we detected
11537 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11538 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11539 * In either case, we need to unpin the FB and let the fb pointer get
11540 * updated, but otherwise we don't need to touch the hardware.
11541 */
11542 if (!intel_crtc->primary_enabled)
11543 goto disable_unpin;
11544
11545 intel_crtc_wait_for_pending_flips(plane->crtc);
11546 intel_disable_primary_hw_plane(plane, plane->crtc);
11547
11548 disable_unpin:
11549 mutex_lock(&dev->struct_mutex);
11550 i915_gem_track_fb(intel_fb_obj(plane->fb), NULL,
11551 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe));
11552 intel_unpin_fb_obj(intel_fb_obj(plane->fb));
11553 mutex_unlock(&dev->struct_mutex);
11554 plane->fb = NULL;
11555
11556 return 0;
11557 }
11558
11559 static int
11560 intel_check_primary_plane(struct drm_plane *plane,
11561 struct intel_plane_state *state)
11562 {
11563 struct drm_crtc *crtc = state->crtc;
11564 struct drm_framebuffer *fb = state->fb;
11565 struct drm_rect *dest = &state->dst;
11566 struct drm_rect *src = &state->src;
11567 const struct drm_rect *clip = &state->clip;
11568
11569 return drm_plane_helper_check_update(plane, crtc, fb,
11570 src, dest, clip,
11571 DRM_PLANE_HELPER_NO_SCALING,
11572 DRM_PLANE_HELPER_NO_SCALING,
11573 false, true, &state->visible);
11574 }
11575
11576 static int
11577 intel_prepare_primary_plane(struct drm_plane *plane,
11578 struct intel_plane_state *state)
11579 {
11580 struct drm_crtc *crtc = state->crtc;
11581 struct drm_framebuffer *fb = state->fb;
11582 struct drm_device *dev = crtc->dev;
11583 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11584 enum pipe pipe = intel_crtc->pipe;
11585 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11586 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11587 int ret;
11588
11589 intel_crtc_wait_for_pending_flips(crtc);
11590
11591 if (intel_crtc_has_pending_flip(crtc)) {
11592 DRM_ERROR("pipe is still busy with an old pageflip\n");
11593 return -EBUSY;
11594 }
11595
11596 if (old_obj != obj) {
11597 mutex_lock(&dev->struct_mutex);
11598 ret = intel_pin_and_fence_fb_obj(plane, fb, NULL);
11599 if (ret == 0)
11600 i915_gem_track_fb(old_obj, obj,
11601 INTEL_FRONTBUFFER_PRIMARY(pipe));
11602 mutex_unlock(&dev->struct_mutex);
11603 if (ret != 0) {
11604 DRM_DEBUG_KMS("pin & fence failed\n");
11605 return ret;
11606 }
11607 }
11608
11609 return 0;
11610 }
11611
11612 static void
11613 intel_commit_primary_plane(struct drm_plane *plane,
11614 struct intel_plane_state *state)
11615 {
11616 struct drm_crtc *crtc = state->crtc;
11617 struct drm_framebuffer *fb = state->fb;
11618 struct drm_device *dev = crtc->dev;
11619 struct drm_i915_private *dev_priv = dev->dev_private;
11620 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11621 enum pipe pipe = intel_crtc->pipe;
11622 struct drm_framebuffer *old_fb = plane->fb;
11623 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11624 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
11625 struct intel_plane *intel_plane = to_intel_plane(plane);
11626 struct drm_rect *src = &state->src;
11627
11628 crtc->primary->fb = fb;
11629 crtc->x = src->x1;
11630 crtc->y = src->y1;
11631
11632 intel_plane->crtc_x = state->orig_dst.x1;
11633 intel_plane->crtc_y = state->orig_dst.y1;
11634 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11635 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11636 intel_plane->src_x = state->orig_src.x1;
11637 intel_plane->src_y = state->orig_src.y1;
11638 intel_plane->src_w = drm_rect_width(&state->orig_src);
11639 intel_plane->src_h = drm_rect_height(&state->orig_src);
11640 intel_plane->obj = obj;
11641
11642 if (intel_crtc->active) {
11643 /*
11644 * FBC does not work on some platforms for rotated
11645 * planes, so disable it when rotation is not 0 and
11646 * update it when rotation is set back to 0.
11647 *
11648 * FIXME: This is redundant with the fbc update done in
11649 * the primary plane enable function except that that
11650 * one is done too late. We eventually need to unify
11651 * this.
11652 */
11653 if (intel_crtc->primary_enabled &&
11654 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11655 dev_priv->fbc.plane == intel_crtc->plane &&
11656 intel_plane->rotation != BIT(DRM_ROTATE_0)) {
11657 intel_disable_fbc(dev);
11658 }
11659
11660 if (state->visible) {
11661 bool was_enabled = intel_crtc->primary_enabled;
11662
11663 /* FIXME: kill this fastboot hack */
11664 intel_update_pipe_size(intel_crtc);
11665
11666 intel_crtc->primary_enabled = true;
11667
11668 dev_priv->display.update_primary_plane(crtc, plane->fb,
11669 crtc->x, crtc->y);
11670
11671 /*
11672 * BDW signals flip done immediately if the plane
11673 * is disabled, even if the plane enable is already
11674 * armed to occur at the next vblank :(
11675 */
11676 if (IS_BROADWELL(dev) && !was_enabled)
11677 intel_wait_for_vblank(dev, intel_crtc->pipe);
11678 } else {
11679 /*
11680 * If clipping results in a non-visible primary plane,
11681 * we'll disable the primary plane. Note that this is
11682 * a bit different than what happens if userspace
11683 * explicitly disables the plane by passing fb=0
11684 * because plane->fb still gets set and pinned.
11685 */
11686 intel_disable_primary_hw_plane(plane, crtc);
11687 }
11688
11689 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
11690
11691 mutex_lock(&dev->struct_mutex);
11692 intel_update_fbc(dev);
11693 mutex_unlock(&dev->struct_mutex);
11694 }
11695
11696 if (old_fb && old_fb != fb) {
11697 if (intel_crtc->active)
11698 intel_wait_for_vblank(dev, intel_crtc->pipe);
11699
11700 mutex_lock(&dev->struct_mutex);
11701 intel_unpin_fb_obj(old_obj);
11702 mutex_unlock(&dev->struct_mutex);
11703 }
11704 }
11705
11706 static int
11707 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11708 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11709 unsigned int crtc_w, unsigned int crtc_h,
11710 uint32_t src_x, uint32_t src_y,
11711 uint32_t src_w, uint32_t src_h)
11712 {
11713 struct intel_plane_state state;
11714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11715 int ret;
11716
11717 state.crtc = crtc;
11718 state.fb = fb;
11719
11720 /* sample coordinates in 16.16 fixed point */
11721 state.src.x1 = src_x;
11722 state.src.x2 = src_x + src_w;
11723 state.src.y1 = src_y;
11724 state.src.y2 = src_y + src_h;
11725
11726 /* integer pixels */
11727 state.dst.x1 = crtc_x;
11728 state.dst.x2 = crtc_x + crtc_w;
11729 state.dst.y1 = crtc_y;
11730 state.dst.y2 = crtc_y + crtc_h;
11731
11732 state.clip.x1 = 0;
11733 state.clip.y1 = 0;
11734 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11735 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11736
11737 state.orig_src = state.src;
11738 state.orig_dst = state.dst;
11739
11740 ret = intel_check_primary_plane(plane, &state);
11741 if (ret)
11742 return ret;
11743
11744 ret = intel_prepare_primary_plane(plane, &state);
11745 if (ret)
11746 return ret;
11747
11748 intel_commit_primary_plane(plane, &state);
11749
11750 return 0;
11751 }
11752
11753 /* Common destruction function for both primary and cursor planes */
11754 static void intel_plane_destroy(struct drm_plane *plane)
11755 {
11756 struct intel_plane *intel_plane = to_intel_plane(plane);
11757 drm_plane_cleanup(plane);
11758 kfree(intel_plane);
11759 }
11760
11761 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11762 .update_plane = intel_primary_plane_setplane,
11763 .disable_plane = intel_primary_plane_disable,
11764 .destroy = intel_plane_destroy,
11765 .set_property = intel_plane_set_property
11766 };
11767
11768 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11769 int pipe)
11770 {
11771 struct intel_plane *primary;
11772 const uint32_t *intel_primary_formats;
11773 int num_formats;
11774
11775 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11776 if (primary == NULL)
11777 return NULL;
11778
11779 primary->can_scale = false;
11780 primary->max_downscale = 1;
11781 primary->pipe = pipe;
11782 primary->plane = pipe;
11783 primary->rotation = BIT(DRM_ROTATE_0);
11784 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11785 primary->plane = !pipe;
11786
11787 if (INTEL_INFO(dev)->gen <= 3) {
11788 intel_primary_formats = intel_primary_formats_gen2;
11789 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11790 } else {
11791 intel_primary_formats = intel_primary_formats_gen4;
11792 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11793 }
11794
11795 drm_universal_plane_init(dev, &primary->base, 0,
11796 &intel_primary_plane_funcs,
11797 intel_primary_formats, num_formats,
11798 DRM_PLANE_TYPE_PRIMARY);
11799
11800 if (INTEL_INFO(dev)->gen >= 4) {
11801 if (!dev->mode_config.rotation_property)
11802 dev->mode_config.rotation_property =
11803 drm_mode_create_rotation_property(dev,
11804 BIT(DRM_ROTATE_0) |
11805 BIT(DRM_ROTATE_180));
11806 if (dev->mode_config.rotation_property)
11807 drm_object_attach_property(&primary->base.base,
11808 dev->mode_config.rotation_property,
11809 primary->rotation);
11810 }
11811
11812 return &primary->base;
11813 }
11814
11815 static int
11816 intel_cursor_plane_disable(struct drm_plane *plane)
11817 {
11818 if (!plane->fb)
11819 return 0;
11820
11821 BUG_ON(!plane->crtc);
11822
11823 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11824 }
11825
11826 static int
11827 intel_check_cursor_plane(struct drm_plane *plane,
11828 struct intel_plane_state *state)
11829 {
11830 struct drm_crtc *crtc = state->crtc;
11831 struct drm_device *dev = crtc->dev;
11832 struct drm_framebuffer *fb = state->fb;
11833 struct drm_rect *dest = &state->dst;
11834 struct drm_rect *src = &state->src;
11835 const struct drm_rect *clip = &state->clip;
11836 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11837 int crtc_w, crtc_h;
11838 unsigned stride;
11839 int ret;
11840
11841 ret = drm_plane_helper_check_update(plane, crtc, fb,
11842 src, dest, clip,
11843 DRM_PLANE_HELPER_NO_SCALING,
11844 DRM_PLANE_HELPER_NO_SCALING,
11845 true, true, &state->visible);
11846 if (ret)
11847 return ret;
11848
11849
11850 /* if we want to turn off the cursor ignore width and height */
11851 if (!obj)
11852 return 0;
11853
11854 /* Check for which cursor types we support */
11855 crtc_w = drm_rect_width(&state->orig_dst);
11856 crtc_h = drm_rect_height(&state->orig_dst);
11857 if (!cursor_size_ok(dev, crtc_w, crtc_h)) {
11858 DRM_DEBUG("Cursor dimension not supported\n");
11859 return -EINVAL;
11860 }
11861
11862 stride = roundup_pow_of_two(crtc_w) * 4;
11863 if (obj->base.size < stride * crtc_h) {
11864 DRM_DEBUG_KMS("buffer is too small\n");
11865 return -ENOMEM;
11866 }
11867
11868 if (fb == crtc->cursor->fb)
11869 return 0;
11870
11871 /* we only need to pin inside GTT if cursor is non-phy */
11872 mutex_lock(&dev->struct_mutex);
11873 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
11874 DRM_DEBUG_KMS("cursor cannot be tiled\n");
11875 ret = -EINVAL;
11876 }
11877 mutex_unlock(&dev->struct_mutex);
11878
11879 return ret;
11880 }
11881
11882 static int
11883 intel_commit_cursor_plane(struct drm_plane *plane,
11884 struct intel_plane_state *state)
11885 {
11886 struct drm_crtc *crtc = state->crtc;
11887 struct drm_framebuffer *fb = state->fb;
11888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11889 struct intel_plane *intel_plane = to_intel_plane(plane);
11890 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11891 struct drm_i915_gem_object *obj = intel_fb->obj;
11892 int crtc_w, crtc_h;
11893
11894 crtc->cursor_x = state->orig_dst.x1;
11895 crtc->cursor_y = state->orig_dst.y1;
11896
11897 intel_plane->crtc_x = state->orig_dst.x1;
11898 intel_plane->crtc_y = state->orig_dst.y1;
11899 intel_plane->crtc_w = drm_rect_width(&state->orig_dst);
11900 intel_plane->crtc_h = drm_rect_height(&state->orig_dst);
11901 intel_plane->src_x = state->orig_src.x1;
11902 intel_plane->src_y = state->orig_src.y1;
11903 intel_plane->src_w = drm_rect_width(&state->orig_src);
11904 intel_plane->src_h = drm_rect_height(&state->orig_src);
11905 intel_plane->obj = obj;
11906
11907 if (fb != crtc->cursor->fb) {
11908 crtc_w = drm_rect_width(&state->orig_dst);
11909 crtc_h = drm_rect_height(&state->orig_dst);
11910 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11911 } else {
11912 intel_crtc_update_cursor(crtc, state->visible);
11913
11914 intel_frontbuffer_flip(crtc->dev,
11915 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe));
11916
11917 return 0;
11918 }
11919 }
11920
11921 static int
11922 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11923 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11924 unsigned int crtc_w, unsigned int crtc_h,
11925 uint32_t src_x, uint32_t src_y,
11926 uint32_t src_w, uint32_t src_h)
11927 {
11928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11929 struct intel_plane_state state;
11930 int ret;
11931
11932 state.crtc = crtc;
11933 state.fb = fb;
11934
11935 /* sample coordinates in 16.16 fixed point */
11936 state.src.x1 = src_x;
11937 state.src.x2 = src_x + src_w;
11938 state.src.y1 = src_y;
11939 state.src.y2 = src_y + src_h;
11940
11941 /* integer pixels */
11942 state.dst.x1 = crtc_x;
11943 state.dst.x2 = crtc_x + crtc_w;
11944 state.dst.y1 = crtc_y;
11945 state.dst.y2 = crtc_y + crtc_h;
11946
11947 state.clip.x1 = 0;
11948 state.clip.y1 = 0;
11949 state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0;
11950 state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0;
11951
11952 state.orig_src = state.src;
11953 state.orig_dst = state.dst;
11954
11955 ret = intel_check_cursor_plane(plane, &state);
11956 if (ret)
11957 return ret;
11958
11959 return intel_commit_cursor_plane(plane, &state);
11960 }
11961
11962 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11963 .update_plane = intel_cursor_plane_update,
11964 .disable_plane = intel_cursor_plane_disable,
11965 .destroy = intel_plane_destroy,
11966 .set_property = intel_plane_set_property,
11967 };
11968
11969 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11970 int pipe)
11971 {
11972 struct intel_plane *cursor;
11973
11974 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11975 if (cursor == NULL)
11976 return NULL;
11977
11978 cursor->can_scale = false;
11979 cursor->max_downscale = 1;
11980 cursor->pipe = pipe;
11981 cursor->plane = pipe;
11982 cursor->rotation = BIT(DRM_ROTATE_0);
11983
11984 drm_universal_plane_init(dev, &cursor->base, 0,
11985 &intel_cursor_plane_funcs,
11986 intel_cursor_formats,
11987 ARRAY_SIZE(intel_cursor_formats),
11988 DRM_PLANE_TYPE_CURSOR);
11989
11990 if (INTEL_INFO(dev)->gen >= 4) {
11991 if (!dev->mode_config.rotation_property)
11992 dev->mode_config.rotation_property =
11993 drm_mode_create_rotation_property(dev,
11994 BIT(DRM_ROTATE_0) |
11995 BIT(DRM_ROTATE_180));
11996 if (dev->mode_config.rotation_property)
11997 drm_object_attach_property(&cursor->base.base,
11998 dev->mode_config.rotation_property,
11999 cursor->rotation);
12000 }
12001
12002 return &cursor->base;
12003 }
12004
12005 static void intel_crtc_init(struct drm_device *dev, int pipe)
12006 {
12007 struct drm_i915_private *dev_priv = dev->dev_private;
12008 struct intel_crtc *intel_crtc;
12009 struct drm_plane *primary = NULL;
12010 struct drm_plane *cursor = NULL;
12011 int i, ret;
12012
12013 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
12014 if (intel_crtc == NULL)
12015 return;
12016
12017 primary = intel_primary_plane_create(dev, pipe);
12018 if (!primary)
12019 goto fail;
12020
12021 cursor = intel_cursor_plane_create(dev, pipe);
12022 if (!cursor)
12023 goto fail;
12024
12025 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
12026 cursor, &intel_crtc_funcs);
12027 if (ret)
12028 goto fail;
12029
12030 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
12031 for (i = 0; i < 256; i++) {
12032 intel_crtc->lut_r[i] = i;
12033 intel_crtc->lut_g[i] = i;
12034 intel_crtc->lut_b[i] = i;
12035 }
12036
12037 /*
12038 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
12039 * is hooked to pipe B. Hence we want plane A feeding pipe B.
12040 */
12041 intel_crtc->pipe = pipe;
12042 intel_crtc->plane = pipe;
12043 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
12044 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
12045 intel_crtc->plane = !pipe;
12046 }
12047
12048 intel_crtc->cursor_base = ~0;
12049 intel_crtc->cursor_cntl = ~0;
12050 intel_crtc->cursor_size = ~0;
12051
12052 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12053 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12054 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12055 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12056
12057 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12058
12059 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
12060
12061 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
12062 return;
12063
12064 fail:
12065 if (primary)
12066 drm_plane_cleanup(primary);
12067 if (cursor)
12068 drm_plane_cleanup(cursor);
12069 kfree(intel_crtc);
12070 }
12071
12072 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12073 {
12074 struct drm_encoder *encoder = connector->base.encoder;
12075 struct drm_device *dev = connector->base.dev;
12076
12077 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
12078
12079 if (!encoder)
12080 return INVALID_PIPE;
12081
12082 return to_intel_crtc(encoder->crtc)->pipe;
12083 }
12084
12085 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
12086 struct drm_file *file)
12087 {
12088 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
12089 struct drm_crtc *drmmode_crtc;
12090 struct intel_crtc *crtc;
12091
12092 if (!drm_core_check_feature(dev, DRIVER_MODESET))
12093 return -ENODEV;
12094
12095 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
12096
12097 if (!drmmode_crtc) {
12098 DRM_ERROR("no such CRTC id\n");
12099 return -ENOENT;
12100 }
12101
12102 crtc = to_intel_crtc(drmmode_crtc);
12103 pipe_from_crtc_id->pipe = crtc->pipe;
12104
12105 return 0;
12106 }
12107
12108 static int intel_encoder_clones(struct intel_encoder *encoder)
12109 {
12110 struct drm_device *dev = encoder->base.dev;
12111 struct intel_encoder *source_encoder;
12112 int index_mask = 0;
12113 int entry = 0;
12114
12115 for_each_intel_encoder(dev, source_encoder) {
12116 if (encoders_cloneable(encoder, source_encoder))
12117 index_mask |= (1 << entry);
12118
12119 entry++;
12120 }
12121
12122 return index_mask;
12123 }
12124
12125 static bool has_edp_a(struct drm_device *dev)
12126 {
12127 struct drm_i915_private *dev_priv = dev->dev_private;
12128
12129 if (!IS_MOBILE(dev))
12130 return false;
12131
12132 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12133 return false;
12134
12135 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
12136 return false;
12137
12138 return true;
12139 }
12140
12141 const char *intel_output_name(int output)
12142 {
12143 static const char *names[] = {
12144 [INTEL_OUTPUT_UNUSED] = "Unused",
12145 [INTEL_OUTPUT_ANALOG] = "Analog",
12146 [INTEL_OUTPUT_DVO] = "DVO",
12147 [INTEL_OUTPUT_SDVO] = "SDVO",
12148 [INTEL_OUTPUT_LVDS] = "LVDS",
12149 [INTEL_OUTPUT_TVOUT] = "TV",
12150 [INTEL_OUTPUT_HDMI] = "HDMI",
12151 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
12152 [INTEL_OUTPUT_EDP] = "eDP",
12153 [INTEL_OUTPUT_DSI] = "DSI",
12154 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
12155 };
12156
12157 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
12158 return "Invalid";
12159
12160 return names[output];
12161 }
12162
12163 static bool intel_crt_present(struct drm_device *dev)
12164 {
12165 struct drm_i915_private *dev_priv = dev->dev_private;
12166
12167 if (INTEL_INFO(dev)->gen >= 9)
12168 return false;
12169
12170 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
12171 return false;
12172
12173 if (IS_CHERRYVIEW(dev))
12174 return false;
12175
12176 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12177 return false;
12178
12179 return true;
12180 }
12181
12182 static void intel_setup_outputs(struct drm_device *dev)
12183 {
12184 struct drm_i915_private *dev_priv = dev->dev_private;
12185 struct intel_encoder *encoder;
12186 bool dpd_is_edp = false;
12187
12188 intel_lvds_init(dev);
12189
12190 if (intel_crt_present(dev))
12191 intel_crt_init(dev);
12192
12193 if (HAS_DDI(dev)) {
12194 int found;
12195
12196 /* Haswell uses DDI functions to detect digital outputs */
12197 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
12198 /* DDI A only supports eDP */
12199 if (found)
12200 intel_ddi_init(dev, PORT_A);
12201
12202 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12203 * register */
12204 found = I915_READ(SFUSE_STRAP);
12205
12206 if (found & SFUSE_STRAP_DDIB_DETECTED)
12207 intel_ddi_init(dev, PORT_B);
12208 if (found & SFUSE_STRAP_DDIC_DETECTED)
12209 intel_ddi_init(dev, PORT_C);
12210 if (found & SFUSE_STRAP_DDID_DETECTED)
12211 intel_ddi_init(dev, PORT_D);
12212 } else if (HAS_PCH_SPLIT(dev)) {
12213 int found;
12214 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
12215
12216 if (has_edp_a(dev))
12217 intel_dp_init(dev, DP_A, PORT_A);
12218
12219 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
12220 /* PCH SDVOB multiplex with HDMIB */
12221 found = intel_sdvo_init(dev, PCH_SDVOB, true);
12222 if (!found)
12223 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
12224 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
12225 intel_dp_init(dev, PCH_DP_B, PORT_B);
12226 }
12227
12228 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
12229 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
12230
12231 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
12232 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
12233
12234 if (I915_READ(PCH_DP_C) & DP_DETECTED)
12235 intel_dp_init(dev, PCH_DP_C, PORT_C);
12236
12237 if (I915_READ(PCH_DP_D) & DP_DETECTED)
12238 intel_dp_init(dev, PCH_DP_D, PORT_D);
12239 } else if (IS_VALLEYVIEW(dev)) {
12240 /*
12241 * The DP_DETECTED bit is the latched state of the DDC
12242 * SDA pin at boot. However since eDP doesn't require DDC
12243 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12244 * eDP ports may have been muxed to an alternate function.
12245 * Thus we can't rely on the DP_DETECTED bit alone to detect
12246 * eDP ports. Consult the VBT as well as DP_DETECTED to
12247 * detect eDP ports.
12248 */
12249 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED)
12250 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12251 PORT_B);
12252 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12253 intel_dp_is_edp(dev, PORT_B))
12254 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
12255
12256 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED)
12257 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12258 PORT_C);
12259 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12260 intel_dp_is_edp(dev, PORT_C))
12261 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
12262
12263 if (IS_CHERRYVIEW(dev)) {
12264 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
12265 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12266 PORT_D);
12267 /* eDP not supported on port D, so don't check VBT */
12268 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12269 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
12270 }
12271
12272 intel_dsi_init(dev);
12273 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
12274 bool found = false;
12275
12276 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12277 DRM_DEBUG_KMS("probing SDVOB\n");
12278 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
12279 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12280 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
12281 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
12282 }
12283
12284 if (!found && SUPPORTS_INTEGRATED_DP(dev))
12285 intel_dp_init(dev, DP_B, PORT_B);
12286 }
12287
12288 /* Before G4X SDVOC doesn't have its own detect register */
12289
12290 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
12291 DRM_DEBUG_KMS("probing SDVOC\n");
12292 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
12293 }
12294
12295 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
12296
12297 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12298 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
12299 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
12300 }
12301 if (SUPPORTS_INTEGRATED_DP(dev))
12302 intel_dp_init(dev, DP_C, PORT_C);
12303 }
12304
12305 if (SUPPORTS_INTEGRATED_DP(dev) &&
12306 (I915_READ(DP_D) & DP_DETECTED))
12307 intel_dp_init(dev, DP_D, PORT_D);
12308 } else if (IS_GEN2(dev))
12309 intel_dvo_init(dev);
12310
12311 if (SUPPORTS_TV(dev))
12312 intel_tv_init(dev);
12313
12314 intel_edp_psr_init(dev);
12315
12316 for_each_intel_encoder(dev, encoder) {
12317 encoder->base.possible_crtcs = encoder->crtc_mask;
12318 encoder->base.possible_clones =
12319 intel_encoder_clones(encoder);
12320 }
12321
12322 intel_init_pch_refclk(dev);
12323
12324 drm_helper_move_panel_connectors_to_head(dev);
12325 }
12326
12327 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12328 {
12329 struct drm_device *dev = fb->dev;
12330 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12331
12332 drm_framebuffer_cleanup(fb);
12333 mutex_lock(&dev->struct_mutex);
12334 WARN_ON(!intel_fb->obj->framebuffer_references--);
12335 drm_gem_object_unreference(&intel_fb->obj->base);
12336 mutex_unlock(&dev->struct_mutex);
12337 kfree(intel_fb);
12338 }
12339
12340 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
12341 struct drm_file *file,
12342 unsigned int *handle)
12343 {
12344 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
12345 struct drm_i915_gem_object *obj = intel_fb->obj;
12346
12347 return drm_gem_handle_create(file, &obj->base, handle);
12348 }
12349
12350 static const struct drm_framebuffer_funcs intel_fb_funcs = {
12351 .destroy = intel_user_framebuffer_destroy,
12352 .create_handle = intel_user_framebuffer_create_handle,
12353 };
12354
12355 static int intel_framebuffer_init(struct drm_device *dev,
12356 struct intel_framebuffer *intel_fb,
12357 struct drm_mode_fb_cmd2 *mode_cmd,
12358 struct drm_i915_gem_object *obj)
12359 {
12360 int aligned_height;
12361 int pitch_limit;
12362 int ret;
12363
12364 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12365
12366 if (obj->tiling_mode == I915_TILING_Y) {
12367 DRM_DEBUG("hardware does not support tiling Y\n");
12368 return -EINVAL;
12369 }
12370
12371 if (mode_cmd->pitches[0] & 63) {
12372 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
12373 mode_cmd->pitches[0]);
12374 return -EINVAL;
12375 }
12376
12377 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
12378 pitch_limit = 32*1024;
12379 } else if (INTEL_INFO(dev)->gen >= 4) {
12380 if (obj->tiling_mode)
12381 pitch_limit = 16*1024;
12382 else
12383 pitch_limit = 32*1024;
12384 } else if (INTEL_INFO(dev)->gen >= 3) {
12385 if (obj->tiling_mode)
12386 pitch_limit = 8*1024;
12387 else
12388 pitch_limit = 16*1024;
12389 } else
12390 /* XXX DSPC is limited to 4k tiled */
12391 pitch_limit = 8*1024;
12392
12393 if (mode_cmd->pitches[0] > pitch_limit) {
12394 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
12395 obj->tiling_mode ? "tiled" : "linear",
12396 mode_cmd->pitches[0], pitch_limit);
12397 return -EINVAL;
12398 }
12399
12400 if (obj->tiling_mode != I915_TILING_NONE &&
12401 mode_cmd->pitches[0] != obj->stride) {
12402 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
12403 mode_cmd->pitches[0], obj->stride);
12404 return -EINVAL;
12405 }
12406
12407 /* Reject formats not supported by any plane early. */
12408 switch (mode_cmd->pixel_format) {
12409 case DRM_FORMAT_C8:
12410 case DRM_FORMAT_RGB565:
12411 case DRM_FORMAT_XRGB8888:
12412 case DRM_FORMAT_ARGB8888:
12413 break;
12414 case DRM_FORMAT_XRGB1555:
12415 case DRM_FORMAT_ARGB1555:
12416 if (INTEL_INFO(dev)->gen > 3) {
12417 DRM_DEBUG("unsupported pixel format: %s\n",
12418 drm_get_format_name(mode_cmd->pixel_format));
12419 return -EINVAL;
12420 }
12421 break;
12422 case DRM_FORMAT_XBGR8888:
12423 case DRM_FORMAT_ABGR8888:
12424 case DRM_FORMAT_XRGB2101010:
12425 case DRM_FORMAT_ARGB2101010:
12426 case DRM_FORMAT_XBGR2101010:
12427 case DRM_FORMAT_ABGR2101010:
12428 if (INTEL_INFO(dev)->gen < 4) {
12429 DRM_DEBUG("unsupported pixel format: %s\n",
12430 drm_get_format_name(mode_cmd->pixel_format));
12431 return -EINVAL;
12432 }
12433 break;
12434 case DRM_FORMAT_YUYV:
12435 case DRM_FORMAT_UYVY:
12436 case DRM_FORMAT_YVYU:
12437 case DRM_FORMAT_VYUY:
12438 if (INTEL_INFO(dev)->gen < 5) {
12439 DRM_DEBUG("unsupported pixel format: %s\n",
12440 drm_get_format_name(mode_cmd->pixel_format));
12441 return -EINVAL;
12442 }
12443 break;
12444 default:
12445 DRM_DEBUG("unsupported pixel format: %s\n",
12446 drm_get_format_name(mode_cmd->pixel_format));
12447 return -EINVAL;
12448 }
12449
12450 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
12451 if (mode_cmd->offsets[0] != 0)
12452 return -EINVAL;
12453
12454 aligned_height = intel_align_height(dev, mode_cmd->height,
12455 obj->tiling_mode);
12456 /* FIXME drm helper for size checks (especially planar formats)? */
12457 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
12458 return -EINVAL;
12459
12460 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
12461 intel_fb->obj = obj;
12462 intel_fb->obj->framebuffer_references++;
12463
12464 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
12465 if (ret) {
12466 DRM_ERROR("framebuffer init failed %d\n", ret);
12467 return ret;
12468 }
12469
12470 return 0;
12471 }
12472
12473 static struct drm_framebuffer *
12474 intel_user_framebuffer_create(struct drm_device *dev,
12475 struct drm_file *filp,
12476 struct drm_mode_fb_cmd2 *mode_cmd)
12477 {
12478 struct drm_i915_gem_object *obj;
12479
12480 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
12481 mode_cmd->handles[0]));
12482 if (&obj->base == NULL)
12483 return ERR_PTR(-ENOENT);
12484
12485 return intel_framebuffer_create(dev, mode_cmd, obj);
12486 }
12487
12488 #ifndef CONFIG_DRM_I915_FBDEV
12489 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
12490 {
12491 }
12492 #endif
12493
12494 static const struct drm_mode_config_funcs intel_mode_funcs = {
12495 .fb_create = intel_user_framebuffer_create,
12496 .output_poll_changed = intel_fbdev_output_poll_changed,
12497 };
12498
12499 /* Set up chip specific display functions */
12500 static void intel_init_display(struct drm_device *dev)
12501 {
12502 struct drm_i915_private *dev_priv = dev->dev_private;
12503
12504 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
12505 dev_priv->display.find_dpll = g4x_find_best_dpll;
12506 else if (IS_CHERRYVIEW(dev))
12507 dev_priv->display.find_dpll = chv_find_best_dpll;
12508 else if (IS_VALLEYVIEW(dev))
12509 dev_priv->display.find_dpll = vlv_find_best_dpll;
12510 else if (IS_PINEVIEW(dev))
12511 dev_priv->display.find_dpll = pnv_find_best_dpll;
12512 else
12513 dev_priv->display.find_dpll = i9xx_find_best_dpll;
12514
12515 if (HAS_DDI(dev)) {
12516 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
12517 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12518 dev_priv->display.crtc_compute_clock =
12519 haswell_crtc_compute_clock;
12520 dev_priv->display.crtc_enable = haswell_crtc_enable;
12521 dev_priv->display.crtc_disable = haswell_crtc_disable;
12522 dev_priv->display.off = ironlake_crtc_off;
12523 if (INTEL_INFO(dev)->gen >= 9)
12524 dev_priv->display.update_primary_plane =
12525 skylake_update_primary_plane;
12526 else
12527 dev_priv->display.update_primary_plane =
12528 ironlake_update_primary_plane;
12529 } else if (HAS_PCH_SPLIT(dev)) {
12530 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
12531 dev_priv->display.get_plane_config = ironlake_get_plane_config;
12532 dev_priv->display.crtc_compute_clock =
12533 ironlake_crtc_compute_clock;
12534 dev_priv->display.crtc_enable = ironlake_crtc_enable;
12535 dev_priv->display.crtc_disable = ironlake_crtc_disable;
12536 dev_priv->display.off = ironlake_crtc_off;
12537 dev_priv->display.update_primary_plane =
12538 ironlake_update_primary_plane;
12539 } else if (IS_VALLEYVIEW(dev)) {
12540 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12541 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12542 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12543 dev_priv->display.crtc_enable = valleyview_crtc_enable;
12544 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12545 dev_priv->display.off = i9xx_crtc_off;
12546 dev_priv->display.update_primary_plane =
12547 i9xx_update_primary_plane;
12548 } else {
12549 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
12550 dev_priv->display.get_plane_config = i9xx_get_plane_config;
12551 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
12552 dev_priv->display.crtc_enable = i9xx_crtc_enable;
12553 dev_priv->display.crtc_disable = i9xx_crtc_disable;
12554 dev_priv->display.off = i9xx_crtc_off;
12555 dev_priv->display.update_primary_plane =
12556 i9xx_update_primary_plane;
12557 }
12558
12559 /* Returns the core display clock speed */
12560 if (IS_VALLEYVIEW(dev))
12561 dev_priv->display.get_display_clock_speed =
12562 valleyview_get_display_clock_speed;
12563 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
12564 dev_priv->display.get_display_clock_speed =
12565 i945_get_display_clock_speed;
12566 else if (IS_I915G(dev))
12567 dev_priv->display.get_display_clock_speed =
12568 i915_get_display_clock_speed;
12569 else if (IS_I945GM(dev) || IS_845G(dev))
12570 dev_priv->display.get_display_clock_speed =
12571 i9xx_misc_get_display_clock_speed;
12572 else if (IS_PINEVIEW(dev))
12573 dev_priv->display.get_display_clock_speed =
12574 pnv_get_display_clock_speed;
12575 else if (IS_I915GM(dev))
12576 dev_priv->display.get_display_clock_speed =
12577 i915gm_get_display_clock_speed;
12578 else if (IS_I865G(dev))
12579 dev_priv->display.get_display_clock_speed =
12580 i865_get_display_clock_speed;
12581 else if (IS_I85X(dev))
12582 dev_priv->display.get_display_clock_speed =
12583 i855_get_display_clock_speed;
12584 else /* 852, 830 */
12585 dev_priv->display.get_display_clock_speed =
12586 i830_get_display_clock_speed;
12587
12588 if (IS_GEN5(dev)) {
12589 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
12590 } else if (IS_GEN6(dev)) {
12591 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
12592 dev_priv->display.modeset_global_resources =
12593 snb_modeset_global_resources;
12594 } else if (IS_IVYBRIDGE(dev)) {
12595 /* FIXME: detect B0+ stepping and use auto training */
12596 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
12597 dev_priv->display.modeset_global_resources =
12598 ivb_modeset_global_resources;
12599 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12600 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
12601 dev_priv->display.modeset_global_resources =
12602 haswell_modeset_global_resources;
12603 } else if (IS_VALLEYVIEW(dev)) {
12604 dev_priv->display.modeset_global_resources =
12605 valleyview_modeset_global_resources;
12606 } else if (INTEL_INFO(dev)->gen >= 9) {
12607 dev_priv->display.modeset_global_resources =
12608 haswell_modeset_global_resources;
12609 }
12610
12611 /* Default just returns -ENODEV to indicate unsupported */
12612 dev_priv->display.queue_flip = intel_default_queue_flip;
12613
12614 switch (INTEL_INFO(dev)->gen) {
12615 case 2:
12616 dev_priv->display.queue_flip = intel_gen2_queue_flip;
12617 break;
12618
12619 case 3:
12620 dev_priv->display.queue_flip = intel_gen3_queue_flip;
12621 break;
12622
12623 case 4:
12624 case 5:
12625 dev_priv->display.queue_flip = intel_gen4_queue_flip;
12626 break;
12627
12628 case 6:
12629 dev_priv->display.queue_flip = intel_gen6_queue_flip;
12630 break;
12631 case 7:
12632 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
12633 dev_priv->display.queue_flip = intel_gen7_queue_flip;
12634 break;
12635 }
12636
12637 intel_panel_init_backlight_funcs(dev);
12638
12639 mutex_init(&dev_priv->pps_mutex);
12640 }
12641
12642 /*
12643 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
12644 * resume, or other times. This quirk makes sure that's the case for
12645 * affected systems.
12646 */
12647 static void quirk_pipea_force(struct drm_device *dev)
12648 {
12649 struct drm_i915_private *dev_priv = dev->dev_private;
12650
12651 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
12652 DRM_INFO("applying pipe a force quirk\n");
12653 }
12654
12655 static void quirk_pipeb_force(struct drm_device *dev)
12656 {
12657 struct drm_i915_private *dev_priv = dev->dev_private;
12658
12659 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
12660 DRM_INFO("applying pipe b force quirk\n");
12661 }
12662
12663 /*
12664 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
12665 */
12666 static void quirk_ssc_force_disable(struct drm_device *dev)
12667 {
12668 struct drm_i915_private *dev_priv = dev->dev_private;
12669 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
12670 DRM_INFO("applying lvds SSC disable quirk\n");
12671 }
12672
12673 /*
12674 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
12675 * brightness value
12676 */
12677 static void quirk_invert_brightness(struct drm_device *dev)
12678 {
12679 struct drm_i915_private *dev_priv = dev->dev_private;
12680 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
12681 DRM_INFO("applying inverted panel brightness quirk\n");
12682 }
12683
12684 /* Some VBT's incorrectly indicate no backlight is present */
12685 static void quirk_backlight_present(struct drm_device *dev)
12686 {
12687 struct drm_i915_private *dev_priv = dev->dev_private;
12688 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
12689 DRM_INFO("applying backlight present quirk\n");
12690 }
12691
12692 struct intel_quirk {
12693 int device;
12694 int subsystem_vendor;
12695 int subsystem_device;
12696 void (*hook)(struct drm_device *dev);
12697 };
12698
12699 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
12700 struct intel_dmi_quirk {
12701 void (*hook)(struct drm_device *dev);
12702 const struct dmi_system_id (*dmi_id_list)[];
12703 };
12704
12705 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
12706 {
12707 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
12708 return 1;
12709 }
12710
12711 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
12712 {
12713 .dmi_id_list = &(const struct dmi_system_id[]) {
12714 {
12715 .callback = intel_dmi_reverse_brightness,
12716 .ident = "NCR Corporation",
12717 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
12718 DMI_MATCH(DMI_PRODUCT_NAME, ""),
12719 },
12720 },
12721 { } /* terminating entry */
12722 },
12723 .hook = quirk_invert_brightness,
12724 },
12725 };
12726
12727 static struct intel_quirk intel_quirks[] = {
12728 /* HP Mini needs pipe A force quirk (LP: #322104) */
12729 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
12730
12731 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
12732 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
12733
12734 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
12735 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
12736
12737 /* 830 needs to leave pipe A & dpll A up */
12738 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
12739
12740 /* 830 needs to leave pipe B & dpll B up */
12741 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
12742
12743 /* Lenovo U160 cannot use SSC on LVDS */
12744 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
12745
12746 /* Sony Vaio Y cannot use SSC on LVDS */
12747 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12748
12749 /* Acer Aspire 5734Z must invert backlight brightness */
12750 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12751
12752 /* Acer/eMachines G725 */
12753 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12754
12755 /* Acer/eMachines e725 */
12756 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12757
12758 /* Acer/Packard Bell NCL20 */
12759 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12760
12761 /* Acer Aspire 4736Z */
12762 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12763
12764 /* Acer Aspire 5336 */
12765 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12766
12767 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
12768 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
12769
12770 /* Acer C720 Chromebook (Core i3 4005U) */
12771 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
12772
12773 /* Toshiba CB35 Chromebook (Celeron 2955U) */
12774 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
12775
12776 /* HP Chromebook 14 (Celeron 2955U) */
12777 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
12778 };
12779
12780 static void intel_init_quirks(struct drm_device *dev)
12781 {
12782 struct pci_dev *d = dev->pdev;
12783 int i;
12784
12785 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12786 struct intel_quirk *q = &intel_quirks[i];
12787
12788 if (d->device == q->device &&
12789 (d->subsystem_vendor == q->subsystem_vendor ||
12790 q->subsystem_vendor == PCI_ANY_ID) &&
12791 (d->subsystem_device == q->subsystem_device ||
12792 q->subsystem_device == PCI_ANY_ID))
12793 q->hook(dev);
12794 }
12795 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12796 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12797 intel_dmi_quirks[i].hook(dev);
12798 }
12799 }
12800
12801 /* Disable the VGA plane that we never use */
12802 static void i915_disable_vga(struct drm_device *dev)
12803 {
12804 struct drm_i915_private *dev_priv = dev->dev_private;
12805 u8 sr1;
12806 u32 vga_reg = i915_vgacntrl_reg(dev);
12807
12808 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12809 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12810 outb(SR01, VGA_SR_INDEX);
12811 sr1 = inb(VGA_SR_DATA);
12812 outb(sr1 | 1<<5, VGA_SR_DATA);
12813 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12814 udelay(300);
12815
12816 /*
12817 * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming
12818 * from S3 without preserving (some of?) the other bits.
12819 */
12820 I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE);
12821 POSTING_READ(vga_reg);
12822 }
12823
12824 void intel_modeset_init_hw(struct drm_device *dev)
12825 {
12826 intel_prepare_ddi(dev);
12827
12828 if (IS_VALLEYVIEW(dev))
12829 vlv_update_cdclk(dev);
12830
12831 intel_init_clock_gating(dev);
12832
12833 intel_enable_gt_powersave(dev);
12834 }
12835
12836 void intel_modeset_init(struct drm_device *dev)
12837 {
12838 struct drm_i915_private *dev_priv = dev->dev_private;
12839 int sprite, ret;
12840 enum pipe pipe;
12841 struct intel_crtc *crtc;
12842
12843 drm_mode_config_init(dev);
12844
12845 dev->mode_config.min_width = 0;
12846 dev->mode_config.min_height = 0;
12847
12848 dev->mode_config.preferred_depth = 24;
12849 dev->mode_config.prefer_shadow = 1;
12850
12851 dev->mode_config.funcs = &intel_mode_funcs;
12852
12853 intel_init_quirks(dev);
12854
12855 intel_init_pm(dev);
12856
12857 if (INTEL_INFO(dev)->num_pipes == 0)
12858 return;
12859
12860 intel_init_display(dev);
12861 intel_init_audio(dev);
12862
12863 if (IS_GEN2(dev)) {
12864 dev->mode_config.max_width = 2048;
12865 dev->mode_config.max_height = 2048;
12866 } else if (IS_GEN3(dev)) {
12867 dev->mode_config.max_width = 4096;
12868 dev->mode_config.max_height = 4096;
12869 } else {
12870 dev->mode_config.max_width = 8192;
12871 dev->mode_config.max_height = 8192;
12872 }
12873
12874 if (IS_845G(dev) || IS_I865G(dev)) {
12875 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
12876 dev->mode_config.cursor_height = 1023;
12877 } else if (IS_GEN2(dev)) {
12878 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12879 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12880 } else {
12881 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12882 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12883 }
12884
12885 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12886
12887 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12888 INTEL_INFO(dev)->num_pipes,
12889 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12890
12891 for_each_pipe(dev_priv, pipe) {
12892 intel_crtc_init(dev, pipe);
12893 for_each_sprite(pipe, sprite) {
12894 ret = intel_plane_init(dev, pipe, sprite);
12895 if (ret)
12896 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12897 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12898 }
12899 }
12900
12901 intel_init_dpio(dev);
12902
12903 intel_shared_dpll_init(dev);
12904
12905 /* save the BIOS value before clobbering it */
12906 dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev));
12907 /* Just disable it once at startup */
12908 i915_disable_vga(dev);
12909 intel_setup_outputs(dev);
12910
12911 /* Just in case the BIOS is doing something questionable. */
12912 intel_disable_fbc(dev);
12913
12914 drm_modeset_lock_all(dev);
12915 intel_modeset_setup_hw_state(dev, false);
12916 drm_modeset_unlock_all(dev);
12917
12918 for_each_intel_crtc(dev, crtc) {
12919 if (!crtc->active)
12920 continue;
12921
12922 /*
12923 * Note that reserving the BIOS fb up front prevents us
12924 * from stuffing other stolen allocations like the ring
12925 * on top. This prevents some ugliness at boot time, and
12926 * can even allow for smooth boot transitions if the BIOS
12927 * fb is large enough for the active pipe configuration.
12928 */
12929 if (dev_priv->display.get_plane_config) {
12930 dev_priv->display.get_plane_config(crtc,
12931 &crtc->plane_config);
12932 /*
12933 * If the fb is shared between multiple heads, we'll
12934 * just get the first one.
12935 */
12936 intel_find_plane_obj(crtc, &crtc->plane_config);
12937 }
12938 }
12939 }
12940
12941 static void intel_enable_pipe_a(struct drm_device *dev)
12942 {
12943 struct intel_connector *connector;
12944 struct drm_connector *crt = NULL;
12945 struct intel_load_detect_pipe load_detect_temp;
12946 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
12947
12948 /* We can't just switch on the pipe A, we need to set things up with a
12949 * proper mode and output configuration. As a gross hack, enable pipe A
12950 * by enabling the load detect pipe once. */
12951 list_for_each_entry(connector,
12952 &dev->mode_config.connector_list,
12953 base.head) {
12954 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12955 crt = &connector->base;
12956 break;
12957 }
12958 }
12959
12960 if (!crt)
12961 return;
12962
12963 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
12964 intel_release_load_detect_pipe(crt, &load_detect_temp);
12965 }
12966
12967 static bool
12968 intel_check_plane_mapping(struct intel_crtc *crtc)
12969 {
12970 struct drm_device *dev = crtc->base.dev;
12971 struct drm_i915_private *dev_priv = dev->dev_private;
12972 u32 reg, val;
12973
12974 if (INTEL_INFO(dev)->num_pipes == 1)
12975 return true;
12976
12977 reg = DSPCNTR(!crtc->plane);
12978 val = I915_READ(reg);
12979
12980 if ((val & DISPLAY_PLANE_ENABLE) &&
12981 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12982 return false;
12983
12984 return true;
12985 }
12986
12987 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12988 {
12989 struct drm_device *dev = crtc->base.dev;
12990 struct drm_i915_private *dev_priv = dev->dev_private;
12991 u32 reg;
12992
12993 /* Clear any frame start delays used for debugging left by the BIOS */
12994 reg = PIPECONF(crtc->config.cpu_transcoder);
12995 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12996
12997 /* restore vblank interrupts to correct state */
12998 if (crtc->active) {
12999 update_scanline_offset(crtc);
13000 drm_vblank_on(dev, crtc->pipe);
13001 } else
13002 drm_vblank_off(dev, crtc->pipe);
13003
13004 /* We need to sanitize the plane -> pipe mapping first because this will
13005 * disable the crtc (and hence change the state) if it is wrong. Note
13006 * that gen4+ has a fixed plane -> pipe mapping. */
13007 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
13008 struct intel_connector *connector;
13009 bool plane;
13010
13011 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13012 crtc->base.base.id);
13013
13014 /* Pipe has the wrong plane attached and the plane is active.
13015 * Temporarily change the plane mapping and disable everything
13016 * ... */
13017 plane = crtc->plane;
13018 crtc->plane = !plane;
13019 crtc->primary_enabled = true;
13020 dev_priv->display.crtc_disable(&crtc->base);
13021 crtc->plane = plane;
13022
13023 /* ... and break all links. */
13024 list_for_each_entry(connector, &dev->mode_config.connector_list,
13025 base.head) {
13026 if (connector->encoder->base.crtc != &crtc->base)
13027 continue;
13028
13029 connector->base.dpms = DRM_MODE_DPMS_OFF;
13030 connector->base.encoder = NULL;
13031 }
13032 /* multiple connectors may have the same encoder:
13033 * handle them and break crtc link separately */
13034 list_for_each_entry(connector, &dev->mode_config.connector_list,
13035 base.head)
13036 if (connector->encoder->base.crtc == &crtc->base) {
13037 connector->encoder->base.crtc = NULL;
13038 connector->encoder->connectors_active = false;
13039 }
13040
13041 WARN_ON(crtc->active);
13042 crtc->base.enabled = false;
13043 }
13044
13045 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13046 crtc->pipe == PIPE_A && !crtc->active) {
13047 /* BIOS forgot to enable pipe A, this mostly happens after
13048 * resume. Force-enable the pipe to fix this, the update_dpms
13049 * call below we restore the pipe to the right state, but leave
13050 * the required bits on. */
13051 intel_enable_pipe_a(dev);
13052 }
13053
13054 /* Adjust the state of the output pipe according to whether we
13055 * have active connectors/encoders. */
13056 intel_crtc_update_dpms(&crtc->base);
13057
13058 if (crtc->active != crtc->base.enabled) {
13059 struct intel_encoder *encoder;
13060
13061 /* This can happen either due to bugs in the get_hw_state
13062 * functions or because the pipe is force-enabled due to the
13063 * pipe A quirk. */
13064 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13065 crtc->base.base.id,
13066 crtc->base.enabled ? "enabled" : "disabled",
13067 crtc->active ? "enabled" : "disabled");
13068
13069 crtc->base.enabled = crtc->active;
13070
13071 /* Because we only establish the connector -> encoder ->
13072 * crtc links if something is active, this means the
13073 * crtc is now deactivated. Break the links. connector
13074 * -> encoder links are only establish when things are
13075 * actually up, hence no need to break them. */
13076 WARN_ON(crtc->active);
13077
13078 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13079 WARN_ON(encoder->connectors_active);
13080 encoder->base.crtc = NULL;
13081 }
13082 }
13083
13084 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
13085 /*
13086 * We start out with underrun reporting disabled to avoid races.
13087 * For correct bookkeeping mark this on active crtcs.
13088 *
13089 * Also on gmch platforms we dont have any hardware bits to
13090 * disable the underrun reporting. Which means we need to start
13091 * out with underrun reporting disabled also on inactive pipes,
13092 * since otherwise we'll complain about the garbage we read when
13093 * e.g. coming up after runtime pm.
13094 *
13095 * No protection against concurrent access is required - at
13096 * worst a fifo underrun happens which also sets this to false.
13097 */
13098 crtc->cpu_fifo_underrun_disabled = true;
13099 crtc->pch_fifo_underrun_disabled = true;
13100 }
13101 }
13102
13103 static void intel_sanitize_encoder(struct intel_encoder *encoder)
13104 {
13105 struct intel_connector *connector;
13106 struct drm_device *dev = encoder->base.dev;
13107
13108 /* We need to check both for a crtc link (meaning that the
13109 * encoder is active and trying to read from a pipe) and the
13110 * pipe itself being active. */
13111 bool has_active_crtc = encoder->base.crtc &&
13112 to_intel_crtc(encoder->base.crtc)->active;
13113
13114 if (encoder->connectors_active && !has_active_crtc) {
13115 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13116 encoder->base.base.id,
13117 encoder->base.name);
13118
13119 /* Connector is active, but has no active pipe. This is
13120 * fallout from our resume register restoring. Disable
13121 * the encoder manually again. */
13122 if (encoder->base.crtc) {
13123 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13124 encoder->base.base.id,
13125 encoder->base.name);
13126 encoder->disable(encoder);
13127 if (encoder->post_disable)
13128 encoder->post_disable(encoder);
13129 }
13130 encoder->base.crtc = NULL;
13131 encoder->connectors_active = false;
13132
13133 /* Inconsistent output/port/pipe state happens presumably due to
13134 * a bug in one of the get_hw_state functions. Or someplace else
13135 * in our code, like the register restore mess on resume. Clamp
13136 * things to off as a safer default. */
13137 list_for_each_entry(connector,
13138 &dev->mode_config.connector_list,
13139 base.head) {
13140 if (connector->encoder != encoder)
13141 continue;
13142 connector->base.dpms = DRM_MODE_DPMS_OFF;
13143 connector->base.encoder = NULL;
13144 }
13145 }
13146 /* Enabled encoders without active connectors will be fixed in
13147 * the crtc fixup. */
13148 }
13149
13150 void i915_redisable_vga_power_on(struct drm_device *dev)
13151 {
13152 struct drm_i915_private *dev_priv = dev->dev_private;
13153 u32 vga_reg = i915_vgacntrl_reg(dev);
13154
13155 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13156 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13157 i915_disable_vga(dev);
13158 }
13159 }
13160
13161 void i915_redisable_vga(struct drm_device *dev)
13162 {
13163 struct drm_i915_private *dev_priv = dev->dev_private;
13164
13165 /* This function can be called both from intel_modeset_setup_hw_state or
13166 * at a very early point in our resume sequence, where the power well
13167 * structures are not yet restored. Since this function is at a very
13168 * paranoid "someone might have enabled VGA while we were not looking"
13169 * level, just check if the power well is enabled instead of trying to
13170 * follow the "don't touch the power well if we don't need it" policy
13171 * the rest of the driver uses. */
13172 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
13173 return;
13174
13175 i915_redisable_vga_power_on(dev);
13176 }
13177
13178 static bool primary_get_hw_state(struct intel_crtc *crtc)
13179 {
13180 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13181
13182 if (!crtc->active)
13183 return false;
13184
13185 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13186 }
13187
13188 static void intel_modeset_readout_hw_state(struct drm_device *dev)
13189 {
13190 struct drm_i915_private *dev_priv = dev->dev_private;
13191 enum pipe pipe;
13192 struct intel_crtc *crtc;
13193 struct intel_encoder *encoder;
13194 struct intel_connector *connector;
13195 int i;
13196
13197 for_each_intel_crtc(dev, crtc) {
13198 memset(&crtc->config, 0, sizeof(crtc->config));
13199
13200 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
13201
13202 crtc->active = dev_priv->display.get_pipe_config(crtc,
13203 &crtc->config);
13204
13205 crtc->base.enabled = crtc->active;
13206 crtc->primary_enabled = primary_get_hw_state(crtc);
13207
13208 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13209 crtc->base.base.id,
13210 crtc->active ? "enabled" : "disabled");
13211 }
13212
13213 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13214 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13215
13216 pll->on = pll->get_hw_state(dev_priv, pll,
13217 &pll->config.hw_state);
13218 pll->active = 0;
13219 pll->config.crtc_mask = 0;
13220 for_each_intel_crtc(dev, crtc) {
13221 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
13222 pll->active++;
13223 pll->config.crtc_mask |= 1 << crtc->pipe;
13224 }
13225 }
13226
13227 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
13228 pll->name, pll->config.crtc_mask, pll->on);
13229
13230 if (pll->config.crtc_mask)
13231 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
13232 }
13233
13234 for_each_intel_encoder(dev, encoder) {
13235 pipe = 0;
13236
13237 if (encoder->get_hw_state(encoder, &pipe)) {
13238 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13239 encoder->base.crtc = &crtc->base;
13240 encoder->get_config(encoder, &crtc->config);
13241 } else {
13242 encoder->base.crtc = NULL;
13243 }
13244
13245 encoder->connectors_active = false;
13246 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
13247 encoder->base.base.id,
13248 encoder->base.name,
13249 encoder->base.crtc ? "enabled" : "disabled",
13250 pipe_name(pipe));
13251 }
13252
13253 list_for_each_entry(connector, &dev->mode_config.connector_list,
13254 base.head) {
13255 if (connector->get_hw_state(connector)) {
13256 connector->base.dpms = DRM_MODE_DPMS_ON;
13257 connector->encoder->connectors_active = true;
13258 connector->base.encoder = &connector->encoder->base;
13259 } else {
13260 connector->base.dpms = DRM_MODE_DPMS_OFF;
13261 connector->base.encoder = NULL;
13262 }
13263 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13264 connector->base.base.id,
13265 connector->base.name,
13266 connector->base.encoder ? "enabled" : "disabled");
13267 }
13268 }
13269
13270 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13271 * and i915 state tracking structures. */
13272 void intel_modeset_setup_hw_state(struct drm_device *dev,
13273 bool force_restore)
13274 {
13275 struct drm_i915_private *dev_priv = dev->dev_private;
13276 enum pipe pipe;
13277 struct intel_crtc *crtc;
13278 struct intel_encoder *encoder;
13279 int i;
13280
13281 intel_modeset_readout_hw_state(dev);
13282
13283 /*
13284 * Now that we have the config, copy it to each CRTC struct
13285 * Note that this could go away if we move to using crtc_config
13286 * checking everywhere.
13287 */
13288 for_each_intel_crtc(dev, crtc) {
13289 if (crtc->active && i915.fastboot) {
13290 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
13291 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13292 crtc->base.base.id);
13293 drm_mode_debug_printmodeline(&crtc->base.mode);
13294 }
13295 }
13296
13297 /* HW state is read out, now we need to sanitize this mess. */
13298 for_each_intel_encoder(dev, encoder) {
13299 intel_sanitize_encoder(encoder);
13300 }
13301
13302 for_each_pipe(dev_priv, pipe) {
13303 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13304 intel_sanitize_crtc(crtc);
13305 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
13306 }
13307
13308 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13309 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13310
13311 if (!pll->on || pll->active)
13312 continue;
13313
13314 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13315
13316 pll->disable(dev_priv, pll);
13317 pll->on = false;
13318 }
13319
13320 if (IS_GEN9(dev))
13321 skl_wm_get_hw_state(dev);
13322 else if (HAS_PCH_SPLIT(dev))
13323 ilk_wm_get_hw_state(dev);
13324
13325 if (force_restore) {
13326 i915_redisable_vga(dev);
13327
13328 /*
13329 * We need to use raw interfaces for restoring state to avoid
13330 * checking (bogus) intermediate states.
13331 */
13332 for_each_pipe(dev_priv, pipe) {
13333 struct drm_crtc *crtc =
13334 dev_priv->pipe_to_crtc_mapping[pipe];
13335
13336 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13337 crtc->primary->fb);
13338 }
13339 } else {
13340 intel_modeset_update_staged_output_state(dev);
13341 }
13342
13343 intel_modeset_check_state(dev);
13344 }
13345
13346 void intel_modeset_gem_init(struct drm_device *dev)
13347 {
13348 struct drm_crtc *c;
13349 struct drm_i915_gem_object *obj;
13350
13351 mutex_lock(&dev->struct_mutex);
13352 intel_init_gt_powersave(dev);
13353 mutex_unlock(&dev->struct_mutex);
13354
13355 intel_modeset_init_hw(dev);
13356
13357 intel_setup_overlay(dev);
13358
13359 /*
13360 * Make sure any fbs we allocated at startup are properly
13361 * pinned & fenced. When we do the allocation it's too early
13362 * for this.
13363 */
13364 mutex_lock(&dev->struct_mutex);
13365 for_each_crtc(dev, c) {
13366 obj = intel_fb_obj(c->primary->fb);
13367 if (obj == NULL)
13368 continue;
13369
13370 if (intel_pin_and_fence_fb_obj(c->primary,
13371 c->primary->fb,
13372 NULL)) {
13373 DRM_ERROR("failed to pin boot fb on pipe %d\n",
13374 to_intel_crtc(c)->pipe);
13375 drm_framebuffer_unreference(c->primary->fb);
13376 c->primary->fb = NULL;
13377 }
13378 }
13379 mutex_unlock(&dev->struct_mutex);
13380 }
13381
13382 void intel_connector_unregister(struct intel_connector *intel_connector)
13383 {
13384 struct drm_connector *connector = &intel_connector->base;
13385
13386 intel_panel_destroy_backlight(connector);
13387 drm_connector_unregister(connector);
13388 }
13389
13390 void intel_modeset_cleanup(struct drm_device *dev)
13391 {
13392 struct drm_i915_private *dev_priv = dev->dev_private;
13393 struct drm_connector *connector;
13394
13395 /*
13396 * Interrupts and polling as the first thing to avoid creating havoc.
13397 * Too much stuff here (turning of rps, connectors, ...) would
13398 * experience fancy races otherwise.
13399 */
13400 intel_irq_uninstall(dev_priv);
13401
13402 /*
13403 * Due to the hpd irq storm handling the hotplug work can re-arm the
13404 * poll handlers. Hence disable polling after hpd handling is shut down.
13405 */
13406 drm_kms_helper_poll_fini(dev);
13407
13408 mutex_lock(&dev->struct_mutex);
13409
13410 intel_unregister_dsm_handler();
13411
13412 intel_disable_fbc(dev);
13413
13414 intel_disable_gt_powersave(dev);
13415
13416 ironlake_teardown_rc6(dev);
13417
13418 mutex_unlock(&dev->struct_mutex);
13419
13420 /* flush any delayed tasks or pending work */
13421 flush_scheduled_work();
13422
13423 /* destroy the backlight and sysfs files before encoders/connectors */
13424 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
13425 struct intel_connector *intel_connector;
13426
13427 intel_connector = to_intel_connector(connector);
13428 intel_connector->unregister(intel_connector);
13429 }
13430
13431 drm_mode_config_cleanup(dev);
13432
13433 intel_cleanup_overlay(dev);
13434
13435 mutex_lock(&dev->struct_mutex);
13436 intel_cleanup_gt_powersave(dev);
13437 mutex_unlock(&dev->struct_mutex);
13438 }
13439
13440 /*
13441 * Return which encoder is currently attached for connector.
13442 */
13443 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
13444 {
13445 return &intel_attached_encoder(connector)->base;
13446 }
13447
13448 void intel_connector_attach_encoder(struct intel_connector *connector,
13449 struct intel_encoder *encoder)
13450 {
13451 connector->encoder = encoder;
13452 drm_mode_connector_attach_encoder(&connector->base,
13453 &encoder->base);
13454 }
13455
13456 /*
13457 * set vga decode state - true == enable VGA decode
13458 */
13459 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
13460 {
13461 struct drm_i915_private *dev_priv = dev->dev_private;
13462 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
13463 u16 gmch_ctrl;
13464
13465 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
13466 DRM_ERROR("failed to read control word\n");
13467 return -EIO;
13468 }
13469
13470 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
13471 return 0;
13472
13473 if (state)
13474 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
13475 else
13476 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
13477
13478 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
13479 DRM_ERROR("failed to write control word\n");
13480 return -EIO;
13481 }
13482
13483 return 0;
13484 }
13485
13486 struct intel_display_error_state {
13487
13488 u32 power_well_driver;
13489
13490 int num_transcoders;
13491
13492 struct intel_cursor_error_state {
13493 u32 control;
13494 u32 position;
13495 u32 base;
13496 u32 size;
13497 } cursor[I915_MAX_PIPES];
13498
13499 struct intel_pipe_error_state {
13500 bool power_domain_on;
13501 u32 source;
13502 u32 stat;
13503 } pipe[I915_MAX_PIPES];
13504
13505 struct intel_plane_error_state {
13506 u32 control;
13507 u32 stride;
13508 u32 size;
13509 u32 pos;
13510 u32 addr;
13511 u32 surface;
13512 u32 tile_offset;
13513 } plane[I915_MAX_PIPES];
13514
13515 struct intel_transcoder_error_state {
13516 bool power_domain_on;
13517 enum transcoder cpu_transcoder;
13518
13519 u32 conf;
13520
13521 u32 htotal;
13522 u32 hblank;
13523 u32 hsync;
13524 u32 vtotal;
13525 u32 vblank;
13526 u32 vsync;
13527 } transcoder[4];
13528 };
13529
13530 struct intel_display_error_state *
13531 intel_display_capture_error_state(struct drm_device *dev)
13532 {
13533 struct drm_i915_private *dev_priv = dev->dev_private;
13534 struct intel_display_error_state *error;
13535 int transcoders[] = {
13536 TRANSCODER_A,
13537 TRANSCODER_B,
13538 TRANSCODER_C,
13539 TRANSCODER_EDP,
13540 };
13541 int i;
13542
13543 if (INTEL_INFO(dev)->num_pipes == 0)
13544 return NULL;
13545
13546 error = kzalloc(sizeof(*error), GFP_ATOMIC);
13547 if (error == NULL)
13548 return NULL;
13549
13550 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13551 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
13552
13553 for_each_pipe(dev_priv, i) {
13554 error->pipe[i].power_domain_on =
13555 __intel_display_power_is_enabled(dev_priv,
13556 POWER_DOMAIN_PIPE(i));
13557 if (!error->pipe[i].power_domain_on)
13558 continue;
13559
13560 error->cursor[i].control = I915_READ(CURCNTR(i));
13561 error->cursor[i].position = I915_READ(CURPOS(i));
13562 error->cursor[i].base = I915_READ(CURBASE(i));
13563
13564 error->plane[i].control = I915_READ(DSPCNTR(i));
13565 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
13566 if (INTEL_INFO(dev)->gen <= 3) {
13567 error->plane[i].size = I915_READ(DSPSIZE(i));
13568 error->plane[i].pos = I915_READ(DSPPOS(i));
13569 }
13570 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13571 error->plane[i].addr = I915_READ(DSPADDR(i));
13572 if (INTEL_INFO(dev)->gen >= 4) {
13573 error->plane[i].surface = I915_READ(DSPSURF(i));
13574 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
13575 }
13576
13577 error->pipe[i].source = I915_READ(PIPESRC(i));
13578
13579 if (HAS_GMCH_DISPLAY(dev))
13580 error->pipe[i].stat = I915_READ(PIPESTAT(i));
13581 }
13582
13583 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
13584 if (HAS_DDI(dev_priv->dev))
13585 error->num_transcoders++; /* Account for eDP. */
13586
13587 for (i = 0; i < error->num_transcoders; i++) {
13588 enum transcoder cpu_transcoder = transcoders[i];
13589
13590 error->transcoder[i].power_domain_on =
13591 __intel_display_power_is_enabled(dev_priv,
13592 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
13593 if (!error->transcoder[i].power_domain_on)
13594 continue;
13595
13596 error->transcoder[i].cpu_transcoder = cpu_transcoder;
13597
13598 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
13599 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
13600 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
13601 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
13602 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
13603 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
13604 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
13605 }
13606
13607 return error;
13608 }
13609
13610 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
13611
13612 void
13613 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
13614 struct drm_device *dev,
13615 struct intel_display_error_state *error)
13616 {
13617 struct drm_i915_private *dev_priv = dev->dev_private;
13618 int i;
13619
13620 if (!error)
13621 return;
13622
13623 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
13624 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
13625 err_printf(m, "PWR_WELL_CTL2: %08x\n",
13626 error->power_well_driver);
13627 for_each_pipe(dev_priv, i) {
13628 err_printf(m, "Pipe [%d]:\n", i);
13629 err_printf(m, " Power: %s\n",
13630 error->pipe[i].power_domain_on ? "on" : "off");
13631 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
13632 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
13633
13634 err_printf(m, "Plane [%d]:\n", i);
13635 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
13636 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
13637 if (INTEL_INFO(dev)->gen <= 3) {
13638 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
13639 err_printf(m, " POS: %08x\n", error->plane[i].pos);
13640 }
13641 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
13642 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
13643 if (INTEL_INFO(dev)->gen >= 4) {
13644 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
13645 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
13646 }
13647
13648 err_printf(m, "Cursor [%d]:\n", i);
13649 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
13650 err_printf(m, " POS: %08x\n", error->cursor[i].position);
13651 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
13652 }
13653
13654 for (i = 0; i < error->num_transcoders; i++) {
13655 err_printf(m, "CPU transcoder: %c\n",
13656 transcoder_name(error->transcoder[i].cpu_transcoder));
13657 err_printf(m, " Power: %s\n",
13658 error->transcoder[i].power_domain_on ? "on" : "off");
13659 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
13660 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
13661 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
13662 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
13663 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
13664 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
13665 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
13666 }
13667 }
13668
13669 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
13670 {
13671 struct intel_crtc *crtc;
13672
13673 for_each_intel_crtc(dev, crtc) {
13674 struct intel_unpin_work *work;
13675
13676 spin_lock_irq(&dev->event_lock);
13677
13678 work = crtc->unpin_work;
13679
13680 if (work && work->event &&
13681 work->event->base.file_priv == file) {
13682 kfree(work->event);
13683 work->event = NULL;
13684 }
13685
13686 spin_unlock_irq(&dev->event_lock);
13687 }
13688 }
Linux kernel - Deliverables
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